Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 | Date : Mon May 18 09:56:19 2020 | Host : baby running 64-bit major release (build 9200) | Command : report_timing_summary -max_paths 10 -file fc7_top_timing_summary_routed.rpt -pb fc7_top_timing_summary_routed.pb -rpx fc7_top_timing_summary_routed.rpx -warn_on_violation | Design : fc7_top | Device : 7k420t-ffg1156 | Speed File : -2 PRODUCTION 1.12 2017-02-17 -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Timing Summary Report ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : false Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes check_timing report Table of Contents ----------------- 1. checking no_clock 2. checking constant_clock 3. checking pulse_width_clock 4. checking unconstrained_internal_endpoints 5. checking no_input_delay 6. checking no_output_delay 7. checking multiple_clock 8. checking generated_clocks 9. checking loops 10. checking partial_input_delay 11. checking partial_output_delay 12. checking latch_loops 1. checking no_clock -------------------- There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[10].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][0]/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[10].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][1]/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[10].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][2]/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[10].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][3]/Q (HIGH) There are 4 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[10].ngCCM_gbt/sel_sec_jtag_reg/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[11].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][0]/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[11].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][1]/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[11].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][2]/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[11].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][3]/Q (HIGH) There are 4 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[11].ngCCM_gbt/sel_sec_jtag_reg/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[12].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][0]/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[12].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][1]/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[12].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][2]/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[12].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][3]/Q (HIGH) There are 4 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[12].ngCCM_gbt/sel_sec_jtag_reg/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][0]/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][1]/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][2]/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[1].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][3]/Q (HIGH) There are 4 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[1].ngCCM_gbt/sel_sec_jtag_reg/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][0]/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][1]/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][2]/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[2].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][3]/Q (HIGH) There are 4 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[2].ngCCM_gbt/sel_sec_jtag_reg/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[3].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][0]/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[3].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][1]/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[3].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][2]/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[3].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][3]/Q (HIGH) There are 4 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[3].ngCCM_gbt/sel_sec_jtag_reg/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[4].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][0]/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[4].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][1]/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[4].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][2]/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[4].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][3]/Q (HIGH) There are 4 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[4].ngCCM_gbt/sel_sec_jtag_reg/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[5].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][0]/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[5].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][1]/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[5].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][2]/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[5].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][3]/Q (HIGH) There are 4 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[5].ngCCM_gbt/sel_sec_jtag_reg/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[6].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][0]/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[6].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][1]/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[6].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][2]/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[6].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][3]/Q (HIGH) There are 4 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[6].ngCCM_gbt/sel_sec_jtag_reg/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[7].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][0]/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[7].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][1]/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[7].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][2]/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[7].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][3]/Q (HIGH) There are 4 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[7].ngCCM_gbt/sel_sec_jtag_reg/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[8].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][0]/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[8].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][1]/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[8].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][2]/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[8].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][3]/Q (HIGH) There are 4 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[8].ngCCM_gbt/sel_sec_jtag_reg/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[9].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][0]/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[9].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][1]/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[9].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][2]/Q (HIGH) There are 6 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[9].ngCCM_gbt/ngccmPinsOutReg_reg[sel_addr][3]/Q (HIGH) There are 4 register/latch pins with no clock driven by root clock pin: ngFEC/SFP_GEN[9].ngCCM_gbt/sel_sec_jtag_reg/Q (HIGH) There are 4 register/latch pins with no clock driven by root clock pin: ngFEC/fabric_clk_div2_reg/Q (HIGH) There is 1 register/latch pin with no clock driven by root clock pin: sys/clocks/rst_ipb_reg/Q (HIGH) There is 1 register/latch pin with no clock driven by root clock pin: sys/ipb_sys_regs/regs_reg[11][12]/Q (HIGH) 2. checking constant_clock -------------------------- There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock ----------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints -------------------------------------------- There are 77 pins that are not constrained for maximum delay. (HIGH) There is 1 pin that is not constrained for maximum delay due to constant clock. (MEDIUM) 5. checking no_input_delay -------------------------- There are 91 input ports with no input delay specified. (HIGH) There are 0 input ports with no input delay but user has a false path constraint. 6. checking no_output_delay --------------------------- There are 87 ports with no output delay specified. (HIGH) There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock -------------------------- There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks ---------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops ----------------- There are 0 combinational loops in the design. 10. checking partial_input_delay -------------------------------- There are 0 input ports with partial input delay specified. 11. checking partial_output_delay --------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops ------------------------ There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- 0.619 0.000 0 354648 0.051 0.000 0 353712 2.000 0.000 0 142022 All user specified timing constraints are met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- clk_o_39_997 {0.000 12.476} 24.953 40.075 fabric_clk {0.000 12.475} 24.951 40.079 fabric_clk_FBOUT {0.000 12.475} 24.951 40.079 clk_o_40_08_phase_mon_mmcm_1 {0.000 12.451} 24.901 40.159 clk_o_39_997_phase_mon_mmcm_2 {0.000 12.476} 24.953 40.076 clkfbout_phase_mon_mmcm_2 {0.000 37.352} 74.704 13.386 clkfbout_phase_mon_mmcm_1 {0.000 24.951} 49.902 20.039 fabric_clk_PSOUT {0.000 12.475} 24.951 40.079 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK {0.000 4.167} 8.333 120.005 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKFABRIC {0.000 4.167} 8.333 120.005 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK {0.000 4.167} 8.333 120.005 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKFABRIC {0.000 4.167} 8.333 120.005 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK {0.000 4.167} 8.333 120.005 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKFABRIC {0.000 4.167} 8.333 120.005 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK {0.000 4.167} 8.333 120.005 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKFABRIC {0.000 4.167} 8.333 120.005 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK {0.000 4.167} 8.333 120.005 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKFABRIC {0.000 4.167} 8.333 120.005 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK {0.000 4.167} 8.333 120.005 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKFABRIC {0.000 4.167} 8.333 120.005 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK {0.000 4.167} 8.333 120.005 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKFABRIC {0.000 4.167} 8.333 120.005 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK {0.000 4.167} 8.333 120.005 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKFABRIC {0.000 4.167} 8.333 120.005 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK {0.000 4.167} 8.333 120.005 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKFABRIC {0.000 4.167} 8.333 120.005 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK {0.000 4.167} 8.333 120.005 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKFABRIC {0.000 4.167} 8.333 120.005 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK {0.000 4.167} 8.333 120.005 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKFABRIC {0.000 4.167} 8.333 120.005 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK {0.000 4.167} 8.333 120.005 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKFABRIC {0.000 4.167} 8.333 120.005 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK {0.000 4.167} 8.333 120.005 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKFABRIC {0.000 4.167} 8.333 120.005 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK {0.000 4.167} 8.333 120.005 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKFABRIC {0.000 4.167} 8.333 120.005 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK {0.000 4.167} 8.333 120.005 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKFABRIC {0.000 4.167} 8.333 120.005 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK {0.000 4.167} 8.333 120.005 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKFABRIC {0.000 4.167} 8.333 120.005 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK {0.000 4.167} 8.333 120.005 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKFABRIC {0.000 4.167} 8.333 120.005 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK {0.000 4.167} 8.333 120.005 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKFABRIC {0.000 4.167} 8.333 120.005 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK {0.000 4.167} 8.333 120.005 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKFABRIC {0.000 4.167} 8.333 120.005 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK {0.000 4.167} 8.333 120.005 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKFABRIC {0.000 4.167} 8.333 120.005 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK {0.000 4.167} 8.333 120.005 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKFABRIC {0.000 4.167} 8.333 120.005 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK {0.000 4.167} 8.333 120.005 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKFABRIC {0.000 4.167} 8.333 120.005 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK {0.000 4.167} 8.333 120.005 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLKFABRIC {0.000 4.167} 8.333 120.005 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK {0.000 4.167} 8.333 120.005 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLKFABRIC {0.000 4.167} 8.333 120.005 osc125_a {0.000 4.000} 8.000 125.000 clk125_ub {0.000 4.000} 8.000 125.000 clk62_5_ub {0.000 8.000} 16.000 62.500 clk_ipb_ub {0.000 16.000} 32.000 31.250 osc125_b {0.000 4.000} 8.000 125.000 rxWordclkl12_1 {0.000 4.100} 8.200 121.951 rxWordclkl12_2 {0.000 4.100} 8.200 121.951 rxWordclkl12_3 {0.000 4.100} 8.200 121.951 rxWordclkl12_4 {0.000 4.100} 8.200 121.951 rxWordclkl12_5 {0.000 4.100} 8.200 121.951 rxWordclkl12_6 {0.000 4.100} 8.200 121.951 rxWordclkl12_7 {0.000 4.100} 8.200 121.951 rxWordclkl12_8 {0.000 4.100} 8.200 121.951 rxWordclkl8_1 {0.000 4.100} 8.200 121.951 rxWordclkl8_2 {0.000 4.100} 8.200 121.951 rxWordclkl8_3 {0.000 4.100} 8.200 121.951 rxWordclkl8_4 {0.000 4.100} 8.200 121.951 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i/RXOUTCLK {0.000 8.000} 16.000 62.500 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i/TXOUTCLK {0.000 8.000} 16.000 62.500 ttc_mgt_xpoint_a {0.000 4.167} 8.333 120.005 ttc_mgt_xpoint_b {0.000 12.475} 24.951 40.079 ttc_mgt_xpoint_c {0.000 4.167} 8.333 120.005 txWordclkl12_1 {0.000 4.100} 8.200 121.951 txWordclkl12_2 {0.000 4.100} 8.200 121.951 txWordclkl12_3 {0.000 4.100} 8.200 121.951 txWordclkl12_4 {0.000 4.100} 8.200 121.951 txWordclkl12_5 {0.000 4.100} 8.200 121.951 txWordclkl12_6 {0.000 4.100} 8.200 121.951 txWordclkl12_7 {0.000 4.100} 8.200 121.951 txWordclkl12_8 {0.000 4.100} 8.200 121.951 txWordclkl8_1 {0.000 4.100} 8.200 121.951 txWordclkl8_2 {0.000 4.100} 8.200 121.951 txWordclkl8_3 {0.000 4.100} 8.200 121.951 txWordclkl8_4 {0.000 4.100} 8.200 121.951 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- clk_o_39_997 12.076 0.000 0 145 fabric_clk 7.475 0.000 0 1 fabric_clk_FBOUT 3.668 0.000 0 63793 0.052 0.000 0 63793 7.475 0.000 0 39451 clk_o_40_08_phase_mon_mmcm_1 7.451 0.000 0 3 clk_o_39_997_phase_mon_mmcm_2 23.544 0.000 0 2 clkfbout_phase_mon_mmcm_2 25.296 0.000 0 3 clkfbout_phase_mon_mmcm_1 48.831 0.000 0 2 fabric_clk_PSOUT 23.651 0.000 0 13 0.145 0.000 0 13 12.076 0.000 0 15 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK 5.909 0.000 0 2 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK 5.909 0.000 0 2 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK 5.909 0.000 0 2 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK 5.909 0.000 0 2 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK 5.909 0.000 0 2 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK 5.909 0.000 0 2 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK 5.909 0.000 0 2 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK 5.909 0.000 0 2 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK 5.909 0.000 0 2 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK 5.909 0.000 0 2 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK 5.909 0.000 0 2 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK 5.909 0.000 0 2 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK 5.909 0.000 0 2 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK 5.909 0.000 0 2 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK 5.909 0.000 0 2 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK 5.909 0.000 0 2 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK 5.909 0.000 0 2 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK 5.909 0.000 0 2 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK 5.909 0.000 0 2 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK 5.909 0.000 0 2 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK 5.909 0.000 0 2 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK 5.909 0.000 0 2 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK 5.909 0.000 0 2 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK 5.909 0.000 0 2 osc125_a 7.029 0.000 0 7 0.172 0.000 0 7 2.000 0.000 0 14 clk125_ub 2.313 0.000 0 9570 0.070 0.000 0 9570 3.358 0.000 0 4652 clk62_5_ub 13.466 0.000 0 151 0.151 0.000 0 151 7.600 0.000 0 120 clk_ipb_ub 10.972 0.000 0 202102 0.051 0.000 0 202102 15.358 0.000 0 82110 rxWordclkl12_1 3.677 0.000 0 2053 0.093 0.000 0 1975 3.458 0.000 0 1055 rxWordclkl12_2 2.628 0.000 0 2053 0.085 0.000 0 1975 3.458 0.000 0 1055 rxWordclkl12_3 3.616 0.000 0 2053 0.095 0.000 0 1975 3.458 0.000 0 1055 rxWordclkl12_4 3.660 0.000 0 2053 0.092 0.000 0 1975 3.458 0.000 0 1055 rxWordclkl12_5 3.903 0.000 0 2053 0.104 0.000 0 1975 3.458 0.000 0 1055 rxWordclkl12_6 3.344 0.000 0 2053 0.084 0.000 0 1975 3.458 0.000 0 1055 rxWordclkl12_7 3.220 0.000 0 2053 0.084 0.000 0 1975 3.458 0.000 0 1055 rxWordclkl12_8 3.878 0.000 0 2053 0.085 0.000 0 1975 3.458 0.000 0 1055 rxWordclkl8_1 3.373 0.000 0 2053 0.108 0.000 0 1975 3.458 0.000 0 1055 rxWordclkl8_2 2.599 0.000 0 2053 0.085 0.000 0 1975 3.458 0.000 0 1055 rxWordclkl8_3 3.589 0.000 0 2053 0.086 0.000 0 1975 3.458 0.000 0 1055 rxWordclkl8_4 3.827 0.000 0 2053 0.106 0.000 0 1975 3.458 0.000 0 1055 ttc_mgt_xpoint_a 7.362 0.000 0 28 0.172 0.000 0 28 3.524 0.000 0 45 ttc_mgt_xpoint_c 2.779 0.000 0 60 0.172 0.000 0 60 3.524 0.000 0 95 txWordclkl12_1 4.197 0.000 0 272 0.108 0.000 0 272 3.458 0.000 0 221 txWordclkl12_2 4.020 0.000 0 272 0.108 0.000 0 272 3.458 0.000 0 221 txWordclkl12_3 4.288 0.000 0 272 0.108 0.000 0 272 3.458 0.000 0 221 txWordclkl12_4 5.158 0.000 0 276 0.094 0.000 0 276 3.458 0.000 0 225 txWordclkl12_5 4.766 0.000 0 272 0.108 0.000 0 272 3.458 0.000 0 221 txWordclkl12_6 4.551 0.000 0 272 0.108 0.000 0 272 3.458 0.000 0 221 txWordclkl12_7 5.223 0.000 0 272 0.083 0.000 0 272 3.458 0.000 0 221 txWordclkl12_8 4.422 0.000 0 272 0.051 0.000 0 272 3.458 0.000 0 221 txWordclkl8_1 5.317 0.000 0 272 0.108 0.000 0 272 3.458 0.000 0 221 txWordclkl8_2 5.193 0.000 0 272 0.094 0.000 0 272 3.458 0.000 0 221 txWordclkl8_3 5.511 0.000 0 272 0.078 0.000 0 272 3.458 0.000 0 221 txWordclkl8_4 5.063 0.000 0 272 0.084 0.000 0 272 3.458 0.000 0 221 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- clk62_5_ub clk125_ub 6.010 0.000 0 26 0.086 0.000 0 26 clk_ipb_ub clk125_ub 0.619 0.000 0 360 0.057 0.000 0 360 clk125_ub clk62_5_ub 6.115 0.000 0 22 0.076 0.000 0 22 clk125_ub clk_ipb_ub 3.143 0.000 0 446 0.063 0.000 0 446 ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- **async_default** clk125_ub clk125_ub 4.195 0.000 0 44 0.527 0.000 0 44 **async_default** clk_ipb_ub clk_ipb_ub 15.713 0.000 0 40858 0.107 0.000 0 40858 **async_default** fabric_clk_FBOUT fabric_clk_FBOUT 16.982 0.000 0 4668 0.227 0.000 0 4668 **async_default** rxWordclkl12_1 rxWordclkl12_1 4.471 0.000 0 416 0.287 0.000 0 416 **async_default** rxWordclkl12_2 rxWordclkl12_2 4.567 0.000 0 416 0.307 0.000 0 416 **async_default** rxWordclkl12_3 rxWordclkl12_3 4.389 0.000 0 416 0.336 0.000 0 416 **async_default** rxWordclkl12_4 rxWordclkl12_4 5.093 0.000 0 416 0.295 0.000 0 416 **async_default** rxWordclkl12_5 rxWordclkl12_5 4.879 0.000 0 416 0.302 0.000 0 416 **async_default** rxWordclkl12_6 rxWordclkl12_6 4.575 0.000 0 416 0.290 0.000 0 416 **async_default** rxWordclkl12_7 rxWordclkl12_7 4.835 0.000 0 416 0.297 0.000 0 416 **async_default** rxWordclkl12_8 rxWordclkl12_8 4.660 0.000 0 416 0.340 0.000 0 416 **async_default** rxWordclkl8_1 rxWordclkl8_1 5.120 0.000 0 416 0.257 0.000 0 416 **async_default** rxWordclkl8_2 rxWordclkl8_2 4.338 0.000 0 416 0.351 0.000 0 416 **async_default** rxWordclkl8_3 rxWordclkl8_3 5.017 0.000 0 416 0.352 0.000 0 416 **async_default** rxWordclkl8_4 rxWordclkl8_4 5.184 0.000 0 416 0.390 0.000 0 416 **async_default** txWordclkl12_1 txWordclkl12_1 4.965 0.000 0 2 1.511 0.000 0 2 **async_default** txWordclkl12_2 txWordclkl12_2 5.374 0.000 0 2 1.470 0.000 0 2 **async_default** txWordclkl12_3 txWordclkl12_3 5.075 0.000 0 2 1.670 0.000 0 2 **async_default** txWordclkl12_4 txWordclkl12_4 5.472 0.000 0 2 1.439 0.000 0 2 **async_default** txWordclkl12_5 txWordclkl12_5 5.871 0.000 0 2 1.219 0.000 0 2 **async_default** txWordclkl12_6 txWordclkl12_6 4.987 0.000 0 2 1.700 0.000 0 2 **async_default** txWordclkl12_7 txWordclkl12_7 5.485 0.000 0 2 1.193 0.000 0 2 **async_default** txWordclkl12_8 txWordclkl12_8 5.331 0.000 0 2 1.471 0.000 0 2 **async_default** txWordclkl8_1 txWordclkl8_1 5.734 0.000 0 2 1.270 0.000 0 2 **async_default** txWordclkl8_2 txWordclkl8_2 5.572 0.000 0 2 1.363 0.000 0 2 **async_default** txWordclkl8_3 txWordclkl8_3 5.706 0.000 0 2 1.287 0.000 0 2 **async_default** txWordclkl8_4 txWordclkl8_4 5.805 0.000 0 2 1.220 0.000 0 2 ------------------------------------------------------------------------------------------------ | Timing Details | -------------- ------------------------------------------------------------------------------------------------ --------------------------------------------------------------------------------------------------- From Clock: clk_o_39_997 To Clock: clk_o_39_997 Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 12.076ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_o_39_997 Waveform(ns): { 0.000 12.477 } Period(ns): 24.953 Sources: { ngFEC/dmdt_clk/mmcm2/U0/clkout1_buf/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a FDRE/C n/a 0.750 24.953 24.203 SLICE_X125Y246 ngFEC/dmdt_meas/DMTD_A/new_edge_sreg_reg[5]/C Min Period n/a FDRE/C n/a 0.750 24.953 24.203 SLICE_X132Y241 ngFEC/dmdt_meas/DMTD_A/tag_o_reg[6]/C Min Period n/a FDRE/C n/a 0.750 24.953 24.203 SLICE_X132Y241 ngFEC/dmdt_meas/DMTD_A/tag_o_reg[7]/C Min Period n/a FDRE/C n/a 0.750 24.953 24.203 SLICE_X132Y241 ngFEC/dmdt_meas/DMTD_A/tag_o_reg[8]/C Min Period n/a FDRE/C n/a 0.750 24.953 24.203 SLICE_X132Y241 ngFEC/dmdt_meas/DMTD_A/tag_o_reg[9]/C Min Period n/a FDRE/C n/a 0.750 24.953 24.203 SLICE_X124Y244 ngFEC/dmdt_meas/DMTD_B/new_edge_sreg_reg[5]/C Min Period n/a FDRE/C n/a 0.750 24.953 24.203 SLICE_X133Y241 ngFEC/dmdt_meas/DMTD_B/tag_o_reg[5]/C Min Period n/a FDRE/C n/a 0.750 24.953 24.203 SLICE_X133Y241 ngFEC/dmdt_meas/DMTD_B/tag_o_reg[6]/C Min Period n/a FDRE/C n/a 0.750 24.953 24.203 SLICE_X133Y241 ngFEC/dmdt_meas/DMTD_B/tag_o_reg[9]/C Min Period n/a FDSE/C n/a 0.700 24.953 24.253 SLICE_X133Y243 ngFEC/dmdt_meas/DMTD_A/FSM_onehot_state_reg[0]/C Low Pulse Width Fast FDRE/C n/a 0.400 12.476 12.076 SLICE_X132Y241 ngFEC/dmdt_meas/DMTD_A/tag_o_reg[6]/C Low Pulse Width Fast FDRE/C n/a 0.400 12.476 12.076 SLICE_X132Y241 ngFEC/dmdt_meas/DMTD_A/tag_o_reg[7]/C Low Pulse Width Fast FDRE/C n/a 0.400 12.476 12.076 SLICE_X132Y241 ngFEC/dmdt_meas/DMTD_A/tag_o_reg[8]/C Low Pulse Width Fast FDRE/C n/a 0.400 12.476 12.076 SLICE_X132Y241 ngFEC/dmdt_meas/DMTD_A/tag_o_reg[9]/C Low Pulse Width Fast FDRE/C n/a 0.400 12.476 12.076 SLICE_X133Y241 ngFEC/dmdt_meas/DMTD_B/tag_o_reg[5]/C Low Pulse Width Fast FDRE/C n/a 0.400 12.476 12.076 SLICE_X133Y241 ngFEC/dmdt_meas/DMTD_B/tag_o_reg[6]/C Low Pulse Width Fast FDRE/C n/a 0.400 12.476 12.076 SLICE_X133Y241 ngFEC/dmdt_meas/DMTD_B/tag_o_reg[9]/C Low Pulse Width Slow FDRE/C n/a 0.400 12.477 12.076 SLICE_X125Y246 ngFEC/dmdt_meas/DMTD_A/new_edge_sreg_reg[5]/C Low Pulse Width Fast FDRE/C n/a 0.400 12.477 12.076 SLICE_X125Y246 ngFEC/dmdt_meas/DMTD_A/new_edge_sreg_reg[5]/C Low Pulse Width Slow FDRE/C n/a 0.400 12.477 12.076 SLICE_X132Y241 ngFEC/dmdt_meas/DMTD_A/tag_o_reg[6]/C High Pulse Width Slow FDSE/C n/a 0.350 12.477 12.127 SLICE_X133Y243 ngFEC/dmdt_meas/DMTD_A/FSM_onehot_state_reg[0]/C High Pulse Width Fast FDSE/C n/a 0.350 12.477 12.127 SLICE_X133Y243 ngFEC/dmdt_meas/DMTD_A/FSM_onehot_state_reg[0]/C High Pulse Width Slow FDRE/C n/a 0.350 12.477 12.127 SLICE_X133Y243 ngFEC/dmdt_meas/DMTD_A/FSM_onehot_state_reg[1]/C High Pulse Width Fast FDRE/C n/a 0.350 12.477 12.127 SLICE_X133Y243 ngFEC/dmdt_meas/DMTD_A/FSM_onehot_state_reg[1]/C High Pulse Width Slow FDRE/C n/a 0.350 12.477 12.127 SLICE_X133Y243 ngFEC/dmdt_meas/DMTD_A/FSM_onehot_state_reg[2]/C High Pulse Width Fast FDRE/C n/a 0.350 12.477 12.127 SLICE_X133Y243 ngFEC/dmdt_meas/DMTD_A/FSM_onehot_state_reg[2]/C High Pulse Width Slow FDRE/C n/a 0.350 12.477 12.127 SLICE_X133Y238 ngFEC/dmdt_meas/DMTD_A/free_cntr_reg[0]/C High Pulse Width Fast FDRE/C n/a 0.350 12.477 12.127 SLICE_X133Y238 ngFEC/dmdt_meas/DMTD_A/free_cntr_reg[0]/C High Pulse Width Slow FDRE/C n/a 0.350 12.477 12.127 SLICE_X130Y239 ngFEC/dmdt_meas/DMTD_A/free_cntr_reg[10]/C High Pulse Width Fast FDRE/C n/a 0.350 12.477 12.127 SLICE_X130Y239 ngFEC/dmdt_meas/DMTD_A/free_cntr_reg[10]/C --------------------------------------------------------------------------------------------------- From Clock: fabric_clk To Clock: fabric_clk Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 7.475ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: fabric_clk Waveform(ns): { 0.000 12.476 } Period(ns): 24.951 Sources: { fabric_clk_p } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.071 24.951 23.880 MMCME2_ADV_X0Y0 ngFEC/fabric_clk_MMCME2/CLKIN1 Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 24.951 75.049 MMCME2_ADV_X0Y0 ngFEC/fabric_clk_MMCME2/CLKIN1 Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 5.000 12.475 7.475 MMCME2_ADV_X0Y0 ngFEC/fabric_clk_MMCME2/CLKIN1 Low Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 5.000 12.475 7.475 MMCME2_ADV_X0Y0 ngFEC/fabric_clk_MMCME2/CLKIN1 High Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 5.000 12.476 7.475 MMCME2_ADV_X0Y0 ngFEC/fabric_clk_MMCME2/CLKIN1 High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 5.000 12.476 7.476 MMCME2_ADV_X0Y0 ngFEC/fabric_clk_MMCME2/CLKIN1 --------------------------------------------------------------------------------------------------- From Clock: fabric_clk_FBOUT To Clock: fabric_clk_FBOUT Setup : 0 Failing Endpoints, Worst Slack 3.668ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.052ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 7.475ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.668ns (required time - arrival time) Source: ngFEC/fabric_clk_div2_reg/C (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[61]/CE (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: fabric_clk_FBOUT Path Type: Setup (Max at Slow Process Corner) Requirement: 24.951ns (fabric_clk_FBOUT rise@24.951ns - fabric_clk_FBOUT rise@0.000ns) Data Path Delay: 20.690ns (logic 0.302ns (1.460%) route 20.388ns (98.540%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.311ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.106ns = ( 26.057 - 24.951 ) Source Clock Delay (SCD): 1.426ns Clock Pessimism Removal (CPR): 0.009ns Clock Uncertainty: 0.081ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.146ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.802 0.802 r ngFEC/fclk_ibuf/O net (fo=1, routed) 1.081 1.883 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -4.638 -2.755 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 2.546 -0.209 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -0.116 r ngFEC/fclk_bufg/O net (fo=39427, routed) 1.542 1.426 ngFEC/CLKFBIN SLICE_X182Y132 FDRE r ngFEC/fabric_clk_div2_reg/C ------------------------------------------------------------------- ------------------- SLICE_X182Y132 FDRE (Prop_fdre_C_Q) 0.259 1.685 f ngFEC/fabric_clk_div2_reg/Q net (fo=2709, routed) 7.129 8.814 ngFEC/SFP_GEN[10].ngCCM_gbt/fabric_clk_div2 SLICE_X148Y41 LUT1 (Prop_lut1_I0_O) 0.043 8.857 r ngFEC/SFP_GEN[10].ngCCM_gbt/TX_Word_tmp[79]_i_1/O net (fo=361, routed) 13.259 22.117 ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[79]_0[0] SLICE_X121Y289 FDRE r ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[61]/CE ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 24.951 24.951 r AK18 0.000 24.951 r fabric_clk_p (IN) net (fo=0) 0.000 24.951 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.725 25.676 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.986 26.662 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -4.330 22.332 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 2.411 24.743 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 24.826 r ngFEC/fclk_bufg/O net (fo=39427, routed) 1.231 26.057 ngFEC/SFP_GEN[4].ngCCM_gbt/CLKFBIN SLICE_X121Y289 FDRE r ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[61]/C clock pessimism 0.009 26.066 clock uncertainty -0.081 25.986 SLICE_X121Y289 FDRE (Setup_fdre_C_CE) -0.201 25.785 ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[61] ------------------------------------------------------------------- required time 25.785 arrival time -22.117 ------------------------------------------------------------------- slack 3.668 Slack (MET) : 3.722ns (required time - arrival time) Source: ngFEC/fabric_clk_div2_reg/C (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[35]/CE (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: fabric_clk_FBOUT Path Type: Setup (Max at Slow Process Corner) Requirement: 24.951ns (fabric_clk_FBOUT rise@24.951ns - fabric_clk_FBOUT rise@0.000ns) Data Path Delay: 20.695ns (logic 0.302ns (1.459%) route 20.393ns (98.541%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.252ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.165ns = ( 26.116 - 24.951 ) Source Clock Delay (SCD): 1.426ns Clock Pessimism Removal (CPR): 0.009ns Clock Uncertainty: 0.081ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.146ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.802 0.802 r ngFEC/fclk_ibuf/O net (fo=1, routed) 1.081 1.883 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -4.638 -2.755 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 2.546 -0.209 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -0.116 r ngFEC/fclk_bufg/O net (fo=39427, routed) 1.542 1.426 ngFEC/CLKFBIN SLICE_X182Y132 FDRE r ngFEC/fabric_clk_div2_reg/C ------------------------------------------------------------------- ------------------- SLICE_X182Y132 FDRE (Prop_fdre_C_Q) 0.259 1.685 f ngFEC/fabric_clk_div2_reg/Q net (fo=2709, routed) 7.129 8.814 ngFEC/SFP_GEN[10].ngCCM_gbt/fabric_clk_div2 SLICE_X148Y41 LUT1 (Prop_lut1_I0_O) 0.043 8.857 r ngFEC/SFP_GEN[10].ngCCM_gbt/TX_Word_tmp[79]_i_1/O net (fo=361, routed) 13.264 22.122 ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[79]_0[0] SLICE_X133Y292 FDRE r ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[35]/CE ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 24.951 24.951 r AK18 0.000 24.951 r fabric_clk_p (IN) net (fo=0) 0.000 24.951 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.725 25.676 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.986 26.662 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -4.330 22.332 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 2.411 24.743 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 24.826 r ngFEC/fclk_bufg/O net (fo=39427, routed) 1.290 26.116 ngFEC/SFP_GEN[4].ngCCM_gbt/CLKFBIN SLICE_X133Y292 FDRE r ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[35]/C clock pessimism 0.009 26.125 clock uncertainty -0.081 26.045 SLICE_X133Y292 FDRE (Setup_fdre_C_CE) -0.201 25.844 ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[35] ------------------------------------------------------------------- required time 25.844 arrival time -22.122 ------------------------------------------------------------------- slack 3.722 Slack (MET) : 3.722ns (required time - arrival time) Source: ngFEC/fabric_clk_div2_reg/C (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[39]/CE (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: fabric_clk_FBOUT Path Type: Setup (Max at Slow Process Corner) Requirement: 24.951ns (fabric_clk_FBOUT rise@24.951ns - fabric_clk_FBOUT rise@0.000ns) Data Path Delay: 20.695ns (logic 0.302ns (1.459%) route 20.393ns (98.541%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.252ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.165ns = ( 26.116 - 24.951 ) Source Clock Delay (SCD): 1.426ns Clock Pessimism Removal (CPR): 0.009ns Clock Uncertainty: 0.081ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.146ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.802 0.802 r ngFEC/fclk_ibuf/O net (fo=1, routed) 1.081 1.883 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -4.638 -2.755 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 2.546 -0.209 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -0.116 r ngFEC/fclk_bufg/O net (fo=39427, routed) 1.542 1.426 ngFEC/CLKFBIN SLICE_X182Y132 FDRE r ngFEC/fabric_clk_div2_reg/C ------------------------------------------------------------------- ------------------- SLICE_X182Y132 FDRE (Prop_fdre_C_Q) 0.259 1.685 f ngFEC/fabric_clk_div2_reg/Q net (fo=2709, routed) 7.129 8.814 ngFEC/SFP_GEN[10].ngCCM_gbt/fabric_clk_div2 SLICE_X148Y41 LUT1 (Prop_lut1_I0_O) 0.043 8.857 r ngFEC/SFP_GEN[10].ngCCM_gbt/TX_Word_tmp[79]_i_1/O net (fo=361, routed) 13.264 22.122 ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[79]_0[0] SLICE_X133Y292 FDRE r ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[39]/CE ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 24.951 24.951 r AK18 0.000 24.951 r fabric_clk_p (IN) net (fo=0) 0.000 24.951 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.725 25.676 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.986 26.662 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -4.330 22.332 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 2.411 24.743 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 24.826 r ngFEC/fclk_bufg/O net (fo=39427, routed) 1.290 26.116 ngFEC/SFP_GEN[4].ngCCM_gbt/CLKFBIN SLICE_X133Y292 FDRE r ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[39]/C clock pessimism 0.009 26.125 clock uncertainty -0.081 26.045 SLICE_X133Y292 FDRE (Setup_fdre_C_CE) -0.201 25.844 ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[39] ------------------------------------------------------------------- required time 25.844 arrival time -22.122 ------------------------------------------------------------------- slack 3.722 Slack (MET) : 3.723ns (required time - arrival time) Source: ngFEC/fabric_clk_div2_reg/C (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[41]/CE (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: fabric_clk_FBOUT Path Type: Setup (Max at Slow Process Corner) Requirement: 24.951ns (fabric_clk_FBOUT rise@24.951ns - fabric_clk_FBOUT rise@0.000ns) Data Path Delay: 20.662ns (logic 0.302ns (1.462%) route 20.360ns (98.538%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.307ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.110ns = ( 26.061 - 24.951 ) Source Clock Delay (SCD): 1.426ns Clock Pessimism Removal (CPR): 0.009ns Clock Uncertainty: 0.081ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.146ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.802 0.802 r ngFEC/fclk_ibuf/O net (fo=1, routed) 1.081 1.883 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -4.638 -2.755 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 2.546 -0.209 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -0.116 r ngFEC/fclk_bufg/O net (fo=39427, routed) 1.542 1.426 ngFEC/CLKFBIN SLICE_X182Y132 FDRE r ngFEC/fabric_clk_div2_reg/C ------------------------------------------------------------------- ------------------- SLICE_X182Y132 FDRE (Prop_fdre_C_Q) 0.259 1.685 f ngFEC/fabric_clk_div2_reg/Q net (fo=2709, routed) 7.129 8.814 ngFEC/SFP_GEN[10].ngCCM_gbt/fabric_clk_div2 SLICE_X148Y41 LUT1 (Prop_lut1_I0_O) 0.043 8.857 r ngFEC/SFP_GEN[10].ngCCM_gbt/TX_Word_tmp[79]_i_1/O net (fo=361, routed) 13.231 22.088 ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[79]_0[0] SLICE_X130Y295 FDRE r ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[41]/CE ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 24.951 24.951 r AK18 0.000 24.951 r fabric_clk_p (IN) net (fo=0) 0.000 24.951 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.725 25.676 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.986 26.662 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -4.330 22.332 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 2.411 24.743 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 24.826 r ngFEC/fclk_bufg/O net (fo=39427, routed) 1.235 26.061 ngFEC/SFP_GEN[4].ngCCM_gbt/CLKFBIN SLICE_X130Y295 FDRE r ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[41]/C clock pessimism 0.009 26.070 clock uncertainty -0.081 25.990 SLICE_X130Y295 FDRE (Setup_fdre_C_CE) -0.178 25.812 ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[41] ------------------------------------------------------------------- required time 25.812 arrival time -22.088 ------------------------------------------------------------------- slack 3.723 Slack (MET) : 3.763ns (required time - arrival time) Source: ngFEC/fabric_clk_div2_reg/C (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[55]/CE (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: fabric_clk_FBOUT Path Type: Setup (Max at Slow Process Corner) Requirement: 24.951ns (fabric_clk_FBOUT rise@24.951ns - fabric_clk_FBOUT rise@0.000ns) Data Path Delay: 20.616ns (logic 0.302ns (1.465%) route 20.314ns (98.535%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.313ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.104ns = ( 26.055 - 24.951 ) Source Clock Delay (SCD): 1.426ns Clock Pessimism Removal (CPR): 0.009ns Clock Uncertainty: 0.081ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.146ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.802 0.802 r ngFEC/fclk_ibuf/O net (fo=1, routed) 1.081 1.883 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -4.638 -2.755 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 2.546 -0.209 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -0.116 r ngFEC/fclk_bufg/O net (fo=39427, routed) 1.542 1.426 ngFEC/CLKFBIN SLICE_X182Y132 FDRE r ngFEC/fabric_clk_div2_reg/C ------------------------------------------------------------------- ------------------- SLICE_X182Y132 FDRE (Prop_fdre_C_Q) 0.259 1.685 f ngFEC/fabric_clk_div2_reg/Q net (fo=2709, routed) 7.129 8.814 ngFEC/SFP_GEN[10].ngCCM_gbt/fabric_clk_div2 SLICE_X148Y41 LUT1 (Prop_lut1_I0_O) 0.043 8.857 r ngFEC/SFP_GEN[10].ngCCM_gbt/TX_Word_tmp[79]_i_1/O net (fo=361, routed) 13.185 22.043 ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[79]_0[0] SLICE_X118Y285 FDRE r ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[55]/CE ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 24.951 24.951 r AK18 0.000 24.951 r fabric_clk_p (IN) net (fo=0) 0.000 24.951 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.725 25.676 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.986 26.662 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -4.330 22.332 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 2.411 24.743 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 24.826 r ngFEC/fclk_bufg/O net (fo=39427, routed) 1.229 26.055 ngFEC/SFP_GEN[4].ngCCM_gbt/CLKFBIN SLICE_X118Y285 FDRE r ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[55]/C clock pessimism 0.009 26.064 clock uncertainty -0.081 25.984 SLICE_X118Y285 FDRE (Setup_fdre_C_CE) -0.178 25.806 ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[55] ------------------------------------------------------------------- required time 25.806 arrival time -22.043 ------------------------------------------------------------------- slack 3.763 Slack (MET) : 3.789ns (required time - arrival time) Source: ngFEC/fabric_clk_div2_reg/C (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[53]/CE (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: fabric_clk_FBOUT Path Type: Setup (Max at Slow Process Corner) Requirement: 24.951ns (fabric_clk_FBOUT rise@24.951ns - fabric_clk_FBOUT rise@0.000ns) Data Path Delay: 20.592ns (logic 0.302ns (1.467%) route 20.290ns (98.533%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.311ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.106ns = ( 26.057 - 24.951 ) Source Clock Delay (SCD): 1.426ns Clock Pessimism Removal (CPR): 0.009ns Clock Uncertainty: 0.081ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.146ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.802 0.802 r ngFEC/fclk_ibuf/O net (fo=1, routed) 1.081 1.883 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -4.638 -2.755 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 2.546 -0.209 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -0.116 r ngFEC/fclk_bufg/O net (fo=39427, routed) 1.542 1.426 ngFEC/CLKFBIN SLICE_X182Y132 FDRE r ngFEC/fabric_clk_div2_reg/C ------------------------------------------------------------------- ------------------- SLICE_X182Y132 FDRE (Prop_fdre_C_Q) 0.259 1.685 f ngFEC/fabric_clk_div2_reg/Q net (fo=2709, routed) 7.129 8.814 ngFEC/SFP_GEN[10].ngCCM_gbt/fabric_clk_div2 SLICE_X148Y41 LUT1 (Prop_lut1_I0_O) 0.043 8.857 r ngFEC/SFP_GEN[10].ngCCM_gbt/TX_Word_tmp[79]_i_1/O net (fo=361, routed) 13.161 22.018 ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[79]_0[0] SLICE_X118Y289 FDRE r ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[53]/CE ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 24.951 24.951 r AK18 0.000 24.951 r fabric_clk_p (IN) net (fo=0) 0.000 24.951 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.725 25.676 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.986 26.662 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -4.330 22.332 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 2.411 24.743 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 24.826 r ngFEC/fclk_bufg/O net (fo=39427, routed) 1.231 26.057 ngFEC/SFP_GEN[4].ngCCM_gbt/CLKFBIN SLICE_X118Y289 FDRE r ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[53]/C clock pessimism 0.009 26.066 clock uncertainty -0.081 25.986 SLICE_X118Y289 FDRE (Setup_fdre_C_CE) -0.178 25.808 ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[53] ------------------------------------------------------------------- required time 25.808 arrival time -22.018 ------------------------------------------------------------------- slack 3.789 Slack (MET) : 3.789ns (required time - arrival time) Source: ngFEC/fabric_clk_div2_reg/C (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[59]/CE (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: fabric_clk_FBOUT Path Type: Setup (Max at Slow Process Corner) Requirement: 24.951ns (fabric_clk_FBOUT rise@24.951ns - fabric_clk_FBOUT rise@0.000ns) Data Path Delay: 20.592ns (logic 0.302ns (1.467%) route 20.290ns (98.533%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.311ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.106ns = ( 26.057 - 24.951 ) Source Clock Delay (SCD): 1.426ns Clock Pessimism Removal (CPR): 0.009ns Clock Uncertainty: 0.081ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.146ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.802 0.802 r ngFEC/fclk_ibuf/O net (fo=1, routed) 1.081 1.883 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -4.638 -2.755 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 2.546 -0.209 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -0.116 r ngFEC/fclk_bufg/O net (fo=39427, routed) 1.542 1.426 ngFEC/CLKFBIN SLICE_X182Y132 FDRE r ngFEC/fabric_clk_div2_reg/C ------------------------------------------------------------------- ------------------- SLICE_X182Y132 FDRE (Prop_fdre_C_Q) 0.259 1.685 f ngFEC/fabric_clk_div2_reg/Q net (fo=2709, routed) 7.129 8.814 ngFEC/SFP_GEN[10].ngCCM_gbt/fabric_clk_div2 SLICE_X148Y41 LUT1 (Prop_lut1_I0_O) 0.043 8.857 r ngFEC/SFP_GEN[10].ngCCM_gbt/TX_Word_tmp[79]_i_1/O net (fo=361, routed) 13.161 22.018 ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[79]_0[0] SLICE_X118Y289 FDRE r ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[59]/CE ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 24.951 24.951 r AK18 0.000 24.951 r fabric_clk_p (IN) net (fo=0) 0.000 24.951 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.725 25.676 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.986 26.662 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -4.330 22.332 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 2.411 24.743 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 24.826 r ngFEC/fclk_bufg/O net (fo=39427, routed) 1.231 26.057 ngFEC/SFP_GEN[4].ngCCM_gbt/CLKFBIN SLICE_X118Y289 FDRE r ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[59]/C clock pessimism 0.009 26.066 clock uncertainty -0.081 25.986 SLICE_X118Y289 FDRE (Setup_fdre_C_CE) -0.178 25.808 ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[59] ------------------------------------------------------------------- required time 25.808 arrival time -22.018 ------------------------------------------------------------------- slack 3.789 Slack (MET) : 3.789ns (required time - arrival time) Source: ngFEC/fabric_clk_div2_reg/C (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[63]/CE (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: fabric_clk_FBOUT Path Type: Setup (Max at Slow Process Corner) Requirement: 24.951ns (fabric_clk_FBOUT rise@24.951ns - fabric_clk_FBOUT rise@0.000ns) Data Path Delay: 20.592ns (logic 0.302ns (1.467%) route 20.290ns (98.533%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.311ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.106ns = ( 26.057 - 24.951 ) Source Clock Delay (SCD): 1.426ns Clock Pessimism Removal (CPR): 0.009ns Clock Uncertainty: 0.081ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.146ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.802 0.802 r ngFEC/fclk_ibuf/O net (fo=1, routed) 1.081 1.883 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -4.638 -2.755 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 2.546 -0.209 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -0.116 r ngFEC/fclk_bufg/O net (fo=39427, routed) 1.542 1.426 ngFEC/CLKFBIN SLICE_X182Y132 FDRE r ngFEC/fabric_clk_div2_reg/C ------------------------------------------------------------------- ------------------- SLICE_X182Y132 FDRE (Prop_fdre_C_Q) 0.259 1.685 f ngFEC/fabric_clk_div2_reg/Q net (fo=2709, routed) 7.129 8.814 ngFEC/SFP_GEN[10].ngCCM_gbt/fabric_clk_div2 SLICE_X148Y41 LUT1 (Prop_lut1_I0_O) 0.043 8.857 r ngFEC/SFP_GEN[10].ngCCM_gbt/TX_Word_tmp[79]_i_1/O net (fo=361, routed) 13.161 22.018 ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[79]_0[0] SLICE_X118Y289 FDRE r ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[63]/CE ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 24.951 24.951 r AK18 0.000 24.951 r fabric_clk_p (IN) net (fo=0) 0.000 24.951 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.725 25.676 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.986 26.662 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -4.330 22.332 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 2.411 24.743 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 24.826 r ngFEC/fclk_bufg/O net (fo=39427, routed) 1.231 26.057 ngFEC/SFP_GEN[4].ngCCM_gbt/CLKFBIN SLICE_X118Y289 FDRE r ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[63]/C clock pessimism 0.009 26.066 clock uncertainty -0.081 25.986 SLICE_X118Y289 FDRE (Setup_fdre_C_CE) -0.178 25.808 ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[63] ------------------------------------------------------------------- required time 25.808 arrival time -22.018 ------------------------------------------------------------------- slack 3.789 Slack (MET) : 3.789ns (required time - arrival time) Source: ngFEC/fabric_clk_div2_reg/C (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[71]/CE (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: fabric_clk_FBOUT Path Type: Setup (Max at Slow Process Corner) Requirement: 24.951ns (fabric_clk_FBOUT rise@24.951ns - fabric_clk_FBOUT rise@0.000ns) Data Path Delay: 20.592ns (logic 0.302ns (1.467%) route 20.290ns (98.533%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.311ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.106ns = ( 26.057 - 24.951 ) Source Clock Delay (SCD): 1.426ns Clock Pessimism Removal (CPR): 0.009ns Clock Uncertainty: 0.081ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.146ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.802 0.802 r ngFEC/fclk_ibuf/O net (fo=1, routed) 1.081 1.883 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -4.638 -2.755 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 2.546 -0.209 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -0.116 r ngFEC/fclk_bufg/O net (fo=39427, routed) 1.542 1.426 ngFEC/CLKFBIN SLICE_X182Y132 FDRE r ngFEC/fabric_clk_div2_reg/C ------------------------------------------------------------------- ------------------- SLICE_X182Y132 FDRE (Prop_fdre_C_Q) 0.259 1.685 f ngFEC/fabric_clk_div2_reg/Q net (fo=2709, routed) 7.129 8.814 ngFEC/SFP_GEN[10].ngCCM_gbt/fabric_clk_div2 SLICE_X148Y41 LUT1 (Prop_lut1_I0_O) 0.043 8.857 r ngFEC/SFP_GEN[10].ngCCM_gbt/TX_Word_tmp[79]_i_1/O net (fo=361, routed) 13.161 22.018 ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[79]_0[0] SLICE_X118Y289 FDRE r ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[71]/CE ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 24.951 24.951 r AK18 0.000 24.951 r fabric_clk_p (IN) net (fo=0) 0.000 24.951 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.725 25.676 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.986 26.662 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -4.330 22.332 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 2.411 24.743 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 24.826 r ngFEC/fclk_bufg/O net (fo=39427, routed) 1.231 26.057 ngFEC/SFP_GEN[4].ngCCM_gbt/CLKFBIN SLICE_X118Y289 FDRE r ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[71]/C clock pessimism 0.009 26.066 clock uncertainty -0.081 25.986 SLICE_X118Y289 FDRE (Setup_fdre_C_CE) -0.178 25.808 ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[71] ------------------------------------------------------------------- required time 25.808 arrival time -22.018 ------------------------------------------------------------------- slack 3.789 Slack (MET) : 3.862ns (required time - arrival time) Source: ngFEC/fabric_clk_div2_reg/C (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[43]/CE (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: fabric_clk_FBOUT Path Type: Setup (Max at Slow Process Corner) Requirement: 24.951ns (fabric_clk_FBOUT rise@24.951ns - fabric_clk_FBOUT rise@0.000ns) Data Path Delay: 20.496ns (logic 0.302ns (1.473%) route 20.194ns (98.527%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.311ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.106ns = ( 26.057 - 24.951 ) Source Clock Delay (SCD): 1.426ns Clock Pessimism Removal (CPR): 0.009ns Clock Uncertainty: 0.081ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.146ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.802 0.802 r ngFEC/fclk_ibuf/O net (fo=1, routed) 1.081 1.883 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -4.638 -2.755 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 2.546 -0.209 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -0.116 r ngFEC/fclk_bufg/O net (fo=39427, routed) 1.542 1.426 ngFEC/CLKFBIN SLICE_X182Y132 FDRE r ngFEC/fabric_clk_div2_reg/C ------------------------------------------------------------------- ------------------- SLICE_X182Y132 FDRE (Prop_fdre_C_Q) 0.259 1.685 f ngFEC/fabric_clk_div2_reg/Q net (fo=2709, routed) 7.129 8.814 ngFEC/SFP_GEN[10].ngCCM_gbt/fabric_clk_div2 SLICE_X148Y41 LUT1 (Prop_lut1_I0_O) 0.043 8.857 r ngFEC/SFP_GEN[10].ngCCM_gbt/TX_Word_tmp[79]_i_1/O net (fo=361, routed) 13.066 21.923 ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[79]_0[0] SLICE_X123Y289 FDRE r ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[43]/CE ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 24.951 24.951 r AK18 0.000 24.951 r fabric_clk_p (IN) net (fo=0) 0.000 24.951 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.725 25.676 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.986 26.662 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -4.330 22.332 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 2.411 24.743 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 24.826 r ngFEC/fclk_bufg/O net (fo=39427, routed) 1.231 26.057 ngFEC/SFP_GEN[4].ngCCM_gbt/CLKFBIN SLICE_X123Y289 FDRE r ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[43]/C clock pessimism 0.009 26.066 clock uncertainty -0.081 25.986 SLICE_X123Y289 FDRE (Setup_fdre_C_CE) -0.201 25.785 ngFEC/SFP_GEN[4].ngCCM_gbt/TX_Word_tmp_reg[43] ------------------------------------------------------------------- required time 25.785 arrival time -21.923 ------------------------------------------------------------------- slack 3.862 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.052ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_CPLLLOCK/data_sync_reg6/C (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/adapt_count_reset_reg/D (rising edge-triggered cell FDSE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: fabric_clk_FBOUT Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_FBOUT rise@0.000ns - fabric_clk_FBOUT rise@0.000ns) Data Path Delay: 0.233ns (logic 0.128ns (54.963%) route 0.105ns (45.037%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.121ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.818ns Source Clock Delay (SCD): 0.838ns Clock Pessimism Removal (CPR): -0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.426 0.426 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.503 0.929 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -1.995 -1.066 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 1.173 0.107 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.133 r ngFEC/fclk_bufg/O net (fo=39427, routed) 0.705 0.838 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_CPLLLOCK/SYSCLK_IN SLICE_X187Y251 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_CPLLLOCK/data_sync_reg6/C ------------------------------------------------------------------- ------------------- SLICE_X187Y251 FDRE (Prop_fdre_C_Q) 0.100 0.938 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_CPLLLOCK/data_sync_reg6/Q net (fo=2, routed) 0.105 1.043 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_CPLLLOCK/cplllock_sync SLICE_X187Y249 LUT6 (Prop_lut6_I0_O) 0.028 1.071 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_CPLLLOCK/adapt_count_reset_i_1/O net (fo=1, routed) 0.000 1.071 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_CPLLLOCK_n_2 SLICE_X187Y249 FDSE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/adapt_count_reset_reg/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.499 0.499 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.553 1.052 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -2.340 -1.288 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 1.242 -0.046 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -0.016 r ngFEC/fclk_bufg/O net (fo=39427, routed) 0.834 0.818 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/SYSCLK_IN SLICE_X187Y249 FDSE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/adapt_count_reset_reg/C clock pessimism 0.141 0.959 SLICE_X187Y249 FDSE (Hold_fdse_C_D) 0.060 1.019 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/adapt_count_reset_reg ------------------------------------------------------------------- required time -1.019 arrival time 1.071 ------------------------------------------------------------------- slack 0.052 Slack (MET) : 0.054ns (arrival time - required time) Source: ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/DataIn_local_reg[14]/C (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/cr_reg[6]/D (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: fabric_clk_FBOUT Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_FBOUT rise@0.000ns - fabric_clk_FBOUT rise@0.000ns) Data Path Delay: 0.315ns (logic 0.146ns (46.333%) route 0.169ns (53.667%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.200ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.804ns Source Clock Delay (SCD): 0.725ns Clock Pessimism Removal (CPR): -0.121ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.426 0.426 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.503 0.929 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -1.995 -1.066 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 1.173 0.107 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.133 r ngFEC/fclk_bufg/O net (fo=39427, routed) 0.592 0.725 ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/clk_local SLICE_X90Y276 FDRE r ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/DataIn_local_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X90Y276 FDRE (Prop_fdre_C_Q) 0.118 0.843 r ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/DataIn_local_reg[14]/Q net (fo=1, routed) 0.169 1.012 ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_TX_Reset/cr_reg[7]_14[2] SLICE_X92Y276 LUT5 (Prop_lut5_I4_O) 0.028 1.040 r ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_TX_Reset/cr[6]_i_1__69/O net (fo=1, routed) 0.000 1.040 ngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/cr_reg[6]_0 SLICE_X92Y276 FDRE r ngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/cr_reg[6]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.499 0.499 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.553 1.052 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -2.340 -1.288 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 1.242 -0.046 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -0.016 r ngFEC/fclk_bufg/O net (fo=39427, routed) 0.820 0.804 ngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/CLKFBIN SLICE_X92Y276 FDRE r ngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/cr_reg[6]/C clock pessimism 0.121 0.925 SLICE_X92Y276 FDRE (Hold_fdre_C_D) 0.061 0.986 ngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/cr_reg[6] ------------------------------------------------------------------- required time -0.986 arrival time 1.040 ------------------------------------------------------------------- slack 0.054 Slack (MET) : 0.055ns (arrival time - required time) Source: ngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/cnt_reg[10]/C (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/cnt_reg[12]/D (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: fabric_clk_FBOUT Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_FBOUT rise@0.000ns - fabric_clk_FBOUT rise@0.000ns) Data Path Delay: 0.445ns (logic 0.247ns (55.536%) route 0.198ns (44.464%)) Logic Levels: 3 (CARRY4=2 LUT3=1) Clock Path Skew: 0.298ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.832ns Source Clock Delay (SCD): 0.675ns Clock Pessimism Removal (CPR): -0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.426 0.426 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.503 0.929 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -1.995 -1.066 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 1.173 0.107 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.133 r ngFEC/fclk_bufg/O net (fo=39427, routed) 0.542 0.675 ngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/CLKFBIN SLICE_X104Y249 FDRE r ngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/cnt_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X104Y249 FDRE (Prop_fdre_C_Q) 0.118 0.793 r ngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/cnt_reg[10]/Q net (fo=3, routed) 0.197 0.990 ngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/cnt_reg[10] SLICE_X104Y249 LUT3 (Prop_lut3_I2_O) 0.026 1.016 r ngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/cnt[8]_i_3__122/O net (fo=1, routed) 0.000 1.016 ngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/cnt[8]_i_3__122_n_0 SLICE_X104Y249 CARRY4 (Prop_carry4_DI[2]_CO[3]) 0.062 1.078 r ngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/cnt_reg[8]_i_1__124/CO[3] net (fo=1, routed) 0.001 1.079 ngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/cnt_reg[8]_i_1__124_n_0 SLICE_X104Y250 CARRY4 (Prop_carry4_CI_O[0]) 0.041 1.120 r ngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/cnt_reg[12]_i_1__111/O[0] net (fo=1, routed) 0.000 1.120 ngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/cnt_reg[12]_i_1__111_n_7 SLICE_X104Y250 FDRE r ngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/cnt_reg[12]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.499 0.499 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.553 1.052 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -2.340 -1.288 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 1.242 -0.046 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -0.016 r ngFEC/fclk_bufg/O net (fo=39427, routed) 0.848 0.832 ngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/CLKFBIN SLICE_X104Y250 FDRE r ngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/cnt_reg[12]/C clock pessimism 0.141 0.973 SLICE_X104Y250 FDRE (Hold_fdre_C_D) 0.092 1.065 ngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/cnt_reg[12] ------------------------------------------------------------------- required time -1.065 arrival time 1.120 ------------------------------------------------------------------- slack 0.055 Slack (MET) : 0.055ns (arrival time - required time) Source: ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/DataIn_local_reg[11]/C (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/SFP_GEN[7].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/cr_reg[3]/D (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: fabric_clk_FBOUT Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_FBOUT rise@0.000ns - fabric_clk_FBOUT rise@0.000ns) Data Path Delay: 0.340ns (logic 0.128ns (37.594%) route 0.212ns (62.406%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.198ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.870ns Source Clock Delay (SCD): 0.773ns Clock Pessimism Removal (CPR): -0.101ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.426 0.426 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.503 0.929 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -1.995 -1.066 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 1.173 0.107 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.133 r ngFEC/fclk_bufg/O net (fo=39427, routed) 0.640 0.773 ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/clk_local SLICE_X91Y61 FDRE r ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/DataIn_local_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y61 FDRE (Prop_fdre_C_Q) 0.100 0.873 r ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/DataIn_local_reg[11]/Q net (fo=1, routed) 0.212 1.086 ngFEC/SFP_GEN[7].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/DataIn_local[11] SLICE_X94Y61 LUT6 (Prop_lut6_I0_O) 0.028 1.114 r ngFEC/SFP_GEN[7].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/cr[3]_i_1__56/O net (fo=1, routed) 0.000 1.114 ngFEC/SFP_GEN[7].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/cr[3]_i_1__56_n_0 SLICE_X94Y61 FDRE r ngFEC/SFP_GEN[7].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/cr_reg[3]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.499 0.499 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.553 1.052 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -2.340 -1.288 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 1.242 -0.046 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -0.016 r ngFEC/fclk_bufg/O net (fo=39427, routed) 0.886 0.870 ngFEC/SFP_GEN[7].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/CLKFBIN SLICE_X94Y61 FDRE r ngFEC/SFP_GEN[7].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/cr_reg[3]/C clock pessimism 0.101 0.971 SLICE_X94Y61 FDRE (Hold_fdre_C_D) 0.087 1.058 ngFEC/SFP_GEN[7].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/cr_reg[3] ------------------------------------------------------------------- required time -1.058 arrival time 1.114 ------------------------------------------------------------------- slack 0.055 Slack (MET) : 0.057ns (arrival time - required time) Source: ngFEC/SFP_GEN[1].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.gf_scl/buffer_reg[3]/C (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/SFP_GEN[1].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.gf_scl/buffer_reg[4]/D (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: fabric_clk_FBOUT Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_FBOUT rise@0.000ns - fabric_clk_FBOUT rise@0.000ns) Data Path Delay: 0.272ns (logic 0.107ns (39.278%) route 0.165ns (60.722%)) Logic Levels: 0 Clock Path Skew: 0.217ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.821ns Source Clock Delay (SCD): 0.753ns Clock Pessimism Removal (CPR): -0.149ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.426 0.426 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.503 0.929 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -1.995 -1.066 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 1.173 0.107 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.133 r ngFEC/fclk_bufg/O net (fo=39427, routed) 0.620 0.753 ngFEC/SFP_GEN[1].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.gf_scl/CLKFBIN SLICE_X166Y200 FDRE r ngFEC/SFP_GEN[1].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.gf_scl/buffer_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X166Y200 FDRE (Prop_fdre_C_Q) 0.107 0.860 r ngFEC/SFP_GEN[1].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.gf_scl/buffer_reg[3]/Q net (fo=3, routed) 0.165 1.026 ngFEC/SFP_GEN[1].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.gf_scl/buffer_reg_n_0_[3] SLICE_X166Y199 FDRE r ngFEC/SFP_GEN[1].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.gf_scl/buffer_reg[4]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.499 0.499 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.553 1.052 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -2.340 -1.288 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 1.242 -0.046 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -0.016 r ngFEC/fclk_bufg/O net (fo=39427, routed) 0.837 0.821 ngFEC/SFP_GEN[1].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.gf_scl/CLKFBIN SLICE_X166Y199 FDRE r ngFEC/SFP_GEN[1].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.gf_scl/buffer_reg[4]/C clock pessimism 0.149 0.970 SLICE_X166Y199 FDRE (Hold_fdre_C_D) -0.002 0.968 ngFEC/SFP_GEN[1].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.gf_scl/buffer_reg[4] ------------------------------------------------------------------- required time -0.968 arrival time 1.026 ------------------------------------------------------------------- slack 0.057 Slack (MET) : 0.057ns (arrival time - required time) Source: ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/DataIn_local_reg[12]/C (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/cr_reg[4]/D (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: fabric_clk_FBOUT Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_FBOUT rise@0.000ns - fabric_clk_FBOUT rise@0.000ns) Data Path Delay: 0.327ns (logic 0.147ns (44.893%) route 0.180ns (55.107%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.200ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.804ns Source Clock Delay (SCD): 0.725ns Clock Pessimism Removal (CPR): -0.121ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.426 0.426 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.503 0.929 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -1.995 -1.066 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 1.173 0.107 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.133 r ngFEC/fclk_bufg/O net (fo=39427, routed) 0.592 0.725 ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/clk_local SLICE_X90Y276 FDRE r ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/DataIn_local_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X90Y276 FDRE (Prop_fdre_C_Q) 0.118 0.843 r ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/DataIn_local_reg[12]/Q net (fo=1, routed) 0.180 1.024 ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_TX_Reset/cr_reg[7]_14[0] SLICE_X92Y276 LUT5 (Prop_lut5_I4_O) 0.029 1.053 r ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_TX_Reset/cr[4]_i_1__69/O net (fo=1, routed) 0.000 1.053 ngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/cr_reg[4]_0 SLICE_X92Y276 FDRE r ngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/cr_reg[4]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.499 0.499 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.553 1.052 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -2.340 -1.288 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 1.242 -0.046 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -0.016 r ngFEC/fclk_bufg/O net (fo=39427, routed) 0.820 0.804 ngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/CLKFBIN SLICE_X92Y276 FDRE r ngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/cr_reg[4]/C clock pessimism 0.121 0.925 SLICE_X92Y276 FDRE (Hold_fdre_C_D) 0.070 0.995 ngFEC/SFP_GEN[3].ngCCM_gbt/i2c_gen[5].LocalI2CBridge_fe/i2c_master/cr_reg[4] ------------------------------------------------------------------- required time -0.995 arrival time 1.053 ------------------------------------------------------------------- slack 0.057 Slack (MET) : 0.058ns (arrival time - required time) Source: ngFEC/SFP_GEN[11].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/txr_reg[7]/C (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/SFP_GEN[11].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr_reg[7]/D (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: fabric_clk_FBOUT Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_FBOUT rise@0.000ns - fabric_clk_FBOUT rise@0.000ns) Data Path Delay: 0.330ns (logic 0.130ns (39.430%) route 0.200ns (60.570%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.197ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.788ns Source Clock Delay (SCD): 0.712ns Clock Pessimism Removal (CPR): -0.121ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.426 0.426 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.503 0.929 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -1.995 -1.066 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 1.173 0.107 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.133 r ngFEC/fclk_bufg/O net (fo=39427, routed) 0.579 0.712 ngFEC/SFP_GEN[11].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/CLKFBIN SLICE_X91Y127 FDRE r ngFEC/SFP_GEN[11].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/txr_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y127 FDRE (Prop_fdre_C_Q) 0.100 0.812 r ngFEC/SFP_GEN[11].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/txr_reg[7]/Q net (fo=1, routed) 0.200 1.012 ngFEC/SFP_GEN[11].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/txr[7] SLICE_X93Y128 LUT3 (Prop_lut3_I0_O) 0.030 1.042 r ngFEC/SFP_GEN[11].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr[7]_i_2__19/O net (fo=1, routed) 0.000 1.042 ngFEC/SFP_GEN[11].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr[7]_i_2__19_n_0 SLICE_X93Y128 FDRE r ngFEC/SFP_GEN[11].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr_reg[7]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.499 0.499 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.553 1.052 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -2.340 -1.288 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 1.242 -0.046 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -0.016 r ngFEC/fclk_bufg/O net (fo=39427, routed) 0.804 0.788 ngFEC/SFP_GEN[11].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/CLKFBIN SLICE_X93Y128 FDRE r ngFEC/SFP_GEN[11].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr_reg[7]/C clock pessimism 0.121 0.909 SLICE_X93Y128 FDRE (Hold_fdre_C_D) 0.075 0.984 ngFEC/SFP_GEN[11].ngCCM_gbt/i2c_gen[7].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr_reg[7] ------------------------------------------------------------------- required time -0.984 arrival time 1.042 ------------------------------------------------------------------- slack 0.058 Slack (MET) : 0.058ns (arrival time - required time) Source: ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/DataIn_local_reg[3]/C (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/SFP_GEN[4].ngCCM_gbt/i2c_gen[2].LocalI2CBridge_fe/i2c_master/txr_reg[3]/D (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: fabric_clk_FBOUT Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_FBOUT rise@0.000ns - fabric_clk_FBOUT rise@0.000ns) Data Path Delay: 0.395ns (logic 0.118ns (29.870%) route 0.277ns (70.130%)) Logic Levels: 0 Clock Path Skew: 0.300ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.907ns Source Clock Delay (SCD): 0.748ns Clock Pessimism Removal (CPR): -0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.426 0.426 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.503 0.929 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -1.995 -1.066 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 1.173 0.107 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.133 r ngFEC/fclk_bufg/O net (fo=39427, routed) 0.615 0.748 ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/clk_local SLICE_X10Y249 FDRE r ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/DataIn_local_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X10Y249 FDRE (Prop_fdre_C_Q) 0.118 0.866 r ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/DataIn_local_reg[3]/Q net (fo=1, routed) 0.277 1.143 ngFEC/SFP_GEN[4].ngCCM_gbt/i2c_gen[2].LocalI2CBridge_fe/i2c_master/DataIn_local[3] SLICE_X10Y250 FDRE r ngFEC/SFP_GEN[4].ngCCM_gbt/i2c_gen[2].LocalI2CBridge_fe/i2c_master/txr_reg[3]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.499 0.499 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.553 1.052 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -2.340 -1.288 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 1.242 -0.046 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -0.016 r ngFEC/fclk_bufg/O net (fo=39427, routed) 0.923 0.907 ngFEC/SFP_GEN[4].ngCCM_gbt/i2c_gen[2].LocalI2CBridge_fe/i2c_master/CLKFBIN SLICE_X10Y250 FDRE r ngFEC/SFP_GEN[4].ngCCM_gbt/i2c_gen[2].LocalI2CBridge_fe/i2c_master/txr_reg[3]/C clock pessimism 0.141 1.048 SLICE_X10Y250 FDRE (Hold_fdre_C_D) 0.037 1.085 ngFEC/SFP_GEN[4].ngCCM_gbt/i2c_gen[2].LocalI2CBridge_fe/i2c_master/txr_reg[3] ------------------------------------------------------------------- required time -1.085 arrival time 1.143 ------------------------------------------------------------------- slack 0.058 Slack (MET) : 0.058ns (arrival time - required time) Source: ngFEC/SFP_GEN[6].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/txr_reg[4]/C (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/SFP_GEN[6].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr_reg[4]/D (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: fabric_clk_FBOUT Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_FBOUT rise@0.000ns - fabric_clk_FBOUT rise@0.000ns) Data Path Delay: 0.420ns (logic 0.130ns (30.948%) route 0.290ns (69.052%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.266ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.947ns Source Clock Delay (SCD): 0.782ns Clock Pessimism Removal (CPR): -0.101ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.426 0.426 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.503 0.929 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -1.995 -1.066 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 1.173 0.107 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.133 r ngFEC/fclk_bufg/O net (fo=39427, routed) 0.649 0.782 ngFEC/SFP_GEN[6].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/CLKFBIN SLICE_X81Y50 FDRE r ngFEC/SFP_GEN[6].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/txr_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X81Y50 FDRE (Prop_fdre_C_Q) 0.100 0.882 r ngFEC/SFP_GEN[6].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/txr_reg[4]/Q net (fo=1, routed) 0.290 1.172 ngFEC/SFP_GEN[6].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/txr[4] SLICE_X76Y48 LUT3 (Prop_lut3_I0_O) 0.030 1.202 r ngFEC/SFP_GEN[6].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr[4]_i_1__64/O net (fo=1, routed) 0.000 1.202 ngFEC/SFP_GEN[6].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr[4]_i_1__64_n_0 SLICE_X76Y48 FDRE r ngFEC/SFP_GEN[6].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr_reg[4]/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.499 0.499 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.553 1.052 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -2.340 -1.288 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 1.242 -0.046 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -0.016 r ngFEC/fclk_bufg/O net (fo=39427, routed) 0.963 0.947 ngFEC/SFP_GEN[6].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/CLKFBIN SLICE_X76Y48 FDRE r ngFEC/SFP_GEN[6].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr_reg[4]/C clock pessimism 0.101 1.048 SLICE_X76Y48 FDRE (Hold_fdre_C_D) 0.096 1.144 ngFEC/SFP_GEN[6].ngCCM_gbt/i2c_gen[0].LocalI2CBridge_fe/i2c_master/byte_ctrl/sr_reg[4] ------------------------------------------------------------------- required time -1.144 arrival time 1.202 ------------------------------------------------------------------- slack 0.058 Slack (MET) : 0.058ns (arrival time - required time) Source: ngFEC/SFP_GEN[10].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_to_reg/C (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/SFP_GEN[10].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_reg/D (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: fabric_clk_FBOUT Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_FBOUT rise@0.000ns - fabric_clk_FBOUT rise@0.000ns) Data Path Delay: 0.412ns (logic 0.128ns (31.046%) route 0.284ns (68.954%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.267ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.919ns Source Clock Delay (SCD): 0.793ns Clock Pessimism Removal (CPR): -0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.426 0.426 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.503 0.929 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -1.995 -1.066 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 1.173 0.107 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.133 r ngFEC/fclk_bufg/O net (fo=39427, routed) 0.660 0.793 ngFEC/SFP_GEN[10].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/CLKFBIN SLICE_X0Y151 FDRE r ngFEC/SFP_GEN[10].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_to_reg/C ------------------------------------------------------------------- ------------------- SLICE_X0Y151 FDRE (Prop_fdre_C_Q) 0.100 0.893 f ngFEC/SFP_GEN[10].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_to_reg/Q net (fo=2, routed) 0.284 1.178 ngFEC/SFP_GEN[10].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.gf_scl/slave_wait_reg_0 SLICE_X2Y148 LUT5 (Prop_lut5_I4_O) 0.028 1.206 r ngFEC/SFP_GEN[10].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/bus_status_ctrl.gf_scl/slave_wait_i_1__2/O net (fo=1, routed) 0.000 1.206 ngFEC/SFP_GEN[10].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait0 SLICE_X2Y148 FDRE r ngFEC/SFP_GEN[10].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_reg/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.499 0.499 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.553 1.052 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -2.340 -1.288 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 1.242 -0.046 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -0.016 r ngFEC/fclk_bufg/O net (fo=39427, routed) 0.935 0.919 ngFEC/SFP_GEN[10].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/CLKFBIN SLICE_X2Y148 FDRE r ngFEC/SFP_GEN[10].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_reg/C clock pessimism 0.141 1.060 SLICE_X2Y148 FDRE (Hold_fdre_C_D) 0.087 1.147 ngFEC/SFP_GEN[10].ngCCM_gbt/i2c_gen[3].LocalI2CBridge_fe/i2c_master/byte_ctrl/bit_ctrl/slave_wait_reg ------------------------------------------------------------------- required time -1.147 arrival time 1.206 ------------------------------------------------------------------- slack 0.058 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: fabric_clk_FBOUT Waveform(ns): { 0.000 12.476 } Period(ns): 24.951 Sources: { ngFEC/fabric_clk_MMCME2/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/DRPCLK n/a 5.714 24.951 19.237 GTXE2_CHANNEL_X0Y4 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/DRPCLK Min Period n/a GTXE2_CHANNEL/DRPCLK n/a 5.714 24.951 19.237 GTXE2_CHANNEL_X0Y5 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/DRPCLK Min Period n/a GTXE2_CHANNEL/DRPCLK n/a 5.714 24.951 19.237 GTXE2_CHANNEL_X0Y6 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/DRPCLK Min Period n/a GTXE2_CHANNEL/DRPCLK n/a 5.714 24.951 19.237 GTXE2_CHANNEL_X0Y7 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/DRPCLK Min Period n/a GTXE2_CHANNEL/DRPCLK n/a 5.714 24.951 19.237 GTXE2_CHANNEL_X0Y28 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/DRPCLK Min Period n/a GTXE2_CHANNEL/DRPCLK n/a 5.714 24.951 19.237 GTXE2_CHANNEL_X0Y31 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/DRPCLK Min Period n/a GTXE2_CHANNEL/DRPCLK n/a 5.714 24.951 19.237 GTXE2_CHANNEL_X0Y30 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/DRPCLK Min Period n/a GTXE2_CHANNEL/DRPCLK n/a 5.714 24.951 19.237 GTXE2_CHANNEL_X0Y25 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/DRPCLK Min Period n/a GTXE2_CHANNEL/DRPCLK n/a 5.714 24.951 19.237 GTXE2_CHANNEL_X0Y24 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/DRPCLK Min Period n/a GTXE2_CHANNEL/DRPCLK n/a 5.714 24.951 19.237 GTXE2_CHANNEL_X0Y21 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/DRPCLK Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 24.951 75.049 MMCME2_ADV_X0Y6 ngFEC/dmdt_clk/mmcm1/U0/mmcm_adv_inst/CLKIN1 Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 24.951 75.049 MMCME2_ADV_X0Y0 ngFEC/fabric_clk_MMCME2/CLKFBIN Max Period n/a MMCME2_ADV/CLKFBOUT n/a 213.360 24.951 188.409 MMCME2_ADV_X0Y0 ngFEC/fabric_clk_MMCME2/CLKFBOUT Low Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 5.000 12.475 7.475 MMCME2_ADV_X0Y6 ngFEC/dmdt_clk/mmcm1/U0/mmcm_adv_inst/CLKIN1 Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 5.000 12.476 7.476 MMCME2_ADV_X0Y6 ngFEC/dmdt_clk/mmcm1/U0/mmcm_adv_inst/CLKIN1 Low Pulse Width Fast MMCME2_ADV/PSCLK n/a 1.000 12.475 11.476 MMCME2_ADV_X0Y0 ngFEC/fabric_clk_MMCME2/PSCLK Low Pulse Width Slow MMCME2_ADV/PSCLK n/a 1.000 12.476 11.476 MMCME2_ADV_X0Y0 ngFEC/fabric_clk_MMCME2/PSCLK Low Pulse Width Fast SRLC32E/CLK n/a 0.642 12.475 11.833 SLICE_X134Y295 ngFEC/i_PSDONE_dl32/CLK Low Pulse Width Slow SRL16E/CLK n/a 0.642 12.476 11.833 SLICE_X86Y45 ngFEC/DTC/Inst_TTC_decoder/i_brcst_str1/CLK Low Pulse Width Slow SRL16E/CLK n/a 0.642 12.476 11.833 SLICE_X86Y45 ngFEC/DTC/Inst_TTC_decoder/i_brcst_str3/CLK Low Pulse Width Fast SRL16E/CLK n/a 0.642 12.476 11.834 SLICE_X86Y45 ngFEC/DTC/Inst_TTC_decoder/i_brcst_str1/CLK Low Pulse Width Fast SRL16E/CLK n/a 0.642 12.476 11.834 SLICE_X86Y45 ngFEC/DTC/Inst_TTC_decoder/i_brcst_str3/CLK Low Pulse Width Slow SRLC32E/CLK n/a 0.642 12.476 11.834 SLICE_X134Y295 ngFEC/i_PSDONE_dl32/CLK High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 5.000 12.476 7.475 MMCME2_ADV_X0Y6 ngFEC/dmdt_clk/mmcm1/U0/mmcm_adv_inst/CLKIN1 High Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 5.000 12.476 7.476 MMCME2_ADV_X0Y6 ngFEC/dmdt_clk/mmcm1/U0/mmcm_adv_inst/CLKIN1 High Pulse Width Slow MMCME2_ADV/PSCLK n/a 1.000 12.476 11.476 MMCME2_ADV_X0Y0 ngFEC/fabric_clk_MMCME2/PSCLK High Pulse Width Fast MMCME2_ADV/PSCLK n/a 1.000 12.476 11.476 MMCME2_ADV_X0Y0 ngFEC/fabric_clk_MMCME2/PSCLK High Pulse Width Slow SRLC32E/CLK n/a 0.642 12.475 11.833 SLICE_X134Y295 ngFEC/i_PSDONE_dl32/CLK High Pulse Width Slow SRL16E/CLK n/a 0.642 12.476 11.833 SLICE_X86Y45 ngFEC/DTC/Inst_TTC_decoder/i_brcst_str1/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 12.476 11.833 SLICE_X86Y45 ngFEC/DTC/Inst_TTC_decoder/i_brcst_str1/CLK High Pulse Width Slow SRL16E/CLK n/a 0.642 12.476 11.833 SLICE_X86Y45 ngFEC/DTC/Inst_TTC_decoder/i_brcst_str3/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 12.476 11.833 SLICE_X86Y45 ngFEC/DTC/Inst_TTC_decoder/i_brcst_str3/CLK High Pulse Width Fast SRLC32E/CLK n/a 0.642 12.476 11.833 SLICE_X134Y295 ngFEC/i_PSDONE_dl32/CLK --------------------------------------------------------------------------------------------------- From Clock: clk_o_40_08_phase_mon_mmcm_1 To Clock: clk_o_40_08_phase_mon_mmcm_1 Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 7.451ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_o_40_08_phase_mon_mmcm_1 Waveform(ns): { 0.000 12.451 } Period(ns): 24.901 Sources: { ngFEC/dmdt_clk/mmcm1/U0/mmcm_adv_inst/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 1.409 24.901 23.493 BUFGCTRL_X0Y25 ngFEC/dmdt_clk/mmcm1/U0/clkout1_buf/I Min Period n/a MMCME2_ADV/CLKOUT0 n/a 1.071 24.901 23.830 MMCME2_ADV_X0Y6 ngFEC/dmdt_clk/mmcm1/U0/mmcm_adv_inst/CLKOUT0 Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.071 24.901 23.830 MMCME2_ADV_X0Y7 ngFEC/dmdt_clk/mmcm2/U0/mmcm_adv_inst/CLKIN1 Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 24.901 75.099 MMCME2_ADV_X0Y7 ngFEC/dmdt_clk/mmcm2/U0/mmcm_adv_inst/CLKIN1 Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 24.901 188.459 MMCME2_ADV_X0Y6 ngFEC/dmdt_clk/mmcm1/U0/mmcm_adv_inst/CLKOUT0 Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 5.000 12.451 7.451 MMCME2_ADV_X0Y7 ngFEC/dmdt_clk/mmcm2/U0/mmcm_adv_inst/CLKIN1 Low Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 5.000 12.451 7.451 MMCME2_ADV_X0Y7 ngFEC/dmdt_clk/mmcm2/U0/mmcm_adv_inst/CLKIN1 High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 5.000 12.451 7.451 MMCME2_ADV_X0Y7 ngFEC/dmdt_clk/mmcm2/U0/mmcm_adv_inst/CLKIN1 High Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 5.000 12.451 7.451 MMCME2_ADV_X0Y7 ngFEC/dmdt_clk/mmcm2/U0/mmcm_adv_inst/CLKIN1 --------------------------------------------------------------------------------------------------- From Clock: clk_o_39_997_phase_mon_mmcm_2 To Clock: clk_o_39_997_phase_mon_mmcm_2 Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 23.544ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_o_39_997_phase_mon_mmcm_2 Waveform(ns): { 0.000 12.476 } Period(ns): 24.953 Sources: { ngFEC/dmdt_clk/mmcm2/U0/mmcm_adv_inst/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 1.409 24.953 23.544 BUFGCTRL_X0Y24 ngFEC/dmdt_clk/mmcm2/U0/clkout1_buf/I Min Period n/a MMCME2_ADV/CLKOUT0 n/a 1.071 24.953 23.882 MMCME2_ADV_X0Y7 ngFEC/dmdt_clk/mmcm2/U0/mmcm_adv_inst/CLKOUT0 Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 24.953 188.407 MMCME2_ADV_X0Y7 ngFEC/dmdt_clk/mmcm2/U0/mmcm_adv_inst/CLKOUT0 --------------------------------------------------------------------------------------------------- From Clock: clkfbout_phase_mon_mmcm_2 To Clock: clkfbout_phase_mon_mmcm_2 Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 25.296ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clkfbout_phase_mon_mmcm_2 Waveform(ns): { 0.000 37.352 } Period(ns): 74.704 Sources: { ngFEC/dmdt_clk/mmcm2/U0/mmcm_adv_inst/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 1.409 74.704 73.295 BUFGCTRL_X0Y26 ngFEC/dmdt_clk/mmcm2/U0/clkf_buf/I Min Period n/a MMCME2_ADV/CLKFBOUT n/a 1.071 74.704 73.633 MMCME2_ADV_X0Y7 ngFEC/dmdt_clk/mmcm2/U0/mmcm_adv_inst/CLKFBOUT Min Period n/a MMCME2_ADV/CLKFBIN n/a 1.071 74.704 73.633 MMCME2_ADV_X0Y7 ngFEC/dmdt_clk/mmcm2/U0/mmcm_adv_inst/CLKFBIN Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 74.704 25.296 MMCME2_ADV_X0Y7 ngFEC/dmdt_clk/mmcm2/U0/mmcm_adv_inst/CLKFBIN Max Period n/a MMCME2_ADV/CLKFBOUT n/a 213.360 74.704 138.656 MMCME2_ADV_X0Y7 ngFEC/dmdt_clk/mmcm2/U0/mmcm_adv_inst/CLKFBOUT --------------------------------------------------------------------------------------------------- From Clock: clkfbout_phase_mon_mmcm_1 To Clock: clkfbout_phase_mon_mmcm_1 Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 48.831ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clkfbout_phase_mon_mmcm_1 Waveform(ns): { 0.000 24.951 } Period(ns): 49.902 Sources: { ngFEC/dmdt_clk/mmcm1/U0/mmcm_adv_inst/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a MMCME2_ADV/CLKFBOUT n/a 1.071 49.902 48.831 MMCME2_ADV_X0Y6 ngFEC/dmdt_clk/mmcm1/U0/mmcm_adv_inst/CLKFBOUT Min Period n/a MMCME2_ADV/CLKFBIN n/a 1.071 49.902 48.831 MMCME2_ADV_X0Y6 ngFEC/dmdt_clk/mmcm1/U0/mmcm_adv_inst/CLKFBIN Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 49.902 50.098 MMCME2_ADV_X0Y6 ngFEC/dmdt_clk/mmcm1/U0/mmcm_adv_inst/CLKFBIN Max Period n/a MMCME2_ADV/CLKFBOUT n/a 213.360 49.902 163.458 MMCME2_ADV_X0Y6 ngFEC/dmdt_clk/mmcm1/U0/mmcm_adv_inst/CLKFBOUT --------------------------------------------------------------------------------------------------- From Clock: fabric_clk_PSOUT To Clock: fabric_clk_PSOUT Setup : 0 Failing Endpoints, Worst Slack 23.651ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.145ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 12.076ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 23.651ns (required time - arrival time) Source: ngFEC/fabric_clk_PS_toggle_reg/C (rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D (rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: fabric_clk_PSOUT Path Type: Setup (Max at Slow Process Corner) Requirement: 24.951ns (fabric_clk_PSOUT rise@24.951ns - fabric_clk_PSOUT rise@0.000ns) Data Path Delay: 1.093ns (logic 0.259ns (23.699%) route 0.834ns (76.301%)) Logic Levels: 0 Clock Path Skew: -0.057ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.432ns = ( 26.383 - 24.951 ) Source Clock Delay (SCD): 1.681ns Clock Pessimism Removal (CPR): 0.192ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_PSOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.802 0.802 r ngFEC/fclk_ibuf/O net (fo=1, routed) 1.081 1.883 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -4.638 -2.755 r ngFEC/fabric_clk_MMCME2/CLKOUT0 net (fo=1, routed) 2.546 -0.209 ngFEC/fabric_clk_PSOUT BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.093 -0.116 r ngFEC/fabric_clk_PS_bufg/O net (fo=13, routed) 1.797 1.681 ngFEC/fabric_clk_PS SLICE_X150Y350 FDRE r ngFEC/fabric_clk_PS_toggle_reg/C ------------------------------------------------------------------- ------------------- SLICE_X150Y350 FDRE (Prop_fdre_C_Q) 0.259 1.940 r ngFEC/fabric_clk_PS_toggle_reg/Q net (fo=13, routed) 0.834 2.774 ngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_in SLICE_X143Y350 FDRE r ngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_PSOUT rise edge) 24.951 24.951 r AK18 0.000 24.951 r fabric_clk_p (IN) net (fo=0) 0.000 24.951 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.725 25.676 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.986 26.662 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -4.330 22.332 r ngFEC/fabric_clk_MMCME2/CLKOUT0 net (fo=1, routed) 2.411 24.743 ngFEC/fabric_clk_PSOUT BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.083 24.826 r ngFEC/fabric_clk_PS_bufg/O net (fo=13, routed) 1.557 26.383 ngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_clk SLICE_X143Y350 FDRE r ngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C clock pessimism 0.192 26.575 clock uncertainty -0.128 26.448 SLICE_X143Y350 FDRE (Setup_fdre_C_D) -0.022 26.426 ngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg ------------------------------------------------------------------- required time 26.426 arrival time -2.774 ------------------------------------------------------------------- slack 23.651 Slack (MET) : 23.765ns (required time - arrival time) Source: ngFEC/fabric_clk_PS_toggle_reg/C (rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/g_pm[9].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D (rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: fabric_clk_PSOUT Path Type: Setup (Max at Slow Process Corner) Requirement: 24.951ns (fabric_clk_PSOUT rise@24.951ns - fabric_clk_PSOUT rise@0.000ns) Data Path Delay: 0.982ns (logic 0.259ns (26.383%) route 0.723ns (73.617%)) Logic Levels: 0 Clock Path Skew: -0.057ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.432ns = ( 26.383 - 24.951 ) Source Clock Delay (SCD): 1.681ns Clock Pessimism Removal (CPR): 0.192ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_PSOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.802 0.802 r ngFEC/fclk_ibuf/O net (fo=1, routed) 1.081 1.883 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -4.638 -2.755 r ngFEC/fabric_clk_MMCME2/CLKOUT0 net (fo=1, routed) 2.546 -0.209 ngFEC/fabric_clk_PSOUT BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.093 -0.116 r ngFEC/fabric_clk_PS_bufg/O net (fo=13, routed) 1.797 1.681 ngFEC/fabric_clk_PS SLICE_X150Y350 FDRE r ngFEC/fabric_clk_PS_toggle_reg/C ------------------------------------------------------------------- ------------------- SLICE_X150Y350 FDRE (Prop_fdre_C_Q) 0.259 1.940 r ngFEC/fabric_clk_PS_toggle_reg/Q net (fo=13, routed) 0.723 2.663 ngFEC/g_pm[9].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_in SLICE_X143Y350 FDRE r ngFEC/g_pm[9].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_PSOUT rise edge) 24.951 24.951 r AK18 0.000 24.951 r fabric_clk_p (IN) net (fo=0) 0.000 24.951 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.725 25.676 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.986 26.662 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -4.330 22.332 r ngFEC/fabric_clk_MMCME2/CLKOUT0 net (fo=1, routed) 2.411 24.743 ngFEC/fabric_clk_PSOUT BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.083 24.826 r ngFEC/fabric_clk_PS_bufg/O net (fo=13, routed) 1.557 26.383 ngFEC/g_pm[9].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_clk SLICE_X143Y350 FDRE r ngFEC/g_pm[9].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C clock pessimism 0.192 26.575 clock uncertainty -0.128 26.448 SLICE_X143Y350 FDRE (Setup_fdre_C_D) -0.019 26.429 ngFEC/g_pm[9].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg ------------------------------------------------------------------- required time 26.429 arrival time -2.663 ------------------------------------------------------------------- slack 23.765 Slack (MET) : 23.876ns (required time - arrival time) Source: ngFEC/fabric_clk_PS_toggle_reg/C (rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/g_pm[8].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D (rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: fabric_clk_PSOUT Path Type: Setup (Max at Slow Process Corner) Requirement: 24.951ns (fabric_clk_PSOUT rise@24.951ns - fabric_clk_PSOUT rise@0.000ns) Data Path Delay: 0.871ns (logic 0.259ns (29.725%) route 0.612ns (70.275%)) Logic Levels: 0 Clock Path Skew: -0.057ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.432ns = ( 26.383 - 24.951 ) Source Clock Delay (SCD): 1.681ns Clock Pessimism Removal (CPR): 0.192ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_PSOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.802 0.802 r ngFEC/fclk_ibuf/O net (fo=1, routed) 1.081 1.883 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -4.638 -2.755 r ngFEC/fabric_clk_MMCME2/CLKOUT0 net (fo=1, routed) 2.546 -0.209 ngFEC/fabric_clk_PSOUT BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.093 -0.116 r ngFEC/fabric_clk_PS_bufg/O net (fo=13, routed) 1.797 1.681 ngFEC/fabric_clk_PS SLICE_X150Y350 FDRE r ngFEC/fabric_clk_PS_toggle_reg/C ------------------------------------------------------------------- ------------------- SLICE_X150Y350 FDRE (Prop_fdre_C_Q) 0.259 1.940 r ngFEC/fabric_clk_PS_toggle_reg/Q net (fo=13, routed) 0.612 2.553 ngFEC/g_pm[8].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_in SLICE_X143Y350 FDRE r ngFEC/g_pm[8].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_PSOUT rise edge) 24.951 24.951 r AK18 0.000 24.951 r fabric_clk_p (IN) net (fo=0) 0.000 24.951 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.725 25.676 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.986 26.662 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -4.330 22.332 r ngFEC/fabric_clk_MMCME2/CLKOUT0 net (fo=1, routed) 2.411 24.743 ngFEC/fabric_clk_PSOUT BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.083 24.826 r ngFEC/fabric_clk_PS_bufg/O net (fo=13, routed) 1.557 26.383 ngFEC/g_pm[8].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_clk SLICE_X143Y350 FDRE r ngFEC/g_pm[8].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C clock pessimism 0.192 26.575 clock uncertainty -0.128 26.448 SLICE_X143Y350 FDRE (Setup_fdre_C_D) -0.019 26.429 ngFEC/g_pm[8].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg ------------------------------------------------------------------- required time 26.429 arrival time -2.553 ------------------------------------------------------------------- slack 23.876 Slack (MET) : 23.936ns (required time - arrival time) Source: ngFEC/fabric_clk_PS_toggle_reg/C (rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D (rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: fabric_clk_PSOUT Path Type: Setup (Max at Slow Process Corner) Requirement: 24.951ns (fabric_clk_PSOUT rise@24.951ns - fabric_clk_PSOUT rise@0.000ns) Data Path Delay: 0.849ns (logic 0.259ns (30.519%) route 0.590ns (69.481%)) Logic Levels: 0 Clock Path Skew: -0.025ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.439ns = ( 26.390 - 24.951 ) Source Clock Delay (SCD): 1.681ns Clock Pessimism Removal (CPR): 0.217ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_PSOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.802 0.802 r ngFEC/fclk_ibuf/O net (fo=1, routed) 1.081 1.883 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -4.638 -2.755 r ngFEC/fabric_clk_MMCME2/CLKOUT0 net (fo=1, routed) 2.546 -0.209 ngFEC/fabric_clk_PSOUT BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.093 -0.116 r ngFEC/fabric_clk_PS_bufg/O net (fo=13, routed) 1.797 1.681 ngFEC/fabric_clk_PS SLICE_X150Y350 FDRE r ngFEC/fabric_clk_PS_toggle_reg/C ------------------------------------------------------------------- ------------------- SLICE_X150Y350 FDRE (Prop_fdre_C_Q) 0.259 1.940 r ngFEC/fabric_clk_PS_toggle_reg/Q net (fo=13, routed) 0.590 2.530 ngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_in SLICE_X148Y351 FDRE r ngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_PSOUT rise edge) 24.951 24.951 r AK18 0.000 24.951 r fabric_clk_p (IN) net (fo=0) 0.000 24.951 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.725 25.676 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.986 26.662 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -4.330 22.332 r ngFEC/fabric_clk_MMCME2/CLKOUT0 net (fo=1, routed) 2.411 24.743 ngFEC/fabric_clk_PSOUT BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.083 24.826 r ngFEC/fabric_clk_PS_bufg/O net (fo=13, routed) 1.564 26.390 ngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_clk SLICE_X148Y351 FDRE r ngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C clock pessimism 0.217 26.607 clock uncertainty -0.128 26.480 SLICE_X148Y351 FDRE (Setup_fdre_C_D) -0.013 26.467 ngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg ------------------------------------------------------------------- required time 26.467 arrival time -2.530 ------------------------------------------------------------------- slack 23.936 Slack (MET) : 23.982ns (required time - arrival time) Source: ngFEC/fabric_clk_PS_toggle_reg/C (rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D (rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: fabric_clk_PSOUT Path Type: Setup (Max at Slow Process Corner) Requirement: 24.951ns (fabric_clk_PSOUT rise@24.951ns - fabric_clk_PSOUT rise@0.000ns) Data Path Delay: 0.753ns (logic 0.259ns (34.413%) route 0.494ns (65.587%)) Logic Levels: 0 Clock Path Skew: -0.057ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.432ns = ( 26.383 - 24.951 ) Source Clock Delay (SCD): 1.681ns Clock Pessimism Removal (CPR): 0.192ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_PSOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.802 0.802 r ngFEC/fclk_ibuf/O net (fo=1, routed) 1.081 1.883 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -4.638 -2.755 r ngFEC/fabric_clk_MMCME2/CLKOUT0 net (fo=1, routed) 2.546 -0.209 ngFEC/fabric_clk_PSOUT BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.093 -0.116 r ngFEC/fabric_clk_PS_bufg/O net (fo=13, routed) 1.797 1.681 ngFEC/fabric_clk_PS SLICE_X150Y350 FDRE r ngFEC/fabric_clk_PS_toggle_reg/C ------------------------------------------------------------------- ------------------- SLICE_X150Y350 FDRE (Prop_fdre_C_Q) 0.259 1.940 r ngFEC/fabric_clk_PS_toggle_reg/Q net (fo=13, routed) 0.494 2.434 ngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_in SLICE_X143Y350 FDRE r ngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_PSOUT rise edge) 24.951 24.951 r AK18 0.000 24.951 r fabric_clk_p (IN) net (fo=0) 0.000 24.951 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.725 25.676 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.986 26.662 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -4.330 22.332 r ngFEC/fabric_clk_MMCME2/CLKOUT0 net (fo=1, routed) 2.411 24.743 ngFEC/fabric_clk_PSOUT BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.083 24.826 r ngFEC/fabric_clk_PS_bufg/O net (fo=13, routed) 1.557 26.383 ngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_clk SLICE_X143Y350 FDRE r ngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C clock pessimism 0.192 26.575 clock uncertainty -0.128 26.448 SLICE_X143Y350 FDRE (Setup_fdre_C_D) -0.031 26.417 ngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg ------------------------------------------------------------------- required time 26.417 arrival time -2.434 ------------------------------------------------------------------- slack 23.982 Slack (MET) : 24.087ns (required time - arrival time) Source: ngFEC/fabric_clk_PS_toggle_reg/C (rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D (rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: fabric_clk_PSOUT Path Type: Setup (Max at Slow Process Corner) Requirement: 24.951ns (fabric_clk_PSOUT rise@24.951ns - fabric_clk_PSOUT rise@0.000ns) Data Path Delay: 0.762ns (logic 0.259ns (33.979%) route 0.503ns (66.021%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.439ns = ( 26.390 - 24.951 ) Source Clock Delay (SCD): 1.681ns Clock Pessimism Removal (CPR): 0.242ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_PSOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.802 0.802 r ngFEC/fclk_ibuf/O net (fo=1, routed) 1.081 1.883 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -4.638 -2.755 r ngFEC/fabric_clk_MMCME2/CLKOUT0 net (fo=1, routed) 2.546 -0.209 ngFEC/fabric_clk_PSOUT BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.093 -0.116 r ngFEC/fabric_clk_PS_bufg/O net (fo=13, routed) 1.797 1.681 ngFEC/fabric_clk_PS SLICE_X150Y350 FDRE r ngFEC/fabric_clk_PS_toggle_reg/C ------------------------------------------------------------------- ------------------- SLICE_X150Y350 FDRE (Prop_fdre_C_Q) 0.259 1.940 r ngFEC/fabric_clk_PS_toggle_reg/Q net (fo=13, routed) 0.503 2.444 ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_in SLICE_X150Y350 FDRE r ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_PSOUT rise edge) 24.951 24.951 r AK18 0.000 24.951 r fabric_clk_p (IN) net (fo=0) 0.000 24.951 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.725 25.676 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.986 26.662 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -4.330 22.332 r ngFEC/fabric_clk_MMCME2/CLKOUT0 net (fo=1, routed) 2.411 24.743 ngFEC/fabric_clk_PSOUT BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.083 24.826 r ngFEC/fabric_clk_PS_bufg/O net (fo=13, routed) 1.564 26.390 ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_clk SLICE_X150Y350 FDRE r ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C clock pessimism 0.242 26.632 clock uncertainty -0.128 26.505 SLICE_X150Y350 FDRE (Setup_fdre_C_D) 0.026 26.531 ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg ------------------------------------------------------------------- required time 26.531 arrival time -2.444 ------------------------------------------------------------------- slack 24.087 Slack (MET) : 24.154ns (required time - arrival time) Source: ngFEC/fabric_clk_PS_toggle_reg/C (rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D (rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: fabric_clk_PSOUT Path Type: Setup (Max at Slow Process Corner) Requirement: 24.951ns (fabric_clk_PSOUT rise@24.951ns - fabric_clk_PSOUT rise@0.000ns) Data Path Delay: 0.656ns (logic 0.259ns (39.486%) route 0.397ns (60.514%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.439ns = ( 26.390 - 24.951 ) Source Clock Delay (SCD): 1.681ns Clock Pessimism Removal (CPR): 0.242ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_PSOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.802 0.802 r ngFEC/fclk_ibuf/O net (fo=1, routed) 1.081 1.883 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -4.638 -2.755 r ngFEC/fabric_clk_MMCME2/CLKOUT0 net (fo=1, routed) 2.546 -0.209 ngFEC/fabric_clk_PSOUT BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.093 -0.116 r ngFEC/fabric_clk_PS_bufg/O net (fo=13, routed) 1.797 1.681 ngFEC/fabric_clk_PS SLICE_X150Y350 FDRE r ngFEC/fabric_clk_PS_toggle_reg/C ------------------------------------------------------------------- ------------------- SLICE_X150Y350 FDRE (Prop_fdre_C_Q) 0.259 1.940 r ngFEC/fabric_clk_PS_toggle_reg/Q net (fo=13, routed) 0.397 2.337 ngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_in SLICE_X150Y350 FDRE r ngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_PSOUT rise edge) 24.951 24.951 r AK18 0.000 24.951 r fabric_clk_p (IN) net (fo=0) 0.000 24.951 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.725 25.676 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.986 26.662 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -4.330 22.332 r ngFEC/fabric_clk_MMCME2/CLKOUT0 net (fo=1, routed) 2.411 24.743 ngFEC/fabric_clk_PSOUT BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.083 24.826 r ngFEC/fabric_clk_PS_bufg/O net (fo=13, routed) 1.564 26.390 ngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_clk SLICE_X150Y350 FDRE r ngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C clock pessimism 0.242 26.632 clock uncertainty -0.128 26.505 SLICE_X150Y350 FDRE (Setup_fdre_C_D) -0.013 26.492 ngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg ------------------------------------------------------------------- required time 26.492 arrival time -2.337 ------------------------------------------------------------------- slack 24.154 Slack (MET) : 24.167ns (required time - arrival time) Source: ngFEC/fabric_clk_PS_toggle_reg/C (rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/g_pm[12].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D (rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: fabric_clk_PSOUT Path Type: Setup (Max at Slow Process Corner) Requirement: 24.951ns (fabric_clk_PSOUT rise@24.951ns - fabric_clk_PSOUT rise@0.000ns) Data Path Delay: 0.623ns (logic 0.259ns (41.578%) route 0.364ns (58.422%)) Logic Levels: 0 Clock Path Skew: -0.025ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.439ns = ( 26.390 - 24.951 ) Source Clock Delay (SCD): 1.681ns Clock Pessimism Removal (CPR): 0.217ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_PSOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.802 0.802 r ngFEC/fclk_ibuf/O net (fo=1, routed) 1.081 1.883 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -4.638 -2.755 r ngFEC/fabric_clk_MMCME2/CLKOUT0 net (fo=1, routed) 2.546 -0.209 ngFEC/fabric_clk_PSOUT BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.093 -0.116 r ngFEC/fabric_clk_PS_bufg/O net (fo=13, routed) 1.797 1.681 ngFEC/fabric_clk_PS SLICE_X150Y350 FDRE r ngFEC/fabric_clk_PS_toggle_reg/C ------------------------------------------------------------------- ------------------- SLICE_X150Y350 FDRE (Prop_fdre_C_Q) 0.259 1.940 r ngFEC/fabric_clk_PS_toggle_reg/Q net (fo=13, routed) 0.364 2.304 ngFEC/g_pm[12].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_in SLICE_X148Y351 FDRE r ngFEC/g_pm[12].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_PSOUT rise edge) 24.951 24.951 r AK18 0.000 24.951 r fabric_clk_p (IN) net (fo=0) 0.000 24.951 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.725 25.676 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.986 26.662 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -4.330 22.332 r ngFEC/fabric_clk_MMCME2/CLKOUT0 net (fo=1, routed) 2.411 24.743 ngFEC/fabric_clk_PSOUT BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.083 24.826 r ngFEC/fabric_clk_PS_bufg/O net (fo=13, routed) 1.564 26.390 ngFEC/g_pm[12].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_clk SLICE_X148Y351 FDRE r ngFEC/g_pm[12].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C clock pessimism 0.217 26.607 clock uncertainty -0.128 26.480 SLICE_X148Y351 FDRE (Setup_fdre_C_D) -0.008 26.472 ngFEC/g_pm[12].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg ------------------------------------------------------------------- required time 26.472 arrival time -2.304 ------------------------------------------------------------------- slack 24.167 Slack (MET) : 24.171ns (required time - arrival time) Source: ngFEC/fabric_clk_PS_toggle_reg/C (rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D (rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: fabric_clk_PSOUT Path Type: Setup (Max at Slow Process Corner) Requirement: 24.951ns (fabric_clk_PSOUT rise@24.951ns - fabric_clk_PSOUT rise@0.000ns) Data Path Delay: 0.656ns (logic 0.259ns (39.486%) route 0.397ns (60.514%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.439ns = ( 26.390 - 24.951 ) Source Clock Delay (SCD): 1.681ns Clock Pessimism Removal (CPR): 0.242ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_PSOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.802 0.802 r ngFEC/fclk_ibuf/O net (fo=1, routed) 1.081 1.883 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -4.638 -2.755 r ngFEC/fabric_clk_MMCME2/CLKOUT0 net (fo=1, routed) 2.546 -0.209 ngFEC/fabric_clk_PSOUT BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.093 -0.116 r ngFEC/fabric_clk_PS_bufg/O net (fo=13, routed) 1.797 1.681 ngFEC/fabric_clk_PS SLICE_X150Y350 FDRE r ngFEC/fabric_clk_PS_toggle_reg/C ------------------------------------------------------------------- ------------------- SLICE_X150Y350 FDRE (Prop_fdre_C_Q) 0.259 1.940 r ngFEC/fabric_clk_PS_toggle_reg/Q net (fo=13, routed) 0.397 2.337 ngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_in SLICE_X150Y350 FDRE r ngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_PSOUT rise edge) 24.951 24.951 r AK18 0.000 24.951 r fabric_clk_p (IN) net (fo=0) 0.000 24.951 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.725 25.676 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.986 26.662 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -4.330 22.332 r ngFEC/fabric_clk_MMCME2/CLKOUT0 net (fo=1, routed) 2.411 24.743 ngFEC/fabric_clk_PSOUT BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.083 24.826 r ngFEC/fabric_clk_PS_bufg/O net (fo=13, routed) 1.564 26.390 ngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_clk SLICE_X150Y350 FDRE r ngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C clock pessimism 0.242 26.632 clock uncertainty -0.128 26.505 SLICE_X150Y350 FDRE (Setup_fdre_C_D) 0.004 26.509 ngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg ------------------------------------------------------------------- required time 26.509 arrival time -2.337 ------------------------------------------------------------------- slack 24.171 Slack (MET) : 24.214ns (required time - arrival time) Source: ngFEC/fabric_clk_PS_toggle_reg/C (rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/fabric_clk_PS_toggle_reg/D (rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: fabric_clk_PSOUT Path Type: Setup (Max at Slow Process Corner) Requirement: 24.951ns (fabric_clk_PSOUT rise@24.951ns - fabric_clk_PSOUT rise@0.000ns) Data Path Delay: 0.675ns (logic 0.302ns (44.752%) route 0.373ns (55.248%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.439ns = ( 26.390 - 24.951 ) Source Clock Delay (SCD): 1.681ns Clock Pessimism Removal (CPR): 0.242ns Clock Uncertainty: 0.128ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.246ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_PSOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.802 0.802 r ngFEC/fclk_ibuf/O net (fo=1, routed) 1.081 1.883 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -4.638 -2.755 r ngFEC/fabric_clk_MMCME2/CLKOUT0 net (fo=1, routed) 2.546 -0.209 ngFEC/fabric_clk_PSOUT BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.093 -0.116 r ngFEC/fabric_clk_PS_bufg/O net (fo=13, routed) 1.797 1.681 ngFEC/fabric_clk_PS SLICE_X150Y350 FDRE r ngFEC/fabric_clk_PS_toggle_reg/C ------------------------------------------------------------------- ------------------- SLICE_X150Y350 FDRE (Prop_fdre_C_Q) 0.259 1.940 f ngFEC/fabric_clk_PS_toggle_reg/Q net (fo=13, routed) 0.373 2.313 ngFEC/fabric_clk_PS_toggle SLICE_X150Y350 LUT1 (Prop_lut1_I0_O) 0.043 2.356 r ngFEC/fabric_clk_PS_toggle_i_1/O net (fo=1, routed) 0.000 2.356 ngFEC/fabric_clk_PS_toggle_i_1_n_0 SLICE_X150Y350 FDRE r ngFEC/fabric_clk_PS_toggle_reg/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_PSOUT rise edge) 24.951 24.951 r AK18 0.000 24.951 r fabric_clk_p (IN) net (fo=0) 0.000 24.951 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.725 25.676 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.986 26.662 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -4.330 22.332 r ngFEC/fabric_clk_MMCME2/CLKOUT0 net (fo=1, routed) 2.411 24.743 ngFEC/fabric_clk_PSOUT BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.083 24.826 r ngFEC/fabric_clk_PS_bufg/O net (fo=13, routed) 1.564 26.390 ngFEC/fabric_clk_PS SLICE_X150Y350 FDRE r ngFEC/fabric_clk_PS_toggle_reg/C clock pessimism 0.242 26.632 clock uncertainty -0.128 26.505 SLICE_X150Y350 FDRE (Setup_fdre_C_D) 0.066 26.571 ngFEC/fabric_clk_PS_toggle_reg ------------------------------------------------------------------- required time 26.571 arrival time -2.356 ------------------------------------------------------------------- slack 24.214 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.145ns (arrival time - required time) Source: ngFEC/fabric_clk_PS_toggle_reg/C (rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D (rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: fabric_clk_PSOUT Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_PSOUT rise@0.000ns - fabric_clk_PSOUT rise@0.000ns) Data Path Delay: 0.190ns (logic 0.118ns (62.162%) route 0.072ns (37.838%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.083ns Source Clock Delay (SCD): 0.964ns Clock Pessimism Removal (CPR): 0.119ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_PSOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.426 0.426 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.503 0.929 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.995 -1.066 r ngFEC/fabric_clk_MMCME2/CLKOUT0 net (fo=1, routed) 1.173 0.107 ngFEC/fabric_clk_PSOUT BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.026 0.133 r ngFEC/fabric_clk_PS_bufg/O net (fo=13, routed) 0.831 0.964 ngFEC/fabric_clk_PS SLICE_X150Y350 FDRE r ngFEC/fabric_clk_PS_toggle_reg/C ------------------------------------------------------------------- ------------------- SLICE_X150Y350 FDRE (Prop_fdre_C_Q) 0.118 1.082 r ngFEC/fabric_clk_PS_toggle_reg/Q net (fo=13, routed) 0.072 1.154 ngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_in SLICE_X150Y350 FDRE r ngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_PSOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.499 0.499 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.553 1.052 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.340 -1.288 r ngFEC/fabric_clk_MMCME2/CLKOUT0 net (fo=1, routed) 1.242 -0.046 ngFEC/fabric_clk_PSOUT BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.030 -0.016 r ngFEC/fabric_clk_PS_bufg/O net (fo=13, routed) 1.099 1.083 ngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_clk SLICE_X150Y350 FDRE r ngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C clock pessimism -0.119 0.964 SLICE_X150Y350 FDRE (Hold_fdre_C_D) 0.045 1.009 ngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg ------------------------------------------------------------------- required time -1.009 arrival time 1.154 ------------------------------------------------------------------- slack 0.145 Slack (MET) : 0.205ns (arrival time - required time) Source: ngFEC/fabric_clk_PS_toggle_reg/C (rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D (rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: fabric_clk_PSOUT Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_PSOUT rise@0.000ns - fabric_clk_PSOUT rise@0.000ns) Data Path Delay: 0.250ns (logic 0.118ns (47.155%) route 0.132ns (52.846%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.083ns Source Clock Delay (SCD): 0.964ns Clock Pessimism Removal (CPR): 0.119ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_PSOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.426 0.426 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.503 0.929 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.995 -1.066 r ngFEC/fabric_clk_MMCME2/CLKOUT0 net (fo=1, routed) 1.173 0.107 ngFEC/fabric_clk_PSOUT BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.026 0.133 r ngFEC/fabric_clk_PS_bufg/O net (fo=13, routed) 0.831 0.964 ngFEC/fabric_clk_PS SLICE_X150Y350 FDRE r ngFEC/fabric_clk_PS_toggle_reg/C ------------------------------------------------------------------- ------------------- SLICE_X150Y350 FDRE (Prop_fdre_C_Q) 0.118 1.082 r ngFEC/fabric_clk_PS_toggle_reg/Q net (fo=13, routed) 0.132 1.215 ngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_in SLICE_X150Y350 FDRE r ngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_PSOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.499 0.499 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.553 1.052 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.340 -1.288 r ngFEC/fabric_clk_MMCME2/CLKOUT0 net (fo=1, routed) 1.242 -0.046 ngFEC/fabric_clk_PSOUT BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.030 -0.016 r ngFEC/fabric_clk_PS_bufg/O net (fo=13, routed) 1.099 1.083 ngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_clk SLICE_X150Y350 FDRE r ngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C clock pessimism -0.119 0.964 SLICE_X150Y350 FDRE (Hold_fdre_C_D) 0.045 1.009 ngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg ------------------------------------------------------------------- required time -1.009 arrival time 1.215 ------------------------------------------------------------------- slack 0.205 Slack (MET) : 0.212ns (arrival time - required time) Source: ngFEC/fabric_clk_PS_toggle_reg/C (rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/g_pm[3].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D (rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: fabric_clk_PSOUT Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_PSOUT rise@0.000ns - fabric_clk_PSOUT rise@0.000ns) Data Path Delay: 0.250ns (logic 0.118ns (47.155%) route 0.132ns (52.846%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.083ns Source Clock Delay (SCD): 0.964ns Clock Pessimism Removal (CPR): 0.119ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_PSOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.426 0.426 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.503 0.929 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.995 -1.066 r ngFEC/fabric_clk_MMCME2/CLKOUT0 net (fo=1, routed) 1.173 0.107 ngFEC/fabric_clk_PSOUT BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.026 0.133 r ngFEC/fabric_clk_PS_bufg/O net (fo=13, routed) 0.831 0.964 ngFEC/fabric_clk_PS SLICE_X150Y350 FDRE r ngFEC/fabric_clk_PS_toggle_reg/C ------------------------------------------------------------------- ------------------- SLICE_X150Y350 FDRE (Prop_fdre_C_Q) 0.118 1.082 r ngFEC/fabric_clk_PS_toggle_reg/Q net (fo=13, routed) 0.132 1.215 ngFEC/g_pm[3].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_in SLICE_X150Y350 FDRE r ngFEC/g_pm[3].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_PSOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.499 0.499 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.553 1.052 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.340 -1.288 r ngFEC/fabric_clk_MMCME2/CLKOUT0 net (fo=1, routed) 1.242 -0.046 ngFEC/fabric_clk_PSOUT BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.030 -0.016 r ngFEC/fabric_clk_PS_bufg/O net (fo=13, routed) 1.099 1.083 ngFEC/g_pm[3].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_clk SLICE_X150Y350 FDRE r ngFEC/g_pm[3].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C clock pessimism -0.119 0.964 SLICE_X150Y350 FDRE (Hold_fdre_C_D) 0.038 1.002 ngFEC/g_pm[3].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg ------------------------------------------------------------------- required time -1.002 arrival time 1.215 ------------------------------------------------------------------- slack 0.212 Slack (MET) : 0.261ns (arrival time - required time) Source: ngFEC/fabric_clk_PS_toggle_reg/C (rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/g_pm[12].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D (rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: fabric_clk_PSOUT Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_PSOUT rise@0.000ns - fabric_clk_PSOUT rise@0.000ns) Data Path Delay: 0.315ns (logic 0.118ns (37.468%) route 0.197ns (62.532%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.083ns Source Clock Delay (SCD): 0.964ns Clock Pessimism Removal (CPR): 0.105ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_PSOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.426 0.426 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.503 0.929 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.995 -1.066 r ngFEC/fabric_clk_MMCME2/CLKOUT0 net (fo=1, routed) 1.173 0.107 ngFEC/fabric_clk_PSOUT BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.026 0.133 r ngFEC/fabric_clk_PS_bufg/O net (fo=13, routed) 0.831 0.964 ngFEC/fabric_clk_PS SLICE_X150Y350 FDRE r ngFEC/fabric_clk_PS_toggle_reg/C ------------------------------------------------------------------- ------------------- SLICE_X150Y350 FDRE (Prop_fdre_C_Q) 0.118 1.082 r ngFEC/fabric_clk_PS_toggle_reg/Q net (fo=13, routed) 0.197 1.279 ngFEC/g_pm[12].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_in SLICE_X148Y351 FDRE r ngFEC/g_pm[12].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_PSOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.499 0.499 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.553 1.052 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.340 -1.288 r ngFEC/fabric_clk_MMCME2/CLKOUT0 net (fo=1, routed) 1.242 -0.046 ngFEC/fabric_clk_PSOUT BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.030 -0.016 r ngFEC/fabric_clk_PS_bufg/O net (fo=13, routed) 1.099 1.083 ngFEC/g_pm[12].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_clk SLICE_X148Y351 FDRE r ngFEC/g_pm[12].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C clock pessimism -0.105 0.978 SLICE_X148Y351 FDRE (Hold_fdre_C_D) 0.040 1.018 ngFEC/g_pm[12].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg ------------------------------------------------------------------- required time -1.018 arrival time 1.279 ------------------------------------------------------------------- slack 0.261 Slack (MET) : 0.264ns (arrival time - required time) Source: ngFEC/fabric_clk_PS_toggle_reg/C (rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/fabric_clk_PS_toggle_reg/D (rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: fabric_clk_PSOUT Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_PSOUT rise@0.000ns - fabric_clk_PSOUT rise@0.000ns) Data Path Delay: 0.351ns (logic 0.146ns (41.616%) route 0.205ns (58.384%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.083ns Source Clock Delay (SCD): 0.964ns Clock Pessimism Removal (CPR): 0.119ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_PSOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.426 0.426 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.503 0.929 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.995 -1.066 r ngFEC/fabric_clk_MMCME2/CLKOUT0 net (fo=1, routed) 1.173 0.107 ngFEC/fabric_clk_PSOUT BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.026 0.133 r ngFEC/fabric_clk_PS_bufg/O net (fo=13, routed) 0.831 0.964 ngFEC/fabric_clk_PS SLICE_X150Y350 FDRE r ngFEC/fabric_clk_PS_toggle_reg/C ------------------------------------------------------------------- ------------------- SLICE_X150Y350 FDRE (Prop_fdre_C_Q) 0.118 1.082 f ngFEC/fabric_clk_PS_toggle_reg/Q net (fo=13, routed) 0.205 1.287 ngFEC/fabric_clk_PS_toggle SLICE_X150Y350 LUT1 (Prop_lut1_I0_O) 0.028 1.315 r ngFEC/fabric_clk_PS_toggle_i_1/O net (fo=1, routed) 0.000 1.315 ngFEC/fabric_clk_PS_toggle_i_1_n_0 SLICE_X150Y350 FDRE r ngFEC/fabric_clk_PS_toggle_reg/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_PSOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.499 0.499 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.553 1.052 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.340 -1.288 r ngFEC/fabric_clk_MMCME2/CLKOUT0 net (fo=1, routed) 1.242 -0.046 ngFEC/fabric_clk_PSOUT BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.030 -0.016 r ngFEC/fabric_clk_PS_bufg/O net (fo=13, routed) 1.099 1.083 ngFEC/fabric_clk_PS SLICE_X150Y350 FDRE r ngFEC/fabric_clk_PS_toggle_reg/C clock pessimism -0.119 0.964 SLICE_X150Y350 FDRE (Hold_fdre_C_D) 0.087 1.051 ngFEC/fabric_clk_PS_toggle_reg ------------------------------------------------------------------- required time -1.051 arrival time 1.315 ------------------------------------------------------------------- slack 0.264 Slack (MET) : 0.292ns (arrival time - required time) Source: ngFEC/fabric_clk_PS_toggle_reg/C (rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D (rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: fabric_clk_PSOUT Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_PSOUT rise@0.000ns - fabric_clk_PSOUT rise@0.000ns) Data Path Delay: 0.330ns (logic 0.118ns (35.765%) route 0.212ns (64.235%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.083ns Source Clock Delay (SCD): 0.964ns Clock Pessimism Removal (CPR): 0.119ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_PSOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.426 0.426 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.503 0.929 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.995 -1.066 r ngFEC/fabric_clk_MMCME2/CLKOUT0 net (fo=1, routed) 1.173 0.107 ngFEC/fabric_clk_PSOUT BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.026 0.133 r ngFEC/fabric_clk_PS_bufg/O net (fo=13, routed) 0.831 0.964 ngFEC/fabric_clk_PS SLICE_X150Y350 FDRE r ngFEC/fabric_clk_PS_toggle_reg/C ------------------------------------------------------------------- ------------------- SLICE_X150Y350 FDRE (Prop_fdre_C_Q) 0.118 1.082 r ngFEC/fabric_clk_PS_toggle_reg/Q net (fo=13, routed) 0.212 1.294 ngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_in SLICE_X150Y350 FDRE r ngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_PSOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.499 0.499 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.553 1.052 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.340 -1.288 r ngFEC/fabric_clk_MMCME2/CLKOUT0 net (fo=1, routed) 1.242 -0.046 ngFEC/fabric_clk_PSOUT BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.030 -0.016 r ngFEC/fabric_clk_PS_bufg/O net (fo=13, routed) 1.099 1.083 ngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_clk SLICE_X150Y350 FDRE r ngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C clock pessimism -0.119 0.964 SLICE_X150Y350 FDRE (Hold_fdre_C_D) 0.038 1.002 ngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg ------------------------------------------------------------------- required time -1.002 arrival time 1.294 ------------------------------------------------------------------- slack 0.292 Slack (MET) : 0.299ns (arrival time - required time) Source: ngFEC/fabric_clk_PS_toggle_reg/C (rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D (rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: fabric_clk_PSOUT Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_PSOUT rise@0.000ns - fabric_clk_PSOUT rise@0.000ns) Data Path Delay: 0.330ns (logic 0.118ns (35.765%) route 0.212ns (64.235%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.083ns Source Clock Delay (SCD): 0.964ns Clock Pessimism Removal (CPR): 0.119ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_PSOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.426 0.426 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.503 0.929 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.995 -1.066 r ngFEC/fabric_clk_MMCME2/CLKOUT0 net (fo=1, routed) 1.173 0.107 ngFEC/fabric_clk_PSOUT BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.026 0.133 r ngFEC/fabric_clk_PS_bufg/O net (fo=13, routed) 0.831 0.964 ngFEC/fabric_clk_PS SLICE_X150Y350 FDRE r ngFEC/fabric_clk_PS_toggle_reg/C ------------------------------------------------------------------- ------------------- SLICE_X150Y350 FDRE (Prop_fdre_C_Q) 0.118 1.082 r ngFEC/fabric_clk_PS_toggle_reg/Q net (fo=13, routed) 0.212 1.294 ngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_in SLICE_X150Y350 FDRE r ngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_PSOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.499 0.499 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.553 1.052 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.340 -1.288 r ngFEC/fabric_clk_MMCME2/CLKOUT0 net (fo=1, routed) 1.242 -0.046 ngFEC/fabric_clk_PSOUT BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.030 -0.016 r ngFEC/fabric_clk_PS_bufg/O net (fo=13, routed) 1.099 1.083 ngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_clk SLICE_X150Y350 FDRE r ngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C clock pessimism -0.119 0.964 SLICE_X150Y350 FDRE (Hold_fdre_C_D) 0.031 0.995 ngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg ------------------------------------------------------------------- required time -0.995 arrival time 1.294 ------------------------------------------------------------------- slack 0.299 Slack (MET) : 0.322ns (arrival time - required time) Source: ngFEC/fabric_clk_PS_toggle_reg/C (rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D (rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: fabric_clk_PSOUT Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_PSOUT rise@0.000ns - fabric_clk_PSOUT rise@0.000ns) Data Path Delay: 0.389ns (logic 0.118ns (30.315%) route 0.271ns (69.685%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.083ns Source Clock Delay (SCD): 0.964ns Clock Pessimism Removal (CPR): 0.119ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_PSOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.426 0.426 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.503 0.929 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.995 -1.066 r ngFEC/fabric_clk_MMCME2/CLKOUT0 net (fo=1, routed) 1.173 0.107 ngFEC/fabric_clk_PSOUT BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.026 0.133 r ngFEC/fabric_clk_PS_bufg/O net (fo=13, routed) 0.831 0.964 ngFEC/fabric_clk_PS SLICE_X150Y350 FDRE r ngFEC/fabric_clk_PS_toggle_reg/C ------------------------------------------------------------------- ------------------- SLICE_X150Y350 FDRE (Prop_fdre_C_Q) 0.118 1.082 r ngFEC/fabric_clk_PS_toggle_reg/Q net (fo=13, routed) 0.271 1.354 ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_in SLICE_X150Y350 FDRE r ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_PSOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.499 0.499 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.553 1.052 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.340 -1.288 r ngFEC/fabric_clk_MMCME2/CLKOUT0 net (fo=1, routed) 1.242 -0.046 ngFEC/fabric_clk_PSOUT BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.030 -0.016 r ngFEC/fabric_clk_PS_bufg/O net (fo=13, routed) 1.099 1.083 ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_clk SLICE_X150Y350 FDRE r ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C clock pessimism -0.119 0.964 SLICE_X150Y350 FDRE (Hold_fdre_C_D) 0.067 1.031 ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg ------------------------------------------------------------------- required time -1.031 arrival time 1.354 ------------------------------------------------------------------- slack 0.322 Slack (MET) : 0.342ns (arrival time - required time) Source: ngFEC/fabric_clk_PS_toggle_reg/C (rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D (rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: fabric_clk_PSOUT Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_PSOUT rise@0.000ns - fabric_clk_PSOUT rise@0.000ns) Data Path Delay: 0.409ns (logic 0.118ns (28.877%) route 0.291ns (71.123%)) Logic Levels: 0 Clock Path Skew: 0.029ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.077ns Source Clock Delay (SCD): 0.964ns Clock Pessimism Removal (CPR): 0.084ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_PSOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.426 0.426 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.503 0.929 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.995 -1.066 r ngFEC/fabric_clk_MMCME2/CLKOUT0 net (fo=1, routed) 1.173 0.107 ngFEC/fabric_clk_PSOUT BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.026 0.133 r ngFEC/fabric_clk_PS_bufg/O net (fo=13, routed) 0.831 0.964 ngFEC/fabric_clk_PS SLICE_X150Y350 FDRE r ngFEC/fabric_clk_PS_toggle_reg/C ------------------------------------------------------------------- ------------------- SLICE_X150Y350 FDRE (Prop_fdre_C_Q) 0.118 1.082 r ngFEC/fabric_clk_PS_toggle_reg/Q net (fo=13, routed) 0.291 1.373 ngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_in SLICE_X143Y350 FDRE r ngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_PSOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.499 0.499 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.553 1.052 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.340 -1.288 r ngFEC/fabric_clk_MMCME2/CLKOUT0 net (fo=1, routed) 1.242 -0.046 ngFEC/fabric_clk_PSOUT BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.030 -0.016 r ngFEC/fabric_clk_PS_bufg/O net (fo=13, routed) 1.093 1.077 ngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_clk SLICE_X143Y350 FDRE r ngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C clock pessimism -0.084 0.993 SLICE_X143Y350 FDRE (Hold_fdre_C_D) 0.038 1.031 ngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg ------------------------------------------------------------------- required time -1.031 arrival time 1.373 ------------------------------------------------------------------- slack 0.342 Slack (MET) : 0.379ns (arrival time - required time) Source: ngFEC/fabric_clk_PS_toggle_reg/C (rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D (rising edge-triggered cell FDRE clocked by fabric_clk_PSOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: fabric_clk_PSOUT Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_PSOUT rise@0.000ns - fabric_clk_PSOUT rise@0.000ns) Data Path Delay: 0.429ns (logic 0.118ns (27.528%) route 0.311ns (72.472%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.083ns Source Clock Delay (SCD): 0.964ns Clock Pessimism Removal (CPR): 0.105ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_PSOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.426 0.426 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.503 0.929 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -1.995 -1.066 r ngFEC/fabric_clk_MMCME2/CLKOUT0 net (fo=1, routed) 1.173 0.107 ngFEC/fabric_clk_PSOUT BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.026 0.133 r ngFEC/fabric_clk_PS_bufg/O net (fo=13, routed) 0.831 0.964 ngFEC/fabric_clk_PS SLICE_X150Y350 FDRE r ngFEC/fabric_clk_PS_toggle_reg/C ------------------------------------------------------------------- ------------------- SLICE_X150Y350 FDRE (Prop_fdre_C_Q) 0.118 1.082 r ngFEC/fabric_clk_PS_toggle_reg/Q net (fo=13, routed) 0.311 1.393 ngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_in SLICE_X148Y351 FDRE r ngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/D ------------------------------------------------------------------- ------------------- (clock fabric_clk_PSOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.499 0.499 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.553 1.052 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0) -2.340 -1.288 r ngFEC/fabric_clk_MMCME2/CLKOUT0 net (fo=1, routed) 1.242 -0.046 ngFEC/fabric_clk_PSOUT BUFGCTRL_X0Y10 BUFG (Prop_bufg_I_O) 0.030 -0.016 r ngFEC/fabric_clk_PS_bufg/O net (fo=13, routed) 1.099 1.083 ngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_clk SLICE_X148Y351 FDRE r ngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C clock pessimism -0.105 0.978 SLICE_X148Y351 FDRE (Hold_fdre_C_D) 0.036 1.014 ngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg ------------------------------------------------------------------- required time -1.014 arrival time 1.393 ------------------------------------------------------------------- slack 0.379 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: fabric_clk_PSOUT Waveform(ns): { 0.000 12.476 } Period(ns): 24.951 Sources: { ngFEC/fabric_clk_MMCME2/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 1.409 24.951 23.542 BUFGCTRL_X0Y10 ngFEC/fabric_clk_PS_bufg/I Min Period n/a MMCME2_ADV/CLKOUT0 n/a 1.071 24.951 23.880 MMCME2_ADV_X0Y0 ngFEC/fabric_clk_MMCME2/CLKOUT0 Min Period n/a FDRE/C n/a 0.750 24.951 24.201 SLICE_X150Y350 ngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C Min Period n/a FDRE/C n/a 0.750 24.951 24.201 SLICE_X150Y350 ngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C Min Period n/a FDRE/C n/a 0.750 24.951 24.201 SLICE_X150Y350 ngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C Min Period n/a FDRE/C n/a 0.700 24.951 24.251 SLICE_X150Y350 ngFEC/fabric_clk_PS_toggle_reg/C Min Period n/a FDRE/C n/a 0.700 24.951 24.251 SLICE_X150Y350 ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C Min Period n/a FDRE/C n/a 0.700 24.951 24.251 SLICE_X150Y350 ngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C Min Period n/a FDRE/C n/a 0.700 24.951 24.251 SLICE_X148Y351 ngFEC/g_pm[12].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C Min Period n/a FDRE/C n/a 0.700 24.951 24.251 SLICE_X143Y350 ngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 24.951 188.409 MMCME2_ADV_X0Y0 ngFEC/fabric_clk_MMCME2/CLKOUT0 Low Pulse Width Slow FDRE/C n/a 0.400 12.476 12.076 SLICE_X150Y350 ngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C Low Pulse Width Fast FDRE/C n/a 0.400 12.476 12.076 SLICE_X150Y350 ngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C Low Pulse Width Slow FDRE/C n/a 0.400 12.476 12.076 SLICE_X150Y350 ngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C Low Pulse Width Fast FDRE/C n/a 0.400 12.476 12.076 SLICE_X150Y350 ngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C Low Pulse Width Slow FDRE/C n/a 0.400 12.476 12.076 SLICE_X150Y350 ngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C Low Pulse Width Fast FDRE/C n/a 0.400 12.476 12.076 SLICE_X150Y350 ngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C Low Pulse Width Fast FDRE/C n/a 0.350 12.475 12.125 SLICE_X143Y350 ngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C Low Pulse Width Fast FDRE/C n/a 0.350 12.475 12.125 SLICE_X143Y350 ngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C Low Pulse Width Fast FDRE/C n/a 0.350 12.475 12.125 SLICE_X143Y350 ngFEC/g_pm[8].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C Low Pulse Width Fast FDRE/C n/a 0.350 12.475 12.125 SLICE_X143Y350 ngFEC/g_pm[9].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C High Pulse Width Slow FDRE/C n/a 0.350 12.476 12.125 SLICE_X150Y350 ngFEC/fabric_clk_PS_toggle_reg/C High Pulse Width Fast FDRE/C n/a 0.350 12.476 12.125 SLICE_X150Y350 ngFEC/fabric_clk_PS_toggle_reg/C High Pulse Width Slow FDRE/C n/a 0.350 12.476 12.125 SLICE_X150Y350 ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C High Pulse Width Fast FDRE/C n/a 0.350 12.476 12.125 SLICE_X150Y350 ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C High Pulse Width Slow FDRE/C n/a 0.350 12.476 12.125 SLICE_X150Y350 ngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C High Pulse Width Fast FDRE/C n/a 0.350 12.476 12.125 SLICE_X150Y350 ngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C High Pulse Width Slow FDRE/C n/a 0.350 12.476 12.125 SLICE_X148Y351 ngFEC/g_pm[12].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C High Pulse Width Fast FDRE/C n/a 0.350 12.476 12.125 SLICE_X148Y351 ngFEC/g_pm[12].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C High Pulse Width Slow FDRE/C n/a 0.350 12.476 12.125 SLICE_X143Y350 ngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C High Pulse Width Slow FDRE/C n/a 0.350 12.476 12.125 SLICE_X150Y350 ngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst/src_ff_reg/C --------------------------------------------------------------------------------------------------- From Clock: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK To Clock: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 5.909ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Waveform(ns): { 0.000 4.167 } Period(ns): 8.333 Sources: { ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/RXOUTCLK n/a 2.424 8.333 5.909 GTXE2_CHANNEL_X0Y28 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Min Period n/a BUFH/I n/a 1.409 8.333 6.925 BUFHCE_X1Y84 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/I --------------------------------------------------------------------------------------------------- From Clock: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK To Clock: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 5.909ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Waveform(ns): { 0.000 4.167 } Period(ns): 8.333 Sources: { ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/TXOUTCLK n/a 2.424 8.333 5.909 GTXE2_CHANNEL_X0Y28 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Min Period n/a BUFG/I n/a 1.409 8.333 6.925 BUFGCTRL_X0Y17 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/I --------------------------------------------------------------------------------------------------- From Clock: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK To Clock: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 5.909ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Waveform(ns): { 0.000 4.167 } Period(ns): 8.333 Sources: { ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/RXOUTCLK n/a 2.424 8.333 5.909 GTXE2_CHANNEL_X0Y31 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Min Period n/a BUFH/I n/a 1.409 8.333 6.925 BUFHCE_X1Y85 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/I --------------------------------------------------------------------------------------------------- From Clock: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK To Clock: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 5.909ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Waveform(ns): { 0.000 4.167 } Period(ns): 8.333 Sources: { ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/TXOUTCLK n/a 2.424 8.333 5.909 GTXE2_CHANNEL_X0Y31 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Min Period n/a BUFG/I n/a 1.409 8.333 6.925 BUFGCTRL_X0Y18 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/I --------------------------------------------------------------------------------------------------- From Clock: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK To Clock: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 5.909ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Waveform(ns): { 0.000 4.167 } Period(ns): 8.333 Sources: { ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/RXOUTCLK n/a 2.424 8.333 5.909 GTXE2_CHANNEL_X0Y30 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Min Period n/a BUFH/I n/a 1.409 8.333 6.925 BUFHCE_X1Y86 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/I --------------------------------------------------------------------------------------------------- From Clock: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK To Clock: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 5.909ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Waveform(ns): { 0.000 4.167 } Period(ns): 8.333 Sources: { ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/TXOUTCLK n/a 2.424 8.333 5.909 GTXE2_CHANNEL_X0Y30 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Min Period n/a BUFG/I n/a 1.409 8.333 6.925 BUFGCTRL_X0Y19 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/I --------------------------------------------------------------------------------------------------- From Clock: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK To Clock: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 5.909ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Waveform(ns): { 0.000 4.167 } Period(ns): 8.333 Sources: { ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/RXOUTCLK n/a 2.424 8.333 5.909 GTXE2_CHANNEL_X0Y25 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Min Period n/a BUFH/I n/a 1.409 8.333 6.925 BUFHCE_X1Y72 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/I --------------------------------------------------------------------------------------------------- From Clock: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK To Clock: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 5.909ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Waveform(ns): { 0.000 4.167 } Period(ns): 8.333 Sources: { ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/TXOUTCLK n/a 2.424 8.333 5.909 GTXE2_CHANNEL_X0Y25 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Min Period n/a BUFG/I n/a 1.409 8.333 6.925 BUFGCTRL_X0Y16 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/I --------------------------------------------------------------------------------------------------- From Clock: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK To Clock: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 5.909ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Waveform(ns): { 0.000 4.167 } Period(ns): 8.333 Sources: { ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/RXOUTCLK n/a 2.424 8.333 5.909 GTXE2_CHANNEL_X0Y24 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Min Period n/a BUFH/I n/a 1.409 8.333 6.925 BUFHCE_X1Y73 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/I --------------------------------------------------------------------------------------------------- From Clock: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK To Clock: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 5.909ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Waveform(ns): { 0.000 4.167 } Period(ns): 8.333 Sources: { ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/TXOUTCLK n/a 2.424 8.333 5.909 GTXE2_CHANNEL_X0Y24 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Min Period n/a BUFG/I n/a 1.409 8.333 6.925 BUFGCTRL_X0Y20 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/I --------------------------------------------------------------------------------------------------- From Clock: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK To Clock: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 5.909ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Waveform(ns): { 0.000 4.167 } Period(ns): 8.333 Sources: { ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/RXOUTCLK n/a 2.424 8.333 5.909 GTXE2_CHANNEL_X0Y21 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Min Period n/a BUFH/I n/a 1.409 8.333 6.925 BUFHCE_X1Y60 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/I --------------------------------------------------------------------------------------------------- From Clock: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK To Clock: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 5.909ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Waveform(ns): { 0.000 4.167 } Period(ns): 8.333 Sources: { ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/TXOUTCLK n/a 2.424 8.333 5.909 GTXE2_CHANNEL_X0Y21 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Min Period n/a BUFG/I n/a 1.409 8.333 6.925 BUFGCTRL_X0Y21 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/I --------------------------------------------------------------------------------------------------- From Clock: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK To Clock: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 5.909ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Waveform(ns): { 0.000 4.167 } Period(ns): 8.333 Sources: { ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/RXOUTCLK n/a 2.424 8.333 5.909 GTXE2_CHANNEL_X0Y20 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Min Period n/a BUFH/I n/a 1.409 8.333 6.925 BUFHCE_X1Y61 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/I --------------------------------------------------------------------------------------------------- From Clock: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK To Clock: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 5.909ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Waveform(ns): { 0.000 4.167 } Period(ns): 8.333 Sources: { ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/TXOUTCLK n/a 2.424 8.333 5.909 GTXE2_CHANNEL_X0Y20 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Min Period n/a BUFG/I n/a 1.409 8.333 6.925 BUFGCTRL_X0Y22 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/I --------------------------------------------------------------------------------------------------- From Clock: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK To Clock: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 5.909ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Waveform(ns): { 0.000 4.167 } Period(ns): 8.333 Sources: { ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/RXOUTCLK n/a 2.424 8.333 5.909 GTXE2_CHANNEL_X0Y23 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Min Period n/a BUFH/I n/a 1.409 8.333 6.925 BUFHCE_X1Y62 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/I --------------------------------------------------------------------------------------------------- From Clock: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK To Clock: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 5.909ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Waveform(ns): { 0.000 4.167 } Period(ns): 8.333 Sources: { ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/TXOUTCLK n/a 2.424 8.333 5.909 GTXE2_CHANNEL_X0Y23 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Min Period n/a BUFG/I n/a 1.409 8.333 6.925 BUFGCTRL_X0Y23 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/I --------------------------------------------------------------------------------------------------- From Clock: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK To Clock: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 5.909ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Waveform(ns): { 0.000 4.167 } Period(ns): 8.333 Sources: { ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/RXOUTCLK n/a 2.424 8.333 5.909 GTXE2_CHANNEL_X0Y4 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Min Period n/a BUFH/I n/a 1.409 8.333 6.925 BUFHCE_X1Y12 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/I --------------------------------------------------------------------------------------------------- From Clock: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK To Clock: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 5.909ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Waveform(ns): { 0.000 4.167 } Period(ns): 8.333 Sources: { ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/TXOUTCLK n/a 2.424 8.333 5.909 GTXE2_CHANNEL_X0Y4 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Min Period n/a BUFG/I n/a 1.409 8.333 6.925 BUFGCTRL_X0Y3 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/I --------------------------------------------------------------------------------------------------- From Clock: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK To Clock: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 5.909ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Waveform(ns): { 0.000 4.167 } Period(ns): 8.333 Sources: { ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/RXOUTCLK n/a 2.424 8.333 5.909 GTXE2_CHANNEL_X0Y5 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Min Period n/a BUFH/I n/a 1.409 8.333 6.925 BUFHCE_X1Y13 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/I --------------------------------------------------------------------------------------------------- From Clock: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK To Clock: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 5.909ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Waveform(ns): { 0.000 4.167 } Period(ns): 8.333 Sources: { ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/TXOUTCLK n/a 2.424 8.333 5.909 GTXE2_CHANNEL_X0Y5 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Min Period n/a BUFG/I n/a 1.409 8.333 6.925 BUFGCTRL_X0Y4 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/I --------------------------------------------------------------------------------------------------- From Clock: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK To Clock: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 5.909ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Waveform(ns): { 0.000 4.167 } Period(ns): 8.333 Sources: { ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/RXOUTCLK n/a 2.424 8.333 5.909 GTXE2_CHANNEL_X0Y6 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Min Period n/a BUFH/I n/a 1.409 8.333 6.925 BUFHCE_X1Y14 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/I --------------------------------------------------------------------------------------------------- From Clock: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK To Clock: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 5.909ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Waveform(ns): { 0.000 4.167 } Period(ns): 8.333 Sources: { ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/TXOUTCLK n/a 2.424 8.333 5.909 GTXE2_CHANNEL_X0Y6 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Min Period n/a BUFG/I n/a 1.409 8.333 6.925 BUFGCTRL_X0Y5 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/I --------------------------------------------------------------------------------------------------- From Clock: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK To Clock: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 5.909ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Waveform(ns): { 0.000 4.167 } Period(ns): 8.333 Sources: { ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/RXOUTCLK n/a 2.424 8.333 5.909 GTXE2_CHANNEL_X0Y7 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK Min Period n/a BUFH/I n/a 1.409 8.333 6.925 BUFHCE_X1Y15 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/I --------------------------------------------------------------------------------------------------- From Clock: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK To Clock: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA PW : 0 Failing Endpoints, Worst Slack 5.909ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Waveform(ns): { 0.000 4.167 } Period(ns): 8.333 Sources: { ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/TXOUTCLK n/a 2.424 8.333 5.909 GTXE2_CHANNEL_X0Y7 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK Min Period n/a BUFG/I n/a 1.409 8.333 6.925 BUFGCTRL_X0Y6 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/I --------------------------------------------------------------------------------------------------- From Clock: osc125_a To Clock: osc125_a Setup : 0 Failing Endpoints, Worst Slack 7.029ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.172ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 2.000ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 7.029ns (required time - arrival time) Source: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK (rising edge-triggered cell SRLC32E clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[95]/D (rising edge-triggered cell FDRE clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: osc125_a Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (osc125_a rise@8.000ns - osc125_a rise@0.000ns) Data Path Delay: 1.000ns (logic 1.000ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.150ns = ( 12.150 - 8.000 ) Source Clock Delay (SCD): 5.300ns Clock Pessimism Removal (CPR): 1.150ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock osc125_a rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.553 5.300 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg SLICE_X186Y105 SRLC32E r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK ------------------------------------------------------------------- ------------------- SLICE_X186Y105 SRLC32E (Prop_srlc32e_CLK_Q) 1.000 6.300 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/Q net (fo=1, routed) 0.000 6.300 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31_n_0 SLICE_X186Y105 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[95]/D ------------------------------------------------------------------- ------------------- (clock osc125_a rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.414 12.150 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg SLICE_X186Y105 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[95]/C clock pessimism 1.150 13.300 clock uncertainty -0.035 13.264 SLICE_X186Y105 FDRE (Setup_fdre_C_D) 0.064 13.328 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[95] ------------------------------------------------------------------- required time 13.328 arrival time -6.300 ------------------------------------------------------------------- slack 7.029 Slack (MET) : 7.029ns (required time - arrival time) Source: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK (rising edge-triggered cell SRLC32E clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[127]/D (rising edge-triggered cell FDRE clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: osc125_a Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (osc125_a rise@8.000ns - osc125_a rise@0.000ns) Data Path Delay: 1.000ns (logic 1.000ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.144ns = ( 12.144 - 8.000 ) Source Clock Delay (SCD): 5.291ns Clock Pessimism Removal (CPR): 1.147ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock osc125_a rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.544 5.291 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg SLICE_X180Y115 SRLC32E r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK ------------------------------------------------------------------- ------------------- SLICE_X180Y115 SRLC32E (Prop_srlc32e_CLK_Q) 1.000 6.291 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/Q net (fo=1, routed) 0.000 6.291 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31_n_0 SLICE_X180Y115 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[127]/D ------------------------------------------------------------------- ------------------- (clock osc125_a rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.408 12.144 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg SLICE_X180Y115 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[127]/C clock pessimism 1.147 13.291 clock uncertainty -0.035 13.255 SLICE_X180Y115 FDRE (Setup_fdre_C_D) 0.064 13.319 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[127] ------------------------------------------------------------------- required time 13.319 arrival time -6.291 ------------------------------------------------------------------- slack 7.029 Slack (MET) : 7.192ns (required time - arrival time) Source: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[31]_srl32/CLK (rising edge-triggered cell SRLC32E clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/D (rising edge-triggered cell SRLC32E clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: osc125_a Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (osc125_a rise@8.000ns - osc125_a rise@0.000ns) Data Path Delay: 0.737ns (logic 0.737ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.144ns = ( 12.144 - 8.000 ) Source Clock Delay (SCD): 5.291ns Clock Pessimism Removal (CPR): 1.147ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock osc125_a rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.544 5.291 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg SLICE_X180Y115 SRLC32E r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[31]_srl32/CLK ------------------------------------------------------------------- ------------------- SLICE_X180Y115 SRLC32E (Prop_srlc32e_CLK_Q31) 0.737 6.028 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[31]_srl32/Q31 net (fo=1, routed) 0.000 6.028 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[31]_srl32_n_1 SLICE_X180Y115 SRLC32E r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/D ------------------------------------------------------------------- ------------------- (clock osc125_a rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.408 12.144 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg SLICE_X180Y115 SRLC32E r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK clock pessimism 1.147 13.291 clock uncertainty -0.035 13.255 SLICE_X180Y115 SRLC32E (Setup_srlc32e_CLK_D) -0.036 13.219 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32 ------------------------------------------------------------------- required time 13.219 arrival time -6.028 ------------------------------------------------------------------- slack 7.192 Slack (MET) : 7.200ns (required time - arrival time) Source: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK (rising edge-triggered cell SRLC32E clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/D (rising edge-triggered cell SRLC32E clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: osc125_a Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (osc125_a rise@8.000ns - osc125_a rise@0.000ns) Data Path Delay: 0.743ns (logic 0.743ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.150ns = ( 12.150 - 8.000 ) Source Clock Delay (SCD): 5.300ns Clock Pessimism Removal (CPR): 1.150ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock osc125_a rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.553 5.300 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg SLICE_X186Y105 SRLC32E r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK ------------------------------------------------------------------- ------------------- SLICE_X186Y105 SRLC32E (Prop_srlc32e_CLK_Q31) 0.743 6.043 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/Q31 net (fo=1, routed) 0.000 6.043 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32_n_1 SLICE_X186Y105 SRLC32E r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/D ------------------------------------------------------------------- ------------------- (clock osc125_a rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.414 12.150 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg SLICE_X186Y105 SRLC32E r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK clock pessimism 1.150 13.300 clock uncertainty -0.035 13.264 SLICE_X186Y105 SRLC32E (Setup_srlc32e_CLK_D) -0.022 13.242 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31 ------------------------------------------------------------------- required time 13.242 arrival time -6.043 ------------------------------------------------------------------- slack 7.200 Slack (MET) : 7.200ns (required time - arrival time) Source: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLK (rising edge-triggered cell SRLC32E clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/D (rising edge-triggered cell SRLC32E clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: osc125_a Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (osc125_a rise@8.000ns - osc125_a rise@0.000ns) Data Path Delay: 0.743ns (logic 0.743ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.144ns = ( 12.144 - 8.000 ) Source Clock Delay (SCD): 5.291ns Clock Pessimism Removal (CPR): 1.147ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock osc125_a rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.544 5.291 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg SLICE_X180Y115 SRLC32E r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLK ------------------------------------------------------------------- ------------------- SLICE_X180Y115 SRLC32E (Prop_srlc32e_CLK_Q31) 0.743 6.034 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/Q31 net (fo=1, routed) 0.000 6.034 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32_n_1 SLICE_X180Y115 SRLC32E r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/D ------------------------------------------------------------------- ------------------- (clock osc125_a rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.408 12.144 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg SLICE_X180Y115 SRLC32E r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK clock pessimism 1.147 13.291 clock uncertainty -0.035 13.255 SLICE_X180Y115 SRLC32E (Setup_srlc32e_CLK_D) -0.022 13.233 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31 ------------------------------------------------------------------- required time 13.233 arrival time -6.034 ------------------------------------------------------------------- slack 7.200 Slack (MET) : 7.204ns (required time - arrival time) Source: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK (rising edge-triggered cell SRLC32E clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D (rising edge-triggered cell SRLC32E clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: osc125_a Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (osc125_a rise@8.000ns - osc125_a rise@0.000ns) Data Path Delay: 0.735ns (logic 0.735ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.150ns = ( 12.150 - 8.000 ) Source Clock Delay (SCD): 5.300ns Clock Pessimism Removal (CPR): 1.150ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock osc125_a rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.553 5.300 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg SLICE_X186Y105 SRLC32E r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK ------------------------------------------------------------------- ------------------- SLICE_X186Y105 SRLC32E (Prop_srlc32e_CLK_Q31) 0.735 6.035 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/Q31 net (fo=1, routed) 0.000 6.035 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32_n_1 SLICE_X186Y105 SRLC32E r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D ------------------------------------------------------------------- ------------------- (clock osc125_a rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.414 12.150 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg SLICE_X186Y105 SRLC32E r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK clock pessimism 1.150 13.300 clock uncertainty -0.035 13.264 SLICE_X186Y105 SRLC32E (Setup_srlc32e_CLK_D) -0.026 13.238 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32 ------------------------------------------------------------------- required time 13.238 arrival time -6.035 ------------------------------------------------------------------- slack 7.204 Slack (MET) : 7.204ns (required time - arrival time) Source: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK (rising edge-triggered cell SRLC32E clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/D (rising edge-triggered cell SRLC32E clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: osc125_a Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (osc125_a rise@8.000ns - osc125_a rise@0.000ns) Data Path Delay: 0.735ns (logic 0.735ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.144ns = ( 12.144 - 8.000 ) Source Clock Delay (SCD): 5.291ns Clock Pessimism Removal (CPR): 1.147ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock osc125_a rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.544 5.291 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg SLICE_X180Y115 SRLC32E r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK ------------------------------------------------------------------- ------------------- SLICE_X180Y115 SRLC32E (Prop_srlc32e_CLK_Q31) 0.735 6.026 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/Q31 net (fo=1, routed) 0.000 6.026 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32_n_1 SLICE_X180Y115 SRLC32E r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/D ------------------------------------------------------------------- ------------------- (clock osc125_a rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.408 12.144 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg SLICE_X180Y115 SRLC32E r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLK clock pessimism 1.147 13.291 clock uncertainty -0.035 13.255 SLICE_X180Y115 SRLC32E (Setup_srlc32e_CLK_D) -0.026 13.229 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32 ------------------------------------------------------------------- required time 13.229 arrival time -6.026 ------------------------------------------------------------------- slack 7.204 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.172ns (arrival time - required time) Source: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK (rising edge-triggered cell SRLC32E clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/D (rising edge-triggered cell SRLC32E clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: osc125_a Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (osc125_a rise@0.000ns - osc125_a rise@0.000ns) Data Path Delay: 0.271ns (logic 0.271ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.286ns Source Clock Delay (SCD): 1.729ns Clock Pessimism Removal (CPR): 0.557ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock osc125_a rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.686 1.729 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg SLICE_X180Y115 SRLC32E r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK ------------------------------------------------------------------- ------------------- SLICE_X180Y115 SRLC32E (Prop_srlc32e_CLK_Q31) 0.271 2.000 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/Q31 net (fo=1, routed) 0.000 2.000 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32_n_1 SLICE_X180Y115 SRLC32E r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/D ------------------------------------------------------------------- ------------------- (clock osc125_a rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.908 2.286 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg SLICE_X180Y115 SRLC32E r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLK clock pessimism -0.557 1.729 SLICE_X180Y115 SRLC32E (Hold_srlc32e_CLK_D) 0.099 1.828 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32 ------------------------------------------------------------------- required time -1.828 arrival time 2.000 ------------------------------------------------------------------- slack 0.172 Slack (MET) : 0.172ns (arrival time - required time) Source: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK (rising edge-triggered cell SRLC32E clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D (rising edge-triggered cell SRLC32E clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: osc125_a Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (osc125_a rise@0.000ns - osc125_a rise@0.000ns) Data Path Delay: 0.271ns (logic 0.271ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.292ns Source Clock Delay (SCD): 1.733ns Clock Pessimism Removal (CPR): 0.559ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock osc125_a rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.690 1.733 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg SLICE_X186Y105 SRLC32E r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK ------------------------------------------------------------------- ------------------- SLICE_X186Y105 SRLC32E (Prop_srlc32e_CLK_Q31) 0.271 2.004 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/Q31 net (fo=1, routed) 0.000 2.004 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32_n_1 SLICE_X186Y105 SRLC32E r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D ------------------------------------------------------------------- ------------------- (clock osc125_a rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.914 2.292 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg SLICE_X186Y105 SRLC32E r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK clock pessimism -0.559 1.733 SLICE_X186Y105 SRLC32E (Hold_srlc32e_CLK_D) 0.099 1.832 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32 ------------------------------------------------------------------- required time -1.832 arrival time 2.004 ------------------------------------------------------------------- slack 0.172 Slack (MET) : 0.174ns (arrival time - required time) Source: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLK (rising edge-triggered cell SRLC32E clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/D (rising edge-triggered cell SRLC32E clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: osc125_a Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (osc125_a rise@0.000ns - osc125_a rise@0.000ns) Data Path Delay: 0.276ns (logic 0.276ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.286ns Source Clock Delay (SCD): 1.729ns Clock Pessimism Removal (CPR): 0.557ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock osc125_a rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.686 1.729 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg SLICE_X180Y115 SRLC32E r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLK ------------------------------------------------------------------- ------------------- SLICE_X180Y115 SRLC32E (Prop_srlc32e_CLK_Q31) 0.276 2.005 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/Q31 net (fo=1, routed) 0.000 2.005 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32_n_1 SLICE_X180Y115 SRLC32E r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/D ------------------------------------------------------------------- ------------------- (clock osc125_a rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.908 2.286 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg SLICE_X180Y115 SRLC32E r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK clock pessimism -0.557 1.729 SLICE_X180Y115 SRLC32E (Hold_srlc32e_CLK_D) 0.102 1.831 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31 ------------------------------------------------------------------- required time -1.831 arrival time 2.005 ------------------------------------------------------------------- slack 0.174 Slack (MET) : 0.174ns (arrival time - required time) Source: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK (rising edge-triggered cell SRLC32E clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/D (rising edge-triggered cell SRLC32E clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: osc125_a Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (osc125_a rise@0.000ns - osc125_a rise@0.000ns) Data Path Delay: 0.276ns (logic 0.276ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.292ns Source Clock Delay (SCD): 1.733ns Clock Pessimism Removal (CPR): 0.559ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock osc125_a rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.690 1.733 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg SLICE_X186Y105 SRLC32E r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK ------------------------------------------------------------------- ------------------- SLICE_X186Y105 SRLC32E (Prop_srlc32e_CLK_Q31) 0.276 2.009 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/Q31 net (fo=1, routed) 0.000 2.009 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32_n_1 SLICE_X186Y105 SRLC32E r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/D ------------------------------------------------------------------- ------------------- (clock osc125_a rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.914 2.292 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg SLICE_X186Y105 SRLC32E r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK clock pessimism -0.559 1.733 SLICE_X186Y105 SRLC32E (Hold_srlc32e_CLK_D) 0.102 1.835 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31 ------------------------------------------------------------------- required time -1.835 arrival time 2.009 ------------------------------------------------------------------- slack 0.174 Slack (MET) : 0.182ns (arrival time - required time) Source: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[31]_srl32/CLK (rising edge-triggered cell SRLC32E clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/D (rising edge-triggered cell SRLC32E clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: osc125_a Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (osc125_a rise@0.000ns - osc125_a rise@0.000ns) Data Path Delay: 0.276ns (logic 0.276ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.286ns Source Clock Delay (SCD): 1.729ns Clock Pessimism Removal (CPR): 0.557ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock osc125_a rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.686 1.729 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg SLICE_X180Y115 SRLC32E r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[31]_srl32/CLK ------------------------------------------------------------------- ------------------- SLICE_X180Y115 SRLC32E (Prop_srlc32e_CLK_Q31) 0.276 2.005 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[31]_srl32/Q31 net (fo=1, routed) 0.000 2.005 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[31]_srl32_n_1 SLICE_X180Y115 SRLC32E r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/D ------------------------------------------------------------------- ------------------- (clock osc125_a rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.908 2.286 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg SLICE_X180Y115 SRLC32E r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK clock pessimism -0.557 1.729 SLICE_X180Y115 SRLC32E (Hold_srlc32e_CLK_D) 0.094 1.823 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32 ------------------------------------------------------------------- required time -1.823 arrival time 2.005 ------------------------------------------------------------------- slack 0.182 Slack (MET) : 0.311ns (arrival time - required time) Source: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK (rising edge-triggered cell SRLC32E clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[127]/D (rising edge-triggered cell FDRE clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: osc125_a Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (osc125_a rise@0.000ns - osc125_a rise@0.000ns) Data Path Delay: 0.398ns (logic 0.398ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.286ns Source Clock Delay (SCD): 1.729ns Clock Pessimism Removal (CPR): 0.557ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock osc125_a rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.686 1.729 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg SLICE_X180Y115 SRLC32E r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK ------------------------------------------------------------------- ------------------- SLICE_X180Y115 SRLC32E (Prop_srlc32e_CLK_Q) 0.398 2.127 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/Q net (fo=1, routed) 0.000 2.127 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31_n_0 SLICE_X180Y115 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[127]/D ------------------------------------------------------------------- ------------------- (clock osc125_a rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.908 2.286 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg SLICE_X180Y115 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[127]/C clock pessimism -0.557 1.729 SLICE_X180Y115 FDRE (Hold_fdre_C_D) 0.087 1.816 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[127] ------------------------------------------------------------------- required time -1.816 arrival time 2.127 ------------------------------------------------------------------- slack 0.311 Slack (MET) : 0.311ns (arrival time - required time) Source: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK (rising edge-triggered cell SRLC32E clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[95]/D (rising edge-triggered cell FDRE clocked by osc125_a {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: osc125_a Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (osc125_a rise@0.000ns - osc125_a rise@0.000ns) Data Path Delay: 0.398ns (logic 0.398ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.292ns Source Clock Delay (SCD): 1.733ns Clock Pessimism Removal (CPR): 0.559ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock osc125_a rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.690 1.733 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg SLICE_X186Y105 SRLC32E r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK ------------------------------------------------------------------- ------------------- SLICE_X186Y105 SRLC32E (Prop_srlc32e_CLK_Q) 0.398 2.131 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/Q net (fo=1, routed) 0.000 2.131 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31_n_0 SLICE_X186Y105 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[95]/D ------------------------------------------------------------------- ------------------- (clock osc125_a rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.914 2.292 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/gtrefclk_bufg SLICE_X186Y105 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[95]/C clock pessimism -0.559 1.733 SLICE_X186Y105 FDRE (Hold_fdre_C_D) 0.087 1.820 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[95] ------------------------------------------------------------------- required time -1.820 arrival time 2.131 ------------------------------------------------------------------- slack 0.311 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: osc125_a Waveform(ns): { 0.000 4.000 } Period(ns): 8.000 Sources: { osc125_a_p } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/DRPCLK n/a 5.714 8.000 2.286 GTXE2_CHANNEL_X0Y8 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i/DRPCLK Min Period n/a GTXE2_CHANNEL/GTREFCLK0 n/a 1.538 8.000 6.462 GTXE2_CHANNEL_X0Y8 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i/GTREFCLK0 Min Period n/a BUFG/I n/a 1.409 8.000 6.591 BUFGCTRL_X0Y8 sys/osc125a_clkbuf/I Min Period n/a IBUFDS_GTE2/I n/a 1.408 8.000 6.592 IBUFDS_GTE2_X0Y5 sys/osc125a_gtebuf/I Min Period n/a PLLE2_ADV/CLKIN1 n/a 1.071 8.000 6.929 PLLE2_ADV_X0Y1 sys/clocks/PLLE2_BASE_inst/CLKIN1 Min Period n/a FDRE/C n/a 0.700 8.000 7.300 SLICE_X186Y105 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[95]/C Min Period n/a FDRE/C n/a 0.700 8.000 7.300 SLICE_X180Y115 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[127]/C Max Period n/a PLLE2_ADV/CLKIN1 n/a 52.633 8.000 44.633 PLLE2_ADV_X0Y1 sys/clocks/PLLE2_BASE_inst/CLKIN1 Low Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 2.000 4.000 2.000 PLLE2_ADV_X0Y1 sys/clocks/PLLE2_BASE_inst/CLKIN1 Low Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 2.000 4.000 2.000 PLLE2_ADV_X0Y1 sys/clocks/PLLE2_BASE_inst/CLKIN1 Low Pulse Width Slow SRLC32E/CLK n/a 0.642 4.000 3.358 SLICE_X186Y105 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK Low Pulse Width Slow SRLC32E/CLK n/a 0.642 4.000 3.358 SLICE_X186Y105 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK Low Pulse Width Slow SRLC32E/CLK n/a 0.642 4.000 3.358 SLICE_X186Y105 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK Low Pulse Width Slow SRLC32E/CLK n/a 0.642 4.000 3.358 SLICE_X180Y115 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK Low Pulse Width Slow SRLC32E/CLK n/a 0.642 4.000 3.358 SLICE_X180Y115 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[31]_srl32/CLK Low Pulse Width Slow SRLC32E/CLK n/a 0.642 4.000 3.358 SLICE_X180Y115 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK Low Pulse Width Slow SRLC32E/CLK n/a 0.642 4.000 3.358 SLICE_X180Y115 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLK Low Pulse Width Fast SRLC32E/CLK n/a 0.642 4.000 3.358 SLICE_X186Y105 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK High Pulse Width Fast PLLE2_ADV/CLKIN1 n/a 2.000 4.000 2.000 PLLE2_ADV_X0Y1 sys/clocks/PLLE2_BASE_inst/CLKIN1 High Pulse Width Slow PLLE2_ADV/CLKIN1 n/a 2.000 4.000 2.000 PLLE2_ADV_X0Y1 sys/clocks/PLLE2_BASE_inst/CLKIN1 High Pulse Width Fast SRLC32E/CLK n/a 0.642 4.000 3.358 SLICE_X186Y105 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK High Pulse Width Fast SRLC32E/CLK n/a 0.642 4.000 3.358 SLICE_X186Y105 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK High Pulse Width Fast SRLC32E/CLK n/a 0.642 4.000 3.358 SLICE_X186Y105 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK High Pulse Width Fast SRLC32E/CLK n/a 0.642 4.000 3.358 SLICE_X180Y115 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK High Pulse Width Fast SRLC32E/CLK n/a 0.642 4.000 3.358 SLICE_X180Y115 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[31]_srl32/CLK High Pulse Width Fast SRLC32E/CLK n/a 0.642 4.000 3.358 SLICE_X180Y115 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK High Pulse Width Fast SRLC32E/CLK n/a 0.642 4.000 3.358 SLICE_X180Y115 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLK High Pulse Width Slow SRLC32E/CLK n/a 0.642 4.000 3.358 SLICE_X180Y115 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK --------------------------------------------------------------------------------------------------- From Clock: clk125_ub To Clock: clk125_ub Setup : 0 Failing Endpoints, Worst Slack 2.313ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.070ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.358ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.313ns (required time - arrival time) Source: sys/clocks/rst_125_reg/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/ipb/udp_if/status_buffer/ipbus_in_reg[106]/R (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125_ub rise@8.000ns - clk125_ub rise@0.000ns) Data Path Delay: 5.294ns (logic 0.266ns (5.025%) route 5.028ns (94.975%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.044ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.003ns = ( 12.003 - 8.000 ) Source Clock Delay (SCD): 5.146ns Clock Pessimism Removal (CPR): 1.099ns Clock Uncertainty: 0.045ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.057ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.205 3.654 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.399 5.146 sys/clocks/PLLE2_BASE_inst_0 SLICE_X96Y115 FDRE r sys/clocks/rst_125_reg/C ------------------------------------------------------------------- ------------------- SLICE_X96Y115 FDRE (Prop_fdre_C_Q) 0.223 5.369 r sys/clocks/rst_125_reg/Q net (fo=1307, routed) 2.735 8.104 sys/ipb/udp_if/rx_transactor/rst_125mhz SLICE_X86Y101 LUT2 (Prop_lut2_I1_O) 0.043 8.147 r sys/ipb/udp_if/rx_transactor/ipbus_in[127]_i_1/O net (fo=128, routed) 2.293 10.439 sys/ipb/udp_if/status_buffer/ipbus_in_reg[0]_0 SLICE_X93Y109 FDRE r sys/ipb/udp_if/status_buffer/ipbus_in_reg[106]/R ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 12.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -3.847 8.575 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.078 10.653 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.267 12.003 sys/ipb/udp_if/status_buffer/history_reg[127]_0 SLICE_X93Y109 FDRE r sys/ipb/udp_if/status_buffer/ipbus_in_reg[106]/C clock pessimism 1.099 13.102 clock uncertainty -0.045 13.056 SLICE_X93Y109 FDRE (Setup_fdre_C_R) -0.304 12.752 sys/ipb/udp_if/status_buffer/ipbus_in_reg[106] ------------------------------------------------------------------- required time 12.752 arrival time -10.439 ------------------------------------------------------------------- slack 2.313 Slack (MET) : 2.313ns (required time - arrival time) Source: sys/clocks/rst_125_reg/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/ipb/udp_if/status_buffer/ipbus_in_reg[122]/R (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125_ub rise@8.000ns - clk125_ub rise@0.000ns) Data Path Delay: 5.294ns (logic 0.266ns (5.025%) route 5.028ns (94.975%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.044ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.003ns = ( 12.003 - 8.000 ) Source Clock Delay (SCD): 5.146ns Clock Pessimism Removal (CPR): 1.099ns Clock Uncertainty: 0.045ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.057ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.205 3.654 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.399 5.146 sys/clocks/PLLE2_BASE_inst_0 SLICE_X96Y115 FDRE r sys/clocks/rst_125_reg/C ------------------------------------------------------------------- ------------------- SLICE_X96Y115 FDRE (Prop_fdre_C_Q) 0.223 5.369 r sys/clocks/rst_125_reg/Q net (fo=1307, routed) 2.735 8.104 sys/ipb/udp_if/rx_transactor/rst_125mhz SLICE_X86Y101 LUT2 (Prop_lut2_I1_O) 0.043 8.147 r sys/ipb/udp_if/rx_transactor/ipbus_in[127]_i_1/O net (fo=128, routed) 2.293 10.439 sys/ipb/udp_if/status_buffer/ipbus_in_reg[0]_0 SLICE_X93Y109 FDRE r sys/ipb/udp_if/status_buffer/ipbus_in_reg[122]/R ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 12.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -3.847 8.575 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.078 10.653 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.267 12.003 sys/ipb/udp_if/status_buffer/history_reg[127]_0 SLICE_X93Y109 FDRE r sys/ipb/udp_if/status_buffer/ipbus_in_reg[122]/C clock pessimism 1.099 13.102 clock uncertainty -0.045 13.056 SLICE_X93Y109 FDRE (Setup_fdre_C_R) -0.304 12.752 sys/ipb/udp_if/status_buffer/ipbus_in_reg[122] ------------------------------------------------------------------- required time 12.752 arrival time -10.439 ------------------------------------------------------------------- slack 2.313 Slack (MET) : 2.313ns (required time - arrival time) Source: sys/clocks/rst_125_reg/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/ipb/udp_if/status_buffer/ipbus_in_reg[74]/R (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125_ub rise@8.000ns - clk125_ub rise@0.000ns) Data Path Delay: 5.294ns (logic 0.266ns (5.025%) route 5.028ns (94.975%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.044ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.003ns = ( 12.003 - 8.000 ) Source Clock Delay (SCD): 5.146ns Clock Pessimism Removal (CPR): 1.099ns Clock Uncertainty: 0.045ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.057ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.205 3.654 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.399 5.146 sys/clocks/PLLE2_BASE_inst_0 SLICE_X96Y115 FDRE r sys/clocks/rst_125_reg/C ------------------------------------------------------------------- ------------------- SLICE_X96Y115 FDRE (Prop_fdre_C_Q) 0.223 5.369 r sys/clocks/rst_125_reg/Q net (fo=1307, routed) 2.735 8.104 sys/ipb/udp_if/rx_transactor/rst_125mhz SLICE_X86Y101 LUT2 (Prop_lut2_I1_O) 0.043 8.147 r sys/ipb/udp_if/rx_transactor/ipbus_in[127]_i_1/O net (fo=128, routed) 2.293 10.439 sys/ipb/udp_if/status_buffer/ipbus_in_reg[0]_0 SLICE_X93Y109 FDRE r sys/ipb/udp_if/status_buffer/ipbus_in_reg[74]/R ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 12.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -3.847 8.575 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.078 10.653 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.267 12.003 sys/ipb/udp_if/status_buffer/history_reg[127]_0 SLICE_X93Y109 FDRE r sys/ipb/udp_if/status_buffer/ipbus_in_reg[74]/C clock pessimism 1.099 13.102 clock uncertainty -0.045 13.056 SLICE_X93Y109 FDRE (Setup_fdre_C_R) -0.304 12.752 sys/ipb/udp_if/status_buffer/ipbus_in_reg[74] ------------------------------------------------------------------- required time 12.752 arrival time -10.439 ------------------------------------------------------------------- slack 2.313 Slack (MET) : 2.313ns (required time - arrival time) Source: sys/clocks/rst_125_reg/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/ipb/udp_if/status_buffer/ipbus_in_reg[90]/R (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125_ub rise@8.000ns - clk125_ub rise@0.000ns) Data Path Delay: 5.294ns (logic 0.266ns (5.025%) route 5.028ns (94.975%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.044ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.003ns = ( 12.003 - 8.000 ) Source Clock Delay (SCD): 5.146ns Clock Pessimism Removal (CPR): 1.099ns Clock Uncertainty: 0.045ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.057ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.205 3.654 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.399 5.146 sys/clocks/PLLE2_BASE_inst_0 SLICE_X96Y115 FDRE r sys/clocks/rst_125_reg/C ------------------------------------------------------------------- ------------------- SLICE_X96Y115 FDRE (Prop_fdre_C_Q) 0.223 5.369 r sys/clocks/rst_125_reg/Q net (fo=1307, routed) 2.735 8.104 sys/ipb/udp_if/rx_transactor/rst_125mhz SLICE_X86Y101 LUT2 (Prop_lut2_I1_O) 0.043 8.147 r sys/ipb/udp_if/rx_transactor/ipbus_in[127]_i_1/O net (fo=128, routed) 2.293 10.439 sys/ipb/udp_if/status_buffer/ipbus_in_reg[0]_0 SLICE_X93Y109 FDRE r sys/ipb/udp_if/status_buffer/ipbus_in_reg[90]/R ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 12.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -3.847 8.575 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.078 10.653 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.267 12.003 sys/ipb/udp_if/status_buffer/history_reg[127]_0 SLICE_X93Y109 FDRE r sys/ipb/udp_if/status_buffer/ipbus_in_reg[90]/C clock pessimism 1.099 13.102 clock uncertainty -0.045 13.056 SLICE_X93Y109 FDRE (Setup_fdre_C_R) -0.304 12.752 sys/ipb/udp_if/status_buffer/ipbus_in_reg[90] ------------------------------------------------------------------- required time 12.752 arrival time -10.439 ------------------------------------------------------------------- slack 2.313 Slack (MET) : 2.313ns (required time - arrival time) Source: sys/clocks/rst_125_reg/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/ipb/udp_if/status_buffer/ipbus_in_reg[98]/R (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125_ub rise@8.000ns - clk125_ub rise@0.000ns) Data Path Delay: 5.294ns (logic 0.266ns (5.025%) route 5.028ns (94.975%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.044ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.003ns = ( 12.003 - 8.000 ) Source Clock Delay (SCD): 5.146ns Clock Pessimism Removal (CPR): 1.099ns Clock Uncertainty: 0.045ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.057ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.205 3.654 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.399 5.146 sys/clocks/PLLE2_BASE_inst_0 SLICE_X96Y115 FDRE r sys/clocks/rst_125_reg/C ------------------------------------------------------------------- ------------------- SLICE_X96Y115 FDRE (Prop_fdre_C_Q) 0.223 5.369 r sys/clocks/rst_125_reg/Q net (fo=1307, routed) 2.735 8.104 sys/ipb/udp_if/rx_transactor/rst_125mhz SLICE_X86Y101 LUT2 (Prop_lut2_I1_O) 0.043 8.147 r sys/ipb/udp_if/rx_transactor/ipbus_in[127]_i_1/O net (fo=128, routed) 2.293 10.439 sys/ipb/udp_if/status_buffer/ipbus_in_reg[0]_0 SLICE_X93Y109 FDRE r sys/ipb/udp_if/status_buffer/ipbus_in_reg[98]/R ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 12.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -3.847 8.575 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.078 10.653 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.267 12.003 sys/ipb/udp_if/status_buffer/history_reg[127]_0 SLICE_X93Y109 FDRE r sys/ipb/udp_if/status_buffer/ipbus_in_reg[98]/C clock pessimism 1.099 13.102 clock uncertainty -0.045 13.056 SLICE_X93Y109 FDRE (Setup_fdre_C_R) -0.304 12.752 sys/ipb/udp_if/status_buffer/ipbus_in_reg[98] ------------------------------------------------------------------- required time 12.752 arrival time -10.439 ------------------------------------------------------------------- slack 2.313 Slack (MET) : 2.434ns (required time - arrival time) Source: sys/clocks/rst_125_reg/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/ipb/udp_if/status_buffer/ipbus_in_reg[36]/R (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125_ub rise@8.000ns - clk125_ub rise@0.000ns) Data Path Delay: 5.089ns (logic 0.266ns (5.227%) route 4.823ns (94.773%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.128ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.992ns = ( 11.992 - 8.000 ) Source Clock Delay (SCD): 5.146ns Clock Pessimism Removal (CPR): 1.026ns Clock Uncertainty: 0.045ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.057ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.205 3.654 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.399 5.146 sys/clocks/PLLE2_BASE_inst_0 SLICE_X96Y115 FDRE r sys/clocks/rst_125_reg/C ------------------------------------------------------------------- ------------------- SLICE_X96Y115 FDRE (Prop_fdre_C_Q) 0.223 5.369 r sys/clocks/rst_125_reg/Q net (fo=1307, routed) 2.735 8.104 sys/ipb/udp_if/rx_transactor/rst_125mhz SLICE_X86Y101 LUT2 (Prop_lut2_I1_O) 0.043 8.147 r sys/ipb/udp_if/rx_transactor/ipbus_in[127]_i_1/O net (fo=128, routed) 2.088 10.234 sys/ipb/udp_if/status_buffer/ipbus_in_reg[0]_0 SLICE_X88Y110 FDRE r sys/ipb/udp_if/status_buffer/ipbus_in_reg[36]/R ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 12.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -3.847 8.575 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.078 10.653 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.256 11.992 sys/ipb/udp_if/status_buffer/history_reg[127]_0 SLICE_X88Y110 FDRE r sys/ipb/udp_if/status_buffer/ipbus_in_reg[36]/C clock pessimism 1.026 13.018 clock uncertainty -0.045 12.972 SLICE_X88Y110 FDRE (Setup_fdre_C_R) -0.304 12.668 sys/ipb/udp_if/status_buffer/ipbus_in_reg[36] ------------------------------------------------------------------- required time 12.668 arrival time -10.234 ------------------------------------------------------------------- slack 2.434 Slack (MET) : 2.434ns (required time - arrival time) Source: sys/clocks/rst_125_reg/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/ipb/udp_if/status_buffer/ipbus_in_reg[4]/R (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125_ub rise@8.000ns - clk125_ub rise@0.000ns) Data Path Delay: 5.089ns (logic 0.266ns (5.227%) route 4.823ns (94.773%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.128ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.992ns = ( 11.992 - 8.000 ) Source Clock Delay (SCD): 5.146ns Clock Pessimism Removal (CPR): 1.026ns Clock Uncertainty: 0.045ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.057ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.205 3.654 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.399 5.146 sys/clocks/PLLE2_BASE_inst_0 SLICE_X96Y115 FDRE r sys/clocks/rst_125_reg/C ------------------------------------------------------------------- ------------------- SLICE_X96Y115 FDRE (Prop_fdre_C_Q) 0.223 5.369 r sys/clocks/rst_125_reg/Q net (fo=1307, routed) 2.735 8.104 sys/ipb/udp_if/rx_transactor/rst_125mhz SLICE_X86Y101 LUT2 (Prop_lut2_I1_O) 0.043 8.147 r sys/ipb/udp_if/rx_transactor/ipbus_in[127]_i_1/O net (fo=128, routed) 2.088 10.234 sys/ipb/udp_if/status_buffer/ipbus_in_reg[0]_0 SLICE_X88Y110 FDRE r sys/ipb/udp_if/status_buffer/ipbus_in_reg[4]/R ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 12.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -3.847 8.575 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.078 10.653 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.256 11.992 sys/ipb/udp_if/status_buffer/history_reg[127]_0 SLICE_X88Y110 FDRE r sys/ipb/udp_if/status_buffer/ipbus_in_reg[4]/C clock pessimism 1.026 13.018 clock uncertainty -0.045 12.972 SLICE_X88Y110 FDRE (Setup_fdre_C_R) -0.304 12.668 sys/ipb/udp_if/status_buffer/ipbus_in_reg[4] ------------------------------------------------------------------- required time 12.668 arrival time -10.234 ------------------------------------------------------------------- slack 2.434 Slack (MET) : 2.434ns (required time - arrival time) Source: sys/clocks/rst_125_reg/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/ipb/udp_if/status_buffer/ipbus_in_reg[68]/R (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125_ub rise@8.000ns - clk125_ub rise@0.000ns) Data Path Delay: 5.089ns (logic 0.266ns (5.227%) route 4.823ns (94.773%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.128ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.992ns = ( 11.992 - 8.000 ) Source Clock Delay (SCD): 5.146ns Clock Pessimism Removal (CPR): 1.026ns Clock Uncertainty: 0.045ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.057ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.205 3.654 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.399 5.146 sys/clocks/PLLE2_BASE_inst_0 SLICE_X96Y115 FDRE r sys/clocks/rst_125_reg/C ------------------------------------------------------------------- ------------------- SLICE_X96Y115 FDRE (Prop_fdre_C_Q) 0.223 5.369 r sys/clocks/rst_125_reg/Q net (fo=1307, routed) 2.735 8.104 sys/ipb/udp_if/rx_transactor/rst_125mhz SLICE_X86Y101 LUT2 (Prop_lut2_I1_O) 0.043 8.147 r sys/ipb/udp_if/rx_transactor/ipbus_in[127]_i_1/O net (fo=128, routed) 2.088 10.234 sys/ipb/udp_if/status_buffer/ipbus_in_reg[0]_0 SLICE_X88Y110 FDRE r sys/ipb/udp_if/status_buffer/ipbus_in_reg[68]/R ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 12.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -3.847 8.575 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.078 10.653 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.256 11.992 sys/ipb/udp_if/status_buffer/history_reg[127]_0 SLICE_X88Y110 FDRE r sys/ipb/udp_if/status_buffer/ipbus_in_reg[68]/C clock pessimism 1.026 13.018 clock uncertainty -0.045 12.972 SLICE_X88Y110 FDRE (Setup_fdre_C_R) -0.304 12.668 sys/ipb/udp_if/status_buffer/ipbus_in_reg[68] ------------------------------------------------------------------- required time 12.668 arrival time -10.234 ------------------------------------------------------------------- slack 2.434 Slack (MET) : 2.434ns (required time - arrival time) Source: sys/clocks/rst_125_reg/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/ipb/udp_if/status_buffer/ipbus_in_reg[92]/R (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125_ub rise@8.000ns - clk125_ub rise@0.000ns) Data Path Delay: 5.089ns (logic 0.266ns (5.227%) route 4.823ns (94.773%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.128ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.992ns = ( 11.992 - 8.000 ) Source Clock Delay (SCD): 5.146ns Clock Pessimism Removal (CPR): 1.026ns Clock Uncertainty: 0.045ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.057ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.205 3.654 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.399 5.146 sys/clocks/PLLE2_BASE_inst_0 SLICE_X96Y115 FDRE r sys/clocks/rst_125_reg/C ------------------------------------------------------------------- ------------------- SLICE_X96Y115 FDRE (Prop_fdre_C_Q) 0.223 5.369 r sys/clocks/rst_125_reg/Q net (fo=1307, routed) 2.735 8.104 sys/ipb/udp_if/rx_transactor/rst_125mhz SLICE_X86Y101 LUT2 (Prop_lut2_I1_O) 0.043 8.147 r sys/ipb/udp_if/rx_transactor/ipbus_in[127]_i_1/O net (fo=128, routed) 2.088 10.234 sys/ipb/udp_if/status_buffer/ipbus_in_reg[0]_0 SLICE_X88Y110 FDRE r sys/ipb/udp_if/status_buffer/ipbus_in_reg[92]/R ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 12.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -3.847 8.575 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.078 10.653 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.256 11.992 sys/ipb/udp_if/status_buffer/history_reg[127]_0 SLICE_X88Y110 FDRE r sys/ipb/udp_if/status_buffer/ipbus_in_reg[92]/C clock pessimism 1.026 13.018 clock uncertainty -0.045 12.972 SLICE_X88Y110 FDRE (Setup_fdre_C_R) -0.304 12.668 sys/ipb/udp_if/status_buffer/ipbus_in_reg[92] ------------------------------------------------------------------- required time 12.668 arrival time -10.234 ------------------------------------------------------------------- slack 2.434 Slack (MET) : 2.436ns (required time - arrival time) Source: sys/clocks/rst_125_reg/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/ipb/udp_if/status_buffer/ipbus_in_reg[116]/R (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125_ub rise@8.000ns - clk125_ub rise@0.000ns) Data Path Delay: 5.087ns (logic 0.266ns (5.229%) route 4.821ns (94.771%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.128ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.992ns = ( 11.992 - 8.000 ) Source Clock Delay (SCD): 5.146ns Clock Pessimism Removal (CPR): 1.026ns Clock Uncertainty: 0.045ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.057ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.205 3.654 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.399 5.146 sys/clocks/PLLE2_BASE_inst_0 SLICE_X96Y115 FDRE r sys/clocks/rst_125_reg/C ------------------------------------------------------------------- ------------------- SLICE_X96Y115 FDRE (Prop_fdre_C_Q) 0.223 5.369 r sys/clocks/rst_125_reg/Q net (fo=1307, routed) 2.735 8.104 sys/ipb/udp_if/rx_transactor/rst_125mhz SLICE_X86Y101 LUT2 (Prop_lut2_I1_O) 0.043 8.147 r sys/ipb/udp_if/rx_transactor/ipbus_in[127]_i_1/O net (fo=128, routed) 2.085 10.232 sys/ipb/udp_if/status_buffer/ipbus_in_reg[0]_0 SLICE_X89Y110 FDRE r sys/ipb/udp_if/status_buffer/ipbus_in_reg[116]/R ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 12.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -3.847 8.575 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.078 10.653 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.256 11.992 sys/ipb/udp_if/status_buffer/history_reg[127]_0 SLICE_X89Y110 FDRE r sys/ipb/udp_if/status_buffer/ipbus_in_reg[116]/C clock pessimism 1.026 13.018 clock uncertainty -0.045 12.972 SLICE_X89Y110 FDRE (Setup_fdre_C_R) -0.304 12.668 sys/ipb/udp_if/status_buffer/ipbus_in_reg[116] ------------------------------------------------------------------- required time 12.668 arrival time -10.232 ------------------------------------------------------------------- slack 2.436 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.070ns (arrival time - required time) Source: sys/uc_if/uc_pipe_if/r_addr_pipe_reg[7]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/uc_if/uc_pipe_if/ram_ipbus_to_pipe/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/ADDRBWRADDR[11] (rising edge-triggered cell RAMB36E1 clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125_ub rise@0.000ns - clk125_ub rise@0.000ns) Data Path Delay: 0.260ns (logic 0.091ns (34.956%) route 0.169ns (65.044%)) Logic Levels: 0 Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.222ns Source Clock Delay (SCD): 1.637ns Clock Pessimism Removal (CPR): 0.542ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.004 1.017 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.594 1.637 sys/uc_if/uc_pipe_if/r_addr_pipe_reg[9]_0 SLICE_X85Y140 FDRE r sys/uc_if/uc_pipe_if/r_addr_pipe_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X85Y140 FDRE (Prop_fdre_C_Q) 0.091 1.728 r sys/uc_if/uc_pipe_if/r_addr_pipe_reg[7]/Q net (fo=5, routed) 0.169 1.897 sys/uc_if/uc_pipe_if/ram_ipbus_to_pipe/addrb[7] RAMB36_X5Y28 RAMB36E1 r sys/uc_if/uc_pipe_if/ram_ipbus_to_pipe/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/ADDRBWRADDR[11] ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.073 1.348 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.845 2.222 sys/uc_if/uc_pipe_if/ram_ipbus_to_pipe/clkb RAMB36_X5Y28 RAMB36E1 r sys/uc_if/uc_pipe_if/ram_ipbus_to_pipe/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKBWRCLK clock pessimism -0.542 1.680 RAMB36_X5Y28 RAMB36E1 (Hold_ramb36e1_CLKBWRCLK_ADDRBWRADDR[11]) 0.147 1.827 sys/uc_if/uc_pipe_if/ram_ipbus_to_pipe/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ------------------------------------------------------------------- required time -1.827 arrival time 1.897 ------------------------------------------------------------------- slack 0.070 Slack (MET) : 0.072ns (arrival time - required time) Source: sys/ipb/udp_if/status_buffer/history_reg[80]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/ipb/udp_if/status_buffer/history_reg[88]/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125_ub rise@0.000ns - clk125_ub rise@0.000ns) Data Path Delay: 0.423ns (logic 0.128ns (30.226%) route 0.295ns (69.774%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.264ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.262ns Source Clock Delay (SCD): 1.635ns Clock Pessimism Removal (CPR): 0.363ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.004 1.017 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.592 1.635 sys/ipb/udp_if/status_buffer/history_reg[127]_0 SLICE_X89Y101 FDRE r sys/ipb/udp_if/status_buffer/history_reg[80]/C ------------------------------------------------------------------- ------------------- SLICE_X89Y101 FDRE (Prop_fdre_C_Q) 0.100 1.735 r sys/ipb/udp_if/status_buffer/history_reg[80]/Q net (fo=2, routed) 0.295 2.030 sys/ipb/udp_if/status_buffer/history[80] SLICE_X90Y99 LUT5 (Prop_lut5_I4_O) 0.028 2.058 r sys/ipb/udp_if/status_buffer/history[88]_i_1/O net (fo=1, routed) 0.000 2.058 sys/ipb/udp_if/status_buffer/history[88]_i_1_n_0 SLICE_X90Y99 FDRE r sys/ipb/udp_if/status_buffer/history_reg[88]/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.073 1.348 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.884 2.262 sys/ipb/udp_if/status_buffer/history_reg[127]_0 SLICE_X90Y99 FDRE r sys/ipb/udp_if/status_buffer/history_reg[88]/C clock pessimism -0.363 1.899 SLICE_X90Y99 FDRE (Hold_fdre_C_D) 0.087 1.986 sys/ipb/udp_if/status_buffer/history_reg[88] ------------------------------------------------------------------- required time -1.986 arrival time 2.058 ------------------------------------------------------------------- slack 0.072 Slack (MET) : 0.076ns (arrival time - required time) Source: sys/ipb/udp_if/payload/addr_int_reg[8]__0/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/ipb/udp_if/ipbus_rx_ram/ram1_reg_0/ADDRARDADDR[8] (rising edge-triggered cell RAMB36E1 clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125_ub rise@0.000ns - clk125_ub rise@0.000ns) Data Path Delay: 0.477ns (logic 0.100ns (20.961%) route 0.377ns (79.039%)) Logic Levels: 0 Clock Path Skew: 0.219ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.218ns Source Clock Delay (SCD): 1.637ns Clock Pessimism Removal (CPR): 0.363ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.004 1.017 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.594 1.637 sys/ipb/udp_if/payload/int_valid_int_reg_0 SLICE_X95Y106 FDRE r sys/ipb/udp_if/payload/addr_int_reg[8]__0/C ------------------------------------------------------------------- ------------------- SLICE_X95Y106 FDRE (Prop_fdre_C_Q) 0.100 1.737 r sys/ipb/udp_if/payload/addr_int_reg[8]__0/Q net (fo=8, routed) 0.377 2.114 sys/ipb/udp_if/ipbus_rx_ram/rx_full_addra[6] RAMB36_X5Y22 RAMB36E1 r sys/ipb/udp_if/ipbus_rx_ram/ram1_reg_0/ADDRARDADDR[8] ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.073 1.348 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.841 2.218 sys/ipb/udp_if/ipbus_rx_ram/ram3_reg_0_0 RAMB36_X5Y22 RAMB36E1 r sys/ipb/udp_if/ipbus_rx_ram/ram1_reg_0/CLKARDCLK clock pessimism -0.363 1.855 RAMB36_X5Y22 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[8]) 0.183 2.038 sys/ipb/udp_if/ipbus_rx_ram/ram1_reg_0 ------------------------------------------------------------------- required time -2.038 arrival time 2.114 ------------------------------------------------------------------- slack 0.076 Slack (MET) : 0.081ns (arrival time - required time) Source: sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[44]__1/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[92]__1_srl6___sys_ipb_udp_if_rx_packet_parser_pkt_data_reg_r_61/D (rising edge-triggered cell SRL16E clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125_ub rise@0.000ns - clk125_ub rise@0.000ns) Data Path Delay: 0.243ns (logic 0.100ns (41.192%) route 0.143ns (58.808%)) Logic Levels: 0 Clock Path Skew: 0.008ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.215ns Source Clock Delay (SCD): 1.664ns Clock Pessimism Removal (CPR): 0.543ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.004 1.017 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.621 1.664 sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[83]__1_0 SLICE_X60Y128 FDRE r sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[44]__1/C ------------------------------------------------------------------- ------------------- SLICE_X60Y128 FDRE (Prop_fdre_C_Q) 0.100 1.764 r sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[44]__1/Q net (fo=1, routed) 0.143 1.906 sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[44]__1_n_0 SLICE_X58Y125 SRL16E r sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[92]__1_srl6___sys_ipb_udp_if_rx_packet_parser_pkt_data_reg_r_61/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.073 1.348 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.837 2.215 sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[83]__1_0 SLICE_X58Y125 SRL16E r sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[92]__1_srl6___sys_ipb_udp_if_rx_packet_parser_pkt_data_reg_r_61/CLK clock pessimism -0.543 1.672 SLICE_X58Y125 SRL16E (Hold_srl16e_CLK_D) 0.154 1.826 sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[92]__1_srl6___sys_ipb_udp_if_rx_packet_parser_pkt_data_reg_r_61 ------------------------------------------------------------------- required time -1.826 arrival time 1.906 ------------------------------------------------------------------- slack 0.081 Slack (MET) : 0.081ns (arrival time - required time) Source: sys/uc_if/uc_trans/addr_reg[8]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/uc_if/uc_trans/ram_in/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/ADDRARDADDR[12] (rising edge-triggered cell RAMB36E1 clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125_ub rise@0.000ns - clk125_ub rise@0.000ns) Data Path Delay: 0.503ns (logic 0.100ns (19.887%) route 0.403ns (80.113%)) Logic Levels: 0 Clock Path Skew: 0.239ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.225ns Source Clock Delay (SCD): 1.624ns Clock Pessimism Removal (CPR): 0.363ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.004 1.017 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.581 1.624 sys/uc_if/uc_trans/addr_reg[9]_0 SLICE_X87Y128 FDRE r sys/uc_if/uc_trans/addr_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X87Y128 FDRE (Prop_fdre_C_Q) 0.100 1.724 r sys/uc_if/uc_trans/addr_reg[8]/Q net (fo=4, routed) 0.403 2.126 sys/uc_if/uc_trans/ram_in/addra[8] RAMB36_X6Y26 RAMB36E1 r sys/uc_if/uc_trans/ram_in/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/ADDRARDADDR[12] ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.073 1.348 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.848 2.225 sys/uc_if/uc_trans/ram_in/clka RAMB36_X6Y26 RAMB36E1 r sys/uc_if/uc_trans/ram_in/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK clock pessimism -0.363 1.862 RAMB36_X6Y26 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[12]) 0.183 2.045 sys/uc_if/uc_trans/ram_in/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ------------------------------------------------------------------- required time -2.045 arrival time 2.126 ------------------------------------------------------------------- slack 0.081 Slack (MET) : 0.082ns (arrival time - required time) Source: sys/ipb/udp_if/status/shift_buf_reg[50]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/ipb/udp_if/status/shift_buf_reg[58]/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125_ub rise@0.000ns - clk125_ub rise@0.000ns) Data Path Delay: 0.367ns (logic 0.128ns (34.882%) route 0.239ns (65.118%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.198ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.193ns Source Clock Delay (SCD): 1.632ns Clock Pessimism Removal (CPR): 0.363ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.004 1.017 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.589 1.632 sys/ipb/udp_if/status/status_we_reg_0 SLICE_X91Y107 FDRE r sys/ipb/udp_if/status/shift_buf_reg[50]/C ------------------------------------------------------------------- ------------------- SLICE_X91Y107 FDRE (Prop_fdre_C_Q) 0.100 1.732 r sys/ipb/udp_if/status/shift_buf_reg[50]/Q net (fo=2, routed) 0.239 1.971 sys/ipb/udp_if/status/shift_buf[50] SLICE_X94Y107 LUT6 (Prop_lut6_I2_O) 0.028 1.999 r sys/ipb/udp_if/status/shift_buf[58]_i_1/O net (fo=1, routed) 0.000 1.999 sys/ipb/udp_if/status/p_1_in[58] SLICE_X94Y107 FDRE r sys/ipb/udp_if/status/shift_buf_reg[58]/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.073 1.348 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.815 2.193 sys/ipb/udp_if/status/status_we_reg_0 SLICE_X94Y107 FDRE r sys/ipb/udp_if/status/shift_buf_reg[58]/C clock pessimism -0.363 1.830 SLICE_X94Y107 FDRE (Hold_fdre_C_D) 0.087 1.917 sys/ipb/udp_if/status/shift_buf_reg[58] ------------------------------------------------------------------- required time -1.917 arrival time 1.999 ------------------------------------------------------------------- slack 0.082 Slack (MET) : 0.082ns (arrival time - required time) Source: sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg[7]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg[7]_srl5/D (rising edge-triggered cell SRL16E clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125_ub rise@0.000ns - clk125_ub rise@0.000ns) Data Path Delay: 0.250ns (logic 0.100ns (39.947%) route 0.150ns (60.053%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.290ns Source Clock Delay (SCD): 1.731ns Clock Pessimism Removal (CPR): 0.545ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.004 1.017 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.688 1.731 sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/userclk2 SLICE_X185Y111 FDRE r sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X185Y111 FDRE (Prop_fdre_C_Q) 0.100 1.831 r sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg[7]/Q net (fo=9, routed) 0.150 1.981 sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/Q[7] SLICE_X186Y111 SRL16E r sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg[7]_srl5/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.073 1.348 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.912 2.290 sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/userclk2 SLICE_X186Y111 SRL16E r sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg[7]_srl5/CLK clock pessimism -0.545 1.745 SLICE_X186Y111 SRL16E (Hold_srl16e_CLK_D) 0.154 1.899 sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg[7]_srl5 ------------------------------------------------------------------- required time -1.899 arrival time 1.981 ------------------------------------------------------------------- slack 0.082 Slack (MET) : 0.083ns (arrival time - required time) Source: sys/uc_if/uc_pipe_if/r_addr_pipe_reg[4]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/uc_if/uc_pipe_if/ram_ipbus_to_pipe/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/ADDRBWRADDR[8] (rising edge-triggered cell RAMB36E1 clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125_ub rise@0.000ns - clk125_ub rise@0.000ns) Data Path Delay: 0.271ns (logic 0.091ns (33.537%) route 0.180ns (66.463%)) Logic Levels: 0 Clock Path Skew: 0.044ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.222ns Source Clock Delay (SCD): 1.637ns Clock Pessimism Removal (CPR): 0.542ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.004 1.017 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.594 1.637 sys/uc_if/uc_pipe_if/r_addr_pipe_reg[9]_0 SLICE_X85Y140 FDRE r sys/uc_if/uc_pipe_if/r_addr_pipe_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X85Y140 FDRE (Prop_fdre_C_Q) 0.091 1.728 r sys/uc_if/uc_pipe_if/r_addr_pipe_reg[4]/Q net (fo=5, routed) 0.180 1.908 sys/uc_if/uc_pipe_if/ram_ipbus_to_pipe/addrb[4] RAMB36_X5Y28 RAMB36E1 r sys/uc_if/uc_pipe_if/ram_ipbus_to_pipe/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/ADDRBWRADDR[8] ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.073 1.348 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.845 2.222 sys/uc_if/uc_pipe_if/ram_ipbus_to_pipe/clkb RAMB36_X5Y28 RAMB36E1 r sys/uc_if/uc_pipe_if/ram_ipbus_to_pipe/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKBWRCLK clock pessimism -0.542 1.680 RAMB36_X5Y28 RAMB36E1 (Hold_ramb36e1_CLKBWRCLK_ADDRBWRADDR[8]) 0.145 1.825 sys/uc_if/uc_pipe_if/ram_ipbus_to_pipe/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ------------------------------------------------------------------- required time -1.825 arrival time 1.908 ------------------------------------------------------------------- slack 0.083 Slack (MET) : 0.084ns (arrival time - required time) Source: sys/ipb/udp_if/rx_packet_parser/pkt_mask_reg[7]__2/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/ipb/udp_if/rx_packet_parser/pkt_mask_reg[39]_srl32____sys_ipb_udp_if_rx_packet_parser_pkt_mask_reg_s_30/D (rising edge-triggered cell SRLC32E clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125_ub rise@0.000ns - clk125_ub rise@0.000ns) Data Path Delay: 0.195ns (logic 0.100ns (51.316%) route 0.095ns (48.684%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.213ns Source Clock Delay (SCD): 1.658ns Clock Pessimism Removal (CPR): 0.543ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.004 1.017 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.615 1.658 sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[83]__1_0 SLICE_X67Y124 FDRE r sys/ipb/udp_if/rx_packet_parser/pkt_mask_reg[7]__2/C ------------------------------------------------------------------- ------------------- SLICE_X67Y124 FDRE (Prop_fdre_C_Q) 0.100 1.758 r sys/ipb/udp_if/rx_packet_parser/pkt_mask_reg[7]__2/Q net (fo=1, routed) 0.095 1.852 sys/ipb/udp_if/rx_packet_parser/pkt_mask_reg[7]__2_n_0 SLICE_X66Y123 SRLC32E r sys/ipb/udp_if/rx_packet_parser/pkt_mask_reg[39]_srl32____sys_ipb_udp_if_rx_packet_parser_pkt_mask_reg_s_30/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.073 1.348 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.835 2.213 sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[83]__1_0 SLICE_X66Y123 SRLC32E r sys/ipb/udp_if/rx_packet_parser/pkt_mask_reg[39]_srl32____sys_ipb_udp_if_rx_packet_parser_pkt_mask_reg_s_30/CLK clock pessimism -0.543 1.670 SLICE_X66Y123 SRLC32E (Hold_srlc32e_CLK_D) 0.099 1.769 sys/ipb/udp_if/rx_packet_parser/pkt_mask_reg[39]_srl32____sys_ipb_udp_if_rx_packet_parser_pkt_mask_reg_s_30 ------------------------------------------------------------------- required time -1.769 arrival time 1.852 ------------------------------------------------------------------- slack 0.084 Slack (MET) : 0.085ns (arrival time - required time) Source: sys/ipb/udp_if/status_buffer/history_reg[37]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/ipb/udp_if/status_buffer/history_reg[45]/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125_ub rise@0.000ns - clk125_ub rise@0.000ns) Data Path Delay: 0.411ns (logic 0.128ns (31.117%) route 0.283ns (68.883%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.266ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.264ns Source Clock Delay (SCD): 1.635ns Clock Pessimism Removal (CPR): 0.363ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.004 1.017 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.592 1.635 sys/ipb/udp_if/status_buffer/history_reg[127]_0 SLICE_X88Y101 FDRE r sys/ipb/udp_if/status_buffer/history_reg[37]/C ------------------------------------------------------------------- ------------------- SLICE_X88Y101 FDRE (Prop_fdre_C_Q) 0.100 1.735 r sys/ipb/udp_if/status_buffer/history_reg[37]/Q net (fo=2, routed) 0.283 2.018 sys/ipb/udp_if/status_buffer/history[37] SLICE_X88Y98 LUT5 (Prop_lut5_I4_O) 0.028 2.046 r sys/ipb/udp_if/status_buffer/history[45]_i_1/O net (fo=1, routed) 0.000 2.046 sys/ipb/udp_if/status_buffer/history[45]_i_1_n_0 SLICE_X88Y98 FDRE r sys/ipb/udp_if/status_buffer/history_reg[45]/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.073 1.348 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.886 2.264 sys/ipb/udp_if/status_buffer/history_reg[127]_0 SLICE_X88Y98 FDRE r sys/ipb/udp_if/status_buffer/history_reg[45]/C clock pessimism -0.363 1.901 SLICE_X88Y98 FDRE (Hold_fdre_C_D) 0.060 1.961 sys/ipb/udp_if/status_buffer/history_reg[45] ------------------------------------------------------------------- required time -1.961 arrival time 2.046 ------------------------------------------------------------------- slack 0.085 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk125_ub Waveform(ns): { 0.000 4.000 } Period(ns): 8.000 Sources: { sys/clocks/PLLE2_BASE_inst/CLKFBOUT } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a RAMB36E1/CLKARDCLK n/a 1.839 8.000 6.161 RAMB36_X4Y24 sys/ipb/udp_if/internal_ram/ram_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKBWRCLK n/a 1.839 8.000 6.161 RAMB36_X4Y24 sys/ipb/udp_if/internal_ram/ram_reg/CLKBWRCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 1.839 8.000 6.161 RAMB36_X5Y22 sys/ipb/udp_if/ipbus_rx_ram/ram1_reg_0/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 1.839 8.000 6.161 RAMB36_X5Y21 sys/ipb/udp_if/ipbus_rx_ram/ram1_reg_1/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 1.839 8.000 6.161 RAMB36_X4Y22 sys/ipb/udp_if/ipbus_rx_ram/ram2_reg_0/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 1.839 8.000 6.161 RAMB36_X5Y23 sys/ipb/udp_if/ipbus_rx_ram/ram2_reg_1/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 1.839 8.000 6.161 RAMB36_X5Y19 sys/ipb/udp_if/ipbus_rx_ram/ram3_reg_0/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 1.839 8.000 6.161 RAMB36_X4Y23 sys/ipb/udp_if/ipbus_rx_ram/ram3_reg_1/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 1.839 8.000 6.161 RAMB36_X6Y20 sys/ipb/udp_if/ipbus_rx_ram/ram4_reg_0/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 1.839 8.000 6.161 RAMB36_X5Y20 sys/ipb/udp_if/ipbus_rx_ram/ram4_reg_1/CLKARDCLK Max Period n/a PLLE2_ADV/CLKFBIN n/a 52.633 8.000 44.633 PLLE2_ADV_X0Y1 sys/clocks/PLLE2_BASE_inst/CLKFBIN Max Period n/a PLLE2_ADV/CLKFBOUT n/a 160.000 8.000 152.000 PLLE2_ADV_X0Y1 sys/clocks/PLLE2_BASE_inst/CLKFBOUT Low Pulse Width Slow SRL16E/CLK n/a 0.642 4.000 3.358 SLICE_X102Y111 sys/eth/mac/i_mac/g_emacclientrxdp[0].SRL16E_inst/CLK Low Pulse Width Slow SRL16E/CLK n/a 0.642 4.000 3.358 SLICE_X102Y111 sys/eth/mac/i_mac/g_emacclientrxdp[1].SRL16E_inst/CLK Low Pulse Width Slow SRL16E/CLK n/a 0.642 4.000 3.358 SLICE_X102Y111 sys/eth/mac/i_mac/g_emacclientrxdp[2].SRL16E_inst/CLK Low Pulse Width Slow SRL16E/CLK n/a 0.642 4.000 3.358 SLICE_X102Y111 sys/eth/mac/i_mac/g_emacclientrxdp[3].SRL16E_inst/CLK Low Pulse Width Slow SRL16E/CLK n/a 0.642 4.000 3.358 SLICE_X102Y111 sys/eth/mac/i_mac/g_emacclientrxdp[4].SRL16E_inst/CLK Low Pulse Width Slow SRL16E/CLK n/a 0.642 4.000 3.358 SLICE_X102Y111 sys/eth/mac/i_mac/g_emacclientrxdp[5].SRL16E_inst/CLK Low Pulse Width Slow SRL16E/CLK n/a 0.642 4.000 3.358 SLICE_X102Y111 sys/eth/mac/i_mac/g_emacclientrxdp[6].SRL16E_inst/CLK Low Pulse Width Slow SRL16E/CLK n/a 0.642 4.000 3.358 SLICE_X102Y111 sys/eth/mac/i_mac/g_emacclientrxdp[7].SRL16E_inst/CLK Low Pulse Width Slow SRL16E/CLK n/a 0.642 4.000 3.358 SLICE_X186Y111 sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg[0]_srl5/CLK Low Pulse Width Slow SRL16E/CLK n/a 0.642 4.000 3.358 SLICE_X186Y111 sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg[1]_srl5/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 4.000 3.358 SLICE_X2Y160 sys/clocks/clkdiv/reset_gen/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 4.000 3.358 SLICE_X102Y111 sys/eth/mac/i_mac/g_emacclientrxdp[0].SRL16E_inst/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 4.000 3.358 SLICE_X102Y111 sys/eth/mac/i_mac/g_emacclientrxdp[1].SRL16E_inst/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 4.000 3.358 SLICE_X102Y111 sys/eth/mac/i_mac/g_emacclientrxdp[2].SRL16E_inst/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 4.000 3.358 SLICE_X102Y111 sys/eth/mac/i_mac/g_emacclientrxdp[3].SRL16E_inst/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 4.000 3.358 SLICE_X102Y111 sys/eth/mac/i_mac/g_emacclientrxdp[4].SRL16E_inst/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 4.000 3.358 SLICE_X102Y111 sys/eth/mac/i_mac/g_emacclientrxdp[5].SRL16E_inst/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 4.000 3.358 SLICE_X102Y111 sys/eth/mac/i_mac/g_emacclientrxdp[6].SRL16E_inst/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 4.000 3.358 SLICE_X102Y111 sys/eth/mac/i_mac/g_emacclientrxdp[7].SRL16E_inst/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 4.000 3.358 SLICE_X174Y112 sys/eth/mac/i_mac/i_ce_rx_crc_dl/CLK --------------------------------------------------------------------------------------------------- From Clock: clk62_5_ub To Clock: clk62_5_ub Setup : 0 Failing Endpoints, Worst Slack 13.466ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.151ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 7.600ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 13.466ns (required time - arrival time) Source: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/C (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]/CE (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 16.000ns (clk62_5_ub rise@16.000ns - clk62_5_ub rise@0.000ns) Data Path Delay: 2.294ns (logic 0.388ns (16.916%) route 1.906ns (83.085%)) Logic Levels: 3 (LUT2=1 LUT4=1 LUT6=1) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.144ns = ( 20.144 - 16.000 ) Source Clock Delay (SCD): 5.291ns Clock Pessimism Removal (CPR): 1.147ns Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 2.205 3.654 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.544 5.291 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk SLICE_X182Y115 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X182Y115 FDRE (Prop_fdre_C_Q) 0.259 5.550 f sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/Q net (fo=2, routed) 0.454 6.004 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2] SLICE_X183Y117 LUT4 (Prop_lut4_I0_O) 0.043 6.047 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7/O net (fo=1, routed) 0.355 6.402 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7_n_0 SLICE_X183Y117 LUT6 (Prop_lut6_I1_O) 0.043 6.445 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/O net (fo=2, routed) 0.612 7.057 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4_n_0 SLICE_X185Y118 LUT2 (Prop_lut2_I0_O) 0.043 7.100 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/O net (fo=17, routed) 0.485 7.584 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2_n_0 SLICE_X182Y115 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 16.000 16.000 r AD6 0.000 16.000 r osc125_a_p (IN) net (fo=0) 0.000 16.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 16.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 16.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 17.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 18.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 18.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 20.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -3.847 16.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 2.078 18.653 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.083 18.736 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.408 20.144 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk SLICE_X182Y115 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]/C clock pessimism 1.147 21.291 clock uncertainty -0.063 21.228 SLICE_X182Y115 FDRE (Setup_fdre_C_CE) -0.178 21.050 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0] ------------------------------------------------------------------- required time 21.050 arrival time -7.584 ------------------------------------------------------------------- slack 13.466 Slack (MET) : 13.466ns (required time - arrival time) Source: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/C (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[1]/CE (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 16.000ns (clk62_5_ub rise@16.000ns - clk62_5_ub rise@0.000ns) Data Path Delay: 2.294ns (logic 0.388ns (16.916%) route 1.906ns (83.085%)) Logic Levels: 3 (LUT2=1 LUT4=1 LUT6=1) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.144ns = ( 20.144 - 16.000 ) Source Clock Delay (SCD): 5.291ns Clock Pessimism Removal (CPR): 1.147ns Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 2.205 3.654 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.544 5.291 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk SLICE_X182Y115 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X182Y115 FDRE (Prop_fdre_C_Q) 0.259 5.550 f sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/Q net (fo=2, routed) 0.454 6.004 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2] SLICE_X183Y117 LUT4 (Prop_lut4_I0_O) 0.043 6.047 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7/O net (fo=1, routed) 0.355 6.402 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7_n_0 SLICE_X183Y117 LUT6 (Prop_lut6_I1_O) 0.043 6.445 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/O net (fo=2, routed) 0.612 7.057 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4_n_0 SLICE_X185Y118 LUT2 (Prop_lut2_I0_O) 0.043 7.100 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/O net (fo=17, routed) 0.485 7.584 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2_n_0 SLICE_X182Y115 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 16.000 16.000 r AD6 0.000 16.000 r osc125_a_p (IN) net (fo=0) 0.000 16.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 16.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 16.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 17.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 18.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 18.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 20.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -3.847 16.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 2.078 18.653 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.083 18.736 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.408 20.144 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk SLICE_X182Y115 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[1]/C clock pessimism 1.147 21.291 clock uncertainty -0.063 21.228 SLICE_X182Y115 FDRE (Setup_fdre_C_CE) -0.178 21.050 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[1] ------------------------------------------------------------------- required time 21.050 arrival time -7.584 ------------------------------------------------------------------- slack 13.466 Slack (MET) : 13.466ns (required time - arrival time) Source: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/C (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/CE (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 16.000ns (clk62_5_ub rise@16.000ns - clk62_5_ub rise@0.000ns) Data Path Delay: 2.294ns (logic 0.388ns (16.916%) route 1.906ns (83.085%)) Logic Levels: 3 (LUT2=1 LUT4=1 LUT6=1) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.144ns = ( 20.144 - 16.000 ) Source Clock Delay (SCD): 5.291ns Clock Pessimism Removal (CPR): 1.147ns Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 2.205 3.654 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.544 5.291 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk SLICE_X182Y115 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X182Y115 FDRE (Prop_fdre_C_Q) 0.259 5.550 f sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/Q net (fo=2, routed) 0.454 6.004 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2] SLICE_X183Y117 LUT4 (Prop_lut4_I0_O) 0.043 6.047 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7/O net (fo=1, routed) 0.355 6.402 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7_n_0 SLICE_X183Y117 LUT6 (Prop_lut6_I1_O) 0.043 6.445 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/O net (fo=2, routed) 0.612 7.057 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4_n_0 SLICE_X185Y118 LUT2 (Prop_lut2_I0_O) 0.043 7.100 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/O net (fo=17, routed) 0.485 7.584 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2_n_0 SLICE_X182Y115 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 16.000 16.000 r AD6 0.000 16.000 r osc125_a_p (IN) net (fo=0) 0.000 16.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 16.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 16.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 17.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 18.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 18.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 20.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -3.847 16.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 2.078 18.653 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.083 18.736 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.408 20.144 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk SLICE_X182Y115 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/C clock pessimism 1.147 21.291 clock uncertainty -0.063 21.228 SLICE_X182Y115 FDRE (Setup_fdre_C_CE) -0.178 21.050 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2] ------------------------------------------------------------------- required time 21.050 arrival time -7.584 ------------------------------------------------------------------- slack 13.466 Slack (MET) : 13.466ns (required time - arrival time) Source: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/C (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[3]/CE (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 16.000ns (clk62_5_ub rise@16.000ns - clk62_5_ub rise@0.000ns) Data Path Delay: 2.294ns (logic 0.388ns (16.916%) route 1.906ns (83.085%)) Logic Levels: 3 (LUT2=1 LUT4=1 LUT6=1) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.144ns = ( 20.144 - 16.000 ) Source Clock Delay (SCD): 5.291ns Clock Pessimism Removal (CPR): 1.147ns Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 2.205 3.654 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.544 5.291 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk SLICE_X182Y115 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X182Y115 FDRE (Prop_fdre_C_Q) 0.259 5.550 f sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/Q net (fo=2, routed) 0.454 6.004 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2] SLICE_X183Y117 LUT4 (Prop_lut4_I0_O) 0.043 6.047 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7/O net (fo=1, routed) 0.355 6.402 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7_n_0 SLICE_X183Y117 LUT6 (Prop_lut6_I1_O) 0.043 6.445 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/O net (fo=2, routed) 0.612 7.057 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4_n_0 SLICE_X185Y118 LUT2 (Prop_lut2_I0_O) 0.043 7.100 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/O net (fo=17, routed) 0.485 7.584 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2_n_0 SLICE_X182Y115 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 16.000 16.000 r AD6 0.000 16.000 r osc125_a_p (IN) net (fo=0) 0.000 16.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 16.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 16.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 17.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 18.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 18.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 20.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -3.847 16.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 2.078 18.653 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.083 18.736 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.408 20.144 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk SLICE_X182Y115 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[3]/C clock pessimism 1.147 21.291 clock uncertainty -0.063 21.228 SLICE_X182Y115 FDRE (Setup_fdre_C_CE) -0.178 21.050 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[3] ------------------------------------------------------------------- required time 21.050 arrival time -7.584 ------------------------------------------------------------------- slack 13.466 Slack (MET) : 13.523ns (required time - arrival time) Source: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/C (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[4]/CE (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 16.000ns (clk62_5_ub rise@16.000ns - clk62_5_ub rise@0.000ns) Data Path Delay: 2.213ns (logic 0.388ns (17.534%) route 1.825ns (82.466%)) Logic Levels: 3 (LUT2=1 LUT4=1 LUT6=1) Clock Path Skew: -0.024ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.143ns = ( 20.143 - 16.000 ) Source Clock Delay (SCD): 5.291ns Clock Pessimism Removal (CPR): 1.124ns Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 2.205 3.654 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.544 5.291 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk SLICE_X182Y115 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X182Y115 FDRE (Prop_fdre_C_Q) 0.259 5.550 f sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/Q net (fo=2, routed) 0.454 6.004 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2] SLICE_X183Y117 LUT4 (Prop_lut4_I0_O) 0.043 6.047 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7/O net (fo=1, routed) 0.355 6.402 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7_n_0 SLICE_X183Y117 LUT6 (Prop_lut6_I1_O) 0.043 6.445 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/O net (fo=2, routed) 0.612 7.057 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4_n_0 SLICE_X185Y118 LUT2 (Prop_lut2_I0_O) 0.043 7.100 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/O net (fo=17, routed) 0.404 7.503 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2_n_0 SLICE_X182Y116 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 16.000 16.000 r AD6 0.000 16.000 r osc125_a_p (IN) net (fo=0) 0.000 16.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 16.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 16.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 17.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 18.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 18.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 20.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -3.847 16.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 2.078 18.653 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.083 18.736 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.407 20.143 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk SLICE_X182Y116 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[4]/C clock pessimism 1.124 21.267 clock uncertainty -0.063 21.204 SLICE_X182Y116 FDRE (Setup_fdre_C_CE) -0.178 21.026 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[4] ------------------------------------------------------------------- required time 21.026 arrival time -7.503 ------------------------------------------------------------------- slack 13.523 Slack (MET) : 13.523ns (required time - arrival time) Source: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/C (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[5]/CE (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 16.000ns (clk62_5_ub rise@16.000ns - clk62_5_ub rise@0.000ns) Data Path Delay: 2.213ns (logic 0.388ns (17.534%) route 1.825ns (82.466%)) Logic Levels: 3 (LUT2=1 LUT4=1 LUT6=1) Clock Path Skew: -0.024ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.143ns = ( 20.143 - 16.000 ) Source Clock Delay (SCD): 5.291ns Clock Pessimism Removal (CPR): 1.124ns Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 2.205 3.654 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.544 5.291 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk SLICE_X182Y115 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X182Y115 FDRE (Prop_fdre_C_Q) 0.259 5.550 f sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/Q net (fo=2, routed) 0.454 6.004 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2] SLICE_X183Y117 LUT4 (Prop_lut4_I0_O) 0.043 6.047 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7/O net (fo=1, routed) 0.355 6.402 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7_n_0 SLICE_X183Y117 LUT6 (Prop_lut6_I1_O) 0.043 6.445 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/O net (fo=2, routed) 0.612 7.057 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4_n_0 SLICE_X185Y118 LUT2 (Prop_lut2_I0_O) 0.043 7.100 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/O net (fo=17, routed) 0.404 7.503 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2_n_0 SLICE_X182Y116 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 16.000 16.000 r AD6 0.000 16.000 r osc125_a_p (IN) net (fo=0) 0.000 16.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 16.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 16.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 17.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 18.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 18.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 20.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -3.847 16.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 2.078 18.653 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.083 18.736 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.407 20.143 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk SLICE_X182Y116 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[5]/C clock pessimism 1.124 21.267 clock uncertainty -0.063 21.204 SLICE_X182Y116 FDRE (Setup_fdre_C_CE) -0.178 21.026 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[5] ------------------------------------------------------------------- required time 21.026 arrival time -7.503 ------------------------------------------------------------------- slack 13.523 Slack (MET) : 13.523ns (required time - arrival time) Source: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/C (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[6]/CE (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 16.000ns (clk62_5_ub rise@16.000ns - clk62_5_ub rise@0.000ns) Data Path Delay: 2.213ns (logic 0.388ns (17.534%) route 1.825ns (82.466%)) Logic Levels: 3 (LUT2=1 LUT4=1 LUT6=1) Clock Path Skew: -0.024ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.143ns = ( 20.143 - 16.000 ) Source Clock Delay (SCD): 5.291ns Clock Pessimism Removal (CPR): 1.124ns Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 2.205 3.654 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.544 5.291 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk SLICE_X182Y115 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X182Y115 FDRE (Prop_fdre_C_Q) 0.259 5.550 f sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/Q net (fo=2, routed) 0.454 6.004 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2] SLICE_X183Y117 LUT4 (Prop_lut4_I0_O) 0.043 6.047 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7/O net (fo=1, routed) 0.355 6.402 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7_n_0 SLICE_X183Y117 LUT6 (Prop_lut6_I1_O) 0.043 6.445 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/O net (fo=2, routed) 0.612 7.057 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4_n_0 SLICE_X185Y118 LUT2 (Prop_lut2_I0_O) 0.043 7.100 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/O net (fo=17, routed) 0.404 7.503 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2_n_0 SLICE_X182Y116 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 16.000 16.000 r AD6 0.000 16.000 r osc125_a_p (IN) net (fo=0) 0.000 16.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 16.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 16.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 17.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 18.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 18.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 20.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -3.847 16.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 2.078 18.653 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.083 18.736 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.407 20.143 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk SLICE_X182Y116 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[6]/C clock pessimism 1.124 21.267 clock uncertainty -0.063 21.204 SLICE_X182Y116 FDRE (Setup_fdre_C_CE) -0.178 21.026 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[6] ------------------------------------------------------------------- required time 21.026 arrival time -7.503 ------------------------------------------------------------------- slack 13.523 Slack (MET) : 13.523ns (required time - arrival time) Source: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/C (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7]/CE (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 16.000ns (clk62_5_ub rise@16.000ns - clk62_5_ub rise@0.000ns) Data Path Delay: 2.213ns (logic 0.388ns (17.534%) route 1.825ns (82.466%)) Logic Levels: 3 (LUT2=1 LUT4=1 LUT6=1) Clock Path Skew: -0.024ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.143ns = ( 20.143 - 16.000 ) Source Clock Delay (SCD): 5.291ns Clock Pessimism Removal (CPR): 1.124ns Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 2.205 3.654 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.544 5.291 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk SLICE_X182Y115 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X182Y115 FDRE (Prop_fdre_C_Q) 0.259 5.550 f sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/Q net (fo=2, routed) 0.454 6.004 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2] SLICE_X183Y117 LUT4 (Prop_lut4_I0_O) 0.043 6.047 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7/O net (fo=1, routed) 0.355 6.402 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7_n_0 SLICE_X183Y117 LUT6 (Prop_lut6_I1_O) 0.043 6.445 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/O net (fo=2, routed) 0.612 7.057 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4_n_0 SLICE_X185Y118 LUT2 (Prop_lut2_I0_O) 0.043 7.100 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/O net (fo=17, routed) 0.404 7.503 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2_n_0 SLICE_X182Y116 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7]/CE ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 16.000 16.000 r AD6 0.000 16.000 r osc125_a_p (IN) net (fo=0) 0.000 16.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 16.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 16.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 17.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 18.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 18.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 20.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -3.847 16.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 2.078 18.653 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.083 18.736 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.407 20.143 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk SLICE_X182Y116 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7]/C clock pessimism 1.124 21.267 clock uncertainty -0.063 21.204 SLICE_X182Y116 FDRE (Setup_fdre_C_CE) -0.178 21.026 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7] ------------------------------------------------------------------- required time 21.026 arrival time -7.503 ------------------------------------------------------------------- slack 13.523 Slack (MET) : 13.603ns (required time - arrival time) Source: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/C (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[16]/CE (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 16.000ns (clk62_5_ub rise@16.000ns - clk62_5_ub rise@0.000ns) Data Path Delay: 2.130ns (logic 0.388ns (18.215%) route 1.742ns (81.785%)) Logic Levels: 3 (LUT2=1 LUT4=1 LUT6=1) Clock Path Skew: -0.026ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.141ns = ( 20.141 - 16.000 ) Source Clock Delay (SCD): 5.291ns Clock Pessimism Removal (CPR): 1.124ns Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 2.205 3.654 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.544 5.291 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk SLICE_X182Y115 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X182Y115 FDRE (Prop_fdre_C_Q) 0.259 5.550 f sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/Q net (fo=2, routed) 0.454 6.004 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2] SLICE_X183Y117 LUT4 (Prop_lut4_I0_O) 0.043 6.047 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7/O net (fo=1, routed) 0.355 6.402 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7_n_0 SLICE_X183Y117 LUT6 (Prop_lut6_I1_O) 0.043 6.445 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/O net (fo=2, routed) 0.612 7.057 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4_n_0 SLICE_X185Y118 LUT2 (Prop_lut2_I0_O) 0.043 7.100 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/O net (fo=17, routed) 0.321 7.421 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2_n_0 SLICE_X182Y119 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[16]/CE ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 16.000 16.000 r AD6 0.000 16.000 r osc125_a_p (IN) net (fo=0) 0.000 16.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 16.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 16.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 17.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 18.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 18.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 20.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -3.847 16.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 2.078 18.653 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.083 18.736 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.405 20.141 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk SLICE_X182Y119 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[16]/C clock pessimism 1.124 21.265 clock uncertainty -0.063 21.202 SLICE_X182Y119 FDRE (Setup_fdre_C_CE) -0.178 21.024 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[16] ------------------------------------------------------------------- required time 21.024 arrival time -7.421 ------------------------------------------------------------------- slack 13.603 Slack (MET) : 13.607ns (required time - arrival time) Source: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/C (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[10]/CE (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 16.000ns (clk62_5_ub rise@16.000ns - clk62_5_ub rise@0.000ns) Data Path Delay: 2.128ns (logic 0.388ns (18.235%) route 1.740ns (81.765%)) Logic Levels: 3 (LUT2=1 LUT4=1 LUT6=1) Clock Path Skew: -0.025ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.142ns = ( 20.142 - 16.000 ) Source Clock Delay (SCD): 5.291ns Clock Pessimism Removal (CPR): 1.124ns Clock Uncertainty: 0.063ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 2.205 3.654 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.544 5.291 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk SLICE_X182Y115 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X182Y115 FDRE (Prop_fdre_C_Q) 0.259 5.550 f sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/Q net (fo=2, routed) 0.454 6.004 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2] SLICE_X183Y117 LUT4 (Prop_lut4_I0_O) 0.043 6.047 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7/O net (fo=1, routed) 0.355 6.402 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_7_n_0 SLICE_X183Y117 LUT6 (Prop_lut6_I1_O) 0.043 6.445 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/O net (fo=2, routed) 0.612 7.057 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4_n_0 SLICE_X185Y118 LUT2 (Prop_lut2_I0_O) 0.043 7.100 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/O net (fo=17, routed) 0.319 7.418 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2_n_0 SLICE_X182Y117 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[10]/CE ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 16.000 16.000 r AD6 0.000 16.000 r osc125_a_p (IN) net (fo=0) 0.000 16.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 16.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 16.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 17.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 18.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 18.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 20.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -3.847 16.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 2.078 18.653 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.083 18.736 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.406 20.142 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk SLICE_X182Y117 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[10]/C clock pessimism 1.124 21.266 clock uncertainty -0.063 21.203 SLICE_X182Y117 FDRE (Setup_fdre_C_CE) -0.178 21.025 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[10] ------------------------------------------------------------------- required time 21.025 arrival time -7.418 ------------------------------------------------------------------- slack 13.607 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.151ns (arrival time - required time) Source: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/run_phase_alignment_int_s3_reg/C (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_reg/D (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk62_5_ub rise@0.000ns - clk62_5_ub rise@0.000ns) Data Path Delay: 0.212ns (logic 0.155ns (72.981%) route 0.057ns (27.019%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.283ns Source Clock Delay (SCD): 1.726ns Clock Pessimism Removal (CPR): 0.557ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 1.004 1.017 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 0.683 1.726 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk SLICE_X183Y118 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/run_phase_alignment_int_s3_reg/C ------------------------------------------------------------------- ------------------- SLICE_X183Y118 FDRE (Prop_fdre_C_Q) 0.091 1.817 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/run_phase_alignment_int_s3_reg/Q net (fo=2, routed) 0.057 1.874 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/run_phase_alignment_int_s3 SLICE_X183Y118 LUT4 (Prop_lut4_I3_O) 0.064 1.938 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_i_1/O net (fo=1, routed) 0.000 1.938 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_i_1_n_0 SLICE_X183Y118 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_reg/D ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 1.073 1.348 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 0.905 2.283 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk SLICE_X183Y118 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_reg/C clock pessimism -0.557 1.726 SLICE_X183Y118 FDRE (Hold_fdre_C_D) 0.061 1.787 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_reg ------------------------------------------------------------------- required time -1.787 arrival time 1.938 ------------------------------------------------------------------- slack 0.151 Slack (MET) : 0.153ns (arrival time - required time) Source: sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync1/C (rising edge-triggered cell FDPE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync2/D (rising edge-triggered cell FDPE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk62_5_ub rise@0.000ns - clk62_5_ub rise@0.000ns) Data Path Delay: 0.147ns (logic 0.091ns (62.053%) route 0.056ns (37.947%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.291ns Source Clock Delay (SCD): 1.733ns Clock Pessimism Removal (CPR): 0.558ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 1.004 1.017 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 0.690 1.733 sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/userclk SLICE_X188Y108 FDPE r sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync1/C ------------------------------------------------------------------- ------------------- SLICE_X188Y108 FDPE (Prop_fdpe_C_Q) 0.091 1.824 r sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync1/Q net (fo=1, routed) 0.056 1.879 sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync_reg1 SLICE_X188Y108 FDPE r sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync2/D ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 1.073 1.348 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 0.913 2.291 sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/userclk SLICE_X188Y108 FDPE r sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync2/C clock pessimism -0.558 1.733 SLICE_X188Y108 FDPE (Hold_fdpe_C_D) -0.006 1.727 sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync2 ------------------------------------------------------------------- required time -1.727 arrival time 1.879 ------------------------------------------------------------------- slack 0.153 Slack (MET) : 0.157ns (arrival time - required time) Source: sys/eth/phy/U0/transceiver_inst/txchardispmode_int_reg[0]/C (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i/TXCHARDISPMODE[0] (rising edge-triggered cell GTXE2_CHANNEL clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk62_5_ub rise@0.000ns - clk62_5_ub rise@0.000ns) Data Path Delay: 0.420ns (logic 0.100ns (23.791%) route 0.320ns (76.209%)) Logic Levels: 0 Clock Path Skew: 0.185ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.463ns Source Clock Delay (SCD): 1.734ns Clock Pessimism Removal (CPR): 0.544ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 1.004 1.017 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 0.691 1.734 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X189Y103 FDRE r sys/eth/phy/U0/transceiver_inst/txchardispmode_int_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X189Y103 FDRE (Prop_fdre_C_Q) 0.100 1.834 r sys/eth/phy/U0/transceiver_inst/txchardispmode_int_reg[0]/Q net (fo=1, routed) 0.320 2.154 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/data_sync_reg1[0] GTXE2_CHANNEL_X0Y8 GTXE2_CHANNEL r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i/TXCHARDISPMODE[0] ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 1.073 1.348 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.085 2.463 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/userclk GTXE2_CHANNEL_X0Y8 GTXE2_CHANNEL r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i/TXUSRCLK2 clock pessimism -0.544 1.919 GTXE2_CHANNEL_X0Y8 GTXE2_CHANNEL (Hold_gtxe2_channel_TXUSRCLK2_TXCHARDISPMODE[0]) 0.078 1.997 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i ------------------------------------------------------------------- required time -1.997 arrival time 2.154 ------------------------------------------------------------------- slack 0.157 Slack (MET) : 0.164ns (arrival time - required time) Source: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg6/C (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/tx_fsm_reset_done_int_s3_reg/D (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk62_5_ub rise@0.000ns - clk62_5_ub rise@0.000ns) Data Path Delay: 0.235ns (logic 0.100ns (42.564%) route 0.135ns (57.436%)) Logic Levels: 0 Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.279ns Source Clock Delay (SCD): 1.722ns Clock Pessimism Removal (CPR): 0.546ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 1.004 1.017 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 0.679 1.722 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/userclk SLICE_X183Y122 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg6/C ------------------------------------------------------------------- ------------------- SLICE_X183Y122 FDRE (Prop_fdre_C_Q) 0.100 1.822 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg6/Q net (fo=1, routed) 0.135 1.956 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/tx_fsm_reset_done_int_s2 SLICE_X182Y122 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/tx_fsm_reset_done_int_s3_reg/D ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 1.073 1.348 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 0.901 2.279 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk SLICE_X182Y122 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/tx_fsm_reset_done_int_s3_reg/C clock pessimism -0.546 1.733 SLICE_X182Y122 FDRE (Hold_fdre_C_D) 0.060 1.793 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/tx_fsm_reset_done_int_s3_reg ------------------------------------------------------------------- required time -1.793 arrival time 1.956 ------------------------------------------------------------------- slack 0.164 Slack (MET) : 0.199ns (arrival time - required time) Source: sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync4/C (rising edge-triggered cell FDPE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync5/D (rising edge-triggered cell FDPE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk62_5_ub rise@0.000ns - clk62_5_ub rise@0.000ns) Data Path Delay: 0.246ns (logic 0.100ns (40.717%) route 0.146ns (59.283%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.291ns Source Clock Delay (SCD): 1.733ns Clock Pessimism Removal (CPR): 0.558ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 1.004 1.017 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 0.690 1.733 sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/userclk SLICE_X188Y108 FDPE r sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync4/C ------------------------------------------------------------------- ------------------- SLICE_X188Y108 FDPE (Prop_fdpe_C_Q) 0.100 1.833 r sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync4/Q net (fo=1, routed) 0.146 1.978 sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync_reg4 SLICE_X188Y108 FDPE r sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync5/D ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 1.073 1.348 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 0.913 2.291 sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/userclk SLICE_X188Y108 FDPE r sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync5/C clock pessimism -0.558 1.733 SLICE_X188Y108 FDPE (Hold_fdpe_C_D) 0.047 1.780 sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync5 ------------------------------------------------------------------- required time -1.780 arrival time 1.978 ------------------------------------------------------------------- slack 0.199 Slack (MET) : 0.204ns (arrival time - required time) Source: sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync5/C (rising edge-triggered cell FDPE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync6/D (rising edge-triggered cell FDPE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk62_5_ub rise@0.000ns - clk62_5_ub rise@0.000ns) Data Path Delay: 0.229ns (logic 0.091ns (39.787%) route 0.138ns (60.213%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.291ns Source Clock Delay (SCD): 1.733ns Clock Pessimism Removal (CPR): 0.544ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 1.004 1.017 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 0.690 1.733 sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/userclk SLICE_X188Y108 FDPE r sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync5/C ------------------------------------------------------------------- ------------------- SLICE_X188Y108 FDPE (Prop_fdpe_C_Q) 0.091 1.824 r sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync5/Q net (fo=1, routed) 0.138 1.961 sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync_reg5 SLICE_X188Y109 FDPE r sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync6/D ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 1.073 1.348 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 0.913 2.291 sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/userclk SLICE_X188Y109 FDPE r sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync6/C clock pessimism -0.544 1.747 SLICE_X188Y109 FDPE (Hold_fdpe_C_D) 0.011 1.758 sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync6 ------------------------------------------------------------------- required time -1.758 arrival time 1.961 ------------------------------------------------------------------- slack 0.204 Slack (MET) : 0.204ns (arrival time - required time) Source: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_wait_bypass_reg/C (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_wait_bypass_reg/D (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk62_5_ub rise@0.000ns - clk62_5_ub rise@0.000ns) Data Path Delay: 0.264ns (logic 0.128ns (48.495%) route 0.136ns (51.505%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.276ns Source Clock Delay (SCD): 1.720ns Clock Pessimism Removal (CPR): 0.556ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 1.004 1.017 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 0.677 1.720 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/userclk SLICE_X185Y124 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_wait_bypass_reg/C ------------------------------------------------------------------- ------------------- SLICE_X185Y124 FDRE (Prop_fdre_C_Q) 0.100 1.820 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_wait_bypass_reg/Q net (fo=2, routed) 0.136 1.956 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_wait_bypass_reg_n_0 SLICE_X185Y124 LUT4 (Prop_lut4_I0_O) 0.028 1.984 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_wait_bypass_i_1__0/O net (fo=1, routed) 0.000 1.984 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_wait_bypass_i_1__0_n_0 SLICE_X185Y124 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_wait_bypass_reg/D ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 1.073 1.348 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 0.898 2.276 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/userclk SLICE_X185Y124 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_wait_bypass_reg/C clock pessimism -0.556 1.720 SLICE_X185Y124 FDRE (Hold_fdre_C_D) 0.060 1.780 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_wait_bypass_reg ------------------------------------------------------------------- required time -1.780 arrival time 1.984 ------------------------------------------------------------------- slack 0.204 Slack (MET) : 0.206ns (arrival time - required time) Source: sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync2/C (rising edge-triggered cell FDPE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync3/D (rising edge-triggered cell FDPE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk62_5_ub rise@0.000ns - clk62_5_ub rise@0.000ns) Data Path Delay: 0.250ns (logic 0.100ns (39.930%) route 0.150ns (60.070%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.291ns Source Clock Delay (SCD): 1.733ns Clock Pessimism Removal (CPR): 0.558ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 1.004 1.017 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 0.690 1.733 sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/userclk SLICE_X188Y108 FDPE r sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync2/C ------------------------------------------------------------------- ------------------- SLICE_X188Y108 FDPE (Prop_fdpe_C_Q) 0.100 1.833 r sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync2/Q net (fo=1, routed) 0.150 1.983 sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync_reg2 SLICE_X188Y108 FDPE r sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync3/D ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 1.073 1.348 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 0.913 2.291 sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/userclk SLICE_X188Y108 FDPE r sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync3/C clock pessimism -0.558 1.733 SLICE_X188Y108 FDPE (Hold_fdpe_C_D) 0.044 1.777 sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync3 ------------------------------------------------------------------- required time -1.777 arrival time 1.983 ------------------------------------------------------------------- slack 0.206 Slack (MET) : 0.215ns (arrival time - required time) Source: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/C (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/D (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk62_5_ub rise@0.000ns - clk62_5_ub rise@0.000ns) Data Path Delay: 0.307ns (logic 0.193ns (62.818%) route 0.114ns (37.182%)) Logic Levels: 1 (CARRY4=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.286ns Source Clock Delay (SCD): 1.729ns Clock Pessimism Removal (CPR): 0.557ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 1.004 1.017 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 0.686 1.729 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk SLICE_X182Y115 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X182Y115 FDRE (Prop_fdre_C_Q) 0.118 1.847 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/Q net (fo=2, routed) 0.114 1.961 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2] SLICE_X182Y115 CARRY4 (Prop_carry4_S[2]_O[2]) 0.075 2.036 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]_i_3/O[2] net (fo=1, routed) 0.000 2.036 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]_i_3_n_5 SLICE_X182Y115 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/D ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 1.073 1.348 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 0.908 2.286 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk SLICE_X182Y115 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2]/C clock pessimism -0.557 1.729 SLICE_X182Y115 FDRE (Hold_fdre_C_D) 0.092 1.821 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[2] ------------------------------------------------------------------- required time -1.821 arrival time 2.036 ------------------------------------------------------------------- slack 0.215 Slack (MET) : 0.216ns (arrival time - required time) Source: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[6]/C (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[6]/D (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk62_5_ub rise@0.000ns - clk62_5_ub rise@0.000ns) Data Path Delay: 0.308ns (logic 0.193ns (62.756%) route 0.115ns (37.244%)) Logic Levels: 1 (CARRY4=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.285ns Source Clock Delay (SCD): 1.728ns Clock Pessimism Removal (CPR): 0.557ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 1.004 1.017 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 0.685 1.728 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk SLICE_X182Y116 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X182Y116 FDRE (Prop_fdre_C_Q) 0.118 1.846 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[6]/Q net (fo=2, routed) 0.115 1.960 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[6] SLICE_X182Y116 CARRY4 (Prop_carry4_S[2]_O[2]) 0.075 2.035 r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[4]_i_1/O[2] net (fo=1, routed) 0.000 2.035 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[4]_i_1_n_5 SLICE_X182Y116 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[6]/D ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 1.073 1.348 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 0.907 2.285 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/userclk SLICE_X182Y116 FDRE r sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[6]/C clock pessimism -0.557 1.728 SLICE_X182Y116 FDRE (Hold_fdre_C_D) 0.092 1.820 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[6] ------------------------------------------------------------------- required time -1.820 arrival time 2.035 ------------------------------------------------------------------- slack 0.216 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk62_5_ub Waveform(ns): { 0.000 8.000 } Period(ns): 16.000 Sources: { sys/clocks/PLLE2_BASE_inst/CLKOUT1 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/RXUSRCLK n/a 3.030 16.000 12.970 GTXE2_CHANNEL_X0Y8 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i/RXUSRCLK Min Period n/a GTXE2_CHANNEL/RXUSRCLK2 n/a 3.030 16.000 12.970 GTXE2_CHANNEL_X0Y8 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i/RXUSRCLK2 Min Period n/a GTXE2_CHANNEL/TXUSRCLK n/a 3.030 16.000 12.970 GTXE2_CHANNEL_X0Y8 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i/TXUSRCLK Min Period n/a GTXE2_CHANNEL/TXUSRCLK2 n/a 3.030 16.000 12.970 GTXE2_CHANNEL_X0Y8 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i/TXUSRCLK2 Min Period n/a BUFG/I n/a 1.409 16.000 14.592 BUFGCTRL_X0Y7 sys/clocks/clk62_5_buf/I Min Period n/a PLLE2_ADV/CLKOUT1 n/a 1.071 16.000 14.929 PLLE2_ADV_X0Y1 sys/clocks/PLLE2_BASE_inst/CLKOUT1 Min Period n/a FDRE/C n/a 0.750 16.000 15.250 SLICE_X185Y124 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/run_phase_alignment_int_s3_reg/C Min Period n/a FDRE/C n/a 0.750 16.000 15.250 SLICE_X185Y125 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C Min Period n/a FDRE/C n/a 0.750 16.000 15.250 SLICE_X185Y125 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg3/C Min Period n/a FDRE/C n/a 0.750 16.000 15.250 SLICE_X185Y125 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg5/C Max Period n/a PLLE2_ADV/CLKOUT1 n/a 160.000 16.000 144.000 PLLE2_ADV_X0Y1 sys/clocks/PLLE2_BASE_inst/CLKOUT1 Low Pulse Width Slow FDRE/C n/a 0.400 8.000 7.600 SLICE_X185Y124 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/run_phase_alignment_int_s3_reg/C Low Pulse Width Slow FDRE/C n/a 0.400 8.000 7.600 SLICE_X185Y125 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C Low Pulse Width Slow FDRE/C n/a 0.400 8.000 7.600 SLICE_X185Y125 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg3/C Low Pulse Width Slow FDRE/C n/a 0.400 8.000 7.600 SLICE_X185Y125 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg5/C Low Pulse Width Slow FDRE/C n/a 0.400 8.000 7.600 SLICE_X184Y125 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/C Low Pulse Width Slow FDRE/C n/a 0.400 8.000 7.600 SLICE_X184Y125 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg3/C Low Pulse Width Slow FDRE/C n/a 0.400 8.000 7.600 SLICE_X184Y125 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg5/C Low Pulse Width Slow FDRE/C n/a 0.400 8.000 7.600 SLICE_X189Y103 sys/eth/phy/U0/transceiver_inst/txdata_int_reg[14]/C Low Pulse Width Slow FDRE/C n/a 0.400 8.000 7.600 SLICE_X189Y103 sys/eth/phy/U0/transceiver_inst/txdata_int_reg[15]/C Low Pulse Width Slow FDRE/C n/a 0.400 8.000 7.600 SLICE_X188Y105 sys/eth/phy/U0/transceiver_inst/txdata_int_reg[7]/C High Pulse Width Fast FDRE/C n/a 0.350 8.000 7.650 SLICE_X182Y117 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[10]/C High Pulse Width Fast FDRE/C n/a 0.350 8.000 7.650 SLICE_X182Y117 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[11]/C High Pulse Width Fast FDRE/C n/a 0.350 8.000 7.650 SLICE_X182Y116 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[4]/C High Pulse Width Fast FDRE/C n/a 0.350 8.000 7.650 SLICE_X182Y116 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[5]/C High Pulse Width Fast FDRE/C n/a 0.350 8.000 7.650 SLICE_X182Y116 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[6]/C High Pulse Width Fast FDRE/C n/a 0.350 8.000 7.650 SLICE_X182Y116 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7]/C High Pulse Width Fast FDRE/C n/a 0.350 8.000 7.650 SLICE_X182Y117 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[8]/C High Pulse Width Fast FDRE/C n/a 0.350 8.000 7.650 SLICE_X182Y117 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[9]/C High Pulse Width Fast FDRE/C n/a 0.350 8.000 7.650 SLICE_X189Y102 sys/eth/phy/U0/transceiver_inst/txbufstatus_reg_reg[1]/C High Pulse Width Slow FDRE/C n/a 0.350 8.000 7.650 SLICE_X185Y124 sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/run_phase_alignment_int_s3_reg/C --------------------------------------------------------------------------------------------------- From Clock: clk_ipb_ub To Clock: clk_ipb_ub Setup : 0 Failing Endpoints, Worst Slack 10.972ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.051ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 15.358ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 10.972ns (required time - arrival time) Source: sys/uc_if/uc_trans/ram_in/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKBWRCLK (rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: ngFEC/SFP_GEN[5].ngFEC_module/bram_array[9].skip_SFP_SEC.buffer_server/server_din_o_reg[23]/D (rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: clk_ipb_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 32.000ns (clk_ipb_ub rise@32.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 21.183ns (logic 1.886ns (8.903%) route 19.297ns (91.097%)) Logic Levels: 2 (LUT5=2) Clock Path Skew: 0.205ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.360ns = ( 36.360 - 32.000 ) Source Clock Delay (SCD): 5.180ns Clock Pessimism Removal (CPR): 1.026ns Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.205 3.654 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.434 5.180 sys/uc_if/uc_trans/ram_in/clkb RAMB36_X6Y26 RAMB36E1 r sys/uc_if/uc_trans/ram_in/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKBWRCLK ------------------------------------------------------------------- ------------------- RAMB36_X6Y26 RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[23]) 1.800 6.980 r sys/uc_if/uc_trans/ram_in/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DOBDO[23] net (fo=3, routed) 1.080 8.060 sys/ipb/trans/iface/doutb[23] SLICE_X83Y131 LUT5 (Prop_lut5_I0_O) 0.043 8.103 r sys/ipb/trans/iface/hlen[7]_i_1/O net (fo=8, routed) 0.600 8.703 sys/ipb/trans/sm/rx_data[23] SLICE_X81Y127 LUT5 (Prop_lut5_I4_O) 0.043 8.746 r sys/ipb/trans/sm/w_data_ipbus[7]_i_1/O net (fo=594, routed) 17.617 26.363 ngFEC/SFP_GEN[5].ngFEC_module/bram_array[9].skip_SFP_SEC.buffer_server/server_din_o_reg[31]_0[23] SLICE_X114Y10 FDRE r ngFEC/SFP_GEN[5].ngFEC_module/bram_array[9].skip_SFP_SEC.buffer_server/server_din_o_reg[23]/D ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 32.000 32.000 r AD6 0.000 32.000 r osc125_a_p (IN) net (fo=0) 0.000 32.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 32.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 32.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 33.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 34.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 36.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -3.847 32.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.078 34.653 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.624 36.360 ngFEC/SFP_GEN[5].ngFEC_module/bram_array[9].skip_SFP_SEC.buffer_server/clk_31_250_bufg SLICE_X114Y10 FDRE r ngFEC/SFP_GEN[5].ngFEC_module/bram_array[9].skip_SFP_SEC.buffer_server/server_din_o_reg[23]/C clock pessimism 1.026 37.386 clock uncertainty -0.069 37.317 SLICE_X114Y10 FDRE (Setup_fdre_C_D) 0.018 37.335 ngFEC/SFP_GEN[5].ngFEC_module/bram_array[9].skip_SFP_SEC.buffer_server/server_din_o_reg[23] ------------------------------------------------------------------- required time 37.335 arrival time -26.363 ------------------------------------------------------------------- slack 10.972 Slack (MET) : 11.398ns (required time - arrival time) Source: sys/uc_if/uc_trans/ram_in/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKBWRCLK (rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: ngFEC/SFP_GEN[5].ngFEC_module/bram_array[9].skip_SFP_SEC.input_size_reg[9][23]/D (rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: clk_ipb_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 32.000ns (clk_ipb_ub rise@32.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 20.774ns (logic 1.929ns (9.286%) route 18.845ns (90.714%)) Logic Levels: 3 (LUT4=1 LUT5=2) Clock Path Skew: 0.206ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.361ns = ( 36.361 - 32.000 ) Source Clock Delay (SCD): 5.180ns Clock Pessimism Removal (CPR): 1.026ns Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.205 3.654 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.434 5.180 sys/uc_if/uc_trans/ram_in/clkb RAMB36_X6Y26 RAMB36E1 r sys/uc_if/uc_trans/ram_in/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKBWRCLK ------------------------------------------------------------------- ------------------- RAMB36_X6Y26 RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[23]) 1.800 6.980 r sys/uc_if/uc_trans/ram_in/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DOBDO[23] net (fo=3, routed) 1.080 8.060 sys/ipb/trans/iface/doutb[23] SLICE_X83Y131 LUT5 (Prop_lut5_I0_O) 0.043 8.103 r sys/ipb/trans/iface/hlen[7]_i_1/O net (fo=8, routed) 0.600 8.703 sys/ipb/trans/sm/rx_data[23] SLICE_X81Y127 LUT5 (Prop_lut5_I4_O) 0.043 8.746 r sys/ipb/trans/sm/w_data_ipbus[7]_i_1/O net (fo=594, routed) 17.165 25.911 sys/rmw_result_reg[31]_11[23] SLICE_X123Y14 LUT4 (Prop_lut4_I3_O) 0.043 25.954 r sys/bram_array[9].skip_SFP_SEC.input_size[9][23]_i_1__3/O net (fo=1, routed) 0.000 25.954 ngFEC/SFP_GEN[5].ngFEC_module/bram_array[9].skip_SFP_SEC.input_size_reg[9][31]_0[23] SLICE_X123Y14 FDCE r ngFEC/SFP_GEN[5].ngFEC_module/bram_array[9].skip_SFP_SEC.input_size_reg[9][23]/D ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 32.000 32.000 r AD6 0.000 32.000 r osc125_a_p (IN) net (fo=0) 0.000 32.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 32.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 32.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 33.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 34.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 36.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -3.847 32.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.078 34.653 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.625 36.361 ngFEC/SFP_GEN[5].ngFEC_module/clk_31_250_bufg SLICE_X123Y14 FDCE r ngFEC/SFP_GEN[5].ngFEC_module/bram_array[9].skip_SFP_SEC.input_size_reg[9][23]/C clock pessimism 1.026 37.387 clock uncertainty -0.069 37.318 SLICE_X123Y14 FDCE (Setup_fdce_C_D) 0.034 37.352 ngFEC/SFP_GEN[5].ngFEC_module/bram_array[9].skip_SFP_SEC.input_size_reg[9][23] ------------------------------------------------------------------- required time 37.352 arrival time -25.954 ------------------------------------------------------------------- slack 11.398 Slack (MET) : 11.435ns (required time - arrival time) Source: sys/ipb/udp_if/ipbus_rx_ram/ram3_reg_1/CLKBWRCLK (rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: ngFEC/SFP_GEN[8].ngFEC_module/bram_array[3].skip_SFP_SEC.input_size_reg[3][21]/D (rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: clk_ipb_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 32.000ns (clk_ipb_ub rise@32.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 20.821ns (logic 1.929ns (9.265%) route 18.892ns (90.735%)) Logic Levels: 3 (LUT3=1 LUT5=2) Clock Path Skew: 0.260ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.402ns = ( 36.402 - 32.000 ) Source Clock Delay (SCD): 5.167ns Clock Pessimism Removal (CPR): 1.026ns Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.205 3.654 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.421 5.167 sys/ipb/udp_if/ipbus_rx_ram/ram3_reg_0_1 RAMB36_X4Y23 RAMB36E1 r sys/ipb/udp_if/ipbus_rx_ram/ram3_reg_1/CLKBWRCLK ------------------------------------------------------------------- ------------------- RAMB36_X4Y23 RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[1]) 1.800 6.967 r sys/ipb/udp_if/ipbus_rx_ram/ram3_reg_1/DOBDO[1] net (fo=3, routed) 1.216 8.183 sys/ipb/trans/iface/trans_in_udp[rdata][21] SLICE_X84Y131 LUT5 (Prop_lut5_I2_O) 0.043 8.226 r sys/ipb/trans/iface/hlen[5]_i_1/O net (fo=8, routed) 0.381 8.608 sys/ipb/trans/sm/rx_data[21] SLICE_X84Y130 LUT5 (Prop_lut5_I4_O) 0.043 8.651 r sys/ipb/trans/sm/w_data_ipbus[5]_i_1/O net (fo=593, routed) 17.294 25.945 sys/rmw_result_reg[31]_11[21] SLICE_X44Y11 LUT3 (Prop_lut3_I2_O) 0.043 25.988 r sys/bram_array[3].skip_SFP_SEC.input_size[3][21]_i_1__6/O net (fo=1, routed) 0.000 25.988 ngFEC/SFP_GEN[8].ngFEC_module/bram_array[3].skip_SFP_SEC.input_size_reg[3][31]_0[21] SLICE_X44Y11 FDCE r ngFEC/SFP_GEN[8].ngFEC_module/bram_array[3].skip_SFP_SEC.input_size_reg[3][21]/D ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 32.000 32.000 r AD6 0.000 32.000 r osc125_a_p (IN) net (fo=0) 0.000 32.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 32.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 32.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 33.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 34.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 36.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -3.847 32.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.078 34.653 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.666 36.402 ngFEC/SFP_GEN[8].ngFEC_module/clk_31_250_bufg SLICE_X44Y11 FDCE r ngFEC/SFP_GEN[8].ngFEC_module/bram_array[3].skip_SFP_SEC.input_size_reg[3][21]/C clock pessimism 1.026 37.428 clock uncertainty -0.069 37.359 SLICE_X44Y11 FDCE (Setup_fdce_C_D) 0.064 37.423 ngFEC/SFP_GEN[8].ngFEC_module/bram_array[3].skip_SFP_SEC.input_size_reg[3][21] ------------------------------------------------------------------- required time 37.423 arrival time -25.988 ------------------------------------------------------------------- slack 11.435 Slack (MET) : 11.727ns (required time - arrival time) Source: sys/uc_if/uc_trans/ram_in/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKBWRCLK (rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: ngFEC/SFP_GEN[5].ngFEC_module/bram_array[12].skip_SFP_SEC.buffer_server/server_din_o_reg[23]/D (rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: clk_ipb_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 32.000ns (clk_ipb_ub rise@32.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 20.458ns (logic 1.886ns (9.219%) route 18.572ns (90.781%)) Logic Levels: 2 (LUT5=2) Clock Path Skew: 0.266ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.421ns = ( 36.421 - 32.000 ) Source Clock Delay (SCD): 5.180ns Clock Pessimism Removal (CPR): 1.026ns Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.205 3.654 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.434 5.180 sys/uc_if/uc_trans/ram_in/clkb RAMB36_X6Y26 RAMB36E1 r sys/uc_if/uc_trans/ram_in/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKBWRCLK ------------------------------------------------------------------- ------------------- RAMB36_X6Y26 RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[23]) 1.800 6.980 r sys/uc_if/uc_trans/ram_in/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DOBDO[23] net (fo=3, routed) 1.080 8.060 sys/ipb/trans/iface/doutb[23] SLICE_X83Y131 LUT5 (Prop_lut5_I0_O) 0.043 8.103 r sys/ipb/trans/iface/hlen[7]_i_1/O net (fo=8, routed) 0.600 8.703 sys/ipb/trans/sm/rx_data[23] SLICE_X81Y127 LUT5 (Prop_lut5_I4_O) 0.043 8.746 r sys/ipb/trans/sm/w_data_ipbus[7]_i_1/O net (fo=594, routed) 16.892 25.638 ngFEC/SFP_GEN[5].ngFEC_module/bram_array[12].skip_SFP_SEC.buffer_server/server_din_o_reg[31]_0[23] SLICE_X133Y8 FDRE r ngFEC/SFP_GEN[5].ngFEC_module/bram_array[12].skip_SFP_SEC.buffer_server/server_din_o_reg[23]/D ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 32.000 32.000 r AD6 0.000 32.000 r osc125_a_p (IN) net (fo=0) 0.000 32.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 32.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 32.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 33.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 34.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 36.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -3.847 32.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.078 34.653 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.685 36.421 ngFEC/SFP_GEN[5].ngFEC_module/bram_array[12].skip_SFP_SEC.buffer_server/clk_31_250_bufg SLICE_X133Y8 FDRE r ngFEC/SFP_GEN[5].ngFEC_module/bram_array[12].skip_SFP_SEC.buffer_server/server_din_o_reg[23]/C clock pessimism 1.026 37.447 clock uncertainty -0.069 37.378 SLICE_X133Y8 FDRE (Setup_fdre_C_D) -0.013 37.365 ngFEC/SFP_GEN[5].ngFEC_module/bram_array[12].skip_SFP_SEC.buffer_server/server_din_o_reg[23] ------------------------------------------------------------------- required time 37.365 arrival time -25.638 ------------------------------------------------------------------- slack 11.727 Slack (MET) : 11.774ns (required time - arrival time) Source: sys/ipb/udp_if/ipbus_rx_ram/ram3_reg_1/CLKBWRCLK (rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: ngFEC/SFP_GEN[8].ngFEC_module/bram_array[3].skip_SFP_SEC.buffer_server/server_din_o_reg[21]/D (rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: clk_ipb_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 32.000ns (clk_ipb_ub rise@32.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 20.470ns (logic 1.886ns (9.214%) route 18.584ns (90.786%)) Logic Levels: 2 (LUT5=2) Clock Path Skew: 0.322ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.464ns = ( 36.464 - 32.000 ) Source Clock Delay (SCD): 5.167ns Clock Pessimism Removal (CPR): 1.026ns Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.205 3.654 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.421 5.167 sys/ipb/udp_if/ipbus_rx_ram/ram3_reg_0_1 RAMB36_X4Y23 RAMB36E1 r sys/ipb/udp_if/ipbus_rx_ram/ram3_reg_1/CLKBWRCLK ------------------------------------------------------------------- ------------------- RAMB36_X4Y23 RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[1]) 1.800 6.967 r sys/ipb/udp_if/ipbus_rx_ram/ram3_reg_1/DOBDO[1] net (fo=3, routed) 1.216 8.183 sys/ipb/trans/iface/trans_in_udp[rdata][21] SLICE_X84Y131 LUT5 (Prop_lut5_I2_O) 0.043 8.226 r sys/ipb/trans/iface/hlen[5]_i_1/O net (fo=8, routed) 0.381 8.608 sys/ipb/trans/sm/rx_data[21] SLICE_X84Y130 LUT5 (Prop_lut5_I4_O) 0.043 8.651 r sys/ipb/trans/sm/w_data_ipbus[5]_i_1/O net (fo=593, routed) 16.986 25.637 ngFEC/SFP_GEN[8].ngFEC_module/bram_array[3].skip_SFP_SEC.buffer_server/server_din_o_reg[31]_0[21] SLICE_X30Y9 FDRE r ngFEC/SFP_GEN[8].ngFEC_module/bram_array[3].skip_SFP_SEC.buffer_server/server_din_o_reg[21]/D ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 32.000 32.000 r AD6 0.000 32.000 r osc125_a_p (IN) net (fo=0) 0.000 32.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 32.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 32.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 33.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 34.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 36.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -3.847 32.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.078 34.653 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.728 36.464 ngFEC/SFP_GEN[8].ngFEC_module/bram_array[3].skip_SFP_SEC.buffer_server/clk_31_250_bufg SLICE_X30Y9 FDRE r ngFEC/SFP_GEN[8].ngFEC_module/bram_array[3].skip_SFP_SEC.buffer_server/server_din_o_reg[21]/C clock pessimism 1.026 37.490 clock uncertainty -0.069 37.421 SLICE_X30Y9 FDRE (Setup_fdre_C_D) -0.010 37.411 ngFEC/SFP_GEN[8].ngFEC_module/bram_array[3].skip_SFP_SEC.buffer_server/server_din_o_reg[21] ------------------------------------------------------------------- required time 37.411 arrival time -25.637 ------------------------------------------------------------------- slack 11.774 Slack (MET) : 11.810ns (required time - arrival time) Source: sys/uc_if/uc_trans/ram_in/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKBWRCLK (rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: ngFEC/SFP_GEN[1].ngFEC_module/bram_array[12].skip_SFP_SEC.buffer_server/server_din_o_reg[23]/D (rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: clk_ipb_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 32.000ns (clk_ipb_ub rise@32.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 19.747ns (logic 1.886ns (9.551%) route 17.861ns (90.449%)) Logic Levels: 2 (LUT5=2) Clock Path Skew: -0.370ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.800ns = ( 35.800 - 32.000 ) Source Clock Delay (SCD): 5.180ns Clock Pessimism Removal (CPR): 1.011ns Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.205 3.654 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.434 5.180 sys/uc_if/uc_trans/ram_in/clkb RAMB36_X6Y26 RAMB36E1 r sys/uc_if/uc_trans/ram_in/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKBWRCLK ------------------------------------------------------------------- ------------------- RAMB36_X6Y26 RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[23]) 1.800 6.980 r sys/uc_if/uc_trans/ram_in/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DOBDO[23] net (fo=3, routed) 1.080 8.060 sys/ipb/trans/iface/doutb[23] SLICE_X83Y131 LUT5 (Prop_lut5_I0_O) 0.043 8.103 r sys/ipb/trans/iface/hlen[7]_i_1/O net (fo=8, routed) 0.600 8.703 sys/ipb/trans/sm/rx_data[23] SLICE_X81Y127 LUT5 (Prop_lut5_I4_O) 0.043 8.746 r sys/ipb/trans/sm/w_data_ipbus[7]_i_1/O net (fo=594, routed) 16.181 24.927 ngFEC/SFP_GEN[1].ngFEC_module/bram_array[12].skip_SFP_SEC.buffer_server/server_din_o_reg[31]_0[23] SLICE_X89Y219 FDRE r ngFEC/SFP_GEN[1].ngFEC_module/bram_array[12].skip_SFP_SEC.buffer_server/server_din_o_reg[23]/D ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 32.000 32.000 r AD6 0.000 32.000 r osc125_a_p (IN) net (fo=0) 0.000 32.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 32.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 32.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 33.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 34.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 36.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -3.847 32.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.078 34.653 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.064 35.800 ngFEC/SFP_GEN[1].ngFEC_module/bram_array[12].skip_SFP_SEC.buffer_server/clk_31_250_bufg SLICE_X89Y219 FDRE r ngFEC/SFP_GEN[1].ngFEC_module/bram_array[12].skip_SFP_SEC.buffer_server/server_din_o_reg[23]/C clock pessimism 1.011 36.811 clock uncertainty -0.069 36.742 SLICE_X89Y219 FDRE (Setup_fdre_C_D) -0.005 36.737 ngFEC/SFP_GEN[1].ngFEC_module/bram_array[12].skip_SFP_SEC.buffer_server/server_din_o_reg[23] ------------------------------------------------------------------- required time 36.737 arrival time -24.927 ------------------------------------------------------------------- slack 11.810 Slack (MET) : 11.821ns (required time - arrival time) Source: sys/ipb/trans/sm/addr_reg[19]/C (rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: ngFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.buffer_server/ram_miso_reg[ipb_rdata][10]/D (rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: clk_ipb_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 32.000ns (clk_ipb_ub rise@32.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 19.968ns (logic 0.560ns (2.804%) route 19.408ns (97.196%)) Logic Levels: 7 (LUT4=2 LUT5=3 LUT6=2) Clock Path Skew: -0.176ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.954ns = ( 35.954 - 32.000 ) Source Clock Delay (SCD): 5.141ns Clock Pessimism Removal (CPR): 1.011ns Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.205 3.654 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.394 5.141 sys/ipb/trans/sm/out SLICE_X82Y138 FDRE r sys/ipb/trans/sm/addr_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X82Y138 FDRE (Prop_fdre_C_Q) 0.259 5.400 r sys/ipb/trans/sm/addr_reg[19]/Q net (fo=746, routed) 14.618 20.018 sys/ipb_from_master[ipb_addr][19] SLICE_X109Y274 LUT5 (Prop_lut5_I1_O) 0.043 20.061 r sys/FSM_sequential_server_ack[1]_i_3__119/O net (fo=56, routed) 0.743 20.804 sys/ngFEC/SFP_GEN[3].ngFEC_module/ram_mosi[14][ipb_addr][18] SLICE_X108Y268 LUT5 (Prop_lut5_I3_O) 0.043 20.847 f sys/FSM_sequential_server_ack[1]_i_8__25/O net (fo=1, routed) 0.255 21.101 sys/FSM_sequential_server_ack[1]_i_8__25_n_0 SLICE_X108Y268 LUT4 (Prop_lut4_I0_O) 0.043 21.144 f sys/FSM_sequential_server_ack[1]_i_7__35/O net (fo=2, routed) 0.444 21.588 sys/FSM_sequential_server_ack[1]_i_7__35_n_0 SLICE_X109Y268 LUT6 (Prop_lut6_I3_O) 0.043 21.631 f sys/ram_miso[ipb_rdata][31]_i_6__21/O net (fo=36, routed) 1.420 23.052 sys/addr_reg[13]_21 SLICE_X113Y278 LUT4 (Prop_lut4_I3_O) 0.043 23.095 r sys/ram_miso[ipb_rdata][31]_i_7__21/O net (fo=30, routed) 1.501 24.596 ngFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.RAM/BRAM_h/ram_miso_reg[ipb_rdata][31]_5 SLICE_X115Y270 LUT6 (Prop_lut6_I5_O) 0.043 24.639 r ngFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.RAM/BRAM_h/ram_miso[ipb_rdata][10]_i_2__35/O net (fo=1, routed) 0.427 25.066 ngFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.RAM/BRAM_h/ram_miso[ipb_rdata][10]_i_2__35_n_0 SLICE_X109Y270 LUT5 (Prop_lut5_I0_O) 0.043 25.109 r ngFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.RAM/BRAM_h/ram_miso[ipb_rdata][10]_i_1__35/O net (fo=1, routed) 0.000 25.109 ngFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.buffer_server/ram_miso_reg[ipb_rdata][31]_2[10] SLICE_X109Y270 FDRE r ngFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.buffer_server/ram_miso_reg[ipb_rdata][10]/D ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 32.000 32.000 r AD6 0.000 32.000 r osc125_a_p (IN) net (fo=0) 0.000 32.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 32.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 32.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 33.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 34.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 36.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -3.847 32.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.078 34.653 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.218 35.954 ngFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.buffer_server/clk_31_250_bufg SLICE_X109Y270 FDRE r ngFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.buffer_server/ram_miso_reg[ipb_rdata][10]/C clock pessimism 1.011 36.965 clock uncertainty -0.069 36.896 SLICE_X109Y270 FDRE (Setup_fdre_C_D) 0.034 36.930 ngFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.buffer_server/ram_miso_reg[ipb_rdata][10] ------------------------------------------------------------------- required time 36.930 arrival time -25.109 ------------------------------------------------------------------- slack 11.821 Slack (MET) : 11.848ns (required time - arrival time) Source: sys/ipb/udp_if/ipbus_rx_ram/ram3_reg_1/CLKBWRCLK (rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: ngFEC/SFP_GEN[8].ngFEC_module/bram_array[2].skip_SFP_SEC.buffer_server/server_din_o_reg[22]/D (rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: clk_ipb_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 32.000ns (clk_ipb_ub rise@32.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 20.404ns (logic 1.886ns (9.243%) route 18.518ns (90.757%)) Logic Levels: 2 (LUT5=2) Clock Path Skew: 0.331ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.473ns = ( 36.473 - 32.000 ) Source Clock Delay (SCD): 5.167ns Clock Pessimism Removal (CPR): 1.026ns Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.205 3.654 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.421 5.167 sys/ipb/udp_if/ipbus_rx_ram/ram3_reg_0_1 RAMB36_X4Y23 RAMB36E1 r sys/ipb/udp_if/ipbus_rx_ram/ram3_reg_1/CLKBWRCLK ------------------------------------------------------------------- ------------------- RAMB36_X4Y23 RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[2]) 1.800 6.967 r sys/ipb/udp_if/ipbus_rx_ram/ram3_reg_1/DOBDO[2] net (fo=3, routed) 1.302 8.269 sys/ipb/trans/iface/trans_in_udp[rdata][22] SLICE_X83Y131 LUT5 (Prop_lut5_I2_O) 0.043 8.312 r sys/ipb/trans/iface/hlen[6]_i_1/O net (fo=8, routed) 0.754 9.066 sys/ipb/trans/sm/rx_data[22] SLICE_X81Y127 LUT5 (Prop_lut5_I4_O) 0.043 9.109 r sys/ipb/trans/sm/w_data_ipbus[6]_i_1/O net (fo=593, routed) 16.463 25.572 ngFEC/SFP_GEN[8].ngFEC_module/bram_array[2].skip_SFP_SEC.buffer_server/server_din_o_reg[31]_0[22] SLICE_X10Y4 FDRE r ngFEC/SFP_GEN[8].ngFEC_module/bram_array[2].skip_SFP_SEC.buffer_server/server_din_o_reg[22]/D ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 32.000 32.000 r AD6 0.000 32.000 r osc125_a_p (IN) net (fo=0) 0.000 32.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 32.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 32.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 33.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 34.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 36.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -3.847 32.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.078 34.653 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.737 36.473 ngFEC/SFP_GEN[8].ngFEC_module/bram_array[2].skip_SFP_SEC.buffer_server/clk_31_250_bufg SLICE_X10Y4 FDRE r ngFEC/SFP_GEN[8].ngFEC_module/bram_array[2].skip_SFP_SEC.buffer_server/server_din_o_reg[22]/C clock pessimism 1.026 37.499 clock uncertainty -0.069 37.430 SLICE_X10Y4 FDRE (Setup_fdre_C_D) -0.010 37.420 ngFEC/SFP_GEN[8].ngFEC_module/bram_array[2].skip_SFP_SEC.buffer_server/server_din_o_reg[22] ------------------------------------------------------------------- required time 37.420 arrival time -25.572 ------------------------------------------------------------------- slack 11.848 Slack (MET) : 11.855ns (required time - arrival time) Source: sys/ipb/trans/sm/addr_reg[19]/C (rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: ngFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.buffer_server/ram_miso_reg[ipb_rdata][4]/D (rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: clk_ipb_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 32.000ns (clk_ipb_ub rise@32.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 19.935ns (logic 0.560ns (2.809%) route 19.375ns (97.191%)) Logic Levels: 7 (LUT4=2 LUT5=3 LUT6=2) Clock Path Skew: -0.175ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.955ns = ( 35.955 - 32.000 ) Source Clock Delay (SCD): 5.141ns Clock Pessimism Removal (CPR): 1.011ns Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.205 3.654 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.394 5.141 sys/ipb/trans/sm/out SLICE_X82Y138 FDRE r sys/ipb/trans/sm/addr_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X82Y138 FDRE (Prop_fdre_C_Q) 0.259 5.400 r sys/ipb/trans/sm/addr_reg[19]/Q net (fo=746, routed) 14.618 20.018 sys/ipb_from_master[ipb_addr][19] SLICE_X109Y274 LUT5 (Prop_lut5_I1_O) 0.043 20.061 r sys/FSM_sequential_server_ack[1]_i_3__119/O net (fo=56, routed) 0.743 20.804 sys/ngFEC/SFP_GEN[3].ngFEC_module/ram_mosi[14][ipb_addr][18] SLICE_X108Y268 LUT5 (Prop_lut5_I3_O) 0.043 20.847 f sys/FSM_sequential_server_ack[1]_i_8__25/O net (fo=1, routed) 0.255 21.101 sys/FSM_sequential_server_ack[1]_i_8__25_n_0 SLICE_X108Y268 LUT4 (Prop_lut4_I0_O) 0.043 21.144 f sys/FSM_sequential_server_ack[1]_i_7__35/O net (fo=2, routed) 0.444 21.588 sys/FSM_sequential_server_ack[1]_i_7__35_n_0 SLICE_X109Y268 LUT6 (Prop_lut6_I3_O) 0.043 21.631 f sys/ram_miso[ipb_rdata][31]_i_6__21/O net (fo=36, routed) 1.420 23.052 sys/addr_reg[13]_21 SLICE_X113Y278 LUT4 (Prop_lut4_I3_O) 0.043 23.095 r sys/ram_miso[ipb_rdata][31]_i_7__21/O net (fo=30, routed) 1.583 24.678 ngFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.RAM/BRAM_h/ram_miso_reg[ipb_rdata][31]_5 SLICE_X112Y269 LUT6 (Prop_lut6_I5_O) 0.043 24.721 r ngFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.RAM/BRAM_h/ram_miso[ipb_rdata][4]_i_2__35/O net (fo=1, routed) 0.312 25.033 ngFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.RAM/BRAM_h/ram_miso[ipb_rdata][4]_i_2__35_n_0 SLICE_X111Y269 LUT5 (Prop_lut5_I0_O) 0.043 25.076 r ngFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.RAM/BRAM_h/ram_miso[ipb_rdata][4]_i_1__35/O net (fo=1, routed) 0.000 25.076 ngFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.buffer_server/ram_miso_reg[ipb_rdata][31]_2[4] SLICE_X111Y269 FDRE r ngFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.buffer_server/ram_miso_reg[ipb_rdata][4]/D ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 32.000 32.000 r AD6 0.000 32.000 r osc125_a_p (IN) net (fo=0) 0.000 32.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 32.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 32.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 33.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 34.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 36.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -3.847 32.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.078 34.653 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.219 35.955 ngFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.buffer_server/clk_31_250_bufg SLICE_X111Y269 FDRE r ngFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.buffer_server/ram_miso_reg[ipb_rdata][4]/C clock pessimism 1.011 36.966 clock uncertainty -0.069 36.897 SLICE_X111Y269 FDRE (Setup_fdre_C_D) 0.034 36.931 ngFEC/SFP_GEN[3].ngFEC_module/bram_array[14].skip_SFP_SEC.buffer_server/ram_miso_reg[ipb_rdata][4] ------------------------------------------------------------------- required time 36.931 arrival time -25.076 ------------------------------------------------------------------- slack 11.855 Slack (MET) : 11.879ns (required time - arrival time) Source: sys/uc_if/uc_trans/ram_in/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKBWRCLK (rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: ngFEC/SFP_GEN[5].ngFEC_module/bram_array[8].skip_SFP_SEC.control_reg_reg[8][23]/D (rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: clk_ipb_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 32.000ns (clk_ipb_ub rise@32.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 20.348ns (logic 1.929ns (9.480%) route 18.419ns (90.520%)) Logic Levels: 3 (LUT2=1 LUT5=2) Clock Path Skew: 0.262ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.417ns = ( 36.417 - 32.000 ) Source Clock Delay (SCD): 5.180ns Clock Pessimism Removal (CPR): 1.026ns Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.205 3.654 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.434 5.180 sys/uc_if/uc_trans/ram_in/clkb RAMB36_X6Y26 RAMB36E1 r sys/uc_if/uc_trans/ram_in/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKBWRCLK ------------------------------------------------------------------- ------------------- RAMB36_X6Y26 RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[23]) 1.800 6.980 r sys/uc_if/uc_trans/ram_in/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DOBDO[23] net (fo=3, routed) 1.080 8.060 sys/ipb/trans/iface/doutb[23] SLICE_X83Y131 LUT5 (Prop_lut5_I0_O) 0.043 8.103 r sys/ipb/trans/iface/hlen[7]_i_1/O net (fo=8, routed) 0.600 8.703 sys/ipb/trans/sm/rx_data[23] SLICE_X81Y127 LUT5 (Prop_lut5_I4_O) 0.043 8.746 r sys/ipb/trans/sm/w_data_ipbus[7]_i_1/O net (fo=594, routed) 16.739 25.486 sys/rmw_result_reg[31]_11[23] SLICE_X135Y16 LUT2 (Prop_lut2_I0_O) 0.043 25.529 r sys/bram_array[8].skip_SFP_SEC.control_reg[8][23]_i_1__3/O net (fo=1, routed) 0.000 25.529 ngFEC/SFP_GEN[5].ngFEC_module/bram_array[8].skip_SFP_SEC.control_reg_reg[8][31]_0[23] SLICE_X135Y16 FDCE r ngFEC/SFP_GEN[5].ngFEC_module/bram_array[8].skip_SFP_SEC.control_reg_reg[8][23]/D ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 32.000 32.000 r AD6 0.000 32.000 r osc125_a_p (IN) net (fo=0) 0.000 32.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 32.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 32.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 33.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 34.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 36.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -3.847 32.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.078 34.653 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.681 36.417 ngFEC/SFP_GEN[5].ngFEC_module/clk_31_250_bufg SLICE_X135Y16 FDCE r ngFEC/SFP_GEN[5].ngFEC_module/bram_array[8].skip_SFP_SEC.control_reg_reg[8][23]/C clock pessimism 1.026 37.443 clock uncertainty -0.069 37.374 SLICE_X135Y16 FDCE (Setup_fdce_C_D) 0.034 37.408 ngFEC/SFP_GEN[5].ngFEC_module/bram_array[8].skip_SFP_SEC.control_reg_reg[8][23] ------------------------------------------------------------------- required time 37.408 arrival time -25.529 ------------------------------------------------------------------- slack 11.879 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.051ns (arrival time - required time) Source: ngFEC/SFP_GEN[2].ngFEC_module/bram_array[0].skip_SFP_SEC.buffer_server/server_din_o_reg[27]/C (rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: ngFEC/SFP_GEN[2].ngFEC_module/bram_array[0].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/DIADI[11] (rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: clk_ipb_ub Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (clk_ipb_ub rise@0.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 0.628ns (logic 0.178ns (28.360%) route 0.450ns (71.640%)) Logic Levels: 0 Clock Path Skew: 0.050ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 5.052ns Source Clock Delay (SCD): 3.874ns Clock Pessimism Removal (CPR): 1.129ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 1.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 2.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 2.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 4.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -3.847 0.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.078 2.653 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.083 2.736 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.138 3.874 ngFEC/SFP_GEN[2].ngFEC_module/bram_array[0].skip_SFP_SEC.buffer_server/clk_31_250_bufg SLICE_X39Y215 FDRE r ngFEC/SFP_GEN[2].ngFEC_module/bram_array[0].skip_SFP_SEC.buffer_server/server_din_o_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X39Y215 FDRE (Prop_fdre_C_Q) 0.178 4.052 r ngFEC/SFP_GEN[2].ngFEC_module/bram_array[0].skip_SFP_SEC.buffer_server/server_din_o_reg[27]/Q net (fo=2, routed) 0.450 4.501 ngFEC/SFP_GEN[2].ngFEC_module/bram_array[0].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/DIADI[11] RAMB36_X2Y43 RAMB36E1 r ngFEC/SFP_GEN[2].ngFEC_module/bram_array[0].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/DIADI[11] ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.205 3.654 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.306 5.052 ngFEC/SFP_GEN[2].ngFEC_module/bram_array[0].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/clk_31_250_bufg RAMB36_X2Y43 RAMB36E1 r ngFEC/SFP_GEN[2].ngFEC_module/bram_array[0].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/CLKARDCLK clock pessimism -1.129 3.923 RAMB36_X2Y43 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[11]) 0.527 4.450 ngFEC/SFP_GEN[2].ngFEC_module/bram_array[0].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl ------------------------------------------------------------------- required time -4.450 arrival time 4.501 ------------------------------------------------------------------- slack 0.051 Slack (MET) : 0.051ns (arrival time - required time) Source: ngFEC/SFP_GEN[4].ngFEC_module/bram_array[3].skip_SFP_SEC.buffer_server/server_din_o_reg[28]/C (rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: ngFEC/SFP_GEN[4].ngFEC_module/bram_array[3].skip_SFP_SEC.RAM/BRAM_h/ramb_bl.ramb36_dp_bl.ram36_bl/DIADI[28] (rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: clk_ipb_ub Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (clk_ipb_ub rise@0.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 0.627ns (logic 0.206ns (32.873%) route 0.421ns (67.127%)) Logic Levels: 0 Clock Path Skew: 0.049ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 5.272ns Source Clock Delay (SCD): 4.065ns Clock Pessimism Removal (CPR): 1.159ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 1.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 2.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 2.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 4.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -3.847 0.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.078 2.653 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.083 2.736 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.329 4.065 ngFEC/SFP_GEN[4].ngFEC_module/bram_array[3].skip_SFP_SEC.buffer_server/clk_31_250_bufg SLICE_X8Y271 FDRE r ngFEC/SFP_GEN[4].ngFEC_module/bram_array[3].skip_SFP_SEC.buffer_server/server_din_o_reg[28]/C ------------------------------------------------------------------- ------------------- SLICE_X8Y271 FDRE (Prop_fdre_C_Q) 0.206 4.271 r ngFEC/SFP_GEN[4].ngFEC_module/bram_array[3].skip_SFP_SEC.buffer_server/server_din_o_reg[28]/Q net (fo=2, routed) 0.421 4.691 ngFEC/SFP_GEN[4].ngFEC_module/bram_array[3].skip_SFP_SEC.RAM/BRAM_h/DIADI[28] RAMB36_X0Y54 RAMB36E1 r ngFEC/SFP_GEN[4].ngFEC_module/bram_array[3].skip_SFP_SEC.RAM/BRAM_h/ramb_bl.ramb36_dp_bl.ram36_bl/DIADI[28] ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.205 3.654 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.526 5.272 ngFEC/SFP_GEN[4].ngFEC_module/bram_array[3].skip_SFP_SEC.RAM/BRAM_h/clk_31_250_bufg RAMB36_X0Y54 RAMB36E1 r ngFEC/SFP_GEN[4].ngFEC_module/bram_array[3].skip_SFP_SEC.RAM/BRAM_h/ramb_bl.ramb36_dp_bl.ram36_bl/CLKARDCLK clock pessimism -1.159 4.113 RAMB36_X0Y54 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[28]) 0.527 4.640 ngFEC/SFP_GEN[4].ngFEC_module/bram_array[3].skip_SFP_SEC.RAM/BRAM_h/ramb_bl.ramb36_dp_bl.ram36_bl ------------------------------------------------------------------- required time -4.640 arrival time 4.691 ------------------------------------------------------------------- slack 0.051 Slack (MET) : 0.051ns (arrival time - required time) Source: ngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/ngccm_din_reg[4]/C (rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: ngFEC/SFP_GEN[7].ngFEC_module/bram_array[7].skip_SFP_SEC.RAM/BRAM_h/ramb_bl.ramb36_dp_bl.ram36_bl/DIBDI[4] (rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: clk_ipb_ub Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (clk_ipb_ub rise@0.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 0.653ns (logic 0.206ns (31.548%) route 0.447ns (68.452%)) Logic Levels: 0 Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 5.341ns Source Clock Delay (SCD): 4.166ns Clock Pessimism Removal (CPR): 1.101ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 1.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 2.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 2.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 4.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -3.847 0.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.078 2.653 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.083 2.736 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.430 4.166 ngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/clk_31_250_bufg SLICE_X80Y87 FDRE r ngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/ngccm_din_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X80Y87 FDRE (Prop_fdre_C_Q) 0.206 4.372 r ngFEC/SFP_GEN[7].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/ngccm_din_reg[4]/Q net (fo=2, routed) 0.447 4.819 ngFEC/SFP_GEN[7].ngFEC_module/bram_array[7].skip_SFP_SEC.RAM/BRAM_h/ramb_bl.ramb36_dp_bl.ram36_bl_6[4] RAMB36_X5Y17 RAMB36E1 r ngFEC/SFP_GEN[7].ngFEC_module/bram_array[7].skip_SFP_SEC.RAM/BRAM_h/ramb_bl.ramb36_dp_bl.ram36_bl/DIBDI[4] ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.205 3.654 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.595 5.341 ngFEC/SFP_GEN[7].ngFEC_module/bram_array[7].skip_SFP_SEC.RAM/BRAM_h/clk_31_250_bufg RAMB36_X5Y17 RAMB36E1 r ngFEC/SFP_GEN[7].ngFEC_module/bram_array[7].skip_SFP_SEC.RAM/BRAM_h/ramb_bl.ramb36_dp_bl.ram36_bl/CLKBWRCLK clock pessimism -1.101 4.240 RAMB36_X5Y17 RAMB36E1 (Hold_ramb36e1_CLKBWRCLK_DIBDI[4]) 0.527 4.767 ngFEC/SFP_GEN[7].ngFEC_module/bram_array[7].skip_SFP_SEC.RAM/BRAM_h/ramb_bl.ramb36_dp_bl.ram36_bl ------------------------------------------------------------------- required time -4.767 arrival time 4.819 ------------------------------------------------------------------- slack 0.051 Slack (MET) : 0.052ns (arrival time - required time) Source: ngFEC/SFP_GEN[10].ngFEC_module/bram_array[12].skip_SFP_SEC.buffer_server/server_din_o_reg[6]/C (rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: ngFEC/SFP_GEN[10].ngFEC_module/bram_array[12].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/DIADI[6] (rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: clk_ipb_ub Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (clk_ipb_ub rise@0.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 0.632ns (logic 0.178ns (28.160%) route 0.454ns (71.840%)) Logic Levels: 0 Clock Path Skew: 0.054ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 5.236ns Source Clock Delay (SCD): 4.061ns Clock Pessimism Removal (CPR): 1.122ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 1.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 2.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 2.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 4.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -3.847 0.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.078 2.653 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.083 2.736 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.325 4.061 ngFEC/SFP_GEN[10].ngFEC_module/bram_array[12].skip_SFP_SEC.buffer_server/clk_31_250_bufg SLICE_X53Y139 FDRE r ngFEC/SFP_GEN[10].ngFEC_module/bram_array[12].skip_SFP_SEC.buffer_server/server_din_o_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X53Y139 FDRE (Prop_fdre_C_Q) 0.178 4.239 r ngFEC/SFP_GEN[10].ngFEC_module/bram_array[12].skip_SFP_SEC.buffer_server/server_din_o_reg[6]/Q net (fo=2, routed) 0.454 4.693 ngFEC/SFP_GEN[10].ngFEC_module/bram_array[12].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/DIADI[6] RAMB36_X3Y27 RAMB36E1 r ngFEC/SFP_GEN[10].ngFEC_module/bram_array[12].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/DIADI[6] ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.205 3.654 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.490 5.236 ngFEC/SFP_GEN[10].ngFEC_module/bram_array[12].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/clk_31_250_bufg RAMB36_X3Y27 RAMB36E1 r ngFEC/SFP_GEN[10].ngFEC_module/bram_array[12].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/CLKARDCLK clock pessimism -1.122 4.114 RAMB36_X3Y27 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[6]) 0.527 4.641 ngFEC/SFP_GEN[10].ngFEC_module/bram_array[12].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl ------------------------------------------------------------------- required time -4.641 arrival time 4.693 ------------------------------------------------------------------- slack 0.052 Slack (MET) : 0.052ns (arrival time - required time) Source: ngFEC/SFP_GEN[8].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/ngccm_din_reg[14]/C (rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: ngFEC/SFP_GEN[8].ngFEC_module/bram_array[5].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/DIBDI[14] (rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: clk_ipb_ub Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (clk_ipb_ub rise@0.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 0.657ns (logic 0.178ns (27.089%) route 0.479ns (72.911%)) Logic Levels: 0 Clock Path Skew: 0.079ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 5.580ns Source Clock Delay (SCD): 4.399ns Clock Pessimism Removal (CPR): 1.103ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 1.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 2.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 2.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 4.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -3.847 0.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.078 2.653 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.083 2.736 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.663 4.399 ngFEC/SFP_GEN[8].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/clk_31_250_bufg SLICE_X60Y4 FDRE r ngFEC/SFP_GEN[8].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/ngccm_din_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X60Y4 FDRE (Prop_fdre_C_Q) 0.178 4.577 r ngFEC/SFP_GEN[8].ngFEC_module/i2c_comm_gen[5].buffer_ngccm/ngccm_din_reg[14]/Q net (fo=2, routed) 0.479 5.056 ngFEC/SFP_GEN[8].ngFEC_module/bram_array[5].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl_1[14] RAMB36_X3Y2 RAMB36E1 r ngFEC/SFP_GEN[8].ngFEC_module/bram_array[5].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/DIBDI[14] ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.205 3.654 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.834 5.580 ngFEC/SFP_GEN[8].ngFEC_module/bram_array[5].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/clk_31_250_bufg RAMB36_X3Y2 RAMB36E1 r ngFEC/SFP_GEN[8].ngFEC_module/bram_array[5].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/CLKBWRCLK clock pessimism -1.103 4.477 RAMB36_X3Y2 RAMB36E1 (Hold_ramb36e1_CLKBWRCLK_DIBDI[14]) 0.527 5.004 ngFEC/SFP_GEN[8].ngFEC_module/bram_array[5].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl ------------------------------------------------------------------- required time -5.004 arrival time 5.056 ------------------------------------------------------------------- slack 0.052 Slack (MET) : 0.052ns (arrival time - required time) Source: ngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/ngccm_din_reg[24]/C (rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: ngFEC/SFP_GEN[4].ngFEC_module/bram_array[1].skip_SFP_SEC.RAM/BRAM_h/ramb_bl.ramb36_dp_bl.ram36_bl/DIBDI[24] (rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: clk_ipb_ub Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (clk_ipb_ub rise@0.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 0.627ns (logic 0.206ns (32.849%) route 0.421ns (67.151%)) Logic Levels: 0 Clock Path Skew: 0.049ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 5.137ns Source Clock Delay (SCD): 3.932ns Clock Pessimism Removal (CPR): 1.157ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 1.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 2.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 2.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 4.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -3.847 0.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.078 2.653 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.083 2.736 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.196 3.932 ngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/clk_31_250_bufg SLICE_X70Y278 FDRE r ngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/ngccm_din_reg[24]/C ------------------------------------------------------------------- ------------------- SLICE_X70Y278 FDRE (Prop_fdre_C_Q) 0.206 4.138 r ngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/ngccm_din_reg[24]/Q net (fo=2, routed) 0.421 4.559 ngFEC/SFP_GEN[4].ngFEC_module/bram_array[1].skip_SFP_SEC.RAM/BRAM_h/ramb_bl.ramb36_dp_bl.ram36_bl_6[16] RAMB36_X4Y55 RAMB36E1 r ngFEC/SFP_GEN[4].ngFEC_module/bram_array[1].skip_SFP_SEC.RAM/BRAM_h/ramb_bl.ramb36_dp_bl.ram36_bl/DIBDI[24] ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.205 3.654 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.391 5.137 ngFEC/SFP_GEN[4].ngFEC_module/bram_array[1].skip_SFP_SEC.RAM/BRAM_h/clk_31_250_bufg RAMB36_X4Y55 RAMB36E1 r ngFEC/SFP_GEN[4].ngFEC_module/bram_array[1].skip_SFP_SEC.RAM/BRAM_h/ramb_bl.ramb36_dp_bl.ram36_bl/CLKBWRCLK clock pessimism -1.157 3.980 RAMB36_X4Y55 RAMB36E1 (Hold_ramb36e1_CLKBWRCLK_DIBDI[24]) 0.527 4.507 ngFEC/SFP_GEN[4].ngFEC_module/bram_array[1].skip_SFP_SEC.RAM/BRAM_h/ramb_bl.ramb36_dp_bl.ram36_bl ------------------------------------------------------------------- required time -4.507 arrival time 4.559 ------------------------------------------------------------------- slack 0.052 Slack (MET) : 0.052ns (arrival time - required time) Source: ngFEC/SFP_GEN[12].ngFEC_module/bram_array[9].skip_SFP_SEC.buffer_server/server_din_o_reg[25]/C (rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: ngFEC/SFP_GEN[12].ngFEC_module/bram_array[9].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/DIADI[9] (rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: clk_ipb_ub Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (clk_ipb_ub rise@0.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 0.631ns (logic 0.178ns (28.202%) route 0.453ns (71.798%)) Logic Levels: 0 Clock Path Skew: 0.053ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 5.174ns Source Clock Delay (SCD): 4.000ns Clock Pessimism Removal (CPR): 1.122ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 1.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 2.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 2.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 4.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -3.847 0.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.078 2.653 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.083 2.736 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.264 4.000 ngFEC/SFP_GEN[12].ngFEC_module/bram_array[9].skip_SFP_SEC.buffer_server/clk_31_250_bufg SLICE_X71Y105 FDRE r ngFEC/SFP_GEN[12].ngFEC_module/bram_array[9].skip_SFP_SEC.buffer_server/server_din_o_reg[25]/C ------------------------------------------------------------------- ------------------- SLICE_X71Y105 FDRE (Prop_fdre_C_Q) 0.178 4.178 r ngFEC/SFP_GEN[12].ngFEC_module/bram_array[9].skip_SFP_SEC.buffer_server/server_din_o_reg[25]/Q net (fo=2, routed) 0.453 4.631 ngFEC/SFP_GEN[12].ngFEC_module/bram_array[9].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/DIADI[9] RAMB36_X4Y21 RAMB36E1 r ngFEC/SFP_GEN[12].ngFEC_module/bram_array[9].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/DIADI[9] ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.205 3.654 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.428 5.174 ngFEC/SFP_GEN[12].ngFEC_module/bram_array[9].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/clk_31_250_bufg RAMB36_X4Y21 RAMB36E1 r ngFEC/SFP_GEN[12].ngFEC_module/bram_array[9].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/CLKARDCLK clock pessimism -1.122 4.052 RAMB36_X4Y21 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[9]) 0.527 4.579 ngFEC/SFP_GEN[12].ngFEC_module/bram_array[9].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl ------------------------------------------------------------------- required time -4.579 arrival time 4.631 ------------------------------------------------------------------- slack 0.052 Slack (MET) : 0.052ns (arrival time - required time) Source: ngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[6].buffer_ngccm/ngccm_din_reg[8]/C (rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: ngFEC/SFP_GEN[4].ngFEC_module/bram_array[6].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/DIBDI[8] (rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: clk_ipb_ub Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (clk_ipb_ub rise@0.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 0.656ns (logic 0.206ns (31.386%) route 0.450ns (68.614%)) Logic Levels: 0 Clock Path Skew: 0.078ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 5.154ns Source Clock Delay (SCD): 3.943ns Clock Pessimism Removal (CPR): 1.134ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 1.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 2.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 2.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 4.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -3.847 0.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.078 2.653 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.083 2.736 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.207 3.943 ngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[6].buffer_ngccm/clk_31_250_bufg SLICE_X72Y259 FDRE r ngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[6].buffer_ngccm/ngccm_din_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X72Y259 FDRE (Prop_fdre_C_Q) 0.206 4.149 r ngFEC/SFP_GEN[4].ngFEC_module/i2c_comm_gen[6].buffer_ngccm/ngccm_din_reg[8]/Q net (fo=2, routed) 0.450 4.599 ngFEC/SFP_GEN[4].ngFEC_module/bram_array[6].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl_0[8] RAMB36_X4Y51 RAMB36E1 r ngFEC/SFP_GEN[4].ngFEC_module/bram_array[6].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/DIBDI[8] ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.205 3.654 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.408 5.154 ngFEC/SFP_GEN[4].ngFEC_module/bram_array[6].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/clk_31_250_bufg RAMB36_X4Y51 RAMB36E1 r ngFEC/SFP_GEN[4].ngFEC_module/bram_array[6].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/CLKBWRCLK clock pessimism -1.134 4.020 RAMB36_X4Y51 RAMB36E1 (Hold_ramb36e1_CLKBWRCLK_DIBDI[8]) 0.527 4.547 ngFEC/SFP_GEN[4].ngFEC_module/bram_array[6].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl ------------------------------------------------------------------- required time -4.547 arrival time 4.599 ------------------------------------------------------------------- slack 0.052 Slack (MET) : 0.052ns (arrival time - required time) Source: ngFEC/SFP_GEN[8].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/ngccm_din_reg[31]/C (rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: ngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/DIBDI[15] (rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: clk_ipb_ub Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (clk_ipb_ub rise@0.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 0.654ns (logic 0.178ns (27.221%) route 0.476ns (72.779%)) Logic Levels: 0 Clock Path Skew: 0.075ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 5.569ns Source Clock Delay (SCD): 4.392ns Clock Pessimism Removal (CPR): 1.103ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 1.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 2.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 2.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 4.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -3.847 0.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.078 2.653 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.083 2.736 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.656 4.392 ngFEC/SFP_GEN[8].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/clk_31_250_bufg SLICE_X53Y28 FDRE r ngFEC/SFP_GEN[8].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/ngccm_din_reg[31]/C ------------------------------------------------------------------- ------------------- SLICE_X53Y28 FDRE (Prop_fdre_C_Q) 0.178 4.570 r ngFEC/SFP_GEN[8].ngFEC_module/i2c_comm_gen[9].buffer_ngccm/ngccm_din_reg[31]/Q net (fo=2, routed) 0.476 5.045 ngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl_4[7] RAMB36_X3Y4 RAMB36E1 r ngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/DIBDI[15] ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.205 3.654 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.823 5.569 ngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/clk_31_250_bufg RAMB36_X3Y4 RAMB36E1 r ngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/CLKBWRCLK clock pessimism -1.103 4.466 RAMB36_X3Y4 RAMB36E1 (Hold_ramb36e1_CLKBWRCLK_DIBDI[15]) 0.527 4.993 ngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl ------------------------------------------------------------------- required time -4.993 arrival time 5.045 ------------------------------------------------------------------- slack 0.052 Slack (MET) : 0.052ns (arrival time - required time) Source: ngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/ngccm_din_reg[6]/C (rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: ngFEC/SFP_GEN[1].ngFEC_module/bram_array[3].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/DIBDI[6] (rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: clk_ipb_ub Path Type: Hold (Min at Slow Process Corner) Requirement: 0.000ns (clk_ipb_ub rise@0.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 0.596ns (logic 0.189ns (31.711%) route 0.407ns (68.289%)) Logic Levels: 0 Clock Path Skew: 0.083ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 5.014ns Source Clock Delay (SCD): 3.835ns Clock Pessimism Removal (CPR): 1.097ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 1.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 2.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 2.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 4.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -3.847 0.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.078 2.653 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.083 2.736 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.099 3.835 ngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/clk_31_250_bufg SLICE_X98Y189 FDRE r ngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/ngccm_din_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X98Y189 FDRE (Prop_fdre_C_Q) 0.189 4.024 r ngFEC/SFP_GEN[1].ngFEC_module/i2c_comm_gen[3].buffer_ngccm/ngccm_din_reg[6]/Q net (fo=2, routed) 0.407 4.431 ngFEC/SFP_GEN[1].ngFEC_module/bram_array[3].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl_1[6] RAMB36_X6Y37 RAMB36E1 r ngFEC/SFP_GEN[1].ngFEC_module/bram_array[3].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/DIBDI[6] ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.205 3.654 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.268 5.014 ngFEC/SFP_GEN[1].ngFEC_module/bram_array[3].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/clk_31_250_bufg RAMB36_X6Y37 RAMB36E1 r ngFEC/SFP_GEN[1].ngFEC_module/bram_array[3].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/CLKBWRCLK clock pessimism -1.097 3.917 RAMB36_X6Y37 RAMB36E1 (Hold_ramb36e1_CLKBWRCLK_DIBDI[6]) 0.461 4.378 ngFEC/SFP_GEN[1].ngFEC_module/bram_array[3].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl ------------------------------------------------------------------- required time -4.378 arrival time 4.431 ------------------------------------------------------------------- slack 0.052 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: clk_ipb_ub Waveform(ns): { 0.000 16.000 } Period(ns): 32.000 Sources: { sys/clocks/PLLE2_BASE_inst/CLKOUT0 } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a ICAPE2/CLK n/a 10.000 32.000 22.000 ICAP_X0Y1 sys/icap_if/icapInterface/icap/CLK Min Period n/a RAMB36E1/CLKARDCLK n/a 1.839 32.000 30.161 RAMB36_X2Y5 ngFEC/SFP_GEN[8].ngFEC_module/bram_array[12].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 1.839 32.000 30.161 RAMB36_X4Y42 ngFEC/SFP_GEN[2].ngFEC_module/bram_array[11].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/CLKARDCLK Min Period n/a RAMB36E1/CLKBWRCLK n/a 1.839 32.000 30.161 RAMB36_X4Y42 ngFEC/SFP_GEN[2].ngFEC_module/bram_array[11].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/CLKBWRCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 1.839 32.000 30.161 RAMB36_X7Y2 ngFEC/SFP_GEN[5].ngFEC_module/bram_array[9].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/CLKARDCLK Min Period n/a RAMB36E1/CLKBWRCLK n/a 1.839 32.000 30.161 RAMB36_X7Y2 ngFEC/SFP_GEN[5].ngFEC_module/bram_array[9].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/CLKBWRCLK Min Period n/a RAMB36E1/CLKBWRCLK n/a 1.839 32.000 30.161 RAMB36_X2Y5 ngFEC/SFP_GEN[8].ngFEC_module/bram_array[12].skip_SFP_SEC.RAM/bram_gen[1].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/CLKBWRCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 1.839 32.000 30.161 RAMB36_X7Y19 ngFEC/SFP_GEN[11].ngFEC_module/bram_array[8].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/CLKARDCLK Min Period n/a RAMB36E1/CLKBWRCLK n/a 1.839 32.000 30.161 RAMB36_X7Y19 ngFEC/SFP_GEN[11].ngFEC_module/bram_array[8].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/CLKBWRCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 1.839 32.000 30.161 RAMB36_X8Y43 ngFEC/SFP_GEN[1].ngFEC_module/bram_array[1].skip_SFP_SEC.RAM/bram_gen[0].BRAM_l/ramb_bl.ramb36_dp_bl.ram36_bl/CLKARDCLK Max Period n/a PLLE2_ADV/CLKOUT0 n/a 160.000 32.000 128.000 PLLE2_ADV_X0Y1 sys/clocks/PLLE2_BASE_inst/CLKOUT0 Low Pulse Width Slow SRL16E/CLK n/a 0.642 16.000 15.358 SLICE_X174Y258 ngFEC/clk_rate_gen[9].clkRate3/counting_sync2_reg_srl2/CLK Low Pulse Width Slow SRL16E/CLK n/a 0.642 16.000 15.358 SLICE_X170Y262 ngFEC/clk_rate_gen[10].clkRate3/counting_sync2_reg_srl2/CLK Low Pulse Width Slow SRL16E/CLK n/a 0.642 16.000 15.358 SLICE_X170Y262 ngFEC/clk_rate_gen[11].clkRate3/counting_sync2_reg_srl2/CLK Low Pulse Width Slow SRL16E/CLK n/a 0.642 16.000 15.358 SLICE_X170Y262 ngFEC/clk_rate_gen[12].clkRate3/counting_sync2_reg_srl2/CLK Low Pulse Width Slow SRL16E/CLK n/a 0.642 16.000 15.358 SLICE_X174Y116 sys/reset_gen/CLK Low Pulse Width Fast SRL16E/CLK n/a 0.642 16.000 15.358 SLICE_X174Y258 ngFEC/clk_rate_gen[9].clkRate3/counting_sync2_reg_srl2/CLK Low Pulse Width Slow SRL16E/CLK n/a 0.642 16.000 15.358 SLICE_X180Y247 ngFEC/clkRate2/counting_sync2_reg_srl2/CLK Low Pulse Width Slow SRL16E/CLK n/a 0.642 16.000 15.358 SLICE_X178Y260 ngFEC/clk_rate_gen[8].clkRate3/counting_sync2_reg_srl2/CLK Low Pulse Width Fast SRL16E/CLK n/a 0.642 16.000 15.358 SLICE_X178Y260 ngFEC/clk_rate_gen[8].clkRate3/counting_sync2_reg_srl2/CLK Low Pulse Width Slow SRL16E/CLK n/a 0.642 16.000 15.358 SLICE_X130Y296 ngFEC/update_toggle_Sync_Regs_reg[1]_srl2/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 16.000 15.358 SLICE_X178Y260 ngFEC/clk_rate_gen[8].clkRate3/counting_sync2_reg_srl2/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 16.000 15.358 SLICE_X178Y248 ngFEC/clkRate1/counting_sync2_reg_srl2/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 16.000 15.358 SLICE_X178Y260 ngFEC/clk_rate_gen[1].clkRate3/counting_sync2_reg_srl2/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 16.000 15.358 SLICE_X178Y260 ngFEC/clk_rate_gen[2].clkRate3/counting_sync2_reg_srl2/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 16.000 15.358 SLICE_X178Y260 ngFEC/clk_rate_gen[3].clkRate3/counting_sync2_reg_srl2/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 16.000 15.358 SLICE_X178Y260 ngFEC/clk_rate_gen[4].clkRate3/counting_sync2_reg_srl2/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 16.000 15.358 SLICE_X178Y260 ngFEC/clk_rate_gen[5].clkRate3/counting_sync2_reg_srl2/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 16.000 15.358 SLICE_X178Y260 ngFEC/clk_rate_gen[6].clkRate3/counting_sync2_reg_srl2/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 16.000 15.358 SLICE_X178Y260 ngFEC/clk_rate_gen[7].clkRate3/counting_sync2_reg_srl2/CLK High Pulse Width Slow SRL16E/CLK n/a 0.642 16.000 15.358 SLICE_X178Y260 ngFEC/clk_rate_gen[8].clkRate3/counting_sync2_reg_srl2/CLK --------------------------------------------------------------------------------------------------- From Clock: rxWordclkl12_1 To Clock: rxWordclkl12_1 Setup : 0 Failing Endpoints, Worst Slack 3.677ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.093ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.458ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.677ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[25]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_1 rise@8.200ns - rxWordclkl12_1 rise@0.000ns) Data Path Delay: 4.109ns (logic 1.103ns (26.846%) route 3.006ns (73.154%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.282ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.639ns = ( 8.839 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.921 0.921 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[1]) 1.009 1.930 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[1] net (fo=13, routed) 2.178 4.109 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gt0_rxdata_out[1] SLICE_X146Y359 LUT5 (Prop_lut5_I4_O) 0.043 4.152 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[89]_i_2/O net (fo=6, routed) 0.553 4.705 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[89]_i_2_n_0 SLICE_X144Y360 LUT4 (Prop_lut4_I3_O) 0.051 4.756 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[25]_i_1/O net (fo=1, routed) 0.275 5.030 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[21] SLICE_X144Y359 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[25]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 8.200 8.200 r BUFHCE_X1Y84 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.639 8.839 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X144Y359 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[25]/C clock pessimism 0.000 8.839 clock uncertainty -0.035 8.804 SLICE_X144Y359 FDCE (Setup_fdce_C_D) -0.097 8.707 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[25] ------------------------------------------------------------------- required time 8.707 arrival time -5.030 ------------------------------------------------------------------- slack 3.677 Slack (MET) : 3.697ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[29]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_1 rise@8.200ns - rxWordclkl12_1 rise@0.000ns) Data Path Delay: 4.066ns (logic 1.211ns (29.783%) route 2.855ns (70.217%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.276ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.645ns = ( 8.845 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.921 0.921 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[1]) 1.009 1.930 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[1] net (fo=13, routed) 1.932 3.863 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gt0_rxdata_out[1] SLICE_X152Y360 LUT5 (Prop_lut5_I0_O) 0.054 3.917 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[93]_i_2/O net (fo=6, routed) 0.551 4.468 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[93]_i_2_n_0 SLICE_X151Y358 LUT4 (Prop_lut4_I1_O) 0.148 4.616 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[29]_i_1/O net (fo=1, routed) 0.372 4.988 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[25] SLICE_X152Y358 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[29]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 8.200 8.200 r BUFHCE_X1Y84 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.645 8.845 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X152Y358 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[29]/C clock pessimism 0.000 8.845 clock uncertainty -0.035 8.810 SLICE_X152Y358 FDCE (Setup_fdce_C_D) -0.125 8.685 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[29] ------------------------------------------------------------------- required time 8.685 arrival time -4.988 ------------------------------------------------------------------- slack 3.697 Slack (MET) : 3.707ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[93]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_1 rise@8.200ns - rxWordclkl12_1 rise@0.000ns) Data Path Delay: 4.079ns (logic 1.211ns (29.692%) route 2.868ns (70.308%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.275ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.646ns = ( 8.846 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.921 0.921 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[1]) 1.009 1.930 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[1] net (fo=13, routed) 1.932 3.863 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gt0_rxdata_out[1] SLICE_X152Y360 LUT5 (Prop_lut5_I0_O) 0.054 3.917 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[93]_i_2/O net (fo=6, routed) 0.564 4.480 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[93]_i_2_n_0 SLICE_X153Y358 LUT4 (Prop_lut4_I1_O) 0.148 4.628 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[93]_i_1/O net (fo=1, routed) 0.372 5.000 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[89] SLICE_X154Y357 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[93]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 8.200 8.200 r BUFHCE_X1Y84 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.646 8.846 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X154Y357 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[93]/C clock pessimism 0.000 8.846 clock uncertainty -0.035 8.811 SLICE_X154Y357 FDCE (Setup_fdce_C_D) -0.104 8.707 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[93] ------------------------------------------------------------------- required time 8.707 arrival time -5.000 ------------------------------------------------------------------- slack 3.707 Slack (MET) : 3.748ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[89]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_1 rise@8.200ns - rxWordclkl12_1 rise@0.000ns) Data Path Delay: 4.029ns (logic 1.107ns (27.479%) route 2.922ns (72.521%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.284ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.637ns = ( 8.837 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.921 0.921 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[1]) 1.009 1.930 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[1] net (fo=13, routed) 2.178 4.109 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gt0_rxdata_out[1] SLICE_X146Y359 LUT5 (Prop_lut5_I4_O) 0.043 4.152 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[89]_i_2/O net (fo=6, routed) 0.550 4.702 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[89]_i_2_n_0 SLICE_X143Y358 LUT4 (Prop_lut4_I3_O) 0.055 4.757 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[89]_i_1/O net (fo=1, routed) 0.193 4.950 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[85] SLICE_X142Y358 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[89]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 8.200 8.200 r BUFHCE_X1Y84 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.637 8.837 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X142Y358 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[89]/C clock pessimism 0.000 8.837 clock uncertainty -0.035 8.802 SLICE_X142Y358 FDCE (Setup_fdce_C_D) -0.104 8.698 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[89] ------------------------------------------------------------------- required time 8.698 arrival time -4.950 ------------------------------------------------------------------- slack 3.748 Slack (MET) : 3.750ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[72]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_1 rise@8.200ns - rxWordclkl12_1 rise@0.000ns) Data Path Delay: 4.194ns (logic 1.201ns (28.637%) route 2.993ns (71.363%)) Logic Levels: 2 (LUT3=1 LUT6=1) Clock Path Skew: -0.284ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.637ns = ( 8.837 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.921 0.921 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[0]) 1.009 1.930 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[0] net (fo=13, routed) 2.066 3.996 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gt0_rxdata_out[0] SLICE_X147Y358 LUT3 (Prop_lut3_I0_O) 0.055 4.051 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[96]_i_4/O net (fo=5, routed) 0.927 4.978 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[96]_i_4_n_0 SLICE_X144Y361 LUT6 (Prop_lut6_I5_O) 0.137 5.115 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[72]_i_1/O net (fo=1, routed) 0.000 5.115 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[68] SLICE_X144Y361 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[72]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 8.200 8.200 r BUFHCE_X1Y84 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.637 8.837 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X144Y361 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[72]/C clock pessimism 0.000 8.837 clock uncertainty -0.035 8.802 SLICE_X144Y361 FDCE (Setup_fdce_C_D) 0.064 8.866 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[72] ------------------------------------------------------------------- required time 8.866 arrival time -5.115 ------------------------------------------------------------------- slack 3.750 Slack (MET) : 3.777ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[88]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_1 rise@8.200ns - rxWordclkl12_1 rise@0.000ns) Data Path Delay: 4.008ns (logic 1.103ns (27.519%) route 2.905ns (72.481%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.284ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.637ns = ( 8.837 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.921 0.921 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[14]) 1.009 1.930 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[14] net (fo=8, routed) 2.011 3.941 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gt0_rxdata_out[16] SLICE_X147Y360 LUT5 (Prop_lut5_I0_O) 0.043 3.984 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[88]_i_2/O net (fo=6, routed) 0.674 4.658 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[88]_i_2_n_0 SLICE_X143Y358 LUT4 (Prop_lut4_I3_O) 0.051 4.709 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[88]_i_1/O net (fo=1, routed) 0.220 4.930 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[84] SLICE_X142Y358 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[88]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 8.200 8.200 r BUFHCE_X1Y84 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.637 8.837 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X142Y358 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[88]/C clock pessimism 0.000 8.837 clock uncertainty -0.035 8.802 SLICE_X142Y358 FDCE (Setup_fdce_C_D) -0.095 8.707 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[88] ------------------------------------------------------------------- required time 8.707 arrival time -4.930 ------------------------------------------------------------------- slack 3.777 Slack (MET) : 3.779ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[60]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_1 rise@8.200ns - rxWordclkl12_1 rise@0.000ns) Data Path Delay: 3.994ns (logic 1.204ns (30.143%) route 2.790ns (69.857%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.276ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.645ns = ( 8.845 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.921 0.921 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[0]) 1.009 1.930 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[0] net (fo=13, routed) 1.760 3.690 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gt0_rxdata_out[0] SLICE_X152Y360 LUT5 (Prop_lut5_I0_O) 0.051 3.741 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[92]_i_2/O net (fo=6, routed) 0.631 4.372 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[92]_i_2_n_0 SLICE_X149Y359 LUT4 (Prop_lut4_I1_O) 0.144 4.516 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[60]_i_1/O net (fo=1, routed) 0.400 4.916 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[56] SLICE_X151Y356 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[60]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 8.200 8.200 r BUFHCE_X1Y84 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.645 8.845 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X151Y356 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[60]/C clock pessimism 0.000 8.845 clock uncertainty -0.035 8.810 SLICE_X151Y356 FDCE (Setup_fdce_C_D) -0.115 8.695 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[60] ------------------------------------------------------------------- required time 8.695 arrival time -4.916 ------------------------------------------------------------------- slack 3.779 Slack (MET) : 3.787ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[61]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_1 rise@8.200ns - rxWordclkl12_1 rise@0.000ns) Data Path Delay: 4.001ns (logic 1.206ns (30.142%) route 2.795ns (69.858%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.278ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.643ns = ( 8.843 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.921 0.921 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[1]) 1.009 1.930 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[1] net (fo=13, routed) 1.932 3.863 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gt0_rxdata_out[1] SLICE_X152Y360 LUT5 (Prop_lut5_I0_O) 0.054 3.917 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[93]_i_2/O net (fo=6, routed) 0.547 4.463 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[93]_i_2_n_0 SLICE_X152Y363 LUT4 (Prop_lut4_I1_O) 0.143 4.606 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[61]_i_1/O net (fo=1, routed) 0.316 4.923 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[57] SLICE_X153Y362 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[61]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 8.200 8.200 r BUFHCE_X1Y84 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.643 8.843 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X153Y362 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[61]/C clock pessimism 0.000 8.843 clock uncertainty -0.035 8.808 SLICE_X153Y362 FDCE (Setup_fdce_C_D) -0.098 8.710 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[61] ------------------------------------------------------------------- required time 8.710 arrival time -4.923 ------------------------------------------------------------------- slack 3.787 Slack (MET) : 3.822ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[26]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_1 rise@8.200ns - rxWordclkl12_1 rise@0.000ns) Data Path Delay: 3.937ns (logic 1.098ns (27.890%) route 2.839ns (72.110%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.285ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.636ns = ( 8.836 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.921 0.921 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[2]) 1.009 1.930 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[2] net (fo=13, routed) 1.818 3.749 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gt0_rxdata_out[2] SLICE_X148Y358 LUT5 (Prop_lut5_I4_O) 0.043 3.792 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[90]_i_2/O net (fo=6, routed) 0.701 4.493 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[90]_i_2_n_0 SLICE_X144Y360 LUT4 (Prop_lut4_I3_O) 0.046 4.539 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[26]_i_1/O net (fo=1, routed) 0.320 4.858 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[22] SLICE_X143Y360 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[26]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 8.200 8.200 r BUFHCE_X1Y84 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.636 8.836 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X143Y360 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[26]/C clock pessimism 0.000 8.836 clock uncertainty -0.035 8.801 SLICE_X143Y360 FDCE (Setup_fdce_C_D) -0.120 8.681 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[26] ------------------------------------------------------------------- required time 8.681 arrival time -4.858 ------------------------------------------------------------------- slack 3.822 Slack (MET) : 3.871ns (required time - arrival time) Source: ngFEC/SFP_GEN[2].ngCCM_gbt/test_comm_cnt2_reg[15]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[2].ngCCM_gbt/ngCCM_status_counter_o_reg[4][5]/CE (rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_1 rise@8.200ns - rxWordclkl12_1 rise@0.000ns) Data Path Delay: 4.134ns (logic 0.266ns (6.434%) route 3.868ns (93.566%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.018ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.631ns = ( 8.831 - 8.200 ) Source Clock Delay (SCD): 0.613ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.613 0.613 ngFEC/SFP_GEN[2].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X127Y369 FDCE r ngFEC/SFP_GEN[2].ngCCM_gbt/test_comm_cnt2_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X127Y369 FDCE (Prop_fdce_C_Q) 0.223 0.836 r ngFEC/SFP_GEN[2].ngCCM_gbt/test_comm_cnt2_reg[15]/Q net (fo=154, routed) 1.600 2.436 ngFEC/SFP_GEN[2].ngCCM_gbt/test_comm_cnt2_reg[15] SLICE_X130Y350 LUT2 (Prop_lut2_I0_O) 0.043 2.479 r ngFEC/SFP_GEN[2].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__5/O net (fo=128, routed) 2.268 4.747 ngFEC/SFP_GEN[2].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__5_n_0 SLICE_X132Y358 FDRE r ngFEC/SFP_GEN[2].ngCCM_gbt/ngCCM_status_counter_o_reg[4][5]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 8.200 8.200 r BUFHCE_X1Y84 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.631 8.831 ngFEC/SFP_GEN[2].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X132Y358 FDRE r ngFEC/SFP_GEN[2].ngCCM_gbt/ngCCM_status_counter_o_reg[4][5]/C clock pessimism 0.000 8.831 clock uncertainty -0.035 8.796 SLICE_X132Y358 FDRE (Setup_fdre_C_CE) -0.178 8.618 ngFEC/SFP_GEN[2].ngCCM_gbt/ngCCM_status_counter_o_reg[4][5] ------------------------------------------------------------------- required time 8.618 arrival time -4.747 ------------------------------------------------------------------- slack 3.871 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.093ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_1 rise@0.000ns - rxWordclkl12_1 rise@0.000ns) Data Path Delay: 0.191ns (logic 0.128ns (66.970%) route 0.063ns (33.030%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.493ns Source Clock Delay (SCD): 0.340ns Clock Pessimism Removal (CPR): 0.142ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.340 0.340 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X137Y364 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X137Y364 FDCE (Prop_fdce_C_Q) 0.100 0.440 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[14]/Q net (fo=2, routed) 0.063 0.503 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_27_in SLICE_X136Y364 LUT3 (Prop_lut3_I0_O) 0.028 0.531 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1/O net (fo=1, routed) 0.000 0.531 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[14] SLICE_X136Y364 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.493 0.493 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X136Y364 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C clock pessimism -0.142 0.351 SLICE_X136Y364 FDRE (Hold_fdre_C_D) 0.087 0.438 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14] ------------------------------------------------------------------- required time -0.438 arrival time 0.531 ------------------------------------------------------------------- slack 0.093 Slack (MET) : 0.101ns (arrival time - required time) Source: ngFEC/SFP_GEN[2].ngCCM_gbt/CrossClock_DV_cnt/shiftA_reg[2]/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[2].ngCCM_gbt/CrossClock_DV_cnt/strbAtoB_o_reg/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_1 rise@0.000ns - rxWordclkl12_1 rise@0.000ns) Data Path Delay: 0.199ns (logic 0.128ns (64.468%) route 0.071ns (35.532%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.499ns Source Clock Delay (SCD): 0.345ns Clock Pessimism Removal (CPR): 0.143ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.345 0.345 ngFEC/SFP_GEN[2].ngCCM_gbt/CrossClock_DV_cnt/MGT_RXUSRCLK_o[0] SLICE_X137Y351 FDRE r ngFEC/SFP_GEN[2].ngCCM_gbt/CrossClock_DV_cnt/shiftA_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X137Y351 FDRE (Prop_fdre_C_Q) 0.100 0.445 f ngFEC/SFP_GEN[2].ngCCM_gbt/CrossClock_DV_cnt/shiftA_reg[2]/Q net (fo=3, routed) 0.071 0.516 ngFEC/SFP_GEN[2].ngCCM_gbt/CrossClock_DV_cnt/shiftA_reg[2]_0[1] SLICE_X136Y351 LUT2 (Prop_lut2_I1_O) 0.028 0.544 r ngFEC/SFP_GEN[2].ngCCM_gbt/CrossClock_DV_cnt/strbAtoB_o_i_1__5/O net (fo=1, routed) 0.000 0.544 ngFEC/SFP_GEN[2].ngCCM_gbt/CrossClock_DV_cnt/strbAtoB_o0 SLICE_X136Y351 FDRE r ngFEC/SFP_GEN[2].ngCCM_gbt/CrossClock_DV_cnt/strbAtoB_o_reg/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.499 0.499 ngFEC/SFP_GEN[2].ngCCM_gbt/CrossClock_DV_cnt/MGT_RXUSRCLK_o[0] SLICE_X136Y351 FDRE r ngFEC/SFP_GEN[2].ngCCM_gbt/CrossClock_DV_cnt/strbAtoB_o_reg/C clock pessimism -0.143 0.356 SLICE_X136Y351 FDRE (Hold_fdre_C_D) 0.087 0.443 ngFEC/SFP_GEN[2].ngCCM_gbt/CrossClock_DV_cnt/strbAtoB_o_reg ------------------------------------------------------------------- required time -0.443 arrival time 0.544 ------------------------------------------------------------------- slack 0.101 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_1 rise@0.000ns - rxWordclkl12_1 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.537ns Source Clock Delay (SCD): 0.382ns Clock Pessimism Removal (CPR): 0.155ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.382 0.382 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in SLICE_X185Y362 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X185Y362 FDRE (Prop_fdre_C_Q) 0.100 0.482 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q net (fo=1, routed) 0.055 0.537 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync1 SLICE_X185Y362 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.537 0.537 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in SLICE_X185Y362 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C clock pessimism -0.155 0.382 SLICE_X185Y362 FDRE (Hold_fdre_C_D) 0.047 0.429 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.429 arrival time 0.537 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_1 rise@0.000ns - rxWordclkl12_1 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.540ns Source Clock Delay (SCD): 0.384ns Clock Pessimism Removal (CPR): 0.156ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.384 0.384 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/gt0_rxusrclk_in SLICE_X187Y359 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X187Y359 FDRE (Prop_fdre_C_Q) 0.100 0.484 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/Q net (fo=1, routed) 0.055 0.539 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync1 SLICE_X187Y359 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.540 0.540 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/gt0_rxusrclk_in SLICE_X187Y359 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/C clock pessimism -0.156 0.384 SLICE_X187Y359 FDRE (Hold_fdre_C_D) 0.047 0.431 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.431 arrival time 0.539 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.111ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_1 rise@0.000ns - rxWordclkl12_1 rise@0.000ns) Data Path Delay: 0.209ns (logic 0.128ns (61.382%) route 0.081ns (38.618%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.495ns Source Clock Delay (SCD): 0.341ns Clock Pessimism Removal (CPR): 0.143ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.341 0.341 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X143Y364 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X143Y364 FDCE (Prop_fdce_C_Q) 0.100 0.441 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[0]/Q net (fo=1, routed) 0.081 0.522 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[0] SLICE_X142Y364 LUT3 (Prop_lut3_I0_O) 0.028 0.550 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1/O net (fo=1, routed) 0.000 0.550 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[0] SLICE_X142Y364 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.495 0.495 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X142Y364 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C clock pessimism -0.143 0.352 SLICE_X142Y364 FDRE (Hold_fdre_C_D) 0.087 0.439 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[0] ------------------------------------------------------------------- required time -0.439 arrival time 0.550 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.113ns (arrival time - required time) Source: ngFEC/SFP_GEN[2].rx_data_reg[2][51]/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[50]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_1 rise@0.000ns - rxWordclkl12_1 rise@0.000ns) Data Path Delay: 0.211ns (logic 0.128ns (60.799%) route 0.083ns (39.201%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.492ns Source Clock Delay (SCD): 0.340ns Clock Pessimism Removal (CPR): 0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.340 0.340 ngFEC/RX_WORDCLK_O[1] SLICE_X139Y365 FDRE r ngFEC/SFP_GEN[2].rx_data_reg[2][51]/C ------------------------------------------------------------------- ------------------- SLICE_X139Y365 FDRE (Prop_fdre_C_Q) 0.100 0.440 r ngFEC/SFP_GEN[2].rx_data_reg[2][51]/Q net (fo=1, routed) 0.083 0.523 ngFEC/gbtbank1_l12_118/RX_Word_rx40_reg[78]_1[35] SLICE_X138Y365 LUT3 (Prop_lut3_I0_O) 0.028 0.551 r ngFEC/gbtbank1_l12_118/RX_Word_rx40[50]_i_1__8/O net (fo=1, routed) 0.000 0.551 ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[83]_0[33] SLICE_X138Y365 FDCE r ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[50]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.492 0.492 ngFEC/SFP_GEN[2].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X138Y365 FDCE r ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[50]/C clock pessimism -0.141 0.351 SLICE_X138Y365 FDCE (Hold_fdce_C_D) 0.087 0.438 ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[50] ------------------------------------------------------------------- required time -0.438 arrival time 0.551 ------------------------------------------------------------------- slack 0.113 Slack (MET) : 0.118ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_1 rise@0.000ns - rxWordclkl12_1 rise@0.000ns) Data Path Delay: 0.216ns (logic 0.128ns (59.307%) route 0.088ns (40.693%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.489ns Source Clock Delay (SCD): 0.335ns Clock Pessimism Removal (CPR): 0.143ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.335 0.335 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X133Y364 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X133Y364 FDCE (Prop_fdce_C_Q) 0.100 0.435 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/Q net (fo=2, routed) 0.088 0.523 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_29_in SLICE_X132Y364 LUT3 (Prop_lut3_I0_O) 0.028 0.551 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1/O net (fo=1, routed) 0.000 0.551 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[15] SLICE_X132Y364 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.489 0.489 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X132Y364 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C clock pessimism -0.143 0.346 SLICE_X132Y364 FDRE (Hold_fdre_C_D) 0.087 0.433 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15] ------------------------------------------------------------------- required time -0.433 arrival time 0.551 ------------------------------------------------------------------- slack 0.118 Slack (MET) : 0.118ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_1 rise@0.000ns - rxWordclkl12_1 rise@0.000ns) Data Path Delay: 0.216ns (logic 0.128ns (59.307%) route 0.088ns (40.693%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.459ns Source Clock Delay (SCD): 0.306ns Clock Pessimism Removal (CPR): 0.142ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.306 0.306 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X131Y364 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X131Y364 FDCE (Prop_fdce_C_Q) 0.100 0.406 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Q net (fo=2, routed) 0.088 0.494 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_33_in SLICE_X130Y364 LUT3 (Prop_lut3_I0_O) 0.028 0.522 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1/O net (fo=1, routed) 0.000 0.522 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[17] SLICE_X130Y364 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.459 0.459 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X130Y364 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C clock pessimism -0.142 0.317 SLICE_X130Y364 FDRE (Hold_fdre_C_D) 0.087 0.404 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17] ------------------------------------------------------------------- required time -0.404 arrival time 0.522 ------------------------------------------------------------------- slack 0.118 Slack (MET) : 0.119ns (arrival time - required time) Source: ngFEC/SFP_GEN[2].ngCCM_gbt/ngCCM_status_counter_reg[7][14]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[2].ngCCM_gbt/ngCCM_status_counter_o_reg[7][14]/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_1 rise@0.000ns - rxWordclkl12_1 rise@0.000ns) Data Path Delay: 0.190ns (logic 0.100ns (52.595%) route 0.090ns (47.405%)) Logic Levels: 0 Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.462ns Source Clock Delay (SCD): 0.308ns Clock Pessimism Removal (CPR): 0.143ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.308 0.308 ngFEC/SFP_GEN[2].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X131Y360 FDCE r ngFEC/SFP_GEN[2].ngCCM_gbt/ngCCM_status_counter_reg[7][14]/C ------------------------------------------------------------------- ------------------- SLICE_X131Y360 FDCE (Prop_fdce_C_Q) 0.100 0.408 r ngFEC/SFP_GEN[2].ngCCM_gbt/ngCCM_status_counter_reg[7][14]/Q net (fo=2, routed) 0.090 0.498 ngFEC/SFP_GEN[2].ngCCM_gbt/ngCCM_status_counter_reg_n_0_[7][14] SLICE_X130Y360 FDRE r ngFEC/SFP_GEN[2].ngCCM_gbt/ngCCM_status_counter_o_reg[7][14]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.462 0.462 ngFEC/SFP_GEN[2].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X130Y360 FDRE r ngFEC/SFP_GEN[2].ngCCM_gbt/ngCCM_status_counter_o_reg[7][14]/C clock pessimism -0.143 0.319 SLICE_X130Y360 FDRE (Hold_fdre_C_D) 0.060 0.379 ngFEC/SFP_GEN[2].ngCCM_gbt/ngCCM_status_counter_o_reg[7][14] ------------------------------------------------------------------- required time -0.379 arrival time 0.498 ------------------------------------------------------------------- slack 0.119 Slack (MET) : 0.121ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_1 rise@0.000ns - rxWordclkl12_1 rise@0.000ns) Data Path Delay: 0.219ns (logic 0.128ns (58.431%) route 0.091ns (41.569%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.495ns Source Clock Delay (SCD): 0.341ns Clock Pessimism Removal (CPR): 0.143ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.341 0.341 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X143Y364 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X143Y364 FDCE (Prop_fdce_C_Q) 0.100 0.441 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[8]/Q net (fo=2, routed) 0.091 0.532 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_15_in SLICE_X142Y364 LUT3 (Prop_lut3_I0_O) 0.028 0.560 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[8]_i_1/O net (fo=1, routed) 0.000 0.560 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[8] SLICE_X142Y364 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.495 0.495 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X142Y364 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C clock pessimism -0.143 0.352 SLICE_X142Y364 FDRE (Hold_fdre_C_D) 0.087 0.439 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[8] ------------------------------------------------------------------- required time -0.439 arrival time 0.560 ------------------------------------------------------------------- slack 0.121 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: rxWordclkl12_1 Waveform(ns): { 0.000 4.100 } Period(ns): 8.200 Sources: { ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/RXUSRCLK n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y28 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK Min Period n/a GTXE2_CHANNEL/RXUSRCLK2 n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y28 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X155Y362 ngFEC/gbtbank1_l12_118/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X155Y362 ngFEC/gbtbank1_l12_118/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X144Y355 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X149Y362 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X149Y362 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X148Y364 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X148Y364 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X147Y364 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C Low Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X154Y369 ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK Low Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X154Y369 ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X148Y364 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X148Y364 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X147Y364 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X147Y364 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X147Y364 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X147Y364 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X147Y364 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X147Y364 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C High Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X154Y369 ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X154Y369 ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X155Y362 ngFEC/gbtbank1_l12_118/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X155Y362 ngFEC/gbtbank1_l12_118/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X155Y362 ngFEC/gbtbank1_l12_118/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X154Y362 ngFEC/gbtbank1_l12_118/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X155Y362 ngFEC/gbtbank1_l12_118/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X155Y362 ngFEC/gbtbank1_l12_118/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][5]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X148Y362 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X148Y362 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C --------------------------------------------------------------------------------------------------- From Clock: rxWordclkl12_2 To Clock: rxWordclkl12_2 Setup : 0 Failing Endpoints, Worst Slack 2.628ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.085ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.458ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.628ns (required time - arrival time) Source: ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][24]/CE (rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_2 rise@8.200ns - rxWordclkl12_2 rise@0.000ns) Data Path Delay: 5.299ns (logic 0.302ns (5.699%) route 4.997ns (94.301%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.037ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.645ns = ( 8.845 - 8.200 ) Source Clock Delay (SCD): 0.682ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.682 0.682 ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X144Y366 FDCE r ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X144Y366 FDCE (Prop_fdce_C_Q) 0.259 0.941 r ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/Q net (fo=154, routed) 2.545 3.486 ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15] SLICE_X127Y352 LUT2 (Prop_lut2_I0_O) 0.043 3.529 r ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4/O net (fo=128, routed) 2.452 5.981 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4_n_0 SLICE_X148Y357 FDRE r ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][24]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 8.200 8.200 r BUFHCE_X1Y85 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.645 8.845 ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X148Y357 FDRE r ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][24]/C clock pessimism 0.000 8.845 clock uncertainty -0.035 8.810 SLICE_X148Y357 FDRE (Setup_fdre_C_CE) -0.201 8.609 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][24] ------------------------------------------------------------------- required time 8.609 arrival time -5.981 ------------------------------------------------------------------- slack 2.628 Slack (MET) : 2.724ns (required time - arrival time) Source: ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][21]/CE (rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_2 rise@8.200ns - rxWordclkl12_2 rise@0.000ns) Data Path Delay: 5.204ns (logic 0.302ns (5.804%) route 4.902ns (94.196%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.036ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.646ns = ( 8.846 - 8.200 ) Source Clock Delay (SCD): 0.682ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.682 0.682 ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X144Y366 FDCE r ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X144Y366 FDCE (Prop_fdce_C_Q) 0.259 0.941 r ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/Q net (fo=154, routed) 2.545 3.486 ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15] SLICE_X127Y352 LUT2 (Prop_lut2_I0_O) 0.043 3.529 r ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4/O net (fo=128, routed) 2.357 5.886 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4_n_0 SLICE_X148Y355 FDRE r ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][21]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 8.200 8.200 r BUFHCE_X1Y85 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.646 8.846 ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X148Y355 FDRE r ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][21]/C clock pessimism 0.000 8.846 clock uncertainty -0.035 8.811 SLICE_X148Y355 FDRE (Setup_fdre_C_CE) -0.201 8.610 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][21] ------------------------------------------------------------------- required time 8.610 arrival time -5.886 ------------------------------------------------------------------- slack 2.724 Slack (MET) : 2.724ns (required time - arrival time) Source: ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][25]/CE (rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_2 rise@8.200ns - rxWordclkl12_2 rise@0.000ns) Data Path Delay: 5.204ns (logic 0.302ns (5.804%) route 4.902ns (94.196%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.036ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.646ns = ( 8.846 - 8.200 ) Source Clock Delay (SCD): 0.682ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.682 0.682 ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X144Y366 FDCE r ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X144Y366 FDCE (Prop_fdce_C_Q) 0.259 0.941 r ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/Q net (fo=154, routed) 2.545 3.486 ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15] SLICE_X127Y352 LUT2 (Prop_lut2_I0_O) 0.043 3.529 r ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4/O net (fo=128, routed) 2.357 5.886 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4_n_0 SLICE_X148Y355 FDRE r ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][25]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 8.200 8.200 r BUFHCE_X1Y85 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.646 8.846 ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X148Y355 FDRE r ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][25]/C clock pessimism 0.000 8.846 clock uncertainty -0.035 8.811 SLICE_X148Y355 FDRE (Setup_fdre_C_CE) -0.201 8.610 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][25] ------------------------------------------------------------------- required time 8.610 arrival time -5.886 ------------------------------------------------------------------- slack 2.724 Slack (MET) : 2.724ns (required time - arrival time) Source: ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][27]/CE (rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_2 rise@8.200ns - rxWordclkl12_2 rise@0.000ns) Data Path Delay: 5.204ns (logic 0.302ns (5.804%) route 4.902ns (94.196%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.036ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.646ns = ( 8.846 - 8.200 ) Source Clock Delay (SCD): 0.682ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.682 0.682 ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X144Y366 FDCE r ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X144Y366 FDCE (Prop_fdce_C_Q) 0.259 0.941 r ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/Q net (fo=154, routed) 2.545 3.486 ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15] SLICE_X127Y352 LUT2 (Prop_lut2_I0_O) 0.043 3.529 r ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4/O net (fo=128, routed) 2.357 5.886 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4_n_0 SLICE_X148Y355 FDRE r ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][27]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 8.200 8.200 r BUFHCE_X1Y85 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.646 8.846 ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X148Y355 FDRE r ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][27]/C clock pessimism 0.000 8.846 clock uncertainty -0.035 8.811 SLICE_X148Y355 FDRE (Setup_fdre_C_CE) -0.201 8.610 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][27] ------------------------------------------------------------------- required time 8.610 arrival time -5.886 ------------------------------------------------------------------- slack 2.724 Slack (MET) : 2.724ns (required time - arrival time) Source: ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][29]/CE (rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_2 rise@8.200ns - rxWordclkl12_2 rise@0.000ns) Data Path Delay: 5.204ns (logic 0.302ns (5.804%) route 4.902ns (94.196%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.036ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.646ns = ( 8.846 - 8.200 ) Source Clock Delay (SCD): 0.682ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.682 0.682 ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X144Y366 FDCE r ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X144Y366 FDCE (Prop_fdce_C_Q) 0.259 0.941 r ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/Q net (fo=154, routed) 2.545 3.486 ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15] SLICE_X127Y352 LUT2 (Prop_lut2_I0_O) 0.043 3.529 r ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4/O net (fo=128, routed) 2.357 5.886 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4_n_0 SLICE_X148Y355 FDRE r ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][29]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 8.200 8.200 r BUFHCE_X1Y85 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.646 8.846 ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X148Y355 FDRE r ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][29]/C clock pessimism 0.000 8.846 clock uncertainty -0.035 8.811 SLICE_X148Y355 FDRE (Setup_fdre_C_CE) -0.201 8.610 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][29] ------------------------------------------------------------------- required time 8.610 arrival time -5.886 ------------------------------------------------------------------- slack 2.724 Slack (MET) : 2.768ns (required time - arrival time) Source: ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][23]/CE (rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_2 rise@8.200ns - rxWordclkl12_2 rise@0.000ns) Data Path Delay: 5.157ns (logic 0.302ns (5.856%) route 4.855ns (94.144%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.039ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.643ns = ( 8.843 - 8.200 ) Source Clock Delay (SCD): 0.682ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.682 0.682 ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X144Y366 FDCE r ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X144Y366 FDCE (Prop_fdce_C_Q) 0.259 0.941 r ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/Q net (fo=154, routed) 2.545 3.486 ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15] SLICE_X127Y352 LUT2 (Prop_lut2_I0_O) 0.043 3.529 r ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4/O net (fo=128, routed) 2.310 5.839 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4_n_0 SLICE_X147Y353 FDRE r ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][23]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 8.200 8.200 r BUFHCE_X1Y85 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.643 8.843 ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X147Y353 FDRE r ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][23]/C clock pessimism 0.000 8.843 clock uncertainty -0.035 8.808 SLICE_X147Y353 FDRE (Setup_fdre_C_CE) -0.201 8.607 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][23] ------------------------------------------------------------------- required time 8.607 arrival time -5.839 ------------------------------------------------------------------- slack 2.768 Slack (MET) : 2.768ns (required time - arrival time) Source: ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][26]/CE (rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_2 rise@8.200ns - rxWordclkl12_2 rise@0.000ns) Data Path Delay: 5.157ns (logic 0.302ns (5.856%) route 4.855ns (94.144%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.039ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.643ns = ( 8.843 - 8.200 ) Source Clock Delay (SCD): 0.682ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.682 0.682 ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X144Y366 FDCE r ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X144Y366 FDCE (Prop_fdce_C_Q) 0.259 0.941 r ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/Q net (fo=154, routed) 2.545 3.486 ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15] SLICE_X127Y352 LUT2 (Prop_lut2_I0_O) 0.043 3.529 r ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4/O net (fo=128, routed) 2.310 5.839 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4_n_0 SLICE_X147Y353 FDRE r ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][26]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 8.200 8.200 r BUFHCE_X1Y85 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.643 8.843 ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X147Y353 FDRE r ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][26]/C clock pessimism 0.000 8.843 clock uncertainty -0.035 8.808 SLICE_X147Y353 FDRE (Setup_fdre_C_CE) -0.201 8.607 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][26] ------------------------------------------------------------------- required time 8.607 arrival time -5.839 ------------------------------------------------------------------- slack 2.768 Slack (MET) : 2.774ns (required time - arrival time) Source: ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][22]/CE (rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_2 rise@8.200ns - rxWordclkl12_2 rise@0.000ns) Data Path Delay: 5.197ns (logic 0.302ns (5.811%) route 4.895ns (94.189%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.016ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.641ns = ( 8.841 - 8.200 ) Source Clock Delay (SCD): 0.682ns Clock Pessimism Removal (CPR): 0.025ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.682 0.682 ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X144Y366 FDCE r ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X144Y366 FDCE (Prop_fdce_C_Q) 0.259 0.941 r ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/Q net (fo=154, routed) 2.545 3.486 ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15] SLICE_X127Y352 LUT2 (Prop_lut2_I0_O) 0.043 3.529 r ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4/O net (fo=128, routed) 2.350 5.879 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4_n_0 SLICE_X144Y353 FDRE r ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][22]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 8.200 8.200 r BUFHCE_X1Y85 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.641 8.841 ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X144Y353 FDRE r ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][22]/C clock pessimism 0.025 8.866 clock uncertainty -0.035 8.831 SLICE_X144Y353 FDRE (Setup_fdre_C_CE) -0.178 8.653 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][22] ------------------------------------------------------------------- required time 8.653 arrival time -5.879 ------------------------------------------------------------------- slack 2.774 Slack (MET) : 2.774ns (required time - arrival time) Source: ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][28]/CE (rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_2 rise@8.200ns - rxWordclkl12_2 rise@0.000ns) Data Path Delay: 5.197ns (logic 0.302ns (5.811%) route 4.895ns (94.189%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.016ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.641ns = ( 8.841 - 8.200 ) Source Clock Delay (SCD): 0.682ns Clock Pessimism Removal (CPR): 0.025ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.682 0.682 ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X144Y366 FDCE r ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X144Y366 FDCE (Prop_fdce_C_Q) 0.259 0.941 r ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/Q net (fo=154, routed) 2.545 3.486 ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15] SLICE_X127Y352 LUT2 (Prop_lut2_I0_O) 0.043 3.529 r ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4/O net (fo=128, routed) 2.350 5.879 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4_n_0 SLICE_X144Y353 FDRE r ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][28]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 8.200 8.200 r BUFHCE_X1Y85 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.641 8.841 ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X144Y353 FDRE r ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][28]/C clock pessimism 0.025 8.866 clock uncertainty -0.035 8.831 SLICE_X144Y353 FDRE (Setup_fdre_C_CE) -0.178 8.653 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][28] ------------------------------------------------------------------- required time 8.653 arrival time -5.879 ------------------------------------------------------------------- slack 2.774 Slack (MET) : 2.774ns (required time - arrival time) Source: ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][30]/CE (rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_2 rise@8.200ns - rxWordclkl12_2 rise@0.000ns) Data Path Delay: 5.197ns (logic 0.302ns (5.811%) route 4.895ns (94.189%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.016ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.641ns = ( 8.841 - 8.200 ) Source Clock Delay (SCD): 0.682ns Clock Pessimism Removal (CPR): 0.025ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.682 0.682 ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X144Y366 FDCE r ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X144Y366 FDCE (Prop_fdce_C_Q) 0.259 0.941 r ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15]/Q net (fo=154, routed) 2.545 3.486 ngFEC/SFP_GEN[3].ngCCM_gbt/test_comm_cnt2_reg[15] SLICE_X127Y352 LUT2 (Prop_lut2_I0_O) 0.043 3.529 r ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4/O net (fo=128, routed) 2.350 5.879 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__4_n_0 SLICE_X144Y353 FDRE r ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][30]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 8.200 8.200 r BUFHCE_X1Y85 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.641 8.841 ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X144Y353 FDRE r ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][30]/C clock pessimism 0.025 8.866 clock uncertainty -0.035 8.831 SLICE_X144Y353 FDRE (Setup_fdre_C_CE) -0.178 8.653 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][30] ------------------------------------------------------------------- required time 8.653 arrival time -5.879 ------------------------------------------------------------------- slack 2.774 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.085ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[3].rx_data_reg[3][43]/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_2 rise@0.000ns - rxWordclkl12_2 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.712%) route 0.055ns (35.288%)) Logic Levels: 0 Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.537ns Source Clock Delay (SCD): 0.382ns Clock Pessimism Removal (CPR): 0.144ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.382 0.382 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X175Y355 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X175Y355 FDRE (Prop_fdre_C_Q) 0.100 0.482 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/Q net (fo=1, routed) 0.055 0.537 ngFEC/GBT_rx_data[2]_1357[43] SLICE_X174Y355 FDRE r ngFEC/SFP_GEN[3].rx_data_reg[3][43]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.537 0.537 ngFEC/RX_WORDCLK_O[2] SLICE_X174Y355 FDRE r ngFEC/SFP_GEN[3].rx_data_reg[3][43]/C clock pessimism -0.144 0.393 SLICE_X174Y355 FDRE (Hold_fdre_C_D) 0.059 0.452 ngFEC/SFP_GEN[3].rx_data_reg[3][43] ------------------------------------------------------------------- required time -0.452 arrival time 0.537 ------------------------------------------------------------------- slack 0.085 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_2 rise@0.000ns - rxWordclkl12_2 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.540ns Source Clock Delay (SCD): 0.384ns Clock Pessimism Removal (CPR): 0.156ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.384 0.384 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/gt0_rxusrclk_in SLICE_X183Y392 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X183Y392 FDRE (Prop_fdre_C_Q) 0.100 0.484 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/Q net (fo=1, routed) 0.055 0.539 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync1 SLICE_X183Y392 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.540 0.540 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/gt0_rxusrclk_in SLICE_X183Y392 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/C clock pessimism -0.156 0.384 SLICE_X183Y392 FDRE (Hold_fdre_C_D) 0.047 0.431 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.431 arrival time 0.539 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.111ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_2 rise@0.000ns - rxWordclkl12_2 rise@0.000ns) Data Path Delay: 0.209ns (logic 0.128ns (61.382%) route 0.081ns (38.618%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.541ns Source Clock Delay (SCD): 0.385ns Clock Pessimism Removal (CPR): 0.145ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.385 0.385 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X183Y354 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X183Y354 FDCE (Prop_fdce_C_Q) 0.100 0.485 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/Q net (fo=1, routed) 0.081 0.566 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[0] SLICE_X182Y354 LUT3 (Prop_lut3_I0_O) 0.028 0.594 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__0/O net (fo=1, routed) 0.000 0.594 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out[0] SLICE_X182Y354 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.541 0.541 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X182Y354 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C clock pessimism -0.145 0.396 SLICE_X182Y354 FDRE (Hold_fdre_C_D) 0.087 0.483 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0] ------------------------------------------------------------------- required time -0.483 arrival time 0.594 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.114ns (arrival time - required time) Source: ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_reg[7][22]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][22]/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_2 rise@0.000ns - rxWordclkl12_2 rise@0.000ns) Data Path Delay: 0.188ns (logic 0.100ns (53.154%) route 0.088ns (46.846%)) Logic Levels: 0 Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.502ns Source Clock Delay (SCD): 0.348ns Clock Pessimism Removal (CPR): 0.143ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.348 0.348 ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X145Y353 FDCE r ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_reg[7][22]/C ------------------------------------------------------------------- ------------------- SLICE_X145Y353 FDCE (Prop_fdce_C_Q) 0.100 0.448 r ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_reg[7][22]/Q net (fo=2, routed) 0.088 0.536 ngFEC/SFP_GEN[3].ngCCM_gbt/L[22] SLICE_X144Y353 FDRE r ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][22]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.502 0.502 ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X144Y353 FDRE r ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][22]/C clock pessimism -0.143 0.359 SLICE_X144Y353 FDRE (Hold_fdre_C_D) 0.063 0.422 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][22] ------------------------------------------------------------------- required time -0.422 arrival time 0.536 ------------------------------------------------------------------- slack 0.114 Slack (MET) : 0.118ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_2 rise@0.000ns - rxWordclkl12_2 rise@0.000ns) Data Path Delay: 0.189ns (logic 0.128ns (67.559%) route 0.061ns (32.441%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.538ns Source Clock Delay (SCD): 0.383ns Clock Pessimism Removal (CPR): 0.144ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.383 0.383 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X172Y350 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X172Y350 FDCE (Prop_fdce_C_Q) 0.100 0.483 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Q net (fo=2, routed) 0.061 0.544 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_33_in SLICE_X173Y350 LUT3 (Prop_lut3_I2_O) 0.028 0.572 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1__0/O net (fo=1, routed) 0.000 0.572 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[15] SLICE_X173Y350 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.538 0.538 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X173Y350 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C clock pessimism -0.144 0.394 SLICE_X173Y350 FDRE (Hold_fdre_C_D) 0.060 0.454 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15] ------------------------------------------------------------------- required time -0.454 arrival time 0.572 ------------------------------------------------------------------- slack 0.118 Slack (MET) : 0.121ns (arrival time - required time) Source: ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[18]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[3].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[2]/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_2 rise@0.000ns - rxWordclkl12_2 rise@0.000ns) Data Path Delay: 0.216ns (logic 0.100ns (46.254%) route 0.116ns (53.746%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.539ns Source Clock Delay (SCD): 0.383ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.383 0.383 ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X177Y358 FDCE r ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X177Y358 FDCE (Prop_fdce_C_Q) 0.100 0.483 r ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[18]/Q net (fo=5, routed) 0.116 0.599 ngFEC/SFP_GEN[3].ngCCM_gbt/gbt_rx_checker/Q[2] SLICE_X178Y358 FDRE r ngFEC/SFP_GEN[3].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[2]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.539 0.539 ngFEC/SFP_GEN[3].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] SLICE_X178Y358 FDRE r ngFEC/SFP_GEN[3].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[2]/C clock pessimism -0.120 0.419 SLICE_X178Y358 FDRE (Hold_fdre_C_D) 0.059 0.478 ngFEC/SFP_GEN[3].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[2] ------------------------------------------------------------------- required time -0.478 arrival time 0.599 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.122ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[7]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[7]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_2 rise@0.000ns - rxWordclkl12_2 rise@0.000ns) Data Path Delay: 0.223ns (logic 0.128ns (57.480%) route 0.095ns (42.520%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.542ns Source Clock Delay (SCD): 0.386ns Clock Pessimism Removal (CPR): 0.142ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.386 0.386 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X181Y352 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X181Y352 FDCE (Prop_fdce_C_Q) 0.100 0.486 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[7]/Q net (fo=1, routed) 0.095 0.581 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[7] SLICE_X180Y351 LUT6 (Prop_lut6_I5_O) 0.028 0.609 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1[7]_i_1__0/O net (fo=1, routed) 0.000 0.609 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/p_0_out[7] SLICE_X180Y351 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[7]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.542 0.542 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X180Y351 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[7]/C clock pessimism -0.142 0.400 SLICE_X180Y351 FDCE (Hold_fdce_C_D) 0.087 0.487 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[7] ------------------------------------------------------------------- required time -0.487 arrival time 0.609 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.124ns (arrival time - required time) Source: ngFEC/SFP_GEN[3].rx_data_reg[3][20]/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[20]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_2 rise@0.000ns - rxWordclkl12_2 rise@0.000ns) Data Path Delay: 0.197ns (logic 0.100ns (50.843%) route 0.097ns (49.157%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.539ns Source Clock Delay (SCD): 0.383ns Clock Pessimism Removal (CPR): 0.142ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.383 0.383 ngFEC/RX_WORDCLK_O[2] SLICE_X177Y357 FDRE r ngFEC/SFP_GEN[3].rx_data_reg[3][20]/C ------------------------------------------------------------------- ------------------- SLICE_X177Y357 FDRE (Prop_fdre_C_Q) 0.100 0.483 r ngFEC/SFP_GEN[3].rx_data_reg[3][20]/Q net (fo=1, routed) 0.097 0.580 ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[83]_0[12] SLICE_X176Y358 FDCE r ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[20]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.539 0.539 ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X176Y358 FDCE r ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[20]/C clock pessimism -0.142 0.397 SLICE_X176Y358 FDCE (Hold_fdce_C_D) 0.059 0.456 ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[20] ------------------------------------------------------------------- required time -0.456 arrival time 0.580 ------------------------------------------------------------------- slack 0.124 Slack (MET) : 0.130ns (arrival time - required time) Source: ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_reg[7][20]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][20]/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_2 rise@0.000ns - rxWordclkl12_2 rise@0.000ns) Data Path Delay: 0.210ns (logic 0.100ns (47.693%) route 0.110ns (52.307%)) Logic Levels: 0 Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.504ns Source Clock Delay (SCD): 0.349ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.349 0.349 ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X145Y352 FDCE r ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_reg[7][20]/C ------------------------------------------------------------------- ------------------- SLICE_X145Y352 FDCE (Prop_fdce_C_Q) 0.100 0.449 r ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_reg[7][20]/Q net (fo=2, routed) 0.110 0.559 ngFEC/SFP_GEN[3].ngCCM_gbt/L[20] SLICE_X146Y352 FDRE r ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][20]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.504 0.504 ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X146Y352 FDRE r ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][20]/C clock pessimism -0.120 0.384 SLICE_X146Y352 FDRE (Hold_fdre_C_D) 0.045 0.429 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][20] ------------------------------------------------------------------- required time -0.429 arrival time 0.559 ------------------------------------------------------------------- slack 0.130 Slack (MET) : 0.131ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_2 rise@0.000ns - rxWordclkl12_2 rise@0.000ns) Data Path Delay: 0.173ns (logic 0.118ns (68.255%) route 0.055ns (31.745%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.541ns Source Clock Delay (SCD): 0.385ns Clock Pessimism Removal (CPR): 0.156ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.385 0.385 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in SLICE_X180Y394 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X180Y394 FDRE (Prop_fdre_C_Q) 0.118 0.503 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q net (fo=1, routed) 0.055 0.558 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync1 SLICE_X180Y394 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.541 0.541 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in SLICE_X180Y394 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C clock pessimism -0.156 0.385 SLICE_X180Y394 FDRE (Hold_fdre_C_D) 0.042 0.427 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.427 arrival time 0.558 ------------------------------------------------------------------- slack 0.131 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: rxWordclkl12_2 Waveform(ns): { 0.000 4.100 } Period(ns): 8.200 Sources: { ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/RXUSRCLK n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y31 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK Min Period n/a GTXE2_CHANNEL/RXUSRCLK2 n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y31 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X136Y362 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[1][14]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X135Y355 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[3][2]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X137Y354 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[3][3]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X136Y362 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[4][12]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X135Y355 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[4][1]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X135Y355 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[4][3]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X120Y356 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][11]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X146Y352 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][20]/C Low Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X166Y362 ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK Low Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X166Y362 ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK Low Pulse Width Slow FDRE/C n/a 0.400 4.100 3.700 SLICE_X137Y354 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[3][3]/C Low Pulse Width Slow FDRE/C n/a 0.400 4.100 3.700 SLICE_X126Y351 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][3]/C Low Pulse Width Slow FDRE/C n/a 0.400 4.100 3.700 SLICE_X126Y351 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][5]/C Low Pulse Width Slow FDRE/C n/a 0.400 4.100 3.700 SLICE_X124Y351 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[7][7]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X136Y358 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_reg[1][2]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X136Y358 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_reg[1][4]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X136Y359 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_reg[1][6]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X136Y359 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_reg[1][7]/C High Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X166Y362 ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X166Y362 ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X137Y363 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[0][15]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X137Y363 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[3][15]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X132Y355 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[4][0]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X130Y361 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[4][11]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X130Y361 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_o_reg[4][15]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X139Y363 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_reg[0][11]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X139Y363 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_reg[0][13]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X139Y363 ngFEC/SFP_GEN[3].ngCCM_gbt/ngCCM_status_counter_reg[0][14]/C --------------------------------------------------------------------------------------------------- From Clock: rxWordclkl12_3 To Clock: rxWordclkl12_3 Setup : 0 Failing Endpoints, Worst Slack 3.616ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.095ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.458ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.616ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[95]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_3 rise@8.200ns - rxWordclkl12_3 rise@0.000ns) Data Path Delay: 4.179ns (logic 1.194ns (28.569%) route 2.985ns (71.431%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.270ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.645ns = ( 8.845 - 8.200 ) Source Clock Delay (SCD): 0.915ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.915 0.915 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDISPERR[1]) 1.009 1.924 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDISPERR[1] net (fo=8, routed) 2.106 4.031 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19]_0[19] SLICE_X164Y360 LUT5 (Prop_lut5_I3_O) 0.046 4.077 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[95]_i_3__1/O net (fo=6, routed) 0.533 4.609 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[95]_i_3__1_n_0 SLICE_X165Y362 LUT4 (Prop_lut4_I1_O) 0.139 4.748 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[95]_i_2__1/O net (fo=1, routed) 0.347 5.095 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_1[91] SLICE_X165Y361 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[95]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 8.200 8.200 r BUFHCE_X1Y86 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.645 8.845 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X165Y361 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[95]/C clock pessimism 0.000 8.845 clock uncertainty -0.035 8.810 SLICE_X165Y361 FDCE (Setup_fdce_C_D) -0.099 8.711 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[95] ------------------------------------------------------------------- required time 8.711 arrival time -5.095 ------------------------------------------------------------------- slack 3.616 Slack (MET) : 3.633ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[28]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_3 rise@8.200ns - rxWordclkl12_3 rise@0.000ns) Data Path Delay: 4.162ns (logic 1.204ns (28.928%) route 2.958ns (71.072%)) Logic Levels: 2 (LUT4=2) Clock Path Skew: -0.268ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.647ns = ( 8.847 - 8.200 ) Source Clock Delay (SCD): 0.915ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.915 0.915 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXCHARISK[0]) 1.009 1.924 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXCHARISK[0] net (fo=5, routed) 1.932 3.856 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19]_0[8] SLICE_X163Y362 LUT4 (Prop_lut4_I0_O) 0.054 3.910 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[92]_i_3__1/O net (fo=5, routed) 0.752 4.662 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[92]_i_3__1_n_0 SLICE_X164Y358 LUT4 (Prop_lut4_I3_O) 0.141 4.803 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[28]_i_1__1/O net (fo=1, routed) 0.275 5.077 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_1[24] SLICE_X163Y358 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[28]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 8.200 8.200 r BUFHCE_X1Y86 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.647 8.847 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X163Y358 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[28]/C clock pessimism 0.000 8.847 clock uncertainty -0.035 8.812 SLICE_X163Y358 FDCE (Setup_fdce_C_D) -0.101 8.711 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[28] ------------------------------------------------------------------- required time 8.711 arrival time -5.077 ------------------------------------------------------------------- slack 3.633 Slack (MET) : 3.660ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[27]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_3 rise@8.200ns - rxWordclkl12_3 rise@0.000ns) Data Path Delay: 4.124ns (logic 1.105ns (26.796%) route 3.019ns (73.204%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.269ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.646ns = ( 8.846 - 8.200 ) Source Clock Delay (SCD): 0.915ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.915 0.915 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[3]) 1.009 1.924 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[3] net (fo=13, routed) 2.183 4.107 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19]_0[3] SLICE_X162Y358 LUT5 (Prop_lut5_I4_O) 0.043 4.150 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[91]_i_3__1/O net (fo=6, routed) 0.472 4.622 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[91]_i_3__1_n_0 SLICE_X157Y358 LUT4 (Prop_lut4_I3_O) 0.053 4.675 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[27]_i_2__1/O net (fo=1, routed) 0.364 5.039 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_1[23] SLICE_X156Y358 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[27]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 8.200 8.200 r BUFHCE_X1Y86 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.646 8.846 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X156Y358 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[27]/C clock pessimism 0.000 8.846 clock uncertainty -0.035 8.811 SLICE_X156Y358 FDCE (Setup_fdce_C_D) -0.111 8.700 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[27] ------------------------------------------------------------------- required time 8.700 arrival time -5.039 ------------------------------------------------------------------- slack 3.660 Slack (MET) : 3.676ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[57]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_3 rise@8.200ns - rxWordclkl12_3 rise@0.000ns) Data Path Delay: 4.094ns (logic 1.106ns (27.017%) route 2.988ns (72.983%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.269ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.646ns = ( 8.846 - 8.200 ) Source Clock Delay (SCD): 0.915ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.915 0.915 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[11]) 1.009 1.924 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[11] net (fo=5, routed) 1.995 3.919 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19]_0[13] SLICE_X162Y358 LUT5 (Prop_lut5_I3_O) 0.043 3.962 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[89]_i_2__1/O net (fo=6, routed) 0.717 4.679 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[89]_i_2__1_n_0 SLICE_X157Y357 LUT4 (Prop_lut4_I3_O) 0.054 4.733 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[57]_i_1__1/O net (fo=1, routed) 0.276 5.009 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_1[53] SLICE_X157Y359 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[57]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 8.200 8.200 r BUFHCE_X1Y86 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.646 8.846 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X157Y359 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[57]/C clock pessimism 0.000 8.846 clock uncertainty -0.035 8.811 SLICE_X157Y359 FDCE (Setup_fdce_C_D) -0.125 8.686 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[57] ------------------------------------------------------------------- required time 8.686 arrival time -5.009 ------------------------------------------------------------------- slack 3.676 Slack (MET) : 3.710ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[58]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_3 rise@8.200ns - rxWordclkl12_3 rise@0.000ns) Data Path Delay: 4.077ns (logic 1.102ns (27.028%) route 2.975ns (72.972%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.269ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.646ns = ( 8.846 - 8.200 ) Source Clock Delay (SCD): 0.915ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.915 0.915 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[12]) 1.009 1.924 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[12] net (fo=5, routed) 1.981 3.905 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19]_0[14] SLICE_X161Y358 LUT5 (Prop_lut5_I3_O) 0.043 3.948 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[90]_i_2__1/O net (fo=6, routed) 0.534 4.482 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[90]_i_2__1_n_0 SLICE_X157Y357 LUT4 (Prop_lut4_I3_O) 0.050 4.532 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[58]_i_1__1/O net (fo=1, routed) 0.460 4.993 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_1[54] SLICE_X157Y359 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[58]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 8.200 8.200 r BUFHCE_X1Y86 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.646 8.846 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X157Y359 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[58]/C clock pessimism 0.000 8.846 clock uncertainty -0.035 8.811 SLICE_X157Y359 FDCE (Setup_fdce_C_D) -0.108 8.703 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[58] ------------------------------------------------------------------- required time 8.703 arrival time -4.993 ------------------------------------------------------------------- slack 3.710 Slack (MET) : 3.728ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[72]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_3 rise@8.200ns - rxWordclkl12_3 rise@0.000ns) Data Path Delay: 4.202ns (logic 1.190ns (28.322%) route 3.012ns (71.678%)) Logic Levels: 2 (LUT3=1 LUT6=1) Clock Path Skew: -0.268ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.647ns = ( 8.847 - 8.200 ) Source Clock Delay (SCD): 0.915ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.915 0.915 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[0]) 1.009 1.924 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[0] net (fo=13, routed) 2.328 4.252 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19]_0[0] SLICE_X162Y357 LUT3 (Prop_lut3_I0_O) 0.047 4.299 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[96]_i_4__1/O net (fo=5, routed) 0.684 4.983 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[96]_i_4__1_n_0 SLICE_X159Y357 LUT6 (Prop_lut6_I5_O) 0.134 5.117 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[72]_i_1__1/O net (fo=1, routed) 0.000 5.117 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_1[68] SLICE_X159Y357 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[72]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 8.200 8.200 r BUFHCE_X1Y86 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.647 8.847 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X159Y357 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[72]/C clock pessimism 0.000 8.847 clock uncertainty -0.035 8.812 SLICE_X159Y357 FDCE (Setup_fdce_C_D) 0.034 8.846 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[72] ------------------------------------------------------------------- required time 8.846 arrival time -5.117 ------------------------------------------------------------------- slack 3.728 Slack (MET) : 3.729ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[59]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_3 rise@8.200ns - rxWordclkl12_3 rise@0.000ns) Data Path Delay: 4.055ns (logic 1.105ns (27.248%) route 2.950ns (72.752%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.269ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.646ns = ( 8.846 - 8.200 ) Source Clock Delay (SCD): 0.915ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.915 0.915 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[3]) 1.009 1.924 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[3] net (fo=13, routed) 2.183 4.107 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19]_0[3] SLICE_X162Y358 LUT5 (Prop_lut5_I4_O) 0.043 4.150 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[91]_i_3__1/O net (fo=6, routed) 0.482 4.632 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[91]_i_3__1_n_0 SLICE_X157Y357 LUT4 (Prop_lut4_I3_O) 0.053 4.685 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[59]_i_2__1/O net (fo=1, routed) 0.285 4.971 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_1[55] SLICE_X157Y359 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[59]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 8.200 8.200 r BUFHCE_X1Y86 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.646 8.846 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X157Y359 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[59]/C clock pessimism 0.000 8.846 clock uncertainty -0.035 8.811 SLICE_X157Y359 FDCE (Setup_fdce_C_D) -0.111 8.700 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[59] ------------------------------------------------------------------- required time 8.700 arrival time -4.971 ------------------------------------------------------------------- slack 3.729 Slack (MET) : 3.749ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[23]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_3 rise@8.200ns - rxWordclkl12_3 rise@0.000ns) Data Path Delay: 4.056ns (logic 1.191ns (29.366%) route 2.865ns (70.634%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.268ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.647ns = ( 8.847 - 8.200 ) Source Clock Delay (SCD): 0.915ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.915 0.915 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDISPERR[1]) 1.009 1.924 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDISPERR[1] net (fo=8, routed) 2.106 4.031 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19]_0[19] SLICE_X164Y360 LUT5 (Prop_lut5_I3_O) 0.046 4.077 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[95]_i_3__1/O net (fo=6, routed) 0.566 4.642 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[95]_i_3__1_n_0 SLICE_X164Y359 LUT4 (Prop_lut4_I1_O) 0.136 4.778 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[23]_i_2__1/O net (fo=1, routed) 0.193 4.971 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_1[19] SLICE_X164Y358 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[23]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 8.200 8.200 r BUFHCE_X1Y86 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.647 8.847 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X164Y358 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[23]/C clock pessimism 0.000 8.847 clock uncertainty -0.035 8.812 SLICE_X164Y358 FDCE (Setup_fdce_C_D) -0.091 8.721 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[23] ------------------------------------------------------------------- required time 8.721 arrival time -4.971 ------------------------------------------------------------------- slack 3.749 Slack (MET) : 3.752ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[92]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_3 rise@8.200ns - rxWordclkl12_3 rise@0.000ns) Data Path Delay: 4.040ns (logic 1.208ns (29.902%) route 2.832ns (70.098%)) Logic Levels: 2 (LUT4=2) Clock Path Skew: -0.270ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.645ns = ( 8.845 - 8.200 ) Source Clock Delay (SCD): 0.915ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.915 0.915 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXCHARISK[0]) 1.009 1.924 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXCHARISK[0] net (fo=5, routed) 1.932 3.856 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19]_0[8] SLICE_X163Y362 LUT4 (Prop_lut4_I0_O) 0.054 3.910 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[92]_i_3__1/O net (fo=5, routed) 0.546 4.456 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[92]_i_3__1_n_0 SLICE_X164Y362 LUT4 (Prop_lut4_I3_O) 0.145 4.601 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[92]_i_1__1/O net (fo=1, routed) 0.354 4.955 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_1[88] SLICE_X165Y361 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[92]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 8.200 8.200 r BUFHCE_X1Y86 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.645 8.845 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X165Y361 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[92]/C clock pessimism 0.000 8.845 clock uncertainty -0.035 8.810 SLICE_X165Y361 FDCE (Setup_fdce_C_D) -0.102 8.708 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[92] ------------------------------------------------------------------- required time 8.708 arrival time -4.955 ------------------------------------------------------------------- slack 3.752 Slack (MET) : 3.777ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[63]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_3 rise@8.200ns - rxWordclkl12_3 rise@0.000ns) Data Path Delay: 4.028ns (logic 1.191ns (29.570%) route 2.837ns (70.430%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.269ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.646ns = ( 8.846 - 8.200 ) Source Clock Delay (SCD): 0.915ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.915 0.915 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDISPERR[1]) 1.009 1.924 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDISPERR[1] net (fo=8, routed) 2.106 4.031 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19]_0[19] SLICE_X164Y360 LUT5 (Prop_lut5_I3_O) 0.046 4.077 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[95]_i_3__1/O net (fo=6, routed) 0.538 4.614 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[95]_i_3__1_n_0 SLICE_X164Y361 LUT4 (Prop_lut4_I1_O) 0.136 4.750 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/reg0[63]_i_2__1/O net (fo=1, routed) 0.193 4.943 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_1[59] SLICE_X164Y360 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[63]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 8.200 8.200 r BUFHCE_X1Y86 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.646 8.846 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X164Y360 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[63]/C clock pessimism 0.000 8.846 clock uncertainty -0.035 8.811 SLICE_X164Y360 FDCE (Setup_fdce_C_D) -0.091 8.720 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[63] ------------------------------------------------------------------- required time 8.720 arrival time -4.943 ------------------------------------------------------------------- slack 3.777 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.095ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_3 rise@0.000ns - rxWordclkl12_3 rise@0.000ns) Data Path Delay: 0.193ns (logic 0.128ns (66.301%) route 0.065ns (33.699%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.507ns Source Clock Delay (SCD): 0.353ns Clock Pessimism Removal (CPR): 0.143ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.353 0.353 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X159Y353 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X159Y353 FDCE (Prop_fdce_C_Q) 0.100 0.453 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Q net (fo=2, routed) 0.065 0.518 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_33_in SLICE_X158Y353 LUT3 (Prop_lut3_I2_O) 0.028 0.546 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1__1/O net (fo=1, routed) 0.000 0.546 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[15] SLICE_X158Y353 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.507 0.507 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X158Y353 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C clock pessimism -0.143 0.364 SLICE_X158Y353 FDRE (Hold_fdre_C_D) 0.087 0.451 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15] ------------------------------------------------------------------- required time -0.451 arrival time 0.546 ------------------------------------------------------------------- slack 0.095 Slack (MET) : 0.107ns (arrival time - required time) Source: ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Clock_20MHz_dl_reg[1]/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/D (rising edge-triggered cell SRL16E clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_3 rise@0.000ns - rxWordclkl12_3 rise@0.000ns) Data Path Delay: 0.221ns (logic 0.118ns (53.297%) route 0.103ns (46.703%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.501ns Source Clock Delay (SCD): 0.349ns Clock Pessimism Removal (CPR): 0.140ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.349 0.349 ngFEC/SFP_GEN[4].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X162Y366 FDRE r ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Clock_20MHz_dl_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X162Y366 FDRE (Prop_fdre_C_Q) 0.118 0.467 r ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Clock_20MHz_dl_reg[1]/Q net (fo=2, routed) 0.103 0.570 ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Clock_20MHz_dl_reg_n_0_[1] SLICE_X164Y366 SRL16E r ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.501 0.501 ngFEC/SFP_GEN[4].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X164Y366 SRL16E r ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK clock pessimism -0.140 0.361 SLICE_X164Y366 SRL16E (Hold_srl16e_CLK_D) 0.102 0.463 ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2 ------------------------------------------------------------------- required time -0.463 arrival time 0.570 ------------------------------------------------------------------- slack 0.107 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_3 rise@0.000ns - rxWordclkl12_3 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.528ns Source Clock Delay (SCD): 0.375ns Clock Pessimism Removal (CPR): 0.153ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.375 0.375 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/gt0_rxusrclk_in SLICE_X179Y378 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X179Y378 FDRE (Prop_fdre_C_Q) 0.100 0.475 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/Q net (fo=1, routed) 0.055 0.530 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync1 SLICE_X179Y378 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.528 0.528 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/gt0_rxusrclk_in SLICE_X179Y378 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/C clock pessimism -0.153 0.375 SLICE_X179Y378 FDRE (Hold_fdre_C_D) 0.047 0.422 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.422 arrival time 0.530 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.111ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_3 rise@0.000ns - rxWordclkl12_3 rise@0.000ns) Data Path Delay: 0.209ns (logic 0.128ns (61.382%) route 0.081ns (38.618%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.508ns Source Clock Delay (SCD): 0.354ns Clock Pessimism Removal (CPR): 0.143ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.354 0.354 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X163Y353 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X163Y353 FDCE (Prop_fdce_C_Q) 0.100 0.454 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[1]/Q net (fo=1, routed) 0.081 0.535 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[1] SLICE_X162Y353 LUT3 (Prop_lut3_I0_O) 0.028 0.563 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__1/O net (fo=1, routed) 0.000 0.563 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out[1] SLICE_X162Y353 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.508 0.508 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X162Y353 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C clock pessimism -0.143 0.365 SLICE_X162Y353 FDRE (Hold_fdre_C_D) 0.087 0.452 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[1] ------------------------------------------------------------------- required time -0.452 arrival time 0.563 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.118ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_3 rise@0.000ns - rxWordclkl12_3 rise@0.000ns) Data Path Delay: 0.216ns (logic 0.128ns (59.307%) route 0.088ns (40.693%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.506ns Source Clock Delay (SCD): 0.351ns Clock Pessimism Removal (CPR): 0.144ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.351 0.351 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X161Y360 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X161Y360 FDCE (Prop_fdce_C_Q) 0.100 0.451 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Q net (fo=2, routed) 0.088 0.539 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_35_in SLICE_X160Y360 LUT3 (Prop_lut3_I2_O) 0.028 0.567 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__1/O net (fo=1, routed) 0.000 0.567 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out[16] SLICE_X160Y360 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.506 0.506 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X160Y360 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C clock pessimism -0.144 0.362 SLICE_X160Y360 FDRE (Hold_fdre_C_D) 0.087 0.449 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[16] ------------------------------------------------------------------- required time -0.449 arrival time 0.567 ------------------------------------------------------------------- slack 0.118 Slack (MET) : 0.121ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[4].rx_data_reg[4][67]/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_3 rise@0.000ns - rxWordclkl12_3 rise@0.000ns) Data Path Delay: 0.195ns (logic 0.100ns (51.365%) route 0.095ns (48.635%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.507ns Source Clock Delay (SCD): 0.352ns Clock Pessimism Removal (CPR): 0.140ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.352 0.352 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X155Y353 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X155Y353 FDRE (Prop_fdre_C_Q) 0.100 0.452 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/Q net (fo=1, routed) 0.095 0.547 ngFEC/GBT_rx_data[3]_1358[67] SLICE_X154Y352 FDRE r ngFEC/SFP_GEN[4].rx_data_reg[4][67]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.507 0.507 ngFEC/RX_WORDCLK_O[3] SLICE_X154Y352 FDRE r ngFEC/SFP_GEN[4].rx_data_reg[4][67]/C clock pessimism -0.140 0.367 SLICE_X154Y352 FDRE (Hold_fdre_C_D) 0.059 0.426 ngFEC/SFP_GEN[4].rx_data_reg[4][67] ------------------------------------------------------------------- required time -0.426 arrival time 0.547 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.123ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_3 rise@0.000ns - rxWordclkl12_3 rise@0.000ns) Data Path Delay: 0.230ns (logic 0.132ns (57.504%) route 0.098ns (42.496%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.530ns Source Clock Delay (SCD): 0.376ns Clock Pessimism Removal (CPR): 0.143ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.376 0.376 ngFEC/gbtbank1_l12_118/MGT_RXUSRCLK_o[3] SLICE_X167Y364 FDCE r ngFEC/gbtbank1_l12_118/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/C ------------------------------------------------------------------- ------------------- SLICE_X167Y364 FDCE (Prop_fdce_C_Q) 0.100 0.476 r ngFEC/gbtbank1_l12_118/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/Q net (fo=127, routed) 0.098 0.574 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0][3] SLICE_X166Y364 LUT2 (Prop_lut2_I0_O) 0.032 0.606 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gbtBank_Clk_gen[3].rx_clken_sr[3][4]_i_1/O net (fo=1, routed) 0.000 0.606 ngFEC/gbtbank1_l12_118/gbt_inst_n_58 SLICE_X166Y364 FDCE r ngFEC/gbtbank1_l12_118/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.530 0.530 ngFEC/gbtbank1_l12_118/MGT_RXUSRCLK_o[3] SLICE_X166Y364 FDCE r ngFEC/gbtbank1_l12_118/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]/C clock pessimism -0.143 0.387 SLICE_X166Y364 FDCE (Hold_fdce_C_D) 0.096 0.483 ngFEC/gbtbank1_l12_118/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4] ------------------------------------------------------------------- required time -0.483 arrival time 0.606 ------------------------------------------------------------------- slack 0.123 Slack (MET) : 0.130ns (arrival time - required time) Source: ngFEC/SFP_GEN[4].ngCCM_gbt/ngCCM_status_counter_reg[7][14]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[4].ngCCM_gbt/ngCCM_status_counter_o_reg[7][14]/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_3 rise@0.000ns - rxWordclkl12_3 rise@0.000ns) Data Path Delay: 0.208ns (logic 0.100ns (48.069%) route 0.108ns (51.931%)) Logic Levels: 0 Clock Path Skew: 0.033ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.463ns Source Clock Delay (SCD): 0.310ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.310 0.310 ngFEC/SFP_GEN[4].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X125Y356 FDCE r ngFEC/SFP_GEN[4].ngCCM_gbt/ngCCM_status_counter_reg[7][14]/C ------------------------------------------------------------------- ------------------- SLICE_X125Y356 FDCE (Prop_fdce_C_Q) 0.100 0.410 r ngFEC/SFP_GEN[4].ngCCM_gbt/ngCCM_status_counter_reg[7][14]/Q net (fo=2, routed) 0.108 0.518 ngFEC/SFP_GEN[4].ngCCM_gbt/ngCCM_status_counter_reg_n_0_[7][14] SLICE_X122Y356 FDRE r ngFEC/SFP_GEN[4].ngCCM_gbt/ngCCM_status_counter_o_reg[7][14]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.463 0.463 ngFEC/SFP_GEN[4].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X122Y356 FDRE r ngFEC/SFP_GEN[4].ngCCM_gbt/ngCCM_status_counter_o_reg[7][14]/C clock pessimism -0.120 0.343 SLICE_X122Y356 FDRE (Hold_fdre_C_D) 0.045 0.388 ngFEC/SFP_GEN[4].ngCCM_gbt/ngCCM_status_counter_o_reg[7][14] ------------------------------------------------------------------- required time -0.388 arrival time 0.518 ------------------------------------------------------------------- slack 0.130 Slack (MET) : 0.131ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_3 rise@0.000ns - rxWordclkl12_3 rise@0.000ns) Data Path Delay: 0.173ns (logic 0.118ns (68.255%) route 0.055ns (31.745%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.531ns Source Clock Delay (SCD): 0.377ns Clock Pessimism Removal (CPR): 0.154ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.377 0.377 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in SLICE_X182Y380 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X182Y380 FDRE (Prop_fdre_C_Q) 0.118 0.495 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q net (fo=1, routed) 0.055 0.550 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync1 SLICE_X182Y380 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.531 0.531 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in SLICE_X182Y380 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C clock pessimism -0.154 0.377 SLICE_X182Y380 FDRE (Hold_fdre_C_D) 0.042 0.419 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.419 arrival time 0.550 ------------------------------------------------------------------- slack 0.131 Slack (MET) : 0.133ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[4].rx_data_reg[4][76]/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_3 rise@0.000ns - rxWordclkl12_3 rise@0.000ns) Data Path Delay: 0.184ns (logic 0.100ns (54.455%) route 0.084ns (45.545%)) Logic Levels: 0 Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.506ns Source Clock Delay (SCD): 0.352ns Clock Pessimism Removal (CPR): 0.143ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.352 0.352 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X153Y355 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X153Y355 FDRE (Prop_fdre_C_Q) 0.100 0.452 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/Q net (fo=1, routed) 0.084 0.536 ngFEC/GBT_rx_data[3]_1358[76] SLICE_X152Y355 FDRE r ngFEC/SFP_GEN[4].rx_data_reg[4][76]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.506 0.506 ngFEC/RX_WORDCLK_O[3] SLICE_X152Y355 FDRE r ngFEC/SFP_GEN[4].rx_data_reg[4][76]/C clock pessimism -0.143 0.363 SLICE_X152Y355 FDRE (Hold_fdre_C_D) 0.040 0.403 ngFEC/SFP_GEN[4].rx_data_reg[4][76] ------------------------------------------------------------------- required time -0.403 arrival time 0.536 ------------------------------------------------------------------- slack 0.133 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: rxWordclkl12_3 Waveform(ns): { 0.000 4.100 } Period(ns): 8.200 Sources: { ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/RXUSRCLK n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y30 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK Min Period n/a GTXE2_CHANNEL/RXUSRCLK2 n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y30 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X164Y366 ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Clock_20MHz_dl_reg[4]__0/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X156Y360 ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[26]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X156Y360 ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[27]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X161Y352 ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[2]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X155Y359 ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[30]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X155Y359 ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[31]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X165Y355 ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[34]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X162Y354 ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[38]/C Low Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X164Y366 ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK Low Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X164Y366 ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X156Y360 ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[26]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X156Y360 ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[27]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X155Y359 ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[30]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X155Y359 ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[31]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X155Y352 ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[46]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X152Y350 ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[50]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X152Y351 ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[54]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X155Y352 ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[58]/C High Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X164Y366 ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X164Y366 ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X155Y361 ngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[14]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X155Y361 ngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[18]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X155Y361 ngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[19]/C High Pulse Width Slow FDPE/C n/a 0.350 4.100 3.750 SLICE_X164Y364 ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X114Y354 ngFEC/SFP_GEN[4].ngCCM_gbt/ngCCM_status_counter_o_reg[4][11]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X114Y353 ngFEC/SFP_GEN[4].ngCCM_gbt/ngCCM_status_counter_o_reg[4][12]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X114Y351 ngFEC/SFP_GEN[4].ngCCM_gbt/ngCCM_status_counter_o_reg[4][1]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X114Y351 ngFEC/SFP_GEN[4].ngCCM_gbt/ngCCM_status_counter_o_reg[4][2]/C --------------------------------------------------------------------------------------------------- From Clock: rxWordclkl12_4 To Clock: rxWordclkl12_4 Setup : 0 Failing Endpoints, Worst Slack 3.660ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.092ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.458ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.660ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[60]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_4 rise@8.200ns - rxWordclkl12_4 rise@0.000ns) Data Path Delay: 4.115ns (logic 1.194ns (29.018%) route 2.921ns (70.982%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.276ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.635ns = ( 8.835 - 8.200 ) Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.911 0.911 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[0]) 1.009 1.920 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[0] net (fo=13, routed) 1.578 3.498 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gt0_rxdata_out[0] SLICE_X166Y322 LUT5 (Prop_lut5_I0_O) 0.047 3.545 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[92]_i_2__2/O net (fo=6, routed) 0.843 4.388 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[92]_i_2__2_n_0 SLICE_X162Y323 LUT4 (Prop_lut4_I1_O) 0.138 4.526 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[60]_i_1__2/O net (fo=1, routed) 0.500 5.026 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[56] SLICE_X161Y322 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[60]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 8.200 8.200 r BUFHCE_X1Y72 BUFH 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.635 8.835 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X161Y322 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[60]/C clock pessimism 0.000 8.835 clock uncertainty -0.035 8.800 SLICE_X161Y322 FDCE (Setup_fdce_C_D) -0.113 8.687 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[60] ------------------------------------------------------------------- required time 8.687 arrival time -5.026 ------------------------------------------------------------------- slack 3.660 Slack (MET) : 3.894ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/FSM_sequential_state_reg[1]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[60]/CE (rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_4 rise@8.200ns - rxWordclkl12_4 rise@0.000ns) Data Path Delay: 3.878ns (logic 1.061ns (27.362%) route 2.817ns (72.638%)) Logic Levels: 5 (CARRY4=1 LUT4=1 LUT5=2 LUT6=1) Clock Path Skew: -0.097ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.635ns = ( 8.835 - 8.200 ) Source Clock Delay (SCD): 0.732ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.732 0.732 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 SLICE_X174Y321 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/FSM_sequential_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X174Y321 FDCE (Prop_fdce_C_Q) 0.236 0.968 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/FSM_sequential_state_reg[1]/Q net (fo=23, routed) 0.685 1.653 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/FSM_sequential_state_reg[1]_0 SLICE_X170Y323 LUT4 (Prop_lut4_I1_O) 0.127 1.780 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0[99]_i_14__2/O net (fo=3, routed) 0.600 2.381 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0[99]_i_14__2_n_0 SLICE_X170Y324 LUT6 (Prop_lut6_I0_O) 0.134 2.515 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0[15]_i_9__2/O net (fo=1, routed) 0.000 2.515 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0[15]_i_9__2_n_0 SLICE_X170Y324 CARRY4 (Prop_carry4_S[0]_O[3]) 0.292 2.807 f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0_reg[15]_i_4__2/O[3] net (fo=11, routed) 0.445 3.252 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg01[7] SLICE_X168Y324 LUT5 (Prop_lut5_I3_O) 0.128 3.380 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[71]_i_3__2/O net (fo=6, routed) 0.440 3.820 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0_reg[67] SLICE_X166Y323 LUT5 (Prop_lut5_I2_O) 0.144 3.964 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0[63]_i_1__2/O net (fo=4, routed) 0.645 4.610 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_0[14] SLICE_X161Y322 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[60]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 8.200 8.200 r BUFHCE_X1Y72 BUFH 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.635 8.835 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X161Y322 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[60]/C clock pessimism 0.000 8.835 clock uncertainty -0.035 8.800 SLICE_X161Y322 FDCE (Setup_fdce_C_CE) -0.296 8.504 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[60] ------------------------------------------------------------------- required time 8.504 arrival time -4.610 ------------------------------------------------------------------- slack 3.894 Slack (MET) : 3.894ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/FSM_sequential_state_reg[1]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[63]/CE (rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_4 rise@8.200ns - rxWordclkl12_4 rise@0.000ns) Data Path Delay: 3.878ns (logic 1.061ns (27.362%) route 2.817ns (72.638%)) Logic Levels: 5 (CARRY4=1 LUT4=1 LUT5=2 LUT6=1) Clock Path Skew: -0.097ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.635ns = ( 8.835 - 8.200 ) Source Clock Delay (SCD): 0.732ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.732 0.732 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 SLICE_X174Y321 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/FSM_sequential_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X174Y321 FDCE (Prop_fdce_C_Q) 0.236 0.968 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/FSM_sequential_state_reg[1]/Q net (fo=23, routed) 0.685 1.653 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/FSM_sequential_state_reg[1]_0 SLICE_X170Y323 LUT4 (Prop_lut4_I1_O) 0.127 1.780 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0[99]_i_14__2/O net (fo=3, routed) 0.600 2.381 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0[99]_i_14__2_n_0 SLICE_X170Y324 LUT6 (Prop_lut6_I0_O) 0.134 2.515 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0[15]_i_9__2/O net (fo=1, routed) 0.000 2.515 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0[15]_i_9__2_n_0 SLICE_X170Y324 CARRY4 (Prop_carry4_S[0]_O[3]) 0.292 2.807 f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0_reg[15]_i_4__2/O[3] net (fo=11, routed) 0.445 3.252 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg01[7] SLICE_X168Y324 LUT5 (Prop_lut5_I3_O) 0.128 3.380 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[71]_i_3__2/O net (fo=6, routed) 0.440 3.820 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0_reg[67] SLICE_X166Y323 LUT5 (Prop_lut5_I2_O) 0.144 3.964 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0[63]_i_1__2/O net (fo=4, routed) 0.645 4.610 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_0[14] SLICE_X161Y322 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[63]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 8.200 8.200 r BUFHCE_X1Y72 BUFH 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.635 8.835 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X161Y322 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[63]/C clock pessimism 0.000 8.835 clock uncertainty -0.035 8.800 SLICE_X161Y322 FDCE (Setup_fdce_C_CE) -0.296 8.504 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[63] ------------------------------------------------------------------- required time 8.504 arrival time -4.610 ------------------------------------------------------------------- slack 3.894 Slack (MET) : 3.936ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[24]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_4 rise@8.200ns - rxWordclkl12_4 rise@0.000ns) Data Path Delay: 3.885ns (logic 1.205ns (31.019%) route 2.680ns (68.981%)) Logic Levels: 2 (LUT4=2) Clock Path Skew: -0.228ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.683ns = ( 8.883 - 8.200 ) Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.911 0.911 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXCHARISK[0]) 1.009 1.920 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXCHARISK[0] net (fo=5, routed) 1.574 3.495 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gt0_rxdata_out[8] SLICE_X171Y322 LUT4 (Prop_lut4_I1_O) 0.049 3.544 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[96]_i_3__2/O net (fo=6, routed) 0.741 4.285 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[96]_i_3__2_n_0 SLICE_X175Y322 LUT4 (Prop_lut4_I1_O) 0.147 4.432 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[24]_i_1__2/O net (fo=1, routed) 0.364 4.796 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[20] SLICE_X171Y322 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[24]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 8.200 8.200 r BUFHCE_X1Y72 BUFH 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.683 8.883 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X171Y322 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[24]/C clock pessimism 0.000 8.883 clock uncertainty -0.035 8.848 SLICE_X171Y322 FDCE (Setup_fdce_C_D) -0.116 8.732 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[24] ------------------------------------------------------------------- required time 8.732 arrival time -4.796 ------------------------------------------------------------------- slack 3.936 Slack (MET) : 3.989ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/FSM_sequential_state_reg[1]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[68]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_4 rise@8.200ns - rxWordclkl12_4 rise@0.000ns) Data Path Delay: 4.144ns (logic 1.090ns (26.303%) route 3.054ns (73.697%)) Logic Levels: 6 (CARRY4=1 LUT3=1 LUT4=1 LUT6=3) Clock Path Skew: -0.096ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.636ns = ( 8.836 - 8.200 ) Source Clock Delay (SCD): 0.732ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.732 0.732 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 SLICE_X174Y321 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/FSM_sequential_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X174Y321 FDCE (Prop_fdce_C_Q) 0.236 0.968 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/FSM_sequential_state_reg[1]/Q net (fo=23, routed) 0.685 1.653 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/FSM_sequential_state_reg[1]_0 SLICE_X170Y323 LUT4 (Prop_lut4_I1_O) 0.127 1.780 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0[99]_i_14__2/O net (fo=3, routed) 0.600 2.381 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0[99]_i_14__2_n_0 SLICE_X170Y324 LUT6 (Prop_lut6_I0_O) 0.134 2.515 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0[15]_i_9__2/O net (fo=1, routed) 0.000 2.515 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0[15]_i_9__2_n_0 SLICE_X170Y324 CARRY4 (Prop_carry4_S[0]_O[3]) 0.292 2.807 f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/reg0_reg[15]_i_4__2/O[3] net (fo=11, routed) 0.493 3.300 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg01[7] SLICE_X168Y325 LUT6 (Prop_lut6_I1_O) 0.120 3.420 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[67]_i_3__2/O net (fo=41, routed) 0.627 4.047 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_i_3__2_5 SLICE_X166Y323 LUT3 (Prop_lut3_I0_O) 0.047 4.094 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[71]_i_4__2/O net (fo=4, routed) 0.648 4.742 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0_reg[68] SLICE_X162Y322 LUT6 (Prop_lut6_I0_O) 0.134 4.876 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[68]_i_1__2/O net (fo=1, routed) 0.000 4.876 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[64] SLICE_X162Y322 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[68]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 8.200 8.200 r BUFHCE_X1Y72 BUFH 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.636 8.836 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X162Y322 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[68]/C clock pessimism 0.000 8.836 clock uncertainty -0.035 8.801 SLICE_X162Y322 FDCE (Setup_fdce_C_D) 0.064 8.865 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[68] ------------------------------------------------------------------- required time 8.865 arrival time -4.876 ------------------------------------------------------------------- slack 3.989 Slack (MET) : 4.005ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[93]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_4 rise@8.200ns - rxWordclkl12_4 rise@0.000ns) Data Path Delay: 3.767ns (logic 1.201ns (31.882%) route 2.566ns (68.118%)) Logic Levels: 2 (LUT4=2) Clock Path Skew: -0.277ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.634ns = ( 8.834 - 8.200 ) Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.911 0.911 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDISPERR[0]) 1.009 1.920 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDISPERR[0] net (fo=5, routed) 1.590 3.511 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gt0_rxdata_out[9] SLICE_X165Y324 LUT4 (Prop_lut4_I0_O) 0.052 3.563 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[93]_i_3__2/O net (fo=5, routed) 0.552 4.114 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[93]_i_3__2_n_0 SLICE_X163Y326 LUT4 (Prop_lut4_I3_O) 0.140 4.254 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[93]_i_1__2/O net (fo=1, routed) 0.424 4.678 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[89] SLICE_X163Y325 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[93]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 8.200 8.200 r BUFHCE_X1Y72 BUFH 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.634 8.834 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X163Y325 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[93]/C clock pessimism 0.000 8.834 clock uncertainty -0.035 8.799 SLICE_X163Y325 FDCE (Setup_fdce_C_D) -0.115 8.684 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[93] ------------------------------------------------------------------- required time 8.684 arrival time -4.678 ------------------------------------------------------------------- slack 4.005 Slack (MET) : 4.014ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[62]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_4 rise@8.200ns - rxWordclkl12_4 rise@0.000ns) Data Path Delay: 3.752ns (logic 1.203ns (32.061%) route 2.549ns (67.939%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.278ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.633ns = ( 8.833 - 8.200 ) Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.911 0.911 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXCHARISK[1]) 1.009 1.920 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXCHARISK[1] net (fo=8, routed) 1.421 3.342 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gt0_rxdata_out[18] SLICE_X167Y324 LUT5 (Prop_lut5_I3_O) 0.054 3.396 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[94]_i_2__2/O net (fo=6, routed) 0.728 4.124 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[94]_i_2__2_n_0 SLICE_X162Y325 LUT4 (Prop_lut4_I1_O) 0.140 4.264 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[62]_i_1__2/O net (fo=1, routed) 0.400 4.664 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[58] SLICE_X161Y325 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[62]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 8.200 8.200 r BUFHCE_X1Y72 BUFH 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.633 8.833 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X161Y325 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[62]/C clock pessimism 0.000 8.833 clock uncertainty -0.035 8.798 SLICE_X161Y325 FDCE (Setup_fdce_C_D) -0.120 8.678 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[62] ------------------------------------------------------------------- required time 8.678 arrival time -4.664 ------------------------------------------------------------------- slack 4.014 Slack (MET) : 4.024ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[94]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_4 rise@8.200ns - rxWordclkl12_4 rise@0.000ns) Data Path Delay: 3.741ns (logic 1.201ns (32.106%) route 2.540ns (67.894%)) Logic Levels: 2 (LUT4=2) Clock Path Skew: -0.277ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.634ns = ( 8.834 - 8.200 ) Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.911 0.911 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[12]) 1.009 1.920 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[12] net (fo=5, routed) 1.263 3.183 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gt0_rxdata_out[14] SLICE_X168Y322 LUT4 (Prop_lut4_I1_O) 0.053 3.236 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[94]_i_3__2/O net (fo=5, routed) 1.009 4.246 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[94]_i_3__2_n_0 SLICE_X164Y326 LUT4 (Prop_lut4_I3_O) 0.139 4.385 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[94]_i_1__2/O net (fo=1, routed) 0.268 4.652 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[90] SLICE_X163Y325 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[94]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 8.200 8.200 r BUFHCE_X1Y72 BUFH 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.634 8.834 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X163Y325 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[94]/C clock pessimism 0.000 8.834 clock uncertainty -0.035 8.799 SLICE_X163Y325 FDCE (Setup_fdce_C_D) -0.122 8.677 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[94] ------------------------------------------------------------------- required time 8.677 arrival time -4.652 ------------------------------------------------------------------- slack 4.024 Slack (MET) : 4.028ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[28]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_4 rise@8.200ns - rxWordclkl12_4 rise@0.000ns) Data Path Delay: 3.766ns (logic 1.198ns (31.814%) route 2.568ns (68.186%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.278ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.633ns = ( 8.833 - 8.200 ) Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.911 0.911 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[0]) 1.009 1.920 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[0] net (fo=13, routed) 1.578 3.498 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gt0_rxdata_out[0] SLICE_X166Y322 LUT5 (Prop_lut5_I0_O) 0.047 3.545 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[92]_i_2__2/O net (fo=6, routed) 0.687 4.232 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[92]_i_2__2_n_0 SLICE_X162Y324 LUT4 (Prop_lut4_I1_O) 0.142 4.374 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[28]_i_1__2/O net (fo=1, routed) 0.303 4.677 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[24] SLICE_X160Y325 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[28]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 8.200 8.200 r BUFHCE_X1Y72 BUFH 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.633 8.833 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X160Y325 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[28]/C clock pessimism 0.000 8.833 clock uncertainty -0.035 8.798 SLICE_X160Y325 FDCE (Setup_fdce_C_D) -0.093 8.705 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[28] ------------------------------------------------------------------- required time 8.705 arrival time -4.677 ------------------------------------------------------------------- slack 4.028 Slack (MET) : 4.034ns (required time - arrival time) Source: ngFEC/SFP_GEN[1].ngCCM_gbt/test_comm_cnt2_reg[15]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[1].ngCCM_gbt/ngCCM_status_counter_o_reg[0][10]/CE (rising edge-triggered cell FDRE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_4 rise@8.200ns - rxWordclkl12_4 rise@0.000ns) Data Path Delay: 3.841ns (logic 0.302ns (7.862%) route 3.539ns (92.138%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.111ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.572ns = ( 8.772 - 8.200 ) Source Clock Delay (SCD): 0.683ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.683 0.683 ngFEC/SFP_GEN[1].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X140Y336 FDCE r ngFEC/SFP_GEN[1].ngCCM_gbt/test_comm_cnt2_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X140Y336 FDCE (Prop_fdce_C_Q) 0.259 0.942 r ngFEC/SFP_GEN[1].ngCCM_gbt/test_comm_cnt2_reg[15]/Q net (fo=154, routed) 1.448 2.390 ngFEC/SFP_GEN[1].ngCCM_gbt/test_comm_cnt2_reg[15] SLICE_X145Y321 LUT2 (Prop_lut2_I0_O) 0.043 2.433 r ngFEC/SFP_GEN[1].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__6/O net (fo=128, routed) 2.091 4.524 ngFEC/SFP_GEN[1].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__6_n_0 SLICE_X130Y314 FDRE r ngFEC/SFP_GEN[1].ngCCM_gbt/ngCCM_status_counter_o_reg[0][10]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 8.200 8.200 r BUFHCE_X1Y72 BUFH 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.572 8.772 ngFEC/SFP_GEN[1].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X130Y314 FDRE r ngFEC/SFP_GEN[1].ngCCM_gbt/ngCCM_status_counter_o_reg[0][10]/C clock pessimism 0.000 8.772 clock uncertainty -0.035 8.737 SLICE_X130Y314 FDRE (Setup_fdre_C_CE) -0.178 8.559 ngFEC/SFP_GEN[1].ngCCM_gbt/ngCCM_status_counter_o_reg[0][10] ------------------------------------------------------------------- required time 8.559 arrival time -4.524 ------------------------------------------------------------------- slack 4.034 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.092ns (arrival time - required time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_4 rise@0.000ns - rxWordclkl12_4 rise@0.000ns) Data Path Delay: 0.190ns (logic 0.128ns (67.322%) route 0.062ns (32.678%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.493ns Source Clock Delay (SCD): 0.341ns Clock Pessimism Removal (CPR): 0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.341 0.341 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X155Y322 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X155Y322 FDCE (Prop_fdce_C_Q) 0.100 0.441 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[16]/Q net (fo=2, routed) 0.062 0.503 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_31_in SLICE_X154Y322 LUT3 (Prop_lut3_I2_O) 0.028 0.531 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1__2/O net (fo=1, routed) 0.000 0.531 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[14] SLICE_X154Y322 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.493 0.493 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X154Y322 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C clock pessimism -0.141 0.352 SLICE_X154Y322 FDRE (Hold_fdre_C_D) 0.087 0.439 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14] ------------------------------------------------------------------- required time -0.439 arrival time 0.531 ------------------------------------------------------------------- slack 0.092 Slack (MET) : 0.093ns (arrival time - required time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_4 rise@0.000ns - rxWordclkl12_4 rise@0.000ns) Data Path Delay: 0.191ns (logic 0.128ns (66.970%) route 0.063ns (33.030%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.501ns Source Clock Delay (SCD): 0.349ns Clock Pessimism Removal (CPR): 0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.349 0.349 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X165Y316 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X165Y316 FDCE (Prop_fdce_C_Q) 0.100 0.449 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Q net (fo=2, routed) 0.063 0.512 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_5_in SLICE_X164Y316 LUT3 (Prop_lut3_I0_O) 0.028 0.540 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[3]_i_1__2/O net (fo=1, routed) 0.000 0.540 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[3] SLICE_X164Y316 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.501 0.501 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X164Y316 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C clock pessimism -0.141 0.360 SLICE_X164Y316 FDRE (Hold_fdre_C_D) 0.087 0.447 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[3] ------------------------------------------------------------------- required time -0.447 arrival time 0.540 ------------------------------------------------------------------- slack 0.093 Slack (MET) : 0.094ns (arrival time - required time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_4 rise@0.000ns - rxWordclkl12_4 rise@0.000ns) Data Path Delay: 0.192ns (logic 0.128ns (66.646%) route 0.064ns (33.354%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.500ns Source Clock Delay (SCD): 0.348ns Clock Pessimism Removal (CPR): 0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.348 0.348 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X165Y317 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X165Y317 FDCE (Prop_fdce_C_Q) 0.100 0.448 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/Q net (fo=2, routed) 0.064 0.512 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/O84[2] SLICE_X164Y317 LUT3 (Prop_lut3_I2_O) 0.028 0.540 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__2/O net (fo=1, routed) 0.000 0.540 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[17] SLICE_X164Y317 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.500 0.500 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X164Y317 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C clock pessimism -0.141 0.359 SLICE_X164Y317 FDRE (Hold_fdre_C_D) 0.087 0.446 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17] ------------------------------------------------------------------- required time -0.446 arrival time 0.540 ------------------------------------------------------------------- slack 0.094 Slack (MET) : 0.111ns (arrival time - required time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[12]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[12]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_4 rise@0.000ns - rxWordclkl12_4 rise@0.000ns) Data Path Delay: 0.209ns (logic 0.128ns (61.382%) route 0.081ns (38.618%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.492ns Source Clock Delay (SCD): 0.341ns Clock Pessimism Removal (CPR): 0.140ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.341 0.341 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X165Y325 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X165Y325 FDCE (Prop_fdce_C_Q) 0.100 0.441 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[12]/Q net (fo=1, routed) 0.081 0.522 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[12] SLICE_X164Y325 LUT6 (Prop_lut6_I5_O) 0.028 0.550 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1[12]_i_1__2/O net (fo=1, routed) 0.000 0.550 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/p_0_out[12] SLICE_X164Y325 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[12]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.492 0.492 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X164Y325 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[12]/C clock pessimism -0.140 0.352 SLICE_X164Y325 FDCE (Hold_fdce_C_D) 0.087 0.439 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[12] ------------------------------------------------------------------- required time -0.439 arrival time 0.550 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.113ns (arrival time - required time) Source: ngFEC/SFP_GEN[1].rx_data_reg[1][64]/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[64]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_4 rise@0.000ns - rxWordclkl12_4 rise@0.000ns) Data Path Delay: 0.211ns (logic 0.128ns (60.799%) route 0.083ns (39.201%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.501ns Source Clock Delay (SCD): 0.348ns Clock Pessimism Removal (CPR): 0.142ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.348 0.348 ngFEC/clktest21_in SLICE_X161Y316 FDRE r ngFEC/SFP_GEN[1].rx_data_reg[1][64]/C ------------------------------------------------------------------- ------------------- SLICE_X161Y316 FDRE (Prop_fdre_C_Q) 0.100 0.448 r ngFEC/SFP_GEN[1].rx_data_reg[1][64]/Q net (fo=1, routed) 0.083 0.531 ngFEC/gbtbank2_l12_117/RX_Word_rx40_reg[78][48] SLICE_X160Y316 LUT3 (Prop_lut3_I2_O) 0.028 0.559 r ngFEC/gbtbank2_l12_117/RX_Word_rx40[64]_i_1__9/O net (fo=1, routed) 0.000 0.559 ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[83]_0[40] SLICE_X160Y316 FDCE r ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[64]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.501 0.501 ngFEC/SFP_GEN[1].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X160Y316 FDCE r ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[64]/C clock pessimism -0.142 0.359 SLICE_X160Y316 FDCE (Hold_fdce_C_D) 0.087 0.446 ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[64] ------------------------------------------------------------------- required time -0.446 arrival time 0.559 ------------------------------------------------------------------- slack 0.113 Slack (MET) : 0.118ns (arrival time - required time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_4 rise@0.000ns - rxWordclkl12_4 rise@0.000ns) Data Path Delay: 0.216ns (logic 0.128ns (59.307%) route 0.088ns (40.693%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.500ns Source Clock Delay (SCD): 0.348ns Clock Pessimism Removal (CPR): 0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.348 0.348 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X165Y317 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X165Y317 FDCE (Prop_fdce_C_Q) 0.100 0.448 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/Q net (fo=2, routed) 0.088 0.536 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_29_in SLICE_X164Y317 LUT3 (Prop_lut3_I0_O) 0.028 0.564 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[15]_i_1__2/O net (fo=1, routed) 0.000 0.564 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[15] SLICE_X164Y317 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.500 0.500 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X164Y317 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15]/C clock pessimism -0.141 0.359 SLICE_X164Y317 FDRE (Hold_fdre_C_D) 0.087 0.446 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[15] ------------------------------------------------------------------- required time -0.446 arrival time 0.564 ------------------------------------------------------------------- slack 0.118 Slack (MET) : 0.122ns (arrival time - required time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_4 rise@0.000ns - rxWordclkl12_4 rise@0.000ns) Data Path Delay: 0.220ns (logic 0.128ns (58.166%) route 0.092ns (41.834%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.501ns Source Clock Delay (SCD): 0.349ns Clock Pessimism Removal (CPR): 0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.349 0.349 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X165Y316 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X165Y316 FDCE (Prop_fdce_C_Q) 0.100 0.449 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[5]/Q net (fo=2, routed) 0.092 0.541 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_9_in SLICE_X164Y316 LUT3 (Prop_lut3_I0_O) 0.028 0.569 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[5]_i_1__2/O net (fo=1, routed) 0.000 0.569 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[5] SLICE_X164Y316 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.501 0.501 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X164Y316 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C clock pessimism -0.141 0.360 SLICE_X164Y316 FDRE (Hold_fdre_C_D) 0.087 0.447 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[5] ------------------------------------------------------------------- required time -0.447 arrival time 0.569 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.126ns (arrival time - required time) Source: ngFEC/SFP_GEN[1].ngCCM_gbt/ngCCM_status_counter_reg[3][13]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[1].ngCCM_gbt/ngCCM_status_counter_o_reg[3][13]/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_4 rise@0.000ns - rxWordclkl12_4 rise@0.000ns) Data Path Delay: 0.198ns (logic 0.100ns (50.586%) route 0.098ns (49.414%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.495ns Source Clock Delay (SCD): 0.341ns Clock Pessimism Removal (CPR): 0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.341 0.341 ngFEC/SFP_GEN[1].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X141Y313 FDCE r ngFEC/SFP_GEN[1].ngCCM_gbt/ngCCM_status_counter_reg[3][13]/C ------------------------------------------------------------------- ------------------- SLICE_X141Y313 FDCE (Prop_fdce_C_Q) 0.100 0.441 r ngFEC/SFP_GEN[1].ngCCM_gbt/ngCCM_status_counter_reg[3][13]/Q net (fo=2, routed) 0.098 0.539 ngFEC/SFP_GEN[1].ngCCM_gbt/ngCCM_status_counter_reg[3]__0[13] SLICE_X140Y314 FDRE r ngFEC/SFP_GEN[1].ngCCM_gbt/ngCCM_status_counter_o_reg[3][13]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.495 0.495 ngFEC/SFP_GEN[1].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X140Y314 FDRE r ngFEC/SFP_GEN[1].ngCCM_gbt/ngCCM_status_counter_o_reg[3][13]/C clock pessimism -0.141 0.354 SLICE_X140Y314 FDRE (Hold_fdre_C_D) 0.059 0.413 ngFEC/SFP_GEN[1].ngCCM_gbt/ngCCM_status_counter_o_reg[3][13] ------------------------------------------------------------------- required time -0.413 arrival time 0.539 ------------------------------------------------------------------- slack 0.126 Slack (MET) : 0.127ns (arrival time - required time) Source: ngFEC/SFP_GEN[1].rx_data_reg[1][23]/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[23]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_4 rise@0.000ns - rxWordclkl12_4 rise@0.000ns) Data Path Delay: 0.197ns (logic 0.100ns (50.843%) route 0.097ns (49.157%)) Logic Levels: 0 Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.493ns Source Clock Delay (SCD): 0.341ns Clock Pessimism Removal (CPR): 0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.341 0.341 ngFEC/clktest21_in SLICE_X151Y321 FDRE r ngFEC/SFP_GEN[1].rx_data_reg[1][23]/C ------------------------------------------------------------------- ------------------- SLICE_X151Y321 FDRE (Prop_fdre_C_Q) 0.100 0.441 r ngFEC/SFP_GEN[1].rx_data_reg[1][23]/Q net (fo=1, routed) 0.097 0.538 ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[83]_0[15] SLICE_X150Y322 FDCE r ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[23]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.493 0.493 ngFEC/SFP_GEN[1].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X150Y322 FDCE r ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[23]/C clock pessimism -0.141 0.352 SLICE_X150Y322 FDCE (Hold_fdce_C_D) 0.059 0.411 ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[23] ------------------------------------------------------------------- required time -0.411 arrival time 0.538 ------------------------------------------------------------------- slack 0.127 Slack (MET) : 0.127ns (arrival time - required time) Source: ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Clock_20MHz_dl_reg[1]/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/D (rising edge-triggered cell SRL16E clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_4 rise@0.000ns - rxWordclkl12_4 rise@0.000ns) Data Path Delay: 0.262ns (logic 0.100ns (38.162%) route 0.162ns (61.838%)) Logic Levels: 0 Clock Path Skew: 0.033ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.504ns Source Clock Delay (SCD): 0.351ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.351 0.351 ngFEC/SFP_GEN[1].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X157Y310 FDRE r ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Clock_20MHz_dl_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X157Y310 FDRE (Prop_fdre_C_Q) 0.100 0.451 r ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Clock_20MHz_dl_reg[1]/Q net (fo=2, routed) 0.162 0.613 ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Clock_20MHz_dl_reg_n_0_[1] SLICE_X154Y310 SRL16E r ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.504 0.504 ngFEC/SFP_GEN[1].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X154Y310 SRL16E r ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK clock pessimism -0.120 0.384 SLICE_X154Y310 SRL16E (Hold_srl16e_CLK_D) 0.102 0.486 ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2 ------------------------------------------------------------------- required time -0.486 arrival time 0.613 ------------------------------------------------------------------- slack 0.127 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: rxWordclkl12_4 Waveform(ns): { 0.000 4.100 } Period(ns): 8.200 Sources: { ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/RXUSRCLK n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y25 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK Min Period n/a GTXE2_CHANNEL/RXUSRCLK2 n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y25 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X158Y300 ngFEC/SFP_GEN[1].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[74]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X158Y300 ngFEC/SFP_GEN[1].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[76]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X154Y310 ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Clock_20MHz_dl_reg[4]__0/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X150Y322 ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[30]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X150Y322 ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[31]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X157Y322 ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[34]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X157Y322 ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[38]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X157Y315 ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[42]/C Low Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X154Y310 ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK Low Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X154Y310 ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK Low Pulse Width Slow FDRE/C n/a 0.400 4.100 3.700 SLICE_X158Y300 ngFEC/SFP_GEN[1].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[74]/C Low Pulse Width Slow FDRE/C n/a 0.400 4.100 3.700 SLICE_X158Y300 ngFEC/SFP_GEN[1].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[76]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X155Y315 ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[62]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X160Y316 ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[66]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X160Y316 ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Word_rx40_reg[76]/C Low Pulse Width Slow FDRE/C n/a 0.400 4.100 3.700 SLICE_X159Y307 ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_m_reg/C Low Pulse Width Fast FDRE/C n/a 0.400 4.100 3.700 SLICE_X153Y318 ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[19]/C Low Pulse Width Slow FDRE/C n/a 0.400 4.100 3.700 SLICE_X166Y316 ngFEC/SFP_GEN[1].rx_data_reg[1][53]/C High Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X154Y310 ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X154Y310 ngFEC/SFP_GEN[1].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X135Y340 ngFEC/SFP_GEN[1].ngCCM_gbt/RX_wordclk_cnt_reg[0]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X135Y340 ngFEC/SFP_GEN[1].ngCCM_gbt/RX_wordclk_cnt_reg[1]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X135Y340 ngFEC/SFP_GEN[1].ngCCM_gbt/RX_wordclk_cnt_reg[2]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X135Y340 ngFEC/SFP_GEN[1].ngCCM_gbt/RX_wordclk_cnt_reg[3]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X135Y341 ngFEC/SFP_GEN[1].ngCCM_gbt/RX_wordclk_cnt_reg[4]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X135Y341 ngFEC/SFP_GEN[1].ngCCM_gbt/RX_wordclk_cnt_reg[5]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X135Y341 ngFEC/SFP_GEN[1].ngCCM_gbt/RX_wordclk_cnt_reg[6]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X135Y341 ngFEC/SFP_GEN[1].ngCCM_gbt/RX_wordclk_cnt_reg[7]/C --------------------------------------------------------------------------------------------------- From Clock: rxWordclkl12_5 To Clock: rxWordclkl12_5 Setup : 0 Failing Endpoints, Worst Slack 3.903ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.104ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.458ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.903ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[26]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_5 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_5 rise@8.200ns - rxWordclkl12_5 rise@0.000ns) Data Path Delay: 4.147ns (logic 0.551ns (13.285%) route 3.596ns (86.715%)) Logic Levels: 4 (CARRY4=1 LUT4=2 LUT6=1) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.698ns = ( 8.898 - 8.200 ) Source Clock Delay (SCD): 0.745ns Clock Pessimism Removal (CPR): 0.025ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.745 0.745 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK SLICE_X177Y311 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X177Y311 FDCE (Prop_fdce_C_Q) 0.223 0.968 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]/Q net (fo=37, routed) 0.935 1.903 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]_0 SLICE_X177Y304 LUT4 (Prop_lut4_I1_O) 0.043 1.946 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[99]_i_17__3/O net (fo=1, routed) 0.000 1.946 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[99]_i_17__3_n_0 SLICE_X177Y304 CARRY4 (Prop_carry4_S[1]_O[1]) 0.109 2.055 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0_reg[99]_i_3__3/O[1] net (fo=18, routed) 1.204 3.259 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg01[1] SLICE_X182Y302 LUT6 (Prop_lut6_I5_O) 0.123 3.382 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[47]_i_3__3/O net (fo=41, routed) 1.042 4.425 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0_reg[43]_0 SLICE_X175Y307 LUT4 (Prop_lut4_I2_O) 0.053 4.478 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[26]_i_1__3/O net (fo=1, routed) 0.415 4.892 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[99]_1[22] SLICE_X176Y307 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[26]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 8.200 8.200 r BUFHCE_X1Y73 BUFH 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.698 8.898 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X176Y307 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[26]/C clock pessimism 0.025 8.923 clock uncertainty -0.035 8.888 SLICE_X176Y307 FDCE (Setup_fdce_C_D) -0.092 8.796 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[26] ------------------------------------------------------------------- required time 8.796 arrival time -4.892 ------------------------------------------------------------------- slack 3.903 Slack (MET) : 3.983ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[25]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_5 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_5 rise@8.200ns - rxWordclkl12_5 rise@0.000ns) Data Path Delay: 4.061ns (logic 0.546ns (13.445%) route 3.515ns (86.555%)) Logic Levels: 4 (CARRY4=1 LUT4=2 LUT6=1) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.698ns = ( 8.898 - 8.200 ) Source Clock Delay (SCD): 0.745ns Clock Pessimism Removal (CPR): 0.025ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.745 0.745 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK SLICE_X177Y311 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X177Y311 FDCE (Prop_fdce_C_Q) 0.223 0.968 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]/Q net (fo=37, routed) 0.935 1.903 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]_0 SLICE_X177Y304 LUT4 (Prop_lut4_I1_O) 0.043 1.946 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[99]_i_17__3/O net (fo=1, routed) 0.000 1.946 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[99]_i_17__3_n_0 SLICE_X177Y304 CARRY4 (Prop_carry4_S[1]_O[1]) 0.109 2.055 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0_reg[99]_i_3__3/O[1] net (fo=18, routed) 1.204 3.259 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg01[1] SLICE_X182Y302 LUT6 (Prop_lut6_I5_O) 0.123 3.382 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[47]_i_3__3/O net (fo=41, routed) 0.956 4.339 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0_reg[43]_0 SLICE_X175Y307 LUT4 (Prop_lut4_I2_O) 0.048 4.387 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[25]_i_1__3/O net (fo=1, routed) 0.419 4.806 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[99]_1[21] SLICE_X176Y307 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[25]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 8.200 8.200 r BUFHCE_X1Y73 BUFH 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.698 8.898 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X176Y307 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[25]/C clock pessimism 0.025 8.923 clock uncertainty -0.035 8.888 SLICE_X176Y307 FDCE (Setup_fdce_C_D) -0.099 8.789 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[25] ------------------------------------------------------------------- required time 8.789 arrival time -4.806 ------------------------------------------------------------------- slack 3.983 Slack (MET) : 3.987ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[6]/CE (rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_5 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_5 rise@8.200ns - rxWordclkl12_5 rise@0.000ns) Data Path Delay: 3.886ns (logic 0.943ns (24.268%) route 2.943ns (75.732%)) Logic Levels: 5 (CARRY4=1 LUT3=1 LUT4=1 LUT6=2) Clock Path Skew: -0.021ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.699ns = ( 8.899 - 8.200 ) Source Clock Delay (SCD): 0.745ns Clock Pessimism Removal (CPR): 0.025ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.745 0.745 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK SLICE_X177Y311 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X177Y311 FDCE (Prop_fdce_C_Q) 0.204 0.949 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/Q net (fo=23, routed) 0.682 1.631 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]_0 SLICE_X177Y304 LUT4 (Prop_lut4_I1_O) 0.136 1.767 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[99]_i_14__3/O net (fo=3, routed) 0.355 2.122 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[99]_i_14__3_n_0 SLICE_X177Y305 LUT6 (Prop_lut6_I0_O) 0.135 2.257 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[15]_i_9__3/O net (fo=1, routed) 0.000 2.257 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[15]_i_9__3_n_0 SLICE_X177Y305 CARRY4 (Prop_carry4_S[0]_O[3]) 0.296 2.553 f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0_reg[15]_i_4__3/O[3] net (fo=11, routed) 0.675 3.228 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg01[7] SLICE_X182Y304 LUT6 (Prop_lut6_I1_O) 0.120 3.348 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[35]_i_3__3/O net (fo=33, routed) 0.719 4.067 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0_reg[3] SLICE_X175Y307 LUT3 (Prop_lut3_I2_O) 0.052 4.119 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[7]_i_1__3/O net (fo=4, routed) 0.512 4.631 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[99]_0[1] SLICE_X176Y303 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 8.200 8.200 r BUFHCE_X1Y73 BUFH 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.699 8.899 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X176Y303 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[6]/C clock pessimism 0.025 8.924 clock uncertainty -0.035 8.889 SLICE_X176Y303 FDCE (Setup_fdce_C_CE) -0.271 8.618 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[6] ------------------------------------------------------------------- required time 8.618 arrival time -4.631 ------------------------------------------------------------------- slack 3.987 Slack (MET) : 4.017ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[5]/CE (rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_5 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_5 rise@8.200ns - rxWordclkl12_5 rise@0.000ns) Data Path Delay: 3.833ns (logic 0.943ns (24.603%) route 2.890ns (75.397%)) Logic Levels: 5 (CARRY4=1 LUT3=1 LUT4=1 LUT6=2) Clock Path Skew: -0.021ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.699ns = ( 8.899 - 8.200 ) Source Clock Delay (SCD): 0.745ns Clock Pessimism Removal (CPR): 0.025ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.745 0.745 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK SLICE_X177Y311 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X177Y311 FDCE (Prop_fdce_C_Q) 0.204 0.949 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/Q net (fo=23, routed) 0.682 1.631 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]_0 SLICE_X177Y304 LUT4 (Prop_lut4_I1_O) 0.136 1.767 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[99]_i_14__3/O net (fo=3, routed) 0.355 2.122 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[99]_i_14__3_n_0 SLICE_X177Y305 LUT6 (Prop_lut6_I0_O) 0.135 2.257 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[15]_i_9__3/O net (fo=1, routed) 0.000 2.257 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[15]_i_9__3_n_0 SLICE_X177Y305 CARRY4 (Prop_carry4_S[0]_O[3]) 0.296 2.553 f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0_reg[15]_i_4__3/O[3] net (fo=11, routed) 0.675 3.228 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg01[7] SLICE_X182Y304 LUT6 (Prop_lut6_I1_O) 0.120 3.348 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[35]_i_3__3/O net (fo=33, routed) 0.719 4.067 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0_reg[3] SLICE_X175Y307 LUT3 (Prop_lut3_I2_O) 0.052 4.119 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[7]_i_1__3/O net (fo=4, routed) 0.459 4.578 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[99]_0[1] SLICE_X177Y305 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 8.200 8.200 r BUFHCE_X1Y73 BUFH 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.699 8.899 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X177Y305 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[5]/C clock pessimism 0.025 8.924 clock uncertainty -0.035 8.889 SLICE_X177Y305 FDCE (Setup_fdce_C_CE) -0.294 8.595 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[5] ------------------------------------------------------------------- required time 8.595 arrival time -4.578 ------------------------------------------------------------------- slack 4.017 Slack (MET) : 4.040ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[4]/CE (rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_5 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_5 rise@8.200ns - rxWordclkl12_5 rise@0.000ns) Data Path Delay: 3.807ns (logic 0.943ns (24.773%) route 2.864ns (75.227%)) Logic Levels: 5 (CARRY4=1 LUT3=1 LUT4=1 LUT6=2) Clock Path Skew: -0.047ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.698ns = ( 8.898 - 8.200 ) Source Clock Delay (SCD): 0.745ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.745 0.745 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK SLICE_X177Y311 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X177Y311 FDCE (Prop_fdce_C_Q) 0.204 0.949 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/Q net (fo=23, routed) 0.682 1.631 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]_0 SLICE_X177Y304 LUT4 (Prop_lut4_I1_O) 0.136 1.767 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[99]_i_14__3/O net (fo=3, routed) 0.355 2.122 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[99]_i_14__3_n_0 SLICE_X177Y305 LUT6 (Prop_lut6_I0_O) 0.135 2.257 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[15]_i_9__3/O net (fo=1, routed) 0.000 2.257 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[15]_i_9__3_n_0 SLICE_X177Y305 CARRY4 (Prop_carry4_S[0]_O[3]) 0.296 2.553 f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0_reg[15]_i_4__3/O[3] net (fo=11, routed) 0.675 3.228 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg01[7] SLICE_X182Y304 LUT6 (Prop_lut6_I1_O) 0.120 3.348 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[35]_i_3__3/O net (fo=33, routed) 0.719 4.067 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0_reg[3] SLICE_X175Y307 LUT3 (Prop_lut3_I2_O) 0.052 4.119 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[7]_i_1__3/O net (fo=4, routed) 0.433 4.552 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[99]_0[1] SLICE_X178Y307 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 8.200 8.200 r BUFHCE_X1Y73 BUFH 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.698 8.898 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X178Y307 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[4]/C clock pessimism 0.000 8.898 clock uncertainty -0.035 8.863 SLICE_X178Y307 FDCE (Setup_fdce_C_CE) -0.271 8.592 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[4] ------------------------------------------------------------------- required time 8.592 arrival time -4.552 ------------------------------------------------------------------- slack 4.040 Slack (MET) : 4.040ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[7]/CE (rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_5 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_5 rise@8.200ns - rxWordclkl12_5 rise@0.000ns) Data Path Delay: 3.807ns (logic 0.943ns (24.773%) route 2.864ns (75.227%)) Logic Levels: 5 (CARRY4=1 LUT3=1 LUT4=1 LUT6=2) Clock Path Skew: -0.047ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.698ns = ( 8.898 - 8.200 ) Source Clock Delay (SCD): 0.745ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.745 0.745 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK SLICE_X177Y311 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X177Y311 FDCE (Prop_fdce_C_Q) 0.204 0.949 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/Q net (fo=23, routed) 0.682 1.631 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]_0 SLICE_X177Y304 LUT4 (Prop_lut4_I1_O) 0.136 1.767 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[99]_i_14__3/O net (fo=3, routed) 0.355 2.122 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[99]_i_14__3_n_0 SLICE_X177Y305 LUT6 (Prop_lut6_I0_O) 0.135 2.257 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[15]_i_9__3/O net (fo=1, routed) 0.000 2.257 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[15]_i_9__3_n_0 SLICE_X177Y305 CARRY4 (Prop_carry4_S[0]_O[3]) 0.296 2.553 f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0_reg[15]_i_4__3/O[3] net (fo=11, routed) 0.675 3.228 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg01[7] SLICE_X182Y304 LUT6 (Prop_lut6_I1_O) 0.120 3.348 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[35]_i_3__3/O net (fo=33, routed) 0.719 4.067 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0_reg[3] SLICE_X175Y307 LUT3 (Prop_lut3_I2_O) 0.052 4.119 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[7]_i_1__3/O net (fo=4, routed) 0.433 4.552 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[99]_0[1] SLICE_X178Y307 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[7]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 8.200 8.200 r BUFHCE_X1Y73 BUFH 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.698 8.898 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X178Y307 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[7]/C clock pessimism 0.000 8.898 clock uncertainty -0.035 8.863 SLICE_X178Y307 FDCE (Setup_fdce_C_CE) -0.271 8.592 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[7] ------------------------------------------------------------------- required time 8.592 arrival time -4.552 ------------------------------------------------------------------- slack 4.040 Slack (MET) : 4.090ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[24]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_5 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_5 rise@8.200ns - rxWordclkl12_5 rise@0.000ns) Data Path Delay: 3.957ns (logic 0.552ns (13.951%) route 3.405ns (86.049%)) Logic Levels: 4 (CARRY4=1 LUT4=2 LUT6=1) Clock Path Skew: -0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.698ns = ( 8.898 - 8.200 ) Source Clock Delay (SCD): 0.745ns Clock Pessimism Removal (CPR): 0.025ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.745 0.745 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK SLICE_X177Y311 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X177Y311 FDCE (Prop_fdce_C_Q) 0.223 0.968 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]/Q net (fo=37, routed) 0.935 1.903 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]_0 SLICE_X177Y304 LUT4 (Prop_lut4_I1_O) 0.043 1.946 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[99]_i_17__3/O net (fo=1, routed) 0.000 1.946 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[99]_i_17__3_n_0 SLICE_X177Y304 CARRY4 (Prop_carry4_S[1]_O[1]) 0.109 2.055 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0_reg[99]_i_3__3/O[1] net (fo=18, routed) 1.204 3.259 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg01[1] SLICE_X182Y302 LUT6 (Prop_lut6_I5_O) 0.123 3.382 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[47]_i_3__3/O net (fo=41, routed) 0.944 4.326 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0_reg[43]_0 SLICE_X175Y307 LUT4 (Prop_lut4_I2_O) 0.054 4.380 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/reg0[24]_i_1__3/O net (fo=1, routed) 0.322 4.702 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[99]_1[20] SLICE_X176Y307 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[24]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 8.200 8.200 r BUFHCE_X1Y73 BUFH 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.698 8.898 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X176Y307 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[24]/C clock pessimism 0.025 8.923 clock uncertainty -0.035 8.888 SLICE_X176Y307 FDCE (Setup_fdce_C_D) -0.096 8.792 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[24] ------------------------------------------------------------------- required time 8.792 arrival time -4.702 ------------------------------------------------------------------- slack 4.090 Slack (MET) : 4.106ns (required time - arrival time) Source: ngFEC/SFP_GEN[9].ngCCM_gbt/test_comm_cnt2_reg[15]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_o_reg[2][7]/CE (rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_5 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_5 rise@8.200ns - rxWordclkl12_5 rise@0.000ns) Data Path Delay: 3.864ns (logic 0.302ns (7.816%) route 3.562ns (92.184%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.006ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.700ns = ( 8.900 - 8.200 ) Source Clock Delay (SCD): 0.694ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.694 0.694 ngFEC/SFP_GEN[9].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X160Y312 FDCE r ngFEC/SFP_GEN[9].ngCCM_gbt/test_comm_cnt2_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X160Y312 FDCE (Prop_fdce_C_Q) 0.259 0.953 r ngFEC/SFP_GEN[9].ngCCM_gbt/test_comm_cnt2_reg[15]/Q net (fo=154, routed) 1.865 2.818 ngFEC/SFP_GEN[9].ngCCM_gbt/test_comm_cnt2_reg[15] SLICE_X163Y300 LUT2 (Prop_lut2_I0_O) 0.043 2.861 r ngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__7/O net (fo=128, routed) 1.697 4.558 ngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__7_n_0 SLICE_X188Y302 FDRE r ngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_o_reg[2][7]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 8.200 8.200 r BUFHCE_X1Y73 BUFH 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.700 8.900 ngFEC/SFP_GEN[9].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X188Y302 FDRE r ngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_o_reg[2][7]/C clock pessimism 0.000 8.900 clock uncertainty -0.035 8.865 SLICE_X188Y302 FDRE (Setup_fdre_C_CE) -0.201 8.664 ngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_o_reg[2][7] ------------------------------------------------------------------- required time 8.664 arrival time -4.558 ------------------------------------------------------------------- slack 4.106 Slack (MET) : 4.106ns (required time - arrival time) Source: ngFEC/SFP_GEN[9].ngCCM_gbt/test_comm_cnt2_reg[15]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_o_reg[3][12]/CE (rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_5 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_5 rise@8.200ns - rxWordclkl12_5 rise@0.000ns) Data Path Delay: 3.864ns (logic 0.302ns (7.816%) route 3.562ns (92.184%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.006ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.700ns = ( 8.900 - 8.200 ) Source Clock Delay (SCD): 0.694ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.694 0.694 ngFEC/SFP_GEN[9].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X160Y312 FDCE r ngFEC/SFP_GEN[9].ngCCM_gbt/test_comm_cnt2_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X160Y312 FDCE (Prop_fdce_C_Q) 0.259 0.953 r ngFEC/SFP_GEN[9].ngCCM_gbt/test_comm_cnt2_reg[15]/Q net (fo=154, routed) 1.865 2.818 ngFEC/SFP_GEN[9].ngCCM_gbt/test_comm_cnt2_reg[15] SLICE_X163Y300 LUT2 (Prop_lut2_I0_O) 0.043 2.861 r ngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__7/O net (fo=128, routed) 1.697 4.558 ngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_o[6][15]_i_1__7_n_0 SLICE_X188Y302 FDRE r ngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_o_reg[3][12]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 8.200 8.200 r BUFHCE_X1Y73 BUFH 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.700 8.900 ngFEC/SFP_GEN[9].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X188Y302 FDRE r ngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_o_reg[3][12]/C clock pessimism 0.000 8.900 clock uncertainty -0.035 8.865 SLICE_X188Y302 FDRE (Setup_fdre_C_CE) -0.201 8.664 ngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_o_reg[3][12] ------------------------------------------------------------------- required time 8.664 arrival time -4.558 ------------------------------------------------------------------- slack 4.106 Slack (MET) : 4.165ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[1]/CE (rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_5 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_5 rise@8.200ns - rxWordclkl12_5 rise@0.000ns) Data Path Delay: 3.771ns (logic 0.934ns (24.767%) route 2.837ns (75.233%)) Logic Levels: 5 (CARRY4=1 LUT4=2 LUT6=2) Clock Path Skew: -0.051ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.694ns = ( 8.894 - 8.200 ) Source Clock Delay (SCD): 0.745ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.745 0.745 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK SLICE_X177Y311 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X177Y311 FDCE (Prop_fdce_C_Q) 0.204 0.949 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/Q net (fo=23, routed) 0.682 1.631 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]_0 SLICE_X177Y304 LUT4 (Prop_lut4_I1_O) 0.136 1.767 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[99]_i_14__3/O net (fo=3, routed) 0.355 2.122 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[99]_i_14__3_n_0 SLICE_X177Y305 LUT6 (Prop_lut6_I0_O) 0.135 2.257 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[15]_i_9__3/O net (fo=1, routed) 0.000 2.257 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[15]_i_9__3_n_0 SLICE_X177Y305 CARRY4 (Prop_carry4_S[0]_O[3]) 0.296 2.553 f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0_reg[15]_i_4__3/O[3] net (fo=11, routed) 0.675 3.228 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg01[7] SLICE_X182Y304 LUT6 (Prop_lut6_I1_O) 0.120 3.348 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[35]_i_3__3/O net (fo=33, routed) 0.719 4.067 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0_reg[3] SLICE_X175Y307 LUT4 (Prop_lut4_I3_O) 0.043 4.110 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/reg0[3]_i_1__3/O net (fo=4, routed) 0.406 4.516 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[99]_0[0] SLICE_X170Y309 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 8.200 8.200 r BUFHCE_X1Y73 BUFH 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.694 8.894 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X170Y309 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[1]/C clock pessimism 0.000 8.894 clock uncertainty -0.035 8.859 SLICE_X170Y309 FDCE (Setup_fdce_C_CE) -0.178 8.681 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[1] ------------------------------------------------------------------- required time 8.681 arrival time -4.516 ------------------------------------------------------------------- slack 4.165 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.104ns (arrival time - required time) Source: ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Clock_20MHz_dl_reg[1]/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/D (rising edge-triggered cell SRL16E clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_5 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_5 rise@0.000ns - rxWordclkl12_5 rise@0.000ns) Data Path Delay: 0.217ns (logic 0.100ns (46.133%) route 0.117ns (53.867%)) Logic Levels: 0 Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.507ns Source Clock Delay (SCD): 0.353ns Clock Pessimism Removal (CPR): 0.143ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.353 0.353 ngFEC/SFP_GEN[9].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X159Y305 FDRE r ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Clock_20MHz_dl_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X159Y305 FDRE (Prop_fdre_C_Q) 0.100 0.453 r ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Clock_20MHz_dl_reg[1]/Q net (fo=2, routed) 0.117 0.570 ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Clock_20MHz_dl_reg_n_0_[1] SLICE_X158Y305 SRL16E r ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.507 0.507 ngFEC/SFP_GEN[9].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X158Y305 SRL16E r ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK clock pessimism -0.143 0.364 SLICE_X158Y305 SRL16E (Hold_srl16e_CLK_D) 0.102 0.466 ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2 ------------------------------------------------------------------- required time -0.466 arrival time 0.570 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.105ns (arrival time - required time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[2]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/shiftPsAddr_reg/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_5 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_5 rise@0.000ns - rxWordclkl12_5 rise@0.000ns) Data Path Delay: 0.203ns (logic 0.128ns (63.073%) route 0.075ns (36.927%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.539ns Source Clock Delay (SCD): 0.383ns Clock Pessimism Removal (CPR): 0.145ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.383 0.383 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK SLICE_X181Y310 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X181Y310 FDCE (Prop_fdce_C_Q) 0.100 0.483 f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[2]/Q net (fo=6, routed) 0.075 0.558 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt[2] SLICE_X180Y310 LUT6 (Prop_lut6_I4_O) 0.028 0.586 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/shiftPsAddr_i_1__3/O net (fo=1, routed) 0.000 0.586 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/shiftPsAddr3_out SLICE_X180Y310 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/shiftPsAddr_reg/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.539 0.539 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK SLICE_X180Y310 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/shiftPsAddr_reg/C clock pessimism -0.145 0.394 SLICE_X180Y310 FDCE (Hold_fdce_C_D) 0.087 0.481 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/shiftPsAddr_reg ------------------------------------------------------------------- required time -0.481 arrival time 0.586 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_5 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_5 rise@0.000ns - rxWordclkl12_5 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.537ns Source Clock Delay (SCD): 0.382ns Clock Pessimism Removal (CPR): 0.155ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.382 0.382 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in SLICE_X185Y312 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X185Y312 FDRE (Prop_fdre_C_Q) 0.100 0.482 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q net (fo=1, routed) 0.055 0.537 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync1 SLICE_X185Y312 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.537 0.537 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in SLICE_X185Y312 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C clock pessimism -0.155 0.382 SLICE_X185Y312 FDRE (Hold_fdre_C_D) 0.047 0.429 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.429 arrival time 0.537 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.110ns (arrival time - required time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[16]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[16]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_5 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_5 rise@0.000ns - rxWordclkl12_5 rise@0.000ns) Data Path Delay: 0.231ns (logic 0.128ns (55.341%) route 0.103ns (44.659%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.034ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.535ns Source Clock Delay (SCD): 0.381ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.381 0.381 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X175Y307 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X175Y307 FDCE (Prop_fdce_C_Q) 0.100 0.481 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[16]/Q net (fo=1, routed) 0.103 0.584 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[16] SLICE_X170Y307 LUT6 (Prop_lut6_I5_O) 0.028 0.612 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1[16]_i_1__3/O net (fo=1, routed) 0.000 0.612 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/p_0_out[16] SLICE_X170Y307 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[16]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.535 0.535 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X170Y307 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[16]/C clock pessimism -0.120 0.415 SLICE_X170Y307 FDCE (Hold_fdce_C_D) 0.087 0.502 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[16] ------------------------------------------------------------------- required time -0.502 arrival time 0.612 ------------------------------------------------------------------- slack 0.110 Slack (MET) : 0.111ns (arrival time - required time) Source: ngFEC/SFP_GEN[9].rx_data_reg[9][28]/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[28]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_5 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_5 rise@0.000ns - rxWordclkl12_5 rise@0.000ns) Data Path Delay: 0.204ns (logic 0.100ns (48.975%) route 0.104ns (51.025%)) Logic Levels: 0 Clock Path Skew: 0.034ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.535ns Source Clock Delay (SCD): 0.381ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.381 0.381 ngFEC/clktest13_in SLICE_X168Y303 FDRE r ngFEC/SFP_GEN[9].rx_data_reg[9][28]/C ------------------------------------------------------------------- ------------------- SLICE_X168Y303 FDRE (Prop_fdre_C_Q) 0.100 0.481 r ngFEC/SFP_GEN[9].rx_data_reg[9][28]/Q net (fo=1, routed) 0.104 0.585 ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[83]_0[20] SLICE_X166Y303 FDCE r ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[28]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.535 0.535 ngFEC/SFP_GEN[9].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X166Y303 FDCE r ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[28]/C clock pessimism -0.120 0.415 SLICE_X166Y303 FDCE (Hold_fdce_C_D) 0.059 0.474 ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[28] ------------------------------------------------------------------- required time -0.474 arrival time 0.585 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.112ns (arrival time - required time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[9].rx_data_reg[9][25]/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_5 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_5 rise@0.000ns - rxWordclkl12_5 rise@0.000ns) Data Path Delay: 0.205ns (logic 0.100ns (48.737%) route 0.105ns (51.263%)) Logic Levels: 0 Clock Path Skew: 0.034ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.536ns Source Clock Delay (SCD): 0.382ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.382 0.382 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X168Y302 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X168Y302 FDRE (Prop_fdre_C_Q) 0.100 0.482 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/Q net (fo=1, routed) 0.105 0.587 ngFEC/GBT_rx_data[5]_1372[25] SLICE_X166Y302 FDRE r ngFEC/SFP_GEN[9].rx_data_reg[9][25]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.536 0.536 ngFEC/clktest13_in SLICE_X166Y302 FDRE r ngFEC/SFP_GEN[9].rx_data_reg[9][25]/C clock pessimism -0.120 0.416 SLICE_X166Y302 FDRE (Hold_fdre_C_D) 0.059 0.475 ngFEC/SFP_GEN[9].rx_data_reg[9][25] ------------------------------------------------------------------- required time -0.475 arrival time 0.587 ------------------------------------------------------------------- slack 0.112 Slack (MET) : 0.114ns (arrival time - required time) Source: ngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_reg[7][25]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_o_reg[7][25]/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_5 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_5 rise@0.000ns - rxWordclkl12_5 rise@0.000ns) Data Path Delay: 0.157ns (logic 0.100ns (63.895%) route 0.057ns (36.105%)) Logic Levels: 0 Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.506ns Source Clock Delay (SCD): 0.351ns Clock Pessimism Removal (CPR): 0.144ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.351 0.351 ngFEC/SFP_GEN[9].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X149Y304 FDCE r ngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_reg[7][25]/C ------------------------------------------------------------------- ------------------- SLICE_X149Y304 FDCE (Prop_fdce_C_Q) 0.100 0.451 r ngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_reg[7][25]/Q net (fo=2, routed) 0.057 0.508 ngFEC/SFP_GEN[9].ngCCM_gbt/L[25] SLICE_X148Y304 FDRE r ngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_o_reg[7][25]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.506 0.506 ngFEC/SFP_GEN[9].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X148Y304 FDRE r ngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_o_reg[7][25]/C clock pessimism -0.144 0.362 SLICE_X148Y304 FDRE (Hold_fdre_C_D) 0.032 0.394 ngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_o_reg[7][25] ------------------------------------------------------------------- required time -0.394 arrival time 0.508 ------------------------------------------------------------------- slack 0.114 Slack (MET) : 0.116ns (arrival time - required time) Source: ngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_reg[3][10]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_o_reg[3][10]/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_5 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_5 rise@0.000ns - rxWordclkl12_5 rise@0.000ns) Data Path Delay: 0.190ns (logic 0.100ns (52.615%) route 0.090ns (47.385%)) Logic Levels: 0 Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.542ns Source Clock Delay (SCD): 0.386ns Clock Pessimism Removal (CPR): 0.145ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.386 0.386 ngFEC/SFP_GEN[9].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X187Y302 FDCE r ngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_reg[3][10]/C ------------------------------------------------------------------- ------------------- SLICE_X187Y302 FDCE (Prop_fdce_C_Q) 0.100 0.486 r ngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_reg[3][10]/Q net (fo=2, routed) 0.090 0.576 ngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_reg[3]__0[10] SLICE_X186Y302 FDRE r ngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_o_reg[3][10]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.542 0.542 ngFEC/SFP_GEN[9].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X186Y302 FDRE r ngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_o_reg[3][10]/C clock pessimism -0.145 0.397 SLICE_X186Y302 FDRE (Hold_fdre_C_D) 0.063 0.460 ngFEC/SFP_GEN[9].ngCCM_gbt/ngCCM_status_counter_o_reg[3][10] ------------------------------------------------------------------- required time -0.460 arrival time 0.576 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.118ns (arrival time - required time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_5 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_5 rise@0.000ns - rxWordclkl12_5 rise@0.000ns) Data Path Delay: 0.216ns (logic 0.128ns (59.274%) route 0.088ns (40.726%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.508ns Source Clock Delay (SCD): 0.354ns Clock Pessimism Removal (CPR): 0.143ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.354 0.354 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X165Y304 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X165Y304 FDCE (Prop_fdce_C_Q) 0.100 0.454 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Q net (fo=2, routed) 0.088 0.542 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_33_in SLICE_X164Y304 LUT3 (Prop_lut3_I0_O) 0.028 0.570 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__3/O net (fo=1, routed) 0.000 0.570 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[17] SLICE_X164Y304 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.508 0.508 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X164Y304 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C clock pessimism -0.143 0.365 SLICE_X164Y304 FDRE (Hold_fdre_C_D) 0.087 0.452 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[17] ------------------------------------------------------------------- required time -0.452 arrival time 0.570 ------------------------------------------------------------------- slack 0.118 Slack (MET) : 0.122ns (arrival time - required time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_5 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_5 rise@0.000ns - rxWordclkl12_5 rise@0.000ns) Data Path Delay: 0.220ns (logic 0.128ns (58.166%) route 0.092ns (41.834%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.506ns Source Clock Delay (SCD): 0.352ns Clock Pessimism Removal (CPR): 0.143ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.352 0.352 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X165Y310 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X165Y310 FDCE (Prop_fdce_C_Q) 0.100 0.452 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/Q net (fo=2, routed) 0.092 0.544 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_29_in SLICE_X164Y310 LUT3 (Prop_lut3_I2_O) 0.028 0.572 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__3/O net (fo=1, routed) 0.000 0.572 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[13] SLICE_X164Y310 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.506 0.506 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X164Y310 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C clock pessimism -0.143 0.363 SLICE_X164Y310 FDRE (Hold_fdre_C_D) 0.087 0.450 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13] ------------------------------------------------------------------- required time -0.450 arrival time 0.572 ------------------------------------------------------------------- slack 0.122 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: rxWordclkl12_5 Waveform(ns): { 0.000 4.100 } Period(ns): 8.200 Sources: { ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/RXUSRCLK n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y24 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK Min Period n/a GTXE2_CHANNEL/RXUSRCLK2 n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y24 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X170Y303 ngFEC/clk_rate_gen[9].clkRate3/clktest_div8_reg/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X161Y300 ngFEC/SFP_GEN[9].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[64]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X161Y300 ngFEC/SFP_GEN[9].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[6]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X161Y300 ngFEC/SFP_GEN[9].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[72]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X160Y301 ngFEC/SFP_GEN[9].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[76]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X178Y308 ngFEC/gbtbank2_l12_117/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X178Y308 ngFEC/gbtbank2_l12_117/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X159Y305 ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Clock_20MHz_dl_reg[0]/C Low Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X158Y305 ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK Low Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X158Y305 ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK Low Pulse Width Slow FDRE/C n/a 0.400 4.100 3.700 SLICE_X170Y303 ngFEC/clk_rate_gen[9].clkRate3/clktest_div8_reg/C Low Pulse Width Slow FDRE/C n/a 0.400 4.100 3.700 SLICE_X159Y305 ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Clock_20MHz_dl_reg[0]/C Low Pulse Width Slow FDRE/C n/a 0.400 4.100 3.700 SLICE_X158Y305 ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Clock_20MHz_dl_reg[4]__0/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X166Y301 ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[25]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X166Y303 ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[29]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X170Y301 ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[2]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X166Y303 ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[30]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X166Y303 ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[31]/C High Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X158Y305 ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X158Y305 ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK High Pulse Width Fast FDCE/C n/a 0.350 4.100 3.750 SLICE_X181Y301 ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_s_reg/C High Pulse Width Fast FDCE/C n/a 0.350 4.100 3.750 SLICE_X181Y301 ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C High Pulse Width Fast FDCE/C n/a 0.350 4.100 3.750 SLICE_X180Y302 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[36]/C High Pulse Width Fast FDCE/C n/a 0.350 4.100 3.750 SLICE_X180Y302 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[37]/C High Pulse Width Fast FDCE/C n/a 0.350 4.100 3.750 SLICE_X180Y302 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[39]/C High Pulse Width Fast FDCE/C n/a 0.350 4.100 3.750 SLICE_X183Y301 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[117]/C High Pulse Width Fast FDCE/C n/a 0.350 4.100 3.750 SLICE_X183Y302 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[119]/C High Pulse Width Fast FDCE/C n/a 0.350 4.100 3.750 SLICE_X183Y302 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[21]/C --------------------------------------------------------------------------------------------------- From Clock: rxWordclkl12_6 To Clock: rxWordclkl12_6 Setup : 0 Failing Endpoints, Worst Slack 3.344ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.084ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.458ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.344ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[95]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_6 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_6 rise@8.200ns - rxWordclkl12_6 rise@0.000ns) Data Path Delay: 4.431ns (logic 1.198ns (27.034%) route 3.233ns (72.966%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.281ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.630ns = ( 8.830 - 8.200 ) Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.911 0.911 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDISPERR[1]) 1.009 1.920 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDISPERR[1] net (fo=8, routed) 2.179 4.100 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gt0_rxdata_out[19] SLICE_X148Y279 LUT5 (Prop_lut5_I3_O) 0.051 4.151 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[95]_i_3__4/O net (fo=6, routed) 0.669 4.820 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[95]_i_3__4_n_0 SLICE_X146Y280 LUT4 (Prop_lut4_I1_O) 0.138 4.958 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[95]_i_2__4/O net (fo=1, routed) 0.385 5.343 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[91] SLICE_X143Y281 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[95]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 8.200 8.200 r BUFHCE_X1Y60 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.630 8.830 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X143Y281 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[95]/C clock pessimism 0.000 8.830 clock uncertainty -0.035 8.795 SLICE_X143Y281 FDCE (Setup_fdce_C_D) -0.108 8.687 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[95] ------------------------------------------------------------------- required time 8.687 arrival time -5.343 ------------------------------------------------------------------- slack 3.344 Slack (MET) : 3.366ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[26]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_6 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_6 rise@8.200ns - rxWordclkl12_6 rise@0.000ns) Data Path Delay: 4.414ns (logic 1.099ns (24.895%) route 3.315ns (75.105%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.283ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.628ns = ( 8.828 - 8.200 ) Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.911 0.911 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXCHARISK[1]) 1.009 1.920 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXCHARISK[1] net (fo=8, routed) 2.462 4.383 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gt0_rxdata_out[18] SLICE_X143Y279 LUT5 (Prop_lut5_I0_O) 0.043 4.426 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[90]_i_2__4/O net (fo=6, routed) 0.535 4.961 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[90]_i_2__4_n_0 SLICE_X140Y281 LUT4 (Prop_lut4_I3_O) 0.047 5.008 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[26]_i_1__4/O net (fo=1, routed) 0.318 5.326 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[22] SLICE_X138Y280 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[26]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 8.200 8.200 r BUFHCE_X1Y60 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.628 8.828 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X138Y280 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[26]/C clock pessimism 0.000 8.828 clock uncertainty -0.035 8.793 SLICE_X138Y280 FDCE (Setup_fdce_C_D) -0.101 8.692 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[26] ------------------------------------------------------------------- required time 8.692 arrival time -5.326 ------------------------------------------------------------------- slack 3.366 Slack (MET) : 3.450ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[57]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_6 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_6 rise@8.200ns - rxWordclkl12_6 rise@0.000ns) Data Path Delay: 4.338ns (logic 1.208ns (27.849%) route 3.130ns (72.151%)) Logic Levels: 2 (LUT4=2) Clock Path Skew: -0.282ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.629ns = ( 8.829 - 8.200 ) Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.911 0.911 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[5]) 1.009 1.920 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[5] net (fo=6, routed) 2.107 4.028 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gt0_rxdata_out[5] SLICE_X141Y276 LUT4 (Prop_lut4_I0_O) 0.054 4.082 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[97]_i_3__4/O net (fo=6, routed) 0.648 4.730 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[97]_i_3__4_n_0 SLICE_X137Y279 LUT4 (Prop_lut4_I1_O) 0.145 4.875 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[57]_i_1__4/O net (fo=1, routed) 0.374 5.249 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[53] SLICE_X142Y279 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[57]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 8.200 8.200 r BUFHCE_X1Y60 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.629 8.829 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X142Y279 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[57]/C clock pessimism 0.000 8.829 clock uncertainty -0.035 8.794 SLICE_X142Y279 FDCE (Setup_fdce_C_D) -0.095 8.699 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[57] ------------------------------------------------------------------- required time 8.699 arrival time -5.249 ------------------------------------------------------------------- slack 3.450 Slack (MET) : 3.462ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[62]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_6 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_6 rise@8.200ns - rxWordclkl12_6 rise@0.000ns) Data Path Delay: 4.319ns (logic 1.211ns (28.040%) route 3.108ns (71.960%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.279ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.632ns = ( 8.832 - 8.200 ) Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.911 0.911 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXCHARISK[1]) 1.009 1.920 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXCHARISK[1] net (fo=8, routed) 2.144 4.064 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gt0_rxdata_out[18] SLICE_X149Y278 LUT5 (Prop_lut5_I3_O) 0.054 4.118 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[94]_i_2__4/O net (fo=6, routed) 0.541 4.659 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[94]_i_2__4_n_0 SLICE_X151Y280 LUT4 (Prop_lut4_I1_O) 0.148 4.807 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[62]_i_1__4/O net (fo=1, routed) 0.423 5.230 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[58] SLICE_X144Y280 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[62]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 8.200 8.200 r BUFHCE_X1Y60 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.632 8.832 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X144Y280 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[62]/C clock pessimism 0.000 8.832 clock uncertainty -0.035 8.797 SLICE_X144Y280 FDCE (Setup_fdce_C_D) -0.104 8.693 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[62] ------------------------------------------------------------------- required time 8.693 arrival time -5.230 ------------------------------------------------------------------- slack 3.462 Slack (MET) : 3.490ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[31]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_6 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_6 rise@8.200ns - rxWordclkl12_6 rise@0.000ns) Data Path Delay: 4.272ns (logic 1.206ns (28.232%) route 3.066ns (71.768%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.277ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.634ns = ( 8.834 - 8.200 ) Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.911 0.911 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDISPERR[1]) 1.009 1.920 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDISPERR[1] net (fo=8, routed) 2.179 4.100 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gt0_rxdata_out[19] SLICE_X148Y279 LUT5 (Prop_lut5_I3_O) 0.051 4.151 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[95]_i_3__4/O net (fo=6, routed) 0.485 4.636 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[95]_i_3__4_n_0 SLICE_X147Y279 LUT4 (Prop_lut4_I1_O) 0.146 4.782 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[31]_i_2__4/O net (fo=1, routed) 0.401 5.183 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[27] SLICE_X148Y278 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[31]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 8.200 8.200 r BUFHCE_X1Y60 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.634 8.834 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X148Y278 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[31]/C clock pessimism 0.000 8.834 clock uncertainty -0.035 8.799 SLICE_X148Y278 FDCE (Setup_fdce_C_D) -0.125 8.674 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[31] ------------------------------------------------------------------- required time 8.674 arrival time -5.183 ------------------------------------------------------------------- slack 3.490 Slack (MET) : 3.500ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[58]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_6 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_6 rise@8.200ns - rxWordclkl12_6 rise@0.000ns) Data Path Delay: 4.281ns (logic 1.099ns (25.669%) route 3.182ns (74.331%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.282ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.629ns = ( 8.829 - 8.200 ) Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.911 0.911 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXCHARISK[1]) 1.009 1.920 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXCHARISK[1] net (fo=8, routed) 2.462 4.383 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gt0_rxdata_out[18] SLICE_X143Y279 LUT5 (Prop_lut5_I0_O) 0.043 4.426 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[90]_i_2__4/O net (fo=6, routed) 0.531 4.956 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[90]_i_2__4_n_0 SLICE_X140Y279 LUT4 (Prop_lut4_I3_O) 0.047 5.003 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[58]_i_1__4/O net (fo=1, routed) 0.189 5.193 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[54] SLICE_X142Y279 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[58]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 8.200 8.200 r BUFHCE_X1Y60 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.629 8.829 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X142Y279 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[58]/C clock pessimism 0.000 8.829 clock uncertainty -0.035 8.794 SLICE_X142Y279 FDCE (Setup_fdce_C_D) -0.101 8.693 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[58] ------------------------------------------------------------------- required time 8.693 arrival time -5.193 ------------------------------------------------------------------- slack 3.500 Slack (MET) : 3.524ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[74]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_6 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_6 rise@8.200ns - rxWordclkl12_6 rise@0.000ns) Data Path Delay: 4.422ns (logic 1.200ns (27.137%) route 3.222ns (72.863%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.284ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.627ns = ( 8.827 - 8.200 ) Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.911 0.911 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXCHARISK[1]) 1.009 1.920 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXCHARISK[1] net (fo=8, routed) 2.462 4.383 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gt0_rxdata_out[18] SLICE_X143Y279 LUT4 (Prop_lut4_I1_O) 0.054 4.437 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[98]_i_2__4/O net (fo=5, routed) 0.760 5.197 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[98]_i_2__4_n_0 SLICE_X140Y278 LUT6 (Prop_lut6_I0_O) 0.137 5.334 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[74]_i_1__4/O net (fo=1, routed) 0.000 5.334 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[70] SLICE_X140Y278 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[74]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 8.200 8.200 r BUFHCE_X1Y60 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.627 8.827 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X140Y278 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[74]/C clock pessimism 0.000 8.827 clock uncertainty -0.035 8.792 SLICE_X140Y278 FDCE (Setup_fdce_C_D) 0.066 8.858 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[74] ------------------------------------------------------------------- required time 8.858 arrival time -5.334 ------------------------------------------------------------------- slack 3.524 Slack (MET) : 3.550ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[27]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_6 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_6 rise@8.200ns - rxWordclkl12_6 rise@0.000ns) Data Path Delay: 4.237ns (logic 1.106ns (26.103%) route 3.131ns (73.897%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.283ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.628ns = ( 8.828 - 8.200 ) Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.911 0.911 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDISPERR[1]) 1.009 1.920 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDISPERR[1] net (fo=8, routed) 2.157 4.077 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gt0_rxdata_out[19] SLICE_X142Y279 LUT5 (Prop_lut5_I0_O) 0.043 4.120 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[91]_i_3__4/O net (fo=6, routed) 0.677 4.798 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[91]_i_3__4_n_0 SLICE_X139Y281 LUT4 (Prop_lut4_I3_O) 0.054 4.852 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[27]_i_2__4/O net (fo=1, routed) 0.297 5.149 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[23] SLICE_X138Y280 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[27]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 8.200 8.200 r BUFHCE_X1Y60 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.628 8.828 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X138Y280 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[27]/C clock pessimism 0.000 8.828 clock uncertainty -0.035 8.793 SLICE_X138Y280 FDCE (Setup_fdce_C_D) -0.094 8.699 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[27] ------------------------------------------------------------------- required time 8.699 arrival time -5.149 ------------------------------------------------------------------- slack 3.550 Slack (MET) : 3.561ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[56]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_6 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_6 rise@8.200ns - rxWordclkl12_6 rise@0.000ns) Data Path Delay: 4.225ns (logic 1.103ns (26.108%) route 3.122ns (73.892%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.283ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.628ns = ( 8.828 - 8.200 ) Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.911 0.911 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[0]) 1.009 1.920 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[0] net (fo=13, routed) 2.274 4.195 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gt0_rxdata_out[0] SLICE_X141Y278 LUT5 (Prop_lut5_I4_O) 0.043 4.238 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[88]_i_2__4/O net (fo=6, routed) 0.657 4.895 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[88]_i_2__4_n_0 SLICE_X137Y281 LUT4 (Prop_lut4_I3_O) 0.051 4.946 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[56]_i_1__4/O net (fo=1, routed) 0.190 5.136 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[52] SLICE_X138Y281 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[56]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 8.200 8.200 r BUFHCE_X1Y60 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.628 8.828 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X138Y281 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[56]/C clock pessimism 0.000 8.828 clock uncertainty -0.035 8.793 SLICE_X138Y281 FDCE (Setup_fdce_C_D) -0.095 8.698 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[56] ------------------------------------------------------------------- required time 8.698 arrival time -5.136 ------------------------------------------------------------------- slack 3.561 Slack (MET) : 3.579ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[94]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_6 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_6 rise@8.200ns - rxWordclkl12_6 rise@0.000ns) Data Path Delay: 4.196ns (logic 1.209ns (28.812%) route 2.987ns (71.188%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.281ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.630ns = ( 8.830 - 8.200 ) Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.911 0.911 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXCHARISK[1]) 1.009 1.920 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXCHARISK[1] net (fo=8, routed) 2.144 4.064 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gt0_rxdata_out[18] SLICE_X149Y278 LUT5 (Prop_lut5_I3_O) 0.054 4.118 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[94]_i_2__4/O net (fo=6, routed) 0.546 4.664 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[94]_i_2__4_n_0 SLICE_X147Y281 LUT4 (Prop_lut4_I1_O) 0.146 4.810 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[94]_i_1__4/O net (fo=1, routed) 0.298 5.108 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[99]_1[90] SLICE_X143Y281 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[94]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 8.200 8.200 r BUFHCE_X1Y60 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.630 8.830 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X143Y281 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[94]/C clock pessimism 0.000 8.830 clock uncertainty -0.035 8.795 SLICE_X143Y281 FDCE (Setup_fdce_C_D) -0.108 8.687 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[94] ------------------------------------------------------------------- required time 8.687 arrival time -5.108 ------------------------------------------------------------------- slack 3.579 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.084ns (arrival time - required time) Source: ngFEC/SFP_GEN[10].rx_data_reg[10][27]/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[27]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_6 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_6 rise@0.000ns - rxWordclkl12_6 rise@0.000ns) Data Path Delay: 0.154ns (logic 0.100ns (65.134%) route 0.054ns (34.866%)) Logic Levels: 0 Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.487ns Source Clock Delay (SCD): 0.336ns Clock Pessimism Removal (CPR): 0.140ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.336 0.336 ngFEC/clktest12_in SLICE_X147Y275 FDRE r ngFEC/SFP_GEN[10].rx_data_reg[10][27]/C ------------------------------------------------------------------- ------------------- SLICE_X147Y275 FDRE (Prop_fdre_C_Q) 0.100 0.436 r ngFEC/SFP_GEN[10].rx_data_reg[10][27]/Q net (fo=1, routed) 0.054 0.490 ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[83]_0[19] SLICE_X146Y275 FDCE r ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[27]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.487 0.487 ngFEC/SFP_GEN[10].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X146Y275 FDCE r ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[27]/C clock pessimism -0.140 0.347 SLICE_X146Y275 FDCE (Hold_fdce_C_D) 0.059 0.406 ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[27] ------------------------------------------------------------------- required time -0.406 arrival time 0.490 ------------------------------------------------------------------- slack 0.084 Slack (MET) : 0.091ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_6 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_6 rise@0.000ns - rxWordclkl12_6 rise@0.000ns) Data Path Delay: 0.189ns (logic 0.128ns (67.678%) route 0.061ns (32.322%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.481ns Source Clock Delay (SCD): 0.329ns Clock Pessimism Removal (CPR): 0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.329 0.329 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X135Y273 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X135Y273 FDCE (Prop_fdce_C_Q) 0.100 0.429 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[10]/Q net (fo=2, routed) 0.061 0.490 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_19_in SLICE_X134Y273 LUT3 (Prop_lut3_I2_O) 0.028 0.518 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[8]_i_1__4/O net (fo=1, routed) 0.000 0.518 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[8] SLICE_X134Y273 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.481 0.481 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X134Y273 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[8]/C clock pessimism -0.141 0.340 SLICE_X134Y273 FDRE (Hold_fdre_C_D) 0.087 0.427 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[8] ------------------------------------------------------------------- required time -0.427 arrival time 0.518 ------------------------------------------------------------------- slack 0.091 Slack (MET) : 0.093ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_6 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_6 rise@0.000ns - rxWordclkl12_6 rise@0.000ns) Data Path Delay: 0.191ns (logic 0.128ns (66.995%) route 0.063ns (33.005%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.483ns Source Clock Delay (SCD): 0.332ns Clock Pessimism Removal (CPR): 0.140ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.332 0.332 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X137Y273 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X137Y273 FDCE (Prop_fdce_C_Q) 0.100 0.432 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[11]/Q net (fo=2, routed) 0.063 0.495 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_21_in SLICE_X136Y273 LUT3 (Prop_lut3_I2_O) 0.028 0.523 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[9]_i_1__4/O net (fo=1, routed) 0.000 0.523 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[9] SLICE_X136Y273 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.483 0.483 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X136Y273 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[9]/C clock pessimism -0.140 0.343 SLICE_X136Y273 FDRE (Hold_fdre_C_D) 0.087 0.430 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[9] ------------------------------------------------------------------- required time -0.430 arrival time 0.523 ------------------------------------------------------------------- slack 0.093 Slack (MET) : 0.094ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_6 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_6 rise@0.000ns - rxWordclkl12_6 rise@0.000ns) Data Path Delay: 0.192ns (logic 0.128ns (66.646%) route 0.064ns (33.354%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.482ns Source Clock Delay (SCD): 0.331ns Clock Pessimism Removal (CPR): 0.140ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.331 0.331 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X139Y274 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X139Y274 FDCE (Prop_fdce_C_Q) 0.100 0.431 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Q net (fo=2, routed) 0.064 0.495 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_35_in SLICE_X138Y274 LUT3 (Prop_lut3_I2_O) 0.028 0.523 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[16]_i_1__4/O net (fo=1, routed) 0.000 0.523 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[16] SLICE_X138Y274 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.482 0.482 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X138Y274 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16]/C clock pessimism -0.140 0.342 SLICE_X138Y274 FDRE (Hold_fdre_C_D) 0.087 0.429 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[16] ------------------------------------------------------------------- required time -0.429 arrival time 0.523 ------------------------------------------------------------------- slack 0.094 Slack (MET) : 0.104ns (arrival time - required time) Source: ngFEC/SFP_GEN[10].rx_data_reg[10][46]/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[46]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_6 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_6 rise@0.000ns - rxWordclkl12_6 rise@0.000ns) Data Path Delay: 0.211ns (logic 0.130ns (61.749%) route 0.081ns (38.251%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.486ns Source Clock Delay (SCD): 0.334ns Clock Pessimism Removal (CPR): 0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.334 0.334 ngFEC/clktest12_in SLICE_X139Y271 FDRE r ngFEC/SFP_GEN[10].rx_data_reg[10][46]/C ------------------------------------------------------------------- ------------------- SLICE_X139Y271 FDRE (Prop_fdre_C_Q) 0.100 0.434 r ngFEC/SFP_GEN[10].rx_data_reg[10][46]/Q net (fo=1, routed) 0.081 0.515 ngFEC/gbtbank3_l12_116/SFP_GEN[10].rx_data_reg[10][30] SLICE_X138Y271 LUT3 (Prop_lut3_I2_O) 0.030 0.545 r ngFEC/gbtbank3_l12_116/RX_Word_rx40[46]_i_1/O net (fo=1, routed) 0.000 0.545 ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[83]_0[31] SLICE_X138Y271 FDCE r ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[46]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.486 0.486 ngFEC/SFP_GEN[10].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X138Y271 FDCE r ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[46]/C clock pessimism -0.141 0.345 SLICE_X138Y271 FDCE (Hold_fdce_C_D) 0.096 0.441 ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[46] ------------------------------------------------------------------- required time -0.441 arrival time 0.545 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_6 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_6 rise@0.000ns - rxWordclkl12_6 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.533ns Source Clock Delay (SCD): 0.379ns Clock Pessimism Removal (CPR): 0.154ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.379 0.379 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in SLICE_X185Y267 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X185Y267 FDRE (Prop_fdre_C_Q) 0.100 0.479 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q net (fo=1, routed) 0.055 0.534 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync1 SLICE_X185Y267 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.533 0.533 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in SLICE_X185Y267 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C clock pessimism -0.154 0.379 SLICE_X185Y267 FDRE (Hold_fdre_C_D) 0.047 0.426 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.426 arrival time 0.534 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_6 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_6 rise@0.000ns - rxWordclkl12_6 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.533ns Source Clock Delay (SCD): 0.379ns Clock Pessimism Removal (CPR): 0.154ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.379 0.379 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/gt0_rxusrclk_in SLICE_X183Y267 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X183Y267 FDRE (Prop_fdre_C_Q) 0.100 0.479 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/Q net (fo=1, routed) 0.055 0.534 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync1 SLICE_X183Y267 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.533 0.533 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/gt0_rxusrclk_in SLICE_X183Y267 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/C clock pessimism -0.154 0.379 SLICE_X183Y267 FDRE (Hold_fdre_C_D) 0.047 0.426 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.426 arrival time 0.534 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.111ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[32]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[32]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_6 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_6 rise@0.000ns - rxWordclkl12_6 rise@0.000ns) Data Path Delay: 0.209ns (logic 0.128ns (61.382%) route 0.081ns (38.618%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.486ns Source Clock Delay (SCD): 0.334ns Clock Pessimism Removal (CPR): 0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.334 0.334 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X137Y278 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[32]/C ------------------------------------------------------------------- ------------------- SLICE_X137Y278 FDCE (Prop_fdce_C_Q) 0.100 0.434 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[32]/Q net (fo=1, routed) 0.081 0.515 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[32] SLICE_X136Y278 LUT6 (Prop_lut6_I5_O) 0.028 0.543 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1[32]_i_1__4/O net (fo=1, routed) 0.000 0.543 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/p_0_out[32] SLICE_X136Y278 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[32]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.486 0.486 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X136Y278 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[32]/C clock pessimism -0.141 0.345 SLICE_X136Y278 FDCE (Hold_fdce_C_D) 0.087 0.432 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[32] ------------------------------------------------------------------- required time -0.432 arrival time 0.543 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.111ns (arrival time - required time) Source: ngFEC/SFP_GEN[10].rx_data_reg[10][0]/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[0]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_6 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_6 rise@0.000ns - rxWordclkl12_6 rise@0.000ns) Data Path Delay: 0.209ns (logic 0.128ns (61.382%) route 0.081ns (38.618%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.495ns Source Clock Delay (SCD): 0.343ns Clock Pessimism Removal (CPR): 0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.343 0.343 ngFEC/clktest12_in SLICE_X147Y282 FDRE r ngFEC/SFP_GEN[10].rx_data_reg[10][0]/C ------------------------------------------------------------------- ------------------- SLICE_X147Y282 FDRE (Prop_fdre_C_Q) 0.100 0.443 r ngFEC/SFP_GEN[10].rx_data_reg[10][0]/Q net (fo=1, routed) 0.081 0.524 ngFEC/gbtbank3_l12_116/SFP_GEN[10].rx_data_reg[10][0] SLICE_X146Y282 LUT3 (Prop_lut3_I2_O) 0.028 0.552 r ngFEC/gbtbank3_l12_116/RX_Word_rx40[0]_i_1/O net (fo=1, routed) 0.000 0.552 ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[83]_0[0] SLICE_X146Y282 FDCE r ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[0]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.495 0.495 ngFEC/SFP_GEN[10].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X146Y282 FDCE r ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[0]/C clock pessimism -0.141 0.354 SLICE_X146Y282 FDCE (Hold_fdce_C_D) 0.087 0.441 ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[0] ------------------------------------------------------------------- required time -0.441 arrival time 0.552 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.111ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[64]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[64]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_6 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_6 rise@0.000ns - rxWordclkl12_6 rise@0.000ns) Data Path Delay: 0.209ns (logic 0.128ns (61.382%) route 0.081ns (38.618%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.485ns Source Clock Delay (SCD): 0.333ns Clock Pessimism Removal (CPR): 0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.333 0.333 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X137Y277 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[64]/C ------------------------------------------------------------------- ------------------- SLICE_X137Y277 FDCE (Prop_fdce_C_Q) 0.100 0.433 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[64]/Q net (fo=1, routed) 0.081 0.514 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[64] SLICE_X136Y277 LUT2 (Prop_lut2_I1_O) 0.028 0.542 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1[64]_i_1__4/O net (fo=1, routed) 0.000 0.542 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/p_0_out[64] SLICE_X136Y277 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[64]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.485 0.485 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X136Y277 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[64]/C clock pessimism -0.141 0.344 SLICE_X136Y277 FDCE (Hold_fdce_C_D) 0.087 0.431 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[64] ------------------------------------------------------------------- required time -0.431 arrival time 0.542 ------------------------------------------------------------------- slack 0.111 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: rxWordclkl12_6 Waveform(ns): { 0.000 4.100 } Period(ns): 8.200 Sources: { ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/RXUSRCLK n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y21 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK Min Period n/a GTXE2_CHANNEL/RXUSRCLK2 n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y21 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X102Y250 ngFEC/SFP_GEN[10].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[62]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X102Y250 ngFEC/SFP_GEN[10].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[64]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X133Y250 ngFEC/SFP_GEN[10].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[76]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X145Y272 ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Clock_20MHz_dl_reg[0]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X146Y272 ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Clock_20MHz_dl_reg[4]__0/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X146Y282 ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[2]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X146Y275 ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[30]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X146Y275 ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[31]/C Low Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X146Y272 ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK Low Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X146Y272 ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK Low Pulse Width Slow FDRE/C n/a 0.400 4.100 3.700 SLICE_X102Y250 ngFEC/SFP_GEN[10].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[62]/C Low Pulse Width Slow FDRE/C n/a 0.400 4.100 3.700 SLICE_X102Y250 ngFEC/SFP_GEN[10].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[64]/C Low Pulse Width Slow FDRE/C n/a 0.400 4.100 3.700 SLICE_X145Y272 ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Clock_20MHz_dl_reg[0]/C Low Pulse Width Slow FDRE/C n/a 0.400 4.100 3.700 SLICE_X146Y272 ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Clock_20MHz_dl_reg[4]__0/C Low Pulse Width Fast FDRE/C n/a 0.400 4.100 3.700 SLICE_X146Y272 ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Clock_20MHz_dl_reg[4]__0/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X146Y275 ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[30]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X146Y275 ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[31]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X146Y275 ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[34]/C High Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X146Y272 ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X146Y272 ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X133Y250 ngFEC/SFP_GEN[10].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[0]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X133Y250 ngFEC/SFP_GEN[10].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[48]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X133Y250 ngFEC/SFP_GEN[10].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[72]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X133Y250 ngFEC/SFP_GEN[10].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[74]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X133Y250 ngFEC/SFP_GEN[10].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[76]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X138Y271 ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[44]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X138Y271 ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[46]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X136Y271 ngFEC/SFP_GEN[10].ngCCM_gbt/RX_Word_rx40_reg[60]/C --------------------------------------------------------------------------------------------------- From Clock: rxWordclkl12_7 To Clock: rxWordclkl12_7 Setup : 0 Failing Endpoints, Worst Slack 3.220ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.084ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.458ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.220ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[28]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_7 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_7 rise@8.200ns - rxWordclkl12_7 rise@0.000ns) Data Path Delay: 4.542ns (logic 1.200ns (26.420%) route 3.342ns (73.580%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.289ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.632ns = ( 8.832 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.921 0.921 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[0]) 1.009 1.930 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[0] net (fo=13, routed) 2.284 4.215 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19][0] SLICE_X151Y270 LUT5 (Prop_lut5_I0_O) 0.051 4.266 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[92]_i_2__5/O net (fo=6, routed) 0.688 4.953 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[92]_i_2__5_n_0 SLICE_X146Y268 LUT4 (Prop_lut4_I1_O) 0.140 5.093 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[28]_i_1__5/O net (fo=1, routed) 0.370 5.464 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[99]_1[24] SLICE_X145Y268 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[28]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 8.200 8.200 r BUFHCE_X1Y61 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.632 8.832 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X145Y268 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[28]/C clock pessimism 0.000 8.832 clock uncertainty -0.035 8.797 SLICE_X145Y268 FDCE (Setup_fdce_C_D) -0.113 8.684 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[28] ------------------------------------------------------------------- required time 8.684 arrival time -5.464 ------------------------------------------------------------------- slack 3.220 Slack (MET) : 3.395ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[62]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_7 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_7 rise@8.200ns - rxWordclkl12_7 rise@0.000ns) Data Path Delay: 4.372ns (logic 1.207ns (27.610%) route 3.165ns (72.390%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.287ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.634ns = ( 8.834 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.921 0.921 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXCHARISK[1]) 1.009 1.930 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXCHARISK[1] net (fo=8, routed) 2.002 3.932 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19][18] SLICE_X151Y269 LUT5 (Prop_lut5_I3_O) 0.054 3.986 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[94]_i_2__5/O net (fo=6, routed) 0.660 4.646 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[94]_i_2__5_n_0 SLICE_X147Y270 LUT4 (Prop_lut4_I1_O) 0.144 4.790 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[62]_i_1__5/O net (fo=1, routed) 0.503 5.293 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[99]_1[58] SLICE_X147Y268 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[62]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 8.200 8.200 r BUFHCE_X1Y61 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.634 8.834 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X147Y268 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[62]/C clock pessimism 0.000 8.834 clock uncertainty -0.035 8.799 SLICE_X147Y268 FDCE (Setup_fdce_C_D) -0.111 8.688 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[62] ------------------------------------------------------------------- required time 8.688 arrival time -5.293 ------------------------------------------------------------------- slack 3.395 Slack (MET) : 3.411ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[60]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_7 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_7 rise@8.200ns - rxWordclkl12_7 rise@0.000ns) Data Path Delay: 4.348ns (logic 1.204ns (27.688%) route 3.144ns (72.312%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.290ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.631ns = ( 8.831 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.921 0.921 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[0]) 1.009 1.930 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[0] net (fo=13, routed) 2.284 4.215 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19][0] SLICE_X151Y270 LUT5 (Prop_lut5_I0_O) 0.051 4.266 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[92]_i_2__5/O net (fo=6, routed) 0.575 4.841 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[92]_i_2__5_n_0 SLICE_X147Y270 LUT4 (Prop_lut4_I1_O) 0.144 4.985 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[60]_i_1__5/O net (fo=1, routed) 0.285 5.270 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[99]_1[56] SLICE_X145Y270 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[60]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 8.200 8.200 r BUFHCE_X1Y61 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.631 8.831 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X145Y270 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[60]/C clock pessimism 0.000 8.831 clock uncertainty -0.035 8.796 SLICE_X145Y270 FDCE (Setup_fdce_C_D) -0.115 8.681 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[60] ------------------------------------------------------------------- required time 8.681 arrival time -5.270 ------------------------------------------------------------------- slack 3.411 Slack (MET) : 3.524ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[29]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_7 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_7 rise@8.200ns - rxWordclkl12_7 rise@0.000ns) Data Path Delay: 4.227ns (logic 1.202ns (28.437%) route 3.025ns (71.563%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.289ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.632ns = ( 8.832 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.921 0.921 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[15]) 1.009 1.930 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[15] net (fo=8, routed) 2.027 3.957 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19][17] SLICE_X153Y270 LUT5 (Prop_lut5_I3_O) 0.051 4.008 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[93]_i_2__5/O net (fo=6, routed) 0.698 4.706 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[93]_i_2__5_n_0 SLICE_X145Y269 LUT4 (Prop_lut4_I1_O) 0.142 4.848 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[29]_i_1__5/O net (fo=1, routed) 0.301 5.148 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[99]_1[25] SLICE_X145Y268 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[29]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 8.200 8.200 r BUFHCE_X1Y61 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.632 8.832 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X145Y268 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[29]/C clock pessimism 0.000 8.832 clock uncertainty -0.035 8.797 SLICE_X145Y268 FDCE (Setup_fdce_C_D) -0.124 8.673 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[29] ------------------------------------------------------------------- required time 8.673 arrival time -5.148 ------------------------------------------------------------------- slack 3.524 Slack (MET) : 3.547ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[61]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_7 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_7 rise@8.200ns - rxWordclkl12_7 rise@0.000ns) Data Path Delay: 4.202ns (logic 1.207ns (28.726%) route 2.995ns (71.274%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.290ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.631ns = ( 8.831 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.921 0.921 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[15]) 1.009 1.930 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[15] net (fo=8, routed) 2.027 3.957 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19][17] SLICE_X153Y270 LUT5 (Prop_lut5_I3_O) 0.051 4.008 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[93]_i_2__5/O net (fo=6, routed) 0.597 4.605 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[93]_i_2__5_n_0 SLICE_X147Y270 LUT4 (Prop_lut4_I1_O) 0.147 4.752 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[61]_i_1__5/O net (fo=1, routed) 0.371 5.123 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[99]_1[57] SLICE_X145Y270 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[61]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 8.200 8.200 r BUFHCE_X1Y61 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.631 8.831 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X145Y270 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[61]/C clock pessimism 0.000 8.831 clock uncertainty -0.035 8.796 SLICE_X145Y270 FDCE (Setup_fdce_C_D) -0.125 8.671 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[61] ------------------------------------------------------------------- required time 8.671 arrival time -5.123 ------------------------------------------------------------------- slack 3.547 Slack (MET) : 3.606ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[30]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_7 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_7 rise@8.200ns - rxWordclkl12_7 rise@0.000ns) Data Path Delay: 4.157ns (logic 1.211ns (29.135%) route 2.946ns (70.865%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.289ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.632ns = ( 8.832 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.921 0.921 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXCHARISK[1]) 1.009 1.930 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXCHARISK[1] net (fo=8, routed) 2.002 3.932 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19][18] SLICE_X151Y269 LUT5 (Prop_lut5_I3_O) 0.054 3.986 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[94]_i_2__5/O net (fo=6, routed) 0.666 4.653 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[94]_i_2__5_n_0 SLICE_X145Y269 LUT4 (Prop_lut4_I1_O) 0.148 4.801 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[30]_i_1__5/O net (fo=1, routed) 0.277 5.078 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[99]_1[26] SLICE_X145Y268 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[30]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 8.200 8.200 r BUFHCE_X1Y61 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.632 8.832 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X145Y268 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[30]/C clock pessimism 0.000 8.832 clock uncertainty -0.035 8.797 SLICE_X145Y268 FDCE (Setup_fdce_C_D) -0.113 8.684 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[30] ------------------------------------------------------------------- required time 8.684 arrival time -5.078 ------------------------------------------------------------------- slack 3.606 Slack (MET) : 3.634ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[92]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_7 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_7 rise@8.200ns - rxWordclkl12_7 rise@0.000ns) Data Path Delay: 4.133ns (logic 1.200ns (29.031%) route 2.933ns (70.969%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.284ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.637ns = ( 8.837 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.921 0.921 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[0]) 1.009 1.930 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[0] net (fo=13, routed) 2.284 4.215 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19][0] SLICE_X151Y270 LUT5 (Prop_lut5_I0_O) 0.051 4.266 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[92]_i_2__5/O net (fo=6, routed) 0.457 4.722 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[92]_i_2__5_n_0 SLICE_X150Y269 LUT4 (Prop_lut4_I1_O) 0.140 4.862 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[92]_i_1__5/O net (fo=1, routed) 0.192 5.055 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[99]_1[88] SLICE_X151Y269 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[92]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 8.200 8.200 r BUFHCE_X1Y61 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.637 8.837 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X151Y269 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[92]/C clock pessimism 0.000 8.837 clock uncertainty -0.035 8.802 SLICE_X151Y269 FDCE (Setup_fdce_C_D) -0.113 8.689 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[92] ------------------------------------------------------------------- required time 8.689 arrival time -5.055 ------------------------------------------------------------------- slack 3.634 Slack (MET) : 3.725ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[93]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_7 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_7 rise@8.200ns - rxWordclkl12_7 rise@0.000ns) Data Path Delay: 4.029ns (logic 1.204ns (29.882%) route 2.825ns (70.118%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.284ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.637ns = ( 8.837 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.921 0.921 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[15]) 1.009 1.930 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[15] net (fo=8, routed) 2.027 3.957 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19][17] SLICE_X153Y270 LUT5 (Prop_lut5_I3_O) 0.051 4.008 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[93]_i_2__5/O net (fo=6, routed) 0.578 4.586 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[93]_i_2__5_n_0 SLICE_X150Y269 LUT4 (Prop_lut4_I1_O) 0.144 4.730 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[93]_i_1__5/O net (fo=1, routed) 0.221 4.951 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[99]_1[89] SLICE_X151Y269 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[93]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 8.200 8.200 r BUFHCE_X1Y61 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.637 8.837 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X151Y269 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[93]/C clock pessimism 0.000 8.837 clock uncertainty -0.035 8.802 SLICE_X151Y269 FDCE (Setup_fdce_C_D) -0.126 8.676 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[93] ------------------------------------------------------------------- required time 8.676 arrival time -4.951 ------------------------------------------------------------------- slack 3.725 Slack (MET) : 3.773ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[20]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_7 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_7 rise@8.200ns - rxWordclkl12_7 rise@0.000ns) Data Path Delay: 4.168ns (logic 1.196ns (28.696%) route 2.972ns (71.304%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.287ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.634ns = ( 8.834 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.921 0.921 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[0]) 1.009 1.930 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[0] net (fo=13, routed) 2.284 4.215 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19][0] SLICE_X151Y270 LUT5 (Prop_lut5_I0_O) 0.051 4.266 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[92]_i_2__5/O net (fo=6, routed) 0.688 4.953 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[92]_i_2__5_n_0 SLICE_X146Y268 LUT4 (Prop_lut4_I1_O) 0.136 5.089 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[20]_i_1__5/O net (fo=1, routed) 0.000 5.089 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[99]_1[16] SLICE_X146Y268 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[20]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 8.200 8.200 r BUFHCE_X1Y61 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.634 8.834 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X146Y268 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[20]/C clock pessimism 0.000 8.834 clock uncertainty -0.035 8.799 SLICE_X146Y268 FDCE (Setup_fdce_C_D) 0.064 8.863 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[20] ------------------------------------------------------------------- required time 8.863 arrival time -5.089 ------------------------------------------------------------------- slack 3.773 Slack (MET) : 3.791ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[31]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_7 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_7 rise@8.200ns - rxWordclkl12_7 rise@0.000ns) Data Path Delay: 3.976ns (logic 1.210ns (30.431%) route 2.766ns (69.569%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.289ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.632ns = ( 8.832 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.921 0.921 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[3]) 1.009 1.930 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[3] net (fo=13, routed) 1.863 3.793 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19][3] SLICE_X155Y269 LUT5 (Prop_lut5_I0_O) 0.055 3.848 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[95]_i_3__5/O net (fo=6, routed) 0.683 4.532 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[95]_i_3__5_n_0 SLICE_X145Y269 LUT4 (Prop_lut4_I1_O) 0.146 4.678 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[31]_i_2__5/O net (fo=1, routed) 0.220 4.898 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[99]_1[27] SLICE_X145Y268 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[31]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 8.200 8.200 r BUFHCE_X1Y61 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.632 8.832 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X145Y268 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[31]/C clock pessimism 0.000 8.832 clock uncertainty -0.035 8.797 SLICE_X145Y268 FDCE (Setup_fdce_C_D) -0.108 8.689 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[31] ------------------------------------------------------------------- required time 8.689 arrival time -4.898 ------------------------------------------------------------------- slack 3.791 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.084ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[53]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[53]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_7 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_7 rise@0.000ns - rxWordclkl12_7 rise@0.000ns) Data Path Delay: 0.182ns (logic 0.128ns (70.512%) route 0.054ns (29.488%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.492ns Source Clock Delay (SCD): 0.340ns Clock Pessimism Removal (CPR): 0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.340 0.340 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X147Y270 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[53]/C ------------------------------------------------------------------- ------------------- SLICE_X147Y270 FDCE (Prop_fdce_C_Q) 0.100 0.440 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[53]/Q net (fo=1, routed) 0.054 0.494 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[53] SLICE_X146Y270 LUT6 (Prop_lut6_I5_O) 0.028 0.522 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1[53]_i_1__5/O net (fo=1, routed) 0.000 0.522 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/p_0_out[53] SLICE_X146Y270 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[53]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.492 0.492 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X146Y270 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[53]/C clock pessimism -0.141 0.351 SLICE_X146Y270 FDCE (Hold_fdce_C_D) 0.087 0.438 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[53] ------------------------------------------------------------------- required time -0.438 arrival time 0.522 ------------------------------------------------------------------- slack 0.084 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_7 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_7 rise@0.000ns - rxWordclkl12_7 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.542ns Source Clock Delay (SCD): 0.386ns Clock Pessimism Removal (CPR): 0.156ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.386 0.386 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in SLICE_X187Y250 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X187Y250 FDRE (Prop_fdre_C_Q) 0.100 0.486 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q net (fo=1, routed) 0.055 0.541 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync1 SLICE_X187Y250 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.542 0.542 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in SLICE_X187Y250 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C clock pessimism -0.156 0.386 SLICE_X187Y250 FDRE (Hold_fdre_C_D) 0.047 0.433 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.433 arrival time 0.541 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.111ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[76]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[76]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_7 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_7 rise@0.000ns - rxWordclkl12_7 rise@0.000ns) Data Path Delay: 0.209ns (logic 0.128ns (61.382%) route 0.081ns (38.618%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.497ns Source Clock Delay (SCD): 0.344ns Clock Pessimism Removal (CPR): 0.142ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.344 0.344 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X151Y268 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[76]/C ------------------------------------------------------------------- ------------------- SLICE_X151Y268 FDCE (Prop_fdce_C_Q) 0.100 0.444 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[76]/Q net (fo=1, routed) 0.081 0.525 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[76] SLICE_X150Y268 LUT2 (Prop_lut2_I1_O) 0.028 0.553 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1[76]_i_1__5/O net (fo=1, routed) 0.000 0.553 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/p_0_out[76] SLICE_X150Y268 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[76]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.497 0.497 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X150Y268 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[76]/C clock pessimism -0.142 0.355 SLICE_X150Y268 FDCE (Hold_fdce_C_D) 0.087 0.442 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[76] ------------------------------------------------------------------- required time -0.442 arrival time 0.553 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.111ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[49]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[49]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_7 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_7 rise@0.000ns - rxWordclkl12_7 rise@0.000ns) Data Path Delay: 0.209ns (logic 0.128ns (61.382%) route 0.081ns (38.618%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.493ns Source Clock Delay (SCD): 0.340ns Clock Pessimism Removal (CPR): 0.142ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.340 0.340 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X151Y272 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[49]/C ------------------------------------------------------------------- ------------------- SLICE_X151Y272 FDCE (Prop_fdce_C_Q) 0.100 0.440 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[49]/Q net (fo=1, routed) 0.081 0.521 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[49] SLICE_X150Y272 LUT6 (Prop_lut6_I5_O) 0.028 0.549 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1[49]_i_1__5/O net (fo=1, routed) 0.000 0.549 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/p_0_out[49] SLICE_X150Y272 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[49]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.493 0.493 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X150Y272 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[49]/C clock pessimism -0.142 0.351 SLICE_X150Y272 FDCE (Hold_fdce_C_D) 0.087 0.438 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[49] ------------------------------------------------------------------- required time -0.438 arrival time 0.549 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.113ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_7 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_7 rise@0.000ns - rxWordclkl12_7 rise@0.000ns) Data Path Delay: 0.211ns (logic 0.128ns (60.799%) route 0.083ns (39.201%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.496ns Source Clock Delay (SCD): 0.344ns Clock Pessimism Removal (CPR): 0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.344 0.344 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X145Y265 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X145Y265 FDCE (Prop_fdce_C_Q) 0.100 0.444 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[8]/Q net (fo=1, routed) 0.083 0.527 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_15_in SLICE_X144Y265 LUT3 (Prop_lut3_I2_O) 0.028 0.555 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[6]_i_1__5/O net (fo=1, routed) 0.000 0.555 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out[6] SLICE_X144Y265 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.496 0.496 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X144Y265 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C clock pessimism -0.141 0.355 SLICE_X144Y265 FDRE (Hold_fdre_C_D) 0.087 0.442 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6] ------------------------------------------------------------------- required time -0.442 arrival time 0.555 ------------------------------------------------------------------- slack 0.113 Slack (MET) : 0.113ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_7 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_7 rise@0.000ns - rxWordclkl12_7 rise@0.000ns) Data Path Delay: 0.211ns (logic 0.128ns (60.799%) route 0.083ns (39.201%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.501ns Source Clock Delay (SCD): 0.349ns Clock Pessimism Removal (CPR): 0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.349 0.349 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X159Y265 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X159Y265 FDCE (Prop_fdce_C_Q) 0.100 0.449 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[1]/Q net (fo=1, routed) 0.083 0.532 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[1] SLICE_X158Y265 LUT3 (Prop_lut3_I0_O) 0.028 0.560 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[1]_i_1__5/O net (fo=1, routed) 0.000 0.560 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[1] SLICE_X158Y265 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.501 0.501 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X158Y265 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1]/C clock pessimism -0.141 0.360 SLICE_X158Y265 FDRE (Hold_fdre_C_D) 0.087 0.447 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[1] ------------------------------------------------------------------- required time -0.447 arrival time 0.560 ------------------------------------------------------------------- slack 0.113 Slack (MET) : 0.117ns (arrival time - required time) Source: ngFEC/SFP_GEN[11].ngCCM_gbt/test_comm_cnt_reg[7]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[11].ngCCM_gbt/ngCCM_status_counter_reg[5][7]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_7 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_7 rise@0.000ns - rxWordclkl12_7 rise@0.000ns) Data Path Delay: 0.191ns (logic 0.100ns (52.340%) route 0.091ns (47.660%)) Logic Levels: 0 Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.506ns Source Clock Delay (SCD): 0.351ns Clock Pessimism Removal (CPR): 0.144ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.351 0.351 ngFEC/SFP_GEN[11].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X151Y255 FDCE r ngFEC/SFP_GEN[11].ngCCM_gbt/test_comm_cnt_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X151Y255 FDCE (Prop_fdce_C_Q) 0.100 0.451 r ngFEC/SFP_GEN[11].ngCCM_gbt/test_comm_cnt_reg[7]/Q net (fo=2, routed) 0.091 0.542 ngFEC/SFP_GEN[11].ngCCM_gbt/test_comm_cnt_reg[7] SLICE_X150Y255 FDCE r ngFEC/SFP_GEN[11].ngCCM_gbt/ngCCM_status_counter_reg[5][7]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.506 0.506 ngFEC/SFP_GEN[11].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X150Y255 FDCE r ngFEC/SFP_GEN[11].ngCCM_gbt/ngCCM_status_counter_reg[5][7]/C clock pessimism -0.144 0.362 SLICE_X150Y255 FDCE (Hold_fdce_C_D) 0.063 0.425 ngFEC/SFP_GEN[11].ngCCM_gbt/ngCCM_status_counter_reg[5][7] ------------------------------------------------------------------- required time -0.425 arrival time 0.542 ------------------------------------------------------------------- slack 0.117 Slack (MET) : 0.118ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_7 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_7 rise@0.000ns - rxWordclkl12_7 rise@0.000ns) Data Path Delay: 0.216ns (logic 0.128ns (59.274%) route 0.088ns (40.726%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.499ns Source Clock Delay (SCD): 0.347ns Clock Pessimism Removal (CPR): 0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.347 0.347 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X155Y266 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X155Y266 FDCE (Prop_fdce_C_Q) 0.100 0.447 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[15]/Q net (fo=2, routed) 0.088 0.535 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_29_in SLICE_X154Y266 LUT3 (Prop_lut3_I2_O) 0.028 0.563 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[13]_i_1__5/O net (fo=1, routed) 0.000 0.563 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[13] SLICE_X154Y266 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.499 0.499 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X154Y266 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C clock pessimism -0.141 0.358 SLICE_X154Y266 FDRE (Hold_fdre_C_D) 0.087 0.445 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[13] ------------------------------------------------------------------- required time -0.445 arrival time 0.563 ------------------------------------------------------------------- slack 0.118 Slack (MET) : 0.122ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_7 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_7 rise@0.000ns - rxWordclkl12_7 rise@0.000ns) Data Path Delay: 0.241ns (logic 0.128ns (53.052%) route 0.113ns (46.948%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.032ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.501ns Source Clock Delay (SCD): 0.349ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.349 0.349 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X159Y265 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X159Y265 FDCE (Prop_fdce_C_Q) 0.100 0.449 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[12]/Q net (fo=2, routed) 0.113 0.562 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_23_in SLICE_X160Y266 LUT3 (Prop_lut3_I0_O) 0.028 0.590 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__5/O net (fo=1, routed) 0.000 0.590 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[12] SLICE_X160Y266 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.501 0.501 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X160Y266 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C clock pessimism -0.120 0.381 SLICE_X160Y266 FDRE (Hold_fdre_C_D) 0.087 0.468 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[12] ------------------------------------------------------------------- required time -0.468 arrival time 0.590 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.131ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_7 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_7 rise@0.000ns - rxWordclkl12_7 rise@0.000ns) Data Path Delay: 0.173ns (logic 0.118ns (68.255%) route 0.055ns (31.745%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.542ns Source Clock Delay (SCD): 0.386ns Clock Pessimism Removal (CPR): 0.156ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.386 0.386 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/gt0_rxusrclk_in SLICE_X186Y250 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X186Y250 FDRE (Prop_fdre_C_Q) 0.118 0.504 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/Q net (fo=1, routed) 0.055 0.559 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync1 SLICE_X186Y250 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.542 0.542 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/gt0_rxusrclk_in SLICE_X186Y250 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/C clock pessimism -0.156 0.386 SLICE_X186Y250 FDRE (Hold_fdre_C_D) 0.042 0.428 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.428 arrival time 0.559 ------------------------------------------------------------------- slack 0.131 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: rxWordclkl12_7 Waveform(ns): { 0.000 4.100 } Period(ns): 8.200 Sources: { ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/RXUSRCLK n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y20 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK Min Period n/a GTXE2_CHANNEL/RXUSRCLK2 n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y20 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X147Y250 ngFEC/SFP_GEN[11].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[52]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X146Y250 ngFEC/SFP_GEN[11].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[76]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X158Y259 ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Clock_20MHz_dl_reg[4]__0/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X141Y265 ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[34]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X140Y263 ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[38]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X151Y261 ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[42]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X145Y262 ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[44]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X147Y264 ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[46]/C Low Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X158Y259 ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK Low Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X158Y259 ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK Low Pulse Width Slow FDRE/C n/a 0.400 4.100 3.700 SLICE_X158Y259 ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Clock_20MHz_dl_reg[4]__0/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X140Y263 ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[38]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X145Y262 ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[44]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X145Y262 ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[44]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X147Y264 ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[46]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X147Y264 ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[46]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X153Y264 ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[58]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X153Y264 ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[66]/C High Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X158Y259 ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X158Y259 ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X151Y261 ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[0]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X150Y261 ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[25]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X150Y261 ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[27]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X151Y261 ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[42]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X158Y263 ngFEC/SFP_GEN[11].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[0]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X150Y262 ngFEC/SFP_GEN[11].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[11]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X158Y263 ngFEC/SFP_GEN[11].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[14]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X158Y263 ngFEC/SFP_GEN[11].ngCCM_gbt/gbt_rx_checker/PRBS_pattern_previous_reg[16]/C --------------------------------------------------------------------------------------------------- From Clock: rxWordclkl12_8 To Clock: rxWordclkl12_8 Setup : 0 Failing Endpoints, Worst Slack 3.878ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.085ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.458ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.878ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[1]/CE (rising edge-triggered cell FDRE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_8 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_8 rise@8.200ns - rxWordclkl12_8 rise@0.000ns) Data Path Delay: 3.857ns (logic 1.095ns (28.387%) route 2.762ns (71.613%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.228ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.694ns = ( 8.894 - 8.200 ) Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.922 0.922 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[0]) 1.009 1.931 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[0] net (fo=13, routed) 1.634 3.566 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gt0_rxdata_out[0] SLICE_X182Y271 LUT4 (Prop_lut4_I1_O) 0.043 3.609 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6/O net (fo=3, routed) 0.750 4.359 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6_n_0 SLICE_X181Y269 LUT6 (Prop_lut6_I1_O) 0.043 4.402 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders[6]_i_1__6/O net (fo=7, routed) 0.378 4.780 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders0 SLICE_X181Y265 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 8.200 8.200 r BUFHCE_X1Y62 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.694 8.894 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK SLICE_X181Y265 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[1]/C clock pessimism 0.000 8.894 clock uncertainty -0.035 8.859 SLICE_X181Y265 FDRE (Setup_fdre_C_CE) -0.201 8.658 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[1] ------------------------------------------------------------------- required time 8.658 arrival time -4.780 ------------------------------------------------------------------- slack 3.878 Slack (MET) : 3.878ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[5]/CE (rising edge-triggered cell FDRE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_8 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_8 rise@8.200ns - rxWordclkl12_8 rise@0.000ns) Data Path Delay: 3.857ns (logic 1.095ns (28.387%) route 2.762ns (71.613%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.228ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.694ns = ( 8.894 - 8.200 ) Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.922 0.922 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[0]) 1.009 1.931 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[0] net (fo=13, routed) 1.634 3.566 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gt0_rxdata_out[0] SLICE_X182Y271 LUT4 (Prop_lut4_I1_O) 0.043 3.609 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6/O net (fo=3, routed) 0.750 4.359 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6_n_0 SLICE_X181Y269 LUT6 (Prop_lut6_I1_O) 0.043 4.402 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders[6]_i_1__6/O net (fo=7, routed) 0.378 4.780 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders0 SLICE_X181Y265 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 8.200 8.200 r BUFHCE_X1Y62 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.694 8.894 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK SLICE_X181Y265 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[5]/C clock pessimism 0.000 8.894 clock uncertainty -0.035 8.859 SLICE_X181Y265 FDRE (Setup_fdre_C_CE) -0.201 8.658 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[5] ------------------------------------------------------------------- required time 8.658 arrival time -4.780 ------------------------------------------------------------------- slack 3.878 Slack (MET) : 3.878ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[6]/CE (rising edge-triggered cell FDRE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_8 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_8 rise@8.200ns - rxWordclkl12_8 rise@0.000ns) Data Path Delay: 3.857ns (logic 1.095ns (28.387%) route 2.762ns (71.613%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.228ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.694ns = ( 8.894 - 8.200 ) Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.922 0.922 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[0]) 1.009 1.931 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[0] net (fo=13, routed) 1.634 3.566 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gt0_rxdata_out[0] SLICE_X182Y271 LUT4 (Prop_lut4_I1_O) 0.043 3.609 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6/O net (fo=3, routed) 0.750 4.359 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6_n_0 SLICE_X181Y269 LUT6 (Prop_lut6_I1_O) 0.043 4.402 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders[6]_i_1__6/O net (fo=7, routed) 0.378 4.780 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders0 SLICE_X181Y265 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 8.200 8.200 r BUFHCE_X1Y62 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.694 8.894 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK SLICE_X181Y265 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[6]/C clock pessimism 0.000 8.894 clock uncertainty -0.035 8.859 SLICE_X181Y265 FDRE (Setup_fdre_C_CE) -0.201 8.658 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[6] ------------------------------------------------------------------- required time 8.658 arrival time -4.780 ------------------------------------------------------------------- slack 3.878 Slack (MET) : 3.914ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[0]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_8 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_8 rise@8.200ns - rxWordclkl12_8 rise@0.000ns) Data Path Delay: 4.052ns (logic 1.181ns (29.148%) route 2.871ns (70.852%)) Logic Levels: 4 (LUT4=2 LUT5=1 LUT6=1) Clock Path Skew: -0.232ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.690ns = ( 8.890 - 8.200 ) Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.922 0.922 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[0]) 1.009 1.931 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[0] net (fo=13, routed) 1.634 3.566 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gt0_rxdata_out[0] SLICE_X182Y271 LUT4 (Prop_lut4_I1_O) 0.043 3.609 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6/O net (fo=3, routed) 0.732 4.341 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6_n_0 SLICE_X182Y269 LUT5 (Prop_lut5_I0_O) 0.043 4.384 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_5__6/O net (fo=1, routed) 0.187 4.571 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_5__6_n_0 SLICE_X182Y270 LUT6 (Prop_lut6_I0_O) 0.043 4.614 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_4__6/O net (fo=2, routed) 0.318 4.931 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_4__6_n_0 SLICE_X187Y270 LUT4 (Prop_lut4_I2_O) 0.043 4.974 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[0]_i_1__7/O net (fo=1, routed) 0.000 4.974 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[0]_i_1__7_n_0 SLICE_X187Y270 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[0]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 8.200 8.200 r BUFHCE_X1Y62 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.690 8.890 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK SLICE_X187Y270 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.000 8.890 clock uncertainty -0.035 8.855 SLICE_X187Y270 FDCE (Setup_fdce_C_D) 0.034 8.889 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 8.889 arrival time -4.974 ------------------------------------------------------------------- slack 3.914 Slack (MET) : 3.932ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[1]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_8 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_8 rise@8.200ns - rxWordclkl12_8 rise@0.000ns) Data Path Delay: 4.058ns (logic 1.187ns (29.253%) route 2.871ns (70.747%)) Logic Levels: 4 (LUT4=1 LUT5=2 LUT6=1) Clock Path Skew: -0.232ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.690ns = ( 8.890 - 8.200 ) Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.922 0.922 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[0]) 1.009 1.931 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[0] net (fo=13, routed) 1.634 3.566 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gt0_rxdata_out[0] SLICE_X182Y271 LUT4 (Prop_lut4_I1_O) 0.043 3.609 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6/O net (fo=3, routed) 0.732 4.341 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6_n_0 SLICE_X182Y269 LUT5 (Prop_lut5_I0_O) 0.043 4.384 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_5__6/O net (fo=1, routed) 0.187 4.571 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_5__6_n_0 SLICE_X182Y270 LUT6 (Prop_lut6_I0_O) 0.043 4.614 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_4__6/O net (fo=2, routed) 0.318 4.931 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_4__6_n_0 SLICE_X187Y270 LUT5 (Prop_lut5_I3_O) 0.049 4.980 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_1__7/O net (fo=1, routed) 0.000 4.980 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_1__7_n_0 SLICE_X187Y270 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[1]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 8.200 8.200 r BUFHCE_X1Y62 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.690 8.890 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK SLICE_X187Y270 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.000 8.890 clock uncertainty -0.035 8.855 SLICE_X187Y270 FDCE (Setup_fdce_C_D) 0.058 8.913 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 8.913 arrival time -4.980 ------------------------------------------------------------------- slack 3.932 Slack (MET) : 3.946ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[0]/CE (rising edge-triggered cell FDRE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_8 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_8 rise@8.200ns - rxWordclkl12_8 rise@0.000ns) Data Path Delay: 3.786ns (logic 1.095ns (28.919%) route 2.691ns (71.081%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.691ns = ( 8.891 - 8.200 ) Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.922 0.922 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[0]) 1.009 1.931 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[0] net (fo=13, routed) 1.634 3.566 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gt0_rxdata_out[0] SLICE_X182Y271 LUT4 (Prop_lut4_I1_O) 0.043 3.609 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6/O net (fo=3, routed) 0.750 4.359 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6_n_0 SLICE_X181Y269 LUT6 (Prop_lut6_I1_O) 0.043 4.402 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders[6]_i_1__6/O net (fo=7, routed) 0.307 4.709 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders0 SLICE_X181Y269 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 8.200 8.200 r BUFHCE_X1Y62 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.691 8.891 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK SLICE_X181Y269 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[0]/C clock pessimism 0.000 8.891 clock uncertainty -0.035 8.856 SLICE_X181Y269 FDRE (Setup_fdre_C_CE) -0.201 8.655 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[0] ------------------------------------------------------------------- required time 8.655 arrival time -4.709 ------------------------------------------------------------------- slack 3.946 Slack (MET) : 3.959ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[2]/CE (rising edge-triggered cell FDRE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_8 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_8 rise@8.200ns - rxWordclkl12_8 rise@0.000ns) Data Path Delay: 3.775ns (logic 1.095ns (29.005%) route 2.680ns (70.995%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.229ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.693ns = ( 8.893 - 8.200 ) Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.922 0.922 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[0]) 1.009 1.931 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[0] net (fo=13, routed) 1.634 3.566 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gt0_rxdata_out[0] SLICE_X182Y271 LUT4 (Prop_lut4_I1_O) 0.043 3.609 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6/O net (fo=3, routed) 0.750 4.359 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6_n_0 SLICE_X181Y269 LUT6 (Prop_lut6_I1_O) 0.043 4.402 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders[6]_i_1__6/O net (fo=7, routed) 0.296 4.698 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders0 SLICE_X181Y266 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 8.200 8.200 r BUFHCE_X1Y62 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.693 8.893 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK SLICE_X181Y266 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[2]/C clock pessimism 0.000 8.893 clock uncertainty -0.035 8.858 SLICE_X181Y266 FDRE (Setup_fdre_C_CE) -0.201 8.657 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[2] ------------------------------------------------------------------- required time 8.657 arrival time -4.698 ------------------------------------------------------------------- slack 3.959 Slack (MET) : 3.959ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[3]/CE (rising edge-triggered cell FDRE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_8 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_8 rise@8.200ns - rxWordclkl12_8 rise@0.000ns) Data Path Delay: 3.775ns (logic 1.095ns (29.005%) route 2.680ns (70.995%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.229ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.693ns = ( 8.893 - 8.200 ) Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.922 0.922 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[0]) 1.009 1.931 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[0] net (fo=13, routed) 1.634 3.566 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gt0_rxdata_out[0] SLICE_X182Y271 LUT4 (Prop_lut4_I1_O) 0.043 3.609 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6/O net (fo=3, routed) 0.750 4.359 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6_n_0 SLICE_X181Y269 LUT6 (Prop_lut6_I1_O) 0.043 4.402 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders[6]_i_1__6/O net (fo=7, routed) 0.296 4.698 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders0 SLICE_X181Y266 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 8.200 8.200 r BUFHCE_X1Y62 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.693 8.893 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK SLICE_X181Y266 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[3]/C clock pessimism 0.000 8.893 clock uncertainty -0.035 8.858 SLICE_X181Y266 FDRE (Setup_fdre_C_CE) -0.201 8.657 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[3] ------------------------------------------------------------------- required time 8.657 arrival time -4.698 ------------------------------------------------------------------- slack 3.959 Slack (MET) : 3.959ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[4]/CE (rising edge-triggered cell FDRE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_8 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_8 rise@8.200ns - rxWordclkl12_8 rise@0.000ns) Data Path Delay: 3.775ns (logic 1.095ns (29.005%) route 2.680ns (70.995%)) Logic Levels: 2 (LUT4=1 LUT6=1) Clock Path Skew: -0.229ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.693ns = ( 8.893 - 8.200 ) Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.922 0.922 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[0]) 1.009 1.931 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[0] net (fo=13, routed) 1.634 3.566 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gt0_rxdata_out[0] SLICE_X182Y271 LUT4 (Prop_lut4_I1_O) 0.043 3.609 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6/O net (fo=3, routed) 0.750 4.359 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state[1]_i_3__6_n_0 SLICE_X181Y269 LUT6 (Prop_lut6_I1_O) 0.043 4.402 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders[6]_i_1__6/O net (fo=7, routed) 0.296 4.698 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders0 SLICE_X181Y266 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 8.200 8.200 r BUFHCE_X1Y62 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.693 8.893 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK SLICE_X181Y266 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[4]/C clock pessimism 0.000 8.893 clock uncertainty -0.035 8.858 SLICE_X181Y266 FDRE (Setup_fdre_C_CE) -0.201 8.657 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[4] ------------------------------------------------------------------- required time 8.657 arrival time -4.698 ------------------------------------------------------------------- slack 3.959 Slack (MET) : 4.035ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[95]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_8 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_8 rise@8.200ns - rxWordclkl12_8 rise@0.000ns) Data Path Delay: 3.806ns (logic 1.200ns (31.532%) route 2.606ns (68.468%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.235ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.687ns = ( 8.887 - 8.200 ) Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.922 0.922 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[3]) 1.009 1.931 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[3] net (fo=13, routed) 1.620 3.552 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19]_0[3] SLICE_X179Y275 LUT5 (Prop_lut5_I0_O) 0.052 3.604 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[95]_i_3__6/O net (fo=6, routed) 0.711 4.315 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[95]_i_3__6_n_0 SLICE_X181Y277 LUT4 (Prop_lut4_I1_O) 0.139 4.454 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/reg0[95]_i_2__6/O net (fo=1, routed) 0.274 4.728 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_1[91] SLICE_X182Y277 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[95]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 8.200 8.200 r BUFHCE_X1Y62 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.687 8.887 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X182Y277 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[95]/C clock pessimism 0.000 8.887 clock uncertainty -0.035 8.852 SLICE_X182Y277 FDCE (Setup_fdce_C_D) -0.089 8.763 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[95] ------------------------------------------------------------------- required time 8.763 arrival time -4.728 ------------------------------------------------------------------- slack 4.035 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.085ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[38]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[38]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_8 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_8 rise@0.000ns - rxWordclkl12_8 rise@0.000ns) Data Path Delay: 0.183ns (logic 0.128ns (70.125%) route 0.055ns (29.875%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.525ns Source Clock Delay (SCD): 0.373ns Clock Pessimism Removal (CPR): 0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.373 0.373 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X179Y276 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[38]/C ------------------------------------------------------------------- ------------------- SLICE_X179Y276 FDCE (Prop_fdce_C_Q) 0.100 0.473 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[38]/Q net (fo=1, routed) 0.055 0.528 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[38] SLICE_X178Y276 LUT6 (Prop_lut6_I5_O) 0.028 0.556 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1[38]_i_1__6/O net (fo=1, routed) 0.000 0.556 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/p_0_out[38] SLICE_X178Y276 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[38]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.525 0.525 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X178Y276 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[38]/C clock pessimism -0.141 0.384 SLICE_X178Y276 FDCE (Hold_fdce_C_D) 0.087 0.471 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[38] ------------------------------------------------------------------- required time -0.471 arrival time 0.556 ------------------------------------------------------------------- slack 0.085 Slack (MET) : 0.086ns (arrival time - required time) Source: ngFEC/SFP_GEN[12].rx_data_reg[12][32]/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[32]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_8 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_8 rise@0.000ns - rxWordclkl12_8 rise@0.000ns) Data Path Delay: 0.184ns (logic 0.128ns (69.743%) route 0.056ns (30.257%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.519ns Source Clock Delay (SCD): 0.367ns Clock Pessimism Removal (CPR): 0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.367 0.367 ngFEC/gbtbank3_l12_116_n_137 SLICE_X167Y274 FDRE r ngFEC/SFP_GEN[12].rx_data_reg[12][32]/C ------------------------------------------------------------------- ------------------- SLICE_X167Y274 FDRE (Prop_fdre_C_Q) 0.100 0.467 r ngFEC/SFP_GEN[12].rx_data_reg[12][32]/Q net (fo=1, routed) 0.056 0.523 ngFEC/gbtbank3_l12_116/RX_Word_rx40_reg[78][16] SLICE_X166Y274 LUT3 (Prop_lut3_I2_O) 0.028 0.551 r ngFEC/gbtbank3_l12_116/RX_Word_rx40[32]_i_1__1/O net (fo=1, routed) 0.000 0.551 ngFEC/SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[83]_0[24] SLICE_X166Y274 FDCE r ngFEC/SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[32]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.519 0.519 ngFEC/SFP_GEN[12].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X166Y274 FDCE r ngFEC/SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[32]/C clock pessimism -0.141 0.378 SLICE_X166Y274 FDCE (Hold_fdce_C_D) 0.087 0.465 ngFEC/SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[32] ------------------------------------------------------------------- required time -0.465 arrival time 0.551 ------------------------------------------------------------------- slack 0.086 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_8 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_8 rise@0.000ns - rxWordclkl12_8 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.539ns Source Clock Delay (SCD): 0.383ns Clock Pessimism Removal (CPR): 0.156ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.383 0.383 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in SLICE_X187Y288 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X187Y288 FDRE (Prop_fdre_C_Q) 0.100 0.483 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q net (fo=1, routed) 0.055 0.538 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync1 SLICE_X187Y288 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.539 0.539 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in SLICE_X187Y288 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C clock pessimism -0.156 0.383 SLICE_X187Y288 FDRE (Hold_fdre_C_D) 0.047 0.430 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.430 arrival time 0.538 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_8 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_8 rise@0.000ns - rxWordclkl12_8 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.536ns Source Clock Delay (SCD): 0.381ns Clock Pessimism Removal (CPR): 0.155ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.381 0.381 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/gt0_rxusrclk_in SLICE_X185Y286 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X185Y286 FDRE (Prop_fdre_C_Q) 0.100 0.481 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/Q net (fo=1, routed) 0.055 0.536 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync1 SLICE_X185Y286 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.536 0.536 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/gt0_rxusrclk_in SLICE_X185Y286 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/C clock pessimism -0.155 0.381 SLICE_X185Y286 FDRE (Hold_fdre_C_D) 0.047 0.428 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.428 arrival time 0.536 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.111ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_8 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_8 rise@0.000ns - rxWordclkl12_8 rise@0.000ns) Data Path Delay: 0.209ns (logic 0.128ns (61.382%) route 0.081ns (38.618%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.521ns Source Clock Delay (SCD): 0.369ns Clock Pessimism Removal (CPR): 0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.369 0.369 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X171Y276 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X171Y276 FDCE (Prop_fdce_C_Q) 0.100 0.469 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[0]/Q net (fo=1, routed) 0.081 0.550 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[0] SLICE_X170Y276 LUT3 (Prop_lut3_I0_O) 0.028 0.578 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__6/O net (fo=1, routed) 0.000 0.578 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out[0] SLICE_X170Y276 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.521 0.521 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X170Y276 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C clock pessimism -0.141 0.380 SLICE_X170Y276 FDRE (Hold_fdre_C_D) 0.087 0.467 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[0] ------------------------------------------------------------------- required time -0.467 arrival time 0.578 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.111ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[54]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[54]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_8 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_8 rise@0.000ns - rxWordclkl12_8 rise@0.000ns) Data Path Delay: 0.209ns (logic 0.128ns (61.382%) route 0.081ns (38.618%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.524ns Source Clock Delay (SCD): 0.372ns Clock Pessimism Removal (CPR): 0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.372 0.372 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X179Y275 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[54]/C ------------------------------------------------------------------- ------------------- SLICE_X179Y275 FDCE (Prop_fdce_C_Q) 0.100 0.472 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[54]/Q net (fo=1, routed) 0.081 0.553 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[54] SLICE_X178Y275 LUT6 (Prop_lut6_I5_O) 0.028 0.581 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1[54]_i_1__6/O net (fo=1, routed) 0.000 0.581 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/p_0_out[54] SLICE_X178Y275 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[54]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.524 0.524 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X178Y275 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[54]/C clock pessimism -0.141 0.383 SLICE_X178Y275 FDCE (Hold_fdce_C_D) 0.087 0.470 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[54] ------------------------------------------------------------------- required time -0.470 arrival time 0.581 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.113ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[59]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[59]/D (rising edge-triggered cell FDCE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_8 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_8 rise@0.000ns - rxWordclkl12_8 rise@0.000ns) Data Path Delay: 0.233ns (logic 0.128ns (54.892%) route 0.105ns (45.108%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.033ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.526ns Source Clock Delay (SCD): 0.373ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.373 0.373 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X184Y273 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[59]/C ------------------------------------------------------------------- ------------------- SLICE_X184Y273 FDCE (Prop_fdce_C_Q) 0.100 0.473 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[59]/Q net (fo=1, routed) 0.105 0.578 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[59] SLICE_X182Y273 LUT6 (Prop_lut6_I5_O) 0.028 0.606 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1[59]_i_1__6/O net (fo=1, routed) 0.000 0.606 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/p_0_out[59] SLICE_X182Y273 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[59]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.526 0.526 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X182Y273 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[59]/C clock pessimism -0.120 0.406 SLICE_X182Y273 FDCE (Hold_fdce_C_D) 0.087 0.493 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[59] ------------------------------------------------------------------- required time -0.493 arrival time 0.606 ------------------------------------------------------------------- slack 0.113 Slack (MET) : 0.118ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_8 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_8 rise@0.000ns - rxWordclkl12_8 rise@0.000ns) Data Path Delay: 0.216ns (logic 0.128ns (59.223%) route 0.088ns (40.777%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.525ns Source Clock Delay (SCD): 0.372ns Clock Pessimism Removal (CPR): 0.142ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.372 0.372 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X171Y270 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X171Y270 FDCE (Prop_fdce_C_Q) 0.100 0.472 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[11]/Q net (fo=2, routed) 0.088 0.560 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_21_in SLICE_X170Y270 LUT3 (Prop_lut3_I0_O) 0.028 0.588 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[11]_i_1__6/O net (fo=1, routed) 0.000 0.588 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[11] SLICE_X170Y270 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.525 0.525 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X170Y270 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11]/C clock pessimism -0.142 0.383 SLICE_X170Y270 FDRE (Hold_fdre_C_D) 0.087 0.470 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[11] ------------------------------------------------------------------- required time -0.470 arrival time 0.588 ------------------------------------------------------------------- slack 0.118 Slack (MET) : 0.119ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_8 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_8 rise@0.000ns - rxWordclkl12_8 rise@0.000ns) Data Path Delay: 0.217ns (logic 0.128ns (59.069%) route 0.089ns (40.931%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.525ns Source Clock Delay (SCD): 0.372ns Clock Pessimism Removal (CPR): 0.142ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.372 0.372 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X175Y271 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X175Y271 FDCE (Prop_fdce_C_Q) 0.100 0.472 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/Q net (fo=2, routed) 0.089 0.561 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_35_in SLICE_X174Y271 LUT3 (Prop_lut3_I0_O) 0.028 0.589 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[18]_i_1__6/O net (fo=1, routed) 0.000 0.589 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out[18] SLICE_X174Y271 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.525 0.525 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X174Y271 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C clock pessimism -0.142 0.383 SLICE_X174Y271 FDRE (Hold_fdre_C_D) 0.087 0.470 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18] ------------------------------------------------------------------- required time -0.470 arrival time 0.589 ------------------------------------------------------------------- slack 0.119 Slack (MET) : 0.124ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[12].rx_data_reg[12][67]/D (rising edge-triggered cell FDRE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl12_8 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_8 rise@0.000ns - rxWordclkl12_8 rise@0.000ns) Data Path Delay: 0.205ns (logic 0.100ns (48.892%) route 0.105ns (51.108%)) Logic Levels: 0 Clock Path Skew: 0.034ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.528ns Source Clock Delay (SCD): 0.374ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.374 0.374 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X169Y268 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X169Y268 FDRE (Prop_fdre_C_Q) 0.100 0.474 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/Q net (fo=1, routed) 0.105 0.579 ngFEC/GBT_rx_data[8]_1383[67] SLICE_X172Y268 FDRE r ngFEC/SFP_GEN[12].rx_data_reg[12][67]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.528 0.528 ngFEC/gbtbank3_l12_116_n_137 SLICE_X172Y268 FDRE r ngFEC/SFP_GEN[12].rx_data_reg[12][67]/C clock pessimism -0.120 0.408 SLICE_X172Y268 FDRE (Hold_fdre_C_D) 0.047 0.455 ngFEC/SFP_GEN[12].rx_data_reg[12][67] ------------------------------------------------------------------- required time -0.455 arrival time 0.579 ------------------------------------------------------------------- slack 0.124 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: rxWordclkl12_8 Waveform(ns): { 0.000 4.100 } Period(ns): 8.200 Sources: { ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/RXUSRCLK n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y23 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK Min Period n/a GTXE2_CHANNEL/RXUSRCLK2 n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y23 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X107Y250 ngFEC/SFP_GEN[12].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[68]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X107Y250 ngFEC/SFP_GEN[12].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[70]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X122Y250 ngFEC/SFP_GEN[12].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[72]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X122Y250 ngFEC/SFP_GEN[12].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[74]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X122Y250 ngFEC/SFP_GEN[12].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[76]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X166Y261 ngFEC/SFP_GEN[12].ngCCM_gbt/RX_Clock_20MHz_dl_reg[4]__0/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X168Y267 ngFEC/SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[21]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X168Y267 ngFEC/SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[22]/C Low Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X166Y261 ngFEC/SFP_GEN[12].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK Low Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X166Y261 ngFEC/SFP_GEN[12].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK Low Pulse Width Slow FDRE/C n/a 0.400 4.100 3.700 SLICE_X107Y250 ngFEC/SFP_GEN[12].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[68]/C Low Pulse Width Slow FDRE/C n/a 0.400 4.100 3.700 SLICE_X107Y250 ngFEC/SFP_GEN[12].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[70]/C Low Pulse Width Slow FDRE/C n/a 0.400 4.100 3.700 SLICE_X122Y250 ngFEC/SFP_GEN[12].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[72]/C Low Pulse Width Slow FDRE/C n/a 0.400 4.100 3.700 SLICE_X122Y250 ngFEC/SFP_GEN[12].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[74]/C Low Pulse Width Slow FDRE/C n/a 0.400 4.100 3.700 SLICE_X122Y250 ngFEC/SFP_GEN[12].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[76]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X168Y267 ngFEC/SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[21]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X168Y267 ngFEC/SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[22]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X168Y267 ngFEC/SFP_GEN[12].ngCCM_gbt/RX_Word_rx40_reg[23]/C High Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X166Y261 ngFEC/SFP_GEN[12].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X166Y261 ngFEC/SFP_GEN[12].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X174Y271 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[18]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X172Y278 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X172Y278 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[5]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X172Y278 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[6]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X175Y278 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X175Y271 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X174Y278 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X173Y271 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[4]/C --------------------------------------------------------------------------------------------------- From Clock: rxWordclkl8_1 To Clock: rxWordclkl8_1 Setup : 0 Failing Endpoints, Worst Slack 3.373ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.108ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.458ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.373ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[46]/CE (rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_1 rise@8.200ns - rxWordclkl8_1 rise@0.000ns) Data Path Delay: 4.493ns (logic 0.266ns (5.920%) route 4.227ns (94.080%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.097ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.648ns = ( 8.848 - 8.200 ) Source Clock Delay (SCD): 0.745ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.745 0.745 ngFEC/gbtbank4_l8_112/MGT_RXUSRCLK_o[1] SLICE_X179Y63 FDCE r ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C ------------------------------------------------------------------- ------------------- SLICE_X179Y63 FDCE (Prop_fdce_C_Q) 0.223 0.968 r ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/Q net (fo=127, routed) 1.982 2.950 ngFEC/SFP_GEN[5].ngCCM_gbt/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0] SLICE_X171Y94 LUT3 (Prop_lut3_I2_O) 0.043 2.993 r ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40[83]_i_1__2/O net (fo=48, routed) 2.246 5.238 ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40 SLICE_X165Y57 FDCE r ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[46]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 8.200 8.200 r BUFHCE_X1Y12 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.648 8.848 ngFEC/SFP_GEN[5].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X165Y57 FDCE r ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[46]/C clock pessimism 0.000 8.848 clock uncertainty -0.035 8.813 SLICE_X165Y57 FDCE (Setup_fdce_C_CE) -0.201 8.612 ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[46] ------------------------------------------------------------------- required time 8.612 arrival time -5.238 ------------------------------------------------------------------- slack 3.373 Slack (MET) : 3.373ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[6]/CE (rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_1 rise@8.200ns - rxWordclkl8_1 rise@0.000ns) Data Path Delay: 4.493ns (logic 0.266ns (5.920%) route 4.227ns (94.080%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.097ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.648ns = ( 8.848 - 8.200 ) Source Clock Delay (SCD): 0.745ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.745 0.745 ngFEC/gbtbank4_l8_112/MGT_RXUSRCLK_o[1] SLICE_X179Y63 FDCE r ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C ------------------------------------------------------------------- ------------------- SLICE_X179Y63 FDCE (Prop_fdce_C_Q) 0.223 0.968 r ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/Q net (fo=127, routed) 1.982 2.950 ngFEC/SFP_GEN[5].ngCCM_gbt/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0] SLICE_X171Y94 LUT3 (Prop_lut3_I2_O) 0.043 2.993 r ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40[83]_i_1__2/O net (fo=48, routed) 2.246 5.238 ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40 SLICE_X165Y57 FDCE r ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 8.200 8.200 r BUFHCE_X1Y12 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.648 8.848 ngFEC/SFP_GEN[5].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X165Y57 FDCE r ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[6]/C clock pessimism 0.000 8.848 clock uncertainty -0.035 8.813 SLICE_X165Y57 FDCE (Setup_fdce_C_CE) -0.201 8.612 ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[6] ------------------------------------------------------------------- required time 8.612 arrival time -5.238 ------------------------------------------------------------------- slack 3.373 Slack (MET) : 3.411ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[64]/CE (rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_1 rise@8.200ns - rxWordclkl8_1 rise@0.000ns) Data Path Delay: 4.480ns (logic 0.266ns (5.937%) route 4.214ns (94.063%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.096ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.649ns = ( 8.849 - 8.200 ) Source Clock Delay (SCD): 0.745ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.745 0.745 ngFEC/gbtbank4_l8_112/MGT_RXUSRCLK_o[1] SLICE_X179Y63 FDCE r ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C ------------------------------------------------------------------- ------------------- SLICE_X179Y63 FDCE (Prop_fdce_C_Q) 0.223 0.968 r ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/Q net (fo=127, routed) 1.982 2.950 ngFEC/SFP_GEN[5].ngCCM_gbt/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0] SLICE_X171Y94 LUT3 (Prop_lut3_I2_O) 0.043 2.993 r ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40[83]_i_1__2/O net (fo=48, routed) 2.232 5.225 ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40 SLICE_X162Y53 FDCE r ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[64]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 8.200 8.200 r BUFHCE_X1Y12 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.649 8.849 ngFEC/SFP_GEN[5].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X162Y53 FDCE r ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[64]/C clock pessimism 0.000 8.849 clock uncertainty -0.035 8.814 SLICE_X162Y53 FDCE (Setup_fdce_C_CE) -0.178 8.636 ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[64] ------------------------------------------------------------------- required time 8.636 arrival time -5.225 ------------------------------------------------------------------- slack 3.411 Slack (MET) : 3.411ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[66]/CE (rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_1 rise@8.200ns - rxWordclkl8_1 rise@0.000ns) Data Path Delay: 4.480ns (logic 0.266ns (5.937%) route 4.214ns (94.063%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.096ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.649ns = ( 8.849 - 8.200 ) Source Clock Delay (SCD): 0.745ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.745 0.745 ngFEC/gbtbank4_l8_112/MGT_RXUSRCLK_o[1] SLICE_X179Y63 FDCE r ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C ------------------------------------------------------------------- ------------------- SLICE_X179Y63 FDCE (Prop_fdce_C_Q) 0.223 0.968 r ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/Q net (fo=127, routed) 1.982 2.950 ngFEC/SFP_GEN[5].ngCCM_gbt/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0] SLICE_X171Y94 LUT3 (Prop_lut3_I2_O) 0.043 2.993 r ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40[83]_i_1__2/O net (fo=48, routed) 2.232 5.225 ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40 SLICE_X162Y53 FDCE r ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[66]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 8.200 8.200 r BUFHCE_X1Y12 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.649 8.849 ngFEC/SFP_GEN[5].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X162Y53 FDCE r ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[66]/C clock pessimism 0.000 8.849 clock uncertainty -0.035 8.814 SLICE_X162Y53 FDCE (Setup_fdce_C_CE) -0.178 8.636 ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[66] ------------------------------------------------------------------- required time 8.636 arrival time -5.225 ------------------------------------------------------------------- slack 3.411 Slack (MET) : 3.617ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[52]/CE (rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_1 rise@8.200ns - rxWordclkl8_1 rise@0.000ns) Data Path Delay: 4.273ns (logic 0.266ns (6.225%) route 4.007ns (93.775%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.096ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.649ns = ( 8.849 - 8.200 ) Source Clock Delay (SCD): 0.745ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.745 0.745 ngFEC/gbtbank4_l8_112/MGT_RXUSRCLK_o[1] SLICE_X179Y63 FDCE r ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C ------------------------------------------------------------------- ------------------- SLICE_X179Y63 FDCE (Prop_fdce_C_Q) 0.223 0.968 r ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/Q net (fo=127, routed) 1.982 2.950 ngFEC/SFP_GEN[5].ngCCM_gbt/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0] SLICE_X171Y94 LUT3 (Prop_lut3_I2_O) 0.043 2.993 r ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40[83]_i_1__2/O net (fo=48, routed) 2.025 5.018 ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40 SLICE_X162Y51 FDCE r ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[52]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 8.200 8.200 r BUFHCE_X1Y12 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.649 8.849 ngFEC/SFP_GEN[5].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X162Y51 FDCE r ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[52]/C clock pessimism 0.000 8.849 clock uncertainty -0.035 8.814 SLICE_X162Y51 FDCE (Setup_fdce_C_CE) -0.178 8.636 ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[52] ------------------------------------------------------------------- required time 8.636 arrival time -5.018 ------------------------------------------------------------------- slack 3.617 Slack (MET) : 3.617ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[54]/CE (rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_1 rise@8.200ns - rxWordclkl8_1 rise@0.000ns) Data Path Delay: 4.273ns (logic 0.266ns (6.225%) route 4.007ns (93.775%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.096ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.649ns = ( 8.849 - 8.200 ) Source Clock Delay (SCD): 0.745ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.745 0.745 ngFEC/gbtbank4_l8_112/MGT_RXUSRCLK_o[1] SLICE_X179Y63 FDCE r ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C ------------------------------------------------------------------- ------------------- SLICE_X179Y63 FDCE (Prop_fdce_C_Q) 0.223 0.968 r ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/Q net (fo=127, routed) 1.982 2.950 ngFEC/SFP_GEN[5].ngCCM_gbt/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0] SLICE_X171Y94 LUT3 (Prop_lut3_I2_O) 0.043 2.993 r ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40[83]_i_1__2/O net (fo=48, routed) 2.025 5.018 ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40 SLICE_X162Y51 FDCE r ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[54]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 8.200 8.200 r BUFHCE_X1Y12 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.649 8.849 ngFEC/SFP_GEN[5].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X162Y51 FDCE r ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[54]/C clock pessimism 0.000 8.849 clock uncertainty -0.035 8.814 SLICE_X162Y51 FDCE (Setup_fdce_C_CE) -0.178 8.636 ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[54] ------------------------------------------------------------------- required time 8.636 arrival time -5.018 ------------------------------------------------------------------- slack 3.617 Slack (MET) : 3.617ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[60]/CE (rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_1 rise@8.200ns - rxWordclkl8_1 rise@0.000ns) Data Path Delay: 4.273ns (logic 0.266ns (6.225%) route 4.007ns (93.775%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.096ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.649ns = ( 8.849 - 8.200 ) Source Clock Delay (SCD): 0.745ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.745 0.745 ngFEC/gbtbank4_l8_112/MGT_RXUSRCLK_o[1] SLICE_X179Y63 FDCE r ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C ------------------------------------------------------------------- ------------------- SLICE_X179Y63 FDCE (Prop_fdce_C_Q) 0.223 0.968 r ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/Q net (fo=127, routed) 1.982 2.950 ngFEC/SFP_GEN[5].ngCCM_gbt/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0] SLICE_X171Y94 LUT3 (Prop_lut3_I2_O) 0.043 2.993 r ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40[83]_i_1__2/O net (fo=48, routed) 2.025 5.018 ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40 SLICE_X162Y51 FDCE r ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[60]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 8.200 8.200 r BUFHCE_X1Y12 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.649 8.849 ngFEC/SFP_GEN[5].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X162Y51 FDCE r ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[60]/C clock pessimism 0.000 8.849 clock uncertainty -0.035 8.814 SLICE_X162Y51 FDCE (Setup_fdce_C_CE) -0.178 8.636 ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[60] ------------------------------------------------------------------- required time 8.636 arrival time -5.018 ------------------------------------------------------------------- slack 3.617 Slack (MET) : 3.617ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[62]/CE (rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_1 rise@8.200ns - rxWordclkl8_1 rise@0.000ns) Data Path Delay: 4.273ns (logic 0.266ns (6.225%) route 4.007ns (93.775%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.096ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.649ns = ( 8.849 - 8.200 ) Source Clock Delay (SCD): 0.745ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.745 0.745 ngFEC/gbtbank4_l8_112/MGT_RXUSRCLK_o[1] SLICE_X179Y63 FDCE r ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C ------------------------------------------------------------------- ------------------- SLICE_X179Y63 FDCE (Prop_fdce_C_Q) 0.223 0.968 r ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/Q net (fo=127, routed) 1.982 2.950 ngFEC/SFP_GEN[5].ngCCM_gbt/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0] SLICE_X171Y94 LUT3 (Prop_lut3_I2_O) 0.043 2.993 r ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40[83]_i_1__2/O net (fo=48, routed) 2.025 5.018 ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40 SLICE_X162Y51 FDCE r ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[62]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 8.200 8.200 r BUFHCE_X1Y12 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.649 8.849 ngFEC/SFP_GEN[5].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X162Y51 FDCE r ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[62]/C clock pessimism 0.000 8.849 clock uncertainty -0.035 8.814 SLICE_X162Y51 FDCE (Setup_fdce_C_CE) -0.178 8.636 ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[62] ------------------------------------------------------------------- required time 8.636 arrival time -5.018 ------------------------------------------------------------------- slack 3.617 Slack (MET) : 3.617ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[68]/CE (rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_1 rise@8.200ns - rxWordclkl8_1 rise@0.000ns) Data Path Delay: 4.273ns (logic 0.266ns (6.225%) route 4.007ns (93.775%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.096ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.649ns = ( 8.849 - 8.200 ) Source Clock Delay (SCD): 0.745ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.745 0.745 ngFEC/gbtbank4_l8_112/MGT_RXUSRCLK_o[1] SLICE_X179Y63 FDCE r ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C ------------------------------------------------------------------- ------------------- SLICE_X179Y63 FDCE (Prop_fdce_C_Q) 0.223 0.968 r ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/Q net (fo=127, routed) 1.982 2.950 ngFEC/SFP_GEN[5].ngCCM_gbt/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0] SLICE_X171Y94 LUT3 (Prop_lut3_I2_O) 0.043 2.993 r ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40[83]_i_1__2/O net (fo=48, routed) 2.025 5.018 ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40 SLICE_X162Y51 FDCE r ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[68]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 8.200 8.200 r BUFHCE_X1Y12 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.649 8.849 ngFEC/SFP_GEN[5].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X162Y51 FDCE r ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[68]/C clock pessimism 0.000 8.849 clock uncertainty -0.035 8.814 SLICE_X162Y51 FDCE (Setup_fdce_C_CE) -0.178 8.636 ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[68] ------------------------------------------------------------------- required time 8.636 arrival time -5.018 ------------------------------------------------------------------- slack 3.617 Slack (MET) : 3.617ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[70]/CE (rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_1 rise@8.200ns - rxWordclkl8_1 rise@0.000ns) Data Path Delay: 4.273ns (logic 0.266ns (6.225%) route 4.007ns (93.775%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.096ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.649ns = ( 8.849 - 8.200 ) Source Clock Delay (SCD): 0.745ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.745 0.745 ngFEC/gbtbank4_l8_112/MGT_RXUSRCLK_o[1] SLICE_X179Y63 FDCE r ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/C ------------------------------------------------------------------- ------------------- SLICE_X179Y63 FDCE (Prop_fdce_C_Q) 0.223 0.968 r ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/Q net (fo=127, routed) 1.982 2.950 ngFEC/SFP_GEN[5].ngCCM_gbt/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0] SLICE_X171Y94 LUT3 (Prop_lut3_I2_O) 0.043 2.993 r ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40[83]_i_1__2/O net (fo=48, routed) 2.025 5.018 ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40 SLICE_X162Y51 FDCE r ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[70]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 8.200 8.200 r BUFHCE_X1Y12 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.649 8.849 ngFEC/SFP_GEN[5].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X162Y51 FDCE r ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[70]/C clock pessimism 0.000 8.849 clock uncertainty -0.035 8.814 SLICE_X162Y51 FDCE (Setup_fdce_C_CE) -0.178 8.636 ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Word_rx40_reg[70] ------------------------------------------------------------------- required time 8.636 arrival time -5.018 ------------------------------------------------------------------- slack 3.617 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_1 rise@0.000ns - rxWordclkl8_1 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.542ns Source Clock Delay (SCD): 0.386ns Clock Pessimism Removal (CPR): 0.156ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.386 0.386 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/gt0_rxusrclk_in SLICE_X185Y52 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X185Y52 FDRE (Prop_fdre_C_Q) 0.100 0.486 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/Q net (fo=1, routed) 0.055 0.541 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync1 SLICE_X185Y52 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.542 0.542 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/gt0_rxusrclk_in SLICE_X185Y52 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/C clock pessimism -0.156 0.386 SLICE_X185Y52 FDRE (Hold_fdre_C_D) 0.047 0.433 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.433 arrival time 0.541 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.111ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D (rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_1 rise@0.000ns - rxWordclkl8_1 rise@0.000ns) Data Path Delay: 0.209ns (logic 0.128ns (61.382%) route 0.081ns (38.618%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.530ns Source Clock Delay (SCD): 0.376ns Clock Pessimism Removal (CPR): 0.143ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.376 0.376 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X167Y63 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X167Y63 FDCE (Prop_fdce_C_Q) 0.100 0.476 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Q net (fo=1, routed) 0.081 0.557 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_33_in SLICE_X166Y63 LUT3 (Prop_lut3_I0_O) 0.028 0.585 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__7/O net (fo=1, routed) 0.000 0.585 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out[17] SLICE_X166Y63 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.530 0.530 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X166Y63 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C clock pessimism -0.143 0.387 SLICE_X166Y63 FDRE (Hold_fdre_C_D) 0.087 0.474 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[17] ------------------------------------------------------------------- required time -0.474 arrival time 0.585 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.111ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[76]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[76]/D (rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_1 rise@0.000ns - rxWordclkl8_1 rise@0.000ns) Data Path Delay: 0.209ns (logic 0.128ns (61.382%) route 0.081ns (38.618%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.538ns Source Clock Delay (SCD): 0.382ns Clock Pessimism Removal (CPR): 0.145ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.382 0.382 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X177Y60 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[76]/C ------------------------------------------------------------------- ------------------- SLICE_X177Y60 FDCE (Prop_fdce_C_Q) 0.100 0.482 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[76]/Q net (fo=1, routed) 0.081 0.563 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0[76] SLICE_X176Y60 LUT2 (Prop_lut2_I1_O) 0.028 0.591 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1[76]_i_1__7/O net (fo=1, routed) 0.000 0.591 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/p_0_out[76] SLICE_X176Y60 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[76]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.538 0.538 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X176Y60 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[76]/C clock pessimism -0.145 0.393 SLICE_X176Y60 FDCE (Hold_fdce_C_D) 0.087 0.480 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg1_reg[76] ------------------------------------------------------------------- required time -0.480 arrival time 0.591 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.113ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_1 rise@0.000ns - rxWordclkl8_1 rise@0.000ns) Data Path Delay: 0.160ns (logic 0.100ns (62.442%) route 0.060ns (37.558%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.542ns Source Clock Delay (SCD): 0.386ns Clock Pessimism Removal (CPR): 0.156ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.386 0.386 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in SLICE_X184Y52 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X184Y52 FDRE (Prop_fdre_C_Q) 0.100 0.486 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q net (fo=1, routed) 0.060 0.546 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync1 SLICE_X184Y52 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.542 0.542 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in SLICE_X184Y52 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C clock pessimism -0.156 0.386 SLICE_X184Y52 FDRE (Hold_fdre_C_D) 0.047 0.433 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.433 arrival time 0.546 ------------------------------------------------------------------- slack 0.113 Slack (MET) : 0.118ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D (rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_1 rise@0.000ns - rxWordclkl8_1 rise@0.000ns) Data Path Delay: 0.216ns (logic 0.128ns (59.274%) route 0.088ns (40.726%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.506ns Source Clock Delay (SCD): 0.352ns Clock Pessimism Removal (CPR): 0.143ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.352 0.352 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X165Y61 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X165Y61 FDCE (Prop_fdce_C_Q) 0.100 0.452 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[17]/Q net (fo=2, routed) 0.088 0.540 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_33_in SLICE_X164Y61 LUT3 (Prop_lut3_I0_O) 0.028 0.568 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[17]_i_1__7/O net (fo=1, routed) 0.000 0.568 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[17] SLICE_X164Y61 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.506 0.506 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X164Y61 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17]/C clock pessimism -0.143 0.363 SLICE_X164Y61 FDRE (Hold_fdre_C_D) 0.087 0.450 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[17] ------------------------------------------------------------------- required time -0.450 arrival time 0.568 ------------------------------------------------------------------- slack 0.118 Slack (MET) : 0.118ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/D (rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_1 rise@0.000ns - rxWordclkl8_1 rise@0.000ns) Data Path Delay: 0.216ns (logic 0.128ns (59.223%) route 0.088ns (40.777%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.533ns Source Clock Delay (SCD): 0.378ns Clock Pessimism Removal (CPR): 0.144ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.378 0.378 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X167Y61 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X167Y61 FDCE (Prop_fdce_C_Q) 0.100 0.478 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[7]/Q net (fo=2, routed) 0.088 0.566 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_13_in SLICE_X166Y61 LUT3 (Prop_lut3_I0_O) 0.028 0.594 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O[7]_i_1__7/O net (fo=1, routed) 0.000 0.594 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/p_40_out[7] SLICE_X166Y61 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.533 0.533 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X166Y61 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C clock pessimism -0.144 0.389 SLICE_X166Y61 FDRE (Hold_fdre_C_D) 0.087 0.476 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/RX_DATA_O_reg[7] ------------------------------------------------------------------- required time -0.476 arrival time 0.594 ------------------------------------------------------------------- slack 0.118 Slack (MET) : 0.121ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C (rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[5].rx_data_reg[5][34]/D (rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_1 rise@0.000ns - rxWordclkl8_1 rise@0.000ns) Data Path Delay: 0.193ns (logic 0.100ns (51.898%) route 0.093ns (48.102%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.503ns Source Clock Delay (SCD): 0.350ns Clock Pessimism Removal (CPR): 0.140ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.350 0.350 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X165Y64 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X165Y64 FDRE (Prop_fdre_C_Q) 0.100 0.450 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/Q net (fo=1, routed) 0.093 0.543 ngFEC/GBT_rx_data[9]_1396[34] SLICE_X162Y64 FDRE r ngFEC/SFP_GEN[5].rx_data_reg[5][34]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.503 0.503 ngFEC/clktest17_in SLICE_X162Y64 FDRE r ngFEC/SFP_GEN[5].rx_data_reg[5][34]/C clock pessimism -0.140 0.363 SLICE_X162Y64 FDRE (Hold_fdre_C_D) 0.059 0.422 ngFEC/SFP_GEN[5].rx_data_reg[5][34] ------------------------------------------------------------------- required time -0.422 arrival time 0.543 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.122ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D (rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_1 rise@0.000ns - rxWordclkl8_1 rise@0.000ns) Data Path Delay: 0.220ns (logic 0.128ns (58.166%) route 0.092ns (41.834%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.508ns Source Clock Delay (SCD): 0.354ns Clock Pessimism Removal (CPR): 0.143ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.354 0.354 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X165Y54 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X165Y54 FDCE (Prop_fdce_C_Q) 0.100 0.454 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/Q net (fo=2, routed) 0.092 0.546 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_3_in SLICE_X164Y54 LUT3 (Prop_lut3_I0_O) 0.028 0.574 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[2]_i_1__7/O net (fo=1, routed) 0.000 0.574 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[2] SLICE_X164Y54 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.508 0.508 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X164Y54 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C clock pessimism -0.143 0.365 SLICE_X164Y54 FDRE (Hold_fdre_C_D) 0.087 0.452 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2] ------------------------------------------------------------------- required time -0.452 arrival time 0.574 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.123ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D (rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_1 rise@0.000ns - rxWordclkl8_1 rise@0.000ns) Data Path Delay: 0.194ns (logic 0.128ns (65.998%) route 0.066ns (34.002%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.536ns Source Clock Delay (SCD): 0.381ns Clock Pessimism Removal (CPR): 0.144ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.381 0.381 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X169Y54 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X169Y54 FDCE (Prop_fdce_C_Q) 0.100 0.481 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/Q net (fo=2, routed) 0.066 0.547 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_31_in SLICE_X168Y54 LUT3 (Prop_lut3_I2_O) 0.028 0.575 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1__7/O net (fo=1, routed) 0.000 0.575 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[14] SLICE_X168Y54 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.536 0.536 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X168Y54 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C clock pessimism -0.144 0.392 SLICE_X168Y54 FDRE (Hold_fdre_C_D) 0.060 0.452 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14] ------------------------------------------------------------------- required time -0.452 arrival time 0.575 ------------------------------------------------------------------- slack 0.123 Slack (MET) : 0.133ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[2]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/shiftPsAddr_reg/D (rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_1 rise@0.000ns - rxWordclkl8_1 rise@0.000ns) Data Path Delay: 0.204ns (logic 0.128ns (62.771%) route 0.076ns (37.229%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.536ns Source Clock Delay (SCD): 0.382ns Clock Pessimism Removal (CPR): 0.143ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.382 0.382 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 SLICE_X189Y63 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X189Y63 FDCE (Prop_fdce_C_Q) 0.100 0.482 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[2]/Q net (fo=6, routed) 0.076 0.558 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt[2] SLICE_X188Y63 LUT6 (Prop_lut6_I4_O) 0.028 0.586 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/shiftPsAddr_i_1__7/O net (fo=1, routed) 0.000 0.586 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/shiftPsAddr3_out SLICE_X188Y63 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/shiftPsAddr_reg/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.536 0.536 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 SLICE_X188Y63 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/shiftPsAddr_reg/C clock pessimism -0.143 0.393 SLICE_X188Y63 FDCE (Hold_fdce_C_D) 0.060 0.453 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/shiftPsAddr_reg ------------------------------------------------------------------- required time -0.453 arrival time 0.586 ------------------------------------------------------------------- slack 0.133 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: rxWordclkl8_1 Waveform(ns): { 0.000 4.100 } Period(ns): 8.200 Sources: { ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/RXUSRCLK n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y4 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK Min Period n/a GTXE2_CHANNEL/RXUSRCLK2 n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y4 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X185Y60 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/FSM_sequential_state_reg[1]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X183Y61 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X189Y63 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[3]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X189Y63 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[4]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X182Y60 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/consecCorrectHeaders_reg[1]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X182Y60 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/consecCorrectHeaders_reg[3]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X184Y60 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/consecFalseHeaders_reg[2]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X181Y63 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/nbCheckedHeaders_reg[0]/C Low Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X170Y73 ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK Low Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X170Y73 ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X183Y61 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X189Y63 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[3]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X189Y63 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[4]/C Low Pulse Width Slow FDRE/C n/a 0.400 4.100 3.700 SLICE_X181Y63 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/nbCheckedHeaders_reg[0]/C Low Pulse Width Slow FDRE/C n/a 0.400 4.100 3.700 SLICE_X181Y64 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/nbCheckedHeaders_reg[3]/C Low Pulse Width Slow FDRE/C n/a 0.400 4.100 3.700 SLICE_X181Y64 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/nbCheckedHeaders_reg[6]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X184Y61 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/psAddress_reg[0]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X184Y61 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/psAddress_reg[2]/C High Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X170Y73 ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X170Y73 ngFEC/SFP_GEN[5].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK High Pulse Width Fast FDRE/C n/a 0.350 4.100 3.750 SLICE_X184Y52 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/run_phase_alignment_int_s3_reg/C High Pulse Width Fast FDRE/C n/a 0.350 4.100 3.750 SLICE_X185Y52 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/rx_fsm_reset_done_int_s3_reg/C High Pulse Width Fast FDRE/C n/a 0.350 4.100 3.750 SLICE_X184Y52 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C High Pulse Width Fast FDRE/C n/a 0.350 4.100 3.750 SLICE_X184Y52 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C High Pulse Width Fast FDRE/C n/a 0.350 4.100 3.750 SLICE_X184Y52 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg3/C High Pulse Width Fast FDRE/C n/a 0.350 4.100 3.750 SLICE_X184Y52 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg4/C High Pulse Width Fast FDRE/C n/a 0.350 4.100 3.750 SLICE_X184Y52 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg5/C High Pulse Width Fast FDRE/C n/a 0.350 4.100 3.750 SLICE_X184Y52 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg6/C --------------------------------------------------------------------------------------------------- From Clock: rxWordclkl8_2 To Clock: rxWordclkl8_2 Setup : 0 Failing Endpoints, Worst Slack 2.599ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.085ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.458ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.599ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[68]/CE (rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_2 rise@8.200ns - rxWordclkl8_2 rise@0.000ns) Data Path Delay: 5.249ns (logic 0.266ns (5.068%) route 4.983ns (94.932%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.116ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.573ns = ( 8.773 - 8.200 ) Source Clock Delay (SCD): 0.689ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.689 0.689 ngFEC/gbtbank4_l8_112/MGT_RXUSRCLK_o[2] SLICE_X153Y64 FDCE r ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C ------------------------------------------------------------------- ------------------- SLICE_X153Y64 FDCE (Prop_fdce_C_Q) 0.223 0.912 r ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/Q net (fo=127, routed) 2.858 3.770 ngFEC/SFP_GEN[6].ngCCM_gbt/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0] SLICE_X140Y97 LUT3 (Prop_lut3_I2_O) 0.043 3.813 r ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40[83]_i_1__1/O net (fo=48, routed) 2.124 5.938 ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40 SLICE_X129Y62 FDCE r ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[68]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 8.200 8.200 r BUFHCE_X1Y13 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.573 8.773 ngFEC/SFP_GEN[6].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X129Y62 FDCE r ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[68]/C clock pessimism 0.000 8.773 clock uncertainty -0.035 8.738 SLICE_X129Y62 FDCE (Setup_fdce_C_CE) -0.201 8.537 ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[68] ------------------------------------------------------------------- required time 8.537 arrival time -5.938 ------------------------------------------------------------------- slack 2.599 Slack (MET) : 2.599ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[70]/CE (rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_2 rise@8.200ns - rxWordclkl8_2 rise@0.000ns) Data Path Delay: 5.249ns (logic 0.266ns (5.068%) route 4.983ns (94.932%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.116ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.573ns = ( 8.773 - 8.200 ) Source Clock Delay (SCD): 0.689ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.689 0.689 ngFEC/gbtbank4_l8_112/MGT_RXUSRCLK_o[2] SLICE_X153Y64 FDCE r ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C ------------------------------------------------------------------- ------------------- SLICE_X153Y64 FDCE (Prop_fdce_C_Q) 0.223 0.912 r ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/Q net (fo=127, routed) 2.858 3.770 ngFEC/SFP_GEN[6].ngCCM_gbt/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0] SLICE_X140Y97 LUT3 (Prop_lut3_I2_O) 0.043 3.813 r ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40[83]_i_1__1/O net (fo=48, routed) 2.124 5.938 ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40 SLICE_X129Y62 FDCE r ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[70]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 8.200 8.200 r BUFHCE_X1Y13 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.573 8.773 ngFEC/SFP_GEN[6].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X129Y62 FDCE r ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[70]/C clock pessimism 0.000 8.773 clock uncertainty -0.035 8.738 SLICE_X129Y62 FDCE (Setup_fdce_C_CE) -0.201 8.537 ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[70] ------------------------------------------------------------------- required time 8.537 arrival time -5.938 ------------------------------------------------------------------- slack 2.599 Slack (MET) : 2.697ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[64]/CE (rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_2 rise@8.200ns - rxWordclkl8_2 rise@0.000ns) Data Path Delay: 5.151ns (logic 0.266ns (5.164%) route 4.885ns (94.836%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.115ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.574ns = ( 8.774 - 8.200 ) Source Clock Delay (SCD): 0.689ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.689 0.689 ngFEC/gbtbank4_l8_112/MGT_RXUSRCLK_o[2] SLICE_X153Y64 FDCE r ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C ------------------------------------------------------------------- ------------------- SLICE_X153Y64 FDCE (Prop_fdce_C_Q) 0.223 0.912 r ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/Q net (fo=127, routed) 2.858 3.770 ngFEC/SFP_GEN[6].ngCCM_gbt/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0] SLICE_X140Y97 LUT3 (Prop_lut3_I2_O) 0.043 3.813 r ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40[83]_i_1__1/O net (fo=48, routed) 2.027 5.840 ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40 SLICE_X129Y60 FDCE r ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[64]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 8.200 8.200 r BUFHCE_X1Y13 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.574 8.774 ngFEC/SFP_GEN[6].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X129Y60 FDCE r ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[64]/C clock pessimism 0.000 8.774 clock uncertainty -0.035 8.739 SLICE_X129Y60 FDCE (Setup_fdce_C_CE) -0.201 8.538 ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[64] ------------------------------------------------------------------- required time 8.538 arrival time -5.840 ------------------------------------------------------------------- slack 2.697 Slack (MET) : 2.697ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[66]/CE (rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_2 rise@8.200ns - rxWordclkl8_2 rise@0.000ns) Data Path Delay: 5.151ns (logic 0.266ns (5.164%) route 4.885ns (94.836%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.115ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.574ns = ( 8.774 - 8.200 ) Source Clock Delay (SCD): 0.689ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.689 0.689 ngFEC/gbtbank4_l8_112/MGT_RXUSRCLK_o[2] SLICE_X153Y64 FDCE r ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C ------------------------------------------------------------------- ------------------- SLICE_X153Y64 FDCE (Prop_fdce_C_Q) 0.223 0.912 r ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/Q net (fo=127, routed) 2.858 3.770 ngFEC/SFP_GEN[6].ngCCM_gbt/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0] SLICE_X140Y97 LUT3 (Prop_lut3_I2_O) 0.043 3.813 r ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40[83]_i_1__1/O net (fo=48, routed) 2.027 5.840 ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40 SLICE_X129Y60 FDCE r ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[66]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 8.200 8.200 r BUFHCE_X1Y13 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.574 8.774 ngFEC/SFP_GEN[6].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X129Y60 FDCE r ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[66]/C clock pessimism 0.000 8.774 clock uncertainty -0.035 8.739 SLICE_X129Y60 FDCE (Setup_fdce_C_CE) -0.201 8.538 ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[66] ------------------------------------------------------------------- required time 8.538 arrival time -5.840 ------------------------------------------------------------------- slack 2.697 Slack (MET) : 2.697ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[72]/CE (rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_2 rise@8.200ns - rxWordclkl8_2 rise@0.000ns) Data Path Delay: 5.151ns (logic 0.266ns (5.164%) route 4.885ns (94.836%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.115ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.574ns = ( 8.774 - 8.200 ) Source Clock Delay (SCD): 0.689ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.689 0.689 ngFEC/gbtbank4_l8_112/MGT_RXUSRCLK_o[2] SLICE_X153Y64 FDCE r ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C ------------------------------------------------------------------- ------------------- SLICE_X153Y64 FDCE (Prop_fdce_C_Q) 0.223 0.912 r ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/Q net (fo=127, routed) 2.858 3.770 ngFEC/SFP_GEN[6].ngCCM_gbt/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0] SLICE_X140Y97 LUT3 (Prop_lut3_I2_O) 0.043 3.813 r ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40[83]_i_1__1/O net (fo=48, routed) 2.027 5.840 ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40 SLICE_X129Y60 FDCE r ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[72]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 8.200 8.200 r BUFHCE_X1Y13 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.574 8.774 ngFEC/SFP_GEN[6].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X129Y60 FDCE r ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[72]/C clock pessimism 0.000 8.774 clock uncertainty -0.035 8.739 SLICE_X129Y60 FDCE (Setup_fdce_C_CE) -0.201 8.538 ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[72] ------------------------------------------------------------------- required time 8.538 arrival time -5.840 ------------------------------------------------------------------- slack 2.697 Slack (MET) : 2.697ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[74]/CE (rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_2 rise@8.200ns - rxWordclkl8_2 rise@0.000ns) Data Path Delay: 5.151ns (logic 0.266ns (5.164%) route 4.885ns (94.836%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.115ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.574ns = ( 8.774 - 8.200 ) Source Clock Delay (SCD): 0.689ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.689 0.689 ngFEC/gbtbank4_l8_112/MGT_RXUSRCLK_o[2] SLICE_X153Y64 FDCE r ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C ------------------------------------------------------------------- ------------------- SLICE_X153Y64 FDCE (Prop_fdce_C_Q) 0.223 0.912 r ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/Q net (fo=127, routed) 2.858 3.770 ngFEC/SFP_GEN[6].ngCCM_gbt/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0] SLICE_X140Y97 LUT3 (Prop_lut3_I2_O) 0.043 3.813 r ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40[83]_i_1__1/O net (fo=48, routed) 2.027 5.840 ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40 SLICE_X129Y60 FDCE r ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[74]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 8.200 8.200 r BUFHCE_X1Y13 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.574 8.774 ngFEC/SFP_GEN[6].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X129Y60 FDCE r ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[74]/C clock pessimism 0.000 8.774 clock uncertainty -0.035 8.739 SLICE_X129Y60 FDCE (Setup_fdce_C_CE) -0.201 8.538 ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[74] ------------------------------------------------------------------- required time 8.538 arrival time -5.840 ------------------------------------------------------------------- slack 2.697 Slack (MET) : 2.807ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[52]/CE (rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_2 rise@8.200ns - rxWordclkl8_2 rise@0.000ns) Data Path Delay: 5.065ns (logic 0.266ns (5.252%) route 4.799ns (94.748%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.115ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.574ns = ( 8.774 - 8.200 ) Source Clock Delay (SCD): 0.689ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.689 0.689 ngFEC/gbtbank4_l8_112/MGT_RXUSRCLK_o[2] SLICE_X153Y64 FDCE r ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C ------------------------------------------------------------------- ------------------- SLICE_X153Y64 FDCE (Prop_fdce_C_Q) 0.223 0.912 r ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/Q net (fo=127, routed) 2.858 3.770 ngFEC/SFP_GEN[6].ngCCM_gbt/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0] SLICE_X140Y97 LUT3 (Prop_lut3_I2_O) 0.043 3.813 r ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40[83]_i_1__1/O net (fo=48, routed) 1.941 5.754 ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40 SLICE_X130Y60 FDCE r ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[52]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 8.200 8.200 r BUFHCE_X1Y13 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.574 8.774 ngFEC/SFP_GEN[6].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X130Y60 FDCE r ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[52]/C clock pessimism 0.000 8.774 clock uncertainty -0.035 8.739 SLICE_X130Y60 FDCE (Setup_fdce_C_CE) -0.178 8.561 ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[52] ------------------------------------------------------------------- required time 8.561 arrival time -5.754 ------------------------------------------------------------------- slack 2.807 Slack (MET) : 2.807ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[54]/CE (rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_2 rise@8.200ns - rxWordclkl8_2 rise@0.000ns) Data Path Delay: 5.065ns (logic 0.266ns (5.252%) route 4.799ns (94.748%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.115ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.574ns = ( 8.774 - 8.200 ) Source Clock Delay (SCD): 0.689ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.689 0.689 ngFEC/gbtbank4_l8_112/MGT_RXUSRCLK_o[2] SLICE_X153Y64 FDCE r ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C ------------------------------------------------------------------- ------------------- SLICE_X153Y64 FDCE (Prop_fdce_C_Q) 0.223 0.912 r ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/Q net (fo=127, routed) 2.858 3.770 ngFEC/SFP_GEN[6].ngCCM_gbt/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0] SLICE_X140Y97 LUT3 (Prop_lut3_I2_O) 0.043 3.813 r ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40[83]_i_1__1/O net (fo=48, routed) 1.941 5.754 ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40 SLICE_X130Y60 FDCE r ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[54]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 8.200 8.200 r BUFHCE_X1Y13 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.574 8.774 ngFEC/SFP_GEN[6].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X130Y60 FDCE r ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[54]/C clock pessimism 0.000 8.774 clock uncertainty -0.035 8.739 SLICE_X130Y60 FDCE (Setup_fdce_C_CE) -0.178 8.561 ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[54] ------------------------------------------------------------------- required time 8.561 arrival time -5.754 ------------------------------------------------------------------- slack 2.807 Slack (MET) : 3.177ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[48]/CE (rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_2 rise@8.200ns - rxWordclkl8_2 rise@0.000ns) Data Path Delay: 4.750ns (logic 0.266ns (5.600%) route 4.484ns (94.400%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.059ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.630ns = ( 8.830 - 8.200 ) Source Clock Delay (SCD): 0.689ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.689 0.689 ngFEC/gbtbank4_l8_112/MGT_RXUSRCLK_o[2] SLICE_X153Y64 FDCE r ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C ------------------------------------------------------------------- ------------------- SLICE_X153Y64 FDCE (Prop_fdce_C_Q) 0.223 0.912 r ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/Q net (fo=127, routed) 2.858 3.770 ngFEC/SFP_GEN[6].ngCCM_gbt/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0] SLICE_X140Y97 LUT3 (Prop_lut3_I2_O) 0.043 3.813 r ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40[83]_i_1__1/O net (fo=48, routed) 1.626 5.439 ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40 SLICE_X134Y61 FDCE r ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[48]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 8.200 8.200 r BUFHCE_X1Y13 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.630 8.830 ngFEC/SFP_GEN[6].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X134Y61 FDCE r ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[48]/C clock pessimism 0.000 8.830 clock uncertainty -0.035 8.795 SLICE_X134Y61 FDCE (Setup_fdce_C_CE) -0.178 8.617 ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[48] ------------------------------------------------------------------- required time 8.617 arrival time -5.439 ------------------------------------------------------------------- slack 3.177 Slack (MET) : 3.177ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[50]/CE (rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_2 rise@8.200ns - rxWordclkl8_2 rise@0.000ns) Data Path Delay: 4.750ns (logic 0.266ns (5.600%) route 4.484ns (94.400%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.059ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.630ns = ( 8.830 - 8.200 ) Source Clock Delay (SCD): 0.689ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.689 0.689 ngFEC/gbtbank4_l8_112/MGT_RXUSRCLK_o[2] SLICE_X153Y64 FDCE r ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/C ------------------------------------------------------------------- ------------------- SLICE_X153Y64 FDCE (Prop_fdce_C_Q) 0.223 0.912 r ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/Q net (fo=127, routed) 2.858 3.770 ngFEC/SFP_GEN[6].ngCCM_gbt/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0] SLICE_X140Y97 LUT3 (Prop_lut3_I2_O) 0.043 3.813 r ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40[83]_i_1__1/O net (fo=48, routed) 1.626 5.439 ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40 SLICE_X134Y61 FDCE r ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[50]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 8.200 8.200 r BUFHCE_X1Y13 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.630 8.830 ngFEC/SFP_GEN[6].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X134Y61 FDCE r ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[50]/C clock pessimism 0.000 8.830 clock uncertainty -0.035 8.795 SLICE_X134Y61 FDCE (Setup_fdce_C_CE) -0.178 8.617 ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[50] ------------------------------------------------------------------- required time 8.617 arrival time -5.439 ------------------------------------------------------------------- slack 3.177 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.085ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[49]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[49]/D (rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_2 rise@0.000ns - rxWordclkl8_2 rise@0.000ns) Data Path Delay: 0.183ns (logic 0.128ns (70.125%) route 0.055ns (29.875%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.498ns Source Clock Delay (SCD): 0.343ns Clock Pessimism Removal (CPR): 0.144ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.343 0.343 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X143Y60 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[49]/C ------------------------------------------------------------------- ------------------- SLICE_X143Y60 FDCE (Prop_fdce_C_Q) 0.100 0.443 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[49]/Q net (fo=1, routed) 0.055 0.498 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[49] SLICE_X142Y60 LUT6 (Prop_lut6_I5_O) 0.028 0.526 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1[49]_i_1__8/O net (fo=1, routed) 0.000 0.526 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/p_0_out[49] SLICE_X142Y60 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[49]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.498 0.498 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X142Y60 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[49]/C clock pessimism -0.144 0.354 SLICE_X142Y60 FDCE (Hold_fdce_C_D) 0.087 0.441 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[49] ------------------------------------------------------------------- required time -0.441 arrival time 0.526 ------------------------------------------------------------------- slack 0.085 Slack (MET) : 0.085ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[54]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[54]/D (rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_2 rise@0.000ns - rxWordclkl8_2 rise@0.000ns) Data Path Delay: 0.183ns (logic 0.128ns (70.125%) route 0.055ns (29.875%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.497ns Source Clock Delay (SCD): 0.344ns Clock Pessimism Removal (CPR): 0.142ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.344 0.344 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X145Y63 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[54]/C ------------------------------------------------------------------- ------------------- SLICE_X145Y63 FDCE (Prop_fdce_C_Q) 0.100 0.444 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[54]/Q net (fo=1, routed) 0.055 0.499 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[54] SLICE_X144Y63 LUT6 (Prop_lut6_I5_O) 0.028 0.527 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1[54]_i_1__8/O net (fo=1, routed) 0.000 0.527 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/p_0_out[54] SLICE_X144Y63 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[54]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.497 0.497 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X144Y63 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[54]/C clock pessimism -0.142 0.355 SLICE_X144Y63 FDCE (Hold_fdce_C_D) 0.087 0.442 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[54] ------------------------------------------------------------------- required time -0.442 arrival time 0.527 ------------------------------------------------------------------- slack 0.085 Slack (MET) : 0.085ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[6]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[6]/D (rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_2 rise@0.000ns - rxWordclkl8_2 rise@0.000ns) Data Path Delay: 0.183ns (logic 0.128ns (70.125%) route 0.055ns (29.875%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.498ns Source Clock Delay (SCD): 0.343ns Clock Pessimism Removal (CPR): 0.144ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.343 0.343 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X141Y61 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X141Y61 FDCE (Prop_fdce_C_Q) 0.100 0.443 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[6]/Q net (fo=1, routed) 0.055 0.498 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[6] SLICE_X140Y61 LUT6 (Prop_lut6_I5_O) 0.028 0.526 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1[6]_i_1__8/O net (fo=1, routed) 0.000 0.526 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/p_0_out[6] SLICE_X140Y61 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[6]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.498 0.498 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X140Y61 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[6]/C clock pessimism -0.144 0.354 SLICE_X140Y61 FDCE (Hold_fdce_C_D) 0.087 0.441 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[6] ------------------------------------------------------------------- required time -0.441 arrival time 0.526 ------------------------------------------------------------------- slack 0.085 Slack (MET) : 0.093ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D (rising edge-triggered cell FDRE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_2 rise@0.000ns - rxWordclkl8_2 rise@0.000ns) Data Path Delay: 0.191ns (logic 0.128ns (66.970%) route 0.063ns (33.030%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.490ns Source Clock Delay (SCD): 0.336ns Clock Pessimism Removal (CPR): 0.143ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.336 0.336 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X133Y62 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X133Y62 FDCE (Prop_fdce_C_Q) 0.100 0.436 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[2]/Q net (fo=2, routed) 0.063 0.499 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_3_in SLICE_X132Y62 LUT3 (Prop_lut3_I0_O) 0.028 0.527 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[2]_i_1__8/O net (fo=1, routed) 0.000 0.527 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[2] SLICE_X132Y62 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.490 0.490 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X132Y62 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2]/C clock pessimism -0.143 0.347 SLICE_X132Y62 FDRE (Hold_fdre_C_D) 0.087 0.434 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[2] ------------------------------------------------------------------- required time -0.434 arrival time 0.527 ------------------------------------------------------------------- slack 0.093 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_2 rise@0.000ns - rxWordclkl8_2 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.532ns Source Clock Delay (SCD): 0.378ns Clock Pessimism Removal (CPR): 0.154ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.378 0.378 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in SLICE_X187Y68 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X187Y68 FDRE (Prop_fdre_C_Q) 0.100 0.478 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q net (fo=1, routed) 0.055 0.533 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync1 SLICE_X187Y68 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.532 0.532 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in SLICE_X187Y68 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C clock pessimism -0.154 0.378 SLICE_X187Y68 FDRE (Hold_fdre_C_D) 0.047 0.425 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.425 arrival time 0.533 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.111ns (arrival time - required time) Source: ngFEC/SFP_GEN[6].rx_data_reg[6][7]/C (rising edge-triggered cell FDRE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[6]/D (rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_2 rise@0.000ns - rxWordclkl8_2 rise@0.000ns) Data Path Delay: 0.209ns (logic 0.128ns (61.382%) route 0.081ns (38.618%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.492ns Source Clock Delay (SCD): 0.340ns Clock Pessimism Removal (CPR): 0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.340 0.340 ngFEC/clktest16_in SLICE_X137Y65 FDRE r ngFEC/SFP_GEN[6].rx_data_reg[6][7]/C ------------------------------------------------------------------- ------------------- SLICE_X137Y65 FDRE (Prop_fdre_C_Q) 0.100 0.440 r ngFEC/SFP_GEN[6].rx_data_reg[6][7]/Q net (fo=1, routed) 0.081 0.521 ngFEC/gbtbank4_l8_112/RX_Word_rx40_reg[78]_0[7] SLICE_X136Y65 LUT3 (Prop_lut3_I0_O) 0.028 0.549 r ngFEC/gbtbank4_l8_112/RX_Word_rx40[6]_i_1__4/O net (fo=1, routed) 0.000 0.549 ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[83]_0[3] SLICE_X136Y65 FDCE r ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[6]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.492 0.492 ngFEC/SFP_GEN[6].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X136Y65 FDCE r ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[6]/C clock pessimism -0.141 0.351 SLICE_X136Y65 FDCE (Hold_fdce_C_D) 0.087 0.438 ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Word_rx40_reg[6] ------------------------------------------------------------------- required time -0.438 arrival time 0.549 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.111ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[5]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[5]/D (rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_2 rise@0.000ns - rxWordclkl8_2 rise@0.000ns) Data Path Delay: 0.209ns (logic 0.128ns (61.382%) route 0.081ns (38.618%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.498ns Source Clock Delay (SCD): 0.343ns Clock Pessimism Removal (CPR): 0.144ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.343 0.343 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X141Y61 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X141Y61 FDCE (Prop_fdce_C_Q) 0.100 0.443 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[5]/Q net (fo=1, routed) 0.081 0.524 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[5] SLICE_X140Y61 LUT6 (Prop_lut6_I5_O) 0.028 0.552 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1[5]_i_1__8/O net (fo=1, routed) 0.000 0.552 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/p_0_out[5] SLICE_X140Y61 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[5]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.498 0.498 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X140Y61 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[5]/C clock pessimism -0.144 0.354 SLICE_X140Y61 FDCE (Hold_fdce_C_D) 0.087 0.441 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[5] ------------------------------------------------------------------- required time -0.441 arrival time 0.552 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.111ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D (rising edge-triggered cell FDRE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_2 rise@0.000ns - rxWordclkl8_2 rise@0.000ns) Data Path Delay: 0.209ns (logic 0.128ns (61.382%) route 0.081ns (38.618%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.499ns Source Clock Delay (SCD): 0.346ns Clock Pessimism Removal (CPR): 0.142ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.346 0.346 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X151Y66 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X151Y66 FDCE (Prop_fdce_C_Q) 0.100 0.446 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/Q net (fo=1, routed) 0.081 0.527 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg_n_0_[0] SLICE_X150Y66 LUT3 (Prop_lut3_I0_O) 0.028 0.555 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[0]_i_1__8/O net (fo=1, routed) 0.000 0.555 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[0] SLICE_X150Y66 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.499 0.499 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X150Y66 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0]/C clock pessimism -0.142 0.357 SLICE_X150Y66 FDRE (Hold_fdre_C_D) 0.087 0.444 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[0] ------------------------------------------------------------------- required time -0.444 arrival time 0.555 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.113ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[47]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[47]/D (rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_2 rise@0.000ns - rxWordclkl8_2 rise@0.000ns) Data Path Delay: 0.211ns (logic 0.128ns (60.799%) route 0.083ns (39.201%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.498ns Source Clock Delay (SCD): 0.345ns Clock Pessimism Removal (CPR): 0.142ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.345 0.345 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X147Y63 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[47]/C ------------------------------------------------------------------- ------------------- SLICE_X147Y63 FDCE (Prop_fdce_C_Q) 0.100 0.445 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[47]/Q net (fo=1, routed) 0.083 0.528 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[47] SLICE_X146Y63 LUT6 (Prop_lut6_I5_O) 0.028 0.556 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1[47]_i_1__8/O net (fo=1, routed) 0.000 0.556 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/p_0_out[47] SLICE_X146Y63 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[47]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.498 0.498 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X146Y63 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[47]/C clock pessimism -0.142 0.356 SLICE_X146Y63 FDCE (Hold_fdce_C_D) 0.087 0.443 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[47] ------------------------------------------------------------------- required time -0.443 arrival time 0.556 ------------------------------------------------------------------- slack 0.113 Slack (MET) : 0.113ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[42]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[42]/D (rising edge-triggered cell FDCE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_2 rise@0.000ns - rxWordclkl8_2 rise@0.000ns) Data Path Delay: 0.211ns (logic 0.128ns (60.799%) route 0.083ns (39.201%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.500ns Source Clock Delay (SCD): 0.346ns Clock Pessimism Removal (CPR): 0.143ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.346 0.346 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X145Y61 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[42]/C ------------------------------------------------------------------- ------------------- SLICE_X145Y61 FDCE (Prop_fdce_C_Q) 0.100 0.446 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[42]/Q net (fo=1, routed) 0.083 0.529 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0[42] SLICE_X144Y61 LUT6 (Prop_lut6_I5_O) 0.028 0.557 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1[42]_i_1__8/O net (fo=1, routed) 0.000 0.557 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/p_0_out[42] SLICE_X144Y61 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[42]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.500 0.500 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X144Y61 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[42]/C clock pessimism -0.143 0.357 SLICE_X144Y61 FDCE (Hold_fdce_C_D) 0.087 0.444 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[42] ------------------------------------------------------------------- required time -0.444 arrival time 0.557 ------------------------------------------------------------------- slack 0.113 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: rxWordclkl8_2 Waveform(ns): { 0.000 4.100 } Period(ns): 8.200 Sources: { ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/RXUSRCLK n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y5 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK Min Period n/a GTXE2_CHANNEL/RXUSRCLK2 n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y5 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X154Y65 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X154Y65 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/RX_HEADER_LOCKED_O_reg/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X156Y66 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[3]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X156Y66 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[4]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X151Y65 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/consecCorrectHeaders_reg[1]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X151Y65 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/consecCorrectHeaders_reg[3]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X156Y64 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/consecFalseHeaders_reg[2]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X155Y66 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/nbCheckedHeaders_reg[3]/C Low Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X140Y86 ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK Low Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X140Y86 ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X154Y65 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X154Y65 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/RX_HEADER_LOCKED_O_reg/C Low Pulse Width Fast FDRE/C n/a 0.400 4.100 3.700 SLICE_X151Y65 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/consecCorrectHeaders_reg[1]/C Low Pulse Width Fast FDRE/C n/a 0.400 4.100 3.700 SLICE_X151Y65 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/consecCorrectHeaders_reg[3]/C Low Pulse Width Fast FDRE/C n/a 0.400 4.100 3.700 SLICE_X151Y64 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/nbCheckedHeaders_reg[6]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X153Y65 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[0]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X153Y65 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[2]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X154Y65 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/FSM_onehot_state_reg[2]/C High Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X140Y86 ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X140Y86 ngFEC/SFP_GEN[6].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X188Y66 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/wait_bypass_count_reg[0]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X188Y66 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/wait_bypass_count_reg[1]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X188Y66 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/wait_bypass_count_reg[2]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X188Y66 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/wait_bypass_count_reg[3]/C High Pulse Width Fast FDRE/C n/a 0.350 4.100 3.750 SLICE_X132Y60 ngFEC/SFP_GEN[6].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[2]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X144Y74 ngFEC/SFP_GEN[6].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[36]/C High Pulse Width Fast FDRE/C n/a 0.350 4.100 3.750 SLICE_X132Y60 ngFEC/SFP_GEN[6].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[48]/C High Pulse Width Fast FDRE/C n/a 0.350 4.100 3.750 SLICE_X132Y60 ngFEC/SFP_GEN[6].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[4]/C --------------------------------------------------------------------------------------------------- From Clock: rxWordclkl8_3 To Clock: rxWordclkl8_3 Setup : 0 Failing Endpoints, Worst Slack 3.589ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.086ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.458ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.589ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[24]/D (rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_3 rise@8.200ns - rxWordclkl8_3 rise@0.000ns) Data Path Delay: 4.199ns (logic 1.208ns (28.768%) route 2.991ns (71.232%)) Logic Levels: 2 (LUT4=2) Clock Path Skew: -0.277ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.638ns = ( 8.838 - 8.200 ) Source Clock Delay (SCD): 0.915ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.915 0.915 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y6 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y6 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[4]) 1.009 1.924 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[4] net (fo=6, routed) 1.775 3.700 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19]_0[4] SLICE_X163Y77 LUT4 (Prop_lut4_I0_O) 0.051 3.751 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[96]_i_3__9/O net (fo=6, routed) 0.711 4.462 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[96]_i_3__9_n_0 SLICE_X159Y75 LUT4 (Prop_lut4_I1_O) 0.148 4.610 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[24]_i_1__9/O net (fo=1, routed) 0.505 5.115 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_1[20] SLICE_X161Y79 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[24]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 8.200 8.200 r BUFHCE_X1Y14 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.638 8.838 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X161Y79 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[24]/C clock pessimism 0.000 8.838 clock uncertainty -0.035 8.803 SLICE_X161Y79 FDCE (Setup_fdce_C_D) -0.099 8.704 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[24] ------------------------------------------------------------------- required time 8.704 arrival time -5.115 ------------------------------------------------------------------- slack 3.589 Slack (MET) : 3.718ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[56]/D (rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_3 rise@8.200ns - rxWordclkl8_3 rise@0.000ns) Data Path Delay: 4.064ns (logic 1.202ns (29.575%) route 2.862ns (70.425%)) Logic Levels: 2 (LUT4=2) Clock Path Skew: -0.282ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.633ns = ( 8.833 - 8.200 ) Source Clock Delay (SCD): 0.915ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.915 0.915 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y6 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y6 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[4]) 1.009 1.924 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[4] net (fo=6, routed) 1.775 3.700 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19]_0[4] SLICE_X163Y77 LUT4 (Prop_lut4_I0_O) 0.051 3.751 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[96]_i_3__9/O net (fo=6, routed) 0.649 4.400 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[96]_i_3__9_n_0 SLICE_X159Y76 LUT4 (Prop_lut4_I1_O) 0.142 4.542 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[56]_i_1__9/O net (fo=1, routed) 0.438 4.980 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_1[52] SLICE_X155Y76 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[56]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 8.200 8.200 r BUFHCE_X1Y14 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.633 8.833 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X155Y76 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[56]/C clock pessimism 0.000 8.833 clock uncertainty -0.035 8.798 SLICE_X155Y76 FDCE (Setup_fdce_C_D) -0.100 8.698 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[56] ------------------------------------------------------------------- required time 8.698 arrival time -4.980 ------------------------------------------------------------------- slack 3.718 Slack (MET) : 3.744ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[28]/CE (rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_3 rise@8.200ns - rxWordclkl8_3 rise@0.000ns) Data Path Delay: 4.101ns (logic 0.828ns (20.190%) route 3.273ns (79.810%)) Logic Levels: 4 (CARRY4=1 LUT4=1 LUT5=2) Clock Path Skew: -0.049ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.685ns = ( 8.885 - 8.200 ) Source Clock Delay (SCD): 0.734ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.734 0.734 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK SLICE_X171Y80 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X171Y80 FDCE (Prop_fdce_C_Q) 0.223 0.957 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/Q net (fo=16, routed) 0.817 1.774 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg_0 SLICE_X163Y78 LUT4 (Prop_lut4_I0_O) 0.051 1.825 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[99]_i_14__9/O net (fo=3, routed) 0.310 2.135 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[99]_i_14__9_n_0 SLICE_X163Y78 CARRY4 (Prop_carry4_DI[1]_O[3]) 0.383 2.518 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[99]_i_3__9/O[3] net (fo=11, routed) 0.896 3.414 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg01[3] SLICE_X167Y74 LUT5 (Prop_lut5_I4_O) 0.120 3.534 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[39]_i_3__9/O net (fo=5, routed) 0.654 4.189 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[35] SLICE_X159Y75 LUT5 (Prop_lut5_I2_O) 0.051 4.240 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[31]_i_1__9/O net (fo=4, routed) 0.596 4.835 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_0[6] SLICE_X166Y79 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[28]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 8.200 8.200 r BUFHCE_X1Y14 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.685 8.885 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X166Y79 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[28]/C clock pessimism 0.000 8.885 clock uncertainty -0.035 8.850 SLICE_X166Y79 FDCE (Setup_fdce_C_CE) -0.271 8.579 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[28] ------------------------------------------------------------------- required time 8.579 arrival time -4.835 ------------------------------------------------------------------- slack 3.744 Slack (MET) : 3.744ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[31]/CE (rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_3 rise@8.200ns - rxWordclkl8_3 rise@0.000ns) Data Path Delay: 4.101ns (logic 0.828ns (20.190%) route 3.273ns (79.810%)) Logic Levels: 4 (CARRY4=1 LUT4=1 LUT5=2) Clock Path Skew: -0.049ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.685ns = ( 8.885 - 8.200 ) Source Clock Delay (SCD): 0.734ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.734 0.734 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK SLICE_X171Y80 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X171Y80 FDCE (Prop_fdce_C_Q) 0.223 0.957 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/Q net (fo=16, routed) 0.817 1.774 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg_0 SLICE_X163Y78 LUT4 (Prop_lut4_I0_O) 0.051 1.825 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[99]_i_14__9/O net (fo=3, routed) 0.310 2.135 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[99]_i_14__9_n_0 SLICE_X163Y78 CARRY4 (Prop_carry4_DI[1]_O[3]) 0.383 2.518 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[99]_i_3__9/O[3] net (fo=11, routed) 0.896 3.414 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg01[3] SLICE_X167Y74 LUT5 (Prop_lut5_I4_O) 0.120 3.534 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[39]_i_3__9/O net (fo=5, routed) 0.654 4.189 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[35] SLICE_X159Y75 LUT5 (Prop_lut5_I2_O) 0.051 4.240 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[31]_i_1__9/O net (fo=4, routed) 0.596 4.835 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_0[6] SLICE_X166Y79 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[31]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 8.200 8.200 r BUFHCE_X1Y14 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.685 8.885 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X166Y79 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[31]/C clock pessimism 0.000 8.885 clock uncertainty -0.035 8.850 SLICE_X166Y79 FDCE (Setup_fdce_C_CE) -0.271 8.579 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[31] ------------------------------------------------------------------- required time 8.579 arrival time -4.835 ------------------------------------------------------------------- slack 3.744 Slack (MET) : 3.796ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[56]/CE (rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_3 rise@8.200ns - rxWordclkl8_3 rise@0.000ns) Data Path Delay: 3.971ns (logic 0.936ns (23.570%) route 3.035ns (76.430%)) Logic Levels: 5 (CARRY4=2 LUT4=1 LUT5=1 LUT6=1) Clock Path Skew: -0.101ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.633ns = ( 8.833 - 8.200 ) Source Clock Delay (SCD): 0.734ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.734 0.734 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK SLICE_X171Y80 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X171Y80 FDCE (Prop_fdce_C_Q) 0.223 0.957 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/Q net (fo=16, routed) 0.817 1.774 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg_0 SLICE_X163Y78 LUT4 (Prop_lut4_I0_O) 0.051 1.825 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[99]_i_14__9/O net (fo=3, routed) 0.310 2.135 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[99]_i_14__9_n_0 SLICE_X163Y78 CARRY4 (Prop_carry4_DI[1]_CO[3]) 0.342 2.477 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[99]_i_3__9/CO[3] net (fo=1, routed) 0.000 2.477 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[99]_i_3__9_n_0 SLICE_X163Y79 CARRY4 (Prop_carry4_CI_O[3]) 0.149 2.626 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[15]_i_4__9/O[3] net (fo=11, routed) 0.852 3.478 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg01[7] SLICE_X168Y74 LUT6 (Prop_lut6_I1_O) 0.120 3.598 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[67]_i_3__9/O net (fo=41, routed) 0.532 4.129 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[35]_0 SLICE_X164Y76 LUT5 (Prop_lut5_I2_O) 0.051 4.180 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[59]_i_1__9/O net (fo=4, routed) 0.525 4.705 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_0[13] SLICE_X155Y76 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[56]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 8.200 8.200 r BUFHCE_X1Y14 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.633 8.833 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X155Y76 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[56]/C clock pessimism 0.000 8.833 clock uncertainty -0.035 8.798 SLICE_X155Y76 FDCE (Setup_fdce_C_CE) -0.296 8.502 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[56] ------------------------------------------------------------------- required time 8.502 arrival time -4.705 ------------------------------------------------------------------- slack 3.796 Slack (MET) : 3.796ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[57]/CE (rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_3 rise@8.200ns - rxWordclkl8_3 rise@0.000ns) Data Path Delay: 3.971ns (logic 0.936ns (23.570%) route 3.035ns (76.430%)) Logic Levels: 5 (CARRY4=2 LUT4=1 LUT5=1 LUT6=1) Clock Path Skew: -0.101ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.633ns = ( 8.833 - 8.200 ) Source Clock Delay (SCD): 0.734ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.734 0.734 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK SLICE_X171Y80 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X171Y80 FDCE (Prop_fdce_C_Q) 0.223 0.957 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/Q net (fo=16, routed) 0.817 1.774 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg_0 SLICE_X163Y78 LUT4 (Prop_lut4_I0_O) 0.051 1.825 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[99]_i_14__9/O net (fo=3, routed) 0.310 2.135 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[99]_i_14__9_n_0 SLICE_X163Y78 CARRY4 (Prop_carry4_DI[1]_CO[3]) 0.342 2.477 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[99]_i_3__9/CO[3] net (fo=1, routed) 0.000 2.477 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[99]_i_3__9_n_0 SLICE_X163Y79 CARRY4 (Prop_carry4_CI_O[3]) 0.149 2.626 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[15]_i_4__9/O[3] net (fo=11, routed) 0.852 3.478 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg01[7] SLICE_X168Y74 LUT6 (Prop_lut6_I1_O) 0.120 3.598 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[67]_i_3__9/O net (fo=41, routed) 0.532 4.129 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[35]_0 SLICE_X164Y76 LUT5 (Prop_lut5_I2_O) 0.051 4.180 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[59]_i_1__9/O net (fo=4, routed) 0.525 4.705 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_0[13] SLICE_X155Y76 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[57]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 8.200 8.200 r BUFHCE_X1Y14 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.633 8.833 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X155Y76 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[57]/C clock pessimism 0.000 8.833 clock uncertainty -0.035 8.798 SLICE_X155Y76 FDCE (Setup_fdce_C_CE) -0.296 8.502 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[57] ------------------------------------------------------------------- required time 8.502 arrival time -4.705 ------------------------------------------------------------------- slack 3.796 Slack (MET) : 3.796ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[58]/CE (rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_3 rise@8.200ns - rxWordclkl8_3 rise@0.000ns) Data Path Delay: 3.971ns (logic 0.936ns (23.570%) route 3.035ns (76.430%)) Logic Levels: 5 (CARRY4=2 LUT4=1 LUT5=1 LUT6=1) Clock Path Skew: -0.101ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.633ns = ( 8.833 - 8.200 ) Source Clock Delay (SCD): 0.734ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.734 0.734 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK SLICE_X171Y80 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X171Y80 FDCE (Prop_fdce_C_Q) 0.223 0.957 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/Q net (fo=16, routed) 0.817 1.774 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg_0 SLICE_X163Y78 LUT4 (Prop_lut4_I0_O) 0.051 1.825 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[99]_i_14__9/O net (fo=3, routed) 0.310 2.135 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[99]_i_14__9_n_0 SLICE_X163Y78 CARRY4 (Prop_carry4_DI[1]_CO[3]) 0.342 2.477 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[99]_i_3__9/CO[3] net (fo=1, routed) 0.000 2.477 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[99]_i_3__9_n_0 SLICE_X163Y79 CARRY4 (Prop_carry4_CI_O[3]) 0.149 2.626 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[15]_i_4__9/O[3] net (fo=11, routed) 0.852 3.478 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg01[7] SLICE_X168Y74 LUT6 (Prop_lut6_I1_O) 0.120 3.598 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[67]_i_3__9/O net (fo=41, routed) 0.532 4.129 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[35]_0 SLICE_X164Y76 LUT5 (Prop_lut5_I2_O) 0.051 4.180 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[59]_i_1__9/O net (fo=4, routed) 0.525 4.705 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_0[13] SLICE_X155Y76 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[58]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 8.200 8.200 r BUFHCE_X1Y14 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.633 8.833 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X155Y76 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[58]/C clock pessimism 0.000 8.833 clock uncertainty -0.035 8.798 SLICE_X155Y76 FDCE (Setup_fdce_C_CE) -0.296 8.502 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[58] ------------------------------------------------------------------- required time 8.502 arrival time -4.705 ------------------------------------------------------------------- slack 3.796 Slack (MET) : 3.796ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[59]/CE (rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_3 rise@8.200ns - rxWordclkl8_3 rise@0.000ns) Data Path Delay: 3.971ns (logic 0.936ns (23.570%) route 3.035ns (76.430%)) Logic Levels: 5 (CARRY4=2 LUT4=1 LUT5=1 LUT6=1) Clock Path Skew: -0.101ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.633ns = ( 8.833 - 8.200 ) Source Clock Delay (SCD): 0.734ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.734 0.734 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK SLICE_X171Y80 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X171Y80 FDCE (Prop_fdce_C_Q) 0.223 0.957 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/Q net (fo=16, routed) 0.817 1.774 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg_0 SLICE_X163Y78 LUT4 (Prop_lut4_I0_O) 0.051 1.825 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[99]_i_14__9/O net (fo=3, routed) 0.310 2.135 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[99]_i_14__9_n_0 SLICE_X163Y78 CARRY4 (Prop_carry4_DI[1]_CO[3]) 0.342 2.477 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[99]_i_3__9/CO[3] net (fo=1, routed) 0.000 2.477 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[99]_i_3__9_n_0 SLICE_X163Y79 CARRY4 (Prop_carry4_CI_O[3]) 0.149 2.626 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[15]_i_4__9/O[3] net (fo=11, routed) 0.852 3.478 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg01[7] SLICE_X168Y74 LUT6 (Prop_lut6_I1_O) 0.120 3.598 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[67]_i_3__9/O net (fo=41, routed) 0.532 4.129 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[35]_0 SLICE_X164Y76 LUT5 (Prop_lut5_I2_O) 0.051 4.180 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[59]_i_1__9/O net (fo=4, routed) 0.525 4.705 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_0[13] SLICE_X155Y76 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[59]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 8.200 8.200 r BUFHCE_X1Y14 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.633 8.833 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X155Y76 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[59]/C clock pessimism 0.000 8.833 clock uncertainty -0.035 8.798 SLICE_X155Y76 FDCE (Setup_fdce_C_CE) -0.296 8.502 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[59] ------------------------------------------------------------------- required time 8.502 arrival time -4.705 ------------------------------------------------------------------- slack 3.796 Slack (MET) : 3.828ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[59]/D (rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_3 rise@8.200ns - rxWordclkl8_3 rise@0.000ns) Data Path Delay: 3.952ns (logic 1.200ns (30.361%) route 2.752ns (69.639%)) Logic Levels: 2 (LUT4=2) Clock Path Skew: -0.282ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.633ns = ( 8.833 - 8.200 ) Source Clock Delay (SCD): 0.915ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.915 0.915 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y6 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y6 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[9]) 1.009 1.924 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[9] net (fo=5, routed) 1.581 3.505 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19]_0[11] SLICE_X162Y77 LUT4 (Prop_lut4_I1_O) 0.047 3.552 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[99]_i_9__9/O net (fo=6, routed) 0.646 4.198 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[99]_i_9__9_n_0 SLICE_X159Y76 LUT4 (Prop_lut4_I1_O) 0.144 4.342 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[59]_i_2__9/O net (fo=1, routed) 0.526 4.868 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_1[55] SLICE_X155Y76 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[59]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 8.200 8.200 r BUFHCE_X1Y14 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.633 8.833 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X155Y76 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[59]/C clock pessimism 0.000 8.833 clock uncertainty -0.035 8.798 SLICE_X155Y76 FDCE (Setup_fdce_C_D) -0.102 8.696 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[59] ------------------------------------------------------------------- required time 8.696 arrival time -4.868 ------------------------------------------------------------------- slack 3.828 Slack (MET) : 3.830ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[24]/CE (rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_3 rise@8.200ns - rxWordclkl8_3 rise@0.000ns) Data Path Delay: 3.947ns (logic 0.956ns (24.221%) route 2.991ns (75.779%)) Logic Levels: 5 (CARRY4=2 LUT4=1 LUT5=1 LUT6=1) Clock Path Skew: -0.096ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.638ns = ( 8.838 - 8.200 ) Source Clock Delay (SCD): 0.734ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.734 0.734 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK SLICE_X171Y80 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X171Y80 FDCE (Prop_fdce_C_Q) 0.223 0.957 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/Q net (fo=16, routed) 0.817 1.774 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg_0 SLICE_X163Y78 LUT4 (Prop_lut4_I0_O) 0.051 1.825 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[99]_i_14__9/O net (fo=3, routed) 0.310 2.135 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[99]_i_14__9_n_0 SLICE_X163Y78 CARRY4 (Prop_carry4_DI[1]_CO[3]) 0.342 2.477 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[99]_i_3__9/CO[3] net (fo=1, routed) 0.000 2.477 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[99]_i_3__9_n_0 SLICE_X163Y79 CARRY4 (Prop_carry4_CI_O[1]) 0.166 2.643 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[15]_i_4__9/O[1] net (fo=11, routed) 0.604 3.248 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg01[5] SLICE_X168Y78 LUT6 (Prop_lut6_I2_O) 0.123 3.371 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[47]_i_3__9/O net (fo=41, routed) 0.742 4.112 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0_reg[43] SLICE_X160Y78 LUT5 (Prop_lut5_I0_O) 0.051 4.163 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/reg0[27]_i_1__9/O net (fo=4, routed) 0.518 4.681 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[99]_0[5] SLICE_X161Y79 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[24]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 8.200 8.200 r BUFHCE_X1Y14 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.638 8.838 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X161Y79 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[24]/C clock pessimism 0.000 8.838 clock uncertainty -0.035 8.803 SLICE_X161Y79 FDCE (Setup_fdce_C_CE) -0.292 8.511 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[24] ------------------------------------------------------------------- required time 8.511 arrival time -4.681 ------------------------------------------------------------------- slack 3.830 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.086ns (arrival time - required time) Source: ngFEC/SFP_GEN[7].rx_data_reg[7][33]/C (rising edge-triggered cell FDRE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[32]/D (rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_3 rise@0.000ns - rxWordclkl8_3 rise@0.000ns) Data Path Delay: 0.184ns (logic 0.128ns (69.743%) route 0.056ns (30.257%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.528ns Source Clock Delay (SCD): 0.375ns Clock Pessimism Removal (CPR): 0.142ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.375 0.375 ngFEC/clktest15_in SLICE_X167Y83 FDRE r ngFEC/SFP_GEN[7].rx_data_reg[7][33]/C ------------------------------------------------------------------- ------------------- SLICE_X167Y83 FDRE (Prop_fdre_C_Q) 0.100 0.475 r ngFEC/SFP_GEN[7].rx_data_reg[7][33]/Q net (fo=1, routed) 0.056 0.531 ngFEC/gbtbank4_l8_112/RX_Word_rx40_reg[78][17] SLICE_X166Y83 LUT3 (Prop_lut3_I0_O) 0.028 0.559 r ngFEC/gbtbank4_l8_112/RX_Word_rx40[32]_i_1__3/O net (fo=1, routed) 0.000 0.559 ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[83]_0[24] SLICE_X166Y83 FDCE r ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[32]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.528 0.528 ngFEC/SFP_GEN[7].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X166Y83 FDCE r ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[32]/C clock pessimism -0.142 0.386 SLICE_X166Y83 FDCE (Hold_fdce_C_D) 0.087 0.473 ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[32] ------------------------------------------------------------------- required time -0.473 arrival time 0.559 ------------------------------------------------------------------- slack 0.086 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_3 rise@0.000ns - rxWordclkl8_3 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.531ns Source Clock Delay (SCD): 0.377ns Clock Pessimism Removal (CPR): 0.154ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.377 0.377 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in SLICE_X185Y80 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X185Y80 FDRE (Prop_fdre_C_Q) 0.100 0.477 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q net (fo=1, routed) 0.055 0.532 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync1 SLICE_X185Y80 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.531 0.531 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in SLICE_X185Y80 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C clock pessimism -0.154 0.377 SLICE_X185Y80 FDRE (Hold_fdre_C_D) 0.047 0.424 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.424 arrival time 0.532 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_3 rise@0.000ns - rxWordclkl8_3 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.530ns Source Clock Delay (SCD): 0.376ns Clock Pessimism Removal (CPR): 0.154ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.376 0.376 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/gt0_rxusrclk_in SLICE_X185Y79 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X185Y79 FDRE (Prop_fdre_C_Q) 0.100 0.476 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/Q net (fo=1, routed) 0.055 0.531 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync1 SLICE_X185Y79 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.530 0.530 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/gt0_rxusrclk_in SLICE_X185Y79 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/C clock pessimism -0.154 0.376 SLICE_X185Y79 FDRE (Hold_fdre_C_D) 0.047 0.423 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.423 arrival time 0.531 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.111ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[44]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[44]/D (rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_3 rise@0.000ns - rxWordclkl8_3 rise@0.000ns) Data Path Delay: 0.209ns (logic 0.128ns (61.382%) route 0.081ns (38.618%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.495ns Source Clock Delay (SCD): 0.343ns Clock Pessimism Removal (CPR): 0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.343 0.343 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X165Y77 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[44]/C ------------------------------------------------------------------- ------------------- SLICE_X165Y77 FDCE (Prop_fdce_C_Q) 0.100 0.443 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[44]/Q net (fo=1, routed) 0.081 0.524 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[44] SLICE_X164Y77 LUT6 (Prop_lut6_I5_O) 0.028 0.552 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1[44]_i_1__9/O net (fo=1, routed) 0.000 0.552 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/p_0_out[44] SLICE_X164Y77 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[44]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.495 0.495 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X164Y77 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[44]/C clock pessimism -0.141 0.354 SLICE_X164Y77 FDCE (Hold_fdce_C_D) 0.087 0.441 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[44] ------------------------------------------------------------------- required time -0.441 arrival time 0.552 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.111ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[20]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[20]/D (rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_3 rise@0.000ns - rxWordclkl8_3 rise@0.000ns) Data Path Delay: 0.209ns (logic 0.128ns (61.382%) route 0.081ns (38.618%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.525ns Source Clock Delay (SCD): 0.372ns Clock Pessimism Removal (CPR): 0.142ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.372 0.372 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X167Y80 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X167Y80 FDCE (Prop_fdce_C_Q) 0.100 0.472 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[20]/Q net (fo=1, routed) 0.081 0.553 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[20] SLICE_X166Y80 LUT6 (Prop_lut6_I5_O) 0.028 0.581 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1[20]_i_1__9/O net (fo=1, routed) 0.000 0.581 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/p_0_out[20] SLICE_X166Y80 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[20]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.525 0.525 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X166Y80 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[20]/C clock pessimism -0.142 0.383 SLICE_X166Y80 FDCE (Hold_fdce_C_D) 0.087 0.470 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[20] ------------------------------------------------------------------- required time -0.470 arrival time 0.581 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.111ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[4]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[4]/D (rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_3 rise@0.000ns - rxWordclkl8_3 rise@0.000ns) Data Path Delay: 0.209ns (logic 0.128ns (61.382%) route 0.081ns (38.618%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.523ns Source Clock Delay (SCD): 0.370ns Clock Pessimism Removal (CPR): 0.142ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.370 0.370 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X171Y77 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X171Y77 FDCE (Prop_fdce_C_Q) 0.100 0.470 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[4]/Q net (fo=1, routed) 0.081 0.551 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[4] SLICE_X170Y77 LUT6 (Prop_lut6_I5_O) 0.028 0.579 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1[4]_i_1__9/O net (fo=1, routed) 0.000 0.579 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/p_0_out[4] SLICE_X170Y77 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[4]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.523 0.523 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X170Y77 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[4]/C clock pessimism -0.142 0.381 SLICE_X170Y77 FDCE (Hold_fdce_C_D) 0.087 0.468 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[4] ------------------------------------------------------------------- required time -0.468 arrival time 0.579 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.114ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[15]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[15]/D (rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_3 rise@0.000ns - rxWordclkl8_3 rise@0.000ns) Data Path Delay: 0.185ns (logic 0.128ns (69.375%) route 0.057ns (30.625%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.525ns Source Clock Delay (SCD): 0.372ns Clock Pessimism Removal (CPR): 0.142ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.372 0.372 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X169Y79 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X169Y79 FDCE (Prop_fdce_C_Q) 0.100 0.472 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[15]/Q net (fo=1, routed) 0.057 0.529 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0[15] SLICE_X168Y79 LUT6 (Prop_lut6_I5_O) 0.028 0.557 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1[15]_i_1__9/O net (fo=1, routed) 0.000 0.557 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/p_0_out[15] SLICE_X168Y79 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[15]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.525 0.525 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X168Y79 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[15]/C clock pessimism -0.142 0.383 SLICE_X168Y79 FDCE (Hold_fdce_C_D) 0.060 0.443 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[15] ------------------------------------------------------------------- required time -0.443 arrival time 0.557 ------------------------------------------------------------------- slack 0.114 Slack (MET) : 0.118ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/D (rising edge-triggered cell FDRE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_3 rise@0.000ns - rxWordclkl8_3 rise@0.000ns) Data Path Delay: 0.216ns (logic 0.128ns (59.307%) route 0.088ns (40.693%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.499ns Source Clock Delay (SCD): 0.346ns Clock Pessimism Removal (CPR): 0.142ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.346 0.346 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X161Y81 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X161Y81 FDCE (Prop_fdce_C_Q) 0.100 0.446 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[7]/Q net (fo=2, routed) 0.088 0.534 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_13_in SLICE_X160Y81 LUT3 (Prop_lut3_I0_O) 0.028 0.562 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[7]_i_1__9/O net (fo=1, routed) 0.000 0.562 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[7] SLICE_X160Y81 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.499 0.499 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X160Y81 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7]/C clock pessimism -0.142 0.357 SLICE_X160Y81 FDRE (Hold_fdre_C_D) 0.087 0.444 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[7] ------------------------------------------------------------------- required time -0.444 arrival time 0.562 ------------------------------------------------------------------- slack 0.118 Slack (MET) : 0.118ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D (rising edge-triggered cell FDRE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_3 rise@0.000ns - rxWordclkl8_3 rise@0.000ns) Data Path Delay: 0.216ns (logic 0.128ns (59.223%) route 0.088ns (40.777%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.495ns Source Clock Delay (SCD): 0.342ns Clock Pessimism Removal (CPR): 0.142ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.342 0.342 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X151Y79 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X151Y79 FDCE (Prop_fdce_C_Q) 0.100 0.442 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[12]/Q net (fo=2, routed) 0.088 0.530 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_23_in SLICE_X150Y79 LUT3 (Prop_lut3_I0_O) 0.028 0.558 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O[12]_i_1__9/O net (fo=1, routed) 0.000 0.558 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/p_40_out[12] SLICE_X150Y79 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.495 0.495 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X150Y79 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12]/C clock pessimism -0.142 0.353 SLICE_X150Y79 FDRE (Hold_fdre_C_D) 0.087 0.440 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[3].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/RX_DATA_O_reg[12] ------------------------------------------------------------------- required time -0.440 arrival time 0.558 ------------------------------------------------------------------- slack 0.118 Slack (MET) : 0.118ns (arrival time - required time) Source: ngFEC/SFP_GEN[7].ngCCM_gbt/ngCCM_status_counter_reg[1][13]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[7].ngCCM_gbt/ngCCM_status_counter_o_reg[1][13]/D (rising edge-triggered cell FDRE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_3 rise@0.000ns - rxWordclkl8_3 rise@0.000ns) Data Path Delay: 0.161ns (logic 0.100ns (61.933%) route 0.061ns (38.067%)) Logic Levels: 0 Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.505ns Source Clock Delay (SCD): 0.351ns Clock Pessimism Removal (CPR): 0.143ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.351 0.351 ngFEC/SFP_GEN[7].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X156Y89 FDCE r ngFEC/SFP_GEN[7].ngCCM_gbt/ngCCM_status_counter_reg[1][13]/C ------------------------------------------------------------------- ------------------- SLICE_X156Y89 FDCE (Prop_fdce_C_Q) 0.100 0.451 r ngFEC/SFP_GEN[7].ngCCM_gbt/ngCCM_status_counter_reg[1][13]/Q net (fo=2, routed) 0.061 0.512 ngFEC/SFP_GEN[7].ngCCM_gbt/ngCCM_status_counter_reg[1]__0[13] SLICE_X157Y89 FDRE r ngFEC/SFP_GEN[7].ngCCM_gbt/ngCCM_status_counter_o_reg[1][13]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.505 0.505 ngFEC/SFP_GEN[7].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X157Y89 FDRE r ngFEC/SFP_GEN[7].ngCCM_gbt/ngCCM_status_counter_o_reg[1][13]/C clock pessimism -0.143 0.362 SLICE_X157Y89 FDRE (Hold_fdre_C_D) 0.032 0.394 ngFEC/SFP_GEN[7].ngCCM_gbt/ngCCM_status_counter_o_reg[1][13] ------------------------------------------------------------------- required time -0.394 arrival time 0.512 ------------------------------------------------------------------- slack 0.118 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: rxWordclkl8_3 Waveform(ns): { 0.000 4.100 } Period(ns): 8.200 Sources: { ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/RXUSRCLK n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y6 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK Min Period n/a GTXE2_CHANNEL/RXUSRCLK2 n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y6 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X172Y80 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[1]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X171Y82 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/RX_HEADER_LOCKED_O_reg/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X176Y80 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[3]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X176Y80 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[4]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X172Y85 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/consecCorrectHeaders_reg[1]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X172Y85 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/consecCorrectHeaders_reg[3]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X173Y81 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/consecFalseHeaders_reg[2]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X170Y81 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[3]/C Low Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X164Y87 ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK Low Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X164Y87 ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X172Y80 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[1]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X171Y82 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/RX_HEADER_LOCKED_O_reg/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X176Y80 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[3]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X176Y80 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[4]/C Low Pulse Width Slow FDRE/C n/a 0.400 4.100 3.700 SLICE_X173Y81 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/consecFalseHeaders_reg[2]/C Low Pulse Width Fast FDRE/C n/a 0.400 4.100 3.700 SLICE_X173Y81 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/consecFalseHeaders_reg[2]/C Low Pulse Width Slow FDRE/C n/a 0.400 4.100 3.700 SLICE_X170Y81 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[3]/C Low Pulse Width Slow FDRE/C n/a 0.400 4.100 3.700 SLICE_X171Y79 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/nbCheckedHeaders_reg[6]/C High Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X164Y87 ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X164Y87 ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X139Y78 ngFEC/SFP_GEN[7].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[56]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X139Y78 ngFEC/SFP_GEN[7].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[62]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X139Y78 ngFEC/SFP_GEN[7].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[66]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X139Y78 ngFEC/SFP_GEN[7].ngCCM_gbt/CrossClock_DV_cnt/DataAtoB_reg_reg[70]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X162Y85 ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[26]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X162Y85 ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[29]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X162Y85 ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[30]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X162Y85 ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[31]/C --------------------------------------------------------------------------------------------------- From Clock: rxWordclkl8_4 To Clock: rxWordclkl8_4 Setup : 0 Failing Endpoints, Worst Slack 3.827ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.106ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.458ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.827ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[90]/D (rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_4 rise@8.200ns - rxWordclkl8_4 rise@0.000ns) Data Path Delay: 3.998ns (logic 1.199ns (29.987%) route 2.799ns (70.013%)) Logic Levels: 2 (LUT4=2) Clock Path Skew: -0.227ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.695ns = ( 8.895 - 8.200 ) Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.922 0.922 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y7 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y7 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[6]) 1.009 1.931 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[6] net (fo=6, routed) 1.388 3.319 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19]_1[6] SLICE_X173Y93 LUT4 (Prop_lut4_I0_O) 0.050 3.369 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[98]_i_3__10/O net (fo=6, routed) 1.075 4.444 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[98]_i_3__10_n_0 SLICE_X173Y87 LUT4 (Prop_lut4_I1_O) 0.140 4.584 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[90]_i_1__10/O net (fo=1, routed) 0.337 4.921 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[99]_1[86] SLICE_X177Y88 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[90]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 8.200 8.200 r BUFHCE_X1Y15 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.695 8.895 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X177Y88 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[90]/C clock pessimism 0.000 8.895 clock uncertainty -0.035 8.860 SLICE_X177Y88 FDCE (Setup_fdce_C_D) -0.112 8.748 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[90] ------------------------------------------------------------------- required time 8.748 arrival time -4.921 ------------------------------------------------------------------- slack 3.827 Slack (MET) : 3.925ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[26]/D (rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_4 rise@8.200ns - rxWordclkl8_4 rise@0.000ns) Data Path Delay: 3.921ns (logic 1.200ns (30.608%) route 2.721ns (69.392%)) Logic Levels: 2 (LUT4=2) Clock Path Skew: -0.230ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.692ns = ( 8.892 - 8.200 ) Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.922 0.922 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y7 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y7 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[6]) 1.009 1.931 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[6] net (fo=6, routed) 1.388 3.319 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19]_1[6] SLICE_X173Y93 LUT4 (Prop_lut4_I0_O) 0.050 3.369 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[98]_i_3__10/O net (fo=6, routed) 1.053 4.422 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[98]_i_3__10_n_0 SLICE_X172Y87 LUT4 (Prop_lut4_I1_O) 0.141 4.563 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[26]_i_1__10/O net (fo=1, routed) 0.280 4.843 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[99]_1[22] SLICE_X170Y87 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[26]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 8.200 8.200 r BUFHCE_X1Y15 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.692 8.892 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X170Y87 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[26]/C clock pessimism 0.000 8.892 clock uncertainty -0.035 8.857 SLICE_X170Y87 FDCE (Setup_fdce_C_D) -0.089 8.768 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[26] ------------------------------------------------------------------- required time 8.768 arrival time -4.843 ------------------------------------------------------------------- slack 3.925 Slack (MET) : 4.095ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[58]/D (rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_4 rise@8.200ns - rxWordclkl8_4 rise@0.000ns) Data Path Delay: 3.750ns (logic 1.198ns (31.948%) route 2.552ns (68.052%)) Logic Levels: 2 (LUT4=2) Clock Path Skew: -0.230ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.692ns = ( 8.892 - 8.200 ) Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.922 0.922 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y7 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y7 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDATA[6]) 1.009 1.931 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDATA[6] net (fo=6, routed) 1.388 3.319 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19]_1[6] SLICE_X173Y93 LUT4 (Prop_lut4_I0_O) 0.050 3.369 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[98]_i_3__10/O net (fo=6, routed) 0.847 4.216 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[98]_i_3__10_n_0 SLICE_X172Y88 LUT4 (Prop_lut4_I1_O) 0.139 4.355 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[58]_i_1__10/O net (fo=1, routed) 0.317 4.672 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[99]_1[54] SLICE_X170Y88 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[58]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 8.200 8.200 r BUFHCE_X1Y15 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.692 8.892 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X170Y88 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[58]/C clock pessimism 0.000 8.892 clock uncertainty -0.035 8.857 SLICE_X170Y88 FDCE (Setup_fdce_C_D) -0.089 8.768 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[58] ------------------------------------------------------------------- required time 8.768 arrival time -4.672 ------------------------------------------------------------------- slack 4.095 Slack (MET) : 4.189ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[23]/D (rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_4 rise@8.200ns - rxWordclkl8_4 rise@0.000ns) Data Path Delay: 3.636ns (logic 1.197ns (32.917%) route 2.439ns (67.083%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.228ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.694ns = ( 8.894 - 8.200 ) Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.922 0.922 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y7 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y7 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDISPERR[1]) 1.009 1.931 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDISPERR[1] net (fo=8, routed) 1.682 3.614 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19]_1[19] SLICE_X171Y91 LUT5 (Prop_lut5_I3_O) 0.048 3.662 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[95]_i_3__10/O net (fo=6, routed) 0.457 4.119 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[95]_i_3__10_n_0 SLICE_X169Y91 LUT4 (Prop_lut4_I1_O) 0.140 4.259 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[23]_i_2__10/O net (fo=1, routed) 0.300 4.559 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[99]_1[19] SLICE_X169Y90 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[23]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 8.200 8.200 r BUFHCE_X1Y15 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.694 8.894 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X169Y90 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[23]/C clock pessimism 0.000 8.894 clock uncertainty -0.035 8.859 SLICE_X169Y90 FDCE (Setup_fdce_C_D) -0.111 8.748 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[23] ------------------------------------------------------------------- required time 8.748 arrival time -4.559 ------------------------------------------------------------------- slack 4.189 Slack (MET) : 4.247ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[63]/D (rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_4 rise@8.200ns - rxWordclkl8_4 rise@0.000ns) Data Path Delay: 3.579ns (logic 1.199ns (33.497%) route 2.380ns (66.503%)) Logic Levels: 2 (LUT4=1 LUT5=1) Clock Path Skew: -0.227ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.695ns = ( 8.895 - 8.200 ) Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.922 0.922 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y7 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y7 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXDISPERR[1]) 1.009 1.931 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXDISPERR[1] net (fo=8, routed) 1.682 3.614 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxdata_out[19]_1[19] SLICE_X171Y91 LUT5 (Prop_lut5_I3_O) 0.048 3.662 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[95]_i_3__10/O net (fo=6, routed) 0.423 4.085 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[95]_i_3__10_n_0 SLICE_X172Y91 LUT4 (Prop_lut4_I1_O) 0.142 4.227 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[63]_i_2__10/O net (fo=1, routed) 0.275 4.502 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[99]_1[59] SLICE_X172Y92 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[63]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 8.200 8.200 r BUFHCE_X1Y15 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.695 8.895 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X172Y92 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[63]/C clock pessimism 0.000 8.895 clock uncertainty -0.035 8.860 SLICE_X172Y92 FDCE (Setup_fdce_C_D) -0.111 8.749 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[63] ------------------------------------------------------------------- required time 8.749 arrival time -4.502 ------------------------------------------------------------------- slack 4.247 Slack (MET) : 4.251ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[0]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[57]/D (rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_4 rise@8.200ns - rxWordclkl8_4 rise@0.000ns) Data Path Delay: 3.754ns (logic 0.937ns (24.963%) route 2.817ns (75.037%)) Logic Levels: 4 (CARRY4=1 LUT4=3) Clock Path Skew: -0.056ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.692ns = ( 8.892 - 8.200 ) Source Clock Delay (SCD): 0.748ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.748 0.748 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/CLK SLICE_X178Y90 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X178Y90 FDCE (Prop_fdce_C_Q) 0.259 1.007 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[0]/Q net (fo=37, routed) 0.742 1.749 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[0]_0 SLICE_X173Y91 LUT4 (Prop_lut4_I2_O) 0.053 1.802 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0[99]_i_14__10/O net (fo=3, routed) 0.228 2.030 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0[99]_i_14__10_n_0 SLICE_X173Y91 CARRY4 (Prop_carry4_DI[1]_O[2]) 0.354 2.384 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[99]_i_3__10/O[2] net (fo=65, routed) 0.597 2.981 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg01_8[2] SLICE_X178Y89 LUT4 (Prop_lut4_I2_O) 0.126 3.107 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[97]_i_3__10/O net (fo=6, routed) 0.880 3.987 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[97]_i_3__10_n_0 SLICE_X172Y88 LUT4 (Prop_lut4_I1_O) 0.145 4.132 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/reg0[57]_i_1__10/O net (fo=1, routed) 0.369 4.502 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[99]_1[53] SLICE_X170Y88 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[57]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 8.200 8.200 r BUFHCE_X1Y15 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.692 8.892 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X170Y88 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[57]/C clock pessimism 0.000 8.892 clock uncertainty -0.035 8.857 SLICE_X170Y88 FDCE (Setup_fdce_C_D) -0.104 8.753 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[57] ------------------------------------------------------------------- required time 8.753 arrival time -4.502 ------------------------------------------------------------------- slack 4.251 Slack (MET) : 4.253ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[1]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[65]/CE (rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_4 rise@8.200ns - rxWordclkl8_4 rise@0.000ns) Data Path Delay: 3.677ns (logic 0.888ns (24.148%) route 2.789ns (75.852%)) Logic Levels: 5 (CARRY4=2 LUT4=1 LUT5=1 LUT6=1) Clock Path Skew: -0.056ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.692ns = ( 8.892 - 8.200 ) Source Clock Delay (SCD): 0.748ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.748 0.748 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/CLK SLICE_X178Y90 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X178Y90 FDCE (Prop_fdce_C_Q) 0.236 0.984 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[1]/Q net (fo=23, routed) 0.745 1.729 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[1]_0 SLICE_X174Y92 LUT4 (Prop_lut4_I1_O) 0.123 1.852 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0[99]_i_13__10/O net (fo=1, routed) 0.366 2.218 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0[99]_i_13__10_n_0 SLICE_X173Y91 CARRY4 (Prop_carry4_DI[2]_CO[3]) 0.197 2.415 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[99]_i_3__10/CO[3] net (fo=1, routed) 0.000 2.415 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[99]_i_3__10_n_0 SLICE_X173Y92 CARRY4 (Prop_carry4_CI_O[1]) 0.166 2.581 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[15]_i_4__10/O[1] net (fo=11, routed) 0.585 3.165 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg01[5] SLICE_X170Y89 LUT6 (Prop_lut6_I2_O) 0.123 3.288 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0[99]_i_8__10/O net (fo=40, routed) 0.628 3.916 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[67]_0 SLICE_X175Y93 LUT5 (Prop_lut5_I0_O) 0.043 3.959 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0[67]_i_1__10/O net (fo=4, routed) 0.466 4.425 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[99]_0[15] SLICE_X174Y87 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[65]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 8.200 8.200 r BUFHCE_X1Y15 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.692 8.892 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X174Y87 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[65]/C clock pessimism 0.000 8.892 clock uncertainty -0.035 8.857 SLICE_X174Y87 FDCE (Setup_fdce_C_CE) -0.178 8.679 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[65] ------------------------------------------------------------------- required time 8.679 arrival time -4.425 ------------------------------------------------------------------- slack 4.253 Slack (MET) : 4.253ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[1]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[67]/CE (rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_4 rise@8.200ns - rxWordclkl8_4 rise@0.000ns) Data Path Delay: 3.677ns (logic 0.888ns (24.148%) route 2.789ns (75.852%)) Logic Levels: 5 (CARRY4=2 LUT4=1 LUT5=1 LUT6=1) Clock Path Skew: -0.056ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.692ns = ( 8.892 - 8.200 ) Source Clock Delay (SCD): 0.748ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.748 0.748 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/CLK SLICE_X178Y90 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X178Y90 FDCE (Prop_fdce_C_Q) 0.236 0.984 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[1]/Q net (fo=23, routed) 0.745 1.729 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[1]_0 SLICE_X174Y92 LUT4 (Prop_lut4_I1_O) 0.123 1.852 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0[99]_i_13__10/O net (fo=1, routed) 0.366 2.218 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0[99]_i_13__10_n_0 SLICE_X173Y91 CARRY4 (Prop_carry4_DI[2]_CO[3]) 0.197 2.415 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[99]_i_3__10/CO[3] net (fo=1, routed) 0.000 2.415 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[99]_i_3__10_n_0 SLICE_X173Y92 CARRY4 (Prop_carry4_CI_O[1]) 0.166 2.581 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[15]_i_4__10/O[1] net (fo=11, routed) 0.585 3.165 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg01[5] SLICE_X170Y89 LUT6 (Prop_lut6_I2_O) 0.123 3.288 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0[99]_i_8__10/O net (fo=40, routed) 0.628 3.916 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[67]_0 SLICE_X175Y93 LUT5 (Prop_lut5_I0_O) 0.043 3.959 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0[67]_i_1__10/O net (fo=4, routed) 0.466 4.425 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[99]_0[15] SLICE_X174Y87 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[67]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 8.200 8.200 r BUFHCE_X1Y15 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.692 8.892 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X174Y87 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[67]/C clock pessimism 0.000 8.892 clock uncertainty -0.035 8.857 SLICE_X174Y87 FDCE (Setup_fdce_C_CE) -0.178 8.679 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[67] ------------------------------------------------------------------- required time 8.679 arrival time -4.425 ------------------------------------------------------------------- slack 4.253 Slack (MET) : 4.280ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[1]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[68]/CE (rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_4 rise@8.200ns - rxWordclkl8_4 rise@0.000ns) Data Path Delay: 3.630ns (logic 0.888ns (24.464%) route 2.742ns (75.536%)) Logic Levels: 5 (CARRY4=2 LUT4=1 LUT6=2) Clock Path Skew: -0.054ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.694ns = ( 8.894 - 8.200 ) Source Clock Delay (SCD): 0.748ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.748 0.748 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/CLK SLICE_X178Y90 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X178Y90 FDCE (Prop_fdce_C_Q) 0.236 0.984 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[1]/Q net (fo=23, routed) 0.745 1.729 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[1]_0 SLICE_X174Y92 LUT4 (Prop_lut4_I1_O) 0.123 1.852 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0[99]_i_13__10/O net (fo=1, routed) 0.366 2.218 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0[99]_i_13__10_n_0 SLICE_X173Y91 CARRY4 (Prop_carry4_DI[2]_CO[3]) 0.197 2.415 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[99]_i_3__10/CO[3] net (fo=1, routed) 0.000 2.415 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[99]_i_3__10_n_0 SLICE_X173Y92 CARRY4 (Prop_carry4_CI_O[1]) 0.166 2.581 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[15]_i_4__10/O[1] net (fo=11, routed) 0.585 3.165 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg01[5] SLICE_X170Y89 LUT6 (Prop_lut6_I2_O) 0.123 3.288 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0[99]_i_8__10/O net (fo=40, routed) 0.665 3.953 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[67]_0 SLICE_X173Y93 LUT6 (Prop_lut6_I3_O) 0.043 3.996 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0[71]_i_1__10/O net (fo=4, routed) 0.382 4.378 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[99]_0[16] SLICE_X171Y91 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[68]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 8.200 8.200 r BUFHCE_X1Y15 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.694 8.894 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X171Y91 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[68]/C clock pessimism 0.000 8.894 clock uncertainty -0.035 8.859 SLICE_X171Y91 FDCE (Setup_fdce_C_CE) -0.201 8.658 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[68] ------------------------------------------------------------------- required time 8.658 arrival time -4.378 ------------------------------------------------------------------- slack 4.280 Slack (MET) : 4.280ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[1]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[69]/CE (rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_4 rise@8.200ns - rxWordclkl8_4 rise@0.000ns) Data Path Delay: 3.630ns (logic 0.888ns (24.464%) route 2.742ns (75.536%)) Logic Levels: 5 (CARRY4=2 LUT4=1 LUT6=2) Clock Path Skew: -0.054ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.694ns = ( 8.894 - 8.200 ) Source Clock Delay (SCD): 0.748ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.748 0.748 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/CLK SLICE_X178Y90 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X178Y90 FDCE (Prop_fdce_C_Q) 0.236 0.984 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[1]/Q net (fo=23, routed) 0.745 1.729 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[1]_0 SLICE_X174Y92 LUT4 (Prop_lut4_I1_O) 0.123 1.852 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0[99]_i_13__10/O net (fo=1, routed) 0.366 2.218 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0[99]_i_13__10_n_0 SLICE_X173Y91 CARRY4 (Prop_carry4_DI[2]_CO[3]) 0.197 2.415 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[99]_i_3__10/CO[3] net (fo=1, routed) 0.000 2.415 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[99]_i_3__10_n_0 SLICE_X173Y92 CARRY4 (Prop_carry4_CI_O[1]) 0.166 2.581 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[15]_i_4__10/O[1] net (fo=11, routed) 0.585 3.165 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg01[5] SLICE_X170Y89 LUT6 (Prop_lut6_I2_O) 0.123 3.288 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0[99]_i_8__10/O net (fo=40, routed) 0.665 3.953 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0_reg[67]_0 SLICE_X173Y93 LUT6 (Prop_lut6_I3_O) 0.043 3.996 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/reg0[71]_i_1__10/O net (fo=4, routed) 0.382 4.378 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[99]_0[16] SLICE_X171Y91 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[69]/CE ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 8.200 8.200 r BUFHCE_X1Y15 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.694 8.894 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X171Y91 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[69]/C clock pessimism 0.000 8.894 clock uncertainty -0.035 8.859 SLICE_X171Y91 FDCE (Setup_fdce_C_CE) -0.201 8.658 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[69] ------------------------------------------------------------------- required time 8.658 arrival time -4.378 ------------------------------------------------------------------- slack 4.280 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.106ns (arrival time - required time) Source: ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Clock_20MHz_dl_reg[1]/C (rising edge-triggered cell FDRE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/D (rising edge-triggered cell SRL16E clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_4 rise@0.000ns - rxWordclkl8_4 rise@0.000ns) Data Path Delay: 0.222ns (logic 0.118ns (53.057%) route 0.104ns (46.943%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.509ns Source Clock Delay (SCD): 0.354ns Clock Pessimism Removal (CPR): 0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.354 0.354 ngFEC/SFP_GEN[8].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X160Y97 FDRE r ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Clock_20MHz_dl_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X160Y97 FDRE (Prop_fdre_C_Q) 0.118 0.472 r ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Clock_20MHz_dl_reg[1]/Q net (fo=2, routed) 0.104 0.576 ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Clock_20MHz_dl_reg_n_0_[1] SLICE_X160Y98 SRL16E r ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.509 0.509 ngFEC/SFP_GEN[8].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X160Y98 SRL16E r ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK clock pessimism -0.141 0.368 SLICE_X160Y98 SRL16E (Hold_srl16e_CLK_D) 0.102 0.470 ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2 ------------------------------------------------------------------- required time -0.470 arrival time 0.576 ------------------------------------------------------------------- slack 0.106 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_4 rise@0.000ns - rxWordclkl8_4 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.540ns Source Clock Delay (SCD): 0.384ns Clock Pessimism Removal (CPR): 0.156ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.384 0.384 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in SLICE_X187Y90 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X187Y90 FDRE (Prop_fdre_C_Q) 0.100 0.484 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q net (fo=1, routed) 0.055 0.539 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync1 SLICE_X187Y90 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.540 0.540 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/gt0_rxusrclk_in SLICE_X187Y90 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C clock pessimism -0.156 0.384 SLICE_X187Y90 FDRE (Hold_fdre_C_D) 0.047 0.431 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.431 arrival time 0.539 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_4 rise@0.000ns - rxWordclkl8_4 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.539ns Source Clock Delay (SCD): 0.383ns Clock Pessimism Removal (CPR): 0.156ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.383 0.383 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/gt0_rxusrclk_in SLICE_X185Y88 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X185Y88 FDRE (Prop_fdre_C_Q) 0.100 0.483 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg1/Q net (fo=1, routed) 0.055 0.538 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync1 SLICE_X185Y88 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.539 0.539 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/gt0_rxusrclk_in SLICE_X185Y88 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2/C clock pessimism -0.156 0.383 SLICE_X185Y88 FDRE (Hold_fdre_C_D) 0.047 0.430 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/sync_rx_fsm_reset_done_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.430 arrival time 0.538 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.114ns (arrival time - required time) Source: ngFEC/SFP_GEN[8].ngCCM_gbt/ngCCM_status_counter_reg[1][11]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[8].ngCCM_gbt/ngCCM_status_counter_o_reg[1][11]/D (rising edge-triggered cell FDRE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_4 rise@0.000ns - rxWordclkl8_4 rise@0.000ns) Data Path Delay: 0.188ns (logic 0.100ns (53.154%) route 0.088ns (46.846%)) Logic Levels: 0 Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.541ns Source Clock Delay (SCD): 0.385ns Clock Pessimism Removal (CPR): 0.145ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.385 0.385 ngFEC/SFP_GEN[8].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X183Y96 FDCE r ngFEC/SFP_GEN[8].ngCCM_gbt/ngCCM_status_counter_reg[1][11]/C ------------------------------------------------------------------- ------------------- SLICE_X183Y96 FDCE (Prop_fdce_C_Q) 0.100 0.485 r ngFEC/SFP_GEN[8].ngCCM_gbt/ngCCM_status_counter_reg[1][11]/Q net (fo=2, routed) 0.088 0.573 ngFEC/SFP_GEN[8].ngCCM_gbt/ngCCM_status_counter_reg[1]__0[11] SLICE_X182Y96 FDRE r ngFEC/SFP_GEN[8].ngCCM_gbt/ngCCM_status_counter_o_reg[1][11]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.541 0.541 ngFEC/SFP_GEN[8].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X182Y96 FDRE r ngFEC/SFP_GEN[8].ngCCM_gbt/ngCCM_status_counter_o_reg[1][11]/C clock pessimism -0.145 0.396 SLICE_X182Y96 FDRE (Hold_fdre_C_D) 0.063 0.459 ngFEC/SFP_GEN[8].ngCCM_gbt/ngCCM_status_counter_o_reg[1][11] ------------------------------------------------------------------- required time -0.459 arrival time 0.573 ------------------------------------------------------------------- slack 0.114 Slack (MET) : 0.116ns (arrival time - required time) Source: ngFEC/SFP_GEN[8].ngCCM_gbt/ngCCM_status_counter_reg[7][10]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[8].ngCCM_gbt/ngCCM_status_counter_o_reg[7][10]/D (rising edge-triggered cell FDRE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_4 rise@0.000ns - rxWordclkl8_4 rise@0.000ns) Data Path Delay: 0.190ns (logic 0.100ns (52.615%) route 0.090ns (47.385%)) Logic Levels: 0 Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.542ns Source Clock Delay (SCD): 0.386ns Clock Pessimism Removal (CPR): 0.145ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.386 0.386 ngFEC/SFP_GEN[8].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X187Y97 FDCE r ngFEC/SFP_GEN[8].ngCCM_gbt/ngCCM_status_counter_reg[7][10]/C ------------------------------------------------------------------- ------------------- SLICE_X187Y97 FDCE (Prop_fdce_C_Q) 0.100 0.486 r ngFEC/SFP_GEN[8].ngCCM_gbt/ngCCM_status_counter_reg[7][10]/Q net (fo=2, routed) 0.090 0.576 ngFEC/SFP_GEN[8].ngCCM_gbt/ngCCM_status_counter_reg_n_0_[7][10] SLICE_X186Y97 FDRE r ngFEC/SFP_GEN[8].ngCCM_gbt/ngCCM_status_counter_o_reg[7][10]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.542 0.542 ngFEC/SFP_GEN[8].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X186Y97 FDRE r ngFEC/SFP_GEN[8].ngCCM_gbt/ngCCM_status_counter_o_reg[7][10]/C clock pessimism -0.145 0.397 SLICE_X186Y97 FDRE (Hold_fdre_C_D) 0.063 0.460 ngFEC/SFP_GEN[8].ngCCM_gbt/ngCCM_status_counter_o_reg[7][10] ------------------------------------------------------------------- required time -0.460 arrival time 0.576 ------------------------------------------------------------------- slack 0.116 Slack (MET) : 0.118ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D (rising edge-triggered cell FDRE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_4 rise@0.000ns - rxWordclkl8_4 rise@0.000ns) Data Path Delay: 0.189ns (logic 0.128ns (67.668%) route 0.061ns (32.332%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.534ns Source Clock Delay (SCD): 0.379ns Clock Pessimism Removal (CPR): 0.144ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.379 0.379 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X168Y88 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X168Y88 FDCE (Prop_fdce_C_Q) 0.100 0.479 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[16]/Q net (fo=2, routed) 0.061 0.540 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_31_in SLICE_X169Y88 LUT3 (Prop_lut3_I2_O) 0.028 0.568 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1__10/O net (fo=1, routed) 0.000 0.568 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/p_40_out[14] SLICE_X169Y88 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.534 0.534 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X169Y88 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C clock pessimism -0.144 0.390 SLICE_X169Y88 FDRE (Hold_fdre_C_D) 0.060 0.450 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/RX_DATA_O_reg[14] ------------------------------------------------------------------- required time -0.450 arrival time 0.568 ------------------------------------------------------------------- slack 0.118 Slack (MET) : 0.120ns (arrival time - required time) Source: ngFEC/SFP_GEN[8].ngCCM_gbt/ngCCM_status_counter_reg[6][1]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[8].ngCCM_gbt/ngCCM_status_counter_o_reg[6][1]/D (rising edge-triggered cell FDRE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_4 rise@0.000ns - rxWordclkl8_4 rise@0.000ns) Data Path Delay: 0.214ns (logic 0.100ns (46.714%) route 0.114ns (53.286%)) Logic Levels: 0 Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.541ns Source Clock Delay (SCD): 0.386ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.386 0.386 ngFEC/SFP_GEN[8].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X189Y95 FDCE r ngFEC/SFP_GEN[8].ngCCM_gbt/ngCCM_status_counter_reg[6][1]/C ------------------------------------------------------------------- ------------------- SLICE_X189Y95 FDCE (Prop_fdce_C_Q) 0.100 0.486 r ngFEC/SFP_GEN[8].ngCCM_gbt/ngCCM_status_counter_reg[6][1]/Q net (fo=2, routed) 0.114 0.600 ngFEC/SFP_GEN[8].ngCCM_gbt/ngCCM_status_counter_reg_n_0_[6][1] SLICE_X186Y94 FDRE r ngFEC/SFP_GEN[8].ngCCM_gbt/ngCCM_status_counter_o_reg[6][1]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.541 0.541 ngFEC/SFP_GEN[8].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X186Y94 FDRE r ngFEC/SFP_GEN[8].ngCCM_gbt/ngCCM_status_counter_o_reg[6][1]/C clock pessimism -0.120 0.421 SLICE_X186Y94 FDRE (Hold_fdre_C_D) 0.059 0.480 ngFEC/SFP_GEN[8].ngCCM_gbt/ngCCM_status_counter_o_reg[6][1] ------------------------------------------------------------------- required time -0.480 arrival time 0.600 ------------------------------------------------------------------- slack 0.120 Slack (MET) : 0.121ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D (rising edge-triggered cell FDRE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_4 rise@0.000ns - rxWordclkl8_4 rise@0.000ns) Data Path Delay: 0.192ns (logic 0.128ns (66.756%) route 0.064ns (33.244%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.507ns Source Clock Delay (SCD): 0.353ns Clock Pessimism Removal (CPR): 0.143ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.353 0.353 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X156Y94 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X156Y94 FDCE (Prop_fdce_C_Q) 0.100 0.453 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[14]/Q net (fo=2, routed) 0.064 0.517 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_27_in SLICE_X157Y94 LUT3 (Prop_lut3_I0_O) 0.028 0.545 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[14]_i_1__10/O net (fo=1, routed) 0.000 0.545 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[14] SLICE_X157Y94 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.507 0.507 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X157Y94 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14]/C clock pessimism -0.143 0.364 SLICE_X157Y94 FDRE (Hold_fdre_C_D) 0.060 0.424 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[14] ------------------------------------------------------------------- required time -0.424 arrival time 0.545 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.124ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/D (rising edge-triggered cell FDRE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_4 rise@0.000ns - rxWordclkl8_4 rise@0.000ns) Data Path Delay: 0.225ns (logic 0.128ns (56.980%) route 0.097ns (43.020%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.507ns Source Clock Delay (SCD): 0.353ns Clock Pessimism Removal (CPR): 0.140ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.353 0.353 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X157Y93 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X157Y93 FDCE (Prop_fdce_C_Q) 0.100 0.453 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[3]/Q net (fo=2, routed) 0.097 0.550 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_5_in SLICE_X158Y93 LUT3 (Prop_lut3_I0_O) 0.028 0.578 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O[3]_i_1__10/O net (fo=1, routed) 0.000 0.578 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/p_40_out[3] SLICE_X158Y93 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.507 0.507 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X158Y93 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3]/C clock pessimism -0.140 0.367 SLICE_X158Y93 FDRE (Hold_fdre_C_D) 0.087 0.454 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[3] ------------------------------------------------------------------- required time -0.454 arrival time 0.578 ------------------------------------------------------------------- slack 0.124 Slack (MET) : 0.129ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C (rising edge-triggered cell FDRE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[8].rx_data_reg[8][34]/D (rising edge-triggered cell FDRE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: rxWordclkl8_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_4 rise@0.000ns - rxWordclkl8_4 rise@0.000ns) Data Path Delay: 0.202ns (logic 0.100ns (49.592%) route 0.102ns (50.408%)) Logic Levels: 0 Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.508ns Source Clock Delay (SCD): 0.353ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.353 0.353 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X159Y93 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X159Y93 FDRE (Prop_fdre_C_Q) 0.100 0.453 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[4].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/RX_DATA_O_reg[13]/Q net (fo=1, routed) 0.102 0.555 ngFEC/GBT_rx_data[12]_1399[34] SLICE_X160Y93 FDRE r ngFEC/SFP_GEN[8].rx_data_reg[8][34]/D ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.508 0.508 ngFEC/gbtbank4_l8_112_n_187 SLICE_X160Y93 FDRE r ngFEC/SFP_GEN[8].rx_data_reg[8][34]/C clock pessimism -0.120 0.388 SLICE_X160Y93 FDRE (Hold_fdre_C_D) 0.038 0.426 ngFEC/SFP_GEN[8].rx_data_reg[8][34] ------------------------------------------------------------------- required time -0.426 arrival time 0.555 ------------------------------------------------------------------- slack 0.129 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: rxWordclkl8_4 Waveform(ns): { 0.000 4.100 } Period(ns): 8.200 Sources: { ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/RXUSRCLK n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y7 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK Min Period n/a GTXE2_CHANNEL/RXUSRCLK2 n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y7 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X171Y98 ngFEC/clk_rate_gen[8].clkRate3/clktest_div8_reg/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X170Y91 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[29]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X173Y90 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[6]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X163Y93 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[100]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X163Y92 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[102]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X163Y93 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[103]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X163Y93 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[109]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X177Y86 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[114]/C Low Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X160Y98 ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK Low Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X160Y98 ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK Low Pulse Width Slow FDRE/C n/a 0.400 4.100 3.700 SLICE_X171Y98 ngFEC/clk_rate_gen[8].clkRate3/clktest_div8_reg/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X177Y86 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[114]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X161Y92 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[116]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X164Y91 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[69]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X165Y91 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[77]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X165Y91 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[85]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X165Y91 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[87]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X178Y88 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[91]/C High Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X160Y98 ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X160Y98 ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Clock_20MHz_dl_reg[3]_srl2/CLK High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X170Y87 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[24]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X170Y87 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[25]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X170Y87 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[26]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X170Y87 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[27]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X171Y88 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[35]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X170Y88 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[56]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X170Y88 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[57]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X170Y88 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[58]/C --------------------------------------------------------------------------------------------------- From Clock: ttc_mgt_xpoint_a To Clock: ttc_mgt_xpoint_a Setup : 0 Failing Endpoints, Worst Slack 7.362ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.172ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.524ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 7.362ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/D (rising edge-triggered cell FDRE clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: ttc_mgt_xpoint_a Path Type: Setup (Max at Slow Process Corner) Requirement: 8.333ns (ttc_mgt_xpoint_a rise@8.333ns - ttc_mgt_xpoint_a rise@0.000ns) Data Path Delay: 1.000ns (logic 1.000ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.623ns = ( 10.956 - 8.333 ) Source Clock Delay (SCD): 3.700ns Clock Pessimism Removal (CPR): 1.077ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_a rise edge) 0.000 0.000 r AH6 0.000 0.000 r ttc_mgt_xpoint_a_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_a_p AH6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_a_p_IBUF IBUFDS_GTE2_X0Y3 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r ngFEC/cdceOut1IbufdsAGtxe2/O net (fo=8, routed) 0.665 3.020 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y14 BUFH (Prop_bufh_I_O) 0.103 3.123 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.577 3.700 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X86Y78 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK ------------------------------------------------------------------- ------------------- SLICE_X86Y78 SRLC32E (Prop_srlc32e_CLK_Q) 1.000 4.700 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/Q net (fo=1, routed) 0.000 4.700 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31_n_0 SLICE_X86Y78 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/D ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_a rise edge) 8.333 8.333 r AH6 0.000 8.333 r ttc_mgt_xpoint_a_p (IN) net (fo=0) 0.000 8.333 ttc_mgt_xpoint_a_p AH6 IBUF (Prop_ibuf_I_O) 0.000 8.333 r ttc_mgt_xpoint_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.333 ngFEC/ttc_mgt_xpoint_a_p_IBUF IBUFDS_GTE2_X0Y3 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.751 r ngFEC/cdceOut1IbufdsAGtxe2/O net (fo=8, routed) 0.606 10.357 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y14 BUFH (Prop_bufh_I_O) 0.066 10.423 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.533 10.956 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X86Y78 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/C clock pessimism 1.077 12.033 clock uncertainty -0.035 11.997 SLICE_X86Y78 FDRE (Setup_fdre_C_D) 0.064 12.061 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127] ------------------------------------------------------------------- required time 12.061 arrival time -4.700 ------------------------------------------------------------------- slack 7.362 Slack (MET) : 7.362ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/D (rising edge-triggered cell FDRE clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: ttc_mgt_xpoint_a Path Type: Setup (Max at Slow Process Corner) Requirement: 8.333ns (ttc_mgt_xpoint_a rise@8.333ns - ttc_mgt_xpoint_a rise@0.000ns) Data Path Delay: 1.000ns (logic 1.000ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.634ns = ( 10.967 - 8.333 ) Source Clock Delay (SCD): 3.714ns Clock Pessimism Removal (CPR): 1.080ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_a rise edge) 0.000 0.000 r AH6 0.000 0.000 r ttc_mgt_xpoint_a_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_a_p AH6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_a_p_IBUF IBUFDS_GTE2_X0Y3 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r ngFEC/cdceOut1IbufdsAGtxe2/O net (fo=8, routed) 0.665 3.020 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y12 BUFH (Prop_bufh_I_O) 0.103 3.123 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.591 3.714 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y55 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y55 SRLC32E (Prop_srlc32e_CLK_Q) 1.000 4.714 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/Q net (fo=1, routed) 0.000 4.714 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31_n_0 SLICE_X90Y55 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/D ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_a rise edge) 8.333 8.333 r AH6 0.000 8.333 r ttc_mgt_xpoint_a_p (IN) net (fo=0) 0.000 8.333 ttc_mgt_xpoint_a_p AH6 IBUF (Prop_ibuf_I_O) 0.000 8.333 r ttc_mgt_xpoint_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.333 ngFEC/ttc_mgt_xpoint_a_p_IBUF IBUFDS_GTE2_X0Y3 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.751 r ngFEC/cdceOut1IbufdsAGtxe2/O net (fo=8, routed) 0.606 10.357 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y12 BUFH (Prop_bufh_I_O) 0.066 10.423 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.544 10.967 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y55 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/C clock pessimism 1.080 12.047 clock uncertainty -0.035 12.011 SLICE_X90Y55 FDRE (Setup_fdre_C_D) 0.064 12.075 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95] ------------------------------------------------------------------- required time 12.075 arrival time -4.714 ------------------------------------------------------------------- slack 7.362 Slack (MET) : 7.362ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/D (rising edge-triggered cell FDRE clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: ttc_mgt_xpoint_a Path Type: Setup (Max at Slow Process Corner) Requirement: 8.333ns (ttc_mgt_xpoint_a rise@8.333ns - ttc_mgt_xpoint_a rise@0.000ns) Data Path Delay: 1.000ns (logic 1.000ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.627ns = ( 10.960 - 8.333 ) Source Clock Delay (SCD): 3.705ns Clock Pessimism Removal (CPR): 1.078ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_a rise edge) 0.000 0.000 r AH6 0.000 0.000 r ttc_mgt_xpoint_a_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_a_p AH6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_a_p_IBUF IBUFDS_GTE2_X0Y3 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r ngFEC/cdceOut1IbufdsAGtxe2/O net (fo=8, routed) 0.665 3.020 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y13 BUFH (Prop_bufh_I_O) 0.103 3.123 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.582 3.705 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y66 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y66 SRLC32E (Prop_srlc32e_CLK_Q) 1.000 4.705 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/Q net (fo=1, routed) 0.000 4.705 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31_n_0 SLICE_X90Y66 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/D ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_a rise edge) 8.333 8.333 r AH6 0.000 8.333 r ttc_mgt_xpoint_a_p (IN) net (fo=0) 0.000 8.333 ttc_mgt_xpoint_a_p AH6 IBUF (Prop_ibuf_I_O) 0.000 8.333 r ttc_mgt_xpoint_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.333 ngFEC/ttc_mgt_xpoint_a_p_IBUF IBUFDS_GTE2_X0Y3 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.751 r ngFEC/cdceOut1IbufdsAGtxe2/O net (fo=8, routed) 0.606 10.357 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y13 BUFH (Prop_bufh_I_O) 0.066 10.423 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.537 10.960 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y66 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/C clock pessimism 1.078 12.038 clock uncertainty -0.035 12.002 SLICE_X90Y66 FDRE (Setup_fdre_C_D) 0.064 12.066 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95] ------------------------------------------------------------------- required time 12.066 arrival time -4.705 ------------------------------------------------------------------- slack 7.362 Slack (MET) : 7.362ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/D (rising edge-triggered cell FDRE clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: ttc_mgt_xpoint_a Path Type: Setup (Max at Slow Process Corner) Requirement: 8.333ns (ttc_mgt_xpoint_a rise@8.333ns - ttc_mgt_xpoint_a rise@0.000ns) Data Path Delay: 1.000ns (logic 1.000ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.626ns = ( 10.959 - 8.333 ) Source Clock Delay (SCD): 3.704ns Clock Pessimism Removal (CPR): 1.078ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_a rise edge) 0.000 0.000 r AH6 0.000 0.000 r ttc_mgt_xpoint_a_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_a_p AH6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_a_p_IBUF IBUFDS_GTE2_X0Y3 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r ngFEC/cdceOut1IbufdsAGtxe2/O net (fo=8, routed) 0.665 3.020 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y13 BUFH (Prop_bufh_I_O) 0.103 3.123 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.581 3.704 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y67 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y67 SRLC32E (Prop_srlc32e_CLK_Q) 1.000 4.704 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/Q net (fo=1, routed) 0.000 4.704 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31_n_0 SLICE_X90Y67 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/D ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_a rise edge) 8.333 8.333 r AH6 0.000 8.333 r ttc_mgt_xpoint_a_p (IN) net (fo=0) 0.000 8.333 ttc_mgt_xpoint_a_p AH6 IBUF (Prop_ibuf_I_O) 0.000 8.333 r ttc_mgt_xpoint_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.333 ngFEC/ttc_mgt_xpoint_a_p_IBUF IBUFDS_GTE2_X0Y3 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.751 r ngFEC/cdceOut1IbufdsAGtxe2/O net (fo=8, routed) 0.606 10.357 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y13 BUFH (Prop_bufh_I_O) 0.066 10.423 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.536 10.959 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y67 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/C clock pessimism 1.078 12.037 clock uncertainty -0.035 12.001 SLICE_X90Y67 FDRE (Setup_fdre_C_D) 0.064 12.065 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127] ------------------------------------------------------------------- required time 12.065 arrival time -4.704 ------------------------------------------------------------------- slack 7.362 Slack (MET) : 7.362ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/D (rising edge-triggered cell FDRE clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: ttc_mgt_xpoint_a Path Type: Setup (Max at Slow Process Corner) Requirement: 8.333ns (ttc_mgt_xpoint_a rise@8.333ns - ttc_mgt_xpoint_a rise@0.000ns) Data Path Delay: 1.000ns (logic 1.000ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.627ns = ( 10.960 - 8.333 ) Source Clock Delay (SCD): 3.705ns Clock Pessimism Removal (CPR): 1.078ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_a rise edge) 0.000 0.000 r AH6 0.000 0.000 r ttc_mgt_xpoint_a_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_a_p AH6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_a_p_IBUF IBUFDS_GTE2_X0Y3 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r ngFEC/cdceOut1IbufdsAGtxe2/O net (fo=8, routed) 0.665 3.020 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y14 BUFH (Prop_bufh_I_O) 0.103 3.123 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.582 3.705 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y83 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y83 SRLC32E (Prop_srlc32e_CLK_Q) 1.000 4.705 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/Q net (fo=1, routed) 0.000 4.705 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31_n_0 SLICE_X90Y83 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/D ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_a rise edge) 8.333 8.333 r AH6 0.000 8.333 r ttc_mgt_xpoint_a_p (IN) net (fo=0) 0.000 8.333 ttc_mgt_xpoint_a_p AH6 IBUF (Prop_ibuf_I_O) 0.000 8.333 r ttc_mgt_xpoint_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.333 ngFEC/ttc_mgt_xpoint_a_p_IBUF IBUFDS_GTE2_X0Y3 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.751 r ngFEC/cdceOut1IbufdsAGtxe2/O net (fo=8, routed) 0.606 10.357 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y14 BUFH (Prop_bufh_I_O) 0.066 10.423 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.537 10.960 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y83 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/C clock pessimism 1.078 12.038 clock uncertainty -0.035 12.002 SLICE_X90Y83 FDRE (Setup_fdre_C_D) 0.064 12.066 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95] ------------------------------------------------------------------- required time 12.066 arrival time -4.705 ------------------------------------------------------------------- slack 7.362 Slack (MET) : 7.362ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/D (rising edge-triggered cell FDRE clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: ttc_mgt_xpoint_a Path Type: Setup (Max at Slow Process Corner) Requirement: 8.333ns (ttc_mgt_xpoint_a rise@8.333ns - ttc_mgt_xpoint_a rise@0.000ns) Data Path Delay: 1.000ns (logic 1.000ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.634ns = ( 10.967 - 8.333 ) Source Clock Delay (SCD): 3.714ns Clock Pessimism Removal (CPR): 1.080ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_a rise edge) 0.000 0.000 r AH6 0.000 0.000 r ttc_mgt_xpoint_a_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_a_p AH6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_a_p_IBUF IBUFDS_GTE2_X0Y3 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r ngFEC/cdceOut1IbufdsAGtxe2/O net (fo=8, routed) 0.665 3.020 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y15 BUFH (Prop_bufh_I_O) 0.103 3.123 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.591 3.714 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y97 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y97 SRLC32E (Prop_srlc32e_CLK_Q) 1.000 4.714 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/Q net (fo=1, routed) 0.000 4.714 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31_n_0 SLICE_X90Y97 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/D ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_a rise edge) 8.333 8.333 r AH6 0.000 8.333 r ttc_mgt_xpoint_a_p (IN) net (fo=0) 0.000 8.333 ttc_mgt_xpoint_a_p AH6 IBUF (Prop_ibuf_I_O) 0.000 8.333 r ttc_mgt_xpoint_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.333 ngFEC/ttc_mgt_xpoint_a_p_IBUF IBUFDS_GTE2_X0Y3 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.751 r ngFEC/cdceOut1IbufdsAGtxe2/O net (fo=8, routed) 0.606 10.357 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y15 BUFH (Prop_bufh_I_O) 0.066 10.423 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.544 10.967 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y97 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/C clock pessimism 1.080 12.047 clock uncertainty -0.035 12.011 SLICE_X90Y97 FDRE (Setup_fdre_C_D) 0.064 12.075 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95] ------------------------------------------------------------------- required time 12.075 arrival time -4.714 ------------------------------------------------------------------- slack 7.362 Slack (MET) : 7.362ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/D (rising edge-triggered cell FDRE clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: ttc_mgt_xpoint_a Path Type: Setup (Max at Slow Process Corner) Requirement: 8.333ns (ttc_mgt_xpoint_a rise@8.333ns - ttc_mgt_xpoint_a rise@0.000ns) Data Path Delay: 1.000ns (logic 1.000ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.632ns = ( 10.965 - 8.333 ) Source Clock Delay (SCD): 3.712ns Clock Pessimism Removal (CPR): 1.080ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_a rise edge) 0.000 0.000 r AH6 0.000 0.000 r ttc_mgt_xpoint_a_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_a_p AH6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_a_p_IBUF IBUFDS_GTE2_X0Y3 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r ngFEC/cdceOut1IbufdsAGtxe2/O net (fo=8, routed) 0.665 3.020 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y15 BUFH (Prop_bufh_I_O) 0.103 3.123 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.589 3.712 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y91 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y91 SRLC32E (Prop_srlc32e_CLK_Q) 1.000 4.712 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/Q net (fo=1, routed) 0.000 4.712 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31_n_0 SLICE_X90Y91 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/D ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_a rise edge) 8.333 8.333 r AH6 0.000 8.333 r ttc_mgt_xpoint_a_p (IN) net (fo=0) 0.000 8.333 ttc_mgt_xpoint_a_p AH6 IBUF (Prop_ibuf_I_O) 0.000 8.333 r ttc_mgt_xpoint_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.333 ngFEC/ttc_mgt_xpoint_a_p_IBUF IBUFDS_GTE2_X0Y3 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.751 r ngFEC/cdceOut1IbufdsAGtxe2/O net (fo=8, routed) 0.606 10.357 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y15 BUFH (Prop_bufh_I_O) 0.066 10.423 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.542 10.965 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y91 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/C clock pessimism 1.080 12.045 clock uncertainty -0.035 12.009 SLICE_X90Y91 FDRE (Setup_fdre_C_D) 0.064 12.073 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127] ------------------------------------------------------------------- required time 12.073 arrival time -4.712 ------------------------------------------------------------------- slack 7.362 Slack (MET) : 7.362ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/D (rising edge-triggered cell FDRE clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: ttc_mgt_xpoint_a Path Type: Setup (Max at Slow Process Corner) Requirement: 8.333ns (ttc_mgt_xpoint_a rise@8.333ns - ttc_mgt_xpoint_a rise@0.000ns) Data Path Delay: 1.000ns (logic 1.000ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.638ns = ( 10.971 - 8.333 ) Source Clock Delay (SCD): 3.719ns Clock Pessimism Removal (CPR): 1.081ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_a rise edge) 0.000 0.000 r AH6 0.000 0.000 r ttc_mgt_xpoint_a_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_a_p AH6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_a_p_IBUF IBUFDS_GTE2_X0Y3 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r ngFEC/cdceOut1IbufdsAGtxe2/O net (fo=8, routed) 0.665 3.020 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y12 BUFH (Prop_bufh_I_O) 0.103 3.123 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.596 3.719 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X84Y52 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK ------------------------------------------------------------------- ------------------- SLICE_X84Y52 SRLC32E (Prop_srlc32e_CLK_Q) 1.000 4.719 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/Q net (fo=1, routed) 0.000 4.719 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31_n_0 SLICE_X84Y52 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/D ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_a rise edge) 8.333 8.333 r AH6 0.000 8.333 r ttc_mgt_xpoint_a_p (IN) net (fo=0) 0.000 8.333 ttc_mgt_xpoint_a_p AH6 IBUF (Prop_ibuf_I_O) 0.000 8.333 r ttc_mgt_xpoint_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.333 ngFEC/ttc_mgt_xpoint_a_p_IBUF IBUFDS_GTE2_X0Y3 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.751 r ngFEC/cdceOut1IbufdsAGtxe2/O net (fo=8, routed) 0.606 10.357 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y12 BUFH (Prop_bufh_I_O) 0.066 10.423 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.548 10.971 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X84Y52 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/C clock pessimism 1.081 12.052 clock uncertainty -0.035 12.016 SLICE_X84Y52 FDRE (Setup_fdre_C_D) 0.064 12.080 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127] ------------------------------------------------------------------- required time 12.080 arrival time -4.719 ------------------------------------------------------------------- slack 7.362 Slack (MET) : 7.525ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[31]_srl32/CLK (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/D (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: ttc_mgt_xpoint_a Path Type: Setup (Max at Slow Process Corner) Requirement: 8.333ns (ttc_mgt_xpoint_a rise@8.333ns - ttc_mgt_xpoint_a rise@0.000ns) Data Path Delay: 0.737ns (logic 0.737ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.626ns = ( 10.959 - 8.333 ) Source Clock Delay (SCD): 3.704ns Clock Pessimism Removal (CPR): 1.078ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_a rise edge) 0.000 0.000 r AH6 0.000 0.000 r ttc_mgt_xpoint_a_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_a_p AH6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_a_p_IBUF IBUFDS_GTE2_X0Y3 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r ngFEC/cdceOut1IbufdsAGtxe2/O net (fo=8, routed) 0.665 3.020 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y13 BUFH (Prop_bufh_I_O) 0.103 3.123 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.581 3.704 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y67 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[31]_srl32/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y67 SRLC32E (Prop_srlc32e_CLK_Q31) 0.737 4.441 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[31]_srl32/Q31 net (fo=1, routed) 0.000 4.441 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[31]_srl32_n_1 SLICE_X90Y67 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/D ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_a rise edge) 8.333 8.333 r AH6 0.000 8.333 r ttc_mgt_xpoint_a_p (IN) net (fo=0) 0.000 8.333 ttc_mgt_xpoint_a_p AH6 IBUF (Prop_ibuf_I_O) 0.000 8.333 r ttc_mgt_xpoint_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.333 ngFEC/ttc_mgt_xpoint_a_p_IBUF IBUFDS_GTE2_X0Y3 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.751 r ngFEC/cdceOut1IbufdsAGtxe2/O net (fo=8, routed) 0.606 10.357 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y13 BUFH (Prop_bufh_I_O) 0.066 10.423 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.536 10.959 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y67 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK clock pessimism 1.078 12.037 clock uncertainty -0.035 12.001 SLICE_X90Y67 SRLC32E (Setup_srlc32e_CLK_D) -0.036 11.965 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32 ------------------------------------------------------------------- required time 11.965 arrival time -4.441 ------------------------------------------------------------------- slack 7.525 Slack (MET) : 7.525ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[31]_srl32/CLK (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/D (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: ttc_mgt_xpoint_a Path Type: Setup (Max at Slow Process Corner) Requirement: 8.333ns (ttc_mgt_xpoint_a rise@8.333ns - ttc_mgt_xpoint_a rise@0.000ns) Data Path Delay: 0.737ns (logic 0.737ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.623ns = ( 10.956 - 8.333 ) Source Clock Delay (SCD): 3.700ns Clock Pessimism Removal (CPR): 1.077ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_a rise edge) 0.000 0.000 r AH6 0.000 0.000 r ttc_mgt_xpoint_a_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_a_p AH6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_a_p_IBUF IBUFDS_GTE2_X0Y3 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r ngFEC/cdceOut1IbufdsAGtxe2/O net (fo=8, routed) 0.665 3.020 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y14 BUFH (Prop_bufh_I_O) 0.103 3.123 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.577 3.700 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X86Y78 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[31]_srl32/CLK ------------------------------------------------------------------- ------------------- SLICE_X86Y78 SRLC32E (Prop_srlc32e_CLK_Q31) 0.737 4.437 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[31]_srl32/Q31 net (fo=1, routed) 0.000 4.437 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[31]_srl32_n_1 SLICE_X86Y78 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/D ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_a rise edge) 8.333 8.333 r AH6 0.000 8.333 r ttc_mgt_xpoint_a_p (IN) net (fo=0) 0.000 8.333 ttc_mgt_xpoint_a_p AH6 IBUF (Prop_ibuf_I_O) 0.000 8.333 r ttc_mgt_xpoint_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.333 ngFEC/ttc_mgt_xpoint_a_p_IBUF IBUFDS_GTE2_X0Y3 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.751 r ngFEC/cdceOut1IbufdsAGtxe2/O net (fo=8, routed) 0.606 10.357 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y14 BUFH (Prop_bufh_I_O) 0.066 10.423 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.533 10.956 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X86Y78 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK clock pessimism 1.077 12.033 clock uncertainty -0.035 11.997 SLICE_X86Y78 SRLC32E (Setup_srlc32e_CLK_D) -0.036 11.961 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32 ------------------------------------------------------------------- required time 11.961 arrival time -4.437 ------------------------------------------------------------------- slack 7.525 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.172ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: ttc_mgt_xpoint_a Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ttc_mgt_xpoint_a rise@0.000ns - ttc_mgt_xpoint_a rise@0.000ns) Data Path Delay: 0.271ns (logic 0.271ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.436ns Source Clock Delay (SCD): 0.939ns Clock Pessimism Removal (CPR): 0.497ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_a rise edge) 0.000 0.000 r AH6 0.000 0.000 r ttc_mgt_xpoint_a_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_a_p AH6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_a_p_IBUF IBUFDS_GTE2_X0Y3 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r ngFEC/cdceOut1IbufdsAGtxe2/O net (fo=8, routed) 0.190 0.631 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y12 BUFH (Prop_bufh_I_O) 0.023 0.654 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.285 0.939 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y55 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y55 SRLC32E (Prop_srlc32e_CLK_Q31) 0.271 1.210 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/Q31 net (fo=1, routed) 0.000 1.210 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32_n_1 SLICE_X90Y55 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_a rise edge) 0.000 0.000 r AH6 0.000 0.000 r ttc_mgt_xpoint_a_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_a_p AH6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_a_p_IBUF IBUFDS_GTE2_X0Y3 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r ngFEC/cdceOut1IbufdsAGtxe2/O net (fo=8, routed) 0.221 0.953 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y12 BUFH (Prop_bufh_I_O) 0.045 0.998 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.438 1.436 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y55 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK clock pessimism -0.497 0.939 SLICE_X90Y55 SRLC32E (Hold_srlc32e_CLK_D) 0.099 1.038 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32 ------------------------------------------------------------------- required time -1.038 arrival time 1.210 ------------------------------------------------------------------- slack 0.172 Slack (MET) : 0.172ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/D (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: ttc_mgt_xpoint_a Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ttc_mgt_xpoint_a rise@0.000ns - ttc_mgt_xpoint_a rise@0.000ns) Data Path Delay: 0.271ns (logic 0.271ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.442ns Source Clock Delay (SCD): 0.945ns Clock Pessimism Removal (CPR): 0.497ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_a rise edge) 0.000 0.000 r AH6 0.000 0.000 r ttc_mgt_xpoint_a_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_a_p AH6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_a_p_IBUF IBUFDS_GTE2_X0Y3 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r ngFEC/cdceOut1IbufdsAGtxe2/O net (fo=8, routed) 0.190 0.631 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y12 BUFH (Prop_bufh_I_O) 0.023 0.654 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.291 0.945 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X84Y52 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK ------------------------------------------------------------------- ------------------- SLICE_X84Y52 SRLC32E (Prop_srlc32e_CLK_Q31) 0.271 1.216 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/Q31 net (fo=1, routed) 0.000 1.216 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32_n_1 SLICE_X84Y52 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/D ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_a rise edge) 0.000 0.000 r AH6 0.000 0.000 r ttc_mgt_xpoint_a_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_a_p AH6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_a_p_IBUF IBUFDS_GTE2_X0Y3 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r ngFEC/cdceOut1IbufdsAGtxe2/O net (fo=8, routed) 0.221 0.953 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y12 BUFH (Prop_bufh_I_O) 0.045 0.998 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.444 1.442 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X84Y52 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLK clock pessimism -0.497 0.945 SLICE_X84Y52 SRLC32E (Hold_srlc32e_CLK_D) 0.099 1.044 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32 ------------------------------------------------------------------- required time -1.044 arrival time 1.216 ------------------------------------------------------------------- slack 0.172 Slack (MET) : 0.172ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: ttc_mgt_xpoint_a Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ttc_mgt_xpoint_a rise@0.000ns - ttc_mgt_xpoint_a rise@0.000ns) Data Path Delay: 0.271ns (logic 0.271ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.429ns Source Clock Delay (SCD): 0.934ns Clock Pessimism Removal (CPR): 0.495ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_a rise edge) 0.000 0.000 r AH6 0.000 0.000 r ttc_mgt_xpoint_a_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_a_p AH6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_a_p_IBUF IBUFDS_GTE2_X0Y3 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r ngFEC/cdceOut1IbufdsAGtxe2/O net (fo=8, routed) 0.190 0.631 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y13 BUFH (Prop_bufh_I_O) 0.023 0.654 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.280 0.934 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y66 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y66 SRLC32E (Prop_srlc32e_CLK_Q31) 0.271 1.205 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/Q31 net (fo=1, routed) 0.000 1.205 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32_n_1 SLICE_X90Y66 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_a rise edge) 0.000 0.000 r AH6 0.000 0.000 r ttc_mgt_xpoint_a_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_a_p AH6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_a_p_IBUF IBUFDS_GTE2_X0Y3 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r ngFEC/cdceOut1IbufdsAGtxe2/O net (fo=8, routed) 0.221 0.953 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y13 BUFH (Prop_bufh_I_O) 0.045 0.998 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.431 1.429 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y66 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK clock pessimism -0.495 0.934 SLICE_X90Y66 SRLC32E (Hold_srlc32e_CLK_D) 0.099 1.033 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32 ------------------------------------------------------------------- required time -1.033 arrival time 1.205 ------------------------------------------------------------------- slack 0.172 Slack (MET) : 0.172ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: ttc_mgt_xpoint_a Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ttc_mgt_xpoint_a rise@0.000ns - ttc_mgt_xpoint_a rise@0.000ns) Data Path Delay: 0.271ns (logic 0.271ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.429ns Source Clock Delay (SCD): 0.934ns Clock Pessimism Removal (CPR): 0.495ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_a rise edge) 0.000 0.000 r AH6 0.000 0.000 r ttc_mgt_xpoint_a_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_a_p AH6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_a_p_IBUF IBUFDS_GTE2_X0Y3 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r ngFEC/cdceOut1IbufdsAGtxe2/O net (fo=8, routed) 0.190 0.631 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y14 BUFH (Prop_bufh_I_O) 0.023 0.654 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.280 0.934 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y83 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y83 SRLC32E (Prop_srlc32e_CLK_Q31) 0.271 1.205 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/Q31 net (fo=1, routed) 0.000 1.205 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32_n_1 SLICE_X90Y83 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_a rise edge) 0.000 0.000 r AH6 0.000 0.000 r ttc_mgt_xpoint_a_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_a_p AH6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_a_p_IBUF IBUFDS_GTE2_X0Y3 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r ngFEC/cdceOut1IbufdsAGtxe2/O net (fo=8, routed) 0.221 0.953 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y14 BUFH (Prop_bufh_I_O) 0.045 0.998 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.431 1.429 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y83 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK clock pessimism -0.495 0.934 SLICE_X90Y83 SRLC32E (Hold_srlc32e_CLK_D) 0.099 1.033 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32 ------------------------------------------------------------------- required time -1.033 arrival time 1.205 ------------------------------------------------------------------- slack 0.172 Slack (MET) : 0.172ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/D (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: ttc_mgt_xpoint_a Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ttc_mgt_xpoint_a rise@0.000ns - ttc_mgt_xpoint_a rise@0.000ns) Data Path Delay: 0.271ns (logic 0.271ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.426ns Source Clock Delay (SCD): 0.930ns Clock Pessimism Removal (CPR): 0.496ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_a rise edge) 0.000 0.000 r AH6 0.000 0.000 r ttc_mgt_xpoint_a_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_a_p AH6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_a_p_IBUF IBUFDS_GTE2_X0Y3 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r ngFEC/cdceOut1IbufdsAGtxe2/O net (fo=8, routed) 0.190 0.631 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y14 BUFH (Prop_bufh_I_O) 0.023 0.654 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.276 0.930 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X86Y78 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK ------------------------------------------------------------------- ------------------- SLICE_X86Y78 SRLC32E (Prop_srlc32e_CLK_Q31) 0.271 1.201 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/Q31 net (fo=1, routed) 0.000 1.201 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32_n_1 SLICE_X86Y78 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/D ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_a rise edge) 0.000 0.000 r AH6 0.000 0.000 r ttc_mgt_xpoint_a_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_a_p AH6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_a_p_IBUF IBUFDS_GTE2_X0Y3 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r ngFEC/cdceOut1IbufdsAGtxe2/O net (fo=8, routed) 0.221 0.953 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y14 BUFH (Prop_bufh_I_O) 0.045 0.998 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.428 1.426 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X86Y78 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLK clock pessimism -0.496 0.930 SLICE_X86Y78 SRLC32E (Hold_srlc32e_CLK_D) 0.099 1.029 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32 ------------------------------------------------------------------- required time -1.029 arrival time 1.201 ------------------------------------------------------------------- slack 0.172 Slack (MET) : 0.172ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: ttc_mgt_xpoint_a Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ttc_mgt_xpoint_a rise@0.000ns - ttc_mgt_xpoint_a rise@0.000ns) Data Path Delay: 0.271ns (logic 0.271ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.437ns Source Clock Delay (SCD): 0.940ns Clock Pessimism Removal (CPR): 0.497ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_a rise edge) 0.000 0.000 r AH6 0.000 0.000 r ttc_mgt_xpoint_a_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_a_p AH6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_a_p_IBUF IBUFDS_GTE2_X0Y3 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r ngFEC/cdceOut1IbufdsAGtxe2/O net (fo=8, routed) 0.190 0.631 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y15 BUFH (Prop_bufh_I_O) 0.023 0.654 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.286 0.940 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y97 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y97 SRLC32E (Prop_srlc32e_CLK_Q31) 0.271 1.211 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/Q31 net (fo=1, routed) 0.000 1.211 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32_n_1 SLICE_X90Y97 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_a rise edge) 0.000 0.000 r AH6 0.000 0.000 r ttc_mgt_xpoint_a_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_a_p AH6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_a_p_IBUF IBUFDS_GTE2_X0Y3 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r ngFEC/cdceOut1IbufdsAGtxe2/O net (fo=8, routed) 0.221 0.953 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y15 BUFH (Prop_bufh_I_O) 0.045 0.998 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.439 1.437 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y97 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK clock pessimism -0.497 0.940 SLICE_X90Y97 SRLC32E (Hold_srlc32e_CLK_D) 0.099 1.039 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32 ------------------------------------------------------------------- required time -1.039 arrival time 1.211 ------------------------------------------------------------------- slack 0.172 Slack (MET) : 0.172ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/D (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: ttc_mgt_xpoint_a Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ttc_mgt_xpoint_a rise@0.000ns - ttc_mgt_xpoint_a rise@0.000ns) Data Path Delay: 0.271ns (logic 0.271ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.435ns Source Clock Delay (SCD): 0.938ns Clock Pessimism Removal (CPR): 0.497ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_a rise edge) 0.000 0.000 r AH6 0.000 0.000 r ttc_mgt_xpoint_a_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_a_p AH6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_a_p_IBUF IBUFDS_GTE2_X0Y3 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r ngFEC/cdceOut1IbufdsAGtxe2/O net (fo=8, routed) 0.190 0.631 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y15 BUFH (Prop_bufh_I_O) 0.023 0.654 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.284 0.938 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y91 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y91 SRLC32E (Prop_srlc32e_CLK_Q31) 0.271 1.209 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/Q31 net (fo=1, routed) 0.000 1.209 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32_n_1 SLICE_X90Y91 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/D ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_a rise edge) 0.000 0.000 r AH6 0.000 0.000 r ttc_mgt_xpoint_a_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_a_p AH6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_a_p_IBUF IBUFDS_GTE2_X0Y3 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r ngFEC/cdceOut1IbufdsAGtxe2/O net (fo=8, routed) 0.221 0.953 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y15 BUFH (Prop_bufh_I_O) 0.045 0.998 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.437 1.435 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y91 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLK clock pessimism -0.497 0.938 SLICE_X90Y91 SRLC32E (Hold_srlc32e_CLK_D) 0.099 1.037 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32 ------------------------------------------------------------------- required time -1.037 arrival time 1.209 ------------------------------------------------------------------- slack 0.172 Slack (MET) : 0.172ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/D (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: ttc_mgt_xpoint_a Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ttc_mgt_xpoint_a rise@0.000ns - ttc_mgt_xpoint_a rise@0.000ns) Data Path Delay: 0.271ns (logic 0.271ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.428ns Source Clock Delay (SCD): 0.933ns Clock Pessimism Removal (CPR): 0.495ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_a rise edge) 0.000 0.000 r AH6 0.000 0.000 r ttc_mgt_xpoint_a_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_a_p AH6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_a_p_IBUF IBUFDS_GTE2_X0Y3 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r ngFEC/cdceOut1IbufdsAGtxe2/O net (fo=8, routed) 0.190 0.631 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y13 BUFH (Prop_bufh_I_O) 0.023 0.654 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.279 0.933 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y67 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y67 SRLC32E (Prop_srlc32e_CLK_Q31) 0.271 1.204 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/Q31 net (fo=1, routed) 0.000 1.204 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32_n_1 SLICE_X90Y67 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/D ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_a rise edge) 0.000 0.000 r AH6 0.000 0.000 r ttc_mgt_xpoint_a_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_a_p AH6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_a_p_IBUF IBUFDS_GTE2_X0Y3 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r ngFEC/cdceOut1IbufdsAGtxe2/O net (fo=8, routed) 0.221 0.953 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y13 BUFH (Prop_bufh_I_O) 0.045 0.998 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.430 1.428 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y67 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLK clock pessimism -0.495 0.933 SLICE_X90Y67 SRLC32E (Hold_srlc32e_CLK_D) 0.099 1.032 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32 ------------------------------------------------------------------- required time -1.032 arrival time 1.204 ------------------------------------------------------------------- slack 0.172 Slack (MET) : 0.174ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLK (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/D (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: ttc_mgt_xpoint_a Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ttc_mgt_xpoint_a rise@0.000ns - ttc_mgt_xpoint_a rise@0.000ns) Data Path Delay: 0.276ns (logic 0.276ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.426ns Source Clock Delay (SCD): 0.930ns Clock Pessimism Removal (CPR): 0.496ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_a rise edge) 0.000 0.000 r AH6 0.000 0.000 r ttc_mgt_xpoint_a_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_a_p AH6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_a_p_IBUF IBUFDS_GTE2_X0Y3 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r ngFEC/cdceOut1IbufdsAGtxe2/O net (fo=8, routed) 0.190 0.631 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y14 BUFH (Prop_bufh_I_O) 0.023 0.654 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.276 0.930 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X86Y78 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLK ------------------------------------------------------------------- ------------------- SLICE_X86Y78 SRLC32E (Prop_srlc32e_CLK_Q31) 0.276 1.206 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/Q31 net (fo=1, routed) 0.000 1.206 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32_n_1 SLICE_X86Y78 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/D ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_a rise edge) 0.000 0.000 r AH6 0.000 0.000 r ttc_mgt_xpoint_a_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_a_p AH6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_a_p_IBUF IBUFDS_GTE2_X0Y3 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r ngFEC/cdceOut1IbufdsAGtxe2/O net (fo=8, routed) 0.221 0.953 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y14 BUFH (Prop_bufh_I_O) 0.045 0.998 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.428 1.426 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X86Y78 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK clock pessimism -0.496 0.930 SLICE_X86Y78 SRLC32E (Hold_srlc32e_CLK_D) 0.102 1.032 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31 ------------------------------------------------------------------- required time -1.032 arrival time 1.206 ------------------------------------------------------------------- slack 0.174 Slack (MET) : 0.174ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/D (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_a {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: ttc_mgt_xpoint_a Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ttc_mgt_xpoint_a rise@0.000ns - ttc_mgt_xpoint_a rise@0.000ns) Data Path Delay: 0.276ns (logic 0.276ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.436ns Source Clock Delay (SCD): 0.939ns Clock Pessimism Removal (CPR): 0.497ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_a rise edge) 0.000 0.000 r AH6 0.000 0.000 r ttc_mgt_xpoint_a_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_a_p AH6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_a_p_IBUF IBUFDS_GTE2_X0Y3 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r ngFEC/cdceOut1IbufdsAGtxe2/O net (fo=8, routed) 0.190 0.631 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y12 BUFH (Prop_bufh_I_O) 0.023 0.654 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.285 0.939 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y55 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y55 SRLC32E (Prop_srlc32e_CLK_Q31) 0.276 1.215 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/Q31 net (fo=1, routed) 0.000 1.215 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32_n_1 SLICE_X90Y55 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/D ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_a rise edge) 0.000 0.000 r AH6 0.000 0.000 r ttc_mgt_xpoint_a_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_a_p AH6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_a_p_IBUF IBUFDS_GTE2_X0Y3 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r ngFEC/cdceOut1IbufdsAGtxe2/O net (fo=8, routed) 0.221 0.953 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y12 BUFH (Prop_bufh_I_O) 0.045 0.998 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.438 1.436 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y55 SRLC32E r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK clock pessimism -0.497 0.939 SLICE_X90Y55 SRLC32E (Hold_srlc32e_CLK_D) 0.102 1.041 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31 ------------------------------------------------------------------- required time -1.041 arrival time 1.215 ------------------------------------------------------------------- slack 0.174 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ttc_mgt_xpoint_a Waveform(ns): { 0.000 4.167 } Period(ns): 8.333 Sources: { ttc_mgt_xpoint_a_p } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/GTREFCLK1 n/a 1.538 8.333 6.795 GTXE2_CHANNEL_X0Y4 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK1 Min Period n/a GTXE2_CHANNEL/GTREFCLK1 n/a 1.538 8.333 6.795 GTXE2_CHANNEL_X0Y5 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK1 Min Period n/a GTXE2_CHANNEL/GTREFCLK1 n/a 1.538 8.333 6.795 GTXE2_CHANNEL_X0Y6 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK1 Min Period n/a GTXE2_CHANNEL/GTREFCLK1 n/a 1.538 8.333 6.795 GTXE2_CHANNEL_X0Y7 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK1 Min Period n/a BUFH/I n/a 1.409 8.333 6.925 BUFHCE_X0Y12 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I Min Period n/a BUFH/I n/a 1.409 8.333 6.925 BUFHCE_X0Y13 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I Min Period n/a BUFH/I n/a 1.409 8.333 6.925 BUFHCE_X0Y14 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I Min Period n/a BUFH/I n/a 1.409 8.333 6.925 BUFHCE_X0Y15 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I Min Period n/a IBUFDS_GTE2/I n/a 1.408 8.333 6.925 IBUFDS_GTE2_X0Y3 ngFEC/cdceOut1IbufdsAGtxe2/I Min Period n/a FDRE/C n/a 0.700 8.333 7.633 SLICE_X90Y55 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/C Low Pulse Width Fast SRLC32E/CLK n/a 0.642 4.166 3.524 SLICE_X90Y55 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK Low Pulse Width Fast SRLC32E/CLK n/a 0.642 4.166 3.524 SLICE_X90Y55 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK Low Pulse Width Fast SRLC32E/CLK n/a 0.642 4.166 3.524 SLICE_X90Y55 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK Low Pulse Width Fast SRLC32E/CLK n/a 0.642 4.166 3.524 SLICE_X90Y97 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK Low Pulse Width Fast SRLC32E/CLK n/a 0.642 4.166 3.524 SLICE_X90Y97 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK Low Pulse Width Fast SRLC32E/CLK n/a 0.642 4.166 3.524 SLICE_X90Y97 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK Low Pulse Width Fast SRLC32E/CLK n/a 0.642 4.166 3.524 SLICE_X90Y66 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK Low Pulse Width Fast SRLC32E/CLK n/a 0.642 4.166 3.524 SLICE_X90Y66 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK Low Pulse Width Fast SRLC32E/CLK n/a 0.642 4.166 3.524 SLICE_X90Y66 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK Low Pulse Width Fast SRLC32E/CLK n/a 0.642 4.166 3.524 SLICE_X90Y67 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK High Pulse Width Slow SRLC32E/CLK n/a 0.642 4.166 3.524 SLICE_X90Y55 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK High Pulse Width Slow SRLC32E/CLK n/a 0.642 4.166 3.524 SLICE_X90Y55 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK High Pulse Width Slow SRLC32E/CLK n/a 0.642 4.166 3.524 SLICE_X90Y55 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK High Pulse Width Slow SRLC32E/CLK n/a 0.642 4.166 3.524 SLICE_X90Y66 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK High Pulse Width Slow SRLC32E/CLK n/a 0.642 4.166 3.524 SLICE_X90Y66 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK High Pulse Width Slow SRLC32E/CLK n/a 0.642 4.166 3.524 SLICE_X90Y66 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK High Pulse Width Slow SRLC32E/CLK n/a 0.642 4.166 3.524 SLICE_X90Y67 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK High Pulse Width Slow SRLC32E/CLK n/a 0.642 4.166 3.524 SLICE_X90Y67 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[31]_srl32/CLK High Pulse Width Slow SRLC32E/CLK n/a 0.642 4.166 3.524 SLICE_X90Y67 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK High Pulse Width Slow SRLC32E/CLK n/a 0.642 4.166 3.524 SLICE_X90Y67 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLK --------------------------------------------------------------------------------------------------- From Clock: ttc_mgt_xpoint_c To Clock: ttc_mgt_xpoint_c Setup : 0 Failing Endpoints, Worst Slack 2.779ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.172ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.524ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 2.779ns (required time - arrival time) Source: ngFEC/phmon/neg_cnt_reg[1]/C (falling edge-triggered cell FDRE clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: ngFEC/phmon/pos_cnt_reg[1]/D (rising edge-triggered cell FDRE clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: ttc_mgt_xpoint_c Path Type: Setup (Max at Slow Process Corner) Requirement: 4.167ns (ttc_mgt_xpoint_c rise@8.333ns - ttc_mgt_xpoint_c fall@4.167ns) Data Path Delay: 1.213ns (logic 0.342ns (28.187%) route 0.871ns (71.813%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: -0.025ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.725ns = ( 11.058 - 8.333 ) Source Clock Delay (SCD): 3.808ns = ( 7.974 - 4.167 ) Clock Pessimism Removal (CPR): 1.058ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_c fall edge) 4.167 4.167 f G8 0.000 4.167 f ttc_mgt_xpoint_c_p (IN) net (fo=0) 0.000 4.167 ttc_mgt_xpoint_c_p G8 IBUF (Prop_ibuf_I_O) 0.000 4.167 f ttc_mgt_xpoint_c_p_IBUF_inst/O net (fo=1, routed) 0.000 4.167 ngFEC/ttc_mgt_xpoint_c_p_IBUF IBUFDS_GTE2_X0Y13 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 6.522 f ngFEC/cdceOut0IbufdsCGtxe2/O net (fo=17, routed) 0.666 7.187 ngFEC/ttcMgtXpoint_from_ibufdsCGtxe2 BUFHCE_X1Y74 BUFH (Prop_bufh_I_O) 0.103 7.290 f ngFEC/i_ttcMgtXpoint_from_ibufdsCGtxe2_buf/O net (fo=7, routed) 0.684 7.974 ngFEC/phmon/ttcMgtXpoint_from_ibufdsCGtxe2_buf SLICE_X135Y346 FDRE r ngFEC/phmon/neg_cnt_reg[1]/C (IS_INVERTED) ------------------------------------------------------------------- ------------------- SLICE_X135Y346 FDRE (Prop_fdre_C_Q) 0.209 8.183 r ngFEC/phmon/neg_cnt_reg[1]/Q net (fo=4, routed) 0.593 8.777 ngFEC/phmon/neg_cnt[1] SLICE_X135Y350 LUT5 (Prop_lut5_I3_O) 0.133 8.910 r ngFEC/phmon/pos_cnt[1]_i_1/O net (fo=1, routed) 0.278 9.188 ngFEC/phmon/pos_cnt[1]_i_1_n_0 SLICE_X135Y349 FDRE r ngFEC/phmon/pos_cnt_reg[1]/D ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_c rise edge) 8.333 8.333 r G8 0.000 8.333 r ttc_mgt_xpoint_c_p (IN) net (fo=0) 0.000 8.333 ttc_mgt_xpoint_c_p G8 IBUF (Prop_ibuf_I_O) 0.000 8.333 r ttc_mgt_xpoint_c_p_IBUF_inst/O net (fo=1, routed) 0.000 8.333 ngFEC/ttc_mgt_xpoint_c_p_IBUF IBUFDS_GTE2_X0Y13 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.751 r ngFEC/cdceOut0IbufdsCGtxe2/O net (fo=17, routed) 0.607 10.358 ngFEC/ttcMgtXpoint_from_ibufdsCGtxe2 BUFHCE_X1Y74 BUFH (Prop_bufh_I_O) 0.066 10.424 r ngFEC/i_ttcMgtXpoint_from_ibufdsCGtxe2_buf/O net (fo=7, routed) 0.634 11.058 ngFEC/phmon/ttcMgtXpoint_from_ibufdsCGtxe2_buf SLICE_X135Y349 FDRE r ngFEC/phmon/pos_cnt_reg[1]/C clock pessimism 1.058 12.116 clock uncertainty -0.035 12.080 SLICE_X135Y349 FDRE (Setup_fdre_C_D) -0.114 11.966 ngFEC/phmon/pos_cnt_reg[1] ------------------------------------------------------------------- required time 11.966 arrival time -9.188 ------------------------------------------------------------------- slack 2.779 Slack (MET) : 2.948ns (required time - arrival time) Source: ngFEC/phmon/neg_cnt_reg[1]/C (falling edge-triggered cell FDRE clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: ngFEC/phmon/pos_cnt_reg[0]/D (rising edge-triggered cell FDRE clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: ttc_mgt_xpoint_c Path Type: Setup (Max at Slow Process Corner) Requirement: 4.167ns (ttc_mgt_xpoint_c rise@8.333ns - ttc_mgt_xpoint_c fall@4.167ns) Data Path Delay: 1.191ns (logic 0.332ns (27.876%) route 0.859ns (72.124%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: -0.025ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.725ns = ( 11.058 - 8.333 ) Source Clock Delay (SCD): 3.808ns = ( 7.974 - 4.167 ) Clock Pessimism Removal (CPR): 1.058ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_c fall edge) 4.167 4.167 f G8 0.000 4.167 f ttc_mgt_xpoint_c_p (IN) net (fo=0) 0.000 4.167 ttc_mgt_xpoint_c_p G8 IBUF (Prop_ibuf_I_O) 0.000 4.167 f ttc_mgt_xpoint_c_p_IBUF_inst/O net (fo=1, routed) 0.000 4.167 ngFEC/ttc_mgt_xpoint_c_p_IBUF IBUFDS_GTE2_X0Y13 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 6.522 f ngFEC/cdceOut0IbufdsCGtxe2/O net (fo=17, routed) 0.666 7.187 ngFEC/ttcMgtXpoint_from_ibufdsCGtxe2 BUFHCE_X1Y74 BUFH (Prop_bufh_I_O) 0.103 7.290 f ngFEC/i_ttcMgtXpoint_from_ibufdsCGtxe2_buf/O net (fo=7, routed) 0.684 7.974 ngFEC/phmon/ttcMgtXpoint_from_ibufdsCGtxe2_buf SLICE_X135Y346 FDRE r ngFEC/phmon/neg_cnt_reg[1]/C (IS_INVERTED) ------------------------------------------------------------------- ------------------- SLICE_X135Y346 FDRE (Prop_fdre_C_Q) 0.209 8.183 r ngFEC/phmon/neg_cnt_reg[1]/Q net (fo=4, routed) 0.859 9.042 ngFEC/phmon/neg_cnt[1] SLICE_X135Y347 LUT4 (Prop_lut4_I2_O) 0.123 9.165 r ngFEC/phmon/pos_cnt[0]_i_1/O net (fo=1, routed) 0.000 9.165 ngFEC/phmon/pos_cnt[0]_i_1_n_0 SLICE_X135Y347 FDRE r ngFEC/phmon/pos_cnt_reg[0]/D ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_c rise edge) 8.333 8.333 r G8 0.000 8.333 r ttc_mgt_xpoint_c_p (IN) net (fo=0) 0.000 8.333 ttc_mgt_xpoint_c_p G8 IBUF (Prop_ibuf_I_O) 0.000 8.333 r ttc_mgt_xpoint_c_p_IBUF_inst/O net (fo=1, routed) 0.000 8.333 ngFEC/ttc_mgt_xpoint_c_p_IBUF IBUFDS_GTE2_X0Y13 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.751 r ngFEC/cdceOut0IbufdsCGtxe2/O net (fo=17, routed) 0.607 10.358 ngFEC/ttcMgtXpoint_from_ibufdsCGtxe2 BUFHCE_X1Y74 BUFH (Prop_bufh_I_O) 0.066 10.424 r ngFEC/i_ttcMgtXpoint_from_ibufdsCGtxe2_buf/O net (fo=7, routed) 0.634 11.058 ngFEC/phmon/ttcMgtXpoint_from_ibufdsCGtxe2_buf SLICE_X135Y347 FDRE r ngFEC/phmon/pos_cnt_reg[0]/C clock pessimism 1.058 12.116 clock uncertainty -0.035 12.080 SLICE_X135Y347 FDRE (Setup_fdre_C_D) 0.033 12.113 ngFEC/phmon/pos_cnt_reg[0] ------------------------------------------------------------------- required time 12.113 arrival time -9.165 ------------------------------------------------------------------- slack 2.948 Slack (MET) : 7.362ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/D (rising edge-triggered cell FDRE clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: ttc_mgt_xpoint_c Path Type: Setup (Max at Slow Process Corner) Requirement: 8.333ns (ttc_mgt_xpoint_c rise@8.333ns - ttc_mgt_xpoint_c rise@0.000ns) Data Path Delay: 1.000ns (logic 1.000ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.639ns = ( 10.972 - 8.333 ) Source Clock Delay (SCD): 3.720ns Clock Pessimism Removal (CPR): 1.081ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_c rise edge) 0.000 0.000 r G8 0.000 0.000 r ttc_mgt_xpoint_c_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_c_p G8 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_c_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_c_p_IBUF IBUFDS_GTE2_X0Y13 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r ngFEC/cdceOut0IbufdsCGtxe2/O net (fo=17, routed) 0.666 3.021 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y74 BUFH (Prop_bufh_I_O) 0.103 3.124 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.596 3.720 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X84Y349 SRLC32E r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK ------------------------------------------------------------------- ------------------- SLICE_X84Y349 SRLC32E (Prop_srlc32e_CLK_Q) 1.000 4.720 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/Q net (fo=1, routed) 0.000 4.720 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31_n_0 SLICE_X84Y349 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/D ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_c rise edge) 8.333 8.333 r G8 0.000 8.333 r ttc_mgt_xpoint_c_p (IN) net (fo=0) 0.000 8.333 ttc_mgt_xpoint_c_p G8 IBUF (Prop_ibuf_I_O) 0.000 8.333 r ttc_mgt_xpoint_c_p_IBUF_inst/O net (fo=1, routed) 0.000 8.333 ngFEC/ttc_mgt_xpoint_c_p_IBUF IBUFDS_GTE2_X0Y13 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.751 r ngFEC/cdceOut0IbufdsCGtxe2/O net (fo=17, routed) 0.607 10.358 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y74 BUFH (Prop_bufh_I_O) 0.066 10.424 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.548 10.972 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X84Y349 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/C clock pessimism 1.081 12.053 clock uncertainty -0.035 12.017 SLICE_X84Y349 FDRE (Setup_fdre_C_D) 0.064 12.081 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95] ------------------------------------------------------------------- required time 12.081 arrival time -4.720 ------------------------------------------------------------------- slack 7.362 Slack (MET) : 7.362ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/D (rising edge-triggered cell FDRE clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: ttc_mgt_xpoint_c Path Type: Setup (Max at Slow Process Corner) Requirement: 8.333ns (ttc_mgt_xpoint_c rise@8.333ns - ttc_mgt_xpoint_c rise@0.000ns) Data Path Delay: 1.000ns (logic 1.000ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.628ns = ( 10.961 - 8.333 ) Source Clock Delay (SCD): 3.706ns Clock Pessimism Removal (CPR): 1.078ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_c rise edge) 0.000 0.000 r G8 0.000 0.000 r ttc_mgt_xpoint_c_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_c_p G8 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_c_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_c_p_IBUF IBUFDS_GTE2_X0Y13 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r ngFEC/cdceOut0IbufdsCGtxe2/O net (fo=17, routed) 0.666 3.021 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y75 BUFH (Prop_bufh_I_O) 0.103 3.124 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.582 3.706 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y316 SRLC32E r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y316 SRLC32E (Prop_srlc32e_CLK_Q) 1.000 4.706 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/Q net (fo=1, routed) 0.000 4.706 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31_n_0 SLICE_X90Y316 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/D ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_c rise edge) 8.333 8.333 r G8 0.000 8.333 r ttc_mgt_xpoint_c_p (IN) net (fo=0) 0.000 8.333 ttc_mgt_xpoint_c_p G8 IBUF (Prop_ibuf_I_O) 0.000 8.333 r ttc_mgt_xpoint_c_p_IBUF_inst/O net (fo=1, routed) 0.000 8.333 ngFEC/ttc_mgt_xpoint_c_p_IBUF IBUFDS_GTE2_X0Y13 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.751 r ngFEC/cdceOut0IbufdsCGtxe2/O net (fo=17, routed) 0.607 10.358 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y75 BUFH (Prop_bufh_I_O) 0.066 10.424 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.537 10.961 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y316 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/C clock pessimism 1.078 12.039 clock uncertainty -0.035 12.003 SLICE_X90Y316 FDRE (Setup_fdre_C_D) 0.064 12.067 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95] ------------------------------------------------------------------- required time 12.067 arrival time -4.706 ------------------------------------------------------------------- slack 7.362 Slack (MET) : 7.362ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/D (rising edge-triggered cell FDRE clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: ttc_mgt_xpoint_c Path Type: Setup (Max at Slow Process Corner) Requirement: 8.333ns (ttc_mgt_xpoint_c rise@8.333ns - ttc_mgt_xpoint_c rise@0.000ns) Data Path Delay: 1.000ns (logic 1.000ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.629ns = ( 10.962 - 8.333 ) Source Clock Delay (SCD): 3.707ns Clock Pessimism Removal (CPR): 1.078ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_c rise edge) 0.000 0.000 r G8 0.000 0.000 r ttc_mgt_xpoint_c_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_c_p G8 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_c_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_c_p_IBUF IBUFDS_GTE2_X0Y13 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r ngFEC/cdceOut0IbufdsCGtxe2/O net (fo=17, routed) 0.666 3.021 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y75 BUFH (Prop_bufh_I_O) 0.103 3.124 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.583 3.707 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y315 SRLC32E r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y315 SRLC32E (Prop_srlc32e_CLK_Q) 1.000 4.707 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/Q net (fo=1, routed) 0.000 4.707 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31_n_0 SLICE_X90Y315 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/D ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_c rise edge) 8.333 8.333 r G8 0.000 8.333 r ttc_mgt_xpoint_c_p (IN) net (fo=0) 0.000 8.333 ttc_mgt_xpoint_c_p G8 IBUF (Prop_ibuf_I_O) 0.000 8.333 r ttc_mgt_xpoint_c_p_IBUF_inst/O net (fo=1, routed) 0.000 8.333 ngFEC/ttc_mgt_xpoint_c_p_IBUF IBUFDS_GTE2_X0Y13 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.751 r ngFEC/cdceOut0IbufdsCGtxe2/O net (fo=17, routed) 0.607 10.358 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y75 BUFH (Prop_bufh_I_O) 0.066 10.424 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.538 10.962 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y315 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/C clock pessimism 1.078 12.040 clock uncertainty -0.035 12.004 SLICE_X90Y315 FDRE (Setup_fdre_C_D) 0.064 12.068 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127] ------------------------------------------------------------------- required time 12.068 arrival time -4.707 ------------------------------------------------------------------- slack 7.362 Slack (MET) : 7.362ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/D (rising edge-triggered cell FDRE clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: ttc_mgt_xpoint_c Path Type: Setup (Max at Slow Process Corner) Requirement: 8.333ns (ttc_mgt_xpoint_c rise@8.333ns - ttc_mgt_xpoint_c rise@0.000ns) Data Path Delay: 1.000ns (logic 1.000ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.639ns = ( 10.972 - 8.333 ) Source Clock Delay (SCD): 3.720ns Clock Pessimism Removal (CPR): 1.081ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_c rise edge) 0.000 0.000 r G8 0.000 0.000 r ttc_mgt_xpoint_c_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_c_p G8 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_c_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_c_p_IBUF IBUFDS_GTE2_X0Y13 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r ngFEC/cdceOut0IbufdsCGtxe2/O net (fo=17, routed) 0.666 3.021 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y79 BUFH (Prop_bufh_I_O) 0.103 3.124 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.596 3.720 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X84Y300 SRLC32E r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK ------------------------------------------------------------------- ------------------- SLICE_X84Y300 SRLC32E (Prop_srlc32e_CLK_Q) 1.000 4.720 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/Q net (fo=1, routed) 0.000 4.720 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31_n_0 SLICE_X84Y300 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/D ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_c rise edge) 8.333 8.333 r G8 0.000 8.333 r ttc_mgt_xpoint_c_p (IN) net (fo=0) 0.000 8.333 ttc_mgt_xpoint_c_p G8 IBUF (Prop_ibuf_I_O) 0.000 8.333 r ttc_mgt_xpoint_c_p_IBUF_inst/O net (fo=1, routed) 0.000 8.333 ngFEC/ttc_mgt_xpoint_c_p_IBUF IBUFDS_GTE2_X0Y13 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.751 r ngFEC/cdceOut0IbufdsCGtxe2/O net (fo=17, routed) 0.607 10.358 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y79 BUFH (Prop_bufh_I_O) 0.066 10.424 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.548 10.972 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X84Y300 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/C clock pessimism 1.081 12.053 clock uncertainty -0.035 12.017 SLICE_X84Y300 FDRE (Setup_fdre_C_D) 0.064 12.081 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127] ------------------------------------------------------------------- required time 12.081 arrival time -4.720 ------------------------------------------------------------------- slack 7.362 Slack (MET) : 7.362ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/D (rising edge-triggered cell FDRE clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: ttc_mgt_xpoint_c Path Type: Setup (Max at Slow Process Corner) Requirement: 8.333ns (ttc_mgt_xpoint_c rise@8.333ns - ttc_mgt_xpoint_c rise@0.000ns) Data Path Delay: 1.000ns (logic 1.000ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.635ns = ( 10.968 - 8.333 ) Source Clock Delay (SCD): 3.715ns Clock Pessimism Removal (CPR): 1.080ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_c rise edge) 0.000 0.000 r G8 0.000 0.000 r ttc_mgt_xpoint_c_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_c_p G8 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_c_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_c_p_IBUF IBUFDS_GTE2_X0Y13 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r ngFEC/cdceOut0IbufdsCGtxe2/O net (fo=17, routed) 0.666 3.021 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y72 BUFH (Prop_bufh_I_O) 0.103 3.124 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.591 3.715 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y344 SRLC32E r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y344 SRLC32E (Prop_srlc32e_CLK_Q) 1.000 4.715 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/Q net (fo=1, routed) 0.000 4.715 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31_n_0 SLICE_X90Y344 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/D ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_c rise edge) 8.333 8.333 r G8 0.000 8.333 r ttc_mgt_xpoint_c_p (IN) net (fo=0) 0.000 8.333 ttc_mgt_xpoint_c_p G8 IBUF (Prop_ibuf_I_O) 0.000 8.333 r ttc_mgt_xpoint_c_p_IBUF_inst/O net (fo=1, routed) 0.000 8.333 ngFEC/ttc_mgt_xpoint_c_p_IBUF IBUFDS_GTE2_X0Y13 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.751 r ngFEC/cdceOut0IbufdsCGtxe2/O net (fo=17, routed) 0.607 10.358 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y72 BUFH (Prop_bufh_I_O) 0.066 10.424 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.544 10.968 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y344 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/C clock pessimism 1.080 12.048 clock uncertainty -0.035 12.012 SLICE_X90Y344 FDRE (Setup_fdre_C_D) 0.064 12.076 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127] ------------------------------------------------------------------- required time 12.076 arrival time -4.715 ------------------------------------------------------------------- slack 7.362 Slack (MET) : 7.362ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/D (rising edge-triggered cell FDRE clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: ttc_mgt_xpoint_c Path Type: Setup (Max at Slow Process Corner) Requirement: 8.333ns (ttc_mgt_xpoint_c rise@8.333ns - ttc_mgt_xpoint_c rise@0.000ns) Data Path Delay: 1.000ns (logic 1.000ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.635ns = ( 10.968 - 8.333 ) Source Clock Delay (SCD): 3.715ns Clock Pessimism Removal (CPR): 1.080ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_c rise edge) 0.000 0.000 r G8 0.000 0.000 r ttc_mgt_xpoint_c_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_c_p G8 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_c_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_c_p_IBUF IBUFDS_GTE2_X0Y13 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r ngFEC/cdceOut0IbufdsCGtxe2/O net (fo=17, routed) 0.666 3.021 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y73 BUFH (Prop_bufh_I_O) 0.103 3.124 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.591 3.715 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y349 SRLC32E r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y349 SRLC32E (Prop_srlc32e_CLK_Q) 1.000 4.715 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/Q net (fo=1, routed) 0.000 4.715 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31_n_0 SLICE_X90Y349 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/D ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_c rise edge) 8.333 8.333 r G8 0.000 8.333 r ttc_mgt_xpoint_c_p (IN) net (fo=0) 0.000 8.333 ttc_mgt_xpoint_c_p G8 IBUF (Prop_ibuf_I_O) 0.000 8.333 r ttc_mgt_xpoint_c_p_IBUF_inst/O net (fo=1, routed) 0.000 8.333 ngFEC/ttc_mgt_xpoint_c_p_IBUF IBUFDS_GTE2_X0Y13 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.751 r ngFEC/cdceOut0IbufdsCGtxe2/O net (fo=17, routed) 0.607 10.358 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y73 BUFH (Prop_bufh_I_O) 0.066 10.424 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.544 10.968 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y349 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/C clock pessimism 1.080 12.048 clock uncertainty -0.035 12.012 SLICE_X90Y349 FDRE (Setup_fdre_C_D) 0.064 12.076 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127] ------------------------------------------------------------------- required time 12.076 arrival time -4.715 ------------------------------------------------------------------- slack 7.362 Slack (MET) : 7.362ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/D (rising edge-triggered cell FDRE clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: ttc_mgt_xpoint_c Path Type: Setup (Max at Slow Process Corner) Requirement: 8.333ns (ttc_mgt_xpoint_c rise@8.333ns - ttc_mgt_xpoint_c rise@0.000ns) Data Path Delay: 1.000ns (logic 1.000ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.635ns = ( 10.968 - 8.333 ) Source Clock Delay (SCD): 3.715ns Clock Pessimism Removal (CPR): 1.080ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_c rise edge) 0.000 0.000 r G8 0.000 0.000 r ttc_mgt_xpoint_c_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_c_p G8 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_c_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_c_p_IBUF IBUFDS_GTE2_X0Y13 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r ngFEC/cdceOut0IbufdsCGtxe2/O net (fo=17, routed) 0.666 3.021 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y74 BUFH (Prop_bufh_I_O) 0.103 3.124 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.591 3.715 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y348 SRLC32E r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y348 SRLC32E (Prop_srlc32e_CLK_Q) 1.000 4.715 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/Q net (fo=1, routed) 0.000 4.715 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31_n_0 SLICE_X90Y348 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/D ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_c rise edge) 8.333 8.333 r G8 0.000 8.333 r ttc_mgt_xpoint_c_p (IN) net (fo=0) 0.000 8.333 ttc_mgt_xpoint_c_p G8 IBUF (Prop_ibuf_I_O) 0.000 8.333 r ttc_mgt_xpoint_c_p_IBUF_inst/O net (fo=1, routed) 0.000 8.333 ngFEC/ttc_mgt_xpoint_c_p_IBUF IBUFDS_GTE2_X0Y13 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.751 r ngFEC/cdceOut0IbufdsCGtxe2/O net (fo=17, routed) 0.607 10.358 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y74 BUFH (Prop_bufh_I_O) 0.066 10.424 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.544 10.968 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y348 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127]/C clock pessimism 1.080 12.048 clock uncertainty -0.035 12.012 SLICE_X90Y348 FDRE (Setup_fdre_C_D) 0.064 12.076 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[127] ------------------------------------------------------------------- required time 12.076 arrival time -4.715 ------------------------------------------------------------------- slack 7.362 Slack (MET) : 7.362ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/D (rising edge-triggered cell FDRE clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: ttc_mgt_xpoint_c Path Type: Setup (Max at Slow Process Corner) Requirement: 8.333ns (ttc_mgt_xpoint_c rise@8.333ns - ttc_mgt_xpoint_c rise@0.000ns) Data Path Delay: 1.000ns (logic 1.000ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 2.635ns = ( 10.968 - 8.333 ) Source Clock Delay (SCD): 3.715ns Clock Pessimism Removal (CPR): 1.080ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_c rise edge) 0.000 0.000 r G8 0.000 0.000 r ttc_mgt_xpoint_c_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_c_p G8 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_c_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_c_p_IBUF IBUFDS_GTE2_X0Y13 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r ngFEC/cdceOut0IbufdsCGtxe2/O net (fo=17, routed) 0.666 3.021 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y76 BUFH (Prop_bufh_I_O) 0.103 3.124 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.591 3.715 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y305 SRLC32E r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y305 SRLC32E (Prop_srlc32e_CLK_Q) 1.000 4.715 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/Q net (fo=1, routed) 0.000 4.715 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31_n_0 SLICE_X90Y305 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/D ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_c rise edge) 8.333 8.333 r G8 0.000 8.333 r ttc_mgt_xpoint_c_p (IN) net (fo=0) 0.000 8.333 ttc_mgt_xpoint_c_p G8 IBUF (Prop_ibuf_I_O) 0.000 8.333 r ttc_mgt_xpoint_c_p_IBUF_inst/O net (fo=1, routed) 0.000 8.333 ngFEC/ttc_mgt_xpoint_c_p_IBUF IBUFDS_GTE2_X0Y13 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.751 r ngFEC/cdceOut0IbufdsCGtxe2/O net (fo=17, routed) 0.607 10.358 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y76 BUFH (Prop_bufh_I_O) 0.066 10.424 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.544 10.968 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y305 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95]/C clock pessimism 1.080 12.048 clock uncertainty -0.035 12.012 SLICE_X90Y305 FDRE (Setup_fdre_C_D) 0.064 12.076 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[95] ------------------------------------------------------------------- required time 12.076 arrival time -4.715 ------------------------------------------------------------------- slack 7.362 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.172ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: ttc_mgt_xpoint_c Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ttc_mgt_xpoint_c rise@0.000ns - ttc_mgt_xpoint_c rise@0.000ns) Data Path Delay: 0.271ns (logic 0.271ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.440ns Source Clock Delay (SCD): 0.942ns Clock Pessimism Removal (CPR): 0.498ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_c rise edge) 0.000 0.000 r G8 0.000 0.000 r ttc_mgt_xpoint_c_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_c_p G8 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_c_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_c_p_IBUF IBUFDS_GTE2_X0Y13 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r ngFEC/cdceOut0IbufdsCGtxe2/O net (fo=17, routed) 0.191 0.632 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y72 BUFH (Prop_bufh_I_O) 0.023 0.655 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.287 0.942 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X86Y349 SRLC32E r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK ------------------------------------------------------------------- ------------------- SLICE_X86Y349 SRLC32E (Prop_srlc32e_CLK_Q31) 0.271 1.213 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/Q31 net (fo=1, routed) 0.000 1.213 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32_n_1 SLICE_X86Y349 SRLC32E r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_c rise edge) 0.000 0.000 r G8 0.000 0.000 r ttc_mgt_xpoint_c_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_c_p G8 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_c_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_c_p_IBUF IBUFDS_GTE2_X0Y13 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r ngFEC/cdceOut0IbufdsCGtxe2/O net (fo=17, routed) 0.222 0.954 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y72 BUFH (Prop_bufh_I_O) 0.045 0.999 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.441 1.440 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X86Y349 SRLC32E r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK clock pessimism -0.498 0.942 SLICE_X86Y349 SRLC32E (Hold_srlc32e_CLK_D) 0.099 1.041 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32 ------------------------------------------------------------------- required time -1.041 arrival time 1.213 ------------------------------------------------------------------- slack 0.172 Slack (MET) : 0.172ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/D (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: ttc_mgt_xpoint_c Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ttc_mgt_xpoint_c rise@0.000ns - ttc_mgt_xpoint_c rise@0.000ns) Data Path Delay: 0.271ns (logic 0.271ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.437ns Source Clock Delay (SCD): 0.940ns Clock Pessimism Removal (CPR): 0.497ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_c rise edge) 0.000 0.000 r G8 0.000 0.000 r ttc_mgt_xpoint_c_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_c_p G8 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_c_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_c_p_IBUF IBUFDS_GTE2_X0Y13 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r ngFEC/cdceOut0IbufdsCGtxe2/O net (fo=17, routed) 0.191 0.632 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y72 BUFH (Prop_bufh_I_O) 0.023 0.655 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.285 0.940 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y344 SRLC32E r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y344 SRLC32E (Prop_srlc32e_CLK_Q31) 0.271 1.211 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/Q31 net (fo=1, routed) 0.000 1.211 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32_n_1 SLICE_X90Y344 SRLC32E r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/D ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_c rise edge) 0.000 0.000 r G8 0.000 0.000 r ttc_mgt_xpoint_c_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_c_p G8 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_c_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_c_p_IBUF IBUFDS_GTE2_X0Y13 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r ngFEC/cdceOut0IbufdsCGtxe2/O net (fo=17, routed) 0.222 0.954 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y72 BUFH (Prop_bufh_I_O) 0.045 0.999 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.438 1.437 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y344 SRLC32E r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLK clock pessimism -0.497 0.940 SLICE_X90Y344 SRLC32E (Hold_srlc32e_CLK_D) 0.099 1.039 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32 ------------------------------------------------------------------- required time -1.039 arrival time 1.211 ------------------------------------------------------------------- slack 0.172 Slack (MET) : 0.172ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: ttc_mgt_xpoint_c Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ttc_mgt_xpoint_c rise@0.000ns - ttc_mgt_xpoint_c rise@0.000ns) Data Path Delay: 0.271ns (logic 0.271ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.440ns Source Clock Delay (SCD): 0.942ns Clock Pessimism Removal (CPR): 0.498ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_c rise edge) 0.000 0.000 r G8 0.000 0.000 r ttc_mgt_xpoint_c_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_c_p G8 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_c_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_c_p_IBUF IBUFDS_GTE2_X0Y13 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r ngFEC/cdceOut0IbufdsCGtxe2/O net (fo=17, routed) 0.191 0.632 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y73 BUFH (Prop_bufh_I_O) 0.023 0.655 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.287 0.942 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X86Y348 SRLC32E r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK ------------------------------------------------------------------- ------------------- SLICE_X86Y348 SRLC32E (Prop_srlc32e_CLK_Q31) 0.271 1.213 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/Q31 net (fo=1, routed) 0.000 1.213 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32_n_1 SLICE_X86Y348 SRLC32E r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_c rise edge) 0.000 0.000 r G8 0.000 0.000 r ttc_mgt_xpoint_c_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_c_p G8 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_c_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_c_p_IBUF IBUFDS_GTE2_X0Y13 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r ngFEC/cdceOut0IbufdsCGtxe2/O net (fo=17, routed) 0.222 0.954 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y73 BUFH (Prop_bufh_I_O) 0.045 0.999 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.441 1.440 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X86Y348 SRLC32E r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK clock pessimism -0.498 0.942 SLICE_X86Y348 SRLC32E (Hold_srlc32e_CLK_D) 0.099 1.041 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32 ------------------------------------------------------------------- required time -1.041 arrival time 1.213 ------------------------------------------------------------------- slack 0.172 Slack (MET) : 0.172ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/D (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: ttc_mgt_xpoint_c Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ttc_mgt_xpoint_c rise@0.000ns - ttc_mgt_xpoint_c rise@0.000ns) Data Path Delay: 0.271ns (logic 0.271ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.438ns Source Clock Delay (SCD): 0.941ns Clock Pessimism Removal (CPR): 0.497ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_c rise edge) 0.000 0.000 r G8 0.000 0.000 r ttc_mgt_xpoint_c_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_c_p G8 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_c_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_c_p_IBUF IBUFDS_GTE2_X0Y13 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r ngFEC/cdceOut0IbufdsCGtxe2/O net (fo=17, routed) 0.191 0.632 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y73 BUFH (Prop_bufh_I_O) 0.023 0.655 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.286 0.941 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y349 SRLC32E r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y349 SRLC32E (Prop_srlc32e_CLK_Q31) 0.271 1.212 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/Q31 net (fo=1, routed) 0.000 1.212 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32_n_1 SLICE_X90Y349 SRLC32E r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/D ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_c rise edge) 0.000 0.000 r G8 0.000 0.000 r ttc_mgt_xpoint_c_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_c_p G8 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_c_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_c_p_IBUF IBUFDS_GTE2_X0Y13 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r ngFEC/cdceOut0IbufdsCGtxe2/O net (fo=17, routed) 0.222 0.954 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y73 BUFH (Prop_bufh_I_O) 0.045 0.999 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.439 1.438 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y349 SRLC32E r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLK clock pessimism -0.497 0.941 SLICE_X90Y349 SRLC32E (Hold_srlc32e_CLK_D) 0.099 1.040 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32 ------------------------------------------------------------------- required time -1.040 arrival time 1.212 ------------------------------------------------------------------- slack 0.172 Slack (MET) : 0.172ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: ttc_mgt_xpoint_c Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ttc_mgt_xpoint_c rise@0.000ns - ttc_mgt_xpoint_c rise@0.000ns) Data Path Delay: 0.271ns (logic 0.271ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.443ns Source Clock Delay (SCD): 0.946ns Clock Pessimism Removal (CPR): 0.497ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_c rise edge) 0.000 0.000 r G8 0.000 0.000 r ttc_mgt_xpoint_c_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_c_p G8 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_c_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_c_p_IBUF IBUFDS_GTE2_X0Y13 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r ngFEC/cdceOut0IbufdsCGtxe2/O net (fo=17, routed) 0.191 0.632 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y74 BUFH (Prop_bufh_I_O) 0.023 0.655 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.291 0.946 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X84Y349 SRLC32E r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK ------------------------------------------------------------------- ------------------- SLICE_X84Y349 SRLC32E (Prop_srlc32e_CLK_Q31) 0.271 1.217 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/Q31 net (fo=1, routed) 0.000 1.217 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32_n_1 SLICE_X84Y349 SRLC32E r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_c rise edge) 0.000 0.000 r G8 0.000 0.000 r ttc_mgt_xpoint_c_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_c_p G8 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_c_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_c_p_IBUF IBUFDS_GTE2_X0Y13 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r ngFEC/cdceOut0IbufdsCGtxe2/O net (fo=17, routed) 0.222 0.954 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y74 BUFH (Prop_bufh_I_O) 0.045 0.999 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.444 1.443 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X84Y349 SRLC32E r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK clock pessimism -0.497 0.946 SLICE_X84Y349 SRLC32E (Hold_srlc32e_CLK_D) 0.099 1.045 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32 ------------------------------------------------------------------- required time -1.045 arrival time 1.217 ------------------------------------------------------------------- slack 0.172 Slack (MET) : 0.172ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/D (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: ttc_mgt_xpoint_c Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ttc_mgt_xpoint_c rise@0.000ns - ttc_mgt_xpoint_c rise@0.000ns) Data Path Delay: 0.271ns (logic 0.271ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.438ns Source Clock Delay (SCD): 0.941ns Clock Pessimism Removal (CPR): 0.497ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_c rise edge) 0.000 0.000 r G8 0.000 0.000 r ttc_mgt_xpoint_c_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_c_p G8 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_c_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_c_p_IBUF IBUFDS_GTE2_X0Y13 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r ngFEC/cdceOut0IbufdsCGtxe2/O net (fo=17, routed) 0.191 0.632 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y74 BUFH (Prop_bufh_I_O) 0.023 0.655 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.286 0.941 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y348 SRLC32E r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y348 SRLC32E (Prop_srlc32e_CLK_Q31) 0.271 1.212 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/Q31 net (fo=1, routed) 0.000 1.212 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32_n_1 SLICE_X90Y348 SRLC32E r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/D ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_c rise edge) 0.000 0.000 r G8 0.000 0.000 r ttc_mgt_xpoint_c_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_c_p G8 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_c_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_c_p_IBUF IBUFDS_GTE2_X0Y13 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r ngFEC/cdceOut0IbufdsCGtxe2/O net (fo=17, routed) 0.222 0.954 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y74 BUFH (Prop_bufh_I_O) 0.045 0.999 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.439 1.438 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y348 SRLC32E r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLK clock pessimism -0.497 0.941 SLICE_X90Y348 SRLC32E (Hold_srlc32e_CLK_D) 0.099 1.040 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32 ------------------------------------------------------------------- required time -1.040 arrival time 1.212 ------------------------------------------------------------------- slack 0.172 Slack (MET) : 0.172ns (arrival time - required time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: ttc_mgt_xpoint_c Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ttc_mgt_xpoint_c rise@0.000ns - ttc_mgt_xpoint_c rise@0.000ns) Data Path Delay: 0.271ns (logic 0.271ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.430ns Source Clock Delay (SCD): 0.935ns Clock Pessimism Removal (CPR): 0.495ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_c rise edge) 0.000 0.000 r G8 0.000 0.000 r ttc_mgt_xpoint_c_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_c_p G8 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_c_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_c_p_IBUF IBUFDS_GTE2_X0Y13 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r ngFEC/cdceOut0IbufdsCGtxe2/O net (fo=17, routed) 0.191 0.632 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y75 BUFH (Prop_bufh_I_O) 0.023 0.655 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.280 0.935 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y316 SRLC32E r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y316 SRLC32E (Prop_srlc32e_CLK_Q31) 0.271 1.206 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/Q31 net (fo=1, routed) 0.000 1.206 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32_n_1 SLICE_X90Y316 SRLC32E r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_c rise edge) 0.000 0.000 r G8 0.000 0.000 r ttc_mgt_xpoint_c_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_c_p G8 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_c_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_c_p_IBUF IBUFDS_GTE2_X0Y13 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r ngFEC/cdceOut0IbufdsCGtxe2/O net (fo=17, routed) 0.222 0.954 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y75 BUFH (Prop_bufh_I_O) 0.045 0.999 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.431 1.430 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y316 SRLC32E r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK clock pessimism -0.495 0.935 SLICE_X90Y316 SRLC32E (Hold_srlc32e_CLK_D) 0.099 1.034 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32 ------------------------------------------------------------------- required time -1.034 arrival time 1.206 ------------------------------------------------------------------- slack 0.172 Slack (MET) : 0.172ns (arrival time - required time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/D (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: ttc_mgt_xpoint_c Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ttc_mgt_xpoint_c rise@0.000ns - ttc_mgt_xpoint_c rise@0.000ns) Data Path Delay: 0.271ns (logic 0.271ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.431ns Source Clock Delay (SCD): 0.936ns Clock Pessimism Removal (CPR): 0.495ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_c rise edge) 0.000 0.000 r G8 0.000 0.000 r ttc_mgt_xpoint_c_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_c_p G8 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_c_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_c_p_IBUF IBUFDS_GTE2_X0Y13 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r ngFEC/cdceOut0IbufdsCGtxe2/O net (fo=17, routed) 0.191 0.632 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y75 BUFH (Prop_bufh_I_O) 0.023 0.655 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.281 0.936 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y315 SRLC32E r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y315 SRLC32E (Prop_srlc32e_CLK_Q31) 0.271 1.207 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/Q31 net (fo=1, routed) 0.000 1.207 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32_n_1 SLICE_X90Y315 SRLC32E r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/D ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_c rise edge) 0.000 0.000 r G8 0.000 0.000 r ttc_mgt_xpoint_c_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_c_p G8 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_c_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_c_p_IBUF IBUFDS_GTE2_X0Y13 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r ngFEC/cdceOut0IbufdsCGtxe2/O net (fo=17, routed) 0.222 0.954 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y75 BUFH (Prop_bufh_I_O) 0.045 0.999 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.432 1.431 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y315 SRLC32E r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLK clock pessimism -0.495 0.936 SLICE_X90Y315 SRLC32E (Hold_srlc32e_CLK_D) 0.099 1.035 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32 ------------------------------------------------------------------- required time -1.035 arrival time 1.207 ------------------------------------------------------------------- slack 0.172 Slack (MET) : 0.172ns (arrival time - required time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: ttc_mgt_xpoint_c Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ttc_mgt_xpoint_c rise@0.000ns - ttc_mgt_xpoint_c rise@0.000ns) Data Path Delay: 0.271ns (logic 0.271ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.437ns Source Clock Delay (SCD): 0.940ns Clock Pessimism Removal (CPR): 0.497ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_c rise edge) 0.000 0.000 r G8 0.000 0.000 r ttc_mgt_xpoint_c_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_c_p G8 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_c_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_c_p_IBUF IBUFDS_GTE2_X0Y13 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r ngFEC/cdceOut0IbufdsCGtxe2/O net (fo=17, routed) 0.191 0.632 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y76 BUFH (Prop_bufh_I_O) 0.023 0.655 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.285 0.940 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y305 SRLC32E r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y305 SRLC32E (Prop_srlc32e_CLK_Q31) 0.271 1.211 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/Q31 net (fo=1, routed) 0.000 1.211 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32_n_1 SLICE_X90Y305 SRLC32E r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/D ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_c rise edge) 0.000 0.000 r G8 0.000 0.000 r ttc_mgt_xpoint_c_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_c_p G8 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_c_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_c_p_IBUF IBUFDS_GTE2_X0Y13 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r ngFEC/cdceOut0IbufdsCGtxe2/O net (fo=17, routed) 0.222 0.954 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y76 BUFH (Prop_bufh_I_O) 0.045 0.999 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.438 1.437 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y305 SRLC32E r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK clock pessimism -0.497 0.940 SLICE_X90Y305 SRLC32E (Hold_srlc32e_CLK_D) 0.099 1.039 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32 ------------------------------------------------------------------- required time -1.039 arrival time 1.211 ------------------------------------------------------------------- slack 0.172 Slack (MET) : 0.172ns (arrival time - required time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/D (rising edge-triggered cell SRLC32E clocked by ttc_mgt_xpoint_c {rise@0.000ns fall@4.167ns period=8.333ns}) Path Group: ttc_mgt_xpoint_c Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (ttc_mgt_xpoint_c rise@0.000ns - ttc_mgt_xpoint_c rise@0.000ns) Data Path Delay: 0.271ns (logic 0.271ns (100.000%) route 0.000ns (0.000%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.437ns Source Clock Delay (SCD): 0.940ns Clock Pessimism Removal (CPR): 0.497ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_c rise edge) 0.000 0.000 r G8 0.000 0.000 r ttc_mgt_xpoint_c_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_c_p G8 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_c_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_c_p_IBUF IBUFDS_GTE2_X0Y13 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r ngFEC/cdceOut0IbufdsCGtxe2/O net (fo=17, routed) 0.191 0.632 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y76 BUFH (Prop_bufh_I_O) 0.023 0.655 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.285 0.940 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y306 SRLC32E r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK ------------------------------------------------------------------- ------------------- SLICE_X90Y306 SRLC32E (Prop_srlc32e_CLK_Q31) 0.271 1.211 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/Q31 net (fo=1, routed) 0.000 1.211 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32_n_1 SLICE_X90Y306 SRLC32E r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/D ------------------------------------------------------------------- ------------------- (clock ttc_mgt_xpoint_c rise edge) 0.000 0.000 r G8 0.000 0.000 r ttc_mgt_xpoint_c_p (IN) net (fo=0) 0.000 0.000 ttc_mgt_xpoint_c_p G8 IBUF (Prop_ibuf_I_O) 0.000 0.000 r ttc_mgt_xpoint_c_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 ngFEC/ttc_mgt_xpoint_c_p_IBUF IBUFDS_GTE2_X0Y13 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r ngFEC/cdceOut0IbufdsCGtxe2/O net (fo=17, routed) 0.222 0.954 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/gt0_gtrefclk1_in BUFHCE_X0Y76 BUFH (Prop_bufh_I_O) 0.045 0.999 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O net (fo=9, routed) 0.438 1.437 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 SLICE_X90Y306 SRLC32E r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLK clock pessimism -0.497 0.940 SLICE_X90Y306 SRLC32E (Hold_srlc32e_CLK_D) 0.099 1.039 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32 ------------------------------------------------------------------- required time -1.039 arrival time 1.211 ------------------------------------------------------------------- slack 0.172 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: ttc_mgt_xpoint_c Waveform(ns): { 0.000 4.167 } Period(ns): 8.333 Sources: { ttc_mgt_xpoint_c_p } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/GTREFCLK1 n/a 1.538 8.333 6.795 GTXE2_CHANNEL_X0Y28 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK1 Min Period n/a GTXE2_CHANNEL/GTREFCLK1 n/a 1.538 8.333 6.795 GTXE2_CHANNEL_X0Y31 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK1 Min Period n/a GTXE2_CHANNEL/GTREFCLK1 n/a 1.538 8.333 6.795 GTXE2_CHANNEL_X0Y30 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK1 Min Period n/a GTXE2_CHANNEL/GTREFCLK1 n/a 1.538 8.333 6.795 GTXE2_CHANNEL_X0Y25 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK1 Min Period n/a GTXE2_CHANNEL/GTREFCLK1 n/a 1.538 8.333 6.795 GTXE2_CHANNEL_X0Y24 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK1 Min Period n/a GTXE2_CHANNEL/GTREFCLK1 n/a 1.538 8.333 6.795 GTXE2_CHANNEL_X0Y21 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK1 Min Period n/a GTXE2_CHANNEL/GTREFCLK1 n/a 1.538 8.333 6.795 GTXE2_CHANNEL_X0Y20 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK1 Min Period n/a GTXE2_CHANNEL/GTREFCLK1 n/a 1.538 8.333 6.795 GTXE2_CHANNEL_X0Y23 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK1 Min Period n/a BUFH/I n/a 1.409 8.333 6.925 BUFHCE_X1Y74 ngFEC/i_ttcMgtXpoint_from_ibufdsCGtxe2_buf/I Min Period n/a BUFH/I n/a 1.409 8.333 6.925 BUFHCE_X0Y72 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/I Low Pulse Width Fast SRLC32E/CLK n/a 0.642 4.166 3.524 SLICE_X84Y349 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK Low Pulse Width Fast SRLC32E/CLK n/a 0.642 4.166 3.524 SLICE_X84Y349 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK Low Pulse Width Fast SRLC32E/CLK n/a 0.642 4.166 3.524 SLICE_X84Y349 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK Low Pulse Width Fast SRLC32E/CLK n/a 0.642 4.166 3.524 SLICE_X84Y300 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK Low Pulse Width Fast SRLC32E/CLK n/a 0.642 4.166 3.524 SLICE_X84Y300 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[31]_srl32/CLK Low Pulse Width Fast SRLC32E/CLK n/a 0.642 4.166 3.524 SLICE_X84Y300 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK Low Pulse Width Fast SRLC32E/CLK n/a 0.642 4.166 3.524 SLICE_X84Y300 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLK Low Pulse Width Fast SRLC32E/CLK n/a 0.642 4.167 3.525 SLICE_X86Y349 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK Low Pulse Width Fast SRLC32E/CLK n/a 0.642 4.167 3.525 SLICE_X86Y349 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK Low Pulse Width Fast SRLC32E/CLK n/a 0.642 4.167 3.525 SLICE_X86Y349 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK High Pulse Width Slow SRLC32E/CLK n/a 0.642 4.166 3.524 SLICE_X84Y349 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32/CLK High Pulse Width Slow SRLC32E/CLK n/a 0.642 4.166 3.524 SLICE_X84Y349 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32/CLK High Pulse Width Slow SRLC32E/CLK n/a 0.642 4.166 3.524 SLICE_X84Y349 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31/CLK High Pulse Width Slow SRLC32E/CLK n/a 0.642 4.166 3.524 SLICE_X84Y300 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK High Pulse Width Slow SRLC32E/CLK n/a 0.642 4.166 3.524 SLICE_X84Y300 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[31]_srl32/CLK High Pulse Width Slow SRLC32E/CLK n/a 0.642 4.166 3.524 SLICE_X84Y300 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK High Pulse Width Slow SRLC32E/CLK n/a 0.642 4.166 3.524 SLICE_X84Y300 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32/CLK High Pulse Width Slow SRLC32E/CLK n/a 0.642 4.166 3.524 SLICE_X90Y344 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31/CLK High Pulse Width Slow SRLC32E/CLK n/a 0.642 4.166 3.524 SLICE_X90Y344 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[31]_srl32/CLK High Pulse Width Slow SRLC32E/CLK n/a 0.642 4.166 3.524 SLICE_X90Y344 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32/CLK --------------------------------------------------------------------------------------------------- From Clock: txWordclkl12_1 To Clock: txWordclkl12_1 Setup : 0 Failing Endpoints, Worst Slack 4.197ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.108ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.458ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.197ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[4]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[4] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_1 rise@8.200ns - txWordclkl12_1 rise@0.000ns) Data Path Delay: 3.987ns (logic 0.223ns (5.593%) route 3.764ns (94.407%)) Logic Levels: 0 Clock Path Skew: 0.438ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.787ns = ( 9.987 - 8.200 ) Source Clock Delay (SCD): 1.362ns Clock Pessimism Removal (CPR): 0.013ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.362 1.362 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X167Y241 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X167Y241 FDCE (Prop_fdce_C_Q) 0.223 1.585 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[4]/Q net (fo=1, routed) 3.764 5.349 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[4] GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[4] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 8.200 8.200 r BUFGCTRL_X0Y17 BUFG 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.787 9.987 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.013 10.000 clock uncertainty -0.035 9.965 GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[4]) -0.419 9.546 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.546 arrival time -5.349 ------------------------------------------------------------------- slack 4.197 Slack (MET) : 4.202ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[3]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[3] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_1 rise@8.200ns - txWordclkl12_1 rise@0.000ns) Data Path Delay: 3.980ns (logic 0.223ns (5.603%) route 3.757ns (94.397%)) Logic Levels: 0 Clock Path Skew: 0.436ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.787ns = ( 9.987 - 8.200 ) Source Clock Delay (SCD): 1.364ns Clock Pessimism Removal (CPR): 0.013ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.364 1.364 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X169Y243 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X169Y243 FDCE (Prop_fdce_C_Q) 0.223 1.587 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[3]/Q net (fo=1, routed) 3.757 5.344 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[3] GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[3] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 8.200 8.200 r BUFGCTRL_X0Y17 BUFG 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.787 9.987 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.013 10.000 clock uncertainty -0.035 9.965 GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[3]) -0.419 9.546 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.546 arrival time -5.344 ------------------------------------------------------------------- slack 4.202 Slack (MET) : 4.268ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[7] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_1 rise@8.200ns - txWordclkl12_1 rise@0.000ns) Data Path Delay: 3.915ns (logic 0.259ns (6.616%) route 3.656ns (93.384%)) Logic Levels: 0 Clock Path Skew: 0.437ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.787ns = ( 9.987 - 8.200 ) Source Clock Delay (SCD): 1.363ns Clock Pessimism Removal (CPR): 0.013ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.363 1.363 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X166Y243 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X166Y243 FDCE (Prop_fdce_C_Q) 0.259 1.622 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/Q net (fo=1, routed) 3.656 5.278 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[7] GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[7] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 8.200 8.200 r BUFGCTRL_X0Y17 BUFG 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.787 9.987 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.013 10.000 clock uncertainty -0.035 9.965 GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[7]) -0.419 9.546 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.546 arrival time -5.278 ------------------------------------------------------------------- slack 4.268 Slack (MET) : 4.307ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[6] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_1 rise@8.200ns - txWordclkl12_1 rise@0.000ns) Data Path Delay: 3.875ns (logic 0.223ns (5.755%) route 3.652ns (94.245%)) Logic Levels: 0 Clock Path Skew: 0.436ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.787ns = ( 9.987 - 8.200 ) Source Clock Delay (SCD): 1.364ns Clock Pessimism Removal (CPR): 0.013ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.364 1.364 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X168Y242 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X168Y242 FDCE (Prop_fdce_C_Q) 0.223 1.587 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/Q net (fo=1, routed) 3.652 5.239 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[6] GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[6] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 8.200 8.200 r BUFGCTRL_X0Y17 BUFG 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.787 9.987 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.013 10.000 clock uncertainty -0.035 9.965 GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[6]) -0.419 9.546 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.546 arrival time -5.239 ------------------------------------------------------------------- slack 4.307 Slack (MET) : 4.314ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[2]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[2] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_1 rise@8.200ns - txWordclkl12_1 rise@0.000ns) Data Path Delay: 3.868ns (logic 0.223ns (5.765%) route 3.645ns (94.235%)) Logic Levels: 0 Clock Path Skew: 0.436ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.787ns = ( 9.987 - 8.200 ) Source Clock Delay (SCD): 1.364ns Clock Pessimism Removal (CPR): 0.013ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.364 1.364 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X169Y243 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X169Y243 FDCE (Prop_fdce_C_Q) 0.223 1.587 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[2]/Q net (fo=1, routed) 3.645 5.232 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[2] GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[2] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 8.200 8.200 r BUFGCTRL_X0Y17 BUFG 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.787 9.987 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.013 10.000 clock uncertainty -0.035 9.965 GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[2]) -0.419 9.546 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.546 arrival time -5.232 ------------------------------------------------------------------- slack 4.314 Slack (MET) : 4.372ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[19]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPMODE[1] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_1 rise@8.200ns - txWordclkl12_1 rise@0.000ns) Data Path Delay: 3.811ns (logic 0.223ns (5.852%) route 3.588ns (94.148%)) Logic Levels: 0 Clock Path Skew: 0.437ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.787ns = ( 9.987 - 8.200 ) Source Clock Delay (SCD): 1.363ns Clock Pessimism Removal (CPR): 0.013ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.363 1.363 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X169Y240 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X169Y240 FDCE (Prop_fdce_C_Q) 0.223 1.586 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[19]/Q net (fo=1, routed) 3.588 5.174 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[19] GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPMODE[1] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 8.200 8.200 r BUFGCTRL_X0Y17 BUFG 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.787 9.987 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.013 10.000 clock uncertainty -0.035 9.965 GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXCHARDISPMODE[1]) -0.419 9.546 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.546 arrival time -5.174 ------------------------------------------------------------------- slack 4.372 Slack (MET) : 4.389ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[1] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_1 rise@8.200ns - txWordclkl12_1 rise@0.000ns) Data Path Delay: 3.793ns (logic 0.223ns (5.879%) route 3.570ns (94.121%)) Logic Levels: 0 Clock Path Skew: 0.436ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.787ns = ( 9.987 - 8.200 ) Source Clock Delay (SCD): 1.364ns Clock Pessimism Removal (CPR): 0.013ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.364 1.364 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X168Y242 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X168Y242 FDCE (Prop_fdce_C_Q) 0.223 1.587 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/Q net (fo=1, routed) 3.570 5.157 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[1] GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[1] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 8.200 8.200 r BUFGCTRL_X0Y17 BUFG 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.787 9.987 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.013 10.000 clock uncertainty -0.035 9.965 GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[1]) -0.419 9.546 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.546 arrival time -5.157 ------------------------------------------------------------------- slack 4.389 Slack (MET) : 4.417ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[15]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[13] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_1 rise@8.200ns - txWordclkl12_1 rise@0.000ns) Data Path Delay: 3.766ns (logic 0.259ns (6.878%) route 3.507ns (93.122%)) Logic Levels: 0 Clock Path Skew: 0.437ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.787ns = ( 9.987 - 8.200 ) Source Clock Delay (SCD): 1.363ns Clock Pessimism Removal (CPR): 0.013ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.363 1.363 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X166Y243 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X166Y243 FDCE (Prop_fdce_C_Q) 0.259 1.622 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[15]/Q net (fo=1, routed) 3.507 5.129 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[15] GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[13] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 8.200 8.200 r BUFGCTRL_X0Y17 BUFG 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.787 9.987 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.013 10.000 clock uncertainty -0.035 9.965 GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[13]) -0.419 9.546 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.546 arrival time -5.129 ------------------------------------------------------------------- slack 4.417 Slack (MET) : 4.463ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[0] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_1 rise@8.200ns - txWordclkl12_1 rise@0.000ns) Data Path Delay: 3.719ns (logic 0.223ns (5.996%) route 3.496ns (94.004%)) Logic Levels: 0 Clock Path Skew: 0.436ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.787ns = ( 9.987 - 8.200 ) Source Clock Delay (SCD): 1.364ns Clock Pessimism Removal (CPR): 0.013ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.364 1.364 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X169Y243 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X169Y243 FDCE (Prop_fdce_C_Q) 0.223 1.587 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/Q net (fo=1, routed) 3.496 5.083 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[0] GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[0] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 8.200 8.200 r BUFGCTRL_X0Y17 BUFG 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.787 9.987 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.013 10.000 clock uncertainty -0.035 9.965 GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[0]) -0.419 9.546 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.546 arrival time -5.083 ------------------------------------------------------------------- slack 4.463 Slack (MET) : 4.507ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPVAL[1] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_1 rise@8.200ns - txWordclkl12_1 rise@0.000ns) Data Path Delay: 3.677ns (logic 0.223ns (6.065%) route 3.454ns (93.935%)) Logic Levels: 0 Clock Path Skew: 0.438ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.787ns = ( 9.987 - 8.200 ) Source Clock Delay (SCD): 1.362ns Clock Pessimism Removal (CPR): 0.013ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.362 1.362 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X167Y241 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X167Y241 FDCE (Prop_fdce_C_Q) 0.223 1.585 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/Q net (fo=1, routed) 3.454 5.039 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[18] GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPVAL[1] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 8.200 8.200 r BUFGCTRL_X0Y17 BUFG 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.787 9.987 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.013 10.000 clock uncertainty -0.035 9.965 GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXCHARDISPVAL[1]) -0.419 9.546 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.546 arrival time -5.039 ------------------------------------------------------------------- slack 4.507 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_1 rise@0.000ns - txWordclkl12_1 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.031ns Source Clock Delay (SCD): 0.782ns Clock Pessimism Removal (CPR): 0.249ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.782 0.782 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in SLICE_X185Y343 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X185Y343 FDRE (Prop_fdre_C_Q) 0.100 0.882 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q net (fo=1, routed) 0.055 0.937 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync1 SLICE_X185Y343 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.031 1.031 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in SLICE_X185Y343 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C clock pessimism -0.249 0.782 SLICE_X185Y343 FDRE (Hold_fdre_C_D) 0.047 0.829 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.829 arrival time 0.937 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D (rising edge-triggered cell FDRE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_1 rise@0.000ns - txWordclkl12_1 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.989ns Source Clock Delay (SCD): 0.743ns Clock Pessimism Removal (CPR): 0.246ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.743 0.743 ngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst/dest_clk SLICE_X151Y316 FDRE r ngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X151Y316 FDRE (Prop_fdre_C_Q) 0.100 0.843 r ngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/Q net (fo=1, routed) 0.055 0.898 ngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff[0] SLICE_X151Y316 FDRE r ngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.989 0.989 ngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst/dest_clk SLICE_X151Y316 FDRE r ngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/C clock pessimism -0.246 0.743 SLICE_X151Y316 FDRE (Hold_fdre_C_D) 0.047 0.790 ngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1] ------------------------------------------------------------------- required time -0.790 arrival time 0.898 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.113ns (arrival time - required time) Source: ngFEC/g_pm[2].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[2].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/D (rising edge-triggered cell FDRE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_1 rise@0.000ns - txWordclkl12_1 rise@0.000ns) Data Path Delay: 0.160ns (logic 0.100ns (62.442%) route 0.060ns (37.558%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.992ns Source Clock Delay (SCD): 0.746ns Clock Pessimism Removal (CPR): 0.246ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.746 0.746 ngFEC/g_pm[2].phase_mon/sample_PS_Sync_inst/dest_clk SLICE_X156Y313 FDRE r ngFEC/g_pm[2].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X156Y313 FDRE (Prop_fdre_C_Q) 0.100 0.846 r ngFEC/g_pm[2].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/Q net (fo=1, routed) 0.060 0.906 ngFEC/g_pm[2].phase_mon/sample_PS_Sync_inst/syncstages_ff[0] SLICE_X156Y313 FDRE r ngFEC/g_pm[2].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.992 0.992 ngFEC/g_pm[2].phase_mon/sample_PS_Sync_inst/dest_clk SLICE_X156Y313 FDRE r ngFEC/g_pm[2].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/C clock pessimism -0.246 0.746 SLICE_X156Y313 FDRE (Hold_fdre_C_D) 0.047 0.793 ngFEC/g_pm[2].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1] ------------------------------------------------------------------- required time -0.793 arrival time 0.906 ------------------------------------------------------------------- slack 0.113 Slack (MET) : 0.113ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_1 rise@0.000ns - txWordclkl12_1 rise@0.000ns) Data Path Delay: 0.160ns (logic 0.100ns (62.442%) route 0.060ns (37.558%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.030ns Source Clock Delay (SCD): 0.781ns Clock Pessimism Removal (CPR): 0.249ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.781 0.781 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in SLICE_X184Y341 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X184Y341 FDRE (Prop_fdre_C_Q) 0.100 0.881 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/Q net (fo=1, routed) 0.060 0.941 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync1 SLICE_X184Y341 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.030 1.030 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in SLICE_X184Y341 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/C clock pessimism -0.249 0.781 SLICE_X184Y341 FDRE (Hold_fdre_C_D) 0.047 0.828 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.828 arrival time 0.941 ------------------------------------------------------------------- slack 0.113 Slack (MET) : 0.131ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D (rising edge-triggered cell FDRE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_1 rise@0.000ns - txWordclkl12_1 rise@0.000ns) Data Path Delay: 0.173ns (logic 0.118ns (68.255%) route 0.055ns (31.745%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.799ns Source Clock Delay (SCD): 0.592ns Clock Pessimism Removal (CPR): 0.207ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.592 0.592 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk SLICE_X162Y247 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X162Y247 FDRE (Prop_fdre_C_Q) 0.118 0.710 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/Q net (fo=1, routed) 0.055 0.765 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff[0] SLICE_X162Y247 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.799 0.799 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk SLICE_X162Y247 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/C clock pessimism -0.207 0.592 SLICE_X162Y247 FDRE (Hold_fdre_C_D) 0.042 0.634 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1] ------------------------------------------------------------------- required time -0.634 arrival time 0.765 ------------------------------------------------------------------- slack 0.131 Slack (MET) : 0.155ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[1]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[2]/D (rising edge-triggered cell FDCE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_1 rise@0.000ns - txWordclkl12_1 rise@0.000ns) Data Path Delay: 0.215ns (logic 0.157ns (73.163%) route 0.058ns (26.837%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.798ns Source Clock Delay (SCD): 0.591ns Clock Pessimism Removal (CPR): 0.207ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.591 0.591 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X165Y246 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X165Y246 FDCE (Prop_fdce_C_Q) 0.091 0.682 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[1]/Q net (fo=42, routed) 0.058 0.740 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/address[1] SLICE_X165Y246 LUT6 (Prop_lut6_I0_O) 0.066 0.806 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address[2]_i_1/O net (fo=1, routed) 0.000 0.806 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address[2]_i_1_n_0 SLICE_X165Y246 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[2]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.798 0.798 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X165Y246 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[2]/C clock pessimism -0.207 0.591 SLICE_X165Y246 FDCE (Hold_fdce_C_D) 0.060 0.651 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[2] ------------------------------------------------------------------- required time -0.651 arrival time 0.806 ------------------------------------------------------------------- slack 0.155 Slack (MET) : 0.161ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[2]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/D (rising edge-triggered cell FDCE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_1 rise@0.000ns - txWordclkl12_1 rise@0.000ns) Data Path Delay: 0.235ns (logic 0.128ns (54.429%) route 0.107ns (45.571%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.798ns Source Clock Delay (SCD): 0.591ns Clock Pessimism Removal (CPR): 0.193ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.591 0.591 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X165Y246 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X165Y246 FDCE (Prop_fdce_C_Q) 0.100 0.691 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[2]/Q net (fo=21, routed) 0.107 0.798 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/address[2] SLICE_X165Y245 LUT6 (Prop_lut6_I4_O) 0.028 0.826 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[5]_i_1/O net (fo=1, routed) 0.000 0.826 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[5]_i_1_n_0 SLICE_X165Y245 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.798 0.798 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X165Y245 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/C clock pessimism -0.193 0.605 SLICE_X165Y245 FDCE (Hold_fdce_C_D) 0.060 0.665 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5] ------------------------------------------------------------------- required time -0.665 arrival time 0.826 ------------------------------------------------------------------- slack 0.161 Slack (MET) : 0.173ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[96]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[16]/D (rising edge-triggered cell FDCE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_1 rise@0.000ns - txWordclkl12_1 rise@0.000ns) Data Path Delay: 0.269ns (logic 0.146ns (54.201%) route 0.123ns (45.799%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.825ns Source Clock Delay (SCD): 0.616ns Clock Pessimism Removal (CPR): 0.173ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.616 0.616 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X166Y240 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[96]/C ------------------------------------------------------------------- ------------------- SLICE_X166Y240 FDCE (Prop_fdce_C_Q) 0.118 0.734 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[96]/Q net (fo=1, routed) 0.123 0.857 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/data4[16] SLICE_X169Y240 LUT6 (Prop_lut6_I0_O) 0.028 0.885 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[16]_i_1/O net (fo=1, routed) 0.000 0.885 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[16]_i_1_n_0 SLICE_X169Y240 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[16]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.825 0.825 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X169Y240 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[16]/C clock pessimism -0.173 0.652 SLICE_X169Y240 FDCE (Hold_fdce_C_D) 0.060 0.712 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[16] ------------------------------------------------------------------- required time -0.712 arrival time 0.885 ------------------------------------------------------------------- slack 0.173 Slack (MET) : 0.181ns (arrival time - required time) Source: ngFEC/g_pm[2].phase_mon/inh_cntr_reg[3]/C (rising edge-triggered cell FDPE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[2].phase_mon/inh_cntr_reg[4]/D (rising edge-triggered cell FDPE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_1 rise@0.000ns - txWordclkl12_1 rise@0.000ns) Data Path Delay: 0.241ns (logic 0.128ns (53.009%) route 0.113ns (46.991%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.994ns Source Clock Delay (SCD): 0.747ns Clock Pessimism Removal (CPR): 0.247ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.747 0.747 ngFEC/g_pm[2].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X155Y311 FDPE r ngFEC/g_pm[2].phase_mon/inh_cntr_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X155Y311 FDPE (Prop_fdpe_C_Q) 0.100 0.847 r ngFEC/g_pm[2].phase_mon/inh_cntr_reg[3]/Q net (fo=2, routed) 0.113 0.960 ngFEC/g_pm[2].phase_mon/inh_cntr_reg_n_0_[3] SLICE_X155Y311 LUT6 (Prop_lut6_I4_O) 0.028 0.988 r ngFEC/g_pm[2].phase_mon/inh_cntr[4]_i_2__0/O net (fo=1, routed) 0.000 0.988 ngFEC/g_pm[2].phase_mon/p_0_in__0[4] SLICE_X155Y311 FDPE r ngFEC/g_pm[2].phase_mon/inh_cntr_reg[4]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.994 0.994 ngFEC/g_pm[2].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X155Y311 FDPE r ngFEC/g_pm[2].phase_mon/inh_cntr_reg[4]/C clock pessimism -0.247 0.747 SLICE_X155Y311 FDPE (Hold_fdpe_C_D) 0.060 0.807 ngFEC/g_pm[2].phase_mon/inh_cntr_reg[4] ------------------------------------------------------------------- required time -0.807 arrival time 0.988 ------------------------------------------------------------------- slack 0.181 Slack (MET) : 0.186ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.ready_reg/C (rising edge-triggered cell FDCE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[1]/D (rising edge-triggered cell FDCE clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_1 rise@0.000ns - txWordclkl12_1 rise@0.000ns) Data Path Delay: 0.272ns (logic 0.148ns (54.400%) route 0.124ns (45.600%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.798ns Source Clock Delay (SCD): 0.591ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.591 0.591 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X164Y246 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.ready_reg/C ------------------------------------------------------------------- ------------------- SLICE_X164Y246 FDCE (Prop_fdce_C_Q) 0.118 0.709 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.ready_reg/Q net (fo=3, routed) 0.124 0.833 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/ready SLICE_X165Y246 LUT5 (Prop_lut5_I3_O) 0.030 0.863 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address[1]_i_1/O net (fo=1, routed) 0.000 0.863 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address[1]_i_1_n_0 SLICE_X165Y246 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[1]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.798 0.798 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X165Y246 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[1]/C clock pessimism -0.196 0.602 SLICE_X165Y246 FDCE (Hold_fdce_C_D) 0.075 0.677 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[1] ------------------------------------------------------------------- required time -0.677 arrival time 0.863 ------------------------------------------------------------------- slack 0.186 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: txWordclkl12_1 Waveform(ns): { 0.000 4.100 } Period(ns): 8.200 Sources: { ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/TXUSRCLK n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y28 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK Min Period n/a GTXE2_CHANNEL/TXUSRCLK2 n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y28 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X155Y312 ngFEC/g_pm[2].phase_mon/PS_max_reg[6]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X155Y312 ngFEC/g_pm[2].phase_mon/PS_max_reg[7]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X155Y312 ngFEC/g_pm[2].phase_mon/PS_max_reg[8]/C Min Period n/a FDPE/C n/a 0.750 8.200 7.450 SLICE_X135Y313 ngFEC/g_pm[2].phase_mon/PS_min_reg[5]/C Min Period n/a FDPE/C n/a 0.750 8.200 7.450 SLICE_X135Y313 ngFEC/g_pm[2].phase_mon/PS_min_reg[6]/C Min Period n/a FDPE/C n/a 0.750 8.200 7.450 SLICE_X135Y313 ngFEC/g_pm[2].phase_mon/PS_min_reg[8]/C Min Period n/a FDPE/C n/a 0.750 8.200 7.450 SLICE_X135Y313 ngFEC/g_pm[2].phase_mon/PS_min_reg[9]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X156Y312 ngFEC/g_pm[2].phase_mon/en_chk_reg[2]/C Low Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X162Y246 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK Low Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X162Y246 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK Low Pulse Width Slow FDRE/C n/a 0.400 4.100 3.700 SLICE_X151Y316 ngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/C Low Pulse Width Slow FDRE/C n/a 0.400 4.100 3.700 SLICE_X151Y316 ngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[2]/C Low Pulse Width Slow FDRE/C n/a 0.400 4.100 3.700 SLICE_X162Y246 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X165Y246 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[1]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X167Y244 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[43]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X169Y244 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[46]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X166Y241 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[4]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X168Y241 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[53]/C High Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X162Y246 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X162Y246 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK High Pulse Width Fast FDCE/C n/a 0.350 4.100 3.750 SLICE_X155Y312 ngFEC/g_pm[2].phase_mon/PS_max_reg[1]/C High Pulse Width Fast FDCE/C n/a 0.350 4.100 3.750 SLICE_X155Y312 ngFEC/g_pm[2].phase_mon/PS_max_reg[3]/C High Pulse Width Fast FDCE/C n/a 0.350 4.100 3.750 SLICE_X155Y312 ngFEC/g_pm[2].phase_mon/PS_max_reg[4]/C High Pulse Width Fast FDCE/C n/a 0.350 4.100 3.750 SLICE_X155Y312 ngFEC/g_pm[2].phase_mon/PS_max_reg[5]/C High Pulse Width Fast FDCE/C n/a 0.350 4.100 3.750 SLICE_X155Y312 ngFEC/g_pm[2].phase_mon/PS_max_reg[6]/C High Pulse Width Fast FDCE/C n/a 0.350 4.100 3.750 SLICE_X155Y312 ngFEC/g_pm[2].phase_mon/PS_max_reg[7]/C High Pulse Width Fast FDCE/C n/a 0.350 4.100 3.750 SLICE_X155Y312 ngFEC/g_pm[2].phase_mon/PS_max_reg[8]/C High Pulse Width Fast FDPE/C n/a 0.350 4.100 3.750 SLICE_X134Y312 ngFEC/g_pm[2].phase_mon/PS_min_reg[0]/C --------------------------------------------------------------------------------------------------- From Clock: txWordclkl12_2 To Clock: txWordclkl12_2 Setup : 0 Failing Endpoints, Worst Slack 4.020ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.108ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.458ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.020ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[6] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_2 rise@8.200ns - txWordclkl12_2 rise@0.000ns) Data Path Delay: 4.095ns (logic 0.259ns (6.324%) route 3.837ns (93.676%)) Logic Levels: 0 Clock Path Skew: 0.369ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.787ns = ( 9.987 - 8.200 ) Source Clock Delay (SCD): 1.461ns Clock Pessimism Removal (CPR): 0.043ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y18 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.461 1.461 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X138Y286 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X138Y286 FDCE (Prop_fdce_C_Q) 0.259 1.720 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/Q net (fo=1, routed) 3.837 5.557 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[6] GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[6] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 8.200 8.200 r BUFGCTRL_X0Y18 BUFG 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.787 9.987 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.043 10.030 clock uncertainty -0.035 9.995 GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[6]) -0.419 9.576 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.576 arrival time -5.556 ------------------------------------------------------------------- slack 4.020 Slack (MET) : 4.021ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[2]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[2] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_2 rise@8.200ns - txWordclkl12_2 rise@0.000ns) Data Path Delay: 4.093ns (logic 0.259ns (6.327%) route 3.834ns (93.673%)) Logic Levels: 0 Clock Path Skew: 0.368ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.787ns = ( 9.987 - 8.200 ) Source Clock Delay (SCD): 1.462ns Clock Pessimism Removal (CPR): 0.043ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y18 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.462 1.462 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X138Y288 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X138Y288 FDCE (Prop_fdce_C_Q) 0.259 1.721 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[2]/Q net (fo=1, routed) 3.834 5.555 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[2] GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[2] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 8.200 8.200 r BUFGCTRL_X0Y18 BUFG 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.787 9.987 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.043 10.030 clock uncertainty -0.035 9.995 GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[2]) -0.419 9.576 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.576 arrival time -5.555 ------------------------------------------------------------------- slack 4.021 Slack (MET) : 4.109ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[0] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_2 rise@8.200ns - txWordclkl12_2 rise@0.000ns) Data Path Delay: 4.005ns (logic 0.223ns (5.568%) route 3.782ns (94.432%)) Logic Levels: 0 Clock Path Skew: 0.368ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.787ns = ( 9.987 - 8.200 ) Source Clock Delay (SCD): 1.462ns Clock Pessimism Removal (CPR): 0.043ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y18 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.462 1.462 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X141Y286 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X141Y286 FDCE (Prop_fdce_C_Q) 0.223 1.685 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/Q net (fo=1, routed) 3.782 5.467 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[0] GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[0] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 8.200 8.200 r BUFGCTRL_X0Y18 BUFG 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.787 9.987 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.043 10.030 clock uncertainty -0.035 9.995 GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[0]) -0.419 9.576 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.576 arrival time -5.467 ------------------------------------------------------------------- slack 4.109 Slack (MET) : 4.148ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[1] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_2 rise@8.200ns - txWordclkl12_2 rise@0.000ns) Data Path Delay: 3.965ns (logic 0.223ns (5.624%) route 3.742ns (94.376%)) Logic Levels: 0 Clock Path Skew: 0.367ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.787ns = ( 9.987 - 8.200 ) Source Clock Delay (SCD): 1.463ns Clock Pessimism Removal (CPR): 0.043ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y18 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.463 1.463 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X137Y289 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X137Y289 FDCE (Prop_fdce_C_Q) 0.223 1.686 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/Q net (fo=1, routed) 3.742 5.428 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[1] GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[1] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 8.200 8.200 r BUFGCTRL_X0Y18 BUFG 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.787 9.987 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.043 10.030 clock uncertainty -0.035 9.995 GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[1]) -0.419 9.576 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.576 arrival time -5.428 ------------------------------------------------------------------- slack 4.148 Slack (MET) : 4.162ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[5] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_2 rise@8.200ns - txWordclkl12_2 rise@0.000ns) Data Path Delay: 3.954ns (logic 0.259ns (6.551%) route 3.695ns (93.449%)) Logic Levels: 0 Clock Path Skew: 0.369ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.787ns = ( 9.987 - 8.200 ) Source Clock Delay (SCD): 1.461ns Clock Pessimism Removal (CPR): 0.043ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y18 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.461 1.461 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X138Y286 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X138Y286 FDCE (Prop_fdce_C_Q) 0.259 1.720 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/Q net (fo=1, routed) 3.695 5.415 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[5] GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[5] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 8.200 8.200 r BUFGCTRL_X0Y18 BUFG 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.787 9.987 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.043 10.030 clock uncertainty -0.035 9.995 GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[5]) -0.419 9.576 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.576 arrival time -5.415 ------------------------------------------------------------------- slack 4.162 Slack (MET) : 4.182ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[15]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[13] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_2 rise@8.200ns - txWordclkl12_2 rise@0.000ns) Data Path Delay: 3.932ns (logic 0.223ns (5.671%) route 3.709ns (94.329%)) Logic Levels: 0 Clock Path Skew: 0.368ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.787ns = ( 9.987 - 8.200 ) Source Clock Delay (SCD): 1.462ns Clock Pessimism Removal (CPR): 0.043ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y18 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.462 1.462 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X141Y286 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X141Y286 FDCE (Prop_fdce_C_Q) 0.223 1.685 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[15]/Q net (fo=1, routed) 3.709 5.394 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[15] GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[13] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 8.200 8.200 r BUFGCTRL_X0Y18 BUFG 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.787 9.987 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.043 10.030 clock uncertainty -0.035 9.995 GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[13]) -0.419 9.576 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.576 arrival time -5.394 ------------------------------------------------------------------- slack 4.182 Slack (MET) : 4.195ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[17]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[15] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_2 rise@8.200ns - txWordclkl12_2 rise@0.000ns) Data Path Delay: 3.922ns (logic 0.259ns (6.603%) route 3.663ns (93.397%)) Logic Levels: 0 Clock Path Skew: 0.371ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.787ns = ( 9.987 - 8.200 ) Source Clock Delay (SCD): 1.459ns Clock Pessimism Removal (CPR): 0.043ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y18 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.459 1.459 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X134Y288 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X134Y288 FDCE (Prop_fdce_C_Q) 0.259 1.718 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[17]/Q net (fo=1, routed) 3.663 5.381 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[17] GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[15] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 8.200 8.200 r BUFGCTRL_X0Y18 BUFG 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.787 9.987 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.043 10.030 clock uncertainty -0.035 9.995 GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[15]) -0.419 9.576 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.576 arrival time -5.381 ------------------------------------------------------------------- slack 4.195 Slack (MET) : 4.209ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[11]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[9] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_2 rise@8.200ns - txWordclkl12_2 rise@0.000ns) Data Path Delay: 3.908ns (logic 0.259ns (6.627%) route 3.649ns (93.373%)) Logic Levels: 0 Clock Path Skew: 0.371ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.787ns = ( 9.987 - 8.200 ) Source Clock Delay (SCD): 1.459ns Clock Pessimism Removal (CPR): 0.043ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y18 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.459 1.459 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X134Y288 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X134Y288 FDCE (Prop_fdce_C_Q) 0.259 1.718 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[11]/Q net (fo=1, routed) 3.649 5.367 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[11] GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[9] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 8.200 8.200 r BUFGCTRL_X0Y18 BUFG 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.787 9.987 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.043 10.030 clock uncertainty -0.035 9.995 GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[9]) -0.419 9.576 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.576 arrival time -5.367 ------------------------------------------------------------------- slack 4.209 Slack (MET) : 4.220ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[8]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPVAL[0] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_2 rise@8.200ns - txWordclkl12_2 rise@0.000ns) Data Path Delay: 3.895ns (logic 0.259ns (6.650%) route 3.636ns (93.350%)) Logic Levels: 0 Clock Path Skew: 0.368ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.787ns = ( 9.987 - 8.200 ) Source Clock Delay (SCD): 1.462ns Clock Pessimism Removal (CPR): 0.043ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y18 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.462 1.462 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X138Y287 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X138Y287 FDCE (Prop_fdce_C_Q) 0.259 1.721 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[8]/Q net (fo=1, routed) 3.636 5.357 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[8] GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPVAL[0] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 8.200 8.200 r BUFGCTRL_X0Y18 BUFG 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.787 9.987 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.043 10.030 clock uncertainty -0.035 9.995 GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXCHARDISPVAL[0]) -0.419 9.576 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.576 arrival time -5.357 ------------------------------------------------------------------- slack 4.220 Slack (MET) : 4.221ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[9]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPMODE[0] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_2 rise@8.200ns - txWordclkl12_2 rise@0.000ns) Data Path Delay: 3.892ns (logic 0.223ns (5.730%) route 3.669ns (94.270%)) Logic Levels: 0 Clock Path Skew: 0.367ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.787ns = ( 9.987 - 8.200 ) Source Clock Delay (SCD): 1.463ns Clock Pessimism Removal (CPR): 0.043ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y18 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.463 1.463 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X137Y289 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X137Y289 FDCE (Prop_fdce_C_Q) 0.223 1.686 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[9]/Q net (fo=1, routed) 3.669 5.355 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[9] GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPMODE[0] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 8.200 8.200 r BUFGCTRL_X0Y18 BUFG 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.787 9.987 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.043 10.030 clock uncertainty -0.035 9.995 GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXCHARDISPMODE[0]) -0.419 9.576 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.576 arrival time -5.355 ------------------------------------------------------------------- slack 4.221 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/g_pm[3].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[3].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D (rising edge-triggered cell FDRE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_2 rise@0.000ns - txWordclkl12_2 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.897ns Source Clock Delay (SCD): 0.669ns Clock Pessimism Removal (CPR): 0.228ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y18 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.669 0.669 ngFEC/g_pm[3].phase_mon/fabric_clk_PS_toggle_Sync_inst/dest_clk SLICE_X151Y297 FDRE r ngFEC/g_pm[3].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X151Y297 FDRE (Prop_fdre_C_Q) 0.100 0.769 r ngFEC/g_pm[3].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/Q net (fo=1, routed) 0.055 0.824 ngFEC/g_pm[3].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff[0] SLICE_X151Y297 FDRE r ngFEC/g_pm[3].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y18 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.897 0.897 ngFEC/g_pm[3].phase_mon/fabric_clk_PS_toggle_Sync_inst/dest_clk SLICE_X151Y297 FDRE r ngFEC/g_pm[3].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/C clock pessimism -0.228 0.669 SLICE_X151Y297 FDRE (Hold_fdre_C_D) 0.047 0.716 ngFEC/g_pm[3].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1] ------------------------------------------------------------------- required time -0.716 arrival time 0.824 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.111ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[93]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[13]/D (rising edge-triggered cell FDCE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_2 rise@0.000ns - txWordclkl12_2 rise@0.000ns) Data Path Delay: 0.209ns (logic 0.128ns (61.382%) route 0.081ns (38.618%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.886ns Source Clock Delay (SCD): 0.659ns Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y18 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.659 0.659 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X139Y288 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[93]/C ------------------------------------------------------------------- ------------------- SLICE_X139Y288 FDCE (Prop_fdce_C_Q) 0.100 0.759 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[93]/Q net (fo=1, routed) 0.081 0.840 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/data4[13] SLICE_X138Y288 LUT6 (Prop_lut6_I0_O) 0.028 0.868 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[13]_i_1__0/O net (fo=1, routed) 0.000 0.868 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[13]_i_1__0_n_0 SLICE_X138Y288 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[13]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y18 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.886 0.886 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X138Y288 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[13]/C clock pessimism -0.216 0.670 SLICE_X138Y288 FDCE (Hold_fdce_C_D) 0.087 0.757 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[13] ------------------------------------------------------------------- required time -0.757 arrival time 0.868 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.113ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D (rising edge-triggered cell FDRE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_2 rise@0.000ns - txWordclkl12_2 rise@0.000ns) Data Path Delay: 0.160ns (logic 0.100ns (62.442%) route 0.060ns (37.558%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.890ns Source Clock Delay (SCD): 0.664ns Clock Pessimism Removal (CPR): 0.226ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y18 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.664 0.664 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk SLICE_X148Y284 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X148Y284 FDRE (Prop_fdre_C_Q) 0.100 0.764 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/Q net (fo=1, routed) 0.060 0.824 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff[0] SLICE_X148Y284 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y18 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.890 0.890 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk SLICE_X148Y284 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/C clock pessimism -0.226 0.664 SLICE_X148Y284 FDRE (Hold_fdre_C_D) 0.047 0.711 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1] ------------------------------------------------------------------- required time -0.711 arrival time 0.824 ------------------------------------------------------------------- slack 0.113 Slack (MET) : 0.122ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[87]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/D (rising edge-triggered cell FDCE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_2 rise@0.000ns - txWordclkl12_2 rise@0.000ns) Data Path Delay: 0.222ns (logic 0.128ns (57.740%) route 0.094ns (42.260%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.884ns Source Clock Delay (SCD): 0.658ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y18 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.658 0.658 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X137Y287 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[87]/C ------------------------------------------------------------------- ------------------- SLICE_X137Y287 FDCE (Prop_fdce_C_Q) 0.100 0.758 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[87]/Q net (fo=1, routed) 0.094 0.852 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/data4[7] SLICE_X138Y287 LUT6 (Prop_lut6_I0_O) 0.028 0.880 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[7]_i_1__0/O net (fo=1, routed) 0.000 0.880 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[7]_i_1__0_n_0 SLICE_X138Y287 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y18 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.884 0.884 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X138Y287 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/C clock pessimism -0.213 0.671 SLICE_X138Y287 FDCE (Hold_fdce_C_D) 0.087 0.758 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7] ------------------------------------------------------------------- required time -0.758 arrival time 0.880 ------------------------------------------------------------------- slack 0.122 Slack (MET) : 0.131ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_2 rise@0.000ns - txWordclkl12_2 rise@0.000ns) Data Path Delay: 0.173ns (logic 0.118ns (68.255%) route 0.055ns (31.745%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.126ns Source Clock Delay (SCD): 0.858ns Clock Pessimism Removal (CPR): 0.268ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y18 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.858 0.858 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in SLICE_X180Y386 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X180Y386 FDRE (Prop_fdre_C_Q) 0.118 0.976 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q net (fo=1, routed) 0.055 1.031 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync1 SLICE_X180Y386 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y18 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.126 1.126 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in SLICE_X180Y386 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C clock pessimism -0.268 0.858 SLICE_X180Y386 FDRE (Hold_fdre_C_D) 0.042 0.900 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.900 arrival time 1.031 ------------------------------------------------------------------- slack 0.131 Slack (MET) : 0.131ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_2 rise@0.000ns - txWordclkl12_2 rise@0.000ns) Data Path Delay: 0.173ns (logic 0.118ns (68.255%) route 0.055ns (31.745%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.125ns Source Clock Delay (SCD): 0.858ns Clock Pessimism Removal (CPR): 0.267ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y18 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.858 0.858 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in SLICE_X178Y385 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X178Y385 FDRE (Prop_fdre_C_Q) 0.118 0.976 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/Q net (fo=1, routed) 0.055 1.031 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync1 SLICE_X178Y385 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y18 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.125 1.125 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in SLICE_X178Y385 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/C clock pessimism -0.267 0.858 SLICE_X178Y385 FDRE (Hold_fdre_C_D) 0.042 0.900 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.900 arrival time 1.031 ------------------------------------------------------------------- slack 0.131 Slack (MET) : 0.131ns (arrival time - required time) Source: ngFEC/g_pm[3].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[3].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/D (rising edge-triggered cell FDRE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_2 rise@0.000ns - txWordclkl12_2 rise@0.000ns) Data Path Delay: 0.173ns (logic 0.118ns (68.255%) route 0.055ns (31.745%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.899ns Source Clock Delay (SCD): 0.671ns Clock Pessimism Removal (CPR): 0.228ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y18 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.671 0.671 ngFEC/g_pm[3].phase_mon/sample_PS_Sync_inst/dest_clk SLICE_X160Y298 FDRE r ngFEC/g_pm[3].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X160Y298 FDRE (Prop_fdre_C_Q) 0.118 0.789 r ngFEC/g_pm[3].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/Q net (fo=1, routed) 0.055 0.844 ngFEC/g_pm[3].phase_mon/sample_PS_Sync_inst/syncstages_ff[0] SLICE_X160Y298 FDRE r ngFEC/g_pm[3].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y18 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.899 0.899 ngFEC/g_pm[3].phase_mon/sample_PS_Sync_inst/dest_clk SLICE_X160Y298 FDRE r ngFEC/g_pm[3].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/C clock pessimism -0.228 0.671 SLICE_X160Y298 FDRE (Hold_fdre_C_D) 0.042 0.713 ngFEC/g_pm[3].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1] ------------------------------------------------------------------- required time -0.713 arrival time 0.844 ------------------------------------------------------------------- slack 0.131 Slack (MET) : 0.138ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[102]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[2]/D (rising edge-triggered cell FDCE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_2 rise@0.000ns - txWordclkl12_2 rise@0.000ns) Data Path Delay: 0.239ns (logic 0.146ns (61.169%) route 0.093ns (38.831%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.886ns Source Clock Delay (SCD): 0.659ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y18 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.659 0.659 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X136Y288 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[102]/C ------------------------------------------------------------------- ------------------- SLICE_X136Y288 FDCE (Prop_fdce_C_Q) 0.118 0.777 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[102]/Q net (fo=1, routed) 0.093 0.870 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/data5[2] SLICE_X138Y288 LUT6 (Prop_lut6_I2_O) 0.028 0.898 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[2]_i_1__0/O net (fo=1, routed) 0.000 0.898 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[2]_i_1__0_n_0 SLICE_X138Y288 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[2]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y18 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.886 0.886 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X138Y288 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[2]/C clock pessimism -0.213 0.673 SLICE_X138Y288 FDCE (Hold_fdce_C_D) 0.087 0.760 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[2] ------------------------------------------------------------------- required time -0.760 arrival time 0.898 ------------------------------------------------------------------- slack 0.138 Slack (MET) : 0.149ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[83]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[3]/D (rising edge-triggered cell FDCE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_2 rise@0.000ns - txWordclkl12_2 rise@0.000ns) Data Path Delay: 0.223ns (logic 0.128ns (57.480%) route 0.095ns (42.520%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.888ns Source Clock Delay (SCD): 0.660ns Clock Pessimism Removal (CPR): 0.214ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y18 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.660 0.660 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X141Y288 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[83]/C ------------------------------------------------------------------- ------------------- SLICE_X141Y288 FDCE (Prop_fdce_C_Q) 0.100 0.760 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[83]/Q net (fo=1, routed) 0.095 0.855 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/data4[3] SLICE_X141Y289 LUT6 (Prop_lut6_I0_O) 0.028 0.883 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[3]_i_1__0/O net (fo=1, routed) 0.000 0.883 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[3]_i_1__0_n_0 SLICE_X141Y289 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[3]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y18 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.888 0.888 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X141Y289 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[3]/C clock pessimism -0.214 0.674 SLICE_X141Y289 FDCE (Hold_fdce_C_D) 0.060 0.734 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[3] ------------------------------------------------------------------- required time -0.734 arrival time 0.883 ------------------------------------------------------------------- slack 0.149 Slack (MET) : 0.152ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[94]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[14]/D (rising edge-triggered cell FDCE clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_2 rise@0.000ns - txWordclkl12_2 rise@0.000ns) Data Path Delay: 0.250ns (logic 0.128ns (51.296%) route 0.122ns (48.704%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.886ns Source Clock Delay (SCD): 0.659ns Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y18 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.659 0.659 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X139Y288 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[94]/C ------------------------------------------------------------------- ------------------- SLICE_X139Y288 FDCE (Prop_fdce_C_Q) 0.100 0.759 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[94]/Q net (fo=1, routed) 0.122 0.881 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/data4[14] SLICE_X138Y288 LUT6 (Prop_lut6_I0_O) 0.028 0.909 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[14]_i_1__0/O net (fo=1, routed) 0.000 0.909 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[14]_i_1__0_n_0 SLICE_X138Y288 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[14]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y18 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.886 0.886 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X138Y288 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[14]/C clock pessimism -0.216 0.670 SLICE_X138Y288 FDCE (Hold_fdce_C_D) 0.087 0.757 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[14] ------------------------------------------------------------------- required time -0.757 arrival time 0.909 ------------------------------------------------------------------- slack 0.152 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: txWordclkl12_2 Waveform(ns): { 0.000 4.100 } Period(ns): 8.200 Sources: { ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/TXUSRCLK n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y31 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK Min Period n/a GTXE2_CHANNEL/TXUSRCLK2 n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y31 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X151Y299 ngFEC/g_pm[3].phase_mon/PS_max_reg[7]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X151Y299 ngFEC/g_pm[3].phase_mon/PS_max_reg[8]/C Min Period n/a FDPE/C n/a 0.750 8.200 7.450 SLICE_X141Y298 ngFEC/g_pm[3].phase_mon/PS_min_reg[4]/C Min Period n/a FDPE/C n/a 0.750 8.200 7.450 SLICE_X141Y298 ngFEC/g_pm[3].phase_mon/PS_min_reg[5]/C Min Period n/a FDPE/C n/a 0.750 8.200 7.450 SLICE_X141Y298 ngFEC/g_pm[3].phase_mon/PS_min_reg[7]/C Min Period n/a FDPE/C n/a 0.750 8.200 7.450 SLICE_X141Y298 ngFEC/g_pm[3].phase_mon/PS_min_reg[8]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X160Y299 ngFEC/g_pm[3].phase_mon/en_chk_reg[2]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X151Y297 ngFEC/g_pm[3].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/C Low Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X146Y284 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK Low Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X146Y284 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X151Y299 ngFEC/g_pm[3].phase_mon/PS_max_reg[7]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X151Y299 ngFEC/g_pm[3].phase_mon/PS_max_reg[8]/C Low Pulse Width Slow FDPE/C n/a 0.400 4.100 3.700 SLICE_X141Y298 ngFEC/g_pm[3].phase_mon/PS_min_reg[4]/C Low Pulse Width Slow FDPE/C n/a 0.400 4.100 3.700 SLICE_X141Y298 ngFEC/g_pm[3].phase_mon/PS_min_reg[5]/C Low Pulse Width Slow FDPE/C n/a 0.400 4.100 3.700 SLICE_X141Y298 ngFEC/g_pm[3].phase_mon/PS_min_reg[7]/C Low Pulse Width Slow FDPE/C n/a 0.400 4.100 3.700 SLICE_X141Y298 ngFEC/g_pm[3].phase_mon/PS_min_reg[8]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X160Y299 ngFEC/g_pm[3].phase_mon/en_chk_reg[2]/C Low Pulse Width Fast FDRE/C n/a 0.400 4.100 3.700 SLICE_X151Y297 ngFEC/g_pm[3].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/C High Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X146Y284 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X146Y284 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X141Y286 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X141Y286 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[12]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X141Y286 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[15]/C High Pulse Width Fast FDCE/C n/a 0.350 4.100 3.750 SLICE_X135Y287 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[16]/C High Pulse Width Fast FDCE/C n/a 0.350 4.100 3.750 SLICE_X134Y287 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[19]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X140Y287 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[20]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X141Y288 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[22]/C High Pulse Width Fast FDCE/C n/a 0.350 4.100 3.750 SLICE_X135Y287 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[28]/C --------------------------------------------------------------------------------------------------- From Clock: txWordclkl12_3 To Clock: txWordclkl12_3 Setup : 0 Failing Endpoints, Worst Slack 4.288ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.108ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.458ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.288ns (required time - arrival time) Source: ngFEC/g_pm[4].phase_mon/PS_min_reg[3]/C (rising edge-triggered cell FDPE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[4].phase_mon/PS_min_reg[4]/CE (rising edge-triggered cell FDPE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_3 rise@8.200ns - txWordclkl12_3 rise@0.000ns) Data Path Delay: 3.571ns (logic 0.839ns (23.495%) route 2.732ns (76.505%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: -0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.233ns = ( 9.433 - 8.200 ) Source Clock Delay (SCD): 1.461ns Clock Pessimism Removal (CPR): 0.123ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y19 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.461 1.461 ngFEC/g_pm[4].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X132Y298 FDPE r ngFEC/g_pm[4].phase_mon/PS_min_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X132Y298 FDPE (Prop_fdpe_C_Q) 0.259 1.720 r ngFEC/g_pm[4].phase_mon/PS_min_reg[3]/Q net (fo=3, routed) 1.109 2.829 ngFEC/g_pm[4].phase_mon/PS_min_reg_n_0_[3] SLICE_X137Y306 LUT4 (Prop_lut4_I0_O) 0.043 2.872 r ngFEC/g_pm[4].phase_mon/PS_min[9]_i_12__2/O net (fo=1, routed) 0.000 2.872 ngFEC/g_pm[4].phase_mon/PS_min[9]_i_12__2_n_0 SLICE_X137Y306 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.267 3.139 r ngFEC/g_pm[4].phase_mon/PS_min_reg[9]_i_3__2/CO[3] net (fo=1, routed) 0.000 3.139 ngFEC/g_pm[4].phase_mon/PS_min_reg[9]_i_3__2_n_0 SLICE_X137Y307 CARRY4 (Prop_carry4_CI_CO[0]) 0.139 3.278 r ngFEC/g_pm[4].phase_mon/PS_min_reg[9]_i_2__2/CO[0] net (fo=1, routed) 0.697 3.975 ngFEC/g_pm[4].phase_mon/ltOp SLICE_X146Y298 LUT5 (Prop_lut5_I2_O) 0.131 4.106 r ngFEC/g_pm[4].phase_mon/PS_min[9]_i_1__2/O net (fo=10, routed) 0.926 5.032 ngFEC/g_pm[4].phase_mon/PS_min SLICE_X131Y299 FDPE r ngFEC/g_pm[4].phase_mon/PS_min_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 8.200 8.200 r BUFGCTRL_X0Y19 BUFG 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.233 9.433 ngFEC/g_pm[4].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X131Y299 FDPE r ngFEC/g_pm[4].phase_mon/PS_min_reg[4]/C clock pessimism 0.123 9.556 clock uncertainty -0.035 9.521 SLICE_X131Y299 FDPE (Setup_fdpe_C_CE) -0.201 9.320 ngFEC/g_pm[4].phase_mon/PS_min_reg[4] ------------------------------------------------------------------- required time 9.320 arrival time -5.032 ------------------------------------------------------------------- slack 4.288 Slack (MET) : 4.288ns (required time - arrival time) Source: ngFEC/g_pm[4].phase_mon/PS_min_reg[3]/C (rising edge-triggered cell FDPE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[4].phase_mon/PS_min_reg[6]/CE (rising edge-triggered cell FDPE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_3 rise@8.200ns - txWordclkl12_3 rise@0.000ns) Data Path Delay: 3.571ns (logic 0.839ns (23.495%) route 2.732ns (76.505%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: -0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.233ns = ( 9.433 - 8.200 ) Source Clock Delay (SCD): 1.461ns Clock Pessimism Removal (CPR): 0.123ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y19 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.461 1.461 ngFEC/g_pm[4].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X132Y298 FDPE r ngFEC/g_pm[4].phase_mon/PS_min_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X132Y298 FDPE (Prop_fdpe_C_Q) 0.259 1.720 r ngFEC/g_pm[4].phase_mon/PS_min_reg[3]/Q net (fo=3, routed) 1.109 2.829 ngFEC/g_pm[4].phase_mon/PS_min_reg_n_0_[3] SLICE_X137Y306 LUT4 (Prop_lut4_I0_O) 0.043 2.872 r ngFEC/g_pm[4].phase_mon/PS_min[9]_i_12__2/O net (fo=1, routed) 0.000 2.872 ngFEC/g_pm[4].phase_mon/PS_min[9]_i_12__2_n_0 SLICE_X137Y306 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.267 3.139 r ngFEC/g_pm[4].phase_mon/PS_min_reg[9]_i_3__2/CO[3] net (fo=1, routed) 0.000 3.139 ngFEC/g_pm[4].phase_mon/PS_min_reg[9]_i_3__2_n_0 SLICE_X137Y307 CARRY4 (Prop_carry4_CI_CO[0]) 0.139 3.278 r ngFEC/g_pm[4].phase_mon/PS_min_reg[9]_i_2__2/CO[0] net (fo=1, routed) 0.697 3.975 ngFEC/g_pm[4].phase_mon/ltOp SLICE_X146Y298 LUT5 (Prop_lut5_I2_O) 0.131 4.106 r ngFEC/g_pm[4].phase_mon/PS_min[9]_i_1__2/O net (fo=10, routed) 0.926 5.032 ngFEC/g_pm[4].phase_mon/PS_min SLICE_X131Y299 FDPE r ngFEC/g_pm[4].phase_mon/PS_min_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 8.200 8.200 r BUFGCTRL_X0Y19 BUFG 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.233 9.433 ngFEC/g_pm[4].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X131Y299 FDPE r ngFEC/g_pm[4].phase_mon/PS_min_reg[6]/C clock pessimism 0.123 9.556 clock uncertainty -0.035 9.521 SLICE_X131Y299 FDPE (Setup_fdpe_C_CE) -0.201 9.320 ngFEC/g_pm[4].phase_mon/PS_min_reg[6] ------------------------------------------------------------------- required time 9.320 arrival time -5.032 ------------------------------------------------------------------- slack 4.288 Slack (MET) : 4.289ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[9]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPMODE[0] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_3 rise@8.200ns - txWordclkl12_3 rise@0.000ns) Data Path Delay: 3.876ns (logic 0.259ns (6.682%) route 3.617ns (93.318%)) Logic Levels: 0 Clock Path Skew: 0.419ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.780ns = ( 9.980 - 8.200 ) Source Clock Delay (SCD): 1.404ns Clock Pessimism Removal (CPR): 0.043ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y19 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.404 1.404 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X126Y295 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X126Y295 FDCE (Prop_fdce_C_Q) 0.259 1.663 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[9]/Q net (fo=1, routed) 3.617 5.280 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[9] GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPMODE[0] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 8.200 8.200 r BUFGCTRL_X0Y19 BUFG 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.780 9.980 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.043 10.023 clock uncertainty -0.035 9.988 GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXCHARDISPMODE[0]) -0.419 9.569 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.569 arrival time -5.280 ------------------------------------------------------------------- slack 4.289 Slack (MET) : 4.308ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[6] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_3 rise@8.200ns - txWordclkl12_3 rise@0.000ns) Data Path Delay: 3.858ns (logic 0.223ns (5.781%) route 3.635ns (94.219%)) Logic Levels: 0 Clock Path Skew: 0.419ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.780ns = ( 9.980 - 8.200 ) Source Clock Delay (SCD): 1.404ns Clock Pessimism Removal (CPR): 0.043ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y19 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.404 1.404 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X129Y293 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X129Y293 FDCE (Prop_fdce_C_Q) 0.223 1.627 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/Q net (fo=1, routed) 3.635 5.262 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[6] GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[6] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 8.200 8.200 r BUFGCTRL_X0Y19 BUFG 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.780 9.980 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.043 10.023 clock uncertainty -0.035 9.988 GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[6]) -0.419 9.569 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.569 arrival time -5.262 ------------------------------------------------------------------- slack 4.308 Slack (MET) : 4.309ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPVAL[1] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_3 rise@8.200ns - txWordclkl12_3 rise@0.000ns) Data Path Delay: 3.856ns (logic 0.259ns (6.717%) route 3.597ns (93.283%)) Logic Levels: 0 Clock Path Skew: 0.419ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.780ns = ( 9.980 - 8.200 ) Source Clock Delay (SCD): 1.404ns Clock Pessimism Removal (CPR): 0.043ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y19 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.404 1.404 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X122Y294 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X122Y294 FDCE (Prop_fdce_C_Q) 0.259 1.663 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/Q net (fo=1, routed) 3.597 5.260 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[18] GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPVAL[1] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 8.200 8.200 r BUFGCTRL_X0Y19 BUFG 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.780 9.980 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.043 10.023 clock uncertainty -0.035 9.988 GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXCHARDISPVAL[1]) -0.419 9.569 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.569 arrival time -5.260 ------------------------------------------------------------------- slack 4.309 Slack (MET) : 4.364ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[7] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_3 rise@8.200ns - txWordclkl12_3 rise@0.000ns) Data Path Delay: 3.802ns (logic 0.259ns (6.812%) route 3.543ns (93.188%)) Logic Levels: 0 Clock Path Skew: 0.420ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.780ns = ( 9.980 - 8.200 ) Source Clock Delay (SCD): 1.403ns Clock Pessimism Removal (CPR): 0.043ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y19 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.403 1.403 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X126Y292 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X126Y292 FDCE (Prop_fdce_C_Q) 0.259 1.662 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/Q net (fo=1, routed) 3.543 5.205 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[7] GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[7] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 8.200 8.200 r BUFGCTRL_X0Y19 BUFG 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.780 9.980 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.043 10.023 clock uncertainty -0.035 9.988 GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[7]) -0.419 9.569 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.569 arrival time -5.205 ------------------------------------------------------------------- slack 4.364 Slack (MET) : 4.367ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[3]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[3] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_3 rise@8.200ns - txWordclkl12_3 rise@0.000ns) Data Path Delay: 3.799ns (logic 0.259ns (6.817%) route 3.540ns (93.183%)) Logic Levels: 0 Clock Path Skew: 0.420ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.780ns = ( 9.980 - 8.200 ) Source Clock Delay (SCD): 1.403ns Clock Pessimism Removal (CPR): 0.043ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y19 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.403 1.403 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X126Y292 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X126Y292 FDCE (Prop_fdce_C_Q) 0.259 1.662 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[3]/Q net (fo=1, routed) 3.540 5.202 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[3] GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[3] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 8.200 8.200 r BUFGCTRL_X0Y19 BUFG 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.780 9.980 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.043 10.023 clock uncertainty -0.035 9.988 GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[3]) -0.419 9.569 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.569 arrival time -5.202 ------------------------------------------------------------------- slack 4.367 Slack (MET) : 4.381ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[16]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[14] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_3 rise@8.200ns - txWordclkl12_3 rise@0.000ns) Data Path Delay: 3.784ns (logic 0.259ns (6.845%) route 3.525ns (93.155%)) Logic Levels: 0 Clock Path Skew: 0.419ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.780ns = ( 9.980 - 8.200 ) Source Clock Delay (SCD): 1.404ns Clock Pessimism Removal (CPR): 0.043ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y19 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.404 1.404 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X122Y294 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X122Y294 FDCE (Prop_fdce_C_Q) 0.259 1.663 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[16]/Q net (fo=1, routed) 3.525 5.188 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[16] GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[14] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 8.200 8.200 r BUFGCTRL_X0Y19 BUFG 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.780 9.980 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.043 10.023 clock uncertainty -0.035 9.988 GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[14]) -0.419 9.569 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.569 arrival time -5.188 ------------------------------------------------------------------- slack 4.381 Slack (MET) : 4.393ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[17]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[15] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_3 rise@8.200ns - txWordclkl12_3 rise@0.000ns) Data Path Delay: 3.772ns (logic 0.259ns (6.866%) route 3.513ns (93.134%)) Logic Levels: 0 Clock Path Skew: 0.419ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.780ns = ( 9.980 - 8.200 ) Source Clock Delay (SCD): 1.404ns Clock Pessimism Removal (CPR): 0.043ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y19 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.404 1.404 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X122Y294 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X122Y294 FDCE (Prop_fdce_C_Q) 0.259 1.663 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[17]/Q net (fo=1, routed) 3.513 5.176 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[17] GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[15] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 8.200 8.200 r BUFGCTRL_X0Y19 BUFG 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.780 9.980 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.043 10.023 clock uncertainty -0.035 9.988 GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[15]) -0.419 9.569 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.569 arrival time -5.176 ------------------------------------------------------------------- slack 4.393 Slack (MET) : 4.396ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[11]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[9] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_3 rise@8.200ns - txWordclkl12_3 rise@0.000ns) Data Path Delay: 3.769ns (logic 0.259ns (6.872%) route 3.510ns (93.128%)) Logic Levels: 0 Clock Path Skew: 0.419ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.780ns = ( 9.980 - 8.200 ) Source Clock Delay (SCD): 1.404ns Clock Pessimism Removal (CPR): 0.043ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y19 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.404 1.404 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X122Y294 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X122Y294 FDCE (Prop_fdce_C_Q) 0.259 1.663 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[11]/Q net (fo=1, routed) 3.510 5.173 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[11] GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[9] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 8.200 8.200 r BUFGCTRL_X0Y19 BUFG 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.780 9.980 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.043 10.023 clock uncertainty -0.035 9.988 GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[9]) -0.419 9.569 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.569 arrival time -5.173 ------------------------------------------------------------------- slack 4.396 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_3 rise@0.000ns - txWordclkl12_3 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.111ns Source Clock Delay (SCD): 0.846ns Clock Pessimism Removal (CPR): 0.265ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y19 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.846 0.846 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in SLICE_X171Y373 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X171Y373 FDRE (Prop_fdre_C_Q) 0.100 0.946 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q net (fo=1, routed) 0.055 1.001 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync1 SLICE_X171Y373 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y19 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.111 1.111 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in SLICE_X171Y373 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C clock pessimism -0.265 0.846 SLICE_X171Y373 FDRE (Hold_fdre_C_D) 0.047 0.893 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.893 arrival time 1.001 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_3 rise@0.000ns - txWordclkl12_3 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.116ns Source Clock Delay (SCD): 0.850ns Clock Pessimism Removal (CPR): 0.266ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y19 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.850 0.850 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in SLICE_X171Y369 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X171Y369 FDRE (Prop_fdre_C_Q) 0.100 0.950 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/Q net (fo=1, routed) 0.055 1.005 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync1 SLICE_X171Y369 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y19 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.116 1.116 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in SLICE_X171Y369 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/C clock pessimism -0.266 0.850 SLICE_X171Y369 FDRE (Hold_fdre_C_D) 0.047 0.897 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.897 arrival time 1.005 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/g_pm[4].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[4].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/D (rising edge-triggered cell FDRE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_3 rise@0.000ns - txWordclkl12_3 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.893ns Source Clock Delay (SCD): 0.666ns Clock Pessimism Removal (CPR): 0.227ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y19 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.666 0.666 ngFEC/g_pm[4].phase_mon/sample_PS_Sync_inst/dest_clk SLICE_X145Y298 FDRE r ngFEC/g_pm[4].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X145Y298 FDRE (Prop_fdre_C_Q) 0.100 0.766 r ngFEC/g_pm[4].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/Q net (fo=1, routed) 0.055 0.821 ngFEC/g_pm[4].phase_mon/sample_PS_Sync_inst/syncstages_ff[0] SLICE_X145Y298 FDRE r ngFEC/g_pm[4].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y19 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.893 0.893 ngFEC/g_pm[4].phase_mon/sample_PS_Sync_inst/dest_clk SLICE_X145Y298 FDRE r ngFEC/g_pm[4].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/C clock pessimism -0.227 0.666 SLICE_X145Y298 FDRE (Hold_fdre_C_D) 0.047 0.713 ngFEC/g_pm[4].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1] ------------------------------------------------------------------- required time -0.713 arrival time 0.821 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D (rising edge-triggered cell FDRE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_3 rise@0.000ns - txWordclkl12_3 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.889ns Source Clock Delay (SCD): 0.661ns Clock Pessimism Removal (CPR): 0.228ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y19 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.661 0.661 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk SLICE_X141Y292 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X141Y292 FDRE (Prop_fdre_C_Q) 0.100 0.761 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/Q net (fo=1, routed) 0.055 0.816 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff[0] SLICE_X141Y292 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y19 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.889 0.889 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk SLICE_X141Y292 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/C clock pessimism -0.228 0.661 SLICE_X141Y292 FDRE (Hold_fdre_C_D) 0.047 0.708 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1] ------------------------------------------------------------------- required time -0.708 arrival time 0.816 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.126ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[107]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/D (rising edge-triggered cell FDCE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_3 rise@0.000ns - txWordclkl12_3 rise@0.000ns) Data Path Delay: 0.247ns (logic 0.146ns (59.039%) route 0.101ns (40.961%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.034ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.852ns Source Clock Delay (SCD): 0.625ns Clock Pessimism Removal (CPR): 0.193ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y19 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.625 0.625 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X122Y292 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[107]/C ------------------------------------------------------------------- ------------------- SLICE_X122Y292 FDCE (Prop_fdce_C_Q) 0.118 0.743 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[107]/Q net (fo=1, routed) 0.101 0.844 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/data5[7] SLICE_X126Y292 LUT6 (Prop_lut6_I2_O) 0.028 0.872 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[7]_i_1__1/O net (fo=1, routed) 0.000 0.872 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[7]_i_1__1_n_0 SLICE_X126Y292 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y19 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.852 0.852 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X126Y292 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/C clock pessimism -0.193 0.659 SLICE_X126Y292 FDCE (Hold_fdce_C_D) 0.087 0.746 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7] ------------------------------------------------------------------- required time -0.746 arrival time 0.872 ------------------------------------------------------------------- slack 0.126 Slack (MET) : 0.131ns (arrival time - required time) Source: ngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D (rising edge-triggered cell FDRE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_3 rise@0.000ns - txWordclkl12_3 rise@0.000ns) Data Path Delay: 0.173ns (logic 0.118ns (68.255%) route 0.055ns (31.745%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.894ns Source Clock Delay (SCD): 0.667ns Clock Pessimism Removal (CPR): 0.227ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y19 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.667 0.667 ngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/dest_clk SLICE_X146Y298 FDRE r ngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X146Y298 FDRE (Prop_fdre_C_Q) 0.118 0.785 r ngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/Q net (fo=1, routed) 0.055 0.840 ngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff[0] SLICE_X146Y298 FDRE r ngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y19 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.894 0.894 ngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/dest_clk SLICE_X146Y298 FDRE r ngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/C clock pessimism -0.227 0.667 SLICE_X146Y298 FDRE (Hold_fdre_C_D) 0.042 0.709 ngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1] ------------------------------------------------------------------- required time -0.709 arrival time 0.840 ------------------------------------------------------------------- slack 0.131 Slack (MET) : 0.131ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/C (rising edge-triggered cell FDRE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/D (rising edge-triggered cell SRL16E clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_3 rise@0.000ns - txWordclkl12_3 rise@0.000ns) Data Path Delay: 0.248ns (logic 0.100ns (40.286%) route 0.148ns (59.714%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.890ns Source Clock Delay (SCD): 0.661ns Clock Pessimism Removal (CPR): 0.214ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y19 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.661 0.661 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk SLICE_X141Y292 FDRE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X141Y292 FDRE (Prop_fdre_C_Q) 0.100 0.761 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/Q net (fo=1, routed) 0.148 0.909 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/dest_out SLICE_X140Y293 SRL16E r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y19 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.890 0.890 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X140Y293 SRL16E r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK clock pessimism -0.214 0.676 SLICE_X140Y293 SRL16E (Hold_srl16e_CLK_D) 0.102 0.778 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3 ------------------------------------------------------------------- required time -0.778 arrival time 0.909 ------------------------------------------------------------------- slack 0.131 Slack (MET) : 0.137ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[85]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/D (rising edge-triggered cell FDCE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_3 rise@0.000ns - txWordclkl12_3 rise@0.000ns) Data Path Delay: 0.208ns (logic 0.128ns (61.615%) route 0.080ns (38.385%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.854ns Source Clock Delay (SCD): 0.627ns Clock Pessimism Removal (CPR): 0.216ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y19 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.627 0.627 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X128Y294 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[85]/C ------------------------------------------------------------------- ------------------- SLICE_X128Y294 FDCE (Prop_fdce_C_Q) 0.100 0.727 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[85]/Q net (fo=1, routed) 0.080 0.807 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/data4[5] SLICE_X129Y294 LUT6 (Prop_lut6_I0_O) 0.028 0.835 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[5]_i_1__1/O net (fo=1, routed) 0.000 0.835 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[5]_i_1__1_n_0 SLICE_X129Y294 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y19 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.854 0.854 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X129Y294 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/C clock pessimism -0.216 0.638 SLICE_X129Y294 FDCE (Hold_fdce_C_D) 0.060 0.698 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5] ------------------------------------------------------------------- required time -0.698 arrival time 0.835 ------------------------------------------------------------------- slack 0.137 Slack (MET) : 0.140ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[117]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[17]/D (rising edge-triggered cell FDCE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_3 rise@0.000ns - txWordclkl12_3 rise@0.000ns) Data Path Delay: 0.241ns (logic 0.146ns (60.660%) route 0.095ns (39.340%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.853ns Source Clock Delay (SCD): 0.626ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y19 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.626 0.626 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X122Y295 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[117]/C ------------------------------------------------------------------- ------------------- SLICE_X122Y295 FDCE (Prop_fdce_C_Q) 0.118 0.744 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[117]/Q net (fo=1, routed) 0.095 0.839 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/data5[17] SLICE_X122Y294 LUT6 (Prop_lut6_I2_O) 0.028 0.867 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[17]_i_1__1/O net (fo=1, routed) 0.000 0.867 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[17]_i_1__1_n_0 SLICE_X122Y294 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[17]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y19 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.853 0.853 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X122Y294 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[17]/C clock pessimism -0.213 0.640 SLICE_X122Y294 FDCE (Hold_fdce_C_D) 0.087 0.727 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[17] ------------------------------------------------------------------- required time -0.727 arrival time 0.867 ------------------------------------------------------------------- slack 0.140 Slack (MET) : 0.159ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[80]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/D (rising edge-triggered cell FDCE clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_3 rise@0.000ns - txWordclkl12_3 rise@0.000ns) Data Path Delay: 0.254ns (logic 0.128ns (50.345%) route 0.126ns (49.655%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.034ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.854ns Source Clock Delay (SCD): 0.627ns Clock Pessimism Removal (CPR): 0.193ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y19 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.627 0.627 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X127Y293 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[80]/C ------------------------------------------------------------------- ------------------- SLICE_X127Y293 FDCE (Prop_fdce_C_Q) 0.100 0.727 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[80]/Q net (fo=1, routed) 0.126 0.853 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/data4[0] SLICE_X129Y293 LUT6 (Prop_lut6_I0_O) 0.028 0.881 r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[0]_i_1__1/O net (fo=1, routed) 0.000 0.881 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[0]_i_1__1_n_0 SLICE_X129Y293 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y19 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.854 0.854 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X129Y293 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/C clock pessimism -0.193 0.661 SLICE_X129Y293 FDCE (Hold_fdce_C_D) 0.061 0.722 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0] ------------------------------------------------------------------- required time -0.722 arrival time 0.881 ------------------------------------------------------------------- slack 0.159 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: txWordclkl12_3 Waveform(ns): { 0.000 4.100 } Period(ns): 8.200 Sources: { ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/TXUSRCLK n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y30 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK Min Period n/a GTXE2_CHANNEL/TXUSRCLK2 n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y30 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X155Y299 ngFEC/g_pm[4].phase_mon/PS_max_reg[4]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X155Y299 ngFEC/g_pm[4].phase_mon/PS_max_reg[5]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X155Y299 ngFEC/g_pm[4].phase_mon/PS_max_reg[6]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X155Y299 ngFEC/g_pm[4].phase_mon/PS_max_reg[7]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X140Y298 ngFEC/g_pm[4].phase_mon/en_chk_reg[2]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X146Y298 ngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X146Y298 ngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[2]/C Min Period n/a FDPE/C n/a 0.750 8.200 7.450 SLICE_X147Y296 ngFEC/g_pm[4].phase_mon/inh_cntr_reg[2]/C Low Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X140Y293 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK Low Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X140Y293 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X155Y299 ngFEC/g_pm[4].phase_mon/PS_max_reg[4]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X155Y299 ngFEC/g_pm[4].phase_mon/PS_max_reg[4]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X155Y299 ngFEC/g_pm[4].phase_mon/PS_max_reg[5]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X155Y299 ngFEC/g_pm[4].phase_mon/PS_max_reg[5]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X155Y299 ngFEC/g_pm[4].phase_mon/PS_max_reg[6]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X155Y299 ngFEC/g_pm[4].phase_mon/PS_max_reg[6]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X155Y299 ngFEC/g_pm[4].phase_mon/PS_max_reg[7]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X155Y299 ngFEC/g_pm[4].phase_mon/PS_max_reg[7]/C High Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X140Y293 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X140Y293 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X124Y293 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[10]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X124Y293 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[13]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X126Y292 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[14]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X124Y293 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[19]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X126Y292 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[3]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X126Y292 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X124Y293 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[8]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X125Y290 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[105]/C --------------------------------------------------------------------------------------------------- From Clock: txWordclkl12_4 To Clock: txWordclkl12_4 Setup : 0 Failing Endpoints, Worst Slack 5.158ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.094ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.458ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.158ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[9]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPMODE[0] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_4 rise@8.200ns - txWordclkl12_4 rise@0.000ns) Data Path Delay: 2.886ns (logic 0.223ns (7.726%) route 2.663ns (92.274%)) Logic Levels: 0 Clock Path Skew: 0.298ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.650ns = ( 9.850 - 8.200 ) Source Clock Delay (SCD): 1.365ns Clock Pessimism Removal (CPR): 0.013ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 1.365 1.365 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X184Y236 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X184Y236 FDCE (Prop_fdce_C_Q) 0.223 1.588 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[9]/Q net (fo=1, routed) 2.663 4.251 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[9] GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPMODE[0] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 8.200 8.200 r BUFGCTRL_X0Y16 BUFG 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 1.650 9.850 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.013 9.863 clock uncertainty -0.035 9.828 GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXCHARDISPMODE[0]) -0.419 9.409 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.409 arrival time -4.251 ------------------------------------------------------------------- slack 5.158 Slack (MET) : 5.284ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[8]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPVAL[0] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_4 rise@8.200ns - txWordclkl12_4 rise@0.000ns) Data Path Delay: 2.760ns (logic 0.223ns (8.081%) route 2.537ns (91.919%)) Logic Levels: 0 Clock Path Skew: 0.297ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.650ns = ( 9.850 - 8.200 ) Source Clock Delay (SCD): 1.366ns Clock Pessimism Removal (CPR): 0.013ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 1.366 1.366 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X184Y238 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X184Y238 FDCE (Prop_fdce_C_Q) 0.223 1.589 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[8]/Q net (fo=1, routed) 2.537 4.126 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[8] GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPVAL[0] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 8.200 8.200 r BUFGCTRL_X0Y16 BUFG 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 1.650 9.850 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.013 9.863 clock uncertainty -0.035 9.828 GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXCHARDISPVAL[0]) -0.419 9.409 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.409 arrival time -4.126 ------------------------------------------------------------------- slack 5.284 Slack (MET) : 5.308ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[5] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_4 rise@8.200ns - txWordclkl12_4 rise@0.000ns) Data Path Delay: 2.736ns (logic 0.223ns (8.150%) route 2.513ns (91.850%)) Logic Levels: 0 Clock Path Skew: 0.298ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.650ns = ( 9.850 - 8.200 ) Source Clock Delay (SCD): 1.365ns Clock Pessimism Removal (CPR): 0.013ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 1.365 1.365 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X185Y236 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X185Y236 FDCE (Prop_fdce_C_Q) 0.223 1.588 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/Q net (fo=1, routed) 2.513 4.101 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[5] GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[5] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 8.200 8.200 r BUFGCTRL_X0Y16 BUFG 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 1.650 9.850 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.013 9.863 clock uncertainty -0.035 9.828 GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[5]) -0.419 9.409 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.409 arrival time -4.101 ------------------------------------------------------------------- slack 5.308 Slack (MET) : 5.336ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[7] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_4 rise@8.200ns - txWordclkl12_4 rise@0.000ns) Data Path Delay: 2.707ns (logic 0.223ns (8.236%) route 2.484ns (91.764%)) Logic Levels: 0 Clock Path Skew: 0.297ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.650ns = ( 9.850 - 8.200 ) Source Clock Delay (SCD): 1.366ns Clock Pessimism Removal (CPR): 0.013ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 1.366 1.366 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X188Y238 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X188Y238 FDCE (Prop_fdce_C_Q) 0.223 1.589 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/Q net (fo=1, routed) 2.484 4.073 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[7] GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[7] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 8.200 8.200 r BUFGCTRL_X0Y16 BUFG 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 1.650 9.850 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.013 9.863 clock uncertainty -0.035 9.828 GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[7]) -0.419 9.409 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.409 arrival time -4.073 ------------------------------------------------------------------- slack 5.336 Slack (MET) : 5.365ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[4]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[4] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_4 rise@8.200ns - txWordclkl12_4 rise@0.000ns) Data Path Delay: 2.679ns (logic 0.223ns (8.325%) route 2.456ns (91.675%)) Logic Levels: 0 Clock Path Skew: 0.298ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.650ns = ( 9.850 - 8.200 ) Source Clock Delay (SCD): 1.365ns Clock Pessimism Removal (CPR): 0.013ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 1.365 1.365 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X185Y236 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X185Y236 FDCE (Prop_fdce_C_Q) 0.223 1.588 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[4]/Q net (fo=1, routed) 2.456 4.044 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[4] GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[4] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 8.200 8.200 r BUFGCTRL_X0Y16 BUFG 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 1.650 9.850 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.013 9.863 clock uncertainty -0.035 9.828 GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[4]) -0.419 9.409 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.409 arrival time -4.044 ------------------------------------------------------------------- slack 5.365 Slack (MET) : 5.369ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[17]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[15] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_4 rise@8.200ns - txWordclkl12_4 rise@0.000ns) Data Path Delay: 2.674ns (logic 0.223ns (8.338%) route 2.451ns (91.662%)) Logic Levels: 0 Clock Path Skew: 0.297ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.650ns = ( 9.850 - 8.200 ) Source Clock Delay (SCD): 1.366ns Clock Pessimism Removal (CPR): 0.013ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 1.366 1.366 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X184Y237 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X184Y237 FDCE (Prop_fdce_C_Q) 0.223 1.589 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[17]/Q net (fo=1, routed) 2.451 4.040 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[17] GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[15] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 8.200 8.200 r BUFGCTRL_X0Y16 BUFG 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 1.650 9.850 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.013 9.863 clock uncertainty -0.035 9.828 GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[15]) -0.419 9.409 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.409 arrival time -4.040 ------------------------------------------------------------------- slack 5.369 Slack (MET) : 5.400ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[1] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_4 rise@8.200ns - txWordclkl12_4 rise@0.000ns) Data Path Delay: 2.643ns (logic 0.223ns (8.436%) route 2.420ns (91.564%)) Logic Levels: 0 Clock Path Skew: 0.297ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.650ns = ( 9.850 - 8.200 ) Source Clock Delay (SCD): 1.366ns Clock Pessimism Removal (CPR): 0.013ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 1.366 1.366 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X188Y238 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X188Y238 FDCE (Prop_fdce_C_Q) 0.223 1.589 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/Q net (fo=1, routed) 2.420 4.009 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[1] GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[1] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 8.200 8.200 r BUFGCTRL_X0Y16 BUFG 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 1.650 9.850 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.013 9.863 clock uncertainty -0.035 9.828 GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[1]) -0.419 9.409 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.409 arrival time -4.009 ------------------------------------------------------------------- slack 5.400 Slack (MET) : 5.413ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[12]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[10] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_4 rise@8.200ns - txWordclkl12_4 rise@0.000ns) Data Path Delay: 2.630ns (logic 0.223ns (8.480%) route 2.407ns (91.520%)) Logic Levels: 0 Clock Path Skew: 0.297ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.650ns = ( 9.850 - 8.200 ) Source Clock Delay (SCD): 1.366ns Clock Pessimism Removal (CPR): 0.013ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 1.366 1.366 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X184Y237 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X184Y237 FDCE (Prop_fdce_C_Q) 0.223 1.589 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[12]/Q net (fo=1, routed) 2.407 3.996 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[12] GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[10] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 8.200 8.200 r BUFGCTRL_X0Y16 BUFG 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 1.650 9.850 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.013 9.863 clock uncertainty -0.035 9.828 GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[10]) -0.419 9.409 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.409 arrival time -3.996 ------------------------------------------------------------------- slack 5.413 Slack (MET) : 5.424ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[13]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[11] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_4 rise@8.200ns - txWordclkl12_4 rise@0.000ns) Data Path Delay: 2.618ns (logic 0.223ns (8.516%) route 2.395ns (91.484%)) Logic Levels: 0 Clock Path Skew: 0.296ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.650ns = ( 9.850 - 8.200 ) Source Clock Delay (SCD): 1.367ns Clock Pessimism Removal (CPR): 0.013ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 1.367 1.367 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X187Y239 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X187Y239 FDCE (Prop_fdce_C_Q) 0.223 1.590 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[13]/Q net (fo=1, routed) 2.395 3.985 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[13] GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[11] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 8.200 8.200 r BUFGCTRL_X0Y16 BUFG 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 1.650 9.850 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.013 9.863 clock uncertainty -0.035 9.828 GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[11]) -0.419 9.409 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.409 arrival time -3.985 ------------------------------------------------------------------- slack 5.424 Slack (MET) : 5.467ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPVAL[1] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_4 rise@8.200ns - txWordclkl12_4 rise@0.000ns) Data Path Delay: 2.575ns (logic 0.223ns (8.659%) route 2.352ns (91.341%)) Logic Levels: 0 Clock Path Skew: 0.296ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.650ns = ( 9.850 - 8.200 ) Source Clock Delay (SCD): 1.367ns Clock Pessimism Removal (CPR): 0.013ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 1.367 1.367 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X187Y239 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X187Y239 FDCE (Prop_fdce_C_Q) 0.223 1.590 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/Q net (fo=1, routed) 2.352 3.942 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[18] GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPVAL[1] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 8.200 8.200 r BUFGCTRL_X0Y16 BUFG 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 1.650 9.850 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.013 9.863 clock uncertainty -0.035 9.828 GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXCHARDISPVAL[1]) -0.419 9.409 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.409 arrival time -3.942 ------------------------------------------------------------------- slack 5.467 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.094ns (arrival time - required time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/C (rising edge-triggered cell FDRE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/D (rising edge-triggered cell SRL16E clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_4 rise@0.000ns - txWordclkl12_4 rise@0.000ns) Data Path Delay: 0.207ns (logic 0.100ns (48.254%) route 0.107ns (51.746%)) Logic Levels: 0 Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.831ns Source Clock Delay (SCD): 0.622ns Clock Pessimism Removal (CPR): 0.198ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 0.622 0.622 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk SLICE_X183Y243 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X183Y243 FDRE (Prop_fdre_C_Q) 0.100 0.722 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/Q net (fo=1, routed) 0.107 0.829 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/dest_out SLICE_X182Y243 SRL16E r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 0.831 0.831 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X182Y243 SRL16E r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK clock pessimism -0.198 0.633 SLICE_X182Y243 SRL16E (Hold_srl16e_CLK_D) 0.102 0.735 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3 ------------------------------------------------------------------- required time -0.735 arrival time 0.829 ------------------------------------------------------------------- slack 0.094 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_4 rise@0.000ns - txWordclkl12_4 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.024ns Source Clock Delay (SCD): 0.777ns Clock Pessimism Removal (CPR): 0.247ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 0.777 0.777 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in SLICE_X177Y315 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X177Y315 FDRE (Prop_fdre_C_Q) 0.100 0.877 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q net (fo=1, routed) 0.055 0.932 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync1 SLICE_X177Y315 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 1.024 1.024 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in SLICE_X177Y315 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C clock pessimism -0.247 0.777 SLICE_X177Y315 FDRE (Hold_fdre_C_D) 0.047 0.824 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.824 arrival time 0.932 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D (rising edge-triggered cell FDRE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_4 rise@0.000ns - txWordclkl12_4 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.890ns Source Clock Delay (SCD): 0.662ns Clock Pessimism Removal (CPR): 0.228ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 0.662 0.662 ngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/dest_clk SLICE_X143Y295 FDRE r ngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X143Y295 FDRE (Prop_fdre_C_Q) 0.100 0.762 r ngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/Q net (fo=1, routed) 0.055 0.817 ngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff[0] SLICE_X143Y295 FDRE r ngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 0.890 0.890 ngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/dest_clk SLICE_X143Y295 FDRE r ngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/C clock pessimism -0.228 0.662 SLICE_X143Y295 FDRE (Hold_fdre_C_D) 0.047 0.709 ngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1] ------------------------------------------------------------------- required time -0.709 arrival time 0.817 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/g_pm[1].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[1].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/D (rising edge-triggered cell FDRE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_4 rise@0.000ns - txWordclkl12_4 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.890ns Source Clock Delay (SCD): 0.662ns Clock Pessimism Removal (CPR): 0.228ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 0.662 0.662 ngFEC/g_pm[1].phase_mon/sample_PS_Sync_inst/dest_clk SLICE_X143Y295 FDRE r ngFEC/g_pm[1].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X143Y295 FDRE (Prop_fdre_C_Q) 0.100 0.762 r ngFEC/g_pm[1].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/Q net (fo=1, routed) 0.055 0.817 ngFEC/g_pm[1].phase_mon/sample_PS_Sync_inst/syncstages_ff[0] SLICE_X143Y295 FDRE r ngFEC/g_pm[1].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 0.890 0.890 ngFEC/g_pm[1].phase_mon/sample_PS_Sync_inst/dest_clk SLICE_X143Y295 FDRE r ngFEC/g_pm[1].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/C clock pessimism -0.228 0.662 SLICE_X143Y295 FDRE (Hold_fdre_C_D) 0.047 0.709 ngFEC/g_pm[1].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1] ------------------------------------------------------------------- required time -0.709 arrival time 0.817 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D (rising edge-triggered cell FDRE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_4 rise@0.000ns - txWordclkl12_4 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.831ns Source Clock Delay (SCD): 0.622ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 0.622 0.622 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk SLICE_X183Y243 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X183Y243 FDRE (Prop_fdre_C_Q) 0.100 0.722 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/Q net (fo=1, routed) 0.055 0.777 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff[0] SLICE_X183Y243 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 0.831 0.831 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk SLICE_X183Y243 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/C clock pessimism -0.209 0.622 SLICE_X183Y243 FDRE (Hold_fdre_C_D) 0.047 0.669 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1] ------------------------------------------------------------------- required time -0.669 arrival time 0.777 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_4 rise@0.000ns - txWordclkl12_4 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.021ns Source Clock Delay (SCD): 0.775ns Clock Pessimism Removal (CPR): 0.246ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 0.775 0.775 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in SLICE_X173Y315 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X173Y315 FDRE (Prop_fdre_C_Q) 0.100 0.875 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/Q net (fo=1, routed) 0.055 0.930 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync1 SLICE_X173Y315 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 1.021 1.021 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in SLICE_X173Y315 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/C clock pessimism -0.246 0.775 SLICE_X173Y315 FDRE (Hold_fdre_C_D) 0.047 0.822 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.822 arrival time 0.930 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.141ns (arrival time - required time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[116]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[16]/D (rising edge-triggered cell FDCE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_4 rise@0.000ns - txWordclkl12_4 rise@0.000ns) Data Path Delay: 0.212ns (logic 0.128ns (60.480%) route 0.084ns (39.520%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.829ns Source Clock Delay (SCD): 0.620ns Clock Pessimism Removal (CPR): 0.198ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 0.620 0.620 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X185Y238 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[116]/C ------------------------------------------------------------------- ------------------- SLICE_X185Y238 FDCE (Prop_fdce_C_Q) 0.100 0.720 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[116]/Q net (fo=1, routed) 0.084 0.804 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/data5[16] SLICE_X184Y238 LUT6 (Prop_lut6_I2_O) 0.028 0.832 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[16]_i_1__2/O net (fo=1, routed) 0.000 0.832 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[16]_i_1__2_n_0 SLICE_X184Y238 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[16]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 0.829 0.829 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X184Y238 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[16]/C clock pessimism -0.198 0.631 SLICE_X184Y238 FDCE (Hold_fdce_C_D) 0.060 0.691 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[16] ------------------------------------------------------------------- required time -0.691 arrival time 0.832 ------------------------------------------------------------------- slack 0.141 Slack (MET) : 0.145ns (arrival time - required time) Source: ngFEC/g_pm[1].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[2]/C (rising edge-triggered cell FDRE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[1].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[3]/D (rising edge-triggered cell FDRE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_4 rise@0.000ns - txWordclkl12_4 rise@0.000ns) Data Path Delay: 0.142ns (logic 0.091ns (64.084%) route 0.051ns (35.916%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.890ns Source Clock Delay (SCD): 0.662ns Clock Pessimism Removal (CPR): 0.228ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 0.662 0.662 ngFEC/g_pm[1].phase_mon/sample_PS_Sync_inst/dest_clk SLICE_X143Y295 FDRE r ngFEC/g_pm[1].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X143Y295 FDRE (Prop_fdre_C_Q) 0.091 0.753 r ngFEC/g_pm[1].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[2]/Q net (fo=1, routed) 0.051 0.804 ngFEC/g_pm[1].phase_mon/sample_PS_Sync_inst/syncstages_ff[2] SLICE_X143Y295 FDRE r ngFEC/g_pm[1].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[3]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 0.890 0.890 ngFEC/g_pm[1].phase_mon/sample_PS_Sync_inst/dest_clk SLICE_X143Y295 FDRE r ngFEC/g_pm[1].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[3]/C clock pessimism -0.228 0.662 SLICE_X143Y295 FDRE (Hold_fdre_C_D) -0.003 0.659 ngFEC/g_pm[1].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[3] ------------------------------------------------------------------- required time -0.659 arrival time 0.804 ------------------------------------------------------------------- slack 0.145 Slack (MET) : 0.147ns (arrival time - required time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[111]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[11]/D (rising edge-triggered cell FDCE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_4 rise@0.000ns - txWordclkl12_4 rise@0.000ns) Data Path Delay: 0.221ns (logic 0.128ns (58.001%) route 0.093ns (41.999%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.829ns Source Clock Delay (SCD): 0.620ns Clock Pessimism Removal (CPR): 0.195ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 0.620 0.620 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X185Y239 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[111]/C ------------------------------------------------------------------- ------------------- SLICE_X185Y239 FDCE (Prop_fdce_C_Q) 0.100 0.720 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[111]/Q net (fo=1, routed) 0.093 0.813 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/data5[11] SLICE_X187Y239 LUT6 (Prop_lut6_I2_O) 0.028 0.841 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[11]_i_1__2/O net (fo=1, routed) 0.000 0.841 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[11]_i_1__2_n_0 SLICE_X187Y239 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[11]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 0.829 0.829 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X187Y239 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[11]/C clock pessimism -0.195 0.634 SLICE_X187Y239 FDCE (Hold_fdce_C_D) 0.060 0.694 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[11] ------------------------------------------------------------------- required time -0.694 arrival time 0.841 ------------------------------------------------------------------- slack 0.147 Slack (MET) : 0.148ns (arrival time - required time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[84]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[4]/D (rising edge-triggered cell FDCE clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_4 rise@0.000ns - txWordclkl12_4 rise@0.000ns) Data Path Delay: 0.220ns (logic 0.128ns (58.265%) route 0.092ns (41.735%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.826ns Source Clock Delay (SCD): 0.619ns Clock Pessimism Removal (CPR): 0.195ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 0.619 0.619 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X185Y237 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[84]/C ------------------------------------------------------------------- ------------------- SLICE_X185Y237 FDCE (Prop_fdce_C_Q) 0.100 0.719 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[84]/Q net (fo=1, routed) 0.092 0.811 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/data4[4] SLICE_X185Y236 LUT6 (Prop_lut6_I0_O) 0.028 0.839 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[4]_i_1__2/O net (fo=1, routed) 0.000 0.839 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[4]_i_1__2_n_0 SLICE_X185Y236 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[4]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 0.826 0.826 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X185Y236 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[4]/C clock pessimism -0.195 0.631 SLICE_X185Y236 FDCE (Hold_fdce_C_D) 0.060 0.691 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[4] ------------------------------------------------------------------- required time -0.691 arrival time 0.839 ------------------------------------------------------------------- slack 0.148 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: txWordclkl12_4 Waveform(ns): { 0.000 4.100 } Period(ns): 8.200 Sources: { ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/TXUSRCLK n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y25 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK Min Period n/a GTXE2_CHANNEL/TXUSRCLK2 n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y25 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X140Y297 ngFEC/g_pm[1].phase_mon/PS_max_reg[7]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X140Y297 ngFEC/g_pm[1].phase_mon/PS_max_reg[8]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X142Y296 ngFEC/g_pm[1].phase_mon/en_chk_reg[2]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X143Y295 ngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X143Y295 ngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[2]/C Min Period n/a FDPE/C n/a 0.750 8.200 7.450 SLICE_X141Y296 ngFEC/g_pm[1].phase_mon/inh_cntr_reg[2]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X143Y295 ngFEC/g_pm[1].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X143Y295 ngFEC/g_pm[1].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[2]/C Low Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X182Y243 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK Low Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X182Y243 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X140Y297 ngFEC/g_pm[1].phase_mon/PS_max_reg[7]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X140Y297 ngFEC/g_pm[1].phase_mon/PS_max_reg[8]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X142Y296 ngFEC/g_pm[1].phase_mon/en_chk_reg[2]/C Low Pulse Width Slow FDRE/C n/a 0.400 4.100 3.700 SLICE_X143Y295 ngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/C Low Pulse Width Slow FDRE/C n/a 0.400 4.100 3.700 SLICE_X143Y295 ngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[2]/C Low Pulse Width Slow FDPE/C n/a 0.400 4.100 3.700 SLICE_X141Y296 ngFEC/g_pm[1].phase_mon/inh_cntr_reg[2]/C Low Pulse Width Slow FDRE/C n/a 0.400 4.100 3.700 SLICE_X143Y295 ngFEC/g_pm[1].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/C Low Pulse Width Slow FDRE/C n/a 0.400 4.100 3.700 SLICE_X143Y295 ngFEC/g_pm[1].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[2]/C High Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X182Y243 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK High Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X182Y243 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X183Y235 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[19]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X183Y235 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[48]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X183Y235 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[8]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X183Y235 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[9]/C High Pulse Width Fast FDCE/C n/a 0.350 4.100 3.750 SLICE_X142Y299 ngFEC/g_pm[1].phase_mon/PS_max_reg[0]/C High Pulse Width Fast FDCE/C n/a 0.350 4.100 3.750 SLICE_X140Y297 ngFEC/g_pm[1].phase_mon/PS_max_reg[1]/C High Pulse Width Fast FDCE/C n/a 0.350 4.100 3.750 SLICE_X140Y297 ngFEC/g_pm[1].phase_mon/PS_max_reg[2]/C High Pulse Width Fast FDCE/C n/a 0.350 4.100 3.750 SLICE_X142Y299 ngFEC/g_pm[1].phase_mon/PS_max_reg[3]/C --------------------------------------------------------------------------------------------------- From Clock: txWordclkl12_5 To Clock: txWordclkl12_5 Setup : 0 Failing Endpoints, Worst Slack 4.766ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.108ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.458ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.766ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[13]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[11] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_5 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_5 rise@8.200ns - txWordclkl12_5 rise@0.000ns) Data Path Delay: 3.284ns (logic 0.223ns (6.790%) route 3.061ns (93.210%)) Logic Levels: 0 Clock Path Skew: 0.304ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.657ns = ( 9.857 - 8.200 ) Source Clock Delay (SCD): 1.366ns Clock Pessimism Removal (CPR): 0.013ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 0.000 0.000 r BUFGCTRL_X0Y20 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.366 1.366 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X184Y211 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X184Y211 FDCE (Prop_fdce_C_Q) 0.223 1.589 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[13]/Q net (fo=1, routed) 3.061 4.650 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[13] GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[11] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 8.200 8.200 r BUFGCTRL_X0Y20 BUFG 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.657 9.857 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.013 9.870 clock uncertainty -0.035 9.835 GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[11]) -0.419 9.416 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.416 arrival time -4.650 ------------------------------------------------------------------- slack 4.766 Slack (MET) : 4.779ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[8]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPVAL[0] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_5 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_5 rise@8.200ns - txWordclkl12_5 rise@0.000ns) Data Path Delay: 3.271ns (logic 0.259ns (7.919%) route 3.012ns (92.081%)) Logic Levels: 0 Clock Path Skew: 0.304ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.657ns = ( 9.857 - 8.200 ) Source Clock Delay (SCD): 1.366ns Clock Pessimism Removal (CPR): 0.013ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 0.000 0.000 r BUFGCTRL_X0Y20 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.366 1.366 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X182Y210 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X182Y210 FDCE (Prop_fdce_C_Q) 0.259 1.625 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[8]/Q net (fo=1, routed) 3.012 4.637 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[8] GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPVAL[0] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 8.200 8.200 r BUFGCTRL_X0Y20 BUFG 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.657 9.857 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.013 9.870 clock uncertainty -0.035 9.835 GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXCHARDISPVAL[0]) -0.419 9.416 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.416 arrival time -4.637 ------------------------------------------------------------------- slack 4.779 Slack (MET) : 4.842ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[7] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_5 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_5 rise@8.200ns - txWordclkl12_5 rise@0.000ns) Data Path Delay: 3.208ns (logic 0.259ns (8.074%) route 2.949ns (91.926%)) Logic Levels: 0 Clock Path Skew: 0.304ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.657ns = ( 9.857 - 8.200 ) Source Clock Delay (SCD): 1.366ns Clock Pessimism Removal (CPR): 0.013ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 0.000 0.000 r BUFGCTRL_X0Y20 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.366 1.366 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X186Y212 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X186Y212 FDCE (Prop_fdce_C_Q) 0.259 1.625 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/Q net (fo=1, routed) 2.949 4.574 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[7] GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[7] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 8.200 8.200 r BUFGCTRL_X0Y20 BUFG 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.657 9.857 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.013 9.870 clock uncertainty -0.035 9.835 GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[7]) -0.419 9.416 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.416 arrival time -4.574 ------------------------------------------------------------------- slack 4.842 Slack (MET) : 4.848ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[6] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_5 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_5 rise@8.200ns - txWordclkl12_5 rise@0.000ns) Data Path Delay: 3.202ns (logic 0.259ns (8.088%) route 2.943ns (91.912%)) Logic Levels: 0 Clock Path Skew: 0.304ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.657ns = ( 9.857 - 8.200 ) Source Clock Delay (SCD): 1.366ns Clock Pessimism Removal (CPR): 0.013ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 0.000 0.000 r BUFGCTRL_X0Y20 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.366 1.366 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X186Y212 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X186Y212 FDCE (Prop_fdce_C_Q) 0.259 1.625 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/Q net (fo=1, routed) 2.943 4.568 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[6] GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[6] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 8.200 8.200 r BUFGCTRL_X0Y20 BUFG 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.657 9.857 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.013 9.870 clock uncertainty -0.035 9.835 GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[6]) -0.419 9.416 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.416 arrival time -4.568 ------------------------------------------------------------------- slack 4.848 Slack (MET) : 4.848ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[2]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[2] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_5 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_5 rise@8.200ns - txWordclkl12_5 rise@0.000ns) Data Path Delay: 3.203ns (logic 0.259ns (8.087%) route 2.944ns (91.913%)) Logic Levels: 0 Clock Path Skew: 0.305ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.657ns = ( 9.857 - 8.200 ) Source Clock Delay (SCD): 1.365ns Clock Pessimism Removal (CPR): 0.013ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 0.000 0.000 r BUFGCTRL_X0Y20 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.365 1.365 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X182Y212 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X182Y212 FDCE (Prop_fdce_C_Q) 0.259 1.624 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[2]/Q net (fo=1, routed) 2.944 4.568 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[2] GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[2] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 8.200 8.200 r BUFGCTRL_X0Y20 BUFG 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.657 9.857 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.013 9.870 clock uncertainty -0.035 9.835 GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[2]) -0.419 9.416 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.416 arrival time -4.568 ------------------------------------------------------------------- slack 4.848 Slack (MET) : 4.849ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[1] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_5 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_5 rise@8.200ns - txWordclkl12_5 rise@0.000ns) Data Path Delay: 3.201ns (logic 0.223ns (6.966%) route 2.978ns (93.034%)) Logic Levels: 0 Clock Path Skew: 0.304ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.657ns = ( 9.857 - 8.200 ) Source Clock Delay (SCD): 1.366ns Clock Pessimism Removal (CPR): 0.013ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 0.000 0.000 r BUFGCTRL_X0Y20 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.366 1.366 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X188Y212 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X188Y212 FDCE (Prop_fdce_C_Q) 0.223 1.589 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/Q net (fo=1, routed) 2.978 4.567 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[1] GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[1] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 8.200 8.200 r BUFGCTRL_X0Y20 BUFG 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.657 9.857 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.013 9.870 clock uncertainty -0.035 9.835 GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[1]) -0.419 9.416 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.416 arrival time -4.567 ------------------------------------------------------------------- slack 4.849 Slack (MET) : 4.853ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[3]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[3] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_5 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_5 rise@8.200ns - txWordclkl12_5 rise@0.000ns) Data Path Delay: 3.198ns (logic 0.223ns (6.973%) route 2.975ns (93.027%)) Logic Levels: 0 Clock Path Skew: 0.305ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.657ns = ( 9.857 - 8.200 ) Source Clock Delay (SCD): 1.365ns Clock Pessimism Removal (CPR): 0.013ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 0.000 0.000 r BUFGCTRL_X0Y20 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.365 1.365 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X183Y212 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X183Y212 FDCE (Prop_fdce_C_Q) 0.223 1.588 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[3]/Q net (fo=1, routed) 2.975 4.563 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[3] GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[3] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 8.200 8.200 r BUFGCTRL_X0Y20 BUFG 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.657 9.857 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.013 9.870 clock uncertainty -0.035 9.835 GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[3]) -0.419 9.416 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.416 arrival time -4.563 ------------------------------------------------------------------- slack 4.853 Slack (MET) : 4.910ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[4]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[4] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_5 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_5 rise@8.200ns - txWordclkl12_5 rise@0.000ns) Data Path Delay: 3.140ns (logic 0.259ns (8.247%) route 2.881ns (91.753%)) Logic Levels: 0 Clock Path Skew: 0.304ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.657ns = ( 9.857 - 8.200 ) Source Clock Delay (SCD): 1.366ns Clock Pessimism Removal (CPR): 0.013ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 0.000 0.000 r BUFGCTRL_X0Y20 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.366 1.366 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X182Y210 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X182Y210 FDCE (Prop_fdce_C_Q) 0.259 1.625 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[4]/Q net (fo=1, routed) 2.881 4.506 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[4] GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[4] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 8.200 8.200 r BUFGCTRL_X0Y20 BUFG 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.657 9.857 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.013 9.870 clock uncertainty -0.035 9.835 GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[4]) -0.419 9.416 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.416 arrival time -4.506 ------------------------------------------------------------------- slack 4.910 Slack (MET) : 5.016ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[19]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPMODE[1] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_5 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_5 rise@8.200ns - txWordclkl12_5 rise@0.000ns) Data Path Delay: 3.034ns (logic 0.223ns (7.349%) route 2.811ns (92.651%)) Logic Levels: 0 Clock Path Skew: 0.304ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.657ns = ( 9.857 - 8.200 ) Source Clock Delay (SCD): 1.366ns Clock Pessimism Removal (CPR): 0.013ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 0.000 0.000 r BUFGCTRL_X0Y20 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.366 1.366 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X184Y211 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X184Y211 FDCE (Prop_fdce_C_Q) 0.223 1.589 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[19]/Q net (fo=1, routed) 2.811 4.400 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[19] GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPMODE[1] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 8.200 8.200 r BUFGCTRL_X0Y20 BUFG 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.657 9.857 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.013 9.870 clock uncertainty -0.035 9.835 GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXCHARDISPMODE[1]) -0.419 9.416 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.416 arrival time -4.400 ------------------------------------------------------------------- slack 5.016 Slack (MET) : 5.057ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[16]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[14] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_5 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_5 rise@8.200ns - txWordclkl12_5 rise@0.000ns) Data Path Delay: 2.993ns (logic 0.223ns (7.450%) route 2.770ns (92.550%)) Logic Levels: 0 Clock Path Skew: 0.304ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.657ns = ( 9.857 - 8.200 ) Source Clock Delay (SCD): 1.366ns Clock Pessimism Removal (CPR): 0.013ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 0.000 0.000 r BUFGCTRL_X0Y20 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.366 1.366 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X187Y212 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X187Y212 FDCE (Prop_fdce_C_Q) 0.223 1.589 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[16]/Q net (fo=1, routed) 2.770 4.359 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[16] GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[14] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 8.200 8.200 r BUFGCTRL_X0Y20 BUFG 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.657 9.857 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.013 9.870 clock uncertainty -0.035 9.835 GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[14]) -0.419 9.416 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.416 arrival time -4.359 ------------------------------------------------------------------- slack 5.057 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/g_pm[9].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[9].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D (rising edge-triggered cell FDRE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_5 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_5 rise@0.000ns - txWordclkl12_5 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.985ns Source Clock Delay (SCD): 0.738ns Clock Pessimism Removal (CPR): 0.247ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 0.000 0.000 r BUFGCTRL_X0Y20 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.738 0.738 ngFEC/g_pm[9].phase_mon/fabric_clk_PS_toggle_Sync_inst/dest_clk SLICE_X143Y313 FDRE r ngFEC/g_pm[9].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X143Y313 FDRE (Prop_fdre_C_Q) 0.100 0.838 r ngFEC/g_pm[9].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/Q net (fo=1, routed) 0.055 0.893 ngFEC/g_pm[9].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff[0] SLICE_X143Y313 FDRE r ngFEC/g_pm[9].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 0.000 0.000 r BUFGCTRL_X0Y20 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.985 0.985 ngFEC/g_pm[9].phase_mon/fabric_clk_PS_toggle_Sync_inst/dest_clk SLICE_X143Y313 FDRE r ngFEC/g_pm[9].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/C clock pessimism -0.247 0.738 SLICE_X143Y313 FDRE (Hold_fdre_C_D) 0.047 0.785 ngFEC/g_pm[9].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1] ------------------------------------------------------------------- required time -0.785 arrival time 0.893 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_5 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_5 rise@0.000ns - txWordclkl12_5 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.022ns Source Clock Delay (SCD): 0.775ns Clock Pessimism Removal (CPR): 0.247ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 0.000 0.000 r BUFGCTRL_X0Y20 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.775 0.775 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in SLICE_X173Y313 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X173Y313 FDRE (Prop_fdre_C_Q) 0.100 0.875 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/Q net (fo=1, routed) 0.055 0.930 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync1 SLICE_X173Y313 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 0.000 0.000 r BUFGCTRL_X0Y20 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.022 1.022 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in SLICE_X173Y313 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/C clock pessimism -0.247 0.775 SLICE_X173Y313 FDRE (Hold_fdre_C_D) 0.047 0.822 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.822 arrival time 0.930 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.113ns (arrival time - required time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[95]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[15]/D (rising edge-triggered cell FDCE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_5 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_5 rise@0.000ns - txWordclkl12_5 rise@0.000ns) Data Path Delay: 0.236ns (logic 0.128ns (54.265%) route 0.108ns (45.735%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.827ns Source Clock Delay (SCD): 0.618ns Clock Pessimism Removal (CPR): 0.173ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 0.000 0.000 r BUFGCTRL_X0Y20 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.618 0.618 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X184Y213 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[95]/C ------------------------------------------------------------------- ------------------- SLICE_X184Y213 FDCE (Prop_fdce_C_Q) 0.100 0.718 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[95]/Q net (fo=1, routed) 0.108 0.826 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/data4[15] SLICE_X182Y212 LUT6 (Prop_lut6_I0_O) 0.028 0.854 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[15]_i_1__3/O net (fo=1, routed) 0.000 0.854 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[15]_i_1__3_n_0 SLICE_X182Y212 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[15]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 0.000 0.000 r BUFGCTRL_X0Y20 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.827 0.827 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X182Y212 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[15]/C clock pessimism -0.173 0.654 SLICE_X182Y212 FDCE (Hold_fdce_C_D) 0.087 0.741 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[15] ------------------------------------------------------------------- required time -0.741 arrival time 0.854 ------------------------------------------------------------------- slack 0.113 Slack (MET) : 0.113ns (arrival time - required time) Source: ngFEC/g_pm[9].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[9].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/D (rising edge-triggered cell FDRE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_5 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_5 rise@0.000ns - txWordclkl12_5 rise@0.000ns) Data Path Delay: 0.160ns (logic 0.100ns (62.442%) route 0.060ns (37.558%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.953ns Source Clock Delay (SCD): 0.707ns Clock Pessimism Removal (CPR): 0.246ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 0.000 0.000 r BUFGCTRL_X0Y20 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.707 0.707 ngFEC/g_pm[9].phase_mon/sample_PS_Sync_inst/dest_clk SLICE_X124Y306 FDRE r ngFEC/g_pm[9].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X124Y306 FDRE (Prop_fdre_C_Q) 0.100 0.807 r ngFEC/g_pm[9].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/Q net (fo=1, routed) 0.060 0.867 ngFEC/g_pm[9].phase_mon/sample_PS_Sync_inst/syncstages_ff[0] SLICE_X124Y306 FDRE r ngFEC/g_pm[9].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 0.000 0.000 r BUFGCTRL_X0Y20 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.953 0.953 ngFEC/g_pm[9].phase_mon/sample_PS_Sync_inst/dest_clk SLICE_X124Y306 FDRE r ngFEC/g_pm[9].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/C clock pessimism -0.246 0.707 SLICE_X124Y306 FDRE (Hold_fdre_C_D) 0.047 0.754 ngFEC/g_pm[9].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1] ------------------------------------------------------------------- required time -0.754 arrival time 0.867 ------------------------------------------------------------------- slack 0.113 Slack (MET) : 0.113ns (arrival time - required time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D (rising edge-triggered cell FDRE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_5 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_5 rise@0.000ns - txWordclkl12_5 rise@0.000ns) Data Path Delay: 0.160ns (logic 0.100ns (62.442%) route 0.060ns (37.558%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.829ns Source Clock Delay (SCD): 0.620ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 0.000 0.000 r BUFGCTRL_X0Y20 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.620 0.620 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk SLICE_X184Y210 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X184Y210 FDRE (Prop_fdre_C_Q) 0.100 0.720 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/Q net (fo=1, routed) 0.060 0.780 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff[0] SLICE_X184Y210 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 0.000 0.000 r BUFGCTRL_X0Y20 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.829 0.829 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk SLICE_X184Y210 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/C clock pessimism -0.209 0.620 SLICE_X184Y210 FDRE (Hold_fdre_C_D) 0.047 0.667 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1] ------------------------------------------------------------------- required time -0.667 arrival time 0.780 ------------------------------------------------------------------- slack 0.113 Slack (MET) : 0.121ns (arrival time - required time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[87]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/D (rising edge-triggered cell FDCE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_5 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_5 rise@0.000ns - txWordclkl12_5 rise@0.000ns) Data Path Delay: 0.221ns (logic 0.128ns (58.001%) route 0.093ns (41.999%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.827ns Source Clock Delay (SCD): 0.619ns Clock Pessimism Removal (CPR): 0.195ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 0.000 0.000 r BUFGCTRL_X0Y20 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.619 0.619 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X185Y212 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[87]/C ------------------------------------------------------------------- ------------------- SLICE_X185Y212 FDCE (Prop_fdce_C_Q) 0.100 0.719 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[87]/Q net (fo=1, routed) 0.093 0.812 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/data4[7] SLICE_X186Y212 LUT6 (Prop_lut6_I0_O) 0.028 0.840 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[7]_i_1__3/O net (fo=1, routed) 0.000 0.840 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[7]_i_1__3_n_0 SLICE_X186Y212 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 0.000 0.000 r BUFGCTRL_X0Y20 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.827 0.827 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X186Y212 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/C clock pessimism -0.195 0.632 SLICE_X186Y212 FDCE (Hold_fdce_C_D) 0.087 0.719 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7] ------------------------------------------------------------------- required time -0.719 arrival time 0.840 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.121ns (arrival time - required time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/C (rising edge-triggered cell FDRE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/D (rising edge-triggered cell SRL16E clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_5 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_5 rise@0.000ns - txWordclkl12_5 rise@0.000ns) Data Path Delay: 0.237ns (logic 0.100ns (42.163%) route 0.137ns (57.837%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.829ns Source Clock Delay (SCD): 0.620ns Clock Pessimism Removal (CPR): 0.195ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 0.000 0.000 r BUFGCTRL_X0Y20 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.620 0.620 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk SLICE_X184Y210 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X184Y210 FDRE (Prop_fdre_C_Q) 0.100 0.720 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/Q net (fo=1, routed) 0.137 0.857 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/dest_out SLICE_X186Y211 SRL16E r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 0.000 0.000 r BUFGCTRL_X0Y20 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.829 0.829 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X186Y211 SRL16E r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK clock pessimism -0.195 0.634 SLICE_X186Y211 SRL16E (Hold_srl16e_CLK_D) 0.102 0.736 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3 ------------------------------------------------------------------- required time -0.736 arrival time 0.857 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.131ns (arrival time - required time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_5 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_5 rise@0.000ns - txWordclkl12_5 rise@0.000ns) Data Path Delay: 0.173ns (logic 0.118ns (68.255%) route 0.055ns (31.745%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.029ns Source Clock Delay (SCD): 0.780ns Clock Pessimism Removal (CPR): 0.249ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 0.000 0.000 r BUFGCTRL_X0Y20 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.780 0.780 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in SLICE_X180Y311 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X180Y311 FDRE (Prop_fdre_C_Q) 0.118 0.898 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q net (fo=1, routed) 0.055 0.953 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync1 SLICE_X180Y311 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 0.000 0.000 r BUFGCTRL_X0Y20 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.029 1.029 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in SLICE_X180Y311 FDRE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C clock pessimism -0.249 0.780 SLICE_X180Y311 FDRE (Hold_fdre_C_D) 0.042 0.822 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.822 arrival time 0.953 ------------------------------------------------------------------- slack 0.131 Slack (MET) : 0.149ns (arrival time - required time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[118]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/D (rising edge-triggered cell FDCE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_5 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_5 rise@0.000ns - txWordclkl12_5 rise@0.000ns) Data Path Delay: 0.250ns (logic 0.128ns (51.134%) route 0.122ns (48.866%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.827ns Source Clock Delay (SCD): 0.618ns Clock Pessimism Removal (CPR): 0.195ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 0.000 0.000 r BUFGCTRL_X0Y20 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.618 0.618 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X185Y213 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[118]/C ------------------------------------------------------------------- ------------------- SLICE_X185Y213 FDCE (Prop_fdce_C_Q) 0.100 0.718 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[118]/Q net (fo=1, routed) 0.122 0.840 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/data5[18] SLICE_X186Y212 LUT6 (Prop_lut6_I2_O) 0.028 0.868 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[18]_i_1__3/O net (fo=1, routed) 0.000 0.868 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[18]_i_1__3_n_0 SLICE_X186Y212 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 0.000 0.000 r BUFGCTRL_X0Y20 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.827 0.827 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X186Y212 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/C clock pessimism -0.195 0.632 SLICE_X186Y212 FDCE (Hold_fdce_C_D) 0.087 0.719 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18] ------------------------------------------------------------------- required time -0.719 arrival time 0.868 ------------------------------------------------------------------- slack 0.149 Slack (MET) : 0.153ns (arrival time - required time) Source: ngFEC/g_pm[9].phase_mon/old_fabric_clk_PS_toggle_reg/C (rising edge-triggered cell FDCE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[9].phase_mon/inh_cntr_reg[3]/D (rising edge-triggered cell FDPE clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_5 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_5 rise@0.000ns - txWordclkl12_5 rise@0.000ns) Data Path Delay: 0.255ns (logic 0.146ns (57.276%) route 0.109ns (42.724%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.991ns Source Clock Delay (SCD): 0.743ns Clock Pessimism Removal (CPR): 0.233ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 0.000 0.000 r BUFGCTRL_X0Y20 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.743 0.743 ngFEC/g_pm[9].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X144Y310 FDCE r ngFEC/g_pm[9].phase_mon/old_fabric_clk_PS_toggle_reg/C ------------------------------------------------------------------- ------------------- SLICE_X144Y310 FDCE (Prop_fdce_C_Q) 0.118 0.861 r ngFEC/g_pm[9].phase_mon/old_fabric_clk_PS_toggle_reg/Q net (fo=9, routed) 0.109 0.970 ngFEC/g_pm[9].phase_mon/old_fabric_clk_PS_toggle_reg_n_0 SLICE_X144Y309 LUT6 (Prop_lut6_I0_O) 0.028 0.998 r ngFEC/g_pm[9].phase_mon/inh_cntr[3]_i_1__7/O net (fo=1, routed) 0.000 0.998 ngFEC/g_pm[9].phase_mon/p_0_in__0[3] SLICE_X144Y309 FDPE r ngFEC/g_pm[9].phase_mon/inh_cntr_reg[3]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 0.000 0.000 r BUFGCTRL_X0Y20 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.991 0.991 ngFEC/g_pm[9].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X144Y309 FDPE r ngFEC/g_pm[9].phase_mon/inh_cntr_reg[3]/C clock pessimism -0.233 0.758 SLICE_X144Y309 FDPE (Hold_fdpe_C_D) 0.087 0.845 ngFEC/g_pm[9].phase_mon/inh_cntr_reg[3] ------------------------------------------------------------------- required time -0.845 arrival time 0.998 ------------------------------------------------------------------- slack 0.153 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: txWordclkl12_5 Waveform(ns): { 0.000 4.100 } Period(ns): 8.200 Sources: { ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/TXUSRCLK n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y24 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK Min Period n/a GTXE2_CHANNEL/TXUSRCLK2 n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y24 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X125Y306 ngFEC/g_pm[9].phase_mon/en_chk_reg[2]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X143Y313 ngFEC/g_pm[9].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X143Y313 ngFEC/g_pm[9].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[2]/C Min Period n/a FDPE/C n/a 0.750 8.200 7.450 SLICE_X144Y309 ngFEC/g_pm[9].phase_mon/inh_cntr_reg[2]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X124Y306 ngFEC/g_pm[9].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X124Y306 ngFEC/g_pm[9].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[2]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X186Y211 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X187Y212 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[1]/C Low Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X186Y211 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK Low Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X186Y211 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK Low Pulse Width Slow FDPE/C n/a 0.400 4.100 3.700 SLICE_X144Y309 ngFEC/g_pm[9].phase_mon/inh_cntr_reg[2]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X187Y212 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[1]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X184Y212 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.ready_reg/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X183Y210 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[59]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X186Y210 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[66]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X186Y210 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[67]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X185Y210 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[6]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X185Y210 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[70]/C High Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X186Y211 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK High Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X186Y211 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK High Pulse Width Fast FDCE/C n/a 0.350 4.100 3.750 SLICE_X153Y312 ngFEC/g_pm[9].phase_mon/PS_max_reg[8]/C High Pulse Width Fast FDCE/C n/a 0.350 4.100 3.750 SLICE_X153Y312 ngFEC/g_pm[9].phase_mon/PS_max_reg[9]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X143Y313 ngFEC/g_pm[9].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X143Y313 ngFEC/g_pm[9].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X143Y313 ngFEC/g_pm[9].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[2]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X143Y313 ngFEC/g_pm[9].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[3]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X183Y214 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[108]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X183Y214 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[117]/C --------------------------------------------------------------------------------------------------- From Clock: txWordclkl12_6 To Clock: txWordclkl12_6 Setup : 0 Failing Endpoints, Worst Slack 4.551ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.108ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.458ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.551ns (required time - arrival time) Source: ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[10].phase_mon/PS_max_reg[0]/CE (rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_6 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_6 rise@8.200ns - txWordclkl12_6 rise@0.000ns) Data Path Delay: 3.386ns (logic 0.707ns (20.881%) route 2.679ns (79.119%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: -0.050ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.303ns = ( 9.503 - 8.200 ) Source Clock Delay (SCD): 1.476ns Clock Pessimism Removal (CPR): 0.123ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 0.000 0.000 r BUFGCTRL_X0Y21 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.476 1.476 ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X157Y299 FDCE r ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X157Y299 FDCE (Prop_fdce_C_Q) 0.223 1.699 r ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/Q net (fo=3, routed) 1.043 2.742 ngFEC/g_pm[10].phase_mon/PS_max_reg_n_0_[6] SLICE_X154Y308 LUT4 (Prop_lut4_I2_O) 0.043 2.785 r ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8/O net (fo=1, routed) 0.000 2.785 ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8_n_0 SLICE_X154Y308 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.180 2.965 r ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2/CO[3] net (fo=1, routed) 0.000 2.965 ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2_n_0 SLICE_X154Y309 CARRY4 (Prop_carry4_CI_CO[0]) 0.133 3.098 r ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_3__2/CO[0] net (fo=1, routed) 0.824 3.922 ngFEC/g_pm[10].phase_mon/gtOp SLICE_X147Y300 LUT5 (Prop_lut5_I2_O) 0.128 4.050 r ngFEC/g_pm[10].phase_mon/PS_max[9]_i_1__8/O net (fo=10, routed) 0.811 4.862 ngFEC/g_pm[10].phase_mon/PS_max SLICE_X154Y298 FDCE r ngFEC/g_pm[10].phase_mon/PS_max_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 8.200 8.200 r BUFGCTRL_X0Y21 BUFG 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.303 9.503 ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X154Y298 FDCE r ngFEC/g_pm[10].phase_mon/PS_max_reg[0]/C clock pessimism 0.123 9.626 clock uncertainty -0.035 9.591 SLICE_X154Y298 FDCE (Setup_fdce_C_CE) -0.178 9.413 ngFEC/g_pm[10].phase_mon/PS_max_reg[0] ------------------------------------------------------------------- required time 9.413 arrival time -4.862 ------------------------------------------------------------------- slack 4.551 Slack (MET) : 4.551ns (required time - arrival time) Source: ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[10].phase_mon/PS_max_reg[1]/CE (rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_6 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_6 rise@8.200ns - txWordclkl12_6 rise@0.000ns) Data Path Delay: 3.386ns (logic 0.707ns (20.881%) route 2.679ns (79.119%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: -0.050ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.303ns = ( 9.503 - 8.200 ) Source Clock Delay (SCD): 1.476ns Clock Pessimism Removal (CPR): 0.123ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 0.000 0.000 r BUFGCTRL_X0Y21 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.476 1.476 ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X157Y299 FDCE r ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X157Y299 FDCE (Prop_fdce_C_Q) 0.223 1.699 r ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/Q net (fo=3, routed) 1.043 2.742 ngFEC/g_pm[10].phase_mon/PS_max_reg_n_0_[6] SLICE_X154Y308 LUT4 (Prop_lut4_I2_O) 0.043 2.785 r ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8/O net (fo=1, routed) 0.000 2.785 ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8_n_0 SLICE_X154Y308 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.180 2.965 r ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2/CO[3] net (fo=1, routed) 0.000 2.965 ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2_n_0 SLICE_X154Y309 CARRY4 (Prop_carry4_CI_CO[0]) 0.133 3.098 r ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_3__2/CO[0] net (fo=1, routed) 0.824 3.922 ngFEC/g_pm[10].phase_mon/gtOp SLICE_X147Y300 LUT5 (Prop_lut5_I2_O) 0.128 4.050 r ngFEC/g_pm[10].phase_mon/PS_max[9]_i_1__8/O net (fo=10, routed) 0.811 4.862 ngFEC/g_pm[10].phase_mon/PS_max SLICE_X154Y298 FDCE r ngFEC/g_pm[10].phase_mon/PS_max_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 8.200 8.200 r BUFGCTRL_X0Y21 BUFG 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.303 9.503 ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X154Y298 FDCE r ngFEC/g_pm[10].phase_mon/PS_max_reg[1]/C clock pessimism 0.123 9.626 clock uncertainty -0.035 9.591 SLICE_X154Y298 FDCE (Setup_fdce_C_CE) -0.178 9.413 ngFEC/g_pm[10].phase_mon/PS_max_reg[1] ------------------------------------------------------------------- required time 9.413 arrival time -4.862 ------------------------------------------------------------------- slack 4.551 Slack (MET) : 4.551ns (required time - arrival time) Source: ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[10].phase_mon/PS_max_reg[5]/CE (rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_6 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_6 rise@8.200ns - txWordclkl12_6 rise@0.000ns) Data Path Delay: 3.386ns (logic 0.707ns (20.881%) route 2.679ns (79.119%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: -0.050ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.303ns = ( 9.503 - 8.200 ) Source Clock Delay (SCD): 1.476ns Clock Pessimism Removal (CPR): 0.123ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 0.000 0.000 r BUFGCTRL_X0Y21 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.476 1.476 ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X157Y299 FDCE r ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X157Y299 FDCE (Prop_fdce_C_Q) 0.223 1.699 r ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/Q net (fo=3, routed) 1.043 2.742 ngFEC/g_pm[10].phase_mon/PS_max_reg_n_0_[6] SLICE_X154Y308 LUT4 (Prop_lut4_I2_O) 0.043 2.785 r ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8/O net (fo=1, routed) 0.000 2.785 ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8_n_0 SLICE_X154Y308 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.180 2.965 r ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2/CO[3] net (fo=1, routed) 0.000 2.965 ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2_n_0 SLICE_X154Y309 CARRY4 (Prop_carry4_CI_CO[0]) 0.133 3.098 r ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_3__2/CO[0] net (fo=1, routed) 0.824 3.922 ngFEC/g_pm[10].phase_mon/gtOp SLICE_X147Y300 LUT5 (Prop_lut5_I2_O) 0.128 4.050 r ngFEC/g_pm[10].phase_mon/PS_max[9]_i_1__8/O net (fo=10, routed) 0.811 4.862 ngFEC/g_pm[10].phase_mon/PS_max SLICE_X154Y298 FDCE r ngFEC/g_pm[10].phase_mon/PS_max_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 8.200 8.200 r BUFGCTRL_X0Y21 BUFG 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.303 9.503 ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X154Y298 FDCE r ngFEC/g_pm[10].phase_mon/PS_max_reg[5]/C clock pessimism 0.123 9.626 clock uncertainty -0.035 9.591 SLICE_X154Y298 FDCE (Setup_fdce_C_CE) -0.178 9.413 ngFEC/g_pm[10].phase_mon/PS_max_reg[5] ------------------------------------------------------------------- required time 9.413 arrival time -4.862 ------------------------------------------------------------------- slack 4.551 Slack (MET) : 4.551ns (required time - arrival time) Source: ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[10].phase_mon/PS_max_reg[7]/CE (rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_6 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_6 rise@8.200ns - txWordclkl12_6 rise@0.000ns) Data Path Delay: 3.386ns (logic 0.707ns (20.881%) route 2.679ns (79.119%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: -0.050ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.303ns = ( 9.503 - 8.200 ) Source Clock Delay (SCD): 1.476ns Clock Pessimism Removal (CPR): 0.123ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 0.000 0.000 r BUFGCTRL_X0Y21 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.476 1.476 ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X157Y299 FDCE r ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X157Y299 FDCE (Prop_fdce_C_Q) 0.223 1.699 r ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/Q net (fo=3, routed) 1.043 2.742 ngFEC/g_pm[10].phase_mon/PS_max_reg_n_0_[6] SLICE_X154Y308 LUT4 (Prop_lut4_I2_O) 0.043 2.785 r ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8/O net (fo=1, routed) 0.000 2.785 ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8_n_0 SLICE_X154Y308 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.180 2.965 r ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2/CO[3] net (fo=1, routed) 0.000 2.965 ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2_n_0 SLICE_X154Y309 CARRY4 (Prop_carry4_CI_CO[0]) 0.133 3.098 r ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_3__2/CO[0] net (fo=1, routed) 0.824 3.922 ngFEC/g_pm[10].phase_mon/gtOp SLICE_X147Y300 LUT5 (Prop_lut5_I2_O) 0.128 4.050 r ngFEC/g_pm[10].phase_mon/PS_max[9]_i_1__8/O net (fo=10, routed) 0.811 4.862 ngFEC/g_pm[10].phase_mon/PS_max SLICE_X154Y298 FDCE r ngFEC/g_pm[10].phase_mon/PS_max_reg[7]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 8.200 8.200 r BUFGCTRL_X0Y21 BUFG 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.303 9.503 ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X154Y298 FDCE r ngFEC/g_pm[10].phase_mon/PS_max_reg[7]/C clock pessimism 0.123 9.626 clock uncertainty -0.035 9.591 SLICE_X154Y298 FDCE (Setup_fdce_C_CE) -0.178 9.413 ngFEC/g_pm[10].phase_mon/PS_max_reg[7] ------------------------------------------------------------------- required time 9.413 arrival time -4.862 ------------------------------------------------------------------- slack 4.551 Slack (MET) : 4.551ns (required time - arrival time) Source: ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[10].phase_mon/PS_max_reg[8]/CE (rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_6 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_6 rise@8.200ns - txWordclkl12_6 rise@0.000ns) Data Path Delay: 3.386ns (logic 0.707ns (20.881%) route 2.679ns (79.119%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: -0.050ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.303ns = ( 9.503 - 8.200 ) Source Clock Delay (SCD): 1.476ns Clock Pessimism Removal (CPR): 0.123ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 0.000 0.000 r BUFGCTRL_X0Y21 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.476 1.476 ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X157Y299 FDCE r ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X157Y299 FDCE (Prop_fdce_C_Q) 0.223 1.699 r ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/Q net (fo=3, routed) 1.043 2.742 ngFEC/g_pm[10].phase_mon/PS_max_reg_n_0_[6] SLICE_X154Y308 LUT4 (Prop_lut4_I2_O) 0.043 2.785 r ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8/O net (fo=1, routed) 0.000 2.785 ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8_n_0 SLICE_X154Y308 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.180 2.965 r ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2/CO[3] net (fo=1, routed) 0.000 2.965 ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2_n_0 SLICE_X154Y309 CARRY4 (Prop_carry4_CI_CO[0]) 0.133 3.098 r ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_3__2/CO[0] net (fo=1, routed) 0.824 3.922 ngFEC/g_pm[10].phase_mon/gtOp SLICE_X147Y300 LUT5 (Prop_lut5_I2_O) 0.128 4.050 r ngFEC/g_pm[10].phase_mon/PS_max[9]_i_1__8/O net (fo=10, routed) 0.811 4.862 ngFEC/g_pm[10].phase_mon/PS_max SLICE_X154Y298 FDCE r ngFEC/g_pm[10].phase_mon/PS_max_reg[8]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 8.200 8.200 r BUFGCTRL_X0Y21 BUFG 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.303 9.503 ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X154Y298 FDCE r ngFEC/g_pm[10].phase_mon/PS_max_reg[8]/C clock pessimism 0.123 9.626 clock uncertainty -0.035 9.591 SLICE_X154Y298 FDCE (Setup_fdce_C_CE) -0.178 9.413 ngFEC/g_pm[10].phase_mon/PS_max_reg[8] ------------------------------------------------------------------- required time 9.413 arrival time -4.862 ------------------------------------------------------------------- slack 4.551 Slack (MET) : 4.551ns (required time - arrival time) Source: ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[10].phase_mon/PS_max_reg[9]/CE (rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_6 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_6 rise@8.200ns - txWordclkl12_6 rise@0.000ns) Data Path Delay: 3.386ns (logic 0.707ns (20.881%) route 2.679ns (79.119%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: -0.050ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.303ns = ( 9.503 - 8.200 ) Source Clock Delay (SCD): 1.476ns Clock Pessimism Removal (CPR): 0.123ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 0.000 0.000 r BUFGCTRL_X0Y21 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.476 1.476 ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X157Y299 FDCE r ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X157Y299 FDCE (Prop_fdce_C_Q) 0.223 1.699 r ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/Q net (fo=3, routed) 1.043 2.742 ngFEC/g_pm[10].phase_mon/PS_max_reg_n_0_[6] SLICE_X154Y308 LUT4 (Prop_lut4_I2_O) 0.043 2.785 r ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8/O net (fo=1, routed) 0.000 2.785 ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8_n_0 SLICE_X154Y308 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.180 2.965 r ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2/CO[3] net (fo=1, routed) 0.000 2.965 ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2_n_0 SLICE_X154Y309 CARRY4 (Prop_carry4_CI_CO[0]) 0.133 3.098 r ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_3__2/CO[0] net (fo=1, routed) 0.824 3.922 ngFEC/g_pm[10].phase_mon/gtOp SLICE_X147Y300 LUT5 (Prop_lut5_I2_O) 0.128 4.050 r ngFEC/g_pm[10].phase_mon/PS_max[9]_i_1__8/O net (fo=10, routed) 0.811 4.862 ngFEC/g_pm[10].phase_mon/PS_max SLICE_X154Y298 FDCE r ngFEC/g_pm[10].phase_mon/PS_max_reg[9]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 8.200 8.200 r BUFGCTRL_X0Y21 BUFG 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.303 9.503 ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X154Y298 FDCE r ngFEC/g_pm[10].phase_mon/PS_max_reg[9]/C clock pessimism 0.123 9.626 clock uncertainty -0.035 9.591 SLICE_X154Y298 FDCE (Setup_fdce_C_CE) -0.178 9.413 ngFEC/g_pm[10].phase_mon/PS_max_reg[9] ------------------------------------------------------------------- required time 9.413 arrival time -4.862 ------------------------------------------------------------------- slack 4.551 Slack (MET) : 4.598ns (required time - arrival time) Source: ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[10].phase_mon/PS_max_reg[2]/CE (rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_6 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_6 rise@8.200ns - txWordclkl12_6 rise@0.000ns) Data Path Delay: 3.365ns (logic 0.707ns (21.009%) route 2.658ns (78.991%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.304ns = ( 9.504 - 8.200 ) Source Clock Delay (SCD): 1.476ns Clock Pessimism Removal (CPR): 0.172ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 0.000 0.000 r BUFGCTRL_X0Y21 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.476 1.476 ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X157Y299 FDCE r ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X157Y299 FDCE (Prop_fdce_C_Q) 0.223 1.699 r ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/Q net (fo=3, routed) 1.043 2.742 ngFEC/g_pm[10].phase_mon/PS_max_reg_n_0_[6] SLICE_X154Y308 LUT4 (Prop_lut4_I2_O) 0.043 2.785 r ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8/O net (fo=1, routed) 0.000 2.785 ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8_n_0 SLICE_X154Y308 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.180 2.965 r ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2/CO[3] net (fo=1, routed) 0.000 2.965 ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2_n_0 SLICE_X154Y309 CARRY4 (Prop_carry4_CI_CO[0]) 0.133 3.098 r ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_3__2/CO[0] net (fo=1, routed) 0.824 3.922 ngFEC/g_pm[10].phase_mon/gtOp SLICE_X147Y300 LUT5 (Prop_lut5_I2_O) 0.128 4.050 r ngFEC/g_pm[10].phase_mon/PS_max[9]_i_1__8/O net (fo=10, routed) 0.791 4.841 ngFEC/g_pm[10].phase_mon/PS_max SLICE_X157Y299 FDCE r ngFEC/g_pm[10].phase_mon/PS_max_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 8.200 8.200 r BUFGCTRL_X0Y21 BUFG 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.304 9.504 ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X157Y299 FDCE r ngFEC/g_pm[10].phase_mon/PS_max_reg[2]/C clock pessimism 0.172 9.676 clock uncertainty -0.035 9.641 SLICE_X157Y299 FDCE (Setup_fdce_C_CE) -0.201 9.440 ngFEC/g_pm[10].phase_mon/PS_max_reg[2] ------------------------------------------------------------------- required time 9.440 arrival time -4.841 ------------------------------------------------------------------- slack 4.598 Slack (MET) : 4.598ns (required time - arrival time) Source: ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[10].phase_mon/PS_max_reg[4]/CE (rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_6 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_6 rise@8.200ns - txWordclkl12_6 rise@0.000ns) Data Path Delay: 3.365ns (logic 0.707ns (21.009%) route 2.658ns (78.991%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.304ns = ( 9.504 - 8.200 ) Source Clock Delay (SCD): 1.476ns Clock Pessimism Removal (CPR): 0.172ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 0.000 0.000 r BUFGCTRL_X0Y21 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.476 1.476 ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X157Y299 FDCE r ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X157Y299 FDCE (Prop_fdce_C_Q) 0.223 1.699 r ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/Q net (fo=3, routed) 1.043 2.742 ngFEC/g_pm[10].phase_mon/PS_max_reg_n_0_[6] SLICE_X154Y308 LUT4 (Prop_lut4_I2_O) 0.043 2.785 r ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8/O net (fo=1, routed) 0.000 2.785 ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8_n_0 SLICE_X154Y308 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.180 2.965 r ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2/CO[3] net (fo=1, routed) 0.000 2.965 ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2_n_0 SLICE_X154Y309 CARRY4 (Prop_carry4_CI_CO[0]) 0.133 3.098 r ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_3__2/CO[0] net (fo=1, routed) 0.824 3.922 ngFEC/g_pm[10].phase_mon/gtOp SLICE_X147Y300 LUT5 (Prop_lut5_I2_O) 0.128 4.050 r ngFEC/g_pm[10].phase_mon/PS_max[9]_i_1__8/O net (fo=10, routed) 0.791 4.841 ngFEC/g_pm[10].phase_mon/PS_max SLICE_X157Y299 FDCE r ngFEC/g_pm[10].phase_mon/PS_max_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 8.200 8.200 r BUFGCTRL_X0Y21 BUFG 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.304 9.504 ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X157Y299 FDCE r ngFEC/g_pm[10].phase_mon/PS_max_reg[4]/C clock pessimism 0.172 9.676 clock uncertainty -0.035 9.641 SLICE_X157Y299 FDCE (Setup_fdce_C_CE) -0.201 9.440 ngFEC/g_pm[10].phase_mon/PS_max_reg[4] ------------------------------------------------------------------- required time 9.440 arrival time -4.841 ------------------------------------------------------------------- slack 4.598 Slack (MET) : 4.598ns (required time - arrival time) Source: ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/CE (rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_6 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_6 rise@8.200ns - txWordclkl12_6 rise@0.000ns) Data Path Delay: 3.365ns (logic 0.707ns (21.009%) route 2.658ns (78.991%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.304ns = ( 9.504 - 8.200 ) Source Clock Delay (SCD): 1.476ns Clock Pessimism Removal (CPR): 0.172ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 0.000 0.000 r BUFGCTRL_X0Y21 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.476 1.476 ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X157Y299 FDCE r ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X157Y299 FDCE (Prop_fdce_C_Q) 0.223 1.699 r ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/Q net (fo=3, routed) 1.043 2.742 ngFEC/g_pm[10].phase_mon/PS_max_reg_n_0_[6] SLICE_X154Y308 LUT4 (Prop_lut4_I2_O) 0.043 2.785 r ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8/O net (fo=1, routed) 0.000 2.785 ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8_n_0 SLICE_X154Y308 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.180 2.965 r ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2/CO[3] net (fo=1, routed) 0.000 2.965 ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2_n_0 SLICE_X154Y309 CARRY4 (Prop_carry4_CI_CO[0]) 0.133 3.098 r ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_3__2/CO[0] net (fo=1, routed) 0.824 3.922 ngFEC/g_pm[10].phase_mon/gtOp SLICE_X147Y300 LUT5 (Prop_lut5_I2_O) 0.128 4.050 r ngFEC/g_pm[10].phase_mon/PS_max[9]_i_1__8/O net (fo=10, routed) 0.791 4.841 ngFEC/g_pm[10].phase_mon/PS_max SLICE_X157Y299 FDCE r ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 8.200 8.200 r BUFGCTRL_X0Y21 BUFG 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.304 9.504 ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X157Y299 FDCE r ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C clock pessimism 0.172 9.676 clock uncertainty -0.035 9.641 SLICE_X157Y299 FDCE (Setup_fdce_C_CE) -0.201 9.440 ngFEC/g_pm[10].phase_mon/PS_max_reg[6] ------------------------------------------------------------------- required time 9.440 arrival time -4.841 ------------------------------------------------------------------- slack 4.598 Slack (MET) : 4.825ns (required time - arrival time) Source: ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[10].phase_mon/PS_max_reg[3]/CE (rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_6 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_6 rise@8.200ns - txWordclkl12_6 rise@0.000ns) Data Path Delay: 3.088ns (logic 0.707ns (22.892%) route 2.381ns (77.108%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: -0.050ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.303ns = ( 9.503 - 8.200 ) Source Clock Delay (SCD): 1.476ns Clock Pessimism Removal (CPR): 0.123ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 0.000 0.000 r BUFGCTRL_X0Y21 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.476 1.476 ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X157Y299 FDCE r ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X157Y299 FDCE (Prop_fdce_C_Q) 0.223 1.699 r ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/Q net (fo=3, routed) 1.043 2.742 ngFEC/g_pm[10].phase_mon/PS_max_reg_n_0_[6] SLICE_X154Y308 LUT4 (Prop_lut4_I2_O) 0.043 2.785 r ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8/O net (fo=1, routed) 0.000 2.785 ngFEC/g_pm[10].phase_mon/PS_max[9]_i_12__8_n_0 SLICE_X154Y308 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.180 2.965 r ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2/CO[3] net (fo=1, routed) 0.000 2.965 ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_5__2_n_0 SLICE_X154Y309 CARRY4 (Prop_carry4_CI_CO[0]) 0.133 3.098 r ngFEC/g_pm[10].phase_mon/PS_max_reg[9]_i_3__2/CO[0] net (fo=1, routed) 0.824 3.922 ngFEC/g_pm[10].phase_mon/gtOp SLICE_X147Y300 LUT5 (Prop_lut5_I2_O) 0.128 4.050 r ngFEC/g_pm[10].phase_mon/PS_max[9]_i_1__8/O net (fo=10, routed) 0.514 4.564 ngFEC/g_pm[10].phase_mon/PS_max SLICE_X153Y298 FDCE r ngFEC/g_pm[10].phase_mon/PS_max_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 8.200 8.200 r BUFGCTRL_X0Y21 BUFG 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.303 9.503 ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X153Y298 FDCE r ngFEC/g_pm[10].phase_mon/PS_max_reg[3]/C clock pessimism 0.123 9.626 clock uncertainty -0.035 9.591 SLICE_X153Y298 FDCE (Setup_fdce_C_CE) -0.201 9.390 ngFEC/g_pm[10].phase_mon/PS_max_reg[3] ------------------------------------------------------------------- required time 9.390 arrival time -4.564 ------------------------------------------------------------------- slack 4.825 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/g_pm[10].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[10].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/D (rising edge-triggered cell FDRE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_6 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_6 rise@0.000ns - txWordclkl12_6 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.889ns Source Clock Delay (SCD): 0.662ns Clock Pessimism Removal (CPR): 0.227ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 0.000 0.000 r BUFGCTRL_X0Y21 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.662 0.662 ngFEC/g_pm[10].phase_mon/sample_PS_Sync_inst/dest_clk SLICE_X137Y297 FDRE r ngFEC/g_pm[10].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X137Y297 FDRE (Prop_fdre_C_Q) 0.100 0.762 r ngFEC/g_pm[10].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/Q net (fo=1, routed) 0.055 0.817 ngFEC/g_pm[10].phase_mon/sample_PS_Sync_inst/syncstages_ff[0] SLICE_X137Y297 FDRE r ngFEC/g_pm[10].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 0.000 0.000 r BUFGCTRL_X0Y21 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.889 0.889 ngFEC/g_pm[10].phase_mon/sample_PS_Sync_inst/dest_clk SLICE_X137Y297 FDRE r ngFEC/g_pm[10].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/C clock pessimism -0.227 0.662 SLICE_X137Y297 FDRE (Hold_fdre_C_D) 0.047 0.709 ngFEC/g_pm[10].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1] ------------------------------------------------------------------- required time -0.709 arrival time 0.817 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_6 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_6 rise@0.000ns - txWordclkl12_6 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.918ns Source Clock Delay (SCD): 0.691ns Clock Pessimism Removal (CPR): 0.227ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 0.000 0.000 r BUFGCTRL_X0Y21 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.691 0.691 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in SLICE_X185Y277 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X185Y277 FDRE (Prop_fdre_C_Q) 0.100 0.791 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q net (fo=1, routed) 0.055 0.846 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync1 SLICE_X185Y277 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 0.000 0.000 r BUFGCTRL_X0Y21 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.918 0.918 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in SLICE_X185Y277 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C clock pessimism -0.227 0.691 SLICE_X185Y277 FDRE (Hold_fdre_C_D) 0.047 0.738 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.738 arrival time 0.846 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_6 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_6 rise@0.000ns - txWordclkl12_6 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.918ns Source Clock Delay (SCD): 0.692ns Clock Pessimism Removal (CPR): 0.226ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 0.000 0.000 r BUFGCTRL_X0Y21 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.692 0.692 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in SLICE_X189Y272 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X189Y272 FDRE (Prop_fdre_C_Q) 0.100 0.792 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/Q net (fo=1, routed) 0.055 0.847 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync1 SLICE_X189Y272 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 0.000 0.000 r BUFGCTRL_X0Y21 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.918 0.918 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in SLICE_X189Y272 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/C clock pessimism -0.226 0.692 SLICE_X189Y272 FDRE (Hold_fdre_C_D) 0.047 0.739 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.739 arrival time 0.847 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.123ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/C (rising edge-triggered cell FDRE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/D (rising edge-triggered cell SRL16E clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_6 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_6 rise@0.000ns - txWordclkl12_6 rise@0.000ns) Data Path Delay: 0.261ns (logic 0.118ns (45.295%) route 0.143ns (54.705%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.828ns Source Clock Delay (SCD): 0.619ns Clock Pessimism Removal (CPR): 0.173ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 0.000 0.000 r BUFGCTRL_X0Y21 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.619 0.619 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk SLICE_X176Y239 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X176Y239 FDRE (Prop_fdre_C_Q) 0.118 0.737 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/Q net (fo=1, routed) 0.143 0.880 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/dest_out SLICE_X178Y238 SRL16E r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 0.000 0.000 r BUFGCTRL_X0Y21 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.828 0.828 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X178Y238 SRL16E r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK clock pessimism -0.173 0.655 SLICE_X178Y238 SRL16E (Hold_srl16e_CLK_D) 0.102 0.757 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3 ------------------------------------------------------------------- required time -0.757 arrival time 0.880 ------------------------------------------------------------------- slack 0.123 Slack (MET) : 0.125ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[80]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/D (rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_6 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_6 rise@0.000ns - txWordclkl12_6 rise@0.000ns) Data Path Delay: 0.197ns (logic 0.146ns (74.289%) route 0.051ns (25.711%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.821ns Source Clock Delay (SCD): 0.614ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 0.000 0.000 r BUFGCTRL_X0Y21 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.614 0.614 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X170Y236 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[80]/C ------------------------------------------------------------------- ------------------- SLICE_X170Y236 FDCE (Prop_fdce_C_Q) 0.118 0.732 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[80]/Q net (fo=1, routed) 0.051 0.783 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/data4[0] SLICE_X171Y236 LUT6 (Prop_lut6_I0_O) 0.028 0.811 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[0]_i_1__4/O net (fo=1, routed) 0.000 0.811 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[0]_i_1__4_n_0 SLICE_X171Y236 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 0.000 0.000 r BUFGCTRL_X0Y21 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.821 0.821 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X171Y236 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/C clock pessimism -0.196 0.625 SLICE_X171Y236 FDCE (Hold_fdce_C_D) 0.061 0.686 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0] ------------------------------------------------------------------- required time -0.686 arrival time 0.811 ------------------------------------------------------------------- slack 0.125 Slack (MET) : 0.131ns (arrival time - required time) Source: ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D (rising edge-triggered cell FDRE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_6 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_6 rise@0.000ns - txWordclkl12_6 rise@0.000ns) Data Path Delay: 0.173ns (logic 0.118ns (68.255%) route 0.055ns (31.745%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.897ns Source Clock Delay (SCD): 0.669ns Clock Pessimism Removal (CPR): 0.228ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 0.000 0.000 r BUFGCTRL_X0Y21 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.669 0.669 ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/dest_clk SLICE_X150Y298 FDRE r ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X150Y298 FDRE (Prop_fdre_C_Q) 0.118 0.787 r ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/Q net (fo=1, routed) 0.055 0.842 ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff[0] SLICE_X150Y298 FDRE r ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 0.000 0.000 r BUFGCTRL_X0Y21 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.897 0.897 ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/dest_clk SLICE_X150Y298 FDRE r ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/C clock pessimism -0.228 0.669 SLICE_X150Y298 FDRE (Hold_fdre_C_D) 0.042 0.711 ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1] ------------------------------------------------------------------- required time -0.711 arrival time 0.842 ------------------------------------------------------------------- slack 0.131 Slack (MET) : 0.131ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D (rising edge-triggered cell FDRE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_6 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_6 rise@0.000ns - txWordclkl12_6 rise@0.000ns) Data Path Delay: 0.173ns (logic 0.118ns (68.255%) route 0.055ns (31.745%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.828ns Source Clock Delay (SCD): 0.619ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 0.000 0.000 r BUFGCTRL_X0Y21 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.619 0.619 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk SLICE_X176Y239 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X176Y239 FDRE (Prop_fdre_C_Q) 0.118 0.737 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/Q net (fo=1, routed) 0.055 0.792 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff[0] SLICE_X176Y239 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 0.000 0.000 r BUFGCTRL_X0Y21 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.828 0.828 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk SLICE_X176Y239 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/C clock pessimism -0.209 0.619 SLICE_X176Y239 FDRE (Hold_fdre_C_D) 0.042 0.661 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1] ------------------------------------------------------------------- required time -0.661 arrival time 0.792 ------------------------------------------------------------------- slack 0.131 Slack (MET) : 0.137ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[116]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[16]/D (rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_6 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_6 rise@0.000ns - txWordclkl12_6 rise@0.000ns) Data Path Delay: 0.208ns (logic 0.128ns (61.615%) route 0.080ns (38.385%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.822ns Source Clock Delay (SCD): 0.615ns Clock Pessimism Removal (CPR): 0.196ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 0.000 0.000 r BUFGCTRL_X0Y21 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.615 0.615 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X172Y235 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[116]/C ------------------------------------------------------------------- ------------------- SLICE_X172Y235 FDCE (Prop_fdce_C_Q) 0.100 0.715 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[116]/Q net (fo=1, routed) 0.080 0.795 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/data5[16] SLICE_X173Y235 LUT6 (Prop_lut6_I2_O) 0.028 0.823 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[16]_i_1__4/O net (fo=1, routed) 0.000 0.823 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[16]_i_1__4_n_0 SLICE_X173Y235 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[16]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 0.000 0.000 r BUFGCTRL_X0Y21 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.822 0.822 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X173Y235 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[16]/C clock pessimism -0.196 0.626 SLICE_X173Y235 FDCE (Hold_fdce_C_D) 0.060 0.686 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[16] ------------------------------------------------------------------- required time -0.686 arrival time 0.823 ------------------------------------------------------------------- slack 0.137 Slack (MET) : 0.143ns (arrival time - required time) Source: ngFEC/g_pm[10].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[3]/C (rising edge-triggered cell FDRE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[10].phase_mon/sample_PS_Sync_q_reg/D (rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_6 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_6 rise@0.000ns - txWordclkl12_6 rise@0.000ns) Data Path Delay: 0.250ns (logic 0.130ns (52.066%) route 0.120ns (47.934%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.889ns Source Clock Delay (SCD): 0.662ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 0.000 0.000 r BUFGCTRL_X0Y21 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.662 0.662 ngFEC/g_pm[10].phase_mon/sample_PS_Sync_inst/dest_clk SLICE_X137Y297 FDRE r ngFEC/g_pm[10].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X137Y297 FDRE (Prop_fdre_C_Q) 0.100 0.762 r ngFEC/g_pm[10].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[3]/Q net (fo=2, routed) 0.120 0.882 ngFEC/g_pm[10].phase_mon/sample_PS_Sync SLICE_X138Y297 LUT5 (Prop_lut5_I0_O) 0.030 0.912 r ngFEC/g_pm[10].phase_mon/sample_PS_Sync_q_i_1__8/O net (fo=1, routed) 0.000 0.912 ngFEC/g_pm[10].phase_mon/sample_PS_Sync_q_i_1__8_n_0 SLICE_X138Y297 FDCE r ngFEC/g_pm[10].phase_mon/sample_PS_Sync_q_reg/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 0.000 0.000 r BUFGCTRL_X0Y21 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.889 0.889 ngFEC/g_pm[10].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X138Y297 FDCE r ngFEC/g_pm[10].phase_mon/sample_PS_Sync_q_reg/C clock pessimism -0.213 0.676 SLICE_X138Y297 FDCE (Hold_fdce_C_D) 0.093 0.769 ngFEC/g_pm[10].phase_mon/sample_PS_Sync_q_reg ------------------------------------------------------------------- required time -0.769 arrival time 0.912 ------------------------------------------------------------------- slack 0.143 Slack (MET) : 0.148ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[85]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/D (rising edge-triggered cell FDCE clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_6 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_6 rise@0.000ns - txWordclkl12_6 rise@0.000ns) Data Path Delay: 0.247ns (logic 0.155ns (62.824%) route 0.092ns (37.176%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.820ns Source Clock Delay (SCD): 0.614ns Clock Pessimism Removal (CPR): 0.194ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 0.000 0.000 r BUFGCTRL_X0Y21 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.614 0.614 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X169Y234 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[85]/C ------------------------------------------------------------------- ------------------- SLICE_X169Y234 FDCE (Prop_fdce_C_Q) 0.091 0.705 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[85]/Q net (fo=1, routed) 0.092 0.797 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/data4[5] SLICE_X170Y234 LUT6 (Prop_lut6_I0_O) 0.064 0.861 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[5]_i_1__4/O net (fo=1, routed) 0.000 0.861 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[5]_i_1__4_n_0 SLICE_X170Y234 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 0.000 0.000 r BUFGCTRL_X0Y21 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.820 0.820 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X170Y234 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/C clock pessimism -0.194 0.626 SLICE_X170Y234 FDCE (Hold_fdce_C_D) 0.087 0.713 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5] ------------------------------------------------------------------- required time -0.713 arrival time 0.861 ------------------------------------------------------------------- slack 0.148 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: txWordclkl12_6 Waveform(ns): { 0.000 4.100 } Period(ns): 8.200 Sources: { ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/TXUSRCLK n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y21 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK Min Period n/a GTXE2_CHANNEL/TXUSRCLK2 n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y21 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X154Y298 ngFEC/g_pm[10].phase_mon/PS_max_reg[8]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X154Y298 ngFEC/g_pm[10].phase_mon/PS_max_reg[9]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X138Y297 ngFEC/g_pm[10].phase_mon/en_chk_reg[2]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X150Y298 ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X150Y298 ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[2]/C Min Period n/a FDPE/C n/a 0.750 8.200 7.450 SLICE_X148Y298 ngFEC/g_pm[10].phase_mon/inh_cntr_reg[2]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X137Y297 ngFEC/g_pm[10].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/C Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X137Y297 ngFEC/g_pm[10].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[2]/C Low Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X178Y238 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK Low Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X178Y238 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X154Y298 ngFEC/g_pm[10].phase_mon/PS_max_reg[8]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X154Y298 ngFEC/g_pm[10].phase_mon/PS_max_reg[8]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X154Y298 ngFEC/g_pm[10].phase_mon/PS_max_reg[9]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X154Y298 ngFEC/g_pm[10].phase_mon/PS_max_reg[9]/C Low Pulse Width Fast FDRE/C n/a 0.400 4.100 3.700 SLICE_X150Y298 ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/C Low Pulse Width Fast FDRE/C n/a 0.400 4.100 3.700 SLICE_X150Y298 ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[2]/C Low Pulse Width Fast FDPE/C n/a 0.400 4.100 3.700 SLICE_X148Y298 ngFEC/g_pm[10].phase_mon/inh_cntr_reg[2]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X175Y237 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[1]/C High Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X178Y238 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X178Y238 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK High Pulse Width Fast FDCE/C n/a 0.350 4.100 3.750 SLICE_X170Y237 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[117]/C High Pulse Width Fast FDCE/C n/a 0.350 4.100 3.750 SLICE_X170Y237 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[119]/C High Pulse Width Fast FDCE/C n/a 0.350 4.100 3.750 SLICE_X171Y237 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[92]/C High Pulse Width Fast FDCE/C n/a 0.350 4.100 3.750 SLICE_X170Y237 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[94]/C High Pulse Width Fast FDCE/C n/a 0.350 4.100 3.750 SLICE_X170Y237 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[95]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X187Y274 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_reg/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X188Y273 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X188Y275 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[10]/C --------------------------------------------------------------------------------------------------- From Clock: txWordclkl12_7 To Clock: txWordclkl12_7 Setup : 0 Failing Endpoints, Worst Slack 5.223ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.083ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.458ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.223ns (required time - arrival time) Source: ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/C (rising edge-triggered cell FDPE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[11].phase_mon/PS_min_reg[1]/CE (rising edge-triggered cell FDPE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_7 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_7 rise@8.200ns - txWordclkl12_7 rise@0.000ns) Data Path Delay: 2.715ns (logic 0.801ns (29.498%) route 1.914ns (70.502%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: -0.025ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.293ns = ( 9.493 - 8.200 ) Source Clock Delay (SCD): 1.466ns Clock Pessimism Removal (CPR): 0.148ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 0.000 0.000 r BUFGCTRL_X0Y22 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.466 1.466 ngFEC/g_pm[11].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X138Y298 FDPE r ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X138Y298 FDPE (Prop_fdpe_C_Q) 0.236 1.702 r ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/Q net (fo=3, routed) 0.652 2.354 ngFEC/g_pm[11].phase_mon/PS_min_reg_n_0_[7] SLICE_X138Y303 LUT4 (Prop_lut4_I0_O) 0.124 2.478 r ngFEC/g_pm[11].phase_mon/PS_min[9]_i_10__9/O net (fo=1, routed) 0.000 2.478 ngFEC/g_pm[11].phase_mon/PS_min[9]_i_10__9_n_0 SLICE_X138Y303 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.180 2.658 r ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_3__9/CO[3] net (fo=1, routed) 0.000 2.658 ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_3__9_n_0 SLICE_X138Y304 CARRY4 (Prop_carry4_CI_CO[0]) 0.133 2.791 r ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_2__9/CO[0] net (fo=1, routed) 0.618 3.410 ngFEC/g_pm[11].phase_mon/ltOp SLICE_X149Y299 LUT5 (Prop_lut5_I2_O) 0.128 3.538 r ngFEC/g_pm[11].phase_mon/PS_min[9]_i_1__9/O net (fo=10, routed) 0.644 4.181 ngFEC/g_pm[11].phase_mon/PS_min SLICE_X139Y297 FDPE r ngFEC/g_pm[11].phase_mon/PS_min_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 8.200 8.200 r BUFGCTRL_X0Y22 BUFG 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.293 9.493 ngFEC/g_pm[11].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X139Y297 FDPE r ngFEC/g_pm[11].phase_mon/PS_min_reg[1]/C clock pessimism 0.148 9.641 clock uncertainty -0.035 9.606 SLICE_X139Y297 FDPE (Setup_fdpe_C_CE) -0.201 9.405 ngFEC/g_pm[11].phase_mon/PS_min_reg[1] ------------------------------------------------------------------- required time 9.405 arrival time -4.181 ------------------------------------------------------------------- slack 5.223 Slack (MET) : 5.223ns (required time - arrival time) Source: ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/C (rising edge-triggered cell FDPE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[11].phase_mon/PS_min_reg[8]/CE (rising edge-triggered cell FDPE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_7 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_7 rise@8.200ns - txWordclkl12_7 rise@0.000ns) Data Path Delay: 2.715ns (logic 0.801ns (29.498%) route 1.914ns (70.502%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: -0.025ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.293ns = ( 9.493 - 8.200 ) Source Clock Delay (SCD): 1.466ns Clock Pessimism Removal (CPR): 0.148ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 0.000 0.000 r BUFGCTRL_X0Y22 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.466 1.466 ngFEC/g_pm[11].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X138Y298 FDPE r ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X138Y298 FDPE (Prop_fdpe_C_Q) 0.236 1.702 r ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/Q net (fo=3, routed) 0.652 2.354 ngFEC/g_pm[11].phase_mon/PS_min_reg_n_0_[7] SLICE_X138Y303 LUT4 (Prop_lut4_I0_O) 0.124 2.478 r ngFEC/g_pm[11].phase_mon/PS_min[9]_i_10__9/O net (fo=1, routed) 0.000 2.478 ngFEC/g_pm[11].phase_mon/PS_min[9]_i_10__9_n_0 SLICE_X138Y303 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.180 2.658 r ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_3__9/CO[3] net (fo=1, routed) 0.000 2.658 ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_3__9_n_0 SLICE_X138Y304 CARRY4 (Prop_carry4_CI_CO[0]) 0.133 2.791 r ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_2__9/CO[0] net (fo=1, routed) 0.618 3.410 ngFEC/g_pm[11].phase_mon/ltOp SLICE_X149Y299 LUT5 (Prop_lut5_I2_O) 0.128 3.538 r ngFEC/g_pm[11].phase_mon/PS_min[9]_i_1__9/O net (fo=10, routed) 0.644 4.181 ngFEC/g_pm[11].phase_mon/PS_min SLICE_X139Y297 FDPE r ngFEC/g_pm[11].phase_mon/PS_min_reg[8]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 8.200 8.200 r BUFGCTRL_X0Y22 BUFG 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.293 9.493 ngFEC/g_pm[11].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X139Y297 FDPE r ngFEC/g_pm[11].phase_mon/PS_min_reg[8]/C clock pessimism 0.148 9.641 clock uncertainty -0.035 9.606 SLICE_X139Y297 FDPE (Setup_fdpe_C_CE) -0.201 9.405 ngFEC/g_pm[11].phase_mon/PS_min_reg[8] ------------------------------------------------------------------- required time 9.405 arrival time -4.181 ------------------------------------------------------------------- slack 5.223 Slack (MET) : 5.323ns (required time - arrival time) Source: ngFEC/g_pm[11].phase_mon/PS_max_reg[0]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[11].phase_mon/PS_max_reg[2]/CE (rising edge-triggered cell FDCE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_7 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_7 rise@8.200ns - txWordclkl12_7 rise@0.000ns) Data Path Delay: 2.615ns (logic 0.795ns (30.396%) route 1.820ns (69.604%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: -0.025ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.304ns = ( 9.504 - 8.200 ) Source Clock Delay (SCD): 1.476ns Clock Pessimism Removal (CPR): 0.147ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 0.000 0.000 r BUFGCTRL_X0Y22 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.476 1.476 ngFEC/g_pm[11].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X156Y299 FDCE r ngFEC/g_pm[11].phase_mon/PS_max_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X156Y299 FDCE (Prop_fdce_C_Q) 0.223 1.699 r ngFEC/g_pm[11].phase_mon/PS_max_reg[0]/Q net (fo=3, routed) 0.815 2.514 ngFEC/g_pm[11].phase_mon/PS_max_reg_n_0_[0] SLICE_X156Y304 LUT4 (Prop_lut4_I2_O) 0.043 2.557 r ngFEC/g_pm[11].phase_mon/PS_max[9]_i_14__9/O net (fo=1, routed) 0.000 2.557 ngFEC/g_pm[11].phase_mon/PS_max[9]_i_14__9_n_0 SLICE_X156Y304 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.259 2.816 r ngFEC/g_pm[11].phase_mon/PS_max_reg[9]_i_4__5/CO[3] net (fo=1, routed) 0.000 2.816 ngFEC/g_pm[11].phase_mon/PS_max_reg[9]_i_4__5_n_0 SLICE_X156Y305 CARRY4 (Prop_carry4_CI_CO[0]) 0.139 2.955 r ngFEC/g_pm[11].phase_mon/PS_max_reg[9]_i_2__5/CO[0] net (fo=1, routed) 0.425 3.380 ngFEC/g_pm[11].phase_mon/gtOp SLICE_X149Y299 LUT5 (Prop_lut5_I2_O) 0.131 3.511 r ngFEC/g_pm[11].phase_mon/PS_max[9]_i_1__9/O net (fo=10, routed) 0.580 4.091 ngFEC/g_pm[11].phase_mon/PS_max SLICE_X156Y298 FDCE r ngFEC/g_pm[11].phase_mon/PS_max_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 8.200 8.200 r BUFGCTRL_X0Y22 BUFG 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.304 9.504 ngFEC/g_pm[11].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X156Y298 FDCE r ngFEC/g_pm[11].phase_mon/PS_max_reg[2]/C clock pessimism 0.147 9.651 clock uncertainty -0.035 9.616 SLICE_X156Y298 FDCE (Setup_fdce_C_CE) -0.201 9.415 ngFEC/g_pm[11].phase_mon/PS_max_reg[2] ------------------------------------------------------------------- required time 9.415 arrival time -4.091 ------------------------------------------------------------------- slack 5.323 Slack (MET) : 5.323ns (required time - arrival time) Source: ngFEC/g_pm[11].phase_mon/PS_max_reg[0]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[11].phase_mon/PS_max_reg[6]/CE (rising edge-triggered cell FDCE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_7 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_7 rise@8.200ns - txWordclkl12_7 rise@0.000ns) Data Path Delay: 2.615ns (logic 0.795ns (30.396%) route 1.820ns (69.604%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: -0.025ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.304ns = ( 9.504 - 8.200 ) Source Clock Delay (SCD): 1.476ns Clock Pessimism Removal (CPR): 0.147ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 0.000 0.000 r BUFGCTRL_X0Y22 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.476 1.476 ngFEC/g_pm[11].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X156Y299 FDCE r ngFEC/g_pm[11].phase_mon/PS_max_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X156Y299 FDCE (Prop_fdce_C_Q) 0.223 1.699 r ngFEC/g_pm[11].phase_mon/PS_max_reg[0]/Q net (fo=3, routed) 0.815 2.514 ngFEC/g_pm[11].phase_mon/PS_max_reg_n_0_[0] SLICE_X156Y304 LUT4 (Prop_lut4_I2_O) 0.043 2.557 r ngFEC/g_pm[11].phase_mon/PS_max[9]_i_14__9/O net (fo=1, routed) 0.000 2.557 ngFEC/g_pm[11].phase_mon/PS_max[9]_i_14__9_n_0 SLICE_X156Y304 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.259 2.816 r ngFEC/g_pm[11].phase_mon/PS_max_reg[9]_i_4__5/CO[3] net (fo=1, routed) 0.000 2.816 ngFEC/g_pm[11].phase_mon/PS_max_reg[9]_i_4__5_n_0 SLICE_X156Y305 CARRY4 (Prop_carry4_CI_CO[0]) 0.139 2.955 r ngFEC/g_pm[11].phase_mon/PS_max_reg[9]_i_2__5/CO[0] net (fo=1, routed) 0.425 3.380 ngFEC/g_pm[11].phase_mon/gtOp SLICE_X149Y299 LUT5 (Prop_lut5_I2_O) 0.131 3.511 r ngFEC/g_pm[11].phase_mon/PS_max[9]_i_1__9/O net (fo=10, routed) 0.580 4.091 ngFEC/g_pm[11].phase_mon/PS_max SLICE_X156Y298 FDCE r ngFEC/g_pm[11].phase_mon/PS_max_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 8.200 8.200 r BUFGCTRL_X0Y22 BUFG 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.304 9.504 ngFEC/g_pm[11].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X156Y298 FDCE r ngFEC/g_pm[11].phase_mon/PS_max_reg[6]/C clock pessimism 0.147 9.651 clock uncertainty -0.035 9.616 SLICE_X156Y298 FDCE (Setup_fdce_C_CE) -0.201 9.415 ngFEC/g_pm[11].phase_mon/PS_max_reg[6] ------------------------------------------------------------------- required time 9.415 arrival time -4.091 ------------------------------------------------------------------- slack 5.323 Slack (MET) : 5.449ns (required time - arrival time) Source: ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/C (rising edge-triggered cell FDPE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[11].phase_mon/PS_min_reg[0]/CE (rising edge-triggered cell FDPE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_7 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_7 rise@8.200ns - txWordclkl12_7 rise@0.000ns) Data Path Delay: 2.537ns (logic 0.801ns (31.570%) route 1.736ns (68.430%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.293ns = ( 9.493 - 8.200 ) Source Clock Delay (SCD): 1.466ns Clock Pessimism Removal (CPR): 0.173ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 0.000 0.000 r BUFGCTRL_X0Y22 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.466 1.466 ngFEC/g_pm[11].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X138Y298 FDPE r ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X138Y298 FDPE (Prop_fdpe_C_Q) 0.236 1.702 r ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/Q net (fo=3, routed) 0.652 2.354 ngFEC/g_pm[11].phase_mon/PS_min_reg_n_0_[7] SLICE_X138Y303 LUT4 (Prop_lut4_I0_O) 0.124 2.478 r ngFEC/g_pm[11].phase_mon/PS_min[9]_i_10__9/O net (fo=1, routed) 0.000 2.478 ngFEC/g_pm[11].phase_mon/PS_min[9]_i_10__9_n_0 SLICE_X138Y303 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.180 2.658 r ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_3__9/CO[3] net (fo=1, routed) 0.000 2.658 ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_3__9_n_0 SLICE_X138Y304 CARRY4 (Prop_carry4_CI_CO[0]) 0.133 2.791 r ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_2__9/CO[0] net (fo=1, routed) 0.618 3.410 ngFEC/g_pm[11].phase_mon/ltOp SLICE_X149Y299 LUT5 (Prop_lut5_I2_O) 0.128 3.538 r ngFEC/g_pm[11].phase_mon/PS_min[9]_i_1__9/O net (fo=10, routed) 0.466 4.003 ngFEC/g_pm[11].phase_mon/PS_min SLICE_X138Y298 FDPE r ngFEC/g_pm[11].phase_mon/PS_min_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 8.200 8.200 r BUFGCTRL_X0Y22 BUFG 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.293 9.493 ngFEC/g_pm[11].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X138Y298 FDPE r ngFEC/g_pm[11].phase_mon/PS_min_reg[0]/C clock pessimism 0.173 9.666 clock uncertainty -0.035 9.631 SLICE_X138Y298 FDPE (Setup_fdpe_C_CE) -0.178 9.453 ngFEC/g_pm[11].phase_mon/PS_min_reg[0] ------------------------------------------------------------------- required time 9.453 arrival time -4.003 ------------------------------------------------------------------- slack 5.449 Slack (MET) : 5.449ns (required time - arrival time) Source: ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/C (rising edge-triggered cell FDPE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[11].phase_mon/PS_min_reg[2]/CE (rising edge-triggered cell FDPE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_7 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_7 rise@8.200ns - txWordclkl12_7 rise@0.000ns) Data Path Delay: 2.537ns (logic 0.801ns (31.570%) route 1.736ns (68.430%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.293ns = ( 9.493 - 8.200 ) Source Clock Delay (SCD): 1.466ns Clock Pessimism Removal (CPR): 0.173ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 0.000 0.000 r BUFGCTRL_X0Y22 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.466 1.466 ngFEC/g_pm[11].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X138Y298 FDPE r ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X138Y298 FDPE (Prop_fdpe_C_Q) 0.236 1.702 r ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/Q net (fo=3, routed) 0.652 2.354 ngFEC/g_pm[11].phase_mon/PS_min_reg_n_0_[7] SLICE_X138Y303 LUT4 (Prop_lut4_I0_O) 0.124 2.478 r ngFEC/g_pm[11].phase_mon/PS_min[9]_i_10__9/O net (fo=1, routed) 0.000 2.478 ngFEC/g_pm[11].phase_mon/PS_min[9]_i_10__9_n_0 SLICE_X138Y303 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.180 2.658 r ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_3__9/CO[3] net (fo=1, routed) 0.000 2.658 ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_3__9_n_0 SLICE_X138Y304 CARRY4 (Prop_carry4_CI_CO[0]) 0.133 2.791 r ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_2__9/CO[0] net (fo=1, routed) 0.618 3.410 ngFEC/g_pm[11].phase_mon/ltOp SLICE_X149Y299 LUT5 (Prop_lut5_I2_O) 0.128 3.538 r ngFEC/g_pm[11].phase_mon/PS_min[9]_i_1__9/O net (fo=10, routed) 0.466 4.003 ngFEC/g_pm[11].phase_mon/PS_min SLICE_X138Y298 FDPE r ngFEC/g_pm[11].phase_mon/PS_min_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 8.200 8.200 r BUFGCTRL_X0Y22 BUFG 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.293 9.493 ngFEC/g_pm[11].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X138Y298 FDPE r ngFEC/g_pm[11].phase_mon/PS_min_reg[2]/C clock pessimism 0.173 9.666 clock uncertainty -0.035 9.631 SLICE_X138Y298 FDPE (Setup_fdpe_C_CE) -0.178 9.453 ngFEC/g_pm[11].phase_mon/PS_min_reg[2] ------------------------------------------------------------------- required time 9.453 arrival time -4.003 ------------------------------------------------------------------- slack 5.449 Slack (MET) : 5.449ns (required time - arrival time) Source: ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/C (rising edge-triggered cell FDPE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[11].phase_mon/PS_min_reg[3]/CE (rising edge-triggered cell FDPE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_7 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_7 rise@8.200ns - txWordclkl12_7 rise@0.000ns) Data Path Delay: 2.537ns (logic 0.801ns (31.570%) route 1.736ns (68.430%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.293ns = ( 9.493 - 8.200 ) Source Clock Delay (SCD): 1.466ns Clock Pessimism Removal (CPR): 0.173ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 0.000 0.000 r BUFGCTRL_X0Y22 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.466 1.466 ngFEC/g_pm[11].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X138Y298 FDPE r ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X138Y298 FDPE (Prop_fdpe_C_Q) 0.236 1.702 r ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/Q net (fo=3, routed) 0.652 2.354 ngFEC/g_pm[11].phase_mon/PS_min_reg_n_0_[7] SLICE_X138Y303 LUT4 (Prop_lut4_I0_O) 0.124 2.478 r ngFEC/g_pm[11].phase_mon/PS_min[9]_i_10__9/O net (fo=1, routed) 0.000 2.478 ngFEC/g_pm[11].phase_mon/PS_min[9]_i_10__9_n_0 SLICE_X138Y303 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.180 2.658 r ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_3__9/CO[3] net (fo=1, routed) 0.000 2.658 ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_3__9_n_0 SLICE_X138Y304 CARRY4 (Prop_carry4_CI_CO[0]) 0.133 2.791 r ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_2__9/CO[0] net (fo=1, routed) 0.618 3.410 ngFEC/g_pm[11].phase_mon/ltOp SLICE_X149Y299 LUT5 (Prop_lut5_I2_O) 0.128 3.538 r ngFEC/g_pm[11].phase_mon/PS_min[9]_i_1__9/O net (fo=10, routed) 0.466 4.003 ngFEC/g_pm[11].phase_mon/PS_min SLICE_X138Y298 FDPE r ngFEC/g_pm[11].phase_mon/PS_min_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 8.200 8.200 r BUFGCTRL_X0Y22 BUFG 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.293 9.493 ngFEC/g_pm[11].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X138Y298 FDPE r ngFEC/g_pm[11].phase_mon/PS_min_reg[3]/C clock pessimism 0.173 9.666 clock uncertainty -0.035 9.631 SLICE_X138Y298 FDPE (Setup_fdpe_C_CE) -0.178 9.453 ngFEC/g_pm[11].phase_mon/PS_min_reg[3] ------------------------------------------------------------------- required time 9.453 arrival time -4.003 ------------------------------------------------------------------- slack 5.449 Slack (MET) : 5.449ns (required time - arrival time) Source: ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/C (rising edge-triggered cell FDPE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[11].phase_mon/PS_min_reg[4]/CE (rising edge-triggered cell FDPE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_7 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_7 rise@8.200ns - txWordclkl12_7 rise@0.000ns) Data Path Delay: 2.537ns (logic 0.801ns (31.570%) route 1.736ns (68.430%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.293ns = ( 9.493 - 8.200 ) Source Clock Delay (SCD): 1.466ns Clock Pessimism Removal (CPR): 0.173ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 0.000 0.000 r BUFGCTRL_X0Y22 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.466 1.466 ngFEC/g_pm[11].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X138Y298 FDPE r ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X138Y298 FDPE (Prop_fdpe_C_Q) 0.236 1.702 r ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/Q net (fo=3, routed) 0.652 2.354 ngFEC/g_pm[11].phase_mon/PS_min_reg_n_0_[7] SLICE_X138Y303 LUT4 (Prop_lut4_I0_O) 0.124 2.478 r ngFEC/g_pm[11].phase_mon/PS_min[9]_i_10__9/O net (fo=1, routed) 0.000 2.478 ngFEC/g_pm[11].phase_mon/PS_min[9]_i_10__9_n_0 SLICE_X138Y303 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.180 2.658 r ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_3__9/CO[3] net (fo=1, routed) 0.000 2.658 ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_3__9_n_0 SLICE_X138Y304 CARRY4 (Prop_carry4_CI_CO[0]) 0.133 2.791 r ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_2__9/CO[0] net (fo=1, routed) 0.618 3.410 ngFEC/g_pm[11].phase_mon/ltOp SLICE_X149Y299 LUT5 (Prop_lut5_I2_O) 0.128 3.538 r ngFEC/g_pm[11].phase_mon/PS_min[9]_i_1__9/O net (fo=10, routed) 0.466 4.003 ngFEC/g_pm[11].phase_mon/PS_min SLICE_X138Y298 FDPE r ngFEC/g_pm[11].phase_mon/PS_min_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 8.200 8.200 r BUFGCTRL_X0Y22 BUFG 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.293 9.493 ngFEC/g_pm[11].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X138Y298 FDPE r ngFEC/g_pm[11].phase_mon/PS_min_reg[4]/C clock pessimism 0.173 9.666 clock uncertainty -0.035 9.631 SLICE_X138Y298 FDPE (Setup_fdpe_C_CE) -0.178 9.453 ngFEC/g_pm[11].phase_mon/PS_min_reg[4] ------------------------------------------------------------------- required time 9.453 arrival time -4.003 ------------------------------------------------------------------- slack 5.449 Slack (MET) : 5.449ns (required time - arrival time) Source: ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/C (rising edge-triggered cell FDPE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[11].phase_mon/PS_min_reg[5]/CE (rising edge-triggered cell FDPE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_7 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_7 rise@8.200ns - txWordclkl12_7 rise@0.000ns) Data Path Delay: 2.537ns (logic 0.801ns (31.570%) route 1.736ns (68.430%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.293ns = ( 9.493 - 8.200 ) Source Clock Delay (SCD): 1.466ns Clock Pessimism Removal (CPR): 0.173ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 0.000 0.000 r BUFGCTRL_X0Y22 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.466 1.466 ngFEC/g_pm[11].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X138Y298 FDPE r ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X138Y298 FDPE (Prop_fdpe_C_Q) 0.236 1.702 r ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/Q net (fo=3, routed) 0.652 2.354 ngFEC/g_pm[11].phase_mon/PS_min_reg_n_0_[7] SLICE_X138Y303 LUT4 (Prop_lut4_I0_O) 0.124 2.478 r ngFEC/g_pm[11].phase_mon/PS_min[9]_i_10__9/O net (fo=1, routed) 0.000 2.478 ngFEC/g_pm[11].phase_mon/PS_min[9]_i_10__9_n_0 SLICE_X138Y303 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.180 2.658 r ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_3__9/CO[3] net (fo=1, routed) 0.000 2.658 ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_3__9_n_0 SLICE_X138Y304 CARRY4 (Prop_carry4_CI_CO[0]) 0.133 2.791 r ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_2__9/CO[0] net (fo=1, routed) 0.618 3.410 ngFEC/g_pm[11].phase_mon/ltOp SLICE_X149Y299 LUT5 (Prop_lut5_I2_O) 0.128 3.538 r ngFEC/g_pm[11].phase_mon/PS_min[9]_i_1__9/O net (fo=10, routed) 0.466 4.003 ngFEC/g_pm[11].phase_mon/PS_min SLICE_X138Y298 FDPE r ngFEC/g_pm[11].phase_mon/PS_min_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 8.200 8.200 r BUFGCTRL_X0Y22 BUFG 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.293 9.493 ngFEC/g_pm[11].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X138Y298 FDPE r ngFEC/g_pm[11].phase_mon/PS_min_reg[5]/C clock pessimism 0.173 9.666 clock uncertainty -0.035 9.631 SLICE_X138Y298 FDPE (Setup_fdpe_C_CE) -0.178 9.453 ngFEC/g_pm[11].phase_mon/PS_min_reg[5] ------------------------------------------------------------------- required time 9.453 arrival time -4.003 ------------------------------------------------------------------- slack 5.449 Slack (MET) : 5.449ns (required time - arrival time) Source: ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/C (rising edge-triggered cell FDPE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[11].phase_mon/PS_min_reg[6]/CE (rising edge-triggered cell FDPE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_7 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_7 rise@8.200ns - txWordclkl12_7 rise@0.000ns) Data Path Delay: 2.537ns (logic 0.801ns (31.570%) route 1.736ns (68.430%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.293ns = ( 9.493 - 8.200 ) Source Clock Delay (SCD): 1.466ns Clock Pessimism Removal (CPR): 0.173ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 0.000 0.000 r BUFGCTRL_X0Y22 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.466 1.466 ngFEC/g_pm[11].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X138Y298 FDPE r ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X138Y298 FDPE (Prop_fdpe_C_Q) 0.236 1.702 r ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/Q net (fo=3, routed) 0.652 2.354 ngFEC/g_pm[11].phase_mon/PS_min_reg_n_0_[7] SLICE_X138Y303 LUT4 (Prop_lut4_I0_O) 0.124 2.478 r ngFEC/g_pm[11].phase_mon/PS_min[9]_i_10__9/O net (fo=1, routed) 0.000 2.478 ngFEC/g_pm[11].phase_mon/PS_min[9]_i_10__9_n_0 SLICE_X138Y303 CARRY4 (Prop_carry4_S[3]_CO[3]) 0.180 2.658 r ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_3__9/CO[3] net (fo=1, routed) 0.000 2.658 ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_3__9_n_0 SLICE_X138Y304 CARRY4 (Prop_carry4_CI_CO[0]) 0.133 2.791 r ngFEC/g_pm[11].phase_mon/PS_min_reg[9]_i_2__9/CO[0] net (fo=1, routed) 0.618 3.410 ngFEC/g_pm[11].phase_mon/ltOp SLICE_X149Y299 LUT5 (Prop_lut5_I2_O) 0.128 3.538 r ngFEC/g_pm[11].phase_mon/PS_min[9]_i_1__9/O net (fo=10, routed) 0.466 4.003 ngFEC/g_pm[11].phase_mon/PS_min SLICE_X138Y298 FDPE r ngFEC/g_pm[11].phase_mon/PS_min_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 8.200 8.200 r BUFGCTRL_X0Y22 BUFG 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.293 9.493 ngFEC/g_pm[11].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X138Y298 FDPE r ngFEC/g_pm[11].phase_mon/PS_min_reg[6]/C clock pessimism 0.173 9.666 clock uncertainty -0.035 9.631 SLICE_X138Y298 FDPE (Setup_fdpe_C_CE) -0.178 9.453 ngFEC/g_pm[11].phase_mon/PS_min_reg[6] ------------------------------------------------------------------- required time 9.453 arrival time -4.003 ------------------------------------------------------------------- slack 5.449 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.083ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/C (rising edge-triggered cell FDRE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/D (rising edge-triggered cell SRL16E clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_7 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_7 rise@0.000ns - txWordclkl12_7 rise@0.000ns) Data Path Delay: 0.195ns (logic 0.100ns (51.316%) route 0.095ns (48.684%)) Logic Levels: 0 Clock Path Skew: 0.010ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.815ns Source Clock Delay (SCD): 0.610ns Clock Pessimism Removal (CPR): 0.195ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 0.000 0.000 r BUFGCTRL_X0Y22 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.610 0.610 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk SLICE_X187Y223 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X187Y223 FDRE (Prop_fdre_C_Q) 0.100 0.710 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/Q net (fo=1, routed) 0.095 0.805 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/dest_out SLICE_X186Y224 SRL16E r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 0.000 0.000 r BUFGCTRL_X0Y22 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.815 0.815 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X186Y224 SRL16E r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK clock pessimism -0.195 0.620 SLICE_X186Y224 SRL16E (Hold_srl16e_CLK_D) 0.102 0.722 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3 ------------------------------------------------------------------- required time -0.722 arrival time 0.805 ------------------------------------------------------------------- slack 0.083 Slack (MET) : 0.098ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]/C (rising edge-triggered cell FDRE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[12]/D (rising edge-triggered cell FDRE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_7 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_7 rise@0.000ns - txWordclkl12_7 rise@0.000ns) Data Path Delay: 0.470ns (logic 0.333ns (70.878%) route 0.137ns (29.122%)) Logic Levels: 5 (CARRY4=4 LUT1=1) Clock Path Skew: 0.301ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.932ns Source Clock Delay (SCD): 0.623ns Clock Pessimism Removal (CPR): 0.008ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 0.000 0.000 r BUFGCTRL_X0Y22 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.623 0.623 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/gt0_txusrclk_in SLICE_X181Y247 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X181Y247 FDRE (Prop_fdre_C_Q) 0.100 0.723 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]/Q net (fo=2, routed) 0.136 0.859 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0] SLICE_X181Y247 LUT1 (Prop_lut1_I0_O) 0.028 0.887 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_5/O net (fo=1, routed) 0.000 0.887 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_5_n_0 SLICE_X181Y247 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.114 1.001 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]_i_3/CO[3] net (fo=1, routed) 0.000 1.001 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]_i_3_n_0 SLICE_X181Y248 CARRY4 (Prop_carry4_CI_CO[3]) 0.025 1.026 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[4]_i_1/CO[3] net (fo=1, routed) 0.000 1.026 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[4]_i_1_n_0 SLICE_X181Y249 CARRY4 (Prop_carry4_CI_CO[3]) 0.025 1.051 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[8]_i_1/CO[3] net (fo=1, routed) 0.001 1.052 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[8]_i_1_n_0 SLICE_X181Y250 CARRY4 (Prop_carry4_CI_O[0]) 0.041 1.093 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[12]_i_1/O[0] net (fo=1, routed) 0.000 1.093 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[12]_i_1_n_7 SLICE_X181Y250 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[12]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 0.000 0.000 r BUFGCTRL_X0Y22 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.932 0.932 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/gt0_txusrclk_in SLICE_X181Y250 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[12]/C clock pessimism -0.008 0.924 SLICE_X181Y250 FDRE (Hold_fdre_C_D) 0.071 0.995 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[12] ------------------------------------------------------------------- required time -0.995 arrival time 1.093 ------------------------------------------------------------------- slack 0.098 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D (rising edge-triggered cell FDRE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_7 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_7 rise@0.000ns - txWordclkl12_7 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.897ns Source Clock Delay (SCD): 0.669ns Clock Pessimism Removal (CPR): 0.228ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 0.000 0.000 r BUFGCTRL_X0Y22 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.669 0.669 ngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/dest_clk SLICE_X151Y298 FDRE r ngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X151Y298 FDRE (Prop_fdre_C_Q) 0.100 0.769 r ngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/Q net (fo=1, routed) 0.055 0.824 ngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff[0] SLICE_X151Y298 FDRE r ngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 0.000 0.000 r BUFGCTRL_X0Y22 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.897 0.897 ngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/dest_clk SLICE_X151Y298 FDRE r ngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/C clock pessimism -0.228 0.669 SLICE_X151Y298 FDRE (Hold_fdre_C_D) 0.047 0.716 ngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1] ------------------------------------------------------------------- required time -0.716 arrival time 0.824 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/g_pm[11].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[11].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/D (rising edge-triggered cell FDRE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_7 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_7 rise@0.000ns - txWordclkl12_7 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.893ns Source Clock Delay (SCD): 0.666ns Clock Pessimism Removal (CPR): 0.227ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 0.000 0.000 r BUFGCTRL_X0Y22 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.666 0.666 ngFEC/g_pm[11].phase_mon/sample_PS_Sync_inst/dest_clk SLICE_X147Y295 FDRE r ngFEC/g_pm[11].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X147Y295 FDRE (Prop_fdre_C_Q) 0.100 0.766 r ngFEC/g_pm[11].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/Q net (fo=1, routed) 0.055 0.821 ngFEC/g_pm[11].phase_mon/sample_PS_Sync_inst/syncstages_ff[0] SLICE_X147Y295 FDRE r ngFEC/g_pm[11].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 0.000 0.000 r BUFGCTRL_X0Y22 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.893 0.893 ngFEC/g_pm[11].phase_mon/sample_PS_Sync_inst/dest_clk SLICE_X147Y295 FDRE r ngFEC/g_pm[11].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/C clock pessimism -0.227 0.666 SLICE_X147Y295 FDRE (Hold_fdre_C_D) 0.047 0.713 ngFEC/g_pm[11].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1] ------------------------------------------------------------------- required time -0.713 arrival time 0.821 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D (rising edge-triggered cell FDRE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_7 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_7 rise@0.000ns - txWordclkl12_7 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.816ns Source Clock Delay (SCD): 0.610ns Clock Pessimism Removal (CPR): 0.206ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 0.000 0.000 r BUFGCTRL_X0Y22 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.610 0.610 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk SLICE_X187Y223 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X187Y223 FDRE (Prop_fdre_C_Q) 0.100 0.710 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/Q net (fo=1, routed) 0.055 0.765 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff[0] SLICE_X187Y223 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 0.000 0.000 r BUFGCTRL_X0Y22 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.816 0.816 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk SLICE_X187Y223 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/C clock pessimism -0.206 0.610 SLICE_X187Y223 FDRE (Hold_fdre_C_D) 0.047 0.657 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1] ------------------------------------------------------------------- required time -0.657 arrival time 0.765 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_7 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_7 rise@0.000ns - txWordclkl12_7 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.831ns Source Clock Delay (SCD): 0.623ns Clock Pessimism Removal (CPR): 0.208ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 0.000 0.000 r BUFGCTRL_X0Y22 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.623 0.623 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in SLICE_X179Y249 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X179Y249 FDRE (Prop_fdre_C_Q) 0.100 0.723 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/Q net (fo=1, routed) 0.055 0.778 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync1 SLICE_X179Y249 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 0.000 0.000 r BUFGCTRL_X0Y22 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.831 0.831 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in SLICE_X179Y249 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/C clock pessimism -0.208 0.623 SLICE_X179Y249 FDRE (Hold_fdre_C_D) 0.047 0.670 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.670 arrival time 0.778 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.109ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]/C (rising edge-triggered cell FDRE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[14]/D (rising edge-triggered cell FDRE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_7 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_7 rise@0.000ns - txWordclkl12_7 rise@0.000ns) Data Path Delay: 0.481ns (logic 0.344ns (71.544%) route 0.137ns (28.456%)) Logic Levels: 5 (CARRY4=4 LUT1=1) Clock Path Skew: 0.301ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.932ns Source Clock Delay (SCD): 0.623ns Clock Pessimism Removal (CPR): 0.008ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 0.000 0.000 r BUFGCTRL_X0Y22 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.623 0.623 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/gt0_txusrclk_in SLICE_X181Y247 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X181Y247 FDRE (Prop_fdre_C_Q) 0.100 0.723 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]/Q net (fo=2, routed) 0.136 0.859 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0] SLICE_X181Y247 LUT1 (Prop_lut1_I0_O) 0.028 0.887 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_5/O net (fo=1, routed) 0.000 0.887 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_5_n_0 SLICE_X181Y247 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.114 1.001 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]_i_3/CO[3] net (fo=1, routed) 0.000 1.001 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]_i_3_n_0 SLICE_X181Y248 CARRY4 (Prop_carry4_CI_CO[3]) 0.025 1.026 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[4]_i_1/CO[3] net (fo=1, routed) 0.000 1.026 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[4]_i_1_n_0 SLICE_X181Y249 CARRY4 (Prop_carry4_CI_CO[3]) 0.025 1.051 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[8]_i_1/CO[3] net (fo=1, routed) 0.001 1.052 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[8]_i_1_n_0 SLICE_X181Y250 CARRY4 (Prop_carry4_CI_O[2]) 0.052 1.104 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[12]_i_1/O[2] net (fo=1, routed) 0.000 1.104 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[12]_i_1_n_5 SLICE_X181Y250 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[14]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 0.000 0.000 r BUFGCTRL_X0Y22 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.932 0.932 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/gt0_txusrclk_in SLICE_X181Y250 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[14]/C clock pessimism -0.008 0.924 SLICE_X181Y250 FDRE (Hold_fdre_C_D) 0.071 0.995 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[14] ------------------------------------------------------------------- required time -0.995 arrival time 1.104 ------------------------------------------------------------------- slack 0.109 Slack (MET) : 0.113ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_7 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_7 rise@0.000ns - txWordclkl12_7 rise@0.000ns) Data Path Delay: 0.160ns (logic 0.100ns (62.442%) route 0.060ns (37.558%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.832ns Source Clock Delay (SCD): 0.624ns Clock Pessimism Removal (CPR): 0.208ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 0.000 0.000 r BUFGCTRL_X0Y22 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.624 0.624 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in SLICE_X188Y247 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X188Y247 FDRE (Prop_fdre_C_Q) 0.100 0.724 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q net (fo=1, routed) 0.060 0.784 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync1 SLICE_X188Y247 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 0.000 0.000 r BUFGCTRL_X0Y22 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.832 0.832 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in SLICE_X188Y247 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C clock pessimism -0.208 0.624 SLICE_X188Y247 FDRE (Hold_fdre_C_D) 0.047 0.671 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.671 arrival time 0.784 ------------------------------------------------------------------- slack 0.113 Slack (MET) : 0.117ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]/C (rising edge-triggered cell FDRE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[13]/D (rising edge-triggered cell FDRE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_7 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_7 rise@0.000ns - txWordclkl12_7 rise@0.000ns) Data Path Delay: 0.489ns (logic 0.352ns (72.010%) route 0.137ns (27.990%)) Logic Levels: 5 (CARRY4=4 LUT1=1) Clock Path Skew: 0.301ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.932ns Source Clock Delay (SCD): 0.623ns Clock Pessimism Removal (CPR): 0.008ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 0.000 0.000 r BUFGCTRL_X0Y22 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.623 0.623 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/gt0_txusrclk_in SLICE_X181Y247 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X181Y247 FDRE (Prop_fdre_C_Q) 0.100 0.723 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]/Q net (fo=2, routed) 0.136 0.859 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0] SLICE_X181Y247 LUT1 (Prop_lut1_I0_O) 0.028 0.887 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_5/O net (fo=1, routed) 0.000 0.887 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_5_n_0 SLICE_X181Y247 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.114 1.001 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]_i_3/CO[3] net (fo=1, routed) 0.000 1.001 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]_i_3_n_0 SLICE_X181Y248 CARRY4 (Prop_carry4_CI_CO[3]) 0.025 1.026 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[4]_i_1/CO[3] net (fo=1, routed) 0.000 1.026 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[4]_i_1_n_0 SLICE_X181Y249 CARRY4 (Prop_carry4_CI_CO[3]) 0.025 1.051 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[8]_i_1/CO[3] net (fo=1, routed) 0.001 1.052 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[8]_i_1_n_0 SLICE_X181Y250 CARRY4 (Prop_carry4_CI_O[1]) 0.060 1.112 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[12]_i_1/O[1] net (fo=1, routed) 0.000 1.112 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[12]_i_1_n_6 SLICE_X181Y250 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[13]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 0.000 0.000 r BUFGCTRL_X0Y22 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.932 0.932 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/gt0_txusrclk_in SLICE_X181Y250 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[13]/C clock pessimism -0.008 0.924 SLICE_X181Y250 FDRE (Hold_fdre_C_D) 0.071 0.995 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[13] ------------------------------------------------------------------- required time -0.995 arrival time 1.112 ------------------------------------------------------------------- slack 0.117 Slack (MET) : 0.122ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]/C (rising edge-triggered cell FDRE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]/D (rising edge-triggered cell FDRE clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_7 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_7 rise@0.000ns - txWordclkl12_7 rise@0.000ns) Data Path Delay: 0.494ns (logic 0.357ns (72.293%) route 0.137ns (27.707%)) Logic Levels: 5 (CARRY4=4 LUT1=1) Clock Path Skew: 0.301ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.932ns Source Clock Delay (SCD): 0.623ns Clock Pessimism Removal (CPR): 0.008ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 0.000 0.000 r BUFGCTRL_X0Y22 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.623 0.623 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/gt0_txusrclk_in SLICE_X181Y247 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X181Y247 FDRE (Prop_fdre_C_Q) 0.100 0.723 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]/Q net (fo=2, routed) 0.136 0.859 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0] SLICE_X181Y247 LUT1 (Prop_lut1_I0_O) 0.028 0.887 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_5/O net (fo=1, routed) 0.000 0.887 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_5_n_0 SLICE_X181Y247 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.114 1.001 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]_i_3/CO[3] net (fo=1, routed) 0.000 1.001 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[0]_i_3_n_0 SLICE_X181Y248 CARRY4 (Prop_carry4_CI_CO[3]) 0.025 1.026 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[4]_i_1/CO[3] net (fo=1, routed) 0.000 1.026 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[4]_i_1_n_0 SLICE_X181Y249 CARRY4 (Prop_carry4_CI_CO[3]) 0.025 1.051 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[8]_i_1/CO[3] net (fo=1, routed) 0.001 1.052 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[8]_i_1_n_0 SLICE_X181Y250 CARRY4 (Prop_carry4_CI_O[3]) 0.065 1.117 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[12]_i_1/O[3] net (fo=1, routed) 0.000 1.117 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[12]_i_1_n_4 SLICE_X181Y250 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 0.000 0.000 r BUFGCTRL_X0Y22 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.932 0.932 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/gt0_txusrclk_in SLICE_X181Y250 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]/C clock pessimism -0.008 0.924 SLICE_X181Y250 FDRE (Hold_fdre_C_D) 0.071 0.995 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15] ------------------------------------------------------------------- required time -0.995 arrival time 1.117 ------------------------------------------------------------------- slack 0.122 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: txWordclkl12_7 Waveform(ns): { 0.000 4.100 } Period(ns): 8.200 Sources: { ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/TXUSRCLK n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y20 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK Min Period n/a GTXE2_CHANNEL/TXUSRCLK2 n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y20 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X156Y299 ngFEC/g_pm[11].phase_mon/PS_max_reg[5]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X156Y299 ngFEC/g_pm[11].phase_mon/PS_max_reg[7]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X156Y299 ngFEC/g_pm[11].phase_mon/PS_max_reg[8]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X156Y299 ngFEC/g_pm[11].phase_mon/PS_max_reg[9]/C Min Period n/a FDPE/C n/a 0.750 8.200 7.450 SLICE_X138Y298 ngFEC/g_pm[11].phase_mon/PS_min_reg[5]/C Min Period n/a FDPE/C n/a 0.750 8.200 7.450 SLICE_X138Y298 ngFEC/g_pm[11].phase_mon/PS_min_reg[6]/C Min Period n/a FDPE/C n/a 0.750 8.200 7.450 SLICE_X138Y298 ngFEC/g_pm[11].phase_mon/PS_min_reg[7]/C Min Period n/a FDPE/C n/a 0.750 8.200 7.450 SLICE_X138Y298 ngFEC/g_pm[11].phase_mon/PS_min_reg[9]/C Low Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X186Y224 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK Low Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X186Y224 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X156Y299 ngFEC/g_pm[11].phase_mon/PS_max_reg[5]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X156Y299 ngFEC/g_pm[11].phase_mon/PS_max_reg[7]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X156Y299 ngFEC/g_pm[11].phase_mon/PS_max_reg[8]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X156Y299 ngFEC/g_pm[11].phase_mon/PS_max_reg[9]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X146Y296 ngFEC/g_pm[11].phase_mon/en_chk_reg[2]/C Low Pulse Width Fast FDRE/C n/a 0.400 4.100 3.700 SLICE_X151Y298 ngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/C Low Pulse Width Fast FDRE/C n/a 0.400 4.100 3.700 SLICE_X151Y298 ngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[2]/C Low Pulse Width Fast FDPE/C n/a 0.400 4.100 3.700 SLICE_X148Y299 ngFEC/g_pm[11].phase_mon/inh_cntr_reg[2]/C High Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X186Y224 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X186Y224 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X186Y224 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X186Y225 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[5]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X184Y226 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[10]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X182Y226 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[11]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X182Y226 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[13]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X179Y227 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[14]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X179Y227 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[15]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X184Y226 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[16]/C --------------------------------------------------------------------------------------------------- From Clock: txWordclkl12_8 To Clock: txWordclkl12_8 Setup : 0 Failing Endpoints, Worst Slack 4.422ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.051ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.458ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.422ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[3]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[3] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_8 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_8 rise@8.200ns - txWordclkl12_8 rise@0.000ns) Data Path Delay: 3.468ns (logic 0.223ns (6.430%) route 3.245ns (93.570%)) Logic Levels: 0 Clock Path Skew: 0.144ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.527ns = ( 9.727 - 8.200 ) Source Clock Delay (SCD): 1.383ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.383 1.383 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X185Y199 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X185Y199 FDCE (Prop_fdce_C_Q) 0.223 1.606 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[3]/Q net (fo=1, routed) 3.245 4.851 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[3] GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[3] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 8.200 8.200 r BUFGCTRL_X0Y23 BUFG 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.527 9.727 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.000 9.727 clock uncertainty -0.035 9.692 GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[3]) -0.419 9.273 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.273 arrival time -4.851 ------------------------------------------------------------------- slack 4.422 Slack (MET) : 4.540ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[8]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPVAL[0] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_8 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_8 rise@8.200ns - txWordclkl12_8 rise@0.000ns) Data Path Delay: 3.351ns (logic 0.259ns (7.729%) route 3.092ns (92.271%)) Logic Levels: 0 Clock Path Skew: 0.145ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.527ns = ( 9.727 - 8.200 ) Source Clock Delay (SCD): 1.382ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.382 1.382 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X180Y196 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X180Y196 FDCE (Prop_fdce_C_Q) 0.259 1.641 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[8]/Q net (fo=1, routed) 3.092 4.733 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[8] GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPVAL[0] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 8.200 8.200 r BUFGCTRL_X0Y23 BUFG 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.527 9.727 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.000 9.727 clock uncertainty -0.035 9.692 GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXCHARDISPVAL[0]) -0.419 9.273 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.273 arrival time -4.733 ------------------------------------------------------------------- slack 4.540 Slack (MET) : 4.548ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPVAL[1] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_8 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_8 rise@8.200ns - txWordclkl12_8 rise@0.000ns) Data Path Delay: 3.343ns (logic 0.223ns (6.670%) route 3.120ns (93.330%)) Logic Levels: 0 Clock Path Skew: 0.145ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.527ns = ( 9.727 - 8.200 ) Source Clock Delay (SCD): 1.382ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.382 1.382 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X181Y196 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X181Y196 FDCE (Prop_fdce_C_Q) 0.223 1.605 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/Q net (fo=1, routed) 3.120 4.725 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[18] GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPVAL[1] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 8.200 8.200 r BUFGCTRL_X0Y23 BUFG 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.527 9.727 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.000 9.727 clock uncertainty -0.035 9.692 GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXCHARDISPVAL[1]) -0.419 9.273 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.273 arrival time -4.725 ------------------------------------------------------------------- slack 4.548 Slack (MET) : 4.573ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[17]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[15] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_8 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_8 rise@8.200ns - txWordclkl12_8 rise@0.000ns) Data Path Delay: 3.318ns (logic 0.223ns (6.721%) route 3.095ns (93.279%)) Logic Levels: 0 Clock Path Skew: 0.145ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.527ns = ( 9.727 - 8.200 ) Source Clock Delay (SCD): 1.382ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.382 1.382 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X181Y196 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X181Y196 FDCE (Prop_fdce_C_Q) 0.223 1.605 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[17]/Q net (fo=1, routed) 3.095 4.700 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[17] GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[15] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 8.200 8.200 r BUFGCTRL_X0Y23 BUFG 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.527 9.727 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.000 9.727 clock uncertainty -0.035 9.692 GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[15]) -0.419 9.273 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.273 arrival time -4.700 ------------------------------------------------------------------- slack 4.573 Slack (MET) : 4.580ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[2]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[2] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_8 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_8 rise@8.200ns - txWordclkl12_8 rise@0.000ns) Data Path Delay: 3.310ns (logic 0.223ns (6.737%) route 3.087ns (93.263%)) Logic Levels: 0 Clock Path Skew: 0.144ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.527ns = ( 9.727 - 8.200 ) Source Clock Delay (SCD): 1.383ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.383 1.383 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X185Y199 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X185Y199 FDCE (Prop_fdce_C_Q) 0.223 1.606 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[2]/Q net (fo=1, routed) 3.087 4.693 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[2] GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[2] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 8.200 8.200 r BUFGCTRL_X0Y23 BUFG 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.527 9.727 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.000 9.727 clock uncertainty -0.035 9.692 GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[2]) -0.419 9.273 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.273 arrival time -4.693 ------------------------------------------------------------------- slack 4.580 Slack (MET) : 4.611ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[6] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_8 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_8 rise@8.200ns - txWordclkl12_8 rise@0.000ns) Data Path Delay: 3.306ns (logic 0.259ns (7.834%) route 3.047ns (92.166%)) Logic Levels: 0 Clock Path Skew: 0.171ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.527ns = ( 9.727 - 8.200 ) Source Clock Delay (SCD): 1.369ns Clock Pessimism Removal (CPR): 0.013ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.369 1.369 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X180Y200 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X180Y200 FDCE (Prop_fdce_C_Q) 0.259 1.628 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/Q net (fo=1, routed) 3.047 4.675 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[6] GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[6] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 8.200 8.200 r BUFGCTRL_X0Y23 BUFG 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.527 9.727 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.013 9.740 clock uncertainty -0.035 9.705 GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[6]) -0.419 9.286 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.286 arrival time -4.675 ------------------------------------------------------------------- slack 4.611 Slack (MET) : 4.660ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[9]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPMODE[0] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_8 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_8 rise@8.200ns - txWordclkl12_8 rise@0.000ns) Data Path Delay: 3.231ns (logic 0.259ns (8.016%) route 2.972ns (91.984%)) Logic Levels: 0 Clock Path Skew: 0.145ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.527ns = ( 9.727 - 8.200 ) Source Clock Delay (SCD): 1.382ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.382 1.382 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X182Y199 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X182Y199 FDCE (Prop_fdce_C_Q) 0.259 1.641 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[9]/Q net (fo=1, routed) 2.972 4.613 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[9] GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXCHARDISPMODE[0] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 8.200 8.200 r BUFGCTRL_X0Y23 BUFG 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.527 9.727 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.000 9.727 clock uncertainty -0.035 9.692 GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXCHARDISPMODE[0]) -0.419 9.273 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.273 arrival time -4.613 ------------------------------------------------------------------- slack 4.660 Slack (MET) : 4.728ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[5] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_8 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_8 rise@8.200ns - txWordclkl12_8 rise@0.000ns) Data Path Delay: 3.189ns (logic 0.259ns (8.121%) route 2.930ns (91.879%)) Logic Levels: 0 Clock Path Skew: 0.171ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.527ns = ( 9.727 - 8.200 ) Source Clock Delay (SCD): 1.369ns Clock Pessimism Removal (CPR): 0.013ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.369 1.369 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X180Y200 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X180Y200 FDCE (Prop_fdce_C_Q) 0.259 1.628 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/Q net (fo=1, routed) 2.930 4.558 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[5] GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[5] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 8.200 8.200 r BUFGCTRL_X0Y23 BUFG 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.527 9.727 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.013 9.740 clock uncertainty -0.035 9.705 GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[5]) -0.419 9.286 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.286 arrival time -4.558 ------------------------------------------------------------------- slack 4.728 Slack (MET) : 4.757ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[15]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[13] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_8 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_8 rise@8.200ns - txWordclkl12_8 rise@0.000ns) Data Path Delay: 3.134ns (logic 0.259ns (8.264%) route 2.875ns (91.736%)) Logic Levels: 0 Clock Path Skew: 0.145ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.527ns = ( 9.727 - 8.200 ) Source Clock Delay (SCD): 1.382ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.382 1.382 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X182Y198 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X182Y198 FDCE (Prop_fdce_C_Q) 0.259 1.641 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[15]/Q net (fo=1, routed) 2.875 4.516 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[15] GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[13] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 8.200 8.200 r BUFGCTRL_X0Y23 BUFG 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.527 9.727 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.000 9.727 clock uncertainty -0.035 9.692 GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[13]) -0.419 9.273 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.273 arrival time -4.516 ------------------------------------------------------------------- slack 4.757 Slack (MET) : 4.769ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[0] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_8 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_8 rise@8.200ns - txWordclkl12_8 rise@0.000ns) Data Path Delay: 3.121ns (logic 0.223ns (7.145%) route 2.898ns (92.855%)) Logic Levels: 0 Clock Path Skew: 0.144ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.527ns = ( 9.727 - 8.200 ) Source Clock Delay (SCD): 1.383ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.383 1.383 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X185Y199 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X185Y199 FDCE (Prop_fdce_C_Q) 0.223 1.606 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/Q net (fo=1, routed) 2.898 4.504 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[0] GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[0] ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 8.200 8.200 r BUFGCTRL_X0Y23 BUFG 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.527 9.727 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.000 9.727 clock uncertainty -0.035 9.692 GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[0]) -0.419 9.273 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.273 arrival time -4.504 ------------------------------------------------------------------- slack 4.769 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.051ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[112]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[12]/D (rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_8 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_8 rise@0.000ns - txWordclkl12_8 rise@0.000ns) Data Path Delay: 0.331ns (logic 0.128ns (38.650%) route 0.203ns (61.350%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.193ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.832ns Source Clock Delay (SCD): 0.639ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.639 0.639 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X177Y196 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[112]/C ------------------------------------------------------------------- ------------------- SLICE_X177Y196 FDCE (Prop_fdce_C_Q) 0.100 0.739 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[112]/Q net (fo=1, routed) 0.203 0.942 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/data5[12] SLICE_X182Y200 LUT6 (Prop_lut6_I2_O) 0.028 0.970 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[12]_i_1__6/O net (fo=1, routed) 0.000 0.970 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[12]_i_1__6_n_0 SLICE_X182Y200 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[12]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.832 0.832 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X182Y200 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[12]/C clock pessimism 0.000 0.832 SLICE_X182Y200 FDCE (Hold_fdce_C_D) 0.087 0.919 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[12] ------------------------------------------------------------------- required time -0.919 arrival time 0.970 ------------------------------------------------------------------- slack 0.051 Slack (MET) : 0.056ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[106]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/D (rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_8 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_8 rise@0.000ns - txWordclkl12_8 rise@0.000ns) Data Path Delay: 0.334ns (logic 0.146ns (43.675%) route 0.188ns (56.325%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.191ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.832ns Source Clock Delay (SCD): 0.641ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.641 0.641 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X178Y199 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[106]/C ------------------------------------------------------------------- ------------------- SLICE_X178Y199 FDCE (Prop_fdce_C_Q) 0.118 0.759 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[106]/Q net (fo=1, routed) 0.188 0.947 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/data5[6] SLICE_X180Y200 LUT6 (Prop_lut6_I2_O) 0.028 0.975 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[6]_i_1__6/O net (fo=1, routed) 0.000 0.975 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[6]_i_1__6_n_0 SLICE_X180Y200 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.832 0.832 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X180Y200 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/C clock pessimism 0.000 0.832 SLICE_X180Y200 FDCE (Hold_fdce_C_D) 0.087 0.919 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6] ------------------------------------------------------------------- required time -0.919 arrival time 0.975 ------------------------------------------------------------------- slack 0.056 Slack (MET) : 0.058ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[107]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/D (rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_8 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_8 rise@0.000ns - txWordclkl12_8 rise@0.000ns) Data Path Delay: 0.337ns (logic 0.128ns (37.996%) route 0.209ns (62.004%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.192ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.832ns Source Clock Delay (SCD): 0.640ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.640 0.640 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X177Y199 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[107]/C ------------------------------------------------------------------- ------------------- SLICE_X177Y199 FDCE (Prop_fdce_C_Q) 0.100 0.740 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[107]/Q net (fo=1, routed) 0.209 0.949 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/data5[7] SLICE_X180Y200 LUT6 (Prop_lut6_I2_O) 0.028 0.977 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[7]_i_1__6/O net (fo=1, routed) 0.000 0.977 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[7]_i_1__6_n_0 SLICE_X180Y200 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.832 0.832 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X180Y200 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/C clock pessimism 0.000 0.832 SLICE_X180Y200 FDCE (Hold_fdce_C_D) 0.087 0.919 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7] ------------------------------------------------------------------- required time -0.919 arrival time 0.977 ------------------------------------------------------------------- slack 0.058 Slack (MET) : 0.064ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[84]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[4]/D (rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_8 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_8 rise@0.000ns - txWordclkl12_8 rise@0.000ns) Data Path Delay: 0.342ns (logic 0.155ns (45.276%) route 0.187ns (54.724%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.191ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.832ns Source Clock Delay (SCD): 0.641ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.641 0.641 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X181Y198 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[84]/C ------------------------------------------------------------------- ------------------- SLICE_X181Y198 FDCE (Prop_fdce_C_Q) 0.091 0.732 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[84]/Q net (fo=1, routed) 0.187 0.919 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/data4[4] SLICE_X180Y200 LUT6 (Prop_lut6_I0_O) 0.064 0.983 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[4]_i_1__6/O net (fo=1, routed) 0.000 0.983 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[4]_i_1__6_n_0 SLICE_X180Y200 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[4]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.832 0.832 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X180Y200 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[4]/C clock pessimism 0.000 0.832 SLICE_X180Y200 FDCE (Hold_fdce_C_D) 0.087 0.919 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[4] ------------------------------------------------------------------- required time -0.919 arrival time 0.983 ------------------------------------------------------------------- slack 0.064 Slack (MET) : 0.082ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/C (rising edge-triggered cell FDRE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[2]/D (rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_8 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_8 rise@0.000ns - txWordclkl12_8 rise@0.000ns) Data Path Delay: 0.392ns (logic 0.171ns (43.582%) route 0.221ns (56.418%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.223ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.845ns Source Clock Delay (SCD): 0.622ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.622 0.622 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X182Y203 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/C ------------------------------------------------------------------- ------------------- SLICE_X182Y203 FDRE (Prop_fdre_C_Q) 0.107 0.729 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/Q net (fo=5, routed) 0.221 0.950 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync[4] SLICE_X182Y199 LUT6 (Prop_lut6_I3_O) 0.064 1.014 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.address[2]_i_1__6/O net (fo=1, routed) 0.000 1.014 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.address[2]_i_1__6_n_0 SLICE_X182Y199 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[2]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.845 0.845 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X182Y199 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[2]/C clock pessimism 0.000 0.845 SLICE_X182Y199 FDCE (Hold_fdce_C_D) 0.087 0.932 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[2] ------------------------------------------------------------------- required time -0.932 arrival time 1.014 ------------------------------------------------------------------- slack 0.082 Slack (MET) : 0.088ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[85]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/D (rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_8 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_8 rise@0.000ns - txWordclkl12_8 rise@0.000ns) Data Path Delay: 0.366ns (logic 0.155ns (42.379%) route 0.211ns (57.621%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.191ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.832ns Source Clock Delay (SCD): 0.641ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.641 0.641 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X181Y199 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[85]/C ------------------------------------------------------------------- ------------------- SLICE_X181Y199 FDCE (Prop_fdce_C_Q) 0.091 0.732 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[85]/Q net (fo=1, routed) 0.211 0.943 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/data4[5] SLICE_X180Y200 LUT6 (Prop_lut6_I0_O) 0.064 1.007 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[5]_i_1__6/O net (fo=1, routed) 0.000 1.007 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[5]_i_1__6_n_0 SLICE_X180Y200 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.832 0.832 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X180Y200 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5]/C clock pessimism 0.000 0.832 SLICE_X180Y200 FDCE (Hold_fdce_C_D) 0.087 0.919 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[5] ------------------------------------------------------------------- required time -0.919 arrival time 1.007 ------------------------------------------------------------------- slack 0.088 Slack (MET) : 0.089ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[81]/C (rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/D (rising edge-triggered cell FDCE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_8 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_8 rise@0.000ns - txWordclkl12_8 rise@0.000ns) Data Path Delay: 0.371ns (logic 0.128ns (34.530%) route 0.243ns (65.470%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.222ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.845ns Source Clock Delay (SCD): 0.623ns Clock Pessimism Removal (CPR): -0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.623 0.623 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X179Y200 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[81]/C ------------------------------------------------------------------- ------------------- SLICE_X179Y200 FDCE (Prop_fdce_C_Q) 0.100 0.723 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[81]/Q net (fo=1, routed) 0.243 0.966 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/data4[1] SLICE_X185Y199 LUT6 (Prop_lut6_I0_O) 0.028 0.994 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[1]_i_1__6/O net (fo=1, routed) 0.000 0.994 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[1]_i_1__6_n_0 SLICE_X185Y199 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.845 0.845 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X185Y199 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/C clock pessimism 0.000 0.845 SLICE_X185Y199 FDCE (Hold_fdce_C_D) 0.060 0.905 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1] ------------------------------------------------------------------- required time -0.905 arrival time 0.994 ------------------------------------------------------------------- slack 0.089 Slack (MET) : 0.094ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/C (rising edge-triggered cell FDRE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/D (rising edge-triggered cell SRL16E clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_8 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_8 rise@0.000ns - txWordclkl12_8 rise@0.000ns) Data Path Delay: 0.207ns (logic 0.100ns (48.254%) route 0.107ns (51.746%)) Logic Levels: 0 Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.831ns Source Clock Delay (SCD): 0.622ns Clock Pessimism Removal (CPR): 0.198ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.622 0.622 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk SLICE_X183Y203 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X183Y203 FDRE (Prop_fdre_C_Q) 0.100 0.722 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/Q net (fo=1, routed) 0.107 0.829 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/dest_out SLICE_X182Y203 SRL16E r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.831 0.831 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X182Y203 SRL16E r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK clock pessimism -0.198 0.633 SLICE_X182Y203 SRL16E (Hold_srl16e_CLK_D) 0.102 0.735 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3 ------------------------------------------------------------------- required time -0.735 arrival time 0.829 ------------------------------------------------------------------- slack 0.094 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/g_pm[12].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[12].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/D (rising edge-triggered cell FDRE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_8 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_8 rise@0.000ns - txWordclkl12_8 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.890ns Source Clock Delay (SCD): 0.662ns Clock Pessimism Removal (CPR): 0.228ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.662 0.662 ngFEC/g_pm[12].phase_mon/sample_PS_Sync_inst/dest_clk SLICE_X143Y296 FDRE r ngFEC/g_pm[12].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X143Y296 FDRE (Prop_fdre_C_Q) 0.100 0.762 r ngFEC/g_pm[12].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/Q net (fo=1, routed) 0.055 0.817 ngFEC/g_pm[12].phase_mon/sample_PS_Sync_inst/syncstages_ff[0] SLICE_X143Y296 FDRE r ngFEC/g_pm[12].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.890 0.890 ngFEC/g_pm[12].phase_mon/sample_PS_Sync_inst/dest_clk SLICE_X143Y296 FDRE r ngFEC/g_pm[12].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/C clock pessimism -0.228 0.662 SLICE_X143Y296 FDRE (Hold_fdre_C_D) 0.047 0.709 ngFEC/g_pm[12].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1] ------------------------------------------------------------------- required time -0.709 arrival time 0.817 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D (rising edge-triggered cell FDRE clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl12_8 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_8 rise@0.000ns - txWordclkl12_8 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.831ns Source Clock Delay (SCD): 0.622ns Clock Pessimism Removal (CPR): 0.209ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.622 0.622 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk SLICE_X183Y203 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X183Y203 FDRE (Prop_fdre_C_Q) 0.100 0.722 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/Q net (fo=1, routed) 0.055 0.777 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff[0] SLICE_X183Y203 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.831 0.831 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk SLICE_X183Y203 FDRE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/C clock pessimism -0.209 0.622 SLICE_X183Y203 FDRE (Hold_fdre_C_D) 0.047 0.669 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1] ------------------------------------------------------------------- required time -0.669 arrival time 0.777 ------------------------------------------------------------------- slack 0.108 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: txWordclkl12_8 Waveform(ns): { 0.000 4.100 } Period(ns): 8.200 Sources: { ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/TXUSRCLK n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y23 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK Min Period n/a GTXE2_CHANNEL/TXUSRCLK2 n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y23 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X153Y299 ngFEC/g_pm[12].phase_mon/PS_max_reg[4]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X153Y299 ngFEC/g_pm[12].phase_mon/PS_max_reg[5]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X153Y299 ngFEC/g_pm[12].phase_mon/PS_max_reg[8]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X153Y299 ngFEC/g_pm[12].phase_mon/PS_max_reg[9]/C Min Period n/a FDPE/C n/a 0.750 8.200 7.450 SLICE_X137Y299 ngFEC/g_pm[12].phase_mon/PS_min_reg[5]/C Min Period n/a FDPE/C n/a 0.750 8.200 7.450 SLICE_X137Y299 ngFEC/g_pm[12].phase_mon/PS_min_reg[6]/C Min Period n/a FDPE/C n/a 0.750 8.200 7.450 SLICE_X137Y299 ngFEC/g_pm[12].phase_mon/PS_min_reg[7]/C Min Period n/a FDPE/C n/a 0.750 8.200 7.450 SLICE_X137Y299 ngFEC/g_pm[12].phase_mon/PS_min_reg[9]/C Low Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X182Y203 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK Low Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X182Y203 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X153Y299 ngFEC/g_pm[12].phase_mon/PS_max_reg[4]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X153Y299 ngFEC/g_pm[12].phase_mon/PS_max_reg[4]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X153Y299 ngFEC/g_pm[12].phase_mon/PS_max_reg[5]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X153Y299 ngFEC/g_pm[12].phase_mon/PS_max_reg[5]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X153Y299 ngFEC/g_pm[12].phase_mon/PS_max_reg[8]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X153Y299 ngFEC/g_pm[12].phase_mon/PS_max_reg[8]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X153Y299 ngFEC/g_pm[12].phase_mon/PS_max_reg[9]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X153Y299 ngFEC/g_pm[12].phase_mon/PS_max_reg[9]/C High Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X182Y203 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X182Y203 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X182Y197 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[5]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X180Y196 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[10]/C High Pulse Width Fast FDCE/C n/a 0.350 4.100 3.750 SLICE_X182Y200 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[12]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X182Y198 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[13]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X182Y199 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[14]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X182Y198 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[15]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X181Y196 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[16]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X181Y196 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[17]/C --------------------------------------------------------------------------------------------------- From Clock: txWordclkl8_1 To Clock: txWordclkl8_1 Setup : 0 Failing Endpoints, Worst Slack 5.317ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.108ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.458ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.317ns (required time - arrival time) Source: ngFEC/g_pm[5].phase_mon/PS_min_reg[5]/C (rising edge-triggered cell FDPE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[5].phase_mon/PS_min_reg[7]/CE (rising edge-triggered cell FDPE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_1 rise@8.200ns - txWordclkl8_1 rise@0.000ns) Data Path Delay: 2.623ns (logic 0.746ns (28.441%) route 1.877ns (71.559%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: -0.047ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.418ns = ( 9.618 - 8.200 ) Source Clock Delay (SCD): 1.618ns Clock Pessimism Removal (CPR): 0.153ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y3 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.618 1.618 ngFEC/g_pm[5].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X132Y313 FDPE r ngFEC/g_pm[5].phase_mon/PS_min_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X132Y313 FDPE (Prop_fdpe_C_Q) 0.259 1.877 r ngFEC/g_pm[5].phase_mon/PS_min_reg[5]/Q net (fo=3, routed) 0.443 2.320 ngFEC/g_pm[5].phase_mon/PS_min_reg_n_0_[5] SLICE_X132Y312 LUT4 (Prop_lut4_I0_O) 0.043 2.363 r ngFEC/g_pm[5].phase_mon/PS_min[9]_i_11__3/O net (fo=1, routed) 0.000 2.363 ngFEC/g_pm[5].phase_mon/PS_min[9]_i_11__3_n_0 SLICE_X132Y312 CARRY4 (Prop_carry4_S[2]_CO[3]) 0.183 2.546 r ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_3__3/CO[3] net (fo=1, routed) 0.000 2.546 ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_3__3_n_0 SLICE_X132Y313 CARRY4 (Prop_carry4_CI_CO[0]) 0.133 2.679 r ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_2__3/CO[0] net (fo=1, routed) 0.575 3.254 ngFEC/g_pm[5].phase_mon/ltOp SLICE_X148Y312 LUT5 (Prop_lut5_I2_O) 0.128 3.382 r ngFEC/g_pm[5].phase_mon/PS_min[9]_i_1__3/O net (fo=10, routed) 0.859 4.241 ngFEC/g_pm[5].phase_mon/PS_min SLICE_X134Y313 FDPE r ngFEC/g_pm[5].phase_mon/PS_min_reg[7]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 8.200 8.200 r BUFGCTRL_X0Y3 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.418 9.618 ngFEC/g_pm[5].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X134Y313 FDPE r ngFEC/g_pm[5].phase_mon/PS_min_reg[7]/C clock pessimism 0.153 9.771 clock uncertainty -0.035 9.736 SLICE_X134Y313 FDPE (Setup_fdpe_C_CE) -0.178 9.558 ngFEC/g_pm[5].phase_mon/PS_min_reg[7] ------------------------------------------------------------------- required time 9.558 arrival time -4.241 ------------------------------------------------------------------- slack 5.317 Slack (MET) : 5.317ns (required time - arrival time) Source: ngFEC/g_pm[5].phase_mon/PS_min_reg[5]/C (rising edge-triggered cell FDPE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[5].phase_mon/PS_min_reg[8]/CE (rising edge-triggered cell FDPE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_1 rise@8.200ns - txWordclkl8_1 rise@0.000ns) Data Path Delay: 2.623ns (logic 0.746ns (28.441%) route 1.877ns (71.559%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: -0.047ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.418ns = ( 9.618 - 8.200 ) Source Clock Delay (SCD): 1.618ns Clock Pessimism Removal (CPR): 0.153ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y3 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.618 1.618 ngFEC/g_pm[5].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X132Y313 FDPE r ngFEC/g_pm[5].phase_mon/PS_min_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X132Y313 FDPE (Prop_fdpe_C_Q) 0.259 1.877 r ngFEC/g_pm[5].phase_mon/PS_min_reg[5]/Q net (fo=3, routed) 0.443 2.320 ngFEC/g_pm[5].phase_mon/PS_min_reg_n_0_[5] SLICE_X132Y312 LUT4 (Prop_lut4_I0_O) 0.043 2.363 r ngFEC/g_pm[5].phase_mon/PS_min[9]_i_11__3/O net (fo=1, routed) 0.000 2.363 ngFEC/g_pm[5].phase_mon/PS_min[9]_i_11__3_n_0 SLICE_X132Y312 CARRY4 (Prop_carry4_S[2]_CO[3]) 0.183 2.546 r ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_3__3/CO[3] net (fo=1, routed) 0.000 2.546 ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_3__3_n_0 SLICE_X132Y313 CARRY4 (Prop_carry4_CI_CO[0]) 0.133 2.679 r ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_2__3/CO[0] net (fo=1, routed) 0.575 3.254 ngFEC/g_pm[5].phase_mon/ltOp SLICE_X148Y312 LUT5 (Prop_lut5_I2_O) 0.128 3.382 r ngFEC/g_pm[5].phase_mon/PS_min[9]_i_1__3/O net (fo=10, routed) 0.859 4.241 ngFEC/g_pm[5].phase_mon/PS_min SLICE_X134Y313 FDPE r ngFEC/g_pm[5].phase_mon/PS_min_reg[8]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 8.200 8.200 r BUFGCTRL_X0Y3 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.418 9.618 ngFEC/g_pm[5].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X134Y313 FDPE r ngFEC/g_pm[5].phase_mon/PS_min_reg[8]/C clock pessimism 0.153 9.771 clock uncertainty -0.035 9.736 SLICE_X134Y313 FDPE (Setup_fdpe_C_CE) -0.178 9.558 ngFEC/g_pm[5].phase_mon/PS_min_reg[8] ------------------------------------------------------------------- required time 9.558 arrival time -4.241 ------------------------------------------------------------------- slack 5.317 Slack (MET) : 5.427ns (required time - arrival time) Source: ngFEC/g_pm[5].phase_mon/PS_min_reg[4]/C (rising edge-triggered cell FDPE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[5].phase_mon/PS_min_reg[1]/CE (rising edge-triggered cell FDPE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_1 rise@8.200ns - txWordclkl8_1 rise@0.000ns) Data Path Delay: 2.534ns (logic 0.710ns (28.014%) route 1.824ns (71.986%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: -0.025ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.417ns = ( 9.617 - 8.200 ) Source Clock Delay (SCD): 1.619ns Clock Pessimism Removal (CPR): 0.177ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y3 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.619 1.619 ngFEC/g_pm[5].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X133Y312 FDPE r ngFEC/g_pm[5].phase_mon/PS_min_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X133Y312 FDPE (Prop_fdpe_C_Q) 0.223 1.842 r ngFEC/g_pm[5].phase_mon/PS_min_reg[4]/Q net (fo=3, routed) 0.474 2.316 ngFEC/g_pm[5].phase_mon/PS_min_reg_n_0_[4] SLICE_X132Y312 LUT4 (Prop_lut4_I2_O) 0.043 2.359 r ngFEC/g_pm[5].phase_mon/PS_min[9]_i_11__3/O net (fo=1, routed) 0.000 2.359 ngFEC/g_pm[5].phase_mon/PS_min[9]_i_11__3_n_0 SLICE_X132Y312 CARRY4 (Prop_carry4_S[2]_CO[3]) 0.183 2.542 r ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_3__3/CO[3] net (fo=1, routed) 0.000 2.542 ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_3__3_n_0 SLICE_X132Y313 CARRY4 (Prop_carry4_CI_CO[0]) 0.133 2.675 r ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_2__3/CO[0] net (fo=1, routed) 0.575 3.250 ngFEC/g_pm[5].phase_mon/ltOp SLICE_X148Y312 LUT5 (Prop_lut5_I2_O) 0.128 3.378 r ngFEC/g_pm[5].phase_mon/PS_min[9]_i_1__3/O net (fo=10, routed) 0.775 4.153 ngFEC/g_pm[5].phase_mon/PS_min SLICE_X132Y313 FDPE r ngFEC/g_pm[5].phase_mon/PS_min_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 8.200 8.200 r BUFGCTRL_X0Y3 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.417 9.617 ngFEC/g_pm[5].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X132Y313 FDPE r ngFEC/g_pm[5].phase_mon/PS_min_reg[1]/C clock pessimism 0.177 9.794 clock uncertainty -0.035 9.759 SLICE_X132Y313 FDPE (Setup_fdpe_C_CE) -0.178 9.581 ngFEC/g_pm[5].phase_mon/PS_min_reg[1] ------------------------------------------------------------------- required time 9.581 arrival time -4.153 ------------------------------------------------------------------- slack 5.427 Slack (MET) : 5.427ns (required time - arrival time) Source: ngFEC/g_pm[5].phase_mon/PS_min_reg[4]/C (rising edge-triggered cell FDPE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[5].phase_mon/PS_min_reg[5]/CE (rising edge-triggered cell FDPE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_1 rise@8.200ns - txWordclkl8_1 rise@0.000ns) Data Path Delay: 2.534ns (logic 0.710ns (28.014%) route 1.824ns (71.986%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: -0.025ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.417ns = ( 9.617 - 8.200 ) Source Clock Delay (SCD): 1.619ns Clock Pessimism Removal (CPR): 0.177ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y3 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.619 1.619 ngFEC/g_pm[5].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X133Y312 FDPE r ngFEC/g_pm[5].phase_mon/PS_min_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X133Y312 FDPE (Prop_fdpe_C_Q) 0.223 1.842 r ngFEC/g_pm[5].phase_mon/PS_min_reg[4]/Q net (fo=3, routed) 0.474 2.316 ngFEC/g_pm[5].phase_mon/PS_min_reg_n_0_[4] SLICE_X132Y312 LUT4 (Prop_lut4_I2_O) 0.043 2.359 r ngFEC/g_pm[5].phase_mon/PS_min[9]_i_11__3/O net (fo=1, routed) 0.000 2.359 ngFEC/g_pm[5].phase_mon/PS_min[9]_i_11__3_n_0 SLICE_X132Y312 CARRY4 (Prop_carry4_S[2]_CO[3]) 0.183 2.542 r ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_3__3/CO[3] net (fo=1, routed) 0.000 2.542 ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_3__3_n_0 SLICE_X132Y313 CARRY4 (Prop_carry4_CI_CO[0]) 0.133 2.675 r ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_2__3/CO[0] net (fo=1, routed) 0.575 3.250 ngFEC/g_pm[5].phase_mon/ltOp SLICE_X148Y312 LUT5 (Prop_lut5_I2_O) 0.128 3.378 r ngFEC/g_pm[5].phase_mon/PS_min[9]_i_1__3/O net (fo=10, routed) 0.775 4.153 ngFEC/g_pm[5].phase_mon/PS_min SLICE_X132Y313 FDPE r ngFEC/g_pm[5].phase_mon/PS_min_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 8.200 8.200 r BUFGCTRL_X0Y3 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.417 9.617 ngFEC/g_pm[5].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X132Y313 FDPE r ngFEC/g_pm[5].phase_mon/PS_min_reg[5]/C clock pessimism 0.177 9.794 clock uncertainty -0.035 9.759 SLICE_X132Y313 FDPE (Setup_fdpe_C_CE) -0.178 9.581 ngFEC/g_pm[5].phase_mon/PS_min_reg[5] ------------------------------------------------------------------- required time 9.581 arrival time -4.153 ------------------------------------------------------------------- slack 5.427 Slack (MET) : 5.427ns (required time - arrival time) Source: ngFEC/g_pm[5].phase_mon/PS_min_reg[4]/C (rising edge-triggered cell FDPE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[5].phase_mon/PS_min_reg[9]/CE (rising edge-triggered cell FDPE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_1 rise@8.200ns - txWordclkl8_1 rise@0.000ns) Data Path Delay: 2.534ns (logic 0.710ns (28.014%) route 1.824ns (71.986%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: -0.025ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.417ns = ( 9.617 - 8.200 ) Source Clock Delay (SCD): 1.619ns Clock Pessimism Removal (CPR): 0.177ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y3 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.619 1.619 ngFEC/g_pm[5].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X133Y312 FDPE r ngFEC/g_pm[5].phase_mon/PS_min_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X133Y312 FDPE (Prop_fdpe_C_Q) 0.223 1.842 r ngFEC/g_pm[5].phase_mon/PS_min_reg[4]/Q net (fo=3, routed) 0.474 2.316 ngFEC/g_pm[5].phase_mon/PS_min_reg_n_0_[4] SLICE_X132Y312 LUT4 (Prop_lut4_I2_O) 0.043 2.359 r ngFEC/g_pm[5].phase_mon/PS_min[9]_i_11__3/O net (fo=1, routed) 0.000 2.359 ngFEC/g_pm[5].phase_mon/PS_min[9]_i_11__3_n_0 SLICE_X132Y312 CARRY4 (Prop_carry4_S[2]_CO[3]) 0.183 2.542 r ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_3__3/CO[3] net (fo=1, routed) 0.000 2.542 ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_3__3_n_0 SLICE_X132Y313 CARRY4 (Prop_carry4_CI_CO[0]) 0.133 2.675 r ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_2__3/CO[0] net (fo=1, routed) 0.575 3.250 ngFEC/g_pm[5].phase_mon/ltOp SLICE_X148Y312 LUT5 (Prop_lut5_I2_O) 0.128 3.378 r ngFEC/g_pm[5].phase_mon/PS_min[9]_i_1__3/O net (fo=10, routed) 0.775 4.153 ngFEC/g_pm[5].phase_mon/PS_min SLICE_X132Y313 FDPE r ngFEC/g_pm[5].phase_mon/PS_min_reg[9]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 8.200 8.200 r BUFGCTRL_X0Y3 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.417 9.617 ngFEC/g_pm[5].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X132Y313 FDPE r ngFEC/g_pm[5].phase_mon/PS_min_reg[9]/C clock pessimism 0.177 9.794 clock uncertainty -0.035 9.759 SLICE_X132Y313 FDPE (Setup_fdpe_C_CE) -0.178 9.581 ngFEC/g_pm[5].phase_mon/PS_min_reg[9] ------------------------------------------------------------------- required time 9.581 arrival time -4.153 ------------------------------------------------------------------- slack 5.427 Slack (MET) : 5.574ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7]/C (rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[10]/CE (rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_1 rise@8.200ns - txWordclkl8_1 rise@0.000ns) Data Path Delay: 2.388ns (logic 0.388ns (16.248%) route 2.000ns (83.752%)) Logic Levels: 3 (LUT2=1 LUT4=2) Clock Path Skew: -0.025ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.753ns = ( 9.953 - 8.200 ) Source Clock Delay (SCD): 1.895ns Clock Pessimism Removal (CPR): 0.117ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y3 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.895 1.895 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/gt0_txusrclk_in SLICE_X176Y47 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X176Y47 FDRE (Prop_fdre_C_Q) 0.259 2.154 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7]/Q net (fo=2, routed) 0.606 2.760 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7] SLICE_X177Y47 LUT4 (Prop_lut4_I2_O) 0.043 2.803 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_6/O net (fo=1, routed) 0.356 3.159 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_6_n_0 SLICE_X177Y49 LUT4 (Prop_lut4_I0_O) 0.043 3.202 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/O net (fo=2, routed) 0.549 3.752 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4_n_0 SLICE_X177Y50 LUT2 (Prop_lut2_I0_O) 0.043 3.795 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/O net (fo=16, routed) 0.488 4.283 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2_n_0 SLICE_X176Y48 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[10]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 8.200 8.200 r BUFGCTRL_X0Y3 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.753 9.953 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/gt0_txusrclk_in SLICE_X176Y48 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[10]/C clock pessimism 0.117 10.070 clock uncertainty -0.035 10.035 SLICE_X176Y48 FDRE (Setup_fdre_C_CE) -0.178 9.857 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[10] ------------------------------------------------------------------- required time 9.857 arrival time -4.283 ------------------------------------------------------------------- slack 5.574 Slack (MET) : 5.574ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7]/C (rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[11]/CE (rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_1 rise@8.200ns - txWordclkl8_1 rise@0.000ns) Data Path Delay: 2.388ns (logic 0.388ns (16.248%) route 2.000ns (83.752%)) Logic Levels: 3 (LUT2=1 LUT4=2) Clock Path Skew: -0.025ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.753ns = ( 9.953 - 8.200 ) Source Clock Delay (SCD): 1.895ns Clock Pessimism Removal (CPR): 0.117ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y3 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.895 1.895 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/gt0_txusrclk_in SLICE_X176Y47 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X176Y47 FDRE (Prop_fdre_C_Q) 0.259 2.154 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7]/Q net (fo=2, routed) 0.606 2.760 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7] SLICE_X177Y47 LUT4 (Prop_lut4_I2_O) 0.043 2.803 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_6/O net (fo=1, routed) 0.356 3.159 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_6_n_0 SLICE_X177Y49 LUT4 (Prop_lut4_I0_O) 0.043 3.202 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/O net (fo=2, routed) 0.549 3.752 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4_n_0 SLICE_X177Y50 LUT2 (Prop_lut2_I0_O) 0.043 3.795 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/O net (fo=16, routed) 0.488 4.283 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2_n_0 SLICE_X176Y48 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[11]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 8.200 8.200 r BUFGCTRL_X0Y3 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.753 9.953 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/gt0_txusrclk_in SLICE_X176Y48 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[11]/C clock pessimism 0.117 10.070 clock uncertainty -0.035 10.035 SLICE_X176Y48 FDRE (Setup_fdre_C_CE) -0.178 9.857 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[11] ------------------------------------------------------------------- required time 9.857 arrival time -4.283 ------------------------------------------------------------------- slack 5.574 Slack (MET) : 5.574ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7]/C (rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[8]/CE (rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_1 rise@8.200ns - txWordclkl8_1 rise@0.000ns) Data Path Delay: 2.388ns (logic 0.388ns (16.248%) route 2.000ns (83.752%)) Logic Levels: 3 (LUT2=1 LUT4=2) Clock Path Skew: -0.025ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.753ns = ( 9.953 - 8.200 ) Source Clock Delay (SCD): 1.895ns Clock Pessimism Removal (CPR): 0.117ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y3 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.895 1.895 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/gt0_txusrclk_in SLICE_X176Y47 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X176Y47 FDRE (Prop_fdre_C_Q) 0.259 2.154 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7]/Q net (fo=2, routed) 0.606 2.760 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7] SLICE_X177Y47 LUT4 (Prop_lut4_I2_O) 0.043 2.803 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_6/O net (fo=1, routed) 0.356 3.159 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_6_n_0 SLICE_X177Y49 LUT4 (Prop_lut4_I0_O) 0.043 3.202 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/O net (fo=2, routed) 0.549 3.752 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4_n_0 SLICE_X177Y50 LUT2 (Prop_lut2_I0_O) 0.043 3.795 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/O net (fo=16, routed) 0.488 4.283 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2_n_0 SLICE_X176Y48 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[8]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 8.200 8.200 r BUFGCTRL_X0Y3 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.753 9.953 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/gt0_txusrclk_in SLICE_X176Y48 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[8]/C clock pessimism 0.117 10.070 clock uncertainty -0.035 10.035 SLICE_X176Y48 FDRE (Setup_fdre_C_CE) -0.178 9.857 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[8] ------------------------------------------------------------------- required time 9.857 arrival time -4.283 ------------------------------------------------------------------- slack 5.574 Slack (MET) : 5.574ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7]/C (rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[9]/CE (rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_1 rise@8.200ns - txWordclkl8_1 rise@0.000ns) Data Path Delay: 2.388ns (logic 0.388ns (16.248%) route 2.000ns (83.752%)) Logic Levels: 3 (LUT2=1 LUT4=2) Clock Path Skew: -0.025ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.753ns = ( 9.953 - 8.200 ) Source Clock Delay (SCD): 1.895ns Clock Pessimism Removal (CPR): 0.117ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y3 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.895 1.895 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/gt0_txusrclk_in SLICE_X176Y47 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X176Y47 FDRE (Prop_fdre_C_Q) 0.259 2.154 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7]/Q net (fo=2, routed) 0.606 2.760 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[7] SLICE_X177Y47 LUT4 (Prop_lut4_I2_O) 0.043 2.803 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_6/O net (fo=1, routed) 0.356 3.159 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_6_n_0 SLICE_X177Y49 LUT4 (Prop_lut4_I0_O) 0.043 3.202 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4/O net (fo=2, routed) 0.549 3.752 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_4_n_0 SLICE_X177Y50 LUT2 (Prop_lut2_I0_O) 0.043 3.795 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2/O net (fo=16, routed) 0.488 4.283 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count[0]_i_2_n_0 SLICE_X176Y48 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[9]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 8.200 8.200 r BUFGCTRL_X0Y3 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.753 9.953 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/gt0_txusrclk_in SLICE_X176Y48 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[9]/C clock pessimism 0.117 10.070 clock uncertainty -0.035 10.035 SLICE_X176Y48 FDRE (Setup_fdre_C_CE) -0.178 9.857 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[9] ------------------------------------------------------------------- required time 9.857 arrival time -4.283 ------------------------------------------------------------------- slack 5.574 Slack (MET) : 5.582ns (required time - arrival time) Source: ngFEC/g_pm[5].phase_mon/PS_min_reg[5]/C (rising edge-triggered cell FDPE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[5].phase_mon/PS_min_reg[0]/CE (rising edge-triggered cell FDPE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_1 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_1 rise@8.200ns - txWordclkl8_1 rise@0.000ns) Data Path Delay: 2.358ns (logic 0.746ns (31.637%) route 1.612ns (68.363%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: -0.024ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.417ns = ( 9.617 - 8.200 ) Source Clock Delay (SCD): 1.618ns Clock Pessimism Removal (CPR): 0.177ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y3 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.618 1.618 ngFEC/g_pm[5].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X132Y313 FDPE r ngFEC/g_pm[5].phase_mon/PS_min_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X132Y313 FDPE (Prop_fdpe_C_Q) 0.259 1.877 r ngFEC/g_pm[5].phase_mon/PS_min_reg[5]/Q net (fo=3, routed) 0.443 2.320 ngFEC/g_pm[5].phase_mon/PS_min_reg_n_0_[5] SLICE_X132Y312 LUT4 (Prop_lut4_I0_O) 0.043 2.363 r ngFEC/g_pm[5].phase_mon/PS_min[9]_i_11__3/O net (fo=1, routed) 0.000 2.363 ngFEC/g_pm[5].phase_mon/PS_min[9]_i_11__3_n_0 SLICE_X132Y312 CARRY4 (Prop_carry4_S[2]_CO[3]) 0.183 2.546 r ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_3__3/CO[3] net (fo=1, routed) 0.000 2.546 ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_3__3_n_0 SLICE_X132Y313 CARRY4 (Prop_carry4_CI_CO[0]) 0.133 2.679 r ngFEC/g_pm[5].phase_mon/PS_min_reg[9]_i_2__3/CO[0] net (fo=1, routed) 0.575 3.254 ngFEC/g_pm[5].phase_mon/ltOp SLICE_X148Y312 LUT5 (Prop_lut5_I2_O) 0.128 3.382 r ngFEC/g_pm[5].phase_mon/PS_min[9]_i_1__3/O net (fo=10, routed) 0.594 3.976 ngFEC/g_pm[5].phase_mon/PS_min SLICE_X133Y312 FDPE r ngFEC/g_pm[5].phase_mon/PS_min_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 8.200 8.200 r BUFGCTRL_X0Y3 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.417 9.617 ngFEC/g_pm[5].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X133Y312 FDPE r ngFEC/g_pm[5].phase_mon/PS_min_reg[0]/C clock pessimism 0.177 9.794 clock uncertainty -0.035 9.759 SLICE_X133Y312 FDPE (Setup_fdpe_C_CE) -0.201 9.558 ngFEC/g_pm[5].phase_mon/PS_min_reg[0] ------------------------------------------------------------------- required time 9.558 arrival time -3.976 ------------------------------------------------------------------- slack 5.582 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_1 rise@0.000ns - txWordclkl8_1 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.058ns Source Clock Delay (SCD): 0.794ns Clock Pessimism Removal (CPR): 0.264ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y3 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.794 0.794 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in SLICE_X177Y47 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X177Y47 FDRE (Prop_fdre_C_Q) 0.100 0.894 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q net (fo=1, routed) 0.055 0.949 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync1 SLICE_X177Y47 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y3 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.058 1.058 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in SLICE_X177Y47 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C clock pessimism -0.264 0.794 SLICE_X177Y47 FDRE (Hold_fdre_C_D) 0.047 0.841 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.841 arrival time 0.949 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D (rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_1 rise@0.000ns - txWordclkl8_1 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.993ns Source Clock Delay (SCD): 0.746ns Clock Pessimism Removal (CPR): 0.247ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y3 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.746 0.746 ngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/dest_clk SLICE_X151Y313 FDRE r ngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X151Y313 FDRE (Prop_fdre_C_Q) 0.100 0.846 r ngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/Q net (fo=1, routed) 0.055 0.901 ngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff[0] SLICE_X151Y313 FDRE r ngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y3 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.993 0.993 ngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/dest_clk SLICE_X151Y313 FDRE r ngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/C clock pessimism -0.247 0.746 SLICE_X151Y313 FDRE (Hold_fdre_C_D) 0.047 0.793 ngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1] ------------------------------------------------------------------- required time -0.793 arrival time 0.901 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/g_pm[5].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[5].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/D (rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_1 rise@0.000ns - txWordclkl8_1 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.994ns Source Clock Delay (SCD): 0.748ns Clock Pessimism Removal (CPR): 0.246ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y3 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.748 0.748 ngFEC/g_pm[5].phase_mon/sample_PS_Sync_inst/dest_clk SLICE_X157Y313 FDRE r ngFEC/g_pm[5].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X157Y313 FDRE (Prop_fdre_C_Q) 0.100 0.848 r ngFEC/g_pm[5].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/Q net (fo=1, routed) 0.055 0.903 ngFEC/g_pm[5].phase_mon/sample_PS_Sync_inst/syncstages_ff[0] SLICE_X157Y313 FDRE r ngFEC/g_pm[5].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y3 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.994 0.994 ngFEC/g_pm[5].phase_mon/sample_PS_Sync_inst/dest_clk SLICE_X157Y313 FDRE r ngFEC/g_pm[5].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/C clock pessimism -0.246 0.748 SLICE_X157Y313 FDRE (Hold_fdre_C_D) 0.047 0.795 ngFEC/g_pm[5].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1] ------------------------------------------------------------------- required time -0.795 arrival time 0.903 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D (rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_1 rise@0.000ns - txWordclkl8_1 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.058ns Source Clock Delay (SCD): 0.794ns Clock Pessimism Removal (CPR): 0.264ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y3 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.794 0.794 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk SLICE_X187Y46 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X187Y46 FDRE (Prop_fdre_C_Q) 0.100 0.894 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/Q net (fo=1, routed) 0.055 0.949 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff[0] SLICE_X187Y46 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y3 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.058 1.058 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk SLICE_X187Y46 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/C clock pessimism -0.264 0.794 SLICE_X187Y46 FDRE (Hold_fdre_C_D) 0.047 0.841 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1] ------------------------------------------------------------------- required time -0.841 arrival time 0.949 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.119ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/C (rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/D (rising edge-triggered cell SRL16E clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_1 rise@0.000ns - txWordclkl8_1 rise@0.000ns) Data Path Delay: 0.236ns (logic 0.100ns (42.445%) route 0.136ns (57.555%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.059ns Source Clock Delay (SCD): 0.794ns Clock Pessimism Removal (CPR): 0.250ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y3 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.794 0.794 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk SLICE_X187Y46 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X187Y46 FDRE (Prop_fdre_C_Q) 0.100 0.894 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/Q net (fo=1, routed) 0.136 1.030 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/dest_out SLICE_X186Y47 SRL16E r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/D ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y3 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.059 1.059 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X186Y47 SRL16E r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK clock pessimism -0.250 0.809 SLICE_X186Y47 SRL16E (Hold_srl16e_CLK_D) 0.102 0.911 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3 ------------------------------------------------------------------- required time -0.911 arrival time 1.030 ------------------------------------------------------------------- slack 0.119 Slack (MET) : 0.131ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_1 rise@0.000ns - txWordclkl8_1 rise@0.000ns) Data Path Delay: 0.173ns (logic 0.118ns (68.255%) route 0.055ns (31.745%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.986ns Source Clock Delay (SCD): 0.742ns Clock Pessimism Removal (CPR): 0.244ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y3 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.742 0.742 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in SLICE_X176Y50 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X176Y50 FDRE (Prop_fdre_C_Q) 0.118 0.860 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/Q net (fo=1, routed) 0.055 0.915 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync1 SLICE_X176Y50 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y3 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.986 0.986 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in SLICE_X176Y50 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/C clock pessimism -0.244 0.742 SLICE_X176Y50 FDRE (Hold_fdre_C_D) 0.042 0.784 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.784 arrival time 0.915 ------------------------------------------------------------------- slack 0.131 Slack (MET) : 0.134ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[82]/C (rising edge-triggered cell FDCE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[2]/D (rising edge-triggered cell FDCE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_1 rise@0.000ns - txWordclkl8_1 rise@0.000ns) Data Path Delay: 0.229ns (logic 0.128ns (55.979%) route 0.101ns (44.021%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.057ns Source Clock Delay (SCD): 0.794ns Clock Pessimism Removal (CPR): 0.228ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y3 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.794 0.794 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X188Y41 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[82]/C ------------------------------------------------------------------- ------------------- SLICE_X188Y41 FDCE (Prop_fdce_C_Q) 0.100 0.894 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[82]/Q net (fo=1, routed) 0.101 0.995 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/data4[2] SLICE_X187Y41 LUT6 (Prop_lut6_I0_O) 0.028 1.023 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[2]_i_1__7/O net (fo=1, routed) 0.000 1.023 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[2]_i_1__7_n_0 SLICE_X187Y41 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[2]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y3 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.057 1.057 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X187Y41 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[2]/C clock pessimism -0.228 0.829 SLICE_X187Y41 FDCE (Hold_fdce_C_D) 0.060 0.889 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[2] ------------------------------------------------------------------- required time -0.889 arrival time 1.023 ------------------------------------------------------------------- slack 0.134 Slack (MET) : 0.137ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[118]/C (rising edge-triggered cell FDCE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/D (rising edge-triggered cell FDCE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_1 rise@0.000ns - txWordclkl8_1 rise@0.000ns) Data Path Delay: 0.208ns (logic 0.128ns (61.615%) route 0.080ns (38.385%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.057ns Source Clock Delay (SCD): 0.794ns Clock Pessimism Removal (CPR): 0.252ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y3 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.794 0.794 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X188Y42 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[118]/C ------------------------------------------------------------------- ------------------- SLICE_X188Y42 FDCE (Prop_fdce_C_Q) 0.100 0.894 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[118]/Q net (fo=1, routed) 0.080 0.974 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/data5[18] SLICE_X189Y42 LUT6 (Prop_lut6_I2_O) 0.028 1.002 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[18]_i_1__7/O net (fo=1, routed) 0.000 1.002 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[18]_i_1__7_n_0 SLICE_X189Y42 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y3 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.057 1.057 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X189Y42 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/C clock pessimism -0.252 0.805 SLICE_X189Y42 FDCE (Hold_fdce_C_D) 0.060 0.865 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18] ------------------------------------------------------------------- required time -0.865 arrival time 1.002 ------------------------------------------------------------------- slack 0.137 Slack (MET) : 0.155ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/tx_fsm_reset_done_int_s3_reg/C (rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_reg/D (rising edge-triggered cell FDRE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_1 rise@0.000ns - txWordclkl8_1 rise@0.000ns) Data Path Delay: 0.215ns (logic 0.157ns (72.918%) route 0.058ns (27.082%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.986ns Source Clock Delay (SCD): 0.742ns Clock Pessimism Removal (CPR): 0.244ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y3 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.742 0.742 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/gt0_txusrclk_in SLICE_X177Y50 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/tx_fsm_reset_done_int_s3_reg/C ------------------------------------------------------------------- ------------------- SLICE_X177Y50 FDRE (Prop_fdre_C_Q) 0.091 0.833 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/tx_fsm_reset_done_int_s3_reg/Q net (fo=2, routed) 0.058 0.891 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/tx_fsm_reset_done_int_s3 SLICE_X177Y50 LUT4 (Prop_lut4_I2_O) 0.066 0.957 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_i_1/O net (fo=1, routed) 0.000 0.957 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_i_1_n_0 SLICE_X177Y50 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_reg/D ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y3 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.986 0.986 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/gt0_txusrclk_in SLICE_X177Y50 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_reg/C clock pessimism -0.244 0.742 SLICE_X177Y50 FDRE (Hold_fdre_C_D) 0.060 0.802 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_reg ------------------------------------------------------------------- required time -0.802 arrival time 0.957 ------------------------------------------------------------------- slack 0.155 Slack (MET) : 0.163ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[100]/C (rising edge-triggered cell FDCE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/D (rising edge-triggered cell FDCE clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_1 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_1 rise@0.000ns - txWordclkl8_1 rise@0.000ns) Data Path Delay: 0.238ns (logic 0.146ns (61.426%) route 0.092ns (38.574%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.058ns Source Clock Delay (SCD): 0.794ns Clock Pessimism Removal (CPR): 0.250ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y3 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.794 0.794 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X186Y43 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[100]/C ------------------------------------------------------------------- ------------------- SLICE_X186Y43 FDCE (Prop_fdce_C_Q) 0.118 0.912 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[100]/Q net (fo=1, routed) 0.092 1.004 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/data5[0] SLICE_X185Y43 LUT6 (Prop_lut6_I2_O) 0.028 1.032 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[0]_i_1__7/O net (fo=1, routed) 0.000 1.032 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[0]_i_1__7_n_0 SLICE_X185Y43 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y3 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.058 1.058 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/CLK SLICE_X185Y43 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/C clock pessimism -0.250 0.808 SLICE_X185Y43 FDCE (Hold_fdce_C_D) 0.061 0.869 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0] ------------------------------------------------------------------- required time -0.869 arrival time 1.032 ------------------------------------------------------------------- slack 0.163 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: txWordclkl8_1 Waveform(ns): { 0.000 4.100 } Period(ns): 8.200 Sources: { ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/TXUSRCLK n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y4 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK Min Period n/a GTXE2_CHANNEL/TXUSRCLK2 n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y4 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X186Y47 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X187Y45 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[1]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X187Y44 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.ready_reg/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X184Y42 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[47]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X188Y40 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[4]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X184Y40 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[56]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X184Y40 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[58]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X183Y40 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[59]/C Low Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X186Y47 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK Low Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X186Y47 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK Low Pulse Width Slow FDRE/C n/a 0.400 4.100 3.700 SLICE_X176Y50 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/C Low Pulse Width Slow FDRE/C n/a 0.400 4.100 3.700 SLICE_X176Y50 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg3/C Low Pulse Width Slow FDRE/C n/a 0.400 4.100 3.700 SLICE_X176Y50 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg5/C Low Pulse Width Slow FDRE/C n/a 0.400 4.100 3.700 SLICE_X177Y50 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/tx_fsm_reset_done_int_s3_reg/C Low Pulse Width Fast FDRE/C n/a 0.400 4.100 3.700 SLICE_X151Y313 ngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/C Low Pulse Width Fast FDRE/C n/a 0.400 4.100 3.700 SLICE_X151Y313 ngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[2]/C Low Pulse Width Fast FDPE/C n/a 0.400 4.100 3.700 SLICE_X148Y311 ngFEC/g_pm[5].phase_mon/inh_cntr_reg[2]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X187Y45 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[1]/C High Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X186Y47 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X186Y47 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK High Pulse Width Fast FDPE/C n/a 0.350 4.100 3.750 SLICE_X133Y312 ngFEC/g_pm[5].phase_mon/PS_min_reg[0]/C High Pulse Width Fast FDPE/C n/a 0.350 4.100 3.750 SLICE_X133Y312 ngFEC/g_pm[5].phase_mon/PS_min_reg[2]/C High Pulse Width Fast FDPE/C n/a 0.350 4.100 3.750 SLICE_X133Y312 ngFEC/g_pm[5].phase_mon/PS_min_reg[3]/C High Pulse Width Fast FDPE/C n/a 0.350 4.100 3.750 SLICE_X133Y312 ngFEC/g_pm[5].phase_mon/PS_min_reg[4]/C High Pulse Width Fast FDPE/C n/a 0.350 4.100 3.750 SLICE_X133Y312 ngFEC/g_pm[5].phase_mon/PS_min_reg[6]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X186Y47 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/C High Pulse Width Fast FDRE/C n/a 0.350 4.100 3.750 SLICE_X186Y47 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X187Y46 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/TOGGLE_sync_reg[5]/C --------------------------------------------------------------------------------------------------- From Clock: txWordclkl8_2 To Clock: txWordclkl8_2 Setup : 0 Failing Endpoints, Worst Slack 5.193ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.094ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.458ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.193ns (required time - arrival time) Source: ngFEC/g_pm[6].phase_mon/PS_min_reg[0]/C (rising edge-triggered cell FDPE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[6].phase_mon/PS_min_reg[4]/CE (rising edge-triggered cell FDPE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_2 rise@8.200ns - txWordclkl8_2 rise@0.000ns) Data Path Delay: 2.661ns (logic 0.831ns (31.228%) route 1.830ns (68.772%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: -0.110ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.364ns = ( 9.564 - 8.200 ) Source Clock Delay (SCD): 1.627ns Clock Pessimism Removal (CPR): 0.153ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y4 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.627 1.627 ngFEC/g_pm[6].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X136Y307 FDPE r ngFEC/g_pm[6].phase_mon/PS_min_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X136Y307 FDPE (Prop_fdpe_C_Q) 0.259 1.886 r ngFEC/g_pm[6].phase_mon/PS_min_reg[0]/Q net (fo=3, routed) 0.497 2.383 ngFEC/g_pm[6].phase_mon/PS_min_reg_n_0_[0] SLICE_X131Y307 LUT4 (Prop_lut4_I2_O) 0.043 2.426 r ngFEC/g_pm[6].phase_mon/PS_min[9]_i_13__4/O net (fo=1, routed) 0.000 2.426 ngFEC/g_pm[6].phase_mon/PS_min[9]_i_13__4_n_0 SLICE_X131Y307 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.259 2.685 r ngFEC/g_pm[6].phase_mon/PS_min_reg[9]_i_3__4/CO[3] net (fo=1, routed) 0.000 2.685 ngFEC/g_pm[6].phase_mon/PS_min_reg[9]_i_3__4_n_0 SLICE_X131Y308 CARRY4 (Prop_carry4_CI_CO[0]) 0.139 2.824 r ngFEC/g_pm[6].phase_mon/PS_min_reg[9]_i_2__4/CO[0] net (fo=1, routed) 0.604 3.428 ngFEC/g_pm[6].phase_mon/ltOp SLICE_X142Y307 LUT5 (Prop_lut5_I2_O) 0.131 3.559 r ngFEC/g_pm[6].phase_mon/PS_min[9]_i_1__4/O net (fo=10, routed) 0.729 4.288 ngFEC/g_pm[6].phase_mon/PS_min SLICE_X131Y307 FDPE r ngFEC/g_pm[6].phase_mon/PS_min_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 8.200 8.200 r BUFGCTRL_X0Y4 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.364 9.564 ngFEC/g_pm[6].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X131Y307 FDPE r ngFEC/g_pm[6].phase_mon/PS_min_reg[4]/C clock pessimism 0.153 9.717 clock uncertainty -0.035 9.682 SLICE_X131Y307 FDPE (Setup_fdpe_C_CE) -0.201 9.481 ngFEC/g_pm[6].phase_mon/PS_min_reg[4] ------------------------------------------------------------------- required time 9.481 arrival time -4.288 ------------------------------------------------------------------- slack 5.193 Slack (MET) : 5.193ns (required time - arrival time) Source: ngFEC/g_pm[6].phase_mon/PS_min_reg[0]/C (rising edge-triggered cell FDPE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[6].phase_mon/PS_min_reg[5]/CE (rising edge-triggered cell FDPE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_2 rise@8.200ns - txWordclkl8_2 rise@0.000ns) Data Path Delay: 2.661ns (logic 0.831ns (31.228%) route 1.830ns (68.772%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: -0.110ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.364ns = ( 9.564 - 8.200 ) Source Clock Delay (SCD): 1.627ns Clock Pessimism Removal (CPR): 0.153ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y4 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.627 1.627 ngFEC/g_pm[6].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X136Y307 FDPE r ngFEC/g_pm[6].phase_mon/PS_min_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X136Y307 FDPE (Prop_fdpe_C_Q) 0.259 1.886 r ngFEC/g_pm[6].phase_mon/PS_min_reg[0]/Q net (fo=3, routed) 0.497 2.383 ngFEC/g_pm[6].phase_mon/PS_min_reg_n_0_[0] SLICE_X131Y307 LUT4 (Prop_lut4_I2_O) 0.043 2.426 r ngFEC/g_pm[6].phase_mon/PS_min[9]_i_13__4/O net (fo=1, routed) 0.000 2.426 ngFEC/g_pm[6].phase_mon/PS_min[9]_i_13__4_n_0 SLICE_X131Y307 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.259 2.685 r ngFEC/g_pm[6].phase_mon/PS_min_reg[9]_i_3__4/CO[3] net (fo=1, routed) 0.000 2.685 ngFEC/g_pm[6].phase_mon/PS_min_reg[9]_i_3__4_n_0 SLICE_X131Y308 CARRY4 (Prop_carry4_CI_CO[0]) 0.139 2.824 r ngFEC/g_pm[6].phase_mon/PS_min_reg[9]_i_2__4/CO[0] net (fo=1, routed) 0.604 3.428 ngFEC/g_pm[6].phase_mon/ltOp SLICE_X142Y307 LUT5 (Prop_lut5_I2_O) 0.131 3.559 r ngFEC/g_pm[6].phase_mon/PS_min[9]_i_1__4/O net (fo=10, routed) 0.729 4.288 ngFEC/g_pm[6].phase_mon/PS_min SLICE_X131Y307 FDPE r ngFEC/g_pm[6].phase_mon/PS_min_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 8.200 8.200 r BUFGCTRL_X0Y4 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.364 9.564 ngFEC/g_pm[6].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X131Y307 FDPE r ngFEC/g_pm[6].phase_mon/PS_min_reg[5]/C clock pessimism 0.153 9.717 clock uncertainty -0.035 9.682 SLICE_X131Y307 FDPE (Setup_fdpe_C_CE) -0.201 9.481 ngFEC/g_pm[6].phase_mon/PS_min_reg[5] ------------------------------------------------------------------- required time 9.481 arrival time -4.288 ------------------------------------------------------------------- slack 5.193 Slack (MET) : 5.193ns (required time - arrival time) Source: ngFEC/g_pm[6].phase_mon/PS_min_reg[0]/C (rising edge-triggered cell FDPE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[6].phase_mon/PS_min_reg[6]/CE (rising edge-triggered cell FDPE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_2 rise@8.200ns - txWordclkl8_2 rise@0.000ns) Data Path Delay: 2.661ns (logic 0.831ns (31.228%) route 1.830ns (68.772%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: -0.110ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.364ns = ( 9.564 - 8.200 ) Source Clock Delay (SCD): 1.627ns Clock Pessimism Removal (CPR): 0.153ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y4 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.627 1.627 ngFEC/g_pm[6].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X136Y307 FDPE r ngFEC/g_pm[6].phase_mon/PS_min_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X136Y307 FDPE (Prop_fdpe_C_Q) 0.259 1.886 r ngFEC/g_pm[6].phase_mon/PS_min_reg[0]/Q net (fo=3, routed) 0.497 2.383 ngFEC/g_pm[6].phase_mon/PS_min_reg_n_0_[0] SLICE_X131Y307 LUT4 (Prop_lut4_I2_O) 0.043 2.426 r ngFEC/g_pm[6].phase_mon/PS_min[9]_i_13__4/O net (fo=1, routed) 0.000 2.426 ngFEC/g_pm[6].phase_mon/PS_min[9]_i_13__4_n_0 SLICE_X131Y307 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.259 2.685 r ngFEC/g_pm[6].phase_mon/PS_min_reg[9]_i_3__4/CO[3] net (fo=1, routed) 0.000 2.685 ngFEC/g_pm[6].phase_mon/PS_min_reg[9]_i_3__4_n_0 SLICE_X131Y308 CARRY4 (Prop_carry4_CI_CO[0]) 0.139 2.824 r ngFEC/g_pm[6].phase_mon/PS_min_reg[9]_i_2__4/CO[0] net (fo=1, routed) 0.604 3.428 ngFEC/g_pm[6].phase_mon/ltOp SLICE_X142Y307 LUT5 (Prop_lut5_I2_O) 0.131 3.559 r ngFEC/g_pm[6].phase_mon/PS_min[9]_i_1__4/O net (fo=10, routed) 0.729 4.288 ngFEC/g_pm[6].phase_mon/PS_min SLICE_X131Y307 FDPE r ngFEC/g_pm[6].phase_mon/PS_min_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 8.200 8.200 r BUFGCTRL_X0Y4 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.364 9.564 ngFEC/g_pm[6].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X131Y307 FDPE r ngFEC/g_pm[6].phase_mon/PS_min_reg[6]/C clock pessimism 0.153 9.717 clock uncertainty -0.035 9.682 SLICE_X131Y307 FDPE (Setup_fdpe_C_CE) -0.201 9.481 ngFEC/g_pm[6].phase_mon/PS_min_reg[6] ------------------------------------------------------------------- required time 9.481 arrival time -4.288 ------------------------------------------------------------------- slack 5.193 Slack (MET) : 5.193ns (required time - arrival time) Source: ngFEC/g_pm[6].phase_mon/PS_min_reg[0]/C (rising edge-triggered cell FDPE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[6].phase_mon/PS_min_reg[9]/CE (rising edge-triggered cell FDPE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_2 rise@8.200ns - txWordclkl8_2 rise@0.000ns) Data Path Delay: 2.661ns (logic 0.831ns (31.228%) route 1.830ns (68.772%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: -0.110ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.364ns = ( 9.564 - 8.200 ) Source Clock Delay (SCD): 1.627ns Clock Pessimism Removal (CPR): 0.153ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y4 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.627 1.627 ngFEC/g_pm[6].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X136Y307 FDPE r ngFEC/g_pm[6].phase_mon/PS_min_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X136Y307 FDPE (Prop_fdpe_C_Q) 0.259 1.886 r ngFEC/g_pm[6].phase_mon/PS_min_reg[0]/Q net (fo=3, routed) 0.497 2.383 ngFEC/g_pm[6].phase_mon/PS_min_reg_n_0_[0] SLICE_X131Y307 LUT4 (Prop_lut4_I2_O) 0.043 2.426 r ngFEC/g_pm[6].phase_mon/PS_min[9]_i_13__4/O net (fo=1, routed) 0.000 2.426 ngFEC/g_pm[6].phase_mon/PS_min[9]_i_13__4_n_0 SLICE_X131Y307 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.259 2.685 r ngFEC/g_pm[6].phase_mon/PS_min_reg[9]_i_3__4/CO[3] net (fo=1, routed) 0.000 2.685 ngFEC/g_pm[6].phase_mon/PS_min_reg[9]_i_3__4_n_0 SLICE_X131Y308 CARRY4 (Prop_carry4_CI_CO[0]) 0.139 2.824 r ngFEC/g_pm[6].phase_mon/PS_min_reg[9]_i_2__4/CO[0] net (fo=1, routed) 0.604 3.428 ngFEC/g_pm[6].phase_mon/ltOp SLICE_X142Y307 LUT5 (Prop_lut5_I2_O) 0.131 3.559 r ngFEC/g_pm[6].phase_mon/PS_min[9]_i_1__4/O net (fo=10, routed) 0.729 4.288 ngFEC/g_pm[6].phase_mon/PS_min SLICE_X131Y307 FDPE r ngFEC/g_pm[6].phase_mon/PS_min_reg[9]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 8.200 8.200 r BUFGCTRL_X0Y4 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.364 9.564 ngFEC/g_pm[6].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X131Y307 FDPE r ngFEC/g_pm[6].phase_mon/PS_min_reg[9]/C clock pessimism 0.153 9.717 clock uncertainty -0.035 9.682 SLICE_X131Y307 FDPE (Setup_fdpe_C_CE) -0.201 9.481 ngFEC/g_pm[6].phase_mon/PS_min_reg[9] ------------------------------------------------------------------- required time 9.481 arrival time -4.288 ------------------------------------------------------------------- slack 5.193 Slack (MET) : 5.200ns (required time - arrival time) Source: ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/C (rising edge-triggered cell FDCE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/CE (rising edge-triggered cell FDCE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_2 rise@8.200ns - txWordclkl8_2 rise@0.000ns) Data Path Delay: 2.787ns (logic 0.831ns (29.818%) route 1.956ns (70.182%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.434ns = ( 9.634 - 8.200 ) Source Clock Delay (SCD): 1.636ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y4 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.636 1.636 ngFEC/g_pm[6].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X154Y306 FDCE r ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X154Y306 FDCE (Prop_fdce_C_Q) 0.259 1.895 r ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/Q net (fo=3, routed) 0.440 2.335 ngFEC/g_pm[6].phase_mon/PS_max_reg_n_0_[1] SLICE_X152Y306 LUT4 (Prop_lut4_I0_O) 0.043 2.378 r ngFEC/g_pm[6].phase_mon/PS_max[9]_i_15__1/O net (fo=1, routed) 0.000 2.378 ngFEC/g_pm[6].phase_mon/PS_max[9]_i_15__1_n_0 SLICE_X152Y306 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.259 2.637 r ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_5__1/CO[3] net (fo=1, routed) 0.000 2.637 ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_5__1_n_0 SLICE_X152Y307 CARRY4 (Prop_carry4_CI_CO[0]) 0.139 2.776 r ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_3__1/CO[0] net (fo=1, routed) 0.710 3.486 ngFEC/g_pm[6].phase_mon/gtOp SLICE_X142Y307 LUT5 (Prop_lut5_I2_O) 0.131 3.617 r ngFEC/g_pm[6].phase_mon/PS_max[9]_i_1__4/O net (fo=10, routed) 0.806 4.423 ngFEC/g_pm[6].phase_mon/PS_max SLICE_X154Y306 FDCE r ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 8.200 8.200 r BUFGCTRL_X0Y4 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.434 9.634 ngFEC/g_pm[6].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X154Y306 FDCE r ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/C clock pessimism 0.202 9.836 clock uncertainty -0.035 9.801 SLICE_X154Y306 FDCE (Setup_fdce_C_CE) -0.178 9.623 ngFEC/g_pm[6].phase_mon/PS_max_reg[1] ------------------------------------------------------------------- required time 9.623 arrival time -4.423 ------------------------------------------------------------------- slack 5.200 Slack (MET) : 5.200ns (required time - arrival time) Source: ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/C (rising edge-triggered cell FDCE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[6].phase_mon/PS_max_reg[2]/CE (rising edge-triggered cell FDCE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_2 rise@8.200ns - txWordclkl8_2 rise@0.000ns) Data Path Delay: 2.787ns (logic 0.831ns (29.818%) route 1.956ns (70.182%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.434ns = ( 9.634 - 8.200 ) Source Clock Delay (SCD): 1.636ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y4 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.636 1.636 ngFEC/g_pm[6].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X154Y306 FDCE r ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X154Y306 FDCE (Prop_fdce_C_Q) 0.259 1.895 r ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/Q net (fo=3, routed) 0.440 2.335 ngFEC/g_pm[6].phase_mon/PS_max_reg_n_0_[1] SLICE_X152Y306 LUT4 (Prop_lut4_I0_O) 0.043 2.378 r ngFEC/g_pm[6].phase_mon/PS_max[9]_i_15__1/O net (fo=1, routed) 0.000 2.378 ngFEC/g_pm[6].phase_mon/PS_max[9]_i_15__1_n_0 SLICE_X152Y306 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.259 2.637 r ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_5__1/CO[3] net (fo=1, routed) 0.000 2.637 ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_5__1_n_0 SLICE_X152Y307 CARRY4 (Prop_carry4_CI_CO[0]) 0.139 2.776 r ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_3__1/CO[0] net (fo=1, routed) 0.710 3.486 ngFEC/g_pm[6].phase_mon/gtOp SLICE_X142Y307 LUT5 (Prop_lut5_I2_O) 0.131 3.617 r ngFEC/g_pm[6].phase_mon/PS_max[9]_i_1__4/O net (fo=10, routed) 0.806 4.423 ngFEC/g_pm[6].phase_mon/PS_max SLICE_X154Y306 FDCE r ngFEC/g_pm[6].phase_mon/PS_max_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 8.200 8.200 r BUFGCTRL_X0Y4 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.434 9.634 ngFEC/g_pm[6].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X154Y306 FDCE r ngFEC/g_pm[6].phase_mon/PS_max_reg[2]/C clock pessimism 0.202 9.836 clock uncertainty -0.035 9.801 SLICE_X154Y306 FDCE (Setup_fdce_C_CE) -0.178 9.623 ngFEC/g_pm[6].phase_mon/PS_max_reg[2] ------------------------------------------------------------------- required time 9.623 arrival time -4.423 ------------------------------------------------------------------- slack 5.200 Slack (MET) : 5.200ns (required time - arrival time) Source: ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/C (rising edge-triggered cell FDCE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[6].phase_mon/PS_max_reg[5]/CE (rising edge-triggered cell FDCE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_2 rise@8.200ns - txWordclkl8_2 rise@0.000ns) Data Path Delay: 2.787ns (logic 0.831ns (29.818%) route 1.956ns (70.182%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.434ns = ( 9.634 - 8.200 ) Source Clock Delay (SCD): 1.636ns Clock Pessimism Removal (CPR): 0.202ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y4 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.636 1.636 ngFEC/g_pm[6].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X154Y306 FDCE r ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X154Y306 FDCE (Prop_fdce_C_Q) 0.259 1.895 r ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/Q net (fo=3, routed) 0.440 2.335 ngFEC/g_pm[6].phase_mon/PS_max_reg_n_0_[1] SLICE_X152Y306 LUT4 (Prop_lut4_I0_O) 0.043 2.378 r ngFEC/g_pm[6].phase_mon/PS_max[9]_i_15__1/O net (fo=1, routed) 0.000 2.378 ngFEC/g_pm[6].phase_mon/PS_max[9]_i_15__1_n_0 SLICE_X152Y306 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.259 2.637 r ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_5__1/CO[3] net (fo=1, routed) 0.000 2.637 ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_5__1_n_0 SLICE_X152Y307 CARRY4 (Prop_carry4_CI_CO[0]) 0.139 2.776 r ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_3__1/CO[0] net (fo=1, routed) 0.710 3.486 ngFEC/g_pm[6].phase_mon/gtOp SLICE_X142Y307 LUT5 (Prop_lut5_I2_O) 0.131 3.617 r ngFEC/g_pm[6].phase_mon/PS_max[9]_i_1__4/O net (fo=10, routed) 0.806 4.423 ngFEC/g_pm[6].phase_mon/PS_max SLICE_X154Y306 FDCE r ngFEC/g_pm[6].phase_mon/PS_max_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 8.200 8.200 r BUFGCTRL_X0Y4 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.434 9.634 ngFEC/g_pm[6].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X154Y306 FDCE r ngFEC/g_pm[6].phase_mon/PS_max_reg[5]/C clock pessimism 0.202 9.836 clock uncertainty -0.035 9.801 SLICE_X154Y306 FDCE (Setup_fdce_C_CE) -0.178 9.623 ngFEC/g_pm[6].phase_mon/PS_max_reg[5] ------------------------------------------------------------------- required time 9.623 arrival time -4.423 ------------------------------------------------------------------- slack 5.200 Slack (MET) : 5.318ns (required time - arrival time) Source: ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/C (rising edge-triggered cell FDCE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[6].phase_mon/PS_max_reg[0]/CE (rising edge-triggered cell FDCE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_2 rise@8.200ns - txWordclkl8_2 rise@0.000ns) Data Path Delay: 2.621ns (logic 0.831ns (31.710%) route 1.790ns (68.290%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: -0.025ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.434ns = ( 9.634 - 8.200 ) Source Clock Delay (SCD): 1.636ns Clock Pessimism Removal (CPR): 0.177ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y4 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.636 1.636 ngFEC/g_pm[6].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X154Y306 FDCE r ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X154Y306 FDCE (Prop_fdce_C_Q) 0.259 1.895 r ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/Q net (fo=3, routed) 0.440 2.335 ngFEC/g_pm[6].phase_mon/PS_max_reg_n_0_[1] SLICE_X152Y306 LUT4 (Prop_lut4_I0_O) 0.043 2.378 r ngFEC/g_pm[6].phase_mon/PS_max[9]_i_15__1/O net (fo=1, routed) 0.000 2.378 ngFEC/g_pm[6].phase_mon/PS_max[9]_i_15__1_n_0 SLICE_X152Y306 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.259 2.637 r ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_5__1/CO[3] net (fo=1, routed) 0.000 2.637 ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_5__1_n_0 SLICE_X152Y307 CARRY4 (Prop_carry4_CI_CO[0]) 0.139 2.776 r ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_3__1/CO[0] net (fo=1, routed) 0.710 3.486 ngFEC/g_pm[6].phase_mon/gtOp SLICE_X142Y307 LUT5 (Prop_lut5_I2_O) 0.131 3.617 r ngFEC/g_pm[6].phase_mon/PS_max[9]_i_1__4/O net (fo=10, routed) 0.640 4.257 ngFEC/g_pm[6].phase_mon/PS_max SLICE_X153Y307 FDCE r ngFEC/g_pm[6].phase_mon/PS_max_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 8.200 8.200 r BUFGCTRL_X0Y4 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.434 9.634 ngFEC/g_pm[6].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X153Y307 FDCE r ngFEC/g_pm[6].phase_mon/PS_max_reg[0]/C clock pessimism 0.177 9.811 clock uncertainty -0.035 9.776 SLICE_X153Y307 FDCE (Setup_fdce_C_CE) -0.201 9.575 ngFEC/g_pm[6].phase_mon/PS_max_reg[0] ------------------------------------------------------------------- required time 9.575 arrival time -4.257 ------------------------------------------------------------------- slack 5.318 Slack (MET) : 5.318ns (required time - arrival time) Source: ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/C (rising edge-triggered cell FDCE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[6].phase_mon/PS_max_reg[3]/CE (rising edge-triggered cell FDCE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_2 rise@8.200ns - txWordclkl8_2 rise@0.000ns) Data Path Delay: 2.621ns (logic 0.831ns (31.710%) route 1.790ns (68.290%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: -0.025ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.434ns = ( 9.634 - 8.200 ) Source Clock Delay (SCD): 1.636ns Clock Pessimism Removal (CPR): 0.177ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y4 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.636 1.636 ngFEC/g_pm[6].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X154Y306 FDCE r ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X154Y306 FDCE (Prop_fdce_C_Q) 0.259 1.895 r ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/Q net (fo=3, routed) 0.440 2.335 ngFEC/g_pm[6].phase_mon/PS_max_reg_n_0_[1] SLICE_X152Y306 LUT4 (Prop_lut4_I0_O) 0.043 2.378 r ngFEC/g_pm[6].phase_mon/PS_max[9]_i_15__1/O net (fo=1, routed) 0.000 2.378 ngFEC/g_pm[6].phase_mon/PS_max[9]_i_15__1_n_0 SLICE_X152Y306 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.259 2.637 r ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_5__1/CO[3] net (fo=1, routed) 0.000 2.637 ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_5__1_n_0 SLICE_X152Y307 CARRY4 (Prop_carry4_CI_CO[0]) 0.139 2.776 r ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_3__1/CO[0] net (fo=1, routed) 0.710 3.486 ngFEC/g_pm[6].phase_mon/gtOp SLICE_X142Y307 LUT5 (Prop_lut5_I2_O) 0.131 3.617 r ngFEC/g_pm[6].phase_mon/PS_max[9]_i_1__4/O net (fo=10, routed) 0.640 4.257 ngFEC/g_pm[6].phase_mon/PS_max SLICE_X153Y307 FDCE r ngFEC/g_pm[6].phase_mon/PS_max_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 8.200 8.200 r BUFGCTRL_X0Y4 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.434 9.634 ngFEC/g_pm[6].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X153Y307 FDCE r ngFEC/g_pm[6].phase_mon/PS_max_reg[3]/C clock pessimism 0.177 9.811 clock uncertainty -0.035 9.776 SLICE_X153Y307 FDCE (Setup_fdce_C_CE) -0.201 9.575 ngFEC/g_pm[6].phase_mon/PS_max_reg[3] ------------------------------------------------------------------- required time 9.575 arrival time -4.257 ------------------------------------------------------------------- slack 5.318 Slack (MET) : 5.318ns (required time - arrival time) Source: ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/C (rising edge-triggered cell FDCE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[6].phase_mon/PS_max_reg[6]/CE (rising edge-triggered cell FDCE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_2 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_2 rise@8.200ns - txWordclkl8_2 rise@0.000ns) Data Path Delay: 2.621ns (logic 0.831ns (31.710%) route 1.790ns (68.290%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: -0.025ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.434ns = ( 9.634 - 8.200 ) Source Clock Delay (SCD): 1.636ns Clock Pessimism Removal (CPR): 0.177ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y4 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.636 1.636 ngFEC/g_pm[6].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X154Y306 FDCE r ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X154Y306 FDCE (Prop_fdce_C_Q) 0.259 1.895 r ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/Q net (fo=3, routed) 0.440 2.335 ngFEC/g_pm[6].phase_mon/PS_max_reg_n_0_[1] SLICE_X152Y306 LUT4 (Prop_lut4_I0_O) 0.043 2.378 r ngFEC/g_pm[6].phase_mon/PS_max[9]_i_15__1/O net (fo=1, routed) 0.000 2.378 ngFEC/g_pm[6].phase_mon/PS_max[9]_i_15__1_n_0 SLICE_X152Y306 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.259 2.637 r ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_5__1/CO[3] net (fo=1, routed) 0.000 2.637 ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_5__1_n_0 SLICE_X152Y307 CARRY4 (Prop_carry4_CI_CO[0]) 0.139 2.776 r ngFEC/g_pm[6].phase_mon/PS_max_reg[9]_i_3__1/CO[0] net (fo=1, routed) 0.710 3.486 ngFEC/g_pm[6].phase_mon/gtOp SLICE_X142Y307 LUT5 (Prop_lut5_I2_O) 0.131 3.617 r ngFEC/g_pm[6].phase_mon/PS_max[9]_i_1__4/O net (fo=10, routed) 0.640 4.257 ngFEC/g_pm[6].phase_mon/PS_max SLICE_X153Y307 FDCE r ngFEC/g_pm[6].phase_mon/PS_max_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 8.200 8.200 r BUFGCTRL_X0Y4 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.434 9.634 ngFEC/g_pm[6].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X153Y307 FDCE r ngFEC/g_pm[6].phase_mon/PS_max_reg[6]/C clock pessimism 0.177 9.811 clock uncertainty -0.035 9.776 SLICE_X153Y307 FDCE (Setup_fdce_C_CE) -0.201 9.575 ngFEC/g_pm[6].phase_mon/PS_max_reg[6] ------------------------------------------------------------------- required time 9.575 arrival time -4.257 ------------------------------------------------------------------- slack 5.318 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.094ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/C (rising edge-triggered cell FDRE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/D (rising edge-triggered cell SRL16E clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_2 rise@0.000ns - txWordclkl8_2 rise@0.000ns) Data Path Delay: 0.207ns (logic 0.100ns (48.254%) route 0.107ns (51.746%)) Logic Levels: 0 Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.951ns Source Clock Delay (SCD): 0.708ns Clock Pessimism Removal (CPR): 0.232ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y4 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.708 0.708 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk SLICE_X161Y61 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X161Y61 FDRE (Prop_fdre_C_Q) 0.100 0.808 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/Q net (fo=1, routed) 0.107 0.915 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/dest_out SLICE_X160Y61 SRL16E r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/D ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y4 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.951 0.951 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X160Y61 SRL16E r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK clock pessimism -0.232 0.719 SLICE_X160Y61 SRL16E (Hold_srl16e_CLK_D) 0.102 0.821 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3 ------------------------------------------------------------------- required time -0.821 arrival time 0.915 ------------------------------------------------------------------- slack 0.094 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D (rising edge-triggered cell FDRE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_2 rise@0.000ns - txWordclkl8_2 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.991ns Source Clock Delay (SCD): 0.743ns Clock Pessimism Removal (CPR): 0.248ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y4 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.743 0.743 ngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/dest_clk SLICE_X143Y309 FDRE r ngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X143Y309 FDRE (Prop_fdre_C_Q) 0.100 0.843 r ngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/Q net (fo=1, routed) 0.055 0.898 ngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff[0] SLICE_X143Y309 FDRE r ngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y4 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.991 0.991 ngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/dest_clk SLICE_X143Y309 FDRE r ngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/C clock pessimism -0.248 0.743 SLICE_X143Y309 FDRE (Hold_fdre_C_D) 0.047 0.790 ngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1] ------------------------------------------------------------------- required time -0.790 arrival time 0.898 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D (rising edge-triggered cell FDRE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_2 rise@0.000ns - txWordclkl8_2 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.951ns Source Clock Delay (SCD): 0.708ns Clock Pessimism Removal (CPR): 0.243ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y4 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.708 0.708 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk SLICE_X161Y61 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X161Y61 FDRE (Prop_fdre_C_Q) 0.100 0.808 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/Q net (fo=1, routed) 0.055 0.863 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff[0] SLICE_X161Y61 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y4 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.951 0.951 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk SLICE_X161Y61 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/C clock pessimism -0.243 0.708 SLICE_X161Y61 FDRE (Hold_fdre_C_D) 0.047 0.755 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1] ------------------------------------------------------------------- required time -0.755 arrival time 0.863 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_2 rise@0.000ns - txWordclkl8_2 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.978ns Source Clock Delay (SCD): 0.736ns Clock Pessimism Removal (CPR): 0.242ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y4 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.736 0.736 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in SLICE_X181Y67 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X181Y67 FDRE (Prop_fdre_C_Q) 0.100 0.836 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q net (fo=1, routed) 0.055 0.891 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync1 SLICE_X181Y67 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y4 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.978 0.978 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in SLICE_X181Y67 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C clock pessimism -0.242 0.736 SLICE_X181Y67 FDRE (Hold_fdre_C_D) 0.047 0.783 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.783 arrival time 0.891 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.109ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[91]/C (rising edge-triggered cell FDCE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[11]/D (rising edge-triggered cell FDCE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_2 rise@0.000ns - txWordclkl8_2 rise@0.000ns) Data Path Delay: 0.231ns (logic 0.128ns (55.341%) route 0.103ns (44.659%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.950ns Source Clock Delay (SCD): 0.707ns Clock Pessimism Removal (CPR): 0.208ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y4 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.707 0.707 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X155Y61 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[91]/C ------------------------------------------------------------------- ------------------- SLICE_X155Y61 FDCE (Prop_fdce_C_Q) 0.100 0.807 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[91]/Q net (fo=1, routed) 0.103 0.910 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/data4[11] SLICE_X158Y61 LUT6 (Prop_lut6_I0_O) 0.028 0.938 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[11]_i_1__8/O net (fo=1, routed) 0.000 0.938 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[11]_i_1__8_n_0 SLICE_X158Y61 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[11]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y4 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.950 0.950 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X158Y61 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[11]/C clock pessimism -0.208 0.742 SLICE_X158Y61 FDCE (Hold_fdce_C_D) 0.087 0.829 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[11] ------------------------------------------------------------------- required time -0.829 arrival time 0.938 ------------------------------------------------------------------- slack 0.109 Slack (MET) : 0.121ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[89]/C (rising edge-triggered cell FDCE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[9]/D (rising edge-triggered cell FDCE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_2 rise@0.000ns - txWordclkl8_2 rise@0.000ns) Data Path Delay: 0.221ns (logic 0.128ns (58.001%) route 0.093ns (41.999%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.947ns Source Clock Delay (SCD): 0.706ns Clock Pessimism Removal (CPR): 0.228ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y4 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.706 0.706 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X153Y62 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[89]/C ------------------------------------------------------------------- ------------------- SLICE_X153Y62 FDCE (Prop_fdce_C_Q) 0.100 0.806 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[89]/Q net (fo=1, routed) 0.093 0.899 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/data4[9] SLICE_X154Y62 LUT6 (Prop_lut6_I0_O) 0.028 0.927 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[9]_i_1__8/O net (fo=1, routed) 0.000 0.927 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[9]_i_1__8_n_0 SLICE_X154Y62 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[9]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y4 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.947 0.947 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X154Y62 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[9]/C clock pessimism -0.228 0.719 SLICE_X154Y62 FDCE (Hold_fdce_C_D) 0.087 0.806 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[9] ------------------------------------------------------------------- required time -0.806 arrival time 0.927 ------------------------------------------------------------------- slack 0.121 Slack (MET) : 0.131ns (arrival time - required time) Source: ngFEC/g_pm[6].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[6].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/D (rising edge-triggered cell FDRE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_2 rise@0.000ns - txWordclkl8_2 rise@0.000ns) Data Path Delay: 0.173ns (logic 0.118ns (68.255%) route 0.055ns (31.745%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.955ns Source Clock Delay (SCD): 0.709ns Clock Pessimism Removal (CPR): 0.246ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y4 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.709 0.709 ngFEC/g_pm[6].phase_mon/sample_PS_Sync_inst/dest_clk SLICE_X126Y306 FDRE r ngFEC/g_pm[6].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X126Y306 FDRE (Prop_fdre_C_Q) 0.118 0.827 r ngFEC/g_pm[6].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/Q net (fo=1, routed) 0.055 0.882 ngFEC/g_pm[6].phase_mon/sample_PS_Sync_inst/syncstages_ff[0] SLICE_X126Y306 FDRE r ngFEC/g_pm[6].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y4 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.955 0.955 ngFEC/g_pm[6].phase_mon/sample_PS_Sync_inst/dest_clk SLICE_X126Y306 FDRE r ngFEC/g_pm[6].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/C clock pessimism -0.246 0.709 SLICE_X126Y306 FDRE (Hold_fdre_C_D) 0.042 0.751 ngFEC/g_pm[6].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1] ------------------------------------------------------------------- required time -0.751 arrival time 0.882 ------------------------------------------------------------------- slack 0.131 Slack (MET) : 0.131ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_2 rise@0.000ns - txWordclkl8_2 rise@0.000ns) Data Path Delay: 0.173ns (logic 0.118ns (68.255%) route 0.055ns (31.745%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.980ns Source Clock Delay (SCD): 0.738ns Clock Pessimism Removal (CPR): 0.242ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y4 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.738 0.738 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in SLICE_X180Y65 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X180Y65 FDRE (Prop_fdre_C_Q) 0.118 0.856 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/Q net (fo=1, routed) 0.055 0.911 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync1 SLICE_X180Y65 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y4 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.980 0.980 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in SLICE_X180Y65 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/C clock pessimism -0.242 0.738 SLICE_X180Y65 FDRE (Hold_fdre_C_D) 0.042 0.780 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.780 arrival time 0.911 ------------------------------------------------------------------- slack 0.131 Slack (MET) : 0.133ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[81]/C (rising edge-triggered cell FDCE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/D (rising edge-triggered cell FDCE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_2 rise@0.000ns - txWordclkl8_2 rise@0.000ns) Data Path Delay: 0.227ns (logic 0.128ns (56.315%) route 0.099ns (43.685%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.034ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.948ns Source Clock Delay (SCD): 0.706ns Clock Pessimism Removal (CPR): 0.208ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y4 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.706 0.706 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X155Y62 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[81]/C ------------------------------------------------------------------- ------------------- SLICE_X155Y62 FDCE (Prop_fdce_C_Q) 0.100 0.806 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[81]/Q net (fo=1, routed) 0.099 0.905 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/data4[1] SLICE_X159Y62 LUT6 (Prop_lut6_I0_O) 0.028 0.933 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[1]_i_1__8/O net (fo=1, routed) 0.000 0.933 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[1]_i_1__8_n_0 SLICE_X159Y62 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y4 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.948 0.948 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/CLK SLICE_X159Y62 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/C clock pessimism -0.208 0.740 SLICE_X159Y62 FDCE (Hold_fdce_C_D) 0.060 0.800 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1] ------------------------------------------------------------------- required time -0.800 arrival time 0.933 ------------------------------------------------------------------- slack 0.133 Slack (MET) : 0.134ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/tx_fsm_reset_done_int_s3_reg/C (rising edge-triggered cell FDRE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_reg/D (rising edge-triggered cell FDRE clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_2 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_2 rise@0.000ns - txWordclkl8_2 rise@0.000ns) Data Path Delay: 0.206ns (logic 0.146ns (70.829%) route 0.060ns (29.171%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.978ns Source Clock Delay (SCD): 0.736ns Clock Pessimism Removal (CPR): 0.231ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y4 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.736 0.736 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/gt0_txusrclk_in SLICE_X180Y67 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/tx_fsm_reset_done_int_s3_reg/C ------------------------------------------------------------------- ------------------- SLICE_X180Y67 FDRE (Prop_fdre_C_Q) 0.118 0.854 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/tx_fsm_reset_done_int_s3_reg/Q net (fo=2, routed) 0.060 0.914 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/tx_fsm_reset_done_int_s3 SLICE_X181Y67 LUT4 (Prop_lut4_I2_O) 0.028 0.942 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_i_1/O net (fo=1, routed) 0.000 0.942 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_i_1_n_0 SLICE_X181Y67 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_reg/D ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y4 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.978 0.978 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/gt0_txusrclk_in SLICE_X181Y67 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_reg/C clock pessimism -0.231 0.747 SLICE_X181Y67 FDRE (Hold_fdre_C_D) 0.061 0.808 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass_reg ------------------------------------------------------------------- required time -0.808 arrival time 0.942 ------------------------------------------------------------------- slack 0.134 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: txWordclkl8_2 Waveform(ns): { 0.000 4.100 } Period(ns): 8.200 Sources: { ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/TXUSRCLK n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y5 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK Min Period n/a GTXE2_CHANNEL/TXUSRCLK2 n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y5 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X160Y61 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X158Y60 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[1]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X154Y60 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.ready_reg/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X155Y59 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[34]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X159Y60 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[51]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X151Y59 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[53]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X155Y59 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[54]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X151Y59 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[58]/C Low Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X160Y61 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK Low Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X160Y61 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X151Y59 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[53]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X151Y59 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[58]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X150Y58 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[59]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X156Y63 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[67]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X150Y58 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[72]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X151Y59 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[73]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X150Y58 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[79]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X154Y61 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[9]/C High Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X160Y61 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X160Y61 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X160Y59 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[93]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X183Y70 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[12]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X183Y70 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[13]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X183Y70 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[14]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X183Y70 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/wait_bypass_count_reg[15]/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X160Y61 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/C High Pulse Width Fast FDRE/C n/a 0.350 4.100 3.750 SLICE_X160Y61 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/C High Pulse Width Slow FDRE/C n/a 0.350 4.100 3.750 SLICE_X155Y60 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/TOGGLE_sync_reg[5]/C --------------------------------------------------------------------------------------------------- From Clock: txWordclkl8_3 To Clock: txWordclkl8_3 Setup : 0 Failing Endpoints, Worst Slack 5.511ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.078ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.458ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.511ns (required time - arrival time) Source: ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/C (rising edge-triggered cell FDPE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[7].phase_mon/PS_min_reg[9]/CE (rising edge-triggered cell FDPE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_3 rise@8.200ns - txWordclkl8_3 rise@0.000ns) Data Path Delay: 2.425ns (logic 0.773ns (31.874%) route 1.652ns (68.126%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: -0.027ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.425ns = ( 9.625 - 8.200 ) Source Clock Delay (SCD): 1.630ns Clock Pessimism Removal (CPR): 0.178ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y5 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.630 1.630 ngFEC/g_pm[7].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X145Y309 FDPE r ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X145Y309 FDPE (Prop_fdpe_C_Q) 0.223 1.853 r ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/Q net (fo=3, routed) 0.538 2.391 ngFEC/g_pm[7].phase_mon/PS_min_reg_n_0_[1] SLICE_X144Y310 LUT4 (Prop_lut4_I0_O) 0.043 2.434 r ngFEC/g_pm[7].phase_mon/PS_min[9]_i_13__5/O net (fo=1, routed) 0.000 2.434 ngFEC/g_pm[7].phase_mon/PS_min[9]_i_13__5_n_0 SLICE_X144Y310 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.246 2.680 r ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_3__5/CO[3] net (fo=1, routed) 0.000 2.680 ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_3__5_n_0 SLICE_X144Y311 CARRY4 (Prop_carry4_CI_CO[0]) 0.133 2.813 r ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_2__5/CO[0] net (fo=1, routed) 0.578 3.391 ngFEC/g_pm[7].phase_mon/ltOp SLICE_X148Y312 LUT5 (Prop_lut5_I2_O) 0.128 3.519 r ngFEC/g_pm[7].phase_mon/PS_min[9]_i_1__5/O net (fo=10, routed) 0.536 4.055 ngFEC/g_pm[7].phase_mon/PS_min SLICE_X145Y311 FDPE r ngFEC/g_pm[7].phase_mon/PS_min_reg[9]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 8.200 8.200 r BUFGCTRL_X0Y5 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.425 9.625 ngFEC/g_pm[7].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X145Y311 FDPE r ngFEC/g_pm[7].phase_mon/PS_min_reg[9]/C clock pessimism 0.178 9.803 clock uncertainty -0.035 9.768 SLICE_X145Y311 FDPE (Setup_fdpe_C_CE) -0.201 9.567 ngFEC/g_pm[7].phase_mon/PS_min_reg[9] ------------------------------------------------------------------- required time 9.567 arrival time -4.055 ------------------------------------------------------------------- slack 5.511 Slack (MET) : 5.541ns (required time - arrival time) Source: ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/C (rising edge-triggered cell FDPE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/CE (rising edge-triggered cell FDPE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_3 rise@8.200ns - txWordclkl8_3 rise@0.000ns) Data Path Delay: 2.422ns (logic 0.773ns (31.913%) route 1.649ns (68.087%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.427ns = ( 9.627 - 8.200 ) Source Clock Delay (SCD): 1.630ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y5 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.630 1.630 ngFEC/g_pm[7].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X145Y309 FDPE r ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X145Y309 FDPE (Prop_fdpe_C_Q) 0.223 1.853 r ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/Q net (fo=3, routed) 0.538 2.391 ngFEC/g_pm[7].phase_mon/PS_min_reg_n_0_[1] SLICE_X144Y310 LUT4 (Prop_lut4_I0_O) 0.043 2.434 r ngFEC/g_pm[7].phase_mon/PS_min[9]_i_13__5/O net (fo=1, routed) 0.000 2.434 ngFEC/g_pm[7].phase_mon/PS_min[9]_i_13__5_n_0 SLICE_X144Y310 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.246 2.680 r ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_3__5/CO[3] net (fo=1, routed) 0.000 2.680 ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_3__5_n_0 SLICE_X144Y311 CARRY4 (Prop_carry4_CI_CO[0]) 0.133 2.813 r ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_2__5/CO[0] net (fo=1, routed) 0.578 3.391 ngFEC/g_pm[7].phase_mon/ltOp SLICE_X148Y312 LUT5 (Prop_lut5_I2_O) 0.128 3.519 r ngFEC/g_pm[7].phase_mon/PS_min[9]_i_1__5/O net (fo=10, routed) 0.533 4.052 ngFEC/g_pm[7].phase_mon/PS_min SLICE_X145Y309 FDPE r ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 8.200 8.200 r BUFGCTRL_X0Y5 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.427 9.627 ngFEC/g_pm[7].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X145Y309 FDPE r ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/C clock pessimism 0.203 9.830 clock uncertainty -0.035 9.795 SLICE_X145Y309 FDPE (Setup_fdpe_C_CE) -0.201 9.594 ngFEC/g_pm[7].phase_mon/PS_min_reg[1] ------------------------------------------------------------------- required time 9.594 arrival time -4.052 ------------------------------------------------------------------- slack 5.541 Slack (MET) : 5.541ns (required time - arrival time) Source: ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/C (rising edge-triggered cell FDPE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[7].phase_mon/PS_min_reg[5]/CE (rising edge-triggered cell FDPE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_3 rise@8.200ns - txWordclkl8_3 rise@0.000ns) Data Path Delay: 2.422ns (logic 0.773ns (31.913%) route 1.649ns (68.087%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: 0.000ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.427ns = ( 9.627 - 8.200 ) Source Clock Delay (SCD): 1.630ns Clock Pessimism Removal (CPR): 0.203ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y5 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.630 1.630 ngFEC/g_pm[7].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X145Y309 FDPE r ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X145Y309 FDPE (Prop_fdpe_C_Q) 0.223 1.853 r ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/Q net (fo=3, routed) 0.538 2.391 ngFEC/g_pm[7].phase_mon/PS_min_reg_n_0_[1] SLICE_X144Y310 LUT4 (Prop_lut4_I0_O) 0.043 2.434 r ngFEC/g_pm[7].phase_mon/PS_min[9]_i_13__5/O net (fo=1, routed) 0.000 2.434 ngFEC/g_pm[7].phase_mon/PS_min[9]_i_13__5_n_0 SLICE_X144Y310 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.246 2.680 r ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_3__5/CO[3] net (fo=1, routed) 0.000 2.680 ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_3__5_n_0 SLICE_X144Y311 CARRY4 (Prop_carry4_CI_CO[0]) 0.133 2.813 r ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_2__5/CO[0] net (fo=1, routed) 0.578 3.391 ngFEC/g_pm[7].phase_mon/ltOp SLICE_X148Y312 LUT5 (Prop_lut5_I2_O) 0.128 3.519 r ngFEC/g_pm[7].phase_mon/PS_min[9]_i_1__5/O net (fo=10, routed) 0.533 4.052 ngFEC/g_pm[7].phase_mon/PS_min SLICE_X145Y309 FDPE r ngFEC/g_pm[7].phase_mon/PS_min_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 8.200 8.200 r BUFGCTRL_X0Y5 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.427 9.627 ngFEC/g_pm[7].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X145Y309 FDPE r ngFEC/g_pm[7].phase_mon/PS_min_reg[5]/C clock pessimism 0.203 9.830 clock uncertainty -0.035 9.795 SLICE_X145Y309 FDPE (Setup_fdpe_C_CE) -0.201 9.594 ngFEC/g_pm[7].phase_mon/PS_min_reg[5] ------------------------------------------------------------------- required time 9.594 arrival time -4.052 ------------------------------------------------------------------- slack 5.541 Slack (MET) : 5.598ns (required time - arrival time) Source: ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/C (rising edge-triggered cell FDPE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[7].phase_mon/PS_min_reg[4]/CE (rising edge-triggered cell FDPE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_3 rise@8.200ns - txWordclkl8_3 rise@0.000ns) Data Path Delay: 2.340ns (logic 0.773ns (33.035%) route 1.567ns (66.965%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: -0.026ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.426ns = ( 9.626 - 8.200 ) Source Clock Delay (SCD): 1.630ns Clock Pessimism Removal (CPR): 0.178ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y5 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.630 1.630 ngFEC/g_pm[7].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X145Y309 FDPE r ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X145Y309 FDPE (Prop_fdpe_C_Q) 0.223 1.853 r ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/Q net (fo=3, routed) 0.538 2.391 ngFEC/g_pm[7].phase_mon/PS_min_reg_n_0_[1] SLICE_X144Y310 LUT4 (Prop_lut4_I0_O) 0.043 2.434 r ngFEC/g_pm[7].phase_mon/PS_min[9]_i_13__5/O net (fo=1, routed) 0.000 2.434 ngFEC/g_pm[7].phase_mon/PS_min[9]_i_13__5_n_0 SLICE_X144Y310 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.246 2.680 r ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_3__5/CO[3] net (fo=1, routed) 0.000 2.680 ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_3__5_n_0 SLICE_X144Y311 CARRY4 (Prop_carry4_CI_CO[0]) 0.133 2.813 r ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_2__5/CO[0] net (fo=1, routed) 0.578 3.391 ngFEC/g_pm[7].phase_mon/ltOp SLICE_X148Y312 LUT5 (Prop_lut5_I2_O) 0.128 3.519 r ngFEC/g_pm[7].phase_mon/PS_min[9]_i_1__5/O net (fo=10, routed) 0.451 3.970 ngFEC/g_pm[7].phase_mon/PS_min SLICE_X145Y310 FDPE r ngFEC/g_pm[7].phase_mon/PS_min_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 8.200 8.200 r BUFGCTRL_X0Y5 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.426 9.626 ngFEC/g_pm[7].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X145Y310 FDPE r ngFEC/g_pm[7].phase_mon/PS_min_reg[4]/C clock pessimism 0.178 9.804 clock uncertainty -0.035 9.769 SLICE_X145Y310 FDPE (Setup_fdpe_C_CE) -0.201 9.568 ngFEC/g_pm[7].phase_mon/PS_min_reg[4] ------------------------------------------------------------------- required time 9.568 arrival time -3.970 ------------------------------------------------------------------- slack 5.598 Slack (MET) : 5.598ns (required time - arrival time) Source: ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/C (rising edge-triggered cell FDPE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[7].phase_mon/PS_min_reg[6]/CE (rising edge-triggered cell FDPE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_3 rise@8.200ns - txWordclkl8_3 rise@0.000ns) Data Path Delay: 2.340ns (logic 0.773ns (33.035%) route 1.567ns (66.965%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: -0.026ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.426ns = ( 9.626 - 8.200 ) Source Clock Delay (SCD): 1.630ns Clock Pessimism Removal (CPR): 0.178ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y5 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.630 1.630 ngFEC/g_pm[7].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X145Y309 FDPE r ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X145Y309 FDPE (Prop_fdpe_C_Q) 0.223 1.853 r ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/Q net (fo=3, routed) 0.538 2.391 ngFEC/g_pm[7].phase_mon/PS_min_reg_n_0_[1] SLICE_X144Y310 LUT4 (Prop_lut4_I0_O) 0.043 2.434 r ngFEC/g_pm[7].phase_mon/PS_min[9]_i_13__5/O net (fo=1, routed) 0.000 2.434 ngFEC/g_pm[7].phase_mon/PS_min[9]_i_13__5_n_0 SLICE_X144Y310 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.246 2.680 r ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_3__5/CO[3] net (fo=1, routed) 0.000 2.680 ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_3__5_n_0 SLICE_X144Y311 CARRY4 (Prop_carry4_CI_CO[0]) 0.133 2.813 r ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_2__5/CO[0] net (fo=1, routed) 0.578 3.391 ngFEC/g_pm[7].phase_mon/ltOp SLICE_X148Y312 LUT5 (Prop_lut5_I2_O) 0.128 3.519 r ngFEC/g_pm[7].phase_mon/PS_min[9]_i_1__5/O net (fo=10, routed) 0.451 3.970 ngFEC/g_pm[7].phase_mon/PS_min SLICE_X145Y310 FDPE r ngFEC/g_pm[7].phase_mon/PS_min_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 8.200 8.200 r BUFGCTRL_X0Y5 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.426 9.626 ngFEC/g_pm[7].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X145Y310 FDPE r ngFEC/g_pm[7].phase_mon/PS_min_reg[6]/C clock pessimism 0.178 9.804 clock uncertainty -0.035 9.769 SLICE_X145Y310 FDPE (Setup_fdpe_C_CE) -0.201 9.568 ngFEC/g_pm[7].phase_mon/PS_min_reg[6] ------------------------------------------------------------------- required time 9.568 arrival time -3.970 ------------------------------------------------------------------- slack 5.598 Slack (MET) : 5.598ns (required time - arrival time) Source: ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/C (rising edge-triggered cell FDPE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[7].phase_mon/PS_min_reg[7]/CE (rising edge-triggered cell FDPE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_3 rise@8.200ns - txWordclkl8_3 rise@0.000ns) Data Path Delay: 2.340ns (logic 0.773ns (33.035%) route 1.567ns (66.965%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: -0.026ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.426ns = ( 9.626 - 8.200 ) Source Clock Delay (SCD): 1.630ns Clock Pessimism Removal (CPR): 0.178ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y5 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.630 1.630 ngFEC/g_pm[7].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X145Y309 FDPE r ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X145Y309 FDPE (Prop_fdpe_C_Q) 0.223 1.853 r ngFEC/g_pm[7].phase_mon/PS_min_reg[1]/Q net (fo=3, routed) 0.538 2.391 ngFEC/g_pm[7].phase_mon/PS_min_reg_n_0_[1] SLICE_X144Y310 LUT4 (Prop_lut4_I0_O) 0.043 2.434 r ngFEC/g_pm[7].phase_mon/PS_min[9]_i_13__5/O net (fo=1, routed) 0.000 2.434 ngFEC/g_pm[7].phase_mon/PS_min[9]_i_13__5_n_0 SLICE_X144Y310 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.246 2.680 r ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_3__5/CO[3] net (fo=1, routed) 0.000 2.680 ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_3__5_n_0 SLICE_X144Y311 CARRY4 (Prop_carry4_CI_CO[0]) 0.133 2.813 r ngFEC/g_pm[7].phase_mon/PS_min_reg[9]_i_2__5/CO[0] net (fo=1, routed) 0.578 3.391 ngFEC/g_pm[7].phase_mon/ltOp SLICE_X148Y312 LUT5 (Prop_lut5_I2_O) 0.128 3.519 r ngFEC/g_pm[7].phase_mon/PS_min[9]_i_1__5/O net (fo=10, routed) 0.451 3.970 ngFEC/g_pm[7].phase_mon/PS_min SLICE_X145Y310 FDPE r ngFEC/g_pm[7].phase_mon/PS_min_reg[7]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 8.200 8.200 r BUFGCTRL_X0Y5 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.426 9.626 ngFEC/g_pm[7].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X145Y310 FDPE r ngFEC/g_pm[7].phase_mon/PS_min_reg[7]/C clock pessimism 0.178 9.804 clock uncertainty -0.035 9.769 SLICE_X145Y310 FDPE (Setup_fdpe_C_CE) -0.201 9.568 ngFEC/g_pm[7].phase_mon/PS_min_reg[7] ------------------------------------------------------------------- required time 9.568 arrival time -3.970 ------------------------------------------------------------------- slack 5.598 Slack (MET) : 5.674ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/C (rising edge-triggered cell FDRE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[5]/CE (rising edge-triggered cell FDCE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_3 rise@8.200ns - txWordclkl8_3 rise@0.000ns) Data Path Delay: 2.238ns (logic 0.359ns (16.042%) route 1.879ns (83.958%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.052ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.413ns = ( 9.613 - 8.200 ) Source Clock Delay (SCD): 1.553ns Clock Pessimism Removal (CPR): 0.088ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y5 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.553 1.553 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X186Y104 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/C ------------------------------------------------------------------- ------------------- SLICE_X186Y104 FDRE (Prop_fdre_C_Q) 0.236 1.789 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/Q net (fo=5, routed) 0.352 2.141 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync[4] SLICE_X184Y104 LUT2 (Prop_lut2_I0_O) 0.123 2.264 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.ready_i_1__9/O net (fo=119, routed) 1.527 3.791 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.ready_i_1__9_n_0 SLICE_X179Y101 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 8.200 8.200 r BUFGCTRL_X0Y5 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.413 9.613 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X179Y101 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[5]/C clock pessimism 0.088 9.701 clock uncertainty -0.035 9.666 SLICE_X179Y101 FDCE (Setup_fdce_C_CE) -0.201 9.465 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[5] ------------------------------------------------------------------- required time 9.465 arrival time -3.791 ------------------------------------------------------------------- slack 5.674 Slack (MET) : 5.674ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/C (rising edge-triggered cell FDRE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[67]/CE (rising edge-triggered cell FDCE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_3 rise@8.200ns - txWordclkl8_3 rise@0.000ns) Data Path Delay: 2.238ns (logic 0.359ns (16.042%) route 1.879ns (83.958%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.052ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.413ns = ( 9.613 - 8.200 ) Source Clock Delay (SCD): 1.553ns Clock Pessimism Removal (CPR): 0.088ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y5 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.553 1.553 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X186Y104 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/C ------------------------------------------------------------------- ------------------- SLICE_X186Y104 FDRE (Prop_fdre_C_Q) 0.236 1.789 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/Q net (fo=5, routed) 0.352 2.141 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync[4] SLICE_X184Y104 LUT2 (Prop_lut2_I0_O) 0.123 2.264 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.ready_i_1__9/O net (fo=119, routed) 1.527 3.791 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.ready_i_1__9_n_0 SLICE_X179Y101 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[67]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 8.200 8.200 r BUFGCTRL_X0Y5 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.413 9.613 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X179Y101 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[67]/C clock pessimism 0.088 9.701 clock uncertainty -0.035 9.666 SLICE_X179Y101 FDCE (Setup_fdce_C_CE) -0.201 9.465 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[67] ------------------------------------------------------------------- required time 9.465 arrival time -3.791 ------------------------------------------------------------------- slack 5.674 Slack (MET) : 5.674ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/C (rising edge-triggered cell FDRE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[75]/CE (rising edge-triggered cell FDCE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_3 rise@8.200ns - txWordclkl8_3 rise@0.000ns) Data Path Delay: 2.238ns (logic 0.359ns (16.042%) route 1.879ns (83.958%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.052ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.413ns = ( 9.613 - 8.200 ) Source Clock Delay (SCD): 1.553ns Clock Pessimism Removal (CPR): 0.088ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y5 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.553 1.553 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X186Y104 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/C ------------------------------------------------------------------- ------------------- SLICE_X186Y104 FDRE (Prop_fdre_C_Q) 0.236 1.789 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/Q net (fo=5, routed) 0.352 2.141 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync[4] SLICE_X184Y104 LUT2 (Prop_lut2_I0_O) 0.123 2.264 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.ready_i_1__9/O net (fo=119, routed) 1.527 3.791 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.ready_i_1__9_n_0 SLICE_X179Y101 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[75]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 8.200 8.200 r BUFGCTRL_X0Y5 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.413 9.613 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X179Y101 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[75]/C clock pessimism 0.088 9.701 clock uncertainty -0.035 9.666 SLICE_X179Y101 FDCE (Setup_fdce_C_CE) -0.201 9.465 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[75] ------------------------------------------------------------------- required time 9.465 arrival time -3.791 ------------------------------------------------------------------- slack 5.674 Slack (MET) : 5.674ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/C (rising edge-triggered cell FDRE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[79]/CE (rising edge-triggered cell FDCE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_3 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_3 rise@8.200ns - txWordclkl8_3 rise@0.000ns) Data Path Delay: 2.238ns (logic 0.359ns (16.042%) route 1.879ns (83.958%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.052ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.413ns = ( 9.613 - 8.200 ) Source Clock Delay (SCD): 1.553ns Clock Pessimism Removal (CPR): 0.088ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y5 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.553 1.553 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X186Y104 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/C ------------------------------------------------------------------- ------------------- SLICE_X186Y104 FDRE (Prop_fdre_C_Q) 0.236 1.789 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/Q net (fo=5, routed) 0.352 2.141 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync[4] SLICE_X184Y104 LUT2 (Prop_lut2_I0_O) 0.123 2.264 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.ready_i_1__9/O net (fo=119, routed) 1.527 3.791 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.ready_i_1__9_n_0 SLICE_X179Y101 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[79]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 8.200 8.200 r BUFGCTRL_X0Y5 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.413 9.613 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X179Y101 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[79]/C clock pessimism 0.088 9.701 clock uncertainty -0.035 9.666 SLICE_X179Y101 FDCE (Setup_fdce_C_CE) -0.201 9.465 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[79] ------------------------------------------------------------------- required time 9.465 arrival time -3.791 ------------------------------------------------------------------- slack 5.674 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.078ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/C (rising edge-triggered cell FDRE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/D (rising edge-triggered cell SRL16E clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_3 rise@0.000ns - txWordclkl8_3 rise@0.000ns) Data Path Delay: 0.194ns (logic 0.100ns (51.581%) route 0.094ns (48.419%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.914ns Source Clock Delay (SCD): 0.690ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y5 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.690 0.690 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk SLICE_X185Y104 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X185Y104 FDRE (Prop_fdre_C_Q) 0.100 0.790 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[3]/Q net (fo=1, routed) 0.094 0.884 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/dest_out SLICE_X186Y104 SRL16E r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/D ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y5 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.914 0.914 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X186Y104 SRL16E r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK clock pessimism -0.210 0.704 SLICE_X186Y104 SRL16E (Hold_srl16e_CLK_D) 0.102 0.806 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3 ------------------------------------------------------------------- required time -0.806 arrival time 0.884 ------------------------------------------------------------------- slack 0.078 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D (rising edge-triggered cell FDRE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_3 rise@0.000ns - txWordclkl8_3 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.993ns Source Clock Delay (SCD): 0.746ns Clock Pessimism Removal (CPR): 0.247ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y5 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.746 0.746 ngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst/dest_clk SLICE_X149Y314 FDRE r ngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X149Y314 FDRE (Prop_fdre_C_Q) 0.100 0.846 r ngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/Q net (fo=1, routed) 0.055 0.901 ngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff[0] SLICE_X149Y314 FDRE r ngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y5 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.993 0.993 ngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst/dest_clk SLICE_X149Y314 FDRE r ngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/C clock pessimism -0.247 0.746 SLICE_X149Y314 FDRE (Hold_fdre_C_D) 0.047 0.793 ngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1] ------------------------------------------------------------------- required time -0.793 arrival time 0.901 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D (rising edge-triggered cell FDRE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_3 rise@0.000ns - txWordclkl8_3 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.914ns Source Clock Delay (SCD): 0.690ns Clock Pessimism Removal (CPR): 0.224ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y5 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.690 0.690 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk SLICE_X185Y104 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X185Y104 FDRE (Prop_fdre_C_Q) 0.100 0.790 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/Q net (fo=1, routed) 0.055 0.845 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff[0] SLICE_X185Y104 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y5 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.914 0.914 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk SLICE_X185Y104 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/C clock pessimism -0.224 0.690 SLICE_X185Y104 FDRE (Hold_fdre_C_D) 0.047 0.737 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1] ------------------------------------------------------------------- required time -0.737 arrival time 0.845 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_3 rise@0.000ns - txWordclkl8_3 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.974ns Source Clock Delay (SCD): 0.732ns Clock Pessimism Removal (CPR): 0.242ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y5 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.732 0.732 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in SLICE_X181Y71 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X181Y71 FDRE (Prop_fdre_C_Q) 0.100 0.832 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q net (fo=1, routed) 0.055 0.887 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync1 SLICE_X181Y71 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y5 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.974 0.974 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in SLICE_X181Y71 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C clock pessimism -0.242 0.732 SLICE_X181Y71 FDRE (Hold_fdre_C_D) 0.047 0.779 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.779 arrival time 0.887 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.126ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[118]/C (rising edge-triggered cell FDCE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/D (rising edge-triggered cell FDCE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_3 rise@0.000ns - txWordclkl8_3 rise@0.000ns) Data Path Delay: 0.228ns (logic 0.128ns (56.068%) route 0.100ns (43.932%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.915ns Source Clock Delay (SCD): 0.690ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y5 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.690 0.690 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X181Y104 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[118]/C ------------------------------------------------------------------- ------------------- SLICE_X181Y104 FDCE (Prop_fdce_C_Q) 0.100 0.790 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[118]/Q net (fo=1, routed) 0.100 0.890 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/data5[18] SLICE_X180Y102 LUT6 (Prop_lut6_I2_O) 0.028 0.918 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[18]_i_1__9/O net (fo=1, routed) 0.000 0.918 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[18]_i_1__9_n_0 SLICE_X180Y102 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y5 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.915 0.915 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X180Y102 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18]/C clock pessimism -0.210 0.705 SLICE_X180Y102 FDCE (Hold_fdce_C_D) 0.087 0.792 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[18] ------------------------------------------------------------------- required time -0.792 arrival time 0.918 ------------------------------------------------------------------- slack 0.126 Slack (MET) : 0.131ns (arrival time - required time) Source: ngFEC/g_pm[7].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[7].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/D (rising edge-triggered cell FDRE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_3 rise@0.000ns - txWordclkl8_3 rise@0.000ns) Data Path Delay: 0.173ns (logic 0.118ns (68.255%) route 0.055ns (31.745%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.997ns Source Clock Delay (SCD): 0.750ns Clock Pessimism Removal (CPR): 0.247ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y5 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.750 0.750 ngFEC/g_pm[7].phase_mon/sample_PS_Sync_inst/dest_clk SLICE_X158Y311 FDRE r ngFEC/g_pm[7].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X158Y311 FDRE (Prop_fdre_C_Q) 0.118 0.868 r ngFEC/g_pm[7].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/Q net (fo=1, routed) 0.055 0.923 ngFEC/g_pm[7].phase_mon/sample_PS_Sync_inst/syncstages_ff[0] SLICE_X158Y311 FDRE r ngFEC/g_pm[7].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y5 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.997 0.997 ngFEC/g_pm[7].phase_mon/sample_PS_Sync_inst/dest_clk SLICE_X158Y311 FDRE r ngFEC/g_pm[7].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/C clock pessimism -0.247 0.750 SLICE_X158Y311 FDRE (Hold_fdre_C_D) 0.042 0.792 ngFEC/g_pm[7].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1] ------------------------------------------------------------------- required time -0.792 arrival time 0.923 ------------------------------------------------------------------- slack 0.131 Slack (MET) : 0.131ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_3 rise@0.000ns - txWordclkl8_3 rise@0.000ns) Data Path Delay: 0.173ns (logic 0.118ns (68.255%) route 0.055ns (31.745%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.973ns Source Clock Delay (SCD): 0.731ns Clock Pessimism Removal (CPR): 0.242ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y5 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.731 0.731 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in SLICE_X186Y72 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X186Y72 FDRE (Prop_fdre_C_Q) 0.118 0.849 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/Q net (fo=1, routed) 0.055 0.904 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync1 SLICE_X186Y72 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y5 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.973 0.973 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in SLICE_X186Y72 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/C clock pessimism -0.242 0.731 SLICE_X186Y72 FDRE (Hold_fdre_C_D) 0.042 0.773 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.773 arrival time 0.904 ------------------------------------------------------------------- slack 0.131 Slack (MET) : 0.137ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[86]/C (rising edge-triggered cell FDCE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/D (rising edge-triggered cell FDCE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_3 rise@0.000ns - txWordclkl8_3 rise@0.000ns) Data Path Delay: 0.260ns (logic 0.128ns (49.243%) route 0.132ns (50.758%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.915ns Source Clock Delay (SCD): 0.691ns Clock Pessimism Removal (CPR): 0.188ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y5 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.691 0.691 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X185Y102 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[86]/C ------------------------------------------------------------------- ------------------- SLICE_X185Y102 FDCE (Prop_fdce_C_Q) 0.100 0.791 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[86]/Q net (fo=1, routed) 0.132 0.923 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/data4[6] SLICE_X182Y102 LUT6 (Prop_lut6_I0_O) 0.028 0.951 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[6]_i_1__9/O net (fo=1, routed) 0.000 0.951 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[6]_i_1__9_n_0 SLICE_X182Y102 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y5 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.915 0.915 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X182Y102 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6]/C clock pessimism -0.188 0.727 SLICE_X182Y102 FDCE (Hold_fdce_C_D) 0.087 0.814 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[6] ------------------------------------------------------------------- required time -0.814 arrival time 0.951 ------------------------------------------------------------------- slack 0.137 Slack (MET) : 0.140ns (arrival time - required time) Source: ngFEC/g_pm[7].phase_mon/inh_cntr_reg[0]/C (rising edge-triggered cell FDPE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[7].phase_mon/inh_cntr_reg[2]/D (rising edge-triggered cell FDPE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_3 rise@0.000ns - txWordclkl8_3 rise@0.000ns) Data Path Delay: 0.226ns (logic 0.130ns (57.601%) route 0.096ns (42.399%)) Logic Levels: 1 (LUT5=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.993ns Source Clock Delay (SCD): 0.746ns Clock Pessimism Removal (CPR): 0.236ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y5 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.746 0.746 ngFEC/g_pm[7].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X148Y313 FDPE r ngFEC/g_pm[7].phase_mon/inh_cntr_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X148Y313 FDPE (Prop_fdpe_C_Q) 0.100 0.846 r ngFEC/g_pm[7].phase_mon/inh_cntr_reg[0]/Q net (fo=5, routed) 0.096 0.942 ngFEC/g_pm[7].phase_mon/inh_cntr_reg_n_0_[0] SLICE_X149Y313 LUT5 (Prop_lut5_I3_O) 0.030 0.972 r ngFEC/g_pm[7].phase_mon/inh_cntr[2]_i_1__5/O net (fo=1, routed) 0.000 0.972 ngFEC/g_pm[7].phase_mon/p_0_in__0[2] SLICE_X149Y313 FDPE r ngFEC/g_pm[7].phase_mon/inh_cntr_reg[2]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y5 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.993 0.993 ngFEC/g_pm[7].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X149Y313 FDPE r ngFEC/g_pm[7].phase_mon/inh_cntr_reg[2]/C clock pessimism -0.236 0.757 SLICE_X149Y313 FDPE (Hold_fdpe_C_D) 0.075 0.832 ngFEC/g_pm[7].phase_mon/inh_cntr_reg[2] ------------------------------------------------------------------- required time -0.832 arrival time 0.972 ------------------------------------------------------------------- slack 0.140 Slack (MET) : 0.152ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[81]/C (rising edge-triggered cell FDCE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/D (rising edge-triggered cell FDCE clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_3 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_3 rise@0.000ns - txWordclkl8_3 rise@0.000ns) Data Path Delay: 0.253ns (logic 0.157ns (62.140%) route 0.096ns (37.860%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.915ns Source Clock Delay (SCD): 0.691ns Clock Pessimism Removal (CPR): 0.210ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y5 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.691 0.691 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X181Y101 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[81]/C ------------------------------------------------------------------- ------------------- SLICE_X181Y101 FDCE (Prop_fdce_C_Q) 0.091 0.782 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[81]/Q net (fo=1, routed) 0.096 0.878 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/data4[1] SLICE_X182Y100 LUT6 (Prop_lut6_I0_O) 0.066 0.944 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[1]_i_1__9/O net (fo=1, routed) 0.000 0.944 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[1]_i_1__9_n_0 SLICE_X182Y100 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y5 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.915 0.915 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/CLK SLICE_X182Y100 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/C clock pessimism -0.210 0.705 SLICE_X182Y100 FDCE (Hold_fdce_C_D) 0.087 0.792 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1] ------------------------------------------------------------------- required time -0.792 arrival time 0.944 ------------------------------------------------------------------- slack 0.152 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: txWordclkl8_3 Waveform(ns): { 0.000 4.100 } Period(ns): 8.200 Sources: { ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/TXUSRCLK n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y6 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK Min Period n/a GTXE2_CHANNEL/TXUSRCLK2 n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y6 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X186Y104 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X184Y103 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[1]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X183Y104 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.ready_reg/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X178Y101 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[59]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X177Y103 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[63]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X177Y101 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[65]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X179Y102 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[70]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X177Y102 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[74]/C Low Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X186Y104 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK Low Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X186Y104 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X149Y308 ngFEC/g_pm[7].phase_mon/PS_max_reg[6]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X149Y308 ngFEC/g_pm[7].phase_mon/PS_max_reg[7]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X151Y312 ngFEC/g_pm[7].phase_mon/en_chk_reg[2]/C Low Pulse Width Fast FDRE/C n/a 0.400 4.100 3.700 SLICE_X149Y314 ngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/C Low Pulse Width Fast FDRE/C n/a 0.400 4.100 3.700 SLICE_X149Y314 ngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[2]/C Low Pulse Width Fast FDPE/C n/a 0.400 4.100 3.700 SLICE_X149Y313 ngFEC/g_pm[7].phase_mon/inh_cntr_reg[2]/C Low Pulse Width Fast FDRE/C n/a 0.400 4.100 3.700 SLICE_X186Y104 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X184Y103 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[1]/C High Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X186Y104 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X186Y104 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X180Y101 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X180Y102 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[10]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X179Y100 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[12]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X182Y102 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[13]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X180Y102 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[14]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X180Y101 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[15]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X182Y102 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[16]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X180Y102 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[17]/C --------------------------------------------------------------------------------------------------- From Clock: txWordclkl8_4 To Clock: txWordclkl8_4 Setup : 0 Failing Endpoints, Worst Slack 5.063ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.084ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.458ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.063ns (required time - arrival time) Source: ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/C (rising edge-triggered cell FDPE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[8].phase_mon/PS_min_reg[1]/CE (rising edge-triggered cell FDPE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_4 rise@8.200ns - txWordclkl8_4 rise@0.000ns) Data Path Delay: 2.819ns (logic 0.831ns (29.479%) route 1.988ns (70.521%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: -0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.362ns = ( 9.562 - 8.200 ) Source Clock Delay (SCD): 1.620ns Clock Pessimism Removal (CPR): 0.153ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y6 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 1.620 1.620 ngFEC/g_pm[8].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X132Y310 FDPE r ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X132Y310 FDPE (Prop_fdpe_C_Q) 0.259 1.879 r ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/Q net (fo=3, routed) 0.466 2.345 ngFEC/g_pm[8].phase_mon/PS_min_reg_n_0_[0] SLICE_X131Y310 LUT4 (Prop_lut4_I2_O) 0.043 2.388 r ngFEC/g_pm[8].phase_mon/PS_min[9]_i_13__6/O net (fo=1, routed) 0.000 2.388 ngFEC/g_pm[8].phase_mon/PS_min[9]_i_13__6_n_0 SLICE_X131Y310 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.259 2.647 r ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_3__6/CO[3] net (fo=1, routed) 0.000 2.647 ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_3__6_n_0 SLICE_X131Y311 CARRY4 (Prop_carry4_CI_CO[0]) 0.139 2.786 r ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_2__6/CO[0] net (fo=1, routed) 0.706 3.492 ngFEC/g_pm[8].phase_mon/ltOp SLICE_X142Y311 LUT5 (Prop_lut5_I2_O) 0.131 3.623 r ngFEC/g_pm[8].phase_mon/PS_min[9]_i_1__6/O net (fo=10, routed) 0.816 4.439 ngFEC/g_pm[8].phase_mon/PS_min SLICE_X130Y310 FDPE r ngFEC/g_pm[8].phase_mon/PS_min_reg[1]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 8.200 8.200 r BUFGCTRL_X0Y6 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 1.362 9.562 ngFEC/g_pm[8].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X130Y310 FDPE r ngFEC/g_pm[8].phase_mon/PS_min_reg[1]/C clock pessimism 0.153 9.715 clock uncertainty -0.035 9.680 SLICE_X130Y310 FDPE (Setup_fdpe_C_CE) -0.178 9.502 ngFEC/g_pm[8].phase_mon/PS_min_reg[1] ------------------------------------------------------------------- required time 9.502 arrival time -4.439 ------------------------------------------------------------------- slack 5.063 Slack (MET) : 5.063ns (required time - arrival time) Source: ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/C (rising edge-triggered cell FDPE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[8].phase_mon/PS_min_reg[2]/CE (rising edge-triggered cell FDPE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_4 rise@8.200ns - txWordclkl8_4 rise@0.000ns) Data Path Delay: 2.819ns (logic 0.831ns (29.479%) route 1.988ns (70.521%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: -0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.362ns = ( 9.562 - 8.200 ) Source Clock Delay (SCD): 1.620ns Clock Pessimism Removal (CPR): 0.153ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y6 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 1.620 1.620 ngFEC/g_pm[8].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X132Y310 FDPE r ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X132Y310 FDPE (Prop_fdpe_C_Q) 0.259 1.879 r ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/Q net (fo=3, routed) 0.466 2.345 ngFEC/g_pm[8].phase_mon/PS_min_reg_n_0_[0] SLICE_X131Y310 LUT4 (Prop_lut4_I2_O) 0.043 2.388 r ngFEC/g_pm[8].phase_mon/PS_min[9]_i_13__6/O net (fo=1, routed) 0.000 2.388 ngFEC/g_pm[8].phase_mon/PS_min[9]_i_13__6_n_0 SLICE_X131Y310 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.259 2.647 r ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_3__6/CO[3] net (fo=1, routed) 0.000 2.647 ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_3__6_n_0 SLICE_X131Y311 CARRY4 (Prop_carry4_CI_CO[0]) 0.139 2.786 r ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_2__6/CO[0] net (fo=1, routed) 0.706 3.492 ngFEC/g_pm[8].phase_mon/ltOp SLICE_X142Y311 LUT5 (Prop_lut5_I2_O) 0.131 3.623 r ngFEC/g_pm[8].phase_mon/PS_min[9]_i_1__6/O net (fo=10, routed) 0.816 4.439 ngFEC/g_pm[8].phase_mon/PS_min SLICE_X130Y310 FDPE r ngFEC/g_pm[8].phase_mon/PS_min_reg[2]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 8.200 8.200 r BUFGCTRL_X0Y6 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 1.362 9.562 ngFEC/g_pm[8].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X130Y310 FDPE r ngFEC/g_pm[8].phase_mon/PS_min_reg[2]/C clock pessimism 0.153 9.715 clock uncertainty -0.035 9.680 SLICE_X130Y310 FDPE (Setup_fdpe_C_CE) -0.178 9.502 ngFEC/g_pm[8].phase_mon/PS_min_reg[2] ------------------------------------------------------------------- required time 9.502 arrival time -4.439 ------------------------------------------------------------------- slack 5.063 Slack (MET) : 5.063ns (required time - arrival time) Source: ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/C (rising edge-triggered cell FDPE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[8].phase_mon/PS_min_reg[3]/CE (rising edge-triggered cell FDPE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_4 rise@8.200ns - txWordclkl8_4 rise@0.000ns) Data Path Delay: 2.819ns (logic 0.831ns (29.479%) route 1.988ns (70.521%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: -0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.362ns = ( 9.562 - 8.200 ) Source Clock Delay (SCD): 1.620ns Clock Pessimism Removal (CPR): 0.153ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y6 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 1.620 1.620 ngFEC/g_pm[8].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X132Y310 FDPE r ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X132Y310 FDPE (Prop_fdpe_C_Q) 0.259 1.879 r ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/Q net (fo=3, routed) 0.466 2.345 ngFEC/g_pm[8].phase_mon/PS_min_reg_n_0_[0] SLICE_X131Y310 LUT4 (Prop_lut4_I2_O) 0.043 2.388 r ngFEC/g_pm[8].phase_mon/PS_min[9]_i_13__6/O net (fo=1, routed) 0.000 2.388 ngFEC/g_pm[8].phase_mon/PS_min[9]_i_13__6_n_0 SLICE_X131Y310 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.259 2.647 r ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_3__6/CO[3] net (fo=1, routed) 0.000 2.647 ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_3__6_n_0 SLICE_X131Y311 CARRY4 (Prop_carry4_CI_CO[0]) 0.139 2.786 r ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_2__6/CO[0] net (fo=1, routed) 0.706 3.492 ngFEC/g_pm[8].phase_mon/ltOp SLICE_X142Y311 LUT5 (Prop_lut5_I2_O) 0.131 3.623 r ngFEC/g_pm[8].phase_mon/PS_min[9]_i_1__6/O net (fo=10, routed) 0.816 4.439 ngFEC/g_pm[8].phase_mon/PS_min SLICE_X130Y310 FDPE r ngFEC/g_pm[8].phase_mon/PS_min_reg[3]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 8.200 8.200 r BUFGCTRL_X0Y6 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 1.362 9.562 ngFEC/g_pm[8].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X130Y310 FDPE r ngFEC/g_pm[8].phase_mon/PS_min_reg[3]/C clock pessimism 0.153 9.715 clock uncertainty -0.035 9.680 SLICE_X130Y310 FDPE (Setup_fdpe_C_CE) -0.178 9.502 ngFEC/g_pm[8].phase_mon/PS_min_reg[3] ------------------------------------------------------------------- required time 9.502 arrival time -4.439 ------------------------------------------------------------------- slack 5.063 Slack (MET) : 5.063ns (required time - arrival time) Source: ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/C (rising edge-triggered cell FDPE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[8].phase_mon/PS_min_reg[4]/CE (rising edge-triggered cell FDPE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_4 rise@8.200ns - txWordclkl8_4 rise@0.000ns) Data Path Delay: 2.819ns (logic 0.831ns (29.479%) route 1.988ns (70.521%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: -0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.362ns = ( 9.562 - 8.200 ) Source Clock Delay (SCD): 1.620ns Clock Pessimism Removal (CPR): 0.153ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y6 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 1.620 1.620 ngFEC/g_pm[8].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X132Y310 FDPE r ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X132Y310 FDPE (Prop_fdpe_C_Q) 0.259 1.879 r ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/Q net (fo=3, routed) 0.466 2.345 ngFEC/g_pm[8].phase_mon/PS_min_reg_n_0_[0] SLICE_X131Y310 LUT4 (Prop_lut4_I2_O) 0.043 2.388 r ngFEC/g_pm[8].phase_mon/PS_min[9]_i_13__6/O net (fo=1, routed) 0.000 2.388 ngFEC/g_pm[8].phase_mon/PS_min[9]_i_13__6_n_0 SLICE_X131Y310 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.259 2.647 r ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_3__6/CO[3] net (fo=1, routed) 0.000 2.647 ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_3__6_n_0 SLICE_X131Y311 CARRY4 (Prop_carry4_CI_CO[0]) 0.139 2.786 r ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_2__6/CO[0] net (fo=1, routed) 0.706 3.492 ngFEC/g_pm[8].phase_mon/ltOp SLICE_X142Y311 LUT5 (Prop_lut5_I2_O) 0.131 3.623 r ngFEC/g_pm[8].phase_mon/PS_min[9]_i_1__6/O net (fo=10, routed) 0.816 4.439 ngFEC/g_pm[8].phase_mon/PS_min SLICE_X130Y310 FDPE r ngFEC/g_pm[8].phase_mon/PS_min_reg[4]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 8.200 8.200 r BUFGCTRL_X0Y6 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 1.362 9.562 ngFEC/g_pm[8].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X130Y310 FDPE r ngFEC/g_pm[8].phase_mon/PS_min_reg[4]/C clock pessimism 0.153 9.715 clock uncertainty -0.035 9.680 SLICE_X130Y310 FDPE (Setup_fdpe_C_CE) -0.178 9.502 ngFEC/g_pm[8].phase_mon/PS_min_reg[4] ------------------------------------------------------------------- required time 9.502 arrival time -4.439 ------------------------------------------------------------------- slack 5.063 Slack (MET) : 5.063ns (required time - arrival time) Source: ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/C (rising edge-triggered cell FDPE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[8].phase_mon/PS_min_reg[6]/CE (rising edge-triggered cell FDPE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_4 rise@8.200ns - txWordclkl8_4 rise@0.000ns) Data Path Delay: 2.819ns (logic 0.831ns (29.479%) route 1.988ns (70.521%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: -0.105ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.362ns = ( 9.562 - 8.200 ) Source Clock Delay (SCD): 1.620ns Clock Pessimism Removal (CPR): 0.153ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y6 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 1.620 1.620 ngFEC/g_pm[8].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X132Y310 FDPE r ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X132Y310 FDPE (Prop_fdpe_C_Q) 0.259 1.879 r ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/Q net (fo=3, routed) 0.466 2.345 ngFEC/g_pm[8].phase_mon/PS_min_reg_n_0_[0] SLICE_X131Y310 LUT4 (Prop_lut4_I2_O) 0.043 2.388 r ngFEC/g_pm[8].phase_mon/PS_min[9]_i_13__6/O net (fo=1, routed) 0.000 2.388 ngFEC/g_pm[8].phase_mon/PS_min[9]_i_13__6_n_0 SLICE_X131Y310 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.259 2.647 r ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_3__6/CO[3] net (fo=1, routed) 0.000 2.647 ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_3__6_n_0 SLICE_X131Y311 CARRY4 (Prop_carry4_CI_CO[0]) 0.139 2.786 r ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_2__6/CO[0] net (fo=1, routed) 0.706 3.492 ngFEC/g_pm[8].phase_mon/ltOp SLICE_X142Y311 LUT5 (Prop_lut5_I2_O) 0.131 3.623 r ngFEC/g_pm[8].phase_mon/PS_min[9]_i_1__6/O net (fo=10, routed) 0.816 4.439 ngFEC/g_pm[8].phase_mon/PS_min SLICE_X130Y310 FDPE r ngFEC/g_pm[8].phase_mon/PS_min_reg[6]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 8.200 8.200 r BUFGCTRL_X0Y6 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 1.362 9.562 ngFEC/g_pm[8].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X130Y310 FDPE r ngFEC/g_pm[8].phase_mon/PS_min_reg[6]/C clock pessimism 0.153 9.715 clock uncertainty -0.035 9.680 SLICE_X130Y310 FDPE (Setup_fdpe_C_CE) -0.178 9.502 ngFEC/g_pm[8].phase_mon/PS_min_reg[6] ------------------------------------------------------------------- required time 9.502 arrival time -4.439 ------------------------------------------------------------------- slack 5.063 Slack (MET) : 5.315ns (required time - arrival time) Source: ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/C (rising edge-triggered cell FDPE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[8].phase_mon/PS_min_reg[9]/CE (rising edge-triggered cell FDPE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_4 rise@8.200ns - txWordclkl8_4 rise@0.000ns) Data Path Delay: 2.565ns (logic 0.831ns (32.395%) route 1.734ns (67.605%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: -0.106ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.361ns = ( 9.561 - 8.200 ) Source Clock Delay (SCD): 1.620ns Clock Pessimism Removal (CPR): 0.153ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y6 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 1.620 1.620 ngFEC/g_pm[8].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X132Y310 FDPE r ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X132Y310 FDPE (Prop_fdpe_C_Q) 0.259 1.879 r ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/Q net (fo=3, routed) 0.466 2.345 ngFEC/g_pm[8].phase_mon/PS_min_reg_n_0_[0] SLICE_X131Y310 LUT4 (Prop_lut4_I2_O) 0.043 2.388 r ngFEC/g_pm[8].phase_mon/PS_min[9]_i_13__6/O net (fo=1, routed) 0.000 2.388 ngFEC/g_pm[8].phase_mon/PS_min[9]_i_13__6_n_0 SLICE_X131Y310 CARRY4 (Prop_carry4_S[0]_CO[3]) 0.259 2.647 r ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_3__6/CO[3] net (fo=1, routed) 0.000 2.647 ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_3__6_n_0 SLICE_X131Y311 CARRY4 (Prop_carry4_CI_CO[0]) 0.139 2.786 r ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_2__6/CO[0] net (fo=1, routed) 0.706 3.492 ngFEC/g_pm[8].phase_mon/ltOp SLICE_X142Y311 LUT5 (Prop_lut5_I2_O) 0.131 3.623 r ngFEC/g_pm[8].phase_mon/PS_min[9]_i_1__6/O net (fo=10, routed) 0.562 4.185 ngFEC/g_pm[8].phase_mon/PS_min SLICE_X130Y311 FDPE r ngFEC/g_pm[8].phase_mon/PS_min_reg[9]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 8.200 8.200 r BUFGCTRL_X0Y6 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 1.361 9.561 ngFEC/g_pm[8].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X130Y311 FDPE r ngFEC/g_pm[8].phase_mon/PS_min_reg[9]/C clock pessimism 0.153 9.714 clock uncertainty -0.035 9.679 SLICE_X130Y311 FDPE (Setup_fdpe_C_CE) -0.178 9.501 ngFEC/g_pm[8].phase_mon/PS_min_reg[9] ------------------------------------------------------------------- required time 9.501 arrival time -4.185 ------------------------------------------------------------------- slack 5.315 Slack (MET) : 5.377ns (required time - arrival time) Source: ngFEC/g_pm[8].phase_mon/PS_min_reg[3]/C (rising edge-triggered cell FDPE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/CE (rising edge-triggered cell FDPE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_4 rise@8.200ns - txWordclkl8_4 rise@0.000ns) Data Path Delay: 2.616ns (logic 0.839ns (32.069%) route 1.777ns (67.931%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: 0.007ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.418ns = ( 9.618 - 8.200 ) Source Clock Delay (SCD): 1.564ns Clock Pessimism Removal (CPR): 0.153ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y6 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 1.564 1.564 ngFEC/g_pm[8].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X130Y310 FDPE r ngFEC/g_pm[8].phase_mon/PS_min_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X130Y310 FDPE (Prop_fdpe_C_Q) 0.259 1.823 r ngFEC/g_pm[8].phase_mon/PS_min_reg[3]/Q net (fo=3, routed) 0.469 2.292 ngFEC/g_pm[8].phase_mon/PS_min_reg_n_0_[3] SLICE_X131Y310 LUT4 (Prop_lut4_I0_O) 0.043 2.335 r ngFEC/g_pm[8].phase_mon/PS_min[9]_i_12__6/O net (fo=1, routed) 0.000 2.335 ngFEC/g_pm[8].phase_mon/PS_min[9]_i_12__6_n_0 SLICE_X131Y310 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.267 2.602 r ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_3__6/CO[3] net (fo=1, routed) 0.000 2.602 ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_3__6_n_0 SLICE_X131Y311 CARRY4 (Prop_carry4_CI_CO[0]) 0.139 2.741 r ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_2__6/CO[0] net (fo=1, routed) 0.706 3.447 ngFEC/g_pm[8].phase_mon/ltOp SLICE_X142Y311 LUT5 (Prop_lut5_I2_O) 0.131 3.578 r ngFEC/g_pm[8].phase_mon/PS_min[9]_i_1__6/O net (fo=10, routed) 0.602 4.180 ngFEC/g_pm[8].phase_mon/PS_min SLICE_X132Y310 FDPE r ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 8.200 8.200 r BUFGCTRL_X0Y6 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 1.418 9.618 ngFEC/g_pm[8].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X132Y310 FDPE r ngFEC/g_pm[8].phase_mon/PS_min_reg[0]/C clock pessimism 0.153 9.771 clock uncertainty -0.035 9.736 SLICE_X132Y310 FDPE (Setup_fdpe_C_CE) -0.178 9.558 ngFEC/g_pm[8].phase_mon/PS_min_reg[0] ------------------------------------------------------------------- required time 9.558 arrival time -4.180 ------------------------------------------------------------------- slack 5.377 Slack (MET) : 5.377ns (required time - arrival time) Source: ngFEC/g_pm[8].phase_mon/PS_min_reg[3]/C (rising edge-triggered cell FDPE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[8].phase_mon/PS_min_reg[5]/CE (rising edge-triggered cell FDPE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_4 rise@8.200ns - txWordclkl8_4 rise@0.000ns) Data Path Delay: 2.616ns (logic 0.839ns (32.069%) route 1.777ns (67.931%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: 0.007ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.418ns = ( 9.618 - 8.200 ) Source Clock Delay (SCD): 1.564ns Clock Pessimism Removal (CPR): 0.153ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y6 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 1.564 1.564 ngFEC/g_pm[8].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X130Y310 FDPE r ngFEC/g_pm[8].phase_mon/PS_min_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X130Y310 FDPE (Prop_fdpe_C_Q) 0.259 1.823 r ngFEC/g_pm[8].phase_mon/PS_min_reg[3]/Q net (fo=3, routed) 0.469 2.292 ngFEC/g_pm[8].phase_mon/PS_min_reg_n_0_[3] SLICE_X131Y310 LUT4 (Prop_lut4_I0_O) 0.043 2.335 r ngFEC/g_pm[8].phase_mon/PS_min[9]_i_12__6/O net (fo=1, routed) 0.000 2.335 ngFEC/g_pm[8].phase_mon/PS_min[9]_i_12__6_n_0 SLICE_X131Y310 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.267 2.602 r ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_3__6/CO[3] net (fo=1, routed) 0.000 2.602 ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_3__6_n_0 SLICE_X131Y311 CARRY4 (Prop_carry4_CI_CO[0]) 0.139 2.741 r ngFEC/g_pm[8].phase_mon/PS_min_reg[9]_i_2__6/CO[0] net (fo=1, routed) 0.706 3.447 ngFEC/g_pm[8].phase_mon/ltOp SLICE_X142Y311 LUT5 (Prop_lut5_I2_O) 0.131 3.578 r ngFEC/g_pm[8].phase_mon/PS_min[9]_i_1__6/O net (fo=10, routed) 0.602 4.180 ngFEC/g_pm[8].phase_mon/PS_min SLICE_X132Y310 FDPE r ngFEC/g_pm[8].phase_mon/PS_min_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 8.200 8.200 r BUFGCTRL_X0Y6 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 1.418 9.618 ngFEC/g_pm[8].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X132Y310 FDPE r ngFEC/g_pm[8].phase_mon/PS_min_reg[5]/C clock pessimism 0.153 9.771 clock uncertainty -0.035 9.736 SLICE_X132Y310 FDPE (Setup_fdpe_C_CE) -0.178 9.558 ngFEC/g_pm[8].phase_mon/PS_min_reg[5] ------------------------------------------------------------------- required time 9.558 arrival time -4.180 ------------------------------------------------------------------- slack 5.377 Slack (MET) : 5.466ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[10]/C (rising edge-triggered cell FDCE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[8] (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_4 rise@8.200ns - txWordclkl8_4 rise@0.000ns) Data Path Delay: 2.458ns (logic 0.259ns (10.536%) route 2.199ns (89.464%)) Logic Levels: 0 Clock Path Skew: 0.178ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.755ns = ( 9.955 - 8.200 ) Source Clock Delay (SCD): 1.667ns Clock Pessimism Removal (CPR): 0.090ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y6 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 1.667 1.667 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/CLK SLICE_X146Y53 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X146Y53 FDCE (Prop_fdce_C_Q) 0.259 1.926 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[10]/Q net (fo=1, routed) 2.199 4.125 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txdata_in[10] GTXE2_CHANNEL_X0Y7 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXDATA[8] ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 8.200 8.200 r BUFGCTRL_X0Y6 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 1.755 9.955 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y7 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 clock pessimism 0.090 10.045 clock uncertainty -0.035 10.010 GTXE2_CHANNEL_X0Y7 GTXE2_CHANNEL (Setup_gtxe2_channel_TXUSRCLK2_TXDATA[8]) -0.419 9.591 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i ------------------------------------------------------------------- required time 9.591 arrival time -4.125 ------------------------------------------------------------------- slack 5.466 Slack (MET) : 5.494ns (required time - arrival time) Source: ngFEC/g_pm[8].phase_mon/PS_max_reg[2]/C (rising edge-triggered cell FDCE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[8].phase_mon/PS_max_reg[5]/CE (rising edge-triggered cell FDCE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_4 Path Type: Setup (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_4 rise@8.200ns - txWordclkl8_4 rise@0.000ns) Data Path Delay: 2.448ns (logic 0.803ns (32.800%) route 1.645ns (67.200%)) Logic Levels: 4 (CARRY4=2 LUT4=1 LUT5=1) Clock Path Skew: -0.021ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.432ns = ( 9.632 - 8.200 ) Source Clock Delay (SCD): 1.635ns Clock Pessimism Removal (CPR): 0.182ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y6 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 1.635 1.635 ngFEC/g_pm[8].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X149Y309 FDCE r ngFEC/g_pm[8].phase_mon/PS_max_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X149Y309 FDCE (Prop_fdce_C_Q) 0.223 1.858 r ngFEC/g_pm[8].phase_mon/PS_max_reg[2]/Q net (fo=3, routed) 0.571 2.429 ngFEC/g_pm[8].phase_mon/PS_max_reg_n_0_[2] SLICE_X147Y309 LUT4 (Prop_lut4_I2_O) 0.043 2.472 r ngFEC/g_pm[8].phase_mon/PS_max[9]_i_13__6/O net (fo=1, routed) 0.000 2.472 ngFEC/g_pm[8].phase_mon/PS_max[9]_i_13__6_n_0 SLICE_X147Y309 CARRY4 (Prop_carry4_S[1]_CO[3]) 0.267 2.739 r ngFEC/g_pm[8].phase_mon/PS_max_reg[9]_i_4__3/CO[3] net (fo=1, routed) 0.000 2.739 ngFEC/g_pm[8].phase_mon/PS_max_reg[9]_i_4__3_n_0 SLICE_X147Y310 CARRY4 (Prop_carry4_CI_CO[0]) 0.139 2.878 r ngFEC/g_pm[8].phase_mon/PS_max_reg[9]_i_2__3/CO[0] net (fo=1, routed) 0.536 3.414 ngFEC/g_pm[8].phase_mon/gtOp SLICE_X143Y310 LUT5 (Prop_lut5_I2_O) 0.131 3.545 r ngFEC/g_pm[8].phase_mon/PS_max[9]_i_1__6/O net (fo=10, routed) 0.538 4.083 ngFEC/g_pm[8].phase_mon/PS_max SLICE_X148Y309 FDCE r ngFEC/g_pm[8].phase_mon/PS_max_reg[5]/CE ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 8.200 8.200 r BUFGCTRL_X0Y6 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 1.432 9.632 ngFEC/g_pm[8].phase_mon/MGT_TXUSRCLK_o[0] SLICE_X148Y309 FDCE r ngFEC/g_pm[8].phase_mon/PS_max_reg[5]/C clock pessimism 0.182 9.814 clock uncertainty -0.035 9.779 SLICE_X148Y309 FDCE (Setup_fdce_C_CE) -0.201 9.578 ngFEC/g_pm[8].phase_mon/PS_max_reg[5] ------------------------------------------------------------------- required time 9.578 arrival time -4.083 ------------------------------------------------------------------- slack 5.494 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.084ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[109]/C (rising edge-triggered cell FDCE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[9]/D (rising edge-triggered cell FDCE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_4 rise@0.000ns - txWordclkl8_4 rise@0.000ns) Data Path Delay: 0.182ns (logic 0.128ns (70.512%) route 0.054ns (29.488%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.948ns Source Clock Delay (SCD): 0.706ns Clock Pessimism Removal (CPR): 0.231ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y6 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 0.706 0.706 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/CLK SLICE_X147Y53 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[109]/C ------------------------------------------------------------------- ------------------- SLICE_X147Y53 FDCE (Prop_fdce_C_Q) 0.100 0.806 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[109]/Q net (fo=1, routed) 0.054 0.860 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/data5[9] SLICE_X146Y53 LUT6 (Prop_lut6_I2_O) 0.028 0.888 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[9]_i_1__10/O net (fo=1, routed) 0.000 0.888 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[9]_i_1__10_n_0 SLICE_X146Y53 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[9]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y6 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 0.948 0.948 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/CLK SLICE_X146Y53 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[9]/C clock pessimism -0.231 0.717 SLICE_X146Y53 FDCE (Hold_fdce_C_D) 0.087 0.804 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[9] ------------------------------------------------------------------- required time -0.804 arrival time 0.888 ------------------------------------------------------------------- slack 0.084 Slack (MET) : 0.086ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[110]/C (rising edge-triggered cell FDCE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[10]/D (rising edge-triggered cell FDCE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_4 rise@0.000ns - txWordclkl8_4 rise@0.000ns) Data Path Delay: 0.184ns (logic 0.128ns (69.743%) route 0.056ns (30.257%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.948ns Source Clock Delay (SCD): 0.706ns Clock Pessimism Removal (CPR): 0.231ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y6 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 0.706 0.706 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/CLK SLICE_X147Y53 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[110]/C ------------------------------------------------------------------- ------------------- SLICE_X147Y53 FDCE (Prop_fdce_C_Q) 0.100 0.806 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[110]/Q net (fo=1, routed) 0.056 0.862 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/data5[10] SLICE_X146Y53 LUT6 (Prop_lut6_I2_O) 0.028 0.890 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[10]_i_1__10/O net (fo=1, routed) 0.000 0.890 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[10]_i_1__10_n_0 SLICE_X146Y53 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[10]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y6 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 0.948 0.948 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/CLK SLICE_X146Y53 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[10]/C clock pessimism -0.231 0.717 SLICE_X146Y53 FDCE (Hold_fdce_C_D) 0.087 0.804 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[10] ------------------------------------------------------------------- required time -0.804 arrival time 0.890 ------------------------------------------------------------------- slack 0.086 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/g_pm[8].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[8].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D (rising edge-triggered cell FDRE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_4 rise@0.000ns - txWordclkl8_4 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.984ns Source Clock Delay (SCD): 0.738ns Clock Pessimism Removal (CPR): 0.246ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y6 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 0.738 0.738 ngFEC/g_pm[8].phase_mon/fabric_clk_PS_toggle_Sync_inst/dest_clk SLICE_X143Y317 FDRE r ngFEC/g_pm[8].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X143Y317 FDRE (Prop_fdre_C_Q) 0.100 0.838 r ngFEC/g_pm[8].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[0]/Q net (fo=1, routed) 0.055 0.893 ngFEC/g_pm[8].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff[0] SLICE_X143Y317 FDRE r ngFEC/g_pm[8].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y6 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 0.984 0.984 ngFEC/g_pm[8].phase_mon/fabric_clk_PS_toggle_Sync_inst/dest_clk SLICE_X143Y317 FDRE r ngFEC/g_pm[8].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1]/C clock pessimism -0.246 0.738 SLICE_X143Y317 FDRE (Hold_fdre_C_D) 0.047 0.785 ngFEC/g_pm[8].phase_mon/fabric_clk_PS_toggle_Sync_inst/syncstages_ff_reg[1] ------------------------------------------------------------------- required time -0.785 arrival time 0.893 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.108ns (arrival time - required time) Source: ngFEC/g_pm[8].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/g_pm[8].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/D (rising edge-triggered cell FDRE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_4 rise@0.000ns - txWordclkl8_4 rise@0.000ns) Data Path Delay: 0.155ns (logic 0.100ns (64.566%) route 0.055ns (35.434%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.953ns Source Clock Delay (SCD): 0.707ns Clock Pessimism Removal (CPR): 0.246ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y6 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 0.707 0.707 ngFEC/g_pm[8].phase_mon/sample_PS_Sync_inst/dest_clk SLICE_X127Y311 FDRE r ngFEC/g_pm[8].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X127Y311 FDRE (Prop_fdre_C_Q) 0.100 0.807 r ngFEC/g_pm[8].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[0]/Q net (fo=1, routed) 0.055 0.862 ngFEC/g_pm[8].phase_mon/sample_PS_Sync_inst/syncstages_ff[0] SLICE_X127Y311 FDRE r ngFEC/g_pm[8].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y6 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 0.953 0.953 ngFEC/g_pm[8].phase_mon/sample_PS_Sync_inst/dest_clk SLICE_X127Y311 FDRE r ngFEC/g_pm[8].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1]/C clock pessimism -0.246 0.707 SLICE_X127Y311 FDRE (Hold_fdre_C_D) 0.047 0.754 ngFEC/g_pm[8].phase_mon/sample_PS_Sync_inst/syncstages_ff_reg[1] ------------------------------------------------------------------- required time -0.754 arrival time 0.862 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.110ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[80]/C (rising edge-triggered cell FDCE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/D (rising edge-triggered cell FDCE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_4 rise@0.000ns - txWordclkl8_4 rise@0.000ns) Data Path Delay: 0.182ns (logic 0.128ns (70.416%) route 0.054ns (29.584%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.951ns Source Clock Delay (SCD): 0.708ns Clock Pessimism Removal (CPR): 0.232ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y6 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 0.708 0.708 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/CLK SLICE_X148Y56 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[80]/C ------------------------------------------------------------------- ------------------- SLICE_X148Y56 FDCE (Prop_fdce_C_Q) 0.100 0.808 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[80]/Q net (fo=1, routed) 0.054 0.862 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/data4[0] SLICE_X149Y56 LUT6 (Prop_lut6_I0_O) 0.028 0.890 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[0]_i_1__10/O net (fo=1, routed) 0.000 0.890 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[0]_i_1__10_n_0 SLICE_X149Y56 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y6 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 0.951 0.951 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/CLK SLICE_X149Y56 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0]/C clock pessimism -0.232 0.719 SLICE_X149Y56 FDCE (Hold_fdce_C_D) 0.061 0.780 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[0] ------------------------------------------------------------------- required time -0.780 arrival time 0.890 ------------------------------------------------------------------- slack 0.110 Slack (MET) : 0.112ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[81]/C (rising edge-triggered cell FDCE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/D (rising edge-triggered cell FDCE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_4 rise@0.000ns - txWordclkl8_4 rise@0.000ns) Data Path Delay: 0.183ns (logic 0.128ns (69.998%) route 0.055ns (30.002%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.951ns Source Clock Delay (SCD): 0.708ns Clock Pessimism Removal (CPR): 0.232ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y6 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 0.708 0.708 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/CLK SLICE_X148Y56 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[81]/C ------------------------------------------------------------------- ------------------- SLICE_X148Y56 FDCE (Prop_fdce_C_Q) 0.100 0.808 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[81]/Q net (fo=1, routed) 0.055 0.863 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/data4[1] SLICE_X149Y56 LUT6 (Prop_lut6_I0_O) 0.028 0.891 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[1]_i_1__10/O net (fo=1, routed) 0.000 0.891 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[1]_i_1__10_n_0 SLICE_X149Y56 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y6 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 0.951 0.951 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/CLK SLICE_X149Y56 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1]/C clock pessimism -0.232 0.719 SLICE_X149Y56 FDCE (Hold_fdce_C_D) 0.060 0.779 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[1] ------------------------------------------------------------------- required time -0.779 arrival time 0.891 ------------------------------------------------------------------- slack 0.112 Slack (MET) : 0.131ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D (rising edge-triggered cell FDRE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_4 rise@0.000ns - txWordclkl8_4 rise@0.000ns) Data Path Delay: 0.173ns (logic 0.118ns (68.255%) route 0.055ns (31.745%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.946ns Source Clock Delay (SCD): 0.704ns Clock Pessimism Removal (CPR): 0.242ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y6 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 0.704 0.704 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk SLICE_X144Y58 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X144Y58 FDRE (Prop_fdre_C_Q) 0.118 0.822 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[0]/Q net (fo=1, routed) 0.055 0.877 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff[0] SLICE_X144Y58 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y6 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 0.946 0.946 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/xpm_cdc_single_inst/dest_clk SLICE_X144Y58 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1]/C clock pessimism -0.242 0.704 SLICE_X144Y58 FDRE (Hold_fdre_C_D) 0.042 0.746 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/xpm_cdc_single_inst/syncstages_ff_reg[1] ------------------------------------------------------------------- required time -0.746 arrival time 0.877 ------------------------------------------------------------------- slack 0.131 Slack (MET) : 0.131ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_4 rise@0.000ns - txWordclkl8_4 rise@0.000ns) Data Path Delay: 0.173ns (logic 0.118ns (68.255%) route 0.055ns (31.745%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.979ns Source Clock Delay (SCD): 0.737ns Clock Pessimism Removal (CPR): 0.242ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y6 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 0.737 0.737 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in SLICE_X180Y83 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X180Y83 FDRE (Prop_fdre_C_Q) 0.118 0.855 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg1/Q net (fo=1, routed) 0.055 0.910 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync1 SLICE_X180Y83 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y6 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 0.979 0.979 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/gt0_txusrclk_in SLICE_X180Y83 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2/C clock pessimism -0.242 0.737 SLICE_X180Y83 FDRE (Hold_fdre_C_D) 0.042 0.779 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_run_phase_alignment_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.779 arrival time 0.910 ------------------------------------------------------------------- slack 0.131 Slack (MET) : 0.131ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/C (rising edge-triggered cell FDRE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D (rising edge-triggered cell FDRE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_4 rise@0.000ns - txWordclkl8_4 rise@0.000ns) Data Path Delay: 0.173ns (logic 0.118ns (68.255%) route 0.055ns (31.745%)) Logic Levels: 0 Clock Path Skew: 0.000ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.980ns Source Clock Delay (SCD): 0.738ns Clock Pessimism Removal (CPR): 0.242ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y6 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 0.738 0.738 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in SLICE_X182Y84 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/C ------------------------------------------------------------------- ------------------- SLICE_X182Y84 FDRE (Prop_fdre_C_Q) 0.118 0.856 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg1/Q net (fo=1, routed) 0.055 0.911 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync1 SLICE_X182Y84 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/D ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y6 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 0.980 0.980 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/gt0_txusrclk_in SLICE_X182Y84 FDRE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2/C clock pessimism -0.242 0.738 SLICE_X182Y84 FDRE (Hold_fdre_C_D) 0.042 0.780 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/sync_tx_fsm_reset_done_int/data_sync_reg2 ------------------------------------------------------------------- required time -0.780 arrival time 0.911 ------------------------------------------------------------------- slack 0.131 Slack (MET) : 0.139ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[87]/C (rising edge-triggered cell FDCE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/D (rising edge-triggered cell FDCE clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: txWordclkl8_4 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_4 rise@0.000ns - txWordclkl8_4 rise@0.000ns) Data Path Delay: 0.211ns (logic 0.128ns (60.586%) route 0.083ns (39.414%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.951ns Source Clock Delay (SCD): 0.708ns Clock Pessimism Removal (CPR): 0.232ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y6 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 0.708 0.708 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/CLK SLICE_X149Y55 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[87]/C ------------------------------------------------------------------- ------------------- SLICE_X149Y55 FDCE (Prop_fdce_C_Q) 0.100 0.808 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[87]/Q net (fo=1, routed) 0.083 0.891 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/data4[7] SLICE_X148Y55 LUT6 (Prop_lut6_I0_O) 0.028 0.919 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[7]_i_1__10/O net (fo=1, routed) 0.000 0.919 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O[7]_i_1__10_n_0 SLICE_X148Y55 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/D ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y6 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 0.951 0.951 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/CLK SLICE_X148Y55 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/C clock pessimism -0.232 0.719 SLICE_X148Y55 FDCE (Hold_fdce_C_D) 0.061 0.780 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7] ------------------------------------------------------------------- required time -0.780 arrival time 0.919 ------------------------------------------------------------------- slack 0.139 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: txWordclkl8_4 Waveform(ns): { 0.000 4.100 } Period(ns): 8.200 Sources: { ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a GTXE2_CHANNEL/TXUSRCLK n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y7 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK Min Period n/a GTXE2_CHANNEL/TXUSRCLK2 n/a 3.030 8.200 5.170 GTXE2_CHANNEL_X0Y7 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 Min Period n/a FDRE/C n/a 0.750 8.200 7.450 SLICE_X146Y55 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X144Y56 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[1]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X146Y54 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[38]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X147Y55 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[44]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X147Y55 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[4]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X146Y54 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[50]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X144Y53 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[51]/C Min Period n/a FDCE/C n/a 0.750 8.200 7.450 SLICE_X145Y52 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[52]/C Low Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X146Y55 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK Low Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X146Y55 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK Low Pulse Width Slow FDRE/C n/a 0.400 4.100 3.700 SLICE_X146Y55 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/C Low Pulse Width Fast FDRE/C n/a 0.400 4.100 3.700 SLICE_X146Y55 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/TOGGLE_sync_reg[4]__0/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X144Y56 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[1]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X144Y56 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.address_reg[1]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X146Y54 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[38]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X146Y54 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[38]/C Low Pulse Width Slow FDCE/C n/a 0.400 4.100 3.700 SLICE_X147Y55 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[44]/C Low Pulse Width Fast FDCE/C n/a 0.400 4.100 3.700 SLICE_X147Y55 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[44]/C High Pulse Width Slow SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X146Y55 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK High Pulse Width Fast SRL16E/CLK n/a 0.642 4.100 3.458 SLICE_X146Y55 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/TOGGLE_sync_reg[3]_srl3/CLK High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X148Y55 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[12]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X148Y55 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[13]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X148Y55 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[15]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X148Y55 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[7]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X151Y51 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.TX_WORD_O_reg[8]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X148Y53 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[100]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X149Y54 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[101]/C High Pulse Width Slow FDCE/C n/a 0.350 4.100 3.750 SLICE_X148Y51 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/txGearboxLatOpt_gen.txFrame_from_frameInverter_reg[103]/C --------------------------------------------------------------------------------------------------- From Clock: clk62_5_ub To Clock: clk125_ub Setup : 0 Failing Endpoints, Worst Slack 6.010ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.086ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 6.010ns (required time - arrival time) Source: sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[0]/C (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[0]/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125_ub rise@8.000ns - clk62_5_ub rise@0.000ns) Data Path Delay: 1.510ns (logic 0.223ns (14.771%) route 1.287ns (85.229%)) Logic Levels: 0 Clock Path Skew: -0.276ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.148ns = ( 12.148 - 8.000 ) Source Clock Delay (SCD): 5.298ns Clock Pessimism Removal (CPR): 0.874ns Clock Uncertainty: 0.183ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 2.205 3.654 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.551 5.298 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X185Y109 FDRE r sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X185Y109 FDRE (Prop_fdre_C_Q) 0.223 5.521 r sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[0]/Q net (fo=1, routed) 1.287 6.807 sys/eth/phy/U0/transceiver_inst/rxdata_reg[0] SLICE_X185Y108 FDRE r sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[0]/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 12.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -3.847 8.575 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.078 10.653 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.412 12.148 sys/eth/phy/U0/transceiver_inst/userclk2 SLICE_X185Y108 FDRE r sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[0]/C clock pessimism 0.874 13.022 clock uncertainty -0.183 12.839 SLICE_X185Y108 FDRE (Setup_fdre_C_D) -0.022 12.817 sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[0] ------------------------------------------------------------------- required time 12.817 arrival time -6.807 ------------------------------------------------------------------- slack 6.010 Slack (MET) : 6.176ns (required time - arrival time) Source: sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[7]/C (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[7]/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125_ub rise@8.000ns - clk62_5_ub rise@0.000ns) Data Path Delay: 1.277ns (logic 0.204ns (15.978%) route 1.073ns (84.022%)) Logic Levels: 0 Clock Path Skew: -0.277ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.147ns = ( 12.147 - 8.000 ) Source Clock Delay (SCD): 5.298ns Clock Pessimism Removal (CPR): 0.874ns Clock Uncertainty: 0.183ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 2.205 3.654 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.551 5.298 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X187Y109 FDRE r sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X187Y109 FDRE (Prop_fdre_C_Q) 0.204 5.502 r sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[7]/Q net (fo=1, routed) 1.073 6.574 sys/eth/phy/U0/transceiver_inst/rxdata_reg[7] SLICE_X185Y110 FDRE r sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[7]/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 12.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -3.847 8.575 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.078 10.653 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.411 12.147 sys/eth/phy/U0/transceiver_inst/userclk2 SLICE_X185Y110 FDRE r sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[7]/C clock pessimism 0.874 13.021 clock uncertainty -0.183 12.838 SLICE_X185Y110 FDRE (Setup_fdre_C_D) -0.088 12.750 sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[7] ------------------------------------------------------------------- required time 12.750 arrival time -6.574 ------------------------------------------------------------------- slack 6.176 Slack (MET) : 6.200ns (required time - arrival time) Source: sys/eth/phy/U0/transceiver_inst/txbufstatus_reg_reg[1]/C (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/txbuferr_reg/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125_ub rise@8.000ns - clk62_5_ub rise@0.000ns) Data Path Delay: 1.319ns (logic 0.223ns (16.907%) route 1.096ns (83.093%)) Logic Levels: 0 Clock Path Skew: -0.276ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.150ns = ( 12.150 - 8.000 ) Source Clock Delay (SCD): 5.300ns Clock Pessimism Removal (CPR): 0.874ns Clock Uncertainty: 0.183ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 2.205 3.654 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.553 5.300 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X189Y102 FDRE r sys/eth/phy/U0/transceiver_inst/txbufstatus_reg_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X189Y102 FDRE (Prop_fdre_C_Q) 0.223 5.523 r sys/eth/phy/U0/transceiver_inst/txbufstatus_reg_reg[1]/Q net (fo=1, routed) 1.096 6.619 sys/eth/phy/U0/transceiver_inst/txbufstatus_reg[1] SLICE_X188Y102 FDRE r sys/eth/phy/U0/transceiver_inst/txbuferr_reg/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 12.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -3.847 8.575 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.078 10.653 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.414 12.150 sys/eth/phy/U0/transceiver_inst/userclk2 SLICE_X188Y102 FDRE r sys/eth/phy/U0/transceiver_inst/txbuferr_reg/C clock pessimism 0.874 13.024 clock uncertainty -0.183 12.841 SLICE_X188Y102 FDRE (Setup_fdre_C_D) -0.022 12.819 sys/eth/phy/U0/transceiver_inst/txbuferr_reg ------------------------------------------------------------------- required time 12.819 arrival time -6.619 ------------------------------------------------------------------- slack 6.200 Slack (MET) : 6.203ns (required time - arrival time) Source: sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[12]/C (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[12]/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125_ub rise@8.000ns - clk62_5_ub rise@0.000ns) Data Path Delay: 1.359ns (logic 0.223ns (16.406%) route 1.136ns (83.594%)) Logic Levels: 0 Clock Path Skew: -0.276ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.148ns = ( 12.148 - 8.000 ) Source Clock Delay (SCD): 5.298ns Clock Pessimism Removal (CPR): 0.874ns Clock Uncertainty: 0.183ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 2.205 3.654 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.551 5.298 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X187Y109 FDRE r sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X187Y109 FDRE (Prop_fdre_C_Q) 0.223 5.521 r sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[12]/Q net (fo=1, routed) 1.136 6.657 sys/eth/phy/U0/transceiver_inst/rxdata_reg[12] SLICE_X186Y109 FDRE r sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[12]/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 12.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -3.847 8.575 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.078 10.653 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.412 12.148 sys/eth/phy/U0/transceiver_inst/userclk2 SLICE_X186Y109 FDRE r sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[12]/C clock pessimism 0.874 13.022 clock uncertainty -0.183 12.839 SLICE_X186Y109 FDRE (Setup_fdre_C_D) 0.021 12.860 sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[12] ------------------------------------------------------------------- required time 12.860 arrival time -6.657 ------------------------------------------------------------------- slack 6.203 Slack (MET) : 6.223ns (required time - arrival time) Source: sys/eth/phy/U0/transceiver_inst/rxnotintable_reg_reg[0]/C (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/rxnotintable_double_reg[0]/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125_ub rise@8.000ns - clk62_5_ub rise@0.000ns) Data Path Delay: 1.227ns (logic 0.204ns (16.621%) route 1.023ns (83.379%)) Logic Levels: 0 Clock Path Skew: -0.276ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.147ns = ( 12.147 - 8.000 ) Source Clock Delay (SCD): 5.297ns Clock Pessimism Removal (CPR): 0.874ns Clock Uncertainty: 0.183ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 2.205 3.654 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.550 5.297 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X189Y110 FDRE r sys/eth/phy/U0/transceiver_inst/rxnotintable_reg_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X189Y110 FDRE (Prop_fdre_C_Q) 0.204 5.501 r sys/eth/phy/U0/transceiver_inst/rxnotintable_reg_reg[0]/Q net (fo=1, routed) 1.023 6.524 sys/eth/phy/U0/transceiver_inst/rxnotintable_reg__0[0] SLICE_X185Y110 FDRE r sys/eth/phy/U0/transceiver_inst/rxnotintable_double_reg[0]/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 12.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -3.847 8.575 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.078 10.653 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.411 12.147 sys/eth/phy/U0/transceiver_inst/userclk2 SLICE_X185Y110 FDRE r sys/eth/phy/U0/transceiver_inst/rxnotintable_double_reg[0]/C clock pessimism 0.874 13.021 clock uncertainty -0.183 12.838 SLICE_X185Y110 FDRE (Setup_fdre_C_D) -0.091 12.747 sys/eth/phy/U0/transceiver_inst/rxnotintable_double_reg[0] ------------------------------------------------------------------- required time 12.747 arrival time -6.524 ------------------------------------------------------------------- slack 6.223 Slack (MET) : 6.223ns (required time - arrival time) Source: sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[13]/C (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[13]/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125_ub rise@8.000ns - clk62_5_ub rise@0.000ns) Data Path Delay: 1.340ns (logic 0.223ns (16.639%) route 1.117ns (83.361%)) Logic Levels: 0 Clock Path Skew: -0.276ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.148ns = ( 12.148 - 8.000 ) Source Clock Delay (SCD): 5.298ns Clock Pessimism Removal (CPR): 0.874ns Clock Uncertainty: 0.183ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 2.205 3.654 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.551 5.298 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X187Y109 FDRE r sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X187Y109 FDRE (Prop_fdre_C_Q) 0.223 5.521 r sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[13]/Q net (fo=1, routed) 1.117 6.638 sys/eth/phy/U0/transceiver_inst/rxdata_reg[13] SLICE_X186Y109 FDRE r sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[13]/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 12.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -3.847 8.575 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.078 10.653 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.412 12.148 sys/eth/phy/U0/transceiver_inst/userclk2 SLICE_X186Y109 FDRE r sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[13]/C clock pessimism 0.874 13.022 clock uncertainty -0.183 12.839 SLICE_X186Y109 FDRE (Setup_fdre_C_D) 0.022 12.861 sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[13] ------------------------------------------------------------------- required time 12.861 arrival time -6.638 ------------------------------------------------------------------- slack 6.223 Slack (MET) : 6.234ns (required time - arrival time) Source: sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[5]/C (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[5]/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125_ub rise@8.000ns - clk62_5_ub rise@0.000ns) Data Path Delay: 1.235ns (logic 0.204ns (16.515%) route 1.031ns (83.485%)) Logic Levels: 0 Clock Path Skew: -0.276ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.148ns = ( 12.148 - 8.000 ) Source Clock Delay (SCD): 5.298ns Clock Pessimism Removal (CPR): 0.874ns Clock Uncertainty: 0.183ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 2.205 3.654 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.551 5.298 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X187Y109 FDRE r sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X187Y109 FDRE (Prop_fdre_C_Q) 0.204 5.502 r sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[5]/Q net (fo=1, routed) 1.031 6.533 sys/eth/phy/U0/transceiver_inst/rxdata_reg[5] SLICE_X186Y109 FDRE r sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[5]/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 12.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -3.847 8.575 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.078 10.653 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.412 12.148 sys/eth/phy/U0/transceiver_inst/userclk2 SLICE_X186Y109 FDRE r sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[5]/C clock pessimism 0.874 13.022 clock uncertainty -0.183 12.839 SLICE_X186Y109 FDRE (Setup_fdre_C_D) -0.072 12.767 sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[5] ------------------------------------------------------------------- required time 12.767 arrival time -6.533 ------------------------------------------------------------------- slack 6.234 Slack (MET) : 6.240ns (required time - arrival time) Source: sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[15]/C (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[15]/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125_ub rise@8.000ns - clk62_5_ub rise@0.000ns) Data Path Delay: 1.291ns (logic 0.223ns (17.268%) route 1.068ns (82.732%)) Logic Levels: 0 Clock Path Skew: -0.277ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.147ns = ( 12.147 - 8.000 ) Source Clock Delay (SCD): 5.298ns Clock Pessimism Removal (CPR): 0.874ns Clock Uncertainty: 0.183ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 2.205 3.654 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.551 5.298 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X185Y109 FDRE r sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X185Y109 FDRE (Prop_fdre_C_Q) 0.223 5.521 r sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[15]/Q net (fo=1, routed) 1.068 6.589 sys/eth/phy/U0/transceiver_inst/rxdata_reg[15] SLICE_X185Y110 FDRE r sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[15]/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 12.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -3.847 8.575 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.078 10.653 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.411 12.147 sys/eth/phy/U0/transceiver_inst/userclk2 SLICE_X185Y110 FDRE r sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[15]/C clock pessimism 0.874 13.021 clock uncertainty -0.183 12.838 SLICE_X185Y110 FDRE (Setup_fdre_C_D) -0.009 12.829 sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[15] ------------------------------------------------------------------- required time 12.829 arrival time -6.589 ------------------------------------------------------------------- slack 6.240 Slack (MET) : 6.245ns (required time - arrival time) Source: sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[11]/C (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[11]/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125_ub rise@8.000ns - clk62_5_ub rise@0.000ns) Data Path Delay: 1.286ns (logic 0.223ns (17.335%) route 1.063ns (82.665%)) Logic Levels: 0 Clock Path Skew: -0.276ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.148ns = ( 12.148 - 8.000 ) Source Clock Delay (SCD): 5.298ns Clock Pessimism Removal (CPR): 0.874ns Clock Uncertainty: 0.183ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 2.205 3.654 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.551 5.298 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X189Y108 FDRE r sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X189Y108 FDRE (Prop_fdre_C_Q) 0.223 5.521 r sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[11]/Q net (fo=1, routed) 1.063 6.584 sys/eth/phy/U0/transceiver_inst/rxdata_reg[11] SLICE_X189Y109 FDRE r sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[11]/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 12.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -3.847 8.575 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.078 10.653 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.412 12.148 sys/eth/phy/U0/transceiver_inst/userclk2 SLICE_X189Y109 FDRE r sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[11]/C clock pessimism 0.874 13.022 clock uncertainty -0.183 12.839 SLICE_X189Y109 FDRE (Setup_fdre_C_D) -0.010 12.829 sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[11] ------------------------------------------------------------------- required time 12.829 arrival time -6.584 ------------------------------------------------------------------- slack 6.245 Slack (MET) : 6.247ns (required time - arrival time) Source: sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[3]/C (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[3]/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125_ub rise@8.000ns - clk62_5_ub rise@0.000ns) Data Path Delay: 1.200ns (logic 0.204ns (16.999%) route 0.996ns (83.001%)) Logic Levels: 0 Clock Path Skew: -0.277ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.147ns = ( 12.147 - 8.000 ) Source Clock Delay (SCD): 5.298ns Clock Pessimism Removal (CPR): 0.874ns Clock Uncertainty: 0.183ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 2.205 3.654 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.551 5.298 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X185Y109 FDRE r sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X185Y109 FDRE (Prop_fdre_C_Q) 0.204 5.502 r sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[3]/Q net (fo=1, routed) 0.996 6.498 sys/eth/phy/U0/transceiver_inst/rxdata_reg[3] SLICE_X185Y110 FDRE r sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[3]/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 12.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -3.847 8.575 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.078 10.653 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.411 12.147 sys/eth/phy/U0/transceiver_inst/userclk2 SLICE_X185Y110 FDRE r sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[3]/C clock pessimism 0.874 13.021 clock uncertainty -0.183 12.838 SLICE_X185Y110 FDRE (Setup_fdre_C_D) -0.093 12.745 sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[3] ------------------------------------------------------------------- required time 12.745 arrival time -6.498 ------------------------------------------------------------------- slack 6.247 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.086ns (arrival time - required time) Source: sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[6]/C (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[6]/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125_ub rise@0.000ns - clk62_5_ub rise@0.000ns) Data Path Delay: 0.573ns (logic 0.091ns (15.879%) route 0.482ns (84.121%)) Logic Levels: 0 Clock Path Skew: 0.296ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.290ns Source Clock Delay (SCD): 1.732ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.183ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 1.004 1.017 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 0.689 1.732 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X185Y109 FDRE r sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X185Y109 FDRE (Prop_fdre_C_Q) 0.091 1.823 r sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[6]/Q net (fo=1, routed) 0.482 2.305 sys/eth/phy/U0/transceiver_inst/rxdata_reg[6] SLICE_X185Y110 FDRE r sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[6]/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.073 1.348 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.912 2.290 sys/eth/phy/U0/transceiver_inst/userclk2 SLICE_X185Y110 FDRE r sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[6]/C clock pessimism -0.262 2.028 clock uncertainty 0.183 2.210 SLICE_X185Y110 FDRE (Hold_fdre_C_D) 0.008 2.218 sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[6] ------------------------------------------------------------------- required time -2.218 arrival time 2.305 ------------------------------------------------------------------- slack 0.086 Slack (MET) : 0.101ns (arrival time - required time) Source: sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[2]/C (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[2]/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125_ub rise@0.000ns - clk62_5_ub rise@0.000ns) Data Path Delay: 0.612ns (logic 0.100ns (16.330%) route 0.512ns (83.670%)) Logic Levels: 0 Clock Path Skew: 0.296ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.290ns Source Clock Delay (SCD): 1.732ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.183ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 1.004 1.017 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 0.689 1.732 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X185Y109 FDRE r sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X185Y109 FDRE (Prop_fdre_C_Q) 0.100 1.832 r sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[2]/Q net (fo=1, routed) 0.512 2.344 sys/eth/phy/U0/transceiver_inst/rxdata_reg[2] SLICE_X185Y110 FDRE r sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[2]/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.073 1.348 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.912 2.290 sys/eth/phy/U0/transceiver_inst/userclk2 SLICE_X185Y110 FDRE r sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[2]/C clock pessimism -0.262 2.028 clock uncertainty 0.183 2.210 SLICE_X185Y110 FDRE (Hold_fdre_C_D) 0.033 2.243 sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[2] ------------------------------------------------------------------- required time -2.243 arrival time 2.344 ------------------------------------------------------------------- slack 0.101 Slack (MET) : 0.102ns (arrival time - required time) Source: sys/eth/phy/U0/transceiver_inst/rxcharisk_reg_reg[0]/C (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/rxcharisk_double_reg[0]/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125_ub rise@0.000ns - clk62_5_ub rise@0.000ns) Data Path Delay: 0.615ns (logic 0.100ns (16.271%) route 0.515ns (83.729%)) Logic Levels: 0 Clock Path Skew: 0.297ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.291ns Source Clock Delay (SCD): 1.732ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.183ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 1.004 1.017 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 0.689 1.732 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X189Y110 FDRE r sys/eth/phy/U0/transceiver_inst/rxcharisk_reg_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X189Y110 FDRE (Prop_fdre_C_Q) 0.100 1.832 r sys/eth/phy/U0/transceiver_inst/rxcharisk_reg_reg[0]/Q net (fo=1, routed) 0.515 2.346 sys/eth/phy/U0/transceiver_inst/rxcharisk_reg__0[0] SLICE_X189Y109 FDRE r sys/eth/phy/U0/transceiver_inst/rxcharisk_double_reg[0]/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.073 1.348 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.913 2.291 sys/eth/phy/U0/transceiver_inst/userclk2 SLICE_X189Y109 FDRE r sys/eth/phy/U0/transceiver_inst/rxcharisk_double_reg[0]/C clock pessimism -0.262 2.029 clock uncertainty 0.183 2.211 SLICE_X189Y109 FDRE (Hold_fdre_C_D) 0.033 2.244 sys/eth/phy/U0/transceiver_inst/rxcharisk_double_reg[0] ------------------------------------------------------------------- required time -2.244 arrival time 2.346 ------------------------------------------------------------------- slack 0.102 Slack (MET) : 0.105ns (arrival time - required time) Source: sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[9]/C (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[9]/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125_ub rise@0.000ns - clk62_5_ub rise@0.000ns) Data Path Delay: 0.593ns (logic 0.091ns (15.337%) route 0.502ns (84.663%)) Logic Levels: 0 Clock Path Skew: 0.297ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.291ns Source Clock Delay (SCD): 1.732ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.183ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 1.004 1.017 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 0.689 1.732 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X187Y109 FDRE r sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X187Y109 FDRE (Prop_fdre_C_Q) 0.091 1.823 r sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[9]/Q net (fo=1, routed) 0.502 2.325 sys/eth/phy/U0/transceiver_inst/rxdata_reg[9] SLICE_X186Y109 FDRE r sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[9]/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.073 1.348 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.913 2.291 sys/eth/phy/U0/transceiver_inst/userclk2 SLICE_X186Y109 FDRE r sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[9]/C clock pessimism -0.262 2.029 clock uncertainty 0.183 2.211 SLICE_X186Y109 FDRE (Hold_fdre_C_D) 0.009 2.220 sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[9] ------------------------------------------------------------------- required time -2.220 arrival time 2.325 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.105ns (arrival time - required time) Source: sys/eth/phy/U0/transceiver_inst/rxcharisk_reg_reg[1]/C (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/rxcharisk_double_reg[1]/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125_ub rise@0.000ns - clk62_5_ub rise@0.000ns) Data Path Delay: 0.617ns (logic 0.100ns (16.218%) route 0.517ns (83.782%)) Logic Levels: 0 Clock Path Skew: 0.296ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.291ns Source Clock Delay (SCD): 1.733ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.183ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 1.004 1.017 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 0.690 1.733 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X189Y108 FDRE r sys/eth/phy/U0/transceiver_inst/rxcharisk_reg_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X189Y108 FDRE (Prop_fdre_C_Q) 0.100 1.833 r sys/eth/phy/U0/transceiver_inst/rxcharisk_reg_reg[1]/Q net (fo=1, routed) 0.517 2.349 sys/eth/phy/U0/transceiver_inst/rxcharisk_reg__0[1] SLICE_X189Y109 FDRE r sys/eth/phy/U0/transceiver_inst/rxcharisk_double_reg[1]/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.073 1.348 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.913 2.291 sys/eth/phy/U0/transceiver_inst/userclk2 SLICE_X189Y109 FDRE r sys/eth/phy/U0/transceiver_inst/rxcharisk_double_reg[1]/C clock pessimism -0.262 2.029 clock uncertainty 0.183 2.211 SLICE_X189Y109 FDRE (Hold_fdre_C_D) 0.033 2.244 sys/eth/phy/U0/transceiver_inst/rxcharisk_double_reg[1] ------------------------------------------------------------------- required time -2.244 arrival time 2.349 ------------------------------------------------------------------- slack 0.105 Slack (MET) : 0.109ns (arrival time - required time) Source: sys/eth/phy/U0/transceiver_inst/rxchariscomma_reg_reg[0]/C (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/rxchariscomma_double_reg[0]/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125_ub rise@0.000ns - clk62_5_ub rise@0.000ns) Data Path Delay: 0.620ns (logic 0.100ns (16.131%) route 0.520ns (83.869%)) Logic Levels: 0 Clock Path Skew: 0.296ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.291ns Source Clock Delay (SCD): 1.733ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.183ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 1.004 1.017 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 0.690 1.733 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X189Y108 FDRE r sys/eth/phy/U0/transceiver_inst/rxchariscomma_reg_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X189Y108 FDRE (Prop_fdre_C_Q) 0.100 1.833 r sys/eth/phy/U0/transceiver_inst/rxchariscomma_reg_reg[0]/Q net (fo=1, routed) 0.520 2.352 sys/eth/phy/U0/transceiver_inst/rxchariscomma_reg__0[0] SLICE_X189Y109 FDRE r sys/eth/phy/U0/transceiver_inst/rxchariscomma_double_reg[0]/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.073 1.348 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.913 2.291 sys/eth/phy/U0/transceiver_inst/userclk2 SLICE_X189Y109 FDRE r sys/eth/phy/U0/transceiver_inst/rxchariscomma_double_reg[0]/C clock pessimism -0.262 2.029 clock uncertainty 0.183 2.211 SLICE_X189Y109 FDRE (Hold_fdre_C_D) 0.032 2.243 sys/eth/phy/U0/transceiver_inst/rxchariscomma_double_reg[0] ------------------------------------------------------------------- required time -2.243 arrival time 2.352 ------------------------------------------------------------------- slack 0.109 Slack (MET) : 0.112ns (arrival time - required time) Source: sys/eth/phy/U0/transceiver_inst/rxnotintable_reg_reg[1]/C (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/rxnotintable_double_reg[1]/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125_ub rise@0.000ns - clk62_5_ub rise@0.000ns) Data Path Delay: 0.603ns (logic 0.091ns (15.086%) route 0.512ns (84.914%)) Logic Levels: 0 Clock Path Skew: 0.296ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.291ns Source Clock Delay (SCD): 1.733ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.183ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 1.004 1.017 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 0.690 1.733 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X189Y108 FDRE r sys/eth/phy/U0/transceiver_inst/rxnotintable_reg_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X189Y108 FDRE (Prop_fdre_C_Q) 0.091 1.824 r sys/eth/phy/U0/transceiver_inst/rxnotintable_reg_reg[1]/Q net (fo=1, routed) 0.512 2.336 sys/eth/phy/U0/transceiver_inst/rxnotintable_reg__0[1] SLICE_X189Y109 FDRE r sys/eth/phy/U0/transceiver_inst/rxnotintable_double_reg[1]/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.073 1.348 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.913 2.291 sys/eth/phy/U0/transceiver_inst/userclk2 SLICE_X189Y109 FDRE r sys/eth/phy/U0/transceiver_inst/rxnotintable_double_reg[1]/C clock pessimism -0.262 2.029 clock uncertainty 0.183 2.211 SLICE_X189Y109 FDRE (Hold_fdre_C_D) 0.013 2.224 sys/eth/phy/U0/transceiver_inst/rxnotintable_double_reg[1] ------------------------------------------------------------------- required time -2.224 arrival time 2.336 ------------------------------------------------------------------- slack 0.112 Slack (MET) : 0.112ns (arrival time - required time) Source: sys/eth/phy/U0/transceiver_inst/rxdisperr_reg_reg[1]/C (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/rxdisperr_double_reg[1]/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125_ub rise@0.000ns - clk62_5_ub rise@0.000ns) Data Path Delay: 0.600ns (logic 0.091ns (15.166%) route 0.509ns (84.834%)) Logic Levels: 0 Clock Path Skew: 0.296ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.291ns Source Clock Delay (SCD): 1.733ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.183ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 1.004 1.017 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 0.690 1.733 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X189Y108 FDRE r sys/eth/phy/U0/transceiver_inst/rxdisperr_reg_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X189Y108 FDRE (Prop_fdre_C_Q) 0.091 1.824 r sys/eth/phy/U0/transceiver_inst/rxdisperr_reg_reg[1]/Q net (fo=1, routed) 0.509 2.333 sys/eth/phy/U0/transceiver_inst/rxdisperr_reg__0[1] SLICE_X189Y109 FDRE r sys/eth/phy/U0/transceiver_inst/rxdisperr_double_reg[1]/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.073 1.348 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.913 2.291 sys/eth/phy/U0/transceiver_inst/userclk2 SLICE_X189Y109 FDRE r sys/eth/phy/U0/transceiver_inst/rxdisperr_double_reg[1]/C clock pessimism -0.262 2.029 clock uncertainty 0.183 2.211 SLICE_X189Y109 FDRE (Hold_fdre_C_D) 0.009 2.220 sys/eth/phy/U0/transceiver_inst/rxdisperr_double_reg[1] ------------------------------------------------------------------- required time -2.220 arrival time 2.333 ------------------------------------------------------------------- slack 0.112 Slack (MET) : 0.113ns (arrival time - required time) Source: sys/eth/phy/U0/transceiver_inst/rxdisperr_reg_reg[0]/C (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/rxdisperr_double_reg[0]/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125_ub rise@0.000ns - clk62_5_ub rise@0.000ns) Data Path Delay: 0.637ns (logic 0.100ns (15.704%) route 0.537ns (84.296%)) Logic Levels: 0 Clock Path Skew: 0.297ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.291ns Source Clock Delay (SCD): 1.732ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.183ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 1.004 1.017 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 0.689 1.732 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X189Y110 FDRE r sys/eth/phy/U0/transceiver_inst/rxdisperr_reg_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X189Y110 FDRE (Prop_fdre_C_Q) 0.100 1.832 r sys/eth/phy/U0/transceiver_inst/rxdisperr_reg_reg[0]/Q net (fo=1, routed) 0.537 2.368 sys/eth/phy/U0/transceiver_inst/rxdisperr_reg__0[0] SLICE_X189Y109 FDRE r sys/eth/phy/U0/transceiver_inst/rxdisperr_double_reg[0]/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.073 1.348 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.913 2.291 sys/eth/phy/U0/transceiver_inst/userclk2 SLICE_X189Y109 FDRE r sys/eth/phy/U0/transceiver_inst/rxdisperr_double_reg[0]/C clock pessimism -0.262 2.029 clock uncertainty 0.183 2.211 SLICE_X189Y109 FDRE (Hold_fdre_C_D) 0.044 2.255 sys/eth/phy/U0/transceiver_inst/rxdisperr_double_reg[0] ------------------------------------------------------------------- required time -2.255 arrival time 2.368 ------------------------------------------------------------------- slack 0.113 Slack (MET) : 0.117ns (arrival time - required time) Source: sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[4]/C (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[4]/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125_ub rise@0.000ns - clk62_5_ub rise@0.000ns) Data Path Delay: 0.637ns (logic 0.100ns (15.708%) route 0.537ns (84.292%)) Logic Levels: 0 Clock Path Skew: 0.297ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.291ns Source Clock Delay (SCD): 1.732ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.183ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 1.004 1.017 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 0.689 1.732 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X187Y109 FDRE r sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X187Y109 FDRE (Prop_fdre_C_Q) 0.100 1.832 r sys/eth/phy/U0/transceiver_inst/rxdata_reg_reg[4]/Q net (fo=1, routed) 0.537 2.368 sys/eth/phy/U0/transceiver_inst/rxdata_reg[4] SLICE_X186Y109 FDRE r sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[4]/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.073 1.348 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.913 2.291 sys/eth/phy/U0/transceiver_inst/userclk2 SLICE_X186Y109 FDRE r sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[4]/C clock pessimism -0.262 2.029 clock uncertainty 0.183 2.211 SLICE_X186Y109 FDRE (Hold_fdre_C_D) 0.040 2.251 sys/eth/phy/U0/transceiver_inst/rxdata_double_reg[4] ------------------------------------------------------------------- required time -2.251 arrival time 2.368 ------------------------------------------------------------------- slack 0.117 --------------------------------------------------------------------------------------------------- From Clock: clk_ipb_ub To Clock: clk125_ub Setup : 0 Failing Endpoints, Worst Slack 0.619ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.057ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.619ns (required time - arrival time) Source: sys/ipb/trans/sm/addr_reg[17]_replica/C (rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: sys/ipb/udp_if/clock_crossing_if/we_buf_reg[0]/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125_ub rise@8.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 6.902ns (logic 1.179ns (17.082%) route 5.723ns (82.918%)) Logic Levels: 14 (LUT4=3 LUT5=3 LUT6=6 MUXF7=1 MUXF8=1) Clock Path Skew: -0.271ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.996ns = ( 11.996 - 8.000 ) Source Clock Delay (SCD): 5.141ns Clock Pessimism Removal (CPR): 0.874ns Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.205 3.654 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.394 5.141 sys/ipb/trans/sm/out SLICE_X82Y138 FDRE r sys/ipb/trans/sm/addr_reg[17]_replica/C ------------------------------------------------------------------- ------------------- SLICE_X82Y138 FDRE (Prop_fdre_C_Q) 0.236 5.377 r sys/ipb/trans/sm/addr_reg[17]_replica/Q net (fo=241, routed) 0.394 5.770 sys/ipb/trans/sm/addr_reg[31]_0[17]_repN SLICE_X83Y138 LUT4 (Prop_lut4_I2_O) 0.123 5.893 r sys/ipb/trans/sm/ipb_mosi_o[13][ipb_strobe]_inferred_i_8/O net (fo=3, routed) 0.436 6.330 sys/ipb/trans/sm/ipb_mosi_o[13][ipb_strobe]_inferred_i_8_n_0 SLICE_X83Y139 LUT6 (Prop_lut6_I2_O) 0.043 6.373 r sys/ipb/trans/sm/ipb_mosi_o[13][ipb_strobe]_inferred_i_4/O net (fo=5, routed) 0.212 6.585 sys/ipb/trans/sm/ipb_mosi_o[13][ipb_strobe]_inferred_i_4_n_0 SLICE_X82Y140 LUT6 (Prop_lut6_I0_O) 0.043 6.628 r sys/ipb/trans/sm/ack_i_5/O net (fo=15, routed) 0.550 7.178 sys/ipb/trans/sm/ack_i_5_n_0 SLICE_X79Y138 LUT6 (Prop_lut6_I4_O) 0.043 7.221 r sys/ipb/trans/sm/ipb_mosi_o[8][ipb_strobe]_inferred_i_2/O net (fo=33, routed) 0.652 7.873 sys/ipb/trans/sm/ipb_mosi_o[8][ipb_strobe]_inferred_i_2_n_0 SLICE_X78Y122 LUT5 (Prop_lut5_I0_O) 0.043 7.916 r sys/ipb/trans/sm/ipb_mosi_o[8][ipb_strobe]_inferred_i_1/O net (fo=47, routed) 0.573 8.489 sys/ipb_mosi[8][ipb_strobe] SLICE_X77Y109 LUT6 (Prop_lut6_I4_O) 0.043 8.532 r sys/ipb_miso_i[8][ipb_ack]_inferred_i_8/O net (fo=1, routed) 0.336 8.868 sys/ipb_miso_i[8][ipb_ack]_inferred_i_8_n_0 SLICE_X79Y106 LUT6 (Prop_lut6_I0_O) 0.043 8.911 r sys/ipb_miso_i[8][ipb_ack]_inferred_i_4/O net (fo=1, routed) 0.000 8.911 sys/ipb_miso_i[8][ipb_ack]_inferred_i_4_n_0 SLICE_X79Y106 MUXF7 (Prop_muxf7_I0_O) 0.120 9.031 r sys/ipb_miso_i[8][ipb_ack]_inferred_i_2/O net (fo=1, routed) 0.000 9.031 sys/ipb_miso_i[8][ipb_ack]_inferred_i_2_n_0 SLICE_X79Y106 MUXF8 (Prop_muxf8_I0_O) 0.045 9.076 r sys/ipb_miso_i[8][ipb_ack]_inferred_i_1/O net (fo=1, routed) 0.964 10.040 sys/ipb_fabric/addr[31]_i_3_5 SLICE_X84Y137 LUT6 (Prop_lut6_I5_O) 0.126 10.166 r sys/ipb_fabric/addr[31]_i_7/O net (fo=1, routed) 0.105 10.271 sys/icap_if/icapInterface/addr_reg[31]_2 SLICE_X84Y137 LUT5 (Prop_lut5_I4_O) 0.043 10.314 r sys/icap_if/icapInterface/addr[31]_i_3/O net (fo=2, routed) 0.248 10.562 sys/ipb/trans/sm/addr_reg[31]_1 SLICE_X83Y137 LUT4 (Prop_lut4_I3_O) 0.043 10.605 r sys/ipb/trans/sm/words_todo[7]_i_3/O net (fo=38, routed) 0.331 10.936 sys/ipb/trans/sm/ack SLICE_X81Y137 LUT4 (Prop_lut4_I1_O) 0.049 10.985 f sys/ipb/trans/sm/ram_reg_0_i_15/O net (fo=6, routed) 0.343 11.328 sys/ipb/trans/iface/first_reg_0 SLICE_X81Y137 LUT5 (Prop_lut5_I4_O) 0.136 11.464 r sys/ipb/trans/iface/ram_reg_0_i_1/O net (fo=9, routed) 0.579 12.043 sys/ipb/udp_if/clock_crossing_if/we_buf_reg[0]_0[0] SLICE_X81Y136 FDRE r sys/ipb/udp_if/clock_crossing_if/we_buf_reg[0]/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 12.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -3.847 8.575 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.078 10.653 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.260 11.996 sys/ipb/udp_if/clock_crossing_if/busy_down_tff_reg_0 SLICE_X81Y136 FDRE r sys/ipb/udp_if/clock_crossing_if/we_buf_reg[0]/C clock pessimism 0.874 12.870 clock uncertainty -0.189 12.681 SLICE_X81Y136 FDRE (Setup_fdre_C_D) -0.019 12.662 sys/ipb/udp_if/clock_crossing_if/we_buf_reg[0] ------------------------------------------------------------------- required time 12.662 arrival time -12.043 ------------------------------------------------------------------- slack 0.619 Slack (MET) : 4.996ns (required time - arrival time) Source: sys/ip_mac/mac_addr_o_reg[27]/C (rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[27]__1/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125_ub rise@8.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 2.484ns (logic 0.311ns (12.520%) route 2.173ns (87.480%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.223ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.042ns = ( 12.042 - 8.000 ) Source Clock Delay (SCD): 5.139ns Clock Pessimism Removal (CPR): 0.874ns Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.205 3.654 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.392 5.139 sys/ip_mac/out SLICE_X80Y135 FDCE r sys/ip_mac/mac_addr_o_reg[27]/C ------------------------------------------------------------------- ------------------- SLICE_X80Y135 FDCE (Prop_fdce_C_Q) 0.259 5.398 r sys/ip_mac/mac_addr_o_reg[27]/Q net (fo=9, routed) 1.861 7.259 sys/ipb/udp_if/rx_reset_block/pkt_data_reg[127]_0[27] SLICE_X61Y125 LUT3 (Prop_lut3_I0_O) 0.052 7.311 r sys/ipb/udp_if/rx_reset_block/pkt_data[27]__1_i_1/O net (fo=1, routed) 0.312 7.623 sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[47]__1_1[19] SLICE_X63Y125 FDRE r sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[27]__1/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 12.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -3.847 8.575 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.078 10.653 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.306 12.042 sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[83]__1_0 SLICE_X63Y125 FDRE r sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[27]__1/C clock pessimism 0.874 12.916 clock uncertainty -0.189 12.727 SLICE_X63Y125 FDRE (Setup_fdre_C_D) -0.108 12.619 sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[27]__1 ------------------------------------------------------------------- required time 12.619 arrival time -7.623 ------------------------------------------------------------------- slack 4.996 Slack (MET) : 5.151ns (required time - arrival time) Source: sys/ip_mac/mac_addr_o_reg[15]/C (rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[95]/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125_ub rise@8.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 2.341ns (logic 0.277ns (11.832%) route 2.064ns (88.168%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.217ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.049ns = ( 12.049 - 8.000 ) Source Clock Delay (SCD): 5.140ns Clock Pessimism Removal (CPR): 0.874ns Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.205 3.654 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.393 5.140 sys/ip_mac/out SLICE_X77Y135 FDCE r sys/ip_mac/mac_addr_o_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X77Y135 FDCE (Prop_fdce_C_Q) 0.223 5.363 r sys/ip_mac/mac_addr_o_reg[15]/Q net (fo=9, routed) 1.611 6.973 sys/ipb/udp_if/rx_reset_block/pkt_data_reg[127]_0[15] SLICE_X63Y132 LUT3 (Prop_lut3_I0_O) 0.054 7.027 r sys/ipb/udp_if/rx_reset_block/pkt_data[95]_i_1/O net (fo=1, routed) 0.453 7.481 sys/ipb/udp_if/rx_packet_parser/D[39] SLICE_X64Y132 FDRE r sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[95]/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 12.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -3.847 8.575 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.078 10.653 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.313 12.049 sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[83]__1_0 SLICE_X64Y132 FDRE r sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[95]/C clock pessimism 0.874 12.923 clock uncertainty -0.189 12.734 SLICE_X64Y132 FDRE (Setup_fdre_C_D) -0.102 12.632 sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[95] ------------------------------------------------------------------- required time 12.632 arrival time -7.481 ------------------------------------------------------------------- slack 5.151 Slack (MET) : 5.153ns (required time - arrival time) Source: sys/ip_mac/mac_addr_o_reg[17]/C (rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[97]/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125_ub rise@8.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 2.330ns (logic 0.305ns (13.093%) route 2.025ns (86.907%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.048ns = ( 12.048 - 8.000 ) Source Clock Delay (SCD): 5.143ns Clock Pessimism Removal (CPR): 0.874ns Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.205 3.654 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.396 5.143 sys/ip_mac/out SLICE_X74Y137 FDCE r sys/ip_mac/mac_addr_o_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X74Y137 FDCE (Prop_fdce_C_Q) 0.259 5.402 r sys/ip_mac/mac_addr_o_reg[17]/Q net (fo=9, routed) 1.581 6.983 sys/ipb/udp_if/rx_reset_block/pkt_data_reg[127]_0[17] SLICE_X66Y130 LUT3 (Prop_lut3_I0_O) 0.046 7.029 r sys/ipb/udp_if/rx_reset_block/pkt_data[97]_i_1/O net (fo=1, routed) 0.443 7.472 sys/ipb/udp_if/rx_packet_parser/D[41] SLICE_X64Y130 FDRE r sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[97]/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 12.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -3.847 8.575 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.078 10.653 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.312 12.048 sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[83]__1_0 SLICE_X64Y130 FDRE r sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[97]/C clock pessimism 0.874 12.922 clock uncertainty -0.189 12.733 SLICE_X64Y130 FDRE (Setup_fdre_C_D) -0.108 12.625 sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[97] ------------------------------------------------------------------- required time 12.625 arrival time -7.472 ------------------------------------------------------------------- slack 5.153 Slack (MET) : 5.226ns (required time - arrival time) Source: sys/ip_mac/mac_addr_o_reg[12]/C (rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[92]/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125_ub rise@8.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 2.253ns (logic 0.310ns (13.758%) route 1.943ns (86.242%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.219ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.047ns = ( 12.047 - 8.000 ) Source Clock Delay (SCD): 5.140ns Clock Pessimism Removal (CPR): 0.874ns Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.205 3.654 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.393 5.140 sys/ip_mac/out SLICE_X74Y135 FDCE r sys/ip_mac/mac_addr_o_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X74Y135 FDCE (Prop_fdce_C_Q) 0.259 5.399 r sys/ip_mac/mac_addr_o_reg[12]/Q net (fo=9, routed) 1.477 6.875 sys/ipb/udp_if/rx_reset_block/pkt_data_reg[127]_0[12] SLICE_X66Y130 LUT3 (Prop_lut3_I0_O) 0.051 6.926 r sys/ipb/udp_if/rx_reset_block/pkt_data[92]_i_1/O net (fo=1, routed) 0.466 7.393 sys/ipb/udp_if/rx_packet_parser/D[36] SLICE_X67Y131 FDRE r sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[92]/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 12.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -3.847 8.575 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.078 10.653 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.311 12.047 sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[83]__1_0 SLICE_X67Y131 FDRE r sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[92]/C clock pessimism 0.874 12.921 clock uncertainty -0.189 12.732 SLICE_X67Y131 FDRE (Setup_fdre_C_D) -0.113 12.619 sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[92] ------------------------------------------------------------------- required time 12.619 arrival time -7.393 ------------------------------------------------------------------- slack 5.226 Slack (MET) : 5.242ns (required time - arrival time) Source: sys/ip_mac/mac_addr_o_reg[18]/C (rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[98]/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125_ub rise@8.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 2.241ns (logic 0.313ns (13.966%) route 1.928ns (86.034%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.212ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.049ns = ( 12.049 - 8.000 ) Source Clock Delay (SCD): 5.135ns Clock Pessimism Removal (CPR): 0.874ns Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.205 3.654 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.388 5.135 sys/ip_mac/out SLICE_X84Y132 FDCE r sys/ip_mac/mac_addr_o_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X84Y132 FDCE (Prop_fdce_C_Q) 0.259 5.394 r sys/ip_mac/mac_addr_o_reg[18]/Q net (fo=9, routed) 1.654 7.048 sys/ipb/udp_if/rx_reset_block/pkt_data_reg[127]_0[18] SLICE_X61Y130 LUT3 (Prop_lut3_I0_O) 0.054 7.102 r sys/ipb/udp_if/rx_reset_block/pkt_data[98]_i_1/O net (fo=1, routed) 0.274 7.376 sys/ipb/udp_if/rx_packet_parser/D[42] SLICE_X61Y129 FDRE r sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[98]/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 12.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -3.847 8.575 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.078 10.653 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.313 12.049 sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[83]__1_0 SLICE_X61Y129 FDRE r sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[98]/C clock pessimism 0.874 12.923 clock uncertainty -0.189 12.734 SLICE_X61Y129 FDRE (Setup_fdre_C_D) -0.116 12.618 sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[98] ------------------------------------------------------------------- required time 12.618 arrival time -7.376 ------------------------------------------------------------------- slack 5.242 Slack (MET) : 5.263ns (required time - arrival time) Source: sys/ip_mac/mac_addr_o_reg[24]/C (rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[24]__1/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125_ub rise@8.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 2.256ns (logic 0.335ns (14.852%) route 1.921ns (85.148%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.221ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.045ns = ( 12.045 - 8.000 ) Source Clock Delay (SCD): 5.140ns Clock Pessimism Removal (CPR): 0.874ns Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.205 3.654 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.393 5.140 sys/ip_mac/out SLICE_X77Y135 FDCE r sys/ip_mac/mac_addr_o_reg[24]/C ------------------------------------------------------------------- ------------------- SLICE_X77Y135 FDCE (Prop_fdce_C_Q) 0.204 5.344 r sys/ip_mac/mac_addr_o_reg[24]/Q net (fo=9, routed) 1.533 6.876 sys/ipb/udp_if/rx_reset_block/pkt_data_reg[127]_0[24] SLICE_X63Y129 LUT3 (Prop_lut3_I0_O) 0.131 7.007 r sys/ipb/udp_if/rx_reset_block/pkt_data[24]__1_i_1/O net (fo=1, routed) 0.388 7.395 sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[47]__1_1[16] SLICE_X62Y128 FDRE r sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[24]__1/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 12.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -3.847 8.575 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.078 10.653 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.309 12.045 sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[83]__1_0 SLICE_X62Y128 FDRE r sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[24]__1/C clock pessimism 0.874 12.919 clock uncertainty -0.189 12.730 SLICE_X62Y128 FDRE (Setup_fdre_C_D) -0.072 12.658 sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[24]__1 ------------------------------------------------------------------- required time 12.658 arrival time -7.395 ------------------------------------------------------------------- slack 5.263 Slack (MET) : 5.358ns (required time - arrival time) Source: sys/ip_mac/mac_addr_o_reg[21]/C (rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[21]__3/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125_ub rise@8.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 2.134ns (logic 0.272ns (12.744%) route 1.862ns (87.256%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.217ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.049ns = ( 12.049 - 8.000 ) Source Clock Delay (SCD): 5.140ns Clock Pessimism Removal (CPR): 0.874ns Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.205 3.654 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.393 5.140 sys/ip_mac/out SLICE_X77Y135 FDCE r sys/ip_mac/mac_addr_o_reg[21]/C ------------------------------------------------------------------- ------------------- SLICE_X77Y135 FDCE (Prop_fdce_C_Q) 0.223 5.363 r sys/ip_mac/mac_addr_o_reg[21]/Q net (fo=9, routed) 1.433 6.796 sys/ipb/udp_if/rx_reset_block/pkt_data_reg[127]_0[21] SLICE_X63Y133 LUT3 (Prop_lut3_I0_O) 0.049 6.845 r sys/ipb/udp_if/rx_reset_block/pkt_data[21]__3_i_1/O net (fo=1, routed) 0.429 7.274 sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[47]__1_1[13] SLICE_X63Y132 FDRE r sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[21]__3/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 12.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -3.847 8.575 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.078 10.653 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.313 12.049 sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[83]__1_0 SLICE_X63Y132 FDRE r sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[21]__3/C clock pessimism 0.874 12.923 clock uncertainty -0.189 12.734 SLICE_X63Y132 FDRE (Setup_fdre_C_D) -0.102 12.632 sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[21]__3 ------------------------------------------------------------------- required time 12.632 arrival time -7.274 ------------------------------------------------------------------- slack 5.358 Slack (MET) : 5.397ns (required time - arrival time) Source: sys/ip_mac/mac_addr_o_reg[40]/C (rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[40]__1/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125_ub rise@8.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 2.081ns (logic 0.365ns (17.542%) route 1.716ns (82.458%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.219ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.045ns = ( 12.045 - 8.000 ) Source Clock Delay (SCD): 5.138ns Clock Pessimism Removal (CPR): 0.874ns Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.205 3.654 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.391 5.138 sys/ip_mac/out SLICE_X74Y133 FDCE r sys/ip_mac/mac_addr_o_reg[40]/C ------------------------------------------------------------------- ------------------- SLICE_X74Y133 FDCE (Prop_fdce_C_Q) 0.236 5.374 r sys/ip_mac/mac_addr_o_reg[40]/Q net (fo=8, routed) 1.263 6.637 sys/ipb/udp_if/rx_reset_block/pkt_data_reg[127]_0[40] SLICE_X63Y127 LUT3 (Prop_lut3_I0_O) 0.129 6.766 r sys/ipb/udp_if/rx_reset_block/pkt_data[40]__1_i_1/O net (fo=1, routed) 0.453 7.218 sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[47]__1_1[32] SLICE_X57Y125 FDRE r sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[40]__1/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 12.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -3.847 8.575 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.078 10.653 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.309 12.045 sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[83]__1_0 SLICE_X57Y125 FDRE r sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[40]__1/C clock pessimism 0.874 12.919 clock uncertainty -0.189 12.730 SLICE_X57Y125 FDRE (Setup_fdre_C_D) -0.115 12.615 sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[40]__1 ------------------------------------------------------------------- required time 12.615 arrival time -7.218 ------------------------------------------------------------------- slack 5.397 Slack (MET) : 5.416ns (required time - arrival time) Source: sys/ip_mac/mac_addr_o_reg[24]/C (rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: sys/ipb/udp_if/RARP_block/x_reg[8]/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk125_ub rise@8.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 2.240ns (logic 0.334ns (14.913%) route 1.906ns (85.087%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: -0.214ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.052ns = ( 12.052 - 8.000 ) Source Clock Delay (SCD): 5.140ns Clock Pessimism Removal (CPR): 0.874ns Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.205 3.654 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.393 5.140 sys/ip_mac/out SLICE_X77Y135 FDCE r sys/ip_mac/mac_addr_o_reg[24]/C ------------------------------------------------------------------- ------------------- SLICE_X77Y135 FDCE (Prop_fdce_C_Q) 0.204 5.344 r sys/ip_mac/mac_addr_o_reg[24]/Q net (fo=9, routed) 1.906 7.249 sys/ip_mac/Q[24] SLICE_X61Y133 LUT3 (Prop_lut3_I0_O) 0.130 7.379 r sys/ip_mac/x[8]_i_1/O net (fo=1, routed) 0.000 7.379 sys/ipb/udp_if/RARP_block/x_reg[15]_1[8] SLICE_X61Y133 FDRE r sys/ipb/udp_if/RARP_block/x_reg[8]/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 12.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -3.847 8.575 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.078 10.653 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.316 12.052 sys/ipb/udp_if/RARP_block/rarp_req_reg_rep__0_0 SLICE_X61Y133 FDRE r sys/ipb/udp_if/RARP_block/x_reg[8]/C clock pessimism 0.874 12.926 clock uncertainty -0.189 12.737 SLICE_X61Y133 FDRE (Setup_fdre_C_D) 0.058 12.795 sys/ipb/udp_if/RARP_block/x_reg[8] ------------------------------------------------------------------- required time 12.795 arrival time -7.379 ------------------------------------------------------------------- slack 5.416 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.057ns (arrival time - required time) Source: sys/ip_mac/ip_addr_o_reg[6]/C (rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: sys/ipb/udp_if/IPADDR/My_IP_addr_reg[6]/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125_ub rise@0.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 0.605ns (logic 0.155ns (25.637%) route 0.450ns (74.363%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.298ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.228ns Source Clock Delay (SCD): 1.668ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 1.004 1.017 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 0.625 1.668 sys/ip_mac/out SLICE_X56Y131 FDCE r sys/ip_mac/ip_addr_o_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y131 FDCE (Prop_fdce_C_Q) 0.091 1.759 r sys/ip_mac/ip_addr_o_reg[6]/Q net (fo=1, routed) 0.450 2.208 sys/ipb/udp_if/IPADDR/My_IP_addr_reg[31]_1[6] SLICE_X51Y132 LUT6 (Prop_lut6_I4_O) 0.064 2.272 r sys/ipb/udp_if/IPADDR/My_IP_addr[6]_i_1/O net (fo=1, routed) 0.000 2.272 sys/ipb/udp_if/IPADDR/My_IP_addr[6]_i_1_n_0 SLICE_X51Y132 FDRE r sys/ipb/udp_if/IPADDR/My_IP_addr_reg[6]/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.073 1.348 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.850 2.228 sys/ipb/udp_if/IPADDR/pkt_mask_reg[41]_0 SLICE_X51Y132 FDRE r sys/ipb/udp_if/IPADDR/My_IP_addr_reg[6]/C clock pessimism -0.262 1.966 clock uncertainty 0.189 2.154 SLICE_X51Y132 FDRE (Hold_fdre_C_D) 0.061 2.215 sys/ipb/udp_if/IPADDR/My_IP_addr_reg[6] ------------------------------------------------------------------- required time -2.215 arrival time 2.272 ------------------------------------------------------------------- slack 0.057 Slack (MET) : 0.058ns (arrival time - required time) Source: sys/ip_mac/ip_addr_o_reg[9]/C (rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: sys/ipb/udp_if/IPADDR/My_IP_addr_reg[9]/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125_ub rise@0.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 0.602ns (logic 0.128ns (21.278%) route 0.474ns (78.722%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.294ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.218ns Source Clock Delay (SCD): 1.662ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 1.004 1.017 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 0.619 1.662 sys/ip_mac/out SLICE_X68Y129 FDCE r sys/ip_mac/ip_addr_o_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X68Y129 FDCE (Prop_fdce_C_Q) 0.100 1.762 r sys/ip_mac/ip_addr_o_reg[9]/Q net (fo=1, routed) 0.474 2.235 sys/ipb/udp_if/IPADDR/My_IP_addr_reg[31]_1[9] SLICE_X59Y127 LUT6 (Prop_lut6_I4_O) 0.028 2.263 r sys/ipb/udp_if/IPADDR/My_IP_addr[9]_i_1/O net (fo=1, routed) 0.000 2.263 sys/ipb/udp_if/IPADDR/My_IP_addr[9]_i_1_n_0 SLICE_X59Y127 FDRE r sys/ipb/udp_if/IPADDR/My_IP_addr_reg[9]/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.073 1.348 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.840 2.218 sys/ipb/udp_if/IPADDR/pkt_mask_reg[41]_0 SLICE_X59Y127 FDRE r sys/ipb/udp_if/IPADDR/My_IP_addr_reg[9]/C clock pessimism -0.262 1.956 clock uncertainty 0.189 2.144 SLICE_X59Y127 FDRE (Hold_fdre_C_D) 0.061 2.205 sys/ipb/udp_if/IPADDR/My_IP_addr_reg[9] ------------------------------------------------------------------- required time -2.205 arrival time 2.263 ------------------------------------------------------------------- slack 0.058 Slack (MET) : 0.059ns (arrival time - required time) Source: sys/ip_mac/ip_addr_o_reg[19]/C (rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: sys/ipb/udp_if/IPADDR/My_IP_addr_reg[19]/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125_ub rise@0.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 0.599ns (logic 0.146ns (24.360%) route 0.453ns (75.640%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.292ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.219ns Source Clock Delay (SCD): 1.665ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 1.004 1.017 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 0.622 1.665 sys/ip_mac/out SLICE_X66Y132 FDCE r sys/ip_mac/ip_addr_o_reg[19]/C ------------------------------------------------------------------- ------------------- SLICE_X66Y132 FDCE (Prop_fdce_C_Q) 0.118 1.783 r sys/ip_mac/ip_addr_o_reg[19]/Q net (fo=1, routed) 0.453 2.236 sys/ipb/udp_if/IPADDR/My_IP_addr_reg[31]_1[19] SLICE_X57Y127 LUT6 (Prop_lut6_I4_O) 0.028 2.264 r sys/ipb/udp_if/IPADDR/My_IP_addr[19]_i_1/O net (fo=1, routed) 0.000 2.264 sys/ipb/udp_if/IPADDR/My_IP_addr[19]_i_1_n_0 SLICE_X57Y127 FDRE r sys/ipb/udp_if/IPADDR/My_IP_addr_reg[19]/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.073 1.348 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.841 2.219 sys/ipb/udp_if/IPADDR/pkt_mask_reg[41]_0 SLICE_X57Y127 FDRE r sys/ipb/udp_if/IPADDR/My_IP_addr_reg[19]/C clock pessimism -0.262 1.957 clock uncertainty 0.189 2.145 SLICE_X57Y127 FDRE (Hold_fdre_C_D) 0.060 2.205 sys/ipb/udp_if/IPADDR/My_IP_addr_reg[19] ------------------------------------------------------------------- required time -2.205 arrival time 2.264 ------------------------------------------------------------------- slack 0.059 Slack (MET) : 0.060ns (arrival time - required time) Source: sys/ip_mac/ip_addr_o_reg[25]/C (rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: sys/ipb/udp_if/IPADDR/My_IP_addr_reg[25]/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125_ub rise@0.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 0.602ns (logic 0.128ns (21.251%) route 0.474ns (78.749%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.294ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.218ns Source Clock Delay (SCD): 1.662ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 1.004 1.017 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 0.619 1.662 sys/ip_mac/out SLICE_X69Y129 FDCE r sys/ip_mac/ip_addr_o_reg[25]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y129 FDCE (Prop_fdce_C_Q) 0.100 1.762 r sys/ip_mac/ip_addr_o_reg[25]/Q net (fo=1, routed) 0.474 2.236 sys/ipb/udp_if/IPADDR/My_IP_addr_reg[31]_1[25] SLICE_X59Y127 LUT6 (Prop_lut6_I4_O) 0.028 2.264 r sys/ipb/udp_if/IPADDR/My_IP_addr[25]_i_1/O net (fo=1, routed) 0.000 2.264 sys/ipb/udp_if/IPADDR/My_IP_addr[25]_i_1_n_0 SLICE_X59Y127 FDRE r sys/ipb/udp_if/IPADDR/My_IP_addr_reg[25]/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.073 1.348 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.840 2.218 sys/ipb/udp_if/IPADDR/pkt_mask_reg[41]_0 SLICE_X59Y127 FDRE r sys/ipb/udp_if/IPADDR/My_IP_addr_reg[25]/C clock pessimism -0.262 1.956 clock uncertainty 0.189 2.144 SLICE_X59Y127 FDRE (Hold_fdre_C_D) 0.060 2.204 sys/ipb/udp_if/IPADDR/My_IP_addr_reg[25] ------------------------------------------------------------------- required time -2.204 arrival time 2.264 ------------------------------------------------------------------- slack 0.060 Slack (MET) : 0.060ns (arrival time - required time) Source: sys/ip_mac/ip_addr_o_reg[22]/C (rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: sys/ipb/udp_if/IPADDR/My_IP_addr_reg[22]/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125_ub rise@0.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 0.634ns (logic 0.128ns (20.203%) route 0.506ns (79.797%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.298ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.228ns Source Clock Delay (SCD): 1.668ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 1.004 1.017 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 0.625 1.668 sys/ip_mac/out SLICE_X56Y131 FDCE r sys/ip_mac/ip_addr_o_reg[22]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y131 FDCE (Prop_fdce_C_Q) 0.100 1.768 r sys/ip_mac/ip_addr_o_reg[22]/Q net (fo=1, routed) 0.506 2.273 sys/ipb/udp_if/IPADDR/My_IP_addr_reg[31]_1[22] SLICE_X50Y132 LUT6 (Prop_lut6_I4_O) 0.028 2.301 r sys/ipb/udp_if/IPADDR/My_IP_addr[22]_i_1/O net (fo=1, routed) 0.000 2.301 sys/ipb/udp_if/IPADDR/My_IP_addr[22]_i_1_n_0 SLICE_X50Y132 FDRE r sys/ipb/udp_if/IPADDR/My_IP_addr_reg[22]/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.073 1.348 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.850 2.228 sys/ipb/udp_if/IPADDR/pkt_mask_reg[41]_0 SLICE_X50Y132 FDRE r sys/ipb/udp_if/IPADDR/My_IP_addr_reg[22]/C clock pessimism -0.262 1.966 clock uncertainty 0.189 2.154 SLICE_X50Y132 FDRE (Hold_fdre_C_D) 0.087 2.241 sys/ipb/udp_if/IPADDR/My_IP_addr_reg[22] ------------------------------------------------------------------- required time -2.241 arrival time 2.301 ------------------------------------------------------------------- slack 0.060 Slack (MET) : 0.061ns (arrival time - required time) Source: sys/ip_mac/ip_addr_o_reg[30]/C (rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: sys/ipb/udp_if/IPADDR/My_IP_addr_reg[30]/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125_ub rise@0.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 0.609ns (logic 0.128ns (21.032%) route 0.481ns (78.968%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.299ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.228ns Source Clock Delay (SCD): 1.667ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 1.004 1.017 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 0.624 1.667 sys/ip_mac/out SLICE_X65Y132 FDCE r sys/ip_mac/ip_addr_o_reg[30]/C ------------------------------------------------------------------- ------------------- SLICE_X65Y132 FDCE (Prop_fdce_C_Q) 0.100 1.767 r sys/ip_mac/ip_addr_o_reg[30]/Q net (fo=1, routed) 0.481 2.247 sys/ipb/udp_if/IPADDR/My_IP_addr_reg[31]_1[30] SLICE_X51Y132 LUT6 (Prop_lut6_I4_O) 0.028 2.275 r sys/ipb/udp_if/IPADDR/My_IP_addr[30]_i_1/O net (fo=1, routed) 0.000 2.275 sys/ipb/udp_if/IPADDR/My_IP_addr[30]_i_1_n_0 SLICE_X51Y132 FDRE r sys/ipb/udp_if/IPADDR/My_IP_addr_reg[30]/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.073 1.348 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.850 2.228 sys/ipb/udp_if/IPADDR/pkt_mask_reg[41]_0 SLICE_X51Y132 FDRE r sys/ipb/udp_if/IPADDR/My_IP_addr_reg[30]/C clock pessimism -0.262 1.966 clock uncertainty 0.189 2.154 SLICE_X51Y132 FDRE (Hold_fdre_C_D) 0.060 2.214 sys/ipb/udp_if/IPADDR/My_IP_addr_reg[30] ------------------------------------------------------------------- required time -2.214 arrival time 2.275 ------------------------------------------------------------------- slack 0.061 Slack (MET) : 0.061ns (arrival time - required time) Source: sys/ip_mac/ip_addr_o_reg[13]/C (rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: sys/ipb/udp_if/IPADDR/My_IP_addr_reg[13]/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125_ub rise@0.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 0.605ns (logic 0.128ns (21.162%) route 0.477ns (78.838%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.295ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.223ns Source Clock Delay (SCD): 1.666ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 1.004 1.017 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 0.623 1.666 sys/ip_mac/out SLICE_X69Y133 FDCE r sys/ip_mac/ip_addr_o_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X69Y133 FDCE (Prop_fdce_C_Q) 0.100 1.766 r sys/ip_mac/ip_addr_o_reg[13]/Q net (fo=1, routed) 0.477 2.242 sys/ipb/udp_if/IPADDR/My_IP_addr_reg[31]_1[13] SLICE_X55Y131 LUT6 (Prop_lut6_I4_O) 0.028 2.270 r sys/ipb/udp_if/IPADDR/My_IP_addr[13]_i_1/O net (fo=1, routed) 0.000 2.270 sys/ipb/udp_if/IPADDR/My_IP_addr[13]_i_1_n_0 SLICE_X55Y131 FDRE r sys/ipb/udp_if/IPADDR/My_IP_addr_reg[13]/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.073 1.348 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.845 2.223 sys/ipb/udp_if/IPADDR/pkt_mask_reg[41]_0 SLICE_X55Y131 FDRE r sys/ipb/udp_if/IPADDR/My_IP_addr_reg[13]/C clock pessimism -0.262 1.961 clock uncertainty 0.189 2.149 SLICE_X55Y131 FDRE (Hold_fdre_C_D) 0.060 2.209 sys/ipb/udp_if/IPADDR/My_IP_addr_reg[13] ------------------------------------------------------------------- required time -2.209 arrival time 2.270 ------------------------------------------------------------------- slack 0.061 Slack (MET) : 0.063ns (arrival time - required time) Source: sys/ip_mac/mac_addr_o_reg[44]/C (rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[124]/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125_ub rise@0.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 0.632ns (logic 0.157ns (24.841%) route 0.475ns (75.159%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.320ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.218ns Source Clock Delay (SCD): 1.636ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 1.004 1.017 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 0.593 1.636 sys/ip_mac/out SLICE_X75Y135 FDCE r sys/ip_mac/mac_addr_o_reg[44]/C ------------------------------------------------------------------- ------------------- SLICE_X75Y135 FDCE (Prop_fdce_C_Q) 0.091 1.727 r sys/ip_mac/mac_addr_o_reg[44]/Q net (fo=8, routed) 0.475 2.202 sys/ipb/udp_if/rx_reset_block/pkt_data_reg[127]_0[44] SLICE_X65Y129 LUT3 (Prop_lut3_I0_O) 0.066 2.268 r sys/ipb/udp_if/rx_reset_block/pkt_data[124]_i_1/O net (fo=1, routed) 0.000 2.268 sys/ipb/udp_if/rx_packet_parser/D[68] SLICE_X65Y129 FDRE r sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[124]/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.073 1.348 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.840 2.218 sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[83]__1_0 SLICE_X65Y129 FDRE r sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[124]/C clock pessimism -0.262 1.956 clock uncertainty 0.189 2.144 SLICE_X65Y129 FDRE (Hold_fdre_C_D) 0.060 2.204 sys/ipb/udp_if/rx_packet_parser/pkt_data_reg[124] ------------------------------------------------------------------- required time -2.204 arrival time 2.268 ------------------------------------------------------------------- slack 0.063 Slack (MET) : 0.064ns (arrival time - required time) Source: sys/ip_mac/mac_addr_o_reg[33]/C (rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: sys/ipb/udp_if/RARP_block/data_buffer_reg[153]/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125_ub rise@0.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 0.635ns (logic 0.128ns (20.159%) route 0.507ns (79.841%)) Logic Levels: 1 (LUT4=1) Clock Path Skew: 0.321ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.218ns Source Clock Delay (SCD): 1.635ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 1.004 1.017 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 0.592 1.635 sys/ip_mac/out SLICE_X75Y133 FDCE r sys/ip_mac/mac_addr_o_reg[33]/C ------------------------------------------------------------------- ------------------- SLICE_X75Y133 FDCE (Prop_fdce_C_Q) 0.100 1.735 r sys/ip_mac/mac_addr_o_reg[33]/Q net (fo=8, routed) 0.507 2.242 sys/ipb/udp_if/RARP_block/data_buffer_reg[87]_0[33] SLICE_X69Y130 LUT4 (Prop_lut4_I1_O) 0.028 2.270 r sys/ipb/udp_if/RARP_block/data_buffer[153]_i_1/O net (fo=1, routed) 0.000 2.270 sys/ipb/udp_if/RARP_block/data_buffer0_out[145] SLICE_X69Y130 FDRE r sys/ipb/udp_if/RARP_block/data_buffer_reg[153]/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.073 1.348 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.840 2.218 sys/ipb/udp_if/RARP_block/rarp_req_reg_rep__0_0 SLICE_X69Y130 FDRE r sys/ipb/udp_if/RARP_block/data_buffer_reg[153]/C clock pessimism -0.262 1.956 clock uncertainty 0.189 2.144 SLICE_X69Y130 FDRE (Hold_fdre_C_D) 0.061 2.205 sys/ipb/udp_if/RARP_block/data_buffer_reg[153] ------------------------------------------------------------------- required time -2.205 arrival time 2.270 ------------------------------------------------------------------- slack 0.064 Slack (MET) : 0.066ns (arrival time - required time) Source: sys/ip_mac/ip_addr_o_reg[17]/C (rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: sys/ipb/udp_if/IPADDR/My_IP_addr_reg[17]/D (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: clk125_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk125_ub rise@0.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 0.605ns (logic 0.146ns (24.126%) route 0.459ns (75.874%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.291ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.218ns Source Clock Delay (SCD): 1.665ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 1.004 1.017 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 0.622 1.665 sys/ip_mac/out SLICE_X66Y132 FDCE r sys/ip_mac/ip_addr_o_reg[17]/C ------------------------------------------------------------------- ------------------- SLICE_X66Y132 FDCE (Prop_fdce_C_Q) 0.118 1.783 r sys/ip_mac/ip_addr_o_reg[17]/Q net (fo=1, routed) 0.459 2.242 sys/ipb/udp_if/IPADDR/My_IP_addr_reg[31]_1[17] SLICE_X59Y127 LUT6 (Prop_lut6_I4_O) 0.028 2.270 r sys/ipb/udp_if/IPADDR/My_IP_addr[17]_i_1/O net (fo=1, routed) 0.000 2.270 sys/ipb/udp_if/IPADDR/My_IP_addr[17]_i_1_n_0 SLICE_X59Y127 FDRE r sys/ipb/udp_if/IPADDR/My_IP_addr_reg[17]/D ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.073 1.348 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.840 2.218 sys/ipb/udp_if/IPADDR/pkt_mask_reg[41]_0 SLICE_X59Y127 FDRE r sys/ipb/udp_if/IPADDR/My_IP_addr_reg[17]/C clock pessimism -0.262 1.956 clock uncertainty 0.189 2.144 SLICE_X59Y127 FDRE (Hold_fdre_C_D) 0.060 2.204 sys/ipb/udp_if/IPADDR/My_IP_addr_reg[17] ------------------------------------------------------------------- required time -2.204 arrival time 2.270 ------------------------------------------------------------------- slack 0.066 --------------------------------------------------------------------------------------------------- From Clock: clk125_ub To Clock: clk62_5_ub Setup : 0 Failing Endpoints, Worst Slack 6.115ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.076ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 6.115ns (required time - arrival time) Source: sys/eth/phy/U0/transceiver_inst/txdata_double_reg[14]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/txdata_int_reg[14]/D (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk62_5_ub rise@16.000ns - clk125_ub rise@8.000ns) Data Path Delay: 1.417ns (logic 0.223ns (15.741%) route 1.194ns (84.259%)) Logic Levels: 0 Clock Path Skew: -0.276ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.150ns = ( 20.150 - 16.000 ) Source Clock Delay (SCD): 5.300ns = ( 13.300 - 8.000 ) Clock Pessimism Removal (CPR): 0.874ns Clock Uncertainty: 0.183ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 10.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 11.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 11.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 13.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -4.148 9.449 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.205 11.654 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 11.747 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.553 13.300 sys/eth/phy/U0/transceiver_inst/userclk2 SLICE_X189Y104 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_double_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X189Y104 FDRE (Prop_fdre_C_Q) 0.223 13.523 r sys/eth/phy/U0/transceiver_inst/txdata_double_reg[14]/Q net (fo=1, routed) 1.194 14.716 sys/eth/phy/U0/transceiver_inst/txdata_double[14] SLICE_X189Y103 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_int_reg[14]/D ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 16.000 16.000 r AD6 0.000 16.000 r osc125_a_p (IN) net (fo=0) 0.000 16.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 16.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 16.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 17.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 18.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 18.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 20.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -3.847 16.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 2.078 18.653 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.083 18.736 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.414 20.150 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X189Y103 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_int_reg[14]/C clock pessimism 0.874 21.024 clock uncertainty -0.183 20.841 SLICE_X189Y103 FDRE (Setup_fdre_C_D) -0.010 20.831 sys/eth/phy/U0/transceiver_inst/txdata_int_reg[14] ------------------------------------------------------------------- required time 20.831 arrival time -14.716 ------------------------------------------------------------------- slack 6.115 Slack (MET) : 6.168ns (required time - arrival time) Source: sys/eth/phy/U0/transceiver_inst/txdata_double_reg[9]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/txdata_int_reg[9]/D (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk62_5_ub rise@16.000ns - clk125_ub rise@8.000ns) Data Path Delay: 1.285ns (logic 0.204ns (15.879%) route 1.081ns (84.121%)) Logic Levels: 0 Clock Path Skew: -0.276ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.150ns = ( 20.150 - 16.000 ) Source Clock Delay (SCD): 5.300ns = ( 13.300 - 8.000 ) Clock Pessimism Removal (CPR): 0.874ns Clock Uncertainty: 0.183ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 10.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 11.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 11.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 13.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -4.148 9.449 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.205 11.654 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 11.747 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.553 13.300 sys/eth/phy/U0/transceiver_inst/userclk2 SLICE_X189Y105 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_double_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X189Y105 FDRE (Prop_fdre_C_Q) 0.204 13.504 r sys/eth/phy/U0/transceiver_inst/txdata_double_reg[9]/Q net (fo=1, routed) 1.081 14.584 sys/eth/phy/U0/transceiver_inst/txdata_double[9] SLICE_X188Y105 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_int_reg[9]/D ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 16.000 16.000 r AD6 0.000 16.000 r osc125_a_p (IN) net (fo=0) 0.000 16.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 16.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 16.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 17.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 18.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 18.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 20.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -3.847 16.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 2.078 18.653 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.083 18.736 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.414 20.150 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X188Y105 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_int_reg[9]/C clock pessimism 0.874 21.024 clock uncertainty -0.183 20.841 SLICE_X188Y105 FDRE (Setup_fdre_C_D) -0.089 20.752 sys/eth/phy/U0/transceiver_inst/txdata_int_reg[9] ------------------------------------------------------------------- required time 20.752 arrival time -14.584 ------------------------------------------------------------------- slack 6.168 Slack (MET) : 6.189ns (required time - arrival time) Source: sys/eth/phy/U0/transceiver_inst/txdata_double_reg[3]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/txdata_int_reg[3]/D (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk62_5_ub rise@16.000ns - clk125_ub rise@8.000ns) Data Path Delay: 1.253ns (logic 0.204ns (16.276%) route 1.049ns (83.724%)) Logic Levels: 0 Clock Path Skew: -0.276ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.149ns = ( 20.149 - 16.000 ) Source Clock Delay (SCD): 5.299ns = ( 13.299 - 8.000 ) Clock Pessimism Removal (CPR): 0.874ns Clock Uncertainty: 0.183ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 10.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 11.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 11.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 13.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -4.148 9.449 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.205 11.654 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 11.747 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.552 13.299 sys/eth/phy/U0/transceiver_inst/userclk2 SLICE_X187Y106 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_double_reg[3]/C ------------------------------------------------------------------- ------------------- SLICE_X187Y106 FDRE (Prop_fdre_C_Q) 0.204 13.503 r sys/eth/phy/U0/transceiver_inst/txdata_double_reg[3]/Q net (fo=1, routed) 1.049 14.552 sys/eth/phy/U0/transceiver_inst/txdata_double[3] SLICE_X188Y106 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_int_reg[3]/D ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 16.000 16.000 r AD6 0.000 16.000 r osc125_a_p (IN) net (fo=0) 0.000 16.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 16.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 16.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 17.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 18.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 18.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 20.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -3.847 16.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 2.078 18.653 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.083 18.736 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.413 20.149 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X188Y106 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_int_reg[3]/C clock pessimism 0.874 21.023 clock uncertainty -0.183 20.840 SLICE_X188Y106 FDRE (Setup_fdre_C_D) -0.099 20.741 sys/eth/phy/U0/transceiver_inst/txdata_int_reg[3] ------------------------------------------------------------------- required time 20.741 arrival time -14.552 ------------------------------------------------------------------- slack 6.189 Slack (MET) : 6.194ns (required time - arrival time) Source: sys/eth/phy/U0/transceiver_inst/txchardispval_double_reg[1]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/txchardispval_int_reg[1]/D (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk62_5_ub rise@16.000ns - clk125_ub rise@8.000ns) Data Path Delay: 1.328ns (logic 0.223ns (16.793%) route 1.105ns (83.207%)) Logic Levels: 0 Clock Path Skew: -0.276ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.150ns = ( 20.150 - 16.000 ) Source Clock Delay (SCD): 5.300ns = ( 13.300 - 8.000 ) Clock Pessimism Removal (CPR): 0.874ns Clock Uncertainty: 0.183ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 10.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 11.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 11.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 13.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -4.148 9.449 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.205 11.654 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 11.747 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.553 13.300 sys/eth/phy/U0/transceiver_inst/userclk2 SLICE_X189Y104 FDRE r sys/eth/phy/U0/transceiver_inst/txchardispval_double_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X189Y104 FDRE (Prop_fdre_C_Q) 0.223 13.523 r sys/eth/phy/U0/transceiver_inst/txchardispval_double_reg[1]/Q net (fo=1, routed) 1.105 14.628 sys/eth/phy/U0/transceiver_inst/txchardispval_double[1] SLICE_X189Y103 FDRE r sys/eth/phy/U0/transceiver_inst/txchardispval_int_reg[1]/D ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 16.000 16.000 r AD6 0.000 16.000 r osc125_a_p (IN) net (fo=0) 0.000 16.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 16.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 16.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 17.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 18.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 18.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 20.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -3.847 16.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 2.078 18.653 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.083 18.736 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.414 20.150 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X189Y103 FDRE r sys/eth/phy/U0/transceiver_inst/txchardispval_int_reg[1]/C clock pessimism 0.874 21.024 clock uncertainty -0.183 20.841 SLICE_X189Y103 FDRE (Setup_fdre_C_D) -0.019 20.822 sys/eth/phy/U0/transceiver_inst/txchardispval_int_reg[1] ------------------------------------------------------------------- required time 20.822 arrival time -14.628 ------------------------------------------------------------------- slack 6.194 Slack (MET) : 6.229ns (required time - arrival time) Source: sys/eth/phy/U0/transceiver_inst/txchardispmode_double_reg[1]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/txchardispmode_int_reg[1]/D (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk62_5_ub rise@16.000ns - clk125_ub rise@8.000ns) Data Path Delay: 1.299ns (logic 0.223ns (17.166%) route 1.076ns (82.834%)) Logic Levels: 0 Clock Path Skew: -0.276ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.150ns = ( 20.150 - 16.000 ) Source Clock Delay (SCD): 5.300ns = ( 13.300 - 8.000 ) Clock Pessimism Removal (CPR): 0.874ns Clock Uncertainty: 0.183ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 10.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 11.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 11.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 13.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -4.148 9.449 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.205 11.654 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 11.747 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.553 13.300 sys/eth/phy/U0/transceiver_inst/userclk2 SLICE_X189Y104 FDRE r sys/eth/phy/U0/transceiver_inst/txchardispmode_double_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X189Y104 FDRE (Prop_fdre_C_Q) 0.223 13.523 r sys/eth/phy/U0/transceiver_inst/txchardispmode_double_reg[1]/Q net (fo=1, routed) 1.076 14.599 sys/eth/phy/U0/transceiver_inst/txchardispmode_double[1] SLICE_X189Y103 FDRE r sys/eth/phy/U0/transceiver_inst/txchardispmode_int_reg[1]/D ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 16.000 16.000 r AD6 0.000 16.000 r osc125_a_p (IN) net (fo=0) 0.000 16.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 16.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 16.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 17.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 18.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 18.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 20.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -3.847 16.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 2.078 18.653 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.083 18.736 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.414 20.150 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X189Y103 FDRE r sys/eth/phy/U0/transceiver_inst/txchardispmode_int_reg[1]/C clock pessimism 0.874 21.024 clock uncertainty -0.183 20.841 SLICE_X189Y103 FDRE (Setup_fdre_C_D) -0.013 20.828 sys/eth/phy/U0/transceiver_inst/txchardispmode_int_reg[1] ------------------------------------------------------------------- required time 20.828 arrival time -14.599 ------------------------------------------------------------------- slack 6.229 Slack (MET) : 6.237ns (required time - arrival time) Source: sys/eth/phy/U0/transceiver_inst/txdata_double_reg[13]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/txdata_int_reg[13]/D (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk62_5_ub rise@16.000ns - clk125_ub rise@8.000ns) Data Path Delay: 1.282ns (logic 0.223ns (17.388%) route 1.060ns (82.612%)) Logic Levels: 0 Clock Path Skew: -0.276ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.150ns = ( 20.150 - 16.000 ) Source Clock Delay (SCD): 5.300ns = ( 13.300 - 8.000 ) Clock Pessimism Removal (CPR): 0.874ns Clock Uncertainty: 0.183ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 10.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 11.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 11.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 13.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -4.148 9.449 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.205 11.654 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 11.747 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.553 13.300 sys/eth/phy/U0/transceiver_inst/userclk2 SLICE_X185Y103 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_double_reg[13]/C ------------------------------------------------------------------- ------------------- SLICE_X185Y103 FDRE (Prop_fdre_C_Q) 0.223 13.523 r sys/eth/phy/U0/transceiver_inst/txdata_double_reg[13]/Q net (fo=1, routed) 1.060 14.582 sys/eth/phy/U0/transceiver_inst/txdata_double[13] SLICE_X184Y104 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_int_reg[13]/D ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 16.000 16.000 r AD6 0.000 16.000 r osc125_a_p (IN) net (fo=0) 0.000 16.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 16.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 16.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 17.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 18.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 18.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 20.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -3.847 16.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 2.078 18.653 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.083 18.736 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.414 20.150 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X184Y104 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_int_reg[13]/C clock pessimism 0.874 21.024 clock uncertainty -0.183 20.841 SLICE_X184Y104 FDRE (Setup_fdre_C_D) -0.022 20.819 sys/eth/phy/U0/transceiver_inst/txdata_int_reg[13] ------------------------------------------------------------------- required time 20.819 arrival time -14.582 ------------------------------------------------------------------- slack 6.237 Slack (MET) : 6.238ns (required time - arrival time) Source: sys/eth/phy/U0/transceiver_inst/txdata_double_reg[6]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/txdata_int_reg[6]/D (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk62_5_ub rise@16.000ns - clk125_ub rise@8.000ns) Data Path Delay: 1.201ns (logic 0.204ns (16.980%) route 0.997ns (83.020%)) Logic Levels: 0 Clock Path Skew: -0.276ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.150ns = ( 20.150 - 16.000 ) Source Clock Delay (SCD): 5.300ns = ( 13.300 - 8.000 ) Clock Pessimism Removal (CPR): 0.874ns Clock Uncertainty: 0.183ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 10.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 11.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 11.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 13.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -4.148 9.449 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.205 11.654 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 11.747 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.553 13.300 sys/eth/phy/U0/transceiver_inst/userclk2 SLICE_X189Y105 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_double_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X189Y105 FDRE (Prop_fdre_C_Q) 0.204 13.504 r sys/eth/phy/U0/transceiver_inst/txdata_double_reg[6]/Q net (fo=1, routed) 0.997 14.501 sys/eth/phy/U0/transceiver_inst/txdata_double[6] SLICE_X188Y105 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_int_reg[6]/D ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 16.000 16.000 r AD6 0.000 16.000 r osc125_a_p (IN) net (fo=0) 0.000 16.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 16.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 16.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 17.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 18.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 18.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 20.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -3.847 16.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 2.078 18.653 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.083 18.736 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.414 20.150 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X188Y105 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_int_reg[6]/C clock pessimism 0.874 21.024 clock uncertainty -0.183 20.841 SLICE_X188Y105 FDRE (Setup_fdre_C_D) -0.102 20.739 sys/eth/phy/U0/transceiver_inst/txdata_int_reg[6] ------------------------------------------------------------------- required time 20.739 arrival time -14.501 ------------------------------------------------------------------- slack 6.238 Slack (MET) : 6.246ns (required time - arrival time) Source: sys/eth/phy/U0/transceiver_inst/txdata_double_reg[15]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/txdata_int_reg[15]/D (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk62_5_ub rise@16.000ns - clk125_ub rise@8.000ns) Data Path Delay: 1.277ns (logic 0.223ns (17.466%) route 1.054ns (82.534%)) Logic Levels: 0 Clock Path Skew: -0.276ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.150ns = ( 20.150 - 16.000 ) Source Clock Delay (SCD): 5.300ns = ( 13.300 - 8.000 ) Clock Pessimism Removal (CPR): 0.874ns Clock Uncertainty: 0.183ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 10.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 11.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 11.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 13.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -4.148 9.449 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.205 11.654 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 11.747 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.553 13.300 sys/eth/phy/U0/transceiver_inst/userclk2 SLICE_X189Y104 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_double_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X189Y104 FDRE (Prop_fdre_C_Q) 0.223 13.523 r sys/eth/phy/U0/transceiver_inst/txdata_double_reg[15]/Q net (fo=1, routed) 1.054 14.576 sys/eth/phy/U0/transceiver_inst/txdata_double[15] SLICE_X189Y103 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_int_reg[15]/D ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 16.000 16.000 r AD6 0.000 16.000 r osc125_a_p (IN) net (fo=0) 0.000 16.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 16.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 16.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 17.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 18.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 18.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 20.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -3.847 16.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 2.078 18.653 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.083 18.736 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.414 20.150 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X189Y103 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_int_reg[15]/C clock pessimism 0.874 21.024 clock uncertainty -0.183 20.841 SLICE_X189Y103 FDRE (Setup_fdre_C_D) -0.019 20.822 sys/eth/phy/U0/transceiver_inst/txdata_int_reg[15] ------------------------------------------------------------------- required time 20.822 arrival time -14.576 ------------------------------------------------------------------- slack 6.246 Slack (MET) : 6.246ns (required time - arrival time) Source: sys/eth/phy/U0/transceiver_inst/txdata_double_reg[10]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/txdata_int_reg[10]/D (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk62_5_ub rise@16.000ns - clk125_ub rise@8.000ns) Data Path Delay: 1.286ns (logic 0.223ns (17.335%) route 1.063ns (82.666%)) Logic Levels: 0 Clock Path Skew: -0.276ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.149ns = ( 20.149 - 16.000 ) Source Clock Delay (SCD): 5.299ns = ( 13.299 - 8.000 ) Clock Pessimism Removal (CPR): 0.874ns Clock Uncertainty: 0.183ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 10.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 11.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 11.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 13.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -4.148 9.449 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.205 11.654 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 11.747 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.552 13.299 sys/eth/phy/U0/transceiver_inst/userclk2 SLICE_X187Y106 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_double_reg[10]/C ------------------------------------------------------------------- ------------------- SLICE_X187Y106 FDRE (Prop_fdre_C_Q) 0.223 13.522 r sys/eth/phy/U0/transceiver_inst/txdata_double_reg[10]/Q net (fo=1, routed) 1.063 14.585 sys/eth/phy/U0/transceiver_inst/txdata_double[10] SLICE_X188Y106 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_int_reg[10]/D ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 16.000 16.000 r AD6 0.000 16.000 r osc125_a_p (IN) net (fo=0) 0.000 16.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 16.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 16.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 17.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 18.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 18.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 20.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -3.847 16.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 2.078 18.653 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.083 18.736 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.413 20.149 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X188Y106 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_int_reg[10]/C clock pessimism 0.874 21.023 clock uncertainty -0.183 20.840 SLICE_X188Y106 FDRE (Setup_fdre_C_D) -0.009 20.831 sys/eth/phy/U0/transceiver_inst/txdata_int_reg[10] ------------------------------------------------------------------- required time 20.831 arrival time -14.585 ------------------------------------------------------------------- slack 6.246 Slack (MET) : 6.246ns (required time - arrival time) Source: sys/eth/phy/U0/transceiver_inst/txdata_double_reg[2]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/txdata_int_reg[2]/D (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk62_5_ub rise@16.000ns - clk125_ub rise@8.000ns) Data Path Delay: 1.202ns (logic 0.204ns (16.969%) route 0.998ns (83.031%)) Logic Levels: 0 Clock Path Skew: -0.276ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.149ns = ( 20.149 - 16.000 ) Source Clock Delay (SCD): 5.299ns = ( 13.299 - 8.000 ) Clock Pessimism Removal (CPR): 0.874ns Clock Uncertainty: 0.183ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 10.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 11.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 11.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 13.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -4.148 9.449 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.205 11.654 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 11.747 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.552 13.299 sys/eth/phy/U0/transceiver_inst/userclk2 SLICE_X187Y106 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_double_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X187Y106 FDRE (Prop_fdre_C_Q) 0.204 13.503 r sys/eth/phy/U0/transceiver_inst/txdata_double_reg[2]/Q net (fo=1, routed) 0.998 14.501 sys/eth/phy/U0/transceiver_inst/txdata_double[2] SLICE_X188Y106 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_int_reg[2]/D ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 16.000 16.000 r AD6 0.000 16.000 r osc125_a_p (IN) net (fo=0) 0.000 16.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 16.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 16.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 17.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 18.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 18.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 20.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -3.847 16.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 2.078 18.653 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.083 18.736 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 1.413 20.149 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X188Y106 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_int_reg[2]/C clock pessimism 0.874 21.023 clock uncertainty -0.183 20.840 SLICE_X188Y106 FDRE (Setup_fdre_C_D) -0.093 20.747 sys/eth/phy/U0/transceiver_inst/txdata_int_reg[2] ------------------------------------------------------------------- required time 20.747 arrival time -14.501 ------------------------------------------------------------------- slack 6.246 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.076ns (arrival time - required time) Source: sys/eth/phy/U0/transceiver_inst/txcharisk_double_reg[0]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/txcharisk_int_reg[0]/D (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk62_5_ub rise@0.000ns - clk125_ub rise@0.000ns) Data Path Delay: 0.594ns (logic 0.100ns (16.841%) route 0.494ns (83.159%)) Logic Levels: 0 Clock Path Skew: 0.296ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.292ns Source Clock Delay (SCD): 1.734ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.183ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.004 1.017 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.691 1.734 sys/eth/phy/U0/transceiver_inst/userclk2 SLICE_X189Y105 FDRE r sys/eth/phy/U0/transceiver_inst/txcharisk_double_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X189Y105 FDRE (Prop_fdre_C_Q) 0.100 1.834 r sys/eth/phy/U0/transceiver_inst/txcharisk_double_reg[0]/Q net (fo=1, routed) 0.494 2.327 sys/eth/phy/U0/transceiver_inst/txcharisk_double[0] SLICE_X188Y105 FDRE r sys/eth/phy/U0/transceiver_inst/txcharisk_int_reg[0]/D ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 1.073 1.348 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 0.914 2.292 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X188Y105 FDRE r sys/eth/phy/U0/transceiver_inst/txcharisk_int_reg[0]/C clock pessimism -0.262 2.030 clock uncertainty 0.183 2.212 SLICE_X188Y105 FDRE (Hold_fdre_C_D) 0.039 2.251 sys/eth/phy/U0/transceiver_inst/txcharisk_int_reg[0] ------------------------------------------------------------------- required time -2.251 arrival time 2.327 ------------------------------------------------------------------- slack 0.076 Slack (MET) : 0.104ns (arrival time - required time) Source: sys/eth/phy/U0/transceiver_inst/txdata_double_reg[12]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/txdata_int_reg[12]/D (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk62_5_ub rise@0.000ns - clk125_ub rise@0.000ns) Data Path Delay: 0.627ns (logic 0.100ns (15.950%) route 0.527ns (84.050%)) Logic Levels: 0 Clock Path Skew: 0.297ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.292ns Source Clock Delay (SCD): 1.733ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.183ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.004 1.017 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.690 1.733 sys/eth/phy/U0/transceiver_inst/userclk2 SLICE_X187Y103 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_double_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X187Y103 FDRE (Prop_fdre_C_Q) 0.100 1.833 r sys/eth/phy/U0/transceiver_inst/txdata_double_reg[12]/Q net (fo=1, routed) 0.527 2.360 sys/eth/phy/U0/transceiver_inst/txdata_double[12] SLICE_X189Y103 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_int_reg[12]/D ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 1.073 1.348 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 0.914 2.292 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X189Y103 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_int_reg[12]/C clock pessimism -0.262 2.030 clock uncertainty 0.183 2.212 SLICE_X189Y103 FDRE (Hold_fdre_C_D) 0.043 2.255 sys/eth/phy/U0/transceiver_inst/txdata_int_reg[12] ------------------------------------------------------------------- required time -2.255 arrival time 2.360 ------------------------------------------------------------------- slack 0.104 Slack (MET) : 0.108ns (arrival time - required time) Source: sys/eth/phy/U0/transceiver_inst/txdata_double_reg[7]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/txdata_int_reg[7]/D (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk62_5_ub rise@0.000ns - clk125_ub rise@0.000ns) Data Path Delay: 0.597ns (logic 0.091ns (15.234%) route 0.506ns (84.766%)) Logic Levels: 0 Clock Path Skew: 0.296ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.292ns Source Clock Delay (SCD): 1.734ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.183ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.004 1.017 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.691 1.734 sys/eth/phy/U0/transceiver_inst/userclk2 SLICE_X189Y105 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_double_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X189Y105 FDRE (Prop_fdre_C_Q) 0.091 1.825 r sys/eth/phy/U0/transceiver_inst/txdata_double_reg[7]/Q net (fo=1, routed) 0.506 2.331 sys/eth/phy/U0/transceiver_inst/txdata_double[7] SLICE_X188Y105 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_int_reg[7]/D ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 1.073 1.348 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 0.914 2.292 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X188Y105 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_int_reg[7]/C clock pessimism -0.262 2.030 clock uncertainty 0.183 2.212 SLICE_X188Y105 FDRE (Hold_fdre_C_D) 0.011 2.223 sys/eth/phy/U0/transceiver_inst/txdata_int_reg[7] ------------------------------------------------------------------- required time -2.223 arrival time 2.331 ------------------------------------------------------------------- slack 0.108 Slack (MET) : 0.111ns (arrival time - required time) Source: sys/eth/phy/U0/transceiver_inst/txdata_double_reg[8]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/txdata_int_reg[8]/D (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk62_5_ub rise@0.000ns - clk125_ub rise@0.000ns) Data Path Delay: 0.634ns (logic 0.100ns (15.772%) route 0.534ns (84.228%)) Logic Levels: 0 Clock Path Skew: 0.296ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.292ns Source Clock Delay (SCD): 1.734ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.183ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.004 1.017 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.691 1.734 sys/eth/phy/U0/transceiver_inst/userclk2 SLICE_X188Y104 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_double_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X188Y104 FDRE (Prop_fdre_C_Q) 0.100 1.834 r sys/eth/phy/U0/transceiver_inst/txdata_double_reg[8]/Q net (fo=1, routed) 0.534 2.368 sys/eth/phy/U0/transceiver_inst/txdata_double[8] SLICE_X188Y105 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_int_reg[8]/D ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 1.073 1.348 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 0.914 2.292 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X188Y105 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_int_reg[8]/C clock pessimism -0.262 2.030 clock uncertainty 0.183 2.212 SLICE_X188Y105 FDRE (Hold_fdre_C_D) 0.044 2.256 sys/eth/phy/U0/transceiver_inst/txdata_int_reg[8] ------------------------------------------------------------------- required time -2.256 arrival time 2.368 ------------------------------------------------------------------- slack 0.111 Slack (MET) : 0.113ns (arrival time - required time) Source: sys/eth/phy/U0/transceiver_inst/txdata_double_reg[5]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/txdata_int_reg[5]/D (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk62_5_ub rise@0.000ns - clk125_ub rise@0.000ns) Data Path Delay: 0.641ns (logic 0.100ns (15.608%) route 0.541ns (84.392%)) Logic Levels: 0 Clock Path Skew: 0.296ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.292ns Source Clock Delay (SCD): 1.734ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.183ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.004 1.017 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.691 1.734 sys/eth/phy/U0/transceiver_inst/userclk2 SLICE_X189Y105 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_double_reg[5]/C ------------------------------------------------------------------- ------------------- SLICE_X189Y105 FDRE (Prop_fdre_C_Q) 0.100 1.834 r sys/eth/phy/U0/transceiver_inst/txdata_double_reg[5]/Q net (fo=1, routed) 0.541 2.374 sys/eth/phy/U0/transceiver_inst/txdata_double[5] SLICE_X188Y106 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_int_reg[5]/D ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 1.073 1.348 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 0.914 2.292 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X188Y106 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_int_reg[5]/C clock pessimism -0.262 2.030 clock uncertainty 0.183 2.212 SLICE_X188Y106 FDRE (Hold_fdre_C_D) 0.049 2.261 sys/eth/phy/U0/transceiver_inst/txdata_int_reg[5] ------------------------------------------------------------------- required time -2.261 arrival time 2.374 ------------------------------------------------------------------- slack 0.113 Slack (MET) : 0.118ns (arrival time - required time) Source: sys/eth/phy/U0/transceiver_inst/txchardispmode_double_reg[0]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/txchardispmode_int_reg[0]/D (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk62_5_ub rise@0.000ns - clk125_ub rise@0.000ns) Data Path Delay: 0.637ns (logic 0.100ns (15.710%) route 0.537ns (84.290%)) Logic Levels: 0 Clock Path Skew: 0.296ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.292ns Source Clock Delay (SCD): 1.734ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.183ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.004 1.017 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.691 1.734 sys/eth/phy/U0/transceiver_inst/userclk2 SLICE_X188Y104 FDRE r sys/eth/phy/U0/transceiver_inst/txchardispmode_double_reg[0]/C ------------------------------------------------------------------- ------------------- SLICE_X188Y104 FDRE (Prop_fdre_C_Q) 0.100 1.834 r sys/eth/phy/U0/transceiver_inst/txchardispmode_double_reg[0]/Q net (fo=1, routed) 0.537 2.370 sys/eth/phy/U0/transceiver_inst/txchardispmode_double[0] SLICE_X189Y103 FDRE r sys/eth/phy/U0/transceiver_inst/txchardispmode_int_reg[0]/D ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 1.073 1.348 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 0.914 2.292 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X189Y103 FDRE r sys/eth/phy/U0/transceiver_inst/txchardispmode_int_reg[0]/C clock pessimism -0.262 2.030 clock uncertainty 0.183 2.212 SLICE_X189Y103 FDRE (Hold_fdre_C_D) 0.040 2.252 sys/eth/phy/U0/transceiver_inst/txchardispmode_int_reg[0] ------------------------------------------------------------------- required time -2.252 arrival time 2.370 ------------------------------------------------------------------- slack 0.118 Slack (MET) : 0.119ns (arrival time - required time) Source: sys/eth/phy/U0/transceiver_inst/txdata_double_reg[4]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/txdata_int_reg[4]/D (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk62_5_ub rise@0.000ns - clk125_ub rise@0.000ns) Data Path Delay: 0.609ns (logic 0.091ns (14.930%) route 0.518ns (85.070%)) Logic Levels: 0 Clock Path Skew: 0.297ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.292ns Source Clock Delay (SCD): 1.733ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.183ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.004 1.017 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.690 1.733 sys/eth/phy/U0/transceiver_inst/userclk2 SLICE_X187Y106 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_double_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X187Y106 FDRE (Prop_fdre_C_Q) 0.091 1.824 r sys/eth/phy/U0/transceiver_inst/txdata_double_reg[4]/Q net (fo=1, routed) 0.518 2.342 sys/eth/phy/U0/transceiver_inst/txdata_double[4] SLICE_X188Y106 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_int_reg[4]/D ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 1.073 1.348 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 0.914 2.292 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X188Y106 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_int_reg[4]/C clock pessimism -0.262 2.030 clock uncertainty 0.183 2.212 SLICE_X188Y106 FDRE (Hold_fdre_C_D) 0.011 2.223 sys/eth/phy/U0/transceiver_inst/txdata_int_reg[4] ------------------------------------------------------------------- required time -2.223 arrival time 2.342 ------------------------------------------------------------------- slack 0.119 Slack (MET) : 0.120ns (arrival time - required time) Source: sys/eth/phy/U0/transceiver_inst/txdata_double_reg[2]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/txdata_int_reg[2]/D (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk62_5_ub rise@0.000ns - clk125_ub rise@0.000ns) Data Path Delay: 0.608ns (logic 0.091ns (14.962%) route 0.517ns (85.038%)) Logic Levels: 0 Clock Path Skew: 0.297ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.292ns Source Clock Delay (SCD): 1.733ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.183ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.004 1.017 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.690 1.733 sys/eth/phy/U0/transceiver_inst/userclk2 SLICE_X187Y106 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_double_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X187Y106 FDRE (Prop_fdre_C_Q) 0.091 1.824 r sys/eth/phy/U0/transceiver_inst/txdata_double_reg[2]/Q net (fo=1, routed) 0.517 2.341 sys/eth/phy/U0/transceiver_inst/txdata_double[2] SLICE_X188Y106 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_int_reg[2]/D ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 1.073 1.348 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 0.914 2.292 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X188Y106 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_int_reg[2]/C clock pessimism -0.262 2.030 clock uncertainty 0.183 2.212 SLICE_X188Y106 FDRE (Hold_fdre_C_D) 0.009 2.221 sys/eth/phy/U0/transceiver_inst/txdata_int_reg[2] ------------------------------------------------------------------- required time -2.221 arrival time 2.341 ------------------------------------------------------------------- slack 0.120 Slack (MET) : 0.120ns (arrival time - required time) Source: sys/eth/phy/U0/transceiver_inst/txcharisk_double_reg[1]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/txcharisk_int_reg[1]/D (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk62_5_ub rise@0.000ns - clk125_ub rise@0.000ns) Data Path Delay: 0.631ns (logic 0.100ns (15.858%) route 0.531ns (84.142%)) Logic Levels: 0 Clock Path Skew: 0.296ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.292ns Source Clock Delay (SCD): 1.734ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.183ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.004 1.017 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.691 1.734 sys/eth/phy/U0/transceiver_inst/userclk2 SLICE_X189Y105 FDRE r sys/eth/phy/U0/transceiver_inst/txcharisk_double_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X189Y105 FDRE (Prop_fdre_C_Q) 0.100 1.834 r sys/eth/phy/U0/transceiver_inst/txcharisk_double_reg[1]/Q net (fo=1, routed) 0.531 2.364 sys/eth/phy/U0/transceiver_inst/txcharisk_double[1] SLICE_X188Y105 FDRE r sys/eth/phy/U0/transceiver_inst/txcharisk_int_reg[1]/D ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 1.073 1.348 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 0.914 2.292 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X188Y105 FDRE r sys/eth/phy/U0/transceiver_inst/txcharisk_int_reg[1]/C clock pessimism -0.262 2.030 clock uncertainty 0.183 2.212 SLICE_X188Y105 FDRE (Hold_fdre_C_D) 0.032 2.244 sys/eth/phy/U0/transceiver_inst/txcharisk_int_reg[1] ------------------------------------------------------------------- required time -2.244 arrival time 2.364 ------------------------------------------------------------------- slack 0.120 Slack (MET) : 0.130ns (arrival time - required time) Source: sys/eth/phy/U0/transceiver_inst/txdata_double_reg[15]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/eth/phy/U0/transceiver_inst/txdata_int_reg[15]/D (rising edge-triggered cell FDRE clocked by clk62_5_ub {rise@0.000ns fall@8.000ns period=16.000ns}) Path Group: clk62_5_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk62_5_ub rise@0.000ns - clk125_ub rise@0.000ns) Data Path Delay: 0.653ns (logic 0.100ns (15.320%) route 0.553ns (84.680%)) Logic Levels: 0 Clock Path Skew: 0.296ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.292ns Source Clock Delay (SCD): 1.734ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.183ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.103ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.004 1.017 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.691 1.734 sys/eth/phy/U0/transceiver_inst/userclk2 SLICE_X189Y104 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_double_reg[15]/C ------------------------------------------------------------------- ------------------- SLICE_X189Y104 FDRE (Prop_fdre_C_Q) 0.100 1.834 r sys/eth/phy/U0/transceiver_inst/txdata_double_reg[15]/Q net (fo=1, routed) 0.553 2.386 sys/eth/phy/U0/transceiver_inst/txdata_double[15] SLICE_X189Y103 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_int_reg[15]/D ------------------------------------------------------------------- ------------------- (clock clk62_5_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT1) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKOUT1 net (fo=1, routed) 1.073 1.348 sys/clocks/clk62_5_ub BUFGCTRL_X0Y7 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk62_5_buf/O net (fo=118, routed) 0.914 2.292 sys/eth/phy/U0/transceiver_inst/userclk SLICE_X189Y103 FDRE r sys/eth/phy/U0/transceiver_inst/txdata_int_reg[15]/C clock pessimism -0.262 2.030 clock uncertainty 0.183 2.212 SLICE_X189Y103 FDRE (Hold_fdre_C_D) 0.044 2.256 sys/eth/phy/U0/transceiver_inst/txdata_int_reg[15] ------------------------------------------------------------------- required time -2.256 arrival time 2.386 ------------------------------------------------------------------- slack 0.130 --------------------------------------------------------------------------------------------------- From Clock: clk125_ub To Clock: clk_ipb_ub Setup : 0 Failing Endpoints, Worst Slack 3.143ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.063ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 3.143ns (required time - arrival time) Source: sys/clocks/rst_125_reg/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/ipb/udp_if/ipbus_tx_ram/ram_reg_5/DIADI[0] (rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: clk_ipb_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk_ipb_ub rise@32.000ns - clk125_ub rise@24.000ns) Data Path Delay: 3.938ns (logic 0.309ns (7.846%) route 3.629ns (92.154%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.187ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.084ns = ( 36.084 - 32.000 ) Source Clock Delay (SCD): 5.146ns = ( 29.146 - 24.000 ) Clock Pessimism Removal (CPR): 0.874ns Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 24.000 24.000 r AD6 0.000 24.000 r osc125_a_p (IN) net (fo=0) 0.000 24.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 24.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 24.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 26.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 27.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 27.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 29.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -4.148 25.449 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.205 27.654 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 27.747 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.399 29.146 sys/clocks/PLLE2_BASE_inst_0 SLICE_X96Y115 FDRE r sys/clocks/rst_125_reg/C ------------------------------------------------------------------- ------------------- SLICE_X96Y115 FDRE (Prop_fdre_C_Q) 0.223 29.369 f sys/clocks/rst_125_reg/Q net (fo=1307, routed) 2.047 31.415 sys/ipb/trans/sm/rst_125mhz SLICE_X69Y131 LUT5 (Prop_lut5_I1_O) 0.043 31.458 r sys/ipb/trans/sm/ram_reg_5_i_11/O net (fo=1, routed) 0.602 32.060 sys/ipb/trans/sm/ram_reg_5_i_11_n_0 SLICE_X74Y131 LUT6 (Prop_lut6_I4_O) 0.043 32.103 r sys/ipb/trans/sm/ram_reg_5_i_4/O net (fo=2, routed) 0.981 33.084 sys/ipb/udp_if/ipbus_tx_ram/tx_dia[20] RAMB36_X3Y23 RAMB36E1 r sys/ipb/udp_if/ipbus_tx_ram/ram_reg_5/DIADI[0] ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 32.000 32.000 r AD6 0.000 32.000 r osc125_a_p (IN) net (fo=0) 0.000 32.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 32.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 32.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 33.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 34.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 36.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -3.847 32.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.078 34.653 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.349 36.084 sys/ipb/udp_if/ipbus_tx_ram/ram_reg_0_0 RAMB36_X3Y23 RAMB36E1 r sys/ipb/udp_if/ipbus_tx_ram/ram_reg_5/CLKARDCLK clock pessimism 0.874 36.958 clock uncertainty -0.189 36.769 RAMB36_X3Y23 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[0]) -0.543 36.226 sys/ipb/udp_if/ipbus_tx_ram/ram_reg_5 ------------------------------------------------------------------- required time 36.226 arrival time -33.084 ------------------------------------------------------------------- slack 3.143 Slack (MET) : 3.386ns (required time - arrival time) Source: sys/clocks/rst_125_reg/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/uc_if/uc_trans/ram_out/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[20] (rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: clk_ipb_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk_ipb_ub rise@32.000ns - clk125_ub rise@24.000ns) Data Path Delay: 3.626ns (logic 0.309ns (8.521%) route 3.317ns (91.479%)) Logic Levels: 2 (LUT5=1 LUT6=1) Clock Path Skew: -0.256ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.015ns = ( 36.015 - 32.000 ) Source Clock Delay (SCD): 5.146ns = ( 29.146 - 24.000 ) Clock Pessimism Removal (CPR): 0.874ns Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 24.000 24.000 r AD6 0.000 24.000 r osc125_a_p (IN) net (fo=0) 0.000 24.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 24.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 24.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 26.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 27.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 27.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 29.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -4.148 25.449 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.205 27.654 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 27.747 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.399 29.146 sys/clocks/PLLE2_BASE_inst_0 SLICE_X96Y115 FDRE r sys/clocks/rst_125_reg/C ------------------------------------------------------------------- ------------------- SLICE_X96Y115 FDRE (Prop_fdre_C_Q) 0.223 29.369 f sys/clocks/rst_125_reg/Q net (fo=1307, routed) 2.047 31.415 sys/ipb/trans/sm/rst_125mhz SLICE_X69Y131 LUT5 (Prop_lut5_I1_O) 0.043 31.458 r sys/ipb/trans/sm/ram_reg_5_i_11/O net (fo=1, routed) 0.602 32.060 sys/ipb/trans/sm/ram_reg_5_i_11_n_0 SLICE_X74Y131 LUT6 (Prop_lut6_I4_O) 0.043 32.103 r sys/ipb/trans/sm/ram_reg_5_i_4/O net (fo=2, routed) 0.669 32.772 sys/uc_if/uc_trans/ram_out/dina[20] RAMB36_X5Y25 RAMB36E1 r sys/uc_if/uc_trans/ram_out/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[20] ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 32.000 32.000 r AD6 0.000 32.000 r osc125_a_p (IN) net (fo=0) 0.000 32.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 32.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 32.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 33.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 34.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 36.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -3.847 32.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.078 34.653 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.280 36.015 sys/uc_if/uc_trans/ram_out/clka RAMB36_X5Y25 RAMB36E1 r sys/uc_if/uc_trans/ram_out/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK clock pessimism 0.874 36.889 clock uncertainty -0.189 36.700 RAMB36_X5Y25 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[20]) -0.543 36.157 sys/uc_if/uc_trans/ram_out/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ------------------------------------------------------------------- required time 36.157 arrival time -32.772 ------------------------------------------------------------------- slack 3.386 Slack (MET) : 3.720ns (required time - arrival time) Source: sys/ipb/udp_if/IPADDR/My_IP_addr_reg[18]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/uc_if/uc_trans/ram_out/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[18] (rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: clk_ipb_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk_ipb_ub rise@32.000ns - clk125_ub rise@24.000ns) Data Path Delay: 3.236ns (logic 0.388ns (11.991%) route 2.848ns (88.009%)) Logic Levels: 3 (LUT4=1 LUT5=1 LUT6=1) Clock Path Skew: -0.312ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.015ns = ( 36.015 - 32.000 ) Source Clock Delay (SCD): 5.202ns = ( 29.202 - 24.000 ) Clock Pessimism Removal (CPR): 0.874ns Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 24.000 24.000 r AD6 0.000 24.000 r osc125_a_p (IN) net (fo=0) 0.000 24.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 24.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 24.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 26.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 27.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 27.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 29.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -4.148 25.449 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.205 27.654 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 27.747 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.455 29.202 sys/ipb/udp_if/IPADDR/pkt_mask_reg[41]_0 SLICE_X50Y132 FDRE r sys/ipb/udp_if/IPADDR/My_IP_addr_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X50Y132 FDRE (Prop_fdre_C_Q) 0.259 29.461 r sys/ipb/udp_if/IPADDR/My_IP_addr_reg[18]/Q net (fo=4, routed) 1.389 30.850 sys/ipb/trans/sm/ram_reg_7_3[18] SLICE_X72Y140 LUT4 (Prop_lut4_I0_O) 0.043 30.893 r sys/ipb/trans/sm/ram_reg_4_i_16/O net (fo=1, routed) 0.447 31.339 sys/ipb/trans/sm/ram_reg_4_i_16_n_0 SLICE_X75Y141 LUT6 (Prop_lut6_I5_O) 0.043 31.382 r sys/ipb/trans/sm/ram_reg_4_i_8/O net (fo=1, routed) 0.445 31.828 sys/ipb/trans/sm/ram_reg_4_i_8_n_0 SLICE_X81Y131 LUT5 (Prop_lut5_I3_O) 0.043 31.871 r sys/ipb/trans/sm/ram_reg_4_i_2/O net (fo=2, routed) 0.567 32.437 sys/uc_if/uc_trans/ram_out/dina[18] RAMB36_X5Y25 RAMB36E1 r sys/uc_if/uc_trans/ram_out/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[18] ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 32.000 32.000 r AD6 0.000 32.000 r osc125_a_p (IN) net (fo=0) 0.000 32.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 32.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 32.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 33.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 34.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 36.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -3.847 32.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.078 34.653 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.280 36.015 sys/uc_if/uc_trans/ram_out/clka RAMB36_X5Y25 RAMB36E1 r sys/uc_if/uc_trans/ram_out/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK clock pessimism 0.874 36.889 clock uncertainty -0.189 36.700 RAMB36_X5Y25 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[18]) -0.543 36.157 sys/uc_if/uc_trans/ram_out/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ------------------------------------------------------------------- required time 36.157 arrival time -32.437 ------------------------------------------------------------------- slack 3.720 Slack (MET) : 3.831ns (required time - arrival time) Source: sys/ipb/udp_if/IPADDR/My_IP_addr_reg[18]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/ipb/udp_if/ipbus_tx_ram/ram_reg_4/DIADI[2] (rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: clk_ipb_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk_ipb_ub rise@32.000ns - clk125_ub rise@24.000ns) Data Path Delay: 3.130ns (logic 0.388ns (12.398%) route 2.742ns (87.602%)) Logic Levels: 3 (LUT4=1 LUT5=1 LUT6=1) Clock Path Skew: -0.307ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.020ns = ( 36.020 - 32.000 ) Source Clock Delay (SCD): 5.202ns = ( 29.202 - 24.000 ) Clock Pessimism Removal (CPR): 0.874ns Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 24.000 24.000 r AD6 0.000 24.000 r osc125_a_p (IN) net (fo=0) 0.000 24.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 24.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 24.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 26.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 27.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 27.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 29.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -4.148 25.449 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.205 27.654 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 27.747 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.455 29.202 sys/ipb/udp_if/IPADDR/pkt_mask_reg[41]_0 SLICE_X50Y132 FDRE r sys/ipb/udp_if/IPADDR/My_IP_addr_reg[18]/C ------------------------------------------------------------------- ------------------- SLICE_X50Y132 FDRE (Prop_fdre_C_Q) 0.259 29.461 r sys/ipb/udp_if/IPADDR/My_IP_addr_reg[18]/Q net (fo=4, routed) 1.389 30.850 sys/ipb/trans/sm/ram_reg_7_3[18] SLICE_X72Y140 LUT4 (Prop_lut4_I0_O) 0.043 30.893 r sys/ipb/trans/sm/ram_reg_4_i_16/O net (fo=1, routed) 0.447 31.339 sys/ipb/trans/sm/ram_reg_4_i_16_n_0 SLICE_X75Y141 LUT6 (Prop_lut6_I5_O) 0.043 31.382 r sys/ipb/trans/sm/ram_reg_4_i_8/O net (fo=1, routed) 0.445 31.828 sys/ipb/trans/sm/ram_reg_4_i_8_n_0 SLICE_X81Y131 LUT5 (Prop_lut5_I3_O) 0.043 31.871 r sys/ipb/trans/sm/ram_reg_4_i_2/O net (fo=2, routed) 0.461 32.331 sys/ipb/udp_if/ipbus_tx_ram/tx_dia[18] RAMB36_X5Y26 RAMB36E1 r sys/ipb/udp_if/ipbus_tx_ram/ram_reg_4/DIADI[2] ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 32.000 32.000 r AD6 0.000 32.000 r osc125_a_p (IN) net (fo=0) 0.000 32.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 32.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 32.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 33.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 34.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 36.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -3.847 32.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.078 34.653 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.285 36.020 sys/ipb/udp_if/ipbus_tx_ram/ram_reg_0_0 RAMB36_X5Y26 RAMB36E1 r sys/ipb/udp_if/ipbus_tx_ram/ram_reg_4/CLKARDCLK clock pessimism 0.874 36.894 clock uncertainty -0.189 36.705 RAMB36_X5Y26 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[2]) -0.543 36.162 sys/ipb/udp_if/ipbus_tx_ram/ram_reg_4 ------------------------------------------------------------------- required time 36.162 arrival time -32.331 ------------------------------------------------------------------- slack 3.831 Slack (MET) : 3.875ns (required time - arrival time) Source: sys/ipb/udp_if/IPADDR/My_IP_addr_reg[12]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/ipb/udp_if/ipbus_tx_ram/ram_reg_3/DIADI[0] (rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: clk_ipb_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk_ipb_ub rise@32.000ns - clk125_ub rise@24.000ns) Data Path Delay: 3.152ns (logic 0.352ns (11.166%) route 2.800ns (88.834%)) Logic Levels: 3 (LUT5=2 LUT6=1) Clock Path Skew: -0.240ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.081ns = ( 36.081 - 32.000 ) Source Clock Delay (SCD): 5.196ns = ( 29.196 - 24.000 ) Clock Pessimism Removal (CPR): 0.874ns Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 24.000 24.000 r AD6 0.000 24.000 r osc125_a_p (IN) net (fo=0) 0.000 24.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 24.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 24.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 26.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 27.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 27.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 29.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -4.148 25.449 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.205 27.654 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 27.747 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.449 29.196 sys/ipb/udp_if/IPADDR/pkt_mask_reg[41]_0 SLICE_X57Y130 FDRE r sys/ipb/udp_if/IPADDR/My_IP_addr_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y130 FDRE (Prop_fdre_C_Q) 0.223 29.419 r sys/ipb/udp_if/IPADDR/My_IP_addr_reg[12]/Q net (fo=4, routed) 0.824 30.243 sys/ipb/trans/sm/ram_reg_7_3[12] SLICE_X68Y133 LUT5 (Prop_lut5_I1_O) 0.043 30.286 r sys/ipb/trans/sm/ram_reg_3_i_18/O net (fo=1, routed) 0.718 31.004 sys/ipb/trans/sm/ram_reg_3_i_18_n_0 SLICE_X72Y139 LUT6 (Prop_lut6_I5_O) 0.043 31.047 r sys/ipb/trans/sm/ram_reg_3_i_11/O net (fo=1, routed) 0.327 31.374 sys/ipb/trans/sm/ram_reg_3_i_11_n_0 SLICE_X74Y134 LUT5 (Prop_lut5_I2_O) 0.043 31.417 r sys/ipb/trans/sm/ram_reg_3_i_4/O net (fo=2, routed) 0.931 32.348 sys/ipb/udp_if/ipbus_tx_ram/tx_dia[12] RAMB36_X3Y25 RAMB36E1 r sys/ipb/udp_if/ipbus_tx_ram/ram_reg_3/DIADI[0] ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 32.000 32.000 r AD6 0.000 32.000 r osc125_a_p (IN) net (fo=0) 0.000 32.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 32.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 32.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 33.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 34.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 36.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -3.847 32.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.078 34.653 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.346 36.081 sys/ipb/udp_if/ipbus_tx_ram/ram_reg_0_0 RAMB36_X3Y25 RAMB36E1 r sys/ipb/udp_if/ipbus_tx_ram/ram_reg_3/CLKARDCLK clock pessimism 0.874 36.955 clock uncertainty -0.189 36.766 RAMB36_X3Y25 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[0]) -0.543 36.223 sys/ipb/udp_if/ipbus_tx_ram/ram_reg_3 ------------------------------------------------------------------- required time 36.223 arrival time -32.348 ------------------------------------------------------------------- slack 3.875 Slack (MET) : 3.896ns (required time - arrival time) Source: sys/ipb/udp_if/IPADDR/My_IP_addr_reg[2]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/uc_if/uc_trans/ram_out/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[2] (rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: clk_ipb_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk_ipb_ub rise@32.000ns - clk125_ub rise@24.000ns) Data Path Delay: 3.065ns (logic 0.388ns (12.658%) route 2.677ns (87.342%)) Logic Levels: 3 (LUT5=2 LUT6=1) Clock Path Skew: -0.307ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.015ns = ( 36.015 - 32.000 ) Source Clock Delay (SCD): 5.197ns = ( 29.197 - 24.000 ) Clock Pessimism Removal (CPR): 0.874ns Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 24.000 24.000 r AD6 0.000 24.000 r osc125_a_p (IN) net (fo=0) 0.000 24.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 24.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 24.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 26.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 27.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 27.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 29.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -4.148 25.449 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.205 27.654 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 27.747 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.450 29.197 sys/ipb/udp_if/IPADDR/pkt_mask_reg[41]_0 SLICE_X50Y128 FDRE r sys/ipb/udp_if/IPADDR/My_IP_addr_reg[2]/C ------------------------------------------------------------------- ------------------- SLICE_X50Y128 FDRE (Prop_fdre_C_Q) 0.259 29.456 r sys/ipb/udp_if/IPADDR/My_IP_addr_reg[2]/Q net (fo=4, routed) 0.957 30.413 sys/ipb/trans/sm/ram_reg_7_3[2] SLICE_X73Y129 LUT5 (Prop_lut5_I4_O) 0.043 30.456 r sys/ipb/trans/sm/ram_reg_0_i_26/O net (fo=1, routed) 0.752 31.208 sys/ipb/trans/sm/ram_reg_0_i_26_n_0 SLICE_X75Y137 LUT6 (Prop_lut6_I5_O) 0.043 31.251 r sys/ipb/trans/sm/ram_reg_0_i_19/O net (fo=1, routed) 0.327 31.578 sys/ipb/trans/sm/ram_reg_0_i_19_n_0 SLICE_X76Y136 LUT5 (Prop_lut5_I2_O) 0.043 31.621 r sys/ipb/trans/sm/ram_reg_0_i_12/O net (fo=2, routed) 0.640 32.262 sys/uc_if/uc_trans/ram_out/dina[2] RAMB36_X5Y25 RAMB36E1 r sys/uc_if/uc_trans/ram_out/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[2] ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 32.000 32.000 r AD6 0.000 32.000 r osc125_a_p (IN) net (fo=0) 0.000 32.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 32.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 32.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 33.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 34.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 36.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -3.847 32.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.078 34.653 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.280 36.015 sys/uc_if/uc_trans/ram_out/clka RAMB36_X5Y25 RAMB36E1 r sys/uc_if/uc_trans/ram_out/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK clock pessimism 0.874 36.889 clock uncertainty -0.189 36.700 RAMB36_X5Y25 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[2]) -0.543 36.157 sys/uc_if/uc_trans/ram_out/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ------------------------------------------------------------------- required time 36.157 arrival time -32.262 ------------------------------------------------------------------- slack 3.896 Slack (MET) : 3.909ns (required time - arrival time) Source: sys/ipb/udp_if/IPADDR/My_IP_addr_reg[21]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/ipb/udp_if/ipbus_tx_ram/ram_reg_5/DIADI[1] (rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: clk_ipb_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk_ipb_ub rise@32.000ns - clk125_ub rise@24.000ns) Data Path Delay: 3.119ns (logic 0.352ns (11.284%) route 2.767ns (88.716%)) Logic Levels: 3 (LUT4=1 LUT5=1 LUT6=1) Clock Path Skew: -0.239ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.084ns = ( 36.084 - 32.000 ) Source Clock Delay (SCD): 5.198ns = ( 29.198 - 24.000 ) Clock Pessimism Removal (CPR): 0.874ns Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 24.000 24.000 r AD6 0.000 24.000 r osc125_a_p (IN) net (fo=0) 0.000 24.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 24.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 24.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 26.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 27.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 27.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 29.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -4.148 25.449 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.205 27.654 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 27.747 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.451 29.198 sys/ipb/udp_if/IPADDR/pkt_mask_reg[41]_0 SLICE_X56Y132 FDRE r sys/ipb/udp_if/IPADDR/My_IP_addr_reg[21]/C ------------------------------------------------------------------- ------------------- SLICE_X56Y132 FDRE (Prop_fdre_C_Q) 0.223 29.421 r sys/ipb/udp_if/IPADDR/My_IP_addr_reg[21]/Q net (fo=4, routed) 0.728 30.149 sys/ipb/trans/sm/ram_reg_7_3[21] SLICE_X73Y135 LUT4 (Prop_lut4_I0_O) 0.043 30.192 r sys/ipb/trans/sm/ram_reg_5_i_18/O net (fo=1, routed) 0.541 30.733 sys/ipb/trans/sm/ram_reg_5_i_18_n_0 SLICE_X78Y138 LUT6 (Prop_lut6_I5_O) 0.043 30.776 r sys/ipb/trans/sm/ram_reg_5_i_10/O net (fo=1, routed) 0.403 31.179 sys/ipb/trans/sm/ram_reg_5_i_10_n_0 SLICE_X79Y133 LUT5 (Prop_lut5_I3_O) 0.043 31.222 r sys/ipb/trans/sm/ram_reg_5_i_3/O net (fo=2, routed) 1.095 32.317 sys/ipb/udp_if/ipbus_tx_ram/tx_dia[21] RAMB36_X3Y23 RAMB36E1 r sys/ipb/udp_if/ipbus_tx_ram/ram_reg_5/DIADI[1] ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 32.000 32.000 r AD6 0.000 32.000 r osc125_a_p (IN) net (fo=0) 0.000 32.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 32.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 32.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 33.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 34.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 36.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -3.847 32.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.078 34.653 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.349 36.084 sys/ipb/udp_if/ipbus_tx_ram/ram_reg_0_0 RAMB36_X3Y23 RAMB36E1 r sys/ipb/udp_if/ipbus_tx_ram/ram_reg_5/CLKARDCLK clock pessimism 0.874 36.958 clock uncertainty -0.189 36.769 RAMB36_X3Y23 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[1]) -0.543 36.226 sys/ipb/udp_if/ipbus_tx_ram/ram_reg_5 ------------------------------------------------------------------- required time 36.226 arrival time -32.317 ------------------------------------------------------------------- slack 3.909 Slack (MET) : 3.982ns (required time - arrival time) Source: sys/ipb/udp_if/IPADDR/My_IP_addr_reg[16]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/uc_if/uc_trans/ram_out/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[16] (rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: clk_ipb_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk_ipb_ub rise@32.000ns - clk125_ub rise@24.000ns) Data Path Delay: 2.973ns (logic 0.388ns (13.051%) route 2.585ns (86.949%)) Logic Levels: 3 (LUT4=1 LUT5=1 LUT6=1) Clock Path Skew: -0.313ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.015ns = ( 36.015 - 32.000 ) Source Clock Delay (SCD): 5.203ns = ( 29.203 - 24.000 ) Clock Pessimism Removal (CPR): 0.874ns Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 24.000 24.000 r AD6 0.000 24.000 r osc125_a_p (IN) net (fo=0) 0.000 24.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 24.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 24.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 26.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 27.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 27.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 29.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -4.148 25.449 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.205 27.654 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 27.747 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.456 29.203 sys/ipb/udp_if/IPADDR/pkt_mask_reg[41]_0 SLICE_X50Y133 FDRE r sys/ipb/udp_if/IPADDR/My_IP_addr_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X50Y133 FDRE (Prop_fdre_C_Q) 0.259 29.462 r sys/ipb/udp_if/IPADDR/My_IP_addr_reg[16]/Q net (fo=4, routed) 1.089 30.551 sys/ipb/trans/sm/ram_reg_7_3[16] SLICE_X75Y137 LUT4 (Prop_lut4_I0_O) 0.043 30.594 r sys/ipb/trans/sm/ram_reg_4_i_18/O net (fo=1, routed) 0.444 31.038 sys/ipb/trans/sm/ram_reg_4_i_18_n_0 SLICE_X75Y138 LUT6 (Prop_lut6_I5_O) 0.043 31.081 r sys/ipb/trans/sm/ram_reg_4_i_12/O net (fo=1, routed) 0.426 31.507 sys/ipb/trans/sm/ram_reg_4_i_12_n_0 SLICE_X79Y134 LUT5 (Prop_lut5_I3_O) 0.043 31.550 r sys/ipb/trans/sm/ram_reg_4_i_4/O net (fo=2, routed) 0.626 32.176 sys/uc_if/uc_trans/ram_out/dina[16] RAMB36_X5Y25 RAMB36E1 r sys/uc_if/uc_trans/ram_out/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[16] ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 32.000 32.000 r AD6 0.000 32.000 r osc125_a_p (IN) net (fo=0) 0.000 32.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 32.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 32.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 33.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 34.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 36.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -3.847 32.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.078 34.653 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.280 36.015 sys/uc_if/uc_trans/ram_out/clka RAMB36_X5Y25 RAMB36E1 r sys/uc_if/uc_trans/ram_out/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK clock pessimism 0.874 36.889 clock uncertainty -0.189 36.700 RAMB36_X5Y25 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[16]) -0.543 36.157 sys/uc_if/uc_trans/ram_out/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ------------------------------------------------------------------- required time 36.157 arrival time -32.176 ------------------------------------------------------------------- slack 3.982 Slack (MET) : 4.051ns (required time - arrival time) Source: sys/ipb/udp_if/IPADDR/My_IP_addr_reg[16]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/ipb/udp_if/ipbus_tx_ram/ram_reg_4/DIADI[0] (rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: clk_ipb_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk_ipb_ub rise@32.000ns - clk125_ub rise@24.000ns) Data Path Delay: 2.909ns (logic 0.388ns (13.337%) route 2.521ns (86.663%)) Logic Levels: 3 (LUT4=1 LUT5=1 LUT6=1) Clock Path Skew: -0.308ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.020ns = ( 36.020 - 32.000 ) Source Clock Delay (SCD): 5.203ns = ( 29.203 - 24.000 ) Clock Pessimism Removal (CPR): 0.874ns Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 24.000 24.000 r AD6 0.000 24.000 r osc125_a_p (IN) net (fo=0) 0.000 24.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 24.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 24.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 26.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 27.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 27.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 29.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -4.148 25.449 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.205 27.654 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 27.747 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.456 29.203 sys/ipb/udp_if/IPADDR/pkt_mask_reg[41]_0 SLICE_X50Y133 FDRE r sys/ipb/udp_if/IPADDR/My_IP_addr_reg[16]/C ------------------------------------------------------------------- ------------------- SLICE_X50Y133 FDRE (Prop_fdre_C_Q) 0.259 29.462 r sys/ipb/udp_if/IPADDR/My_IP_addr_reg[16]/Q net (fo=4, routed) 1.089 30.551 sys/ipb/trans/sm/ram_reg_7_3[16] SLICE_X75Y137 LUT4 (Prop_lut4_I0_O) 0.043 30.594 r sys/ipb/trans/sm/ram_reg_4_i_18/O net (fo=1, routed) 0.444 31.038 sys/ipb/trans/sm/ram_reg_4_i_18_n_0 SLICE_X75Y138 LUT6 (Prop_lut6_I5_O) 0.043 31.081 r sys/ipb/trans/sm/ram_reg_4_i_12/O net (fo=1, routed) 0.426 31.507 sys/ipb/trans/sm/ram_reg_4_i_12_n_0 SLICE_X79Y134 LUT5 (Prop_lut5_I3_O) 0.043 31.550 r sys/ipb/trans/sm/ram_reg_4_i_4/O net (fo=2, routed) 0.562 32.112 sys/ipb/udp_if/ipbus_tx_ram/tx_dia[16] RAMB36_X5Y26 RAMB36E1 r sys/ipb/udp_if/ipbus_tx_ram/ram_reg_4/DIADI[0] ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 32.000 32.000 r AD6 0.000 32.000 r osc125_a_p (IN) net (fo=0) 0.000 32.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 32.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 32.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 33.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 34.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 36.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -3.847 32.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.078 34.653 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.285 36.020 sys/ipb/udp_if/ipbus_tx_ram/ram_reg_0_0 RAMB36_X5Y26 RAMB36E1 r sys/ipb/udp_if/ipbus_tx_ram/ram_reg_4/CLKARDCLK clock pessimism 0.874 36.894 clock uncertainty -0.189 36.705 RAMB36_X5Y26 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[0]) -0.543 36.162 sys/ipb/udp_if/ipbus_tx_ram/ram_reg_4 ------------------------------------------------------------------- required time 36.162 arrival time -32.112 ------------------------------------------------------------------- slack 4.051 Slack (MET) : 4.111ns (required time - arrival time) Source: sys/ipb/udp_if/IPADDR/My_IP_addr_reg[12]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/uc_if/uc_trans/ram_out/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[12] (rising edge-triggered cell RAMB36E1 clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: clk_ipb_ub Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (clk_ipb_ub rise@32.000ns - clk125_ub rise@24.000ns) Data Path Delay: 2.851ns (logic 0.352ns (12.348%) route 2.499ns (87.652%)) Logic Levels: 3 (LUT5=2 LUT6=1) Clock Path Skew: -0.306ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.015ns = ( 36.015 - 32.000 ) Source Clock Delay (SCD): 5.196ns = ( 29.196 - 24.000 ) Clock Pessimism Removal (CPR): 0.874ns Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 24.000 24.000 r AD6 0.000 24.000 r osc125_a_p (IN) net (fo=0) 0.000 24.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 24.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 24.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 26.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 27.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 27.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 29.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -4.148 25.449 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.205 27.654 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 27.747 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.449 29.196 sys/ipb/udp_if/IPADDR/pkt_mask_reg[41]_0 SLICE_X57Y130 FDRE r sys/ipb/udp_if/IPADDR/My_IP_addr_reg[12]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y130 FDRE (Prop_fdre_C_Q) 0.223 29.419 r sys/ipb/udp_if/IPADDR/My_IP_addr_reg[12]/Q net (fo=4, routed) 0.824 30.243 sys/ipb/trans/sm/ram_reg_7_3[12] SLICE_X68Y133 LUT5 (Prop_lut5_I1_O) 0.043 30.286 r sys/ipb/trans/sm/ram_reg_3_i_18/O net (fo=1, routed) 0.718 31.004 sys/ipb/trans/sm/ram_reg_3_i_18_n_0 SLICE_X72Y139 LUT6 (Prop_lut6_I5_O) 0.043 31.047 r sys/ipb/trans/sm/ram_reg_3_i_11/O net (fo=1, routed) 0.327 31.374 sys/ipb/trans/sm/ram_reg_3_i_11_n_0 SLICE_X74Y134 LUT5 (Prop_lut5_I2_O) 0.043 31.417 r sys/ipb/trans/sm/ram_reg_3_i_4/O net (fo=2, routed) 0.629 32.046 sys/uc_if/uc_trans/ram_out/dina[12] RAMB36_X5Y25 RAMB36E1 r sys/uc_if/uc_trans/ram_out/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[12] ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 32.000 32.000 r AD6 0.000 32.000 r osc125_a_p (IN) net (fo=0) 0.000 32.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 32.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 32.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 33.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 34.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 36.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -3.847 32.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.078 34.653 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.280 36.015 sys/uc_if/uc_trans/ram_out/clka RAMB36_X5Y25 RAMB36E1 r sys/uc_if/uc_trans/ram_out/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK clock pessimism 0.874 36.889 clock uncertainty -0.189 36.700 RAMB36_X5Y25 RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[12]) -0.543 36.157 sys/uc_if/uc_trans/ram_out/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ------------------------------------------------------------------- required time 36.157 arrival time -32.046 ------------------------------------------------------------------- slack 4.111 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.063ns (arrival time - required time) Source: ngFEC/clk_rate_gen[3].clkRate3/rateCtr_reg[21]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: ngFEC/clk_rate_gen[3].clkRate3/value_reg[24]/D (rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: clk_ipb_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_ipb_ub rise@0.000ns - clk125_ub rise@0.000ns) Data Path Delay: 0.596ns (logic 0.118ns (19.792%) route 0.478ns (80.208%)) Logic Levels: 0 Clock Path Skew: 0.302ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.310ns Source Clock Delay (SCD): 1.746ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.004 1.017 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.703 1.746 ngFEC/clk_rate_gen[3].clkRate3/osc125_a_bufg SLICE_X182Y258 FDRE r ngFEC/clk_rate_gen[3].clkRate3/rateCtr_reg[21]/C ------------------------------------------------------------------- ------------------- SLICE_X182Y258 FDRE (Prop_fdre_C_Q) 0.118 1.864 r ngFEC/clk_rate_gen[3].clkRate3/rateCtr_reg[21]/Q net (fo=2, routed) 0.478 2.342 ngFEC/clk_rate_gen[3].clkRate3/rateCtr_reg[21] SLICE_X185Y259 FDRE r ngFEC/clk_rate_gen[3].clkRate3/value_reg[24]/D ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 1.073 1.348 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 0.932 2.310 ngFEC/clk_rate_gen[3].clkRate3/clk_31_250_bufg SLICE_X185Y259 FDRE r ngFEC/clk_rate_gen[3].clkRate3/value_reg[24]/C clock pessimism -0.262 2.048 clock uncertainty 0.189 2.236 SLICE_X185Y259 FDRE (Hold_fdre_C_D) 0.043 2.279 ngFEC/clk_rate_gen[3].clkRate3/value_reg[24] ------------------------------------------------------------------- required time -2.279 arrival time 2.342 ------------------------------------------------------------------- slack 0.063 Slack (MET) : 0.068ns (arrival time - required time) Source: sys/uc_if/uc_pipe_if/w_addr_pipe_reg[1]/C (rising edge-triggered cell FDSE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/uc_if/uc_pipe_if/ipbus_out_reg[ipb_rdata][1]/D (rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: clk_ipb_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_ipb_ub rise@0.000ns - clk125_ub rise@0.000ns) Data Path Delay: 0.645ns (logic 0.146ns (22.636%) route 0.499ns (77.364%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.301ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.193ns Source Clock Delay (SCD): 1.630ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.004 1.017 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.587 1.630 sys/uc_if/uc_pipe_if/r_addr_pipe_reg[9]_0 SLICE_X86Y136 FDSE r sys/uc_if/uc_pipe_if/w_addr_pipe_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X86Y136 FDSE (Prop_fdse_C_Q) 0.118 1.748 r sys/uc_if/uc_pipe_if/w_addr_pipe_reg[1]/Q net (fo=8, routed) 0.499 2.247 sys/uc_if/uc_pipe_if/w_addr_pipe_reg__0[1] SLICE_X84Y141 LUT6 (Prop_lut6_I5_O) 0.028 2.275 r sys/uc_if/uc_pipe_if/ipbus_out[ipb_rdata][1]_i_1/O net (fo=1, routed) 0.000 2.275 sys/uc_if/uc_pipe_if/ipbus_out[ipb_rdata][1]_i_1_n_0 SLICE_X84Y141 FDRE r sys/uc_if/uc_pipe_if/ipbus_out_reg[ipb_rdata][1]/D ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 1.073 1.348 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 0.815 2.193 sys/uc_if/uc_pipe_if/out SLICE_X84Y141 FDRE r sys/uc_if/uc_pipe_if/ipbus_out_reg[ipb_rdata][1]/C clock pessimism -0.262 1.931 clock uncertainty 0.189 2.119 SLICE_X84Y141 FDRE (Hold_fdre_C_D) 0.087 2.206 sys/uc_if/uc_pipe_if/ipbus_out_reg[ipb_rdata][1] ------------------------------------------------------------------- required time -2.206 arrival time 2.275 ------------------------------------------------------------------- slack 0.068 Slack (MET) : 0.074ns (arrival time - required time) Source: ngFEC/clkRate0/rateCtr_reg[6]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: ngFEC/clkRate0/value_reg[9]/D (rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: clk_ipb_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_ipb_ub rise@0.000ns - clk125_ub rise@0.000ns) Data Path Delay: 0.589ns (logic 0.100ns (16.992%) route 0.489ns (83.008%)) Logic Levels: 0 Clock Path Skew: 0.279ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.178ns Source Clock Delay (SCD): 1.637ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.004 1.017 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.594 1.637 ngFEC/clkRate0/osc125_a_bufg SLICE_X163Y248 FDRE r ngFEC/clkRate0/rateCtr_reg[6]/C ------------------------------------------------------------------- ------------------- SLICE_X163Y248 FDRE (Prop_fdre_C_Q) 0.100 1.737 r ngFEC/clkRate0/rateCtr_reg[6]/Q net (fo=2, routed) 0.489 2.225 ngFEC/clkRate0/rateCtr_reg[6] SLICE_X163Y246 FDRE r ngFEC/clkRate0/value_reg[9]/D ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 1.073 1.348 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 0.800 2.178 ngFEC/clkRate0/clk_31_250_bufg SLICE_X163Y246 FDRE r ngFEC/clkRate0/value_reg[9]/C clock pessimism -0.262 1.916 clock uncertainty 0.189 2.104 SLICE_X163Y246 FDRE (Hold_fdre_C_D) 0.047 2.151 ngFEC/clkRate0/value_reg[9] ------------------------------------------------------------------- required time -2.151 arrival time 2.225 ------------------------------------------------------------------- slack 0.074 Slack (MET) : 0.077ns (arrival time - required time) Source: sys/uc_if/uc_pipe_if/r_addr_pipe_reg[8]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/uc_if/uc_pipe_if/ipbus_out_reg[ipb_rdata][8]/D (rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: clk_ipb_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_ipb_ub rise@0.000ns - clk125_ub rise@0.000ns) Data Path Delay: 0.620ns (logic 0.128ns (20.641%) route 0.492ns (79.359%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.293ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.192ns Source Clock Delay (SCD): 1.637ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.004 1.017 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.594 1.637 sys/uc_if/uc_pipe_if/r_addr_pipe_reg[9]_0 SLICE_X85Y140 FDRE r sys/uc_if/uc_pipe_if/r_addr_pipe_reg[8]/C ------------------------------------------------------------------- ------------------- SLICE_X85Y140 FDRE (Prop_fdre_C_Q) 0.100 1.737 r sys/uc_if/uc_pipe_if/r_addr_pipe_reg[8]/Q net (fo=4, routed) 0.492 2.229 sys/uc_if/uc_pipe_if/r_addr_pipe_reg__0[8] SLICE_X85Y138 LUT6 (Prop_lut6_I2_O) 0.028 2.257 r sys/uc_if/uc_pipe_if/ipbus_out[ipb_rdata][8]_i_1/O net (fo=1, routed) 0.000 2.257 sys/uc_if/uc_pipe_if/ipbus_out[ipb_rdata][8]_i_1_n_0 SLICE_X85Y138 FDRE r sys/uc_if/uc_pipe_if/ipbus_out_reg[ipb_rdata][8]/D ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 1.073 1.348 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 0.814 2.192 sys/uc_if/uc_pipe_if/out SLICE_X85Y138 FDRE r sys/uc_if/uc_pipe_if/ipbus_out_reg[ipb_rdata][8]/C clock pessimism -0.262 1.930 clock uncertainty 0.189 2.118 SLICE_X85Y138 FDRE (Hold_fdre_C_D) 0.061 2.179 sys/uc_if/uc_pipe_if/ipbus_out_reg[ipb_rdata][8] ------------------------------------------------------------------- required time -2.179 arrival time 2.257 ------------------------------------------------------------------- slack 0.077 Slack (MET) : 0.081ns (arrival time - required time) Source: ngFEC/clk_rate_gen[8].clkRate3/rateCtr_reg[14]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: ngFEC/clk_rate_gen[8].clkRate3/value_reg[17]/D (rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: clk_ipb_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_ipb_ub rise@0.000ns - clk125_ub rise@0.000ns) Data Path Delay: 0.638ns (logic 0.100ns (15.685%) route 0.538ns (84.315%)) Logic Levels: 0 Clock Path Skew: 0.301ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.310ns Source Clock Delay (SCD): 1.747ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.004 1.017 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.704 1.747 ngFEC/clk_rate_gen[8].clkRate3/osc125_a_bufg SLICE_X179Y254 FDRE r ngFEC/clk_rate_gen[8].clkRate3/rateCtr_reg[14]/C ------------------------------------------------------------------- ------------------- SLICE_X179Y254 FDRE (Prop_fdre_C_Q) 0.100 1.847 r ngFEC/clk_rate_gen[8].clkRate3/rateCtr_reg[14]/Q net (fo=2, routed) 0.538 2.384 ngFEC/clk_rate_gen[8].clkRate3/rateCtr_reg[14] SLICE_X176Y255 FDRE r ngFEC/clk_rate_gen[8].clkRate3/value_reg[17]/D ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 1.073 1.348 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 0.932 2.310 ngFEC/clk_rate_gen[8].clkRate3/clk_31_250_bufg SLICE_X176Y255 FDRE r ngFEC/clk_rate_gen[8].clkRate3/value_reg[17]/C clock pessimism -0.262 2.048 clock uncertainty 0.189 2.236 SLICE_X176Y255 FDRE (Hold_fdre_C_D) 0.067 2.303 ngFEC/clk_rate_gen[8].clkRate3/value_reg[17] ------------------------------------------------------------------- required time -2.303 arrival time 2.384 ------------------------------------------------------------------- slack 0.081 Slack (MET) : 0.082ns (arrival time - required time) Source: ngFEC/clk_rate_gen[7].clkRate3/rateCtr_reg[22]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: ngFEC/clk_rate_gen[7].clkRate3/value_reg[25]/D (rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: clk_ipb_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_ipb_ub rise@0.000ns - clk125_ub rise@0.000ns) Data Path Delay: 0.621ns (logic 0.100ns (16.111%) route 0.521ns (83.889%)) Logic Levels: 0 Clock Path Skew: 0.301ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.307ns Source Clock Delay (SCD): 1.744ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.004 1.017 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.701 1.744 ngFEC/clk_rate_gen[7].clkRate3/osc125_a_bufg SLICE_X175Y255 FDRE r ngFEC/clk_rate_gen[7].clkRate3/rateCtr_reg[22]/C ------------------------------------------------------------------- ------------------- SLICE_X175Y255 FDRE (Prop_fdre_C_Q) 0.100 1.844 r ngFEC/clk_rate_gen[7].clkRate3/rateCtr_reg[22]/Q net (fo=2, routed) 0.521 2.364 ngFEC/clk_rate_gen[7].clkRate3/rateCtr_reg[22] SLICE_X175Y256 FDRE r ngFEC/clk_rate_gen[7].clkRate3/value_reg[25]/D ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 1.073 1.348 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 0.929 2.307 ngFEC/clk_rate_gen[7].clkRate3/clk_31_250_bufg SLICE_X175Y256 FDRE r ngFEC/clk_rate_gen[7].clkRate3/value_reg[25]/C clock pessimism -0.262 2.045 clock uncertainty 0.189 2.233 SLICE_X175Y256 FDRE (Hold_fdre_C_D) 0.049 2.282 ngFEC/clk_rate_gen[7].clkRate3/value_reg[25] ------------------------------------------------------------------- required time -2.282 arrival time 2.364 ------------------------------------------------------------------- slack 0.082 Slack (MET) : 0.088ns (arrival time - required time) Source: sys/uc_if/uc_pipe_if/r_addr_pipe_reg[9]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/uc_if/uc_pipe_if/ipbus_out_reg[ipb_rdata][9]/D (rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: clk_ipb_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_ipb_ub rise@0.000ns - clk125_ub rise@0.000ns) Data Path Delay: 0.632ns (logic 0.155ns (24.544%) route 0.477ns (75.456%)) Logic Levels: 1 (LUT6=1) Clock Path Skew: 0.294ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.193ns Source Clock Delay (SCD): 1.637ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.004 1.017 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.594 1.637 sys/uc_if/uc_pipe_if/r_addr_pipe_reg[9]_0 SLICE_X85Y140 FDRE r sys/uc_if/uc_pipe_if/r_addr_pipe_reg[9]/C ------------------------------------------------------------------- ------------------- SLICE_X85Y140 FDRE (Prop_fdre_C_Q) 0.091 1.728 r sys/uc_if/uc_pipe_if/r_addr_pipe_reg[9]/Q net (fo=3, routed) 0.477 2.204 sys/uc_if/uc_pipe_if/r_addr_pipe_reg__0[9] SLICE_X85Y141 LUT6 (Prop_lut6_I2_O) 0.064 2.268 r sys/uc_if/uc_pipe_if/ipbus_out[ipb_rdata][9]_i_1/O net (fo=1, routed) 0.000 2.268 sys/uc_if/uc_pipe_if/ipbus_out[ipb_rdata][9]_i_1_n_0 SLICE_X85Y141 FDRE r sys/uc_if/uc_pipe_if/ipbus_out_reg[ipb_rdata][9]/D ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 1.073 1.348 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 0.815 2.193 sys/uc_if/uc_pipe_if/out SLICE_X85Y141 FDRE r sys/uc_if/uc_pipe_if/ipbus_out_reg[ipb_rdata][9]/C clock pessimism -0.262 1.931 clock uncertainty 0.189 2.119 SLICE_X85Y141 FDRE (Hold_fdre_C_D) 0.061 2.180 sys/uc_if/uc_pipe_if/ipbus_out_reg[ipb_rdata][9] ------------------------------------------------------------------- required time -2.180 arrival time 2.268 ------------------------------------------------------------------- slack 0.088 Slack (MET) : 0.090ns (arrival time - required time) Source: ngFEC/clk_rate_gen[4].clkRate3/rateCtr_reg[1]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: ngFEC/clk_rate_gen[4].clkRate3/value_reg[4]/D (rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: clk_ipb_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_ipb_ub rise@0.000ns - clk125_ub rise@0.000ns) Data Path Delay: 0.631ns (logic 0.118ns (18.711%) route 0.513ns (81.289%)) Logic Levels: 0 Clock Path Skew: 0.303ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.312ns Source Clock Delay (SCD): 1.747ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.004 1.017 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.704 1.747 ngFEC/clk_rate_gen[4].clkRate3/osc125_a_bufg SLICE_X180Y254 FDRE r ngFEC/clk_rate_gen[4].clkRate3/rateCtr_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X180Y254 FDRE (Prop_fdre_C_Q) 0.118 1.865 r ngFEC/clk_rate_gen[4].clkRate3/rateCtr_reg[1]/Q net (fo=2, routed) 0.513 2.377 ngFEC/clk_rate_gen[4].clkRate3/rateCtr_reg[1] SLICE_X181Y252 FDRE r ngFEC/clk_rate_gen[4].clkRate3/value_reg[4]/D ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 1.073 1.348 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 0.934 2.312 ngFEC/clk_rate_gen[4].clkRate3/clk_31_250_bufg SLICE_X181Y252 FDRE r ngFEC/clk_rate_gen[4].clkRate3/value_reg[4]/C clock pessimism -0.262 2.050 clock uncertainty 0.189 2.238 SLICE_X181Y252 FDRE (Hold_fdre_C_D) 0.049 2.287 ngFEC/clk_rate_gen[4].clkRate3/value_reg[4] ------------------------------------------------------------------- required time -2.287 arrival time 2.377 ------------------------------------------------------------------- slack 0.090 Slack (MET) : 0.090ns (arrival time - required time) Source: ngFEC/clk_rate_gen[4].clkRate3/rateCtr_reg[4]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: ngFEC/clk_rate_gen[4].clkRate3/value_reg[7]/D (rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: clk_ipb_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_ipb_ub rise@0.000ns - clk125_ub rise@0.000ns) Data Path Delay: 0.622ns (logic 0.118ns (18.967%) route 0.504ns (81.033%)) Logic Levels: 0 Clock Path Skew: 0.303ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.312ns Source Clock Delay (SCD): 1.747ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.004 1.017 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.704 1.747 ngFEC/clk_rate_gen[4].clkRate3/osc125_a_bufg SLICE_X180Y255 FDRE r ngFEC/clk_rate_gen[4].clkRate3/rateCtr_reg[4]/C ------------------------------------------------------------------- ------------------- SLICE_X180Y255 FDRE (Prop_fdre_C_Q) 0.118 1.865 r ngFEC/clk_rate_gen[4].clkRate3/rateCtr_reg[4]/Q net (fo=2, routed) 0.504 2.369 ngFEC/clk_rate_gen[4].clkRate3/rateCtr_reg[4] SLICE_X182Y252 FDRE r ngFEC/clk_rate_gen[4].clkRate3/value_reg[7]/D ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 1.073 1.348 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 0.934 2.312 ngFEC/clk_rate_gen[4].clkRate3/clk_31_250_bufg SLICE_X182Y252 FDRE r ngFEC/clk_rate_gen[4].clkRate3/value_reg[7]/C clock pessimism -0.262 2.050 clock uncertainty 0.189 2.238 SLICE_X182Y252 FDRE (Hold_fdre_C_D) 0.040 2.278 ngFEC/clk_rate_gen[4].clkRate3/value_reg[7] ------------------------------------------------------------------- required time -2.278 arrival time 2.369 ------------------------------------------------------------------- slack 0.090 Slack (MET) : 0.092ns (arrival time - required time) Source: ngFEC/clkRate1/rateCtr_reg[20]/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: ngFEC/clkRate1/value_reg[23]/D (rising edge-triggered cell FDRE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: clk_ipb_ub Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_ipb_ub rise@0.000ns - clk125_ub rise@0.000ns) Data Path Delay: 0.624ns (logic 0.100ns (16.027%) route 0.524ns (83.973%)) Logic Levels: 0 Clock Path Skew: 0.302ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.310ns Source Clock Delay (SCD): 1.746ns Clock Pessimism Removal (CPR): 0.262ns Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.004 1.017 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.703 1.746 ngFEC/clkRate1/osc125_a_bufg SLICE_X183Y258 FDRE r ngFEC/clkRate1/rateCtr_reg[20]/C ------------------------------------------------------------------- ------------------- SLICE_X183Y258 FDRE (Prop_fdre_C_Q) 0.100 1.846 r ngFEC/clkRate1/rateCtr_reg[20]/Q net (fo=2, routed) 0.524 2.369 ngFEC/clkRate1/rateCtr_reg[20] SLICE_X183Y259 FDRE r ngFEC/clkRate1/value_reg[23]/D ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 1.073 1.348 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 0.932 2.310 ngFEC/clkRate1/clk_31_250_bufg SLICE_X183Y259 FDRE r ngFEC/clkRate1/value_reg[23]/C clock pessimism -0.262 2.048 clock uncertainty 0.189 2.236 SLICE_X183Y259 FDRE (Hold_fdre_C_D) 0.041 2.277 ngFEC/clkRate1/value_reg[23] ------------------------------------------------------------------- required time -2.277 arrival time 2.369 ------------------------------------------------------------------- slack 0.092 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: clk125_ub To Clock: clk125_ub Setup : 0 Failing Endpoints, Worst Slack 4.195ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.527ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.195ns (required time - arrival time) Source: sys/clocks/rst_125_reg/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/uc_if/spi/cs_sreg_reg[0]/CLR (recovery check against rising-edge clock clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (clk125_ub rise@8.000ns - clk125_ub rise@0.000ns) Data Path Delay: 3.415ns (logic 0.223ns (6.531%) route 3.192ns (93.469%)) Logic Levels: 0 Clock Path Skew: -0.133ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.987ns = ( 11.987 - 8.000 ) Source Clock Delay (SCD): 5.146ns Clock Pessimism Removal (CPR): 1.026ns Clock Uncertainty: 0.045ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.057ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.205 3.654 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.399 5.146 sys/clocks/PLLE2_BASE_inst_0 SLICE_X96Y115 FDRE r sys/clocks/rst_125_reg/C ------------------------------------------------------------------- ------------------- SLICE_X96Y115 FDRE (Prop_fdre_C_Q) 0.223 5.369 f sys/clocks/rst_125_reg/Q net (fo=1307, routed) 3.192 8.560 sys/uc_if/spi/rst_125mhz SLICE_X77Y127 FDCE f sys/uc_if/spi/cs_sreg_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 12.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -3.847 8.575 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.078 10.653 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.251 11.987 sys/uc_if/spi/SerialOutRegister_reg[1]_0 SLICE_X77Y127 FDCE r sys/uc_if/spi/cs_sreg_reg[0]/C clock pessimism 1.026 13.013 clock uncertainty -0.045 12.967 SLICE_X77Y127 FDCE (Recov_fdce_C_CLR) -0.212 12.755 sys/uc_if/spi/cs_sreg_reg[0] ------------------------------------------------------------------- required time 12.755 arrival time -8.560 ------------------------------------------------------------------- slack 4.195 Slack (MET) : 4.195ns (required time - arrival time) Source: sys/clocks/rst_125_reg/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/uc_if/spi/cs_sreg_reg[1]/CLR (recovery check against rising-edge clock clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (clk125_ub rise@8.000ns - clk125_ub rise@0.000ns) Data Path Delay: 3.415ns (logic 0.223ns (6.531%) route 3.192ns (93.469%)) Logic Levels: 0 Clock Path Skew: -0.133ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.987ns = ( 11.987 - 8.000 ) Source Clock Delay (SCD): 5.146ns Clock Pessimism Removal (CPR): 1.026ns Clock Uncertainty: 0.045ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.057ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.205 3.654 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.399 5.146 sys/clocks/PLLE2_BASE_inst_0 SLICE_X96Y115 FDRE r sys/clocks/rst_125_reg/C ------------------------------------------------------------------- ------------------- SLICE_X96Y115 FDRE (Prop_fdre_C_Q) 0.223 5.369 f sys/clocks/rst_125_reg/Q net (fo=1307, routed) 3.192 8.560 sys/uc_if/spi/rst_125mhz SLICE_X77Y127 FDCE f sys/uc_if/spi/cs_sreg_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 12.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -3.847 8.575 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.078 10.653 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.251 11.987 sys/uc_if/spi/SerialOutRegister_reg[1]_0 SLICE_X77Y127 FDCE r sys/uc_if/spi/cs_sreg_reg[1]/C clock pessimism 1.026 13.013 clock uncertainty -0.045 12.967 SLICE_X77Y127 FDCE (Recov_fdce_C_CLR) -0.212 12.755 sys/uc_if/spi/cs_sreg_reg[1] ------------------------------------------------------------------- required time 12.755 arrival time -8.560 ------------------------------------------------------------------- slack 4.195 Slack (MET) : 4.195ns (required time - arrival time) Source: sys/clocks/rst_125_reg/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/uc_if/spi/sck_sreg_reg[0]/CLR (recovery check against rising-edge clock clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (clk125_ub rise@8.000ns - clk125_ub rise@0.000ns) Data Path Delay: 3.415ns (logic 0.223ns (6.531%) route 3.192ns (93.469%)) Logic Levels: 0 Clock Path Skew: -0.133ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.987ns = ( 11.987 - 8.000 ) Source Clock Delay (SCD): 5.146ns Clock Pessimism Removal (CPR): 1.026ns Clock Uncertainty: 0.045ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.057ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.205 3.654 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.399 5.146 sys/clocks/PLLE2_BASE_inst_0 SLICE_X96Y115 FDRE r sys/clocks/rst_125_reg/C ------------------------------------------------------------------- ------------------- SLICE_X96Y115 FDRE (Prop_fdre_C_Q) 0.223 5.369 f sys/clocks/rst_125_reg/Q net (fo=1307, routed) 3.192 8.560 sys/uc_if/spi/rst_125mhz SLICE_X77Y127 FDCE f sys/uc_if/spi/sck_sreg_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 12.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -3.847 8.575 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.078 10.653 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.251 11.987 sys/uc_if/spi/SerialOutRegister_reg[1]_0 SLICE_X77Y127 FDCE r sys/uc_if/spi/sck_sreg_reg[0]/C clock pessimism 1.026 13.013 clock uncertainty -0.045 12.967 SLICE_X77Y127 FDCE (Recov_fdce_C_CLR) -0.212 12.755 sys/uc_if/spi/sck_sreg_reg[0] ------------------------------------------------------------------- required time 12.755 arrival time -8.560 ------------------------------------------------------------------- slack 4.195 Slack (MET) : 4.195ns (required time - arrival time) Source: sys/clocks/rst_125_reg/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/uc_if/spi/sck_sreg_reg[1]/CLR (recovery check against rising-edge clock clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (clk125_ub rise@8.000ns - clk125_ub rise@0.000ns) Data Path Delay: 3.415ns (logic 0.223ns (6.531%) route 3.192ns (93.469%)) Logic Levels: 0 Clock Path Skew: -0.133ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.987ns = ( 11.987 - 8.000 ) Source Clock Delay (SCD): 5.146ns Clock Pessimism Removal (CPR): 1.026ns Clock Uncertainty: 0.045ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.057ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.205 3.654 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.399 5.146 sys/clocks/PLLE2_BASE_inst_0 SLICE_X96Y115 FDRE r sys/clocks/rst_125_reg/C ------------------------------------------------------------------- ------------------- SLICE_X96Y115 FDRE (Prop_fdre_C_Q) 0.223 5.369 f sys/clocks/rst_125_reg/Q net (fo=1307, routed) 3.192 8.560 sys/uc_if/spi/rst_125mhz SLICE_X77Y127 FDCE f sys/uc_if/spi/sck_sreg_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 12.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -3.847 8.575 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.078 10.653 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.251 11.987 sys/uc_if/spi/SerialOutRegister_reg[1]_0 SLICE_X77Y127 FDCE r sys/uc_if/spi/sck_sreg_reg[1]/C clock pessimism 1.026 13.013 clock uncertainty -0.045 12.967 SLICE_X77Y127 FDCE (Recov_fdce_C_CLR) -0.212 12.755 sys/uc_if/spi/sck_sreg_reg[1] ------------------------------------------------------------------- required time 12.755 arrival time -8.560 ------------------------------------------------------------------- slack 4.195 Slack (MET) : 4.329ns (required time - arrival time) Source: sys/clocks/rst_125_reg/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/uc_if/spi/si_sreg_reg[0]/CLR (recovery check against rising-edge clock clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (clk125_ub rise@8.000ns - clk125_ub rise@0.000ns) Data Path Delay: 3.285ns (logic 0.223ns (6.788%) route 3.062ns (93.212%)) Logic Levels: 0 Clock Path Skew: -0.128ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.992ns = ( 11.992 - 8.000 ) Source Clock Delay (SCD): 5.146ns Clock Pessimism Removal (CPR): 1.026ns Clock Uncertainty: 0.045ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.057ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.205 3.654 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.399 5.146 sys/clocks/PLLE2_BASE_inst_0 SLICE_X96Y115 FDRE r sys/clocks/rst_125_reg/C ------------------------------------------------------------------- ------------------- SLICE_X96Y115 FDRE (Prop_fdre_C_Q) 0.223 5.369 f sys/clocks/rst_125_reg/Q net (fo=1307, routed) 3.062 8.431 sys/uc_if/spi/rst_125mhz SLICE_X81Y132 FDCE f sys/uc_if/spi/si_sreg_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 12.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -3.847 8.575 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.078 10.653 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.256 11.992 sys/uc_if/spi/SerialOutRegister_reg[1]_0 SLICE_X81Y132 FDCE r sys/uc_if/spi/si_sreg_reg[0]/C clock pessimism 1.026 13.018 clock uncertainty -0.045 12.972 SLICE_X81Y132 FDCE (Recov_fdce_C_CLR) -0.212 12.760 sys/uc_if/spi/si_sreg_reg[0] ------------------------------------------------------------------- required time 12.760 arrival time -8.431 ------------------------------------------------------------------- slack 4.329 Slack (MET) : 4.384ns (required time - arrival time) Source: sys/clocks/rst_125_reg/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/uc_if/spi/si_sreg_reg[1]/CLR (recovery check against rising-edge clock clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (clk125_ub rise@8.000ns - clk125_ub rise@0.000ns) Data Path Delay: 3.226ns (logic 0.223ns (6.913%) route 3.003ns (93.087%)) Logic Levels: 0 Clock Path Skew: -0.133ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.987ns = ( 11.987 - 8.000 ) Source Clock Delay (SCD): 5.146ns Clock Pessimism Removal (CPR): 1.026ns Clock Uncertainty: 0.045ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.057ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.205 3.654 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.399 5.146 sys/clocks/PLLE2_BASE_inst_0 SLICE_X96Y115 FDRE r sys/clocks/rst_125_reg/C ------------------------------------------------------------------- ------------------- SLICE_X96Y115 FDRE (Prop_fdre_C_Q) 0.223 5.369 f sys/clocks/rst_125_reg/Q net (fo=1307, routed) 3.003 8.371 sys/uc_if/spi/rst_125mhz SLICE_X81Y127 FDCE f sys/uc_if/spi/si_sreg_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 12.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -3.847 8.575 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.078 10.653 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.251 11.987 sys/uc_if/spi/SerialOutRegister_reg[1]_0 SLICE_X81Y127 FDCE r sys/uc_if/spi/si_sreg_reg[1]/C clock pessimism 1.026 13.013 clock uncertainty -0.045 12.967 SLICE_X81Y127 FDCE (Recov_fdce_C_CLR) -0.212 12.755 sys/uc_if/spi/si_sreg_reg[1] ------------------------------------------------------------------- required time 12.755 arrival time -8.371 ------------------------------------------------------------------- slack 4.384 Slack (MET) : 4.397ns (required time - arrival time) Source: sys/clocks/rst_125_reg/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/uc_if/spi/mode_reg[0]/CLR (recovery check against rising-edge clock clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (clk125_ub rise@8.000ns - clk125_ub rise@0.000ns) Data Path Delay: 3.234ns (logic 0.223ns (6.895%) route 3.011ns (93.105%)) Logic Levels: 0 Clock Path Skew: -0.136ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.984ns = ( 11.984 - 8.000 ) Source Clock Delay (SCD): 5.146ns Clock Pessimism Removal (CPR): 1.026ns Clock Uncertainty: 0.045ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.057ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.205 3.654 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.399 5.146 sys/clocks/PLLE2_BASE_inst_0 SLICE_X96Y115 FDRE r sys/clocks/rst_125_reg/C ------------------------------------------------------------------- ------------------- SLICE_X96Y115 FDRE (Prop_fdre_C_Q) 0.223 5.369 f sys/clocks/rst_125_reg/Q net (fo=1307, routed) 3.011 8.380 sys/uc_if/spi/rst_125mhz SLICE_X82Y125 FDCE f sys/uc_if/spi/mode_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 12.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -3.847 8.575 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.078 10.653 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.248 11.984 sys/uc_if/spi/SerialOutRegister_reg[1]_0 SLICE_X82Y125 FDCE r sys/uc_if/spi/mode_reg[0]/C clock pessimism 1.026 13.010 clock uncertainty -0.045 12.964 SLICE_X82Y125 FDCE (Recov_fdce_C_CLR) -0.187 12.777 sys/uc_if/spi/mode_reg[0] ------------------------------------------------------------------- required time 12.777 arrival time -8.380 ------------------------------------------------------------------- slack 4.397 Slack (MET) : 4.430ns (required time - arrival time) Source: sys/clocks/rst_125_reg/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/uc_if/spi/SerialInRegister_reg[0]/CLR (recovery check against rising-edge clock clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (clk125_ub rise@8.000ns - clk125_ub rise@0.000ns) Data Path Delay: 3.234ns (logic 0.223ns (6.895%) route 3.011ns (93.105%)) Logic Levels: 0 Clock Path Skew: -0.136ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.984ns = ( 11.984 - 8.000 ) Source Clock Delay (SCD): 5.146ns Clock Pessimism Removal (CPR): 1.026ns Clock Uncertainty: 0.045ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.057ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.205 3.654 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.399 5.146 sys/clocks/PLLE2_BASE_inst_0 SLICE_X96Y115 FDRE r sys/clocks/rst_125_reg/C ------------------------------------------------------------------- ------------------- SLICE_X96Y115 FDRE (Prop_fdre_C_Q) 0.223 5.369 f sys/clocks/rst_125_reg/Q net (fo=1307, routed) 3.011 8.380 sys/uc_if/spi/rst_125mhz SLICE_X82Y125 FDCE f sys/uc_if/spi/SerialInRegister_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 12.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -3.847 8.575 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.078 10.653 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.248 11.984 sys/uc_if/spi/SerialOutRegister_reg[1]_0 SLICE_X82Y125 FDCE r sys/uc_if/spi/SerialInRegister_reg[0]/C clock pessimism 1.026 13.010 clock uncertainty -0.045 12.964 SLICE_X82Y125 FDCE (Recov_fdce_C_CLR) -0.154 12.810 sys/uc_if/spi/SerialInRegister_reg[0] ------------------------------------------------------------------- required time 12.810 arrival time -8.380 ------------------------------------------------------------------- slack 4.430 Slack (MET) : 4.430ns (required time - arrival time) Source: sys/clocks/rst_125_reg/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/uc_if/spi/mode_reg[1]/CLR (recovery check against rising-edge clock clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (clk125_ub rise@8.000ns - clk125_ub rise@0.000ns) Data Path Delay: 3.234ns (logic 0.223ns (6.895%) route 3.011ns (93.105%)) Logic Levels: 0 Clock Path Skew: -0.136ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.984ns = ( 11.984 - 8.000 ) Source Clock Delay (SCD): 5.146ns Clock Pessimism Removal (CPR): 1.026ns Clock Uncertainty: 0.045ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.057ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.205 3.654 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.399 5.146 sys/clocks/PLLE2_BASE_inst_0 SLICE_X96Y115 FDRE r sys/clocks/rst_125_reg/C ------------------------------------------------------------------- ------------------- SLICE_X96Y115 FDRE (Prop_fdre_C_Q) 0.223 5.369 f sys/clocks/rst_125_reg/Q net (fo=1307, routed) 3.011 8.380 sys/uc_if/spi/rst_125mhz SLICE_X82Y125 FDCE f sys/uc_if/spi/mode_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 12.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -3.847 8.575 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.078 10.653 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.248 11.984 sys/uc_if/spi/SerialOutRegister_reg[1]_0 SLICE_X82Y125 FDCE r sys/uc_if/spi/mode_reg[1]/C clock pessimism 1.026 13.010 clock uncertainty -0.045 12.964 SLICE_X82Y125 FDCE (Recov_fdce_C_CLR) -0.154 12.810 sys/uc_if/spi/mode_reg[1] ------------------------------------------------------------------- required time 12.810 arrival time -8.380 ------------------------------------------------------------------- slack 4.430 Slack (MET) : 4.430ns (required time - arrival time) Source: sys/clocks/rst_125_reg/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/uc_if/spi/rx_state_reg/CLR (recovery check against rising-edge clock clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (clk125_ub rise@8.000ns - clk125_ub rise@0.000ns) Data Path Delay: 3.234ns (logic 0.223ns (6.895%) route 3.011ns (93.105%)) Logic Levels: 0 Clock Path Skew: -0.136ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 3.984ns = ( 11.984 - 8.000 ) Source Clock Delay (SCD): 5.146ns Clock Pessimism Removal (CPR): 1.026ns Clock Uncertainty: 0.045ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.057ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.205 3.654 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.399 5.146 sys/clocks/PLLE2_BASE_inst_0 SLICE_X96Y115 FDRE r sys/clocks/rst_125_reg/C ------------------------------------------------------------------- ------------------- SLICE_X96Y115 FDRE (Prop_fdre_C_Q) 0.223 5.369 f sys/clocks/rst_125_reg/Q net (fo=1307, routed) 3.011 8.380 sys/uc_if/spi/rst_125mhz SLICE_X82Y125 FDCE f sys/uc_if/spi/rx_state_reg/CLR ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 8.000 8.000 r AD6 0.000 8.000 r osc125_a_p (IN) net (fo=0) 0.000 8.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 8.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 8.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 9.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 10.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 12.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -3.847 8.575 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 2.078 10.653 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.083 10.736 r sys/clocks/clk125_buf/O net (fo=4650, routed) 1.248 11.984 sys/uc_if/spi/SerialOutRegister_reg[1]_0 SLICE_X82Y125 FDCE r sys/uc_if/spi/rx_state_reg/C clock pessimism 1.026 13.010 clock uncertainty -0.045 12.964 SLICE_X82Y125 FDCE (Recov_fdce_C_CLR) -0.154 12.810 sys/uc_if/spi/rx_state_reg ------------------------------------------------------------------- required time 12.810 arrival time -8.380 ------------------------------------------------------------------- slack 4.430 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.527ns (arrival time - required time) Source: sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET/reset_sync6/C (rising edge-triggered cell FDPE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.RESET_INT_PIPE_reg/PRE (removal check against rising-edge clock clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk125_ub rise@0.000ns - clk125_ub rise@0.000ns) Data Path Delay: 0.469ns (logic 0.157ns (33.478%) route 0.312ns (66.522%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.291ns Source Clock Delay (SCD): 1.732ns Clock Pessimism Removal (CPR): 0.545ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.004 1.017 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.689 1.732 sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET/userclk2 SLICE_X184Y109 FDPE r sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET/reset_sync6/C ------------------------------------------------------------------- ------------------- SLICE_X184Y109 FDPE (Prop_fdpe_C_Q) 0.091 1.823 f sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET/reset_sync6/Q net (fo=1, routed) 0.180 2.003 sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET/reset_out SLICE_X185Y109 LUT2 (Prop_lut2_I0_O) 0.066 2.069 f sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET/MGT_RESET.RESET_INT_PIPE_i_1/O net (fo=2, routed) 0.132 2.201 sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET_n_0 SLICE_X187Y108 FDPE f sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.RESET_INT_PIPE_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.073 1.348 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.913 2.291 sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/userclk2 SLICE_X187Y108 FDPE r sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.RESET_INT_PIPE_reg/C clock pessimism -0.545 1.746 SLICE_X187Y108 FDPE (Remov_fdpe_C_PRE) -0.072 1.674 sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.RESET_INT_PIPE_reg ------------------------------------------------------------------- required time -1.674 arrival time 2.201 ------------------------------------------------------------------- slack 0.527 Slack (MET) : 0.527ns (arrival time - required time) Source: sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET/reset_sync6/C (rising edge-triggered cell FDPE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.RESET_INT_reg/PRE (removal check against rising-edge clock clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk125_ub rise@0.000ns - clk125_ub rise@0.000ns) Data Path Delay: 0.469ns (logic 0.157ns (33.478%) route 0.312ns (66.522%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.291ns Source Clock Delay (SCD): 1.732ns Clock Pessimism Removal (CPR): 0.545ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.004 1.017 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.689 1.732 sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET/userclk2 SLICE_X184Y109 FDPE r sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET/reset_sync6/C ------------------------------------------------------------------- ------------------- SLICE_X184Y109 FDPE (Prop_fdpe_C_Q) 0.091 1.823 f sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET/reset_sync6/Q net (fo=1, routed) 0.180 2.003 sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET/reset_out SLICE_X185Y109 LUT2 (Prop_lut2_I0_O) 0.066 2.069 f sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET/MGT_RESET.RESET_INT_PIPE_i_1/O net (fo=2, routed) 0.132 2.201 sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET_n_0 SLICE_X187Y108 FDPE f sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.RESET_INT_reg/PRE ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.073 1.348 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.913 2.291 sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/userclk2 SLICE_X187Y108 FDPE r sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.RESET_INT_reg/C clock pessimism -0.545 1.746 SLICE_X187Y108 FDPE (Remov_fdpe_C_PRE) -0.072 1.674 sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.RESET_INT_reg ------------------------------------------------------------------- required time -1.674 arrival time 2.201 ------------------------------------------------------------------- slack 0.527 Slack (MET) : 0.783ns (arrival time - required time) Source: sys/clocks/rst_125_reg/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/uc_if/spi/SerialInRegister_reg[1]/CLR (removal check against rising-edge clock clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk125_ub rise@0.000ns - clk125_ub rise@0.000ns) Data Path Delay: 0.893ns (logic 0.100ns (11.193%) route 0.793ns (88.807%)) Logic Levels: 0 Clock Path Skew: 0.179ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.178ns Source Clock Delay (SCD): 1.636ns Clock Pessimism Removal (CPR): 0.363ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.004 1.017 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.593 1.636 sys/clocks/PLLE2_BASE_inst_0 SLICE_X96Y115 FDRE r sys/clocks/rst_125_reg/C ------------------------------------------------------------------- ------------------- SLICE_X96Y115 FDRE (Prop_fdre_C_Q) 0.100 1.736 f sys/clocks/rst_125_reg/Q net (fo=1307, routed) 0.793 2.529 sys/uc_if/spi/rst_125mhz SLICE_X85Y125 FDCE f sys/uc_if/spi/SerialInRegister_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.073 1.348 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.800 2.178 sys/uc_if/spi/SerialOutRegister_reg[1]_0 SLICE_X85Y125 FDCE r sys/uc_if/spi/SerialInRegister_reg[1]/C clock pessimism -0.363 1.815 SLICE_X85Y125 FDCE (Remov_fdce_C_CLR) -0.069 1.746 sys/uc_if/spi/SerialInRegister_reg[1] ------------------------------------------------------------------- required time -1.746 arrival time 2.529 ------------------------------------------------------------------- slack 0.783 Slack (MET) : 0.783ns (arrival time - required time) Source: sys/clocks/rst_125_reg/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/uc_if/spi/SerialInRegister_reg[2]/CLR (removal check against rising-edge clock clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk125_ub rise@0.000ns - clk125_ub rise@0.000ns) Data Path Delay: 0.893ns (logic 0.100ns (11.193%) route 0.793ns (88.807%)) Logic Levels: 0 Clock Path Skew: 0.179ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.178ns Source Clock Delay (SCD): 1.636ns Clock Pessimism Removal (CPR): 0.363ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.004 1.017 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.593 1.636 sys/clocks/PLLE2_BASE_inst_0 SLICE_X96Y115 FDRE r sys/clocks/rst_125_reg/C ------------------------------------------------------------------- ------------------- SLICE_X96Y115 FDRE (Prop_fdre_C_Q) 0.100 1.736 f sys/clocks/rst_125_reg/Q net (fo=1307, routed) 0.793 2.529 sys/uc_if/spi/rst_125mhz SLICE_X85Y125 FDCE f sys/uc_if/spi/SerialInRegister_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.073 1.348 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.800 2.178 sys/uc_if/spi/SerialOutRegister_reg[1]_0 SLICE_X85Y125 FDCE r sys/uc_if/spi/SerialInRegister_reg[2]/C clock pessimism -0.363 1.815 SLICE_X85Y125 FDCE (Remov_fdce_C_CLR) -0.069 1.746 sys/uc_if/spi/SerialInRegister_reg[2] ------------------------------------------------------------------- required time -1.746 arrival time 2.529 ------------------------------------------------------------------- slack 0.783 Slack (MET) : 0.783ns (arrival time - required time) Source: sys/clocks/rst_125_reg/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/uc_if/spi/SerialInRegister_reg[3]/CLR (removal check against rising-edge clock clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk125_ub rise@0.000ns - clk125_ub rise@0.000ns) Data Path Delay: 0.893ns (logic 0.100ns (11.193%) route 0.793ns (88.807%)) Logic Levels: 0 Clock Path Skew: 0.179ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.178ns Source Clock Delay (SCD): 1.636ns Clock Pessimism Removal (CPR): 0.363ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.004 1.017 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.593 1.636 sys/clocks/PLLE2_BASE_inst_0 SLICE_X96Y115 FDRE r sys/clocks/rst_125_reg/C ------------------------------------------------------------------- ------------------- SLICE_X96Y115 FDRE (Prop_fdre_C_Q) 0.100 1.736 f sys/clocks/rst_125_reg/Q net (fo=1307, routed) 0.793 2.529 sys/uc_if/spi/rst_125mhz SLICE_X85Y125 FDCE f sys/uc_if/spi/SerialInRegister_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.073 1.348 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.800 2.178 sys/uc_if/spi/SerialOutRegister_reg[1]_0 SLICE_X85Y125 FDCE r sys/uc_if/spi/SerialInRegister_reg[3]/C clock pessimism -0.363 1.815 SLICE_X85Y125 FDCE (Remov_fdce_C_CLR) -0.069 1.746 sys/uc_if/spi/SerialInRegister_reg[3] ------------------------------------------------------------------- required time -1.746 arrival time 2.529 ------------------------------------------------------------------- slack 0.783 Slack (MET) : 0.783ns (arrival time - required time) Source: sys/clocks/rst_125_reg/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/uc_if/spi/SerialInValid_reg/CLR (removal check against rising-edge clock clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk125_ub rise@0.000ns - clk125_ub rise@0.000ns) Data Path Delay: 0.893ns (logic 0.100ns (11.193%) route 0.793ns (88.807%)) Logic Levels: 0 Clock Path Skew: 0.179ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.178ns Source Clock Delay (SCD): 1.636ns Clock Pessimism Removal (CPR): 0.363ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.004 1.017 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.593 1.636 sys/clocks/PLLE2_BASE_inst_0 SLICE_X96Y115 FDRE r sys/clocks/rst_125_reg/C ------------------------------------------------------------------- ------------------- SLICE_X96Y115 FDRE (Prop_fdre_C_Q) 0.100 1.736 f sys/clocks/rst_125_reg/Q net (fo=1307, routed) 0.793 2.529 sys/uc_if/spi/rst_125mhz SLICE_X85Y125 FDCE f sys/uc_if/spi/SerialInValid_reg/CLR ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.073 1.348 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.800 2.178 sys/uc_if/spi/SerialOutRegister_reg[1]_0 SLICE_X85Y125 FDCE r sys/uc_if/spi/SerialInValid_reg/C clock pessimism -0.363 1.815 SLICE_X85Y125 FDCE (Remov_fdce_C_CLR) -0.069 1.746 sys/uc_if/spi/SerialInValid_reg ------------------------------------------------------------------- required time -1.746 arrival time 2.529 ------------------------------------------------------------------- slack 0.783 Slack (MET) : 0.784ns (arrival time - required time) Source: sys/clocks/rst_125_reg/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/uc_if/spi/SerialInRegister_reg[10]/CLR (removal check against rising-edge clock clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk125_ub rise@0.000ns - clk125_ub rise@0.000ns) Data Path Delay: 0.916ns (logic 0.100ns (10.919%) route 0.816ns (89.081%)) Logic Levels: 0 Clock Path Skew: 0.182ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.181ns Source Clock Delay (SCD): 1.636ns Clock Pessimism Removal (CPR): 0.363ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.004 1.017 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.593 1.636 sys/clocks/PLLE2_BASE_inst_0 SLICE_X96Y115 FDRE r sys/clocks/rst_125_reg/C ------------------------------------------------------------------- ------------------- SLICE_X96Y115 FDRE (Prop_fdre_C_Q) 0.100 1.736 f sys/clocks/rst_125_reg/Q net (fo=1307, routed) 0.816 2.551 sys/uc_if/spi/rst_125mhz SLICE_X84Y127 FDCE f sys/uc_if/spi/SerialInRegister_reg[10]/CLR ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.073 1.348 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.803 2.181 sys/uc_if/spi/SerialOutRegister_reg[1]_0 SLICE_X84Y127 FDCE r sys/uc_if/spi/SerialInRegister_reg[10]/C clock pessimism -0.363 1.818 SLICE_X84Y127 FDCE (Remov_fdce_C_CLR) -0.050 1.768 sys/uc_if/spi/SerialInRegister_reg[10] ------------------------------------------------------------------- required time -1.768 arrival time 2.551 ------------------------------------------------------------------- slack 0.784 Slack (MET) : 0.784ns (arrival time - required time) Source: sys/clocks/rst_125_reg/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/uc_if/spi/SerialInRegister_reg[11]/CLR (removal check against rising-edge clock clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk125_ub rise@0.000ns - clk125_ub rise@0.000ns) Data Path Delay: 0.916ns (logic 0.100ns (10.919%) route 0.816ns (89.081%)) Logic Levels: 0 Clock Path Skew: 0.182ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.181ns Source Clock Delay (SCD): 1.636ns Clock Pessimism Removal (CPR): 0.363ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.004 1.017 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.593 1.636 sys/clocks/PLLE2_BASE_inst_0 SLICE_X96Y115 FDRE r sys/clocks/rst_125_reg/C ------------------------------------------------------------------- ------------------- SLICE_X96Y115 FDRE (Prop_fdre_C_Q) 0.100 1.736 f sys/clocks/rst_125_reg/Q net (fo=1307, routed) 0.816 2.551 sys/uc_if/spi/rst_125mhz SLICE_X84Y127 FDCE f sys/uc_if/spi/SerialInRegister_reg[11]/CLR ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.073 1.348 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.803 2.181 sys/uc_if/spi/SerialOutRegister_reg[1]_0 SLICE_X84Y127 FDCE r sys/uc_if/spi/SerialInRegister_reg[11]/C clock pessimism -0.363 1.818 SLICE_X84Y127 FDCE (Remov_fdce_C_CLR) -0.050 1.768 sys/uc_if/spi/SerialInRegister_reg[11] ------------------------------------------------------------------- required time -1.768 arrival time 2.551 ------------------------------------------------------------------- slack 0.784 Slack (MET) : 0.784ns (arrival time - required time) Source: sys/clocks/rst_125_reg/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/uc_if/spi/SerialInRegister_reg[14]/CLR (removal check against rising-edge clock clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk125_ub rise@0.000ns - clk125_ub rise@0.000ns) Data Path Delay: 0.916ns (logic 0.100ns (10.919%) route 0.816ns (89.081%)) Logic Levels: 0 Clock Path Skew: 0.182ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.181ns Source Clock Delay (SCD): 1.636ns Clock Pessimism Removal (CPR): 0.363ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.004 1.017 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.593 1.636 sys/clocks/PLLE2_BASE_inst_0 SLICE_X96Y115 FDRE r sys/clocks/rst_125_reg/C ------------------------------------------------------------------- ------------------- SLICE_X96Y115 FDRE (Prop_fdre_C_Q) 0.100 1.736 f sys/clocks/rst_125_reg/Q net (fo=1307, routed) 0.816 2.551 sys/uc_if/spi/rst_125mhz SLICE_X84Y127 FDCE f sys/uc_if/spi/SerialInRegister_reg[14]/CLR ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.073 1.348 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.803 2.181 sys/uc_if/spi/SerialOutRegister_reg[1]_0 SLICE_X84Y127 FDCE r sys/uc_if/spi/SerialInRegister_reg[14]/C clock pessimism -0.363 1.818 SLICE_X84Y127 FDCE (Remov_fdce_C_CLR) -0.050 1.768 sys/uc_if/spi/SerialInRegister_reg[14] ------------------------------------------------------------------- required time -1.768 arrival time 2.551 ------------------------------------------------------------------- slack 0.784 Slack (MET) : 0.784ns (arrival time - required time) Source: sys/clocks/rst_125_reg/C (rising edge-triggered cell FDRE clocked by clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: sys/uc_if/spi/SerialInRegister_reg[8]/CLR (removal check against rising-edge clock clk125_ub {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk125_ub rise@0.000ns - clk125_ub rise@0.000ns) Data Path Delay: 0.916ns (logic 0.100ns (10.919%) route 0.816ns (89.081%)) Logic Levels: 0 Clock Path Skew: 0.182ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.181ns Source Clock Delay (SCD): 1.636ns Clock Pessimism Removal (CPR): 0.363ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.004 1.017 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.593 1.636 sys/clocks/PLLE2_BASE_inst_0 SLICE_X96Y115 FDRE r sys/clocks/rst_125_reg/C ------------------------------------------------------------------- ------------------- SLICE_X96Y115 FDRE (Prop_fdre_C_Q) 0.100 1.736 f sys/clocks/rst_125_reg/Q net (fo=1307, routed) 0.816 2.551 sys/uc_if/spi/rst_125mhz SLICE_X84Y127 FDCE f sys/uc_if/spi/SerialInRegister_reg[8]/CLR ------------------------------------------------------------------- ------------------- (clock clk125_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKFBOUT) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKFBOUT net (fo=1, routed) 1.073 1.348 sys/clocks/clk125_ub BUFGCTRL_X0Y2 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk125_buf/O net (fo=4650, routed) 0.803 2.181 sys/uc_if/spi/SerialOutRegister_reg[1]_0 SLICE_X84Y127 FDCE r sys/uc_if/spi/SerialInRegister_reg[8]/C clock pessimism -0.363 1.818 SLICE_X84Y127 FDCE (Remov_fdce_C_CLR) -0.050 1.768 sys/uc_if/spi/SerialInRegister_reg[8] ------------------------------------------------------------------- required time -1.768 arrival time 2.551 ------------------------------------------------------------------- slack 0.784 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: clk_ipb_ub To Clock: clk_ipb_ub Setup : 0 Failing Endpoints, Worst Slack 15.713ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.107ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 15.713ns (required time - arrival time) Source: ngFEC/ctrl_regs_inst/regs_reg[1][8]/C (rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: ngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][13]/CLR (recovery check against rising-edge clock clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 32.000ns (clk_ipb_ub rise@32.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 16.371ns (logic 0.302ns (1.845%) route 16.069ns (98.155%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.364ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.390ns = ( 36.390 - 32.000 ) Source Clock Delay (SCD): 5.037ns Clock Pessimism Removal (CPR): 1.011ns Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.205 3.654 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.290 5.037 ngFEC/ctrl_regs_inst/clk_31_250_bufg SLICE_X132Y229 FDCE r ngFEC/ctrl_regs_inst/regs_reg[1][8]/C ------------------------------------------------------------------- ------------------- SLICE_X132Y229 FDCE (Prop_fdce_C_Q) 0.259 5.296 r ngFEC/ctrl_regs_inst/regs_reg[1][8]/Q net (fo=7, routed) 0.832 6.128 sys/clocks/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0[0] SLICE_X146Y235 LUT3 (Prop_lut3_I1_O) 0.043 6.171 f sys/clocks/bram_array[0].skip_SFP_SEC.control_reg[0][31]_i_3/O net (fo=11748, routed) 15.236 21.407 ngFEC/SFP_GEN[8].ngFEC_module/TTC_rst SLICE_X51Y24 FDCE f ngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][13]/CLR ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 32.000 32.000 r AD6 0.000 32.000 r osc125_a_p (IN) net (fo=0) 0.000 32.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 32.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 32.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 33.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 34.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 36.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -3.847 32.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.078 34.653 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.654 36.390 ngFEC/SFP_GEN[8].ngFEC_module/clk_31_250_bufg SLICE_X51Y24 FDCE r ngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][13]/C clock pessimism 1.011 37.401 clock uncertainty -0.069 37.332 SLICE_X51Y24 FDCE (Recov_fdce_C_CLR) -0.212 37.120 ngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][13] ------------------------------------------------------------------- required time 37.120 arrival time -21.407 ------------------------------------------------------------------- slack 15.713 Slack (MET) : 15.713ns (required time - arrival time) Source: ngFEC/ctrl_regs_inst/regs_reg[1][8]/C (rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: ngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][15]/CLR (recovery check against rising-edge clock clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 32.000ns (clk_ipb_ub rise@32.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 16.371ns (logic 0.302ns (1.845%) route 16.069ns (98.155%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.364ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.390ns = ( 36.390 - 32.000 ) Source Clock Delay (SCD): 5.037ns Clock Pessimism Removal (CPR): 1.011ns Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.205 3.654 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.290 5.037 ngFEC/ctrl_regs_inst/clk_31_250_bufg SLICE_X132Y229 FDCE r ngFEC/ctrl_regs_inst/regs_reg[1][8]/C ------------------------------------------------------------------- ------------------- SLICE_X132Y229 FDCE (Prop_fdce_C_Q) 0.259 5.296 r ngFEC/ctrl_regs_inst/regs_reg[1][8]/Q net (fo=7, routed) 0.832 6.128 sys/clocks/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0[0] SLICE_X146Y235 LUT3 (Prop_lut3_I1_O) 0.043 6.171 f sys/clocks/bram_array[0].skip_SFP_SEC.control_reg[0][31]_i_3/O net (fo=11748, routed) 15.236 21.407 ngFEC/SFP_GEN[8].ngFEC_module/TTC_rst SLICE_X51Y24 FDCE f ngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][15]/CLR ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 32.000 32.000 r AD6 0.000 32.000 r osc125_a_p (IN) net (fo=0) 0.000 32.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 32.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 32.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 33.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 34.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 36.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -3.847 32.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.078 34.653 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.654 36.390 ngFEC/SFP_GEN[8].ngFEC_module/clk_31_250_bufg SLICE_X51Y24 FDCE r ngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][15]/C clock pessimism 1.011 37.401 clock uncertainty -0.069 37.332 SLICE_X51Y24 FDCE (Recov_fdce_C_CLR) -0.212 37.120 ngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][15] ------------------------------------------------------------------- required time 37.120 arrival time -21.407 ------------------------------------------------------------------- slack 15.713 Slack (MET) : 15.713ns (required time - arrival time) Source: ngFEC/ctrl_regs_inst/regs_reg[1][8]/C (rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: ngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][18]/CLR (recovery check against rising-edge clock clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 32.000ns (clk_ipb_ub rise@32.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 16.371ns (logic 0.302ns (1.845%) route 16.069ns (98.155%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.364ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.390ns = ( 36.390 - 32.000 ) Source Clock Delay (SCD): 5.037ns Clock Pessimism Removal (CPR): 1.011ns Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.205 3.654 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.290 5.037 ngFEC/ctrl_regs_inst/clk_31_250_bufg SLICE_X132Y229 FDCE r ngFEC/ctrl_regs_inst/regs_reg[1][8]/C ------------------------------------------------------------------- ------------------- SLICE_X132Y229 FDCE (Prop_fdce_C_Q) 0.259 5.296 r ngFEC/ctrl_regs_inst/regs_reg[1][8]/Q net (fo=7, routed) 0.832 6.128 sys/clocks/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0[0] SLICE_X146Y235 LUT3 (Prop_lut3_I1_O) 0.043 6.171 f sys/clocks/bram_array[0].skip_SFP_SEC.control_reg[0][31]_i_3/O net (fo=11748, routed) 15.236 21.407 ngFEC/SFP_GEN[8].ngFEC_module/TTC_rst SLICE_X51Y24 FDCE f ngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][18]/CLR ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 32.000 32.000 r AD6 0.000 32.000 r osc125_a_p (IN) net (fo=0) 0.000 32.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 32.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 32.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 33.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 34.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 36.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -3.847 32.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.078 34.653 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.654 36.390 ngFEC/SFP_GEN[8].ngFEC_module/clk_31_250_bufg SLICE_X51Y24 FDCE r ngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][18]/C clock pessimism 1.011 37.401 clock uncertainty -0.069 37.332 SLICE_X51Y24 FDCE (Recov_fdce_C_CLR) -0.212 37.120 ngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][18] ------------------------------------------------------------------- required time 37.120 arrival time -21.407 ------------------------------------------------------------------- slack 15.713 Slack (MET) : 15.713ns (required time - arrival time) Source: ngFEC/ctrl_regs_inst/regs_reg[1][8]/C (rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: ngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][19]/CLR (recovery check against rising-edge clock clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 32.000ns (clk_ipb_ub rise@32.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 16.371ns (logic 0.302ns (1.845%) route 16.069ns (98.155%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.364ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.390ns = ( 36.390 - 32.000 ) Source Clock Delay (SCD): 5.037ns Clock Pessimism Removal (CPR): 1.011ns Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.205 3.654 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.290 5.037 ngFEC/ctrl_regs_inst/clk_31_250_bufg SLICE_X132Y229 FDCE r ngFEC/ctrl_regs_inst/regs_reg[1][8]/C ------------------------------------------------------------------- ------------------- SLICE_X132Y229 FDCE (Prop_fdce_C_Q) 0.259 5.296 r ngFEC/ctrl_regs_inst/regs_reg[1][8]/Q net (fo=7, routed) 0.832 6.128 sys/clocks/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0[0] SLICE_X146Y235 LUT3 (Prop_lut3_I1_O) 0.043 6.171 f sys/clocks/bram_array[0].skip_SFP_SEC.control_reg[0][31]_i_3/O net (fo=11748, routed) 15.236 21.407 ngFEC/SFP_GEN[8].ngFEC_module/TTC_rst SLICE_X51Y24 FDCE f ngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][19]/CLR ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 32.000 32.000 r AD6 0.000 32.000 r osc125_a_p (IN) net (fo=0) 0.000 32.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 32.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 32.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 33.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 34.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 36.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -3.847 32.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.078 34.653 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.654 36.390 ngFEC/SFP_GEN[8].ngFEC_module/clk_31_250_bufg SLICE_X51Y24 FDCE r ngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][19]/C clock pessimism 1.011 37.401 clock uncertainty -0.069 37.332 SLICE_X51Y24 FDCE (Recov_fdce_C_CLR) -0.212 37.120 ngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][19] ------------------------------------------------------------------- required time 37.120 arrival time -21.407 ------------------------------------------------------------------- slack 15.713 Slack (MET) : 15.748ns (required time - arrival time) Source: ngFEC/ctrl_regs_inst/regs_reg[1][8]/C (rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: ngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][9]/CLR (recovery check against rising-edge clock clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 32.000ns (clk_ipb_ub rise@32.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 16.394ns (logic 0.302ns (1.842%) route 16.092ns (98.158%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.365ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.391ns = ( 36.391 - 32.000 ) Source Clock Delay (SCD): 5.037ns Clock Pessimism Removal (CPR): 1.011ns Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.205 3.654 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.290 5.037 ngFEC/ctrl_regs_inst/clk_31_250_bufg SLICE_X132Y229 FDCE r ngFEC/ctrl_regs_inst/regs_reg[1][8]/C ------------------------------------------------------------------- ------------------- SLICE_X132Y229 FDCE (Prop_fdce_C_Q) 0.259 5.296 r ngFEC/ctrl_regs_inst/regs_reg[1][8]/Q net (fo=7, routed) 0.832 6.128 sys/clocks/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0[0] SLICE_X146Y235 LUT3 (Prop_lut3_I1_O) 0.043 6.171 f sys/clocks/bram_array[0].skip_SFP_SEC.control_reg[0][31]_i_3/O net (fo=11748, routed) 15.260 21.431 ngFEC/SFP_GEN[8].ngFEC_module/TTC_rst SLICE_X50Y23 FDCE f ngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][9]/CLR ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 32.000 32.000 r AD6 0.000 32.000 r osc125_a_p (IN) net (fo=0) 0.000 32.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 32.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 32.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 33.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 34.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 36.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -3.847 32.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.078 34.653 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.655 36.391 ngFEC/SFP_GEN[8].ngFEC_module/clk_31_250_bufg SLICE_X50Y23 FDCE r ngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][9]/C clock pessimism 1.011 37.402 clock uncertainty -0.069 37.333 SLICE_X50Y23 FDCE (Recov_fdce_C_CLR) -0.154 37.179 ngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][9] ------------------------------------------------------------------- required time 37.179 arrival time -21.431 ------------------------------------------------------------------- slack 15.748 Slack (MET) : 15.905ns (required time - arrival time) Source: ngFEC/ctrl_regs_inst/regs_reg[1][8]/C (rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: ngFEC/SFP_GEN[8].ngFEC_module/bram_array[12].skip_SFP_SEC.input_size_reg[12][17]/CLR (recovery check against rising-edge clock clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 32.000ns (clk_ipb_ub rise@32.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 16.186ns (logic 0.302ns (1.866%) route 15.884ns (98.134%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.371ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.397ns = ( 36.397 - 32.000 ) Source Clock Delay (SCD): 5.037ns Clock Pessimism Removal (CPR): 1.011ns Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.205 3.654 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.290 5.037 ngFEC/ctrl_regs_inst/clk_31_250_bufg SLICE_X132Y229 FDCE r ngFEC/ctrl_regs_inst/regs_reg[1][8]/C ------------------------------------------------------------------- ------------------- SLICE_X132Y229 FDCE (Prop_fdce_C_Q) 0.259 5.296 r ngFEC/ctrl_regs_inst/regs_reg[1][8]/Q net (fo=7, routed) 0.832 6.128 sys/clocks/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0[0] SLICE_X146Y235 LUT3 (Prop_lut3_I1_O) 0.043 6.171 f sys/clocks/bram_array[0].skip_SFP_SEC.control_reg[0][31]_i_3/O net (fo=11748, routed) 15.051 21.222 ngFEC/SFP_GEN[8].ngFEC_module/TTC_rst SLICE_X45Y31 FDCE f ngFEC/SFP_GEN[8].ngFEC_module/bram_array[12].skip_SFP_SEC.input_size_reg[12][17]/CLR ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 32.000 32.000 r AD6 0.000 32.000 r osc125_a_p (IN) net (fo=0) 0.000 32.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 32.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 32.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 33.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 34.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 36.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -3.847 32.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.078 34.653 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.661 36.397 ngFEC/SFP_GEN[8].ngFEC_module/clk_31_250_bufg SLICE_X45Y31 FDCE r ngFEC/SFP_GEN[8].ngFEC_module/bram_array[12].skip_SFP_SEC.input_size_reg[12][17]/C clock pessimism 1.011 37.408 clock uncertainty -0.069 37.339 SLICE_X45Y31 FDCE (Recov_fdce_C_CLR) -0.212 37.127 ngFEC/SFP_GEN[8].ngFEC_module/bram_array[12].skip_SFP_SEC.input_size_reg[12][17] ------------------------------------------------------------------- required time 37.127 arrival time -21.222 ------------------------------------------------------------------- slack 15.905 Slack (MET) : 15.905ns (required time - arrival time) Source: ngFEC/ctrl_regs_inst/regs_reg[1][8]/C (rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: ngFEC/SFP_GEN[8].ngFEC_module/bram_array[12].skip_SFP_SEC.input_size_reg[12][18]/CLR (recovery check against rising-edge clock clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 32.000ns (clk_ipb_ub rise@32.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 16.186ns (logic 0.302ns (1.866%) route 15.884ns (98.134%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.371ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.397ns = ( 36.397 - 32.000 ) Source Clock Delay (SCD): 5.037ns Clock Pessimism Removal (CPR): 1.011ns Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.205 3.654 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.290 5.037 ngFEC/ctrl_regs_inst/clk_31_250_bufg SLICE_X132Y229 FDCE r ngFEC/ctrl_regs_inst/regs_reg[1][8]/C ------------------------------------------------------------------- ------------------- SLICE_X132Y229 FDCE (Prop_fdce_C_Q) 0.259 5.296 r ngFEC/ctrl_regs_inst/regs_reg[1][8]/Q net (fo=7, routed) 0.832 6.128 sys/clocks/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0[0] SLICE_X146Y235 LUT3 (Prop_lut3_I1_O) 0.043 6.171 f sys/clocks/bram_array[0].skip_SFP_SEC.control_reg[0][31]_i_3/O net (fo=11748, routed) 15.051 21.222 ngFEC/SFP_GEN[8].ngFEC_module/TTC_rst SLICE_X45Y31 FDCE f ngFEC/SFP_GEN[8].ngFEC_module/bram_array[12].skip_SFP_SEC.input_size_reg[12][18]/CLR ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 32.000 32.000 r AD6 0.000 32.000 r osc125_a_p (IN) net (fo=0) 0.000 32.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 32.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 32.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 33.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 34.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 36.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -3.847 32.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.078 34.653 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.661 36.397 ngFEC/SFP_GEN[8].ngFEC_module/clk_31_250_bufg SLICE_X45Y31 FDCE r ngFEC/SFP_GEN[8].ngFEC_module/bram_array[12].skip_SFP_SEC.input_size_reg[12][18]/C clock pessimism 1.011 37.408 clock uncertainty -0.069 37.339 SLICE_X45Y31 FDCE (Recov_fdce_C_CLR) -0.212 37.127 ngFEC/SFP_GEN[8].ngFEC_module/bram_array[12].skip_SFP_SEC.input_size_reg[12][18] ------------------------------------------------------------------- required time 37.127 arrival time -21.222 ------------------------------------------------------------------- slack 15.905 Slack (MET) : 15.905ns (required time - arrival time) Source: ngFEC/ctrl_regs_inst/regs_reg[1][8]/C (rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: ngFEC/SFP_GEN[8].ngFEC_module/bram_array[12].skip_SFP_SEC.input_size_reg[12][22]/CLR (recovery check against rising-edge clock clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 32.000ns (clk_ipb_ub rise@32.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 16.186ns (logic 0.302ns (1.866%) route 15.884ns (98.134%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.371ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.397ns = ( 36.397 - 32.000 ) Source Clock Delay (SCD): 5.037ns Clock Pessimism Removal (CPR): 1.011ns Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.205 3.654 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.290 5.037 ngFEC/ctrl_regs_inst/clk_31_250_bufg SLICE_X132Y229 FDCE r ngFEC/ctrl_regs_inst/regs_reg[1][8]/C ------------------------------------------------------------------- ------------------- SLICE_X132Y229 FDCE (Prop_fdce_C_Q) 0.259 5.296 r ngFEC/ctrl_regs_inst/regs_reg[1][8]/Q net (fo=7, routed) 0.832 6.128 sys/clocks/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0[0] SLICE_X146Y235 LUT3 (Prop_lut3_I1_O) 0.043 6.171 f sys/clocks/bram_array[0].skip_SFP_SEC.control_reg[0][31]_i_3/O net (fo=11748, routed) 15.051 21.222 ngFEC/SFP_GEN[8].ngFEC_module/TTC_rst SLICE_X45Y31 FDCE f ngFEC/SFP_GEN[8].ngFEC_module/bram_array[12].skip_SFP_SEC.input_size_reg[12][22]/CLR ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 32.000 32.000 r AD6 0.000 32.000 r osc125_a_p (IN) net (fo=0) 0.000 32.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 32.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 32.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 33.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 34.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 36.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -3.847 32.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.078 34.653 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.661 36.397 ngFEC/SFP_GEN[8].ngFEC_module/clk_31_250_bufg SLICE_X45Y31 FDCE r ngFEC/SFP_GEN[8].ngFEC_module/bram_array[12].skip_SFP_SEC.input_size_reg[12][22]/C clock pessimism 1.011 37.408 clock uncertainty -0.069 37.339 SLICE_X45Y31 FDCE (Recov_fdce_C_CLR) -0.212 37.127 ngFEC/SFP_GEN[8].ngFEC_module/bram_array[12].skip_SFP_SEC.input_size_reg[12][22] ------------------------------------------------------------------- required time 37.127 arrival time -21.222 ------------------------------------------------------------------- slack 15.905 Slack (MET) : 15.905ns (required time - arrival time) Source: ngFEC/ctrl_regs_inst/regs_reg[1][8]/C (rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: ngFEC/SFP_GEN[8].ngFEC_module/bram_array[12].skip_SFP_SEC.input_size_reg[12][23]/CLR (recovery check against rising-edge clock clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 32.000ns (clk_ipb_ub rise@32.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 16.186ns (logic 0.302ns (1.866%) route 15.884ns (98.134%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.371ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.397ns = ( 36.397 - 32.000 ) Source Clock Delay (SCD): 5.037ns Clock Pessimism Removal (CPR): 1.011ns Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.205 3.654 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.290 5.037 ngFEC/ctrl_regs_inst/clk_31_250_bufg SLICE_X132Y229 FDCE r ngFEC/ctrl_regs_inst/regs_reg[1][8]/C ------------------------------------------------------------------- ------------------- SLICE_X132Y229 FDCE (Prop_fdce_C_Q) 0.259 5.296 r ngFEC/ctrl_regs_inst/regs_reg[1][8]/Q net (fo=7, routed) 0.832 6.128 sys/clocks/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0[0] SLICE_X146Y235 LUT3 (Prop_lut3_I1_O) 0.043 6.171 f sys/clocks/bram_array[0].skip_SFP_SEC.control_reg[0][31]_i_3/O net (fo=11748, routed) 15.051 21.222 ngFEC/SFP_GEN[8].ngFEC_module/TTC_rst SLICE_X45Y31 FDCE f ngFEC/SFP_GEN[8].ngFEC_module/bram_array[12].skip_SFP_SEC.input_size_reg[12][23]/CLR ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 32.000 32.000 r AD6 0.000 32.000 r osc125_a_p (IN) net (fo=0) 0.000 32.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 32.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 32.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 33.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 34.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 36.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -3.847 32.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.078 34.653 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.661 36.397 ngFEC/SFP_GEN[8].ngFEC_module/clk_31_250_bufg SLICE_X45Y31 FDCE r ngFEC/SFP_GEN[8].ngFEC_module/bram_array[12].skip_SFP_SEC.input_size_reg[12][23]/C clock pessimism 1.011 37.408 clock uncertainty -0.069 37.339 SLICE_X45Y31 FDCE (Recov_fdce_C_CLR) -0.212 37.127 ngFEC/SFP_GEN[8].ngFEC_module/bram_array[12].skip_SFP_SEC.input_size_reg[12][23] ------------------------------------------------------------------- required time 37.127 arrival time -21.222 ------------------------------------------------------------------- slack 15.905 Slack (MET) : 15.908ns (required time - arrival time) Source: ngFEC/ctrl_regs_inst/regs_reg[1][8]/C (rising edge-triggered cell FDCE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: ngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][20]/CLR (recovery check against rising-edge clock clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 32.000ns (clk_ipb_ub rise@32.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 16.176ns (logic 0.302ns (1.867%) route 15.874ns (98.133%)) Logic Levels: 1 (LUT3=1) Clock Path Skew: 0.364ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 4.390ns = ( 36.390 - 32.000 ) Source Clock Delay (SCD): 5.037ns Clock Pessimism Removal (CPR): 1.011ns Clock Uncertainty: 0.069ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.118ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 2.355 2.355 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.298 3.654 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.850 5.597 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -4.148 1.449 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.205 3.654 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.093 3.747 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.290 5.037 ngFEC/ctrl_regs_inst/clk_31_250_bufg SLICE_X132Y229 FDCE r ngFEC/ctrl_regs_inst/regs_reg[1][8]/C ------------------------------------------------------------------- ------------------- SLICE_X132Y229 FDCE (Prop_fdce_C_Q) 0.259 5.296 r ngFEC/ctrl_regs_inst/regs_reg[1][8]/Q net (fo=7, routed) 0.832 6.128 sys/clocks/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0[0] SLICE_X146Y235 LUT3 (Prop_lut3_I1_O) 0.043 6.171 f sys/clocks/bram_array[0].skip_SFP_SEC.control_reg[0][31]_i_3/O net (fo=11748, routed) 15.041 21.212 ngFEC/SFP_GEN[8].ngFEC_module/TTC_rst SLICE_X51Y25 FDCE f ngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][20]/CLR ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 32.000 32.000 r AD6 0.000 32.000 r osc125_a_p (IN) net (fo=0) 0.000 32.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 32.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 32.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 1.418 33.418 r sys/osc125a_gtebuf/O net (fo=2, routed) 1.234 34.653 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.686 36.422 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -3.847 32.575 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 2.078 34.653 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.083 34.736 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 1.654 36.390 ngFEC/SFP_GEN[8].ngFEC_module/clk_31_250_bufg SLICE_X51Y25 FDCE r ngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][20]/C clock pessimism 1.011 37.401 clock uncertainty -0.069 37.332 SLICE_X51Y25 FDCE (Recov_fdce_C_CLR) -0.212 37.120 ngFEC/SFP_GEN[8].ngFEC_module/bram_array[9].skip_SFP_SEC.control_reg_reg[9][20] ------------------------------------------------------------------- required time 37.120 arrival time -21.212 ------------------------------------------------------------------- slack 15.908 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.107ns (arrival time - required time) Source: ngFEC/SFP_GEN[12].ngFEC_module/bram_array[7].skip_SFP_SEC.synch_reset_reg[7]/C (rising edge-triggered cell FDPE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: ngFEC/SFP_GEN[12].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/timeout_cyc_reg[23]/CLR (removal check against rising-edge clock clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_ipb_ub rise@0.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 0.304ns (logic 0.100ns (32.867%) route 0.204ns (67.133%)) Logic Levels: 0 Clock Path Skew: 0.266ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.305ns Source Clock Delay (SCD): 1.676ns Clock Pessimism Removal (CPR): 0.363ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 1.004 1.017 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 0.633 1.676 ngFEC/SFP_GEN[12].ngFEC_module/clk_31_250_bufg SLICE_X57Y101 FDPE r ngFEC/SFP_GEN[12].ngFEC_module/bram_array[7].skip_SFP_SEC.synch_reset_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y101 FDPE (Prop_fdpe_C_Q) 0.100 1.776 f ngFEC/SFP_GEN[12].ngFEC_module/bram_array[7].skip_SFP_SEC.synch_reset_reg[7]/Q net (fo=164, routed) 0.204 1.980 ngFEC/SFP_GEN[12].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/response_length_reg[1]_0 SLICE_X55Y99 FDCE f ngFEC/SFP_GEN[12].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/timeout_cyc_reg[23]/CLR ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 1.073 1.348 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 0.927 2.305 ngFEC/SFP_GEN[12].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/clk_31_250_bufg SLICE_X55Y99 FDCE r ngFEC/SFP_GEN[12].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/timeout_cyc_reg[23]/C clock pessimism -0.363 1.942 SLICE_X55Y99 FDCE (Remov_fdce_C_CLR) -0.069 1.873 ngFEC/SFP_GEN[12].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/timeout_cyc_reg[23] ------------------------------------------------------------------- required time -1.873 arrival time 1.980 ------------------------------------------------------------------- slack 0.107 Slack (MET) : 0.107ns (arrival time - required time) Source: ngFEC/SFP_GEN[12].ngFEC_module/bram_array[7].skip_SFP_SEC.synch_reset_reg[7]/C (rising edge-triggered cell FDPE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: ngFEC/SFP_GEN[12].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/timeout_cyc_reg[25]/CLR (removal check against rising-edge clock clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_ipb_ub rise@0.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 0.304ns (logic 0.100ns (32.867%) route 0.204ns (67.133%)) Logic Levels: 0 Clock Path Skew: 0.266ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.305ns Source Clock Delay (SCD): 1.676ns Clock Pessimism Removal (CPR): 0.363ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 1.004 1.017 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 0.633 1.676 ngFEC/SFP_GEN[12].ngFEC_module/clk_31_250_bufg SLICE_X57Y101 FDPE r ngFEC/SFP_GEN[12].ngFEC_module/bram_array[7].skip_SFP_SEC.synch_reset_reg[7]/C ------------------------------------------------------------------- ------------------- SLICE_X57Y101 FDPE (Prop_fdpe_C_Q) 0.100 1.776 f ngFEC/SFP_GEN[12].ngFEC_module/bram_array[7].skip_SFP_SEC.synch_reset_reg[7]/Q net (fo=164, routed) 0.204 1.980 ngFEC/SFP_GEN[12].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/response_length_reg[1]_0 SLICE_X55Y99 FDCE f ngFEC/SFP_GEN[12].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/timeout_cyc_reg[25]/CLR ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 1.073 1.348 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 0.927 2.305 ngFEC/SFP_GEN[12].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/clk_31_250_bufg SLICE_X55Y99 FDCE r ngFEC/SFP_GEN[12].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/timeout_cyc_reg[25]/C clock pessimism -0.363 1.942 SLICE_X55Y99 FDCE (Remov_fdce_C_CLR) -0.069 1.873 ngFEC/SFP_GEN[12].ngFEC_module/i2c_comm_gen[7].buffer_ngccm/timeout_cyc_reg[25] ------------------------------------------------------------------- required time -1.873 arrival time 1.980 ------------------------------------------------------------------- slack 0.107 Slack (MET) : 0.140ns (arrival time - required time) Source: ngFEC/SFP_GEN[6].ngFEC_module/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0/C (rising edge-triggered cell FDPE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: ngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/jtag_command_reg[17]/CLR (removal check against rising-edge clock clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_ipb_ub rise@0.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 0.338ns (logic 0.100ns (29.577%) route 0.238ns (70.423%)) Logic Levels: 0 Clock Path Skew: 0.267ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.358ns Source Clock Delay (SCD): 1.708ns Clock Pessimism Removal (CPR): 0.383ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 1.004 1.017 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 0.665 1.708 ngFEC/SFP_GEN[6].ngFEC_module/clk_31_250_bufg SLICE_X119Y56 FDPE r ngFEC/SFP_GEN[6].ngFEC_module/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0/C ------------------------------------------------------------------- ------------------- SLICE_X119Y56 FDPE (Prop_fdpe_C_Q) 0.100 1.808 f ngFEC/SFP_GEN[6].ngFEC_module/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0/Q net (fo=96, routed) 0.238 2.046 ngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/AR[1] SLICE_X116Y48 FDCE f ngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/jtag_command_reg[17]/CLR ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 1.073 1.348 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 0.980 2.358 ngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/clk_31_250_bufg SLICE_X116Y48 FDCE r ngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/jtag_command_reg[17]/C clock pessimism -0.383 1.975 SLICE_X116Y48 FDCE (Remov_fdce_C_CLR) -0.069 1.906 ngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/jtag_command_reg[17] ------------------------------------------------------------------- required time -1.906 arrival time 2.046 ------------------------------------------------------------------- slack 0.140 Slack (MET) : 0.140ns (arrival time - required time) Source: ngFEC/SFP_GEN[6].ngFEC_module/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0/C (rising edge-triggered cell FDPE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: ngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/jtag_command_reg[2]/CLR (removal check against rising-edge clock clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_ipb_ub rise@0.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 0.338ns (logic 0.100ns (29.577%) route 0.238ns (70.423%)) Logic Levels: 0 Clock Path Skew: 0.267ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.358ns Source Clock Delay (SCD): 1.708ns Clock Pessimism Removal (CPR): 0.383ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 1.004 1.017 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 0.665 1.708 ngFEC/SFP_GEN[6].ngFEC_module/clk_31_250_bufg SLICE_X119Y56 FDPE r ngFEC/SFP_GEN[6].ngFEC_module/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0/C ------------------------------------------------------------------- ------------------- SLICE_X119Y56 FDPE (Prop_fdpe_C_Q) 0.100 1.808 f ngFEC/SFP_GEN[6].ngFEC_module/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0/Q net (fo=96, routed) 0.238 2.046 ngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/AR[1] SLICE_X116Y48 FDCE f ngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/jtag_command_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 1.073 1.348 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 0.980 2.358 ngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/clk_31_250_bufg SLICE_X116Y48 FDCE r ngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/jtag_command_reg[2]/C clock pessimism -0.383 1.975 SLICE_X116Y48 FDCE (Remov_fdce_C_CLR) -0.069 1.906 ngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/jtag_command_reg[2] ------------------------------------------------------------------- required time -1.906 arrival time 2.046 ------------------------------------------------------------------- slack 0.140 Slack (MET) : 0.140ns (arrival time - required time) Source: ngFEC/SFP_GEN[6].ngFEC_module/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0/C (rising edge-triggered cell FDPE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: ngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/jtag_command_reg[4]/CLR (removal check against rising-edge clock clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_ipb_ub rise@0.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 0.338ns (logic 0.100ns (29.577%) route 0.238ns (70.423%)) Logic Levels: 0 Clock Path Skew: 0.267ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.358ns Source Clock Delay (SCD): 1.708ns Clock Pessimism Removal (CPR): 0.383ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 1.004 1.017 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 0.665 1.708 ngFEC/SFP_GEN[6].ngFEC_module/clk_31_250_bufg SLICE_X119Y56 FDPE r ngFEC/SFP_GEN[6].ngFEC_module/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0/C ------------------------------------------------------------------- ------------------- SLICE_X119Y56 FDPE (Prop_fdpe_C_Q) 0.100 1.808 f ngFEC/SFP_GEN[6].ngFEC_module/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0/Q net (fo=96, routed) 0.238 2.046 ngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/AR[1] SLICE_X116Y48 FDCE f ngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/jtag_command_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 1.073 1.348 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 0.980 2.358 ngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/clk_31_250_bufg SLICE_X116Y48 FDCE r ngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/jtag_command_reg[4]/C clock pessimism -0.383 1.975 SLICE_X116Y48 FDCE (Remov_fdce_C_CLR) -0.069 1.906 ngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/jtag_command_reg[4] ------------------------------------------------------------------- required time -1.906 arrival time 2.046 ------------------------------------------------------------------- slack 0.140 Slack (MET) : 0.140ns (arrival time - required time) Source: ngFEC/SFP_GEN[6].ngFEC_module/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0/C (rising edge-triggered cell FDPE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: ngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/jtag_command_reg[6]/CLR (removal check against rising-edge clock clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_ipb_ub rise@0.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 0.338ns (logic 0.100ns (29.577%) route 0.238ns (70.423%)) Logic Levels: 0 Clock Path Skew: 0.267ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.358ns Source Clock Delay (SCD): 1.708ns Clock Pessimism Removal (CPR): 0.383ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 1.004 1.017 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 0.665 1.708 ngFEC/SFP_GEN[6].ngFEC_module/clk_31_250_bufg SLICE_X119Y56 FDPE r ngFEC/SFP_GEN[6].ngFEC_module/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0/C ------------------------------------------------------------------- ------------------- SLICE_X119Y56 FDPE (Prop_fdpe_C_Q) 0.100 1.808 f ngFEC/SFP_GEN[6].ngFEC_module/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0/Q net (fo=96, routed) 0.238 2.046 ngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/AR[1] SLICE_X116Y48 FDCE f ngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/jtag_command_reg[6]/CLR ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 1.073 1.348 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 0.980 2.358 ngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/clk_31_250_bufg SLICE_X116Y48 FDCE r ngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/jtag_command_reg[6]/C clock pessimism -0.383 1.975 SLICE_X116Y48 FDCE (Remov_fdce_C_CLR) -0.069 1.906 ngFEC/SFP_GEN[6].ngFEC_module/buffer_ngccm_jtag/jtag_command_reg[6] ------------------------------------------------------------------- required time -1.906 arrival time 2.046 ------------------------------------------------------------------- slack 0.140 Slack (MET) : 0.165ns (arrival time - required time) Source: ngFEC/SFP_GEN[1].ngFEC_module/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0/C (rising edge-triggered cell FDPE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: ngFEC/SFP_GEN[1].ngFEC_module/bram_array[14].skip_SFP_SEC.buffer_server/server_wr_o_reg[0]/CLR (removal check against rising-edge clock clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_ipb_ub rise@0.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 0.333ns (logic 0.100ns (30.026%) route 0.233ns (69.974%)) Logic Levels: 0 Clock Path Skew: 0.218ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.186ns Source Clock Delay (SCD): 1.633ns Clock Pessimism Removal (CPR): 0.335ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 1.004 1.017 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 0.590 1.633 ngFEC/SFP_GEN[1].ngFEC_module/clk_31_250_bufg SLICE_X151Y206 FDPE r ngFEC/SFP_GEN[1].ngFEC_module/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0/C ------------------------------------------------------------------- ------------------- SLICE_X151Y206 FDPE (Prop_fdpe_C_Q) 0.100 1.733 f ngFEC/SFP_GEN[1].ngFEC_module/bram_array[14].skip_SFP_SEC.synch_reset_reg[14]_rep__0/Q net (fo=96, routed) 0.233 1.966 ngFEC/SFP_GEN[1].ngFEC_module/bram_array[14].skip_SFP_SEC.buffer_server/AR[0] SLICE_X150Y197 FDCE f ngFEC/SFP_GEN[1].ngFEC_module/bram_array[14].skip_SFP_SEC.buffer_server/server_wr_o_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 1.073 1.348 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 0.808 2.186 ngFEC/SFP_GEN[1].ngFEC_module/bram_array[14].skip_SFP_SEC.buffer_server/clk_31_250_bufg SLICE_X150Y197 FDCE r ngFEC/SFP_GEN[1].ngFEC_module/bram_array[14].skip_SFP_SEC.buffer_server/server_wr_o_reg[0]/C clock pessimism -0.335 1.851 SLICE_X150Y197 FDCE (Remov_fdce_C_CLR) -0.050 1.801 ngFEC/SFP_GEN[1].ngFEC_module/bram_array[14].skip_SFP_SEC.buffer_server/server_wr_o_reg[0] ------------------------------------------------------------------- required time -1.801 arrival time 1.966 ------------------------------------------------------------------- slack 0.165 Slack (MET) : 0.168ns (arrival time - required time) Source: ngFEC/SFP_GEN[2].ngFEC_module/bram_array[1].skip_SFP_SEC.synch_reset_reg[1]/C (rising edge-triggered cell FDPE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[25]/CLR (removal check against rising-edge clock clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_ipb_ub rise@0.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 0.313ns (logic 0.100ns (31.911%) route 0.213ns (68.089%)) Logic Levels: 0 Clock Path Skew: 0.214ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.123ns Source Clock Delay (SCD): 1.574ns Clock Pessimism Removal (CPR): 0.335ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 1.004 1.017 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 0.531 1.574 ngFEC/SFP_GEN[2].ngFEC_module/clk_31_250_bufg SLICE_X81Y200 FDPE r ngFEC/SFP_GEN[2].ngFEC_module/bram_array[1].skip_SFP_SEC.synch_reset_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X81Y200 FDPE (Prop_fdpe_C_Q) 0.100 1.674 f ngFEC/SFP_GEN[2].ngFEC_module/bram_array[1].skip_SFP_SEC.synch_reset_reg[1]/Q net (fo=167, routed) 0.213 1.887 ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/status_reg_reg[1]_0 SLICE_X85Y199 FDCE f ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[25]/CLR ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 1.073 1.348 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 0.745 2.123 ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/clk_31_250_bufg SLICE_X85Y199 FDCE r ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[25]/C clock pessimism -0.335 1.788 SLICE_X85Y199 FDCE (Remov_fdce_C_CLR) -0.069 1.719 ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[25] ------------------------------------------------------------------- required time -1.719 arrival time 1.887 ------------------------------------------------------------------- slack 0.168 Slack (MET) : 0.168ns (arrival time - required time) Source: ngFEC/SFP_GEN[2].ngFEC_module/bram_array[1].skip_SFP_SEC.synch_reset_reg[1]/C (rising edge-triggered cell FDPE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[28]/CLR (removal check against rising-edge clock clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_ipb_ub rise@0.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 0.313ns (logic 0.100ns (31.911%) route 0.213ns (68.089%)) Logic Levels: 0 Clock Path Skew: 0.214ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.123ns Source Clock Delay (SCD): 1.574ns Clock Pessimism Removal (CPR): 0.335ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 1.004 1.017 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 0.531 1.574 ngFEC/SFP_GEN[2].ngFEC_module/clk_31_250_bufg SLICE_X81Y200 FDPE r ngFEC/SFP_GEN[2].ngFEC_module/bram_array[1].skip_SFP_SEC.synch_reset_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X81Y200 FDPE (Prop_fdpe_C_Q) 0.100 1.674 f ngFEC/SFP_GEN[2].ngFEC_module/bram_array[1].skip_SFP_SEC.synch_reset_reg[1]/Q net (fo=167, routed) 0.213 1.887 ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/status_reg_reg[1]_0 SLICE_X85Y199 FDCE f ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[28]/CLR ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 1.073 1.348 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 0.745 2.123 ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/clk_31_250_bufg SLICE_X85Y199 FDCE r ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[28]/C clock pessimism -0.335 1.788 SLICE_X85Y199 FDCE (Remov_fdce_C_CLR) -0.069 1.719 ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[28] ------------------------------------------------------------------- required time -1.719 arrival time 1.887 ------------------------------------------------------------------- slack 0.168 Slack (MET) : 0.168ns (arrival time - required time) Source: ngFEC/SFP_GEN[2].ngFEC_module/bram_array[1].skip_SFP_SEC.synch_reset_reg[1]/C (rising edge-triggered cell FDPE clocked by clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Destination: ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[29]/CLR (removal check against rising-edge clock clk_ipb_ub {rise@0.000ns fall@16.000ns period=32.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (clk_ipb_ub rise@0.000ns - clk_ipb_ub rise@0.000ns) Data Path Delay: 0.313ns (logic 0.100ns (31.911%) route 0.213ns (68.089%)) Logic Levels: 0 Clock Path Skew: 0.214ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.123ns Source Clock Delay (SCD): 1.574ns Clock Pessimism Removal (CPR): 0.335ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.441 0.441 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.575 1.017 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/osc125a_clkbuf/O net (fo=11, routed) 0.750 1.793 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -1.780 0.013 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 1.004 1.017 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.026 1.043 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 0.531 1.574 ngFEC/SFP_GEN[2].ngFEC_module/clk_31_250_bufg SLICE_X81Y200 FDPE r ngFEC/SFP_GEN[2].ngFEC_module/bram_array[1].skip_SFP_SEC.synch_reset_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X81Y200 FDPE (Prop_fdpe_C_Q) 0.100 1.674 f ngFEC/SFP_GEN[2].ngFEC_module/bram_array[1].skip_SFP_SEC.synch_reset_reg[1]/Q net (fo=167, routed) 0.213 1.887 ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/status_reg_reg[1]_0 SLICE_X85Y199 FDCE f ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[29]/CLR ------------------------------------------------------------------- ------------------- (clock clk_ipb_ub rise edge) 0.000 0.000 r AD6 0.000 0.000 r osc125_a_p (IN) net (fo=0) 0.000 0.000 osc125_a_p AD6 IBUF (Prop_ibuf_I_O) 0.000 0.000 r osc125_a_p_IBUF_inst/O net (fo=1, routed) 0.000 0.000 sys/osc125_a_p_IBUF IBUFDS_GTE2_X0Y5 IBUFDS_GTE2 (Prop_ibufds_gte2_I_O) 0.732 0.732 r sys/osc125a_gtebuf/O net (fo=2, routed) 0.615 1.348 sys/osc125a_gtebuf_n_0 BUFGCTRL_X0Y8 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/osc125a_clkbuf/O net (fo=11, routed) 1.003 2.381 sys/clocks/gtrefclk_bufg PLLE2_ADV_X0Y1 PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0) -2.106 0.275 r sys/clocks/PLLE2_BASE_inst/CLKOUT0 net (fo=1, routed) 1.073 1.348 sys/clocks/clk_ipb_ub BUFGCTRL_X0Y9 BUFG (Prop_bufg_I_O) 0.030 1.378 r sys/clocks/clk_ipb_buf/O net (fo=82108, routed) 0.745 2.123 ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/clk_31_250_bufg SLICE_X85Y199 FDCE r ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[29]/C clock pessimism -0.335 1.788 SLICE_X85Y199 FDCE (Remov_fdce_C_CLR) -0.069 1.719 ngFEC/SFP_GEN[2].ngFEC_module/i2c_comm_gen[1].buffer_ngccm/sleep_cyc_reg[29] ------------------------------------------------------------------- required time -1.719 arrival time 1.887 ------------------------------------------------------------------- slack 0.168 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: fabric_clk_FBOUT To Clock: fabric_clk_FBOUT Setup : 0 Failing Endpoints, Worst Slack 16.982ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.227ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 16.982ns (required time - arrival time) Source: ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/C (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[25]/PRE (recovery check against rising-edge clock fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 24.951ns (fabric_clk_FBOUT rise@24.951ns - fabric_clk_FBOUT rise@0.000ns) Data Path Delay: 7.731ns (logic 0.360ns (4.657%) route 7.371ns (95.343%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.021ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.255ns = ( 26.206 - 24.951 ) Source Clock Delay (SCD): 1.331ns Clock Pessimism Removal (CPR): 0.097ns Clock Uncertainty: 0.081ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.146ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.802 0.802 r ngFEC/fclk_ibuf/O net (fo=1, routed) 1.081 1.883 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -4.638 -2.755 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 2.546 -0.209 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -0.116 r ngFEC/fclk_bufg/O net (fo=39427, routed) 1.447 1.331 ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/CLKFBIN SLICE_X50Y123 FDRE r ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/C ------------------------------------------------------------------- ------------------- SLICE_X50Y123 FDRE (Prop_fdre_C_Q) 0.236 1.567 f ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/Q net (fo=67, routed) 2.617 4.185 ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset_n_4 SLICE_X104Y179 LUT2 (Prop_lut2_I0_O) 0.124 4.309 f ngFEC/SFP_GEN[12].ngCCM_gbt/FSM_sequential_StateJTAGTDO[1]_i_2/O net (fo=159, routed) 4.753 9.062 ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/jtag_reset_local[0] SLICE_X32Y132 FDPE f ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[25]/PRE ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 24.951 24.951 r AK18 0.000 24.951 r fabric_clk_p (IN) net (fo=0) 0.000 24.951 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.725 25.676 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.986 26.662 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -4.330 22.332 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 2.411 24.743 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 24.826 r ngFEC/fclk_bufg/O net (fo=39427, routed) 1.380 26.206 ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/CLKFBIN SLICE_X32Y132 FDPE r ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[25]/C clock pessimism 0.097 26.303 clock uncertainty -0.081 26.223 SLICE_X32Y132 FDPE (Recov_fdpe_C_PRE) -0.178 26.045 ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[25] ------------------------------------------------------------------- required time 26.045 arrival time -9.062 ------------------------------------------------------------------- slack 16.982 Slack (MET) : 16.982ns (required time - arrival time) Source: ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/C (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[26]/PRE (recovery check against rising-edge clock fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 24.951ns (fabric_clk_FBOUT rise@24.951ns - fabric_clk_FBOUT rise@0.000ns) Data Path Delay: 7.731ns (logic 0.360ns (4.657%) route 7.371ns (95.343%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.021ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.255ns = ( 26.206 - 24.951 ) Source Clock Delay (SCD): 1.331ns Clock Pessimism Removal (CPR): 0.097ns Clock Uncertainty: 0.081ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.146ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.802 0.802 r ngFEC/fclk_ibuf/O net (fo=1, routed) 1.081 1.883 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -4.638 -2.755 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 2.546 -0.209 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -0.116 r ngFEC/fclk_bufg/O net (fo=39427, routed) 1.447 1.331 ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/CLKFBIN SLICE_X50Y123 FDRE r ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/C ------------------------------------------------------------------- ------------------- SLICE_X50Y123 FDRE (Prop_fdre_C_Q) 0.236 1.567 f ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/Q net (fo=67, routed) 2.617 4.185 ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset_n_4 SLICE_X104Y179 LUT2 (Prop_lut2_I0_O) 0.124 4.309 f ngFEC/SFP_GEN[12].ngCCM_gbt/FSM_sequential_StateJTAGTDO[1]_i_2/O net (fo=159, routed) 4.753 9.062 ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/jtag_reset_local[0] SLICE_X32Y132 FDPE f ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[26]/PRE ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 24.951 24.951 r AK18 0.000 24.951 r fabric_clk_p (IN) net (fo=0) 0.000 24.951 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.725 25.676 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.986 26.662 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -4.330 22.332 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 2.411 24.743 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 24.826 r ngFEC/fclk_bufg/O net (fo=39427, routed) 1.380 26.206 ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/CLKFBIN SLICE_X32Y132 FDPE r ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[26]/C clock pessimism 0.097 26.303 clock uncertainty -0.081 26.223 SLICE_X32Y132 FDPE (Recov_fdpe_C_PRE) -0.178 26.045 ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[26] ------------------------------------------------------------------- required time 26.045 arrival time -9.062 ------------------------------------------------------------------- slack 16.982 Slack (MET) : 16.982ns (required time - arrival time) Source: ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/C (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[27]/PRE (recovery check against rising-edge clock fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 24.951ns (fabric_clk_FBOUT rise@24.951ns - fabric_clk_FBOUT rise@0.000ns) Data Path Delay: 7.731ns (logic 0.360ns (4.657%) route 7.371ns (95.343%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.021ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.255ns = ( 26.206 - 24.951 ) Source Clock Delay (SCD): 1.331ns Clock Pessimism Removal (CPR): 0.097ns Clock Uncertainty: 0.081ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.146ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.802 0.802 r ngFEC/fclk_ibuf/O net (fo=1, routed) 1.081 1.883 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -4.638 -2.755 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 2.546 -0.209 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -0.116 r ngFEC/fclk_bufg/O net (fo=39427, routed) 1.447 1.331 ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/CLKFBIN SLICE_X50Y123 FDRE r ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/C ------------------------------------------------------------------- ------------------- SLICE_X50Y123 FDRE (Prop_fdre_C_Q) 0.236 1.567 f ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/Q net (fo=67, routed) 2.617 4.185 ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset_n_4 SLICE_X104Y179 LUT2 (Prop_lut2_I0_O) 0.124 4.309 f ngFEC/SFP_GEN[12].ngCCM_gbt/FSM_sequential_StateJTAGTDO[1]_i_2/O net (fo=159, routed) 4.753 9.062 ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/jtag_reset_local[0] SLICE_X32Y132 FDPE f ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[27]/PRE ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 24.951 24.951 r AK18 0.000 24.951 r fabric_clk_p (IN) net (fo=0) 0.000 24.951 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.725 25.676 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.986 26.662 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -4.330 22.332 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 2.411 24.743 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 24.826 r ngFEC/fclk_bufg/O net (fo=39427, routed) 1.380 26.206 ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/CLKFBIN SLICE_X32Y132 FDPE r ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[27]/C clock pessimism 0.097 26.303 clock uncertainty -0.081 26.223 SLICE_X32Y132 FDPE (Recov_fdpe_C_PRE) -0.178 26.045 ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[27] ------------------------------------------------------------------- required time 26.045 arrival time -9.062 ------------------------------------------------------------------- slack 16.982 Slack (MET) : 17.001ns (required time - arrival time) Source: ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/C (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[29]/PRE (recovery check against rising-edge clock fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 24.951ns (fabric_clk_FBOUT rise@24.951ns - fabric_clk_FBOUT rise@0.000ns) Data Path Delay: 7.713ns (logic 0.360ns (4.668%) route 7.353ns (95.332%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.256ns = ( 26.207 - 24.951 ) Source Clock Delay (SCD): 1.331ns Clock Pessimism Removal (CPR): 0.097ns Clock Uncertainty: 0.081ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.146ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.802 0.802 r ngFEC/fclk_ibuf/O net (fo=1, routed) 1.081 1.883 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -4.638 -2.755 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 2.546 -0.209 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -0.116 r ngFEC/fclk_bufg/O net (fo=39427, routed) 1.447 1.331 ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/CLKFBIN SLICE_X50Y123 FDRE r ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/C ------------------------------------------------------------------- ------------------- SLICE_X50Y123 FDRE (Prop_fdre_C_Q) 0.236 1.567 f ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/Q net (fo=67, routed) 2.617 4.185 ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset_n_4 SLICE_X104Y179 LUT2 (Prop_lut2_I0_O) 0.124 4.309 f ngFEC/SFP_GEN[12].ngCCM_gbt/FSM_sequential_StateJTAGTDO[1]_i_2/O net (fo=159, routed) 4.735 9.044 ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/jtag_reset_local[0] SLICE_X32Y133 FDPE f ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[29]/PRE ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 24.951 24.951 r AK18 0.000 24.951 r fabric_clk_p (IN) net (fo=0) 0.000 24.951 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.725 25.676 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.986 26.662 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -4.330 22.332 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 2.411 24.743 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 24.826 r ngFEC/fclk_bufg/O net (fo=39427, routed) 1.381 26.207 ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/CLKFBIN SLICE_X32Y133 FDPE r ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[29]/C clock pessimism 0.097 26.304 clock uncertainty -0.081 26.224 SLICE_X32Y133 FDPE (Recov_fdpe_C_PRE) -0.178 26.046 ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[29] ------------------------------------------------------------------- required time 26.046 arrival time -9.044 ------------------------------------------------------------------- slack 17.001 Slack (MET) : 17.001ns (required time - arrival time) Source: ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/C (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[30]/PRE (recovery check against rising-edge clock fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 24.951ns (fabric_clk_FBOUT rise@24.951ns - fabric_clk_FBOUT rise@0.000ns) Data Path Delay: 7.713ns (logic 0.360ns (4.668%) route 7.353ns (95.332%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.256ns = ( 26.207 - 24.951 ) Source Clock Delay (SCD): 1.331ns Clock Pessimism Removal (CPR): 0.097ns Clock Uncertainty: 0.081ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.146ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.802 0.802 r ngFEC/fclk_ibuf/O net (fo=1, routed) 1.081 1.883 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -4.638 -2.755 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 2.546 -0.209 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -0.116 r ngFEC/fclk_bufg/O net (fo=39427, routed) 1.447 1.331 ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/CLKFBIN SLICE_X50Y123 FDRE r ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/C ------------------------------------------------------------------- ------------------- SLICE_X50Y123 FDRE (Prop_fdre_C_Q) 0.236 1.567 f ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/Q net (fo=67, routed) 2.617 4.185 ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset_n_4 SLICE_X104Y179 LUT2 (Prop_lut2_I0_O) 0.124 4.309 f ngFEC/SFP_GEN[12].ngCCM_gbt/FSM_sequential_StateJTAGTDO[1]_i_2/O net (fo=159, routed) 4.735 9.044 ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/jtag_reset_local[0] SLICE_X32Y133 FDPE f ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[30]/PRE ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 24.951 24.951 r AK18 0.000 24.951 r fabric_clk_p (IN) net (fo=0) 0.000 24.951 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.725 25.676 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.986 26.662 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -4.330 22.332 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 2.411 24.743 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 24.826 r ngFEC/fclk_bufg/O net (fo=39427, routed) 1.381 26.207 ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/CLKFBIN SLICE_X32Y133 FDPE r ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[30]/C clock pessimism 0.097 26.304 clock uncertainty -0.081 26.224 SLICE_X32Y133 FDPE (Recov_fdpe_C_PRE) -0.178 26.046 ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[30] ------------------------------------------------------------------- required time 26.046 arrival time -9.044 ------------------------------------------------------------------- slack 17.001 Slack (MET) : 17.001ns (required time - arrival time) Source: ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/C (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[31]/PRE (recovery check against rising-edge clock fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 24.951ns (fabric_clk_FBOUT rise@24.951ns - fabric_clk_FBOUT rise@0.000ns) Data Path Delay: 7.713ns (logic 0.360ns (4.668%) route 7.353ns (95.332%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.022ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.256ns = ( 26.207 - 24.951 ) Source Clock Delay (SCD): 1.331ns Clock Pessimism Removal (CPR): 0.097ns Clock Uncertainty: 0.081ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.146ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.802 0.802 r ngFEC/fclk_ibuf/O net (fo=1, routed) 1.081 1.883 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -4.638 -2.755 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 2.546 -0.209 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -0.116 r ngFEC/fclk_bufg/O net (fo=39427, routed) 1.447 1.331 ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/CLKFBIN SLICE_X50Y123 FDRE r ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/C ------------------------------------------------------------------- ------------------- SLICE_X50Y123 FDRE (Prop_fdre_C_Q) 0.236 1.567 f ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/Q net (fo=67, routed) 2.617 4.185 ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset_n_4 SLICE_X104Y179 LUT2 (Prop_lut2_I0_O) 0.124 4.309 f ngFEC/SFP_GEN[12].ngCCM_gbt/FSM_sequential_StateJTAGTDO[1]_i_2/O net (fo=159, routed) 4.735 9.044 ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/jtag_reset_local[0] SLICE_X32Y133 FDPE f ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[31]/PRE ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 24.951 24.951 r AK18 0.000 24.951 r fabric_clk_p (IN) net (fo=0) 0.000 24.951 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.725 25.676 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.986 26.662 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -4.330 22.332 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 2.411 24.743 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 24.826 r ngFEC/fclk_bufg/O net (fo=39427, routed) 1.381 26.207 ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/CLKFBIN SLICE_X32Y133 FDPE r ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[31]/C clock pessimism 0.097 26.304 clock uncertainty -0.081 26.224 SLICE_X32Y133 FDPE (Recov_fdpe_C_PRE) -0.178 26.046 ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/SleepCount_reg[31] ------------------------------------------------------------------- required time 26.046 arrival time -9.044 ------------------------------------------------------------------- slack 17.001 Slack (MET) : 17.041ns (required time - arrival time) Source: ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/C (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/ClkDiv_o_reg[1]/CLR (recovery check against rising-edge clock fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 24.951ns (fabric_clk_FBOUT rise@24.951ns - fabric_clk_FBOUT rise@0.000ns) Data Path Delay: 7.635ns (logic 0.360ns (4.715%) route 7.275ns (95.285%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.018ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.252ns = ( 26.203 - 24.951 ) Source Clock Delay (SCD): 1.331ns Clock Pessimism Removal (CPR): 0.097ns Clock Uncertainty: 0.081ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.146ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.802 0.802 r ngFEC/fclk_ibuf/O net (fo=1, routed) 1.081 1.883 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -4.638 -2.755 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 2.546 -0.209 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -0.116 r ngFEC/fclk_bufg/O net (fo=39427, routed) 1.447 1.331 ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/CLKFBIN SLICE_X50Y123 FDRE r ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/C ------------------------------------------------------------------- ------------------- SLICE_X50Y123 FDRE (Prop_fdre_C_Q) 0.236 1.567 f ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/Q net (fo=67, routed) 2.617 4.185 ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset_n_4 SLICE_X104Y179 LUT2 (Prop_lut2_I0_O) 0.124 4.309 f ngFEC/SFP_GEN[12].ngCCM_gbt/FSM_sequential_StateJTAGTDO[1]_i_2/O net (fo=159, routed) 4.658 8.967 ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/jtag_reset_local[0] SLICE_X37Y131 FDCE f ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/ClkDiv_o_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 24.951 24.951 r AK18 0.000 24.951 r fabric_clk_p (IN) net (fo=0) 0.000 24.951 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.725 25.676 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.986 26.662 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -4.330 22.332 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 2.411 24.743 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 24.826 r ngFEC/fclk_bufg/O net (fo=39427, routed) 1.377 26.203 ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/CLKFBIN SLICE_X37Y131 FDCE r ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/ClkDiv_o_reg[1]/C clock pessimism 0.097 26.300 clock uncertainty -0.081 26.220 SLICE_X37Y131 FDCE (Recov_fdce_C_CLR) -0.212 26.008 ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/ClkDiv_o_reg[1] ------------------------------------------------------------------- required time 26.008 arrival time -8.967 ------------------------------------------------------------------- slack 17.041 Slack (MET) : 17.041ns (required time - arrival time) Source: ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/C (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/ClkDiv_o_reg[2]/CLR (recovery check against rising-edge clock fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 24.951ns (fabric_clk_FBOUT rise@24.951ns - fabric_clk_FBOUT rise@0.000ns) Data Path Delay: 7.635ns (logic 0.360ns (4.715%) route 7.275ns (95.285%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.018ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.252ns = ( 26.203 - 24.951 ) Source Clock Delay (SCD): 1.331ns Clock Pessimism Removal (CPR): 0.097ns Clock Uncertainty: 0.081ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.146ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.802 0.802 r ngFEC/fclk_ibuf/O net (fo=1, routed) 1.081 1.883 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -4.638 -2.755 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 2.546 -0.209 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -0.116 r ngFEC/fclk_bufg/O net (fo=39427, routed) 1.447 1.331 ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/CLKFBIN SLICE_X50Y123 FDRE r ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/C ------------------------------------------------------------------- ------------------- SLICE_X50Y123 FDRE (Prop_fdre_C_Q) 0.236 1.567 f ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/Q net (fo=67, routed) 2.617 4.185 ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset_n_4 SLICE_X104Y179 LUT2 (Prop_lut2_I0_O) 0.124 4.309 f ngFEC/SFP_GEN[12].ngCCM_gbt/FSM_sequential_StateJTAGTDO[1]_i_2/O net (fo=159, routed) 4.658 8.967 ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/jtag_reset_local[0] SLICE_X37Y131 FDCE f ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/ClkDiv_o_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 24.951 24.951 r AK18 0.000 24.951 r fabric_clk_p (IN) net (fo=0) 0.000 24.951 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.725 25.676 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.986 26.662 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -4.330 22.332 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 2.411 24.743 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 24.826 r ngFEC/fclk_bufg/O net (fo=39427, routed) 1.377 26.203 ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/CLKFBIN SLICE_X37Y131 FDCE r ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/ClkDiv_o_reg[2]/C clock pessimism 0.097 26.300 clock uncertainty -0.081 26.220 SLICE_X37Y131 FDCE (Recov_fdce_C_CLR) -0.212 26.008 ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/ClkDiv_o_reg[2] ------------------------------------------------------------------- required time 26.008 arrival time -8.967 ------------------------------------------------------------------- slack 17.041 Slack (MET) : 17.041ns (required time - arrival time) Source: ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/C (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/ClkDiv_o_reg[3]/CLR (recovery check against rising-edge clock fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 24.951ns (fabric_clk_FBOUT rise@24.951ns - fabric_clk_FBOUT rise@0.000ns) Data Path Delay: 7.635ns (logic 0.360ns (4.715%) route 7.275ns (95.285%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.018ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.252ns = ( 26.203 - 24.951 ) Source Clock Delay (SCD): 1.331ns Clock Pessimism Removal (CPR): 0.097ns Clock Uncertainty: 0.081ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.146ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.802 0.802 r ngFEC/fclk_ibuf/O net (fo=1, routed) 1.081 1.883 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -4.638 -2.755 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 2.546 -0.209 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -0.116 r ngFEC/fclk_bufg/O net (fo=39427, routed) 1.447 1.331 ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/CLKFBIN SLICE_X50Y123 FDRE r ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/C ------------------------------------------------------------------- ------------------- SLICE_X50Y123 FDRE (Prop_fdre_C_Q) 0.236 1.567 f ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/Q net (fo=67, routed) 2.617 4.185 ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset_n_4 SLICE_X104Y179 LUT2 (Prop_lut2_I0_O) 0.124 4.309 f ngFEC/SFP_GEN[12].ngCCM_gbt/FSM_sequential_StateJTAGTDO[1]_i_2/O net (fo=159, routed) 4.658 8.967 ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/jtag_reset_local[0] SLICE_X37Y131 FDCE f ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/ClkDiv_o_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 24.951 24.951 r AK18 0.000 24.951 r fabric_clk_p (IN) net (fo=0) 0.000 24.951 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.725 25.676 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.986 26.662 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -4.330 22.332 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 2.411 24.743 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 24.826 r ngFEC/fclk_bufg/O net (fo=39427, routed) 1.377 26.203 ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/CLKFBIN SLICE_X37Y131 FDCE r ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/ClkDiv_o_reg[3]/C clock pessimism 0.097 26.300 clock uncertainty -0.081 26.220 SLICE_X37Y131 FDCE (Recov_fdce_C_CLR) -0.212 26.008 ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/ClkDiv_o_reg[3] ------------------------------------------------------------------- required time 26.008 arrival time -8.967 ------------------------------------------------------------------- slack 17.041 Slack (MET) : 17.041ns (required time - arrival time) Source: ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/C (rising edge-triggered cell FDRE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/Count_o_reg[12]/CLR (recovery check against rising-edge clock fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 24.951ns (fabric_clk_FBOUT rise@24.951ns - fabric_clk_FBOUT rise@0.000ns) Data Path Delay: 7.635ns (logic 0.360ns (4.715%) route 7.275ns (95.285%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.018ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.252ns = ( 26.203 - 24.951 ) Source Clock Delay (SCD): 1.331ns Clock Pessimism Removal (CPR): 0.097ns Clock Uncertainty: 0.081ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.071ns Discrete Jitter (DJ): 0.146ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.802 0.802 r ngFEC/fclk_ibuf/O net (fo=1, routed) 1.081 1.883 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -4.638 -2.755 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 2.546 -0.209 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.093 -0.116 r ngFEC/fclk_bufg/O net (fo=39427, routed) 1.447 1.331 ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/CLKFBIN SLICE_X50Y123 FDRE r ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/C ------------------------------------------------------------------- ------------------- SLICE_X50Y123 FDRE (Prop_fdre_C_Q) 0.236 1.567 f ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset/sync_o_reg_rep__2/Q net (fo=67, routed) 2.617 4.185 ngFEC/SFP_GEN[12].ngCCM_gbt/Sync_TX_Reset_n_4 SLICE_X104Y179 LUT2 (Prop_lut2_I0_O) 0.124 4.309 f ngFEC/SFP_GEN[12].ngCCM_gbt/FSM_sequential_StateJTAGTDO[1]_i_2/O net (fo=159, routed) 4.658 8.967 ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/jtag_reset_local[0] SLICE_X37Y131 FDCE f ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/Count_o_reg[12]/CLR ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 24.951 24.951 r AK18 0.000 24.951 r fabric_clk_p (IN) net (fo=0) 0.000 24.951 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.725 25.676 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.986 26.662 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -4.330 22.332 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 2.411 24.743 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.083 24.826 r ngFEC/fclk_bufg/O net (fo=39427, routed) 1.377 26.203 ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/CLKFBIN SLICE_X37Y131 FDCE r ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/Count_o_reg[12]/C clock pessimism 0.097 26.300 clock uncertainty -0.081 26.220 SLICE_X37Y131 FDCE (Recov_fdce_C_CLR) -0.212 26.008 ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/Count_o_reg[12] ------------------------------------------------------------------- required time 26.008 arrival time -8.967 ------------------------------------------------------------------- slack 17.041 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.227ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[2]/CLR (removal check against rising-edge clock fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_FBOUT rise@0.000ns - fabric_clk_FBOUT rise@0.000ns) Data Path Delay: 0.211ns (logic 0.100ns (47.367%) route 0.111ns (52.633%)) Logic Levels: 0 Clock Path Skew: 0.034ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.908ns Source Clock Delay (SCD): 0.830ns Clock Pessimism Removal (CPR): 0.044ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.426 0.426 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.503 0.929 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -1.995 -1.066 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 1.173 0.107 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.133 r ngFEC/fclk_bufg/O net (fo=39427, routed) 0.697 0.830 ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLKFBIN SLICE_X177Y282 FDPE r ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X177Y282 FDPE (Prop_fdpe_C_Q) 0.100 0.930 f ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/Q net (fo=24, routed) 0.111 1.041 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/mgt_rxreset_s[3] SLICE_X178Y282 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.499 0.499 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.553 1.052 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -2.340 -1.288 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 1.242 -0.046 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -0.016 r ngFEC/fclk_bufg/O net (fo=39427, routed) 0.924 0.908 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/CLKFBIN SLICE_X178Y282 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[2]/C clock pessimism -0.044 0.864 SLICE_X178Y282 FDCE (Remov_fdce_C_CLR) -0.050 0.814 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[2] ------------------------------------------------------------------- required time -0.814 arrival time 1.041 ------------------------------------------------------------------- slack 0.227 Slack (MET) : 0.227ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[3]/CLR (removal check against rising-edge clock fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_FBOUT rise@0.000ns - fabric_clk_FBOUT rise@0.000ns) Data Path Delay: 0.211ns (logic 0.100ns (47.367%) route 0.111ns (52.633%)) Logic Levels: 0 Clock Path Skew: 0.034ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.908ns Source Clock Delay (SCD): 0.830ns Clock Pessimism Removal (CPR): 0.044ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.426 0.426 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.503 0.929 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -1.995 -1.066 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 1.173 0.107 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.133 r ngFEC/fclk_bufg/O net (fo=39427, routed) 0.697 0.830 ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLKFBIN SLICE_X177Y282 FDPE r ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X177Y282 FDPE (Prop_fdpe_C_Q) 0.100 0.930 f ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/Q net (fo=24, routed) 0.111 1.041 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/mgt_rxreset_s[3] SLICE_X178Y282 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.499 0.499 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.553 1.052 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -2.340 -1.288 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 1.242 -0.046 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -0.016 r ngFEC/fclk_bufg/O net (fo=39427, routed) 0.924 0.908 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/CLKFBIN SLICE_X178Y282 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[3]/C clock pessimism -0.044 0.864 SLICE_X178Y282 FDCE (Remov_fdce_C_CLR) -0.050 0.814 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[3] ------------------------------------------------------------------- required time -0.814 arrival time 1.041 ------------------------------------------------------------------- slack 0.227 Slack (MET) : 0.227ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[4]/CLR (removal check against rising-edge clock fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_FBOUT rise@0.000ns - fabric_clk_FBOUT rise@0.000ns) Data Path Delay: 0.211ns (logic 0.100ns (47.367%) route 0.111ns (52.633%)) Logic Levels: 0 Clock Path Skew: 0.034ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.908ns Source Clock Delay (SCD): 0.830ns Clock Pessimism Removal (CPR): 0.044ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.426 0.426 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.503 0.929 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -1.995 -1.066 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 1.173 0.107 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.133 r ngFEC/fclk_bufg/O net (fo=39427, routed) 0.697 0.830 ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLKFBIN SLICE_X177Y282 FDPE r ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X177Y282 FDPE (Prop_fdpe_C_Q) 0.100 0.930 f ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/Q net (fo=24, routed) 0.111 1.041 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/mgt_rxreset_s[3] SLICE_X178Y282 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.499 0.499 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.553 1.052 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -2.340 -1.288 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 1.242 -0.046 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -0.016 r ngFEC/fclk_bufg/O net (fo=39427, routed) 0.924 0.908 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/CLKFBIN SLICE_X178Y282 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[4]/C clock pessimism -0.044 0.864 SLICE_X178Y282 FDCE (Remov_fdce_C_CLR) -0.050 0.814 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[4] ------------------------------------------------------------------- required time -0.814 arrival time 1.041 ------------------------------------------------------------------- slack 0.227 Slack (MET) : 0.227ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[5]/CLR (removal check against rising-edge clock fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_FBOUT rise@0.000ns - fabric_clk_FBOUT rise@0.000ns) Data Path Delay: 0.211ns (logic 0.100ns (47.367%) route 0.111ns (52.633%)) Logic Levels: 0 Clock Path Skew: 0.034ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.908ns Source Clock Delay (SCD): 0.830ns Clock Pessimism Removal (CPR): 0.044ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.426 0.426 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.503 0.929 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -1.995 -1.066 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 1.173 0.107 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.133 r ngFEC/fclk_bufg/O net (fo=39427, routed) 0.697 0.830 ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLKFBIN SLICE_X177Y282 FDPE r ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X177Y282 FDPE (Prop_fdpe_C_Q) 0.100 0.930 f ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/Q net (fo=24, routed) 0.111 1.041 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/mgt_rxreset_s[3] SLICE_X178Y282 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.499 0.499 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.553 1.052 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -2.340 -1.288 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 1.242 -0.046 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -0.016 r ngFEC/fclk_bufg/O net (fo=39427, routed) 0.924 0.908 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/CLKFBIN SLICE_X178Y282 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[5]/C clock pessimism -0.044 0.864 SLICE_X178Y282 FDCE (Remov_fdce_C_CLR) -0.050 0.814 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[5] ------------------------------------------------------------------- required time -0.814 arrival time 1.041 ------------------------------------------------------------------- slack 0.227 Slack (MET) : 0.246ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[0]/CLR (removal check against rising-edge clock fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_FBOUT rise@0.000ns - fabric_clk_FBOUT rise@0.000ns) Data Path Delay: 0.211ns (logic 0.100ns (47.367%) route 0.111ns (52.633%)) Logic Levels: 0 Clock Path Skew: 0.034ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.908ns Source Clock Delay (SCD): 0.830ns Clock Pessimism Removal (CPR): 0.044ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.426 0.426 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.503 0.929 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -1.995 -1.066 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 1.173 0.107 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.133 r ngFEC/fclk_bufg/O net (fo=39427, routed) 0.697 0.830 ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLKFBIN SLICE_X177Y282 FDPE r ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X177Y282 FDPE (Prop_fdpe_C_Q) 0.100 0.930 f ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/Q net (fo=24, routed) 0.111 1.041 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/mgt_rxreset_s[3] SLICE_X179Y282 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.499 0.499 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.553 1.052 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -2.340 -1.288 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 1.242 -0.046 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -0.016 r ngFEC/fclk_bufg/O net (fo=39427, routed) 0.924 0.908 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/CLKFBIN SLICE_X179Y282 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[0]/C clock pessimism -0.044 0.864 SLICE_X179Y282 FDCE (Remov_fdce_C_CLR) -0.069 0.795 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[0] ------------------------------------------------------------------- required time -0.795 arrival time 1.041 ------------------------------------------------------------------- slack 0.246 Slack (MET) : 0.246ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[1]/CLR (removal check against rising-edge clock fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_FBOUT rise@0.000ns - fabric_clk_FBOUT rise@0.000ns) Data Path Delay: 0.211ns (logic 0.100ns (47.367%) route 0.111ns (52.633%)) Logic Levels: 0 Clock Path Skew: 0.034ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.908ns Source Clock Delay (SCD): 0.830ns Clock Pessimism Removal (CPR): 0.044ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.426 0.426 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.503 0.929 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -1.995 -1.066 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 1.173 0.107 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.133 r ngFEC/fclk_bufg/O net (fo=39427, routed) 0.697 0.830 ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLKFBIN SLICE_X177Y282 FDPE r ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X177Y282 FDPE (Prop_fdpe_C_Q) 0.100 0.930 f ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/Q net (fo=24, routed) 0.111 1.041 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/mgt_rxreset_s[3] SLICE_X179Y282 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.499 0.499 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.553 1.052 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -2.340 -1.288 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 1.242 -0.046 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -0.016 r ngFEC/fclk_bufg/O net (fo=39427, routed) 0.924 0.908 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/CLKFBIN SLICE_X179Y282 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[1]/C clock pessimism -0.044 0.864 SLICE_X179Y282 FDCE (Remov_fdce_C_CLR) -0.069 0.795 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[1] ------------------------------------------------------------------- required time -0.795 arrival time 1.041 ------------------------------------------------------------------- slack 0.246 Slack (MET) : 0.274ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[12]/CLR (removal check against rising-edge clock fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_FBOUT rise@0.000ns - fabric_clk_FBOUT rise@0.000ns) Data Path Delay: 0.259ns (logic 0.100ns (38.673%) route 0.159ns (61.327%)) Logic Levels: 0 Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.909ns Source Clock Delay (SCD): 0.830ns Clock Pessimism Removal (CPR): 0.044ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.426 0.426 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.503 0.929 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -1.995 -1.066 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 1.173 0.107 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.133 r ngFEC/fclk_bufg/O net (fo=39427, routed) 0.697 0.830 ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLKFBIN SLICE_X177Y282 FDPE r ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X177Y282 FDPE (Prop_fdpe_C_Q) 0.100 0.930 f ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/Q net (fo=24, routed) 0.159 1.089 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/mgt_rxreset_s[3] SLICE_X178Y283 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[12]/CLR ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.499 0.499 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.553 1.052 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -2.340 -1.288 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 1.242 -0.046 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -0.016 r ngFEC/fclk_bufg/O net (fo=39427, routed) 0.925 0.909 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/CLKFBIN SLICE_X178Y283 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[12]/C clock pessimism -0.044 0.865 SLICE_X178Y283 FDCE (Remov_fdce_C_CLR) -0.050 0.815 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[12] ------------------------------------------------------------------- required time -0.815 arrival time 1.089 ------------------------------------------------------------------- slack 0.274 Slack (MET) : 0.274ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[6]/CLR (removal check against rising-edge clock fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_FBOUT rise@0.000ns - fabric_clk_FBOUT rise@0.000ns) Data Path Delay: 0.259ns (logic 0.100ns (38.673%) route 0.159ns (61.327%)) Logic Levels: 0 Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.909ns Source Clock Delay (SCD): 0.830ns Clock Pessimism Removal (CPR): 0.044ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.426 0.426 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.503 0.929 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -1.995 -1.066 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 1.173 0.107 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.133 r ngFEC/fclk_bufg/O net (fo=39427, routed) 0.697 0.830 ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLKFBIN SLICE_X177Y282 FDPE r ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X177Y282 FDPE (Prop_fdpe_C_Q) 0.100 0.930 f ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/Q net (fo=24, routed) 0.159 1.089 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/mgt_rxreset_s[3] SLICE_X178Y283 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[6]/CLR ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.499 0.499 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.553 1.052 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -2.340 -1.288 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 1.242 -0.046 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -0.016 r ngFEC/fclk_bufg/O net (fo=39427, routed) 0.925 0.909 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/CLKFBIN SLICE_X178Y283 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[6]/C clock pessimism -0.044 0.865 SLICE_X178Y283 FDCE (Remov_fdce_C_CLR) -0.050 0.815 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[6] ------------------------------------------------------------------- required time -0.815 arrival time 1.089 ------------------------------------------------------------------- slack 0.274 Slack (MET) : 0.274ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[7]/CLR (removal check against rising-edge clock fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_FBOUT rise@0.000ns - fabric_clk_FBOUT rise@0.000ns) Data Path Delay: 0.259ns (logic 0.100ns (38.673%) route 0.159ns (61.327%)) Logic Levels: 0 Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.909ns Source Clock Delay (SCD): 0.830ns Clock Pessimism Removal (CPR): 0.044ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.426 0.426 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.503 0.929 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -1.995 -1.066 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 1.173 0.107 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.133 r ngFEC/fclk_bufg/O net (fo=39427, routed) 0.697 0.830 ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLKFBIN SLICE_X177Y282 FDPE r ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X177Y282 FDPE (Prop_fdpe_C_Q) 0.100 0.930 f ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/Q net (fo=24, routed) 0.159 1.089 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/mgt_rxreset_s[3] SLICE_X178Y283 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[7]/CLR ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.499 0.499 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.553 1.052 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -2.340 -1.288 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 1.242 -0.046 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -0.016 r ngFEC/fclk_bufg/O net (fo=39427, routed) 0.925 0.909 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/CLKFBIN SLICE_X178Y283 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[7]/C clock pessimism -0.044 0.865 SLICE_X178Y283 FDCE (Remov_fdce_C_CLR) -0.050 0.815 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[7] ------------------------------------------------------------------- required time -0.815 arrival time 1.089 ------------------------------------------------------------------- slack 0.274 Slack (MET) : 0.274ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[8]/CLR (removal check against rising-edge clock fabric_clk_FBOUT {rise@0.000ns fall@12.476ns period=24.951ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (fabric_clk_FBOUT rise@0.000ns - fabric_clk_FBOUT rise@0.000ns) Data Path Delay: 0.259ns (logic 0.100ns (38.673%) route 0.159ns (61.327%)) Logic Levels: 0 Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.909ns Source Clock Delay (SCD): 0.830ns Clock Pessimism Removal (CPR): 0.044ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.426 0.426 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.503 0.929 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -1.995 -1.066 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 1.173 0.107 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.133 r ngFEC/fclk_bufg/O net (fo=39427, routed) 0.697 0.830 ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/CLKFBIN SLICE_X177Y282 FDPE r ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X177Y282 FDPE (Prop_fdpe_C_Q) 0.100 0.930 f ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/Q net (fo=24, routed) 0.159 1.089 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/mgt_rxreset_s[3] SLICE_X178Y283 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[8]/CLR ------------------------------------------------------------------- ------------------- (clock fabric_clk_FBOUT rise edge) 0.000 0.000 r AK18 0.000 0.000 r fabric_clk_p (IN) net (fo=0) 0.000 0.000 ngFEC/fabric_clk_p AK18 IBUFDS (Prop_ibufds_I_O) 0.499 0.499 r ngFEC/fclk_ibuf/O net (fo=1, routed) 0.553 1.052 ngFEC/fabric_clk_nobuf MMCME2_ADV_X0Y0 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT) -2.340 -1.288 r ngFEC/fabric_clk_MMCME2/CLKFBOUT net (fo=1, routed) 1.242 -0.046 ngFEC/fabric_clk_FBOUT BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.030 -0.016 r ngFEC/fclk_bufg/O net (fo=39427, routed) 0.925 0.909 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/CLKFBIN SLICE_X178Y283 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[8]/C clock pessimism -0.044 0.865 SLICE_X178Y283 FDCE (Remov_fdce_C_CLR) -0.050 0.815 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].timer_reg[8] ------------------------------------------------------------------- required time -0.815 arrival time 1.089 ------------------------------------------------------------------- slack 0.274 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: rxWordclkl12_1 To Clock: rxWordclkl12_1 Setup : 0 Failing Endpoints, Worst Slack 4.471ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.287ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.471ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/shiftPsAddr_reg/CLR (recovery check against rising-edge clock rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_1 rise@8.200ns - rxWordclkl12_1 rise@0.000ns) Data Path Delay: 3.200ns (logic 1.052ns (32.875%) route 2.148ns (67.125%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.281ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.640ns = ( 8.840 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.921 0.921 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.930 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.418 3.348 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/out[0] SLICE_X161Y364 LUT2 (Prop_lut2_I0_O) 0.043 3.391 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1/O net (fo=25, routed) 0.730 4.122 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/rx_reset_s_2 SLICE_X155Y366 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/shiftPsAddr_reg/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 8.200 8.200 r BUFHCE_X1Y84 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.640 8.840 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 SLICE_X155Y366 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/shiftPsAddr_reg/C clock pessimism 0.000 8.840 clock uncertainty -0.035 8.805 SLICE_X155Y366 FDCE (Recov_fdce_C_CLR) -0.212 8.593 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/shiftPsAddr_reg ------------------------------------------------------------------- required time 8.593 arrival time -4.122 ------------------------------------------------------------------- slack 4.471 Slack (MET) : 4.655ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[0]/CLR (recovery check against rising-edge clock rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_1 rise@8.200ns - rxWordclkl12_1 rise@0.000ns) Data Path Delay: 3.017ns (logic 1.052ns (34.871%) route 1.965ns (65.130%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.280ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.641ns = ( 8.841 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.921 0.921 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.930 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.418 3.348 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/out[0] SLICE_X161Y364 LUT2 (Prop_lut2_I0_O) 0.043 3.391 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1/O net (fo=25, routed) 0.547 3.938 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/rx_reset_s_2 SLICE_X156Y366 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 8.200 8.200 r BUFHCE_X1Y84 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.641 8.841 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 SLICE_X156Y366 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[0]/C clock pessimism 0.000 8.841 clock uncertainty -0.035 8.806 SLICE_X156Y366 FDCE (Recov_fdce_C_CLR) -0.212 8.594 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[0] ------------------------------------------------------------------- required time 8.594 arrival time -3.938 ------------------------------------------------------------------- slack 4.655 Slack (MET) : 4.655ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[1]/CLR (recovery check against rising-edge clock rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_1 rise@8.200ns - rxWordclkl12_1 rise@0.000ns) Data Path Delay: 3.017ns (logic 1.052ns (34.871%) route 1.965ns (65.130%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.280ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.641ns = ( 8.841 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.921 0.921 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.930 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.418 3.348 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/out[0] SLICE_X161Y364 LUT2 (Prop_lut2_I0_O) 0.043 3.391 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1/O net (fo=25, routed) 0.547 3.938 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/rx_reset_s_2 SLICE_X156Y366 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 8.200 8.200 r BUFHCE_X1Y84 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.641 8.841 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 SLICE_X156Y366 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[1]/C clock pessimism 0.000 8.841 clock uncertainty -0.035 8.806 SLICE_X156Y366 FDCE (Recov_fdce_C_CLR) -0.212 8.594 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[1] ------------------------------------------------------------------- required time 8.594 arrival time -3.938 ------------------------------------------------------------------- slack 4.655 Slack (MET) : 4.655ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[2]/CLR (recovery check against rising-edge clock rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_1 rise@8.200ns - rxWordclkl12_1 rise@0.000ns) Data Path Delay: 3.017ns (logic 1.052ns (34.871%) route 1.965ns (65.130%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.280ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.641ns = ( 8.841 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.921 0.921 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.930 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.418 3.348 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/out[0] SLICE_X161Y364 LUT2 (Prop_lut2_I0_O) 0.043 3.391 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1/O net (fo=25, routed) 0.547 3.938 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/rx_reset_s_2 SLICE_X156Y366 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 8.200 8.200 r BUFHCE_X1Y84 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.641 8.841 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 SLICE_X156Y366 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[2]/C clock pessimism 0.000 8.841 clock uncertainty -0.035 8.806 SLICE_X156Y366 FDCE (Recov_fdce_C_CLR) -0.212 8.594 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[2] ------------------------------------------------------------------- required time 8.594 arrival time -3.938 ------------------------------------------------------------------- slack 4.655 Slack (MET) : 4.655ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[3]/CLR (recovery check against rising-edge clock rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_1 rise@8.200ns - rxWordclkl12_1 rise@0.000ns) Data Path Delay: 3.017ns (logic 1.052ns (34.871%) route 1.965ns (65.130%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.280ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.641ns = ( 8.841 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.921 0.921 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.930 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.418 3.348 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/out[0] SLICE_X161Y364 LUT2 (Prop_lut2_I0_O) 0.043 3.391 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1/O net (fo=25, routed) 0.547 3.938 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/rx_reset_s_2 SLICE_X156Y366 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 8.200 8.200 r BUFHCE_X1Y84 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.641 8.841 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 SLICE_X156Y366 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[3]/C clock pessimism 0.000 8.841 clock uncertainty -0.035 8.806 SLICE_X156Y366 FDCE (Recov_fdce_C_CLR) -0.212 8.594 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[3] ------------------------------------------------------------------- required time 8.594 arrival time -3.938 ------------------------------------------------------------------- slack 4.655 Slack (MET) : 4.655ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[4]/CLR (recovery check against rising-edge clock rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_1 rise@8.200ns - rxWordclkl12_1 rise@0.000ns) Data Path Delay: 3.017ns (logic 1.052ns (34.871%) route 1.965ns (65.130%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.280ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.641ns = ( 8.841 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.921 0.921 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.930 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.418 3.348 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/out[0] SLICE_X161Y364 LUT2 (Prop_lut2_I0_O) 0.043 3.391 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1/O net (fo=25, routed) 0.547 3.938 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/rx_reset_s_2 SLICE_X156Y366 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 8.200 8.200 r BUFHCE_X1Y84 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.641 8.841 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 SLICE_X156Y366 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[4]/C clock pessimism 0.000 8.841 clock uncertainty -0.035 8.806 SLICE_X156Y366 FDCE (Recov_fdce_C_CLR) -0.212 8.594 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[4] ------------------------------------------------------------------- required time 8.594 arrival time -3.938 ------------------------------------------------------------------- slack 4.655 Slack (MET) : 4.717ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCmd_reg/CLR (recovery check against rising-edge clock rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_1 rise@8.200ns - rxWordclkl12_1 rise@0.000ns) Data Path Delay: 2.955ns (logic 1.052ns (35.603%) route 1.903ns (64.397%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.280ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.641ns = ( 8.841 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.921 0.921 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.930 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.418 3.348 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/out[0] SLICE_X161Y364 LUT2 (Prop_lut2_I0_O) 0.043 3.391 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1/O net (fo=25, routed) 0.485 3.876 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/rx_reset_s_2 SLICE_X155Y365 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCmd_reg/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 8.200 8.200 r BUFHCE_X1Y84 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.641 8.841 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 SLICE_X155Y365 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCmd_reg/C clock pessimism 0.000 8.841 clock uncertainty -0.035 8.806 SLICE_X155Y365 FDCE (Recov_fdce_C_CLR) -0.212 8.594 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCmd_reg ------------------------------------------------------------------- required time 8.594 arrival time -3.876 ------------------------------------------------------------------- slack 4.717 Slack (MET) : 4.717ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/READY_o_reg/CLR (recovery check against rising-edge clock rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_1 rise@8.200ns - rxWordclkl12_1 rise@0.000ns) Data Path Delay: 2.955ns (logic 1.052ns (35.603%) route 1.903ns (64.397%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.280ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.641ns = ( 8.841 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.921 0.921 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.930 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.418 3.348 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/out[0] SLICE_X161Y364 LUT2 (Prop_lut2_I0_O) 0.043 3.391 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1/O net (fo=25, routed) 0.485 3.876 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/RX_RESET_I SLICE_X155Y365 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/READY_o_reg/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 8.200 8.200 r BUFHCE_X1Y84 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.641 8.841 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/RX_WORDCLK_I SLICE_X155Y365 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/READY_o_reg/C clock pessimism 0.000 8.841 clock uncertainty -0.035 8.806 SLICE_X155Y365 FDCE (Recov_fdce_C_CLR) -0.212 8.594 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/READY_o_reg ------------------------------------------------------------------- required time 8.594 arrival time -3.876 ------------------------------------------------------------------- slack 4.717 Slack (MET) : 4.742ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/psAddress_reg[0]/CLR (recovery check against rising-edge clock rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_1 rise@8.200ns - rxWordclkl12_1 rise@0.000ns) Data Path Delay: 2.955ns (logic 1.052ns (35.603%) route 1.903ns (64.397%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.280ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.641ns = ( 8.841 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.921 0.921 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.930 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.418 3.348 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/out[0] SLICE_X161Y364 LUT2 (Prop_lut2_I0_O) 0.043 3.391 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1/O net (fo=25, routed) 0.485 3.876 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/rx_reset_s_2 SLICE_X154Y365 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/psAddress_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 8.200 8.200 r BUFHCE_X1Y84 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.641 8.841 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 SLICE_X154Y365 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/psAddress_reg[0]/C clock pessimism 0.000 8.841 clock uncertainty -0.035 8.806 SLICE_X154Y365 FDCE (Recov_fdce_C_CLR) -0.187 8.619 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/psAddress_reg[0] ------------------------------------------------------------------- required time 8.619 arrival time -3.876 ------------------------------------------------------------------- slack 4.742 Slack (MET) : 4.742ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/psAddress_reg[2]/CLR (recovery check against rising-edge clock rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_1 rise@8.200ns - rxWordclkl12_1 rise@0.000ns) Data Path Delay: 2.955ns (logic 1.052ns (35.603%) route 1.903ns (64.397%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.280ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.641ns = ( 8.841 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.921 0.921 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.930 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.418 3.348 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/out[0] SLICE_X161Y364 LUT2 (Prop_lut2_I0_O) 0.043 3.391 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1/O net (fo=25, routed) 0.485 3.876 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/rx_reset_s_2 SLICE_X154Y365 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/psAddress_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 8.200 8.200 r BUFHCE_X1Y84 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.641 8.841 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 SLICE_X154Y365 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/psAddress_reg[2]/C clock pessimism 0.000 8.841 clock uncertainty -0.035 8.806 SLICE_X154Y365 FDCE (Recov_fdce_C_CLR) -0.187 8.619 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/psAddress_reg[2] ------------------------------------------------------------------- required time 8.619 arrival time -3.876 ------------------------------------------------------------------- slack 4.742 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.287ns (arrival time - required time) Source: ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR (removal check against rising-edge clock rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_1 rise@0.000ns - rxWordclkl12_1 rise@0.000ns) Data Path Delay: 0.269ns (logic 0.100ns (37.116%) route 0.169ns (62.884%)) Logic Levels: 0 Clock Path Skew: 0.032ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.501ns Source Clock Delay (SCD): 0.349ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.349 0.349 ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X152Y362 FDRE r ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X152Y362 FDRE (Prop_fdre_C_Q) 0.100 0.449 f ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.169 0.618 ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Reset SLICE_X150Y364 FDCE f ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.501 0.501 ngFEC/SFP_GEN[2].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X150Y364 FDCE r ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[17]/C clock pessimism -0.120 0.381 SLICE_X150Y364 FDCE (Remov_fdce_C_CLR) -0.050 0.331 ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[17] ------------------------------------------------------------------- required time -0.331 arrival time 0.618 ------------------------------------------------------------------- slack 0.287 Slack (MET) : 0.287ns (arrival time - required time) Source: ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[19]/CLR (removal check against rising-edge clock rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_1 rise@0.000ns - rxWordclkl12_1 rise@0.000ns) Data Path Delay: 0.269ns (logic 0.100ns (37.116%) route 0.169ns (62.884%)) Logic Levels: 0 Clock Path Skew: 0.032ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.501ns Source Clock Delay (SCD): 0.349ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.349 0.349 ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X152Y362 FDRE r ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X152Y362 FDRE (Prop_fdre_C_Q) 0.100 0.449 f ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.169 0.618 ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Reset SLICE_X150Y364 FDCE f ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[19]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.501 0.501 ngFEC/SFP_GEN[2].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X150Y364 FDCE r ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[19]/C clock pessimism -0.120 0.381 SLICE_X150Y364 FDCE (Remov_fdce_C_CLR) -0.050 0.331 ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[19] ------------------------------------------------------------------- required time -0.331 arrival time 0.618 ------------------------------------------------------------------- slack 0.287 Slack (MET) : 0.287ns (arrival time - required time) Source: ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR (removal check against rising-edge clock rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_1 rise@0.000ns - rxWordclkl12_1 rise@0.000ns) Data Path Delay: 0.269ns (logic 0.100ns (37.116%) route 0.169ns (62.884%)) Logic Levels: 0 Clock Path Skew: 0.032ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.501ns Source Clock Delay (SCD): 0.349ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.349 0.349 ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X152Y362 FDRE r ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X152Y362 FDRE (Prop_fdre_C_Q) 0.100 0.449 f ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.169 0.618 ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Reset SLICE_X150Y364 FDCE f ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[32]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.501 0.501 ngFEC/SFP_GEN[2].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X150Y364 FDCE r ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[32]/C clock pessimism -0.120 0.381 SLICE_X150Y364 FDCE (Remov_fdce_C_CLR) -0.050 0.331 ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[32] ------------------------------------------------------------------- required time -0.331 arrival time 0.618 ------------------------------------------------------------------- slack 0.287 Slack (MET) : 0.366ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[92]/CLR (removal check against rising-edge clock rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_1 rise@0.000ns - rxWordclkl12_1 rise@0.000ns) Data Path Delay: 0.328ns (logic 0.100ns (30.495%) route 0.228ns (69.505%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.505ns Source Clock Delay (SCD): 0.353ns Clock Pessimism Removal (CPR): 0.140ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.353 0.353 ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X155Y351 FDPE r ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X155Y351 FDPE (Prop_fdpe_C_Q) 0.100 0.453 f ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.228 0.681 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X154Y357 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[92]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.505 0.505 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X154Y357 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[92]/C clock pessimism -0.140 0.365 SLICE_X154Y357 FDCE (Remov_fdce_C_CLR) -0.050 0.315 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[92] ------------------------------------------------------------------- required time -0.315 arrival time 0.681 ------------------------------------------------------------------- slack 0.366 Slack (MET) : 0.366ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[93]/CLR (removal check against rising-edge clock rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_1 rise@0.000ns - rxWordclkl12_1 rise@0.000ns) Data Path Delay: 0.328ns (logic 0.100ns (30.495%) route 0.228ns (69.505%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.505ns Source Clock Delay (SCD): 0.353ns Clock Pessimism Removal (CPR): 0.140ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.353 0.353 ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X155Y351 FDPE r ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X155Y351 FDPE (Prop_fdpe_C_Q) 0.100 0.453 f ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.228 0.681 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X154Y357 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[93]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.505 0.505 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X154Y357 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[93]/C clock pessimism -0.140 0.365 SLICE_X154Y357 FDCE (Remov_fdce_C_CLR) -0.050 0.315 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[93] ------------------------------------------------------------------- required time -0.315 arrival time 0.681 ------------------------------------------------------------------- slack 0.366 Slack (MET) : 0.381ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[60]/CLR (removal check against rising-edge clock rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_1 rise@0.000ns - rxWordclkl12_1 rise@0.000ns) Data Path Delay: 0.345ns (logic 0.100ns (28.968%) route 0.245ns (71.032%)) Logic Levels: 0 Clock Path Skew: 0.033ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.506ns Source Clock Delay (SCD): 0.353ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.353 0.353 ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X155Y351 FDPE r ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X155Y351 FDPE (Prop_fdpe_C_Q) 0.100 0.453 f ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.245 0.698 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X151Y356 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[60]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.506 0.506 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X151Y356 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[60]/C clock pessimism -0.120 0.386 SLICE_X151Y356 FDCE (Remov_fdce_C_CLR) -0.069 0.317 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[60] ------------------------------------------------------------------- required time -0.317 arrival time 0.698 ------------------------------------------------------------------- slack 0.381 Slack (MET) : 0.396ns (arrival time - required time) Source: ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR (removal check against rising-edge clock rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_1 rise@0.000ns - rxWordclkl12_1 rise@0.000ns) Data Path Delay: 0.373ns (logic 0.100ns (26.844%) route 0.273ns (73.156%)) Logic Levels: 0 Clock Path Skew: 0.027ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.496ns Source Clock Delay (SCD): 0.349ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.349 0.349 ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X152Y362 FDRE r ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X152Y362 FDRE (Prop_fdre_C_Q) 0.100 0.449 f ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.273 0.722 ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Reset SLICE_X146Y366 FDCE f ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.496 0.496 ngFEC/SFP_GEN[2].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X146Y366 FDCE r ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[18]/C clock pessimism -0.120 0.376 SLICE_X146Y366 FDCE (Remov_fdce_C_CLR) -0.050 0.326 ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[18] ------------------------------------------------------------------- required time -0.326 arrival time 0.722 ------------------------------------------------------------------- slack 0.396 Slack (MET) : 0.396ns (arrival time - required time) Source: ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR (removal check against rising-edge clock rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_1 rise@0.000ns - rxWordclkl12_1 rise@0.000ns) Data Path Delay: 0.373ns (logic 0.100ns (26.844%) route 0.273ns (73.156%)) Logic Levels: 0 Clock Path Skew: 0.027ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.496ns Source Clock Delay (SCD): 0.349ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.349 0.349 ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X152Y362 FDRE r ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X152Y362 FDRE (Prop_fdre_C_Q) 0.100 0.449 f ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.273 0.722 ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Reset SLICE_X146Y366 FDCE f ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.496 0.496 ngFEC/SFP_GEN[2].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X146Y366 FDCE r ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[23]/C clock pessimism -0.120 0.376 SLICE_X146Y366 FDCE (Remov_fdce_C_CLR) -0.050 0.326 ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[23] ------------------------------------------------------------------- required time -0.326 arrival time 0.722 ------------------------------------------------------------------- slack 0.396 Slack (MET) : 0.396ns (arrival time - required time) Source: ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[24]/CLR (removal check against rising-edge clock rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_1 rise@0.000ns - rxWordclkl12_1 rise@0.000ns) Data Path Delay: 0.373ns (logic 0.100ns (26.844%) route 0.273ns (73.156%)) Logic Levels: 0 Clock Path Skew: 0.027ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.496ns Source Clock Delay (SCD): 0.349ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.349 0.349 ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X152Y362 FDRE r ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X152Y362 FDRE (Prop_fdre_C_Q) 0.100 0.449 f ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.273 0.722 ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Reset SLICE_X146Y366 FDCE f ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[24]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.496 0.496 ngFEC/SFP_GEN[2].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X146Y366 FDCE r ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[24]/C clock pessimism -0.120 0.376 SLICE_X146Y366 FDCE (Remov_fdce_C_CLR) -0.050 0.326 ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[24] ------------------------------------------------------------------- required time -0.326 arrival time 0.722 ------------------------------------------------------------------- slack 0.396 Slack (MET) : 0.396ns (arrival time - required time) Source: ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[25]/CLR (removal check against rising-edge clock rxWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_1 rise@0.000ns - rxWordclkl12_1 rise@0.000ns) Data Path Delay: 0.373ns (logic 0.100ns (26.844%) route 0.273ns (73.156%)) Logic Levels: 0 Clock Path Skew: 0.027ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.496ns Source Clock Delay (SCD): 0.349ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.349 0.349 ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X152Y362 FDRE r ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X152Y362 FDRE (Prop_fdre_C_Q) 0.100 0.449 f ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.273 0.722 ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Reset SLICE_X146Y366 FDCE f ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[25]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_1 rise edge) 0.000 0.000 r BUFHCE_X1Y84 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.496 0.496 ngFEC/SFP_GEN[2].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X146Y366 FDCE r ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[25]/C clock pessimism -0.120 0.376 SLICE_X146Y366 FDCE (Remov_fdce_C_CLR) -0.050 0.326 ngFEC/SFP_GEN[2].ngCCM_gbt/RX_Word_rx40_reg[25] ------------------------------------------------------------------- required time -0.326 arrival time 0.722 ------------------------------------------------------------------- slack 0.396 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: rxWordclkl12_2 To Clock: rxWordclkl12_2 Setup : 0 Failing Endpoints, Worst Slack 4.567ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.307ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.567ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[0]/CLR (recovery check against rising-edge clock rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_2 rise@8.200ns - rxWordclkl12_2 rise@0.000ns) Data Path Delay: 3.186ns (logic 1.052ns (33.016%) route 2.134ns (66.984%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.698ns = ( 8.898 - 8.200 ) Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.922 0.922 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.931 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.213 3.145 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] SLICE_X185Y372 LUT2 (Prop_lut2_I0_O) 0.043 3.188 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1/O net (fo=25, routed) 0.921 4.109 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_1 SLICE_X186Y358 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 8.200 8.200 r BUFHCE_X1Y85 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.698 8.898 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK SLICE_X186Y358 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[0]/C clock pessimism 0.000 8.898 clock uncertainty -0.035 8.863 SLICE_X186Y358 FDCE (Recov_fdce_C_CLR) -0.187 8.676 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[0] ------------------------------------------------------------------- required time 8.676 arrival time -4.109 ------------------------------------------------------------------- slack 4.567 Slack (MET) : 4.567ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[2]/CLR (recovery check against rising-edge clock rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_2 rise@8.200ns - rxWordclkl12_2 rise@0.000ns) Data Path Delay: 3.186ns (logic 1.052ns (33.016%) route 2.134ns (66.984%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.698ns = ( 8.898 - 8.200 ) Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.922 0.922 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.931 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.213 3.145 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] SLICE_X185Y372 LUT2 (Prop_lut2_I0_O) 0.043 3.188 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1/O net (fo=25, routed) 0.921 4.109 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_1 SLICE_X186Y358 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 8.200 8.200 r BUFHCE_X1Y85 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.698 8.898 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK SLICE_X186Y358 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[2]/C clock pessimism 0.000 8.898 clock uncertainty -0.035 8.863 SLICE_X186Y358 FDCE (Recov_fdce_C_CLR) -0.187 8.676 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[2] ------------------------------------------------------------------- required time 8.676 arrival time -4.109 ------------------------------------------------------------------- slack 4.567 Slack (MET) : 4.567ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]/CLR (recovery check against rising-edge clock rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_2 rise@8.200ns - rxWordclkl12_2 rise@0.000ns) Data Path Delay: 3.161ns (logic 1.052ns (33.278%) route 2.109ns (66.722%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.698ns = ( 8.898 - 8.200 ) Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.922 0.922 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.931 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.213 3.145 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] SLICE_X185Y372 LUT2 (Prop_lut2_I0_O) 0.043 3.188 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1/O net (fo=25, routed) 0.896 4.084 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_1 SLICE_X184Y359 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 8.200 8.200 r BUFHCE_X1Y85 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.698 8.898 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK SLICE_X184Y359 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.000 8.898 clock uncertainty -0.035 8.863 SLICE_X184Y359 FDCE (Recov_fdce_C_CLR) -0.212 8.651 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 8.651 arrival time -4.084 ------------------------------------------------------------------- slack 4.567 Slack (MET) : 4.567ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/CLR (recovery check against rising-edge clock rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_2 rise@8.200ns - rxWordclkl12_2 rise@0.000ns) Data Path Delay: 3.161ns (logic 1.052ns (33.278%) route 2.109ns (66.722%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.698ns = ( 8.898 - 8.200 ) Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.922 0.922 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.931 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.213 3.145 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] SLICE_X185Y372 LUT2 (Prop_lut2_I0_O) 0.043 3.188 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1/O net (fo=25, routed) 0.896 4.084 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_1 SLICE_X184Y359 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 8.200 8.200 r BUFHCE_X1Y85 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.698 8.898 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK SLICE_X184Y359 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.000 8.898 clock uncertainty -0.035 8.863 SLICE_X184Y359 FDCE (Recov_fdce_C_CLR) -0.212 8.651 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 8.651 arrival time -4.084 ------------------------------------------------------------------- slack 4.567 Slack (MET) : 4.569ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/RX_HEADER_LOCKED_O_reg/CLR (recovery check against rising-edge clock rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_2 rise@8.200ns - rxWordclkl12_2 rise@0.000ns) Data Path Delay: 3.159ns (logic 1.052ns (33.300%) route 2.107ns (66.700%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.698ns = ( 8.898 - 8.200 ) Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.922 0.922 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.931 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.213 3.145 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] SLICE_X185Y372 LUT2 (Prop_lut2_I0_O) 0.043 3.188 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1/O net (fo=25, routed) 0.894 4.082 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_1 SLICE_X185Y359 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/RX_HEADER_LOCKED_O_reg/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 8.200 8.200 r BUFHCE_X1Y85 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.698 8.898 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK SLICE_X185Y359 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/RX_HEADER_LOCKED_O_reg/C clock pessimism 0.000 8.898 clock uncertainty -0.035 8.863 SLICE_X185Y359 FDCE (Recov_fdce_C_CLR) -0.212 8.651 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/RX_HEADER_LOCKED_O_reg ------------------------------------------------------------------- required time 8.651 arrival time -4.082 ------------------------------------------------------------------- slack 4.569 Slack (MET) : 4.569ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCmd_reg/CLR (recovery check against rising-edge clock rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_2 rise@8.200ns - rxWordclkl12_2 rise@0.000ns) Data Path Delay: 3.159ns (logic 1.052ns (33.300%) route 2.107ns (66.700%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.698ns = ( 8.898 - 8.200 ) Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.922 0.922 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.931 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.213 3.145 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] SLICE_X185Y372 LUT2 (Prop_lut2_I0_O) 0.043 3.188 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1/O net (fo=25, routed) 0.894 4.082 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_1 SLICE_X185Y359 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCmd_reg/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 8.200 8.200 r BUFHCE_X1Y85 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.698 8.898 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK SLICE_X185Y359 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCmd_reg/C clock pessimism 0.000 8.898 clock uncertainty -0.035 8.863 SLICE_X185Y359 FDCE (Recov_fdce_C_CLR) -0.212 8.651 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCmd_reg ------------------------------------------------------------------- required time 8.651 arrival time -4.082 ------------------------------------------------------------------- slack 4.569 Slack (MET) : 4.569ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/READY_o_reg/CLR (recovery check against rising-edge clock rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_2 rise@8.200ns - rxWordclkl12_2 rise@0.000ns) Data Path Delay: 3.159ns (logic 1.052ns (33.300%) route 2.107ns (66.700%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.698ns = ( 8.898 - 8.200 ) Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.922 0.922 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.931 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.213 3.145 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] SLICE_X185Y372 LUT2 (Prop_lut2_I0_O) 0.043 3.188 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1/O net (fo=25, routed) 0.894 4.082 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/RX_RESET_I SLICE_X185Y359 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/READY_o_reg/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 8.200 8.200 r BUFHCE_X1Y85 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.698 8.898 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/RX_WORDCLK_I SLICE_X185Y359 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/READY_o_reg/C clock pessimism 0.000 8.898 clock uncertainty -0.035 8.863 SLICE_X185Y359 FDCE (Recov_fdce_C_CLR) -0.212 8.651 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/READY_o_reg ------------------------------------------------------------------- required time 8.651 arrival time -4.082 ------------------------------------------------------------------- slack 4.569 Slack (MET) : 4.600ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/headerFlag_s_reg/CLR (recovery check against rising-edge clock rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_2 rise@8.200ns - rxWordclkl12_2 rise@0.000ns) Data Path Delay: 3.186ns (logic 1.052ns (33.016%) route 2.134ns (66.984%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.698ns = ( 8.898 - 8.200 ) Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.922 0.922 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.931 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.213 3.145 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] SLICE_X185Y372 LUT2 (Prop_lut2_I0_O) 0.043 3.188 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1/O net (fo=25, routed) 0.921 4.109 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_1 SLICE_X186Y358 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/headerFlag_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 8.200 8.200 r BUFHCE_X1Y85 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.698 8.898 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK SLICE_X186Y358 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/headerFlag_s_reg/C clock pessimism 0.000 8.898 clock uncertainty -0.035 8.863 SLICE_X186Y358 FDCE (Recov_fdce_C_CLR) -0.154 8.709 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/headerFlag_s_reg ------------------------------------------------------------------- required time 8.709 arrival time -4.109 ------------------------------------------------------------------- slack 4.600 Slack (MET) : 4.600ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[1]/CLR (recovery check against rising-edge clock rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_2 rise@8.200ns - rxWordclkl12_2 rise@0.000ns) Data Path Delay: 3.186ns (logic 1.052ns (33.016%) route 2.134ns (66.984%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.698ns = ( 8.898 - 8.200 ) Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.922 0.922 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.931 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.213 3.145 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] SLICE_X185Y372 LUT2 (Prop_lut2_I0_O) 0.043 3.188 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1/O net (fo=25, routed) 0.921 4.109 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_1 SLICE_X186Y358 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 8.200 8.200 r BUFHCE_X1Y85 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.698 8.898 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK SLICE_X186Y358 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[1]/C clock pessimism 0.000 8.898 clock uncertainty -0.035 8.863 SLICE_X186Y358 FDCE (Recov_fdce_C_CLR) -0.154 8.709 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[1] ------------------------------------------------------------------- required time 8.709 arrival time -4.109 ------------------------------------------------------------------- slack 4.600 Slack (MET) : 4.876ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/FSM_onehot_state_reg[1]/CLR (recovery check against rising-edge clock rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_2 rise@8.200ns - rxWordclkl12_2 rise@0.000ns) Data Path Delay: 2.849ns (logic 1.052ns (36.921%) route 1.797ns (63.079%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.227ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.695ns = ( 8.895 - 8.200 ) Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.922 0.922 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.931 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.213 3.145 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] SLICE_X185Y372 LUT2 (Prop_lut2_I0_O) 0.043 3.188 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1/O net (fo=25, routed) 0.584 3.772 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/RX_RESET_I SLICE_X188Y364 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/FSM_onehot_state_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 8.200 8.200 r BUFHCE_X1Y85 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.695 8.895 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/RX_WORDCLK_I SLICE_X188Y364 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/FSM_onehot_state_reg[1]/C clock pessimism 0.000 8.895 clock uncertainty -0.035 8.860 SLICE_X188Y364 FDCE (Recov_fdce_C_CLR) -0.212 8.648 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/FSM_onehot_state_reg[1] ------------------------------------------------------------------- required time 8.648 arrival time -3.772 ------------------------------------------------------------------- slack 4.876 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.307ns (arrival time - required time) Source: ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[72]/CLR (removal check against rising-edge clock rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_2 rise@0.000ns - rxWordclkl12_2 rise@0.000ns) Data Path Delay: 0.253ns (logic 0.100ns (39.587%) route 0.153ns (60.413%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.535ns Source Clock Delay (SCD): 0.379ns Clock Pessimism Removal (CPR): 0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.379 0.379 ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X168Y361 FDRE r ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X168Y361 FDRE (Prop_fdre_C_Q) 0.100 0.479 f ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.153 0.632 ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Reset SLICE_X169Y358 FDCE f ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[72]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.535 0.535 ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X169Y358 FDCE r ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[72]/C clock pessimism -0.141 0.394 SLICE_X169Y358 FDCE (Remov_fdce_C_CLR) -0.069 0.325 ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[72] ------------------------------------------------------------------- required time -0.325 arrival time 0.632 ------------------------------------------------------------------- slack 0.307 Slack (MET) : 0.307ns (arrival time - required time) Source: ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[74]/CLR (removal check against rising-edge clock rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_2 rise@0.000ns - rxWordclkl12_2 rise@0.000ns) Data Path Delay: 0.253ns (logic 0.100ns (39.587%) route 0.153ns (60.413%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.535ns Source Clock Delay (SCD): 0.379ns Clock Pessimism Removal (CPR): 0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.379 0.379 ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X168Y361 FDRE r ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X168Y361 FDRE (Prop_fdre_C_Q) 0.100 0.479 f ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.153 0.632 ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Reset SLICE_X169Y358 FDCE f ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[74]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.535 0.535 ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X169Y358 FDCE r ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[74]/C clock pessimism -0.141 0.394 SLICE_X169Y358 FDCE (Remov_fdce_C_CLR) -0.069 0.325 ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[74] ------------------------------------------------------------------- required time -0.325 arrival time 0.632 ------------------------------------------------------------------- slack 0.307 Slack (MET) : 0.307ns (arrival time - required time) Source: ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[76]/CLR (removal check against rising-edge clock rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_2 rise@0.000ns - rxWordclkl12_2 rise@0.000ns) Data Path Delay: 0.253ns (logic 0.100ns (39.587%) route 0.153ns (60.413%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.535ns Source Clock Delay (SCD): 0.379ns Clock Pessimism Removal (CPR): 0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.379 0.379 ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X168Y361 FDRE r ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X168Y361 FDRE (Prop_fdre_C_Q) 0.100 0.479 f ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.153 0.632 ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Reset SLICE_X169Y358 FDCE f ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[76]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.535 0.535 ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X169Y358 FDCE r ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[76]/C clock pessimism -0.141 0.394 SLICE_X169Y358 FDCE (Remov_fdce_C_CLR) -0.069 0.325 ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[76] ------------------------------------------------------------------- required time -0.325 arrival time 0.632 ------------------------------------------------------------------- slack 0.307 Slack (MET) : 0.307ns (arrival time - required time) Source: ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[78]/CLR (removal check against rising-edge clock rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_2 rise@0.000ns - rxWordclkl12_2 rise@0.000ns) Data Path Delay: 0.253ns (logic 0.100ns (39.587%) route 0.153ns (60.413%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.535ns Source Clock Delay (SCD): 0.379ns Clock Pessimism Removal (CPR): 0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.379 0.379 ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X168Y361 FDRE r ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X168Y361 FDRE (Prop_fdre_C_Q) 0.100 0.479 f ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.153 0.632 ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Reset SLICE_X169Y358 FDCE f ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[78]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.535 0.535 ngFEC/SFP_GEN[3].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X169Y358 FDCE r ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[78]/C clock pessimism -0.141 0.394 SLICE_X169Y358 FDCE (Remov_fdce_C_CLR) -0.069 0.325 ngFEC/SFP_GEN[3].ngCCM_gbt/RX_Word_rx40_reg[78] ------------------------------------------------------------------- required time -0.325 arrival time 0.632 ------------------------------------------------------------------- slack 0.307 Slack (MET) : 0.308ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[32]/CLR (removal check against rising-edge clock rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_2 rise@0.000ns - rxWordclkl12_2 rise@0.000ns) Data Path Delay: 0.294ns (logic 0.118ns (40.119%) route 0.176ns (59.881%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.541ns Source Clock Delay (SCD): 0.385ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.385 0.385 ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X176Y350 FDPE r ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X176Y350 FDPE (Prop_fdpe_C_Q) 0.118 0.503 f ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.176 0.679 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X178Y350 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[32]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.541 0.541 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X178Y350 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[32]/C clock pessimism -0.120 0.421 SLICE_X178Y350 FDCE (Remov_fdce_C_CLR) -0.050 0.371 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[32] ------------------------------------------------------------------- required time -0.371 arrival time 0.679 ------------------------------------------------------------------- slack 0.308 Slack (MET) : 0.308ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[35]/CLR (removal check against rising-edge clock rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_2 rise@0.000ns - rxWordclkl12_2 rise@0.000ns) Data Path Delay: 0.294ns (logic 0.118ns (40.119%) route 0.176ns (59.881%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.541ns Source Clock Delay (SCD): 0.385ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.385 0.385 ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X176Y350 FDPE r ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X176Y350 FDPE (Prop_fdpe_C_Q) 0.118 0.503 f ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.176 0.679 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X178Y350 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[35]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.541 0.541 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X178Y350 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[35]/C clock pessimism -0.120 0.421 SLICE_X178Y350 FDCE (Remov_fdce_C_CLR) -0.050 0.371 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[35] ------------------------------------------------------------------- required time -0.371 arrival time 0.679 ------------------------------------------------------------------- slack 0.308 Slack (MET) : 0.308ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[48]/CLR (removal check against rising-edge clock rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_2 rise@0.000ns - rxWordclkl12_2 rise@0.000ns) Data Path Delay: 0.294ns (logic 0.118ns (40.119%) route 0.176ns (59.881%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.541ns Source Clock Delay (SCD): 0.385ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.385 0.385 ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X176Y350 FDPE r ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X176Y350 FDPE (Prop_fdpe_C_Q) 0.118 0.503 f ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.176 0.679 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X178Y350 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[48]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.541 0.541 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X178Y350 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[48]/C clock pessimism -0.120 0.421 SLICE_X178Y350 FDCE (Remov_fdce_C_CLR) -0.050 0.371 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[48] ------------------------------------------------------------------- required time -0.371 arrival time 0.679 ------------------------------------------------------------------- slack 0.308 Slack (MET) : 0.308ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[59]/CLR (removal check against rising-edge clock rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_2 rise@0.000ns - rxWordclkl12_2 rise@0.000ns) Data Path Delay: 0.294ns (logic 0.118ns (40.119%) route 0.176ns (59.881%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.541ns Source Clock Delay (SCD): 0.385ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.385 0.385 ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X176Y350 FDPE r ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X176Y350 FDPE (Prop_fdpe_C_Q) 0.118 0.503 f ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.176 0.679 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X178Y350 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[59]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.541 0.541 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X178Y350 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[59]/C clock pessimism -0.120 0.421 SLICE_X178Y350 FDCE (Remov_fdce_C_CLR) -0.050 0.371 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[59] ------------------------------------------------------------------- required time -0.371 arrival time 0.679 ------------------------------------------------------------------- slack 0.308 Slack (MET) : 0.327ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[105]/CLR (removal check against rising-edge clock rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_2 rise@0.000ns - rxWordclkl12_2 rise@0.000ns) Data Path Delay: 0.294ns (logic 0.118ns (40.119%) route 0.176ns (59.881%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.541ns Source Clock Delay (SCD): 0.385ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.385 0.385 ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X176Y350 FDPE r ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X176Y350 FDPE (Prop_fdpe_C_Q) 0.118 0.503 f ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.176 0.679 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X179Y350 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[105]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.541 0.541 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X179Y350 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[105]/C clock pessimism -0.120 0.421 SLICE_X179Y350 FDCE (Remov_fdce_C_CLR) -0.069 0.352 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[105] ------------------------------------------------------------------- required time -0.352 arrival time 0.679 ------------------------------------------------------------------- slack 0.327 Slack (MET) : 0.327ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[114]/CLR (removal check against rising-edge clock rxWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_2 rise@0.000ns - rxWordclkl12_2 rise@0.000ns) Data Path Delay: 0.294ns (logic 0.118ns (40.119%) route 0.176ns (59.881%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.541ns Source Clock Delay (SCD): 0.385ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.385 0.385 ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X176Y350 FDPE r ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X176Y350 FDPE (Prop_fdpe_C_Q) 0.118 0.503 f ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.176 0.679 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X179Y350 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[114]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_2 rise edge) 0.000 0.000 r BUFHCE_X1Y85 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.541 0.541 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X179Y350 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[114]/C clock pessimism -0.120 0.421 SLICE_X179Y350 FDCE (Remov_fdce_C_CLR) -0.069 0.352 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[114] ------------------------------------------------------------------- required time -0.352 arrival time 0.679 ------------------------------------------------------------------- slack 0.327 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: rxWordclkl12_3 To Clock: rxWordclkl12_3 Setup : 0 Failing Endpoints, Worst Slack 4.389ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.336ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.389ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/CLR (recovery check against rising-edge clock rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_3 rise@8.200ns - rxWordclkl12_3 rise@0.000ns) Data Path Delay: 3.340ns (logic 1.052ns (31.493%) route 2.288ns (68.507%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.223ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.692ns = ( 8.892 - 8.200 ) Source Clock Delay (SCD): 0.915ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.915 0.915 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.924 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.527 3.451 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] SLICE_X169Y366 LUT2 (Prop_lut2_I0_O) 0.043 3.494 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1/O net (fo=25, routed) 0.762 4.256 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/rx_reset_s_0 SLICE_X171Y363 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 8.200 8.200 r BUFHCE_X1Y86 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.692 8.892 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK SLICE_X171Y363 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg/C clock pessimism 0.000 8.892 clock uncertainty -0.035 8.857 SLICE_X171Y363 FDCE (Recov_fdce_C_CLR) -0.212 8.645 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/headerFlag_s_reg ------------------------------------------------------------------- required time 8.645 arrival time -4.256 ------------------------------------------------------------------- slack 4.389 Slack (MET) : 4.389ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/psAddress_reg[0]/CLR (recovery check against rising-edge clock rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_3 rise@8.200ns - rxWordclkl12_3 rise@0.000ns) Data Path Delay: 3.340ns (logic 1.052ns (31.493%) route 2.288ns (68.507%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.223ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.692ns = ( 8.892 - 8.200 ) Source Clock Delay (SCD): 0.915ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.915 0.915 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.924 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.527 3.451 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] SLICE_X169Y366 LUT2 (Prop_lut2_I0_O) 0.043 3.494 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1/O net (fo=25, routed) 0.762 4.256 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/rx_reset_s_0 SLICE_X171Y363 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/psAddress_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 8.200 8.200 r BUFHCE_X1Y86 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.692 8.892 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK SLICE_X171Y363 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/psAddress_reg[0]/C clock pessimism 0.000 8.892 clock uncertainty -0.035 8.857 SLICE_X171Y363 FDCE (Recov_fdce_C_CLR) -0.212 8.645 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/psAddress_reg[0] ------------------------------------------------------------------- required time 8.645 arrival time -4.256 ------------------------------------------------------------------- slack 4.389 Slack (MET) : 4.389ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/psAddress_reg[1]/CLR (recovery check against rising-edge clock rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_3 rise@8.200ns - rxWordclkl12_3 rise@0.000ns) Data Path Delay: 3.340ns (logic 1.052ns (31.493%) route 2.288ns (68.507%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.223ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.692ns = ( 8.892 - 8.200 ) Source Clock Delay (SCD): 0.915ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.915 0.915 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.924 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.527 3.451 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] SLICE_X169Y366 LUT2 (Prop_lut2_I0_O) 0.043 3.494 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1/O net (fo=25, routed) 0.762 4.256 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/rx_reset_s_0 SLICE_X171Y363 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/psAddress_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 8.200 8.200 r BUFHCE_X1Y86 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.692 8.892 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK SLICE_X171Y363 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/psAddress_reg[1]/C clock pessimism 0.000 8.892 clock uncertainty -0.035 8.857 SLICE_X171Y363 FDCE (Recov_fdce_C_CLR) -0.212 8.645 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/psAddress_reg[1] ------------------------------------------------------------------- required time 8.645 arrival time -4.256 ------------------------------------------------------------------- slack 4.389 Slack (MET) : 4.389ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/psAddress_reg[2]/CLR (recovery check against rising-edge clock rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_3 rise@8.200ns - rxWordclkl12_3 rise@0.000ns) Data Path Delay: 3.340ns (logic 1.052ns (31.493%) route 2.288ns (68.507%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.223ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.692ns = ( 8.892 - 8.200 ) Source Clock Delay (SCD): 0.915ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.915 0.915 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.924 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.527 3.451 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] SLICE_X169Y366 LUT2 (Prop_lut2_I0_O) 0.043 3.494 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1/O net (fo=25, routed) 0.762 4.256 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/rx_reset_s_0 SLICE_X171Y363 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/psAddress_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 8.200 8.200 r BUFHCE_X1Y86 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.692 8.892 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK SLICE_X171Y363 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/psAddress_reg[2]/C clock pessimism 0.000 8.892 clock uncertainty -0.035 8.857 SLICE_X171Y363 FDCE (Recov_fdce_C_CLR) -0.212 8.645 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/psAddress_reg[2] ------------------------------------------------------------------- required time 8.645 arrival time -4.256 ------------------------------------------------------------------- slack 4.389 Slack (MET) : 4.449ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCmd_reg/CLR (recovery check against rising-edge clock rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_3 rise@8.200ns - rxWordclkl12_3 rise@0.000ns) Data Path Delay: 3.279ns (logic 1.052ns (32.084%) route 2.227ns (67.916%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.691ns = ( 8.891 - 8.200 ) Source Clock Delay (SCD): 0.915ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.915 0.915 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.924 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.527 3.451 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] SLICE_X169Y366 LUT2 (Prop_lut2_I0_O) 0.043 3.494 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1/O net (fo=25, routed) 0.700 4.194 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/rx_reset_s_0 SLICE_X173Y364 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCmd_reg/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 8.200 8.200 r BUFHCE_X1Y86 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.691 8.891 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK SLICE_X173Y364 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCmd_reg/C clock pessimism 0.000 8.891 clock uncertainty -0.035 8.856 SLICE_X173Y364 FDCE (Recov_fdce_C_CLR) -0.212 8.644 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCmd_reg ------------------------------------------------------------------- required time 8.644 arrival time -4.194 ------------------------------------------------------------------- slack 4.449 Slack (MET) : 4.449ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/shiftPsAddr_reg/CLR (recovery check against rising-edge clock rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_3 rise@8.200ns - rxWordclkl12_3 rise@0.000ns) Data Path Delay: 3.279ns (logic 1.052ns (32.084%) route 2.227ns (67.916%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.691ns = ( 8.891 - 8.200 ) Source Clock Delay (SCD): 0.915ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.915 0.915 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.924 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.527 3.451 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] SLICE_X169Y366 LUT2 (Prop_lut2_I0_O) 0.043 3.494 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1/O net (fo=25, routed) 0.700 4.194 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/rx_reset_s_0 SLICE_X173Y364 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/shiftPsAddr_reg/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 8.200 8.200 r BUFHCE_X1Y86 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.691 8.891 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK SLICE_X173Y364 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/shiftPsAddr_reg/C clock pessimism 0.000 8.891 clock uncertainty -0.035 8.856 SLICE_X173Y364 FDCE (Recov_fdce_C_CLR) -0.212 8.644 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/shiftPsAddr_reg ------------------------------------------------------------------- required time 8.644 arrival time -4.194 ------------------------------------------------------------------- slack 4.449 Slack (MET) : 4.449ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/READY_o_reg/CLR (recovery check against rising-edge clock rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_3 rise@8.200ns - rxWordclkl12_3 rise@0.000ns) Data Path Delay: 3.279ns (logic 1.052ns (32.084%) route 2.227ns (67.916%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.691ns = ( 8.891 - 8.200 ) Source Clock Delay (SCD): 0.915ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.915 0.915 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.924 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.527 3.451 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] SLICE_X169Y366 LUT2 (Prop_lut2_I0_O) 0.043 3.494 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1/O net (fo=25, routed) 0.700 4.194 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_RESET_I SLICE_X173Y364 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/READY_o_reg/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 8.200 8.200 r BUFHCE_X1Y86 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.691 8.891 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_WORDCLK_I SLICE_X173Y364 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/READY_o_reg/C clock pessimism 0.000 8.891 clock uncertainty -0.035 8.856 SLICE_X173Y364 FDCE (Recov_fdce_C_CLR) -0.212 8.644 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/READY_o_reg ------------------------------------------------------------------- required time 8.644 arrival time -4.194 ------------------------------------------------------------------- slack 4.449 Slack (MET) : 4.534ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_BITSLIPCMD_o_reg/CLR (recovery check against rising-edge clock rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_3 rise@8.200ns - rxWordclkl12_3 rise@0.000ns) Data Path Delay: 3.194ns (logic 1.052ns (32.932%) route 2.142ns (67.068%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.691ns = ( 8.891 - 8.200 ) Source Clock Delay (SCD): 0.915ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.915 0.915 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.924 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.527 3.451 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] SLICE_X169Y366 LUT2 (Prop_lut2_I0_O) 0.043 3.494 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1/O net (fo=25, routed) 0.616 4.110 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_RESET_I SLICE_X175Y364 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_BITSLIPCMD_o_reg/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 8.200 8.200 r BUFHCE_X1Y86 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.691 8.891 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_WORDCLK_I SLICE_X175Y364 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_BITSLIPCMD_o_reg/C clock pessimism 0.000 8.891 clock uncertainty -0.035 8.856 SLICE_X175Y364 FDCE (Recov_fdce_C_CLR) -0.212 8.644 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_BITSLIPCMD_o_reg ------------------------------------------------------------------- required time 8.644 arrival time -4.110 ------------------------------------------------------------------- slack 4.534 Slack (MET) : 4.559ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[0]/PRE (recovery check against rising-edge clock rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_3 rise@8.200ns - rxWordclkl12_3 rise@0.000ns) Data Path Delay: 3.194ns (logic 1.052ns (32.932%) route 2.142ns (67.068%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.691ns = ( 8.891 - 8.200 ) Source Clock Delay (SCD): 0.915ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.915 0.915 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.924 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.527 3.451 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] SLICE_X169Y366 LUT2 (Prop_lut2_I0_O) 0.043 3.494 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1/O net (fo=25, routed) 0.616 4.110 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_RESET_I SLICE_X174Y364 FDPE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[0]/PRE ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 8.200 8.200 r BUFHCE_X1Y86 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.691 8.891 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_WORDCLK_I SLICE_X174Y364 FDPE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[0]/C clock pessimism 0.000 8.891 clock uncertainty -0.035 8.856 SLICE_X174Y364 FDPE (Recov_fdpe_C_PRE) -0.187 8.669 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[0] ------------------------------------------------------------------- required time 8.669 arrival time -4.110 ------------------------------------------------------------------- slack 4.559 Slack (MET) : 4.559ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[2]/CLR (recovery check against rising-edge clock rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_3 rise@8.200ns - rxWordclkl12_3 rise@0.000ns) Data Path Delay: 3.194ns (logic 1.052ns (32.932%) route 2.142ns (67.068%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.691ns = ( 8.891 - 8.200 ) Source Clock Delay (SCD): 0.915ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.915 0.915 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.924 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.527 3.451 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] SLICE_X169Y366 LUT2 (Prop_lut2_I0_O) 0.043 3.494 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1/O net (fo=25, routed) 0.616 4.110 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_RESET_I SLICE_X174Y364 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 8.200 8.200 r BUFHCE_X1Y86 BUFH 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.691 8.891 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_WORDCLK_I SLICE_X174Y364 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[2]/C clock pessimism 0.000 8.891 clock uncertainty -0.035 8.856 SLICE_X174Y364 FDCE (Recov_fdce_C_CLR) -0.187 8.669 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[2] ------------------------------------------------------------------- required time 8.669 arrival time -4.110 ------------------------------------------------------------------- slack 4.559 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.336ns (arrival time - required time) Source: ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[28]/CLR (removal check against rising-edge clock rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_3 rise@0.000ns - rxWordclkl12_3 rise@0.000ns) Data Path Delay: 0.322ns (logic 0.118ns (36.660%) route 0.204ns (63.340%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.506ns Source Clock Delay (SCD): 0.350ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.350 0.350 ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X162Y363 FDRE r ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X162Y363 FDRE (Prop_fdre_C_Q) 0.118 0.468 f ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.204 0.672 ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Reset SLICE_X160Y361 FDCE f ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[28]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.506 0.506 ngFEC/SFP_GEN[4].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X160Y361 FDCE r ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[28]/C clock pessimism -0.120 0.386 SLICE_X160Y361 FDCE (Remov_fdce_C_CLR) -0.050 0.336 ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[28] ------------------------------------------------------------------- required time -0.336 arrival time 0.672 ------------------------------------------------------------------- slack 0.336 Slack (MET) : 0.336ns (arrival time - required time) Source: ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[29]/CLR (removal check against rising-edge clock rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_3 rise@0.000ns - rxWordclkl12_3 rise@0.000ns) Data Path Delay: 0.322ns (logic 0.118ns (36.660%) route 0.204ns (63.340%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.506ns Source Clock Delay (SCD): 0.350ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.350 0.350 ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X162Y363 FDRE r ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X162Y363 FDRE (Prop_fdre_C_Q) 0.118 0.468 f ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.204 0.672 ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Reset SLICE_X160Y361 FDCE f ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[29]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.506 0.506 ngFEC/SFP_GEN[4].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X160Y361 FDCE r ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[29]/C clock pessimism -0.120 0.386 SLICE_X160Y361 FDCE (Remov_fdce_C_CLR) -0.050 0.336 ngFEC/SFP_GEN[4].ngCCM_gbt/RX_Word_rx40_reg[29] ------------------------------------------------------------------- required time -0.336 arrival time 0.672 ------------------------------------------------------------------- slack 0.336 Slack (MET) : 0.343ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[0]/CLR (removal check against rising-edge clock rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_3 rise@0.000ns - rxWordclkl12_3 rise@0.000ns) Data Path Delay: 0.353ns (logic 0.118ns (33.420%) route 0.235ns (66.580%)) Logic Levels: 0 Clock Path Skew: 0.060ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.530ns Source Clock Delay (SCD): 0.350ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.350 0.350 ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X164Y364 FDPE r ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X164Y364 FDPE (Prop_fdpe_C_Q) 0.118 0.468 f ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.235 0.703 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X166Y363 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.530 0.530 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X166Y363 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[0]/C clock pessimism -0.120 0.410 SLICE_X166Y363 FDCE (Remov_fdce_C_CLR) -0.050 0.360 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[0] ------------------------------------------------------------------- required time -0.360 arrival time 0.703 ------------------------------------------------------------------- slack 0.343 Slack (MET) : 0.343ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[1]/CLR (removal check against rising-edge clock rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_3 rise@0.000ns - rxWordclkl12_3 rise@0.000ns) Data Path Delay: 0.353ns (logic 0.118ns (33.420%) route 0.235ns (66.580%)) Logic Levels: 0 Clock Path Skew: 0.060ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.530ns Source Clock Delay (SCD): 0.350ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.350 0.350 ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X164Y364 FDPE r ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X164Y364 FDPE (Prop_fdpe_C_Q) 0.118 0.468 f ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.235 0.703 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X166Y363 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.530 0.530 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X166Y363 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[1]/C clock pessimism -0.120 0.410 SLICE_X166Y363 FDCE (Remov_fdce_C_CLR) -0.050 0.360 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[1] ------------------------------------------------------------------- required time -0.360 arrival time 0.703 ------------------------------------------------------------------- slack 0.343 Slack (MET) : 0.343ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[2]/CLR (removal check against rising-edge clock rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_3 rise@0.000ns - rxWordclkl12_3 rise@0.000ns) Data Path Delay: 0.353ns (logic 0.118ns (33.420%) route 0.235ns (66.580%)) Logic Levels: 0 Clock Path Skew: 0.060ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.530ns Source Clock Delay (SCD): 0.350ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.350 0.350 ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X164Y364 FDPE r ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X164Y364 FDPE (Prop_fdpe_C_Q) 0.118 0.468 f ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.235 0.703 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X166Y363 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.530 0.530 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X166Y363 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[2]/C clock pessimism -0.120 0.410 SLICE_X166Y363 FDCE (Remov_fdce_C_CLR) -0.050 0.360 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[2] ------------------------------------------------------------------- required time -0.360 arrival time 0.703 ------------------------------------------------------------------- slack 0.343 Slack (MET) : 0.343ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/firstOut_reg/CLR (removal check against rising-edge clock rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_3 rise@0.000ns - rxWordclkl12_3 rise@0.000ns) Data Path Delay: 0.353ns (logic 0.118ns (33.420%) route 0.235ns (66.580%)) Logic Levels: 0 Clock Path Skew: 0.060ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.530ns Source Clock Delay (SCD): 0.350ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.350 0.350 ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X164Y364 FDPE r ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X164Y364 FDPE (Prop_fdpe_C_Q) 0.118 0.468 f ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.235 0.703 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X166Y363 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/firstOut_reg/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.530 0.530 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X166Y363 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/firstOut_reg/C clock pessimism -0.120 0.410 SLICE_X166Y363 FDCE (Remov_fdce_C_CLR) -0.050 0.360 ngFEC/gbtbank1_l12_118/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/firstOut_reg ------------------------------------------------------------------- required time -0.360 arrival time 0.703 ------------------------------------------------------------------- slack 0.343 Slack (MET) : 0.381ns (arrival time - required time) Source: ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[28]/CLR (removal check against rising-edge clock rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_3 rise@0.000ns - rxWordclkl12_3 rise@0.000ns) Data Path Delay: 0.395ns (logic 0.118ns (29.882%) route 0.277ns (70.118%)) Logic Levels: 0 Clock Path Skew: 0.064ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.534ns Source Clock Delay (SCD): 0.350ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.350 0.350 ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X162Y363 FDRE r ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X162Y363 FDRE (Prop_fdre_C_Q) 0.118 0.468 f ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.277 0.745 ngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/AR[0] SLICE_X166Y357 FDCE f ngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[28]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.534 0.534 ngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] SLICE_X166Y357 FDCE r ngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[28]/C clock pessimism -0.120 0.414 SLICE_X166Y357 FDCE (Remov_fdce_C_CLR) -0.050 0.364 ngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[28] ------------------------------------------------------------------- required time -0.364 arrival time 0.745 ------------------------------------------------------------------- slack 0.381 Slack (MET) : 0.381ns (arrival time - required time) Source: ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[29]/CLR (removal check against rising-edge clock rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_3 rise@0.000ns - rxWordclkl12_3 rise@0.000ns) Data Path Delay: 0.395ns (logic 0.118ns (29.882%) route 0.277ns (70.118%)) Logic Levels: 0 Clock Path Skew: 0.064ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.534ns Source Clock Delay (SCD): 0.350ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.350 0.350 ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X162Y363 FDRE r ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X162Y363 FDRE (Prop_fdre_C_Q) 0.118 0.468 f ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.277 0.745 ngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/AR[0] SLICE_X166Y357 FDCE f ngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[29]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.534 0.534 ngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] SLICE_X166Y357 FDCE r ngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[29]/C clock pessimism -0.120 0.414 SLICE_X166Y357 FDCE (Remov_fdce_C_CLR) -0.050 0.364 ngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[29] ------------------------------------------------------------------- required time -0.364 arrival time 0.745 ------------------------------------------------------------------- slack 0.381 Slack (MET) : 0.381ns (arrival time - required time) Source: ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[30]/CLR (removal check against rising-edge clock rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_3 rise@0.000ns - rxWordclkl12_3 rise@0.000ns) Data Path Delay: 0.395ns (logic 0.118ns (29.882%) route 0.277ns (70.118%)) Logic Levels: 0 Clock Path Skew: 0.064ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.534ns Source Clock Delay (SCD): 0.350ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.350 0.350 ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X162Y363 FDRE r ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X162Y363 FDRE (Prop_fdre_C_Q) 0.118 0.468 f ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.277 0.745 ngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/AR[0] SLICE_X166Y357 FDCE f ngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[30]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.534 0.534 ngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] SLICE_X166Y357 FDCE r ngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[30]/C clock pessimism -0.120 0.414 SLICE_X166Y357 FDCE (Remov_fdce_C_CLR) -0.050 0.364 ngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[30] ------------------------------------------------------------------- required time -0.364 arrival time 0.745 ------------------------------------------------------------------- slack 0.381 Slack (MET) : 0.381ns (arrival time - required time) Source: ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[31]/CLR (removal check against rising-edge clock rxWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_3 rise@0.000ns - rxWordclkl12_3 rise@0.000ns) Data Path Delay: 0.395ns (logic 0.118ns (29.882%) route 0.277ns (70.118%)) Logic Levels: 0 Clock Path Skew: 0.064ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.534ns Source Clock Delay (SCD): 0.350ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.350 0.350 ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X162Y363 FDRE r ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X162Y363 FDRE (Prop_fdre_C_Q) 0.118 0.468 f ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.277 0.745 ngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/AR[0] SLICE_X166Y357 FDCE f ngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[31]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_3 rise edge) 0.000 0.000 r BUFHCE_X1Y86 BUFH 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.534 0.534 ngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] SLICE_X166Y357 FDCE r ngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[31]/C clock pessimism -0.120 0.414 SLICE_X166Y357 FDCE (Remov_fdce_C_CLR) -0.050 0.364 ngFEC/SFP_GEN[4].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[31] ------------------------------------------------------------------- required time -0.364 arrival time 0.745 ------------------------------------------------------------------- slack 0.381 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: rxWordclkl12_4 To Clock: rxWordclkl12_4 Setup : 0 Failing Endpoints, Worst Slack 5.093ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.295ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.093ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r3_reg[1]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR (recovery check against rising-edge clock rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_4 rise@8.200ns - rxWordclkl12_4 rise@0.000ns) Data Path Delay: 2.682ns (logic 0.349ns (13.011%) route 2.333ns (86.989%)) Logic Levels: 2 (LUT1=1 LUT3=1) Clock Path Skew: -0.086ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.648ns = ( 8.848 - 8.200 ) Source Clock Delay (SCD): 0.734ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.734 0.734 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/CLK SLICE_X170Y319 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r3_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X170Y319 FDCE (Prop_fdce_C_Q) 0.259 0.993 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r3_reg[1]/Q net (fo=1, routed) 0.329 1.322 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r3_reg_n_0_[1] SLICE_X172Y319 LUT3 (Prop_lut3_I2_O) 0.043 1.365 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/g_rx_frameclk_lock_cnt[0].rx_frameclk_lock_Sync_inst_i_1/O net (fo=8, routed) 1.510 2.875 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/DONE_o_reg_0 SLICE_X162Y299 LUT1 (Prop_lut1_I0_O) 0.047 2.922 f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/mgtRxReady_s_i_1__2/O net (fo=2, routed) 0.494 3.416 ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X159Y302 FDCE f ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 8.200 8.200 r BUFHCE_X1Y72 BUFH 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.648 8.848 ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X159Y302 FDCE r ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg/C clock pessimism 0.000 8.848 clock uncertainty -0.035 8.813 SLICE_X159Y302 FDCE (Recov_fdce_C_CLR) -0.303 8.510 ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_s_reg ------------------------------------------------------------------- required time 8.510 arrival time -3.416 ------------------------------------------------------------------- slack 5.093 Slack (MET) : 5.093ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r3_reg[1]/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR (recovery check against rising-edge clock rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_4 rise@8.200ns - rxWordclkl12_4 rise@0.000ns) Data Path Delay: 2.682ns (logic 0.349ns (13.011%) route 2.333ns (86.989%)) Logic Levels: 2 (LUT1=1 LUT3=1) Clock Path Skew: -0.086ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.648ns = ( 8.848 - 8.200 ) Source Clock Delay (SCD): 0.734ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.734 0.734 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/CLK SLICE_X170Y319 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r3_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X170Y319 FDCE (Prop_fdce_C_Q) 0.259 0.993 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r3_reg[1]/Q net (fo=1, routed) 0.329 1.322 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r3_reg_n_0_[1] SLICE_X172Y319 LUT3 (Prop_lut3_I2_O) 0.043 1.365 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/g_rx_frameclk_lock_cnt[0].rx_frameclk_lock_Sync_inst_i_1/O net (fo=8, routed) 1.510 2.875 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/DONE_o_reg_0 SLICE_X162Y299 LUT1 (Prop_lut1_I0_O) 0.047 2.922 f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/mgtRxReady_s_i_1__2/O net (fo=2, routed) 0.494 3.416 ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg_0 SLICE_X159Y302 FDCE f ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 8.200 8.200 r BUFHCE_X1Y72 BUFH 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.648 8.848 ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X159Y302 FDCE r ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C clock pessimism 0.000 8.848 clock uncertainty -0.035 8.813 SLICE_X159Y302 FDCE (Recov_fdce_C_CLR) -0.303 8.510 ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg ------------------------------------------------------------------- required time 8.510 arrival time -3.416 ------------------------------------------------------------------- slack 5.093 Slack (MET) : 5.172ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR (recovery check against rising-edge clock rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_4 rise@8.200ns - rxWordclkl12_4 rise@0.000ns) Data Path Delay: 2.596ns (logic 0.365ns (14.062%) route 2.231ns (85.938%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.096ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.635ns = ( 8.835 - 8.200 ) Source Clock Delay (SCD): 0.731ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.731 0.731 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X170Y321 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X170Y321 FDCE (Prop_fdce_C_Q) 0.236 0.967 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=3, routed) 0.330 1.297 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg_0 SLICE_X170Y320 LUT1 (Prop_lut1_I0_O) 0.129 1.426 f ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__8/O net (fo=80, routed) 1.901 3.327 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X155Y321 FDCE f ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 8.200 8.200 r BUFHCE_X1Y72 BUFH 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.635 8.835 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X155Y321 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0]/C clock pessimism 0.000 8.835 clock uncertainty -0.035 8.800 SLICE_X155Y321 FDCE (Recov_fdce_C_CLR) -0.301 8.499 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[0] ------------------------------------------------------------------- required time 8.499 arrival time -3.327 ------------------------------------------------------------------- slack 5.172 Slack (MET) : 5.172ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR (recovery check against rising-edge clock rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_4 rise@8.200ns - rxWordclkl12_4 rise@0.000ns) Data Path Delay: 2.596ns (logic 0.365ns (14.062%) route 2.231ns (85.938%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.096ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.635ns = ( 8.835 - 8.200 ) Source Clock Delay (SCD): 0.731ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.731 0.731 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X170Y321 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X170Y321 FDCE (Prop_fdce_C_Q) 0.236 0.967 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=3, routed) 0.330 1.297 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg_0 SLICE_X170Y320 LUT1 (Prop_lut1_I0_O) 0.129 1.426 f ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__8/O net (fo=80, routed) 1.901 3.327 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X155Y321 FDCE f ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 8.200 8.200 r BUFHCE_X1Y72 BUFH 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.635 8.835 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X155Y321 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C clock pessimism 0.000 8.835 clock uncertainty -0.035 8.800 SLICE_X155Y321 FDCE (Recov_fdce_C_CLR) -0.301 8.499 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[19] ------------------------------------------------------------------- required time 8.499 arrival time -3.327 ------------------------------------------------------------------- slack 5.172 Slack (MET) : 5.172ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR (recovery check against rising-edge clock rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_4 rise@8.200ns - rxWordclkl12_4 rise@0.000ns) Data Path Delay: 2.596ns (logic 0.365ns (14.062%) route 2.231ns (85.938%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.096ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.635ns = ( 8.835 - 8.200 ) Source Clock Delay (SCD): 0.731ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.731 0.731 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X170Y321 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X170Y321 FDCE (Prop_fdce_C_Q) 0.236 0.967 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=3, routed) 0.330 1.297 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg_0 SLICE_X170Y320 LUT1 (Prop_lut1_I0_O) 0.129 1.426 f ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__8/O net (fo=80, routed) 1.901 3.327 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X155Y321 FDCE f ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 8.200 8.200 r BUFHCE_X1Y72 BUFH 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.635 8.835 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X155Y321 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9]/C clock pessimism 0.000 8.835 clock uncertainty -0.035 8.800 SLICE_X155Y321 FDCE (Recov_fdce_C_CLR) -0.301 8.499 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[9] ------------------------------------------------------------------- required time 8.499 arrival time -3.327 ------------------------------------------------------------------- slack 5.172 Slack (MET) : 5.281ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r2_reg[1]/CLR (recovery check against rising-edge clock rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_4 rise@8.200ns - rxWordclkl12_4 rise@0.000ns) Data Path Delay: 2.505ns (logic 1.052ns (41.995%) route 1.453ns (58.005%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.687ns = ( 8.887 - 8.200 ) Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.911 0.911 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.920 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 0.847 2.768 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/rx_reset_done[1] SLICE_X170Y319 LUT1 (Prop_lut1_I0_O) 0.043 2.811 f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r[1]_i_1__0/O net (fo=3, routed) 0.606 3.417 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r[1]_i_1__0_n_0 SLICE_X170Y319 FDCE f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r2_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 8.200 8.200 r BUFHCE_X1Y72 BUFH 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.687 8.887 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/CLK SLICE_X170Y319 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r2_reg[1]/C clock pessimism 0.000 8.887 clock uncertainty -0.035 8.852 SLICE_X170Y319 FDCE (Recov_fdce_C_CLR) -0.154 8.698 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r2_reg[1] ------------------------------------------------------------------- required time 8.698 arrival time -3.417 ------------------------------------------------------------------- slack 5.281 Slack (MET) : 5.281ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r3_reg[1]/CLR (recovery check against rising-edge clock rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_4 rise@8.200ns - rxWordclkl12_4 rise@0.000ns) Data Path Delay: 2.505ns (logic 1.052ns (41.995%) route 1.453ns (58.005%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.687ns = ( 8.887 - 8.200 ) Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.911 0.911 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.920 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 0.847 2.768 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/rx_reset_done[1] SLICE_X170Y319 LUT1 (Prop_lut1_I0_O) 0.043 2.811 f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r[1]_i_1__0/O net (fo=3, routed) 0.606 3.417 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r[1]_i_1__0_n_0 SLICE_X170Y319 FDCE f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r3_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 8.200 8.200 r BUFHCE_X1Y72 BUFH 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.687 8.887 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/CLK SLICE_X170Y319 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r3_reg[1]/C clock pessimism 0.000 8.887 clock uncertainty -0.035 8.852 SLICE_X170Y319 FDCE (Recov_fdce_C_CLR) -0.154 8.698 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r3_reg[1] ------------------------------------------------------------------- required time 8.698 arrival time -3.417 ------------------------------------------------------------------- slack 5.281 Slack (MET) : 5.281ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r_reg[1]/CLR (recovery check against rising-edge clock rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_4 rise@8.200ns - rxWordclkl12_4 rise@0.000ns) Data Path Delay: 2.505ns (logic 1.052ns (41.995%) route 1.453ns (58.005%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.687ns = ( 8.887 - 8.200 ) Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.911 0.911 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.920 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 0.847 2.768 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/rx_reset_done[1] SLICE_X170Y319 LUT1 (Prop_lut1_I0_O) 0.043 2.811 f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r[1]_i_1__0/O net (fo=3, routed) 0.606 3.417 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r[1]_i_1__0_n_0 SLICE_X170Y319 FDCE f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 8.200 8.200 r BUFHCE_X1Y72 BUFH 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.687 8.887 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/CLK SLICE_X170Y319 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r_reg[1]/C clock pessimism 0.000 8.887 clock uncertainty -0.035 8.852 SLICE_X170Y319 FDCE (Recov_fdce_C_CLR) -0.154 8.698 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r_reg[1] ------------------------------------------------------------------- required time 8.698 arrival time -3.417 ------------------------------------------------------------------- slack 5.281 Slack (MET) : 5.325ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR (recovery check against rising-edge clock rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_4 rise@8.200ns - rxWordclkl12_4 rise@0.000ns) Data Path Delay: 2.500ns (logic 0.365ns (14.603%) route 2.135ns (85.397%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.097ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.634ns = ( 8.834 - 8.200 ) Source Clock Delay (SCD): 0.731ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.731 0.731 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X170Y321 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X170Y321 FDCE (Prop_fdce_C_Q) 0.236 0.967 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=3, routed) 0.330 1.297 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg_0 SLICE_X170Y320 LUT1 (Prop_lut1_I0_O) 0.129 1.426 f ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__8/O net (fo=80, routed) 1.805 3.231 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X150Y321 FDCE f ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 8.200 8.200 r BUFHCE_X1Y72 BUFH 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.634 8.834 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X150Y321 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20]/C clock pessimism 0.000 8.834 clock uncertainty -0.035 8.799 SLICE_X150Y321 FDCE (Recov_fdce_C_CLR) -0.243 8.556 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[20] ------------------------------------------------------------------- required time 8.556 arrival time -3.231 ------------------------------------------------------------------- slack 5.325 Slack (MET) : 5.369ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR (recovery check against rising-edge clock rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_4 rise@8.200ns - rxWordclkl12_4 rise@0.000ns) Data Path Delay: 2.401ns (logic 0.365ns (15.205%) route 2.036ns (84.795%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.094ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.637ns = ( 8.837 - 8.200 ) Source Clock Delay (SCD): 0.731ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.731 0.731 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X170Y321 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X170Y321 FDCE (Prop_fdce_C_Q) 0.236 0.967 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=3, routed) 0.330 1.297 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg_0 SLICE_X170Y320 LUT1 (Prop_lut1_I0_O) 0.129 1.426 f ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__8/O net (fo=80, routed) 1.706 3.132 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/AR[0] SLICE_X151Y319 FDCE f ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 8.200 8.200 r BUFHCE_X1Y72 BUFH 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.637 8.837 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/CLK SLICE_X151Y319 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17]/C clock pessimism 0.000 8.837 clock uncertainty -0.035 8.802 SLICE_X151Y319 FDCE (Recov_fdce_C_CLR) -0.301 8.501 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[0].gbtRxDescrambler21bit/feedbackRegister_reg[17] ------------------------------------------------------------------- required time 8.501 arrival time -3.132 ------------------------------------------------------------------- slack 5.369 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.295ns (arrival time - required time) Source: ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[28]/CLR (removal check against rising-edge clock rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_4 rise@0.000ns - rxWordclkl12_4 rise@0.000ns) Data Path Delay: 0.280ns (logic 0.100ns (35.735%) route 0.180ns (64.265%)) Logic Levels: 0 Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.507ns Source Clock Delay (SCD): 0.352ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.352 0.352 ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X159Y307 FDRE r ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X159Y307 FDRE (Prop_fdre_C_Q) 0.100 0.452 f ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.180 0.632 ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/AR[0] SLICE_X162Y307 FDCE f ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[28]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.507 0.507 ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] SLICE_X162Y307 FDCE r ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[28]/C clock pessimism -0.120 0.387 SLICE_X162Y307 FDCE (Remov_fdce_C_CLR) -0.050 0.337 ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[28] ------------------------------------------------------------------- required time -0.337 arrival time 0.632 ------------------------------------------------------------------- slack 0.295 Slack (MET) : 0.295ns (arrival time - required time) Source: ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[29]/CLR (removal check against rising-edge clock rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_4 rise@0.000ns - rxWordclkl12_4 rise@0.000ns) Data Path Delay: 0.280ns (logic 0.100ns (35.735%) route 0.180ns (64.265%)) Logic Levels: 0 Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.507ns Source Clock Delay (SCD): 0.352ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.352 0.352 ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X159Y307 FDRE r ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X159Y307 FDRE (Prop_fdre_C_Q) 0.100 0.452 f ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.180 0.632 ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/AR[0] SLICE_X162Y307 FDCE f ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[29]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.507 0.507 ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] SLICE_X162Y307 FDCE r ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[29]/C clock pessimism -0.120 0.387 SLICE_X162Y307 FDCE (Remov_fdce_C_CLR) -0.050 0.337 ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[29] ------------------------------------------------------------------- required time -0.337 arrival time 0.632 ------------------------------------------------------------------- slack 0.295 Slack (MET) : 0.295ns (arrival time - required time) Source: ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[30]/CLR (removal check against rising-edge clock rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_4 rise@0.000ns - rxWordclkl12_4 rise@0.000ns) Data Path Delay: 0.280ns (logic 0.100ns (35.735%) route 0.180ns (64.265%)) Logic Levels: 0 Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.507ns Source Clock Delay (SCD): 0.352ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.352 0.352 ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X159Y307 FDRE r ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X159Y307 FDRE (Prop_fdre_C_Q) 0.100 0.452 f ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.180 0.632 ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/AR[0] SLICE_X162Y307 FDCE f ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[30]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.507 0.507 ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] SLICE_X162Y307 FDCE r ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[30]/C clock pessimism -0.120 0.387 SLICE_X162Y307 FDCE (Remov_fdce_C_CLR) -0.050 0.337 ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[30] ------------------------------------------------------------------- required time -0.337 arrival time 0.632 ------------------------------------------------------------------- slack 0.295 Slack (MET) : 0.295ns (arrival time - required time) Source: ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[31]/CLR (removal check against rising-edge clock rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_4 rise@0.000ns - rxWordclkl12_4 rise@0.000ns) Data Path Delay: 0.280ns (logic 0.100ns (35.735%) route 0.180ns (64.265%)) Logic Levels: 0 Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.507ns Source Clock Delay (SCD): 0.352ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.352 0.352 ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X159Y307 FDRE r ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X159Y307 FDRE (Prop_fdre_C_Q) 0.100 0.452 f ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.180 0.632 ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/AR[0] SLICE_X162Y307 FDCE f ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[31]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.507 0.507 ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] SLICE_X162Y307 FDCE r ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[31]/C clock pessimism -0.120 0.387 SLICE_X162Y307 FDCE (Remov_fdce_C_CLR) -0.050 0.337 ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[31] ------------------------------------------------------------------- required time -0.337 arrival time 0.632 ------------------------------------------------------------------- slack 0.295 Slack (MET) : 0.334ns (arrival time - required time) Source: ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[24]/CLR (removal check against rising-edge clock rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_4 rise@0.000ns - rxWordclkl12_4 rise@0.000ns) Data Path Delay: 0.320ns (logic 0.100ns (31.294%) route 0.220ns (68.706%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.508ns Source Clock Delay (SCD): 0.352ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.352 0.352 ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X159Y307 FDRE r ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X159Y307 FDRE (Prop_fdre_C_Q) 0.100 0.452 f ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.220 0.672 ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/AR[0] SLICE_X162Y306 FDCE f ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[24]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.508 0.508 ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] SLICE_X162Y306 FDCE r ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[24]/C clock pessimism -0.120 0.388 SLICE_X162Y306 FDCE (Remov_fdce_C_CLR) -0.050 0.338 ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[24] ------------------------------------------------------------------- required time -0.338 arrival time 0.672 ------------------------------------------------------------------- slack 0.334 Slack (MET) : 0.334ns (arrival time - required time) Source: ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[25]/CLR (removal check against rising-edge clock rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_4 rise@0.000ns - rxWordclkl12_4 rise@0.000ns) Data Path Delay: 0.320ns (logic 0.100ns (31.294%) route 0.220ns (68.706%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.508ns Source Clock Delay (SCD): 0.352ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.352 0.352 ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X159Y307 FDRE r ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X159Y307 FDRE (Prop_fdre_C_Q) 0.100 0.452 f ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.220 0.672 ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/AR[0] SLICE_X162Y306 FDCE f ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[25]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.508 0.508 ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] SLICE_X162Y306 FDCE r ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[25]/C clock pessimism -0.120 0.388 SLICE_X162Y306 FDCE (Remov_fdce_C_CLR) -0.050 0.338 ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[25] ------------------------------------------------------------------- required time -0.338 arrival time 0.672 ------------------------------------------------------------------- slack 0.334 Slack (MET) : 0.334ns (arrival time - required time) Source: ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[26]/CLR (removal check against rising-edge clock rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_4 rise@0.000ns - rxWordclkl12_4 rise@0.000ns) Data Path Delay: 0.320ns (logic 0.100ns (31.294%) route 0.220ns (68.706%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.508ns Source Clock Delay (SCD): 0.352ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.352 0.352 ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X159Y307 FDRE r ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X159Y307 FDRE (Prop_fdre_C_Q) 0.100 0.452 f ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.220 0.672 ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/AR[0] SLICE_X162Y306 FDCE f ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[26]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.508 0.508 ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] SLICE_X162Y306 FDCE r ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[26]/C clock pessimism -0.120 0.388 SLICE_X162Y306 FDCE (Remov_fdce_C_CLR) -0.050 0.338 ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[26] ------------------------------------------------------------------- required time -0.338 arrival time 0.672 ------------------------------------------------------------------- slack 0.334 Slack (MET) : 0.334ns (arrival time - required time) Source: ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[27]/CLR (removal check against rising-edge clock rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_4 rise@0.000ns - rxWordclkl12_4 rise@0.000ns) Data Path Delay: 0.320ns (logic 0.100ns (31.294%) route 0.220ns (68.706%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.508ns Source Clock Delay (SCD): 0.352ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.352 0.352 ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X159Y307 FDRE r ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X159Y307 FDRE (Prop_fdre_C_Q) 0.100 0.452 f ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.220 0.672 ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/AR[0] SLICE_X162Y306 FDCE f ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[27]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.508 0.508 ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] SLICE_X162Y306 FDCE r ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[27]/C clock pessimism -0.120 0.388 SLICE_X162Y306 FDCE (Remov_fdce_C_CLR) -0.050 0.338 ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[27] ------------------------------------------------------------------- required time -0.338 arrival time 0.672 ------------------------------------------------------------------- slack 0.334 Slack (MET) : 0.383ns (arrival time - required time) Source: ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[20]/CLR (removal check against rising-edge clock rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_4 rise@0.000ns - rxWordclkl12_4 rise@0.000ns) Data Path Delay: 0.369ns (logic 0.100ns (27.129%) route 0.269ns (72.871%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.508ns Source Clock Delay (SCD): 0.352ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.352 0.352 ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X159Y307 FDRE r ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X159Y307 FDRE (Prop_fdre_C_Q) 0.100 0.452 f ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.269 0.721 ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/AR[0] SLICE_X162Y305 FDCE f ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[20]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.508 0.508 ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] SLICE_X162Y305 FDCE r ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[20]/C clock pessimism -0.120 0.388 SLICE_X162Y305 FDCE (Remov_fdce_C_CLR) -0.050 0.338 ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[20] ------------------------------------------------------------------- required time -0.338 arrival time 0.721 ------------------------------------------------------------------- slack 0.383 Slack (MET) : 0.383ns (arrival time - required time) Source: ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[21]/CLR (removal check against rising-edge clock rxWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_4 rise@0.000ns - rxWordclkl12_4 rise@0.000ns) Data Path Delay: 0.369ns (logic 0.100ns (27.129%) route 0.269ns (72.871%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.508ns Source Clock Delay (SCD): 0.352ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.352 0.352 ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X159Y307 FDRE r ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X159Y307 FDRE (Prop_fdre_C_Q) 0.100 0.452 f ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.269 0.721 ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/AR[0] SLICE_X162Y305 FDCE f ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[21]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_4 rise edge) 0.000 0.000 r BUFHCE_X1Y72 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.508 0.508 ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] SLICE_X162Y305 FDCE r ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[21]/C clock pessimism -0.120 0.388 SLICE_X162Y305 FDCE (Remov_fdce_C_CLR) -0.050 0.338 ngFEC/SFP_GEN[1].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[21] ------------------------------------------------------------------- required time -0.338 arrival time 0.721 ------------------------------------------------------------------- slack 0.383 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: rxWordclkl12_5 To Clock: rxWordclkl12_5 Setup : 0 Failing Endpoints, Worst Slack 4.879ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.302ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.879ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxResetDone_r2_reg[2]/CLR (recovery check against rising-edge clock rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_5 rise@8.200ns - rxWordclkl12_5 rise@0.000ns) Data Path Delay: 2.756ns (logic 1.058ns (38.390%) route 1.698ns (61.610%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.228ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.693ns = ( 8.893 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.921 0.921 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.930 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.071 3.001 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/rx_reset_done[2] SLICE_X170Y310 LUT1 (Prop_lut1_I0_O) 0.049 3.050 f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxResetDone_r[2]_i_1__0/O net (fo=3, routed) 0.627 3.677 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxResetDone_r[2]_i_1__0_n_0 SLICE_X171Y310 FDCE f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxResetDone_r2_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 8.200 8.200 r BUFHCE_X1Y73 BUFH 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.693 8.893 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out SLICE_X171Y310 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxResetDone_r2_reg[2]/C clock pessimism 0.000 8.893 clock uncertainty -0.035 8.858 SLICE_X171Y310 FDCE (Recov_fdce_C_CLR) -0.301 8.557 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxResetDone_r2_reg[2] ------------------------------------------------------------------- required time 8.557 arrival time -3.677 ------------------------------------------------------------------- slack 4.879 Slack (MET) : 4.879ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxResetDone_r3_reg[2]/CLR (recovery check against rising-edge clock rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_5 rise@8.200ns - rxWordclkl12_5 rise@0.000ns) Data Path Delay: 2.756ns (logic 1.058ns (38.390%) route 1.698ns (61.610%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.228ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.693ns = ( 8.893 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.921 0.921 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.930 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.071 3.001 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/rx_reset_done[2] SLICE_X170Y310 LUT1 (Prop_lut1_I0_O) 0.049 3.050 f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxResetDone_r[2]_i_1__0/O net (fo=3, routed) 0.627 3.677 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxResetDone_r[2]_i_1__0_n_0 SLICE_X171Y310 FDCE f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxResetDone_r3_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 8.200 8.200 r BUFHCE_X1Y73 BUFH 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.693 8.893 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out SLICE_X171Y310 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxResetDone_r3_reg[2]/C clock pessimism 0.000 8.893 clock uncertainty -0.035 8.858 SLICE_X171Y310 FDCE (Recov_fdce_C_CLR) -0.301 8.557 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxResetDone_r3_reg[2] ------------------------------------------------------------------- required time 8.557 arrival time -3.677 ------------------------------------------------------------------- slack 4.879 Slack (MET) : 4.879ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxResetDone_r_reg[2]/CLR (recovery check against rising-edge clock rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_5 rise@8.200ns - rxWordclkl12_5 rise@0.000ns) Data Path Delay: 2.756ns (logic 1.058ns (38.390%) route 1.698ns (61.610%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.228ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.693ns = ( 8.893 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.921 0.921 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.930 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.071 3.001 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/rx_reset_done[2] SLICE_X170Y310 LUT1 (Prop_lut1_I0_O) 0.049 3.050 f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxResetDone_r[2]_i_1__0/O net (fo=3, routed) 0.627 3.677 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxResetDone_r[2]_i_1__0_n_0 SLICE_X171Y310 FDCE f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxResetDone_r_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 8.200 8.200 r BUFHCE_X1Y73 BUFH 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.693 8.893 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out SLICE_X171Y310 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxResetDone_r_reg[2]/C clock pessimism 0.000 8.893 clock uncertainty -0.035 8.858 SLICE_X171Y310 FDCE (Recov_fdce_C_CLR) -0.301 8.557 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxResetDone_r_reg[2] ------------------------------------------------------------------- required time 8.557 arrival time -3.677 ------------------------------------------------------------------- slack 4.879 Slack (MET) : 4.919ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR (recovery check against rising-edge clock rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_5 rise@8.200ns - rxWordclkl12_5 rise@0.000ns) Data Path Delay: 2.888ns (logic 0.270ns (9.348%) route 2.618ns (90.652%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.054ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.694ns = ( 8.894 - 8.200 ) Source Clock Delay (SCD): 0.748ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.748 0.748 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X177Y306 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X177Y306 FDCE (Prop_fdce_C_Q) 0.223 0.971 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=3, routed) 0.776 1.747 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg_0 SLICE_X170Y306 LUT1 (Prop_lut1_I0_O) 0.047 1.794 f ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__7/O net (fo=80, routed) 1.843 3.636 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/AR[0] SLICE_X168Y309 FDCE f ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 8.200 8.200 r BUFHCE_X1Y73 BUFH 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.694 8.894 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/CLK SLICE_X168Y309 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg/C clock pessimism 0.000 8.894 clock uncertainty -0.035 8.859 SLICE_X168Y309 FDCE (Recov_fdce_C_CLR) -0.303 8.556 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/RX_ISDATA_FLAG_O_reg ------------------------------------------------------------------- required time 8.556 arrival time -3.636 ------------------------------------------------------------------- slack 4.919 Slack (MET) : 5.217ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (recovery check against rising-edge clock rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_5 rise@8.200ns - rxWordclkl12_5 rise@0.000ns) Data Path Delay: 2.650ns (logic 0.270ns (10.188%) route 2.380ns (89.812%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.053ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.695ns = ( 8.895 - 8.200 ) Source Clock Delay (SCD): 0.748ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.748 0.748 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X177Y306 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X177Y306 FDCE (Prop_fdce_C_Q) 0.223 0.971 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=3, routed) 0.776 1.747 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg_0 SLICE_X170Y306 LUT1 (Prop_lut1_I0_O) 0.047 1.794 f ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__7/O net (fo=80, routed) 1.604 3.398 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X166Y304 FDCE f ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 8.200 8.200 r BUFHCE_X1Y73 BUFH 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.695 8.895 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X166Y304 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C clock pessimism 0.000 8.895 clock uncertainty -0.035 8.860 SLICE_X166Y304 FDCE (Recov_fdce_C_CLR) -0.245 8.615 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[2] ------------------------------------------------------------------- required time 8.615 arrival time -3.398 ------------------------------------------------------------------- slack 5.217 Slack (MET) : 5.217ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR (recovery check against rising-edge clock rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_5 rise@8.200ns - rxWordclkl12_5 rise@0.000ns) Data Path Delay: 2.650ns (logic 0.270ns (10.188%) route 2.380ns (89.812%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.053ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.695ns = ( 8.895 - 8.200 ) Source Clock Delay (SCD): 0.748ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.748 0.748 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X177Y306 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X177Y306 FDCE (Prop_fdce_C_Q) 0.223 0.971 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=3, routed) 0.776 1.747 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg_0 SLICE_X170Y306 LUT1 (Prop_lut1_I0_O) 0.047 1.794 f ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__7/O net (fo=80, routed) 1.604 3.398 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X166Y304 FDCE f ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 8.200 8.200 r BUFHCE_X1Y73 BUFH 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.695 8.895 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X166Y304 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C clock pessimism 0.000 8.895 clock uncertainty -0.035 8.860 SLICE_X166Y304 FDCE (Recov_fdce_C_CLR) -0.245 8.615 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[4] ------------------------------------------------------------------- required time 8.615 arrival time -3.398 ------------------------------------------------------------------- slack 5.217 Slack (MET) : 5.217ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR (recovery check against rising-edge clock rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_5 rise@8.200ns - rxWordclkl12_5 rise@0.000ns) Data Path Delay: 2.650ns (logic 0.270ns (10.188%) route 2.380ns (89.812%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.053ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.695ns = ( 8.895 - 8.200 ) Source Clock Delay (SCD): 0.748ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.748 0.748 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X177Y306 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X177Y306 FDCE (Prop_fdce_C_Q) 0.223 0.971 r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=3, routed) 0.776 1.747 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg_0 SLICE_X170Y306 LUT1 (Prop_lut1_I0_O) 0.047 1.794 f ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__7/O net (fo=80, routed) 1.604 3.398 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X166Y304 FDCE f ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 8.200 8.200 r BUFHCE_X1Y73 BUFH 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.695 8.895 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X166Y304 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C clock pessimism 0.000 8.895 clock uncertainty -0.035 8.860 SLICE_X166Y304 FDCE (Recov_fdce_C_CLR) -0.245 8.615 ngFEC/gbtbank2_l12_117/gbt_inst/gbt_rxdatapath_multilink_gen[2].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[6] ------------------------------------------------------------------- required time 8.615 arrival time -3.398 ------------------------------------------------------------------- slack 5.217 Slack (MET) : 5.325ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[0]/CLR (recovery check against rising-edge clock rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_5 rise@8.200ns - rxWordclkl12_5 rise@0.000ns) Data Path Delay: 2.403ns (logic 1.052ns (43.770%) route 1.351ns (56.230%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.697ns = ( 8.897 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.921 0.921 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.930 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 0.833 2.763 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] SLICE_X176Y310 LUT2 (Prop_lut2_I0_O) 0.043 2.806 f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__0/O net (fo=25, routed) 0.518 3.325 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_0 SLICE_X181Y310 FDCE f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 8.200 8.200 r BUFHCE_X1Y73 BUFH 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.697 8.897 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK SLICE_X181Y310 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[0]/C clock pessimism 0.000 8.897 clock uncertainty -0.035 8.862 SLICE_X181Y310 FDCE (Recov_fdce_C_CLR) -0.212 8.650 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[0] ------------------------------------------------------------------- required time 8.650 arrival time -3.325 ------------------------------------------------------------------- slack 5.325 Slack (MET) : 5.325ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[1]/CLR (recovery check against rising-edge clock rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_5 rise@8.200ns - rxWordclkl12_5 rise@0.000ns) Data Path Delay: 2.403ns (logic 1.052ns (43.770%) route 1.351ns (56.230%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.697ns = ( 8.897 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.921 0.921 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.930 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 0.833 2.763 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] SLICE_X176Y310 LUT2 (Prop_lut2_I0_O) 0.043 2.806 f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__0/O net (fo=25, routed) 0.518 3.325 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_0 SLICE_X181Y310 FDCE f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 8.200 8.200 r BUFHCE_X1Y73 BUFH 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.697 8.897 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK SLICE_X181Y310 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[1]/C clock pessimism 0.000 8.897 clock uncertainty -0.035 8.862 SLICE_X181Y310 FDCE (Recov_fdce_C_CLR) -0.212 8.650 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[1] ------------------------------------------------------------------- required time 8.650 arrival time -3.325 ------------------------------------------------------------------- slack 5.325 Slack (MET) : 5.325ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[2]/CLR (recovery check against rising-edge clock rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_5 rise@8.200ns - rxWordclkl12_5 rise@0.000ns) Data Path Delay: 2.403ns (logic 1.052ns (43.770%) route 1.351ns (56.230%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.697ns = ( 8.897 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.921 0.921 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.930 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 0.833 2.763 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] SLICE_X176Y310 LUT2 (Prop_lut2_I0_O) 0.043 2.806 f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__0/O net (fo=25, routed) 0.518 3.325 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_0 SLICE_X181Y310 FDCE f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 8.200 8.200 r BUFHCE_X1Y73 BUFH 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.697 8.897 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK SLICE_X181Y310 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[2]/C clock pessimism 0.000 8.897 clock uncertainty -0.035 8.862 SLICE_X181Y310 FDCE (Recov_fdce_C_CLR) -0.212 8.650 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[2] ------------------------------------------------------------------- required time 8.650 arrival time -3.325 ------------------------------------------------------------------- slack 5.325 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.302ns (arrival time - required time) Source: ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR (removal check against rising-edge clock rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_5 rise@0.000ns - rxWordclkl12_5 rise@0.000ns) Data Path Delay: 0.269ns (logic 0.100ns (37.203%) route 0.169ns (62.797%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.509ns Source Clock Delay (SCD): 0.353ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.353 0.353 ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X161Y303 FDRE r ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X161Y303 FDRE (Prop_fdre_C_Q) 0.100 0.453 f ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.169 0.622 ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Reset SLICE_X163Y302 FDCE f ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.509 0.509 ngFEC/SFP_GEN[9].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X163Y302 FDCE r ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[21]/C clock pessimism -0.120 0.389 SLICE_X163Y302 FDCE (Remov_fdce_C_CLR) -0.069 0.320 ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[21] ------------------------------------------------------------------- required time -0.320 arrival time 0.622 ------------------------------------------------------------------- slack 0.302 Slack (MET) : 0.302ns (arrival time - required time) Source: ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR (removal check against rising-edge clock rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_5 rise@0.000ns - rxWordclkl12_5 rise@0.000ns) Data Path Delay: 0.269ns (logic 0.100ns (37.203%) route 0.169ns (62.797%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.509ns Source Clock Delay (SCD): 0.353ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.353 0.353 ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X161Y303 FDRE r ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X161Y303 FDRE (Prop_fdre_C_Q) 0.100 0.453 f ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.169 0.622 ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Reset SLICE_X163Y302 FDCE f ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.509 0.509 ngFEC/SFP_GEN[9].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X163Y302 FDCE r ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[23]/C clock pessimism -0.120 0.389 SLICE_X163Y302 FDCE (Remov_fdce_C_CLR) -0.069 0.320 ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[23] ------------------------------------------------------------------- required time -0.320 arrival time 0.622 ------------------------------------------------------------------- slack 0.302 Slack (MET) : 0.302ns (arrival time - required time) Source: ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[44]/CLR (removal check against rising-edge clock rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_5 rise@0.000ns - rxWordclkl12_5 rise@0.000ns) Data Path Delay: 0.269ns (logic 0.100ns (37.203%) route 0.169ns (62.797%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.509ns Source Clock Delay (SCD): 0.353ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.353 0.353 ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X161Y303 FDRE r ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X161Y303 FDRE (Prop_fdre_C_Q) 0.100 0.453 f ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.169 0.622 ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Reset SLICE_X163Y302 FDCE f ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[44]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.509 0.509 ngFEC/SFP_GEN[9].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X163Y302 FDCE r ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[44]/C clock pessimism -0.120 0.389 SLICE_X163Y302 FDCE (Remov_fdce_C_CLR) -0.069 0.320 ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[44] ------------------------------------------------------------------- required time -0.320 arrival time 0.622 ------------------------------------------------------------------- slack 0.302 Slack (MET) : 0.302ns (arrival time - required time) Source: ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[50]/CLR (removal check against rising-edge clock rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_5 rise@0.000ns - rxWordclkl12_5 rise@0.000ns) Data Path Delay: 0.269ns (logic 0.100ns (37.203%) route 0.169ns (62.797%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.509ns Source Clock Delay (SCD): 0.353ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.353 0.353 ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X161Y303 FDRE r ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X161Y303 FDRE (Prop_fdre_C_Q) 0.100 0.453 f ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.169 0.622 ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Reset SLICE_X163Y302 FDCE f ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[50]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.509 0.509 ngFEC/SFP_GEN[9].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X163Y302 FDCE r ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[50]/C clock pessimism -0.120 0.389 SLICE_X163Y302 FDCE (Remov_fdce_C_CLR) -0.069 0.320 ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[50] ------------------------------------------------------------------- required time -0.320 arrival time 0.622 ------------------------------------------------------------------- slack 0.302 Slack (MET) : 0.302ns (arrival time - required time) Source: ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[81]/CLR (removal check against rising-edge clock rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_5 rise@0.000ns - rxWordclkl12_5 rise@0.000ns) Data Path Delay: 0.269ns (logic 0.100ns (37.203%) route 0.169ns (62.797%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.509ns Source Clock Delay (SCD): 0.353ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.353 0.353 ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X161Y303 FDRE r ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X161Y303 FDRE (Prop_fdre_C_Q) 0.100 0.453 f ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.169 0.622 ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Reset SLICE_X163Y302 FDCE f ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[81]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.509 0.509 ngFEC/SFP_GEN[9].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X163Y302 FDCE r ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[81]/C clock pessimism -0.120 0.389 SLICE_X163Y302 FDCE (Remov_fdce_C_CLR) -0.069 0.320 ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[81] ------------------------------------------------------------------- required time -0.320 arrival time 0.622 ------------------------------------------------------------------- slack 0.302 Slack (MET) : 0.302ns (arrival time - required time) Source: ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[83]/CLR (removal check against rising-edge clock rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_5 rise@0.000ns - rxWordclkl12_5 rise@0.000ns) Data Path Delay: 0.269ns (logic 0.100ns (37.203%) route 0.169ns (62.797%)) Logic Levels: 0 Clock Path Skew: 0.036ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.509ns Source Clock Delay (SCD): 0.353ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.353 0.353 ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X161Y303 FDRE r ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X161Y303 FDRE (Prop_fdre_C_Q) 0.100 0.453 f ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.169 0.622 ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Reset SLICE_X163Y302 FDCE f ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[83]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.509 0.509 ngFEC/SFP_GEN[9].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X163Y302 FDCE r ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[83]/C clock pessimism -0.120 0.389 SLICE_X163Y302 FDCE (Remov_fdce_C_CLR) -0.069 0.320 ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[83] ------------------------------------------------------------------- required time -0.320 arrival time 0.622 ------------------------------------------------------------------- slack 0.302 Slack (MET) : 0.309ns (arrival time - required time) Source: ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[52]/CLR (removal check against rising-edge clock rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_5 rise@0.000ns - rxWordclkl12_5 rise@0.000ns) Data Path Delay: 0.273ns (logic 0.100ns (36.615%) route 0.173ns (63.385%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.508ns Source Clock Delay (SCD): 0.353ns Clock Pessimism Removal (CPR): 0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.353 0.353 ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X161Y303 FDRE r ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X161Y303 FDRE (Prop_fdre_C_Q) 0.100 0.453 f ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.173 0.626 ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Reset SLICE_X160Y305 FDCE f ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[52]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.508 0.508 ngFEC/SFP_GEN[9].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X160Y305 FDCE r ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[52]/C clock pessimism -0.141 0.367 SLICE_X160Y305 FDCE (Remov_fdce_C_CLR) -0.050 0.317 ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[52] ------------------------------------------------------------------- required time -0.317 arrival time 0.626 ------------------------------------------------------------------- slack 0.309 Slack (MET) : 0.309ns (arrival time - required time) Source: ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[64]/CLR (removal check against rising-edge clock rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_5 rise@0.000ns - rxWordclkl12_5 rise@0.000ns) Data Path Delay: 0.273ns (logic 0.100ns (36.615%) route 0.173ns (63.385%)) Logic Levels: 0 Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.508ns Source Clock Delay (SCD): 0.353ns Clock Pessimism Removal (CPR): 0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.353 0.353 ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X161Y303 FDRE r ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X161Y303 FDRE (Prop_fdre_C_Q) 0.100 0.453 f ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.173 0.626 ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Reset SLICE_X160Y305 FDCE f ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[64]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.508 0.508 ngFEC/SFP_GEN[9].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X160Y305 FDCE r ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[64]/C clock pessimism -0.141 0.367 SLICE_X160Y305 FDCE (Remov_fdce_C_CLR) -0.050 0.317 ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[64] ------------------------------------------------------------------- required time -0.317 arrival time 0.626 ------------------------------------------------------------------- slack 0.309 Slack (MET) : 0.353ns (arrival time - required time) Source: ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[60]/CLR (removal check against rising-edge clock rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_5 rise@0.000ns - rxWordclkl12_5 rise@0.000ns) Data Path Delay: 0.319ns (logic 0.100ns (31.385%) route 0.219ns (68.615%)) Logic Levels: 0 Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.508ns Source Clock Delay (SCD): 0.353ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.353 0.353 ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X161Y303 FDRE r ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X161Y303 FDRE (Prop_fdre_C_Q) 0.100 0.453 f ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.219 0.672 ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Reset SLICE_X165Y305 FDCE f ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[60]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.508 0.508 ngFEC/SFP_GEN[9].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X165Y305 FDCE r ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[60]/C clock pessimism -0.120 0.388 SLICE_X165Y305 FDCE (Remov_fdce_C_CLR) -0.069 0.319 ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[60] ------------------------------------------------------------------- required time -0.319 arrival time 0.672 ------------------------------------------------------------------- slack 0.353 Slack (MET) : 0.353ns (arrival time - required time) Source: ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[62]/CLR (removal check against rising-edge clock rxWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_5 rise@0.000ns - rxWordclkl12_5 rise@0.000ns) Data Path Delay: 0.319ns (logic 0.100ns (31.385%) route 0.219ns (68.615%)) Logic Levels: 0 Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.508ns Source Clock Delay (SCD): 0.353ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.353 0.353 ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X161Y303 FDRE r ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X161Y303 FDRE (Prop_fdre_C_Q) 0.100 0.453 f ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.219 0.672 ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Reset SLICE_X165Y305 FDCE f ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[62]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_5 rise edge) 0.000 0.000 r BUFHCE_X1Y73 BUFH 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.508 0.508 ngFEC/SFP_GEN[9].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X165Y305 FDCE r ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[62]/C clock pessimism -0.120 0.388 SLICE_X165Y305 FDCE (Remov_fdce_C_CLR) -0.069 0.319 ngFEC/SFP_GEN[9].ngCCM_gbt/RX_Word_rx40_reg[62] ------------------------------------------------------------------- required time -0.319 arrival time 0.672 ------------------------------------------------------------------- slack 0.353 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: rxWordclkl12_6 To Clock: rxWordclkl12_6 Setup : 0 Failing Endpoints, Worst Slack 4.575ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.290ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.575ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/RX_BITSLIPCMD_o_reg/CLR (recovery check against rising-edge clock rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_6 rise@8.200ns - rxWordclkl12_6 rise@0.000ns) Data Path Delay: 3.007ns (logic 1.062ns (35.316%) route 1.945ns (64.684%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.278ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.633ns = ( 8.833 - 8.200 ) Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.911 0.911 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.920 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.365 3.286 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/out[0] SLICE_X151Y275 LUT2 (Prop_lut2_I0_O) 0.053 3.339 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1__1/O net (fo=25, routed) 0.580 3.919 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/RX_RESET_I SLICE_X156Y274 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/RX_BITSLIPCMD_o_reg/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 8.200 8.200 r BUFHCE_X1Y60 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.633 8.833 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/RX_WORDCLK_I SLICE_X156Y274 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/RX_BITSLIPCMD_o_reg/C clock pessimism 0.000 8.833 clock uncertainty -0.035 8.798 SLICE_X156Y274 FDCE (Recov_fdce_C_CLR) -0.304 8.494 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/RX_BITSLIPCMD_o_reg ------------------------------------------------------------------- required time 8.494 arrival time -3.919 ------------------------------------------------------------------- slack 4.575 Slack (MET) : 4.577ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/shiftPsAddr_reg/CLR (recovery check against rising-edge clock rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_6 rise@8.200ns - rxWordclkl12_6 rise@0.000ns) Data Path Delay: 3.005ns (logic 1.062ns (35.345%) route 1.943ns (64.655%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.279ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.632ns = ( 8.832 - 8.200 ) Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.911 0.911 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.920 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.365 3.286 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/out[0] SLICE_X151Y275 LUT2 (Prop_lut2_I0_O) 0.053 3.339 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1__1/O net (fo=25, routed) 0.577 3.916 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/rx_reset_s_2 SLICE_X155Y275 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/shiftPsAddr_reg/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 8.200 8.200 r BUFHCE_X1Y60 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.632 8.832 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 SLICE_X155Y275 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/shiftPsAddr_reg/C clock pessimism 0.000 8.832 clock uncertainty -0.035 8.797 SLICE_X155Y275 FDCE (Recov_fdce_C_CLR) -0.304 8.493 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/shiftPsAddr_reg ------------------------------------------------------------------- required time 8.493 arrival time -3.916 ------------------------------------------------------------------- slack 4.577 Slack (MET) : 4.674ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r2_reg[1]/CLR (recovery check against rising-edge clock rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_6 rise@8.200ns - rxWordclkl12_6 rise@0.000ns) Data Path Delay: 3.000ns (logic 1.052ns (35.064%) route 1.948ns (64.936%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.278ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.633ns = ( 8.833 - 8.200 ) Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.911 0.911 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.920 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.561 3.481 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/rx_reset_done[1] SLICE_X149Y272 LUT1 (Prop_lut1_I0_O) 0.043 3.524 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r[1]_i_1__1/O net (fo=3, routed) 0.387 3.912 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r[1]_i_1__1_n_0 SLICE_X149Y272 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r2_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 8.200 8.200 r BUFHCE_X1Y60 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.633 8.833 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/CLK SLICE_X149Y272 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r2_reg[1]/C clock pessimism 0.000 8.833 clock uncertainty -0.035 8.798 SLICE_X149Y272 FDCE (Recov_fdce_C_CLR) -0.212 8.586 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r2_reg[1] ------------------------------------------------------------------- required time 8.586 arrival time -3.912 ------------------------------------------------------------------- slack 4.674 Slack (MET) : 4.674ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r3_reg[1]/CLR (recovery check against rising-edge clock rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_6 rise@8.200ns - rxWordclkl12_6 rise@0.000ns) Data Path Delay: 3.000ns (logic 1.052ns (35.064%) route 1.948ns (64.936%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.278ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.633ns = ( 8.833 - 8.200 ) Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.911 0.911 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.920 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.561 3.481 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/rx_reset_done[1] SLICE_X149Y272 LUT1 (Prop_lut1_I0_O) 0.043 3.524 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r[1]_i_1__1/O net (fo=3, routed) 0.387 3.912 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r[1]_i_1__1_n_0 SLICE_X149Y272 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r3_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 8.200 8.200 r BUFHCE_X1Y60 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.633 8.833 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/CLK SLICE_X149Y272 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r3_reg[1]/C clock pessimism 0.000 8.833 clock uncertainty -0.035 8.798 SLICE_X149Y272 FDCE (Recov_fdce_C_CLR) -0.212 8.586 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r3_reg[1] ------------------------------------------------------------------- required time 8.586 arrival time -3.912 ------------------------------------------------------------------- slack 4.674 Slack (MET) : 4.674ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r_reg[1]/CLR (recovery check against rising-edge clock rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_6 rise@8.200ns - rxWordclkl12_6 rise@0.000ns) Data Path Delay: 3.000ns (logic 1.052ns (35.064%) route 1.948ns (64.936%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.278ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.633ns = ( 8.833 - 8.200 ) Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.911 0.911 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.920 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.561 3.481 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/rx_reset_done[1] SLICE_X149Y272 LUT1 (Prop_lut1_I0_O) 0.043 3.524 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r[1]_i_1__1/O net (fo=3, routed) 0.387 3.912 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r[1]_i_1__1_n_0 SLICE_X149Y272 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 8.200 8.200 r BUFHCE_X1Y60 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.633 8.833 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/CLK SLICE_X149Y272 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r_reg[1]/C clock pessimism 0.000 8.833 clock uncertainty -0.035 8.798 SLICE_X149Y272 FDCE (Recov_fdce_C_CLR) -0.212 8.586 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxResetDone_r_reg[1] ------------------------------------------------------------------- required time 8.586 arrival time -3.912 ------------------------------------------------------------------- slack 4.674 Slack (MET) : 4.694ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[0]/CLR (recovery check against rising-edge clock rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_6 rise@8.200ns - rxWordclkl12_6 rise@0.000ns) Data Path Delay: 2.887ns (logic 1.062ns (36.784%) route 1.825ns (63.216%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.279ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.632ns = ( 8.832 - 8.200 ) Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.911 0.911 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.920 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.365 3.286 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/out[0] SLICE_X151Y275 LUT2 (Prop_lut2_I0_O) 0.053 3.339 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1__1/O net (fo=25, routed) 0.460 3.799 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/rx_reset_s_2 SLICE_X155Y274 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 8.200 8.200 r BUFHCE_X1Y60 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.632 8.832 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 SLICE_X155Y274 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[0]/C clock pessimism 0.000 8.832 clock uncertainty -0.035 8.797 SLICE_X155Y274 FDCE (Recov_fdce_C_CLR) -0.304 8.493 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[0] ------------------------------------------------------------------- required time 8.493 arrival time -3.799 ------------------------------------------------------------------- slack 4.694 Slack (MET) : 4.694ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[1]/CLR (recovery check against rising-edge clock rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_6 rise@8.200ns - rxWordclkl12_6 rise@0.000ns) Data Path Delay: 2.887ns (logic 1.062ns (36.784%) route 1.825ns (63.216%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.279ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.632ns = ( 8.832 - 8.200 ) Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.911 0.911 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.920 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.365 3.286 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/out[0] SLICE_X151Y275 LUT2 (Prop_lut2_I0_O) 0.053 3.339 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1__1/O net (fo=25, routed) 0.460 3.799 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/rx_reset_s_2 SLICE_X155Y274 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 8.200 8.200 r BUFHCE_X1Y60 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.632 8.832 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 SLICE_X155Y274 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[1]/C clock pessimism 0.000 8.832 clock uncertainty -0.035 8.797 SLICE_X155Y274 FDCE (Recov_fdce_C_CLR) -0.304 8.493 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[1] ------------------------------------------------------------------- required time 8.493 arrival time -3.799 ------------------------------------------------------------------- slack 4.694 Slack (MET) : 4.694ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[2]/CLR (recovery check against rising-edge clock rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_6 rise@8.200ns - rxWordclkl12_6 rise@0.000ns) Data Path Delay: 2.887ns (logic 1.062ns (36.784%) route 1.825ns (63.216%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.279ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.632ns = ( 8.832 - 8.200 ) Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.911 0.911 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.920 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.365 3.286 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/out[0] SLICE_X151Y275 LUT2 (Prop_lut2_I0_O) 0.053 3.339 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1__1/O net (fo=25, routed) 0.460 3.799 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/rx_reset_s_2 SLICE_X155Y274 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 8.200 8.200 r BUFHCE_X1Y60 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.632 8.832 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 SLICE_X155Y274 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[2]/C clock pessimism 0.000 8.832 clock uncertainty -0.035 8.797 SLICE_X155Y274 FDCE (Recov_fdce_C_CLR) -0.304 8.493 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[2] ------------------------------------------------------------------- required time 8.493 arrival time -3.799 ------------------------------------------------------------------- slack 4.694 Slack (MET) : 4.694ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[3]/CLR (recovery check against rising-edge clock rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_6 rise@8.200ns - rxWordclkl12_6 rise@0.000ns) Data Path Delay: 2.887ns (logic 1.062ns (36.784%) route 1.825ns (63.216%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.279ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.632ns = ( 8.832 - 8.200 ) Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.911 0.911 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.920 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.365 3.286 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/out[0] SLICE_X151Y275 LUT2 (Prop_lut2_I0_O) 0.053 3.339 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1__1/O net (fo=25, routed) 0.460 3.799 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/rx_reset_s_2 SLICE_X155Y274 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 8.200 8.200 r BUFHCE_X1Y60 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.632 8.832 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 SLICE_X155Y274 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[3]/C clock pessimism 0.000 8.832 clock uncertainty -0.035 8.797 SLICE_X155Y274 FDCE (Recov_fdce_C_CLR) -0.304 8.493 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[3] ------------------------------------------------------------------- required time 8.493 arrival time -3.799 ------------------------------------------------------------------- slack 4.694 Slack (MET) : 4.694ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[4]/CLR (recovery check against rising-edge clock rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_6 rise@8.200ns - rxWordclkl12_6 rise@0.000ns) Data Path Delay: 2.887ns (logic 1.062ns (36.784%) route 1.825ns (63.216%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.279ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.632ns = ( 8.832 - 8.200 ) Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.911 0.911 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.920 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.365 3.286 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/out[0] SLICE_X151Y275 LUT2 (Prop_lut2_I0_O) 0.053 3.339 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1__1/O net (fo=25, routed) 0.460 3.799 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/rx_reset_s_2 SLICE_X155Y274 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 8.200 8.200 r BUFHCE_X1Y60 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.632 8.832 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 SLICE_X155Y274 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[4]/C clock pessimism 0.000 8.832 clock uncertainty -0.035 8.797 SLICE_X155Y274 FDCE (Recov_fdce_C_CLR) -0.304 8.493 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[4] ------------------------------------------------------------------- required time 8.493 arrival time -3.799 ------------------------------------------------------------------- slack 4.694 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.290ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/CLR (removal check against rising-edge clock rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_6 rise@0.000ns - rxWordclkl12_6 rise@0.000ns) Data Path Delay: 0.251ns (logic 0.100ns (39.768%) route 0.151ns (60.232%)) Logic Levels: 0 Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.490ns Source Clock Delay (SCD): 0.338ns Clock Pessimism Removal (CPR): 0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.338 0.338 ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X151Y275 FDPE r ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X151Y275 FDPE (Prop_fdpe_C_Q) 0.100 0.438 f ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.151 0.589 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X150Y275 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.490 0.490 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X150Y275 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C clock pessimism -0.141 0.349 SLICE_X150Y275 FDCE (Remov_fdce_C_CLR) -0.050 0.299 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg ------------------------------------------------------------------- required time -0.299 arrival time 0.589 ------------------------------------------------------------------- slack 0.290 Slack (MET) : 0.376ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/cnter_reg[0]/CLR (removal check against rising-edge clock rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_6 rise@0.000ns - rxWordclkl12_6 rise@0.000ns) Data Path Delay: 0.318ns (logic 0.100ns (31.442%) route 0.218ns (68.558%)) Logic Levels: 0 Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.490ns Source Clock Delay (SCD): 0.338ns Clock Pessimism Removal (CPR): 0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.338 0.338 ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X151Y275 FDPE r ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X151Y275 FDPE (Prop_fdpe_C_Q) 0.100 0.438 f ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.218 0.656 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X149Y275 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/cnter_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.490 0.490 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X149Y275 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/cnter_reg[0]/C clock pessimism -0.141 0.349 SLICE_X149Y275 FDCE (Remov_fdce_C_CLR) -0.069 0.280 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/cnter_reg[0] ------------------------------------------------------------------- required time -0.280 arrival time 0.656 ------------------------------------------------------------------- slack 0.376 Slack (MET) : 0.376ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/cnter_reg[1]/CLR (removal check against rising-edge clock rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_6 rise@0.000ns - rxWordclkl12_6 rise@0.000ns) Data Path Delay: 0.318ns (logic 0.100ns (31.442%) route 0.218ns (68.558%)) Logic Levels: 0 Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.490ns Source Clock Delay (SCD): 0.338ns Clock Pessimism Removal (CPR): 0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.338 0.338 ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X151Y275 FDPE r ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X151Y275 FDPE (Prop_fdpe_C_Q) 0.100 0.438 f ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.218 0.656 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X149Y275 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/cnter_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.490 0.490 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X149Y275 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/cnter_reg[1]/C clock pessimism -0.141 0.349 SLICE_X149Y275 FDCE (Remov_fdce_C_CLR) -0.069 0.280 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/cnter_reg[1] ------------------------------------------------------------------- required time -0.280 arrival time 0.656 ------------------------------------------------------------------- slack 0.376 Slack (MET) : 0.376ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/cnter_reg[2]/CLR (removal check against rising-edge clock rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_6 rise@0.000ns - rxWordclkl12_6 rise@0.000ns) Data Path Delay: 0.318ns (logic 0.100ns (31.442%) route 0.218ns (68.558%)) Logic Levels: 0 Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.490ns Source Clock Delay (SCD): 0.338ns Clock Pessimism Removal (CPR): 0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.338 0.338 ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X151Y275 FDPE r ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X151Y275 FDPE (Prop_fdpe_C_Q) 0.100 0.438 f ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.218 0.656 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X149Y275 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/cnter_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.490 0.490 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X149Y275 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/cnter_reg[2]/C clock pessimism -0.141 0.349 SLICE_X149Y275 FDCE (Remov_fdce_C_CLR) -0.069 0.280 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/cnter_reg[2] ------------------------------------------------------------------- required time -0.280 arrival time 0.656 ------------------------------------------------------------------- slack 0.376 Slack (MET) : 0.376ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/firstOut_reg/CLR (removal check against rising-edge clock rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_6 rise@0.000ns - rxWordclkl12_6 rise@0.000ns) Data Path Delay: 0.318ns (logic 0.100ns (31.442%) route 0.218ns (68.558%)) Logic Levels: 0 Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.490ns Source Clock Delay (SCD): 0.338ns Clock Pessimism Removal (CPR): 0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.338 0.338 ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X151Y275 FDPE r ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X151Y275 FDPE (Prop_fdpe_C_Q) 0.100 0.438 f ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.218 0.656 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X149Y275 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/firstOut_reg/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.490 0.490 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X149Y275 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/firstOut_reg/C clock pessimism -0.141 0.349 SLICE_X149Y275 FDCE (Remov_fdce_C_CLR) -0.069 0.280 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/firstOut_reg ------------------------------------------------------------------- required time -0.280 arrival time 0.656 ------------------------------------------------------------------- slack 0.376 Slack (MET) : 0.462ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[37]/CLR (removal check against rising-edge clock rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_6 rise@0.000ns - rxWordclkl12_6 rise@0.000ns) Data Path Delay: 0.408ns (logic 0.100ns (24.504%) route 0.308ns (75.496%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.494ns Source Clock Delay (SCD): 0.338ns Clock Pessimism Removal (CPR): 0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.338 0.338 ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X151Y275 FDPE r ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X151Y275 FDPE (Prop_fdpe_C_Q) 0.100 0.438 f ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.308 0.746 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X149Y278 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[37]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.494 0.494 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X149Y278 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[37]/C clock pessimism -0.141 0.353 SLICE_X149Y278 FDCE (Remov_fdce_C_CLR) -0.069 0.284 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[37] ------------------------------------------------------------------- required time -0.284 arrival time 0.746 ------------------------------------------------------------------- slack 0.462 Slack (MET) : 0.464ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[29]/CLR (removal check against rising-edge clock rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_6 rise@0.000ns - rxWordclkl12_6 rise@0.000ns) Data Path Delay: 0.410ns (logic 0.100ns (24.379%) route 0.310ns (75.621%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.494ns Source Clock Delay (SCD): 0.338ns Clock Pessimism Removal (CPR): 0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.338 0.338 ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X151Y275 FDPE r ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X151Y275 FDPE (Prop_fdpe_C_Q) 0.100 0.438 f ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.310 0.748 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X148Y278 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[29]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.494 0.494 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X148Y278 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[29]/C clock pessimism -0.141 0.353 SLICE_X148Y278 FDCE (Remov_fdce_C_CLR) -0.069 0.284 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[29] ------------------------------------------------------------------- required time -0.284 arrival time 0.748 ------------------------------------------------------------------- slack 0.464 Slack (MET) : 0.464ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[31]/CLR (removal check against rising-edge clock rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_6 rise@0.000ns - rxWordclkl12_6 rise@0.000ns) Data Path Delay: 0.410ns (logic 0.100ns (24.379%) route 0.310ns (75.621%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.494ns Source Clock Delay (SCD): 0.338ns Clock Pessimism Removal (CPR): 0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.338 0.338 ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X151Y275 FDPE r ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X151Y275 FDPE (Prop_fdpe_C_Q) 0.100 0.438 f ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.310 0.748 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X148Y278 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[31]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.494 0.494 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X148Y278 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[31]/C clock pessimism -0.141 0.353 SLICE_X148Y278 FDCE (Remov_fdce_C_CLR) -0.069 0.284 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/reg0_reg[31] ------------------------------------------------------------------- required time -0.284 arrival time 0.748 ------------------------------------------------------------------- slack 0.464 Slack (MET) : 0.468ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE (removal check against rising-edge clock rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_6 rise@0.000ns - rxWordclkl12_6 rise@0.000ns) Data Path Delay: 0.406ns (logic 0.146ns (35.942%) route 0.260ns (64.058%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.010ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.490ns Source Clock Delay (SCD): 0.339ns Clock Pessimism Removal (CPR): 0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.339 0.339 ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X150Y276 FDCE r ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X150Y276 FDCE (Prop_fdce_C_Q) 0.118 0.457 r ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/Q net (fo=1, routed) 0.118 0.575 ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReady_sync_s SLICE_X151Y275 LUT2 (Prop_lut2_I1_O) 0.028 0.603 f ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_i_1__4/O net (fo=1, routed) 0.143 0.745 ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s0 SLICE_X151Y275 FDPE f ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.490 0.490 ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X151Y275 FDPE r ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/C clock pessimism -0.141 0.349 SLICE_X151Y275 FDPE (Remov_fdpe_C_PRE) -0.072 0.277 ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg ------------------------------------------------------------------- required time -0.277 arrival time 0.745 ------------------------------------------------------------------- slack 0.468 Slack (MET) : 0.512ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR (removal check against rising-edge clock rxWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_6 rise@0.000ns - rxWordclkl12_6 rise@0.000ns) Data Path Delay: 0.436ns (logic 0.145ns (33.266%) route 0.291ns (66.734%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.493ns Source Clock Delay (SCD): 0.338ns Clock Pessimism Removal (CPR): 0.141ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.338 0.338 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X150Y275 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X150Y275 FDCE (Prop_fdce_C_Q) 0.118 0.456 r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=3, routed) 0.146 0.602 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg_0 SLICE_X150Y275 LUT1 (Prop_lut1_I0_O) 0.027 0.629 f ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__14/O net (fo=80, routed) 0.145 0.774 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/AR[0] SLICE_X150Y277 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_6 rise edge) 0.000 0.000 r BUFHCE_X1Y60 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1055, routed) 0.493 0.493 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/CLK SLICE_X150Y277 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2]/C clock pessimism -0.141 0.352 SLICE_X150Y277 FDCE (Remov_fdce_C_CLR) -0.090 0.262 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[1].gbtRxDescrambler21bit/feedbackRegister_reg[2] ------------------------------------------------------------------- required time -0.262 arrival time 0.774 ------------------------------------------------------------------- slack 0.512 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: rxWordclkl12_7 To Clock: rxWordclkl12_7 Setup : 0 Failing Endpoints, Worst Slack 4.835ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.297ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.835ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[3]/CLR (recovery check against rising-edge clock rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_7 rise@8.200ns - rxWordclkl12_7 rise@0.000ns) Data Path Delay: 2.865ns (logic 1.052ns (36.722%) route 1.813ns (63.278%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.277ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.644ns = ( 8.844 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.921 0.921 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.930 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 0.974 2.905 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] SLICE_X171Y262 LUT2 (Prop_lut2_I0_O) 0.043 2.948 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__1/O net (fo=25, routed) 0.839 3.786 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_1 SLICE_X162Y264 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 8.200 8.200 r BUFHCE_X1Y61 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.644 8.844 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK SLICE_X162Y264 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[3]/C clock pessimism 0.000 8.844 clock uncertainty -0.035 8.809 SLICE_X162Y264 FDCE (Recov_fdce_C_CLR) -0.187 8.622 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[3] ------------------------------------------------------------------- required time 8.622 arrival time -3.786 ------------------------------------------------------------------- slack 4.835 Slack (MET) : 4.835ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[4]/CLR (recovery check against rising-edge clock rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_7 rise@8.200ns - rxWordclkl12_7 rise@0.000ns) Data Path Delay: 2.865ns (logic 1.052ns (36.722%) route 1.813ns (63.278%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.277ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.644ns = ( 8.844 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.921 0.921 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.930 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 0.974 2.905 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] SLICE_X171Y262 LUT2 (Prop_lut2_I0_O) 0.043 2.948 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__1/O net (fo=25, routed) 0.839 3.786 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_1 SLICE_X162Y264 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 8.200 8.200 r BUFHCE_X1Y61 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.644 8.844 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK SLICE_X162Y264 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[4]/C clock pessimism 0.000 8.844 clock uncertainty -0.035 8.809 SLICE_X162Y264 FDCE (Recov_fdce_C_CLR) -0.187 8.622 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[4] ------------------------------------------------------------------- required time 8.622 arrival time -3.786 ------------------------------------------------------------------- slack 4.835 Slack (MET) : 4.839ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/CLR (recovery check against rising-edge clock rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_7 rise@8.200ns - rxWordclkl12_7 rise@0.000ns) Data Path Delay: 2.860ns (logic 1.052ns (36.786%) route 1.808ns (63.214%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.278ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.643ns = ( 8.843 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.921 0.921 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.930 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 0.974 2.905 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] SLICE_X171Y262 LUT2 (Prop_lut2_I0_O) 0.043 2.948 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__1/O net (fo=25, routed) 0.834 3.781 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_1 SLICE_X162Y265 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 8.200 8.200 r BUFHCE_X1Y61 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.643 8.843 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK SLICE_X162Y265 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.000 8.843 clock uncertainty -0.035 8.808 SLICE_X162Y265 FDCE (Recov_fdce_C_CLR) -0.187 8.621 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 8.621 arrival time -3.781 ------------------------------------------------------------------- slack 4.839 Slack (MET) : 4.839ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[0]/CLR (recovery check against rising-edge clock rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_7 rise@8.200ns - rxWordclkl12_7 rise@0.000ns) Data Path Delay: 2.860ns (logic 1.052ns (36.786%) route 1.808ns (63.214%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.278ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.643ns = ( 8.843 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.921 0.921 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.930 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 0.974 2.905 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] SLICE_X171Y262 LUT2 (Prop_lut2_I0_O) 0.043 2.948 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__1/O net (fo=25, routed) 0.834 3.781 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_1 SLICE_X162Y265 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 8.200 8.200 r BUFHCE_X1Y61 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.643 8.843 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK SLICE_X162Y265 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[0]/C clock pessimism 0.000 8.843 clock uncertainty -0.035 8.808 SLICE_X162Y265 FDCE (Recov_fdce_C_CLR) -0.187 8.621 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[0] ------------------------------------------------------------------- required time 8.621 arrival time -3.781 ------------------------------------------------------------------- slack 4.839 Slack (MET) : 4.839ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[2]/CLR (recovery check against rising-edge clock rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_7 rise@8.200ns - rxWordclkl12_7 rise@0.000ns) Data Path Delay: 2.860ns (logic 1.052ns (36.786%) route 1.808ns (63.214%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.278ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.643ns = ( 8.843 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.921 0.921 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.930 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 0.974 2.905 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] SLICE_X171Y262 LUT2 (Prop_lut2_I0_O) 0.043 2.948 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__1/O net (fo=25, routed) 0.834 3.781 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_1 SLICE_X162Y265 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 8.200 8.200 r BUFHCE_X1Y61 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.643 8.843 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK SLICE_X162Y265 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[2]/C clock pessimism 0.000 8.843 clock uncertainty -0.035 8.808 SLICE_X162Y265 FDCE (Recov_fdce_C_CLR) -0.187 8.621 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[2] ------------------------------------------------------------------- required time 8.621 arrival time -3.781 ------------------------------------------------------------------- slack 4.839 Slack (MET) : 4.868ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[0]/CLR (recovery check against rising-edge clock rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_7 rise@8.200ns - rxWordclkl12_7 rise@0.000ns) Data Path Delay: 2.865ns (logic 1.052ns (36.722%) route 1.813ns (63.278%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.277ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.644ns = ( 8.844 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.921 0.921 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.930 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 0.974 2.905 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] SLICE_X171Y262 LUT2 (Prop_lut2_I0_O) 0.043 2.948 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__1/O net (fo=25, routed) 0.839 3.786 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_1 SLICE_X162Y264 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 8.200 8.200 r BUFHCE_X1Y61 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.644 8.844 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK SLICE_X162Y264 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[0]/C clock pessimism 0.000 8.844 clock uncertainty -0.035 8.809 SLICE_X162Y264 FDCE (Recov_fdce_C_CLR) -0.154 8.655 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[0] ------------------------------------------------------------------- required time 8.655 arrival time -3.786 ------------------------------------------------------------------- slack 4.868 Slack (MET) : 4.868ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[1]/CLR (recovery check against rising-edge clock rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_7 rise@8.200ns - rxWordclkl12_7 rise@0.000ns) Data Path Delay: 2.865ns (logic 1.052ns (36.722%) route 1.813ns (63.278%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.277ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.644ns = ( 8.844 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.921 0.921 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.930 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 0.974 2.905 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] SLICE_X171Y262 LUT2 (Prop_lut2_I0_O) 0.043 2.948 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__1/O net (fo=25, routed) 0.839 3.786 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_1 SLICE_X162Y264 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 8.200 8.200 r BUFHCE_X1Y61 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.644 8.844 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK SLICE_X162Y264 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[1]/C clock pessimism 0.000 8.844 clock uncertainty -0.035 8.809 SLICE_X162Y264 FDCE (Recov_fdce_C_CLR) -0.154 8.655 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[1] ------------------------------------------------------------------- required time 8.655 arrival time -3.786 ------------------------------------------------------------------- slack 4.868 Slack (MET) : 4.868ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[2]/CLR (recovery check against rising-edge clock rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_7 rise@8.200ns - rxWordclkl12_7 rise@0.000ns) Data Path Delay: 2.865ns (logic 1.052ns (36.722%) route 1.813ns (63.278%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.277ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.644ns = ( 8.844 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.921 0.921 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.930 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 0.974 2.905 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] SLICE_X171Y262 LUT2 (Prop_lut2_I0_O) 0.043 2.948 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__1/O net (fo=25, routed) 0.839 3.786 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_1 SLICE_X162Y264 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 8.200 8.200 r BUFHCE_X1Y61 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.644 8.844 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK SLICE_X162Y264 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[2]/C clock pessimism 0.000 8.844 clock uncertainty -0.035 8.809 SLICE_X162Y264 FDCE (Recov_fdce_C_CLR) -0.154 8.655 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[2] ------------------------------------------------------------------- required time 8.655 arrival time -3.786 ------------------------------------------------------------------- slack 4.868 Slack (MET) : 4.872ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]/CLR (recovery check against rising-edge clock rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_7 rise@8.200ns - rxWordclkl12_7 rise@0.000ns) Data Path Delay: 2.860ns (logic 1.052ns (36.786%) route 1.808ns (63.214%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.278ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.643ns = ( 8.843 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.921 0.921 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.930 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 0.974 2.905 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] SLICE_X171Y262 LUT2 (Prop_lut2_I0_O) 0.043 2.948 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__1/O net (fo=25, routed) 0.834 3.781 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_1 SLICE_X162Y265 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 8.200 8.200 r BUFHCE_X1Y61 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.643 8.843 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK SLICE_X162Y265 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.000 8.843 clock uncertainty -0.035 8.808 SLICE_X162Y265 FDCE (Recov_fdce_C_CLR) -0.154 8.654 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 8.654 arrival time -3.781 ------------------------------------------------------------------- slack 4.872 Slack (MET) : 4.872ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/headerFlag_s_reg/CLR (recovery check against rising-edge clock rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_7 rise@8.200ns - rxWordclkl12_7 rise@0.000ns) Data Path Delay: 2.860ns (logic 1.052ns (36.786%) route 1.808ns (63.214%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.278ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.643ns = ( 8.843 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.921 0.921 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.930 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 0.974 2.905 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] SLICE_X171Y262 LUT2 (Prop_lut2_I0_O) 0.043 2.948 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__1/O net (fo=25, routed) 0.834 3.781 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_1 SLICE_X162Y265 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/headerFlag_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 8.200 8.200 r BUFHCE_X1Y61 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.643 8.843 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK SLICE_X162Y265 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/headerFlag_s_reg/C clock pessimism 0.000 8.843 clock uncertainty -0.035 8.808 SLICE_X162Y265 FDCE (Recov_fdce_C_CLR) -0.154 8.654 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/headerFlag_s_reg ------------------------------------------------------------------- required time 8.654 arrival time -3.781 ------------------------------------------------------------------- slack 4.872 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.297ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/cnter_reg[2]/CLR (removal check against rising-edge clock rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_7 rise@0.000ns - rxWordclkl12_7 rise@0.000ns) Data Path Delay: 0.278ns (logic 0.100ns (35.916%) route 0.178ns (64.084%)) Logic Levels: 0 Clock Path Skew: 0.031ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.499ns Source Clock Delay (SCD): 0.348ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.348 0.348 ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X163Y267 FDPE r ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X163Y267 FDPE (Prop_fdpe_C_Q) 0.100 0.448 f ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.178 0.626 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X158Y267 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/cnter_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.499 0.499 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X158Y267 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/cnter_reg[2]/C clock pessimism -0.120 0.379 SLICE_X158Y267 FDCE (Remov_fdce_C_CLR) -0.050 0.329 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/cnter_reg[2] ------------------------------------------------------------------- required time -0.329 arrival time 0.626 ------------------------------------------------------------------- slack 0.297 Slack (MET) : 0.341ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_reg/CLR (removal check against rising-edge clock rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_7 rise@0.000ns - rxWordclkl12_7 rise@0.000ns) Data Path Delay: 0.304ns (logic 0.100ns (32.860%) route 0.204ns (67.140%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.501ns Source Clock Delay (SCD): 0.348ns Clock Pessimism Removal (CPR): 0.140ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.348 0.348 ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X163Y267 FDPE r ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X163Y267 FDPE (Prop_fdpe_C_Q) 0.100 0.448 f ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.204 0.652 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X162Y266 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_reg/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.501 0.501 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X162Y266 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_reg/C clock pessimism -0.140 0.361 SLICE_X162Y266 FDCE (Remov_fdce_C_CLR) -0.050 0.311 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/firstOut_reg ------------------------------------------------------------------- required time -0.311 arrival time 0.652 ------------------------------------------------------------------- slack 0.341 Slack (MET) : 0.362ns (arrival time - required time) Source: ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[20]/CLR (removal check against rising-edge clock rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_7 rise@0.000ns - rxWordclkl12_7 rise@0.000ns) Data Path Delay: 0.322ns (logic 0.100ns (31.081%) route 0.222ns (68.919%)) Logic Levels: 0 Clock Path Skew: 0.029ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.500ns Source Clock Delay (SCD): 0.351ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.351 0.351 ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X157Y260 FDRE r ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X157Y260 FDRE (Prop_fdre_C_Q) 0.100 0.451 f ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.222 0.673 ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Reset SLICE_X148Y265 FDCE f ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[20]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.500 0.500 ngFEC/SFP_GEN[11].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X148Y265 FDCE r ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[20]/C clock pessimism -0.120 0.380 SLICE_X148Y265 FDCE (Remov_fdce_C_CLR) -0.069 0.311 ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[20] ------------------------------------------------------------------- required time -0.311 arrival time 0.673 ------------------------------------------------------------------- slack 0.362 Slack (MET) : 0.362ns (arrival time - required time) Source: ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[28]/CLR (removal check against rising-edge clock rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_7 rise@0.000ns - rxWordclkl12_7 rise@0.000ns) Data Path Delay: 0.322ns (logic 0.100ns (31.081%) route 0.222ns (68.919%)) Logic Levels: 0 Clock Path Skew: 0.029ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.500ns Source Clock Delay (SCD): 0.351ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.351 0.351 ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X157Y260 FDRE r ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X157Y260 FDRE (Prop_fdre_C_Q) 0.100 0.451 f ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.222 0.673 ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Reset SLICE_X148Y265 FDCE f ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[28]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.500 0.500 ngFEC/SFP_GEN[11].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X148Y265 FDCE r ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[28]/C clock pessimism -0.120 0.380 SLICE_X148Y265 FDCE (Remov_fdce_C_CLR) -0.069 0.311 ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[28] ------------------------------------------------------------------- required time -0.311 arrival time 0.673 ------------------------------------------------------------------- slack 0.362 Slack (MET) : 0.376ns (arrival time - required time) Source: ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[48]/CLR (removal check against rising-edge clock rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_7 rise@0.000ns - rxWordclkl12_7 rise@0.000ns) Data Path Delay: 0.338ns (logic 0.100ns (29.548%) route 0.238ns (70.452%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.503ns Source Clock Delay (SCD): 0.351ns Clock Pessimism Removal (CPR): 0.140ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.351 0.351 ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X157Y260 FDRE r ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X157Y260 FDRE (Prop_fdre_C_Q) 0.100 0.451 f ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.238 0.689 ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Reset SLICE_X158Y262 FDCE f ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[48]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.503 0.503 ngFEC/SFP_GEN[11].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X158Y262 FDCE r ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[48]/C clock pessimism -0.140 0.363 SLICE_X158Y262 FDCE (Remov_fdce_C_CLR) -0.050 0.313 ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[48] ------------------------------------------------------------------- required time -0.313 arrival time 0.689 ------------------------------------------------------------------- slack 0.376 Slack (MET) : 0.376ns (arrival time - required time) Source: ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[50]/CLR (removal check against rising-edge clock rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_7 rise@0.000ns - rxWordclkl12_7 rise@0.000ns) Data Path Delay: 0.338ns (logic 0.100ns (29.548%) route 0.238ns (70.452%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.503ns Source Clock Delay (SCD): 0.351ns Clock Pessimism Removal (CPR): 0.140ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.351 0.351 ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X157Y260 FDRE r ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X157Y260 FDRE (Prop_fdre_C_Q) 0.100 0.451 f ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.238 0.689 ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Reset SLICE_X158Y262 FDCE f ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[50]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.503 0.503 ngFEC/SFP_GEN[11].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X158Y262 FDCE r ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[50]/C clock pessimism -0.140 0.363 SLICE_X158Y262 FDCE (Remov_fdce_C_CLR) -0.050 0.313 ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[50] ------------------------------------------------------------------- required time -0.313 arrival time 0.689 ------------------------------------------------------------------- slack 0.376 Slack (MET) : 0.376ns (arrival time - required time) Source: ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[52]/CLR (removal check against rising-edge clock rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_7 rise@0.000ns - rxWordclkl12_7 rise@0.000ns) Data Path Delay: 0.338ns (logic 0.100ns (29.548%) route 0.238ns (70.452%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.503ns Source Clock Delay (SCD): 0.351ns Clock Pessimism Removal (CPR): 0.140ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.351 0.351 ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X157Y260 FDRE r ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X157Y260 FDRE (Prop_fdre_C_Q) 0.100 0.451 f ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.238 0.689 ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Reset SLICE_X158Y262 FDCE f ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[52]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.503 0.503 ngFEC/SFP_GEN[11].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X158Y262 FDCE r ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[52]/C clock pessimism -0.140 0.363 SLICE_X158Y262 FDCE (Remov_fdce_C_CLR) -0.050 0.313 ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[52] ------------------------------------------------------------------- required time -0.313 arrival time 0.689 ------------------------------------------------------------------- slack 0.376 Slack (MET) : 0.376ns (arrival time - required time) Source: ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[54]/CLR (removal check against rising-edge clock rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_7 rise@0.000ns - rxWordclkl12_7 rise@0.000ns) Data Path Delay: 0.338ns (logic 0.100ns (29.548%) route 0.238ns (70.452%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.503ns Source Clock Delay (SCD): 0.351ns Clock Pessimism Removal (CPR): 0.140ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.351 0.351 ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X157Y260 FDRE r ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X157Y260 FDRE (Prop_fdre_C_Q) 0.100 0.451 f ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.238 0.689 ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Reset SLICE_X158Y262 FDCE f ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[54]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.503 0.503 ngFEC/SFP_GEN[11].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X158Y262 FDCE r ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[54]/C clock pessimism -0.140 0.363 SLICE_X158Y262 FDCE (Remov_fdce_C_CLR) -0.050 0.313 ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[54] ------------------------------------------------------------------- required time -0.313 arrival time 0.689 ------------------------------------------------------------------- slack 0.376 Slack (MET) : 0.376ns (arrival time - required time) Source: ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[68]/CLR (removal check against rising-edge clock rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_7 rise@0.000ns - rxWordclkl12_7 rise@0.000ns) Data Path Delay: 0.338ns (logic 0.100ns (29.548%) route 0.238ns (70.452%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.503ns Source Clock Delay (SCD): 0.351ns Clock Pessimism Removal (CPR): 0.140ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.351 0.351 ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X157Y260 FDRE r ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X157Y260 FDRE (Prop_fdre_C_Q) 0.100 0.451 f ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.238 0.689 ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Reset SLICE_X158Y262 FDCE f ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[68]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.503 0.503 ngFEC/SFP_GEN[11].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X158Y262 FDCE r ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[68]/C clock pessimism -0.140 0.363 SLICE_X158Y262 FDCE (Remov_fdce_C_CLR) -0.050 0.313 ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[68] ------------------------------------------------------------------- required time -0.313 arrival time 0.689 ------------------------------------------------------------------- slack 0.376 Slack (MET) : 0.376ns (arrival time - required time) Source: ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[70]/CLR (removal check against rising-edge clock rxWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_7 rise@0.000ns - rxWordclkl12_7 rise@0.000ns) Data Path Delay: 0.338ns (logic 0.100ns (29.548%) route 0.238ns (70.452%)) Logic Levels: 0 Clock Path Skew: 0.012ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.503ns Source Clock Delay (SCD): 0.351ns Clock Pessimism Removal (CPR): 0.140ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.351 0.351 ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X157Y260 FDRE r ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X157Y260 FDRE (Prop_fdre_C_Q) 0.100 0.451 f ngFEC/SFP_GEN[11].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.238 0.689 ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Reset SLICE_X158Y262 FDCE f ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[70]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_7 rise edge) 0.000 0.000 r BUFHCE_X1Y61 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1055, routed) 0.503 0.503 ngFEC/SFP_GEN[11].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X158Y262 FDCE r ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[70]/C clock pessimism -0.140 0.363 SLICE_X158Y262 FDCE (Remov_fdce_C_CLR) -0.050 0.313 ngFEC/SFP_GEN[11].ngCCM_gbt/RX_Word_rx40_reg[70] ------------------------------------------------------------------- required time -0.313 arrival time 0.689 ------------------------------------------------------------------- slack 0.376 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: rxWordclkl12_8 To Clock: rxWordclkl12_8 Setup : 0 Failing Endpoints, Worst Slack 4.660ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.340ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.660ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r2_reg[3]/CLR (recovery check against rising-edge clock rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_8 rise@8.200ns - rxWordclkl12_8 rise@0.000ns) Data Path Delay: 2.970ns (logic 1.062ns (35.757%) route 1.908ns (64.243%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.230ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.692ns = ( 8.892 - 8.200 ) Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.922 0.922 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.931 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.503 3.434 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/rx_reset_done[3] SLICE_X181Y267 LUT1 (Prop_lut1_I0_O) 0.053 3.487 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r[3]_i_1__0/O net (fo=3, routed) 0.405 3.893 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r[3]_i_1__0_n_0 SLICE_X181Y267 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r2_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 8.200 8.200 r BUFHCE_X1Y62 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.692 8.892 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_0 SLICE_X181Y267 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r2_reg[3]/C clock pessimism 0.000 8.892 clock uncertainty -0.035 8.857 SLICE_X181Y267 FDCE (Recov_fdce_C_CLR) -0.304 8.553 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r2_reg[3] ------------------------------------------------------------------- required time 8.553 arrival time -3.893 ------------------------------------------------------------------- slack 4.660 Slack (MET) : 4.660ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r3_reg[3]/CLR (recovery check against rising-edge clock rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_8 rise@8.200ns - rxWordclkl12_8 rise@0.000ns) Data Path Delay: 2.970ns (logic 1.062ns (35.757%) route 1.908ns (64.243%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.230ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.692ns = ( 8.892 - 8.200 ) Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.922 0.922 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.931 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.503 3.434 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/rx_reset_done[3] SLICE_X181Y267 LUT1 (Prop_lut1_I0_O) 0.053 3.487 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r[3]_i_1__0/O net (fo=3, routed) 0.405 3.893 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r[3]_i_1__0_n_0 SLICE_X181Y267 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r3_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 8.200 8.200 r BUFHCE_X1Y62 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.692 8.892 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_0 SLICE_X181Y267 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r3_reg[3]/C clock pessimism 0.000 8.892 clock uncertainty -0.035 8.857 SLICE_X181Y267 FDCE (Recov_fdce_C_CLR) -0.304 8.553 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r3_reg[3] ------------------------------------------------------------------- required time 8.553 arrival time -3.893 ------------------------------------------------------------------- slack 4.660 Slack (MET) : 4.660ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r_reg[3]/CLR (recovery check against rising-edge clock rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_8 rise@8.200ns - rxWordclkl12_8 rise@0.000ns) Data Path Delay: 2.970ns (logic 1.062ns (35.757%) route 1.908ns (64.243%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.230ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.692ns = ( 8.892 - 8.200 ) Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.922 0.922 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.931 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.503 3.434 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/rx_reset_done[3] SLICE_X181Y267 LUT1 (Prop_lut1_I0_O) 0.053 3.487 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r[3]_i_1__0/O net (fo=3, routed) 0.405 3.893 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r[3]_i_1__0_n_0 SLICE_X181Y267 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 8.200 8.200 r BUFHCE_X1Y62 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.692 8.892 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_0 SLICE_X181Y267 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r_reg[3]/C clock pessimism 0.000 8.892 clock uncertainty -0.035 8.857 SLICE_X181Y267 FDCE (Recov_fdce_C_CLR) -0.304 8.553 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r_reg[3] ------------------------------------------------------------------- required time 8.553 arrival time -3.893 ------------------------------------------------------------------- slack 4.660 Slack (MET) : 4.707ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[0]/CLR (recovery check against rising-edge clock rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_8 rise@8.200ns - rxWordclkl12_8 rise@0.000ns) Data Path Delay: 2.922ns (logic 1.062ns (36.351%) route 1.860ns (63.649%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.232ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.690ns = ( 8.890 - 8.200 ) Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.922 0.922 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.931 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.348 3.279 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] SLICE_X184Y267 LUT2 (Prop_lut2_I0_O) 0.053 3.332 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1__0/O net (fo=25, routed) 0.512 3.844 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/rx_reset_s_0 SLICE_X187Y270 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 8.200 8.200 r BUFHCE_X1Y62 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.690 8.890 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK SLICE_X187Y270 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.000 8.890 clock uncertainty -0.035 8.855 SLICE_X187Y270 FDCE (Recov_fdce_C_CLR) -0.304 8.551 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 8.551 arrival time -3.844 ------------------------------------------------------------------- slack 4.707 Slack (MET) : 4.707ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[1]/CLR (recovery check against rising-edge clock rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_8 rise@8.200ns - rxWordclkl12_8 rise@0.000ns) Data Path Delay: 2.922ns (logic 1.062ns (36.351%) route 1.860ns (63.649%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.232ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.690ns = ( 8.890 - 8.200 ) Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.922 0.922 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.931 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.348 3.279 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] SLICE_X184Y267 LUT2 (Prop_lut2_I0_O) 0.053 3.332 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1__0/O net (fo=25, routed) 0.512 3.844 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/rx_reset_s_0 SLICE_X187Y270 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 8.200 8.200 r BUFHCE_X1Y62 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.690 8.890 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK SLICE_X187Y270 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.000 8.890 clock uncertainty -0.035 8.855 SLICE_X187Y270 FDCE (Recov_fdce_C_CLR) -0.304 8.551 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 8.551 arrival time -3.844 ------------------------------------------------------------------- slack 4.707 Slack (MET) : 4.805ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[1]/CLR (recovery check against rising-edge clock rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_8 rise@8.200ns - rxWordclkl12_8 rise@0.000ns) Data Path Delay: 2.829ns (logic 1.062ns (37.539%) route 1.767ns (62.461%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.226ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.696ns = ( 8.896 - 8.200 ) Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.922 0.922 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.931 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.348 3.279 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] SLICE_X184Y267 LUT2 (Prop_lut2_I0_O) 0.053 3.332 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1__0/O net (fo=25, routed) 0.419 3.751 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_RESET_I SLICE_X184Y262 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 8.200 8.200 r BUFHCE_X1Y62 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.696 8.896 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_WORDCLK_I SLICE_X184Y262 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[1]/C clock pessimism 0.000 8.896 clock uncertainty -0.035 8.861 SLICE_X184Y262 FDCE (Recov_fdce_C_CLR) -0.304 8.557 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[1] ------------------------------------------------------------------- required time 8.557 arrival time -3.751 ------------------------------------------------------------------- slack 4.805 Slack (MET) : 4.805ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[2]/CLR (recovery check against rising-edge clock rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_8 rise@8.200ns - rxWordclkl12_8 rise@0.000ns) Data Path Delay: 2.829ns (logic 1.062ns (37.539%) route 1.767ns (62.461%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.226ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.696ns = ( 8.896 - 8.200 ) Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.922 0.922 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.931 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.348 3.279 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] SLICE_X184Y267 LUT2 (Prop_lut2_I0_O) 0.053 3.332 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1__0/O net (fo=25, routed) 0.419 3.751 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_RESET_I SLICE_X184Y262 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 8.200 8.200 r BUFHCE_X1Y62 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.696 8.896 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_WORDCLK_I SLICE_X184Y262 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[2]/C clock pessimism 0.000 8.896 clock uncertainty -0.035 8.861 SLICE_X184Y262 FDCE (Recov_fdce_C_CLR) -0.304 8.557 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[2] ------------------------------------------------------------------- required time 8.557 arrival time -3.751 ------------------------------------------------------------------- slack 4.805 Slack (MET) : 4.839ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[0]/PRE (recovery check against rising-edge clock rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_8 rise@8.200ns - rxWordclkl12_8 rise@0.000ns) Data Path Delay: 2.829ns (logic 1.062ns (37.539%) route 1.767ns (62.461%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.226ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.696ns = ( 8.896 - 8.200 ) Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.922 0.922 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.931 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.348 3.279 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] SLICE_X184Y267 LUT2 (Prop_lut2_I0_O) 0.053 3.332 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1__0/O net (fo=25, routed) 0.419 3.751 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_RESET_I SLICE_X184Y262 FDPE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[0]/PRE ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 8.200 8.200 r BUFHCE_X1Y62 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.696 8.896 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_WORDCLK_I SLICE_X184Y262 FDPE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[0]/C clock pessimism 0.000 8.896 clock uncertainty -0.035 8.861 SLICE_X184Y262 FDPE (Recov_fdpe_C_PRE) -0.270 8.591 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[0] ------------------------------------------------------------------- required time 8.591 arrival time -3.751 ------------------------------------------------------------------- slack 4.839 Slack (MET) : 4.858ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[0]/CLR (recovery check against rising-edge clock rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_8 rise@8.200ns - rxWordclkl12_8 rise@0.000ns) Data Path Delay: 2.771ns (logic 1.062ns (38.320%) route 1.709ns (61.680%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.691ns = ( 8.891 - 8.200 ) Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.922 0.922 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.931 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.348 3.279 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] SLICE_X184Y267 LUT2 (Prop_lut2_I0_O) 0.053 3.332 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1__0/O net (fo=25, routed) 0.361 3.694 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/rx_reset_s_0 SLICE_X184Y268 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 8.200 8.200 r BUFHCE_X1Y62 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.691 8.891 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK SLICE_X184Y268 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[0]/C clock pessimism 0.000 8.891 clock uncertainty -0.035 8.856 SLICE_X184Y268 FDCE (Recov_fdce_C_CLR) -0.304 8.552 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[0] ------------------------------------------------------------------- required time 8.552 arrival time -3.694 ------------------------------------------------------------------- slack 4.858 Slack (MET) : 4.858ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[1]/CLR (recovery check against rising-edge clock rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl12_8 rise@8.200ns - rxWordclkl12_8 rise@0.000ns) Data Path Delay: 2.771ns (logic 1.062ns (38.320%) route 1.709ns (61.680%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.691ns = ( 8.891 - 8.200 ) Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.922 0.922 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.931 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.348 3.279 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] SLICE_X184Y267 LUT2 (Prop_lut2_I0_O) 0.053 3.332 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1__0/O net (fo=25, routed) 0.361 3.694 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/rx_reset_s_0 SLICE_X184Y268 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 8.200 8.200 r BUFHCE_X1Y62 BUFH 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.691 8.891 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK SLICE_X184Y268 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[1]/C clock pessimism 0.000 8.891 clock uncertainty -0.035 8.856 SLICE_X184Y268 FDCE (Recov_fdce_C_CLR) -0.304 8.552 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[1] ------------------------------------------------------------------- required time 8.552 arrival time -3.694 ------------------------------------------------------------------- slack 4.858 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.340ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[18]/CLR (removal check against rising-edge clock rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_8 rise@0.000ns - rxWordclkl12_8 rise@0.000ns) Data Path Delay: 0.282ns (logic 0.100ns (35.406%) route 0.182ns (64.594%)) Logic Levels: 0 Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.530ns Source Clock Delay (SCD): 0.377ns Clock Pessimism Removal (CPR): 0.142ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.377 0.377 ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 SLICE_X184Y269 FDPE r ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X184Y269 FDPE (Prop_fdpe_C_Q) 0.100 0.477 f ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.182 0.659 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X185Y270 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[18]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.530 0.530 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X185Y270 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[18]/C clock pessimism -0.142 0.388 SLICE_X185Y270 FDCE (Remov_fdce_C_CLR) -0.069 0.319 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[18] ------------------------------------------------------------------- required time -0.319 arrival time 0.659 ------------------------------------------------------------------- slack 0.340 Slack (MET) : 0.340ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[33]/CLR (removal check against rising-edge clock rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_8 rise@0.000ns - rxWordclkl12_8 rise@0.000ns) Data Path Delay: 0.282ns (logic 0.100ns (35.406%) route 0.182ns (64.594%)) Logic Levels: 0 Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.530ns Source Clock Delay (SCD): 0.377ns Clock Pessimism Removal (CPR): 0.142ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.377 0.377 ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 SLICE_X184Y269 FDPE r ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X184Y269 FDPE (Prop_fdpe_C_Q) 0.100 0.477 f ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.182 0.659 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X185Y270 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[33]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.530 0.530 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X185Y270 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[33]/C clock pessimism -0.142 0.388 SLICE_X185Y270 FDCE (Remov_fdce_C_CLR) -0.069 0.319 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[33] ------------------------------------------------------------------- required time -0.319 arrival time 0.659 ------------------------------------------------------------------- slack 0.340 Slack (MET) : 0.395ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[33]/CLR (removal check against rising-edge clock rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_8 rise@0.000ns - rxWordclkl12_8 rise@0.000ns) Data Path Delay: 0.336ns (logic 0.100ns (29.721%) route 0.236ns (70.279%)) Logic Levels: 0 Clock Path Skew: 0.010ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.529ns Source Clock Delay (SCD): 0.377ns Clock Pessimism Removal (CPR): 0.142ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.377 0.377 ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 SLICE_X184Y269 FDPE r ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X184Y269 FDPE (Prop_fdpe_C_Q) 0.100 0.477 f ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.236 0.713 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X185Y271 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[33]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.529 0.529 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X185Y271 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[33]/C clock pessimism -0.142 0.387 SLICE_X185Y271 FDCE (Remov_fdce_C_CLR) -0.069 0.318 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg0_reg[33] ------------------------------------------------------------------- required time -0.318 arrival time 0.713 ------------------------------------------------------------------- slack 0.395 Slack (MET) : 0.401ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[40]/CLR (removal check against rising-edge clock rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_8 rise@0.000ns - rxWordclkl12_8 rise@0.000ns) Data Path Delay: 0.384ns (logic 0.100ns (26.074%) route 0.284ns (73.926%)) Logic Levels: 0 Clock Path Skew: 0.033ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.530ns Source Clock Delay (SCD): 0.377ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.377 0.377 ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 SLICE_X184Y269 FDPE r ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X184Y269 FDPE (Prop_fdpe_C_Q) 0.100 0.477 f ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.284 0.761 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X180Y270 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[40]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.530 0.530 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X180Y270 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[40]/C clock pessimism -0.120 0.410 SLICE_X180Y270 FDCE (Remov_fdce_C_CLR) -0.050 0.360 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[40] ------------------------------------------------------------------- required time -0.360 arrival time 0.761 ------------------------------------------------------------------- slack 0.401 Slack (MET) : 0.401ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[43]/CLR (removal check against rising-edge clock rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_8 rise@0.000ns - rxWordclkl12_8 rise@0.000ns) Data Path Delay: 0.384ns (logic 0.100ns (26.074%) route 0.284ns (73.926%)) Logic Levels: 0 Clock Path Skew: 0.033ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.530ns Source Clock Delay (SCD): 0.377ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.377 0.377 ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 SLICE_X184Y269 FDPE r ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X184Y269 FDPE (Prop_fdpe_C_Q) 0.100 0.477 f ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.284 0.761 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X180Y270 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[43]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.530 0.530 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X180Y270 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[43]/C clock pessimism -0.120 0.410 SLICE_X180Y270 FDCE (Remov_fdce_C_CLR) -0.050 0.360 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[43] ------------------------------------------------------------------- required time -0.360 arrival time 0.761 ------------------------------------------------------------------- slack 0.401 Slack (MET) : 0.401ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[56]/CLR (removal check against rising-edge clock rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_8 rise@0.000ns - rxWordclkl12_8 rise@0.000ns) Data Path Delay: 0.384ns (logic 0.100ns (26.074%) route 0.284ns (73.926%)) Logic Levels: 0 Clock Path Skew: 0.033ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.530ns Source Clock Delay (SCD): 0.377ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.377 0.377 ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 SLICE_X184Y269 FDPE r ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X184Y269 FDPE (Prop_fdpe_C_Q) 0.100 0.477 f ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.284 0.761 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X180Y270 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[56]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.530 0.530 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X180Y270 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[56]/C clock pessimism -0.120 0.410 SLICE_X180Y270 FDCE (Remov_fdce_C_CLR) -0.050 0.360 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/reg1_reg[56] ------------------------------------------------------------------- required time -0.360 arrival time 0.761 ------------------------------------------------------------------- slack 0.401 Slack (MET) : 0.420ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[0]/CLR (removal check against rising-edge clock rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_8 rise@0.000ns - rxWordclkl12_8 rise@0.000ns) Data Path Delay: 0.384ns (logic 0.100ns (26.074%) route 0.284ns (73.926%)) Logic Levels: 0 Clock Path Skew: 0.033ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.530ns Source Clock Delay (SCD): 0.377ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.377 0.377 ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 SLICE_X184Y269 FDPE r ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X184Y269 FDPE (Prop_fdpe_C_Q) 0.100 0.477 f ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.284 0.761 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X181Y270 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.530 0.530 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X181Y270 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[0]/C clock pessimism -0.120 0.410 SLICE_X181Y270 FDCE (Remov_fdce_C_CLR) -0.069 0.341 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[0] ------------------------------------------------------------------- required time -0.341 arrival time 0.761 ------------------------------------------------------------------- slack 0.420 Slack (MET) : 0.420ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[1]/CLR (removal check against rising-edge clock rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_8 rise@0.000ns - rxWordclkl12_8 rise@0.000ns) Data Path Delay: 0.384ns (logic 0.100ns (26.074%) route 0.284ns (73.926%)) Logic Levels: 0 Clock Path Skew: 0.033ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.530ns Source Clock Delay (SCD): 0.377ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.377 0.377 ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 SLICE_X184Y269 FDPE r ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X184Y269 FDPE (Prop_fdpe_C_Q) 0.100 0.477 f ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.284 0.761 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X181Y270 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.530 0.530 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X181Y270 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[1]/C clock pessimism -0.120 0.410 SLICE_X181Y270 FDCE (Remov_fdce_C_CLR) -0.069 0.341 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[1] ------------------------------------------------------------------- required time -0.341 arrival time 0.761 ------------------------------------------------------------------- slack 0.420 Slack (MET) : 0.420ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[2]/CLR (removal check against rising-edge clock rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_8 rise@0.000ns - rxWordclkl12_8 rise@0.000ns) Data Path Delay: 0.384ns (logic 0.100ns (26.074%) route 0.284ns (73.926%)) Logic Levels: 0 Clock Path Skew: 0.033ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.530ns Source Clock Delay (SCD): 0.377ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.377 0.377 ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 SLICE_X184Y269 FDPE r ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X184Y269 FDPE (Prop_fdpe_C_Q) 0.100 0.477 f ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.284 0.761 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X181Y270 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.530 0.530 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X181Y270 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[2]/C clock pessimism -0.120 0.410 SLICE_X181Y270 FDCE (Remov_fdce_C_CLR) -0.069 0.341 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/cnter_reg[2] ------------------------------------------------------------------- required time -0.341 arrival time 0.761 ------------------------------------------------------------------- slack 0.420 Slack (MET) : 0.420ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/firstOut_reg/CLR (removal check against rising-edge clock rxWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl12_8 rise@0.000ns - rxWordclkl12_8 rise@0.000ns) Data Path Delay: 0.384ns (logic 0.100ns (26.074%) route 0.284ns (73.926%)) Logic Levels: 0 Clock Path Skew: 0.033ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.530ns Source Clock Delay (SCD): 0.377ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.377 0.377 ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 SLICE_X184Y269 FDPE r ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X184Y269 FDPE (Prop_fdpe_C_Q) 0.100 0.477 f ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.284 0.761 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X181Y270 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/firstOut_reg/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl12_8 rise edge) 0.000 0.000 r BUFHCE_X1Y62 BUFH 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1055, routed) 0.530 0.530 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/CLK SLICE_X181Y270 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/firstOut_reg/C clock pessimism -0.120 0.410 SLICE_X181Y270 FDCE (Remov_fdce_C_CLR) -0.069 0.341 ngFEC/gbtbank3_l12_116/gbt_inst/gbt_rxgearbox_multilink_gen[3].gbt_rxgearbox_inst/firstOut_reg ------------------------------------------------------------------- required time -0.341 arrival time 0.761 ------------------------------------------------------------------- slack 0.420 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: rxWordclkl8_1 To Clock: rxWordclkl8_1 Setup : 0 Failing Endpoints, Worst Slack 5.120ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.257ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.120ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR (recovery check against rising-edge clock rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_1 rise@8.200ns - rxWordclkl8_1 rise@0.000ns) Data Path Delay: 2.673ns (logic 0.311ns (11.633%) route 2.362ns (88.367%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.091ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.649ns = ( 8.849 - 8.200 ) Source Clock Delay (SCD): 0.740ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.740 0.740 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X174Y64 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X174Y64 FDCE (Prop_fdce_C_Q) 0.259 0.999 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=3, routed) 0.702 1.701 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg_0 SLICE_X172Y66 LUT1 (Prop_lut1_I0_O) 0.052 1.753 f ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__22/O net (fo=80, routed) 1.660 3.413 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] SLICE_X164Y52 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 8.200 8.200 r BUFHCE_X1Y12 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.649 8.849 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X164Y52 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[4]/C clock pessimism 0.000 8.849 clock uncertainty -0.035 8.814 SLICE_X164Y52 FDCE (Recov_fdce_C_CLR) -0.280 8.534 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[4] ------------------------------------------------------------------- required time 8.534 arrival time -3.413 ------------------------------------------------------------------- slack 5.120 Slack (MET) : 5.120ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR (recovery check against rising-edge clock rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_1 rise@8.200ns - rxWordclkl8_1 rise@0.000ns) Data Path Delay: 2.673ns (logic 0.311ns (11.633%) route 2.362ns (88.367%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.091ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.649ns = ( 8.849 - 8.200 ) Source Clock Delay (SCD): 0.740ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.740 0.740 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X174Y64 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X174Y64 FDCE (Prop_fdce_C_Q) 0.259 0.999 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=3, routed) 0.702 1.701 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg_0 SLICE_X172Y66 LUT1 (Prop_lut1_I0_O) 0.052 1.753 f ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__22/O net (fo=80, routed) 1.660 3.413 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] SLICE_X164Y52 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 8.200 8.200 r BUFHCE_X1Y12 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.649 8.849 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X164Y52 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[5]/C clock pessimism 0.000 8.849 clock uncertainty -0.035 8.814 SLICE_X164Y52 FDCE (Recov_fdce_C_CLR) -0.280 8.534 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[5] ------------------------------------------------------------------- required time 8.534 arrival time -3.413 ------------------------------------------------------------------- slack 5.120 Slack (MET) : 5.120ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR (recovery check against rising-edge clock rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_1 rise@8.200ns - rxWordclkl8_1 rise@0.000ns) Data Path Delay: 2.673ns (logic 0.311ns (11.633%) route 2.362ns (88.367%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.091ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.649ns = ( 8.849 - 8.200 ) Source Clock Delay (SCD): 0.740ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.740 0.740 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X174Y64 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X174Y64 FDCE (Prop_fdce_C_Q) 0.259 0.999 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=3, routed) 0.702 1.701 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg_0 SLICE_X172Y66 LUT1 (Prop_lut1_I0_O) 0.052 1.753 f ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__22/O net (fo=80, routed) 1.660 3.413 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] SLICE_X164Y52 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[6]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 8.200 8.200 r BUFHCE_X1Y12 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.649 8.849 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X164Y52 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[6]/C clock pessimism 0.000 8.849 clock uncertainty -0.035 8.814 SLICE_X164Y52 FDCE (Recov_fdce_C_CLR) -0.280 8.534 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[6] ------------------------------------------------------------------- required time 8.534 arrival time -3.413 ------------------------------------------------------------------- slack 5.120 Slack (MET) : 5.120ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR (recovery check against rising-edge clock rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_1 rise@8.200ns - rxWordclkl8_1 rise@0.000ns) Data Path Delay: 2.673ns (logic 0.311ns (11.633%) route 2.362ns (88.367%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.091ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.649ns = ( 8.849 - 8.200 ) Source Clock Delay (SCD): 0.740ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.740 0.740 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X174Y64 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X174Y64 FDCE (Prop_fdce_C_Q) 0.259 0.999 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=3, routed) 0.702 1.701 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg_0 SLICE_X172Y66 LUT1 (Prop_lut1_I0_O) 0.052 1.753 f ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__22/O net (fo=80, routed) 1.660 3.413 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] SLICE_X164Y52 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[7]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 8.200 8.200 r BUFHCE_X1Y12 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.649 8.849 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X164Y52 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[7]/C clock pessimism 0.000 8.849 clock uncertainty -0.035 8.814 SLICE_X164Y52 FDCE (Recov_fdce_C_CLR) -0.280 8.534 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[7] ------------------------------------------------------------------- required time 8.534 arrival time -3.413 ------------------------------------------------------------------- slack 5.120 Slack (MET) : 5.153ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR (recovery check against rising-edge clock rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_1 rise@8.200ns - rxWordclkl8_1 rise@0.000ns) Data Path Delay: 2.673ns (logic 0.311ns (11.633%) route 2.362ns (88.367%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.091ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.649ns = ( 8.849 - 8.200 ) Source Clock Delay (SCD): 0.740ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.740 0.740 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X174Y64 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X174Y64 FDCE (Prop_fdce_C_Q) 0.259 0.999 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=3, routed) 0.702 1.701 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg_0 SLICE_X172Y66 LUT1 (Prop_lut1_I0_O) 0.052 1.753 f ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__22/O net (fo=80, routed) 1.660 3.413 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X164Y52 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 8.200 8.200 r BUFHCE_X1Y12 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.649 8.849 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X164Y52 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16]/C clock pessimism 0.000 8.849 clock uncertainty -0.035 8.814 SLICE_X164Y52 FDCE (Recov_fdce_C_CLR) -0.247 8.567 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[16] ------------------------------------------------------------------- required time 8.567 arrival time -3.413 ------------------------------------------------------------------- slack 5.153 Slack (MET) : 5.153ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR (recovery check against rising-edge clock rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_1 rise@8.200ns - rxWordclkl8_1 rise@0.000ns) Data Path Delay: 2.673ns (logic 0.311ns (11.633%) route 2.362ns (88.367%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.091ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.649ns = ( 8.849 - 8.200 ) Source Clock Delay (SCD): 0.740ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.740 0.740 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X174Y64 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X174Y64 FDCE (Prop_fdce_C_Q) 0.259 0.999 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=3, routed) 0.702 1.701 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg_0 SLICE_X172Y66 LUT1 (Prop_lut1_I0_O) 0.052 1.753 f ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__22/O net (fo=80, routed) 1.660 3.413 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X164Y52 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 8.200 8.200 r BUFHCE_X1Y12 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.649 8.849 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X164Y52 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18]/C clock pessimism 0.000 8.849 clock uncertainty -0.035 8.814 SLICE_X164Y52 FDCE (Recov_fdce_C_CLR) -0.247 8.567 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[18] ------------------------------------------------------------------- required time 8.567 arrival time -3.413 ------------------------------------------------------------------- slack 5.153 Slack (MET) : 5.153ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR (recovery check against rising-edge clock rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_1 rise@8.200ns - rxWordclkl8_1 rise@0.000ns) Data Path Delay: 2.673ns (logic 0.311ns (11.633%) route 2.362ns (88.367%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.091ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.649ns = ( 8.849 - 8.200 ) Source Clock Delay (SCD): 0.740ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.740 0.740 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X174Y64 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X174Y64 FDCE (Prop_fdce_C_Q) 0.259 0.999 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=3, routed) 0.702 1.701 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg_0 SLICE_X172Y66 LUT1 (Prop_lut1_I0_O) 0.052 1.753 f ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__22/O net (fo=80, routed) 1.660 3.413 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/AR[0] SLICE_X164Y52 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 8.200 8.200 r BUFHCE_X1Y12 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.649 8.849 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/CLK SLICE_X164Y52 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19]/C clock pessimism 0.000 8.849 clock uncertainty -0.035 8.814 SLICE_X164Y52 FDCE (Recov_fdce_C_CLR) -0.247 8.567 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[2].gbtRxDescrambler21bit/feedbackRegister_reg[19] ------------------------------------------------------------------- required time 8.567 arrival time -3.413 ------------------------------------------------------------------- slack 5.153 Slack (MET) : 5.153ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR (recovery check against rising-edge clock rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_1 rise@8.200ns - rxWordclkl8_1 rise@0.000ns) Data Path Delay: 2.673ns (logic 0.311ns (11.633%) route 2.362ns (88.367%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.091ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.649ns = ( 8.849 - 8.200 ) Source Clock Delay (SCD): 0.740ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.740 0.740 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/CLK SLICE_X174Y64 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/C ------------------------------------------------------------------- ------------------- SLICE_X174Y64 FDCE (Prop_fdce_C_Q) 0.259 0.999 r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg/Q net (fo=3, routed) 0.702 1.701 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/READY_O_reg_0 SLICE_X172Y66 LUT1 (Prop_lut1_I0_O) 0.052 1.753 f ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[1].gbt_rxgearbox_inst/feedbackRegister[20]_i_2__22/O net (fo=80, routed) 1.660 3.413 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/AR[0] SLICE_X164Y52 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 8.200 8.200 r BUFHCE_X1Y12 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.649 8.849 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/CLK SLICE_X164Y52 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3]/C clock pessimism 0.000 8.849 clock uncertainty -0.035 8.814 SLICE_X164Y52 FDCE (Recov_fdce_C_CLR) -0.247 8.567 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxdatapath_multilink_gen[1].gbt_rxdatapath_inst/descrambler/gbtRxDescrambler84bit_gen[3].gbtRxDescrambler21bit/feedbackRegister_reg[3] ------------------------------------------------------------------- required time 8.567 arrival time -3.413 ------------------------------------------------------------------- slack 5.153 Slack (MET) : 5.170ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg/CLR (recovery check against rising-edge clock rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_1 rise@8.200ns - rxWordclkl8_1 rise@0.000ns) Data Path Delay: 2.468ns (logic 1.055ns (42.744%) route 1.413ns (57.255%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.225ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.696ns = ( 8.896 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.921 0.921 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y4 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y4 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.930 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 0.775 2.705 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/out[0] SLICE_X186Y60 LUT2 (Prop_lut2_I0_O) 0.046 2.751 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1__2/O net (fo=25, routed) 0.638 3.390 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/rx_reset_s_3 SLICE_X183Y61 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 8.200 8.200 r BUFHCE_X1Y12 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.696 8.896 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 SLICE_X183Y61 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg/C clock pessimism 0.000 8.896 clock uncertainty -0.035 8.861 SLICE_X183Y61 FDCE (Recov_fdce_C_CLR) -0.301 8.560 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg ------------------------------------------------------------------- required time 8.560 arrival time -3.390 ------------------------------------------------------------------- slack 5.170 Slack (MET) : 5.170ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCmd_reg/CLR (recovery check against rising-edge clock rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_1 rise@8.200ns - rxWordclkl8_1 rise@0.000ns) Data Path Delay: 2.468ns (logic 1.055ns (42.744%) route 1.413ns (57.255%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.225ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.696ns = ( 8.896 - 8.200 ) Source Clock Delay (SCD): 0.921ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.921 0.921 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y4 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y4 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.930 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 0.775 2.705 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/out[0] SLICE_X186Y60 LUT2 (Prop_lut2_I0_O) 0.046 2.751 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1__2/O net (fo=25, routed) 0.638 3.390 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/rx_reset_s_3 SLICE_X183Y61 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCmd_reg/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 8.200 8.200 r BUFHCE_X1Y12 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.696 8.896 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg_0 SLICE_X183Y61 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCmd_reg/C clock pessimism 0.000 8.896 clock uncertainty -0.035 8.861 SLICE_X183Y61 FDCE (Recov_fdce_C_CLR) -0.301 8.560 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCmd_reg ------------------------------------------------------------------- required time 8.560 arrival time -3.390 ------------------------------------------------------------------- slack 5.170 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.257ns (arrival time - required time) Source: ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[4]/CLR (removal check against rising-edge clock rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_1 rise@0.000ns - rxWordclkl8_1 rise@0.000ns) Data Path Delay: 0.240ns (logic 0.100ns (41.738%) route 0.140ns (58.262%)) Logic Levels: 0 Clock Path Skew: 0.033ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.536ns Source Clock Delay (SCD): 0.383ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.383 0.383 ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X175Y97 FDRE r ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X175Y97 FDRE (Prop_fdre_C_Q) 0.100 0.483 f ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.140 0.623 ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/AR[0] SLICE_X170Y93 FDCE f ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.536 0.536 ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] SLICE_X170Y93 FDCE r ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[4]/C clock pessimism -0.120 0.416 SLICE_X170Y93 FDCE (Remov_fdce_C_CLR) -0.050 0.366 ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[4] ------------------------------------------------------------------- required time -0.366 arrival time 0.623 ------------------------------------------------------------------- slack 0.257 Slack (MET) : 0.257ns (arrival time - required time) Source: ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[5]/CLR (removal check against rising-edge clock rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_1 rise@0.000ns - rxWordclkl8_1 rise@0.000ns) Data Path Delay: 0.240ns (logic 0.100ns (41.738%) route 0.140ns (58.262%)) Logic Levels: 0 Clock Path Skew: 0.033ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.536ns Source Clock Delay (SCD): 0.383ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.383 0.383 ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X175Y97 FDRE r ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X175Y97 FDRE (Prop_fdre_C_Q) 0.100 0.483 f ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.140 0.623 ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/AR[0] SLICE_X170Y93 FDCE f ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[5]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.536 0.536 ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] SLICE_X170Y93 FDCE r ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[5]/C clock pessimism -0.120 0.416 SLICE_X170Y93 FDCE (Remov_fdce_C_CLR) -0.050 0.366 ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[5] ------------------------------------------------------------------- required time -0.366 arrival time 0.623 ------------------------------------------------------------------- slack 0.257 Slack (MET) : 0.257ns (arrival time - required time) Source: ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[6]/CLR (removal check against rising-edge clock rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_1 rise@0.000ns - rxWordclkl8_1 rise@0.000ns) Data Path Delay: 0.240ns (logic 0.100ns (41.738%) route 0.140ns (58.262%)) Logic Levels: 0 Clock Path Skew: 0.033ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.536ns Source Clock Delay (SCD): 0.383ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.383 0.383 ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X175Y97 FDRE r ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X175Y97 FDRE (Prop_fdre_C_Q) 0.100 0.483 f ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.140 0.623 ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/AR[0] SLICE_X170Y93 FDCE f ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[6]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.536 0.536 ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] SLICE_X170Y93 FDCE r ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[6]/C clock pessimism -0.120 0.416 SLICE_X170Y93 FDCE (Remov_fdce_C_CLR) -0.050 0.366 ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[6] ------------------------------------------------------------------- required time -0.366 arrival time 0.623 ------------------------------------------------------------------- slack 0.257 Slack (MET) : 0.257ns (arrival time - required time) Source: ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[7]/CLR (removal check against rising-edge clock rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_1 rise@0.000ns - rxWordclkl8_1 rise@0.000ns) Data Path Delay: 0.240ns (logic 0.100ns (41.738%) route 0.140ns (58.262%)) Logic Levels: 0 Clock Path Skew: 0.033ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.536ns Source Clock Delay (SCD): 0.383ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.383 0.383 ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X175Y97 FDRE r ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X175Y97 FDRE (Prop_fdre_C_Q) 0.100 0.483 f ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.140 0.623 ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/AR[0] SLICE_X170Y93 FDCE f ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[7]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.536 0.536 ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] SLICE_X170Y93 FDCE r ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[7]/C clock pessimism -0.120 0.416 SLICE_X170Y93 FDCE (Remov_fdce_C_CLR) -0.050 0.366 ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[7] ------------------------------------------------------------------- required time -0.366 arrival time 0.623 ------------------------------------------------------------------- slack 0.257 Slack (MET) : 0.272ns (arrival time - required time) Source: ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[24]/CLR (removal check against rising-edge clock rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_1 rise@0.000ns - rxWordclkl8_1 rise@0.000ns) Data Path Delay: 0.256ns (logic 0.100ns (38.990%) route 0.156ns (61.010%)) Logic Levels: 0 Clock Path Skew: 0.034ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.537ns Source Clock Delay (SCD): 0.383ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.383 0.383 ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X175Y97 FDRE r ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X175Y97 FDRE (Prop_fdre_C_Q) 0.100 0.483 f ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.156 0.639 ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/AR[0] SLICE_X170Y98 FDCE f ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[24]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.537 0.537 ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] SLICE_X170Y98 FDCE r ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[24]/C clock pessimism -0.120 0.417 SLICE_X170Y98 FDCE (Remov_fdce_C_CLR) -0.050 0.367 ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[24] ------------------------------------------------------------------- required time -0.367 arrival time 0.639 ------------------------------------------------------------------- slack 0.272 Slack (MET) : 0.272ns (arrival time - required time) Source: ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[25]/CLR (removal check against rising-edge clock rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_1 rise@0.000ns - rxWordclkl8_1 rise@0.000ns) Data Path Delay: 0.256ns (logic 0.100ns (38.990%) route 0.156ns (61.010%)) Logic Levels: 0 Clock Path Skew: 0.034ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.537ns Source Clock Delay (SCD): 0.383ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.383 0.383 ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X175Y97 FDRE r ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X175Y97 FDRE (Prop_fdre_C_Q) 0.100 0.483 f ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.156 0.639 ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/AR[0] SLICE_X170Y98 FDCE f ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[25]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.537 0.537 ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] SLICE_X170Y98 FDCE r ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[25]/C clock pessimism -0.120 0.417 SLICE_X170Y98 FDCE (Remov_fdce_C_CLR) -0.050 0.367 ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[25] ------------------------------------------------------------------- required time -0.367 arrival time 0.639 ------------------------------------------------------------------- slack 0.272 Slack (MET) : 0.272ns (arrival time - required time) Source: ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[26]/CLR (removal check against rising-edge clock rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_1 rise@0.000ns - rxWordclkl8_1 rise@0.000ns) Data Path Delay: 0.256ns (logic 0.100ns (38.990%) route 0.156ns (61.010%)) Logic Levels: 0 Clock Path Skew: 0.034ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.537ns Source Clock Delay (SCD): 0.383ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.383 0.383 ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X175Y97 FDRE r ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X175Y97 FDRE (Prop_fdre_C_Q) 0.100 0.483 f ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.156 0.639 ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/AR[0] SLICE_X170Y98 FDCE f ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[26]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.537 0.537 ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] SLICE_X170Y98 FDCE r ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[26]/C clock pessimism -0.120 0.417 SLICE_X170Y98 FDCE (Remov_fdce_C_CLR) -0.050 0.367 ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[26] ------------------------------------------------------------------- required time -0.367 arrival time 0.639 ------------------------------------------------------------------- slack 0.272 Slack (MET) : 0.272ns (arrival time - required time) Source: ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[27]/CLR (removal check against rising-edge clock rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_1 rise@0.000ns - rxWordclkl8_1 rise@0.000ns) Data Path Delay: 0.256ns (logic 0.100ns (38.990%) route 0.156ns (61.010%)) Logic Levels: 0 Clock Path Skew: 0.034ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.537ns Source Clock Delay (SCD): 0.383ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.383 0.383 ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X175Y97 FDRE r ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X175Y97 FDRE (Prop_fdre_C_Q) 0.100 0.483 f ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.156 0.639 ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/AR[0] SLICE_X170Y98 FDCE f ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[27]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.537 0.537 ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] SLICE_X170Y98 FDCE r ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[27]/C clock pessimism -0.120 0.417 SLICE_X170Y98 FDCE (Remov_fdce_C_CLR) -0.050 0.367 ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[27] ------------------------------------------------------------------- required time -0.367 arrival time 0.639 ------------------------------------------------------------------- slack 0.272 Slack (MET) : 0.278ns (arrival time - required time) Source: ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[20]/CLR (removal check against rising-edge clock rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_1 rise@0.000ns - rxWordclkl8_1 rise@0.000ns) Data Path Delay: 0.262ns (logic 0.100ns (38.232%) route 0.162ns (61.768%)) Logic Levels: 0 Clock Path Skew: 0.034ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.537ns Source Clock Delay (SCD): 0.383ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.383 0.383 ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X175Y97 FDRE r ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X175Y97 FDRE (Prop_fdre_C_Q) 0.100 0.483 f ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.162 0.645 ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/AR[0] SLICE_X170Y97 FDCE f ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[20]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.537 0.537 ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] SLICE_X170Y97 FDCE r ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[20]/C clock pessimism -0.120 0.417 SLICE_X170Y97 FDCE (Remov_fdce_C_CLR) -0.050 0.367 ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[20] ------------------------------------------------------------------- required time -0.367 arrival time 0.645 ------------------------------------------------------------------- slack 0.278 Slack (MET) : 0.278ns (arrival time - required time) Source: ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[21]/CLR (removal check against rising-edge clock rxWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_1 rise@0.000ns - rxWordclkl8_1 rise@0.000ns) Data Path Delay: 0.262ns (logic 0.100ns (38.232%) route 0.162ns (61.768%)) Logic Levels: 0 Clock Path Skew: 0.034ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.537ns Source Clock Delay (SCD): 0.383ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.383 0.383 ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X175Y97 FDRE r ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X175Y97 FDRE (Prop_fdre_C_Q) 0.100 0.483 f ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.162 0.645 ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/AR[0] SLICE_X170Y97 FDCE f ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[21]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_1 rise edge) 0.000 0.000 r BUFHCE_X1Y12 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O net (fo=1057, routed) 0.537 0.537 ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/MGT_RXUSRCLK_o[0] SLICE_X170Y97 FDCE r ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[21]/C clock pessimism -0.120 0.417 SLICE_X170Y97 FDCE (Remov_fdce_C_CLR) -0.050 0.367 ngFEC/SFP_GEN[5].ngCCM_gbt/gbt_rx_checker/PRBS_rx_pattern_error_cnt_reg[21] ------------------------------------------------------------------- required time -0.367 arrival time 0.645 ------------------------------------------------------------------- slack 0.278 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: rxWordclkl8_2 To Clock: rxWordclkl8_2 Setup : 0 Failing Endpoints, Worst Slack 4.338ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.351ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.338ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/shiftPsAddr_reg/CLR (recovery check against rising-edge clock rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_2 rise@8.200ns - rxWordclkl8_2 rise@0.000ns) Data Path Delay: 3.253ns (logic 1.062ns (32.649%) route 2.191ns (67.351%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.269ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.642ns = ( 8.842 - 8.200 ) Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.911 0.911 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y5 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y5 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.920 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.750 3.671 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] SLICE_X156Y65 LUT2 (Prop_lut2_I0_O) 0.053 3.724 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__2/O net (fo=25, routed) 0.440 4.164 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_2 SLICE_X156Y65 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/shiftPsAddr_reg/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 8.200 8.200 r BUFHCE_X1Y13 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.642 8.842 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK SLICE_X156Y65 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/shiftPsAddr_reg/C clock pessimism 0.000 8.842 clock uncertainty -0.035 8.807 SLICE_X156Y65 FDCE (Recov_fdce_C_CLR) -0.304 8.503 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/shiftPsAddr_reg ------------------------------------------------------------------- required time 8.503 arrival time -4.164 ------------------------------------------------------------------- slack 4.338 Slack (MET) : 4.445ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/RX_BITSLIPCMD_o_reg/CLR (recovery check against rising-edge clock rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_2 rise@8.200ns - rxWordclkl8_2 rise@0.000ns) Data Path Delay: 3.144ns (logic 1.062ns (33.776%) route 2.082ns (66.224%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.271ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.640ns = ( 8.840 - 8.200 ) Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.911 0.911 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y5 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y5 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.920 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.750 3.671 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] SLICE_X156Y65 LUT2 (Prop_lut2_I0_O) 0.053 3.724 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__2/O net (fo=25, routed) 0.332 4.056 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/RX_RESET_I SLICE_X153Y66 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/RX_BITSLIPCMD_o_reg/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 8.200 8.200 r BUFHCE_X1Y13 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.640 8.840 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/RX_WORDCLK_I SLICE_X153Y66 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/RX_BITSLIPCMD_o_reg/C clock pessimism 0.000 8.840 clock uncertainty -0.035 8.805 SLICE_X153Y66 FDCE (Recov_fdce_C_CLR) -0.304 8.501 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/RX_BITSLIPCMD_o_reg ------------------------------------------------------------------- required time 8.501 arrival time -4.056 ------------------------------------------------------------------- slack 4.445 Slack (MET) : 4.446ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/headerFlag_s_reg/CLR (recovery check against rising-edge clock rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_2 rise@8.200ns - rxWordclkl8_2 rise@0.000ns) Data Path Delay: 3.144ns (logic 1.062ns (33.776%) route 2.082ns (66.224%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.270ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.641ns = ( 8.841 - 8.200 ) Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.911 0.911 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y5 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y5 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.920 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.750 3.671 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] SLICE_X156Y65 LUT2 (Prop_lut2_I0_O) 0.053 3.724 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__2/O net (fo=25, routed) 0.332 4.056 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_2 SLICE_X153Y65 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/headerFlag_s_reg/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 8.200 8.200 r BUFHCE_X1Y13 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.641 8.841 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK SLICE_X153Y65 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/headerFlag_s_reg/C clock pessimism 0.000 8.841 clock uncertainty -0.035 8.806 SLICE_X153Y65 FDCE (Recov_fdce_C_CLR) -0.304 8.502 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/headerFlag_s_reg ------------------------------------------------------------------- required time 8.502 arrival time -4.056 ------------------------------------------------------------------- slack 4.446 Slack (MET) : 4.446ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[0]/CLR (recovery check against rising-edge clock rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_2 rise@8.200ns - rxWordclkl8_2 rise@0.000ns) Data Path Delay: 3.144ns (logic 1.062ns (33.776%) route 2.082ns (66.224%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.270ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.641ns = ( 8.841 - 8.200 ) Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.911 0.911 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y5 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y5 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.920 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.750 3.671 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] SLICE_X156Y65 LUT2 (Prop_lut2_I0_O) 0.053 3.724 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__2/O net (fo=25, routed) 0.332 4.056 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_2 SLICE_X153Y65 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 8.200 8.200 r BUFHCE_X1Y13 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.641 8.841 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK SLICE_X153Y65 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[0]/C clock pessimism 0.000 8.841 clock uncertainty -0.035 8.806 SLICE_X153Y65 FDCE (Recov_fdce_C_CLR) -0.304 8.502 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[0] ------------------------------------------------------------------- required time 8.502 arrival time -4.056 ------------------------------------------------------------------- slack 4.446 Slack (MET) : 4.446ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[1]/CLR (recovery check against rising-edge clock rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_2 rise@8.200ns - rxWordclkl8_2 rise@0.000ns) Data Path Delay: 3.144ns (logic 1.062ns (33.776%) route 2.082ns (66.224%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.270ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.641ns = ( 8.841 - 8.200 ) Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.911 0.911 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y5 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y5 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.920 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.750 3.671 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] SLICE_X156Y65 LUT2 (Prop_lut2_I0_O) 0.053 3.724 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__2/O net (fo=25, routed) 0.332 4.056 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_2 SLICE_X153Y65 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 8.200 8.200 r BUFHCE_X1Y13 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.641 8.841 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK SLICE_X153Y65 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[1]/C clock pessimism 0.000 8.841 clock uncertainty -0.035 8.806 SLICE_X153Y65 FDCE (Recov_fdce_C_CLR) -0.304 8.502 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[1] ------------------------------------------------------------------- required time 8.502 arrival time -4.056 ------------------------------------------------------------------- slack 4.446 Slack (MET) : 4.446ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[2]/CLR (recovery check against rising-edge clock rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_2 rise@8.200ns - rxWordclkl8_2 rise@0.000ns) Data Path Delay: 3.144ns (logic 1.062ns (33.776%) route 2.082ns (66.224%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.270ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.641ns = ( 8.841 - 8.200 ) Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.911 0.911 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y5 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y5 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.920 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.750 3.671 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] SLICE_X156Y65 LUT2 (Prop_lut2_I0_O) 0.053 3.724 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__2/O net (fo=25, routed) 0.332 4.056 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_2 SLICE_X153Y65 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 8.200 8.200 r BUFHCE_X1Y13 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.641 8.841 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK SLICE_X153Y65 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[2]/C clock pessimism 0.000 8.841 clock uncertainty -0.035 8.806 SLICE_X153Y65 FDCE (Recov_fdce_C_CLR) -0.304 8.502 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/psAddress_reg[2] ------------------------------------------------------------------- required time 8.502 arrival time -4.056 ------------------------------------------------------------------- slack 4.446 Slack (MET) : 4.446ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/READY_o_reg/CLR (recovery check against rising-edge clock rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_2 rise@8.200ns - rxWordclkl8_2 rise@0.000ns) Data Path Delay: 3.144ns (logic 1.062ns (33.776%) route 2.082ns (66.224%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.270ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.641ns = ( 8.841 - 8.200 ) Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.911 0.911 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y5 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y5 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.920 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.750 3.671 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] SLICE_X156Y65 LUT2 (Prop_lut2_I0_O) 0.053 3.724 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__2/O net (fo=25, routed) 0.332 4.056 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/RX_RESET_I SLICE_X153Y65 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/READY_o_reg/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 8.200 8.200 r BUFHCE_X1Y13 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.641 8.841 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/RX_WORDCLK_I SLICE_X153Y65 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/READY_o_reg/C clock pessimism 0.000 8.841 clock uncertainty -0.035 8.806 SLICE_X153Y65 FDCE (Recov_fdce_C_CLR) -0.304 8.502 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/READY_o_reg ------------------------------------------------------------------- required time 8.502 arrival time -4.056 ------------------------------------------------------------------- slack 4.446 Slack (MET) : 4.453ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[0]/CLR (recovery check against rising-edge clock rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_2 rise@8.200ns - rxWordclkl8_2 rise@0.000ns) Data Path Delay: 3.137ns (logic 1.062ns (33.849%) route 2.075ns (66.151%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.270ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.641ns = ( 8.841 - 8.200 ) Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.911 0.911 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y5 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y5 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.920 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.750 3.671 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] SLICE_X156Y65 LUT2 (Prop_lut2_I0_O) 0.053 3.724 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__2/O net (fo=25, routed) 0.325 4.049 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_2 SLICE_X156Y66 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 8.200 8.200 r BUFHCE_X1Y13 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.641 8.841 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK SLICE_X156Y66 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[0]/C clock pessimism 0.000 8.841 clock uncertainty -0.035 8.806 SLICE_X156Y66 FDCE (Recov_fdce_C_CLR) -0.304 8.502 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[0] ------------------------------------------------------------------- required time 8.502 arrival time -4.049 ------------------------------------------------------------------- slack 4.453 Slack (MET) : 4.453ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[1]/CLR (recovery check against rising-edge clock rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_2 rise@8.200ns - rxWordclkl8_2 rise@0.000ns) Data Path Delay: 3.137ns (logic 1.062ns (33.849%) route 2.075ns (66.151%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.270ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.641ns = ( 8.841 - 8.200 ) Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.911 0.911 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y5 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y5 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.920 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.750 3.671 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] SLICE_X156Y65 LUT2 (Prop_lut2_I0_O) 0.053 3.724 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__2/O net (fo=25, routed) 0.325 4.049 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_2 SLICE_X156Y66 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 8.200 8.200 r BUFHCE_X1Y13 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.641 8.841 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK SLICE_X156Y66 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[1]/C clock pessimism 0.000 8.841 clock uncertainty -0.035 8.806 SLICE_X156Y66 FDCE (Recov_fdce_C_CLR) -0.304 8.502 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[1] ------------------------------------------------------------------- required time 8.502 arrival time -4.049 ------------------------------------------------------------------- slack 4.453 Slack (MET) : 4.453ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[2]/CLR (recovery check against rising-edge clock rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_2 rise@8.200ns - rxWordclkl8_2 rise@0.000ns) Data Path Delay: 3.137ns (logic 1.062ns (33.849%) route 2.075ns (66.151%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.270ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.641ns = ( 8.841 - 8.200 ) Source Clock Delay (SCD): 0.911ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.911 0.911 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y5 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y5 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.920 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.750 3.671 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/out[0] SLICE_X156Y65 LUT2 (Prop_lut2_I0_O) 0.053 3.724 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__2/O net (fo=25, routed) 0.325 4.049 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/rx_reset_s_2 SLICE_X156Y66 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 8.200 8.200 r BUFHCE_X1Y13 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.641 8.841 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/CLK SLICE_X156Y66 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[2]/C clock pessimism 0.000 8.841 clock uncertainty -0.035 8.806 SLICE_X156Y66 FDCE (Recov_fdce_C_CLR) -0.304 8.502 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[2] ------------------------------------------------------------------- required time 8.502 arrival time -4.049 ------------------------------------------------------------------- slack 4.453 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.351ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[36]/CLR (removal check against rising-edge clock rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_2 rise@0.000ns - rxWordclkl8_2 rise@0.000ns) Data Path Delay: 0.316ns (logic 0.100ns (31.673%) route 0.216ns (68.327%)) Logic Levels: 0 Clock Path Skew: 0.034ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.500ns Source Clock Delay (SCD): 0.346ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.346 0.346 ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X155Y67 FDPE r ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X155Y67 FDPE (Prop_fdpe_C_Q) 0.100 0.446 f ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.216 0.662 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X148Y65 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[36]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.500 0.500 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X148Y65 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[36]/C clock pessimism -0.120 0.380 SLICE_X148Y65 FDCE (Remov_fdce_C_CLR) -0.069 0.311 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[36] ------------------------------------------------------------------- required time -0.311 arrival time 0.662 ------------------------------------------------------------------- slack 0.351 Slack (MET) : 0.351ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[37]/CLR (removal check against rising-edge clock rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_2 rise@0.000ns - rxWordclkl8_2 rise@0.000ns) Data Path Delay: 0.316ns (logic 0.100ns (31.673%) route 0.216ns (68.327%)) Logic Levels: 0 Clock Path Skew: 0.034ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.500ns Source Clock Delay (SCD): 0.346ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.346 0.346 ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X155Y67 FDPE r ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X155Y67 FDPE (Prop_fdpe_C_Q) 0.100 0.446 f ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.216 0.662 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X148Y65 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[37]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.500 0.500 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X148Y65 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[37]/C clock pessimism -0.120 0.380 SLICE_X148Y65 FDCE (Remov_fdce_C_CLR) -0.069 0.311 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[37] ------------------------------------------------------------------- required time -0.311 arrival time 0.662 ------------------------------------------------------------------- slack 0.351 Slack (MET) : 0.351ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[38]/CLR (removal check against rising-edge clock rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_2 rise@0.000ns - rxWordclkl8_2 rise@0.000ns) Data Path Delay: 0.316ns (logic 0.100ns (31.673%) route 0.216ns (68.327%)) Logic Levels: 0 Clock Path Skew: 0.034ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.500ns Source Clock Delay (SCD): 0.346ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.346 0.346 ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X155Y67 FDPE r ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X155Y67 FDPE (Prop_fdpe_C_Q) 0.100 0.446 f ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.216 0.662 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X148Y65 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[38]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.500 0.500 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X148Y65 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[38]/C clock pessimism -0.120 0.380 SLICE_X148Y65 FDCE (Remov_fdce_C_CLR) -0.069 0.311 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[38] ------------------------------------------------------------------- required time -0.311 arrival time 0.662 ------------------------------------------------------------------- slack 0.351 Slack (MET) : 0.351ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[39]/CLR (removal check against rising-edge clock rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_2 rise@0.000ns - rxWordclkl8_2 rise@0.000ns) Data Path Delay: 0.316ns (logic 0.100ns (31.673%) route 0.216ns (68.327%)) Logic Levels: 0 Clock Path Skew: 0.034ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.500ns Source Clock Delay (SCD): 0.346ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.346 0.346 ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X155Y67 FDPE r ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X155Y67 FDPE (Prop_fdpe_C_Q) 0.100 0.446 f ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.216 0.662 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X148Y65 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[39]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.500 0.500 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X148Y65 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[39]/C clock pessimism -0.120 0.380 SLICE_X148Y65 FDCE (Remov_fdce_C_CLR) -0.069 0.311 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg1_reg[39] ------------------------------------------------------------------- required time -0.311 arrival time 0.662 ------------------------------------------------------------------- slack 0.351 Slack (MET) : 0.394ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/CLR (removal check against rising-edge clock rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_2 rise@0.000ns - rxWordclkl8_2 rise@0.000ns) Data Path Delay: 0.360ns (logic 0.100ns (27.744%) route 0.260ns (72.256%)) Logic Levels: 0 Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.501ns Source Clock Delay (SCD): 0.346ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.346 0.346 ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X155Y67 FDPE r ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X155Y67 FDPE (Prop_fdpe_C_Q) 0.100 0.446 f ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.260 0.706 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X149Y64 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.501 0.501 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X149Y64 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg/C clock pessimism -0.120 0.381 SLICE_X149Y64 FDCE (Remov_fdce_C_CLR) -0.069 0.312 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/READY_O_reg ------------------------------------------------------------------- required time -0.312 arrival time 0.706 ------------------------------------------------------------------- slack 0.394 Slack (MET) : 0.397ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[36]/CLR (removal check against rising-edge clock rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_2 rise@0.000ns - rxWordclkl8_2 rise@0.000ns) Data Path Delay: 0.363ns (logic 0.100ns (27.583%) route 0.263ns (72.417%)) Logic Levels: 0 Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.501ns Source Clock Delay (SCD): 0.346ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.346 0.346 ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X155Y67 FDPE r ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X155Y67 FDPE (Prop_fdpe_C_Q) 0.100 0.446 f ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.263 0.709 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X148Y64 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[36]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.501 0.501 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X148Y64 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[36]/C clock pessimism -0.120 0.381 SLICE_X148Y64 FDCE (Remov_fdce_C_CLR) -0.069 0.312 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[36] ------------------------------------------------------------------- required time -0.312 arrival time 0.709 ------------------------------------------------------------------- slack 0.397 Slack (MET) : 0.397ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[37]/CLR (removal check against rising-edge clock rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_2 rise@0.000ns - rxWordclkl8_2 rise@0.000ns) Data Path Delay: 0.363ns (logic 0.100ns (27.583%) route 0.263ns (72.417%)) Logic Levels: 0 Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.501ns Source Clock Delay (SCD): 0.346ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.346 0.346 ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X155Y67 FDPE r ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X155Y67 FDPE (Prop_fdpe_C_Q) 0.100 0.446 f ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.263 0.709 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X148Y64 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[37]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.501 0.501 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X148Y64 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[37]/C clock pessimism -0.120 0.381 SLICE_X148Y64 FDCE (Remov_fdce_C_CLR) -0.069 0.312 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[37] ------------------------------------------------------------------- required time -0.312 arrival time 0.709 ------------------------------------------------------------------- slack 0.397 Slack (MET) : 0.397ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[38]/CLR (removal check against rising-edge clock rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_2 rise@0.000ns - rxWordclkl8_2 rise@0.000ns) Data Path Delay: 0.363ns (logic 0.100ns (27.583%) route 0.263ns (72.417%)) Logic Levels: 0 Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.501ns Source Clock Delay (SCD): 0.346ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.346 0.346 ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X155Y67 FDPE r ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X155Y67 FDPE (Prop_fdpe_C_Q) 0.100 0.446 f ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.263 0.709 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X148Y64 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[38]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.501 0.501 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X148Y64 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[38]/C clock pessimism -0.120 0.381 SLICE_X148Y64 FDCE (Remov_fdce_C_CLR) -0.069 0.312 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[38] ------------------------------------------------------------------- required time -0.312 arrival time 0.709 ------------------------------------------------------------------- slack 0.397 Slack (MET) : 0.397ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[39]/CLR (removal check against rising-edge clock rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_2 rise@0.000ns - rxWordclkl8_2 rise@0.000ns) Data Path Delay: 0.363ns (logic 0.100ns (27.583%) route 0.263ns (72.417%)) Logic Levels: 0 Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.501ns Source Clock Delay (SCD): 0.346ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.346 0.346 ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X155Y67 FDPE r ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X155Y67 FDPE (Prop_fdpe_C_Q) 0.100 0.446 f ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.263 0.709 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X148Y64 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[39]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.501 0.501 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X148Y64 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[39]/C clock pessimism -0.120 0.381 SLICE_X148Y64 FDCE (Remov_fdce_C_CLR) -0.069 0.312 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/reg0_reg[39] ------------------------------------------------------------------- required time -0.312 arrival time 0.709 ------------------------------------------------------------------- slack 0.397 Slack (MET) : 0.474ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/cnter_reg[0]/CLR (removal check against rising-edge clock rxWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_2 rise@0.000ns - rxWordclkl8_2 rise@0.000ns) Data Path Delay: 0.459ns (logic 0.100ns (21.809%) route 0.359ns (78.191%)) Logic Levels: 0 Clock Path Skew: 0.035ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.501ns Source Clock Delay (SCD): 0.346ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.346 0.346 ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/RX_FRAMECLK_I SLICE_X155Y67 FDPE r ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X155Y67 FDPE (Prop_fdpe_C_Q) 0.100 0.446 f ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.359 0.805 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X150Y64 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/cnter_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_2 rise edge) 0.000 0.000 r BUFHCE_X1Y13 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O net (fo=1057, routed) 0.501 0.501 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/CLK SLICE_X150Y64 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/cnter_reg[0]/C clock pessimism -0.120 0.381 SLICE_X150Y64 FDCE (Remov_fdce_C_CLR) -0.050 0.331 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[2].gbt_rxgearbox_inst/cnter_reg[0] ------------------------------------------------------------------- required time -0.331 arrival time 0.805 ------------------------------------------------------------------- slack 0.474 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: rxWordclkl8_3 To Clock: rxWordclkl8_3 Setup : 0 Failing Endpoints, Worst Slack 5.017ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.352ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.017ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r2_reg[3]/CLR (recovery check against rising-edge clock rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_3 rise@8.200ns - rxWordclkl8_3 rise@0.000ns) Data Path Delay: 2.706ns (logic 1.052ns (38.871%) route 1.654ns (61.129%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.229ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.686ns = ( 8.886 - 8.200 ) Source Clock Delay (SCD): 0.915ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.915 0.915 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y6 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y6 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.924 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.353 3.277 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/rx_reset_done[3] SLICE_X167Y82 LUT1 (Prop_lut1_I0_O) 0.043 3.320 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r[3]_i_1__1/O net (fo=3, routed) 0.302 3.622 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r[3]_i_1__1_n_0 SLICE_X167Y81 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r2_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 8.200 8.200 r BUFHCE_X1Y14 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.686 8.886 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_0 SLICE_X167Y81 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r2_reg[3]/C clock pessimism 0.000 8.886 clock uncertainty -0.035 8.851 SLICE_X167Y81 FDCE (Recov_fdce_C_CLR) -0.212 8.639 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r2_reg[3] ------------------------------------------------------------------- required time 8.639 arrival time -3.622 ------------------------------------------------------------------- slack 5.017 Slack (MET) : 5.017ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r3_reg[3]/CLR (recovery check against rising-edge clock rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_3 rise@8.200ns - rxWordclkl8_3 rise@0.000ns) Data Path Delay: 2.706ns (logic 1.052ns (38.871%) route 1.654ns (61.129%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.229ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.686ns = ( 8.886 - 8.200 ) Source Clock Delay (SCD): 0.915ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.915 0.915 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y6 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y6 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.924 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.353 3.277 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/rx_reset_done[3] SLICE_X167Y82 LUT1 (Prop_lut1_I0_O) 0.043 3.320 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r[3]_i_1__1/O net (fo=3, routed) 0.302 3.622 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r[3]_i_1__1_n_0 SLICE_X167Y81 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r3_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 8.200 8.200 r BUFHCE_X1Y14 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.686 8.886 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_0 SLICE_X167Y81 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r3_reg[3]/C clock pessimism 0.000 8.886 clock uncertainty -0.035 8.851 SLICE_X167Y81 FDCE (Recov_fdce_C_CLR) -0.212 8.639 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r3_reg[3] ------------------------------------------------------------------- required time 8.639 arrival time -3.622 ------------------------------------------------------------------- slack 5.017 Slack (MET) : 5.017ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r_reg[3]/CLR (recovery check against rising-edge clock rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_3 rise@8.200ns - rxWordclkl8_3 rise@0.000ns) Data Path Delay: 2.706ns (logic 1.052ns (38.871%) route 1.654ns (61.129%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.229ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.686ns = ( 8.886 - 8.200 ) Source Clock Delay (SCD): 0.915ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.915 0.915 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y6 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y6 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.924 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.353 3.277 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/rx_reset_done[3] SLICE_X167Y82 LUT1 (Prop_lut1_I0_O) 0.043 3.320 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r[3]_i_1__1/O net (fo=3, routed) 0.302 3.622 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r[3]_i_1__1_n_0 SLICE_X167Y81 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 8.200 8.200 r BUFHCE_X1Y14 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.686 8.886 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_0 SLICE_X167Y81 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r_reg[3]/C clock pessimism 0.000 8.886 clock uncertainty -0.035 8.851 SLICE_X167Y81 FDCE (Recov_fdce_C_CLR) -0.212 8.639 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxResetDone_r_reg[3] ------------------------------------------------------------------- required time 8.639 arrival time -3.622 ------------------------------------------------------------------- slack 5.017 Slack (MET) : 5.060ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/shiftPsAddr_reg/CLR (recovery check against rising-edge clock rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_3 rise@8.200ns - rxWordclkl8_3 rise@0.000ns) Data Path Delay: 2.725ns (logic 1.052ns (38.608%) route 1.673ns (61.392%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.225ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.690ns = ( 8.890 - 8.200 ) Source Clock Delay (SCD): 0.915ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.915 0.915 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y6 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y6 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.924 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.000 2.925 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] SLICE_X169Y82 LUT2 (Prop_lut2_I0_O) 0.043 2.968 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1__1/O net (fo=25, routed) 0.672 3.640 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/rx_reset_s_1 SLICE_X176Y81 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/shiftPsAddr_reg/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 8.200 8.200 r BUFHCE_X1Y14 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.690 8.890 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK SLICE_X176Y81 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/shiftPsAddr_reg/C clock pessimism 0.000 8.890 clock uncertainty -0.035 8.855 SLICE_X176Y81 FDCE (Recov_fdce_C_CLR) -0.154 8.701 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/shiftPsAddr_reg ------------------------------------------------------------------- required time 8.701 arrival time -3.640 ------------------------------------------------------------------- slack 5.060 Slack (MET) : 5.065ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[0]/CLR (recovery check against rising-edge clock rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_3 rise@8.200ns - rxWordclkl8_3 rise@0.000ns) Data Path Delay: 2.659ns (logic 1.052ns (39.562%) route 1.607ns (60.438%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.228ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.687ns = ( 8.887 - 8.200 ) Source Clock Delay (SCD): 0.915ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.915 0.915 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y6 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y6 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.924 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.000 2.925 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] SLICE_X169Y82 LUT2 (Prop_lut2_I0_O) 0.043 2.968 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1__1/O net (fo=25, routed) 0.607 3.575 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/rx_reset_s_1 SLICE_X172Y80 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 8.200 8.200 r BUFHCE_X1Y14 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.687 8.887 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK SLICE_X172Y80 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[0]/C clock pessimism 0.000 8.887 clock uncertainty -0.035 8.852 SLICE_X172Y80 FDCE (Recov_fdce_C_CLR) -0.212 8.640 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[0] ------------------------------------------------------------------- required time 8.640 arrival time -3.575 ------------------------------------------------------------------- slack 5.065 Slack (MET) : 5.065ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[1]/CLR (recovery check against rising-edge clock rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_3 rise@8.200ns - rxWordclkl8_3 rise@0.000ns) Data Path Delay: 2.659ns (logic 1.052ns (39.562%) route 1.607ns (60.438%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.228ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.687ns = ( 8.887 - 8.200 ) Source Clock Delay (SCD): 0.915ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.915 0.915 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y6 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y6 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.924 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.000 2.925 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] SLICE_X169Y82 LUT2 (Prop_lut2_I0_O) 0.043 2.968 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1__1/O net (fo=25, routed) 0.607 3.575 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/rx_reset_s_1 SLICE_X172Y80 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 8.200 8.200 r BUFHCE_X1Y14 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.687 8.887 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK SLICE_X172Y80 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[1]/C clock pessimism 0.000 8.887 clock uncertainty -0.035 8.852 SLICE_X172Y80 FDCE (Recov_fdce_C_CLR) -0.212 8.640 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[1] ------------------------------------------------------------------- required time 8.640 arrival time -3.575 ------------------------------------------------------------------- slack 5.065 Slack (MET) : 5.093ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[1]/CLR (recovery check against rising-edge clock rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_3 rise@8.200ns - rxWordclkl8_3 rise@0.000ns) Data Path Delay: 2.634ns (logic 1.052ns (39.934%) route 1.582ns (60.066%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.225ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.690ns = ( 8.890 - 8.200 ) Source Clock Delay (SCD): 0.915ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.915 0.915 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y6 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y6 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.924 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.000 2.925 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] SLICE_X169Y82 LUT2 (Prop_lut2_I0_O) 0.043 2.968 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1__1/O net (fo=25, routed) 0.582 3.550 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_RESET_I SLICE_X172Y84 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 8.200 8.200 r BUFHCE_X1Y14 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.690 8.890 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_WORDCLK_I SLICE_X172Y84 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[1]/C clock pessimism 0.000 8.890 clock uncertainty -0.035 8.855 SLICE_X172Y84 FDCE (Recov_fdce_C_CLR) -0.212 8.643 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[1] ------------------------------------------------------------------- required time 8.643 arrival time -3.550 ------------------------------------------------------------------- slack 5.093 Slack (MET) : 5.093ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[2]/CLR (recovery check against rising-edge clock rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_3 rise@8.200ns - rxWordclkl8_3 rise@0.000ns) Data Path Delay: 2.634ns (logic 1.052ns (39.934%) route 1.582ns (60.066%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.225ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.690ns = ( 8.890 - 8.200 ) Source Clock Delay (SCD): 0.915ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.915 0.915 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y6 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y6 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.924 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.000 2.925 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] SLICE_X169Y82 LUT2 (Prop_lut2_I0_O) 0.043 2.968 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1__1/O net (fo=25, routed) 0.582 3.550 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_RESET_I SLICE_X172Y84 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 8.200 8.200 r BUFHCE_X1Y14 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.690 8.890 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_WORDCLK_I SLICE_X172Y84 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[2]/C clock pessimism 0.000 8.890 clock uncertainty -0.035 8.855 SLICE_X172Y84 FDCE (Recov_fdce_C_CLR) -0.212 8.643 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[2] ------------------------------------------------------------------- required time 8.643 arrival time -3.550 ------------------------------------------------------------------- slack 5.093 Slack (MET) : 5.113ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[3]/CLR (recovery check against rising-edge clock rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_3 rise@8.200ns - rxWordclkl8_3 rise@0.000ns) Data Path Delay: 2.639ns (logic 1.052ns (39.858%) route 1.587ns (60.142%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.225ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.690ns = ( 8.890 - 8.200 ) Source Clock Delay (SCD): 0.915ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.915 0.915 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y6 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y6 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.924 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.000 2.925 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] SLICE_X169Y82 LUT2 (Prop_lut2_I0_O) 0.043 2.968 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1__1/O net (fo=25, routed) 0.587 3.555 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/rx_reset_s_1 SLICE_X176Y80 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 8.200 8.200 r BUFHCE_X1Y14 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.690 8.890 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK SLICE_X176Y80 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[3]/C clock pessimism 0.000 8.890 clock uncertainty -0.035 8.855 SLICE_X176Y80 FDCE (Recov_fdce_C_CLR) -0.187 8.668 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[3] ------------------------------------------------------------------- required time 8.668 arrival time -3.555 ------------------------------------------------------------------- slack 5.113 Slack (MET) : 5.113ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[4]/CLR (recovery check against rising-edge clock rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_3 rise@8.200ns - rxWordclkl8_3 rise@0.000ns) Data Path Delay: 2.639ns (logic 1.052ns (39.858%) route 1.587ns (60.142%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.225ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.690ns = ( 8.890 - 8.200 ) Source Clock Delay (SCD): 0.915ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.915 0.915 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y6 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y6 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.924 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 1.000 2.925 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/out[0] SLICE_X169Y82 LUT2 (Prop_lut2_I0_O) 0.043 2.968 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1__1/O net (fo=25, routed) 0.587 3.555 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/rx_reset_s_1 SLICE_X176Y80 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 8.200 8.200 r BUFHCE_X1Y14 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.690 8.890 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/CLK SLICE_X176Y80 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[4]/C clock pessimism 0.000 8.890 clock uncertainty -0.035 8.855 SLICE_X176Y80 FDCE (Recov_fdce_C_CLR) -0.187 8.668 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[4] ------------------------------------------------------------------- required time 8.668 arrival time -3.555 ------------------------------------------------------------------- slack 5.113 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.352ns (arrival time - required time) Source: ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[26]/CLR (removal check against rising-edge clock rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_3 rise@0.000ns - rxWordclkl8_3 rise@0.000ns) Data Path Delay: 0.313ns (logic 0.100ns (31.920%) route 0.213ns (68.080%)) Logic Levels: 0 Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.503ns Source Clock Delay (SCD): 0.350ns Clock Pessimism Removal (CPR): 0.142ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.350 0.350 ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X163Y85 FDRE r ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X163Y85 FDRE (Prop_fdre_C_Q) 0.100 0.450 f ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.213 0.663 ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Reset SLICE_X162Y85 FDCE f ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[26]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.503 0.503 ngFEC/SFP_GEN[7].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X162Y85 FDCE r ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[26]/C clock pessimism -0.142 0.361 SLICE_X162Y85 FDCE (Remov_fdce_C_CLR) -0.050 0.311 ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[26] ------------------------------------------------------------------- required time -0.311 arrival time 0.663 ------------------------------------------------------------------- slack 0.352 Slack (MET) : 0.352ns (arrival time - required time) Source: ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[29]/CLR (removal check against rising-edge clock rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_3 rise@0.000ns - rxWordclkl8_3 rise@0.000ns) Data Path Delay: 0.313ns (logic 0.100ns (31.920%) route 0.213ns (68.080%)) Logic Levels: 0 Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.503ns Source Clock Delay (SCD): 0.350ns Clock Pessimism Removal (CPR): 0.142ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.350 0.350 ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X163Y85 FDRE r ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X163Y85 FDRE (Prop_fdre_C_Q) 0.100 0.450 f ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.213 0.663 ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Reset SLICE_X162Y85 FDCE f ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[29]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.503 0.503 ngFEC/SFP_GEN[7].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X162Y85 FDCE r ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[29]/C clock pessimism -0.142 0.361 SLICE_X162Y85 FDCE (Remov_fdce_C_CLR) -0.050 0.311 ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[29] ------------------------------------------------------------------- required time -0.311 arrival time 0.663 ------------------------------------------------------------------- slack 0.352 Slack (MET) : 0.352ns (arrival time - required time) Source: ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[30]/CLR (removal check against rising-edge clock rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_3 rise@0.000ns - rxWordclkl8_3 rise@0.000ns) Data Path Delay: 0.313ns (logic 0.100ns (31.920%) route 0.213ns (68.080%)) Logic Levels: 0 Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.503ns Source Clock Delay (SCD): 0.350ns Clock Pessimism Removal (CPR): 0.142ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.350 0.350 ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X163Y85 FDRE r ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X163Y85 FDRE (Prop_fdre_C_Q) 0.100 0.450 f ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.213 0.663 ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Reset SLICE_X162Y85 FDCE f ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[30]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.503 0.503 ngFEC/SFP_GEN[7].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X162Y85 FDCE r ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[30]/C clock pessimism -0.142 0.361 SLICE_X162Y85 FDCE (Remov_fdce_C_CLR) -0.050 0.311 ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[30] ------------------------------------------------------------------- required time -0.311 arrival time 0.663 ------------------------------------------------------------------- slack 0.352 Slack (MET) : 0.352ns (arrival time - required time) Source: ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[31]/CLR (removal check against rising-edge clock rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_3 rise@0.000ns - rxWordclkl8_3 rise@0.000ns) Data Path Delay: 0.313ns (logic 0.100ns (31.920%) route 0.213ns (68.080%)) Logic Levels: 0 Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.503ns Source Clock Delay (SCD): 0.350ns Clock Pessimism Removal (CPR): 0.142ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.350 0.350 ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X163Y85 FDRE r ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X163Y85 FDRE (Prop_fdre_C_Q) 0.100 0.450 f ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.213 0.663 ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Reset SLICE_X162Y85 FDCE f ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[31]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.503 0.503 ngFEC/SFP_GEN[7].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X162Y85 FDCE r ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[31]/C clock pessimism -0.142 0.361 SLICE_X162Y85 FDCE (Remov_fdce_C_CLR) -0.050 0.311 ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[31] ------------------------------------------------------------------- required time -0.311 arrival time 0.663 ------------------------------------------------------------------- slack 0.352 Slack (MET) : 0.365ns (arrival time - required time) Source: ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[16]/CLR (removal check against rising-edge clock rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_3 rise@0.000ns - rxWordclkl8_3 rise@0.000ns) Data Path Delay: 0.307ns (logic 0.100ns (32.608%) route 0.207ns (67.392%)) Logic Levels: 0 Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.501ns Source Clock Delay (SCD): 0.350ns Clock Pessimism Removal (CPR): 0.140ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.350 0.350 ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X163Y85 FDRE r ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X163Y85 FDRE (Prop_fdre_C_Q) 0.100 0.450 f ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.207 0.657 ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Reset SLICE_X163Y83 FDCE f ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[16]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.501 0.501 ngFEC/SFP_GEN[7].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X163Y83 FDCE r ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[16]/C clock pessimism -0.140 0.361 SLICE_X163Y83 FDCE (Remov_fdce_C_CLR) -0.069 0.292 ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[16] ------------------------------------------------------------------- required time -0.292 arrival time 0.657 ------------------------------------------------------------------- slack 0.365 Slack (MET) : 0.365ns (arrival time - required time) Source: ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR (removal check against rising-edge clock rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_3 rise@0.000ns - rxWordclkl8_3 rise@0.000ns) Data Path Delay: 0.307ns (logic 0.100ns (32.608%) route 0.207ns (67.392%)) Logic Levels: 0 Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.501ns Source Clock Delay (SCD): 0.350ns Clock Pessimism Removal (CPR): 0.140ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.350 0.350 ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X163Y85 FDRE r ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X163Y85 FDRE (Prop_fdre_C_Q) 0.100 0.450 f ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.207 0.657 ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Reset SLICE_X163Y83 FDCE f ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[17]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.501 0.501 ngFEC/SFP_GEN[7].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X163Y83 FDCE r ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[17]/C clock pessimism -0.140 0.361 SLICE_X163Y83 FDCE (Remov_fdce_C_CLR) -0.069 0.292 ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[17] ------------------------------------------------------------------- required time -0.292 arrival time 0.657 ------------------------------------------------------------------- slack 0.365 Slack (MET) : 0.365ns (arrival time - required time) Source: ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR (removal check against rising-edge clock rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_3 rise@0.000ns - rxWordclkl8_3 rise@0.000ns) Data Path Delay: 0.307ns (logic 0.100ns (32.608%) route 0.207ns (67.392%)) Logic Levels: 0 Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.501ns Source Clock Delay (SCD): 0.350ns Clock Pessimism Removal (CPR): 0.140ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.350 0.350 ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X163Y85 FDRE r ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X163Y85 FDRE (Prop_fdre_C_Q) 0.100 0.450 f ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.207 0.657 ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Reset SLICE_X163Y83 FDCE f ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[18]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.501 0.501 ngFEC/SFP_GEN[7].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X163Y83 FDCE r ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[18]/C clock pessimism -0.140 0.361 SLICE_X163Y83 FDCE (Remov_fdce_C_CLR) -0.069 0.292 ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[18] ------------------------------------------------------------------- required time -0.292 arrival time 0.657 ------------------------------------------------------------------- slack 0.365 Slack (MET) : 0.365ns (arrival time - required time) Source: ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[19]/CLR (removal check against rising-edge clock rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_3 rise@0.000ns - rxWordclkl8_3 rise@0.000ns) Data Path Delay: 0.307ns (logic 0.100ns (32.608%) route 0.207ns (67.392%)) Logic Levels: 0 Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.501ns Source Clock Delay (SCD): 0.350ns Clock Pessimism Removal (CPR): 0.140ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.350 0.350 ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X163Y85 FDRE r ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X163Y85 FDRE (Prop_fdre_C_Q) 0.100 0.450 f ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.207 0.657 ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Reset SLICE_X163Y83 FDCE f ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[19]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.501 0.501 ngFEC/SFP_GEN[7].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X163Y83 FDCE r ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[19]/C clock pessimism -0.140 0.361 SLICE_X163Y83 FDCE (Remov_fdce_C_CLR) -0.069 0.292 ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[19] ------------------------------------------------------------------- required time -0.292 arrival time 0.657 ------------------------------------------------------------------- slack 0.365 Slack (MET) : 0.365ns (arrival time - required time) Source: ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR (removal check against rising-edge clock rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_3 rise@0.000ns - rxWordclkl8_3 rise@0.000ns) Data Path Delay: 0.307ns (logic 0.100ns (32.608%) route 0.207ns (67.392%)) Logic Levels: 0 Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.501ns Source Clock Delay (SCD): 0.350ns Clock Pessimism Removal (CPR): 0.140ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.350 0.350 ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X163Y85 FDRE r ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X163Y85 FDRE (Prop_fdre_C_Q) 0.100 0.450 f ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.207 0.657 ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Reset SLICE_X163Y83 FDCE f ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[21]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.501 0.501 ngFEC/SFP_GEN[7].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X163Y83 FDCE r ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[21]/C clock pessimism -0.140 0.361 SLICE_X163Y83 FDCE (Remov_fdce_C_CLR) -0.069 0.292 ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[21] ------------------------------------------------------------------- required time -0.292 arrival time 0.657 ------------------------------------------------------------------- slack 0.365 Slack (MET) : 0.365ns (arrival time - required time) Source: ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR (removal check against rising-edge clock rxWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_3 rise@0.000ns - rxWordclkl8_3 rise@0.000ns) Data Path Delay: 0.307ns (logic 0.100ns (32.608%) route 0.207ns (67.392%)) Logic Levels: 0 Clock Path Skew: 0.011ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.501ns Source Clock Delay (SCD): 0.350ns Clock Pessimism Removal (CPR): 0.140ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.350 0.350 ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X163Y85 FDRE r ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X163Y85 FDRE (Prop_fdre_C_Q) 0.100 0.450 f ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.207 0.657 ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Reset SLICE_X163Y83 FDCE f ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[23]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_3 rise edge) 0.000 0.000 r BUFHCE_X1Y14 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O net (fo=1057, routed) 0.501 0.501 ngFEC/SFP_GEN[7].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X163Y83 FDCE r ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[23]/C clock pessimism -0.140 0.361 SLICE_X163Y83 FDCE (Remov_fdce_C_CLR) -0.069 0.292 ngFEC/SFP_GEN[7].ngCCM_gbt/RX_Word_rx40_reg[23] ------------------------------------------------------------------- required time -0.292 arrival time 0.657 ------------------------------------------------------------------- slack 0.365 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: rxWordclkl8_4 To Clock: rxWordclkl8_4 Setup : 0 Failing Endpoints, Worst Slack 5.184ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.390ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.184ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/shiftPsAddr_reg/CLR (recovery check against rising-edge clock rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_4 rise@8.200ns - rxWordclkl8_4 rise@0.000ns) Data Path Delay: 2.600ns (logic 1.052ns (40.467%) route 1.548ns (59.533%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.227ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.695ns = ( 8.895 - 8.200 ) Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.922 0.922 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y7 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y7 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.931 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 0.686 2.618 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/out[0] SLICE_X180Y91 LUT2 (Prop_lut2_I0_O) 0.043 2.661 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/gtxLatOpt_gen[4].rxBitSlipControl_i_1/O net (fo=25, routed) 0.862 3.522 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/rx_reset_s_0 SLICE_X178Y86 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/shiftPsAddr_reg/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 8.200 8.200 r BUFHCE_X1Y15 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.695 8.895 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/CLK SLICE_X178Y86 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/shiftPsAddr_reg/C clock pessimism 0.000 8.895 clock uncertainty -0.035 8.860 SLICE_X178Y86 FDCE (Recov_fdce_C_CLR) -0.154 8.706 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/shiftPsAddr_reg ------------------------------------------------------------------- required time 8.706 arrival time -3.522 ------------------------------------------------------------------- slack 5.184 Slack (MET) : 5.184ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxBitSlipControl/READY_o_reg/CLR (recovery check against rising-edge clock rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_4 rise@8.200ns - rxWordclkl8_4 rise@0.000ns) Data Path Delay: 2.600ns (logic 1.052ns (40.467%) route 1.548ns (59.533%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.227ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.695ns = ( 8.895 - 8.200 ) Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.922 0.922 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y7 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y7 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.931 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 0.686 2.618 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/out[0] SLICE_X180Y91 LUT2 (Prop_lut2_I0_O) 0.043 2.661 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/gtxLatOpt_gen[4].rxBitSlipControl_i_1/O net (fo=25, routed) 0.862 3.522 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxBitSlipControl/RX_RESET_I SLICE_X178Y86 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxBitSlipControl/READY_o_reg/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 8.200 8.200 r BUFHCE_X1Y15 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.695 8.895 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxBitSlipControl/RX_WORDCLK_I SLICE_X178Y86 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxBitSlipControl/READY_o_reg/C clock pessimism 0.000 8.895 clock uncertainty -0.035 8.860 SLICE_X178Y86 FDCE (Recov_fdce_C_CLR) -0.154 8.706 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxBitSlipControl/READY_o_reg ------------------------------------------------------------------- required time 8.706 arrival time -3.522 ------------------------------------------------------------------- slack 5.184 Slack (MET) : 5.303ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/RX_HEADER_LOCKED_O_reg/CLR (recovery check against rising-edge clock rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_4 rise@8.200ns - rxWordclkl8_4 rise@0.000ns) Data Path Delay: 2.422ns (logic 1.052ns (43.435%) route 1.370ns (56.565%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: -0.227ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.695ns = ( 8.895 - 8.200 ) Source Clock Delay (SCD): 0.922ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.922 0.922 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxusrclk2_in GTXE2_CHANNEL_X0Y7 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y7 GTXE2_CHANNEL (Prop_gtxe2_channel_RXUSRCLK2_RXRESETDONE) 1.009 1.931 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXRESETDONE net (fo=5, routed) 0.686 2.618 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/out[0] SLICE_X180Y91 LUT2 (Prop_lut2_I0_O) 0.043 2.661 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/gtxLatOpt_gen[4].rxBitSlipControl_i_1/O net (fo=25, routed) 0.684 3.345 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/rx_reset_s_0 SLICE_X175Y93 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/RX_HEADER_LOCKED_O_reg/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 8.200 8.200 r BUFHCE_X1Y15 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.695 8.895 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/CLK SLICE_X175Y93 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/RX_HEADER_LOCKED_O_reg/C clock pessimism 0.000 8.895 clock uncertainty -0.035 8.860 SLICE_X175Y93 FDCE (Recov_fdce_C_CLR) -0.212 8.648 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/RX_HEADER_LOCKED_O_reg ------------------------------------------------------------------- required time 8.648 arrival time -3.345 ------------------------------------------------------------------- slack 5.303 Slack (MET) : 5.315ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[32]/CLR (recovery check against rising-edge clock rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_4 rise@8.200ns - rxWordclkl8_4 rise@0.000ns) Data Path Delay: 2.634ns (logic 0.259ns (9.832%) route 2.375ns (90.168%)) Logic Levels: 0 Clock Path Skew: -0.003ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.692ns = ( 8.892 - 8.200 ) Source Clock Delay (SCD): 0.695ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.695 0.695 ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 SLICE_X162Y88 FDPE r ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X162Y88 FDPE (Prop_fdpe_C_Q) 0.259 0.954 f ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 2.375 3.329 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X175Y86 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[32]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 8.200 8.200 r BUFHCE_X1Y15 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.692 8.892 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X175Y86 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[32]/C clock pessimism 0.000 8.892 clock uncertainty -0.035 8.857 SLICE_X175Y86 FDCE (Recov_fdce_C_CLR) -0.212 8.645 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[32] ------------------------------------------------------------------- required time 8.645 arrival time -3.329 ------------------------------------------------------------------- slack 5.315 Slack (MET) : 5.315ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[34]/CLR (recovery check against rising-edge clock rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_4 rise@8.200ns - rxWordclkl8_4 rise@0.000ns) Data Path Delay: 2.634ns (logic 0.259ns (9.832%) route 2.375ns (90.168%)) Logic Levels: 0 Clock Path Skew: -0.003ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.692ns = ( 8.892 - 8.200 ) Source Clock Delay (SCD): 0.695ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.695 0.695 ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 SLICE_X162Y88 FDPE r ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X162Y88 FDPE (Prop_fdpe_C_Q) 0.259 0.954 f ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 2.375 3.329 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X175Y86 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[34]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 8.200 8.200 r BUFHCE_X1Y15 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.692 8.892 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X175Y86 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[34]/C clock pessimism 0.000 8.892 clock uncertainty -0.035 8.857 SLICE_X175Y86 FDCE (Recov_fdce_C_CLR) -0.212 8.645 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[34] ------------------------------------------------------------------- required time 8.645 arrival time -3.329 ------------------------------------------------------------------- slack 5.315 Slack (MET) : 5.315ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[64]/CLR (recovery check against rising-edge clock rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_4 rise@8.200ns - rxWordclkl8_4 rise@0.000ns) Data Path Delay: 2.634ns (logic 0.259ns (9.832%) route 2.375ns (90.168%)) Logic Levels: 0 Clock Path Skew: -0.003ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.692ns = ( 8.892 - 8.200 ) Source Clock Delay (SCD): 0.695ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.695 0.695 ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 SLICE_X162Y88 FDPE r ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X162Y88 FDPE (Prop_fdpe_C_Q) 0.259 0.954 f ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 2.375 3.329 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X175Y86 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[64]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 8.200 8.200 r BUFHCE_X1Y15 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.692 8.892 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X175Y86 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[64]/C clock pessimism 0.000 8.892 clock uncertainty -0.035 8.857 SLICE_X175Y86 FDCE (Recov_fdce_C_CLR) -0.212 8.645 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[64] ------------------------------------------------------------------- required time 8.645 arrival time -3.329 ------------------------------------------------------------------- slack 5.315 Slack (MET) : 5.315ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[65]/CLR (recovery check against rising-edge clock rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_4 rise@8.200ns - rxWordclkl8_4 rise@0.000ns) Data Path Delay: 2.634ns (logic 0.259ns (9.832%) route 2.375ns (90.168%)) Logic Levels: 0 Clock Path Skew: -0.003ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.692ns = ( 8.892 - 8.200 ) Source Clock Delay (SCD): 0.695ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.695 0.695 ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 SLICE_X162Y88 FDPE r ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X162Y88 FDPE (Prop_fdpe_C_Q) 0.259 0.954 f ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 2.375 3.329 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X175Y86 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[65]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 8.200 8.200 r BUFHCE_X1Y15 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.692 8.892 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X175Y86 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[65]/C clock pessimism 0.000 8.892 clock uncertainty -0.035 8.857 SLICE_X175Y86 FDCE (Recov_fdce_C_CLR) -0.212 8.645 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[65] ------------------------------------------------------------------- required time 8.645 arrival time -3.329 ------------------------------------------------------------------- slack 5.315 Slack (MET) : 5.400ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[40]/CLR (recovery check against rising-edge clock rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_4 rise@8.200ns - rxWordclkl8_4 rise@0.000ns) Data Path Delay: 2.550ns (logic 0.259ns (10.157%) route 2.291ns (89.843%)) Logic Levels: 0 Clock Path Skew: -0.003ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.692ns = ( 8.892 - 8.200 ) Source Clock Delay (SCD): 0.695ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.695 0.695 ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 SLICE_X162Y88 FDPE r ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X162Y88 FDPE (Prop_fdpe_C_Q) 0.259 0.954 f ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 2.291 3.245 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X175Y87 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[40]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 8.200 8.200 r BUFHCE_X1Y15 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.692 8.892 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X175Y87 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[40]/C clock pessimism 0.000 8.892 clock uncertainty -0.035 8.857 SLICE_X175Y87 FDCE (Recov_fdce_C_CLR) -0.212 8.645 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[40] ------------------------------------------------------------------- required time 8.645 arrival time -3.245 ------------------------------------------------------------------- slack 5.400 Slack (MET) : 5.400ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[43]/CLR (recovery check against rising-edge clock rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_4 rise@8.200ns - rxWordclkl8_4 rise@0.000ns) Data Path Delay: 2.550ns (logic 0.259ns (10.157%) route 2.291ns (89.843%)) Logic Levels: 0 Clock Path Skew: -0.003ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.692ns = ( 8.892 - 8.200 ) Source Clock Delay (SCD): 0.695ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.695 0.695 ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 SLICE_X162Y88 FDPE r ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X162Y88 FDPE (Prop_fdpe_C_Q) 0.259 0.954 f ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 2.291 3.245 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X175Y87 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[43]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 8.200 8.200 r BUFHCE_X1Y15 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.692 8.892 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X175Y87 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[43]/C clock pessimism 0.000 8.892 clock uncertainty -0.035 8.857 SLICE_X175Y87 FDCE (Recov_fdce_C_CLR) -0.212 8.645 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[43] ------------------------------------------------------------------- required time 8.645 arrival time -3.245 ------------------------------------------------------------------- slack 5.400 Slack (MET) : 5.400ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[66]/CLR (recovery check against rising-edge clock rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (rxWordclkl8_4 rise@8.200ns - rxWordclkl8_4 rise@0.000ns) Data Path Delay: 2.550ns (logic 0.259ns (10.157%) route 2.291ns (89.843%)) Logic Levels: 0 Clock Path Skew: -0.003ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.692ns = ( 8.892 - 8.200 ) Source Clock Delay (SCD): 0.695ns Clock Pessimism Removal (CPR): 0.000ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.695 0.695 ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 SLICE_X162Y88 FDPE r ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X162Y88 FDPE (Prop_fdpe_C_Q) 0.259 0.954 f ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 2.291 3.245 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X175Y87 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[66]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 8.200 8.200 r BUFHCE_X1Y15 BUFH 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.692 8.892 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X175Y87 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[66]/C clock pessimism 0.000 8.892 clock uncertainty -0.035 8.857 SLICE_X175Y87 FDCE (Recov_fdce_C_CLR) -0.212 8.645 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[66] ------------------------------------------------------------------- required time 8.645 arrival time -3.245 ------------------------------------------------------------------- slack 5.400 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.390ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C (rising edge-triggered cell FDCE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE (removal check against rising-edge clock rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_4 rise@0.000ns - rxWordclkl8_4 rise@0.000ns) Data Path Delay: 0.352ns (logic 0.146ns (41.453%) route 0.206ns (58.547%)) Logic Levels: 1 (LUT2=1) Clock Path Skew: 0.014ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.506ns Source Clock Delay (SCD): 0.352ns Clock Pessimism Removal (CPR): 0.140ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.352 0.352 ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 SLICE_X162Y89 FDCE r ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X162Y89 FDCE (Prop_fdce_C_Q) 0.118 0.470 r ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s_reg/Q net (fo=1, routed) 0.116 0.586 ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_sync_s SLICE_X163Y89 LUT2 (Prop_lut2_I1_O) 0.028 0.614 f ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_i_1__10/O net (fo=1, routed) 0.091 0.704 ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s0 SLICE_X162Y88 FDPE f ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.506 0.506 ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 SLICE_X162Y88 FDPE r ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C clock pessimism -0.140 0.366 SLICE_X162Y88 FDPE (Remov_fdpe_C_PRE) -0.052 0.314 ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg ------------------------------------------------------------------- required time -0.314 arrival time 0.704 ------------------------------------------------------------------- slack 0.390 Slack (MET) : 0.418ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[76]/CLR (removal check against rising-edge clock rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_4 rise@0.000ns - rxWordclkl8_4 rise@0.000ns) Data Path Delay: 0.411ns (logic 0.118ns (28.684%) route 0.293ns (71.316%)) Logic Levels: 0 Clock Path Skew: 0.062ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.534ns Source Clock Delay (SCD): 0.352ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.352 0.352 ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 SLICE_X162Y88 FDPE r ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X162Y88 FDPE (Prop_fdpe_C_Q) 0.118 0.470 f ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.293 0.763 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X167Y91 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[76]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.534 0.534 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X167Y91 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[76]/C clock pessimism -0.120 0.414 SLICE_X167Y91 FDCE (Remov_fdce_C_CLR) -0.069 0.345 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[76] ------------------------------------------------------------------- required time -0.345 arrival time 0.763 ------------------------------------------------------------------- slack 0.418 Slack (MET) : 0.418ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[77]/CLR (removal check against rising-edge clock rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_4 rise@0.000ns - rxWordclkl8_4 rise@0.000ns) Data Path Delay: 0.411ns (logic 0.118ns (28.684%) route 0.293ns (71.316%)) Logic Levels: 0 Clock Path Skew: 0.062ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.534ns Source Clock Delay (SCD): 0.352ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.352 0.352 ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 SLICE_X162Y88 FDPE r ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X162Y88 FDPE (Prop_fdpe_C_Q) 0.118 0.470 f ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.293 0.763 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X167Y91 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[77]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.534 0.534 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X167Y91 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[77]/C clock pessimism -0.120 0.414 SLICE_X167Y91 FDCE (Remov_fdce_C_CLR) -0.069 0.345 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[77] ------------------------------------------------------------------- required time -0.345 arrival time 0.763 ------------------------------------------------------------------- slack 0.418 Slack (MET) : 0.418ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[78]/CLR (removal check against rising-edge clock rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_4 rise@0.000ns - rxWordclkl8_4 rise@0.000ns) Data Path Delay: 0.411ns (logic 0.118ns (28.684%) route 0.293ns (71.316%)) Logic Levels: 0 Clock Path Skew: 0.062ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.534ns Source Clock Delay (SCD): 0.352ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.352 0.352 ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 SLICE_X162Y88 FDPE r ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X162Y88 FDPE (Prop_fdpe_C_Q) 0.118 0.470 f ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.293 0.763 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X167Y91 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[78]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.534 0.534 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X167Y91 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[78]/C clock pessimism -0.120 0.414 SLICE_X167Y91 FDCE (Remov_fdce_C_CLR) -0.069 0.345 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[78] ------------------------------------------------------------------- required time -0.345 arrival time 0.763 ------------------------------------------------------------------- slack 0.418 Slack (MET) : 0.418ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[79]/CLR (removal check against rising-edge clock rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_4 rise@0.000ns - rxWordclkl8_4 rise@0.000ns) Data Path Delay: 0.411ns (logic 0.118ns (28.684%) route 0.293ns (71.316%)) Logic Levels: 0 Clock Path Skew: 0.062ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.534ns Source Clock Delay (SCD): 0.352ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.352 0.352 ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 SLICE_X162Y88 FDPE r ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X162Y88 FDPE (Prop_fdpe_C_Q) 0.118 0.470 f ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.293 0.763 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X167Y91 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[79]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.534 0.534 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X167Y91 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[79]/C clock pessimism -0.120 0.414 SLICE_X167Y91 FDCE (Remov_fdce_C_CLR) -0.069 0.345 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg0_reg[79] ------------------------------------------------------------------- required time -0.345 arrival time 0.763 ------------------------------------------------------------------- slack 0.418 Slack (MET) : 0.449ns (arrival time - required time) Source: ngFEC/SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR (removal check against rising-edge clock rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_4 rise@0.000ns - rxWordclkl8_4 rise@0.000ns) Data Path Delay: 0.417ns (logic 0.118ns (28.325%) route 0.299ns (71.675%)) Logic Levels: 0 Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.506ns Source Clock Delay (SCD): 0.349ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.349 0.349 ngFEC/SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X146Y94 FDRE r ngFEC/SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X146Y94 FDRE (Prop_fdre_C_Q) 0.118 0.467 f ngFEC/SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.299 0.766 ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Reset SLICE_X156Y91 FDCE f ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[36]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.506 0.506 ngFEC/SFP_GEN[8].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X156Y91 FDCE r ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[36]/C clock pessimism -0.120 0.386 SLICE_X156Y91 FDCE (Remov_fdce_C_CLR) -0.069 0.317 ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[36] ------------------------------------------------------------------- required time -0.317 arrival time 0.766 ------------------------------------------------------------------- slack 0.449 Slack (MET) : 0.449ns (arrival time - required time) Source: ngFEC/SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR (removal check against rising-edge clock rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_4 rise@0.000ns - rxWordclkl8_4 rise@0.000ns) Data Path Delay: 0.417ns (logic 0.118ns (28.325%) route 0.299ns (71.675%)) Logic Levels: 0 Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.506ns Source Clock Delay (SCD): 0.349ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.349 0.349 ngFEC/SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X146Y94 FDRE r ngFEC/SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X146Y94 FDRE (Prop_fdre_C_Q) 0.118 0.467 f ngFEC/SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.299 0.766 ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Reset SLICE_X156Y91 FDCE f ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[38]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.506 0.506 ngFEC/SFP_GEN[8].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X156Y91 FDCE r ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[38]/C clock pessimism -0.120 0.386 SLICE_X156Y91 FDCE (Remov_fdce_C_CLR) -0.069 0.317 ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[38] ------------------------------------------------------------------- required time -0.317 arrival time 0.766 ------------------------------------------------------------------- slack 0.449 Slack (MET) : 0.449ns (arrival time - required time) Source: ngFEC/SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[4]/CLR (removal check against rising-edge clock rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_4 rise@0.000ns - rxWordclkl8_4 rise@0.000ns) Data Path Delay: 0.417ns (logic 0.118ns (28.325%) route 0.299ns (71.675%)) Logic Levels: 0 Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.506ns Source Clock Delay (SCD): 0.349ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.349 0.349 ngFEC/SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X146Y94 FDRE r ngFEC/SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X146Y94 FDRE (Prop_fdre_C_Q) 0.118 0.467 f ngFEC/SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.299 0.766 ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Reset SLICE_X156Y91 FDCE f ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.506 0.506 ngFEC/SFP_GEN[8].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X156Y91 FDCE r ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[4]/C clock pessimism -0.120 0.386 SLICE_X156Y91 FDCE (Remov_fdce_C_CLR) -0.069 0.317 ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[4] ------------------------------------------------------------------- required time -0.317 arrival time 0.766 ------------------------------------------------------------------- slack 0.449 Slack (MET) : 0.449ns (arrival time - required time) Source: ngFEC/SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C (rising edge-triggered cell FDRE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[6]/CLR (removal check against rising-edge clock rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_4 rise@0.000ns - rxWordclkl8_4 rise@0.000ns) Data Path Delay: 0.417ns (logic 0.118ns (28.325%) route 0.299ns (71.675%)) Logic Levels: 0 Clock Path Skew: 0.037ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.506ns Source Clock Delay (SCD): 0.349ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.349 0.349 ngFEC/SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/MGT_RXUSRCLK_o[0] SLICE_X146Y94 FDRE r ngFEC/SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/C ------------------------------------------------------------------- ------------------- SLICE_X146Y94 FDRE (Prop_fdre_C_Q) 0.118 0.467 f ngFEC/SFP_GEN[8].ngCCM_gbt/Sync_RX_Reset/sync_o_reg/Q net (fo=82, routed) 0.299 0.766 ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Reset SLICE_X156Y91 FDCE f ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[6]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.506 0.506 ngFEC/SFP_GEN[8].ngCCM_gbt/MGT_RXUSRCLK_o[0] SLICE_X156Y91 FDCE r ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[6]/C clock pessimism -0.120 0.386 SLICE_X156Y91 FDCE (Remov_fdce_C_CLR) -0.069 0.317 ngFEC/SFP_GEN[8].ngCCM_gbt/RX_Word_rx40_reg[6] ------------------------------------------------------------------- required time -0.317 arrival time 0.766 ------------------------------------------------------------------- slack 0.449 Slack (MET) : 0.456ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C (rising edge-triggered cell FDPE clocked by rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[20]/CLR (removal check against rising-edge clock rxWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (rxWordclkl8_4 rise@0.000ns - rxWordclkl8_4 rise@0.000ns) Data Path Delay: 0.449ns (logic 0.118ns (26.299%) route 0.331ns (73.701%)) Logic Levels: 0 Clock Path Skew: 0.062ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.534ns Source Clock Delay (SCD): 0.352ns Clock Pessimism Removal (CPR): 0.120ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.352 0.352 ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReady_s_reg_0 SLICE_X162Y88 FDPE r ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/C ------------------------------------------------------------------- ------------------- SLICE_X162Y88 FDPE (Prop_fdpe_C_Q) 0.118 0.470 f ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/Q net (fo=225, routed) 0.331 0.801 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/gbt_rxreset_s[0] SLICE_X167Y90 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[20]/CLR ------------------------------------------------------------------- ------------------- (clock rxWordclkl8_4 rise edge) 0.000 0.000 r BUFHCE_X1Y15 BUFH 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O net (fo=1057, routed) 0.534 0.534 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/CLK SLICE_X167Y90 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[20]/C clock pessimism -0.120 0.414 SLICE_X167Y90 FDCE (Remov_fdce_C_CLR) -0.069 0.345 ngFEC/gbtbank4_l8_112/gbt_inst/gbt_rxgearbox_multilink_gen[4].gbt_rxgearbox_inst/reg1_reg[20] ------------------------------------------------------------------- required time -0.345 arrival time 0.801 ------------------------------------------------------------------- slack 0.456 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: txWordclkl12_1 To Clock: txWordclkl12_1 Setup : 0 Failing Endpoints, Worst Slack 4.965ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 1.511ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.965ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/CLR (recovery check against rising-edge clock txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_1 rise@8.200ns - txWordclkl12_1 rise@0.000ns) Data Path Delay: 2.531ns (logic 0.987ns (38.999%) route 1.544ns (61.001%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.514ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.434ns = ( 9.634 - 8.200 ) Source Clock Delay (SCD): 2.021ns Clock Pessimism Removal (CPR): 0.073ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 2.021 2.021 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.944 2.965 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 1.309 4.274 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/tx_reset_done[1] SLICE_X165Y342 LUT1 (Prop_lut1_I0_O) 0.043 4.317 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1/O net (fo=2, routed) 0.235 4.552 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1_n_0 SLICE_X164Y342 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 8.200 8.200 r BUFGCTRL_X0Y17 BUFG 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.434 9.634 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out SLICE_X164Y342 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/C clock pessimism 0.073 9.707 clock uncertainty -0.035 9.672 SLICE_X164Y342 FDCE (Recov_fdce_C_CLR) -0.154 9.518 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1] ------------------------------------------------------------------- required time 9.518 arrival time -4.552 ------------------------------------------------------------------- slack 4.965 Slack (MET) : 4.965ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/CLR (recovery check against rising-edge clock txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_1 rise@8.200ns - txWordclkl12_1 rise@0.000ns) Data Path Delay: 2.531ns (logic 0.987ns (38.999%) route 1.544ns (61.001%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.514ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.434ns = ( 9.634 - 8.200 ) Source Clock Delay (SCD): 2.021ns Clock Pessimism Removal (CPR): 0.073ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 2.021 2.021 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.944 2.965 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 1.309 4.274 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/tx_reset_done[1] SLICE_X165Y342 LUT1 (Prop_lut1_I0_O) 0.043 4.317 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1/O net (fo=2, routed) 0.235 4.552 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1_n_0 SLICE_X164Y342 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 8.200 8.200 r BUFGCTRL_X0Y17 BUFG 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.434 9.634 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out SLICE_X164Y342 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/C clock pessimism 0.073 9.707 clock uncertainty -0.035 9.672 SLICE_X164Y342 FDCE (Recov_fdce_C_CLR) -0.154 9.518 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1] ------------------------------------------------------------------- required time 9.518 arrival time -4.552 ------------------------------------------------------------------- slack 4.965 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.511ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/CLR (removal check against rising-edge clock txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_1 rise@0.000ns - txWordclkl12_1 rise@0.000ns) Data Path Delay: 1.376ns (logic 0.557ns (40.484%) route 0.819ns (59.516%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.997ns Source Clock Delay (SCD): 1.034ns Clock Pessimism Removal (CPR): 0.048ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.034 1.034 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.529 1.563 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 0.718 2.281 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/tx_reset_done[1] SLICE_X165Y342 LUT1 (Prop_lut1_I0_O) 0.028 2.309 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1/O net (fo=2, routed) 0.101 2.410 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1_n_0 SLICE_X164Y342 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.997 0.997 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out SLICE_X164Y342 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/C clock pessimism -0.048 0.949 SLICE_X164Y342 FDCE (Remov_fdce_C_CLR) -0.050 0.899 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1] ------------------------------------------------------------------- required time -0.899 arrival time 2.410 ------------------------------------------------------------------- slack 1.511 Slack (MET) : 1.511ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/CLR (removal check against rising-edge clock txWordclkl12_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_1 rise@0.000ns - txWordclkl12_1 rise@0.000ns) Data Path Delay: 1.376ns (logic 0.557ns (40.484%) route 0.819ns (59.516%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.085ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.997ns Source Clock Delay (SCD): 1.034ns Clock Pessimism Removal (CPR): 0.048ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.034 1.034 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y28 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.529 1.563 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 0.718 2.281 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/tx_reset_done[1] SLICE_X165Y342 LUT1 (Prop_lut1_I0_O) 0.028 2.309 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1/O net (fo=2, routed) 0.101 2.410 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1_n_0 SLICE_X164Y342 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl12_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y17 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.997 0.997 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out SLICE_X164Y342 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/C clock pessimism -0.048 0.949 SLICE_X164Y342 FDCE (Remov_fdce_C_CLR) -0.050 0.899 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1] ------------------------------------------------------------------- required time -0.899 arrival time 2.410 ------------------------------------------------------------------- slack 1.511 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: txWordclkl12_2 To Clock: txWordclkl12_2 Setup : 0 Failing Endpoints, Worst Slack 5.374ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 1.470ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.374ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/CLR (recovery check against rising-edge clock txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_2 rise@8.200ns - txWordclkl12_2 rise@0.000ns) Data Path Delay: 2.347ns (logic 0.987ns (42.054%) route 1.360ns (57.946%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.607ns = ( 9.807 - 8.200 ) Source Clock Delay (SCD): 2.021ns Clock Pessimism Removal (CPR): 0.183ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y18 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 2.021 2.021 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.944 2.965 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 1.041 4.007 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/tx_reset_done[2] SLICE_X184Y369 LUT1 (Prop_lut1_I0_O) 0.043 4.050 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1/O net (fo=2, routed) 0.319 4.368 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1_n_0 SLICE_X184Y369 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 8.200 8.200 r BUFGCTRL_X0Y18 BUFG 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.607 9.807 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 SLICE_X184Y369 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/C clock pessimism 0.183 9.990 clock uncertainty -0.035 9.955 SLICE_X184Y369 FDCE (Recov_fdce_C_CLR) -0.212 9.743 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2] ------------------------------------------------------------------- required time 9.743 arrival time -4.368 ------------------------------------------------------------------- slack 5.374 Slack (MET) : 5.374ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/CLR (recovery check against rising-edge clock txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_2 rise@8.200ns - txWordclkl12_2 rise@0.000ns) Data Path Delay: 2.347ns (logic 0.987ns (42.054%) route 1.360ns (57.946%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.231ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.607ns = ( 9.807 - 8.200 ) Source Clock Delay (SCD): 2.021ns Clock Pessimism Removal (CPR): 0.183ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y18 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 2.021 2.021 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.944 2.965 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 1.041 4.007 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/tx_reset_done[2] SLICE_X184Y369 LUT1 (Prop_lut1_I0_O) 0.043 4.050 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1/O net (fo=2, routed) 0.319 4.368 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1_n_0 SLICE_X184Y369 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 8.200 8.200 r BUFGCTRL_X0Y18 BUFG 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.607 9.807 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 SLICE_X184Y369 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/C clock pessimism 0.183 9.990 clock uncertainty -0.035 9.955 SLICE_X184Y369 FDCE (Recov_fdce_C_CLR) -0.212 9.743 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2] ------------------------------------------------------------------- required time 9.743 arrival time -4.368 ------------------------------------------------------------------- slack 5.374 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.470ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/CLR (removal check against rising-edge clock txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_2 rise@0.000ns - txWordclkl12_2 rise@0.000ns) Data Path Delay: 1.255ns (logic 0.557ns (44.382%) route 0.698ns (55.618%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.146ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.121ns Source Clock Delay (SCD): 1.034ns Clock Pessimism Removal (CPR): 0.233ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y18 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.034 1.034 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.529 1.563 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 0.553 2.117 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/tx_reset_done[2] SLICE_X184Y369 LUT1 (Prop_lut1_I0_O) 0.028 2.145 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1/O net (fo=2, routed) 0.145 2.289 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1_n_0 SLICE_X184Y369 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y18 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.121 1.121 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 SLICE_X184Y369 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/C clock pessimism -0.233 0.888 SLICE_X184Y369 FDCE (Remov_fdce_C_CLR) -0.069 0.819 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2] ------------------------------------------------------------------- required time -0.819 arrival time 2.289 ------------------------------------------------------------------- slack 1.470 Slack (MET) : 1.470ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/CLR (removal check against rising-edge clock txWordclkl12_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_2 rise@0.000ns - txWordclkl12_2 rise@0.000ns) Data Path Delay: 1.255ns (logic 0.557ns (44.382%) route 0.698ns (55.618%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.146ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.121ns Source Clock Delay (SCD): 1.034ns Clock Pessimism Removal (CPR): 0.233ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y18 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.034 1.034 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y31 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.529 1.563 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 0.553 2.117 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/tx_reset_done[2] SLICE_X184Y369 LUT1 (Prop_lut1_I0_O) 0.028 2.145 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1/O net (fo=2, routed) 0.145 2.289 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1_n_0 SLICE_X184Y369 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl12_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y18 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.121 1.121 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 SLICE_X184Y369 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/C clock pessimism -0.233 0.888 SLICE_X184Y369 FDCE (Remov_fdce_C_CLR) -0.069 0.819 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2] ------------------------------------------------------------------- required time -0.819 arrival time 2.289 ------------------------------------------------------------------- slack 1.470 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: txWordclkl12_3 To Clock: txWordclkl12_3 Setup : 0 Failing Endpoints, Worst Slack 5.075ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 1.670ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.075ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]/CLR (recovery check against rising-edge clock txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_3 rise@8.200ns - txWordclkl12_3 rise@0.000ns) Data Path Delay: 2.708ns (logic 0.987ns (36.449%) route 1.721ns (63.551%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.227ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.602ns = ( 9.802 - 8.200 ) Source Clock Delay (SCD): 2.012ns Clock Pessimism Removal (CPR): 0.183ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y19 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 2.012 2.012 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.944 2.956 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 1.404 4.361 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/tx_reset_done[3] SLICE_X166Y368 LUT1 (Prop_lut1_I0_O) 0.043 4.404 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1/O net (fo=2, routed) 0.317 4.720 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1_n_0 SLICE_X166Y368 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 8.200 8.200 r BUFGCTRL_X0Y19 BUFG 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.602 9.802 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1 SLICE_X166Y368 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]/C clock pessimism 0.183 9.985 clock uncertainty -0.035 9.950 SLICE_X166Y368 FDCE (Recov_fdce_C_CLR) -0.154 9.796 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3] ------------------------------------------------------------------- required time 9.796 arrival time -4.720 ------------------------------------------------------------------- slack 5.075 Slack (MET) : 5.075ns (required time - arrival time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]/CLR (recovery check against rising-edge clock txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_3 rise@8.200ns - txWordclkl12_3 rise@0.000ns) Data Path Delay: 2.708ns (logic 0.987ns (36.449%) route 1.721ns (63.551%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.227ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.602ns = ( 9.802 - 8.200 ) Source Clock Delay (SCD): 2.012ns Clock Pessimism Removal (CPR): 0.183ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y19 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 2.012 2.012 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.944 2.956 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 1.404 4.361 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/tx_reset_done[3] SLICE_X166Y368 LUT1 (Prop_lut1_I0_O) 0.043 4.404 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1/O net (fo=2, routed) 0.317 4.720 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1_n_0 SLICE_X166Y368 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 8.200 8.200 r BUFGCTRL_X0Y19 BUFG 0.000 8.200 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.602 9.802 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1 SLICE_X166Y368 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]/C clock pessimism 0.183 9.985 clock uncertainty -0.035 9.950 SLICE_X166Y368 FDCE (Recov_fdce_C_CLR) -0.154 9.796 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3] ------------------------------------------------------------------- required time 9.796 arrival time -4.720 ------------------------------------------------------------------- slack 5.075 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.670ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]/CLR (removal check against rising-edge clock txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_3 rise@0.000ns - txWordclkl12_3 rise@0.000ns) Data Path Delay: 1.474ns (logic 0.557ns (37.792%) route 0.917ns (62.208%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.146ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.116ns Source Clock Delay (SCD): 1.029ns Clock Pessimism Removal (CPR): 0.233ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y19 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.029 1.029 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.529 1.558 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 0.774 2.333 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/tx_reset_done[3] SLICE_X166Y368 LUT1 (Prop_lut1_I0_O) 0.028 2.361 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1/O net (fo=2, routed) 0.143 2.503 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1_n_0 SLICE_X166Y368 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y19 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.116 1.116 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1 SLICE_X166Y368 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]/C clock pessimism -0.233 0.883 SLICE_X166Y368 FDCE (Remov_fdce_C_CLR) -0.050 0.833 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3] ------------------------------------------------------------------- required time -0.833 arrival time 2.503 ------------------------------------------------------------------- slack 1.670 Slack (MET) : 1.670ns (arrival time - required time) Source: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]/CLR (removal check against rising-edge clock txWordclkl12_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_3 rise@0.000ns - txWordclkl12_3 rise@0.000ns) Data Path Delay: 1.474ns (logic 0.557ns (37.792%) route 0.917ns (62.208%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.146ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.116ns Source Clock Delay (SCD): 1.029ns Clock Pessimism Removal (CPR): 0.233ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y19 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.029 1.029 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y30 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.529 1.558 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 0.774 2.333 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/tx_reset_done[3] SLICE_X166Y368 LUT1 (Prop_lut1_I0_O) 0.028 2.361 f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1/O net (fo=2, routed) 0.143 2.503 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1_n_0 SLICE_X166Y368 FDCE f ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl12_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y19 BUFG 0.000 0.000 r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.116 1.116 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1 SLICE_X166Y368 FDCE r ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]/C clock pessimism -0.233 0.883 SLICE_X166Y368 FDCE (Remov_fdce_C_CLR) -0.050 0.833 ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3] ------------------------------------------------------------------- required time -0.833 arrival time 2.503 ------------------------------------------------------------------- slack 1.670 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: txWordclkl12_4 To Clock: txWordclkl12_4 Setup : 0 Failing Endpoints, Worst Slack 5.472ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 1.439ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.472ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/CLR (recovery check against rising-edge clock txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_4 rise@8.200ns - txWordclkl12_4 rise@0.000ns) Data Path Delay: 2.317ns (logic 0.987ns (42.604%) route 1.330ns (57.396%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.222ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.477ns = ( 9.677 - 8.200 ) Source Clock Delay (SCD): 1.852ns Clock Pessimism Removal (CPR): 0.153ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 1.852 1.852 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.944 2.796 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 0.942 3.738 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/tx_reset_done[1] SLICE_X170Y314 LUT1 (Prop_lut1_I0_O) 0.043 3.781 f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__0/O net (fo=2, routed) 0.388 4.169 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__0_n_0 SLICE_X170Y314 FDCE f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 8.200 8.200 r BUFGCTRL_X0Y16 BUFG 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 1.477 9.677 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out SLICE_X170Y314 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/C clock pessimism 0.153 9.830 clock uncertainty -0.035 9.795 SLICE_X170Y314 FDCE (Recov_fdce_C_CLR) -0.154 9.641 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1] ------------------------------------------------------------------- required time 9.641 arrival time -4.169 ------------------------------------------------------------------- slack 5.472 Slack (MET) : 5.472ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/CLR (recovery check against rising-edge clock txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_4 rise@8.200ns - txWordclkl12_4 rise@0.000ns) Data Path Delay: 2.317ns (logic 0.987ns (42.604%) route 1.330ns (57.396%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.222ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.477ns = ( 9.677 - 8.200 ) Source Clock Delay (SCD): 1.852ns Clock Pessimism Removal (CPR): 0.153ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 1.852 1.852 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.944 2.796 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 0.942 3.738 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/tx_reset_done[1] SLICE_X170Y314 LUT1 (Prop_lut1_I0_O) 0.043 3.781 f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__0/O net (fo=2, routed) 0.388 4.169 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__0_n_0 SLICE_X170Y314 FDCE f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 8.200 8.200 r BUFGCTRL_X0Y16 BUFG 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 1.477 9.677 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out SLICE_X170Y314 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/C clock pessimism 0.153 9.830 clock uncertainty -0.035 9.795 SLICE_X170Y314 FDCE (Recov_fdce_C_CLR) -0.154 9.641 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1] ------------------------------------------------------------------- required time 9.641 arrival time -4.169 ------------------------------------------------------------------- slack 5.472 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.439ns (arrival time - required time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/CLR (removal check against rising-edge clock txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_4 rise@0.000ns - txWordclkl12_4 rise@0.000ns) Data Path Delay: 1.248ns (logic 0.557ns (44.643%) route 0.691ns (55.357%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.141ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.021ns Source Clock Delay (SCD): 0.949ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 0.949 0.949 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.529 1.478 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 0.508 1.986 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/tx_reset_done[1] SLICE_X170Y314 LUT1 (Prop_lut1_I0_O) 0.028 2.014 f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__0/O net (fo=2, routed) 0.183 2.197 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__0_n_0 SLICE_X170Y314 FDCE f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 1.021 1.021 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out SLICE_X170Y314 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/C clock pessimism -0.213 0.808 SLICE_X170Y314 FDCE (Remov_fdce_C_CLR) -0.050 0.758 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1] ------------------------------------------------------------------- required time -0.758 arrival time 2.197 ------------------------------------------------------------------- slack 1.439 Slack (MET) : 1.439ns (arrival time - required time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/CLR (removal check against rising-edge clock txWordclkl12_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_4 rise@0.000ns - txWordclkl12_4 rise@0.000ns) Data Path Delay: 1.248ns (logic 0.557ns (44.643%) route 0.691ns (55.357%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.141ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.021ns Source Clock Delay (SCD): 0.949ns Clock Pessimism Removal (CPR): 0.213ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 0.949 0.949 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y25 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.529 1.478 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 0.508 1.986 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/tx_reset_done[1] SLICE_X170Y314 LUT1 (Prop_lut1_I0_O) 0.028 2.014 f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__0/O net (fo=2, routed) 0.183 2.197 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__0_n_0 SLICE_X170Y314 FDCE f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl12_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y16 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=225, routed) 1.021 1.021 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out SLICE_X170Y314 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/C clock pessimism -0.213 0.808 SLICE_X170Y314 FDCE (Remov_fdce_C_CLR) -0.050 0.758 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1] ------------------------------------------------------------------- required time -0.758 arrival time 2.197 ------------------------------------------------------------------- slack 1.439 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: txWordclkl12_5 To Clock: txWordclkl12_5 Setup : 0 Failing Endpoints, Worst Slack 5.871ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 1.219ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.871ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/CLR (recovery check against rising-edge clock txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_5 rise@8.200ns - txWordclkl12_5 rise@0.000ns) Data Path Delay: 1.885ns (logic 0.987ns (52.365%) route 0.898ns (47.635%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.196ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.486ns = ( 9.686 - 8.200 ) Source Clock Delay (SCD): 1.861ns Clock Pessimism Removal (CPR): 0.179ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 0.000 0.000 r BUFGCTRL_X0Y20 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.861 1.861 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.944 2.805 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 0.510 3.316 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/tx_reset_done[2] SLICE_X187Y304 LUT1 (Prop_lut1_I0_O) 0.043 3.359 f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__0/O net (fo=2, routed) 0.388 3.746 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__0_n_0 SLICE_X188Y304 FDCE f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 8.200 8.200 r BUFGCTRL_X0Y20 BUFG 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.486 9.686 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 SLICE_X188Y304 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/C clock pessimism 0.179 9.865 clock uncertainty -0.035 9.830 SLICE_X188Y304 FDCE (Recov_fdce_C_CLR) -0.212 9.618 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2] ------------------------------------------------------------------- required time 9.618 arrival time -3.746 ------------------------------------------------------------------- slack 5.871 Slack (MET) : 5.871ns (required time - arrival time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/CLR (recovery check against rising-edge clock txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_5 rise@8.200ns - txWordclkl12_5 rise@0.000ns) Data Path Delay: 1.885ns (logic 0.987ns (52.365%) route 0.898ns (47.635%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.196ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.486ns = ( 9.686 - 8.200 ) Source Clock Delay (SCD): 1.861ns Clock Pessimism Removal (CPR): 0.179ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 0.000 0.000 r BUFGCTRL_X0Y20 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.861 1.861 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.944 2.805 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 0.510 3.316 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/tx_reset_done[2] SLICE_X187Y304 LUT1 (Prop_lut1_I0_O) 0.043 3.359 f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__0/O net (fo=2, routed) 0.388 3.746 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__0_n_0 SLICE_X188Y304 FDCE f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 8.200 8.200 r BUFGCTRL_X0Y20 BUFG 0.000 8.200 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.486 9.686 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 SLICE_X188Y304 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/C clock pessimism 0.179 9.865 clock uncertainty -0.035 9.830 SLICE_X188Y304 FDCE (Recov_fdce_C_CLR) -0.212 9.618 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2] ------------------------------------------------------------------- required time 9.618 arrival time -3.746 ------------------------------------------------------------------- slack 5.871 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.219ns (arrival time - required time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/CLR (removal check against rising-edge clock txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_5 rise@0.000ns - txWordclkl12_5 rise@0.000ns) Data Path Delay: 0.993ns (logic 0.557ns (56.101%) route 0.436ns (43.899%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.157ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.031ns Source Clock Delay (SCD): 0.954ns Clock Pessimism Removal (CPR): 0.234ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 0.000 0.000 r BUFGCTRL_X0Y20 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.954 0.954 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.529 1.483 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 0.254 1.738 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/tx_reset_done[2] SLICE_X187Y304 LUT1 (Prop_lut1_I0_O) 0.028 1.766 f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__0/O net (fo=2, routed) 0.182 1.947 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__0_n_0 SLICE_X188Y304 FDCE f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 0.000 0.000 r BUFGCTRL_X0Y20 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.031 1.031 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 SLICE_X188Y304 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/C clock pessimism -0.234 0.797 SLICE_X188Y304 FDCE (Remov_fdce_C_CLR) -0.069 0.728 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2] ------------------------------------------------------------------- required time -0.728 arrival time 1.947 ------------------------------------------------------------------- slack 1.219 Slack (MET) : 1.219ns (arrival time - required time) Source: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/CLR (removal check against rising-edge clock txWordclkl12_5 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_5 rise@0.000ns - txWordclkl12_5 rise@0.000ns) Data Path Delay: 0.993ns (logic 0.557ns (56.101%) route 0.436ns (43.899%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.157ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 1.031ns Source Clock Delay (SCD): 0.954ns Clock Pessimism Removal (CPR): 0.234ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 0.000 0.000 r BUFGCTRL_X0Y20 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.954 0.954 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y24 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.529 1.483 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 0.254 1.738 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/tx_reset_done[2] SLICE_X187Y304 LUT1 (Prop_lut1_I0_O) 0.028 1.766 f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__0/O net (fo=2, routed) 0.182 1.947 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__0_n_0 SLICE_X188Y304 FDCE f ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl12_5 rise edge) 0.000 0.000 r BUFGCTRL_X0Y20 BUFG 0.000 0.000 r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.031 1.031 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 SLICE_X188Y304 FDCE r ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/C clock pessimism -0.234 0.797 SLICE_X188Y304 FDCE (Remov_fdce_C_CLR) -0.069 0.728 ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2] ------------------------------------------------------------------- required time -0.728 arrival time 1.947 ------------------------------------------------------------------- slack 1.219 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: txWordclkl12_6 To Clock: txWordclkl12_6 Setup : 0 Failing Endpoints, Worst Slack 4.987ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 1.700ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 4.987ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/CLR (recovery check against rising-edge clock txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_6 rise@8.200ns - txWordclkl12_6 rise@0.000ns) Data Path Delay: 2.733ns (logic 0.987ns (36.110%) route 1.746ns (63.890%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.232ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.337ns = ( 9.537 - 8.200 ) Source Clock Delay (SCD): 1.692ns Clock Pessimism Removal (CPR): 0.123ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 0.000 0.000 r BUFGCTRL_X0Y21 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.692 1.692 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.944 2.636 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 1.511 4.148 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/tx_reset_done[1] SLICE_X167Y273 LUT1 (Prop_lut1_I0_O) 0.043 4.191 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__1/O net (fo=2, routed) 0.235 4.426 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__1_n_0 SLICE_X167Y273 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 8.200 8.200 r BUFGCTRL_X0Y21 BUFG 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.337 9.537 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out SLICE_X167Y273 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/C clock pessimism 0.123 9.660 clock uncertainty -0.035 9.625 SLICE_X167Y273 FDCE (Recov_fdce_C_CLR) -0.212 9.413 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1] ------------------------------------------------------------------- required time 9.413 arrival time -4.426 ------------------------------------------------------------------- slack 4.987 Slack (MET) : 4.987ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/CLR (recovery check against rising-edge clock txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_6 rise@8.200ns - txWordclkl12_6 rise@0.000ns) Data Path Delay: 2.733ns (logic 0.987ns (36.110%) route 1.746ns (63.890%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.232ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.337ns = ( 9.537 - 8.200 ) Source Clock Delay (SCD): 1.692ns Clock Pessimism Removal (CPR): 0.123ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 0.000 0.000 r BUFGCTRL_X0Y21 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.692 1.692 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.944 2.636 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 1.511 4.148 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/tx_reset_done[1] SLICE_X167Y273 LUT1 (Prop_lut1_I0_O) 0.043 4.191 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__1/O net (fo=2, routed) 0.235 4.426 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__1_n_0 SLICE_X167Y273 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 8.200 8.200 r BUFGCTRL_X0Y21 BUFG 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.337 9.537 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out SLICE_X167Y273 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/C clock pessimism 0.123 9.660 clock uncertainty -0.035 9.625 SLICE_X167Y273 FDCE (Recov_fdce_C_CLR) -0.212 9.413 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1] ------------------------------------------------------------------- required time 9.413 arrival time -4.426 ------------------------------------------------------------------- slack 4.987 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.700ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/CLR (removal check against rising-edge clock txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_6 rise@0.000ns - txWordclkl12_6 rise@0.000ns) Data Path Delay: 1.478ns (logic 0.557ns (37.678%) route 0.921ns (62.322%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.152ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.910ns Source Clock Delay (SCD): 0.869ns Clock Pessimism Removal (CPR): 0.193ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 0.000 0.000 r BUFGCTRL_X0Y21 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.869 0.869 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.529 1.398 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 0.820 2.219 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/tx_reset_done[1] SLICE_X167Y273 LUT1 (Prop_lut1_I0_O) 0.028 2.247 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__1/O net (fo=2, routed) 0.101 2.348 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__1_n_0 SLICE_X167Y273 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 0.000 0.000 r BUFGCTRL_X0Y21 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.910 0.910 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out SLICE_X167Y273 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/C clock pessimism -0.193 0.717 SLICE_X167Y273 FDCE (Remov_fdce_C_CLR) -0.069 0.648 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1] ------------------------------------------------------------------- required time -0.648 arrival time 2.348 ------------------------------------------------------------------- slack 1.700 Slack (MET) : 1.700ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/CLR (removal check against rising-edge clock txWordclkl12_6 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_6 rise@0.000ns - txWordclkl12_6 rise@0.000ns) Data Path Delay: 1.478ns (logic 0.557ns (37.678%) route 0.921ns (62.322%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.152ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.910ns Source Clock Delay (SCD): 0.869ns Clock Pessimism Removal (CPR): 0.193ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 0.000 0.000 r BUFGCTRL_X0Y21 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.869 0.869 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y21 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.529 1.398 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 0.820 2.219 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/tx_reset_done[1] SLICE_X167Y273 LUT1 (Prop_lut1_I0_O) 0.028 2.247 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__1/O net (fo=2, routed) 0.101 2.348 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__1_n_0 SLICE_X167Y273 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl12_6 rise edge) 0.000 0.000 r BUFGCTRL_X0Y21 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.910 0.910 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out SLICE_X167Y273 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/C clock pessimism -0.193 0.717 SLICE_X167Y273 FDCE (Remov_fdce_C_CLR) -0.069 0.648 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1] ------------------------------------------------------------------- required time -0.648 arrival time 2.348 ------------------------------------------------------------------- slack 1.700 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: txWordclkl12_7 To Clock: txWordclkl12_7 Setup : 0 Failing Endpoints, Worst Slack 5.485ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 1.193ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.485ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/CLR (recovery check against rising-edge clock txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_7 rise@8.200ns - txWordclkl12_7 rise@0.000ns) Data Path Delay: 2.005ns (logic 0.987ns (49.222%) route 1.018ns (50.778%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.462ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.226ns = ( 9.426 - 8.200 ) Source Clock Delay (SCD): 1.701ns Clock Pessimism Removal (CPR): 0.013ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 0.000 0.000 r BUFGCTRL_X0Y22 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.701 1.701 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.944 2.645 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 0.617 3.263 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/tx_reset_done[2] SLICE_X188Y246 LUT1 (Prop_lut1_I0_O) 0.043 3.306 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__1/O net (fo=2, routed) 0.401 3.707 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__1_n_0 SLICE_X188Y246 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 8.200 8.200 r BUFGCTRL_X0Y22 BUFG 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.226 9.426 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 SLICE_X188Y246 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/C clock pessimism 0.013 9.439 clock uncertainty -0.035 9.404 SLICE_X188Y246 FDCE (Recov_fdce_C_CLR) -0.212 9.192 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2] ------------------------------------------------------------------- required time 9.192 arrival time -3.707 ------------------------------------------------------------------- slack 5.485 Slack (MET) : 5.485ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/CLR (recovery check against rising-edge clock txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_7 rise@8.200ns - txWordclkl12_7 rise@0.000ns) Data Path Delay: 2.005ns (logic 0.987ns (49.222%) route 1.018ns (50.778%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.462ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.226ns = ( 9.426 - 8.200 ) Source Clock Delay (SCD): 1.701ns Clock Pessimism Removal (CPR): 0.013ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 0.000 0.000 r BUFGCTRL_X0Y22 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.701 1.701 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.944 2.645 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 0.617 3.263 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/tx_reset_done[2] SLICE_X188Y246 LUT1 (Prop_lut1_I0_O) 0.043 3.306 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__1/O net (fo=2, routed) 0.401 3.707 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__1_n_0 SLICE_X188Y246 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 8.200 8.200 r BUFGCTRL_X0Y22 BUFG 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.226 9.426 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 SLICE_X188Y246 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/C clock pessimism 0.013 9.439 clock uncertainty -0.035 9.404 SLICE_X188Y246 FDCE (Recov_fdce_C_CLR) -0.212 9.192 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2] ------------------------------------------------------------------- required time 9.192 arrival time -3.707 ------------------------------------------------------------------- slack 5.485 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.193ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/CLR (removal check against rising-edge clock txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_7 rise@0.000ns - txWordclkl12_7 rise@0.000ns) Data Path Delay: 1.072ns (logic 0.557ns (51.949%) route 0.515ns (48.051%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.051ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.831ns Source Clock Delay (SCD): 0.874ns Clock Pessimism Removal (CPR): 0.008ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 0.000 0.000 r BUFGCTRL_X0Y22 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.874 0.874 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.529 1.403 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 0.321 1.725 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/tx_reset_done[2] SLICE_X188Y246 LUT1 (Prop_lut1_I0_O) 0.028 1.753 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__1/O net (fo=2, routed) 0.194 1.947 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__1_n_0 SLICE_X188Y246 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 0.000 0.000 r BUFGCTRL_X0Y22 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.831 0.831 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 SLICE_X188Y246 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/C clock pessimism -0.008 0.823 SLICE_X188Y246 FDCE (Remov_fdce_C_CLR) -0.069 0.754 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2] ------------------------------------------------------------------- required time -0.754 arrival time 1.947 ------------------------------------------------------------------- slack 1.193 Slack (MET) : 1.193ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/CLR (removal check against rising-edge clock txWordclkl12_7 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_7 rise@0.000ns - txWordclkl12_7 rise@0.000ns) Data Path Delay: 1.072ns (logic 0.557ns (51.949%) route 0.515ns (48.051%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.051ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.831ns Source Clock Delay (SCD): 0.874ns Clock Pessimism Removal (CPR): 0.008ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 0.000 0.000 r BUFGCTRL_X0Y22 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.874 0.874 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y20 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.529 1.403 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 0.321 1.725 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/tx_reset_done[2] SLICE_X188Y246 LUT1 (Prop_lut1_I0_O) 0.028 1.753 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__1/O net (fo=2, routed) 0.194 1.947 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__1_n_0 SLICE_X188Y246 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl12_7 rise edge) 0.000 0.000 r BUFGCTRL_X0Y22 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.831 0.831 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 SLICE_X188Y246 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/C clock pessimism -0.008 0.823 SLICE_X188Y246 FDCE (Remov_fdce_C_CLR) -0.069 0.754 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2] ------------------------------------------------------------------- required time -0.754 arrival time 1.947 ------------------------------------------------------------------- slack 1.193 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: txWordclkl12_8 To Clock: txWordclkl12_8 Setup : 0 Failing Endpoints, Worst Slack 5.331ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 1.471ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.331ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]/CLR (recovery check against rising-edge clock txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_8 rise@8.200ns - txWordclkl12_8 rise@0.000ns) Data Path Delay: 2.392ns (logic 0.987ns (41.268%) route 1.405ns (58.732%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.230ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.348ns = ( 9.548 - 8.200 ) Source Clock Delay (SCD): 1.701ns Clock Pessimism Removal (CPR): 0.123ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.701 1.701 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.944 2.645 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 1.086 3.732 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/tx_reset_done[3] SLICE_X184Y282 LUT1 (Prop_lut1_I0_O) 0.043 3.775 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1__0/O net (fo=2, routed) 0.319 4.093 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1__0_n_0 SLICE_X185Y282 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 8.200 8.200 r BUFGCTRL_X0Y23 BUFG 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.348 9.548 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1 SLICE_X185Y282 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]/C clock pessimism 0.123 9.671 clock uncertainty -0.035 9.636 SLICE_X185Y282 FDCE (Recov_fdce_C_CLR) -0.212 9.424 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3] ------------------------------------------------------------------- required time 9.424 arrival time -4.093 ------------------------------------------------------------------- slack 5.331 Slack (MET) : 5.331ns (required time - arrival time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]/CLR (recovery check against rising-edge clock txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl12_8 rise@8.200ns - txWordclkl12_8 rise@0.000ns) Data Path Delay: 2.392ns (logic 0.987ns (41.268%) route 1.405ns (58.732%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.230ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.348ns = ( 9.548 - 8.200 ) Source Clock Delay (SCD): 1.701ns Clock Pessimism Removal (CPR): 0.123ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.701 1.701 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.944 2.645 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 1.086 3.732 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/tx_reset_done[3] SLICE_X184Y282 LUT1 (Prop_lut1_I0_O) 0.043 3.775 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1__0/O net (fo=2, routed) 0.319 4.093 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1__0_n_0 SLICE_X185Y282 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 8.200 8.200 r BUFGCTRL_X0Y23 BUFG 0.000 8.200 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.348 9.548 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1 SLICE_X185Y282 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]/C clock pessimism 0.123 9.671 clock uncertainty -0.035 9.636 SLICE_X185Y282 FDCE (Recov_fdce_C_CLR) -0.212 9.424 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3] ------------------------------------------------------------------- required time 9.424 arrival time -4.093 ------------------------------------------------------------------- slack 5.331 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.471ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]/CLR (removal check against rising-edge clock txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_8 rise@0.000ns - txWordclkl12_8 rise@0.000ns) Data Path Delay: 1.258ns (logic 0.557ns (44.288%) route 0.701ns (55.712%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.144ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.923ns Source Clock Delay (SCD): 0.874ns Clock Pessimism Removal (CPR): 0.193ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.874 0.874 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.529 1.403 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 0.558 1.962 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/tx_reset_done[3] SLICE_X184Y282 LUT1 (Prop_lut1_I0_O) 0.028 1.990 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1__0/O net (fo=2, routed) 0.143 2.132 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1__0_n_0 SLICE_X185Y282 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.923 0.923 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1 SLICE_X185Y282 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]/C clock pessimism -0.193 0.730 SLICE_X185Y282 FDCE (Remov_fdce_C_CLR) -0.069 0.661 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3] ------------------------------------------------------------------- required time -0.661 arrival time 2.132 ------------------------------------------------------------------- slack 1.471 Slack (MET) : 1.471ns (arrival time - required time) Source: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]/CLR (removal check against rising-edge clock txWordclkl12_8 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl12_8 rise@0.000ns - txWordclkl12_8 rise@0.000ns) Data Path Delay: 1.258ns (logic 0.557ns (44.288%) route 0.701ns (55.712%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.144ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.923ns Source Clock Delay (SCD): 0.874ns Clock Pessimism Removal (CPR): 0.193ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.874 0.874 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y23 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.529 1.403 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 0.558 1.962 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/tx_reset_done[3] SLICE_X184Y282 LUT1 (Prop_lut1_I0_O) 0.028 1.990 f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1__0/O net (fo=2, routed) 0.143 2.132 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1__0_n_0 SLICE_X185Y282 FDCE f ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl12_8 rise edge) 0.000 0.000 r BUFGCTRL_X0Y23 BUFG 0.000 0.000 r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.923 0.923 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1 SLICE_X185Y282 FDCE r ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]/C clock pessimism -0.193 0.730 SLICE_X185Y282 FDCE (Remov_fdce_C_CLR) -0.069 0.661 ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3] ------------------------------------------------------------------- required time -0.661 arrival time 2.132 ------------------------------------------------------------------- slack 1.471 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: txWordclkl8_1 To Clock: txWordclkl8_1 Setup : 0 Failing Endpoints, Worst Slack 5.734ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 1.270ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.734ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/CLR (recovery check against rising-edge clock txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_1 rise@8.200ns - txWordclkl8_1 rise@0.000ns) Data Path Delay: 1.962ns (logic 0.991ns (50.506%) route 0.971ns (49.494%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.223ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.583ns = ( 9.783 - 8.200 ) Source Clock Delay (SCD): 1.896ns Clock Pessimism Removal (CPR): 0.090ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y3 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.896 1.896 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y4 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y4 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.944 2.840 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 0.674 3.515 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/tx_reset_done[1] SLICE_X180Y54 LUT1 (Prop_lut1_I0_O) 0.047 3.562 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__2/O net (fo=2, routed) 0.297 3.859 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__2_n_0 SLICE_X178Y54 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 8.200 8.200 r BUFGCTRL_X0Y3 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.583 9.783 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out SLICE_X178Y54 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/C clock pessimism 0.090 9.873 clock uncertainty -0.035 9.838 SLICE_X178Y54 FDCE (Recov_fdce_C_CLR) -0.245 9.593 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1] ------------------------------------------------------------------- required time 9.593 arrival time -3.859 ------------------------------------------------------------------- slack 5.734 Slack (MET) : 5.734ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/CLR (recovery check against rising-edge clock txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_1 rise@8.200ns - txWordclkl8_1 rise@0.000ns) Data Path Delay: 1.962ns (logic 0.991ns (50.506%) route 0.971ns (49.494%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.223ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.583ns = ( 9.783 - 8.200 ) Source Clock Delay (SCD): 1.896ns Clock Pessimism Removal (CPR): 0.090ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y3 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.896 1.896 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y4 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y4 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.944 2.840 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 0.674 3.515 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/tx_reset_done[1] SLICE_X180Y54 LUT1 (Prop_lut1_I0_O) 0.047 3.562 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__2/O net (fo=2, routed) 0.297 3.859 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__2_n_0 SLICE_X178Y54 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 8.200 8.200 r BUFGCTRL_X0Y3 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 1.583 9.783 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out SLICE_X178Y54 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/C clock pessimism 0.090 9.873 clock uncertainty -0.035 9.838 SLICE_X178Y54 FDCE (Recov_fdce_C_CLR) -0.245 9.593 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1] ------------------------------------------------------------------- required time 9.593 arrival time -3.859 ------------------------------------------------------------------- slack 5.734 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.270ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/CLR (removal check against rising-edge clock txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_1 rise@0.000ns - txWordclkl8_1 rise@0.000ns) Data Path Delay: 1.041ns (logic 0.556ns (53.403%) route 0.485ns (46.597%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.137ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.985ns Source Clock Delay (SCD): 0.914ns Clock Pessimism Removal (CPR): 0.208ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y3 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.914 0.914 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y4 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y4 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.529 1.443 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 0.346 1.790 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/tx_reset_done[1] SLICE_X180Y54 LUT1 (Prop_lut1_I0_O) 0.027 1.817 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__2/O net (fo=2, routed) 0.139 1.956 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__2_n_0 SLICE_X178Y54 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y3 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.985 0.985 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out SLICE_X178Y54 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1]/C clock pessimism -0.208 0.777 SLICE_X178Y54 FDCE (Remov_fdce_C_CLR) -0.091 0.686 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r2_reg[1] ------------------------------------------------------------------- required time -0.686 arrival time 1.956 ------------------------------------------------------------------- slack 1.270 Slack (MET) : 1.270ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/CLR (removal check against rising-edge clock txWordclkl8_1 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_1 rise@0.000ns - txWordclkl8_1 rise@0.000ns) Data Path Delay: 1.041ns (logic 0.556ns (53.403%) route 0.485ns (46.597%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.137ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.985ns Source Clock Delay (SCD): 0.914ns Clock Pessimism Removal (CPR): 0.208ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y3 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.914 0.914 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y4 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y4 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.529 1.443 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 0.346 1.790 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/tx_reset_done[1] SLICE_X180Y54 LUT1 (Prop_lut1_I0_O) 0.027 1.817 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__2/O net (fo=2, routed) 0.139 1.956 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r[1]_i_1__2_n_0 SLICE_X178Y54 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl8_1 rise edge) 0.000 0.000 r BUFGCTRL_X0Y3 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O net (fo=221, routed) 0.985 0.985 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out SLICE_X178Y54 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1]/C clock pessimism -0.208 0.777 SLICE_X178Y54 FDCE (Remov_fdce_C_CLR) -0.091 0.686 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txResetDone_r_reg[1] ------------------------------------------------------------------- required time -0.686 arrival time 1.956 ------------------------------------------------------------------- slack 1.270 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: txWordclkl8_2 To Clock: txWordclkl8_2 Setup : 0 Failing Endpoints, Worst Slack 5.572ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 1.363ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.572ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/CLR (recovery check against rising-edge clock txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_2 rise@8.200ns - txWordclkl8_2 rise@0.000ns) Data Path Delay: 2.219ns (logic 0.987ns (44.472%) route 1.232ns (55.528%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.219ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.578ns = ( 9.778 - 8.200 ) Source Clock Delay (SCD): 1.887ns Clock Pessimism Removal (CPR): 0.090ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y4 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.887 1.887 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y5 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y5 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.944 2.831 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 0.922 3.754 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/tx_reset_done[2] SLICE_X179Y64 LUT1 (Prop_lut1_I0_O) 0.043 3.797 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__2/O net (fo=2, routed) 0.310 4.107 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__2_n_0 SLICE_X176Y64 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 8.200 8.200 r BUFGCTRL_X0Y4 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.578 9.778 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 SLICE_X176Y64 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/C clock pessimism 0.090 9.868 clock uncertainty -0.035 9.833 SLICE_X176Y64 FDCE (Recov_fdce_C_CLR) -0.154 9.679 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2] ------------------------------------------------------------------- required time 9.679 arrival time -4.107 ------------------------------------------------------------------- slack 5.572 Slack (MET) : 5.572ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/CLR (recovery check against rising-edge clock txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_2 rise@8.200ns - txWordclkl8_2 rise@0.000ns) Data Path Delay: 2.219ns (logic 0.987ns (44.472%) route 1.232ns (55.528%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.219ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.578ns = ( 9.778 - 8.200 ) Source Clock Delay (SCD): 1.887ns Clock Pessimism Removal (CPR): 0.090ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y4 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.887 1.887 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y5 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y5 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.944 2.831 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 0.922 3.754 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/tx_reset_done[2] SLICE_X179Y64 LUT1 (Prop_lut1_I0_O) 0.043 3.797 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__2/O net (fo=2, routed) 0.310 4.107 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__2_n_0 SLICE_X176Y64 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 8.200 8.200 r BUFGCTRL_X0Y4 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 1.578 9.778 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 SLICE_X176Y64 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/C clock pessimism 0.090 9.868 clock uncertainty -0.035 9.833 SLICE_X176Y64 FDCE (Recov_fdce_C_CLR) -0.154 9.679 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2] ------------------------------------------------------------------- required time 9.679 arrival time -4.107 ------------------------------------------------------------------- slack 5.572 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.363ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/CLR (removal check against rising-edge clock txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_2 rise@0.000ns - txWordclkl8_2 rise@0.000ns) Data Path Delay: 1.175ns (logic 0.557ns (47.390%) route 0.618ns (52.610%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.137ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.980ns Source Clock Delay (SCD): 0.909ns Clock Pessimism Removal (CPR): 0.208ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y4 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.909 0.909 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y5 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y5 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.529 1.438 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 0.474 1.913 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/tx_reset_done[2] SLICE_X179Y64 LUT1 (Prop_lut1_I0_O) 0.028 1.941 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__2/O net (fo=2, routed) 0.144 2.085 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__2_n_0 SLICE_X176Y64 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y4 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.980 0.980 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 SLICE_X176Y64 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2]/C clock pessimism -0.208 0.772 SLICE_X176Y64 FDCE (Remov_fdce_C_CLR) -0.050 0.722 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r2_reg[2] ------------------------------------------------------------------- required time -0.722 arrival time 2.085 ------------------------------------------------------------------- slack 1.363 Slack (MET) : 1.363ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/CLR (removal check against rising-edge clock txWordclkl8_2 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_2 rise@0.000ns - txWordclkl8_2 rise@0.000ns) Data Path Delay: 1.175ns (logic 0.557ns (47.390%) route 0.618ns (52.610%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.137ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.980ns Source Clock Delay (SCD): 0.909ns Clock Pessimism Removal (CPR): 0.208ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y4 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.909 0.909 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y5 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y5 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.529 1.438 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 0.474 1.913 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/tx_reset_done[2] SLICE_X179Y64 LUT1 (Prop_lut1_I0_O) 0.028 1.941 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__2/O net (fo=2, routed) 0.144 2.085 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r[2]_i_1__2_n_0 SLICE_X176Y64 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl8_2 rise edge) 0.000 0.000 r BUFGCTRL_X0Y4 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O net (fo=221, routed) 0.980 0.980 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 SLICE_X176Y64 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2]/C clock pessimism -0.208 0.772 SLICE_X176Y64 FDCE (Remov_fdce_C_CLR) -0.050 0.722 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txResetDone_r_reg[2] ------------------------------------------------------------------- required time -0.722 arrival time 2.085 ------------------------------------------------------------------- slack 1.363 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: txWordclkl8_3 To Clock: txWordclkl8_3 Setup : 0 Failing Endpoints, Worst Slack 5.706ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 1.287ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.706ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]/CLR (recovery check against rising-edge clock txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_3 rise@8.200ns - txWordclkl8_3 rise@0.000ns) Data Path Delay: 2.082ns (logic 0.987ns (47.408%) route 1.095ns (52.592%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.222ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.575ns = ( 9.775 - 8.200 ) Source Clock Delay (SCD): 1.887ns Clock Pessimism Removal (CPR): 0.090ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y5 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.887 1.887 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y6 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y6 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.944 2.831 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 0.766 3.598 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/tx_reset_done[3] SLICE_X176Y80 LUT1 (Prop_lut1_I0_O) 0.043 3.641 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1__1/O net (fo=2, routed) 0.329 3.969 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1__1_n_0 SLICE_X176Y82 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 8.200 8.200 r BUFGCTRL_X0Y5 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.575 9.775 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1 SLICE_X176Y82 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]/C clock pessimism 0.090 9.865 clock uncertainty -0.035 9.830 SLICE_X176Y82 FDCE (Recov_fdce_C_CLR) -0.154 9.676 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3] ------------------------------------------------------------------- required time 9.676 arrival time -3.969 ------------------------------------------------------------------- slack 5.706 Slack (MET) : 5.706ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]/CLR (recovery check against rising-edge clock txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_3 rise@8.200ns - txWordclkl8_3 rise@0.000ns) Data Path Delay: 2.082ns (logic 0.987ns (47.408%) route 1.095ns (52.592%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.222ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.575ns = ( 9.775 - 8.200 ) Source Clock Delay (SCD): 1.887ns Clock Pessimism Removal (CPR): 0.090ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y5 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.887 1.887 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y6 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y6 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.944 2.831 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 0.766 3.598 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/tx_reset_done[3] SLICE_X176Y80 LUT1 (Prop_lut1_I0_O) 0.043 3.641 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1__1/O net (fo=2, routed) 0.329 3.969 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1__1_n_0 SLICE_X176Y82 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 8.200 8.200 r BUFGCTRL_X0Y5 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 1.575 9.775 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1 SLICE_X176Y82 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]/C clock pessimism 0.090 9.865 clock uncertainty -0.035 9.830 SLICE_X176Y82 FDCE (Recov_fdce_C_CLR) -0.154 9.676 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3] ------------------------------------------------------------------- required time 9.676 arrival time -3.969 ------------------------------------------------------------------- slack 5.706 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.287ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]/CLR (removal check against rising-edge clock txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_3 rise@0.000ns - txWordclkl8_3 rise@0.000ns) Data Path Delay: 1.097ns (logic 0.557ns (50.777%) route 0.540ns (49.223%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.140ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.977ns Source Clock Delay (SCD): 0.909ns Clock Pessimism Removal (CPR): 0.208ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y5 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.909 0.909 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y6 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y6 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.529 1.438 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 0.391 1.830 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/tx_reset_done[3] SLICE_X176Y80 LUT1 (Prop_lut1_I0_O) 0.028 1.858 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1__1/O net (fo=2, routed) 0.149 2.006 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1__1_n_0 SLICE_X176Y82 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y5 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.977 0.977 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1 SLICE_X176Y82 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3]/C clock pessimism -0.208 0.769 SLICE_X176Y82 FDCE (Remov_fdce_C_CLR) -0.050 0.719 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r2_reg[3] ------------------------------------------------------------------- required time -0.719 arrival time 2.006 ------------------------------------------------------------------- slack 1.287 Slack (MET) : 1.287ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]/CLR (removal check against rising-edge clock txWordclkl8_3 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_3 rise@0.000ns - txWordclkl8_3 rise@0.000ns) Data Path Delay: 1.097ns (logic 0.557ns (50.777%) route 0.540ns (49.223%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.140ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.977ns Source Clock Delay (SCD): 0.909ns Clock Pessimism Removal (CPR): 0.208ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y5 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.909 0.909 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y6 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y6 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.529 1.438 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 0.391 1.830 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/tx_reset_done[3] SLICE_X176Y80 LUT1 (Prop_lut1_I0_O) 0.028 1.858 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1__1/O net (fo=2, routed) 0.149 2.006 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r[3]_i_1__1_n_0 SLICE_X176Y82 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl8_3 rise edge) 0.000 0.000 r BUFGCTRL_X0Y5 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O net (fo=221, routed) 0.977 0.977 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1 SLICE_X176Y82 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3]/C clock pessimism -0.208 0.769 SLICE_X176Y82 FDCE (Remov_fdce_C_CLR) -0.050 0.719 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txResetDone_r_reg[3] ------------------------------------------------------------------- required time -0.719 arrival time 2.006 ------------------------------------------------------------------- slack 1.287 --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: txWordclkl8_4 To Clock: txWordclkl8_4 Setup : 0 Failing Endpoints, Worst Slack 5.805ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 1.220ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.805ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r2_reg[4]/CLR (recovery check against rising-edge clock txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_4 rise@8.200ns - txWordclkl8_4 rise@0.000ns) Data Path Delay: 1.923ns (logic 0.987ns (51.325%) route 0.936ns (48.675%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.582ns = ( 9.782 - 8.200 ) Source Clock Delay (SCD): 1.896ns Clock Pessimism Removal (CPR): 0.090ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y6 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 1.896 1.896 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y7 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y7 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.944 2.840 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 0.617 3.458 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/tx_reset_done[4] SLICE_X184Y91 LUT1 (Prop_lut1_I0_O) 0.043 3.501 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r[4]_i_1/O net (fo=2, routed) 0.319 3.820 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r[4]_i_1_n_0 SLICE_X184Y91 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r2_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 8.200 8.200 r BUFGCTRL_X0Y6 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 1.582 9.782 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_2 SLICE_X184Y91 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r2_reg[4]/C clock pessimism 0.090 9.872 clock uncertainty -0.035 9.837 SLICE_X184Y91 FDCE (Recov_fdce_C_CLR) -0.212 9.625 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r2_reg[4] ------------------------------------------------------------------- required time 9.625 arrival time -3.820 ------------------------------------------------------------------- slack 5.805 Slack (MET) : 5.805ns (required time - arrival time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r_reg[4]/CLR (recovery check against rising-edge clock txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.200ns (txWordclkl8_4 rise@8.200ns - txWordclkl8_4 rise@0.000ns) Data Path Delay: 1.923ns (logic 0.987ns (51.325%) route 0.936ns (48.675%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.224ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 1.582ns = ( 9.782 - 8.200 ) Source Clock Delay (SCD): 1.896ns Clock Pessimism Removal (CPR): 0.090ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y6 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 1.896 1.896 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y7 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y7 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.944 2.840 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 0.617 3.458 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/tx_reset_done[4] SLICE_X184Y91 LUT1 (Prop_lut1_I0_O) 0.043 3.501 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r[4]_i_1/O net (fo=2, routed) 0.319 3.820 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r[4]_i_1_n_0 SLICE_X184Y91 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 8.200 8.200 r BUFGCTRL_X0Y6 BUFG 0.000 8.200 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 1.582 9.782 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_2 SLICE_X184Y91 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r_reg[4]/C clock pessimism 0.090 9.872 clock uncertainty -0.035 9.837 SLICE_X184Y91 FDCE (Recov_fdce_C_CLR) -0.212 9.625 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r_reg[4] ------------------------------------------------------------------- required time 9.625 arrival time -3.820 ------------------------------------------------------------------- slack 5.805 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 1.220ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r2_reg[4]/CLR (removal check against rising-edge clock txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_4 rise@0.000ns - txWordclkl8_4 rise@0.000ns) Data Path Delay: 1.013ns (logic 0.557ns (54.983%) route 0.456ns (45.017%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.137ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.985ns Source Clock Delay (SCD): 0.914ns Clock Pessimism Removal (CPR): 0.208ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y6 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 0.914 0.914 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y7 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y7 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.529 1.443 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 0.311 1.755 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/tx_reset_done[4] SLICE_X184Y91 LUT1 (Prop_lut1_I0_O) 0.028 1.783 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r[4]_i_1/O net (fo=2, routed) 0.145 1.928 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r[4]_i_1_n_0 SLICE_X184Y91 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r2_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y6 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 0.985 0.985 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_2 SLICE_X184Y91 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r2_reg[4]/C clock pessimism -0.208 0.777 SLICE_X184Y91 FDCE (Remov_fdce_C_CLR) -0.069 0.708 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r2_reg[4] ------------------------------------------------------------------- required time -0.708 arrival time 1.928 ------------------------------------------------------------------- slack 1.220 Slack (MET) : 1.220ns (arrival time - required time) Source: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 (rising edge-triggered cell GTXE2_CHANNEL clocked by txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Destination: ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r_reg[4]/CLR (removal check against rising-edge clock txWordclkl8_4 {rise@0.000ns fall@4.100ns period=8.200ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (txWordclkl8_4 rise@0.000ns - txWordclkl8_4 rise@0.000ns) Data Path Delay: 1.013ns (logic 0.557ns (54.983%) route 0.456ns (45.017%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.137ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.985ns Source Clock Delay (SCD): 0.914ns Clock Pessimism Removal (CPR): 0.208ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y6 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 0.914 0.914 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txusrclk2_in GTXE2_CHANNEL_X0Y7 GTXE2_CHANNEL r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXUSRCLK2 ------------------------------------------------------------------- ------------------- GTXE2_CHANNEL_X0Y7 GTXE2_CHANNEL (Prop_gtxe2_channel_TXUSRCLK2_TXRESETDONE) 0.529 1.443 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXRESETDONE net (fo=3, routed) 0.311 1.755 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/tx_reset_done[4] SLICE_X184Y91 LUT1 (Prop_lut1_I0_O) 0.028 1.783 f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r[4]_i_1/O net (fo=2, routed) 0.145 1.928 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r[4]_i_1_n_0 SLICE_X184Y91 FDCE f ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r_reg[4]/CLR ------------------------------------------------------------------- ------------------- (clock txWordclkl8_4 rise edge) 0.000 0.000 r BUFGCTRL_X0Y6 BUFG 0.000 0.000 r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O net (fo=221, routed) 0.985 0.985 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_2 SLICE_X184Y91 FDCE r ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r_reg[4]/C clock pessimism -0.208 0.777 SLICE_X184Y91 FDCE (Remov_fdce_C_CLR) -0.069 0.708 ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txResetDone_r_reg[4] ------------------------------------------------------------------- required time -0.708 arrival time 1.928 ------------------------------------------------------------------- slack 1.220