Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 | Date : Mon May 18 09:54:26 2020 | Host : baby running 64-bit major release (build 9200) | Command : report_methodology -file fc7_top_methodology_drc_routed.rpt -pb fc7_top_methodology_drc_routed.pb -rpx fc7_top_methodology_drc_routed.rpx | Design : fc7_top | Device : xc7k420tffg1156-2 | Speed File : -2 | Design State : Fully Routed ----------------------------------------------------------------------------------------------------------------------------------------------------------- Report Methodology Table of Contents ----------------- 1. REPORT SUMMARY 2. REPORT DETAILS 1. REPORT SUMMARY ----------------- Netlist: netlist Floorplan: design_1 Design limits: Max violations: Violations found: 502 +-----------+----------+----------------------------------------------------+------------+ | Rule | Severity | Description | Violations | +-----------+----------+----------------------------------------------------+------------+ | CKLD-1 | Warning | Clock Net has non-BUF driver and too many loads | 1 | | LUTAR-1 | Warning | LUT drives async reset alert | 158 | | PDRC-190 | Warning | Suboptimally placed synchronized register chain | 5 | | TIMING-2 | Warning | Invalid primary clock source pin | 13 | | TIMING-3 | Warning | Invalid primary clock on Clock Modifying Block | 12 | | TIMING-4 | Warning | Invalid primary clock redefinition on a clock tree | 13 | | TIMING-9 | Warning | Unknown CDC Logic | 1 | | TIMING-10 | Warning | Missing property on synchronizer | 1 | | TIMING-17 | Warning | Non-clocked sequential cell | 4 | | TIMING-18 | Warning | Missing input or output delay | 193 | | TIMING-20 | Warning | Non-clocked latch | 73 | | TIMING-24 | Warning | Overridden Max delay datapath only | 24 | | XDCB-5 | Warning | Runtime inefficient way to find pin objects | 4 | +-----------+----------+----------------------------------------------------+------------+ 2. REPORT DETAILS ----------------- CKLD-1#1 Warning Clock Net has non-BUF driver and too many loads Clock net ngFEC/fabric_clk_div2 is not driven by a Clock Buffer and has more than 512 loads. Driver(s): ngFEC/gbtbank1_l12_118/fabric_clk_div2, ngFEC/SFP_GEN[4].ngCCM_gbt/fabric_clk_div2, ngFEC/SFP_GEN[10].ngCCM_gbt/fabric_clk_div2, ngFEC/SFP_GEN[11].ngCCM_gbt/fabric_clk_div2, ngFEC/SFP_GEN[12].ngCCM_gbt/fabric_clk_div2, ngFEC/SFP_GEN[1].ngCCM_gbt/fabric_clk_div2, ngFEC/SFP_GEN[2].ngCCM_gbt/fabric_clk_div2, ngFEC/SFP_GEN[3].ngCCM_gbt/fabric_clk_div2, ngFEC/SFP_GEN[5].ngCCM_gbt/fabric_clk_div2, ngFEC/SFP_GEN[6].ngCCM_gbt/fabric_clk_div2, ngFEC/SFP_GEN[7].ngCCM_gbt/fabric_clk_div2, ngFEC/SFP_GEN[8].ngCCM_gbt/fabric_clk_div2, ngFEC/SFP_GEN[9].ngCCM_gbt/fabric_clk_div2, ngFEC/clkRate2/fabric_clk_div2, ngFEC/ctrl_regs_inst/fabric_clk_div2 (the first 15 of 19 listed) Related violations: LUTAR-1#1 Warning LUT drives async reset alert LUT cell ngFEC/SFP_GEN[10].ngCCM_gbt/FSM_sequential_StateJTAGTDO[1]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#2 Warning LUT drives async reset alert LUT cell ngFEC/SFP_GEN[11].ngCCM_gbt/FSM_sequential_StateJTAGTDO[1]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, ngFEC/SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, ngFEC/SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, ngFEC/SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, ngFEC/SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, ngFEC/SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, ngFEC/SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, ngFEC/SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, ngFEC/SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, ngFEC/SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, ngFEC/SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, ngFEC/SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, ngFEC/SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, ngFEC/SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, ngFEC/SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#3 Warning LUT drives async reset alert LUT cell ngFEC/SFP_GEN[12].ngCCM_gbt/FSM_sequential_StateJTAGTDO[1]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#4 Warning LUT drives async reset alert LUT cell ngFEC/SFP_GEN[1].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_2__6, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, ngFEC/SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, ngFEC/SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, ngFEC/SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, ngFEC/SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, ngFEC/SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, ngFEC/SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, ngFEC/SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, ngFEC/SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, ngFEC/SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, ngFEC/SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, ngFEC/SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, ngFEC/SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, ngFEC/SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, ngFEC/SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#5 Warning LUT drives async reset alert LUT cell ngFEC/SFP_GEN[2].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_2__5, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, ngFEC/SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, ngFEC/SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, ngFEC/SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, ngFEC/SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, ngFEC/SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, ngFEC/SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, ngFEC/SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, ngFEC/SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, ngFEC/SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, ngFEC/SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, ngFEC/SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, ngFEC/SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, ngFEC/SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, ngFEC/SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#6 Warning LUT drives async reset alert LUT cell ngFEC/SFP_GEN[3].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_2__4, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, ngFEC/SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, ngFEC/SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, ngFEC/SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, ngFEC/SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, ngFEC/SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, ngFEC/SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, ngFEC/SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, ngFEC/SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, ngFEC/SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, ngFEC/SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, ngFEC/SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, ngFEC/SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, ngFEC/SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, ngFEC/SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#7 Warning LUT drives async reset alert LUT cell ngFEC/SFP_GEN[4].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_2__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, ngFEC/SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, ngFEC/SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, ngFEC/SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, ngFEC/SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, ngFEC/SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, ngFEC/SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, ngFEC/SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, ngFEC/SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, ngFEC/SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, ngFEC/SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, ngFEC/SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, ngFEC/SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, ngFEC/SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, ngFEC/SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#8 Warning LUT drives async reset alert LUT cell ngFEC/SFP_GEN[5].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, ngFEC/SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, ngFEC/SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, ngFEC/SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, ngFEC/SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, ngFEC/SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, ngFEC/SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, ngFEC/SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, ngFEC/SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, ngFEC/SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, ngFEC/SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, ngFEC/SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, ngFEC/SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, ngFEC/SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, ngFEC/SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#9 Warning LUT drives async reset alert LUT cell ngFEC/SFP_GEN[6].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, ngFEC/SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, ngFEC/SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, ngFEC/SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, ngFEC/SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, ngFEC/SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, ngFEC/SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, ngFEC/SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, ngFEC/SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, ngFEC/SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, ngFEC/SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, ngFEC/SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, ngFEC/SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, ngFEC/SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, ngFEC/SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#10 Warning LUT drives async reset alert LUT cell ngFEC/SFP_GEN[7].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, ngFEC/SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, ngFEC/SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, ngFEC/SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, ngFEC/SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, ngFEC/SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, ngFEC/SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, ngFEC/SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, ngFEC/SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, ngFEC/SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, ngFEC/SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, ngFEC/SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, ngFEC/SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, ngFEC/SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, ngFEC/SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#11 Warning LUT drives async reset alert LUT cell ngFEC/SFP_GEN[8].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, ngFEC/SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, ngFEC/SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, ngFEC/SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, ngFEC/SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, ngFEC/SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, ngFEC/SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, ngFEC/SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, ngFEC/SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, ngFEC/SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, ngFEC/SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, ngFEC/SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, ngFEC/SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, ngFEC/SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, ngFEC/SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#12 Warning LUT drives async reset alert LUT cell ngFEC/SFP_GEN[9].ngCCM_gbt/Sync_TX_Reset/FSM_sequential_StateJTAGTDO[1]_i_2__7, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[0]/CLR, ngFEC/SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[10]/CLR, ngFEC/SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[11]/CLR, ngFEC/SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[12]/CLR, ngFEC/SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[13]/CLR, ngFEC/SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[14]/CLR, ngFEC/SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[15]/CLR, ngFEC/SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[1]/CLR, ngFEC/SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[2]/CLR, ngFEC/SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[3]/CLR, ngFEC/SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[4]/CLR, ngFEC/SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[5]/CLR, ngFEC/SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[6]/CLR, ngFEC/SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[7]/CLR, ngFEC/SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/BitCount_reg[8]/CLR (the first 15 of 154 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#13 Warning LUT drives async reset alert LUT cell ngFEC/ctrl_regs_inst/FSM_onehot_state[2]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/cdce_synch/FSM_onehot_state_reg[1]/CLR, ngFEC/cdce_synch/FSM_onehot_state_reg[2]/CLR, ngFEC/cdce_synch/timer_reg[0]/CLR, ngFEC/cdce_synch/timer_reg[10]/CLR, ngFEC/cdce_synch/timer_reg[11]/CLR, ngFEC/cdce_synch/timer_reg[12]/CLR, ngFEC/cdce_synch/timer_reg[13]/CLR, ngFEC/cdce_synch/timer_reg[14]/CLR, ngFEC/cdce_synch/timer_reg[15]/CLR, ngFEC/cdce_synch/timer_reg[16]/CLR, ngFEC/cdce_synch/timer_reg[17]/CLR, ngFEC/cdce_synch/timer_reg[18]/CLR, ngFEC/cdce_synch/timer_reg[19]/CLR, ngFEC/cdce_synch/timer_reg[1]/CLR, ngFEC/cdce_synch/timer_reg[2]/CLR (the first 15 of 26 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#14 Warning LUT drives async reset alert LUT cell ngFEC/ctrl_regs_inst/PS_max[9]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/g_pm[10].phase_mon/PS_max_reg[0]/CLR, ngFEC/g_pm[10].phase_mon/PS_max_reg[1]/CLR, ngFEC/g_pm[10].phase_mon/PS_max_reg[2]/CLR, ngFEC/g_pm[10].phase_mon/PS_max_reg[3]/CLR, ngFEC/g_pm[10].phase_mon/PS_max_reg[4]/CLR, ngFEC/g_pm[10].phase_mon/PS_max_reg[5]/CLR, ngFEC/g_pm[10].phase_mon/PS_max_reg[6]/CLR, ngFEC/g_pm[10].phase_mon/PS_max_reg[7]/CLR, ngFEC/g_pm[10].phase_mon/PS_max_reg[8]/CLR, ngFEC/g_pm[10].phase_mon/PS_max_reg[9]/CLR, ngFEC/g_pm[10].phase_mon/en_chk_reg[0]/CLR, ngFEC/g_pm[10].phase_mon/en_chk_reg[1]/CLR, ngFEC/g_pm[10].phase_mon/en_chk_reg[2]/CLR, ngFEC/g_pm[10].phase_mon/old_fabric_clk_PS_toggle_reg/CLR, ngFEC/g_pm[10].phase_mon/sample_PS_Sync_q_reg/CLR (the first 15 of 90 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#15 Warning LUT drives async reset alert LUT cell ngFEC/ctrl_regs_inst/PS_max[9]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/g_pm[6].phase_mon/PS_max_reg[0]/CLR, ngFEC/g_pm[6].phase_mon/PS_max_reg[1]/CLR, ngFEC/g_pm[6].phase_mon/PS_max_reg[2]/CLR, ngFEC/g_pm[6].phase_mon/PS_max_reg[3]/CLR, ngFEC/g_pm[6].phase_mon/PS_max_reg[4]/CLR, ngFEC/g_pm[6].phase_mon/PS_max_reg[5]/CLR, ngFEC/g_pm[6].phase_mon/PS_max_reg[6]/CLR, ngFEC/g_pm[6].phase_mon/PS_max_reg[7]/CLR, ngFEC/g_pm[6].phase_mon/PS_max_reg[8]/CLR, ngFEC/g_pm[6].phase_mon/PS_max_reg[9]/CLR, ngFEC/g_pm[6].phase_mon/en_chk_reg[0]/CLR, ngFEC/g_pm[6].phase_mon/en_chk_reg[1]/CLR, ngFEC/g_pm[6].phase_mon/en_chk_reg[2]/CLR, ngFEC/g_pm[6].phase_mon/old_fabric_clk_PS_toggle_reg/CLR, ngFEC/g_pm[6].phase_mon/sample_PS_Sync_q_reg/CLR (the first 15 of 120 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#16 Warning LUT drives async reset alert LUT cell ngFEC/ctrl_regs_inst/PS_max[9]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/g_pm[2].phase_mon/PS_max_reg[0]/CLR, ngFEC/g_pm[2].phase_mon/PS_max_reg[1]/CLR, ngFEC/g_pm[2].phase_mon/PS_max_reg[2]/CLR, ngFEC/g_pm[2].phase_mon/PS_max_reg[3]/CLR, ngFEC/g_pm[2].phase_mon/PS_max_reg[4]/CLR, ngFEC/g_pm[2].phase_mon/PS_max_reg[5]/CLR, ngFEC/g_pm[2].phase_mon/PS_max_reg[6]/CLR, ngFEC/g_pm[2].phase_mon/PS_max_reg[7]/CLR, ngFEC/g_pm[2].phase_mon/PS_max_reg[8]/CLR, ngFEC/g_pm[2].phase_mon/PS_max_reg[9]/CLR, ngFEC/g_pm[2].phase_mon/en_chk_reg[0]/CLR, ngFEC/g_pm[2].phase_mon/en_chk_reg[1]/CLR, ngFEC/g_pm[2].phase_mon/en_chk_reg[2]/CLR, ngFEC/g_pm[2].phase_mon/old_fabric_clk_PS_toggle_reg/CLR, ngFEC/g_pm[2].phase_mon/sample_PS_Sync_q_reg/CLR (the first 15 of 120 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#17 Warning LUT drives async reset alert LUT cell ngFEC/ctrl_regs_inst/PS_max[9]_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/g_pm[1].phase_mon/PS_max_reg[0]/CLR, ngFEC/g_pm[1].phase_mon/PS_max_reg[1]/CLR, ngFEC/g_pm[1].phase_mon/PS_max_reg[2]/CLR, ngFEC/g_pm[1].phase_mon/PS_max_reg[3]/CLR, ngFEC/g_pm[1].phase_mon/PS_max_reg[4]/CLR, ngFEC/g_pm[1].phase_mon/PS_max_reg[5]/CLR, ngFEC/g_pm[1].phase_mon/PS_max_reg[6]/CLR, ngFEC/g_pm[1].phase_mon/PS_max_reg[7]/CLR, ngFEC/g_pm[1].phase_mon/PS_max_reg[8]/CLR, ngFEC/g_pm[1].phase_mon/PS_max_reg[9]/CLR, ngFEC/g_pm[1].phase_mon/en_chk_reg[0]/CLR, ngFEC/g_pm[1].phase_mon/en_chk_reg[1]/CLR, ngFEC/g_pm[1].phase_mon/en_chk_reg[2]/CLR, ngFEC/g_pm[1].phase_mon/old_fabric_clk_PS_toggle_reg/CLR, ngFEC/g_pm[1].phase_mon/sample_PS_Sync_q_reg/CLR (the first 15 of 30 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#18 Warning LUT drives async reset alert LUT cell ngFEC/ctrl_regs_inst/genRxRstMgtClk_s_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE, ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#19 Warning LUT drives async reset alert LUT cell ngFEC/ctrl_regs_inst/genRxRstMgtClk_s_i_1__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE, ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#20 Warning LUT drives async reset alert LUT cell ngFEC/ctrl_regs_inst/genRxRstMgtClk_s_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE, ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#21 Warning LUT drives async reset alert LUT cell ngFEC/ctrl_regs_inst/genRxRstMgtClk_s_i_1__10, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE, ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#22 Warning LUT drives async reset alert LUT cell ngFEC/ctrl_regs_inst/genRxRstMgtClk_s_i_1__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE, ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#23 Warning LUT drives async reset alert LUT cell ngFEC/ctrl_regs_inst/genRxRstMgtClk_s_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE, ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#24 Warning LUT drives async reset alert LUT cell ngFEC/ctrl_regs_inst/genRxRstMgtClk_s_i_1__4, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE, ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#25 Warning LUT drives async reset alert LUT cell ngFEC/ctrl_regs_inst/genRxRstMgtClk_s_i_1__5, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE, ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#26 Warning LUT drives async reset alert LUT cell ngFEC/ctrl_regs_inst/genRxRstMgtClk_s_i_1__6, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE, ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#27 Warning LUT drives async reset alert LUT cell ngFEC/ctrl_regs_inst/genRxRstMgtClk_s_i_1__7, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE, ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#28 Warning LUT drives async reset alert LUT cell ngFEC/ctrl_regs_inst/genRxRstMgtClk_s_i_1__8, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[3].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE, ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[3].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#29 Warning LUT drives async reset alert LUT cell ngFEC/ctrl_regs_inst/genRxRstMgtClk_s_i_1__9, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRxRstMgtClk_s_reg/PRE, ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genRxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#30 Warning LUT drives async reset alert LUT cell ngFEC/ctrl_regs_inst/genTxRstMgtClk_s_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/genTxRstMgtClk_s_reg/PRE, ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/genTxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#31 Warning LUT drives async reset alert LUT cell ngFEC/ctrl_regs_inst/genTxRstMgtClk_s_i_1__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genTxRstMgtClk_s_reg/PRE, ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genTxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#32 Warning LUT drives async reset alert LUT cell ngFEC/ctrl_regs_inst/genTxRstMgtClk_s_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genTxRstMgtClk_s_reg/PRE, ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genTxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#33 Warning LUT drives async reset alert LUT cell ngFEC/ctrl_regs_inst/genTxRstMgtClk_s_i_1__10, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genTxRstMgtClk_s_reg/PRE, ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genTxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#34 Warning LUT drives async reset alert LUT cell ngFEC/ctrl_regs_inst/genTxRstMgtClk_s_i_1__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genTxRstMgtClk_s_reg/PRE, ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genTxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#35 Warning LUT drives async reset alert LUT cell ngFEC/ctrl_regs_inst/genTxRstMgtClk_s_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genTxRstMgtClk_s_reg/PRE, ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genTxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#36 Warning LUT drives async reset alert LUT cell ngFEC/ctrl_regs_inst/genTxRstMgtClk_s_i_1__4, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/genTxRstMgtClk_s_reg/PRE, ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/genTxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#37 Warning LUT drives async reset alert LUT cell ngFEC/ctrl_regs_inst/genTxRstMgtClk_s_i_1__5, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genTxRstMgtClk_s_reg/PRE, ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genTxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#38 Warning LUT drives async reset alert LUT cell ngFEC/ctrl_regs_inst/genTxRstMgtClk_s_i_1__6, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genTxRstMgtClk_s_reg/PRE, ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/genTxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#39 Warning LUT drives async reset alert LUT cell ngFEC/ctrl_regs_inst/genTxRstMgtClk_s_i_1__7, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/genTxRstMgtClk_s_reg/PRE, ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/genTxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#40 Warning LUT drives async reset alert LUT cell ngFEC/ctrl_regs_inst/genTxRstMgtClk_s_i_1__8, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[3].gbtBank_gbtBankRst/genTxRstMgtClk_s_reg/PRE, ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[3].gbtBank_gbtBankRst/genTxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#41 Warning LUT drives async reset alert LUT cell ngFEC/ctrl_regs_inst/genTxRstMgtClk_s_i_1__9, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genTxRstMgtClk_s_reg/PRE, ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/genTxRstMgtClk_sync_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#42 Warning LUT drives async reset alert LUT cell ngFEC/ctrl_regs_inst/mmcm_adv_inst_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/dmdt_clk/mmcm1/U0/mmcm_adv_inst/RST, ngFEC/dmdt_clk/mmcm2/U0/mmcm_adv_inst/RST, ngFEC/dmdt_meas/DMTD_A/U_sync_tag_strobe/sync_posedge.ppulse_o_reg/CLR, ngFEC/dmdt_meas/DMTD_A/U_sync_tag_strobe/sync_posedge.sync0_reg/CLR, ngFEC/dmdt_meas/DMTD_A/U_sync_tag_strobe/sync_posedge.sync1_reg/CLR, ngFEC/dmdt_meas/DMTD_A/U_sync_tag_strobe/sync_posedge.sync2_reg/CLR, ngFEC/dmdt_meas/DMTD_B/U_sync_tag_strobe/sync_posedge.ppulse_o_reg/CLR, ngFEC/dmdt_meas/DMTD_B/U_sync_tag_strobe/sync_posedge.sync0_reg/CLR, ngFEC/dmdt_meas/DMTD_B/U_sync_tag_strobe/sync_posedge.sync1_reg/CLR, ngFEC/dmdt_meas/DMTD_B/U_sync_tag_strobe/sync_posedge.sync2_reg/CLR, ngFEC/dmdt_meas/sync_busy_clka/sync_posedge.sync0_reg/CLR, ngFEC/dmdt_meas/sync_busy_clka/sync_posedge.sync1_reg/CLR, ngFEC/dmdt_meas/sync_busy_clka/sync_posedge.synced_o_reg/CLR, ngFEC/dmdt_meas/sync_done_clka/sync_posedge.sync0_reg/CLR, ngFEC/dmdt_meas/sync_done_clka/sync_posedge.sync1_reg/CLR (the first 15 of 115 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#43 Warning LUT drives async reset alert LUT cell ngFEC/ctrl_regs_inst/timer[0]_i_3__10, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[0]/CLR, ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[10]/CLR, ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[11]/CLR, ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[12]/CLR, ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[13]/CLR, ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[14]/CLR, ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[15]/CLR, ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[16]/CLR, ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[17]/CLR, ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[18]/CLR, ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[19]/CLR, ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[1]/CLR, ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[20]/CLR, ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[21]/CLR, ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[22]/CLR (the first 15 of 108 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#44 Warning LUT drives async reset alert LUT cell ngFEC/ctrl_regs_inst/timer[0]_i_3__11, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[0]/CLR, ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[10]/CLR, ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[11]/CLR, ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[12]/CLR, ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[13]/CLR, ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[14]/CLR, ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[15]/CLR, ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[16]/CLR, ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[17]/CLR, ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[18]/CLR, ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[19]/CLR, ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[1]/CLR, ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[20]/CLR, ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[21]/CLR, ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[22]/CLR (the first 15 of 81 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#45 Warning LUT drives async reset alert LUT cell ngFEC/ctrl_regs_inst/timer[0]_i_3__9, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[0]/CLR, ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[10]/CLR, ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[11]/CLR, ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[12]/CLR, ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[13]/CLR, ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[14]/CLR, ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[15]/CLR, ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[16]/CLR, ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[17]/CLR, ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[18]/CLR, ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[19]/CLR, ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[1]/CLR, ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[20]/CLR, ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[21]/CLR, ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/timer_reg[22]/CLR (the first 15 of 135 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#46 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#47 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE, ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg_rep/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#48 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[0]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[1]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[2]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[3]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[4]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_done_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#49 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[0]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[1]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[2]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[3]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[4]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_done_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#50 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#51 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtTxReset_s_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#52 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_i_1__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#53 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtTxReset_s_i_1__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE, ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtTxReset_s_reg_rep/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#54 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[0]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[1]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[2]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[3]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[4]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_done_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#55 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[0]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[1]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[2]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[3]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[4]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_done_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#56 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#57 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtTxReset_s_i_1__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#58 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#59 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE, ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg_rep/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#60 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[0]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[1]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[2]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[3]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[4]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_done_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#61 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[0]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[1]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[2]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[3]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[4]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_done_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#62 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#63 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtTxReset_s_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#64 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank1_l12_118/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0]/CLR, ngFEC/gbtbank1_l12_118/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]/CLR, ngFEC/gbtbank1_l12_118/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2]/CLR, ngFEC/gbtbank1_l12_118/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/CLR, ngFEC/gbtbank1_l12_118/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4]/CLR, ngFEC/gbtbank1_l12_118/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][5]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#65 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank1_l12_118/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0]/CLR, ngFEC/gbtbank1_l12_118/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/CLR, ngFEC/gbtbank1_l12_118/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2]/CLR, ngFEC/gbtbank1_l12_118/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/CLR, ngFEC/gbtbank1_l12_118/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]/CLR, ngFEC/gbtbank1_l12_118/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][5]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#66 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank1_l12_118/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/CLR, ngFEC/gbtbank1_l12_118/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1]/CLR, ngFEC/gbtbank1_l12_118/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2]/CLR, ngFEC/gbtbank1_l12_118/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/CLR, ngFEC/gbtbank1_l12_118/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]/CLR, ngFEC/gbtbank1_l12_118/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][5]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#67 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/DONE_o_reg/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/FSM_onehot_state_reg[1]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/FSM_onehot_state_reg[2]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/READY_o_reg/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/RX_BITSLIPCMD_o_reg/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/FSM_onehot_state_reg[0]/PRE, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/FSM_sequential_state_reg[0]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/FSM_sequential_state_reg[1]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCmd_reg/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[0]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[1]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[2]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[3]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[4]/CLR (the first 15 of 20 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#68 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/DONE_o_reg/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/FSM_onehot_state_reg[1]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/FSM_onehot_state_reg[2]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/READY_o_reg/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/RX_BITSLIPCMD_o_reg/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/FSM_onehot_state_reg[0]/PRE, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/RX_HEADER_LOCKED_O_reg/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCmd_reg/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[0]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[1]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[2]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[3]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[4]/CLR (the first 15 of 20 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#69 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/DONE_o_reg/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[1]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[2]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/READY_o_reg/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_BITSLIPCMD_o_reg/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[0]/PRE, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[0]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[1]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/RX_HEADER_LOCKED_O_reg/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCmd_reg/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[0]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[1]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[2]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[3]/CLR, ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[4]/CLR (the first 15 of 20 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#70 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/mgtTxReady_s_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtTxReady_s_reg/CLR, ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtTxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#71 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/mgtTxReady_s_i_1__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtTxReady_s_reg/CLR, ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtTxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#72 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/mgtTxReady_s_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtTxReady_s_reg/CLR, ngFEC/gbtbank1_l12_118/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtTxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#73 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_i_1__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#74 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_i_1__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE, ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg_rep/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#75 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst_i_1__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[0]/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[1]/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[2]/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[3]/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[4]/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_done_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#76 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[0]/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[1]/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[2]/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[3]/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[4]/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_done_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#77 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#78 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtTxReset_s_i_1__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#79 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#80 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtTxReset_s_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE, ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtTxReset_s_reg_rep/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#81 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst_i_1__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[0]/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[1]/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[2]/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[3]/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[4]/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_done_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#82 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[0]/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[1]/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[2]/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[3]/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[4]/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_done_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#83 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#84 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtTxReset_s_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#85 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank2_l12_117/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0]/CLR, ngFEC/gbtbank2_l12_117/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]/CLR, ngFEC/gbtbank2_l12_117/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2]/CLR, ngFEC/gbtbank2_l12_117/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/CLR, ngFEC/gbtbank2_l12_117/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4]/CLR, ngFEC/gbtbank2_l12_117/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][5]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#86 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank2_l12_117/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0]/CLR, ngFEC/gbtbank2_l12_117/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/CLR, ngFEC/gbtbank2_l12_117/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2]/CLR, ngFEC/gbtbank2_l12_117/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/CLR, ngFEC/gbtbank2_l12_117/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]/CLR, ngFEC/gbtbank2_l12_117/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][5]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#87 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/DONE_o_reg/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/FSM_onehot_state_reg[1]/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/FSM_onehot_state_reg[2]/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/READY_o_reg/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/RX_BITSLIPCMD_o_reg/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/FSM_onehot_state_reg[0]/PRE, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/FSM_sequential_state_reg[0]/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/FSM_sequential_state_reg[1]/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCmd_reg/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[0]/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[1]/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[2]/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[3]/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[4]/CLR (the first 15 of 20 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#88 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/DONE_o_reg/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/FSM_onehot_state_reg[1]/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/FSM_onehot_state_reg[2]/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/READY_o_reg/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/RX_BITSLIPCMD_o_reg/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/FSM_onehot_state_reg[0]/PRE, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/RX_HEADER_LOCKED_O_reg/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCmd_reg/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[0]/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[1]/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[2]/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[3]/CLR, ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[4]/CLR (the first 15 of 20 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#89 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/mgtTxReady_s_i_1__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtTxReady_s_reg/CLR, ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtTxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#90 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/mgtTxReady_s_i_1__3, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtTxReady_s_reg/CLR, ngFEC/gbtbank2_l12_117/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtTxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#91 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_i_1__4, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#92 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_i_1__4, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE, ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg_rep/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#93 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[0]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[1]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[2]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[3]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[4]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_done_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#94 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[0]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[1]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[2]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[3]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[4]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_done_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#95 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#96 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtTxReset_s_i_1__4, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#97 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_i_1__5, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#98 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtTxReset_s_i_1__5, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE, ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtTxReset_s_reg_rep/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#99 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[0]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[1]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[2]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[3]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[4]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_done_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#100 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[0]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[1]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[2]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[3]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[4]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_done_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#101 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#102 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtTxReset_s_i_1__5, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#103 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_i_1__6, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#104 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_i_1__6, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE, ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg_rep/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#105 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst_i_1__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[0]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[1]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[2]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[3]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[4]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_done_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#106 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[0]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[1]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[2]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[3]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[4]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_done_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#107 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#108 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtTxReset_s_i_1__6, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#109 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank3_l12_116/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0]/CLR, ngFEC/gbtbank3_l12_116/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]/CLR, ngFEC/gbtbank3_l12_116/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2]/CLR, ngFEC/gbtbank3_l12_116/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/CLR, ngFEC/gbtbank3_l12_116/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4]/CLR, ngFEC/gbtbank3_l12_116/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][5]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#110 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank3_l12_116/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0]/CLR, ngFEC/gbtbank3_l12_116/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/CLR, ngFEC/gbtbank3_l12_116/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2]/CLR, ngFEC/gbtbank3_l12_116/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/CLR, ngFEC/gbtbank3_l12_116/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]/CLR, ngFEC/gbtbank3_l12_116/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][5]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#111 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank3_l12_116/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/CLR, ngFEC/gbtbank3_l12_116/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1]/CLR, ngFEC/gbtbank3_l12_116/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2]/CLR, ngFEC/gbtbank3_l12_116/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/CLR, ngFEC/gbtbank3_l12_116/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]/CLR, ngFEC/gbtbank3_l12_116/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][5]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#112 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/DONE_o_reg/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/FSM_onehot_state_reg[1]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/FSM_onehot_state_reg[2]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/READY_o_reg/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/RX_BITSLIPCMD_o_reg/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/FSM_onehot_state_reg[0]/PRE, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/FSM_sequential_state_reg[0]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/FSM_sequential_state_reg[1]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCmd_reg/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[0]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[1]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[2]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[3]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[4]/CLR (the first 15 of 20 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#113 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/DONE_o_reg/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/FSM_onehot_state_reg[1]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/FSM_onehot_state_reg[2]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/READY_o_reg/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/RX_BITSLIPCMD_o_reg/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/FSM_onehot_state_reg[0]/PRE, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/RX_HEADER_LOCKED_O_reg/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCmd_reg/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[0]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[1]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[2]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[3]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[4]/CLR (the first 15 of 20 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#114 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1__0, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/DONE_o_reg/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[1]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[2]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/READY_o_reg/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_BITSLIPCMD_o_reg/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[0]/PRE, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[0]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[1]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/RX_HEADER_LOCKED_O_reg/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCmd_reg/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[0]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[1]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[2]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[3]/CLR, ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[4]/CLR (the first 15 of 20 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#115 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/mgtTxReady_s_i_1__4, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtTxReady_s_reg/CLR, ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtTxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#116 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/mgtTxReady_s_i_1__5, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtTxReady_s_reg/CLR, ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtTxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#117 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/mgtTxReady_s_i_1__6, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtTxReady_s_reg/CLR, ngFEC/gbtbank3_l12_116/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtTxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#118 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_i_1__7, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#119 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_i_1__7, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE, ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gbtTxReset_s_reg_rep/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#120 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst_i_1__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[0]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[1]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[2]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[3]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[4]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_done_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#121 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[1].gbtBank_gbtBankRst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[0]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[1]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[2]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[3]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[4]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_done_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#122 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#123 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtTxReset_s_i_1__7, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#124 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_i_1__8, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#125 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtTxReset_s_i_1__8, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE, ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gbtTxReset_s_reg_rep/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#126 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst_i_1__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[0]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[1]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[2]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[3]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[4]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_done_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#127 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[0]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[1]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[2]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[3]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[4]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_done_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#128 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#129 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtTxReset_s_i_1__8, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#130 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_i_1__9, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#131 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_i_1__9, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE, ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gbtTxReset_s_reg_rep/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#132 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[0]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[1]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[2]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[3]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[4]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_done_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#133 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[3].gbtBank_gbtBankRst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[0]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[1]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[2]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[3]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[4]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_done_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#134 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#135 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtTxReset_s_i_1__9, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#136 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_i_1__10, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#137 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtTxReset_s_i_1__10, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtTxReset_s_reg/PRE, ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gbtTxReset_s_reg_rep/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#138 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[0]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[1]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[2]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[3]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_count_reg[4]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_txresetfsm_i/init_wait_done_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#139 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[0]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[1]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[2]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[3]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_count_reg[4]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/gt0_rxresetfsm_i/init_wait_done_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#140 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReset_s0, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtRxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#141 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtTxReset_s_i_1__10, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtTxReset_s_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#142 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gbtBank_Clk_gen[1].rx_clken_sr[1][5]_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][0]/CLR, ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][1]/CLR, ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][2]/CLR, ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][3]/CLR, ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][4]/CLR, ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[1].rx_clken_sr_reg[1][5]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#143 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gbtBank_Clk_gen[2].rx_clken_sr[2][5]_i_2__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][0]/CLR, ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][1]/CLR, ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][2]/CLR, ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][3]/CLR, ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][4]/CLR, ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[2].rx_clken_sr_reg[2][5]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#144 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gbtBank_Clk_gen[3].rx_clken_sr[3][5]_i_2__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][0]/CLR, ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][1]/CLR, ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][2]/CLR, ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][3]/CLR, ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][4]/CLR, ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[3].rx_clken_sr_reg[3][5]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#145 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gbtBank_Clk_gen[4].rx_clken_sr[4][5]_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][0]/CLR, ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][1]/CLR, ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][2]/CLR, ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][3]/CLR, ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][4]/CLR, ngFEC/gbtbank4_l8_112/gbtBank_Clk_gen[4].rx_clken_sr_reg[4][5]/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#146 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/gtxLatOpt_gen[1].rxBitSlipControl_i_1__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/DONE_o_reg/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/FSM_onehot_state_reg[1]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/FSM_onehot_state_reg[2]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/READY_o_reg/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/RX_BITSLIPCMD_o_reg/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxBitSlipControl/FSM_onehot_state_reg[0]/PRE, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/FSM_sequential_state_reg[0]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/FSM_sequential_state_reg[1]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/RX_HEADER_LOCKED_O_reg/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCmd_reg/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[0]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[1]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[2]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[3]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].patternSearch/bitSlipCnt_reg[4]/CLR (the first 15 of 20 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#147 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/gtxLatOpt_gen[2].rxBitSlipControl_i_1__2, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/DONE_o_reg/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/FSM_onehot_state_reg[1]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/FSM_onehot_state_reg[2]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/READY_o_reg/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/RX_BITSLIPCMD_o_reg/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxBitSlipControl/FSM_onehot_state_reg[0]/PRE, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[0]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/FSM_sequential_state_reg[1]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/RX_HEADER_LOCKED_O_reg/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCmd_reg/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[0]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[1]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[2]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[3]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].patternSearch/bitSlipCnt_reg[4]/CLR (the first 15 of 20 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#148 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/gtxLatOpt_gen[3].rxBitSlipControl_i_1__1, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/DONE_o_reg/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[1]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[2]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/READY_o_reg/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/RX_BITSLIPCMD_o_reg/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxBitSlipControl/FSM_onehot_state_reg[0]/PRE, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[0]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/FSM_sequential_state_reg[1]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/RX_HEADER_LOCKED_O_reg/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCmd_reg/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[0]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[1]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[2]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[3]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].patternSearch/bitSlipCnt_reg[4]/CLR (the first 15 of 20 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#149 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/gtxLatOpt_gen[4].rxBitSlipControl_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxBitSlipControl/DONE_o_reg/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxBitSlipControl/FSM_onehot_state_reg[1]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxBitSlipControl/FSM_onehot_state_reg[2]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxBitSlipControl/READY_o_reg/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxBitSlipControl/RX_BITSLIPCMD_o_reg/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxBitSlipControl/FSM_onehot_state_reg[0]/PRE, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[0]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/FSM_sequential_state_reg[1]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/RX_HEADER_LOCKED_O_reg/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/bitSlipCmd_reg/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/bitSlipCnt_reg[0]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/bitSlipCnt_reg[1]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/bitSlipCnt_reg[2]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/bitSlipCnt_reg[3]/CLR, ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].patternSearch/bitSlipCnt_reg[4]/CLR (the first 15 of 20 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#150 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/mgtTxReady_s_i_1__10, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtTxReady_s_reg/CLR, ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[1].gbtBank_gbtBankRst/mgtTxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#151 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/mgtTxReady_s_i_1__7, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtTxReady_s_reg/CLR, ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[4].gbtBank_gbtBankRst/mgtTxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#152 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/mgtTxReady_s_i_1__8, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtTxReady_s_reg/CLR, ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[3].gbtBank_gbtBankRst/mgtTxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#153 Warning LUT drives async reset alert LUT cell ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/mgtTxReady_s_i_1__9, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtTxReady_s_reg/CLR, ngFEC/gbtbank4_l8_112/gbtBank_rst_gen[2].gbtBank_gbtBankRst/mgtTxReady_sync_s_reg/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#154 Warning LUT drives async reset alert LUT cell sys/clocks/bram_array[0].skip_SFP_SEC.control_reg[0][31]_i_3, with 2 or more inputs, drives asynchronous preset/clear pin(s) ngFEC/SFP_GEN[10].ngFEC_module/bram_array[0].skip_SFP_SEC.control_reg_reg[0][0]/CLR, ngFEC/SFP_GEN[10].ngFEC_module/bram_array[0].skip_SFP_SEC.control_reg_reg[0][10]/CLR, ngFEC/SFP_GEN[10].ngFEC_module/bram_array[0].skip_SFP_SEC.control_reg_reg[0][11]/CLR, ngFEC/SFP_GEN[10].ngFEC_module/bram_array[0].skip_SFP_SEC.control_reg_reg[0][12]/CLR, ngFEC/SFP_GEN[10].ngFEC_module/bram_array[0].skip_SFP_SEC.control_reg_reg[0][13]/CLR, ngFEC/SFP_GEN[10].ngFEC_module/bram_array[0].skip_SFP_SEC.control_reg_reg[0][14]/CLR, ngFEC/SFP_GEN[10].ngFEC_module/bram_array[0].skip_SFP_SEC.control_reg_reg[0][15]/CLR, ngFEC/SFP_GEN[10].ngFEC_module/bram_array[0].skip_SFP_SEC.control_reg_reg[0][16]/CLR, ngFEC/SFP_GEN[10].ngFEC_module/bram_array[0].skip_SFP_SEC.control_reg_reg[0][17]/CLR, ngFEC/SFP_GEN[10].ngFEC_module/bram_array[0].skip_SFP_SEC.control_reg_reg[0][18]/CLR, ngFEC/SFP_GEN[10].ngFEC_module/bram_array[0].skip_SFP_SEC.control_reg_reg[0][19]/CLR, ngFEC/SFP_GEN[10].ngFEC_module/bram_array[0].skip_SFP_SEC.control_reg_reg[0][1]/CLR, ngFEC/SFP_GEN[10].ngFEC_module/bram_array[0].skip_SFP_SEC.control_reg_reg[0][20]/CLR, ngFEC/SFP_GEN[10].ngFEC_module/bram_array[0].skip_SFP_SEC.control_reg_reg[0][21]/CLR, ngFEC/SFP_GEN[10].ngFEC_module/bram_array[0].skip_SFP_SEC.control_reg_reg[0][22]/CLR (the first 15 of 11724 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#155 Warning LUT drives async reset alert LUT cell sys/clocks/rst_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) sys/clocks/timer_reg[0]/CLR, sys/clocks/timer_reg[12]/CLR, sys/clocks/timer_reg[14]/CLR, sys/clocks/timer_reg[1]/CLR, sys/clocks/timer_reg[20]/CLR, sys/clocks/timer_reg[22]/CLR, sys/clocks/timer_reg[23]/CLR, sys/clocks/timer_reg[24]/CLR, sys/clocks/timer_reg[25]/CLR, sys/clocks/timer_reg[26]/CLR, sys/clocks/timer_reg[27]/CLR, sys/clocks/timer_reg[28]/CLR, sys/clocks/timer_reg[29]/CLR, sys/clocks/timer_reg[2]/CLR, sys/clocks/timer_reg[30]/CLR (the first 15 of 34 listed). The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#156 Warning LUT drives async reset alert LUT cell sys/clocks/sck_reg_LDC_i_2, with 2 or more inputs, drives asynchronous preset/clear pin(s) sys/spi/sck_reg_C/CLR, sys/spi/sck_reg_LDC/CLR. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#157 Warning LUT drives async reset alert LUT cell sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET/MGT_RESET.RESET_INT_PIPE_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.RESET_INT_PIPE_reg/PRE, sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.RESET_INT_reg/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: LUTAR-1#158 Warning LUT drives async reset alert LUT cell sys/ipb_sys_regs/sck_reg_LDC_i_1, with 2 or more inputs, drives asynchronous preset/clear pin(s) sys/spi/sck_reg_P/PRE. The LUT may glitch and trigger an unexpected reset, even if it is a properly timed path. Related violations: PDRC-190#1 Warning Suboptimally placed synchronized register chain The FDPE cell sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET/reset_sync5 in site SLICE_X184Y108 is part of a synchronized register chain that is suboptimally placed as the load FDPE cell sys/eth/phy/U0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/MGT_RESET.SYNC_ASYNC_RESET/reset_sync6 is not placed in the same (SLICE) site. Related violations: PDRC-190#2 Warning Suboptimally placed synchronized register chain The FDPE cell sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync5 in site SLICE_X188Y108 is part of a synchronized register chain that is suboptimally placed as the load FDPE cell sys/eth/phy/U0/transceiver_inst/reclock_encommaalign/reset_sync6 is not placed in the same (SLICE) site. Related violations: PDRC-190#3 Warning Suboptimally placed synchronized register chain The FDPE cell sys/eth/phy/U0/transceiver_inst/reclock_rxreset/reset_sync5 in site SLICE_X187Y115 is part of a synchronized register chain that is suboptimally placed as the load FDPE cell sys/eth/phy/U0/transceiver_inst/reclock_rxreset/reset_sync6 is not placed in the same (SLICE) site. Related violations: PDRC-190#4 Warning Suboptimally placed synchronized register chain The FDPE cell sys/eth/phy/U0/transceiver_inst/reclock_txreset/reset_sync5 in site SLICE_X184Y114 is part of a synchronized register chain that is suboptimally placed as the load FDPE cell sys/eth/phy/U0/transceiver_inst/reclock_txreset/reset_sync6 is not placed in the same (SLICE) site. Related violations: PDRC-190#5 Warning Suboptimally placed synchronized register chain The FDRE cell sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_data_valid/data_sync_reg2 in site SLICE_X186Y117 is part of a synchronized register chain that is suboptimally placed as the load FDRE cell sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_data_valid/data_sync_reg3 is not placed in the same (SLICE) site. Related violations: TIMING-2#1 Warning Invalid primary clock source pin A primary clock clk_o_39_997 is created on an inappropriate pin ngFEC/dmdt_clk/mmcm2/U0/clkout1_buf/O. It is recommended to create a primary clock only on a proper clock source (input port or primitive output pin with no timing arc) Related violations: TIMING-2#2 Warning Invalid primary clock source pin A primary clock txWordclkl12_1 is created on an inappropriate pin ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O. It is recommended to create a primary clock only on a proper clock source (input port or primitive output pin with no timing arc) Related violations: TIMING-2#3 Warning Invalid primary clock source pin A primary clock txWordclkl12_2 is created on an inappropriate pin ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O. It is recommended to create a primary clock only on a proper clock source (input port or primitive output pin with no timing arc) Related violations: TIMING-2#4 Warning Invalid primary clock source pin A primary clock txWordclkl12_3 is created on an inappropriate pin ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O. It is recommended to create a primary clock only on a proper clock source (input port or primitive output pin with no timing arc) Related violations: TIMING-2#5 Warning Invalid primary clock source pin A primary clock txWordclkl12_4 is created on an inappropriate pin ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O. It is recommended to create a primary clock only on a proper clock source (input port or primitive output pin with no timing arc) Related violations: TIMING-2#6 Warning Invalid primary clock source pin A primary clock txWordclkl12_5 is created on an inappropriate pin ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O. It is recommended to create a primary clock only on a proper clock source (input port or primitive output pin with no timing arc) Related violations: TIMING-2#7 Warning Invalid primary clock source pin A primary clock txWordclkl12_6 is created on an inappropriate pin ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O. It is recommended to create a primary clock only on a proper clock source (input port or primitive output pin with no timing arc) Related violations: TIMING-2#8 Warning Invalid primary clock source pin A primary clock txWordclkl12_7 is created on an inappropriate pin ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O. It is recommended to create a primary clock only on a proper clock source (input port or primitive output pin with no timing arc) Related violations: TIMING-2#9 Warning Invalid primary clock source pin A primary clock txWordclkl12_8 is created on an inappropriate pin ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O. It is recommended to create a primary clock only on a proper clock source (input port or primitive output pin with no timing arc) Related violations: TIMING-2#10 Warning Invalid primary clock source pin A primary clock txWordclkl8_1 is created on an inappropriate pin ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O. It is recommended to create a primary clock only on a proper clock source (input port or primitive output pin with no timing arc) Related violations: TIMING-2#11 Warning Invalid primary clock source pin A primary clock txWordclkl8_2 is created on an inappropriate pin ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O. It is recommended to create a primary clock only on a proper clock source (input port or primitive output pin with no timing arc) Related violations: TIMING-2#12 Warning Invalid primary clock source pin A primary clock txWordclkl8_3 is created on an inappropriate pin ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O. It is recommended to create a primary clock only on a proper clock source (input port or primitive output pin with no timing arc) Related violations: TIMING-2#13 Warning Invalid primary clock source pin A primary clock txWordclkl8_4 is created on an inappropriate pin ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O. It is recommended to create a primary clock only on a proper clock source (input port or primitive output pin with no timing arc) Related violations: TIMING-3#1 Warning Invalid primary clock on Clock Modifying Block A primary clock rxWordclkl12_1 is created on the output pin or net ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O of a Clock Modifying Block Related violations: TIMING-3#2 Warning Invalid primary clock on Clock Modifying Block A primary clock rxWordclkl12_2 is created on the output pin or net ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O of a Clock Modifying Block Related violations: TIMING-3#3 Warning Invalid primary clock on Clock Modifying Block A primary clock rxWordclkl12_3 is created on the output pin or net ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O of a Clock Modifying Block Related violations: TIMING-3#4 Warning Invalid primary clock on Clock Modifying Block A primary clock rxWordclkl12_4 is created on the output pin or net ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O of a Clock Modifying Block Related violations: TIMING-3#5 Warning Invalid primary clock on Clock Modifying Block A primary clock rxWordclkl12_5 is created on the output pin or net ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O of a Clock Modifying Block Related violations: TIMING-3#6 Warning Invalid primary clock on Clock Modifying Block A primary clock rxWordclkl12_6 is created on the output pin or net ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O of a Clock Modifying Block Related violations: TIMING-3#7 Warning Invalid primary clock on Clock Modifying Block A primary clock rxWordclkl12_7 is created on the output pin or net ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O of a Clock Modifying Block Related violations: TIMING-3#8 Warning Invalid primary clock on Clock Modifying Block A primary clock rxWordclkl12_8 is created on the output pin or net ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O of a Clock Modifying Block Related violations: TIMING-3#9 Warning Invalid primary clock on Clock Modifying Block A primary clock rxWordclkl8_1 is created on the output pin or net ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O of a Clock Modifying Block Related violations: TIMING-3#10 Warning Invalid primary clock on Clock Modifying Block A primary clock rxWordclkl8_2 is created on the output pin or net ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O of a Clock Modifying Block Related violations: TIMING-3#11 Warning Invalid primary clock on Clock Modifying Block A primary clock rxWordclkl8_3 is created on the output pin or net ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O of a Clock Modifying Block Related violations: TIMING-3#12 Warning Invalid primary clock on Clock Modifying Block A primary clock rxWordclkl8_4 is created on the output pin or net ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O of a Clock Modifying Block Related violations: TIMING-4#1 Warning Invalid primary clock redefinition on a clock tree Invalid clock redefinition on a clock tree. The primary clock clk_o_39_997 is defined downstream of clock clk_o_39_997_phase_mon_mmcm_2 and overrides its insertion delay and/or waveform definition Related violations: TIMING-4#2 Warning Invalid primary clock redefinition on a clock tree Invalid clock redefinition on a clock tree. The primary clock txWordclkl12_1 is defined downstream of clock ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK and overrides its insertion delay and/or waveform definition Related violations: TIMING-4#3 Warning Invalid primary clock redefinition on a clock tree Invalid clock redefinition on a clock tree. The primary clock txWordclkl12_2 is defined downstream of clock ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK and overrides its insertion delay and/or waveform definition Related violations: TIMING-4#4 Warning Invalid primary clock redefinition on a clock tree Invalid clock redefinition on a clock tree. The primary clock txWordclkl12_3 is defined downstream of clock ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK and overrides its insertion delay and/or waveform definition Related violations: TIMING-4#5 Warning Invalid primary clock redefinition on a clock tree Invalid clock redefinition on a clock tree. The primary clock txWordclkl12_4 is defined downstream of clock ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK and overrides its insertion delay and/or waveform definition Related violations: TIMING-4#6 Warning Invalid primary clock redefinition on a clock tree Invalid clock redefinition on a clock tree. The primary clock txWordclkl12_5 is defined downstream of clock ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK and overrides its insertion delay and/or waveform definition Related violations: TIMING-4#7 Warning Invalid primary clock redefinition on a clock tree Invalid clock redefinition on a clock tree. The primary clock txWordclkl12_6 is defined downstream of clock ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK and overrides its insertion delay and/or waveform definition Related violations: TIMING-4#8 Warning Invalid primary clock redefinition on a clock tree Invalid clock redefinition on a clock tree. The primary clock txWordclkl12_7 is defined downstream of clock ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK and overrides its insertion delay and/or waveform definition Related violations: TIMING-4#9 Warning Invalid primary clock redefinition on a clock tree Invalid clock redefinition on a clock tree. The primary clock txWordclkl12_8 is defined downstream of clock ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK and overrides its insertion delay and/or waveform definition Related violations: TIMING-4#10 Warning Invalid primary clock redefinition on a clock tree Invalid clock redefinition on a clock tree. The primary clock txWordclkl8_1 is defined downstream of clock ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK and overrides its insertion delay and/or waveform definition Related violations: TIMING-4#11 Warning Invalid primary clock redefinition on a clock tree Invalid clock redefinition on a clock tree. The primary clock txWordclkl8_2 is defined downstream of clock ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK and overrides its insertion delay and/or waveform definition Related violations: TIMING-4#12 Warning Invalid primary clock redefinition on a clock tree Invalid clock redefinition on a clock tree. The primary clock txWordclkl8_3 is defined downstream of clock ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK and overrides its insertion delay and/or waveform definition Related violations: TIMING-4#13 Warning Invalid primary clock redefinition on a clock tree Invalid clock redefinition on a clock tree. The primary clock txWordclkl8_4 is defined downstream of clock ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK and overrides its insertion delay and/or waveform definition Related violations: TIMING-9#1 Warning Unknown CDC Logic One or more asynchronous Clock Domain Crossing has been detected between 2 clock domains through a set_false_path or a set_clock_groups or set_max_delay -datapath_only constraint but no double-registers logic synchronizer has been found on the side of the capture clock. It is recommended to run report_cdc for a complete and detailed CDC coverage. Please consider using XPM_CDC to avoid Critical severities Related violations: TIMING-10#1 Warning Missing property on synchronizer One or more logic synchronizer has been detected between 2 clock domains but the synchronizer does not have the property ASYNC_REG defined on one or both registers. It is recommended to run report_cdc for a complete and detailed CDC coverage Related violations: TIMING-17#1 Warning Non-clocked sequential cell The clock pin ngFEC/clkRate2/clktest_div1_reg/C is not reached by a timing clock Related violations: TIMING-17#2 Warning Non-clocked sequential cell The clock pin ngFEC/clkRate2/clktest_div2_reg/C is not reached by a timing clock Related violations: TIMING-17#3 Warning Non-clocked sequential cell The clock pin ngFEC/clkRate2/clktest_div4_reg/C is not reached by a timing clock Related violations: TIMING-17#4 Warning Non-clocked sequential cell The clock pin ngFEC/clkRate2/clktest_div8_reg/C is not reached by a timing clock Related violations: TIMING-18#1 Warning Missing input or output delay An input delay is missing on cpld2fpga_ebi_nrd relative to clock(s) osc125_a Related violations: TIMING-18#2 Warning Missing input or output delay An input delay is missing on cpld2fpga_ebi_nwe_0 relative to clock(s) osc125_a Related violations: TIMING-18#3 Warning Missing input or output delay An input delay is missing on cpld2fpga_gpio[0] relative to clock(s) osc125_a Related violations: TIMING-18#4 Warning Missing input or output delay An input delay is missing on cpld2fpga_gpio[1] relative to clock(s) osc125_a Related violations: TIMING-18#5 Warning Missing input or output delay An input delay is missing on cpld2fpga_gpio[2] relative to clock(s) osc125_a Related violations: TIMING-18#6 Warning Missing input or output delay An input delay is missing on cpld2fpga_gpio[3] relative to clock(s) osc125_a Related violations: TIMING-18#7 Warning Missing input or output delay An input delay is missing on fmc_l12_la_n[0] relative to clock(s) fabric_clk, rxWordclkl12_2, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_7, txWordclkl12_2, txWordclkl12_4, txWordclkl12_5, txWordclkl12_7 Related violations: TIMING-18#8 Warning Missing input or output delay An input delay is missing on fmc_l12_la_n[10] relative to clock(s) fabric_clk, rxWordclkl12_2, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_7, txWordclkl12_2, txWordclkl12_4, txWordclkl12_5, txWordclkl12_7 Related violations: TIMING-18#9 Warning Missing input or output delay An input delay is missing on fmc_l12_la_n[11] relative to clock(s) fabric_clk, rxWordclkl12_2, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_7, txWordclkl12_2, txWordclkl12_4, txWordclkl12_5, txWordclkl12_7 Related violations: TIMING-18#10 Warning Missing input or output delay An input delay is missing on fmc_l12_la_n[12] relative to clock(s) fabric_clk, rxWordclkl12_2, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_7, txWordclkl12_2, txWordclkl12_4, txWordclkl12_5, txWordclkl12_7 Related violations: TIMING-18#11 Warning Missing input or output delay An input delay is missing on fmc_l12_la_n[13] relative to clock(s) fabric_clk, rxWordclkl12_2, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_7, txWordclkl12_2, txWordclkl12_4, txWordclkl12_5, txWordclkl12_7 Related violations: TIMING-18#12 Warning Missing input or output delay An input delay is missing on fmc_l12_la_n[14] relative to clock(s) fabric_clk, rxWordclkl12_2, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_7, txWordclkl12_2, txWordclkl12_4, txWordclkl12_5, txWordclkl12_7 Related violations: TIMING-18#13 Warning Missing input or output delay An input delay is missing on fmc_l12_la_n[15] relative to clock(s) fabric_clk, rxWordclkl12_2, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_7, txWordclkl12_2, txWordclkl12_4, txWordclkl12_5, txWordclkl12_7 Related violations: TIMING-18#14 Warning Missing input or output delay An input delay is missing on fmc_l12_la_n[16] relative to clock(s) fabric_clk, rxWordclkl12_2, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_7, txWordclkl12_2, txWordclkl12_4, txWordclkl12_5, txWordclkl12_7 Related violations: TIMING-18#15 Warning Missing input or output delay An input delay is missing on fmc_l12_la_n[17] relative to clock(s) fabric_clk, rxWordclkl12_2, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_7, txWordclkl12_2, txWordclkl12_4, txWordclkl12_5, txWordclkl12_7 Related violations: TIMING-18#16 Warning Missing input or output delay An input delay is missing on fmc_l12_la_n[18] relative to clock(s) fabric_clk, rxWordclkl12_2, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_7, txWordclkl12_2, txWordclkl12_4, txWordclkl12_5, txWordclkl12_7 Related violations: TIMING-18#17 Warning Missing input or output delay An input delay is missing on fmc_l12_la_n[19] relative to clock(s) fabric_clk, rxWordclkl12_2, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_7, txWordclkl12_2, txWordclkl12_4, txWordclkl12_5, txWordclkl12_7 Related violations: TIMING-18#18 Warning Missing input or output delay An input delay is missing on fmc_l12_la_n[1] relative to clock(s) fabric_clk, rxWordclkl12_2, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_7, txWordclkl12_2, txWordclkl12_4, txWordclkl12_5, txWordclkl12_7 Related violations: TIMING-18#19 Warning Missing input or output delay An input delay is missing on fmc_l12_la_n[20] relative to clock(s) fabric_clk, rxWordclkl12_2, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_7, txWordclkl12_2, txWordclkl12_4, txWordclkl12_5, txWordclkl12_7 Related violations: TIMING-18#20 Warning Missing input or output delay An input delay is missing on fmc_l12_la_n[21] relative to clock(s) fabric_clk, rxWordclkl12_2, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_7, txWordclkl12_2, txWordclkl12_4, txWordclkl12_5, txWordclkl12_7 Related violations: TIMING-18#21 Warning Missing input or output delay An input delay is missing on fmc_l12_la_n[22] relative to clock(s) fabric_clk, rxWordclkl12_2, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_7, txWordclkl12_2, txWordclkl12_4, txWordclkl12_5, txWordclkl12_7 Related violations: TIMING-18#22 Warning Missing input or output delay An input delay is missing on fmc_l12_la_n[23] relative to clock(s) fabric_clk, rxWordclkl12_2, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_7, txWordclkl12_2, txWordclkl12_4, txWordclkl12_5, txWordclkl12_7 Related violations: TIMING-18#23 Warning Missing input or output delay An input delay is missing on fmc_l12_la_n[24] relative to clock(s) fabric_clk, rxWordclkl12_2, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_7, txWordclkl12_2, txWordclkl12_4, txWordclkl12_5, txWordclkl12_7 Related violations: TIMING-18#24 Warning Missing input or output delay An input delay is missing on fmc_l12_la_n[25] relative to clock(s) fabric_clk, rxWordclkl12_2, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_7, txWordclkl12_2, txWordclkl12_4, txWordclkl12_5, txWordclkl12_7 Related violations: TIMING-18#25 Warning Missing input or output delay An input delay is missing on fmc_l12_la_n[26] relative to clock(s) fabric_clk, rxWordclkl12_2, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_7, txWordclkl12_2, txWordclkl12_4, txWordclkl12_5, txWordclkl12_7 Related violations: TIMING-18#26 Warning Missing input or output delay An input delay is missing on fmc_l12_la_n[27] relative to clock(s) fabric_clk, rxWordclkl12_2, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_7, txWordclkl12_2, txWordclkl12_4, txWordclkl12_5, txWordclkl12_7 Related violations: TIMING-18#27 Warning Missing input or output delay An input delay is missing on fmc_l12_la_n[28] relative to clock(s) fabric_clk, rxWordclkl12_2, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_7, txWordclkl12_2, txWordclkl12_4, txWordclkl12_5, txWordclkl12_7 Related violations: TIMING-18#28 Warning Missing input or output delay An input delay is missing on fmc_l12_la_n[29] relative to clock(s) fabric_clk, rxWordclkl12_2, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_7, txWordclkl12_2, txWordclkl12_4, txWordclkl12_5, txWordclkl12_7 Related violations: TIMING-18#29 Warning Missing input or output delay An input delay is missing on fmc_l12_la_n[2] relative to clock(s) fabric_clk, rxWordclkl12_2, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_7, txWordclkl12_2, txWordclkl12_4, txWordclkl12_5, txWordclkl12_7 Related violations: TIMING-18#30 Warning Missing input or output delay An input delay is missing on fmc_l12_la_n[30] relative to clock(s) fabric_clk, rxWordclkl12_2, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_7, txWordclkl12_2, txWordclkl12_4, txWordclkl12_5, txWordclkl12_7 Related violations: TIMING-18#31 Warning Missing input or output delay An input delay is missing on fmc_l12_la_n[31] relative to clock(s) fabric_clk, rxWordclkl12_2, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_7, txWordclkl12_2, txWordclkl12_4, txWordclkl12_5, txWordclkl12_7 Related violations: TIMING-18#32 Warning Missing input or output delay An input delay is missing on fmc_l12_la_n[32] relative to clock(s) fabric_clk, rxWordclkl12_2, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_7, txWordclkl12_2, txWordclkl12_4, txWordclkl12_5, txWordclkl12_7 Related violations: TIMING-18#33 Warning Missing input or output delay An input delay is missing on fmc_l12_la_n[33] relative to clock(s) fabric_clk, rxWordclkl12_2, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_7, txWordclkl12_2, txWordclkl12_4, txWordclkl12_5, txWordclkl12_7 Related violations: TIMING-18#34 Warning Missing input or output delay An input delay is missing on fmc_l12_la_n[3] relative to clock(s) fabric_clk, rxWordclkl12_2, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_7, txWordclkl12_2, txWordclkl12_4, txWordclkl12_5, txWordclkl12_7 Related violations: TIMING-18#35 Warning Missing input or output delay An input delay is missing on fmc_l12_la_n[4] relative to clock(s) fabric_clk, rxWordclkl12_2, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_7, txWordclkl12_2, txWordclkl12_4, txWordclkl12_5, txWordclkl12_7 Related violations: TIMING-18#36 Warning Missing input or output delay An input delay is missing on fmc_l12_la_n[5] relative to clock(s) fabric_clk, rxWordclkl12_2, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_7, txWordclkl12_2, txWordclkl12_4, txWordclkl12_5, txWordclkl12_7 Related violations: TIMING-18#37 Warning Missing input or output delay An input delay is missing on fmc_l12_la_n[6] relative to clock(s) fabric_clk, rxWordclkl12_2, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_7, txWordclkl12_2, txWordclkl12_4, txWordclkl12_5, txWordclkl12_7 Related violations: TIMING-18#38 Warning Missing input or output delay An input delay is missing on fmc_l12_la_n[7] relative to clock(s) fabric_clk, rxWordclkl12_2, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_7, txWordclkl12_2, txWordclkl12_4, txWordclkl12_5, txWordclkl12_7 Related violations: TIMING-18#39 Warning Missing input or output delay An input delay is missing on fmc_l12_la_n[8] relative to clock(s) fabric_clk, rxWordclkl12_2, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_7, txWordclkl12_2, txWordclkl12_4, txWordclkl12_5, txWordclkl12_7 Related violations: TIMING-18#40 Warning Missing input or output delay An input delay is missing on fmc_l12_la_n[9] relative to clock(s) fabric_clk, rxWordclkl12_2, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_7, txWordclkl12_2, txWordclkl12_4, txWordclkl12_5, txWordclkl12_7 Related violations: TIMING-18#41 Warning Missing input or output delay An input delay is missing on fmc_l12_la_p[0] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_3, rxWordclkl12_6, rxWordclkl12_8, txWordclkl12_1, txWordclkl12_3, txWordclkl12_6, txWordclkl12_8 Related violations: TIMING-18#42 Warning Missing input or output delay An input delay is missing on fmc_l12_la_p[10] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_3, rxWordclkl12_6, rxWordclkl12_8, txWordclkl12_1, txWordclkl12_3, txWordclkl12_6, txWordclkl12_8 Related violations: TIMING-18#43 Warning Missing input or output delay An input delay is missing on fmc_l12_la_p[11] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_3, rxWordclkl12_6, rxWordclkl12_8, txWordclkl12_1, txWordclkl12_3, txWordclkl12_6, txWordclkl12_8 Related violations: TIMING-18#44 Warning Missing input or output delay An input delay is missing on fmc_l12_la_p[12] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_3, rxWordclkl12_6, rxWordclkl12_8, txWordclkl12_1, txWordclkl12_3, txWordclkl12_6, txWordclkl12_8 Related violations: TIMING-18#45 Warning Missing input or output delay An input delay is missing on fmc_l12_la_p[13] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_3, rxWordclkl12_6, rxWordclkl12_8, txWordclkl12_1, txWordclkl12_3, txWordclkl12_6, txWordclkl12_8 Related violations: TIMING-18#46 Warning Missing input or output delay An input delay is missing on fmc_l12_la_p[14] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_3, rxWordclkl12_6, rxWordclkl12_8, txWordclkl12_1, txWordclkl12_3, txWordclkl12_6, txWordclkl12_8 Related violations: TIMING-18#47 Warning Missing input or output delay An input delay is missing on fmc_l12_la_p[15] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_3, rxWordclkl12_6, rxWordclkl12_8, txWordclkl12_1, txWordclkl12_3, txWordclkl12_6, txWordclkl12_8 Related violations: TIMING-18#48 Warning Missing input or output delay An input delay is missing on fmc_l12_la_p[16] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_3, rxWordclkl12_6, rxWordclkl12_8, txWordclkl12_1, txWordclkl12_3, txWordclkl12_6, txWordclkl12_8 Related violations: TIMING-18#49 Warning Missing input or output delay An input delay is missing on fmc_l12_la_p[17] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_3, rxWordclkl12_6, rxWordclkl12_8, txWordclkl12_1, txWordclkl12_3, txWordclkl12_6, txWordclkl12_8 Related violations: TIMING-18#50 Warning Missing input or output delay An input delay is missing on fmc_l12_la_p[18] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_3, rxWordclkl12_6, rxWordclkl12_8, txWordclkl12_1, txWordclkl12_3, txWordclkl12_6, txWordclkl12_8 Related violations: TIMING-18#51 Warning Missing input or output delay An input delay is missing on fmc_l12_la_p[19] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_3, rxWordclkl12_6, rxWordclkl12_8, txWordclkl12_1, txWordclkl12_3, txWordclkl12_6, txWordclkl12_8 Related violations: TIMING-18#52 Warning Missing input or output delay An input delay is missing on fmc_l12_la_p[1] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_3, rxWordclkl12_6, rxWordclkl12_8, txWordclkl12_1, txWordclkl12_3, txWordclkl12_6, txWordclkl12_8 Related violations: TIMING-18#53 Warning Missing input or output delay An input delay is missing on fmc_l12_la_p[20] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_3, rxWordclkl12_6, rxWordclkl12_8, txWordclkl12_1, txWordclkl12_3, txWordclkl12_6, txWordclkl12_8 Related violations: TIMING-18#54 Warning Missing input or output delay An input delay is missing on fmc_l12_la_p[21] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_3, rxWordclkl12_6, rxWordclkl12_8, txWordclkl12_1, txWordclkl12_3, txWordclkl12_6, txWordclkl12_8 Related violations: TIMING-18#55 Warning Missing input or output delay An input delay is missing on fmc_l12_la_p[22] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_3, rxWordclkl12_6, rxWordclkl12_8, txWordclkl12_1, txWordclkl12_3, txWordclkl12_6, txWordclkl12_8 Related violations: TIMING-18#56 Warning Missing input or output delay An input delay is missing on fmc_l12_la_p[23] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_3, rxWordclkl12_6, rxWordclkl12_8, txWordclkl12_1, txWordclkl12_3, txWordclkl12_6, txWordclkl12_8 Related violations: TIMING-18#57 Warning Missing input or output delay An input delay is missing on fmc_l12_la_p[24] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_3, rxWordclkl12_6, rxWordclkl12_8, txWordclkl12_1, txWordclkl12_3, txWordclkl12_6, txWordclkl12_8 Related violations: TIMING-18#58 Warning Missing input or output delay An input delay is missing on fmc_l12_la_p[25] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_3, rxWordclkl12_6, rxWordclkl12_8, txWordclkl12_1, txWordclkl12_3, txWordclkl12_6, txWordclkl12_8 Related violations: TIMING-18#59 Warning Missing input or output delay An input delay is missing on fmc_l12_la_p[26] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_3, rxWordclkl12_6, rxWordclkl12_8, txWordclkl12_1, txWordclkl12_3, txWordclkl12_6, txWordclkl12_8 Related violations: TIMING-18#60 Warning Missing input or output delay An input delay is missing on fmc_l12_la_p[27] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_3, rxWordclkl12_6, rxWordclkl12_8, txWordclkl12_1, txWordclkl12_3, txWordclkl12_6, txWordclkl12_8 Related violations: TIMING-18#61 Warning Missing input or output delay An input delay is missing on fmc_l12_la_p[28] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_3, rxWordclkl12_6, rxWordclkl12_8, txWordclkl12_1, txWordclkl12_3, txWordclkl12_6, txWordclkl12_8 Related violations: TIMING-18#62 Warning Missing input or output delay An input delay is missing on fmc_l12_la_p[29] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_3, rxWordclkl12_6, rxWordclkl12_8, txWordclkl12_1, txWordclkl12_3, txWordclkl12_6, txWordclkl12_8 Related violations: TIMING-18#63 Warning Missing input or output delay An input delay is missing on fmc_l12_la_p[2] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_3, rxWordclkl12_6, rxWordclkl12_8, txWordclkl12_1, txWordclkl12_3, txWordclkl12_6, txWordclkl12_8 Related violations: TIMING-18#64 Warning Missing input or output delay An input delay is missing on fmc_l12_la_p[30] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_3, rxWordclkl12_6, rxWordclkl12_8, txWordclkl12_1, txWordclkl12_3, txWordclkl12_6, txWordclkl12_8 Related violations: TIMING-18#65 Warning Missing input or output delay An input delay is missing on fmc_l12_la_p[31] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_3, rxWordclkl12_6, rxWordclkl12_8, txWordclkl12_1, txWordclkl12_3, txWordclkl12_6, txWordclkl12_8 Related violations: TIMING-18#66 Warning Missing input or output delay An input delay is missing on fmc_l12_la_p[32] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_3, rxWordclkl12_6, rxWordclkl12_8, txWordclkl12_1, txWordclkl12_3, txWordclkl12_6, txWordclkl12_8 Related violations: TIMING-18#67 Warning Missing input or output delay An input delay is missing on fmc_l12_la_p[33] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_3, rxWordclkl12_6, rxWordclkl12_8, txWordclkl12_1, txWordclkl12_3, txWordclkl12_6, txWordclkl12_8 Related violations: TIMING-18#68 Warning Missing input or output delay An input delay is missing on fmc_l12_la_p[3] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_3, rxWordclkl12_6, rxWordclkl12_8, txWordclkl12_1, txWordclkl12_3, txWordclkl12_6, txWordclkl12_8 Related violations: TIMING-18#69 Warning Missing input or output delay An input delay is missing on fmc_l12_la_p[4] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_3, rxWordclkl12_6, rxWordclkl12_8, txWordclkl12_1, txWordclkl12_3, txWordclkl12_6, txWordclkl12_8 Related violations: TIMING-18#70 Warning Missing input or output delay An input delay is missing on fmc_l12_la_p[5] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_3, rxWordclkl12_6, rxWordclkl12_8, txWordclkl12_1, txWordclkl12_3, txWordclkl12_6, txWordclkl12_8 Related violations: TIMING-18#71 Warning Missing input or output delay An input delay is missing on fmc_l12_la_p[6] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_3, rxWordclkl12_6, rxWordclkl12_8, txWordclkl12_1, txWordclkl12_3, txWordclkl12_6, txWordclkl12_8 Related violations: TIMING-18#72 Warning Missing input or output delay An input delay is missing on fmc_l12_la_p[7] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_3, rxWordclkl12_6, rxWordclkl12_8, txWordclkl12_1, txWordclkl12_3, txWordclkl12_6, txWordclkl12_8 Related violations: TIMING-18#73 Warning Missing input or output delay An input delay is missing on fmc_l12_la_p[8] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_3, rxWordclkl12_6, rxWordclkl12_8, txWordclkl12_1, txWordclkl12_3, txWordclkl12_6, txWordclkl12_8 Related violations: TIMING-18#74 Warning Missing input or output delay An input delay is missing on fmc_l12_la_p[9] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_3, rxWordclkl12_6, rxWordclkl12_8, txWordclkl12_1, txWordclkl12_3, txWordclkl12_6, txWordclkl12_8 Related violations: TIMING-18#75 Warning Missing input or output delay An input delay is missing on fmc_l12_pg_m2c relative to clock(s) fabric_clk Related violations: TIMING-18#76 Warning Missing input or output delay An input delay is missing on fmc_l12_spare[10] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_2, rxWordclkl12_3, rxWordclkl12_4, rxWordclkl8_1, rxWordclkl8_2, rxWordclkl8_3, rxWordclkl8_4, ttc_mgt_xpoint_c Related violations: TIMING-18#77 Warning Missing input or output delay An input delay is missing on fmc_l12_spare[11] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_2, rxWordclkl12_3, rxWordclkl12_4, rxWordclkl8_1, rxWordclkl8_2, rxWordclkl8_3, rxWordclkl8_4, ttc_mgt_xpoint_c Related violations: TIMING-18#78 Warning Missing input or output delay An input delay is missing on fmc_l12_spare[12] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_2, rxWordclkl12_3, rxWordclkl12_4, rxWordclkl8_1, rxWordclkl8_2, rxWordclkl8_3, rxWordclkl8_4, ttc_mgt_xpoint_c Related violations: TIMING-18#79 Warning Missing input or output delay An input delay is missing on fmc_l12_spare[13] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_2, rxWordclkl12_3, rxWordclkl12_4, rxWordclkl8_1, rxWordclkl8_2, rxWordclkl8_3, rxWordclkl8_4, ttc_mgt_xpoint_c Related violations: TIMING-18#80 Warning Missing input or output delay An input delay is missing on fmc_l12_spare[6] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_2, rxWordclkl12_3, rxWordclkl12_4, rxWordclkl8_1, rxWordclkl8_2, rxWordclkl8_3, rxWordclkl8_4, ttc_mgt_xpoint_c Related violations: TIMING-18#81 Warning Missing input or output delay An input delay is missing on fmc_l12_spare[7] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_2, rxWordclkl12_3, rxWordclkl12_4, rxWordclkl8_1, rxWordclkl8_2, rxWordclkl8_3, rxWordclkl8_4, ttc_mgt_xpoint_c Related violations: TIMING-18#82 Warning Missing input or output delay An input delay is missing on fmc_l12_spare[8] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_2, rxWordclkl12_3, rxWordclkl12_4, rxWordclkl8_1, rxWordclkl8_2, rxWordclkl8_3, rxWordclkl8_4, ttc_mgt_xpoint_c Related violations: TIMING-18#83 Warning Missing input or output delay An input delay is missing on fmc_l12_spare[9] relative to clock(s) fabric_clk, rxWordclkl12_1, rxWordclkl12_2, rxWordclkl12_3, rxWordclkl12_4, rxWordclkl8_1, rxWordclkl8_2, rxWordclkl8_3, rxWordclkl8_4, ttc_mgt_xpoint_c Related violations: TIMING-18#84 Warning Missing input or output delay An input delay is missing on fmc_l8_la_n[0] relative to clock(s) fabric_clk, rxWordclkl8_1, rxWordclkl8_3, txWordclkl8_1, txWordclkl8_3 Related violations: TIMING-18#85 Warning Missing input or output delay An input delay is missing on fmc_l8_la_n[10] relative to clock(s) fabric_clk, rxWordclkl8_1, rxWordclkl8_3, txWordclkl8_1, txWordclkl8_3 Related violations: TIMING-18#86 Warning Missing input or output delay An input delay is missing on fmc_l8_la_n[11] relative to clock(s) fabric_clk, rxWordclkl8_1, rxWordclkl8_3, txWordclkl8_1, txWordclkl8_3 Related violations: TIMING-18#87 Warning Missing input or output delay An input delay is missing on fmc_l8_la_n[12] relative to clock(s) fabric_clk, rxWordclkl8_1, rxWordclkl8_3, txWordclkl8_1, txWordclkl8_3 Related violations: TIMING-18#88 Warning Missing input or output delay An input delay is missing on fmc_l8_la_n[13] relative to clock(s) fabric_clk, rxWordclkl8_1, rxWordclkl8_3, txWordclkl8_1, txWordclkl8_3 Related violations: TIMING-18#89 Warning Missing input or output delay An input delay is missing on fmc_l8_la_n[14] relative to clock(s) fabric_clk, rxWordclkl8_1, rxWordclkl8_3, txWordclkl8_1, txWordclkl8_3 Related violations: TIMING-18#90 Warning Missing input or output delay An input delay is missing on fmc_l8_la_n[15] relative to clock(s) fabric_clk, rxWordclkl8_1, rxWordclkl8_3, txWordclkl8_1, txWordclkl8_3 Related violations: TIMING-18#91 Warning Missing input or output delay An input delay is missing on fmc_l8_la_n[16] relative to clock(s) fabric_clk, rxWordclkl8_1, rxWordclkl8_3, txWordclkl8_1, txWordclkl8_3 Related violations: TIMING-18#92 Warning Missing input or output delay An input delay is missing on fmc_l8_la_n[17] relative to clock(s) fabric_clk, rxWordclkl8_1, rxWordclkl8_3, txWordclkl8_1, txWordclkl8_3 Related violations: TIMING-18#93 Warning Missing input or output delay An input delay is missing on fmc_l8_la_n[18] relative to clock(s) fabric_clk, rxWordclkl8_1, rxWordclkl8_3, txWordclkl8_1, txWordclkl8_3 Related violations: TIMING-18#94 Warning Missing input or output delay An input delay is missing on fmc_l8_la_n[19] relative to clock(s) fabric_clk, rxWordclkl8_1, rxWordclkl8_3, txWordclkl8_1, txWordclkl8_3 Related violations: TIMING-18#95 Warning Missing input or output delay An input delay is missing on fmc_l8_la_n[1] relative to clock(s) fabric_clk, rxWordclkl8_1, rxWordclkl8_3, txWordclkl8_1, txWordclkl8_3 Related violations: TIMING-18#96 Warning Missing input or output delay An input delay is missing on fmc_l8_la_n[20] relative to clock(s) fabric_clk, rxWordclkl8_1, rxWordclkl8_3, txWordclkl8_1, txWordclkl8_3 Related violations: TIMING-18#97 Warning Missing input or output delay An input delay is missing on fmc_l8_la_n[21] relative to clock(s) fabric_clk, rxWordclkl8_1, rxWordclkl8_3, txWordclkl8_1, txWordclkl8_3 Related violations: TIMING-18#98 Warning Missing input or output delay An input delay is missing on fmc_l8_la_n[22] relative to clock(s) fabric_clk, rxWordclkl8_1, rxWordclkl8_3, txWordclkl8_1, txWordclkl8_3 Related violations: TIMING-18#99 Warning Missing input or output delay An input delay is missing on fmc_l8_la_n[23] relative to clock(s) fabric_clk, rxWordclkl8_1, rxWordclkl8_3, txWordclkl8_1, txWordclkl8_3 Related violations: TIMING-18#100 Warning Missing input or output delay An input delay is missing on fmc_l8_la_n[24] relative to clock(s) fabric_clk, rxWordclkl8_1, rxWordclkl8_3, txWordclkl8_1, txWordclkl8_3 Related violations: TIMING-18#101 Warning Missing input or output delay An input delay is missing on fmc_l8_la_n[25] relative to clock(s) fabric_clk, rxWordclkl8_1, rxWordclkl8_3, txWordclkl8_1, txWordclkl8_3 Related violations: TIMING-18#102 Warning Missing input or output delay An input delay is missing on fmc_l8_la_n[26] relative to clock(s) fabric_clk, rxWordclkl8_1, rxWordclkl8_3, txWordclkl8_1, txWordclkl8_3 Related violations: TIMING-18#103 Warning Missing input or output delay An input delay is missing on fmc_l8_la_n[27] relative to clock(s) fabric_clk, rxWordclkl8_1, rxWordclkl8_3, txWordclkl8_1, txWordclkl8_3 Related violations: TIMING-18#104 Warning Missing input or output delay An input delay is missing on fmc_l8_la_n[28] relative to clock(s) fabric_clk, rxWordclkl8_1, rxWordclkl8_3, txWordclkl8_1, txWordclkl8_3 Related violations: TIMING-18#105 Warning Missing input or output delay An input delay is missing on fmc_l8_la_n[29] relative to clock(s) fabric_clk, rxWordclkl8_1, rxWordclkl8_3, txWordclkl8_1, txWordclkl8_3 Related violations: TIMING-18#106 Warning Missing input or output delay An input delay is missing on fmc_l8_la_n[2] relative to clock(s) fabric_clk, rxWordclkl8_1, rxWordclkl8_3, txWordclkl8_1, txWordclkl8_3 Related violations: TIMING-18#107 Warning Missing input or output delay An input delay is missing on fmc_l8_la_n[30] relative to clock(s) fabric_clk, rxWordclkl8_1, rxWordclkl8_3, txWordclkl8_1, txWordclkl8_3 Related violations: TIMING-18#108 Warning Missing input or output delay An input delay is missing on fmc_l8_la_n[31] relative to clock(s) fabric_clk, rxWordclkl8_1, rxWordclkl8_3, txWordclkl8_1, txWordclkl8_3 Related violations: TIMING-18#109 Warning Missing input or output delay An input delay is missing on fmc_l8_la_n[32] relative to clock(s) fabric_clk, rxWordclkl8_1, rxWordclkl8_3, txWordclkl8_1, txWordclkl8_3 Related violations: TIMING-18#110 Warning Missing input or output delay An input delay is missing on fmc_l8_la_n[33] relative to clock(s) fabric_clk, rxWordclkl8_1, rxWordclkl8_3, txWordclkl8_1, txWordclkl8_3 Related violations: TIMING-18#111 Warning Missing input or output delay An input delay is missing on fmc_l8_la_n[3] relative to clock(s) fabric_clk, rxWordclkl8_1, rxWordclkl8_3, txWordclkl8_1, txWordclkl8_3 Related violations: TIMING-18#112 Warning Missing input or output delay An input delay is missing on fmc_l8_la_n[4] relative to clock(s) fabric_clk, rxWordclkl8_1, rxWordclkl8_3, txWordclkl8_1, txWordclkl8_3 Related violations: TIMING-18#113 Warning Missing input or output delay An input delay is missing on fmc_l8_la_n[5] relative to clock(s) fabric_clk, rxWordclkl8_1, rxWordclkl8_3, txWordclkl8_1, txWordclkl8_3 Related violations: TIMING-18#114 Warning Missing input or output delay An input delay is missing on fmc_l8_la_n[6] relative to clock(s) fabric_clk, rxWordclkl8_1, rxWordclkl8_3, txWordclkl8_1, txWordclkl8_3 Related violations: TIMING-18#115 Warning Missing input or output delay An input delay is missing on fmc_l8_la_n[7] relative to clock(s) fabric_clk, rxWordclkl8_1, rxWordclkl8_3, txWordclkl8_1, txWordclkl8_3 Related violations: TIMING-18#116 Warning Missing input or output delay An input delay is missing on fmc_l8_la_n[8] relative to clock(s) fabric_clk, rxWordclkl8_1, rxWordclkl8_3, txWordclkl8_1, txWordclkl8_3 Related violations: TIMING-18#117 Warning Missing input or output delay An input delay is missing on fmc_l8_la_n[9] relative to clock(s) fabric_clk, rxWordclkl8_1, rxWordclkl8_3, txWordclkl8_1, txWordclkl8_3 Related violations: TIMING-18#118 Warning Missing input or output delay An input delay is missing on fmc_l8_la_p[0] relative to clock(s) fabric_clk, rxWordclkl8_2, rxWordclkl8_4, txWordclkl8_2, txWordclkl8_4 Related violations: TIMING-18#119 Warning Missing input or output delay An input delay is missing on fmc_l8_la_p[10] relative to clock(s) fabric_clk, rxWordclkl8_2, rxWordclkl8_4, txWordclkl8_2, txWordclkl8_4 Related violations: TIMING-18#120 Warning Missing input or output delay An input delay is missing on fmc_l8_la_p[11] relative to clock(s) fabric_clk, rxWordclkl8_2, rxWordclkl8_4, txWordclkl8_2, txWordclkl8_4 Related violations: TIMING-18#121 Warning Missing input or output delay An input delay is missing on fmc_l8_la_p[12] relative to clock(s) fabric_clk, rxWordclkl8_2, rxWordclkl8_4, txWordclkl8_2, txWordclkl8_4 Related violations: TIMING-18#122 Warning Missing input or output delay An input delay is missing on fmc_l8_la_p[13] relative to clock(s) fabric_clk, rxWordclkl8_2, rxWordclkl8_4, txWordclkl8_2, txWordclkl8_4 Related violations: TIMING-18#123 Warning Missing input or output delay An input delay is missing on fmc_l8_la_p[14] relative to clock(s) fabric_clk, rxWordclkl8_2, rxWordclkl8_4, txWordclkl8_2, txWordclkl8_4 Related violations: TIMING-18#124 Warning Missing input or output delay An input delay is missing on fmc_l8_la_p[15] relative to clock(s) fabric_clk, rxWordclkl8_2, rxWordclkl8_4, txWordclkl8_2, txWordclkl8_4 Related violations: TIMING-18#125 Warning Missing input or output delay An input delay is missing on fmc_l8_la_p[16] relative to clock(s) fabric_clk, rxWordclkl8_2, rxWordclkl8_4, txWordclkl8_2, txWordclkl8_4 Related violations: TIMING-18#126 Warning Missing input or output delay An input delay is missing on fmc_l8_la_p[17] relative to clock(s) fabric_clk, rxWordclkl8_2, rxWordclkl8_4, txWordclkl8_2, txWordclkl8_4 Related violations: TIMING-18#127 Warning Missing input or output delay An input delay is missing on fmc_l8_la_p[18] relative to clock(s) fabric_clk, rxWordclkl8_2, rxWordclkl8_4, txWordclkl8_2, txWordclkl8_4 Related violations: TIMING-18#128 Warning Missing input or output delay An input delay is missing on fmc_l8_la_p[19] relative to clock(s) fabric_clk, rxWordclkl8_2, rxWordclkl8_4, txWordclkl8_2, txWordclkl8_4 Related violations: TIMING-18#129 Warning Missing input or output delay An input delay is missing on fmc_l8_la_p[1] relative to clock(s) fabric_clk, rxWordclkl8_2, rxWordclkl8_4, txWordclkl8_2, txWordclkl8_4 Related violations: TIMING-18#130 Warning Missing input or output delay An input delay is missing on fmc_l8_la_p[20] relative to clock(s) fabric_clk, rxWordclkl8_2, rxWordclkl8_4, txWordclkl8_2, txWordclkl8_4 Related violations: TIMING-18#131 Warning Missing input or output delay An input delay is missing on fmc_l8_la_p[21] relative to clock(s) fabric_clk, rxWordclkl8_2, rxWordclkl8_4, txWordclkl8_2, txWordclkl8_4 Related violations: TIMING-18#132 Warning Missing input or output delay An input delay is missing on fmc_l8_la_p[22] relative to clock(s) fabric_clk, rxWordclkl8_2, rxWordclkl8_4, txWordclkl8_2, txWordclkl8_4 Related violations: TIMING-18#133 Warning Missing input or output delay An input delay is missing on fmc_l8_la_p[23] relative to clock(s) fabric_clk, rxWordclkl8_2, rxWordclkl8_4, txWordclkl8_2, txWordclkl8_4 Related violations: TIMING-18#134 Warning Missing input or output delay An input delay is missing on fmc_l8_la_p[24] relative to clock(s) fabric_clk, rxWordclkl8_2, rxWordclkl8_4, txWordclkl8_2, txWordclkl8_4 Related violations: TIMING-18#135 Warning Missing input or output delay An input delay is missing on fmc_l8_la_p[25] relative to clock(s) fabric_clk, rxWordclkl8_2, rxWordclkl8_4, txWordclkl8_2, txWordclkl8_4 Related violations: TIMING-18#136 Warning Missing input or output delay An input delay is missing on fmc_l8_la_p[26] relative to clock(s) fabric_clk, rxWordclkl8_2, rxWordclkl8_4, txWordclkl8_2, txWordclkl8_4 Related violations: TIMING-18#137 Warning Missing input or output delay An input delay is missing on fmc_l8_la_p[27] relative to clock(s) fabric_clk, rxWordclkl8_2, rxWordclkl8_4, txWordclkl8_2, txWordclkl8_4 Related violations: TIMING-18#138 Warning Missing input or output delay An input delay is missing on fmc_l8_la_p[28] relative to clock(s) fabric_clk, rxWordclkl8_2, rxWordclkl8_4, txWordclkl8_2, txWordclkl8_4 Related violations: TIMING-18#139 Warning Missing input or output delay An input delay is missing on fmc_l8_la_p[29] relative to clock(s) fabric_clk, rxWordclkl8_2, rxWordclkl8_4, txWordclkl8_2, txWordclkl8_4 Related violations: TIMING-18#140 Warning Missing input or output delay An input delay is missing on fmc_l8_la_p[2] relative to clock(s) fabric_clk, rxWordclkl8_2, rxWordclkl8_4, txWordclkl8_2, txWordclkl8_4 Related violations: TIMING-18#141 Warning Missing input or output delay An input delay is missing on fmc_l8_la_p[30] relative to clock(s) fabric_clk, rxWordclkl8_2, rxWordclkl8_4, txWordclkl8_2, txWordclkl8_4 Related violations: TIMING-18#142 Warning Missing input or output delay An input delay is missing on fmc_l8_la_p[31] relative to clock(s) fabric_clk, rxWordclkl8_2, rxWordclkl8_4, txWordclkl8_2, txWordclkl8_4 Related violations: TIMING-18#143 Warning Missing input or output delay An input delay is missing on fmc_l8_la_p[32] relative to clock(s) fabric_clk, rxWordclkl8_2, rxWordclkl8_4, txWordclkl8_2, txWordclkl8_4 Related violations: TIMING-18#144 Warning Missing input or output delay An input delay is missing on fmc_l8_la_p[33] relative to clock(s) fabric_clk, rxWordclkl8_2, rxWordclkl8_4, txWordclkl8_2, txWordclkl8_4 Related violations: TIMING-18#145 Warning Missing input or output delay An input delay is missing on fmc_l8_la_p[3] relative to clock(s) fabric_clk, rxWordclkl8_2, rxWordclkl8_4, txWordclkl8_2, txWordclkl8_4 Related violations: TIMING-18#146 Warning Missing input or output delay An input delay is missing on fmc_l8_la_p[4] relative to clock(s) fabric_clk, rxWordclkl8_2, rxWordclkl8_4, txWordclkl8_2, txWordclkl8_4 Related violations: TIMING-18#147 Warning Missing input or output delay An input delay is missing on fmc_l8_la_p[5] relative to clock(s) fabric_clk, rxWordclkl8_2, rxWordclkl8_4, txWordclkl8_2, txWordclkl8_4 Related violations: TIMING-18#148 Warning Missing input or output delay An input delay is missing on fmc_l8_la_p[6] relative to clock(s) fabric_clk, rxWordclkl8_2, rxWordclkl8_4, txWordclkl8_2, txWordclkl8_4 Related violations: TIMING-18#149 Warning Missing input or output delay An input delay is missing on fmc_l8_la_p[7] relative to clock(s) fabric_clk, rxWordclkl8_2, rxWordclkl8_4, txWordclkl8_2, txWordclkl8_4 Related violations: TIMING-18#150 Warning Missing input or output delay An input delay is missing on fmc_l8_la_p[8] relative to clock(s) fabric_clk, rxWordclkl8_2, rxWordclkl8_4, txWordclkl8_2, txWordclkl8_4 Related violations: TIMING-18#151 Warning Missing input or output delay An input delay is missing on fmc_l8_la_p[9] relative to clock(s) fabric_clk, rxWordclkl8_2, rxWordclkl8_4, txWordclkl8_2, txWordclkl8_4 Related violations: TIMING-18#152 Warning Missing input or output delay An input delay is missing on fmc_l8_pg_m2c relative to clock(s) fabric_clk Related violations: TIMING-18#153 Warning Missing input or output delay An input delay is missing on fmc_l8_spare[0] relative to clock(s) clk_o_39_997, fabric_clk, rxWordclkl12_1, rxWordclkl12_2, rxWordclkl12_3, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_6, rxWordclkl12_7, rxWordclkl12_8, rxWordclkl8_1, rxWordclkl8_2, rxWordclkl8_3, rxWordclkl8_4, ttc_mgt_xpoint_c Related violations: TIMING-18#154 Warning Missing input or output delay An input delay is missing on fmc_l8_spare[10] relative to clock(s) clk_o_39_997, fabric_clk, rxWordclkl12_1, rxWordclkl12_2, rxWordclkl12_3, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_6, rxWordclkl12_7, rxWordclkl12_8, rxWordclkl8_1, rxWordclkl8_2, rxWordclkl8_3, rxWordclkl8_4, ttc_mgt_xpoint_c Related violations: TIMING-18#155 Warning Missing input or output delay An input delay is missing on fmc_l8_spare[11] relative to clock(s) clk_o_39_997, fabric_clk, rxWordclkl12_1, rxWordclkl12_2, rxWordclkl12_3, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_6, rxWordclkl12_7, rxWordclkl12_8, rxWordclkl8_1, rxWordclkl8_2, rxWordclkl8_3, rxWordclkl8_4, ttc_mgt_xpoint_c Related violations: TIMING-18#156 Warning Missing input or output delay An input delay is missing on fmc_l8_spare[12] relative to clock(s) clk_o_39_997, fabric_clk, rxWordclkl12_1, rxWordclkl12_2, rxWordclkl12_3, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_6, rxWordclkl12_7, rxWordclkl12_8, rxWordclkl8_1, rxWordclkl8_2, rxWordclkl8_3, rxWordclkl8_4, ttc_mgt_xpoint_c Related violations: TIMING-18#157 Warning Missing input or output delay An input delay is missing on fmc_l8_spare[13] relative to clock(s) clk_o_39_997, fabric_clk, rxWordclkl12_1, rxWordclkl12_2, rxWordclkl12_3, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_6, rxWordclkl12_7, rxWordclkl12_8, rxWordclkl8_1, rxWordclkl8_2, rxWordclkl8_3, rxWordclkl8_4, ttc_mgt_xpoint_c Related violations: TIMING-18#158 Warning Missing input or output delay An input delay is missing on fmc_l8_spare[14] relative to clock(s) clk_o_39_997, fabric_clk, rxWordclkl12_1, rxWordclkl12_2, rxWordclkl12_3, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_6, rxWordclkl12_7, rxWordclkl12_8, rxWordclkl8_1, rxWordclkl8_2, rxWordclkl8_3, rxWordclkl8_4, ttc_mgt_xpoint_c Related violations: TIMING-18#159 Warning Missing input or output delay An input delay is missing on fmc_l8_spare[15] relative to clock(s) clk_o_39_997, fabric_clk, rxWordclkl12_1, rxWordclkl12_2, rxWordclkl12_3, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_6, rxWordclkl12_7, rxWordclkl12_8, rxWordclkl8_1, rxWordclkl8_2, rxWordclkl8_3, rxWordclkl8_4, ttc_mgt_xpoint_c Related violations: TIMING-18#160 Warning Missing input or output delay An input delay is missing on fmc_l8_spare[16] relative to clock(s) clk_o_39_997, fabric_clk, rxWordclkl12_1, rxWordclkl12_2, rxWordclkl12_3, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_6, rxWordclkl12_7, rxWordclkl12_8, rxWordclkl8_1, rxWordclkl8_2, rxWordclkl8_3, rxWordclkl8_4, ttc_mgt_xpoint_c Related violations: TIMING-18#161 Warning Missing input or output delay An input delay is missing on fmc_l8_spare[17] relative to clock(s) clk_o_39_997, fabric_clk, rxWordclkl12_1, rxWordclkl12_2, rxWordclkl12_3, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_6, rxWordclkl12_7, rxWordclkl12_8, rxWordclkl8_1, rxWordclkl8_2, rxWordclkl8_3, rxWordclkl8_4, ttc_mgt_xpoint_c Related violations: TIMING-18#162 Warning Missing input or output delay An input delay is missing on fmc_l8_spare[18] relative to clock(s) clk_o_39_997, fabric_clk, rxWordclkl12_1, rxWordclkl12_2, rxWordclkl12_3, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_6, rxWordclkl12_7, rxWordclkl12_8, rxWordclkl8_1, rxWordclkl8_2, rxWordclkl8_3, rxWordclkl8_4, ttc_mgt_xpoint_c Related violations: TIMING-18#163 Warning Missing input or output delay An input delay is missing on fmc_l8_spare[19] relative to clock(s) clk_o_39_997, fabric_clk, rxWordclkl12_1, rxWordclkl12_2, rxWordclkl12_3, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_6, rxWordclkl12_7, rxWordclkl12_8, rxWordclkl8_1, rxWordclkl8_2, rxWordclkl8_3, rxWordclkl8_4, ttc_mgt_xpoint_c Related violations: TIMING-18#164 Warning Missing input or output delay An input delay is missing on fmc_l8_spare[1] relative to clock(s) clk_o_39_997, fabric_clk, rxWordclkl12_1, rxWordclkl12_2, rxWordclkl12_3, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_6, rxWordclkl12_7, rxWordclkl12_8, rxWordclkl8_1, rxWordclkl8_2, rxWordclkl8_3, rxWordclkl8_4, ttc_mgt_xpoint_c Related violations: TIMING-18#165 Warning Missing input or output delay An input delay is missing on fmc_l8_spare[2] relative to clock(s) clk_o_39_997, fabric_clk, rxWordclkl12_1, rxWordclkl12_2, rxWordclkl12_3, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_6, rxWordclkl12_7, rxWordclkl12_8, rxWordclkl8_1, rxWordclkl8_2, rxWordclkl8_3, rxWordclkl8_4, ttc_mgt_xpoint_c Related violations: TIMING-18#166 Warning Missing input or output delay An input delay is missing on fmc_l8_spare[3] relative to clock(s) clk_o_39_997, fabric_clk, rxWordclkl12_1, rxWordclkl12_2, rxWordclkl12_3, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_6, rxWordclkl12_7, rxWordclkl12_8, rxWordclkl8_1, rxWordclkl8_2, rxWordclkl8_3, rxWordclkl8_4, ttc_mgt_xpoint_c Related violations: TIMING-18#167 Warning Missing input or output delay An input delay is missing on fmc_l8_spare[4] relative to clock(s) clk_o_39_997, fabric_clk, rxWordclkl12_1, rxWordclkl12_2, rxWordclkl12_3, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_6, rxWordclkl12_7, rxWordclkl12_8, rxWordclkl8_1, rxWordclkl8_2, rxWordclkl8_3, rxWordclkl8_4, ttc_mgt_xpoint_c Related violations: TIMING-18#168 Warning Missing input or output delay An input delay is missing on fmc_l8_spare[5] relative to clock(s) clk_o_39_997, fabric_clk, rxWordclkl12_1, rxWordclkl12_2, rxWordclkl12_3, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_6, rxWordclkl12_7, rxWordclkl12_8, rxWordclkl8_1, rxWordclkl8_2, rxWordclkl8_3, rxWordclkl8_4, ttc_mgt_xpoint_c Related violations: TIMING-18#169 Warning Missing input or output delay An input delay is missing on fmc_l8_spare[6] relative to clock(s) clk_o_39_997, fabric_clk, rxWordclkl12_1, rxWordclkl12_2, rxWordclkl12_3, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_6, rxWordclkl12_7, rxWordclkl12_8, rxWordclkl8_1, rxWordclkl8_2, rxWordclkl8_3, rxWordclkl8_4, ttc_mgt_xpoint_c Related violations: TIMING-18#170 Warning Missing input or output delay An input delay is missing on fmc_l8_spare[7] relative to clock(s) clk_o_39_997, fabric_clk, rxWordclkl12_1, rxWordclkl12_2, rxWordclkl12_3, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_6, rxWordclkl12_7, rxWordclkl12_8, rxWordclkl8_1, rxWordclkl8_2, rxWordclkl8_3, rxWordclkl8_4, ttc_mgt_xpoint_c Related violations: TIMING-18#171 Warning Missing input or output delay An input delay is missing on fmc_l8_spare[8] relative to clock(s) clk_o_39_997, fabric_clk, rxWordclkl12_1, rxWordclkl12_2, rxWordclkl12_3, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_6, rxWordclkl12_7, rxWordclkl12_8, rxWordclkl8_1, rxWordclkl8_2, rxWordclkl8_3, rxWordclkl8_4, ttc_mgt_xpoint_c Related violations: TIMING-18#172 Warning Missing input or output delay An input delay is missing on fmc_l8_spare[9] relative to clock(s) clk_o_39_997, fabric_clk, rxWordclkl12_1, rxWordclkl12_2, rxWordclkl12_3, rxWordclkl12_4, rxWordclkl12_5, rxWordclkl12_6, rxWordclkl12_7, rxWordclkl12_8, rxWordclkl8_1, rxWordclkl8_2, rxWordclkl8_3, rxWordclkl8_4, ttc_mgt_xpoint_c Related violations: TIMING-18#173 Warning Missing input or output delay An input delay is missing on fpga_config_data[0] relative to clock(s) osc125_a Related violations: TIMING-18#174 Warning Missing input or output delay An input delay is missing on fpga_config_data[10] relative to clock(s) osc125_a Related violations: TIMING-18#175 Warning Missing input or output delay An input delay is missing on fpga_config_data[11] relative to clock(s) osc125_a Related violations: TIMING-18#176 Warning Missing input or output delay An input delay is missing on fpga_config_data[12] relative to clock(s) osc125_a Related violations: TIMING-18#177 Warning Missing input or output delay An input delay is missing on fpga_config_data[13] relative to clock(s) osc125_a Related violations: TIMING-18#178 Warning Missing input or output delay An input delay is missing on fpga_config_data[14] relative to clock(s) osc125_a Related violations: TIMING-18#179 Warning Missing input or output delay An input delay is missing on fpga_config_data[15] relative to clock(s) osc125_a Related violations: TIMING-18#180 Warning Missing input or output delay An input delay is missing on fpga_config_data[1] relative to clock(s) osc125_a Related violations: TIMING-18#181 Warning Missing input or output delay An input delay is missing on fpga_config_data[2] relative to clock(s) osc125_a Related violations: TIMING-18#182 Warning Missing input or output delay An input delay is missing on fpga_config_data[3] relative to clock(s) osc125_a Related violations: TIMING-18#183 Warning Missing input or output delay An input delay is missing on fpga_config_data[4] relative to clock(s) osc125_a Related violations: TIMING-18#184 Warning Missing input or output delay An input delay is missing on fpga_config_data[5] relative to clock(s) osc125_a Related violations: TIMING-18#185 Warning Missing input or output delay An input delay is missing on fpga_config_data[6] relative to clock(s) osc125_a Related violations: TIMING-18#186 Warning Missing input or output delay An input delay is missing on fpga_config_data[7] relative to clock(s) osc125_a Related violations: TIMING-18#187 Warning Missing input or output delay An input delay is missing on fpga_config_data[8] relative to clock(s) osc125_a Related violations: TIMING-18#188 Warning Missing input or output delay An input delay is missing on fpga_config_data[9] relative to clock(s) osc125_a Related violations: TIMING-18#189 Warning Missing input or output delay An input delay is missing on k7_fabric_amc_rx_n03 relative to clock(s) fabric_clk Related violations: TIMING-18#190 Warning Missing input or output delay An input delay is missing on k7_fabric_amc_rx_p03 relative to clock(s) fabric_clk Related violations: TIMING-18#191 Warning Missing input or output delay An output delay is missing on cdce_sync_r1 relative to clock(s) fabric_clk Related violations: TIMING-18#192 Warning Missing input or output delay An output delay is missing on sysled1_b relative to clock(s) osc125_a Related violations: TIMING-18#193 Warning Missing input or output delay An output delay is missing on sysled1_r relative to clock(s) osc125_a Related violations: TIMING-20#1 Warning Non-clocked latch The latch ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_bridge_tck_i_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_bridge_tck_i_reg/G is not reached by a timing clock Related violations: TIMING-20#2 Warning Non-clocked latch The latch ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_bridge_tdo_i_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_bridge_tdo_i_reg/G is not reached by a timing clock Related violations: TIMING-20#3 Warning Non-clocked latch The latch ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_tck_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_tck_o_reg/G is not reached by a timing clock Related violations: TIMING-20#4 Warning Non-clocked latch The latch ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_tdi_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_tdi_o_reg/G is not reached by a timing clock Related violations: TIMING-20#5 Warning Non-clocked latch The latch ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_tms_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_tms_o_reg/G is not reached by a timing clock Related violations: TIMING-20#6 Warning Non-clocked latch The latch ngFEC/SFP_GEN[10].ngCCM_gbt/sec_jtag_tdi_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[10].ngCCM_gbt/sec_jtag_tdi_o_reg/G is not reached by a timing clock Related violations: TIMING-20#7 Warning Non-clocked latch The latch ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_bridge_tck_i_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_bridge_tck_i_reg/G is not reached by a timing clock Related violations: TIMING-20#8 Warning Non-clocked latch The latch ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_bridge_tdo_i_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_bridge_tdo_i_reg/G is not reached by a timing clock Related violations: TIMING-20#9 Warning Non-clocked latch The latch ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_tck_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_tck_o_reg/G is not reached by a timing clock Related violations: TIMING-20#10 Warning Non-clocked latch The latch ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_tdi_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_tdi_o_reg/G is not reached by a timing clock Related violations: TIMING-20#11 Warning Non-clocked latch The latch ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_tms_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_tms_o_reg/G is not reached by a timing clock Related violations: TIMING-20#12 Warning Non-clocked latch The latch ngFEC/SFP_GEN[11].ngCCM_gbt/sec_jtag_tdi_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[11].ngCCM_gbt/sec_jtag_tdi_o_reg/G is not reached by a timing clock Related violations: TIMING-20#13 Warning Non-clocked latch The latch ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_bridge_tck_i_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_bridge_tck_i_reg/G is not reached by a timing clock Related violations: TIMING-20#14 Warning Non-clocked latch The latch ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_bridge_tdo_i_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_bridge_tdo_i_reg/G is not reached by a timing clock Related violations: TIMING-20#15 Warning Non-clocked latch The latch ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_tck_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_tck_o_reg/G is not reached by a timing clock Related violations: TIMING-20#16 Warning Non-clocked latch The latch ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_tdi_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_tdi_o_reg/G is not reached by a timing clock Related violations: TIMING-20#17 Warning Non-clocked latch The latch ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_tms_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_tms_o_reg/G is not reached by a timing clock Related violations: TIMING-20#18 Warning Non-clocked latch The latch ngFEC/SFP_GEN[12].ngCCM_gbt/sec_jtag_tdi_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[12].ngCCM_gbt/sec_jtag_tdi_o_reg/G is not reached by a timing clock Related violations: TIMING-20#19 Warning Non-clocked latch The latch ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_bridge_tck_i_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_bridge_tck_i_reg/G is not reached by a timing clock Related violations: TIMING-20#20 Warning Non-clocked latch The latch ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_bridge_tdo_i_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_bridge_tdo_i_reg/G is not reached by a timing clock Related violations: TIMING-20#21 Warning Non-clocked latch The latch ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_tck_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_tck_o_reg/G is not reached by a timing clock Related violations: TIMING-20#22 Warning Non-clocked latch The latch ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_tdi_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_tdi_o_reg/G is not reached by a timing clock Related violations: TIMING-20#23 Warning Non-clocked latch The latch ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_tms_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_tms_o_reg/G is not reached by a timing clock Related violations: TIMING-20#24 Warning Non-clocked latch The latch ngFEC/SFP_GEN[1].ngCCM_gbt/sec_jtag_tdi_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[1].ngCCM_gbt/sec_jtag_tdi_o_reg/G is not reached by a timing clock Related violations: TIMING-20#25 Warning Non-clocked latch The latch ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_bridge_tck_i_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_bridge_tck_i_reg/G is not reached by a timing clock Related violations: TIMING-20#26 Warning Non-clocked latch The latch ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_bridge_tdo_i_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_bridge_tdo_i_reg/G is not reached by a timing clock Related violations: TIMING-20#27 Warning Non-clocked latch The latch ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_tck_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_tck_o_reg/G is not reached by a timing clock Related violations: TIMING-20#28 Warning Non-clocked latch The latch ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_tdi_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_tdi_o_reg/G is not reached by a timing clock Related violations: TIMING-20#29 Warning Non-clocked latch The latch ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_tms_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_tms_o_reg/G is not reached by a timing clock Related violations: TIMING-20#30 Warning Non-clocked latch The latch ngFEC/SFP_GEN[2].ngCCM_gbt/sec_jtag_tdi_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[2].ngCCM_gbt/sec_jtag_tdi_o_reg/G is not reached by a timing clock Related violations: TIMING-20#31 Warning Non-clocked latch The latch ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_bridge_tck_i_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_bridge_tck_i_reg/G is not reached by a timing clock Related violations: TIMING-20#32 Warning Non-clocked latch The latch ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_bridge_tdo_i_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_bridge_tdo_i_reg/G is not reached by a timing clock Related violations: TIMING-20#33 Warning Non-clocked latch The latch ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_tck_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_tck_o_reg/G is not reached by a timing clock Related violations: TIMING-20#34 Warning Non-clocked latch The latch ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_tdi_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_tdi_o_reg/G is not reached by a timing clock Related violations: TIMING-20#35 Warning Non-clocked latch The latch ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_tms_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_tms_o_reg/G is not reached by a timing clock Related violations: TIMING-20#36 Warning Non-clocked latch The latch ngFEC/SFP_GEN[3].ngCCM_gbt/sec_jtag_tdi_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[3].ngCCM_gbt/sec_jtag_tdi_o_reg/G is not reached by a timing clock Related violations: TIMING-20#37 Warning Non-clocked latch The latch ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_bridge_tck_i_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_bridge_tck_i_reg/G is not reached by a timing clock Related violations: TIMING-20#38 Warning Non-clocked latch The latch ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_bridge_tdo_i_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_bridge_tdo_i_reg/G is not reached by a timing clock Related violations: TIMING-20#39 Warning Non-clocked latch The latch ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_tck_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_tck_o_reg/G is not reached by a timing clock Related violations: TIMING-20#40 Warning Non-clocked latch The latch ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_tdi_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_tdi_o_reg/G is not reached by a timing clock Related violations: TIMING-20#41 Warning Non-clocked latch The latch ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_tms_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_tms_o_reg/G is not reached by a timing clock Related violations: TIMING-20#42 Warning Non-clocked latch The latch ngFEC/SFP_GEN[4].ngCCM_gbt/sec_jtag_tdi_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[4].ngCCM_gbt/sec_jtag_tdi_o_reg/G is not reached by a timing clock Related violations: TIMING-20#43 Warning Non-clocked latch The latch ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_bridge_tck_i_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_bridge_tck_i_reg/G is not reached by a timing clock Related violations: TIMING-20#44 Warning Non-clocked latch The latch ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_bridge_tdo_i_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_bridge_tdo_i_reg/G is not reached by a timing clock Related violations: TIMING-20#45 Warning Non-clocked latch The latch ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_tck_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_tck_o_reg/G is not reached by a timing clock Related violations: TIMING-20#46 Warning Non-clocked latch The latch ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_tdi_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_tdi_o_reg/G is not reached by a timing clock Related violations: TIMING-20#47 Warning Non-clocked latch The latch ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_tms_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_tms_o_reg/G is not reached by a timing clock Related violations: TIMING-20#48 Warning Non-clocked latch The latch ngFEC/SFP_GEN[5].ngCCM_gbt/sec_jtag_tdi_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[5].ngCCM_gbt/sec_jtag_tdi_o_reg/G is not reached by a timing clock Related violations: TIMING-20#49 Warning Non-clocked latch The latch ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_bridge_tck_i_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_bridge_tck_i_reg/G is not reached by a timing clock Related violations: TIMING-20#50 Warning Non-clocked latch The latch ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_bridge_tdo_i_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_bridge_tdo_i_reg/G is not reached by a timing clock Related violations: TIMING-20#51 Warning Non-clocked latch The latch ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_tck_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_tck_o_reg/G is not reached by a timing clock Related violations: TIMING-20#52 Warning Non-clocked latch The latch ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_tdi_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_tdi_o_reg/G is not reached by a timing clock Related violations: TIMING-20#53 Warning Non-clocked latch The latch ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_tms_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_tms_o_reg/G is not reached by a timing clock Related violations: TIMING-20#54 Warning Non-clocked latch The latch ngFEC/SFP_GEN[6].ngCCM_gbt/sec_jtag_tdi_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[6].ngCCM_gbt/sec_jtag_tdi_o_reg/G is not reached by a timing clock Related violations: TIMING-20#55 Warning Non-clocked latch The latch ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_bridge_tck_i_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_bridge_tck_i_reg/G is not reached by a timing clock Related violations: TIMING-20#56 Warning Non-clocked latch The latch ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_bridge_tdo_i_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_bridge_tdo_i_reg/G is not reached by a timing clock Related violations: TIMING-20#57 Warning Non-clocked latch The latch ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_tck_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_tck_o_reg/G is not reached by a timing clock Related violations: TIMING-20#58 Warning Non-clocked latch The latch ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_tdi_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_tdi_o_reg/G is not reached by a timing clock Related violations: TIMING-20#59 Warning Non-clocked latch The latch ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_tms_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_tms_o_reg/G is not reached by a timing clock Related violations: TIMING-20#60 Warning Non-clocked latch The latch ngFEC/SFP_GEN[7].ngCCM_gbt/sec_jtag_tdi_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[7].ngCCM_gbt/sec_jtag_tdi_o_reg/G is not reached by a timing clock Related violations: TIMING-20#61 Warning Non-clocked latch The latch ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_bridge_tck_i_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_bridge_tck_i_reg/G is not reached by a timing clock Related violations: TIMING-20#62 Warning Non-clocked latch The latch ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_bridge_tdo_i_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_bridge_tdo_i_reg/G is not reached by a timing clock Related violations: TIMING-20#63 Warning Non-clocked latch The latch ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_tck_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_tck_o_reg/G is not reached by a timing clock Related violations: TIMING-20#64 Warning Non-clocked latch The latch ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_tdi_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_tdi_o_reg/G is not reached by a timing clock Related violations: TIMING-20#65 Warning Non-clocked latch The latch ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_tms_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_tms_o_reg/G is not reached by a timing clock Related violations: TIMING-20#66 Warning Non-clocked latch The latch ngFEC/SFP_GEN[8].ngCCM_gbt/sec_jtag_tdi_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[8].ngCCM_gbt/sec_jtag_tdi_o_reg/G is not reached by a timing clock Related violations: TIMING-20#67 Warning Non-clocked latch The latch ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_bridge_tck_i_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_bridge_tck_i_reg/G is not reached by a timing clock Related violations: TIMING-20#68 Warning Non-clocked latch The latch ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_bridge_tdo_i_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_bridge_tdo_i_reg/G is not reached by a timing clock Related violations: TIMING-20#69 Warning Non-clocked latch The latch ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_tck_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_tck_o_reg/G is not reached by a timing clock Related violations: TIMING-20#70 Warning Non-clocked latch The latch ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_tdi_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_tdi_o_reg/G is not reached by a timing clock Related violations: TIMING-20#71 Warning Non-clocked latch The latch ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_tms_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_tms_o_reg/G is not reached by a timing clock Related violations: TIMING-20#72 Warning Non-clocked latch The latch ngFEC/SFP_GEN[9].ngCCM_gbt/sec_jtag_tdi_o_reg cannot be properly analyzed as its control pin ngFEC/SFP_GEN[9].ngCCM_gbt/sec_jtag_tdi_o_reg/G is not reached by a timing clock Related violations: TIMING-20#73 Warning Non-clocked latch The latch sys/spi/sck_reg_LDC cannot be properly analyzed as its control pin sys/spi/sck_reg_LDC/G is not reached by a timing clock Related violations: TIMING-24#1 Warning Overridden Max delay datapath only A set_clock_groups or a set_false path (see constraint position 113 in the Timing Constraints window in Vivado IDE) between clocks fabric_clk_FBOUT and txWordclkl12_1 overrides a set_max_delay -datapath_only (position 143). It is not recommended to override a set_max_delay -datapath_only constraint. Replace the set_clock_groups or set_false_path between clocks with point-to-point set_false_path constraints Related violations: TIMING-24#2 Warning Overridden Max delay datapath only A set_clock_groups or a set_false path (see constraint position 113 in the Timing Constraints window in Vivado IDE) between clocks fabric_clk_FBOUT and txWordclkl12_2 overrides a set_max_delay -datapath_only (position 143). It is not recommended to override a set_max_delay -datapath_only constraint. Replace the set_clock_groups or set_false_path between clocks with point-to-point set_false_path constraints Related violations: TIMING-24#3 Warning Overridden Max delay datapath only A set_clock_groups or a set_false path (see constraint position 113 in the Timing Constraints window in Vivado IDE) between clocks fabric_clk_FBOUT and txWordclkl12_3 overrides a set_max_delay -datapath_only (position 143). It is not recommended to override a set_max_delay -datapath_only constraint. Replace the set_clock_groups or set_false_path between clocks with point-to-point set_false_path constraints Related violations: TIMING-24#4 Warning Overridden Max delay datapath only A set_clock_groups or a set_false path (see constraint position 113 in the Timing Constraints window in Vivado IDE) between clocks fabric_clk_FBOUT and txWordclkl12_4 overrides a set_max_delay -datapath_only (position 143). It is not recommended to override a set_max_delay -datapath_only constraint. Replace the set_clock_groups or set_false_path between clocks with point-to-point set_false_path constraints Related violations: TIMING-24#5 Warning Overridden Max delay datapath only A set_clock_groups or a set_false path (see constraint position 113 in the Timing Constraints window in Vivado IDE) between clocks fabric_clk_FBOUT and txWordclkl12_5 overrides a set_max_delay -datapath_only (position 143). It is not recommended to override a set_max_delay -datapath_only constraint. Replace the set_clock_groups or set_false_path between clocks with point-to-point set_false_path constraints Related violations: TIMING-24#6 Warning Overridden Max delay datapath only A set_clock_groups or a set_false path (see constraint position 113 in the Timing Constraints window in Vivado IDE) between clocks fabric_clk_FBOUT and txWordclkl12_6 overrides a set_max_delay -datapath_only (position 143). It is not recommended to override a set_max_delay -datapath_only constraint. Replace the set_clock_groups or set_false_path between clocks with point-to-point set_false_path constraints Related violations: TIMING-24#7 Warning Overridden Max delay datapath only A set_clock_groups or a set_false path (see constraint position 113 in the Timing Constraints window in Vivado IDE) between clocks fabric_clk_FBOUT and txWordclkl12_7 overrides a set_max_delay -datapath_only (position 143). It is not recommended to override a set_max_delay -datapath_only constraint. Replace the set_clock_groups or set_false_path between clocks with point-to-point set_false_path constraints Related violations: TIMING-24#8 Warning Overridden Max delay datapath only A set_clock_groups or a set_false path (see constraint position 113 in the Timing Constraints window in Vivado IDE) between clocks fabric_clk_FBOUT and txWordclkl12_8 overrides a set_max_delay -datapath_only (position 143). It is not recommended to override a set_max_delay -datapath_only constraint. Replace the set_clock_groups or set_false_path between clocks with point-to-point set_false_path constraints Related violations: TIMING-24#9 Warning Overridden Max delay datapath only A set_clock_groups or a set_false path (see constraint position 113 in the Timing Constraints window in Vivado IDE) between clocks fabric_clk_FBOUT and txWordclkl8_1 overrides a set_max_delay -datapath_only (position 143). It is not recommended to override a set_max_delay -datapath_only constraint. Replace the set_clock_groups or set_false_path between clocks with point-to-point set_false_path constraints Related violations: TIMING-24#10 Warning Overridden Max delay datapath only A set_clock_groups or a set_false path (see constraint position 113 in the Timing Constraints window in Vivado IDE) between clocks fabric_clk_FBOUT and txWordclkl8_2 overrides a set_max_delay -datapath_only (position 143). It is not recommended to override a set_max_delay -datapath_only constraint. Replace the set_clock_groups or set_false_path between clocks with point-to-point set_false_path constraints Related violations: TIMING-24#11 Warning Overridden Max delay datapath only A set_clock_groups or a set_false path (see constraint position 113 in the Timing Constraints window in Vivado IDE) between clocks fabric_clk_FBOUT and txWordclkl8_3 overrides a set_max_delay -datapath_only (position 143). It is not recommended to override a set_max_delay -datapath_only constraint. Replace the set_clock_groups or set_false_path between clocks with point-to-point set_false_path constraints Related violations: TIMING-24#12 Warning Overridden Max delay datapath only A set_clock_groups or a set_false path (see constraint position 113 in the Timing Constraints window in Vivado IDE) between clocks fabric_clk_FBOUT and txWordclkl8_4 overrides a set_max_delay -datapath_only (position 143). It is not recommended to override a set_max_delay -datapath_only constraint. Replace the set_clock_groups or set_false_path between clocks with point-to-point set_false_path constraints Related violations: TIMING-24#13 Warning Overridden Max delay datapath only A set_clock_groups or a set_false path (see constraint position 127 in the Timing Constraints window in Vivado IDE) between clocks fabric_clk_FBOUT and txWordclkl12_1 overrides a set_max_delay -datapath_only (position 143). It is not recommended to override a set_max_delay -datapath_only constraint. Replace the set_clock_groups or set_false_path between clocks with point-to-point set_false_path constraints Related violations: TIMING-24#14 Warning Overridden Max delay datapath only A set_clock_groups or a set_false path (see constraint position 128 in the Timing Constraints window in Vivado IDE) between clocks fabric_clk_FBOUT and txWordclkl12_2 overrides a set_max_delay -datapath_only (position 143). It is not recommended to override a set_max_delay -datapath_only constraint. Replace the set_clock_groups or set_false_path between clocks with point-to-point set_false_path constraints Related violations: TIMING-24#15 Warning Overridden Max delay datapath only A set_clock_groups or a set_false path (see constraint position 129 in the Timing Constraints window in Vivado IDE) between clocks fabric_clk_FBOUT and txWordclkl12_3 overrides a set_max_delay -datapath_only (position 143). It is not recommended to override a set_max_delay -datapath_only constraint. Replace the set_clock_groups or set_false_path between clocks with point-to-point set_false_path constraints Related violations: TIMING-24#16 Warning Overridden Max delay datapath only A set_clock_groups or a set_false path (see constraint position 130 in the Timing Constraints window in Vivado IDE) between clocks fabric_clk_FBOUT and txWordclkl12_4 overrides a set_max_delay -datapath_only (position 143). It is not recommended to override a set_max_delay -datapath_only constraint. Replace the set_clock_groups or set_false_path between clocks with point-to-point set_false_path constraints Related violations: TIMING-24#17 Warning Overridden Max delay datapath only A set_clock_groups or a set_false path (see constraint position 131 in the Timing Constraints window in Vivado IDE) between clocks fabric_clk_FBOUT and txWordclkl12_5 overrides a set_max_delay -datapath_only (position 143). It is not recommended to override a set_max_delay -datapath_only constraint. Replace the set_clock_groups or set_false_path between clocks with point-to-point set_false_path constraints Related violations: TIMING-24#18 Warning Overridden Max delay datapath only A set_clock_groups or a set_false path (see constraint position 132 in the Timing Constraints window in Vivado IDE) between clocks fabric_clk_FBOUT and txWordclkl12_6 overrides a set_max_delay -datapath_only (position 143). It is not recommended to override a set_max_delay -datapath_only constraint. Replace the set_clock_groups or set_false_path between clocks with point-to-point set_false_path constraints Related violations: TIMING-24#19 Warning Overridden Max delay datapath only A set_clock_groups or a set_false path (see constraint position 133 in the Timing Constraints window in Vivado IDE) between clocks fabric_clk_FBOUT and txWordclkl12_7 overrides a set_max_delay -datapath_only (position 143). It is not recommended to override a set_max_delay -datapath_only constraint. Replace the set_clock_groups or set_false_path between clocks with point-to-point set_false_path constraints Related violations: TIMING-24#20 Warning Overridden Max delay datapath only A set_clock_groups or a set_false path (see constraint position 134 in the Timing Constraints window in Vivado IDE) between clocks fabric_clk_FBOUT and txWordclkl12_8 overrides a set_max_delay -datapath_only (position 143). It is not recommended to override a set_max_delay -datapath_only constraint. Replace the set_clock_groups or set_false_path between clocks with point-to-point set_false_path constraints Related violations: TIMING-24#21 Warning Overridden Max delay datapath only A set_clock_groups or a set_false path (see constraint position 139 in the Timing Constraints window in Vivado IDE) between clocks fabric_clk_FBOUT and txWordclkl8_1 overrides a set_max_delay -datapath_only (position 143). It is not recommended to override a set_max_delay -datapath_only constraint. Replace the set_clock_groups or set_false_path between clocks with point-to-point set_false_path constraints Related violations: TIMING-24#22 Warning Overridden Max delay datapath only A set_clock_groups or a set_false path (see constraint position 140 in the Timing Constraints window in Vivado IDE) between clocks fabric_clk_FBOUT and txWordclkl8_2 overrides a set_max_delay -datapath_only (position 143). It is not recommended to override a set_max_delay -datapath_only constraint. Replace the set_clock_groups or set_false_path between clocks with point-to-point set_false_path constraints Related violations: TIMING-24#23 Warning Overridden Max delay datapath only A set_clock_groups or a set_false path (see constraint position 141 in the Timing Constraints window in Vivado IDE) between clocks fabric_clk_FBOUT and txWordclkl8_3 overrides a set_max_delay -datapath_only (position 143). It is not recommended to override a set_max_delay -datapath_only constraint. Replace the set_clock_groups or set_false_path between clocks with point-to-point set_false_path constraints Related violations: TIMING-24#24 Warning Overridden Max delay datapath only A set_clock_groups or a set_false path (see constraint position 142 in the Timing Constraints window in Vivado IDE) between clocks fabric_clk_FBOUT and txWordclkl8_4 overrides a set_max_delay -datapath_only (position 143). It is not recommended to override a set_max_delay -datapath_only constraint. Replace the set_clock_groups or set_false_path between clocks with point-to-point set_false_path constraints Related violations: XDCB-5#1 Warning Runtime inefficient way to find pin objects The option '-from : [get_pins -hier -filter {NAME =~ */*/*/*.gbt_rxgearbox_inst/reg1_reg*/C}]' of constraint 'set_max_delay' uses inefficient query to find pin objects (see constraint position '144' in the Timing Constraint window in Vivado IDE). To reduce runtime, it is recommended to get the pins through the cell objects. Please refer to Using Constraints Guide (Constraints Efficiency). An example of optimal query is: get_pins -filter {REF_PIN_NAME=~yy*} -of_objects [get_cells -hierarchical xx*]. Current XDC: D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/vproject/ngFEC_new/ngFEC_new.srcs/sources_1/new/usr_clkX12.xdc (Line: 124) Related violations: XDCB-5#2 Warning Runtime inefficient way to find pin objects The option '-from : [get_pins -hier -filter {NAME =~ */*/*/*/scrambler/*/*/C}]' of constraint 'set_max_delay' uses inefficient query to find pin objects (see constraint position '143' in the Timing Constraint window in Vivado IDE). To reduce runtime, it is recommended to get the pins through the cell objects. Please refer to Using Constraints Guide (Constraints Efficiency). An example of optimal query is: get_pins -filter {REF_PIN_NAME=~yy*} -of_objects [get_cells -hierarchical xx*]. Current XDC: D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/vproject/ngFEC_new/ngFEC_new.srcs/sources_1/new/usr_clkX12.xdc (Line: 118) Related violations: XDCB-5#3 Warning Runtime inefficient way to find pin objects The option '-to : [get_pins -hier -filter {NAME =~ */*/*/*.gbt_txgearbox_inst/*/D}]' of constraint 'set_max_delay' uses inefficient query to find pin objects (see constraint position '143' in the Timing Constraint window in Vivado IDE). To reduce runtime, it is recommended to get the pins through the cell objects. Please refer to Using Constraints Guide (Constraints Efficiency). An example of optimal query is: get_pins -filter {REF_PIN_NAME=~yy*} -of_objects [get_cells -hierarchical xx*]. Current XDC: D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/vproject/ngFEC_new/ngFEC_new.srcs/sources_1/new/usr_clkX12.xdc (Line: 118) Related violations: XDCB-5#4 Warning Runtime inefficient way to find pin objects The option '-to : [get_pins -hier -filter {NAME =~ */*/*/*/descrambler/*/D}]' of constraint 'set_max_delay' uses inefficient query to find pin objects (see constraint position '144' in the Timing Constraint window in Vivado IDE). To reduce runtime, it is recommended to get the pins through the cell objects. Please refer to Using Constraints Guide (Constraints Efficiency). An example of optimal query is: get_pins -filter {REF_PIN_NAME=~yy*} -of_objects [get_cells -hierarchical xx*]. Current XDC: D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/vproject/ngFEC_new/ngFEC_new.srcs/sources_1/new/usr_clkX12.xdc (Line: 124) Related violations: