2016.3" PB_VioResultsB 1.2fc7_top_drc_routed.rpxhpx DRC ResultsWarning"BUFC-1*Input Buffer Connections2BUFC-1#18BInput buffer sys/i2c_m/bufgen[0].scl_buf/IBUF (in sys/i2c_m/bufgen[0].scl_buf macro) has no loads. It is recommended to have an input buffer drive an internal load.JInput buffer sys/i2c_m/bufgen[0].scl_buf/IBUF (in sys/i2c_m/bufgen[0].scl_buf macro) has no loads. It is recommended to have an input buffer drive an internal load. IBUF *Warning"CHECK-3*Report rule limit reached2 CHECK-3#18Bk7_fabric_amc_rx_n03 * =k7_fabric_amc_rx_p03 *cWarning"PDRC-153*Gated clock check2 PDRC-153#18BNet ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_tck_o_reg_i_1/O, cell ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_tck_o_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.JNet ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_tck_o_reg_i_1/O, cell ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_tck_o_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. jtag_tck_o3_out * O 4*jtag_tck_o_reg_i_1 4jtag_tck_o_reg_i_1 *Warning"PDRC-153*Gated clock check2 PDRC-153#28BNet ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_1/O, cell ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.JNet ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_1/O, cell ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.  jtag_trst_o1 *' %O 4*jtag_bridge_tdo_i_reg_i_1& $4jtag_bridge_tdo_i_reg_i_1 *Warning"PDRC-153*Gated clock check2 PDRC-153#38BNet ngFEC/SFP_GEN[10].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[10].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1/O, cell ngFEC/SFP_GEN[10].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.JNet ngFEC/SFP_GEN[10].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[10].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1/O, cell ngFEC/SFP_GEN[10].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.( &sec_jtag_tdi_o_reg_i_1_n_0 *$ "O 4*sec_jtag_tdi_o_reg_i_1# !4sec_jtag_tdi_o_reg_i_1 *eWarning"PDRC-153*Gated clock check2 PDRC-153#48BNet ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_tck_o_reg_i_1/O, cell ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_tck_o_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.JNet ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_tck_o_reg_i_1/O, cell ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_tck_o_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. jtag_tck_o3_out *! O *jtag_tck_o_reg_i_1 jtag_tck_o_reg_i_1 *Warning"PDRC-153*Gated clock check2 PDRC-153#58BNet ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_1/O, cell ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.JNet ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_1/O, cell ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.  jtag_trst_o1 *( &O *jtag_bridge_tdo_i_reg_i_1' %jtag_bridge_tdo_i_reg_i_1 *Warning"PDRC-153*Gated clock check2 PDRC-153#68BNet ngFEC/SFP_GEN[11].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[11].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1/O, cell ngFEC/SFP_GEN[11].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.JNet ngFEC/SFP_GEN[11].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[11].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1/O, cell ngFEC/SFP_GEN[11].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.( &sec_jtag_tdi_o_reg_i_1_n_0 *% #O *sec_jtag_tdi_o_reg_i_1$ "sec_jtag_tdi_o_reg_i_1 *eWarning"PDRC-153*Gated clock check2 PDRC-153#78BNet ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_tck_o_reg_i_1/O, cell ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_tck_o_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.JNet ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_tck_o_reg_i_1/O, cell ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_tck_o_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. jtag_tck_o3_out *! O *jtag_tck_o_reg_i_1 jtag_tck_o_reg_i_1 *Warning"PDRC-153*Gated clock check2 PDRC-153#88BNet ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_1/O, cell ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.JNet ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_1/O, cell ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.  jtag_trst_o1 *( &O *jtag_bridge_tdo_i_reg_i_1' %jtag_bridge_tdo_i_reg_i_1 * Warning"PDRC-153*Gated clock check2 PDRC-153#98BNet ngFEC/SFP_GEN[12].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[12].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1/O, cell ngFEC/SFP_GEN[12].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.JNet ngFEC/SFP_GEN[12].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[12].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1/O, cell ngFEC/SFP_GEN[12].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.( &sec_jtag_tdi_o_reg_i_1_n_0 *% #O *sec_jtag_tdi_o_reg_i_1$ "sec_jtag_tdi_o_reg_i_1 *r Warning"PDRC-153*Gated clock check2 PDRC-153#108BNet ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_tck_o_reg_i_1__6/O, cell ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_tck_o_reg_i_1__6. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.JNet ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_tck_o_reg_i_1__6/O, cell ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_tck_o_reg_i_1__6. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. jtag_tck_o3_out *$ "O *jtag_tck_o_reg_i_1__6# !jtag_tck_o_reg_i_1__6 * Warning"PDRC-153*Gated clock check2 PDRC-153#118BNet ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__6/O, cell ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__6. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.JNet ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__6/O, cell ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__6. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.  jtag_trst_o1 *+ )O *jtag_bridge_tdo_i_reg_i_2__6* (jtag_bridge_tdo_i_reg_i_2__6 * Warning"PDRC-153*Gated clock check2 PDRC-153#128BNet ngFEC/SFP_GEN[1].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__6_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[1].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__6/O, cell ngFEC/SFP_GEN[1].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__6. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.JNet ngFEC/SFP_GEN[1].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__6_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[1].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__6/O, cell ngFEC/SFP_GEN[1].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__6. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.+ )sec_jtag_tdi_o_reg_i_1__6_n_0 *( &O *sec_jtag_tdi_o_reg_i_1__6' %sec_jtag_tdi_o_reg_i_1__6 *r Warning"PDRC-153*Gated clock check2 PDRC-153#138BNet ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_tck_o_reg_i_1__5/O, cell ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_tck_o_reg_i_1__5. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.JNet ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_tck_o_reg_i_1__5/O, cell ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_tck_o_reg_i_1__5. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. jtag_tck_o3_out *$ "O *jtag_tck_o_reg_i_1__5# !jtag_tck_o_reg_i_1__5 *Warning"PDRC-153*Gated clock check2 PDRC-153#148BNet ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__5/O, cell ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__5. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.JNet ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__5/O, cell ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__5. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.  jtag_trst_o1 *+ )O *jtag_bridge_tdo_i_reg_i_2__5* (jtag_bridge_tdo_i_reg_i_2__5 *Warning"PDRC-153*Gated clock check2 PDRC-153#158BNet ngFEC/SFP_GEN[2].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__5_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[2].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__5/O, cell ngFEC/SFP_GEN[2].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__5. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.JNet ngFEC/SFP_GEN[2].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__5_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[2].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__5/O, cell ngFEC/SFP_GEN[2].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__5. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.+ )sec_jtag_tdi_o_reg_i_1__5_n_0 *( &O *sec_jtag_tdi_o_reg_i_1__5' %sec_jtag_tdi_o_reg_i_1__5 *rWarning"PDRC-153*Gated clock check2 PDRC-153#168BNet ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_tck_o_reg_i_1__4/O, cell ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_tck_o_reg_i_1__4. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.JNet ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_tck_o_reg_i_1__4/O, cell ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_tck_o_reg_i_1__4. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. jtag_tck_o3_out *$ "O *jtag_tck_o_reg_i_1__4# !jtag_tck_o_reg_i_1__4 *Warning"PDRC-153*Gated clock check2 PDRC-153#178BNet ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__4/O, cell ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__4. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.JNet ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__4/O, cell ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__4. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.  jtag_trst_o1 *+ )O *jtag_bridge_tdo_i_reg_i_2__4* (jtag_bridge_tdo_i_reg_i_2__4 *Warning"PDRC-153*Gated clock check2 PDRC-153#188BNet ngFEC/SFP_GEN[3].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__4_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[3].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__4/O, cell ngFEC/SFP_GEN[3].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__4. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.JNet ngFEC/SFP_GEN[3].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__4_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[3].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__4/O, cell ngFEC/SFP_GEN[3].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__4. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.+ )sec_jtag_tdi_o_reg_i_1__4_n_0 *( &O *sec_jtag_tdi_o_reg_i_1__4' %sec_jtag_tdi_o_reg_i_1__4 *rWarning"PDRC-153*Gated clock check2 PDRC-153#198BNet ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_tck_o_reg_i_1__3/O, cell ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_tck_o_reg_i_1__3. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.JNet ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_tck_o_reg_i_1__3/O, cell ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_tck_o_reg_i_1__3. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. jtag_tck_o3_out *$ "O ʥ *jtag_tck_o_reg_i_1__3# !ʥ jtag_tck_o_reg_i_1__3 *Warning"PDRC-153*Gated clock check2 PDRC-153#208BNet ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__3/O, cell ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__3. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.JNet ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__3/O, cell ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__3. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.  jtag_trst_o1 *+ )O ̥ *jtag_bridge_tdo_i_reg_i_2__3* (̥ jtag_bridge_tdo_i_reg_i_2__3 *Warning"PDRC-153*Gated clock check2 PDRC-153#218BNet ngFEC/SFP_GEN[4].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__3_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[4].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__3/O, cell ngFEC/SFP_GEN[4].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__3. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.JNet ngFEC/SFP_GEN[4].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__3_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[4].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__3/O, cell ngFEC/SFP_GEN[4].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__3. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.+ )sec_jtag_tdi_o_reg_i_1__3_n_0 *( &O ˥ *sec_jtag_tdi_o_reg_i_1__3' %˥ sec_jtag_tdi_o_reg_i_1__3 *rWarning"PDRC-153*Gated clock check2 PDRC-153#228BNet ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_tck_o_reg_i_1__2/O, cell ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_tck_o_reg_i_1__2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.JNet ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_tck_o_reg_i_1__2/O, cell ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_tck_o_reg_i_1__2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. jtag_tck_o3_out *$ "O *jtag_tck_o_reg_i_1__2# ! jtag_tck_o_reg_i_1__2 *Warning"PDRC-153*Gated clock check2 PDRC-153#238BNet ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__2/O, cell ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.JNet ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__2/O, cell ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.  jtag_trst_o1 *+ )O *jtag_bridge_tdo_i_reg_i_2__2* ( jtag_bridge_tdo_i_reg_i_2__2 *Warning"PDRC-153*Gated clock check2 PDRC-153#248BNet ngFEC/SFP_GEN[5].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__2_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[5].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__2/O, cell ngFEC/SFP_GEN[5].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.JNet ngFEC/SFP_GEN[5].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__2_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[5].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__2/O, cell ngFEC/SFP_GEN[5].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.+ )sec_jtag_tdi_o_reg_i_1__2_n_0 *( &O *sec_jtag_tdi_o_reg_i_1__2' % sec_jtag_tdi_o_reg_i_1__2 *rWarning"PDRC-153*Gated clock check2 PDRC-153#258BNet ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_tck_o_reg_i_1__1/O, cell ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_tck_o_reg_i_1__1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.JNet ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_tck_o_reg_i_1__1/O, cell ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_tck_o_reg_i_1__1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. jtag_tck_o3_out *$ "O *jtag_tck_o_reg_i_1__1# ! jtag_tck_o_reg_i_1__1 *Warning"PDRC-153*Gated clock check2 PDRC-153#268BNet ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__1/O, cell ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.JNet ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__1/O, cell ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.  jtag_trst_o1 *+ )O *jtag_bridge_tdo_i_reg_i_2__1* ( jtag_bridge_tdo_i_reg_i_2__1 *Warning"PDRC-153*Gated clock check2 PDRC-153#278BNet ngFEC/SFP_GEN[6].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__1_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[6].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__1/O, cell ngFEC/SFP_GEN[6].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.JNet ngFEC/SFP_GEN[6].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__1_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[6].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__1/O, cell ngFEC/SFP_GEN[6].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.+ )sec_jtag_tdi_o_reg_i_1__1_n_0 *( &O *sec_jtag_tdi_o_reg_i_1__1' % sec_jtag_tdi_o_reg_i_1__1 *rWarning"PDRC-153*Gated clock check2 PDRC-153#288BNet ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_tck_o_reg_i_1__0/O, cell ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_tck_o_reg_i_1__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.JNet ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_tck_o_reg_i_1__0/O, cell ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_tck_o_reg_i_1__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. jtag_tck_o3_out *$ "O *jtag_tck_o_reg_i_1__0# ! jtag_tck_o_reg_i_1__0 *Warning"PDRC-153*Gated clock check2 PDRC-153#298BNet ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__0/O, cell ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.JNet ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__0/O, cell ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.  jtag_trst_o1 *+ )O *jtag_bridge_tdo_i_reg_i_2__0* ( jtag_bridge_tdo_i_reg_i_2__0 *Warning"PDRC-153*Gated clock check2 PDRC-153#308BNet ngFEC/SFP_GEN[7].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__0_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[7].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__0/O, cell ngFEC/SFP_GEN[7].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.JNet ngFEC/SFP_GEN[7].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__0_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[7].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__0/O, cell ngFEC/SFP_GEN[7].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.+ )sec_jtag_tdi_o_reg_i_1__0_n_0 *( &O *sec_jtag_tdi_o_reg_i_1__0' % sec_jtag_tdi_o_reg_i_1__0 *`Warning"PDRC-153*Gated clock check2 PDRC-153#318BNet ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_tck_o_reg_i_1/O, cell ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_tck_o_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.JNet ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_tck_o_reg_i_1/O, cell ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_tck_o_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. jtag_tck_o3_out *! O *jtag_tck_o_reg_i_1 jtag_tck_o_reg_i_1 * Warning"PDRC-153*Gated clock check2 PDRC-153#328BNet ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2/O, cell ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.JNet ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2/O, cell ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.  jtag_trst_o1 *( &O *jtag_bridge_tdo_i_reg_i_2' %jtag_bridge_tdo_i_reg_i_2 *!Warning"PDRC-153*Gated clock check2 PDRC-153#338BNet ngFEC/SFP_GEN[8].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[8].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1/O, cell ngFEC/SFP_GEN[8].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.JNet ngFEC/SFP_GEN[8].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[8].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1/O, cell ngFEC/SFP_GEN[8].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.( &sec_jtag_tdi_o_reg_i_1_n_0 *% #O *sec_jtag_tdi_o_reg_i_1$ "sec_jtag_tdi_o_reg_i_1 *r"Warning"PDRC-153*Gated clock check2 PDRC-153#348BNet ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_tck_o_reg_i_1__7/O, cell ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_tck_o_reg_i_1__7. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.JNet ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_tck_o_reg_i_1__7/O, cell ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_tck_o_reg_i_1__7. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. jtag_tck_o3_out *$ "O *jtag_tck_o_reg_i_1__7# !jtag_tck_o_reg_i_1__7 *#Warning"PDRC-153*Gated clock check2 PDRC-153#358BNet ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__7/O, cell ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__7. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.JNet ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__7/O, cell ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__7. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.  jtag_trst_o1 *+ )O *jtag_bridge_tdo_i_reg_i_2__7* (jtag_bridge_tdo_i_reg_i_2__7 *$Warning"PDRC-153*Gated clock check2 PDRC-153#368BNet ngFEC/SFP_GEN[9].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__7_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[9].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__7/O, cell ngFEC/SFP_GEN[9].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__7. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.JNet ngFEC/SFP_GEN[9].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__7_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[9].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__7/O, cell ngFEC/SFP_GEN[9].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__7. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.+ )sec_jtag_tdi_o_reg_i_1__7_n_0 *( &O *sec_jtag_tdi_o_reg_i_1__7' %sec_jtag_tdi_o_reg_i_1__7 *%Warning"PDRC-153*Gated clock check2 PDRC-153#378BNet sys/ipb_sys_regs/regs_reg[11][12]_0 is a gated clock net sourced by a combinational pin sys/ipb_sys_regs/sck_reg_LDC_i_1/O, cell sys/ipb_sys_regs/sck_reg_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.JNet sys/ipb_sys_regs/regs_reg[11][12]_0 is a gated clock net sourced by a combinational pin sys/ipb_sys_regs/sck_reg_LDC_i_1/O, cell sys/ipb_sys_regs/sck_reg_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. regs_reg[11][12]_0 * O ۟*sck_reg_LDC_i_1 ۟sck_reg_LDC_i_1 *Warning"PLIO-3*.Placement Constraints Check for IO constraints2PLIO-3#18BPartially locked IO Bus is found. Following components of the IO Bus amc_tx_n[15:1] are not locked: amc_tx_n[11] amc_tx_n[10] amc_tx_n[9] amc_tx_n[8] amc_tx_n[7] amc_tx_n[6] amc_tx_n[5] amc_tx_n[4] amc_tx_n[3] amc_tx_n[2] amc_tx_n[1]JPartially locked IO Bus is found. Following components of the IO Bus amc_tx_n[15:1] are not locked: amc_tx_n[11] amc_tx_n[10] amc_tx_n[9] amc_tx_n[8] amc_tx_n[7] amc_tx_n[6] amc_tx_n[5] amc_tx_n[4] amc_tx_n[3] amc_tx_n[2] amc_tx_n[1]X%STR%ELG%STR%ELG%STR%ELG%STR%ELG%STR%ELG%STR%ELG%STR%ELG%STR%ELG%STR%ELG%STR%ELG%STR%ELG            amc_tx_n *  amc_tx_n[11] *  amc_tx_n[10] *  amc_tx_n[9] *  amc_tx_n[8] *  amc_tx_n[7] *  amc_tx_n[6] *  amc_tx_n[5] *  amc_tx_n[4] *  amc_tx_n[3] *  amc_tx_n[2] *  amc_tx_n[1] *Warning"PLIO-3*.Placement Constraints Check for IO constraints2PLIO-3#28BPartially locked IO Bus is found. Following components of the IO Bus amc_tx_p[15:1] are not locked: amc_tx_p[11] amc_tx_p[10] amc_tx_p[9] amc_tx_p[8] amc_tx_p[7] amc_tx_p[6] amc_tx_p[5] amc_tx_p[4] amc_tx_p[3] amc_tx_p[2] amc_tx_p[1]JPartially locked IO Bus is found. Following components of the IO Bus amc_tx_p[15:1] are not locked: amc_tx_p[11] amc_tx_p[10] amc_tx_p[9] amc_tx_p[8] amc_tx_p[7] amc_tx_p[6] amc_tx_p[5] amc_tx_p[4] amc_tx_p[3] amc_tx_p[2] amc_tx_p[1]X%STR%ELG%STR%ELG%STR%ELG%STR%ELG%STR%ELG%STR%ELG%STR%ELG%STR%ELG%STR%ELG%STR%ELG%STR%ELG            amc_tx_p *  amc_tx_p[11] *  amc_tx_p[10] *  amc_tx_p[9] *  amc_tx_p[8] *  amc_tx_p[7] *  amc_tx_p[6] *  amc_tx_p[5] *  amc_tx_p[4] *  amc_tx_p[3] *  amc_tx_p[2] *  amc_tx_p[1] *mWarning"PLIO-3*.Placement Constraints Check for IO constraints2PLIO-3#38BPartially locked IO Bus is found. Following components of the IO Bus k7_amc_rx_n[15:1] are not locked: k7_amc_rx_n[11] k7_amc_rx_n[10] k7_amc_rx_n[9] k7_amc_rx_n[8] k7_amc_rx_n[7] k7_amc_rx_n[6] k7_amc_rx_n[5] k7_amc_rx_n[4] k7_amc_rx_n[3] k7_amc_rx_n[2] k7_amc_rx_n[1]JPartially locked IO Bus is found. Following components of the IO Bus k7_amc_rx_n[15:1] are not locked: k7_amc_rx_n[11] k7_amc_rx_n[10] k7_amc_rx_n[9] k7_amc_rx_n[8] k7_amc_rx_n[7] k7_amc_rx_n[6] k7_amc_rx_n[5] k7_amc_rx_n[4] k7_amc_rx_n[3] k7_amc_rx_n[2] k7_amc_rx_n[1]X%STR%ELG%STR%ELG%STR%ELG%STR%ELG%STR%ELG%STR%ELG%STR%ELG%STR%ELG%STR%ELG%STR%ELG%STR%ELG             k7_amc_rx_n * k7_amc_rx_n[11] * k7_amc_rx_n[10] * k7_amc_rx_n[9] * k7_amc_rx_n[8] * k7_amc_rx_n[7] * k7_amc_rx_n[6] * k7_amc_rx_n[5] * k7_amc_rx_n[4] * k7_amc_rx_n[3] * k7_amc_rx_n[2] * k7_amc_rx_n[1] *mWarning"PLIO-3*.Placement Constraints Check for IO constraints2PLIO-3#48BPartially locked IO Bus is found. Following components of the IO Bus k7_amc_rx_p[15:1] are not locked: k7_amc_rx_p[11] k7_amc_rx_p[10] k7_amc_rx_p[9] k7_amc_rx_p[8] k7_amc_rx_p[7] k7_amc_rx_p[6] k7_amc_rx_p[5] k7_amc_rx_p[4] k7_amc_rx_p[3] k7_amc_rx_p[2] k7_amc_rx_p[1]JPartially locked IO Bus is found. Following components of the IO Bus k7_amc_rx_p[15:1] are not locked: k7_amc_rx_p[11] k7_amc_rx_p[10] k7_amc_rx_p[9] k7_amc_rx_p[8] k7_amc_rx_p[7] k7_amc_rx_p[6] k7_amc_rx_p[5] k7_amc_rx_p[4] k7_amc_rx_p[3] k7_amc_rx_p[2] k7_amc_rx_p[1]X%STR%ELG%STR%ELG%STR%ELG%STR%ELG%STR%ELG%STR%ELG%STR%ELG%STR%ELG%STR%ELG%STR%ELG%STR%ELG             k7_amc_rx_p * k7_amc_rx_p[11] * k7_amc_rx_p[10] * k7_amc_rx_p[9] * k7_amc_rx_p[8] * k7_amc_rx_p[7] * k7_amc_rx_p[6] * k7_amc_rx_p[5] * k7_amc_rx_p[4] * k7_amc_rx_p[3] * k7_amc_rx_p[2] * k7_amc_rx_p[1] *oWarning" REQP-1839*RAMB36 async control check2 REQP-1839#18BThe RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[10] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[5]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.JThe RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[10] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[5]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.RAMB36E1 : memory_reg *( &ADDRARDADDR[10] :* memory_reg BRAM_wr_adr[5] *0 .9#FSM_sequential_StateJTAGCtrl_reg[0] *oWarning" REQP-1839*RAMB36 async control check2 REQP-1839#28BThe RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[10] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[5]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.JThe RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[10] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[5]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.RAMB36E1 : memory_reg *( &ADDRARDADDR[10] :* memory_reg BRAM_wr_adr[5] *0 .9#FSM_sequential_StateJTAGCtrl_reg[1] *oWarning" REQP-1839*RAMB36 async control check2 REQP-1839#38BThe RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[11] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[6]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.JThe RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[11] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[6]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.RAMB36E1 : memory_reg *( &ADDRARDADDR[11] :* memory_reg BRAM_wr_adr[6] *0 .9#FSM_sequential_StateJTAGCtrl_reg[0] *oWarning" REQP-1839*RAMB36 async control check2 REQP-1839#48BThe RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[11] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[6]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.JThe RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[11] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[6]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.RAMB36E1 : memory_reg *( &ADDRARDADDR[11] :* memory_reg BRAM_wr_adr[6] *0 .9#FSM_sequential_StateJTAGCtrl_reg[1] *oWarning" REQP-1839*RAMB36 async control check2 REQP-1839#58BThe RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[12] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[7]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.JThe RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[12] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[7]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.RAMB36E1 : memory_reg *( &ADDRARDADDR[12] :* memory_reg BRAM_wr_adr[7] *0 .9#FSM_sequential_StateJTAGCtrl_reg[0] *oWarning" REQP-1839*RAMB36 async control check2 REQP-1839#68BThe RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[12] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[7]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.JThe RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[12] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[7]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.RAMB36E1 : memory_reg *( &ADDRARDADDR[12] :* memory_reg BRAM_wr_adr[7] *0 .9#FSM_sequential_StateJTAGCtrl_reg[1] *oWarning" REQP-1839*RAMB36 async control check2 REQP-1839#78BThe RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[13] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[8]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.JThe RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[13] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[8]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.RAMB36E1 : memory_reg *( &ADDRARDADDR[13] :* memory_reg BRAM_wr_adr[8] *0 .9#FSM_sequential_StateJTAGCtrl_reg[0] *oWarning" REQP-1839*RAMB36 async control check2 REQP-1839#88BThe RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[13] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[8]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.JThe RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[13] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[8]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.RAMB36E1 : memory_reg *( &ADDRARDADDR[13] :* memory_reg BRAM_wr_adr[8] *0 .9#FSM_sequential_StateJTAGCtrl_reg[1] *o Warning" REQP-1839*RAMB36 async control check2 REQP-1839#98BThe RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[14] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[9]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.JThe RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[14] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[9]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.RAMB36E1 : memory_reg *( &ADDRARDADDR[14] :* memory_reg BRAM_wr_adr[9] *0 .9#FSM_sequential_StateJTAGCtrl_reg[0] *p Warning" REQP-1839*RAMB36 async control check2 REQP-1839#108BThe RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[14] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[9]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.JThe RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[14] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[9]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.RAMB36E1 : memory_reg *( &ADDRARDADDR[14] :* memory_reg BRAM_wr_adr[9] *0 .9#FSM_sequential_StateJTAGCtrl_reg[1] *m Warning" REQP-1839*RAMB36 async control check2 REQP-1839#118BThe RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[5] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[0]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.JThe RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[5] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[0]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.RAMB36E1 : memory_reg *' %ADDRARDADDR[5] :* memory_reg BRAM_wr_adr[0] *0 .9#FSM_sequential_StateJTAGCtrl_reg[0] *m Warning" REQP-1839*RAMB36 async control check2 REQP-1839#128BThe RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[5] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[0]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.JThe RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[5] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[0]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.RAMB36E1 : memory_reg *' %ADDRARDADDR[5] :* memory_reg BRAM_wr_adr[0] *0 .9#FSM_sequential_StateJTAGCtrl_reg[1] *m Warning" REQP-1839*RAMB36 async control check2 REQP-1839#138BThe RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[6] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[1]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.JThe RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[6] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[1]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.RAMB36E1 : memory_reg *' %ADDRARDADDR[6] :* memory_reg BRAM_wr_adr[1] *0 .9#FSM_sequential_StateJTAGCtrl_reg[0] *mWarning" REQP-1839*RAMB36 async control check2 REQP-1839#148BThe RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[6] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[1]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.JThe RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[6] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[1]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.RAMB36E1 : memory_reg *' %ADDRARDADDR[6] :* memory_reg BRAM_wr_adr[1] *0 .9#FSM_sequential_StateJTAGCtrl_reg[1] *mWarning" REQP-1839*RAMB36 async control check2 REQP-1839#158BThe RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[7] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[2]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.JThe RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[7] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[2]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.RAMB36E1 : memory_reg *' %ADDRARDADDR[7] :* memory_reg BRAM_wr_adr[2] *0 .9#FSM_sequential_StateJTAGCtrl_reg[0] *mWarning" REQP-1839*RAMB36 async control check2 REQP-1839#168BThe RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[7] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[2]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.JThe RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[7] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[2]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.RAMB36E1 : memory_reg *' %ADDRARDADDR[7] :* memory_reg BRAM_wr_adr[2] *0 .9#FSM_sequential_StateJTAGCtrl_reg[1] *mWarning" REQP-1839*RAMB36 async control check2 REQP-1839#178BThe RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[8] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[3]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.JThe RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[8] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[3]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.RAMB36E1 : memory_reg *' %ADDRARDADDR[8] :* memory_reg BRAM_wr_adr[3] *0 .9#FSM_sequential_StateJTAGCtrl_reg[0] *mWarning" REQP-1839*RAMB36 async control check2 REQP-1839#188BThe RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[8] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[3]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.JThe RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[8] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[3]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.RAMB36E1 : memory_reg *' %ADDRARDADDR[8] :* memory_reg BRAM_wr_adr[3] *0 .9#FSM_sequential_StateJTAGCtrl_reg[1] *mWarning" REQP-1839*RAMB36 async control check2 REQP-1839#198BThe RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[9] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[4]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.JThe RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[9] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[4]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.RAMB36E1 : memory_reg *' %ADDRARDADDR[9] :* memory_reg BRAM_wr_adr[4] *0 .9#FSM_sequential_StateJTAGCtrl_reg[0] *mWarning" REQP-1839*RAMB36 async control check2 REQP-1839#208BThe RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[9] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[4]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.JThe RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[9] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[4]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.RAMB36E1 : memory_reg *' %ADDRARDADDR[9] :* memory_reg BRAM_wr_adr[4] *0 .9#FSM_sequential_StateJTAGCtrl_reg[1] *2Warning"RPBF-3*IO port buffering is incomplete2RPBF-3#18BeDevice port cpld2fpga_gpio[0] expects both input and output buffering but the buffers are incomplete.JeDevice port cpld2fpga_gpio[0] expects both input and output buffering but the buffers are incomplete. cpld2fpga_gpio[0] *2Warning"RPBF-3*IO port buffering is incomplete2RPBF-3#28BeDevice port cpld2fpga_gpio[1] expects both input and output buffering but the buffers are incomplete.JeDevice port cpld2fpga_gpio[1] expects both input and output buffering but the buffers are incomplete. cpld2fpga_gpio[1] *2Warning"RPBF-3*IO port buffering is incomplete2RPBF-3#38BeDevice port cpld2fpga_gpio[2] expects both input and output buffering but the buffers are incomplete.JeDevice port cpld2fpga_gpio[2] expects both input and output buffering but the buffers are incomplete. cpld2fpga_gpio[2] *2Warning"RPBF-3*IO port buffering is incomplete2RPBF-3#48BeDevice port cpld2fpga_gpio[3] expects both input and output buffering but the buffers are incomplete.JeDevice port cpld2fpga_gpio[3] expects both input and output buffering but the buffers are incomplete. cpld2fpga_gpio[3] */Warning"RPBF-3*IO port buffering is incomplete2RPBF-3#58BdDevice port fmc_l12_la_n[10] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l12_la_n[10] expects both input and output buffering but the buffers are incomplete. fmc_l12_la_n[10] */Warning"RPBF-3*IO port buffering is incomplete2RPBF-3#68BdDevice port fmc_l12_la_n[11] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l12_la_n[11] expects both input and output buffering but the buffers are incomplete. fmc_l12_la_n[11] */Warning"RPBF-3*IO port buffering is incomplete2RPBF-3#78BdDevice port fmc_l12_la_n[13] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l12_la_n[13] expects both input and output buffering but the buffers are incomplete. fmc_l12_la_n[13] */Warning"RPBF-3*IO port buffering is incomplete2RPBF-3#88BdDevice port fmc_l12_la_n[14] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l12_la_n[14] expects both input and output buffering but the buffers are incomplete. fmc_l12_la_n[14] */ Warning"RPBF-3*IO port buffering is incomplete2RPBF-3#98BdDevice port fmc_l12_la_n[15] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l12_la_n[15] expects both input and output buffering but the buffers are incomplete. fmc_l12_la_n[15] *0 Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#108BdDevice port fmc_l12_la_n[17] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l12_la_n[17] expects both input and output buffering but the buffers are incomplete. fmc_l12_la_n[17] *0 Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#118BdDevice port fmc_l12_la_n[18] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l12_la_n[18] expects both input and output buffering but the buffers are incomplete. ߅fmc_l12_la_n[18] *0 Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#128BdDevice port fmc_l12_la_n[19] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l12_la_n[19] expects both input and output buffering but the buffers are incomplete. ޅfmc_l12_la_n[19] *0 Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#138BdDevice port fmc_l12_la_n[20] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l12_la_n[20] expects both input and output buffering but the buffers are incomplete. ݅fmc_l12_la_n[20] *0Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#148BdDevice port fmc_l12_la_n[22] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l12_la_n[22] expects both input and output buffering but the buffers are incomplete. ۅfmc_l12_la_n[22] *0Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#158BdDevice port fmc_l12_la_n[23] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l12_la_n[23] expects both input and output buffering but the buffers are incomplete. څfmc_l12_la_n[23] *0Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#168BdDevice port fmc_l12_la_n[24] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l12_la_n[24] expects both input and output buffering but the buffers are incomplete. مfmc_l12_la_n[24] *0Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#178BdDevice port fmc_l12_la_n[26] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l12_la_n[26] expects both input and output buffering but the buffers are incomplete. ׅfmc_l12_la_n[26] *0Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#188BdDevice port fmc_l12_la_n[27] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l12_la_n[27] expects both input and output buffering but the buffers are incomplete. օfmc_l12_la_n[27] *0Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#198BdDevice port fmc_l12_la_n[29] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l12_la_n[29] expects both input and output buffering but the buffers are incomplete. ԅfmc_l12_la_n[29] *0Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#208BdDevice port fmc_l12_la_n[30] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l12_la_n[30] expects both input and output buffering but the buffers are incomplete. Ӆfmc_l12_la_n[30] *0Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#218BdDevice port fmc_l12_la_n[31] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l12_la_n[31] expects both input and output buffering but the buffers are incomplete. ҅fmc_l12_la_n[31] *0Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#228BdDevice port fmc_l12_la_n[33] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l12_la_n[33] expects both input and output buffering but the buffers are incomplete. Ѕfmc_l12_la_n[33] *-Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#238BcDevice port fmc_l12_la_n[4] expects both input and output buffering but the buffers are incomplete.JcDevice port fmc_l12_la_n[4] expects both input and output buffering but the buffers are incomplete. fmc_l12_la_n[4] *-Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#248BcDevice port fmc_l12_la_n[6] expects both input and output buffering but the buffers are incomplete.JcDevice port fmc_l12_la_n[6] expects both input and output buffering but the buffers are incomplete. fmc_l12_la_n[6] *-Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#258BcDevice port fmc_l12_la_n[7] expects both input and output buffering but the buffers are incomplete.JcDevice port fmc_l12_la_n[7] expects both input and output buffering but the buffers are incomplete. fmc_l12_la_n[7] *-Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#268BcDevice port fmc_l12_la_n[8] expects both input and output buffering but the buffers are incomplete.JcDevice port fmc_l12_la_n[8] expects both input and output buffering but the buffers are incomplete. fmc_l12_la_n[8] *0Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#278BdDevice port fmc_l12_la_p[10] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l12_la_p[10] expects both input and output buffering but the buffers are incomplete. ͅfmc_l12_la_p[10] *0Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#288BdDevice port fmc_l12_la_p[11] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l12_la_p[11] expects both input and output buffering but the buffers are incomplete. ̅fmc_l12_la_p[11] *0Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#298BdDevice port fmc_l12_la_p[12] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l12_la_p[12] expects both input and output buffering but the buffers are incomplete. ˅fmc_l12_la_p[12] *0Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#308BdDevice port fmc_l12_la_p[14] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l12_la_p[14] expects both input and output buffering but the buffers are incomplete. Ʌfmc_l12_la_p[14] *0Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#318BdDevice port fmc_l12_la_p[15] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l12_la_p[15] expects both input and output buffering but the buffers are incomplete. ȅfmc_l12_la_p[15] *0 Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#328BdDevice port fmc_l12_la_p[17] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l12_la_p[17] expects both input and output buffering but the buffers are incomplete. ƅfmc_l12_la_p[17] *0!Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#338BdDevice port fmc_l12_la_p[18] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l12_la_p[18] expects both input and output buffering but the buffers are incomplete. Ņfmc_l12_la_p[18] *0"Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#348BdDevice port fmc_l12_la_p[19] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l12_la_p[19] expects both input and output buffering but the buffers are incomplete. ąfmc_l12_la_p[19] *0#Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#358BdDevice port fmc_l12_la_p[20] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l12_la_p[20] expects both input and output buffering but the buffers are incomplete. Åfmc_l12_la_p[20] *0$Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#368BdDevice port fmc_l12_la_p[21] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l12_la_p[21] expects both input and output buffering but the buffers are incomplete. …fmc_l12_la_p[21] *0%Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#378BdDevice port fmc_l12_la_p[23] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l12_la_p[23] expects both input and output buffering but the buffers are incomplete. fmc_l12_la_p[23] *0&Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#388BdDevice port fmc_l12_la_p[24] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l12_la_p[24] expects both input and output buffering but the buffers are incomplete. fmc_l12_la_p[24] *0'Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#398BdDevice port fmc_l12_la_p[26] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l12_la_p[26] expects both input and output buffering but the buffers are incomplete. fmc_l12_la_p[26] *0(Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#408BdDevice port fmc_l12_la_p[27] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l12_la_p[27] expects both input and output buffering but the buffers are incomplete. fmc_l12_la_p[27] *0)Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#418BdDevice port fmc_l12_la_p[28] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l12_la_p[28] expects both input and output buffering but the buffers are incomplete. fmc_l12_la_p[28] *0*Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#428BdDevice port fmc_l12_la_p[30] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l12_la_p[30] expects both input and output buffering but the buffers are incomplete. fmc_l12_la_p[30] *0+Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#438BdDevice port fmc_l12_la_p[31] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l12_la_p[31] expects both input and output buffering but the buffers are incomplete. fmc_l12_la_p[31] *0,Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#448BdDevice port fmc_l12_la_p[33] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l12_la_p[33] expects both input and output buffering but the buffers are incomplete. fmc_l12_la_p[33] *--Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#458BcDevice port fmc_l12_la_p[4] expects both input and output buffering but the buffers are incomplete.JcDevice port fmc_l12_la_p[4] expects both input and output buffering but the buffers are incomplete. fmc_l12_la_p[4] *-.Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#468BcDevice port fmc_l12_la_p[5] expects both input and output buffering but the buffers are incomplete.JcDevice port fmc_l12_la_p[5] expects both input and output buffering but the buffers are incomplete. fmc_l12_la_p[5] *-/Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#478BcDevice port fmc_l12_la_p[7] expects both input and output buffering but the buffers are incomplete.JcDevice port fmc_l12_la_p[7] expects both input and output buffering but the buffers are incomplete. fmc_l12_la_p[7] *-0Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#488BcDevice port fmc_l12_la_p[8] expects both input and output buffering but the buffers are incomplete.JcDevice port fmc_l12_la_p[8] expects both input and output buffering but the buffers are incomplete. υfmc_l12_la_p[8] *01Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#498BdDevice port fmc_l12_spare[6] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l12_spare[6] expects both input and output buffering but the buffers are incomplete. fmc_l12_spare[6] *02Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#508BdDevice port fmc_l12_spare[7] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l12_spare[7] expects both input and output buffering but the buffers are incomplete. fmc_l12_spare[7] *-3Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#518BcDevice port fmc_l8_la_n[10] expects both input and output buffering but the buffers are incomplete.JcDevice port fmc_l8_la_n[10] expects both input and output buffering but the buffers are incomplete. fmc_l8_la_n[10] *-4Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#528BcDevice port fmc_l8_la_n[11] expects both input and output buffering but the buffers are incomplete.JcDevice port fmc_l8_la_n[11] expects both input and output buffering but the buffers are incomplete. fmc_l8_la_n[11] *-5Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#538BcDevice port fmc_l8_la_n[13] expects both input and output buffering but the buffers are incomplete.JcDevice port fmc_l8_la_n[13] expects both input and output buffering but the buffers are incomplete. fmc_l8_la_n[13] *-6Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#548BcDevice port fmc_l8_la_n[14] expects both input and output buffering but the buffers are incomplete.JcDevice port fmc_l8_la_n[14] expects both input and output buffering but the buffers are incomplete. fmc_l8_la_n[14] *-7Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#558BcDevice port fmc_l8_la_n[15] expects both input and output buffering but the buffers are incomplete.JcDevice port fmc_l8_la_n[15] expects both input and output buffering but the buffers are incomplete. fmc_l8_la_n[15] *-8Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#568BcDevice port fmc_l8_la_n[17] expects both input and output buffering but the buffers are incomplete.JcDevice port fmc_l8_la_n[17] expects both input and output buffering but the buffers are incomplete. fmc_l8_la_n[17] *-9Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#578BcDevice port fmc_l8_la_n[18] expects both input and output buffering but the buffers are incomplete.JcDevice port fmc_l8_la_n[18] expects both input and output buffering but the buffers are incomplete. fmc_l8_la_n[18] *-:Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#588BcDevice port fmc_l8_la_n[19] expects both input and output buffering but the buffers are incomplete.JcDevice port fmc_l8_la_n[19] expects both input and output buffering but the buffers are incomplete. fmc_l8_la_n[19] **;Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#598BbDevice port fmc_l8_la_n[4] expects both input and output buffering but the buffers are incomplete.JbDevice port fmc_l8_la_n[4] expects both input and output buffering but the buffers are incomplete. fmc_l8_la_n[4] **<Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#608BbDevice port fmc_l8_la_n[6] expects both input and output buffering but the buffers are incomplete.JbDevice port fmc_l8_la_n[6] expects both input and output buffering but the buffers are incomplete. fmc_l8_la_n[6] **=Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#618BbDevice port fmc_l8_la_n[7] expects both input and output buffering but the buffers are incomplete.JbDevice port fmc_l8_la_n[7] expects both input and output buffering but the buffers are incomplete. fmc_l8_la_n[7] **>Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#628BbDevice port fmc_l8_la_n[8] expects both input and output buffering but the buffers are incomplete.JbDevice port fmc_l8_la_n[8] expects both input and output buffering but the buffers are incomplete. fmc_l8_la_n[8] *-?Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#638BcDevice port fmc_l8_la_p[10] expects both input and output buffering but the buffers are incomplete.JcDevice port fmc_l8_la_p[10] expects both input and output buffering but the buffers are incomplete. fmc_l8_la_p[10] *-@Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#648BcDevice port fmc_l8_la_p[11] expects both input and output buffering but the buffers are incomplete.JcDevice port fmc_l8_la_p[11] expects both input and output buffering but the buffers are incomplete. fmc_l8_la_p[11] *-AWarning"RPBF-3*IO port buffering is incomplete2 RPBF-3#658BcDevice port fmc_l8_la_p[12] expects both input and output buffering but the buffers are incomplete.JcDevice port fmc_l8_la_p[12] expects both input and output buffering but the buffers are incomplete. fmc_l8_la_p[12] *-BWarning"RPBF-3*IO port buffering is incomplete2 RPBF-3#668BcDevice port fmc_l8_la_p[14] expects both input and output buffering but the buffers are incomplete.JcDevice port fmc_l8_la_p[14] expects both input and output buffering but the buffers are incomplete. fmc_l8_la_p[14] *-CWarning"RPBF-3*IO port buffering is incomplete2 RPBF-3#678BcDevice port fmc_l8_la_p[15] expects both input and output buffering but the buffers are incomplete.JcDevice port fmc_l8_la_p[15] expects both input and output buffering but the buffers are incomplete. fmc_l8_la_p[15] *-DWarning"RPBF-3*IO port buffering is incomplete2 RPBF-3#688BcDevice port fmc_l8_la_p[17] expects both input and output buffering but the buffers are incomplete.JcDevice port fmc_l8_la_p[17] expects both input and output buffering but the buffers are incomplete. fmc_l8_la_p[17] *-EWarning"RPBF-3*IO port buffering is incomplete2 RPBF-3#698BcDevice port fmc_l8_la_p[18] expects both input and output buffering but the buffers are incomplete.JcDevice port fmc_l8_la_p[18] expects both input and output buffering but the buffers are incomplete. fmc_l8_la_p[18] *-FWarning"RPBF-3*IO port buffering is incomplete2 RPBF-3#708BcDevice port fmc_l8_la_p[19] expects both input and output buffering but the buffers are incomplete.JcDevice port fmc_l8_la_p[19] expects both input and output buffering but the buffers are incomplete. fmc_l8_la_p[19] **GWarning"RPBF-3*IO port buffering is incomplete2 RPBF-3#718BbDevice port fmc_l8_la_p[4] expects both input and output buffering but the buffers are incomplete.JbDevice port fmc_l8_la_p[4] expects both input and output buffering but the buffers are incomplete. fmc_l8_la_p[4] **HWarning"RPBF-3*IO port buffering is incomplete2 RPBF-3#728BbDevice port fmc_l8_la_p[5] expects both input and output buffering but the buffers are incomplete.JbDevice port fmc_l8_la_p[5] expects both input and output buffering but the buffers are incomplete. fmc_l8_la_p[5] **IWarning"RPBF-3*IO port buffering is incomplete2 RPBF-3#738BbDevice port fmc_l8_la_p[7] expects both input and output buffering but the buffers are incomplete.JbDevice port fmc_l8_la_p[7] expects both input and output buffering but the buffers are incomplete. fmc_l8_la_p[7] **JWarning"RPBF-3*IO port buffering is incomplete2 RPBF-3#748BbDevice port fmc_l8_la_p[8] expects both input and output buffering but the buffers are incomplete.JbDevice port fmc_l8_la_p[8] expects both input and output buffering but the buffers are incomplete. fmc_l8_la_p[8] *-KWarning"RPBF-3*IO port buffering is incomplete2 RPBF-3#758BcDevice port fmc_l8_spare[0] expects both input and output buffering but the buffers are incomplete.JcDevice port fmc_l8_spare[0] expects both input and output buffering but the buffers are incomplete. fmc_l8_spare[0] *0LWarning"RPBF-3*IO port buffering is incomplete2 RPBF-3#768BdDevice port fmc_l8_spare[10] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l8_spare[10] expects both input and output buffering but the buffers are incomplete. fmc_l8_spare[10] *0MWarning"RPBF-3*IO port buffering is incomplete2 RPBF-3#778BdDevice port fmc_l8_spare[11] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l8_spare[11] expects both input and output buffering but the buffers are incomplete. fmc_l8_spare[11] *0NWarning"RPBF-3*IO port buffering is incomplete2 RPBF-3#788BdDevice port fmc_l8_spare[12] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l8_spare[12] expects both input and output buffering but the buffers are incomplete. fmc_l8_spare[12] *0OWarning"RPBF-3*IO port buffering is incomplete2 RPBF-3#798BdDevice port fmc_l8_spare[13] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l8_spare[13] expects both input and output buffering but the buffers are incomplete. fmc_l8_spare[13] *0PWarning"RPBF-3*IO port buffering is incomplete2 RPBF-3#808BdDevice port fmc_l8_spare[14] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l8_spare[14] expects both input and output buffering but the buffers are incomplete. fmc_l8_spare[14] *0QWarning"RPBF-3*IO port buffering is incomplete2 RPBF-3#818BdDevice port fmc_l8_spare[15] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l8_spare[15] expects both input and output buffering but the buffers are incomplete. fmc_l8_spare[15] *0RWarning"RPBF-3*IO port buffering is incomplete2 RPBF-3#828BdDevice port fmc_l8_spare[16] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l8_spare[16] expects both input and output buffering but the buffers are incomplete. fmc_l8_spare[16] *0SWarning"RPBF-3*IO port buffering is incomplete2 RPBF-3#838BdDevice port fmc_l8_spare[17] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l8_spare[17] expects both input and output buffering but the buffers are incomplete. fmc_l8_spare[17] *0TWarning"RPBF-3*IO port buffering is incomplete2 RPBF-3#848BdDevice port fmc_l8_spare[18] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l8_spare[18] expects both input and output buffering but the buffers are incomplete. fmc_l8_spare[18] *0UWarning"RPBF-3*IO port buffering is incomplete2 RPBF-3#858BdDevice port fmc_l8_spare[19] expects both input and output buffering but the buffers are incomplete.JdDevice port fmc_l8_spare[19] expects both input and output buffering but the buffers are incomplete. fmc_l8_spare[19] *-VWarning"RPBF-3*IO port buffering is incomplete2 RPBF-3#868BcDevice port fmc_l8_spare[1] expects both input and output buffering but the buffers are incomplete.JcDevice port fmc_l8_spare[1] expects both input and output buffering but the buffers are incomplete. fmc_l8_spare[1] *-WWarning"RPBF-3*IO port buffering is incomplete2 RPBF-3#878BcDevice port fmc_l8_spare[2] expects both input and output buffering but the buffers are incomplete.JcDevice port fmc_l8_spare[2] expects both input and output buffering but the buffers are incomplete. fmc_l8_spare[2] *-XWarning"RPBF-3*IO port buffering is incomplete2 RPBF-3#888BcDevice port fmc_l8_spare[3] expects both input and output buffering but the buffers are incomplete.JcDevice port fmc_l8_spare[3] expects both input and output buffering but the buffers are incomplete. fmc_l8_spare[3] *-YWarning"RPBF-3*IO port buffering is incomplete2 RPBF-3#898BcDevice port fmc_l8_spare[4] expects both input and output buffering but the buffers are incomplete.JcDevice port fmc_l8_spare[4] expects both input and output buffering but the buffers are incomplete. fmc_l8_spare[4] *,ZWarning"RPBF-3*IO port buffering is incomplete2 RPBF-3#908BcDevice port fmc_l8_spare[5] expects both input and output buffering but the buffers are incomplete.JcDevice port fmc_l8_spare[5] expects both input and output buffering but the buffers are incomplete. 1fmc_l8_spare[5] *-[Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#918BcDevice port fmc_l8_spare[6] expects both input and output buffering but the buffers are incomplete.JcDevice port fmc_l8_spare[6] expects both input and output buffering but the buffers are incomplete. fmc_l8_spare[6] *-\Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#928BcDevice port fmc_l8_spare[7] expects both input and output buffering but the buffers are incomplete.JcDevice port fmc_l8_spare[7] expects both input and output buffering but the buffers are incomplete. fmc_l8_spare[7] *-]Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#938BcDevice port fmc_l8_spare[8] expects both input and output buffering but the buffers are incomplete.JcDevice port fmc_l8_spare[8] expects both input and output buffering but the buffers are incomplete. fmc_l8_spare[8] *-^Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#948BcDevice port fmc_l8_spare[9] expects both input and output buffering but the buffers are incomplete.JcDevice port fmc_l8_spare[9] expects both input and output buffering but the buffers are incomplete. fmc_l8_spare[9] *:_Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#958BhDevice port k7_fabric_amc_rx_n03 expects both input and output buffering but the buffers are incomplete.JhDevice port k7_fabric_amc_rx_n03 expects both input and output buffering but the buffers are incomplete. >k7_fabric_amc_rx_n03 *:`Warning"RPBF-3*IO port buffering is incomplete2 RPBF-3#968BhDevice port k7_fabric_amc_rx_p03 expects both input and output buffering but the buffers are incomplete.JhDevice port k7_fabric_amc_rx_p03 expects both input and output buffering but the buffers are incomplete. =k7_fabric_amc_rx_p03 *