Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 | Date : Mon May 18 09:52:44 2020 | Host : baby running 64-bit major release (build 9200) | Command : report_drc -file fc7_top_drc_routed.rpt -pb fc7_top_drc_routed.pb -rpx fc7_top_drc_routed.rpx | Design : fc7_top | Device : xc7k420tffg1156-2 | Speed File : -2 | Design State : Fully Routed --------------------------------------------------------------------------------------------------------------- Report DRC Table of Contents ----------------- 1. REPORT SUMMARY 2. REPORT DETAILS 1. REPORT SUMMARY ----------------- Netlist: netlist Floorplan: design_1 Design limits: Ruledeck: default Max violations: Violations found: 160 +-----------+----------+------------------------------------------------+------------+ | Rule | Severity | Description | Violations | +-----------+----------+------------------------------------------------+------------+ | BUFC-1 | Warning | Input Buffer Connections | 1 | | CHECK-3 | Warning | Report rule limit reached | 1 | | LVDS-1 | Warning | Bidirection LVDS IOs | 1 | | PDRC-153 | Warning | Gated clock check | 37 | | PLIO-3 | Warning | Placement Constraints Check for IO constraints | 4 | | REQP-1839 | Warning | RAMB36 async control check | 20 | | RPBF-3 | Warning | IO port buffering is incomplete | 96 | +-----------+----------+------------------------------------------------+------------+ 2. REPORT DETAILS ----------------- BUFC-1#1 Warning Input Buffer Connections Input buffer sys/i2c_m/bufgen[0].scl_buf/IBUF (in sys/i2c_m/bufgen[0].scl_buf macro) has no loads. It is recommended to have an input buffer drive an internal load. Related violations: CHECK-3#1 Warning Report rule limit reached REQP-1839 rule limit reached: 20 violations have been found. Related violations: LVDS-1#1 Warning Bidirection LVDS IOs The following port(s) use the LVDS_25 I/O standard and have bi-directional differential usage. Please note that LVDS_25 is a fixed impedance structure optimized to 100ohm differential. This is only intended to be used in point-to-point transmissions that do not have turn around timing requirements. If the intended usage is a bus structure, please use BLVDS/BLVDS_25, instead. k7_fabric_amc_rx_n03, k7_fabric_amc_rx_p03. Related violations: PDRC-153#1 Warning Gated clock check Net ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_tck_o_reg_i_1/O, cell ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_tck_o_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. Related violations: PDRC-153#2 Warning Gated clock check Net ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_1/O, cell ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. Related violations: PDRC-153#3 Warning Gated clock check Net ngFEC/SFP_GEN[10].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[10].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1/O, cell ngFEC/SFP_GEN[10].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. Related violations: PDRC-153#4 Warning Gated clock check Net ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_tck_o_reg_i_1/O, cell ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_tck_o_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. Related violations: PDRC-153#5 Warning Gated clock check Net ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_1/O, cell ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. Related violations: PDRC-153#6 Warning Gated clock check Net ngFEC/SFP_GEN[11].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[11].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1/O, cell ngFEC/SFP_GEN[11].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. Related violations: PDRC-153#7 Warning Gated clock check Net ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_tck_o_reg_i_1/O, cell ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_tck_o_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. Related violations: PDRC-153#8 Warning Gated clock check Net ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_1/O, cell ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. Related violations: PDRC-153#9 Warning Gated clock check Net ngFEC/SFP_GEN[12].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[12].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1/O, cell ngFEC/SFP_GEN[12].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. Related violations: PDRC-153#10 Warning Gated clock check Net ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_tck_o_reg_i_1__6/O, cell ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_tck_o_reg_i_1__6. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. Related violations: PDRC-153#11 Warning Gated clock check Net ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__6/O, cell ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__6. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. Related violations: PDRC-153#12 Warning Gated clock check Net ngFEC/SFP_GEN[1].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__6_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[1].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__6/O, cell ngFEC/SFP_GEN[1].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__6. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. Related violations: PDRC-153#13 Warning Gated clock check Net ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_tck_o_reg_i_1__5/O, cell ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_tck_o_reg_i_1__5. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. Related violations: PDRC-153#14 Warning Gated clock check Net ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__5/O, cell ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__5. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. Related violations: PDRC-153#15 Warning Gated clock check Net ngFEC/SFP_GEN[2].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__5_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[2].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__5/O, cell ngFEC/SFP_GEN[2].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__5. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. Related violations: PDRC-153#16 Warning Gated clock check Net ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_tck_o_reg_i_1__4/O, cell ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_tck_o_reg_i_1__4. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. Related violations: PDRC-153#17 Warning Gated clock check Net ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__4/O, cell ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__4. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. Related violations: PDRC-153#18 Warning Gated clock check Net ngFEC/SFP_GEN[3].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__4_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[3].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__4/O, cell ngFEC/SFP_GEN[3].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__4. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. Related violations: PDRC-153#19 Warning Gated clock check Net ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_tck_o_reg_i_1__3/O, cell ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_tck_o_reg_i_1__3. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. Related violations: PDRC-153#20 Warning Gated clock check Net ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__3/O, cell ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__3. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. Related violations: PDRC-153#21 Warning Gated clock check Net ngFEC/SFP_GEN[4].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__3_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[4].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__3/O, cell ngFEC/SFP_GEN[4].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__3. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. Related violations: PDRC-153#22 Warning Gated clock check Net ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_tck_o_reg_i_1__2/O, cell ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_tck_o_reg_i_1__2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. Related violations: PDRC-153#23 Warning Gated clock check Net ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__2/O, cell ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. Related violations: PDRC-153#24 Warning Gated clock check Net ngFEC/SFP_GEN[5].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__2_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[5].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__2/O, cell ngFEC/SFP_GEN[5].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. Related violations: PDRC-153#25 Warning Gated clock check Net ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_tck_o_reg_i_1__1/O, cell ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_tck_o_reg_i_1__1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. Related violations: PDRC-153#26 Warning Gated clock check Net ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__1/O, cell ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. Related violations: PDRC-153#27 Warning Gated clock check Net ngFEC/SFP_GEN[6].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__1_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[6].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__1/O, cell ngFEC/SFP_GEN[6].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. Related violations: PDRC-153#28 Warning Gated clock check Net ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_tck_o_reg_i_1__0/O, cell ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_tck_o_reg_i_1__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. Related violations: PDRC-153#29 Warning Gated clock check Net ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__0/O, cell ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. Related violations: PDRC-153#30 Warning Gated clock check Net ngFEC/SFP_GEN[7].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__0_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[7].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__0/O, cell ngFEC/SFP_GEN[7].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. Related violations: PDRC-153#31 Warning Gated clock check Net ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_tck_o_reg_i_1/O, cell ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_tck_o_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. Related violations: PDRC-153#32 Warning Gated clock check Net ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2/O, cell ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. Related violations: PDRC-153#33 Warning Gated clock check Net ngFEC/SFP_GEN[8].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[8].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1/O, cell ngFEC/SFP_GEN[8].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. Related violations: PDRC-153#34 Warning Gated clock check Net ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_tck_o_reg_i_1__7/O, cell ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_tck_o_reg_i_1__7. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. Related violations: PDRC-153#35 Warning Gated clock check Net ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__7/O, cell ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__7. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. Related violations: PDRC-153#36 Warning Gated clock check Net ngFEC/SFP_GEN[9].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__7_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[9].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__7/O, cell ngFEC/SFP_GEN[9].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__7. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. Related violations: PDRC-153#37 Warning Gated clock check Net sys/ipb_sys_regs/regs_reg[11][12]_0 is a gated clock net sourced by a combinational pin sys/ipb_sys_regs/sck_reg_LDC_i_1/O, cell sys/ipb_sys_regs/sck_reg_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. Related violations: PLIO-3#1 Warning Placement Constraints Check for IO constraints Partially locked IO Bus is found. Following components of the IO Bus amc_tx_n[15:1] are not locked: amc_tx_n[11] amc_tx_n[10] amc_tx_n[9] amc_tx_n[8] amc_tx_n[7] amc_tx_n[6] amc_tx_n[5] amc_tx_n[4] amc_tx_n[3] amc_tx_n[2] amc_tx_n[1] Related violations: PLIO-3#2 Warning Placement Constraints Check for IO constraints Partially locked IO Bus is found. Following components of the IO Bus amc_tx_p[15:1] are not locked: amc_tx_p[11] amc_tx_p[10] amc_tx_p[9] amc_tx_p[8] amc_tx_p[7] amc_tx_p[6] amc_tx_p[5] amc_tx_p[4] amc_tx_p[3] amc_tx_p[2] amc_tx_p[1] Related violations: PLIO-3#3 Warning Placement Constraints Check for IO constraints Partially locked IO Bus is found. Following components of the IO Bus k7_amc_rx_n[15:1] are not locked: k7_amc_rx_n[11] k7_amc_rx_n[10] k7_amc_rx_n[9] k7_amc_rx_n[8] k7_amc_rx_n[7] k7_amc_rx_n[6] k7_amc_rx_n[5] k7_amc_rx_n[4] k7_amc_rx_n[3] k7_amc_rx_n[2] k7_amc_rx_n[1] Related violations: PLIO-3#4 Warning Placement Constraints Check for IO constraints Partially locked IO Bus is found. Following components of the IO Bus k7_amc_rx_p[15:1] are not locked: k7_amc_rx_p[11] k7_amc_rx_p[10] k7_amc_rx_p[9] k7_amc_rx_p[8] k7_amc_rx_p[7] k7_amc_rx_p[6] k7_amc_rx_p[5] k7_amc_rx_p[4] k7_amc_rx_p[3] k7_amc_rx_p[2] k7_amc_rx_p[1] Related violations: REQP-1839#1 Warning RAMB36 async control check The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[10] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[5]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#2 Warning RAMB36 async control check The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[10] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[5]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#3 Warning RAMB36 async control check The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[11] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[6]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#4 Warning RAMB36 async control check The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[11] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[6]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#5 Warning RAMB36 async control check The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[12] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[7]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#6 Warning RAMB36 async control check The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[12] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[7]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#7 Warning RAMB36 async control check The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[13] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[8]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#8 Warning RAMB36 async control check The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[13] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[8]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#9 Warning RAMB36 async control check The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[14] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[9]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#10 Warning RAMB36 async control check The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[14] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[9]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#11 Warning RAMB36 async control check The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[5] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[0]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#12 Warning RAMB36 async control check The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[5] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[0]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#13 Warning RAMB36 async control check The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[6] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[1]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#14 Warning RAMB36 async control check The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[6] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[1]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#15 Warning RAMB36 async control check The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[7] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[2]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#16 Warning RAMB36 async control check The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[7] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[2]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#17 Warning RAMB36 async control check The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[8] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[3]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#18 Warning RAMB36 async control check The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[8] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[3]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#19 Warning RAMB36 async control check The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[9] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[4]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#20 Warning RAMB36 async control check The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[9] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[4]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: RPBF-3#1 Warning IO port buffering is incomplete Device port cpld2fpga_gpio[0] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#2 Warning IO port buffering is incomplete Device port cpld2fpga_gpio[1] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#3 Warning IO port buffering is incomplete Device port cpld2fpga_gpio[2] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#4 Warning IO port buffering is incomplete Device port cpld2fpga_gpio[3] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#5 Warning IO port buffering is incomplete Device port fmc_l12_la_n[10] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#6 Warning IO port buffering is incomplete Device port fmc_l12_la_n[11] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#7 Warning IO port buffering is incomplete Device port fmc_l12_la_n[13] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#8 Warning IO port buffering is incomplete Device port fmc_l12_la_n[14] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#9 Warning IO port buffering is incomplete Device port fmc_l12_la_n[15] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#10 Warning IO port buffering is incomplete Device port fmc_l12_la_n[17] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#11 Warning IO port buffering is incomplete Device port fmc_l12_la_n[18] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#12 Warning IO port buffering is incomplete Device port fmc_l12_la_n[19] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#13 Warning IO port buffering is incomplete Device port fmc_l12_la_n[20] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#14 Warning IO port buffering is incomplete Device port fmc_l12_la_n[22] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#15 Warning IO port buffering is incomplete Device port fmc_l12_la_n[23] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#16 Warning IO port buffering is incomplete Device port fmc_l12_la_n[24] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#17 Warning IO port buffering is incomplete Device port fmc_l12_la_n[26] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#18 Warning IO port buffering is incomplete Device port fmc_l12_la_n[27] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#19 Warning IO port buffering is incomplete Device port fmc_l12_la_n[29] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#20 Warning IO port buffering is incomplete Device port fmc_l12_la_n[30] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#21 Warning IO port buffering is incomplete Device port fmc_l12_la_n[31] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#22 Warning IO port buffering is incomplete Device port fmc_l12_la_n[33] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#23 Warning IO port buffering is incomplete Device port fmc_l12_la_n[4] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#24 Warning IO port buffering is incomplete Device port fmc_l12_la_n[6] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#25 Warning IO port buffering is incomplete Device port fmc_l12_la_n[7] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#26 Warning IO port buffering is incomplete Device port fmc_l12_la_n[8] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#27 Warning IO port buffering is incomplete Device port fmc_l12_la_p[10] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#28 Warning IO port buffering is incomplete Device port fmc_l12_la_p[11] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#29 Warning IO port buffering is incomplete Device port fmc_l12_la_p[12] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#30 Warning IO port buffering is incomplete Device port fmc_l12_la_p[14] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#31 Warning IO port buffering is incomplete Device port fmc_l12_la_p[15] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#32 Warning IO port buffering is incomplete Device port fmc_l12_la_p[17] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#33 Warning IO port buffering is incomplete Device port fmc_l12_la_p[18] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#34 Warning IO port buffering is incomplete Device port fmc_l12_la_p[19] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#35 Warning IO port buffering is incomplete Device port fmc_l12_la_p[20] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#36 Warning IO port buffering is incomplete Device port fmc_l12_la_p[21] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#37 Warning IO port buffering is incomplete Device port fmc_l12_la_p[23] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#38 Warning IO port buffering is incomplete Device port fmc_l12_la_p[24] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#39 Warning IO port buffering is incomplete Device port fmc_l12_la_p[26] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#40 Warning IO port buffering is incomplete Device port fmc_l12_la_p[27] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#41 Warning IO port buffering is incomplete Device port fmc_l12_la_p[28] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#42 Warning IO port buffering is incomplete Device port fmc_l12_la_p[30] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#43 Warning IO port buffering is incomplete Device port fmc_l12_la_p[31] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#44 Warning IO port buffering is incomplete Device port fmc_l12_la_p[33] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#45 Warning IO port buffering is incomplete Device port fmc_l12_la_p[4] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#46 Warning IO port buffering is incomplete Device port fmc_l12_la_p[5] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#47 Warning IO port buffering is incomplete Device port fmc_l12_la_p[7] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#48 Warning IO port buffering is incomplete Device port fmc_l12_la_p[8] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#49 Warning IO port buffering is incomplete Device port fmc_l12_spare[6] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#50 Warning IO port buffering is incomplete Device port fmc_l12_spare[7] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#51 Warning IO port buffering is incomplete Device port fmc_l8_la_n[10] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#52 Warning IO port buffering is incomplete Device port fmc_l8_la_n[11] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#53 Warning IO port buffering is incomplete Device port fmc_l8_la_n[13] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#54 Warning IO port buffering is incomplete Device port fmc_l8_la_n[14] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#55 Warning IO port buffering is incomplete Device port fmc_l8_la_n[15] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#56 Warning IO port buffering is incomplete Device port fmc_l8_la_n[17] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#57 Warning IO port buffering is incomplete Device port fmc_l8_la_n[18] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#58 Warning IO port buffering is incomplete Device port fmc_l8_la_n[19] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#59 Warning IO port buffering is incomplete Device port fmc_l8_la_n[4] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#60 Warning IO port buffering is incomplete Device port fmc_l8_la_n[6] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#61 Warning IO port buffering is incomplete Device port fmc_l8_la_n[7] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#62 Warning IO port buffering is incomplete Device port fmc_l8_la_n[8] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#63 Warning IO port buffering is incomplete Device port fmc_l8_la_p[10] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#64 Warning IO port buffering is incomplete Device port fmc_l8_la_p[11] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#65 Warning IO port buffering is incomplete Device port fmc_l8_la_p[12] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#66 Warning IO port buffering is incomplete Device port fmc_l8_la_p[14] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#67 Warning IO port buffering is incomplete Device port fmc_l8_la_p[15] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#68 Warning IO port buffering is incomplete Device port fmc_l8_la_p[17] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#69 Warning IO port buffering is incomplete Device port fmc_l8_la_p[18] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#70 Warning IO port buffering is incomplete Device port fmc_l8_la_p[19] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#71 Warning IO port buffering is incomplete Device port fmc_l8_la_p[4] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#72 Warning IO port buffering is incomplete Device port fmc_l8_la_p[5] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#73 Warning IO port buffering is incomplete Device port fmc_l8_la_p[7] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#74 Warning IO port buffering is incomplete Device port fmc_l8_la_p[8] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#75 Warning IO port buffering is incomplete Device port fmc_l8_spare[0] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#76 Warning IO port buffering is incomplete Device port fmc_l8_spare[10] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#77 Warning IO port buffering is incomplete Device port fmc_l8_spare[11] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#78 Warning IO port buffering is incomplete Device port fmc_l8_spare[12] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#79 Warning IO port buffering is incomplete Device port fmc_l8_spare[13] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#80 Warning IO port buffering is incomplete Device port fmc_l8_spare[14] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#81 Warning IO port buffering is incomplete Device port fmc_l8_spare[15] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#82 Warning IO port buffering is incomplete Device port fmc_l8_spare[16] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#83 Warning IO port buffering is incomplete Device port fmc_l8_spare[17] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#84 Warning IO port buffering is incomplete Device port fmc_l8_spare[18] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#85 Warning IO port buffering is incomplete Device port fmc_l8_spare[19] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#86 Warning IO port buffering is incomplete Device port fmc_l8_spare[1] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#87 Warning IO port buffering is incomplete Device port fmc_l8_spare[2] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#88 Warning IO port buffering is incomplete Device port fmc_l8_spare[3] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#89 Warning IO port buffering is incomplete Device port fmc_l8_spare[4] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#90 Warning IO port buffering is incomplete Device port fmc_l8_spare[5] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#91 Warning IO port buffering is incomplete Device port fmc_l8_spare[6] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#92 Warning IO port buffering is incomplete Device port fmc_l8_spare[7] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#93 Warning IO port buffering is incomplete Device port fmc_l8_spare[8] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#94 Warning IO port buffering is incomplete Device port fmc_l8_spare[9] expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#95 Warning IO port buffering is incomplete Device port k7_fabric_amc_rx_n03 expects both input and output buffering but the buffers are incomplete. Related violations: RPBF-3#96 Warning IO port buffering is incomplete Device port k7_fabric_amc_rx_p03 expects both input and output buffering but the buffers are incomplete. Related violations: