Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------- | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 | Date : Mon May 18 09:56:31 2020 | Host : baby running 64-bit major release (build 9200) | Command : report_clock_utilization -file fc7_top_clock_utilization_routed.rpt | Design : fc7_top | Device : 7k420t-ffg1156 | Speed File : -2 PRODUCTION 1.12 2017-02-17 ------------------------------------------------------------------------------------- Clock Utilization Report Table of Contents ----------------- 1. Clock Primitive Utilization 2. Global Clock Resources 3. Global Clock Source Details 4. Local Clock Details 5. Clock Regions: Key Resource Utilization 6. Clock Regions : Global Clock Summary 7. Device Cell Placement Summary for Global Clock g0 8. Device Cell Placement Summary for Global Clock g1 9. Device Cell Placement Summary for Global Clock g2 10. Device Cell Placement Summary for Global Clock g3 11. Device Cell Placement Summary for Global Clock g4 12. Device Cell Placement Summary for Global Clock g5 13. Device Cell Placement Summary for Global Clock g6 14. Device Cell Placement Summary for Global Clock g7 15. Device Cell Placement Summary for Global Clock g8 16. Device Cell Placement Summary for Global Clock g9 17. Device Cell Placement Summary for Global Clock g10 18. Device Cell Placement Summary for Global Clock g11 19. Device Cell Placement Summary for Global Clock g12 20. Device Cell Placement Summary for Global Clock g13 21. Device Cell Placement Summary for Global Clock g14 22. Device Cell Placement Summary for Global Clock g15 23. Device Cell Placement Summary for Global Clock g16 24. Device Cell Placement Summary for Global Clock g17 25. Device Cell Placement Summary for Global Clock g18 26. Device Cell Placement Summary for Global Clock g19 27. Device Cell Placement Summary for Global Clock g20 28. Device Cell Placement Summary for Global Clock g21 29. Device Cell Placement Summary for Global Clock g22 30. Device Cell Placement Summary for Global Clock g23 31. Device Cell Placement Summary for Global Clock g24 32. Device Cell Placement Summary for Global Clock g25 33. Device Cell Placement Summary for Global Clock g26 34. Device Cell Placement Summary for Global Clock g27 35. Device Cell Placement Summary for Global Clock g28 36. Device Cell Placement Summary for Global Clock g29 37. Device Cell Placement Summary for Global Clock g30 38. Device Cell Placement Summary for Global Clock g31 39. Device Cell Placement Summary for Global Clock g32 40. Device Cell Placement Summary for Global Clock g33 41. Device Cell Placement Summary for Global Clock g34 42. Device Cell Placement Summary for Global Clock g35 43. Device Cell Placement Summary for Global Clock g36 44. Device Cell Placement Summary for Global Clock g37 45. Device Cell Placement Summary for Global Clock g38 46. Device Cell Placement Summary for Global Clock g39 47. Device Cell Placement Summary for Global Clock g40 48. Device Cell Placement Summary for Global Clock g41 49. Device Cell Placement Summary for Global Clock g42 50. Device Cell Placement Summary for Global Clock g43 51. Device Cell Placement Summary for Global Clock g44 52. Device Cell Placement Summary for Global Clock g45 53. Device Cell Placement Summary for Global Clock g46 54. Clock Region Cell Placement per Global Clock: Region X0Y0 55. Clock Region Cell Placement per Global Clock: Region X1Y0 56. Clock Region Cell Placement per Global Clock: Region X0Y1 57. Clock Region Cell Placement per Global Clock: Region X1Y1 58. Clock Region Cell Placement per Global Clock: Region X0Y2 59. Clock Region Cell Placement per Global Clock: Region X1Y2 60. Clock Region Cell Placement per Global Clock: Region X0Y3 61. Clock Region Cell Placement per Global Clock: Region X1Y3 62. Clock Region Cell Placement per Global Clock: Region X0Y4 63. Clock Region Cell Placement per Global Clock: Region X1Y4 64. Clock Region Cell Placement per Global Clock: Region X0Y5 65. Clock Region Cell Placement per Global Clock: Region X1Y5 66. Clock Region Cell Placement per Global Clock: Region X0Y6 67. Clock Region Cell Placement per Global Clock: Region X1Y6 68. Clock Region Cell Placement per Global Clock: Region X0Y7 69. Clock Region Cell Placement per Global Clock: Region X1Y7 1. Clock Primitive Utilization ------------------------------ +----------+------+-----------+-----+--------------+--------+ | Type | Used | Available | LOC | Clock Region | Pblock | +----------+------+-----------+-----+--------------+--------+ | BUFGCTRL | 22 | 32 | 0 | 0 | 0 | | BUFH | 25 | 192 | 0 | 0 | 0 | | BUFIO | 0 | 32 | 0 | 0 | 0 | | BUFMR | 0 | 16 | 0 | 0 | 0 | | BUFR | 0 | 32 | 0 | 0 | 0 | | MMCM | 3 | 8 | 0 | 0 | 0 | | PLL | 1 | 8 | 0 | 0 | 0 | +----------+------+-----------+-----+--------------+--------+ 2. Global Clock Resources ------------------------- +-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | +-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y9 | n/a | 14 | 82108 | 0 | 32.000 | clk_ipb_ub | sys/clocks/clk_ipb_buf/O | sys/clocks/ipb_clk_i | | g1 | src1 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 16 | 39421 | 6 | 24.951 | fabric_clk_FBOUT | ngFEC/fclk_bufg/O | ngFEC/CLKFBIN | | g2 | src0 | BUFG/O | None | BUFGCTRL_X0Y2 | n/a | 9 | 4650 | 0 | 8.000 | clk125_ub | sys/clocks/clk125_buf/O | sys/clocks/PLLE2_BASE_inst_0 | | g3 | src2 | BUFH/O | None | BUFHCE_X1Y84 | X1Y7 | 1 | 1055 | 2 | 8.200 | rxWordclkl12_1 | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/CLK | | g4 | src3 | BUFH/O | None | BUFHCE_X1Y85 | X1Y7 | 1 | 1055 | 2 | 8.200 | rxWordclkl12_2 | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out | | g5 | src4 | BUFH/O | None | BUFHCE_X1Y86 | X1Y7 | 1 | 1055 | 2 | 8.200 | rxWordclkl12_3 | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_0 | | g6 | src5 | BUFH/O | None | BUFHCE_X1Y72 | X1Y6 | 1 | 1055 | 2 | 8.200 | rxWordclkl12_4 | ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O | ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/CLK | | g7 | src6 | BUFH/O | None | BUFHCE_X1Y73 | X1Y6 | 1 | 1055 | 0 | 8.200 | rxWordclkl12_5 | ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O | ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out | | g8 | src7 | BUFH/O | None | BUFHCE_X1Y60 | X1Y5 | 1 | 1055 | 0 | 8.200 | rxWordclkl12_6 | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/CLK | | g9 | src8 | BUFH/O | None | BUFHCE_X1Y61 | X1Y5 | 1 | 1055 | 0 | 8.200 | rxWordclkl12_7 | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out | | g10 | src9 | BUFH/O | None | BUFHCE_X1Y62 | X1Y5 | 1 | 1055 | 0 | 8.200 | rxWordclkl12_8 | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_0 | | g11 | src10 | BUFH/O | None | BUFHCE_X1Y12 | X1Y1 | 1 | 1055 | 2 | 8.200 | rxWordclkl8_1 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg/O | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/CLK | | g12 | src11 | BUFH/O | None | BUFHCE_X1Y13 | X1Y1 | 1 | 1055 | 2 | 8.200 | rxWordclkl8_2 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg/O | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out | | g13 | src12 | BUFH/O | None | BUFHCE_X1Y14 | X1Y1 | 1 | 1055 | 2 | 8.200 | rxWordclkl8_3 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg/O | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_0 | | g14 | src13 | BUFH/O | None | BUFHCE_X1Y15 | X1Y1 | 1 | 1055 | 2 | 8.200 | rxWordclkl8_4 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg/O | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_1 | | g15 | src5 | BUFG/O | None | BUFGCTRL_X0Y16 | n/a | 3 | 225 | 0 | 8.200 | txWordclkl12_4 | ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O | ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out | | g16 | src2 | BUFG/O | None | BUFGCTRL_X0Y17 | n/a | 3 | 221 | 0 | 8.200 | txWordclkl12_1 | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out | | g17 | src3 | BUFG/O | None | BUFGCTRL_X0Y18 | n/a | 2 | 221 | 0 | 8.200 | txWordclkl12_2 | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 | | g18 | src4 | BUFG/O | None | BUFGCTRL_X0Y19 | n/a | 2 | 221 | 0 | 8.200 | txWordclkl12_3 | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1 | | g19 | src6 | BUFG/O | None | BUFGCTRL_X0Y20 | n/a | 2 | 221 | 0 | 8.200 | txWordclkl12_5 | ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O | ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 | | g20 | src7 | BUFG/O | None | BUFGCTRL_X0Y21 | n/a | 2 | 221 | 0 | 8.200 | txWordclkl12_6 | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out | | g21 | src8 | BUFG/O | None | BUFGCTRL_X0Y22 | n/a | 2 | 221 | 0 | 8.200 | txWordclkl12_7 | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 | | g22 | src9 | BUFG/O | None | BUFGCTRL_X0Y23 | n/a | 3 | 221 | 0 | 8.200 | txWordclkl12_8 | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1 | | g23 | src10 | BUFG/O | None | BUFGCTRL_X0Y3 | n/a | 3 | 221 | 0 | 8.200 | txWordclkl8_1 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg/O | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out | | g24 | src11 | BUFG/O | None | BUFGCTRL_X0Y4 | n/a | 2 | 221 | 0 | 8.200 | txWordclkl8_2 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg/O | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 | | g25 | src12 | BUFG/O | None | BUFGCTRL_X0Y5 | n/a | 3 | 221 | 0 | 8.200 | txWordclkl8_3 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg/O | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1 | | g26 | src13 | BUFG/O | None | BUFGCTRL_X0Y6 | n/a | 2 | 221 | 0 | 8.200 | txWordclkl8_4 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg/O | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_2 | | g27 | src14 | BUFG/O | None | BUFGCTRL_X0Y24 | n/a | 2 | 145 | 0 | 24.953 | clk_o_39_997 | ngFEC/dmdt_clk/mmcm2/U0/clkout1_buf/O | ngFEC/dmdt_clk/mmcm2/U0/dmdt_phase_meas_clk | | g28 | src0 | BUFG/O | None | BUFGCTRL_X0Y7 | n/a | 1 | 118 | 0 | 16.000 | clk62_5_ub | sys/clocks/clk62_5_buf/O | sys/clocks/userclk | | g29 | src15 | BUFGCTRL/O | None | BUFGCTRL_X0Y1 | n/a | 3 | 28 | 0 | 24.951 | fabric_clk_FBOUT | ngFEC/cdce_synch/bufg_mux/O | ngFEC/cdce_synch/CLK | | g30 | src1 | BUFG/O | None | BUFGCTRL_X0Y10 | n/a | 1 | 13 | 0 | 24.951 | fabric_clk_PSOUT | ngFEC/fabric_clk_PS_bufg/O | ngFEC/fabric_clk_PS | | g31 | src16 | BUFG/O | None | BUFGCTRL_X0Y8 | n/a | 2 | 11 | 0 | 8.000 | osc125_a | sys/osc125a_clkbuf/O | sys/osc125_a_bufg_0 | | g32 | src17 | BUFH/O | None | BUFHCE_X0Y72 | X0Y6 | 1 | 9 | 0 | 8.333 | ttc_mgt_xpoint_c | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 | | g33 | src17 | BUFH/O | None | BUFHCE_X0Y73 | X0Y6 | 1 | 9 | 0 | 8.333 | ttc_mgt_xpoint_c | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 | | g34 | src17 | BUFH/O | None | BUFHCE_X0Y74 | X0Y6 | 1 | 9 | 0 | 8.333 | ttc_mgt_xpoint_c | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 | | g35 | src17 | BUFH/O | None | BUFHCE_X0Y75 | X0Y6 | 1 | 9 | 0 | 8.333 | ttc_mgt_xpoint_c | ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O | ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 | | g36 | src17 | BUFH/O | None | BUFHCE_X0Y76 | X0Y6 | 1 | 9 | 0 | 8.333 | ttc_mgt_xpoint_c | ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O | ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 | | g37 | src17 | BUFH/O | None | BUFHCE_X0Y77 | X0Y6 | 1 | 9 | 0 | 8.333 | ttc_mgt_xpoint_c | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 | | g38 | src17 | BUFH/O | None | BUFHCE_X0Y78 | X0Y6 | 1 | 9 | 0 | 8.333 | ttc_mgt_xpoint_c | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 | | g39 | src17 | BUFH/O | None | BUFHCE_X0Y79 | X0Y6 | 1 | 9 | 0 | 8.333 | ttc_mgt_xpoint_c | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 | | g40 | src17 | BUFH/O | None | BUFHCE_X1Y74 | X1Y6 | 1 | 5 | 2 | 8.333 | ttc_mgt_xpoint_c | ngFEC/i_ttcMgtXpoint_from_ibufdsCGtxe2_buf/O | ngFEC/ttcMgtXpoint_from_ibufdsCGtxe2_buf | | g41 | src18 | BUFH/O | None | BUFHCE_X0Y12 | X0Y1 | 1 | 9 | 0 | 8.333 | ttc_mgt_xpoint_a | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 | | g42 | src18 | BUFH/O | None | BUFHCE_X0Y13 | X0Y1 | 1 | 9 | 0 | 8.333 | ttc_mgt_xpoint_a | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 | | g43 | src18 | BUFH/O | None | BUFHCE_X0Y14 | X0Y1 | 1 | 9 | 0 | 8.333 | ttc_mgt_xpoint_a | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 | | g44 | src18 | BUFH/O | None | BUFHCE_X0Y15 | X0Y1 | 1 | 9 | 0 | 8.333 | ttc_mgt_xpoint_a | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf/O | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 | | g45 | src19 | BUFG/O | None | BUFGCTRL_X0Y25 | n/a | 1 | 1 | 0 | 24.901 | clk_o_40_08_phase_mon_mmcm_1 | ngFEC/dmdt_clk/mmcm1/U0/clkout1_buf/O | ngFEC/dmdt_clk/mmcm1/U0/clk_i_40_08 | | g46 | src14 | BUFG/O | None | BUFGCTRL_X0Y26 | n/a | 1 | 1 | 0 | 74.704 | clkfbout_phase_mon_mmcm_2 | ngFEC/dmdt_clk/mmcm2/U0/clkf_buf/O | ngFEC/dmdt_clk/mmcm2/U0/clkfbout_buf_phase_mon_mmcm_2 | +-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) 3. Global Clock Source Details ------------------------------ +-----------+---------------------------------------------+------------------------+---------------------+---------------------+--------------+-------------+-----------------+---------------------+------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+ | Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | +-----------+---------------------------------------------+------------------------+---------------------+---------------------+--------------+-------------+-----------------+---------------------+------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+ | src0 | g2 | PLLE2_ADV/CLKFBOUT | None | PLLE2_ADV_X0Y1 | X0Y1 | 1 | 0 | 8.000 | clk125_ub | sys/clocks/PLLE2_BASE_inst/CLKFBOUT | sys/clocks/clk125_ub | | src0 | g28 | PLLE2_ADV/CLKOUT1 | None | PLLE2_ADV_X0Y1 | X0Y1 | 1 | 0 | 16.000 | clk62_5_ub | sys/clocks/PLLE2_BASE_inst/CLKOUT1 | sys/clocks/clk62_5_ub | | src0 | g0 | PLLE2_ADV/CLKOUT0 | None | PLLE2_ADV_X0Y1 | X0Y1 | 1 | 0 | 32.000 | clk_ipb_ub | sys/clocks/PLLE2_BASE_inst/CLKOUT0 | sys/clocks/clk_ipb_ub | | src1 | g1 | MMCME2_ADV/CLKFBOUT | None | MMCME2_ADV_X0Y0 | X0Y0 | 1 | 0 | 24.951 | fabric_clk_FBOUT | ngFEC/fabric_clk_MMCME2/CLKFBOUT | ngFEC/fabric_clk_FBOUT | | src1 | g30 | MMCME2_ADV/CLKOUT0 | None | MMCME2_ADV_X0Y0 | X0Y0 | 1 | 0 | 24.951 | fabric_clk_PSOUT | ngFEC/fabric_clk_MMCME2/CLKOUT0 | ngFEC/fabric_clk_PSOUT | | src2 | g3 | GTXE2_CHANNEL/RXOUTCLK | GTXE2_CHANNEL_X0Y28 | GTXE2_CHANNEL_X0Y28 | X1Y7 | 1 | 0 | 8.333 | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxoutclk_out | | src2 | g16 | GTXE2_CHANNEL/TXOUTCLK | GTXE2_CHANNEL_X0Y28 | GTXE2_CHANNEL_X0Y28 | X1Y7 | 1 | 0 | 8.333 | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txoutclk_out | | src3 | g4 | GTXE2_CHANNEL/RXOUTCLK | GTXE2_CHANNEL_X0Y31 | GTXE2_CHANNEL_X0Y31 | X1Y7 | 1 | 0 | 8.333 | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxoutclk_out | | src3 | g17 | GTXE2_CHANNEL/TXOUTCLK | GTXE2_CHANNEL_X0Y31 | GTXE2_CHANNEL_X0Y31 | X1Y7 | 1 | 0 | 8.333 | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txoutclk_out | | src4 | g5 | GTXE2_CHANNEL/RXOUTCLK | GTXE2_CHANNEL_X0Y30 | GTXE2_CHANNEL_X0Y30 | X1Y7 | 1 | 0 | 8.333 | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxoutclk_out | | src4 | g18 | GTXE2_CHANNEL/TXOUTCLK | GTXE2_CHANNEL_X0Y30 | GTXE2_CHANNEL_X0Y30 | X1Y7 | 1 | 0 | 8.333 | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txoutclk_out | | src5 | g6 | GTXE2_CHANNEL/RXOUTCLK | GTXE2_CHANNEL_X0Y25 | GTXE2_CHANNEL_X0Y25 | X1Y6 | 1 | 0 | 8.333 | ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK | ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK | ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxoutclk_out | | src5 | g15 | GTXE2_CHANNEL/TXOUTCLK | GTXE2_CHANNEL_X0Y25 | GTXE2_CHANNEL_X0Y25 | X1Y6 | 1 | 0 | 8.333 | ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK | ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK | ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txoutclk_out | | src6 | g7 | GTXE2_CHANNEL/RXOUTCLK | GTXE2_CHANNEL_X0Y24 | GTXE2_CHANNEL_X0Y24 | X1Y6 | 1 | 0 | 8.333 | ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK | ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK | ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxoutclk_out | | src6 | g19 | GTXE2_CHANNEL/TXOUTCLK | GTXE2_CHANNEL_X0Y24 | GTXE2_CHANNEL_X0Y24 | X1Y6 | 1 | 0 | 8.333 | ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK | ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK | ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txoutclk_out | | src7 | g8 | GTXE2_CHANNEL/RXOUTCLK | GTXE2_CHANNEL_X0Y21 | GTXE2_CHANNEL_X0Y21 | X1Y5 | 1 | 0 | 8.333 | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxoutclk_out | | src7 | g20 | GTXE2_CHANNEL/TXOUTCLK | GTXE2_CHANNEL_X0Y21 | GTXE2_CHANNEL_X0Y21 | X1Y5 | 1 | 0 | 8.333 | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txoutclk_out | | src8 | g9 | GTXE2_CHANNEL/RXOUTCLK | GTXE2_CHANNEL_X0Y20 | GTXE2_CHANNEL_X0Y20 | X1Y5 | 1 | 0 | 8.333 | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxoutclk_out | | src8 | g21 | GTXE2_CHANNEL/TXOUTCLK | GTXE2_CHANNEL_X0Y20 | GTXE2_CHANNEL_X0Y20 | X1Y5 | 1 | 0 | 8.333 | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txoutclk_out | | src9 | g10 | GTXE2_CHANNEL/RXOUTCLK | GTXE2_CHANNEL_X0Y23 | GTXE2_CHANNEL_X0Y23 | X1Y5 | 1 | 0 | 8.333 | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxoutclk_out | | src9 | g22 | GTXE2_CHANNEL/TXOUTCLK | GTXE2_CHANNEL_X0Y23 | GTXE2_CHANNEL_X0Y23 | X1Y5 | 1 | 0 | 8.333 | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txoutclk_out | | src10 | g11 | GTXE2_CHANNEL/RXOUTCLK | GTXE2_CHANNEL_X0Y4 | GTXE2_CHANNEL_X0Y4 | X1Y1 | 1 | 0 | 8.333 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxoutclk_out | | src10 | g23 | GTXE2_CHANNEL/TXOUTCLK | GTXE2_CHANNEL_X0Y4 | GTXE2_CHANNEL_X0Y4 | X1Y1 | 1 | 0 | 8.333 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txoutclk_out | | src11 | g12 | GTXE2_CHANNEL/RXOUTCLK | GTXE2_CHANNEL_X0Y5 | GTXE2_CHANNEL_X0Y5 | X1Y1 | 1 | 0 | 8.333 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxoutclk_out | | src11 | g24 | GTXE2_CHANNEL/TXOUTCLK | GTXE2_CHANNEL_X0Y5 | GTXE2_CHANNEL_X0Y5 | X1Y1 | 1 | 0 | 8.333 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txoutclk_out | | src12 | g13 | GTXE2_CHANNEL/RXOUTCLK | GTXE2_CHANNEL_X0Y6 | GTXE2_CHANNEL_X0Y6 | X1Y1 | 1 | 0 | 8.333 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxoutclk_out | | src12 | g25 | GTXE2_CHANNEL/TXOUTCLK | GTXE2_CHANNEL_X0Y6 | GTXE2_CHANNEL_X0Y6 | X1Y1 | 1 | 0 | 8.333 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txoutclk_out | | src13 | g14 | GTXE2_CHANNEL/RXOUTCLK | GTXE2_CHANNEL_X0Y7 | GTXE2_CHANNEL_X0Y7 | X1Y1 | 1 | 0 | 8.333 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/RXOUTCLK | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_rxoutclk_out | | src13 | g26 | GTXE2_CHANNEL/TXOUTCLK | GTXE2_CHANNEL_X0Y7 | GTXE2_CHANNEL_X0Y7 | X1Y1 | 1 | 0 | 8.333 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/TXOUTCLK | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gt0_txoutclk_out | | src14 | g27 | MMCME2_ADV/CLKOUT0 | None | MMCME2_ADV_X0Y7 | X0Y7 | 1 | 0 | 24.953 | clk_o_39_997_phase_mon_mmcm_2 | ngFEC/dmdt_clk/mmcm2/U0/mmcm_adv_inst/CLKOUT0 | ngFEC/dmdt_clk/mmcm2/U0/clk_o_39_997_phase_mon_mmcm_2 | | src14 | g46 | MMCME2_ADV/CLKFBOUT | None | MMCME2_ADV_X0Y7 | X0Y7 | 1 | 0 | 74.704 | clkfbout_phase_mon_mmcm_2 | ngFEC/dmdt_clk/mmcm2/U0/mmcm_adv_inst/CLKFBOUT | ngFEC/dmdt_clk/mmcm2/U0/clkfbout_phase_mon_mmcm_2 | | src15 | g29 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 39421 | 6 | 24.951 | fabric_clk_FBOUT | ngFEC/fclk_bufg/O | ngFEC/CLKFBIN | | src16 | g31 | IBUFDS_GTE2/O | IBUFDS_GTE2_X0Y5 | IBUFDS_GTE2_X0Y5 | X1Y2 | 2 | 0 | 8.000 | osc125_a | sys/osc125a_gtebuf/O | sys/osc125a_gtebuf_n_0 | | src17 | g32, g33, g34, g35, g36, g37, g38, g39, g40 | IBUFDS_GTE2/O | IBUFDS_GTE2_X0Y13 | IBUFDS_GTE2_X0Y13 | X1Y6 | 17 | 0 | 8.333 | ttc_mgt_xpoint_c | ngFEC/cdceOut0IbufdsCGtxe2/O | ngFEC/ttcMgtXpoint_from_ibufdsCGtxe2 | | src18 | g41, g42, g43, g44 | IBUFDS_GTE2/O | IBUFDS_GTE2_X0Y3 | IBUFDS_GTE2_X0Y3 | X1Y1 | 8 | 0 | 8.333 | ttc_mgt_xpoint_a | ngFEC/cdceOut1IbufdsAGtxe2/O | ngFEC/ttcMgtXpoint_from_ibufdsAGtxe2 | | src19 | g45 | MMCME2_ADV/CLKOUT0 | None | MMCME2_ADV_X0Y6 | X0Y6 | 1 | 0 | 24.901 | clk_o_40_08_phase_mon_mmcm_1 | ngFEC/dmdt_clk/mmcm1/U0/mmcm_adv_inst/CLKOUT0 | ngFEC/dmdt_clk/mmcm1/U0/clk_o_40_08_phase_mon_mmcm_1 | +-----------+---------------------------------------------+------------------------+---------------------+---------------------+--------------+-------------+-----------------+---------------------+------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) 4. Local Clock Details ---------------------- +----------+-----------------+------------+--------------------+--------------+-------------+-----------------+--------------+-------+-----------------------------+-----------------------+ | Local Id | Driver Type/Pin | Constraint | Site/BEL | Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | +----------+-----------------+------------+--------------------+--------------+-------------+-----------------+--------------+-------+-----------------------------+-----------------------|| | 0 | FDRE/Q | None | SLICE_X182Y132/AFF | X1Y2 | 4 | 2705 | | | ngFEC/fabric_clk_div2_reg/Q | ngFEC/fabric_clk_div2 - Static - +----------+-----------------+------------+--------------------+--------------+-------------+-----------------+--------------+-------+-----------------------------+-----------------------|| * Local Clocks in this context represents only clocks driven by non-global buffers ** Clock Loads column represents the clock pin loads (pin count) *** Non-Clock Loads column represents the non-clock pin loads (pin count) 5. Clock Regions: Key Resource Utilization ------------------------------------------ +-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+---------------+--------------+--------------+--------------+--------------+ | | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+-------+-------+------+-------+------+-------+------+-------+------+-------+ | Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+-------+-------+------+-------+------+-------+------+-------+------+-------+ | X0Y0 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 50 | 0 | 50 | 9940 | 4600 | 3492 | 1600 | 0 | 120 | 57 | 60 | 0 | 120 | | X1Y0 | 3 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 12222 | 4900 | 4413 | 1800 | 0 | 120 | 56 | 60 | 0 | 120 | | X0Y1 | 8 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 11234 | 4600 | 3873 | 1600 | 0 | 120 | 56 | 60 | 0 | 120 | | X1Y1 | 11 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 12709 | 4900 | 4636 | 1800 | 0 | 120 | 43 | 60 | 0 | 120 | | X0Y2 | 4 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 12503 | 4600 | 4430 | 1600 | 0 | 120 | 60 | 60 | 0 | 120 | | X1Y2 | 7 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 12891 | 4900 | 4718 | 1800 | 0 | 120 | 55 | 60 | 0 | 120 | | X0Y3 | 4 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 10138 | 4000 | 4124 | 1600 | 0 | 120 | 55 | 60 | 0 | 120 | | X1Y3 | 4 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 11294 | 4900 | 4341 | 1800 | 0 | 120 | 47 | 60 | 0 | 120 | | X0Y4 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 8677 | 4000 | 3407 | 1600 | 0 | 120 | 48 | 60 | 0 | 120 | | X1Y4 | 10 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 11769 | 4750 | 4439 | 1750 | 0 | 110 | 36 | 55 | 0 | 120 | | X0Y5 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 8384 | 4600 | 3074 | 1600 | 0 | 120 | 42 | 60 | 0 | 120 | | X1Y5 | 12 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 11011 | 4900 | 4040 | 1800 | 0 | 120 | 18 | 60 | 0 | 120 | | X0Y6 | 10 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 51 | 4600 | 101 | 1600 | 0 | 120 | 0 | 60 | 0 | 120 | | X1Y6 | 12 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 3790 | 4900 | 1332 | 1800 | 0 | 120 | 0 | 60 | 0 | 120 | | X0Y7 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 4600 | 0 | 1600 | 0 | 120 | 0 | 60 | 0 | 120 | | X1Y7 | 10 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 3889 | 4900 | 1482 | 1800 | 0 | 120 | 0 | 60 | 0 | 120 | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+-------+-------+------+-------+------+-------+------+-------+------+-------+ * Global Clock column represents track count; while other columns represents cell counts 6. Clock Regions : Global Clock Summary --------------------------------------- All Modules +----+----+----+ | | X0 | X1 | +----+----+----+ | Y7 | 2 | 10 | | Y6 | 10 | 12 | | Y5 | 2 | 12 | | Y4 | 2 | 10 | | Y3 | 4 | 4 | | Y2 | 4 | 7 | | Y1 | 8 | 11 | | Y0 | 2 | 3 | +----+----+----+ 7. Device Cell Placement Summary for Global Clock g0 ---------------------------------------------------- +-----------+-----------------+-------------------+------------+-------------+----------------+-------------+----------+----------------+----------+----------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+------------+-------------+----------------+-------------+----------+----------------+----------+----------------------+ | g0 | BUFG/O | n/a | clk_ipb_ub | 32.000 | {0.000 16.000} | 81568 | 0 | 0 | 0 | sys/clocks/ipb_clk_i | +-----------+-----------------+-------------------+------------+-------------+----------------+-------------+----------+----------------+----------+----------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+-------+-------+ | | X0 | X1 | +----+-------+-------+ | Y7 | 0 | 0 | | Y6 | 12 | 242 | | Y5 | 5825 | 3069 | | Y4 | 6410 | 6487 | | Y3 | 7388 | 7859 | | Y2 | 7544 | 8348 | | Y1 | 8026 | 4890 | | Y0 | 7701 | 7767 | +----+-------+-------+ 8. Device Cell Placement Summary for Global Clock g1 ---------------------------------------------------- +-----------+-----------------+-------------------+------------------+-------------+----------------+-------------+----------+----------------+----------+---------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+------------------+-------------+----------------+-------------+----------+----------------+----------+---------------+ | g1 | BUFG/O | n/a | fabric_clk_FBOUT | 24.951 | {0.000 12.476} | 39387 | 0 | 3 | 12 | ngFEC/CLKFBIN | +-----------+-----------------+-------------------+------------------+-------------+----------------+-------------+----------+----------------+----------+---------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+-------+-------+ | | X0 | X1 | +----+-------+-------+ | Y7 | 0 | 650 | | Y6 | 24 | 1107 | | Y5 | 2601 | 3616 | | Y4 | 2315 | 4273 | | Y3 | 2751 | 3348 | | Y2 | 2330 | 3351 | | Y1 | 3149 | 3245 | | Y0 | 2300 | 4341 | +----+-------+-------+ 9. Device Cell Placement Summary for Global Clock g2 ---------------------------------------------------- +-----------+-----------------+-------------------+-----------+-------------+---------------+-------------+----------+----------------+----------+------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-----------+-------------+---------------+-------------+----------+----------------+----------+------------------------------+ | g2 | BUFG/O | n/a | clk125_ub | 8.000 | {0.000 4.000} | 4647 | 0 | 1 | 1 | sys/clocks/PLLE2_BASE_inst_0 | +-----------+-----------------+-------------------+-----------+-------------+---------------+-------------+----------+----------------+----------+------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+-------+-------+ | | X0 | X1 | +----+-------+-------+ | Y7 | 0 | 2 | | Y6 | 0 | 0 | | Y5 | 0 | 624 | | Y4 | 0 | 116 | | Y3 | 30 | 9 | | Y2 | 2745 | 1005 | | Y1 | 109 | 9 | | Y0 | 0 | 0 | +----+-------+-------+ 10. Device Cell Placement Summary for Global Clock g3 ----------------------------------------------------- +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+----------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+----------------------------------------------+ | g3 | BUFH/O | X1Y7 | rxWordclkl12_1 | 8.200 | {0.000 4.100} | 1055 | 0 | 0 | 1 | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/CLK | +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+----------------------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+-----------+ | | X0 | X1 | +----+----+-----------+ | Y7 | 0 | (D) 1056 | | Y6 | 0 | 0 | | Y5 | 0 | 0 | | Y4 | 0 | 0 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | 0 | 0 | | Y0 | 0 | 0 | +----+----+-----------+ 11. Device Cell Placement Summary for Global Clock g4 ----------------------------------------------------- +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------+ | g4 | BUFH/O | X1Y7 | rxWordclkl12_2 | 8.200 | {0.000 4.100} | 1055 | 0 | 0 | 1 | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out | +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+-----------+ | | X0 | X1 | +----+----+-----------+ | Y7 | 0 | (D) 1056 | | Y6 | 0 | 0 | | Y5 | 0 | 0 | | Y4 | 0 | 0 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | 0 | 0 | | Y0 | 0 | 0 | +----+----+-----------+ 12. Device Cell Placement Summary for Global Clock g5 ----------------------------------------------------- +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+--------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+--------------------------------------------------------------------+ | g5 | BUFH/O | X1Y7 | rxWordclkl12_3 | 8.200 | {0.000 4.100} | 1055 | 0 | 0 | 1 | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_0 | +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+--------------------------------------------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+-----------+ | | X0 | X1 | +----+----+-----------+ | Y7 | 0 | (D) 1056 | | Y6 | 0 | 0 | | Y5 | 0 | 0 | | Y4 | 0 | 0 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | 0 | 0 | | Y0 | 0 | 0 | +----+----+-----------+ 13. Device Cell Placement Summary for Global Clock g6 ----------------------------------------------------- +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+----------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+----------------------------------------------+ | g6 | BUFH/O | X1Y6 | rxWordclkl12_4 | 8.200 | {0.000 4.100} | 1055 | 0 | 0 | 1 | ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/CLK | +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+----------------------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+-----------+ | | X0 | X1 | +----+----+-----------+ | Y7 | 0 | 0 | | Y6 | 0 | (D) 1056 | | Y5 | 0 | 0 | | Y4 | 0 | 0 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | 0 | 0 | | Y0 | 0 | 0 | +----+----+-----------+ 14. Device Cell Placement Summary for Global Clock g7 ----------------------------------------------------- +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------+ | g7 | BUFH/O | X1Y6 | rxWordclkl12_5 | 8.200 | {0.000 4.100} | 1053 | 0 | 0 | 1 | ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out | +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+-----------+ | | X0 | X1 | +----+----+-----------+ | Y7 | 0 | 0 | | Y6 | 0 | (D) 1054 | | Y5 | 0 | 0 | | Y4 | 0 | 0 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | 0 | 0 | | Y0 | 0 | 0 | +----+----+-----------+ 15. Device Cell Placement Summary for Global Clock g8 ----------------------------------------------------- +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+----------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+----------------------------------------------+ | g8 | BUFH/O | X1Y5 | rxWordclkl12_6 | 8.200 | {0.000 4.100} | 1053 | 0 | 0 | 1 | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/CLK | +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+----------------------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+-----------+ | | X0 | X1 | +----+----+-----------+ | Y7 | 0 | 0 | | Y6 | 0 | 0 | | Y5 | 0 | (D) 1054 | | Y4 | 0 | 0 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | 0 | 0 | | Y0 | 0 | 0 | +----+----+-----------+ 16. Device Cell Placement Summary for Global Clock g9 ----------------------------------------------------- +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------+ | g9 | BUFH/O | X1Y5 | rxWordclkl12_7 | 8.200 | {0.000 4.100} | 1053 | 0 | 0 | 1 | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out | +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+-----------+ | | X0 | X1 | +----+----+-----------+ | Y7 | 0 | 0 | | Y6 | 0 | 0 | | Y5 | 0 | (D) 1054 | | Y4 | 0 | 0 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | 0 | 0 | | Y0 | 0 | 0 | +----+----+-----------+ 17. Device Cell Placement Summary for Global Clock g10 ------------------------------------------------------ +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+--------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+--------------------------------------------------------------------+ | g10 | BUFH/O | X1Y5 | rxWordclkl12_8 | 8.200 | {0.000 4.100} | 1053 | 0 | 0 | 1 | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_0 | +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+--------------------------------------------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+-----------+ | | X0 | X1 | +----+----+-----------+ | Y7 | 0 | 0 | | Y6 | 0 | 0 | | Y5 | 0 | (D) 1054 | | Y4 | 0 | 0 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | 0 | 0 | | Y0 | 0 | 0 | +----+----+-----------+ 18. Device Cell Placement Summary for Global Clock g11 ------------------------------------------------------ +-----------+-----------------+-------------------+---------------+-------------+---------------+-------------+----------+----------------+----------+---------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+---------------+-------------+---------------+-------------+----------+----------------+----------+---------------------------------------------+ | g11 | BUFH/O | X1Y1 | rxWordclkl8_1 | 8.200 | {0.000 4.100} | 1055 | 0 | 0 | 1 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/CLK | +-----------+-----------------+-------------------+---------------+-------------+---------------+-------------+----------+----------------+----------+---------------------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+-----------+ | | X0 | X1 | +----+----+-----------+ | Y7 | 0 | 0 | | Y6 | 0 | 0 | | Y5 | 0 | 0 | | Y4 | 0 | 0 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | 0 | (D) 1056 | | Y0 | 0 | 0 | +----+----+-----------+ 19. Device Cell Placement Summary for Global Clock g12 ------------------------------------------------------ +-----------+-----------------+-------------------+---------------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+---------------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------------------------------------------+ | g12 | BUFH/O | X1Y1 | rxWordclkl8_2 | 8.200 | {0.000 4.100} | 1055 | 0 | 0 | 1 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out | +-----------+-----------------+-------------------+---------------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------------------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+-----------+ | | X0 | X1 | +----+----+-----------+ | Y7 | 0 | 0 | | Y6 | 0 | 0 | | Y5 | 0 | 0 | | Y4 | 0 | 0 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | 0 | (D) 1056 | | Y0 | 0 | 0 | +----+----+-----------+ 20. Device Cell Placement Summary for Global Clock g13 ------------------------------------------------------ +-----------+-----------------+-------------------+---------------+-------------+---------------+-------------+----------+----------------+----------+-------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+---------------+-------------+---------------+-------------+----------+----------------+----------+-------------------------------------------------------------------+ | g13 | BUFH/O | X1Y1 | rxWordclkl8_3 | 8.200 | {0.000 4.100} | 1055 | 0 | 0 | 1 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_0 | +-----------+-----------------+-------------------+---------------+-------------+---------------+-------------+----------+----------------+----------+-------------------------------------------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+-----------+ | | X0 | X1 | +----+----+-----------+ | Y7 | 0 | 0 | | Y6 | 0 | 0 | | Y5 | 0 | 0 | | Y4 | 0 | 0 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | 0 | (D) 1056 | | Y0 | 0 | 0 | +----+----+-----------+ 21. Device Cell Placement Summary for Global Clock g14 ------------------------------------------------------ +-----------+-----------------+-------------------+---------------+-------------+---------------+-------------+----------+----------------+----------+-------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+---------------+-------------+---------------+-------------+----------+----------------+----------+-------------------------------------------------------------------+ | g14 | BUFH/O | X1Y1 | rxWordclkl8_4 | 8.200 | {0.000 4.100} | 1055 | 0 | 0 | 1 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_1 | +-----------+-----------------+-------------------+---------------+-------------+---------------+-------------+----------+----------------+----------+-------------------------------------------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+-----------+ | | X0 | X1 | +----+----+-----------+ | Y7 | 0 | 0 | | Y6 | 0 | 0 | | Y5 | 0 | 0 | | Y4 | 0 | 0 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | 0 | (D) 1056 | | Y0 | 0 | 0 | +----+----+-----------+ 22. Device Cell Placement Summary for Global Clock g15 ------------------------------------------------------ +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------+ | g15 | BUFG/O | n/a | txWordclkl12_4 | 8.200 | {0.000 4.100} | 223 | 0 | 0 | 1 | ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out | +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+------+ | | X0 | X1 | +----+----+------+ | Y7 | 0 | 0 | | Y6 | 0 | 44 | | Y5 | 0 | 28 | | Y4 | 0 | 152 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | 0 | 0 | | Y0 | 0 | 0 | +----+----+------+ 23. Device Cell Placement Summary for Global Clock g16 ------------------------------------------------------ +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------+ | g16 | BUFG/O | n/a | txWordclkl12_1 | 8.200 | {0.000 4.100} | 219 | 0 | 0 | 1 | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out | +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+------+ | | X0 | X1 | +----+----+------+ | Y7 | 0 | 1 | | Y6 | 0 | 71 | | Y5 | 0 | 0 | | Y4 | 0 | 148 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | 0 | 0 | | Y0 | 0 | 0 | +----+----+------+ 24. Device Cell Placement Summary for Global Clock g17 ------------------------------------------------------ +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+--------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+--------------------------------------------------------------------+ | g17 | BUFG/O | n/a | txWordclkl12_2 | 8.200 | {0.000 4.100} | 219 | 0 | 0 | 1 | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 | +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+--------------------------------------------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+------+ | | X0 | X1 | +----+----+------+ | Y7 | 0 | 34 | | Y6 | 0 | 0 | | Y5 | 0 | 186 | | Y4 | 0 | 0 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | 0 | 0 | | Y0 | 0 | 0 | +----+----+------+ 25. Device Cell Placement Summary for Global Clock g18 ------------------------------------------------------ +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+--------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+--------------------------------------------------------------------+ | g18 | BUFG/O | n/a | txWordclkl12_3 | 8.200 | {0.000 4.100} | 219 | 0 | 0 | 1 | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1 | +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+--------------------------------------------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+------+ | | X0 | X1 | +----+----+------+ | Y7 | 0 | 34 | | Y6 | 0 | 0 | | Y5 | 0 | 186 | | Y4 | 0 | 0 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | 0 | 0 | | Y0 | 0 | 0 | +----+----+------+ 26. Device Cell Placement Summary for Global Clock g19 ------------------------------------------------------ +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+--------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+--------------------------------------------------------------------+ | g19 | BUFG/O | n/a | txWordclkl12_5 | 8.200 | {0.000 4.100} | 219 | 0 | 0 | 1 | ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 | +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+--------------------------------------------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+------+ | | X0 | X1 | +----+----+------+ | Y7 | 0 | 0 | | Y6 | 0 | 72 | | Y5 | 0 | 0 | | Y4 | 0 | 148 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | 0 | 0 | | Y0 | 0 | 0 | +----+----+------+ 27. Device Cell Placement Summary for Global Clock g20 ------------------------------------------------------ +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------+ | g20 | BUFG/O | n/a | txWordclkl12_6 | 8.200 | {0.000 4.100} | 219 | 0 | 0 | 1 | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out | +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+------+ | | X0 | X1 | +----+----+------+ | Y7 | 0 | 0 | | Y6 | 0 | 0 | | Y5 | 0 | 72 | | Y4 | 0 | 148 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | 0 | 0 | | Y0 | 0 | 0 | +----+----+------+ 28. Device Cell Placement Summary for Global Clock g21 ------------------------------------------------------ +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+--------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+--------------------------------------------------------------------+ | g21 | BUFG/O | n/a | txWordclkl12_7 | 8.200 | {0.000 4.100} | 219 | 0 | 0 | 1 | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 | +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+--------------------------------------------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+------+ | | X0 | X1 | +----+----+------+ | Y7 | 0 | 0 | | Y6 | 0 | 0 | | Y5 | 0 | 43 | | Y4 | 0 | 177 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | 0 | 0 | | Y0 | 0 | 0 | +----+----+------+ 29. Device Cell Placement Summary for Global Clock g22 ------------------------------------------------------ +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+--------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+--------------------------------------------------------------------+ | g22 | BUFG/O | n/a | txWordclkl12_8 | 8.200 | {0.000 4.100} | 219 | 0 | 0 | 1 | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1 | +-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+--------------------------------------------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+------+ | | X0 | X1 | +----+----+------+ | Y7 | 0 | 0 | | Y6 | 0 | 0 | | Y5 | 0 | 72 | | Y4 | 0 | 23 | | Y3 | 0 | 125 | | Y2 | 0 | 0 | | Y1 | 0 | 0 | | Y0 | 0 | 0 | +----+----+------+ 30. Device Cell Placement Summary for Global Clock g23 ------------------------------------------------------ +-----------+-----------------+-------------------+---------------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+---------------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------------------------------------------+ | g23 | BUFG/O | n/a | txWordclkl8_1 | 8.200 | {0.000 4.100} | 219 | 0 | 0 | 1 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out | +-----------+-----------------+-------------------+---------------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------------------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+------+ | | X0 | X1 | +----+----+------+ | Y7 | 0 | 0 | | Y6 | 0 | 38 | | Y5 | 0 | 0 | | Y4 | 0 | 0 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | 0 | 11 | | Y0 | 0 | 171 | +----+----+------+ 31. Device Cell Placement Summary for Global Clock g24 ------------------------------------------------------ +-----------+-----------------+-------------------+---------------+-------------+---------------+-------------+----------+----------------+----------+-------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+---------------+-------------+---------------+-------------+----------+----------------+----------+-------------------------------------------------------------------+ | g24 | BUFG/O | n/a | txWordclkl8_2 | 8.200 | {0.000 4.100} | 219 | 0 | 0 | 1 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 | +-----------+-----------------+-------------------+---------------+-------------+---------------+-------------+----------+----------------+----------+-------------------------------------------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+------+ | | X0 | X1 | +----+----+------+ | Y7 | 0 | 0 | | Y6 | 0 | 38 | | Y5 | 0 | 0 | | Y4 | 0 | 0 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | 0 | 182 | | Y0 | 0 | 0 | +----+----+------+ 32. Device Cell Placement Summary for Global Clock g25 ------------------------------------------------------ +-----------+-----------------+-------------------+---------------+-------------+---------------+-------------+----------+----------------+----------+-------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+---------------+-------------+---------------+-------------+----------+----------------+----------+-------------------------------------------------------------------+ | g25 | BUFG/O | n/a | txWordclkl8_3 | 8.200 | {0.000 4.100} | 219 | 0 | 0 | 1 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1 | +-----------+-----------------+-------------------+---------------+-------------+---------------+-------------+----------+----------------+----------+-------------------------------------------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+------+ | | X0 | X1 | +----+----+------+ | Y7 | 0 | 0 | | Y6 | 0 | 38 | | Y5 | 0 | 0 | | Y4 | 0 | 0 | | Y3 | 0 | 0 | | Y2 | 0 | 147 | | Y1 | 0 | 35 | | Y0 | 0 | 0 | +----+----+------+ 33. Device Cell Placement Summary for Global Clock g26 ------------------------------------------------------ +-----------+-----------------+-------------------+---------------+-------------+---------------+-------------+----------+----------------+----------+-------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+---------------+-------------+---------------+-------------+----------+----------------+----------+-------------------------------------------------------------------+ | g26 | BUFG/O | n/a | txWordclkl8_4 | 8.200 | {0.000 4.100} | 219 | 0 | 0 | 1 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_2 | +-----------+-----------------+-------------------+---------------+-------------+---------------+-------------+----------+----------------+----------+-------------------------------------------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+------+ | | X0 | X1 | +----+----+------+ | Y7 | 0 | 0 | | Y6 | 0 | 38 | | Y5 | 0 | 0 | | Y4 | 0 | 0 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | 0 | 182 | | Y0 | 0 | 0 | +----+----+------+ 34. Device Cell Placement Summary for Global Clock g27 ------------------------------------------------------ +-----------+-----------------+-------------------+--------------+-------------+----------------+-------------+----------+----------------+----------+---------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+--------------+-------------+----------------+-------------+----------+----------------+----------+---------------------------------------------+ | g27 | BUFG/O | n/a | clk_o_39_997 | 24.953 | {0.000 12.476} | 145 | 0 | 0 | 0 | ngFEC/dmdt_clk/mmcm2/U0/dmdt_phase_meas_clk | +-----------+-----------------+-------------------+--------------+-------------+----------------+-------------+----------+----------------+----------+---------------------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+------+ | | X0 | X1 | +----+----+------+ | Y7 | 0 | 6 | | Y6 | 0 | 0 | | Y5 | 0 | 0 | | Y4 | 0 | 139 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | 0 | 0 | | Y0 | 0 | 0 | +----+----+------+ 35. Device Cell Placement Summary for Global Clock g28 ------------------------------------------------------ +-----------+-----------------+-------------------+------------+-------------+---------------+-------------+----------+----------------+----------+--------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+------------+-------------+---------------+-------------+----------+----------------+----------+--------------------+ | g28 | BUFG/O | n/a | clk62_5_ub | 16.000 | {0.000 8.000} | 114 | 0 | 0 | 1 | sys/clocks/userclk | +-----------+-----------------+-------------------+------------+-------------+---------------+-------------+----------+----------------+----------+--------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+------+ | | X0 | X1 | +----+----+------+ | Y7 | 0 | 0 | | Y6 | 0 | 0 | | Y5 | 0 | 0 | | Y4 | 0 | 0 | | Y3 | 0 | 0 | | Y2 | 0 | 115 | | Y1 | 0 | 0 | | Y0 | 0 | 0 | +----+----+------+ 36. Device Cell Placement Summary for Global Clock g29 ------------------------------------------------------ +-----------+-----------------+-------------------+------------------+-------------+----------------+-------------+----------+----------------+----------+----------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+------------------+-------------+----------------+-------------+----------+----------------+----------+----------------------+ | g29 | BUFGCTRL/O | n/a | fabric_clk_FBOUT | 24.951 | {0.000 12.476} | 28 | 0 | 0 | 0 | ngFEC/cdce_synch/CLK | +-----------+-----------------+-------------------+------------------+-------------+----------------+-------------+----------+----------------+----------+----------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+-----+----+ | | X0 | X1 | +----+-----+----+ | Y7 | 0 | 0 | | Y6 | 0 | 0 | | Y5 | 0 | 0 | | Y4 | 0 | 0 | | Y3 | 26 | 0 | | Y2 | 1 | 1 | | Y1 | 0 | 0 | | Y0 | 0 | 0 | +----+-----+----+ 37. Device Cell Placement Summary for Global Clock g30 ------------------------------------------------------ +-----------+-----------------+-------------------+------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------+ | g30 | BUFG/O | n/a | fabric_clk_PSOUT | 24.951 | {0.000 12.476} | 13 | 0 | 0 | 0 | ngFEC/fabric_clk_PS | +-----------+-----------------+-------------------+------------------+-------------+----------------+-------------+----------+----------------+----------+---------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+-----+ | | X0 | X1 | +----+----+-----+ | Y7 | 0 | 13 | | Y6 | 0 | 0 | | Y5 | 0 | 0 | | Y4 | 0 | 0 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | 0 | 0 | | Y0 | 0 | 0 | +----+----+-----+ 38. Device Cell Placement Summary for Global Clock g31 ------------------------------------------------------ +-----------+-----------------+-------------------+----------+-------------+---------------+-------------+----------+----------------+----------+---------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+----------+-------------+---------------+-------------+----------+----------------+----------+---------------------+ | g31 | BUFG/O | n/a | osc125_a | 8.000 | {0.000 4.000} | 9 | 0 | 1 | 1 | sys/osc125_a_bufg_0 | +-----------+-----------------+-------------------+----------+-------------+---------------+-------------+----------+----------------+----------+---------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+-----+ | | X0 | X1 | +----+----+-----+ | Y7 | 0 | 0 | | Y6 | 0 | 0 | | Y5 | 0 | 0 | | Y4 | 0 | 0 | | Y3 | 0 | 0 | | Y2 | 0 | 10 | | Y1 | 1 | 0 | | Y0 | 0 | 0 | +----+----+-----+ 39. Device Cell Placement Summary for Global Clock g32 ------------------------------------------------------ +-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------+ | g32 | BUFH/O | X0Y6 | ttc_mgt_xpoint_c | 8.333 | {0.000 4.167} | 9 | 0 | 0 | 0 | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 | +-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+--------+----+ | | X0 | X1 | +----+--------+----+ | Y7 | 0 | 0 | | Y6 | (D) 9 | 0 | | Y5 | 0 | 0 | | Y4 | 0 | 0 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | 0 | 0 | | Y0 | 0 | 0 | +----+--------+----+ 40. Device Cell Placement Summary for Global Clock g33 ------------------------------------------------------ +-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------+ | g33 | BUFH/O | X0Y6 | ttc_mgt_xpoint_c | 8.333 | {0.000 4.167} | 9 | 0 | 0 | 0 | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 | +-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+--------+----+ | | X0 | X1 | +----+--------+----+ | Y7 | 0 | 0 | | Y6 | (D) 9 | 0 | | Y5 | 0 | 0 | | Y4 | 0 | 0 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | 0 | 0 | | Y0 | 0 | 0 | +----+--------+----+ 41. Device Cell Placement Summary for Global Clock g34 ------------------------------------------------------ +-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------+ | g34 | BUFH/O | X0Y6 | ttc_mgt_xpoint_c | 8.333 | {0.000 4.167} | 9 | 0 | 0 | 0 | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 | +-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+--------+----+ | | X0 | X1 | +----+--------+----+ | Y7 | 0 | 0 | | Y6 | (D) 9 | 0 | | Y5 | 0 | 0 | | Y4 | 0 | 0 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | 0 | 0 | | Y0 | 0 | 0 | +----+--------+----+ 42. Device Cell Placement Summary for Global Clock g35 ------------------------------------------------------ +-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------+ | g35 | BUFH/O | X0Y6 | ttc_mgt_xpoint_c | 8.333 | {0.000 4.167} | 9 | 0 | 0 | 0 | ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 | +-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+--------+----+ | | X0 | X1 | +----+--------+----+ | Y7 | 0 | 0 | | Y6 | (D) 9 | 0 | | Y5 | 0 | 0 | | Y4 | 0 | 0 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | 0 | 0 | | Y0 | 0 | 0 | +----+--------+----+ 43. Device Cell Placement Summary for Global Clock g36 ------------------------------------------------------ +-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------+ | g36 | BUFH/O | X0Y6 | ttc_mgt_xpoint_c | 8.333 | {0.000 4.167} | 9 | 0 | 0 | 0 | ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 | +-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+--------+----+ | | X0 | X1 | +----+--------+----+ | Y7 | 0 | 0 | | Y6 | (D) 9 | 0 | | Y5 | 0 | 0 | | Y4 | 0 | 0 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | 0 | 0 | | Y0 | 0 | 0 | +----+--------+----+ 44. Device Cell Placement Summary for Global Clock g37 ------------------------------------------------------ +-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------+ | g37 | BUFH/O | X0Y6 | ttc_mgt_xpoint_c | 8.333 | {0.000 4.167} | 9 | 0 | 0 | 0 | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 | +-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+--------+----+ | | X0 | X1 | +----+--------+----+ | Y7 | 0 | 0 | | Y6 | (D) 9 | 0 | | Y5 | 0 | 0 | | Y4 | 0 | 0 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | 0 | 0 | | Y0 | 0 | 0 | +----+--------+----+ 45. Device Cell Placement Summary for Global Clock g38 ------------------------------------------------------ +-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------+ | g38 | BUFH/O | X0Y6 | ttc_mgt_xpoint_c | 8.333 | {0.000 4.167} | 9 | 0 | 0 | 0 | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 | +-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+--------+----+ | | X0 | X1 | +----+--------+----+ | Y7 | 0 | 0 | | Y6 | (D) 9 | 0 | | Y5 | 0 | 0 | | Y4 | 0 | 0 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | 0 | 0 | | Y0 | 0 | 0 | +----+--------+----+ 46. Device Cell Placement Summary for Global Clock g39 ------------------------------------------------------ +-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------+ | g39 | BUFH/O | X0Y6 | ttc_mgt_xpoint_c | 8.333 | {0.000 4.167} | 9 | 0 | 0 | 0 | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 | +-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+--------+----+ | | X0 | X1 | +----+--------+----+ | Y7 | 0 | 0 | | Y6 | (D) 9 | 0 | | Y5 | 0 | 0 | | Y4 | 0 | 0 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | 0 | 0 | | Y0 | 0 | 0 | +----+--------+----+ 47. Device Cell Placement Summary for Global Clock g40 ------------------------------------------------------ +-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------+ | g40 | BUFH/O | X1Y6 | ttc_mgt_xpoint_c | 8.333 | {0.000 4.167} | 7 | 0 | 0 | 0 | ngFEC/ttcMgtXpoint_from_ibufdsCGtxe2_buf | +-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+------------------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+--------+ | | X0 | X1 | +----+----+--------+ | Y7 | 0 | 0 | | Y6 | 0 | (D) 7 | | Y5 | 0 | 0 | | Y4 | 0 | 0 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | 0 | 0 | | Y0 | 0 | 0 | +----+----+--------+ 48. Device Cell Placement Summary for Global Clock g41 ------------------------------------------------------ +-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------+ | g41 | BUFH/O | X0Y1 | ttc_mgt_xpoint_a | 8.333 | {0.000 4.167} | 9 | 0 | 0 | 0 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 | +-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+--------+----+ | | X0 | X1 | +----+--------+----+ | Y7 | 0 | 0 | | Y6 | 0 | 0 | | Y5 | 0 | 0 | | Y4 | 0 | 0 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | (D) 9 | 0 | | Y0 | 0 | 0 | +----+--------+----+ 49. Device Cell Placement Summary for Global Clock g42 ------------------------------------------------------ +-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------+ | g42 | BUFH/O | X0Y1 | ttc_mgt_xpoint_a | 8.333 | {0.000 4.167} | 9 | 0 | 0 | 0 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 | +-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+--------+----+ | | X0 | X1 | +----+--------+----+ | Y7 | 0 | 0 | | Y6 | 0 | 0 | | Y5 | 0 | 0 | | Y4 | 0 | 0 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | (D) 9 | 0 | | Y0 | 0 | 0 | +----+--------+----+ 50. Device Cell Placement Summary for Global Clock g43 ------------------------------------------------------ +-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------+ | g43 | BUFH/O | X0Y1 | ttc_mgt_xpoint_a | 8.333 | {0.000 4.167} | 9 | 0 | 0 | 0 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 | +-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+--------+----+ | | X0 | X1 | +----+--------+----+ | Y7 | 0 | 0 | | Y6 | 0 | 0 | | Y5 | 0 | 0 | | Y4 | 0 | 0 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | (D) 9 | 0 | | Y0 | 0 | 0 | +----+--------+----+ 51. Device Cell Placement Summary for Global Clock g44 ------------------------------------------------------ +-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------+ | g44 | BUFH/O | X0Y1 | ttc_mgt_xpoint_a | 8.333 | {0.000 4.167} | 9 | 0 | 0 | 0 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 | +-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+-----------------------------------------------------------------------------------------------------------------------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+--------+----+ | | X0 | X1 | +----+--------+----+ | Y7 | 0 | 0 | | Y6 | 0 | 0 | | Y5 | 0 | 0 | | Y4 | 0 | 0 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | (D) 9 | 0 | | Y0 | 0 | 0 | +----+--------+----+ 52. Device Cell Placement Summary for Global Clock g45 ------------------------------------------------------ +-----------+-----------------+-------------------+------------------------------+-------------+----------------+-------------+----------+----------------+----------+-------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+------------------------------+-------------+----------------+-------------+----------+----------------+----------+-------------------------------------+ | g45 | BUFG/O | n/a | clk_o_40_08_phase_mon_mmcm_1 | 24.901 | {0.000 12.451} | 0 | 0 | 1 | 0 | ngFEC/dmdt_clk/mmcm1/U0/clk_i_40_08 | +-----------+-----------------+-------------------+------------------------------+-------------+----------------+-------------+----------+----------------+----------+-------------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+----+ | | X0 | X1 | +----+----+----+ | Y7 | 1 | 0 | | Y6 | 0 | 0 | | Y5 | 0 | 0 | | Y4 | 0 | 0 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | 0 | 0 | | Y0 | 0 | 0 | +----+----+----+ 53. Device Cell Placement Summary for Global Clock g46 ------------------------------------------------------ +-----------+-----------------+-------------------+---------------------------+-------------+----------------+-------------+----------+----------------+----------+-------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+---------------------------+-------------+----------------+-------------+----------+----------------+----------+-------------------------------------------------------+ | g46 | BUFG/O | n/a | clkfbout_phase_mon_mmcm_2 | 74.704 | {0.000 37.352} | 0 | 0 | 1 | 0 | ngFEC/dmdt_clk/mmcm2/U0/clkfbout_buf_phase_mon_mmcm_2 | +-----------+-----------------+-------------------+---------------------------+-------------+----------------+-------------+----------+----------------+----------+-------------------------------------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+----+ | | X0 | X1 | +----+----+----+ | Y7 | 1 | 0 | | Y6 | 0 | 0 | | Y5 | 0 | 0 | | Y4 | 0 | 0 | | Y3 | 0 | 0 | | Y2 | 0 | 0 | | Y1 | 0 | 0 | | Y0 | 0 | 0 | +----+----+----+ 54. Clock Region Cell Placement per Global Clock: Region X0Y0 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------+ | g0 | n/a | BUFG/O | None | 7701 | 0 | 7644 | 0 | 57 | 0 | 0 | 0 | 0 | 0 | sys/clocks/ipb_clk_i | | g1 | n/a | BUFG/O | None | 2300 | 0 | 2296 | 2 | 0 | 0 | 0 | 1 | 0 | 0 | ngFEC/CLKFBIN | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 55. Clock Region Cell Placement per Global Clock: Region X1Y0 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------+ | g0 | n/a | BUFG/O | None | 7767 | 0 | 7714 | 0 | 53 | 0 | 0 | 0 | 0 | 0 | sys/clocks/ipb_clk_i | | g1 | n/a | BUFG/O | None | 4341 | 0 | 4338 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | ngFEC/CLKFBIN | | g23 | n/a | BUFG/O | None | 171 | 0 | 170 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 56. Clock Region Cell Placement per Global Clock: Region X0Y1 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | n/a | BUFG/O | None | 8026 | 0 | 7970 | 0 | 56 | 0 | 0 | 0 | 0 | 0 | sys/clocks/ipb_clk_i | | g1 | n/a | BUFG/O | None | 3149 | 0 | 3149 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ngFEC/CLKFBIN | | g2 | n/a | BUFG/O | None | 109 | 0 | 107 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | sys/clocks/PLLE2_BASE_inst_0 | | g31 | n/a | BUFG/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | sys/osc125_a_bufg_0 | | g41 | n/a | BUFH/O | None | 9 | 0 | 2 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 | | g42 | n/a | BUFH/O | None | 9 | 0 | 2 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 | | g43 | n/a | BUFH/O | None | 9 | 0 | 2 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 | | g44 | n/a | BUFH/O | None | 9 | 0 | 2 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-----------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 57. Clock Region Cell Placement per Global Clock: Region X1Y1 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-------------------------------------------------------------------+ | g0 | n/a | BUFG/O | None | 4890 | 0 | 4848 | 0 | 42 | 0 | 0 | 0 | 0 | 0 | sys/clocks/ipb_clk_i | | g1 | n/a | BUFG/O | None | 3245 | 0 | 3240 | 0 | 1 | 0 | 4 | 0 | 0 | 0 | ngFEC/CLKFBIN | | g2 | n/a | BUFG/O | None | 9 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | sys/clocks/PLLE2_BASE_inst_0 | | g11 | n/a | BUFH/O | None | 1054 | 2 | 1052 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/CLK | | g12 | n/a | BUFH/O | None | 1054 | 2 | 1052 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out | | g13 | n/a | BUFH/O | None | 1054 | 2 | 1052 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_0 | | g14 | n/a | BUFH/O | None | 1054 | 2 | 1052 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_1 | | g23 | n/a | BUFG/O | None | 11 | 0 | 10 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out | | g24 | n/a | BUFG/O | None | 182 | 0 | 180 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 | | g25 | n/a | BUFG/O | None | 35 | 0 | 34 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1 | | g26 | n/a | BUFG/O | None | 182 | 0 | 180 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_2 | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 58. Clock Region Cell Placement per Global Clock: Region X0Y2 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------+ | g0 | n/a | BUFG/O | None | 7544 | 0 | 7486 | 0 | 58 | 0 | 0 | 0 | 0 | 0 | sys/clocks/ipb_clk_i | | g1 | n/a | BUFG/O | None | 2330 | 0 | 2329 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | ngFEC/CLKFBIN | | g2 | n/a | BUFG/O | None | 2745 | 0 | 2687 | 40 | 18 | 0 | 0 | 0 | 0 | 0 | sys/clocks/PLLE2_BASE_inst_0 | | g29 | n/a | BUFGCTRL/O | None | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ngFEC/cdce_synch/CLK | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 59. Clock Region Cell Placement per Global Clock: Region X1Y2 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-------------------------------------------------------------------+ | g0 | n/a | BUFG/O | None | 8348 | 0 | 8293 | 1 | 54 | 0 | 0 | 0 | 0 | 0 | sys/clocks/ipb_clk_i | | g1 | n/a | BUFG/O | None | 3351 | 0 | 3350 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | ngFEC/CLKFBIN | | g2 | n/a | BUFG/O | None | 1005 | 0 | 985 | 17 | 2 | 0 | 1 | 0 | 0 | 0 | sys/clocks/PLLE2_BASE_inst_0 | | g25 | n/a | BUFG/O | None | 147 | 0 | 146 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1 | | g28 | n/a | BUFG/O | None | 115 | 0 | 114 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | sys/clocks/userclk | | g29 | n/a | BUFGCTRL/O | None | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ngFEC/cdce_synch/CLK | | g31 | n/a | BUFG/O | None | 10 | 0 | 2 | 7 | 0 | 0 | 1 | 0 | 0 | 0 | sys/osc125_a_bufg_0 | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+-------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 60. Clock Region Cell Placement per Global Clock: Region X0Y3 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------+ | g0 | n/a | BUFG/O | None | 7388 | 0 | 7333 | 0 | 54 | 0 | 0 | 0 | 0 | 0 | sys/clocks/ipb_clk_i | | g1 | n/a | BUFG/O | None | 2751 | 0 | 2750 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | ngFEC/CLKFBIN | | g2 | n/a | BUFG/O | None | 30 | 0 | 29 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | sys/clocks/PLLE2_BASE_inst_0 | | g29 | n/a | BUFGCTRL/O | None | 26 | 0 | 26 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ngFEC/cdce_synch/CLK | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 61. Clock Region Cell Placement per Global Clock: Region X1Y3 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------------------------------------------+ | g0 | n/a | BUFG/O | None | 7859 | 0 | 7813 | 0 | 46 | 0 | 0 | 0 | 0 | 0 | sys/clocks/ipb_clk_i | | g1 | n/a | BUFG/O | None | 3348 | 0 | 3347 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | ngFEC/CLKFBIN | | g2 | n/a | BUFG/O | None | 9 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | sys/clocks/PLLE2_BASE_inst_0 | | g22 | n/a | BUFG/O | None | 125 | 0 | 125 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1 | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 62. Clock Region Cell Placement per Global Clock: Region X0Y4 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------+ | g0 | n/a | BUFG/O | None | 6410 | 0 | 6363 | 0 | 47 | 0 | 0 | 0 | 0 | 0 | sys/clocks/ipb_clk_i | | g1 | n/a | BUFG/O | None | 2315 | 0 | 2314 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | ngFEC/CLKFBIN | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 63. Clock Region Cell Placement per Global Clock: Region X1Y4 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------------------------------------------+ | g0 | n/a | BUFG/O | None | 6487 | 0 | 6450 | 2 | 35 | 0 | 0 | 0 | 0 | 0 | sys/clocks/ipb_clk_i | | g1 | n/a | BUFG/O | None | 4271 | 2 | 4270 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | ngFEC/CLKFBIN | | g2 | n/a | BUFG/O | None | 116 | 0 | 116 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | sys/clocks/PLLE2_BASE_inst_0 | | g15 | n/a | BUFG/O | None | 152 | 0 | 151 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out | | g16 | n/a | BUFG/O | None | 148 | 0 | 147 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out | | g19 | n/a | BUFG/O | None | 148 | 0 | 147 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 | | g20 | n/a | BUFG/O | None | 148 | 0 | 147 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out | | g21 | n/a | BUFG/O | None | 177 | 0 | 176 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 | | g22 | n/a | BUFG/O | None | 23 | 0 | 22 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1 | | g27 | n/a | BUFG/O | None | 139 | 0 | 139 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ngFEC/dmdt_clk/mmcm2/U0/dmdt_phase_meas_clk | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 64. Clock Region Cell Placement per Global Clock: Region X0Y5 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------+ | g0 | n/a | BUFG/O | None | 5825 | 0 | 5784 | 0 | 41 | 0 | 0 | 0 | 0 | 0 | sys/clocks/ipb_clk_i | | g1 | n/a | BUFG/O | None | 2601 | 0 | 2600 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | ngFEC/CLKFBIN | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 65. Clock Region Cell Placement per Global Clock: Region X1Y5 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------------------------------------------+ | g0 | n/a | BUFG/O | None | 3069 | 0 | 3038 | 14 | 17 | 0 | 0 | 0 | 0 | 0 | sys/clocks/ipb_clk_i | | g1 | n/a | BUFG/O | None | 3616 | 0 | 3611 | 1 | 1 | 0 | 3 | 0 | 0 | 0 | ngFEC/CLKFBIN | | g2 | n/a | BUFG/O | None | 624 | 0 | 624 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | sys/clocks/PLLE2_BASE_inst_0 | | g8 | n/a | BUFH/O | None | 1054 | 0 | 1052 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/CLK | | g9 | n/a | BUFH/O | None | 1054 | 0 | 1052 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out | | g10 | n/a | BUFH/O | None | 1054 | 0 | 1052 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_0 | | g15 | n/a | BUFG/O | None | 28 | 0 | 28 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out | | g17 | n/a | BUFG/O | None | 186 | 0 | 185 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 | | g18 | n/a | BUFG/O | None | 186 | 0 | 185 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1 | | g20 | n/a | BUFG/O | None | 72 | 0 | 71 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out | | g21 | n/a | BUFG/O | None | 43 | 0 | 42 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 | | g22 | n/a | BUFG/O | None | 72 | 0 | 71 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1 | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 66. Clock Region Cell Placement per Global Clock: Region X0Y6 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------+ | g0 | n/a | BUFG/O | None | 12 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | sys/clocks/ipb_clk_i | | g1 | n/a | BUFG/O | None | 24 | 0 | 23 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | ngFEC/CLKFBIN | | g32 | n/a | BUFH/O | None | 9 | 0 | 2 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 | | g33 | n/a | BUFH/O | None | 9 | 0 | 2 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 | | g34 | n/a | BUFH/O | None | 9 | 0 | 2 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 | | g35 | n/a | BUFH/O | None | 9 | 0 | 2 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 | | g36 | n/a | BUFH/O | None | 9 | 0 | 2 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 | | g37 | n/a | BUFH/O | None | 9 | 0 | 2 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 | | g38 | n/a | BUFH/O | None | 9 | 0 | 2 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 | | g39 | n/a | BUFH/O | None | 9 | 0 | 2 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0 | +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+------------------------------------------------------------------------------------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 67. Clock Region Cell Placement per Global Clock: Region X1Y6 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------------------------------------------+ | g0 | n/a | BUFG/O | None | 242 | 0 | 242 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | sys/clocks/ipb_clk_i | | g1 | n/a | BUFG/O | None | 1104 | 3 | 1103 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | ngFEC/CLKFBIN | | g6 | n/a | BUFH/O | None | 1054 | 2 | 1052 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/CLK | | g7 | n/a | BUFH/O | None | 1054 | 0 | 1052 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out | | g15 | n/a | BUFG/O | None | 44 | 0 | 43 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out | | g16 | n/a | BUFG/O | None | 71 | 0 | 71 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out | | g19 | n/a | BUFG/O | None | 72 | 0 | 71 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 | | g23 | n/a | BUFG/O | None | 38 | 0 | 38 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out | | g24 | n/a | BUFG/O | None | 38 | 0 | 38 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 | | g25 | n/a | BUFG/O | None | 38 | 0 | 38 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1 | | g26 | n/a | BUFG/O | None | 38 | 0 | 38 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_2 | | g40 | n/a | BUFH/O | None | 5 | 2 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ngFEC/ttcMgtXpoint_from_ibufdsCGtxe2_buf | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 68. Clock Region Cell Placement per Global Clock: Region X0Y7 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------------------------------------------+ | g45 | n/a | BUFG/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | ngFEC/dmdt_clk/mmcm1/U0/clk_i_40_08 | | g46 | n/a | BUFG/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | ngFEC/dmdt_clk/mmcm2/U0/clkfbout_buf_phase_mon_mmcm_2 | +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 69. Clock Region Cell Placement per Global Clock: Region X1Y7 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------------------------------------------+ | g1 | n/a | BUFG/O | None | 649 | 1 | 647 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | ngFEC/CLKFBIN | | g2 | n/a | BUFG/O | None | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | sys/clocks/PLLE2_BASE_inst_0 | | g3 | n/a | BUFH/O | None | 1054 | 2 | 1052 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/CLK | | g4 | n/a | BUFH/O | None | 1054 | 2 | 1052 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out | | g5 | n/a | BUFH/O | None | 1054 | 2 | 1052 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_0 | | g16 | n/a | BUFG/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out | | g17 | n/a | BUFG/O | None | 34 | 0 | 33 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0 | | g18 | n/a | BUFG/O | None | 34 | 0 | 33 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1 | | g27 | n/a | BUFG/O | None | 6 | 0 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ngFEC/dmdt_clk/mmcm2/U0/dmdt_phase_meas_clk | | g30 | n/a | BUFG/O | None | 13 | 0 | 13 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ngFEC/fabric_clk_PS | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+--------------------------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts # Location of BUFG Primitives set_property LOC BUFGCTRL_X0Y8 [get_cells sys/osc125a_clkbuf] set_property LOC BUFGCTRL_X0Y7 [get_cells sys/clocks/clk62_5_buf] set_property LOC BUFGCTRL_X0Y9 [get_cells sys/clocks/clk_ipb_buf] set_property LOC BUFGCTRL_X0Y2 [get_cells sys/clocks/clk125_buf] set_property LOC BUFGCTRL_X0Y6 [get_cells ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg] set_property LOC BUFGCTRL_X0Y5 [get_cells ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg] set_property LOC BUFGCTRL_X0Y4 [get_cells ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg] set_property LOC BUFGCTRL_X0Y3 [get_cells ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg] set_property LOC BUFGCTRL_X0Y23 [get_cells ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg] set_property LOC BUFGCTRL_X0Y22 [get_cells ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg] set_property LOC BUFGCTRL_X0Y21 [get_cells ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg] set_property LOC BUFGCTRL_X0Y20 [get_cells ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg] set_property LOC BUFGCTRL_X0Y16 [get_cells ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg] set_property LOC BUFGCTRL_X0Y19 [get_cells ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg] set_property LOC BUFGCTRL_X0Y18 [get_cells ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg] set_property LOC BUFGCTRL_X0Y17 [get_cells ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg] set_property LOC BUFGCTRL_X0Y10 [get_cells ngFEC/fabric_clk_PS_bufg] set_property LOC BUFGCTRL_X0Y24 [get_cells ngFEC/dmdt_clk/mmcm2/U0/clkout1_buf] set_property LOC BUFGCTRL_X0Y26 [get_cells ngFEC/dmdt_clk/mmcm2/U0/clkf_buf] set_property LOC BUFGCTRL_X0Y25 [get_cells ngFEC/dmdt_clk/mmcm1/U0/clkout1_buf] set_property LOC BUFGCTRL_X0Y1 [get_cells ngFEC/cdce_synch/bufg_mux] set_property LOC BUFGCTRL_X0Y0 [get_cells ngFEC/fclk_bufg] # Location of BUFH Primitives set_property LOC BUFHCE_X1Y74 [get_cells ngFEC/i_ttcMgtXpoint_from_ibufdsCGtxe2_buf] set_property LOC BUFHCE_X0Y15 [get_cells ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf] set_property LOC BUFHCE_X0Y14 [get_cells ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf] set_property LOC BUFHCE_X0Y13 [get_cells ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf] set_property LOC BUFHCE_X0Y12 [get_cells ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf] set_property LOC BUFHCE_X1Y15 [get_cells ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg] set_property LOC BUFHCE_X1Y14 [get_cells ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg] set_property LOC BUFHCE_X1Y13 [get_cells ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg] set_property LOC BUFHCE_X1Y12 [get_cells ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg] set_property LOC BUFHCE_X0Y79 [get_cells ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf] set_property LOC BUFHCE_X0Y78 [get_cells ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf] set_property LOC BUFHCE_X0Y77 [get_cells ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf] set_property LOC BUFHCE_X1Y62 [get_cells ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg] set_property LOC BUFHCE_X1Y61 [get_cells ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg] set_property LOC BUFHCE_X1Y60 [get_cells ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg] set_property LOC BUFHCE_X0Y76 [get_cells ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf] set_property LOC BUFHCE_X0Y75 [get_cells ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf] set_property LOC BUFHCE_X1Y73 [get_cells ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg] set_property LOC BUFHCE_X1Y72 [get_cells ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg] set_property LOC BUFHCE_X0Y74 [get_cells ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf] set_property LOC BUFHCE_X0Y73 [get_cells ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf] set_property LOC BUFHCE_X0Y72 [get_cells ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf] set_property LOC BUFHCE_X1Y86 [get_cells ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg] set_property LOC BUFHCE_X1Y85 [get_cells ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg] set_property LOC BUFHCE_X1Y84 [get_cells ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg] # Location of IO Primitives which is load of clock spine # Location of clock ports set_property LOC IOB_X0Y23 [get_ports fabric_clk_n] set_property LOC IOB_X0Y24 [get_ports fabric_clk_p] set_property LOC IPAD_X1Y71 [get_ports osc125_a_n] set_property LOC IPAD_X1Y70 [get_ports osc125_a_p] set_property LOC IPAD_X1Y41 [get_ports ttc_mgt_xpoint_a_n] set_property LOC IPAD_X1Y40 [get_ports ttc_mgt_xpoint_a_p] set_property LOC IPAD_X1Y197 [get_ports ttc_mgt_xpoint_c_n] set_property LOC IPAD_X1Y196 [get_ports ttc_mgt_xpoint_c_p] # Clock net "sys/osc125_a_bufg_0" driven by instance "sys/osc125a_clkbuf" located at site "BUFGCTRL_X0Y8" #startgroup create_pblock {CLKAG_sys/osc125_a_bufg_0} add_cells_to_pblock [get_pblocks {CLKAG_sys/osc125_a_bufg_0}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL && NAME!=sys/clocks/PLLE2_BASE_inst} -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="sys/osc125_a_bufg_0"}]]] resize_pblock [get_pblocks {CLKAG_sys/osc125_a_bufg_0}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "sys/clocks/userclk" driven by instance "sys/clocks/clk62_5_buf" located at site "BUFGCTRL_X0Y7" #startgroup create_pblock {CLKAG_sys/clocks/userclk} add_cells_to_pblock [get_pblocks {CLKAG_sys/clocks/userclk}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="sys/clocks/userclk"}]]] resize_pblock [get_pblocks {CLKAG_sys/clocks/userclk}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "sys/clocks/ipb_clk_i" driven by instance "sys/clocks/clk_ipb_buf" located at site "BUFGCTRL_X0Y9" #startgroup create_pblock {CLKAG_sys/clocks/ipb_clk_i} add_cells_to_pblock [get_pblocks {CLKAG_sys/clocks/ipb_clk_i}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="sys/clocks/ipb_clk_i"}]]] resize_pblock [get_pblocks {CLKAG_sys/clocks/ipb_clk_i}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "sys/clocks/PLLE2_BASE_inst_0" driven by instance "sys/clocks/clk125_buf" located at site "BUFGCTRL_X0Y2" #startgroup create_pblock {CLKAG_sys/clocks/PLLE2_BASE_inst_0} add_cells_to_pblock [get_pblocks {CLKAG_sys/clocks/PLLE2_BASE_inst_0}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL && NAME!=sys/clocks/PLLE2_BASE_inst} -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="sys/clocks/PLLE2_BASE_inst_0"}]]] resize_pblock [get_pblocks {CLKAG_sys/clocks/PLLE2_BASE_inst_0}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/ttcMgtXpoint_from_ibufdsCGtxe2_buf" driven by instance "ngFEC/i_ttcMgtXpoint_from_ibufdsCGtxe2_buf" located at site "BUFHCE_X1Y74" #startgroup create_pblock {CLKAG_ngFEC/ttcMgtXpoint_from_ibufdsCGtxe2_buf} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/ttcMgtXpoint_from_ibufdsCGtxe2_buf}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/ttcMgtXpoint_from_ibufdsCGtxe2_buf"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/ttcMgtXpoint_from_ibufdsCGtxe2_buf}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0" driven by instance "ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf" located at site "BUFHCE_X0Y15" #startgroup create_pblock {CLKAG_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0" driven by instance "ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf" located at site "BUFHCE_X0Y14" #startgroup create_pblock {CLKAG_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0" driven by instance "ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf" located at site "BUFHCE_X0Y13" #startgroup create_pblock {CLKAG_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0" driven by instance "ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf" located at site "BUFHCE_X0Y12" #startgroup create_pblock {CLKAG_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_2" driven by instance "ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].txWordClkBufg" located at site "BUFGCTRL_X0Y6" #startgroup create_pblock {CLKAG_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_2} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_2}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_2"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_2}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1" driven by instance "ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg" located at site "BUFGCTRL_X0Y5" #startgroup create_pblock {CLKAG_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0" driven by instance "ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg" located at site "BUFGCTRL_X0Y4" #startgroup create_pblock {CLKAG_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out" driven by instance "ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg" located at site "BUFGCTRL_X0Y3" #startgroup create_pblock {CLKAG_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_1" driven by instance "ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].rxWordClkBufg" located at site "BUFHCE_X1Y15" #startgroup create_pblock {CLKAG_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_1} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_1}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_1"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_1}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_0" driven by instance "ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg" located at site "BUFHCE_X1Y14" #startgroup create_pblock {CLKAG_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_0} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_0}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_0"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_0}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out" driven by instance "ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg" located at site "BUFHCE_X1Y13" #startgroup create_pblock {CLKAG_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/CLK" driven by instance "ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg" located at site "BUFHCE_X1Y12" #startgroup create_pblock {CLKAG_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/CLK} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/CLK}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/CLK"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/CLK}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0" driven by instance "ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf" located at site "BUFHCE_X0Y79" #startgroup create_pblock {CLKAG_ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0" driven by instance "ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf" located at site "BUFHCE_X0Y78" #startgroup create_pblock {CLKAG_ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0" driven by instance "ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf" located at site "BUFHCE_X0Y77" #startgroup create_pblock {CLKAG_ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1" driven by instance "ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg" located at site "BUFGCTRL_X0Y23" #startgroup create_pblock {CLKAG_ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0" driven by instance "ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg" located at site "BUFGCTRL_X0Y22" #startgroup create_pblock {CLKAG_ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out" driven by instance "ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg" located at site "BUFGCTRL_X0Y21" #startgroup create_pblock {CLKAG_ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_0" driven by instance "ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg" located at site "BUFHCE_X1Y62" #startgroup create_pblock {CLKAG_ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_0} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_0}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_0"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_0}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out" driven by instance "ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg" located at site "BUFHCE_X1Y61" #startgroup create_pblock {CLKAG_ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/CLK" driven by instance "ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg" located at site "BUFHCE_X1Y60" #startgroup create_pblock {CLKAG_ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/CLK} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/CLK}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/CLK"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/CLK}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0" driven by instance "ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf" located at site "BUFHCE_X0Y76" #startgroup create_pblock {CLKAG_ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0" driven by instance "ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf" located at site "BUFHCE_X0Y75" #startgroup create_pblock {CLKAG_ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0" driven by instance "ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg" located at site "BUFGCTRL_X0Y20" #startgroup create_pblock {CLKAG_ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out" driven by instance "ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg" located at site "BUFGCTRL_X0Y16" #startgroup create_pblock {CLKAG_ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out" driven by instance "ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg" located at site "BUFHCE_X1Y73" #startgroup create_pblock {CLKAG_ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/CLK" driven by instance "ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg" located at site "BUFHCE_X1Y72" #startgroup create_pblock {CLKAG_ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/CLK} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/CLK}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/CLK"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/CLK}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0" driven by instance "ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf" located at site "BUFHCE_X0Y74" #startgroup create_pblock {CLKAG_ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0" driven by instance "ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf" located at site "BUFHCE_X0Y73" #startgroup create_pblock {CLKAG_ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0" driven by instance "ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf" located at site "BUFHCE_X0Y72" #startgroup create_pblock {CLKAG_ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/cpll_railing0_i/use_bufh_cpll.refclk_buf_n_0}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1" driven by instance "ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].txWordClkBufg" located at site "BUFGCTRL_X0Y19" #startgroup create_pblock {CLKAG_ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_1}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0" driven by instance "ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].txWordClkBufg" located at site "BUFGCTRL_X0Y18" #startgroup create_pblock {CLKAG_ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out_0}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out" driven by instance "ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].txWordClkBufg" located at site "BUFGCTRL_X0Y17" #startgroup create_pblock {CLKAG_ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_txoutclk_out}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_0" driven by instance "ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].rxWordClkBufg" located at site "BUFHCE_X1Y86" #startgroup create_pblock {CLKAG_ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_0} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_0}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_0"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out_0}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out" driven by instance "ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].rxWordClkBufg" located at site "BUFHCE_X1Y85" #startgroup create_pblock {CLKAG_ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/bbstub_gt0_rxoutclk_out}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/CLK" driven by instance "ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].rxWordClkBufg" located at site "BUFHCE_X1Y84" #startgroup create_pblock {CLKAG_ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/CLK} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/CLK}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/CLK"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/CLK}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/fabric_clk_PS" driven by instance "ngFEC/fabric_clk_PS_bufg" located at site "BUFGCTRL_X0Y10" #startgroup create_pblock {CLKAG_ngFEC/fabric_clk_PS} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/fabric_clk_PS}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/fabric_clk_PS"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/fabric_clk_PS}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/dmdt_clk/mmcm2/U0/dmdt_phase_meas_clk" driven by instance "ngFEC/dmdt_clk/mmcm2/U0/clkout1_buf" located at site "BUFGCTRL_X0Y24" #startgroup create_pblock {CLKAG_ngFEC/dmdt_clk/mmcm2/U0/dmdt_phase_meas_clk} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/dmdt_clk/mmcm2/U0/dmdt_phase_meas_clk}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/dmdt_clk/mmcm2/U0/dmdt_phase_meas_clk"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/dmdt_clk/mmcm2/U0/dmdt_phase_meas_clk}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/cdce_synch/CLK" driven by instance "ngFEC/cdce_synch/bufg_mux" located at site "BUFGCTRL_X0Y1" #startgroup create_pblock {CLKAG_ngFEC/cdce_synch/CLK} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/cdce_synch/CLK}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/cdce_synch/CLK"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/cdce_synch/CLK}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup # Clock net "ngFEC/CLKFBIN" driven by instance "ngFEC/fclk_bufg" located at site "BUFGCTRL_X0Y0" #startgroup create_pblock {CLKAG_ngFEC/CLKFBIN} add_cells_to_pblock [get_pblocks {CLKAG_ngFEC/CLKFBIN}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL && NAME!=ngFEC/fabric_clk_MMCME2 && NAME!=ngFEC/dmdt_clk/mmcm1/U0/mmcm_adv_inst && NAME!=ngFEC/cdce_synch/bufg_mux} -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="ngFEC/CLKFBIN"}]]] resize_pblock [get_pblocks {CLKAG_ngFEC/CLKFBIN}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4 CLOCKREGION_X0Y5:CLOCKREGION_X0Y5 CLOCKREGION_X0Y6:CLOCKREGION_X0Y6 CLOCKREGION_X0Y7:CLOCKREGION_X0Y7 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2 CLOCKREGION_X1Y3:CLOCKREGION_X1Y3 CLOCKREGION_X1Y4:CLOCKREGION_X1Y4 CLOCKREGION_X1Y5:CLOCKREGION_X1Y5 CLOCKREGION_X1Y6:CLOCKREGION_X1Y6 CLOCKREGION_X1Y7:CLOCKREGION_X1Y7} #endgroup