#----------------------------------------------------------- # Vivado v2018.3 (64-bit) # SW Build 2405991 on Thu Dec 6 23:38:27 MST 2018 # IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 # Start of session at: Mon May 18 09:12:49 2020 # Process ID: 17772 # Current directory: D:/Design_collection/ngFECv0x43d/ngFEC_new.runs/impl_1 # Command line: vivado.exe -log fc7_top.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source fc7_top.tcl -notrace # Log file: D:/Design_collection/ngFECv0x43d/ngFEC_new.runs/impl_1/fc7_top.vdi # Journal file: D:/Design_collection/ngFECv0x43d/ngFEC_new.runs/impl_1\vivado.jou #----------------------------------------------------------- source fc7_top.tcl -notrace Command: link_design -top fc7_top -part xc7k420tffg1156-2 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Project 1-454] Reading design checkpoint 'd:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt.dcp' for cell 'ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst' INFO: [Project 1-454] Reading design checkpoint 'd:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/gig_ethernet_pcs_pma_16_1.dcp' for cell 'sys/eth/phy' INFO: [Netlist 29-17] Analyzing 16229 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2018.3 INFO: [Device 21-403] Loading part xc7k420tffg1156-2 INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt.xdc] for cell 'ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0' Finished Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt.xdc] for cell 'ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0' Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt.xdc] for cell 'ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0' Finished Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt.xdc] for cell 'ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0' Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt.xdc] for cell 'ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0' Finished Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt.xdc] for cell 'ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0' Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt.xdc] for cell 'ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0' Finished Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt.xdc] for cell 'ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0' Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt.xdc] for cell 'ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0' Finished Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt.xdc] for cell 'ngFEC/gbtbank2_l12_117/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0' Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt.xdc] for cell 'ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0' Finished Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt.xdc] for cell 'ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0' Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt.xdc] for cell 'ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0' Finished Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt.xdc] for cell 'ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0' Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt.xdc] for cell 'ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0' Finished Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt.xdc] for cell 'ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0' Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt.xdc] for cell 'ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0' Finished Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt.xdc] for cell 'ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0' Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt.xdc] for cell 'ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0' Finished Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt.xdc] for cell 'ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0' Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt.xdc] for cell 'ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0' Finished Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt.xdc] for cell 'ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0' Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt.xdc] for cell 'ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0' Finished Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt.xdc] for cell 'ngFEC/gbtbank4_l8_112/gbt_inst/mgt_inst/gtxLatOpt_gen[4].xlx_k7v7_mgt_latopt_inst/U0' Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/gig_ethernet_pcs_pma_16_1_board.xdc] for cell 'sys/eth/phy/U0' Finished Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/gig_ethernet_pcs_pma_16_1_board.xdc] for cell 'sys/eth/phy/U0' Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1.xdc] for cell 'sys/eth/phy/U0' Finished Parsing XDC File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1.xdc] for cell 'sys/eth/phy/U0' Parsing XDC File [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/xdc/sys.xdc] Finished Parsing XDC File [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/xdc/sys.xdc] Parsing XDC File [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/xdc/user_io.xdc] Finished Parsing XDC File [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/xdc/user_io.xdc] Parsing XDC File [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/vproject/ngFEC_new/ngFEC_new.srcs/sources_1/new/usr_clkX12.xdc] INFO: [Timing 38-35] Done setting XDC timing constraints. [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/vproject/ngFEC_new/ngFEC_new.srcs/sources_1/new/usr_clkX12.xdc:67] INFO: [Timing 38-2] Deriving generated clocks [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/vproject/ngFEC_new/ngFEC_new.srcs/sources_1/new/usr_clkX12.xdc:67] get_clocks: Time (s): cpu = 00:00:38 ; elapsed = 00:00:28 . Memory (MB): peak = 2748.000 ; gain = 965.199 Finished Parsing XDC File [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/vproject/ngFEC_new/ngFEC_new.srcs/sources_1/new/usr_clkX12.xdc] Parsing XDC File [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/xdc/usr_io_fmc.xdc] Finished Parsing XDC File [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/xdc/usr_io_fmc.xdc] Parsing XDC File [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/xdc/usr_mgt_fmcX12.xdc] Finished Parsing XDC File [D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/constrs_1/imports/fc7half/HB_HE_FC7/fw/src/ngFEC/xdc/usr_mgt_fmcX12.xdc] Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[1].phase_mon/sample_PS_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[1].phase_mon/sample_PS_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank1_l12_118/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank2_l12_117/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank3_l12_116/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/xpm_cdc_single_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[4].gbt_txgearbox_inst/xpm_cdc_single_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[3].gbt_txgearbox_inst/xpm_cdc_single_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[2].gbt_txgearbox_inst/xpm_cdc_single_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/gbtbank4_l8_112/gbt_inst/gbt_txgearbox_multilink_gen[1].gbt_txgearbox_inst/xpm_cdc_single_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[12].phase_mon/fabric_clk_PS_toggle_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[12].phase_mon/fabric_clk_PS_toggle_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[12].phase_mon/sample_PS_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[12].phase_mon/sample_PS_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[11].phase_mon/fabric_clk_PS_toggle_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[11].phase_mon/sample_PS_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[11].phase_mon/sample_PS_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[10].phase_mon/fabric_clk_PS_toggle_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[10].phase_mon/sample_PS_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[10].phase_mon/sample_PS_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[9].phase_mon/fabric_clk_PS_toggle_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[9].phase_mon/fabric_clk_PS_toggle_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[9].phase_mon/sample_PS_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[9].phase_mon/sample_PS_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[8].phase_mon/fabric_clk_PS_toggle_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[8].phase_mon/fabric_clk_PS_toggle_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[8].phase_mon/sample_PS_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[8].phase_mon/sample_PS_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[7].phase_mon/fabric_clk_PS_toggle_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[7].phase_mon/sample_PS_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[7].phase_mon/sample_PS_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[6].phase_mon/fabric_clk_PS_toggle_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[6].phase_mon/sample_PS_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[6].phase_mon/sample_PS_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[5].phase_mon/fabric_clk_PS_toggle_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[5].phase_mon/sample_PS_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[5].phase_mon/sample_PS_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[4].phase_mon/fabric_clk_PS_toggle_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[4].phase_mon/sample_PS_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[4].phase_mon/sample_PS_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[3].phase_mon/fabric_clk_PS_toggle_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[3].phase_mon/fabric_clk_PS_toggle_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[3].phase_mon/sample_PS_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[3].phase_mon/sample_PS_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[2].phase_mon/fabric_clk_PS_toggle_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[2].phase_mon/sample_PS_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[2].phase_mon/sample_PS_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_pm[1].phase_mon/fabric_clk_PS_toggle_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[0].rx_frameclk_lock_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[0].rx_frameclk_lock_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[1].rx_frameclk_lock_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[1].rx_frameclk_lock_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[2].rx_frameclk_lock_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[2].rx_frameclk_lock_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[3].rx_frameclk_lock_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[3].rx_frameclk_lock_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[4].rx_frameclk_lock_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[4].rx_frameclk_lock_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[5].rx_frameclk_lock_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[5].rx_frameclk_lock_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[6].rx_frameclk_lock_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[6].rx_frameclk_lock_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[7].rx_frameclk_lock_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[7].rx_frameclk_lock_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[8].rx_frameclk_lock_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[8].rx_frameclk_lock_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[9].rx_frameclk_lock_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[9].rx_frameclk_lock_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[10].rx_frameclk_lock_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[10].rx_frameclk_lock_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[11].rx_frameclk_lock_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_rx_frameclk_lock_cnt[11].rx_frameclk_lock_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[0].tx_ready_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[0].tx_ready_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[1].tx_ready_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[1].tx_ready_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[2].tx_ready_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[2].tx_ready_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[3].tx_ready_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[3].tx_ready_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[4].tx_ready_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[4].tx_ready_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[5].tx_ready_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[5].tx_ready_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[6].tx_ready_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[6].tx_ready_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[7].tx_ready_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[7].tx_ready_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[8].tx_ready_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[8].tx_ready_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[9].tx_ready_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[9].tx_ready_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[10].tx_ready_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[10].tx_ready_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[11].tx_ready_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/g_tx_ready_cnt[11].tx_ready_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[8].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[7].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[6].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[5].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[4].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[3].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[2].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[1].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[12].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[11].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/tck_in_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[15].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[14].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[12].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[11].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[10].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[9].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[8].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[7].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[6].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[5].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[4].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[3].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[2].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[1].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' Finished Sourcing Tcl File [D:/Xilinx/Vivado/2018.3/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_single.tcl] for cell 'ngFEC/SFP_GEN[9].ngCCM_gbt/IPbus_gen[0].skip_SFP_SEC.IPbus_local_inst/IPbus_strobe_Sync_inst' INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.135 . Memory (MB): peak = 3352.520 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: A total of 43 instances were transformed. IOBUF => IOBUF (IBUF, OBUFT): 42 instances OBUFDS => OBUFDS: 1 instances 11 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:01:56 ; elapsed = 00:01:46 . Memory (MB): peak = 3352.520 ; gain = 2989.172 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7k420t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k420t' INFO: [Common 17-1540] The version limit for your license is '2020.01' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Parsing TCL File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/tcl/v7ht.tcl] from IP D:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/ngFEC_mgt.xci Sourcing Tcl File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/tcl/v7ht.tcl] **************************************************************************************** * WARNING: This script only supports the xc7vh290t, xc7vh580t and xc7vh870t devices. * * Your current part is xc7k420t. * **************************************************************************************** Finished Sourcing Tcl File [d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/ngFEC_mgt/tcl/v7ht.tcl] Running DRC as a precondition to command opt_design Starting DRC Task INFO: [DRC 23-27] Running DRC with 2 threads WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port cpld2fpga_gpio[0] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port cpld2fpga_gpio[1] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port cpld2fpga_gpio[2] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port cpld2fpga_gpio[3] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[10] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[11] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[13] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[14] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[15] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[17] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[18] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[19] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[20] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[22] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[23] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[24] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[26] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[27] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[29] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[30] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[31] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[33] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[4] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[6] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[7] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[8] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[10] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[11] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[12] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[14] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[15] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[17] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[18] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[19] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[20] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[21] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[23] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[24] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[26] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[27] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[28] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[30] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[31] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[33] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[4] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[5] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[7] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[8] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_spare[6] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_spare[7] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_n[10] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_n[11] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_n[13] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_n[14] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_n[15] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_n[17] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_n[18] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_n[19] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_n[4] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_n[6] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_n[7] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_n[8] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_p[10] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_p[11] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_p[12] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_p[14] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_p[15] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_p[17] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_p[18] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_p[19] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_p[4] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_p[5] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_p[7] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_p[8] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_spare[0] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_spare[10] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_spare[11] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_spare[12] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_spare[13] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_spare[14] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_spare[15] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_spare[16] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_spare[17] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_spare[18] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_spare[19] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_spare[1] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_spare[2] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_spare[3] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_spare[4] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_spare[5] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_spare[6] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_spare[7] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_spare[8] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_spare[9] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port k7_fabric_amc_rx_n03 expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port k7_fabric_amc_rx_p03 expects both input and output buffering but the buffers are incomplete. INFO: [Project 1-461] DRC finished with 0 Errors, 96 Warnings INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 3352.520 ; gain = 0.000 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: 10c9ab98d Time (s): cpu = 00:00:22 ; elapsed = 00:00:14 . Memory (MB): peak = 3352.520 ; gain = 0.000 Starting Logic Optimization Task Phase 1 Retarget INFO: [Opt 31-138] Pushed 373 inverter(s) to 734 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 1 Retarget | Checksum: 204094707 Time (s): cpu = 00:00:32 ; elapsed = 00:00:25 . Memory (MB): peak = 3352.520 ; gain = 0.000 INFO: [Opt 31-389] Phase Retarget created 226 cells and removed 1482 cells INFO: [Opt 31-1021] In phase Retarget, 435 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 2 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 2 Constant propagation | Checksum: 1ad3fc8ae Time (s): cpu = 00:00:42 ; elapsed = 00:00:36 . Memory (MB): peak = 3352.520 ; gain = 0.000 INFO: [Opt 31-389] Phase Constant propagation created 3244 cells and removed 8482 cells INFO: [Opt 31-1021] In phase Constant propagation, 396 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 3 Sweep Phase 3 Sweep | Checksum: 16ed37936 Time (s): cpu = 00:01:02 ; elapsed = 00:00:56 . Memory (MB): peak = 3352.520 ; gain = 0.000 INFO: [Opt 31-389] Phase Sweep created 34 cells and removed 6595 cells INFO: [Opt 31-1021] In phase Sweep, 1167 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Phase 4 BUFG optimization Phase 4 BUFG optimization | Checksum: 16ed37936 Time (s): cpu = 00:01:09 ; elapsed = 00:01:03 . Memory (MB): peak = 3352.520 ; gain = 0.000 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 5 Shift Register Optimization Phase 5 Shift Register Optimization | Checksum: d4bf9cd9 Time (s): cpu = 00:01:37 ; elapsed = 00:01:30 . Memory (MB): peak = 3352.520 ; gain = 0.000 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 6 Post Processing Netlist Phase 6 Post Processing Netlist | Checksum: f853391a Time (s): cpu = 00:01:40 ; elapsed = 00:01:34 . Memory (MB): peak = 3352.520 ; gain = 0.000 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells INFO: [Opt 31-1021] In phase Post Processing Netlist, 204 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 226 | 1482 | 435 | | Constant propagation | 3244 | 8482 | 396 | | Sweep | 34 | 6595 | 1167 | | BUFG optimization | 0 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 204 | ------------------------------------------------------------------------------------------------------------------------- Starting Connectivity Check Task Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3352.520 ; gain = 0.000 Ending Logic Optimization Task | Checksum: 1674494c4 Time (s): cpu = 00:01:43 ; elapsed = 00:01:36 . Memory (MB): peak = 3352.520 ; gain = 0.000 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Pwropt 34-9] Applying IDT optimizations ... INFO: [Pwropt 34-10] Applying ODC optimizations ... INFO: [Physopt 32-619] Estimated Timing Summary | WNS=2.016 | TNS=0.000 | Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 4 BRAM(s) out of a total of 573 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Pwropt 34-201] Structural ODC has moved 4 WE to EN ports Number of BRAM Ports augmented: 8 newly gated: 21 Total Ports: 1146 Ending PowerOpt Patch Enables Task | Checksum: 15c277682 Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 5909.789 ; gain = 0.000 Ending Power Optimization Task | Checksum: 15c277682 Time (s): cpu = 00:05:46 ; elapsed = 00:03:20 . Memory (MB): peak = 5909.789 ; gain = 2557.270 Starting Final Cleanup Task Starting Logic Optimization Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Logic Optimization Task | Checksum: 15e501d5e Time (s): cpu = 00:00:46 ; elapsed = 00:00:34 . Memory (MB): peak = 5909.789 ; gain = 0.000 Ending Final Cleanup Task | Checksum: 15e501d5e Time (s): cpu = 00:00:50 ; elapsed = 00:00:38 . Memory (MB): peak = 5909.789 ; gain = 0.000 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.135 . Memory (MB): peak = 5909.789 ; gain = 0.000 Ending Netlist Obfuscation Task | Checksum: 15e501d5e Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.136 . Memory (MB): peak = 5909.789 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation 39 Infos, 96 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:08:57 ; elapsed = 00:06:05 . Memory (MB): peak = 5909.789 ; gain = 2557.270 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.136 . Memory (MB): peak = 5909.789 ; gain = 0.000 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.134 . Memory (MB): peak = 5909.789 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.137 . Memory (MB): peak = 5909.789 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'D:/Design_collection/ngFECv0x43d/ngFEC_new.runs/impl_1/fc7_top_opt.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:01:07 ; elapsed = 00:00:45 . Memory (MB): peak = 5909.789 ; gain = 0.000 INFO: [runtcl-4] Executing : report_drc -file fc7_top_drc_opted.rpt -pb fc7_top_drc_opted.pb -rpx fc7_top_drc_opted.rpx Command: report_drc -file fc7_top_drc_opted.rpt -pb fc7_top_drc_opted.pb -rpx fc7_top_drc_opted.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Coretcl 2-168] The results of DRC are in file D:/Design_collection/ngFECv0x43d/ngFEC_new.runs/impl_1/fc7_top_drc_opted.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:00:28 ; elapsed = 00:00:15 . Memory (MB): peak = 5909.789 ; gain = 0.000 Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7k420t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k420t' INFO: [Common 17-1540] The version limit for your license is '2020.01' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [DRC 23-27] Running DRC with 2 threads WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1839 rule limit reached: 20 violations have been found. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[10] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[5]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[10] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[5]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[11] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[6]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[11] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[6]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[12] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[7]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[12] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[7]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[13] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[8]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[13] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[8]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[14] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[9]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[14] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[9]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[5] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[0]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[5] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[0]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[6] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[1]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[6] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[1]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[7] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[2]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[7] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[2]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[8] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[3]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[8] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[3]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[9] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[4]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[9] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[4]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port cpld2fpga_gpio[0] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port cpld2fpga_gpio[1] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port cpld2fpga_gpio[2] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port cpld2fpga_gpio[3] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[10] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[11] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[13] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[14] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[15] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[17] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[18] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[19] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[20] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[22] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[23] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[24] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[26] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[27] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[29] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[30] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[31] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[33] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[4] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[6] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[7] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_n[8] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[10] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[11] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[12] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[14] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[15] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[17] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[18] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[19] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[20] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[21] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[23] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[24] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[26] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[27] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[28] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[30] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[31] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[33] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[4] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[5] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[7] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_la_p[8] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_spare[6] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l12_spare[7] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_n[10] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_n[11] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_n[13] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_n[14] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_n[15] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_n[17] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_n[18] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_n[19] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_n[4] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_n[6] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_n[7] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_n[8] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_p[10] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_p[11] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_p[12] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_p[14] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_p[15] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_p[17] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_p[18] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_p[19] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_p[4] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_p[5] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_p[7] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_la_p[8] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_spare[0] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_spare[10] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_spare[11] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_spare[12] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_spare[13] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_spare[14] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_spare[15] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_spare[16] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_spare[17] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_spare[18] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_spare[19] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_spare[1] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_spare[2] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_spare[3] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_spare[4] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_spare[5] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_spare[6] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_spare[7] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_spare[8] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port fmc_l8_spare[9] expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port k7_fabric_amc_rx_n03 expects both input and output buffering but the buffers are incomplete. WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port k7_fabric_amc_rx_p03 expects both input and output buffering but the buffers are incomplete. INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 117 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.144 . Memory (MB): peak = 5909.789 ; gain = 0.000 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 11553df4f Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.197 . Memory (MB): peak = 5909.789 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.197 . Memory (MB): peak = 5909.789 ; gain = 0.000 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device WARNING: [Place 30-87] Partially locked IO Bus is found. Following components of the IO Bus amc_tx_n are not locked: 'amc_tx_n[11]' 'amc_tx_n[10]' 'amc_tx_n[9]' 'amc_tx_n[8]' 'amc_tx_n[7]' 'amc_tx_n[6]' 'amc_tx_n[5]' 'amc_tx_n[4]' 'amc_tx_n[3]' 'amc_tx_n[2]' 'amc_tx_n[1]' WARNING: [Place 30-87] Partially locked IO Bus is found. Following components of the IO Bus amc_tx_p are not locked: 'amc_tx_p[11]' 'amc_tx_p[10]' 'amc_tx_p[9]' 'amc_tx_p[8]' 'amc_tx_p[7]' 'amc_tx_p[6]' 'amc_tx_p[5]' 'amc_tx_p[4]' 'amc_tx_p[3]' 'amc_tx_p[2]' 'amc_tx_p[1]' WARNING: [Place 30-87] Partially locked IO Bus is found. Following components of the IO Bus k7_amc_rx_n are not locked: 'k7_amc_rx_n[11]' 'k7_amc_rx_n[10]' 'k7_amc_rx_n[9]' 'k7_amc_rx_n[8]' 'k7_amc_rx_n[7]' 'k7_amc_rx_n[6]' 'k7_amc_rx_n[5]' 'k7_amc_rx_n[4]' 'k7_amc_rx_n[3]' 'k7_amc_rx_n[2]' 'k7_amc_rx_n[1]' WARNING: [Place 30-87] Partially locked IO Bus is found. Following components of the IO Bus k7_amc_rx_p are not locked: 'k7_amc_rx_p[11]' 'k7_amc_rx_p[10]' 'k7_amc_rx_p[9]' 'k7_amc_rx_p[8]' 'k7_amc_rx_p[7]' 'k7_amc_rx_p[6]' 'k7_amc_rx_p[5]' 'k7_amc_rx_p[4]' 'k7_amc_rx_p[3]' 'k7_amc_rx_p[2]' 'k7_amc_rx_p[1]' INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1881b8ff6 Time (s): cpu = 00:01:07 ; elapsed = 00:00:48 . Memory (MB): peak = 5909.789 ; gain = 0.000 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 14d15e4a4 Time (s): cpu = 00:02:58 ; elapsed = 00:02:09 . Memory (MB): peak = 5909.789 ; gain = 0.000 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 14d15e4a4 Time (s): cpu = 00:02:59 ; elapsed = 00:02:11 . Memory (MB): peak = 5909.789 ; gain = 0.000 Phase 1 Placer Initialization | Checksum: 14d15e4a4 Time (s): cpu = 00:03:00 ; elapsed = 00:02:11 . Memory (MB): peak = 5909.789 ; gain = 0.000 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 140c33cb7 Time (s): cpu = 00:03:36 ; elapsed = 00:02:33 . Memory (MB): peak = 5909.789 ; gain = 0.000 Phase 2.2 Physical Synthesis In Placer INFO: [Physopt 32-76] Pass 1. Identified 2 candidate nets for fanout optimization. INFO: [Physopt 32-81] Processed net sys/ipb/trans/sm/addr_reg[31]_0[16]. Replicated 28 times. INFO: [Physopt 32-81] Processed net sys/ipb/trans/sm/addr_reg[31]_0[17]. Replicated 17 times. INFO: [Physopt 32-232] Optimized 2 nets. Created 45 new instances. INFO: [Physopt 32-775] End 1 Pass. Optimized 2 nets or cells. Created 45 new cells, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.267 . Memory (MB): peak = 5909.789 ; gain = 0.000 INFO: [Physopt 32-670] No setup violation found. Critical Cell Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. INFO: [Physopt 32-949] No candidate nets found for HD net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.133 . Memory (MB): peak = 5909.789 ; gain = 0.000 Summary of Physical Synthesis Optimizations ============================================ ---------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ---------------------------------------------------------------------------------------------------------------------------------------- | Very High Fanout | 45 | 0 | 2 | 0 | 1 | 00:00:58 | | Critical Cell | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | HD Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 45 | 0 | 2 | 0 | 2 | 00:00:58 | ---------------------------------------------------------------------------------------------------------------------------------------- Phase 2.2 Physical Synthesis In Placer | Checksum: 2165492ca Time (s): cpu = 00:11:48 ; elapsed = 00:09:09 . Memory (MB): peak = 5909.789 ; gain = 0.000 Phase 2 Global Placement | Checksum: bea216e9 Time (s): cpu = 00:12:05 ; elapsed = 00:09:22 . Memory (MB): peak = 5909.789 ; gain = 0.000 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: bea216e9 Time (s): cpu = 00:12:07 ; elapsed = 00:09:23 . Memory (MB): peak = 5909.789 ; gain = 0.000 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: db018df0 Time (s): cpu = 00:13:29 ; elapsed = 00:10:16 . Memory (MB): peak = 5909.789 ; gain = 0.000 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 866c0bca Time (s): cpu = 00:13:34 ; elapsed = 00:10:20 . Memory (MB): peak = 5909.789 ; gain = 0.000 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: 1600258ea Time (s): cpu = 00:13:36 ; elapsed = 00:10:22 . Memory (MB): peak = 5909.789 ; gain = 0.000 Phase 3.5 Small Shape Detail Placement Phase 3.5.1 Place Remaining Phase 3.5.1 Place Remaining | Checksum: 15ca12b4b Time (s): cpu = 00:16:21 ; elapsed = 00:13:14 . Memory (MB): peak = 5909.789 ; gain = 0.000 Phase 3.5 Small Shape Detail Placement | Checksum: 15ca12b4b Time (s): cpu = 00:16:24 ; elapsed = 00:13:17 . Memory (MB): peak = 5909.789 ; gain = 0.000 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 135efe82c Time (s): cpu = 00:16:42 ; elapsed = 00:13:37 . Memory (MB): peak = 5909.789 ; gain = 0.000 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 160c453c7 Time (s): cpu = 00:16:45 ; elapsed = 00:13:40 . Memory (MB): peak = 5909.789 ; gain = 0.000 Phase 3 Detail Placement | Checksum: 160c453c7 Time (s): cpu = 00:16:47 ; elapsed = 00:13:42 . Memory (MB): peak = 5909.789 ; gain = 0.000 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: f1c2ab69 Phase 4.1.1.1 BUFG Insertion INFO: [Place 46-33] Processed net sys/clocks/TTC_rst, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net sys/clocks/rst_ipb, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-33] Processed net ngFEC/fabric_clk_div2, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-46] BUFG insertion identified 3 candidate nets, 0 success, 0 bufg driver replicated, 3 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason Phase 4.1.1.1 BUFG Insertion | Checksum: f1c2ab69 Time (s): cpu = 00:18:36 ; elapsed = 00:14:56 . Memory (MB): peak = 5909.789 ; gain = 0.000 INFO: [Place 30-746] Post Placement Timing Summary WNS=0.583. For the most accurate timing information please run report_timing. Phase 4.1.1 Post Placement Optimization | Checksum: 15cfd72dd Time (s): cpu = 00:18:48 ; elapsed = 00:15:07 . Memory (MB): peak = 5909.789 ; gain = 0.000 Phase 4.1 Post Commit Optimization | Checksum: 15cfd72dd Time (s): cpu = 00:18:50 ; elapsed = 00:15:09 . Memory (MB): peak = 5909.789 ; gain = 0.000 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: 15cfd72dd Time (s): cpu = 00:18:53 ; elapsed = 00:15:12 . Memory (MB): peak = 5909.789 ; gain = 0.000 Phase 4.3 Placer Reporting Phase 4.3 Placer Reporting | Checksum: 15cfd72dd Time (s): cpu = 00:18:56 ; elapsed = 00:15:14 . Memory (MB): peak = 5909.789 ; gain = 0.000 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.150 . Memory (MB): peak = 5909.789 ; gain = 0.000 Phase 4.4 Final Placement Cleanup | Checksum: 12a4bf385 Time (s): cpu = 00:18:58 ; elapsed = 00:15:16 . Memory (MB): peak = 5909.789 ; gain = 0.000 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 12a4bf385 Time (s): cpu = 00:19:00 ; elapsed = 00:15:18 . Memory (MB): peak = 5909.789 ; gain = 0.000 Ending Placer Task | Checksum: feab5849 Time (s): cpu = 00:19:01 ; elapsed = 00:15:19 . Memory (MB): peak = 5909.789 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation 73 Infos, 217 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:19:20 ; elapsed = 00:15:36 . Memory (MB): peak = 5909.789 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.135 . Memory (MB): peak = 5909.789 ; gain = 0.000 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.139 . Memory (MB): peak = 5909.789 ; gain = 0.000 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:01:08 ; elapsed = 00:00:23 . Memory (MB): peak = 5909.789 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'D:/Design_collection/ngFECv0x43d/ngFEC_new.runs/impl_1/fc7_top_placed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:01:34 ; elapsed = 00:00:51 . Memory (MB): peak = 5909.789 ; gain = 0.000 INFO: [runtcl-4] Executing : report_io -file fc7_top_io_placed.rpt report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.274 . Memory (MB): peak = 5909.789 ; gain = 0.000 INFO: [runtcl-4] Executing : report_utilization -file fc7_top_utilization_placed.rpt -pb fc7_top_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file fc7_top_control_sets_placed.rpt report_control_sets: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 5909.789 ; gain = 0.000 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7k420t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k420t' INFO: [Common 17-1540] The version limit for your license is '2020.01' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Running DRC as a precondition to command route_design INFO: [DRC 23-27] Running DRC with 2 threads WARNING: [DRC PLIO-3] Placement Constraints Check for IO constraints: Partially locked IO Bus is found. Following components of the IO Bus amc_tx_n[15:1] are not locked: amc_tx_n[11] amc_tx_n[10] amc_tx_n[9] amc_tx_n[8] amc_tx_n[7] amc_tx_n[6] amc_tx_n[5] amc_tx_n[4] amc_tx_n[3] amc_tx_n[2] and 1 more (total of 12.) WARNING: [DRC PLIO-3] Placement Constraints Check for IO constraints: Partially locked IO Bus is found. Following components of the IO Bus amc_tx_p[15:1] are not locked: amc_tx_p[11] amc_tx_p[10] amc_tx_p[9] amc_tx_p[8] amc_tx_p[7] amc_tx_p[6] amc_tx_p[5] amc_tx_p[4] amc_tx_p[3] amc_tx_p[2] and 1 more (total of 12.) WARNING: [DRC PLIO-3] Placement Constraints Check for IO constraints: Partially locked IO Bus is found. Following components of the IO Bus k7_amc_rx_n[15:1] are not locked: k7_amc_rx_n[11] k7_amc_rx_n[10] k7_amc_rx_n[9] k7_amc_rx_n[8] k7_amc_rx_n[7] k7_amc_rx_n[6] k7_amc_rx_n[5] k7_amc_rx_n[4] k7_amc_rx_n[3] k7_amc_rx_n[2] and 1 more (total of 12.) WARNING: [DRC PLIO-3] Placement Constraints Check for IO constraints: Partially locked IO Bus is found. Following components of the IO Bus k7_amc_rx_p[15:1] are not locked: k7_amc_rx_p[11] k7_amc_rx_p[10] k7_amc_rx_p[9] k7_amc_rx_p[8] k7_amc_rx_p[7] k7_amc_rx_p[6] k7_amc_rx_p[5] k7_amc_rx_p[4] k7_amc_rx_p[3] k7_amc_rx_p[2] and 1 more (total of 12.) INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 4 Warnings INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs Checksum: PlaceDB: a903d1be ConstDB: 0 ShapeSum: 55a7868b RouteDB: 0 Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: e08d330d Time (s): cpu = 00:02:08 ; elapsed = 00:01:23 . Memory (MB): peak = 5909.789 ; gain = 0.000 Post Restoration Checksum: NetGraph: 3eb3ac54 NumContArr: a1d986b9 Constraints: 0 Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer Phase 2.1 Create Timer | Checksum: e08d330d Time (s): cpu = 00:02:11 ; elapsed = 00:01:26 . Memory (MB): peak = 5909.789 ; gain = 0.000 Phase 2.2 Fix Topology Constraints Phase 2.2 Fix Topology Constraints | Checksum: e08d330d Time (s): cpu = 00:02:14 ; elapsed = 00:01:28 . Memory (MB): peak = 5909.789 ; gain = 0.000 Phase 2.3 Pre Route Cleanup Phase 2.3 Pre Route Cleanup | Checksum: e08d330d Time (s): cpu = 00:02:15 ; elapsed = 00:01:29 . Memory (MB): peak = 5909.789 ; gain = 0.000 Phase 2.4 Update Timing Phase 2.4 Update Timing | Checksum: 1a0c8b2a6 Time (s): cpu = 00:04:37 ; elapsed = 00:03:09 . Memory (MB): peak = 5909.789 ; gain = 0.000 INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.037 | TNS=0.000 | WHS=-0.440 | THS=-12621.345| Phase 2 Router Initialization | Checksum: 1b27738ea Time (s): cpu = 00:05:43 ; elapsed = 00:03:49 . Memory (MB): peak = 5909.789 ; gain = 0.000 Phase 3 Initial Routing Phase 3 Initial Routing | Checksum: 1d359dd7a Time (s): cpu = 00:09:02 ; elapsed = 00:05:39 . Memory (MB): peak = 5909.789 ; gain = 0.000 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 45353 Number of Nodes with overlaps = 6314 Number of Nodes with overlaps = 1710 Number of Nodes with overlaps = 314 Number of Nodes with overlaps = 108 Number of Nodes with overlaps = 30 Number of Nodes with overlaps = 10 Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.607 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 146df2eb0 Time (s): cpu = 00:17:27 ; elapsed = 00:11:19 . Memory (MB): peak = 5909.789 ; gain = 0.000 Phase 4 Rip-up And Reroute | Checksum: 146df2eb0 Time (s): cpu = 00:17:28 ; elapsed = 00:11:20 . Memory (MB): peak = 5909.789 ; gain = 0.000 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1 Delay CleanUp | Checksum: 146df2eb0 Time (s): cpu = 00:17:30 ; elapsed = 00:11:21 . Memory (MB): peak = 5909.789 ; gain = 0.000 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 146df2eb0 Time (s): cpu = 00:17:30 ; elapsed = 00:11:22 . Memory (MB): peak = 5909.789 ; gain = 0.000 Phase 5 Delay and Skew Optimization | Checksum: 146df2eb0 Time (s): cpu = 00:17:31 ; elapsed = 00:11:23 . Memory (MB): peak = 5909.789 ; gain = 0.000 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 151d68afb Time (s): cpu = 00:17:53 ; elapsed = 00:11:36 . Memory (MB): peak = 5909.789 ; gain = 0.000 INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.607 | TNS=0.000 | WHS=-0.012 | THS=-0.177 | Phase 6.1 Hold Fix Iter | Checksum: f9f3b382 Time (s): cpu = 00:18:01 ; elapsed = 00:11:41 . Memory (MB): peak = 5909.789 ; gain = 0.000 Phase 6 Post Hold Fix | Checksum: 17672ccdf Time (s): cpu = 00:18:02 ; elapsed = 00:11:43 . Memory (MB): peak = 5909.789 ; gain = 0.000 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 16.5632 % Global Horizontal Routing Utilization = 17.2116 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 7 Route finalize | Checksum: ca853298 Time (s): cpu = 00:18:05 ; elapsed = 00:11:45 . Memory (MB): peak = 5909.789 ; gain = 0.000 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: ca853298 Time (s): cpu = 00:18:06 ; elapsed = 00:11:46 . Memory (MB): peak = 5909.789 ; gain = 0.000 Phase 9 Depositing Routes INFO: [Route 35-467] Router swapped GT pin sys/eth/phy/U0/transceiver_inst/gtwizard_inst/U0/gtwizard_i/gt0_GTWIZARD_i/gtxe2_i/GTREFCLK0 to physical pin GTXE2_CHANNEL_X0Y8/GTREFCLK1 INFO: [Route 35-467] Router swapped GT pin ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK1 to physical pin GTXE2_CHANNEL_X0Y28/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK1 to physical pin GTXE2_CHANNEL_X0Y31/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin ngFEC/gbtbank1_l12_118/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK1 to physical pin GTXE2_CHANNEL_X0Y30/GTNORTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[1].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK1 to physical pin GTXE2_CHANNEL_X0Y21/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[2].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK1 to physical pin GTXE2_CHANNEL_X0Y20/GTSOUTHREFCLK1 INFO: [Route 35-467] Router swapped GT pin ngFEC/gbtbank3_l12_116/gbt_inst/mgt_inst/gtxLatOpt_gen[3].xlx_k7v7_mgt_latopt_inst/U0/ngFEC_mgt_i/gt0_ngFEC_mgt_i/gtxe2_i/GTREFCLK1 to physical pin GTXE2_CHANNEL_X0Y23/GTSOUTHREFCLK1 Phase 9 Depositing Routes | Checksum: 71f20b3b Time (s): cpu = 00:18:33 ; elapsed = 00:12:17 . Memory (MB): peak = 5909.789 ; gain = 0.000 Phase 10 Post Router Timing Phase 10.1 Update Timing Phase 10.1 Update Timing | Checksum: f13b0a68 Time (s): cpu = 00:18:55 ; elapsed = 00:12:32 . Memory (MB): peak = 5909.789 ; gain = 0.000 INFO: [Route 35-57] Estimated Timing Summary | WNS=0.607 | TNS=0.000 | WHS=0.050 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. Phase 10 Post Router Timing | Checksum: f13b0a68 Time (s): cpu = 00:18:56 ; elapsed = 00:12:33 . Memory (MB): peak = 5909.789 ; gain = 0.000 INFO: [Route 35-16] Router Completed Successfully Time (s): cpu = 00:18:57 ; elapsed = 00:12:34 . Memory (MB): peak = 5909.789 ; gain = 0.000 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 98 Infos, 221 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:19:34 ; elapsed = 00:12:54 . Memory (MB): peak = 5909.789 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.139 . Memory (MB): peak = 5909.789 ; gain = 0.000 INFO: [Timing 38-480] Writing timing data to binary archive. Writing placer database... Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.137 . Memory (MB): peak = 5909.789 ; gain = 0.000 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:01:26 ; elapsed = 00:00:31 . Memory (MB): peak = 5909.789 ; gain = 0.000 INFO: [Common 17-1381] The checkpoint 'D:/Design_collection/ngFECv0x43d/ngFEC_new.runs/impl_1/fc7_top_routed.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:01:45 ; elapsed = 00:00:52 . Memory (MB): peak = 5909.789 ; gain = 0.000 INFO: [runtcl-4] Executing : report_drc -file fc7_top_drc_routed.rpt -pb fc7_top_drc_routed.pb -rpx fc7_top_drc_routed.rpx Command: report_drc -file fc7_top_drc_routed.rpt -pb fc7_top_drc_routed.pb -rpx fc7_top_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 2 threads INFO: [Coretcl 2-168] The results of DRC are in file D:/Design_collection/ngFECv0x43d/ngFEC_new.runs/impl_1/fc7_top_drc_routed.rpt. report_drc completed successfully report_drc: Time (s): cpu = 00:01:15 ; elapsed = 00:00:41 . Memory (MB): peak = 5909.789 ; gain = 0.000 INFO: [runtcl-4] Executing : report_methodology -file fc7_top_methodology_drc_routed.rpt -pb fc7_top_methodology_drc_routed.pb -rpx fc7_top_methodology_drc_routed.rpx Command: report_methodology -file fc7_top_methodology_drc_routed.rpt -pb fc7_top_methodology_drc_routed.pb -rpx fc7_top_methodology_drc_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [DRC 23-133] Running Methodology with 2 threads INFO: [Coretcl 2-1520] The results of Report Methodology are in file D:/Design_collection/ngFECv0x43d/ngFEC_new.runs/impl_1/fc7_top_methodology_drc_routed.rpt. report_methodology completed successfully report_methodology: Time (s): cpu = 00:02:54 ; elapsed = 00:01:42 . Memory (MB): peak = 6359.125 ; gain = 449.336 INFO: [runtcl-4] Executing : report_power -file fc7_top_power_routed.rpt -pb fc7_top_power_summary_routed.pb -rpx fc7_top_power_routed.rpx Command: report_power -file fc7_top_power_routed.rpt -pb fc7_top_power_summary_routed.pb -rpx fc7_top_power_routed.rpx INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 110 Infos, 222 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully report_power: Time (s): cpu = 00:02:49 ; elapsed = 00:01:38 . Memory (MB): peak = 6634.668 ; gain = 275.543 INFO: [runtcl-4] Executing : report_route_status -file fc7_top_route_status.rpt -pb fc7_top_route_status.pb INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file fc7_top_timing_summary_routed.rpt -pb fc7_top_timing_summary_routed.pb -rpx fc7_top_timing_summary_routed.rpx -warn_on_violation INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs report_timing_summary: Time (s): cpu = 00:00:17 ; elapsed = 00:00:12 . Memory (MB): peak = 6803.063 ; gain = 144.691 INFO: [runtcl-4] Executing : report_incremental_reuse -file fc7_top_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report. INFO: [runtcl-4] Executing : report_clock_utilization -file fc7_top_clock_utilization_routed.rpt report_clock_utilization: Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 6814.688 ; gain = 11.625 Command: write_bitstream -force fc7_top.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7k420t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k420t' INFO: [Common 17-1540] The version limit for your license is '2020.01' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. Running DRC as a precondition to command write_bitstream INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 2 threads WARNING: [DRC BUFC-1] Input Buffer Connections: Input buffer sys/i2c_m/bufgen[0].scl_buf/IBUF has no loads. It is recommended to have an input buffer drive an internal load. WARNING: [DRC CHECK-3] Report rule limit reached: REQP-1839 rule limit reached: 20 violations have been found. WARNING: [DRC LVDS-1] Bidirection LVDS IOs: The following port(s) use the LVDS_25 I/O standard and have bi-directional differential usage. Please note that LVDS_25 is a fixed impedance structure optimized to 100ohm differential. This is only intended to be used in point-to-point transmissions that do not have turn around timing requirements. If the intended usage is a bus structure, please use BLVDS/BLVDS_25, instead. k7_fabric_amc_rx_n03, and k7_fabric_amc_rx_p03. WARNING: [DRC PDRC-153] Gated clock check: Net ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_tck_o_reg_i_1/O, cell ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_tck_o_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_1/O, cell ngFEC/SFP_GEN[10].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ngFEC/SFP_GEN[10].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[10].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1/O, cell ngFEC/SFP_GEN[10].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_tck_o_reg_i_1/O, cell ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_tck_o_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_1/O, cell ngFEC/SFP_GEN[11].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ngFEC/SFP_GEN[11].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[11].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1/O, cell ngFEC/SFP_GEN[11].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_tck_o_reg_i_1/O, cell ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_tck_o_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_1/O, cell ngFEC/SFP_GEN[12].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ngFEC/SFP_GEN[12].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[12].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1/O, cell ngFEC/SFP_GEN[12].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_tck_o_reg_i_1__6/O, cell ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_tck_o_reg_i_1__6. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__6/O, cell ngFEC/SFP_GEN[1].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__6. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ngFEC/SFP_GEN[1].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__6_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[1].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__6/O, cell ngFEC/SFP_GEN[1].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__6. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_tck_o_reg_i_1__5/O, cell ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_tck_o_reg_i_1__5. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__5/O, cell ngFEC/SFP_GEN[2].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__5. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ngFEC/SFP_GEN[2].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__5_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[2].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__5/O, cell ngFEC/SFP_GEN[2].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__5. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_tck_o_reg_i_1__4/O, cell ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_tck_o_reg_i_1__4. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__4/O, cell ngFEC/SFP_GEN[3].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__4. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ngFEC/SFP_GEN[3].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__4_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[3].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__4/O, cell ngFEC/SFP_GEN[3].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__4. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_tck_o_reg_i_1__3/O, cell ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_tck_o_reg_i_1__3. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__3/O, cell ngFEC/SFP_GEN[4].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__3. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ngFEC/SFP_GEN[4].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__3_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[4].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__3/O, cell ngFEC/SFP_GEN[4].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__3. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_tck_o_reg_i_1__2/O, cell ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_tck_o_reg_i_1__2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__2/O, cell ngFEC/SFP_GEN[5].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ngFEC/SFP_GEN[5].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__2_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[5].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__2/O, cell ngFEC/SFP_GEN[5].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_tck_o_reg_i_1__1/O, cell ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_tck_o_reg_i_1__1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__1/O, cell ngFEC/SFP_GEN[6].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ngFEC/SFP_GEN[6].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__1_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[6].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__1/O, cell ngFEC/SFP_GEN[6].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_tck_o_reg_i_1__0/O, cell ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_tck_o_reg_i_1__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__0/O, cell ngFEC/SFP_GEN[7].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ngFEC/SFP_GEN[7].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__0_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[7].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__0/O, cell ngFEC/SFP_GEN[7].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_tck_o_reg_i_1/O, cell ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_tck_o_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2/O, cell ngFEC/SFP_GEN[8].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ngFEC/SFP_GEN[8].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[8].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1/O, cell ngFEC/SFP_GEN[8].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_tck_o3_out is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_tck_o_reg_i_1__7/O, cell ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_tck_o_reg_i_1__7. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_trst_o1 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__7/O, cell ngFEC/SFP_GEN[9].ngCCM_gbt/jtag_bridge_tdo_i_reg_i_2__7. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net ngFEC/SFP_GEN[9].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__7_n_0 is a gated clock net sourced by a combinational pin ngFEC/SFP_GEN[9].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__7/O, cell ngFEC/SFP_GEN[9].ngCCM_gbt/sec_jtag_tdi_o_reg_i_1__7. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC PDRC-153] Gated clock check: Net sys/ipb_sys_regs/regs_reg[11][12]_0 is a gated clock net sourced by a combinational pin sys/ipb_sys_regs/sck_reg_LDC_i_1/O, cell sys/ipb_sys_regs/sck_reg_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[10] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[5]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[10] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[5]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[11] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[6]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[11] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[6]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[12] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[7]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[12] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[7]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[13] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[8]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[13] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[8]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[14] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[9]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[14] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[9]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[5] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[0]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[5] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[0]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[6] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[1]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[6] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[1]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[7] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[2]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[7] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[2]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[8] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[3]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[8] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[3]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[9] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[4]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg has an input control pin ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/memory_reg/ADDRARDADDR[9] (net: ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/JTAG_BRAM/BRAM_wr_adr[4]) which is driven by a register (ngFEC/SFP_GEN[10].ngCCM_gbt/LocalJTAGBridge_inst/JTAGMaster_inst/FSM_sequential_StateJTAGCtrl_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. INFO: [Vivado 12-3199] DRC finished with 0 Errors, 60 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Designutils 20-2272] Running write_bitstream with 2 threads. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Writing bitstream ./fc7_top.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-118] WebTalk data collection is enabled (User setting is ON. Install Setting is ON.). INFO: [Common 17-83] Releasing license: Implementation 127 Infos, 282 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:04:15 ; elapsed = 00:02:35 . Memory (MB): peak = 7873.457 ; gain = 1058.770 INFO: [Common 17-206] Exiting Vivado at Mon May 18 09:59:12 2020...