Command: %s 53* vivadotcl2l Xsynth_design -top gig_ethernet_pcs_pma_16_1 -part xc7k420tffg1156-2 -mode out_of_context2default:defaultZ4-113hpx : Starting synth_design 149* vivadotclZ4-321hpx  @Attempting to get a license for feature '%s' and/or device '%s' 308*common2 Synthesis2default:default2 xc7k420t2default:defaultZ17-347hpx  0Got license for feature '%s' and/or device '%s' 310*common2 Synthesis2default:default2 xc7k420t2default:defaultZ17-349hpx  The version limit for your license is '%s' and has expired for new software. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases. 719*common2 2020.012default:defaultZ17-1540hpx  %s *synth2 xStarting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 473.020 ; gain = 101.223 2default:defaulthp x   synthesizing module '%s'638*oasys2- gig_ethernet_pcs_pma_16_12default:default2 zd:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1.vhd2default:default2 1572default:default8@Z8-638hpx g %s *synth2O ; Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer 2default:defaulthp x  g %s *synth2O ; Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys23 gig_ethernet_pcs_pma_16_1_block2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_block.vhd2default:default2 962default:default2 U02default:default23 gig_ethernet_pcs_pma_16_1_block2default:default2 zd:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1.vhd2default:default2 2282default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys23 gig_ethernet_pcs_pma_16_1_block2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_block.vhd2default:default2 1562default:default8@Z8-638hpx g %s *synth2O ; Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer 2default:defaulthp x   -Port '%s' is missing in component declaration4102*oasys2 s_axi_aclk2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_block.vhd2default:default2 2632default:default8@Z8-5640hpx  -Port '%s' is missing in component declaration4102*oasys2 s_axi_resetn2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_block.vhd2default:default2 2632default:default8@Z8-5640hpx  -Port '%s' is missing in component declaration4102*oasys2 s_axi_awaddr2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_block.vhd2default:default2 2632default:default8@Z8-5640hpx  -Port '%s' is missing in component declaration4102*oasys2! s_axi_awvalid2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_block.vhd2default:default2 2632default:default8@Z8-5640hpx  -Port '%s' is missing in component declaration4102*oasys2! s_axi_awready2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_block.vhd2default:default2 2632default:default8@Z8-5640hpx  -Port '%s' is missing in component declaration4102*oasys2 s_axi_wdata2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_block.vhd2default:default2 2632default:default8@Z8-5640hpx  -Port '%s' is missing in component declaration4102*oasys2 s_axi_wvalid2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_block.vhd2default:default2 2632default:default8@Z8-5640hpx  -Port '%s' is missing in component declaration4102*oasys2 s_axi_wready2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_block.vhd2default:default2 2632default:default8@Z8-5640hpx  -Port '%s' is missing in component declaration4102*oasys2 s_axi_bresp2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_block.vhd2default:default2 2632default:default8@Z8-5640hpx  -Port '%s' is missing in component declaration4102*oasys2 s_axi_bvalid2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_block.vhd2default:default2 2632default:default8@Z8-5640hpx  -Port '%s' is missing in component declaration4102*oasys2 s_axi_bready2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_block.vhd2default:default2 2632default:default8@Z8-5640hpx  -Port '%s' is missing in component declaration4102*oasys2 s_axi_araddr2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_block.vhd2default:default2 2632default:default8@Z8-5640hpx  -Port '%s' is missing in component declaration4102*oasys2! s_axi_arvalid2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_block.vhd2default:default2 2632default:default8@Z8-5640hpx  -Port '%s' is missing in component declaration4102*oasys2! s_axi_arready2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_block.vhd2default:default2 2632default:default8@Z8-5640hpx  -Port '%s' is missing in component declaration4102*oasys2 s_axi_rdata2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_block.vhd2default:default2 2632default:default8@Z8-5640hpx  -Port '%s' is missing in component declaration4102*oasys2 s_axi_rresp2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_block.vhd2default:default2 2632default:default8@Z8-5640hpx  -Port '%s' is missing in component declaration4102*oasys2 s_axi_rvalid2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_block.vhd2default:default2 2632default:default8@Z8-5640hpx  -Port '%s' is missing in component declaration4102*oasys2 s_axi_rready2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_block.vhd2default:default2 2632default:default8@Z8-5640hpx y %s *synth2a M Parameter C_ELABORATION_TRANSIENT_DIR bound to: BlankString - type: string 2default:defaulthp x  | %s *synth2d P Parameter C_COMPONENT_NAME bound to: gig_ethernet_pcs_pma_16_1 - type: string 2default:defaulthp x  h %s *synth2P < Parameter C_RX_GMII_CLK bound to: TXOUTCLK - type: string 2default:defaulthp x  b %s *synth2J 6 Parameter C_FAMILY bound to: kintex7 - type: string 2default:defaulthp x  \ %s *synth2D 0 Parameter C_IS_SGMII bound to: 0 - type: bool 2default:defaulthp x  c %s *synth2K 7 Parameter C_USE_TRANSCEIVER bound to: 1 - type: bool 2default:defaulthp x  ] %s *synth2E 1 Parameter C_HAS_TEMAC bound to: 1 - type: bool 2default:defaulthp x  [ %s *synth2C / Parameter C_USE_TBI bound to: 0 - type: bool 2default:defaulthp x  \ %s *synth2D 0 Parameter C_USE_LVDS bound to: 0 - type: bool 2default:defaulthp x  Z %s *synth2B . Parameter C_HAS_AN bound to: 0 - type: bool 2default:defaulthp x  \ %s *synth2D 0 Parameter C_HAS_MDIO bound to: 0 - type: bool 2default:defaulthp x  b %s *synth2J 6 Parameter C_SGMII_PHY_MODE bound to: 0 - type: bool 2default:defaulthp x  e %s *synth2M 9 Parameter C_DYNAMIC_SWITCHING bound to: 0 - type: bool 2default:defaulthp x  g %s *synth2O ; Parameter C_SGMII_FABRIC_BUFFER bound to: 1 - type: bool 2default:defaulthp x  X %s *synth2@ , Parameter C_2_5G bound to: 0 - type: bool 2default:defaulthp x  [ %s *synth2C / Parameter C_1588 bound to: 0 - type: integer 2default:defaulthp x  ` %s *synth2H 4 Parameter B_SHIFTER_ADDR bound to: 10'b0101001110 2default:defaulthp x  e %s *synth2M 9 Parameter GT_RX_BYTE_WIDTH bound to: 1 - type: integer 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys20 gig_ethernet_pcs_pma_v16_1_52default:default2 }d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/hdl/gig_ethernet_pcs_pma_v16_1_rfs.vhd2default:default2 174682default:default22 gig_ethernet_pcs_pma_16_1_core2default:default20 gig_ethernet_pcs_pma_v16_1_52default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_block.vhd2default:default2 4382default:default8@Z8-3491hpx g %s *synth2O ; Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys29 %gig_ethernet_pcs_pma_16_1_transceiver2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_transceiver.vhd2default:default2 692default:default2$ transceiver_inst2default:default29 %gig_ethernet_pcs_pma_16_1_transceiver2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_block.vhd2default:default2 5502default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys29 %gig_ethernet_pcs_pma_16_1_transceiver2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_transceiver.vhd2default:default2 1602default:default8@Z8-638hpx g %s *synth2O ; Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer 2default:defaulthp x  S %s *synth2; ' Parameter INITIALISE bound to: 2'b00 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys28 $gig_ethernet_pcs_pma_16_1_sync_block2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_sync_block.vhd2default:default2 672default:default2) sync_block_data_valid2default:default28 $gig_ethernet_pcs_pma_16_1_sync_block2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_transceiver.vhd2default:default2 4372default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys28 $gig_ethernet_pcs_pma_16_1_sync_block2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_sync_block.vhd2default:default2 802default:default8@Z8-638hpx S %s *synth2; ' Parameter INITIALISE bound to: 2'b00 2default:defaulthp x  L %s *synth24 Parameter INIT bound to: 1'b0 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2" data_sync_reg12default:default2 FD2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_sync_block.vhd2default:default2 1132default:default8@Z8-113hpx L %s *synth24 Parameter INIT bound to: 1'b0 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2" data_sync_reg22default:default2 FD2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_sync_block.vhd2default:default2 1232default:default8@Z8-113hpx L %s *synth24 Parameter INIT bound to: 1'b0 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2" data_sync_reg32default:default2 FD2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_sync_block.vhd2default:default2 1332default:default8@Z8-113hpx L %s *synth24 Parameter INIT bound to: 1'b0 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2" data_sync_reg42default:default2 FD2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_sync_block.vhd2default:default2 1432default:default8@Z8-113hpx L %s *synth24 Parameter INIT bound to: 1'b0 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2" data_sync_reg52default:default2 FD2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_sync_block.vhd2default:default2 1532default:default8@Z8-113hpx L %s *synth24 Parameter INIT bound to: 1'b0 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2" data_sync_reg62default:default2 FD2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_sync_block.vhd2default:default2 1632default:default8@Z8-113hpx  %done synthesizing module '%s' (%s#%s)256*oasys28 $gig_ethernet_pcs_pma_16_1_sync_block2default:default2 82default:default2 12default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_sync_block.vhd2default:default2 802default:default8@Z8-256hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2= )gig_ethernet_pcs_pma_16_1_reset_wtd_timer2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_reset_wtd_timer.vhd2default:default2 702default:default2# reset_wtd_timer2default:default2= )gig_ethernet_pcs_pma_16_1_reset_wtd_timer2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_transceiver.vhd2default:default2 4442default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys2= )gig_ethernet_pcs_pma_16_1_reset_wtd_timer2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_reset_wtd_timer.vhd2default:default2 812default:default8@Z8-638hpx i %s *synth2Q = Parameter WAIT_TIME bound to: 24'b100011110000110100011000 2default:defaulthp x   %done synthesizing module '%s' (%s#%s)256*oasys2= )gig_ethernet_pcs_pma_16_1_reset_wtd_timer2default:default2 92default:default2 12default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_reset_wtd_timer.vhd2default:default2 812default:default8@Z8-256hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys28 $gig_ethernet_pcs_pma_16_1_reset_sync2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_reset_sync.vhd2default:default2 662default:default2( reclock_encommaalign2default:default28 $gig_ethernet_pcs_pma_16_1_reset_sync2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_transceiver.vhd2default:default2 4682default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys28 $gig_ethernet_pcs_pma_16_1_reset_sync2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_reset_sync.vhd2default:default2 792default:default8@Z8-638hpx S %s *synth2; ' Parameter INITIALISE bound to: 2'b11 2default:defaulthp x  L %s *synth24 Parameter INIT bound to: 1'b1 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 reset_sync12default:default2 FDP2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_reset_sync.vhd2default:default2 1082default:default8@Z8-113hpx L %s *synth24 Parameter INIT bound to: 1'b1 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 reset_sync22default:default2 FDP2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_reset_sync.vhd2default:default2 1192default:default8@Z8-113hpx L %s *synth24 Parameter INIT bound to: 1'b1 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 reset_sync32default:default2 FDP2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_reset_sync.vhd2default:default2 1302default:default8@Z8-113hpx L %s *synth24 Parameter INIT bound to: 1'b1 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 reset_sync42default:default2 FDP2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_reset_sync.vhd2default:default2 1412default:default8@Z8-113hpx L %s *synth24 Parameter INIT bound to: 1'b1 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 reset_sync52default:default2 FDP2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_reset_sync.vhd2default:default2 1522default:default8@Z8-113hpx L %s *synth24 Parameter INIT bound to: 1'b1 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 reset_sync62default:default2 FDP2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_reset_sync.vhd2default:default2 1632default:default8@Z8-113hpx  %done synthesizing module '%s' (%s#%s)256*oasys28 $gig_ethernet_pcs_pma_16_1_reset_sync2default:default2 102default:default2 12default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_reset_sync.vhd2default:default2 792default:default8@Z8-256hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys28 $gig_ethernet_pcs_pma_16_1_reset_sync2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_reset_sync.vhd2default:default2 662default:default2# reclock_txreset2default:default28 $gig_ethernet_pcs_pma_16_1_reset_sync2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_transceiver.vhd2default:default2 4772default:default8@Z8-3491hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys28 $gig_ethernet_pcs_pma_16_1_reset_sync2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_reset_sync.vhd2default:default2 662default:default2# reclock_rxreset2default:default28 $gig_ethernet_pcs_pma_16_1_reset_sync2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_transceiver.vhd2default:default2 4862default:default8@Z8-3491hpx g %s *synth2O ; Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys26 "gig_ethernet_pcs_pma_16_1_GTWIZARD2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_gtwizard.vhd2default:default2 722default:default2! gtwizard_inst2default:default26 "gig_ethernet_pcs_pma_16_1_GTWIZARD2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_transceiver.vhd2default:default2 6772default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys26 "gig_ethernet_pcs_pma_16_1_GTWIZARD2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_gtwizard.vhd2default:default2 2192default:default8@Z8-638hpx g %s *synth2O ; Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer 2default:defaulthp x  r %s *synth2Z F Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string 2default:defaulthp x  g %s *synth2O ; Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer 2default:defaulthp x  h %s *synth2P < Parameter STABLE_CLOCK_PERIOD bound to: 5 - type: integer 2default:defaulthp x  j %s *synth2R > Parameter EXAMPLE_USE_CHIPSCOPE bound to: 0 - type: integer 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2; 'gig_ethernet_pcs_pma_16_1_GTWIZARD_init2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_gtwizard_init.vhd2default:default2 752default:default2 U02default:default2; 'gig_ethernet_pcs_pma_16_1_GTWIZARD_init2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_gtwizard.vhd2default:default2 3772default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys2; 'gig_ethernet_pcs_pma_16_1_GTWIZARD_init2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_gtwizard_init.vhd2default:default2 2282default:default8@Z8-638hpx r %s *synth2Z F Parameter EXAMPLE_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string 2default:defaulthp x  g %s *synth2O ; Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer 2default:defaulthp x  h %s *synth2P < Parameter STABLE_CLOCK_PERIOD bound to: 5 - type: integer 2default:defaulthp x  j %s *synth2R > Parameter EXAMPLE_USE_CHIPSCOPE bound to: 0 - type: integer 2default:defaulthp x  r %s *synth2Z F Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2? +gig_ethernet_pcs_pma_16_1_GTWIZARD_multi_gt2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_gtwizard_multi_gt.vhd2default:default2 732default:default2 gtwizard_i2default:default2? +gig_ethernet_pcs_pma_16_1_GTWIZARD_multi_gt2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_gtwizard_init.vhd2default:default2 5372default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys2? +gig_ethernet_pcs_pma_16_1_GTWIZARD_multi_gt2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_gtwizard_multi_gt.vhd2default:default2 2212default:default8@Z8-638hpx r %s *synth2Z F Parameter WRAPPER_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string 2default:defaulthp x  y %s *synth2a M Parameter RX_DFE_KL_CFG2_IN bound to: 32'b00110000000100010100100010101100 2default:defaulthp x  r %s *synth2Z F Parameter PMA_RSV_IN bound to: 32'b00000000000000011000010010000000 2default:defaulthp x  m %s *synth2U A Parameter GT_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string 2default:defaulthp x  n %s *synth2V B Parameter RX_DFE_KL_CFG2_IN bound to: 806439084 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter PMA_RSV_IN bound to: 99456 - type: integer 2default:defaulthp x   %s *synth2p \ Parameter PCS_RSVD_ATTR_IN bound to: 48'b000000000000000000000000000000000000000000000000 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys29 %gig_ethernet_pcs_pma_16_1_GTWIZARD_GT2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_gtwizard_gt.vhd2default:default2 722default:default2" gt0_GTWIZARD_i2default:default29 %gig_ethernet_pcs_pma_16_1_GTWIZARD_GT2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_gtwizard_multi_gt.vhd2default:default2 4172default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys29 %gig_ethernet_pcs_pma_16_1_GTWIZARD_GT2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_gtwizard_gt.vhd2default:default2 2162default:default8@Z8-638hpx m %s *synth2U A Parameter GT_SIM_GTRESET_SPEEDUP bound to: TRUE - type: string 2default:defaulthp x  n %s *synth2V B Parameter RX_DFE_KL_CFG2_IN bound to: 806439084 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter PMA_RSV_IN bound to: 99456 - type: integer 2default:defaulthp x   %s *synth2p \ Parameter PCS_RSVD_ATTR_IN bound to: 48'b000000000000000000000000000000000000000000000000 2default:defaulthp x  j %s *synth2R > Parameter ALIGN_COMMA_DOUBLE bound to: FALSE - type: string 2default:defaulthp x  d %s *synth2L 8 Parameter ALIGN_COMMA_ENABLE bound to: 10'b0001111111 2default:defaulthp x  e %s *synth2M 9 Parameter ALIGN_COMMA_WORD bound to: 2 - type: integer 2default:defaulthp x  g %s *synth2O ; Parameter ALIGN_MCOMMA_DET bound to: TRUE - type: string 2default:defaulthp x  d %s *synth2L 8 Parameter ALIGN_MCOMMA_VALUE bound to: 10'b1010000011 2default:defaulthp x  g %s *synth2O ; Parameter ALIGN_PCOMMA_DET bound to: TRUE - type: string 2default:defaulthp x  d %s *synth2L 8 Parameter ALIGN_PCOMMA_VALUE bound to: 10'b0101111100 2default:defaulthp x  n %s *synth2V B Parameter CBCC_DATA_SOURCE_SEL bound to: DECODED - type: string 2default:defaulthp x  l %s *synth2T @ Parameter CHAN_BOND_KEEP_ALIGN bound to: FALSE - type: string 2default:defaulthp x  g %s *synth2O ; Parameter CHAN_BOND_MAX_SKEW bound to: 1 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter CHAN_BOND_SEQ_1_1 bound to: 10'b0000000000 2default:defaulthp x  c %s *synth2K 7 Parameter CHAN_BOND_SEQ_1_2 bound to: 10'b0000000000 2default:defaulthp x  c %s *synth2K 7 Parameter CHAN_BOND_SEQ_1_3 bound to: 10'b0000000000 2default:defaulthp x  c %s *synth2K 7 Parameter CHAN_BOND_SEQ_1_4 bound to: 10'b0000000000 2default:defaulthp x  a %s *synth2I 5 Parameter CHAN_BOND_SEQ_1_ENABLE bound to: 4'b1111 2default:defaulthp x  c %s *synth2K 7 Parameter CHAN_BOND_SEQ_2_1 bound to: 10'b0000000000 2default:defaulthp x  c %s *synth2K 7 Parameter CHAN_BOND_SEQ_2_2 bound to: 10'b0000000000 2default:defaulthp x  c %s *synth2K 7 Parameter CHAN_BOND_SEQ_2_3 bound to: 10'b0000000000 2default:defaulthp x  c %s *synth2K 7 Parameter CHAN_BOND_SEQ_2_4 bound to: 10'b0000000000 2default:defaulthp x  a %s *synth2I 5 Parameter CHAN_BOND_SEQ_2_ENABLE bound to: 4'b1111 2default:defaulthp x  k %s *synth2S ? Parameter CHAN_BOND_SEQ_2_USE bound to: FALSE - type: string 2default:defaulthp x  f %s *synth2N : Parameter CHAN_BOND_SEQ_LEN bound to: 1 - type: integer 2default:defaulthp x  f %s *synth2N : Parameter CLK_CORRECT_USE bound to: TRUE - type: string 2default:defaulthp x  i %s *synth2Q = Parameter CLK_COR_KEEP_IDLE bound to: FALSE - type: string 2default:defaulthp x  e %s *synth2M 9 Parameter CLK_COR_MAX_LAT bound to: 36 - type: integer 2default:defaulthp x  e %s *synth2M 9 Parameter CLK_COR_MIN_LAT bound to: 33 - type: integer 2default:defaulthp x  i %s *synth2Q = Parameter CLK_COR_PRECEDENCE bound to: TRUE - type: string 2default:defaulthp x  h %s *synth2P < Parameter CLK_COR_REPEAT_WAIT bound to: 0 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter CLK_COR_SEQ_1_1 bound to: 10'b0110111100 2default:defaulthp x  a %s *synth2I 5 Parameter CLK_COR_SEQ_1_2 bound to: 10'b0001010000 2default:defaulthp x  a %s *synth2I 5 Parameter CLK_COR_SEQ_1_3 bound to: 10'b0000000000 2default:defaulthp x  a %s *synth2I 5 Parameter CLK_COR_SEQ_1_4 bound to: 10'b0000000000 2default:defaulthp x  _ %s *synth2G 3 Parameter CLK_COR_SEQ_1_ENABLE bound to: 4'b1111 2default:defaulthp x  a %s *synth2I 5 Parameter CLK_COR_SEQ_2_1 bound to: 10'b0110111100 2default:defaulthp x  a %s *synth2I 5 Parameter CLK_COR_SEQ_2_2 bound to: 10'b0010110101 2default:defaulthp x  a %s *synth2I 5 Parameter CLK_COR_SEQ_2_3 bound to: 10'b0000000000 2default:defaulthp x  a %s *synth2I 5 Parameter CLK_COR_SEQ_2_4 bound to: 10'b0000000000 2default:defaulthp x  _ %s *synth2G 3 Parameter CLK_COR_SEQ_2_ENABLE bound to: 4'b1111 2default:defaulthp x  h %s *synth2P < Parameter CLK_COR_SEQ_2_USE bound to: TRUE - type: string 2default:defaulthp x  d %s *synth2L 8 Parameter CLK_COR_SEQ_LEN bound to: 2 - type: integer 2default:defaulthp x  h %s *synth2P < Parameter CPLL_CFG bound to: 24'b101111000000011111011100 2default:defaulthp x  _ %s *synth2G 3 Parameter CPLL_FBDIV bound to: 4 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter CPLL_FBDIV_45 bound to: 5 - type: integer 2default:defaulthp x  m %s *synth2U A Parameter CPLL_INIT_CFG bound to: 24'b000000000000000000011110 2default:defaulthp x  e %s *synth2M 9 Parameter CPLL_LOCK_CFG bound to: 16'b0000000111101000 2default:defaulthp x  d %s *synth2L 8 Parameter CPLL_REFCLK_DIV bound to: 1 - type: integer 2default:defaulthp x  h %s *synth2P < Parameter DEC_MCOMMA_DETECT bound to: TRUE - type: string 2default:defaulthp x  h %s *synth2P < Parameter DEC_PCOMMA_DETECT bound to: TRUE - type: string 2default:defaulthp x  l %s *synth2T @ Parameter DEC_VALID_COMMA_ONLY bound to: FALSE - type: string 2default:defaulthp x  l %s *synth2T @ Parameter DMONITOR_CFG bound to: 24'b000000000000101000000000 2default:defaulthp x  W %s *synth2? + Parameter ES_CONTROL bound to: 6'b000000 2default:defaulthp x  d %s *synth2L 8 Parameter ES_ERRDET_EN bound to: FALSE - type: string 2default:defaulthp x  e %s *synth2M 9 Parameter ES_EYE_SCAN_EN bound to: TRUE - type: string 2default:defaulthp x  b %s *synth2J 6 Parameter ES_HORZ_OFFSET bound to: 12'b000000000000 2default:defaulthp x  \ %s *synth2D 0 Parameter ES_PMA_CFG bound to: 10'b0000000000 2default:defaulthp x  W %s *synth2? + Parameter ES_PRESCALE bound to: 5'b00000 2default:defaulthp x   %s *synth2 x Parameter ES_QUALIFIER bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2 x Parameter ES_QUAL_MASK bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x   %s *synth2 y Parameter ES_SDATA_MASK bound to: 80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000 2default:defaulthp x  ^ %s *synth2F 2 Parameter ES_VERT_OFFSET bound to: 9'b000000000 2default:defaulthp x  ` %s *synth2H 4 Parameter FTS_DESKEW_SEQ_ENABLE bound to: 4'b1111 2default:defaulthp x  ^ %s *synth2F 2 Parameter FTS_LANE_DESKEW_CFG bound to: 4'b1111 2default:defaulthp x  j %s *synth2R > Parameter FTS_LANE_DESKEW_EN bound to: FALSE - type: string 2default:defaulthp x  V %s *synth2> * Parameter GEARBOX_MODE bound to: 3'b000 2default:defaulthp x  b %s *synth2J 6 Parameter IS_CPLLLOCKDETCLK_INVERTED bound to: 1'b0 2default:defaulthp x  Z %s *synth2B . Parameter IS_DRPCLK_INVERTED bound to: 1'b0 2default:defaulthp x  ] %s *synth2E 1 Parameter IS_GTGREFCLK_INVERTED bound to: 1'b0 2default:defaulthp x  ] %s *synth2E 1 Parameter IS_RXUSRCLK2_INVERTED bound to: 1'b0 2default:defaulthp x  \ %s *synth2D 0 Parameter IS_RXUSRCLK_INVERTED bound to: 1'b0 2default:defaulthp x  a %s *synth2I 5 Parameter IS_TXPHDLYTSTCLK_INVERTED bound to: 1'b0 2default:defaulthp x  ] %s *synth2E 1 Parameter IS_TXUSRCLK2_INVERTED bound to: 1'b0 2default:defaulthp x  \ %s *synth2D 0 Parameter IS_TXUSRCLK_INVERTED bound to: 1'b0 2default:defaulthp x  Z %s *synth2B . Parameter OUTREFCLK_SEL_INV bound to: 2'b11 2default:defaulthp x  c %s *synth2K 7 Parameter PCS_PCIE_EN bound to: FALSE - type: string 2default:defaulthp x   %s *synth2m Y Parameter PCS_RSVD_ATTR bound to: 48'b000000000000000000000000000000000000000000000000 2default:defaulthp x  i %s *synth2Q = Parameter PD_TRANS_TIME_FROM_P2 bound to: 12'b000000111100 2default:defaulthp x  d %s *synth2L 8 Parameter PD_TRANS_TIME_NONE_P2 bound to: 8'b00011001 2default:defaulthp x  b %s *synth2J 6 Parameter PD_TRANS_TIME_TO_P2 bound to: 8'b01100100 2default:defaulthp x  ` %s *synth2H 4 Parameter PMA_RSV bound to: 99456 - type: integer 2default:defaulthp x  ` %s *synth2H 4 Parameter PMA_RSV2 bound to: 16'b0010000001010000 2default:defaulthp x  Q %s *synth29 % Parameter PMA_RSV3 bound to: 2'b00 2default:defaulthp x  p %s *synth2X D Parameter PMA_RSV4 bound to: 32'b00000000000000000000000000000000 2default:defaulthp x  [ %s *synth2C / Parameter RXBUFRESET_TIME bound to: 5'b00001 2default:defaulthp x  f %s *synth2N : Parameter RXBUF_ADDR_MODE bound to: FULL - type: string 2default:defaulthp x  ] %s *synth2E 1 Parameter RXBUF_EIDLE_HI_CNT bound to: 4'b1000 2default:defaulthp x  ] %s *synth2E 1 Parameter RXBUF_EIDLE_LO_CNT bound to: 4'b0000 2default:defaulthp x  _ %s *synth2G 3 Parameter RXBUF_EN bound to: TRUE - type: string 2default:defaulthp x  o %s *synth2W C Parameter RXBUF_RESET_ON_CB_CHANGE bound to: TRUE - type: string 2default:defaulthp x  q %s *synth2Y E Parameter RXBUF_RESET_ON_COMMAALIGN bound to: FALSE - type: string 2default:defaulthp x  l %s *synth2T @ Parameter RXBUF_RESET_ON_EIDLE bound to: FALSE - type: string 2default:defaulthp x  q %s *synth2Y E Parameter RXBUF_RESET_ON_RATE_CHANGE bound to: TRUE - type: string 2default:defaulthp x  h %s *synth2P < Parameter RXBUF_THRESH_OVFLW bound to: 61 - type: integer 2default:defaulthp x  i %s *synth2Q = Parameter RXBUF_THRESH_OVRD bound to: FALSE - type: string 2default:defaulthp x  h %s *synth2P < Parameter RXBUF_THRESH_UNDFLW bound to: 8 - type: integer 2default:defaulthp x  _ %s *synth2G 3 Parameter RXCDRFREQRESET_TIME bound to: 5'b00001 2default:defaulthp x  ] %s *synth2E 1 Parameter RXCDRPHRESET_TIME bound to: 5'b00001 2default:defaulthp x   %s *synth2 m Parameter RXCDR_CFG bound to: 72'b000000110000000000000000001000111111111100010000000100000000000000100000 2default:defaulthp x  _ %s *synth2G 3 Parameter RXCDR_FR_RESET_ON_EIDLE bound to: 1'b0 2default:defaulthp x  _ %s *synth2G 3 Parameter RXCDR_HOLD_DURING_EIDLE bound to: 1'b0 2default:defaulthp x  [ %s *synth2C / Parameter RXCDR_LOCK_CFG bound to: 6'b010101 2default:defaulthp x  _ %s *synth2G 3 Parameter RXCDR_PH_RESET_ON_EIDLE bound to: 1'b0 2default:defaulthp x  ` %s *synth2H 4 Parameter RXDFELPMRESET_TIME bound to: 7'b0001111 2default:defaulthp x  a %s *synth2I 5 Parameter RXDLY_CFG bound to: 16'b0000000000011111 2default:defaulthp x  ^ %s *synth2F 2 Parameter RXDLY_LCFG bound to: 12'b000000110000 2default:defaulthp x  e %s *synth2M 9 Parameter RXDLY_TAP_CFG bound to: 16'b0000000000000000 2default:defaulthp x  d %s *synth2L 8 Parameter RXGEARBOX_EN bound to: FALSE - type: string 2default:defaulthp x  ] %s *synth2E 1 Parameter RXISCANRESET_TIME bound to: 5'b00001 2default:defaulthp x  b %s *synth2J 6 Parameter RXLPM_HF_CFG bound to: 14'b00000011110000 2default:defaulthp x  b %s *synth2J 6 Parameter RXLPM_LF_CFG bound to: 14'b00000011110000 2default:defaulthp x  W %s *synth2? + Parameter RXOOB_CFG bound to: 7'b0000110 2default:defaulthp x  ^ %s *synth2F 2 Parameter RXOUT_DIV bound to: 4 - type: integer 2default:defaulthp x  [ %s *synth2C / Parameter RXPCSRESET_TIME bound to: 5'b00001 2default:defaulthp x  k %s *synth2S ? Parameter RXPHDLY_CFG bound to: 24'b000010000100000000100000 2default:defaulthp x  h %s *synth2P < Parameter RXPH_CFG bound to: 24'b000000000000000000000000 2default:defaulthp x  \ %s *synth2D 0 Parameter RXPH_MONITOR_SEL bound to: 5'b00000 2default:defaulthp x  [ %s *synth2C / Parameter RXPMARESET_TIME bound to: 5'b00011 2default:defaulthp x  [ %s *synth2C / Parameter RXPRBS_ERR_LOOPBACK bound to: 1'b0 2default:defaulthp x  f %s *synth2N : Parameter RXSLIDE_AUTO_WAIT bound to: 7 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter RXSLIDE_MODE bound to: OFF - type: string 2default:defaulthp x  _ %s *synth2G 3 Parameter RX_BIAS_CFG bound to: 12'b000000000100 2default:defaulthp x  Z %s *synth2B . Parameter RX_BUFFER_CFG bound to: 6'b000000 2default:defaulthp x  a %s *synth2I 5 Parameter RX_CLK25_DIV bound to: 5 - type: integer 2default:defaulthp x  T %s *synth2< ( Parameter RX_CLKMUX_PD bound to: 1'b1 2default:defaulthp x  R %s *synth2: & Parameter RX_CM_SEL bound to: 2'b11 2default:defaulthp x  T %s *synth2< ( Parameter RX_CM_TRIM bound to: 3'b010 2default:defaulthp x  c %s *synth2K 7 Parameter RX_DATA_WIDTH bound to: 20 - type: integer 2default:defaulthp x  W %s *synth2? + Parameter RX_DDI_SEL bound to: 6'b000000 2default:defaulthp x  ` %s *synth2H 4 Parameter RX_DEBUG_CFG bound to: 12'b000000000000 2default:defaulthp x  l %s *synth2T @ Parameter RX_DEFER_RESET_BUF_EN bound to: TRUE - type: string 2default:defaulthp x  o %s *synth2W C Parameter RX_DFE_GAIN_CFG bound to: 24'b000000100000111111101010 2default:defaulthp x  a %s *synth2I 5 Parameter RX_DFE_H2_CFG bound to: 12'b000000000000 2default:defaulthp x  a %s *synth2I 5 Parameter RX_DFE_H3_CFG bound to: 12'b000001000000 2default:defaulthp x  ` %s *synth2H 4 Parameter RX_DFE_H4_CFG bound to: 11'b00011110000 2default:defaulthp x  ` %s *synth2H 4 Parameter RX_DFE_H5_CFG bound to: 11'b00011100000 2default:defaulthp x  b %s *synth2J 6 Parameter RX_DFE_KL_CFG bound to: 13'b0000011111110 2default:defaulthp x  k %s *synth2S ? Parameter RX_DFE_KL_CFG2 bound to: 806439084 - type: integer 2default:defaulthp x  f %s *synth2N : Parameter RX_DFE_LPM_CFG bound to: 16'b0000100100000100 2default:defaulthp x  d %s *synth2L 8 Parameter RX_DFE_LPM_HOLD_DURING_EIDLE bound to: 1'b0 2default:defaulthp x  f %s *synth2N : Parameter RX_DFE_UT_CFG bound to: 17'b10001111000000000 2default:defaulthp x  f %s *synth2N : Parameter RX_DFE_VP_CFG bound to: 17'b00011111100000011 2default:defaulthp x  c %s *synth2K 7 Parameter RX_DFE_XYD_CFG bound to: 13'b0000000000000 2default:defaulthp x  k %s *synth2S ? Parameter RX_DISPERR_SEQ_MATCH bound to: TRUE - type: string 2default:defaulthp x  e %s *synth2M 9 Parameter RX_INT_DATAWIDTH bound to: 0 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter RX_OS_CFG bound to: 13'b0000010000000 2default:defaulthp x  f %s *synth2N : Parameter RX_SIG_VALID_DLY bound to: 10 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter RX_XCLK_SEL bound to: RXREC - type: string 2default:defaulthp x  a %s *synth2I 5 Parameter SAS_MAX_COM bound to: 64 - type: integer 2default:defaulthp x  a %s *synth2I 5 Parameter SAS_MIN_COM bound to: 36 - type: integer 2default:defaulthp x  ] %s *synth2E 1 Parameter SATA_BURST_SEQ_LEN bound to: 4'b0101 2default:defaulthp x  X %s *synth2@ , Parameter SATA_BURST_VAL bound to: 3'b100 2default:defaulthp x  k %s *synth2S ? Parameter SATA_CPLL_CFG bound to: VCO_3000MHZ - type: string 2default:defaulthp x  X %s *synth2@ , Parameter SATA_EIDLE_VAL bound to: 3'b100 2default:defaulthp x  c %s *synth2K 7 Parameter SATA_MAX_BURST bound to: 8 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter SATA_MAX_INIT bound to: 21 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter SATA_MAX_WAKE bound to: 7 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter SATA_MIN_BURST bound to: 4 - type: integer 2default:defaulthp x  c %s *synth2K 7 Parameter SATA_MIN_INIT bound to: 12 - type: integer 2default:defaulthp x  b %s *synth2J 6 Parameter SATA_MIN_WAKE bound to: 4 - type: integer 2default:defaulthp x  i %s *synth2Q = Parameter SHOW_REALIGN_COMMA bound to: TRUE - type: string 2default:defaulthp x  \ %s *synth2D 0 Parameter SIM_CPLLREFCLK_SEL bound to: 3'b001 2default:defaulthp x  o %s *synth2W C Parameter SIM_RECEIVER_DETECT_PASS bound to: TRUE - type: string 2default:defaulthp x  h %s *synth2P < Parameter SIM_RESET_SPEEDUP bound to: TRUE - type: string 2default:defaulthp x  l %s *synth2T @ Parameter SIM_TX_EIDLE_DRIVE_LEVEL bound to: X - type: string 2default:defaulthp x  a %s *synth2I 5 Parameter SIM_VERSION bound to: 4.0 - type: string 2default:defaulthp x  Y %s *synth2A - Parameter TERM_RCAL_CFG bound to: 5'b10000 2default:defaulthp x  V %s *synth2> * Parameter TERM_RCAL_OVRD bound to: 1'b0 2default:defaulthp x  ^ %s *synth2F 2 Parameter TRANS_TIME_RATE bound to: 8'b00001110 2default:defaulthp x  o %s *synth2W C Parameter TST_RSV bound to: 32'b00000000000000000000000000000000 2default:defaulthp x  _ %s *synth2G 3 Parameter TXBUF_EN bound to: TRUE - type: string 2default:defaulthp x  q %s *synth2Y E Parameter TXBUF_RESET_ON_RATE_CHANGE bound to: TRUE - type: string 2default:defaulthp x  a %s *synth2I 5 Parameter TXDLY_CFG bound to: 16'b0000000000011111 2default:defaulthp x  ^ %s *synth2F 2 Parameter TXDLY_LCFG bound to: 12'b000000110000 2default:defaulthp x  e %s *synth2M 9 Parameter TXDLY_TAP_CFG bound to: 16'b0000000000000000 2default:defaulthp x  d %s *synth2L 8 Parameter TXGEARBOX_EN bound to: FALSE - type: string 2default:defaulthp x  ^ %s *synth2F 2 Parameter TXOUT_DIV bound to: 4 - type: integer 2default:defaulthp x  [ %s *synth2C / Parameter TXPCSRESET_TIME bound to: 5'b00001 2default:defaulthp x  k %s *synth2S ? Parameter TXPHDLY_CFG bound to: 24'b000010000100000000100000 2default:defaulthp x  ` %s *synth2H 4 Parameter TXPH_CFG bound to: 16'b0000011110000000 2default:defaulthp x  \ %s *synth2D 0 Parameter TXPH_MONITOR_SEL bound to: 5'b00000 2default:defaulthp x  [ %s *synth2C / Parameter TXPMARESET_TIME bound to: 5'b00001 2default:defaulthp x  a %s *synth2I 5 Parameter TX_CLK25_DIV bound to: 5 - type: integer 2default:defaulthp x  T %s *synth2< ( Parameter TX_CLKMUX_PD bound to: 1'b1 2default:defaulthp x  c %s *synth2K 7 Parameter TX_DATA_WIDTH bound to: 20 - type: integer 2default:defaulthp x  V %s *synth2> * Parameter TX_DEEMPH0 bound to: 5'b00000 2default:defaulthp x  V %s *synth2> * Parameter TX_DEEMPH1 bound to: 5'b00000 2default:defaulthp x  f %s *synth2N : Parameter TX_DRIVE_MODE bound to: DIRECT - type: string 2default:defaulthp x  _ %s *synth2G 3 Parameter TX_EIDLE_ASSERT_DELAY bound to: 3'b110 2default:defaulthp x  a %s *synth2I 5 Parameter TX_EIDLE_DEASSERT_DELAY bound to: 3'b100 2default:defaulthp x  e %s *synth2M 9 Parameter TX_INT_DATAWIDTH bound to: 0 - type: integer 2default:defaulthp x  m %s *synth2U A Parameter TX_LOOPBACK_DRIVE_HIZ bound to: FALSE - type: string 2default:defaulthp x  Y %s *synth2A - Parameter TX_MAINCURSOR_SEL bound to: 1'b0 2default:defaulthp x  ^ %s *synth2F 2 Parameter TX_MARGIN_FULL_0 bound to: 7'b1001110 2default:defaulthp x  ^ %s *synth2F 2 Parameter TX_MARGIN_FULL_1 bound to: 7'b1001001 2default:defaulthp x  ^ %s *synth2F 2 Parameter TX_MARGIN_FULL_2 bound to: 7'b1000101 2default:defaulthp x  ^ %s *synth2F 2 Parameter TX_MARGIN_FULL_3 bound to: 7'b1000010 2default:defaulthp x  ^ %s *synth2F 2 Parameter TX_MARGIN_FULL_4 bound to: 7'b1000000 2default:defaulthp x  ] %s *synth2E 1 Parameter TX_MARGIN_LOW_0 bound to: 7'b1000110 2default:defaulthp x  ] %s *synth2E 1 Parameter TX_MARGIN_LOW_1 bound to: 7'b1000100 2default:defaulthp x  ] %s *synth2E 1 Parameter TX_MARGIN_LOW_2 bound to: 7'b1000010 2default:defaulthp x  ] %s *synth2E 1 Parameter TX_MARGIN_LOW_3 bound to: 7'b1000000 2default:defaulthp x  ] %s *synth2E 1 Parameter TX_MARGIN_LOW_4 bound to: 7'b1000000 2default:defaulthp x  Y %s *synth2A - Parameter TX_PREDRIVER_MODE bound to: 1'b0 2default:defaulthp x  X %s *synth2@ , Parameter TX_QPI_STATUS_EN bound to: 1'b0 2default:defaulthp x  g %s *synth2O ; Parameter TX_RXDETECT_CFG bound to: 16'b0001100000110010 2default:defaulthp x  Y %s *synth2A - Parameter TX_RXDETECT_REF bound to: 3'b100 2default:defaulthp x  c %s *synth2K 7 Parameter TX_XCLK_SEL bound to: TXOUT - type: string 2default:defaulthp x  S %s *synth2; ' Parameter UCODEER_CLR bound to: 1'b0 2default:defaulthp x   ,binding component instance '%s' to cell '%s'113*oasys2 gtxe2_i2default:default2! GTXE2_CHANNEL2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_gtwizard_gt.vhd2default:default2 2622default:default8@Z8-113hpx  %done synthesizing module '%s' (%s#%s)256*oasys29 %gig_ethernet_pcs_pma_16_1_GTWIZARD_GT2default:default2 112default:default2 12default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_gtwizard_gt.vhd2default:default2 2162default:default8@Z8-256hpx  Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2: &gig_ethernet_pcs_pma_16_1_cpll_railing2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_cpll_railing.vhd2default:default2 752default:default2# cpll_railing0_i2default:default2: &gig_ethernet_pcs_pma_16_1_cpll_railing2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_gtwizard_multi_gt.vhd2default:default2 5582default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys2: &gig_ethernet_pcs_pma_16_1_cpll_railing2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_cpll_railing.vhd2default:default2 862default:default8@Z8-638hpx  %done synthesizing module '%s' (%s#%s)256*oasys2: &gig_ethernet_pcs_pma_16_1_cpll_railing2default:default2 122default:default2 12default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_cpll_railing.vhd2default:default2 862default:default8@Z8-256hpx  %done synthesizing module '%s' (%s#%s)256*oasys2? +gig_ethernet_pcs_pma_16_1_GTWIZARD_multi_gt2default:default2 132default:default2 12default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_gtwizard_multi_gt.vhd2default:default2 2212default:default8@Z8-256hpx g %s *synth2O ; Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer 2default:defaulthp x  h %s *synth2P < Parameter STABLE_CLOCK_PERIOD bound to: 5 - type: integer 2default:defaulthp x  k %s *synth2S ? Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter TX_QPLL_USED bound to: 0 - type: bool 2default:defaulthp x  ^ %s *synth2F 2 Parameter RX_QPLL_USED bound to: 0 - type: bool 2default:defaulthp x  h %s *synth2P < Parameter PHASE_ALIGNMENT_MANUAL bound to: 0 - type: bool 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2< (gig_ethernet_pcs_pma_16_1_TX_STARTUP_FSM2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_tx_startup_fsm.vhd2default:default2 782default:default2$ gt0_txresetfsm_i2default:default2< (gig_ethernet_pcs_pma_16_1_TX_STARTUP_FSM2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_gtwizard_init.vhd2default:default2 7022default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys2< (gig_ethernet_pcs_pma_16_1_TX_STARTUP_FSM2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_tx_startup_fsm.vhd2default:default2 1252default:default8@Z8-638hpx g %s *synth2O ; Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer 2default:defaulthp x  h %s *synth2P < Parameter STABLE_CLOCK_PERIOD bound to: 5 - type: integer 2default:defaulthp x  k %s *synth2S ? Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter TX_QPLL_USED bound to: 0 - type: bool 2default:defaulthp x  ^ %s *synth2F 2 Parameter RX_QPLL_USED bound to: 0 - type: bool 2default:defaulthp x  h %s *synth2P < Parameter PHASE_ALIGNMENT_MANUAL bound to: 0 - type: bool 2default:defaulthp x  S %s *synth2; ' Parameter INITIALISE bound to: 2'b00 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys28 $gig_ethernet_pcs_pma_16_1_sync_block2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_sync_block.vhd2default:default2 672default:default20 sync_run_phase_alignment_int2default:default28 $gig_ethernet_pcs_pma_16_1_sync_block2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_tx_startup_fsm.vhd2default:default2 2952default:default8@Z8-3491hpx S %s *synth2; ' Parameter INITIALISE bound to: 2'b00 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys28 $gig_ethernet_pcs_pma_16_1_sync_block2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_sync_block.vhd2default:default2 672default:default2. sync_tx_fsm_reset_done_int2default:default28 $gig_ethernet_pcs_pma_16_1_sync_block2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_tx_startup_fsm.vhd2default:default2 3032default:default8@Z8-3491hpx S %s *synth2; ' Parameter INITIALISE bound to: 2'b00 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys28 $gig_ethernet_pcs_pma_16_1_sync_block2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_sync_block.vhd2default:default2 672default:default2$ sync_TXRESETDONE2default:default28 $gig_ethernet_pcs_pma_16_1_sync_block2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_tx_startup_fsm.vhd2default:default2 3202default:default8@Z8-3491hpx S %s *synth2; ' Parameter INITIALISE bound to: 2'b00 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys28 $gig_ethernet_pcs_pma_16_1_sync_block2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_sync_block.vhd2default:default2 672default:default2- sync_time_out_wait_bypass2default:default28 $gig_ethernet_pcs_pma_16_1_sync_block2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_tx_startup_fsm.vhd2default:default2 3282default:default8@Z8-3491hpx S %s *synth2; ' Parameter INITIALISE bound to: 2'b00 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys28 $gig_ethernet_pcs_pma_16_1_sync_block2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_sync_block.vhd2default:default2 672default:default2, sync_mmcm_lock_reclocked2default:default28 $gig_ethernet_pcs_pma_16_1_sync_block2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_tx_startup_fsm.vhd2default:default2 3362default:default8@Z8-3491hpx S %s *synth2; ' Parameter INITIALISE bound to: 2'b00 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys28 $gig_ethernet_pcs_pma_16_1_sync_block2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_sync_block.vhd2default:default2 672default:default2! sync_cplllock2default:default28 $gig_ethernet_pcs_pma_16_1_sync_block2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_tx_startup_fsm.vhd2default:default2 3562default:default8@Z8-3491hpx  +Unused sequential element %s was removed. 4326*oasys2% cplllock_prev_reg2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_tx_startup_fsm.vhd2default:default2 3512default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2% qplllock_prev_reg2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_tx_startup_fsm.vhd2default:default2 3522default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2) cplllock_ris_edge_reg2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_tx_startup_fsm.vhd2default:default2 3702default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2) qplllock_ris_edge_reg2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_tx_startup_fsm.vhd2default:default2 3852default:default8@Z8-6014hpx  %done synthesizing module '%s' (%s#%s)256*oasys2< (gig_ethernet_pcs_pma_16_1_TX_STARTUP_FSM2default:default2 142default:default2 12default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_tx_startup_fsm.vhd2default:default2 1252default:default8@Z8-256hpx g %s *synth2O ; Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer 2default:defaulthp x  ] %s *synth2E 1 Parameter EQ_MODE bound to: LPM - type: string 2default:defaulthp x  h %s *synth2P < Parameter STABLE_CLOCK_PERIOD bound to: 5 - type: integer 2default:defaulthp x  k %s *synth2S ? Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter TX_QPLL_USED bound to: 0 - type: bool 2default:defaulthp x  ^ %s *synth2F 2 Parameter RX_QPLL_USED bound to: 0 - type: bool 2default:defaulthp x  h %s *synth2P < Parameter PHASE_ALIGNMENT_MANUAL bound to: 0 - type: bool 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys2< (gig_ethernet_pcs_pma_16_1_RX_STARTUP_FSM2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_rx_startup_fsm.vhd2default:default2 762default:default2$ gt0_rxresetfsm_i2default:default2< (gig_ethernet_pcs_pma_16_1_RX_STARTUP_FSM2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_gtwizard_init.vhd2default:default2 7412default:default8@Z8-3491hpx  synthesizing module '%s'638*oasys2< (gig_ethernet_pcs_pma_16_1_RX_STARTUP_FSM2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_rx_startup_fsm.vhd2default:default2 1302default:default8@Z8-638hpx g %s *synth2O ; Parameter EXAMPLE_SIMULATION bound to: 0 - type: integer 2default:defaulthp x  ] %s *synth2E 1 Parameter EQ_MODE bound to: LPM - type: string 2default:defaulthp x  h %s *synth2P < Parameter STABLE_CLOCK_PERIOD bound to: 5 - type: integer 2default:defaulthp x  k %s *synth2S ? Parameter RETRY_COUNTER_BITWIDTH bound to: 8 - type: integer 2default:defaulthp x  ^ %s *synth2F 2 Parameter TX_QPLL_USED bound to: 0 - type: bool 2default:defaulthp x  ^ %s *synth2F 2 Parameter RX_QPLL_USED bound to: 0 - type: bool 2default:defaulthp x  h %s *synth2P < Parameter PHASE_ALIGNMENT_MANUAL bound to: 0 - type: bool 2default:defaulthp x  S %s *synth2; ' Parameter INITIALISE bound to: 2'b00 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys28 $gig_ethernet_pcs_pma_16_1_sync_block2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_sync_block.vhd2default:default2 672default:default20 sync_run_phase_alignment_int2default:default28 $gig_ethernet_pcs_pma_16_1_sync_block2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_rx_startup_fsm.vhd2default:default2 3772default:default8@Z8-3491hpx S %s *synth2; ' Parameter INITIALISE bound to: 2'b00 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys28 $gig_ethernet_pcs_pma_16_1_sync_block2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_sync_block.vhd2default:default2 672default:default2. sync_tx_fsm_reset_done_int2default:default28 $gig_ethernet_pcs_pma_16_1_sync_block2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_rx_startup_fsm.vhd2default:default2 3852default:default8@Z8-3491hpx S %s *synth2; ' Parameter INITIALISE bound to: 2'b00 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys28 $gig_ethernet_pcs_pma_16_1_sync_block2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_sync_block.vhd2default:default2 672default:default2$ sync_RXRESETDONE2default:default28 $gig_ethernet_pcs_pma_16_1_sync_block2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_rx_startup_fsm.vhd2default:default2 4022default:default8@Z8-3491hpx S %s *synth2; ' Parameter INITIALISE bound to: 2'b00 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys28 $gig_ethernet_pcs_pma_16_1_sync_block2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_sync_block.vhd2default:default2 672default:default2- sync_time_out_wait_bypass2default:default28 $gig_ethernet_pcs_pma_16_1_sync_block2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_rx_startup_fsm.vhd2default:default2 4102default:default8@Z8-3491hpx S %s *synth2; ' Parameter INITIALISE bound to: 2'b00 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys28 $gig_ethernet_pcs_pma_16_1_sync_block2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_sync_block.vhd2default:default2 672default:default2, sync_mmcm_lock_reclocked2default:default28 $gig_ethernet_pcs_pma_16_1_sync_block2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_rx_startup_fsm.vhd2default:default2 4182default:default8@Z8-3491hpx S %s *synth2; ' Parameter INITIALISE bound to: 2'b00 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys28 $gig_ethernet_pcs_pma_16_1_sync_block2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_sync_block.vhd2default:default2 672default:default2# sync_data_valid2default:default28 $gig_ethernet_pcs_pma_16_1_sync_block2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_rx_startup_fsm.vhd2default:default2 4262default:default8@Z8-3491hpx S %s *synth2; ' Parameter INITIALISE bound to: 2'b00 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys28 $gig_ethernet_pcs_pma_16_1_sync_block2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_sync_block.vhd2default:default2 672default:default2! sync_cplllock2default:default28 $gig_ethernet_pcs_pma_16_1_sync_block2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_rx_startup_fsm.vhd2default:default2 4462default:default8@Z8-3491hpx  +Unused sequential element %s was removed. 4326*oasys2& time_out_500us_reg2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_rx_startup_fsm.vhd2default:default2 3212default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2% cplllock_prev_reg2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_rx_startup_fsm.vhd2default:default2 4412default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2% qplllock_prev_reg2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_rx_startup_fsm.vhd2default:default2 4422default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2) cplllock_ris_edge_reg2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_rx_startup_fsm.vhd2default:default2 4582default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2) qplllock_ris_edge_reg2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_rx_startup_fsm.vhd2default:default2 4732default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2% refclk_stable_reg2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_rx_startup_fsm.vhd2default:default2 5062default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2+ refclk_stable_count_reg2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_rx_startup_fsm.vhd2default:default2 5052default:default8@Z8-6014hpx  +Unused sequential element %s was removed. 4326*oasys2* pll_reset_asserted_reg2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_rx_startup_fsm.vhd2default:default2 5562default:default8@Z8-6014hpx  %done synthesizing module '%s' (%s#%s)256*oasys2< (gig_ethernet_pcs_pma_16_1_RX_STARTUP_FSM2default:default2 152default:default2 12default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_rx_startup_fsm.vhd2default:default2 1302default:default8@Z8-256hpx  %done synthesizing module '%s' (%s#%s)256*oasys2; 'gig_ethernet_pcs_pma_16_1_GTWIZARD_init2default:default2 162default:default2 12default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_gtwizard_init.vhd2default:default2 2282default:default8@Z8-256hpx  %done synthesizing module '%s' (%s#%s)256*oasys26 "gig_ethernet_pcs_pma_16_1_GTWIZARD2default:default2 172default:default2 12default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_gtwizard.vhd2default:default2 2192default:default8@Z8-256hpx  %done synthesizing module '%s' (%s#%s)256*oasys29 %gig_ethernet_pcs_pma_16_1_transceiver2default:default2 182default:default2 12default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_transceiver.vhd2default:default2 1602default:default8@Z8-256hpx S %s *synth2; ' Parameter INITIALISE bound to: 2'b00 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys28 $gig_ethernet_pcs_pma_16_1_sync_block2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_sync_block.vhd2default:default2 672default:default2, sync_block_tx_reset_done2default:default28 $gig_ethernet_pcs_pma_16_1_sync_block2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_block.vhd2default:default2 6452default:default8@Z8-3491hpx S %s *synth2; ' Parameter INITIALISE bound to: 2'b00 2default:defaulthp x   Hmodule '%s' declared at '%s:%s' bound to instance '%s' of component '%s'3392*oasys28 $gig_ethernet_pcs_pma_16_1_sync_block2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_sync_block.vhd2default:default2 672default:default2, sync_block_rx_reset_done2default:default28 $gig_ethernet_pcs_pma_16_1_sync_block2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_block.vhd2default:default2 6522default:default8@Z8-3491hpx  %done synthesizing module '%s' (%s#%s)256*oasys23 gig_ethernet_pcs_pma_16_1_block2default:default2 192default:default2 12default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_block.vhd2default:default2 1562default:default8@Z8-256hpx  %done synthesizing module '%s' (%s#%s)256*oasys2- gig_ethernet_pcs_pma_16_12default:default2 202default:default2 12default:default2 zd:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1.vhd2default:default2 1572default:default8@Z8-256hpx  !design %s has unconnected port %s3331*oasys2< (gig_ethernet_pcs_pma_16_1_RX_STARTUP_FSM2default:default2" QPLLREFCLKLOST2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2< (gig_ethernet_pcs_pma_16_1_RX_STARTUP_FSM2default:default2" CPLLREFCLKLOST2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2< (gig_ethernet_pcs_pma_16_1_RX_STARTUP_FSM2default:default2 QPLLLOCK2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2< (gig_ethernet_pcs_pma_16_1_TX_STARTUP_FSM2default:default2" QPLLREFCLKLOST2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2< (gig_ethernet_pcs_pma_16_1_TX_STARTUP_FSM2default:default2 QPLLLOCK2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2; 'gig_ethernet_pcs_pma_16_1_GTWIZARD_init2default:default2$ gt0_cpllreset_in2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2; 'gig_ethernet_pcs_pma_16_1_GTWIZARD_init2default:default2# gt0_rxusrclk_in2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2; 'gig_ethernet_pcs_pma_16_1_GTWIZARD_init2default:default2$ gt0_rxusrclk2_in2default:defaultZ8-3331hpx z !design %s has unconnected port %s3331*oasys2 RX2default:default2 RXRUNDISP2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 RX2default:default2" RXBUFSTATUS[0]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 SYNCHRONISE2default:default2" RXBUFSTATUS[0]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2' LINK_TIMER_VALUE[9]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2' LINK_TIMER_VALUE[8]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2' LINK_TIMER_VALUE[7]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2' LINK_TIMER_VALUE[6]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2' LINK_TIMER_VALUE[5]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2' LINK_TIMER_VALUE[4]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2' LINK_TIMER_VALUE[3]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2' LINK_TIMER_VALUE[2]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2' LINK_TIMER_VALUE[1]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2' LINK_TIMER_VALUE[0]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2' LINK_TIMER_BASEX[9]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2' LINK_TIMER_BASEX[8]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2' LINK_TIMER_BASEX[7]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2' LINK_TIMER_BASEX[6]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2' LINK_TIMER_BASEX[5]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2' LINK_TIMER_BASEX[4]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2' LINK_TIMER_BASEX[3]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2' LINK_TIMER_BASEX[2]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2' LINK_TIMER_BASEX[1]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2' LINK_TIMER_BASEX[0]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2' LINK_TIMER_SGMII[9]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2' LINK_TIMER_SGMII[8]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2' LINK_TIMER_SGMII[7]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2' LINK_TIMER_SGMII[6]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2' LINK_TIMER_SGMII[5]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2' LINK_TIMER_SGMII[4]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2' LINK_TIMER_SGMII[3]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2' LINK_TIMER_SGMII[2]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2' LINK_TIMER_SGMII[1]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2' LINK_TIMER_SGMII[0]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2- RX_GT_NOMINAL_LATENCY[15]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2- RX_GT_NOMINAL_LATENCY[14]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2- RX_GT_NOMINAL_LATENCY[13]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2- RX_GT_NOMINAL_LATENCY[12]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2- RX_GT_NOMINAL_LATENCY[11]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2- RX_GT_NOMINAL_LATENCY[10]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2, RX_GT_NOMINAL_LATENCY[9]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2, RX_GT_NOMINAL_LATENCY[8]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2, RX_GT_NOMINAL_LATENCY[7]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2, RX_GT_NOMINAL_LATENCY[6]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2, RX_GT_NOMINAL_LATENCY[5]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2, RX_GT_NOMINAL_LATENCY[4]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2, RX_GT_NOMINAL_LATENCY[3]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2, RX_GT_NOMINAL_LATENCY[2]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2, RX_GT_NOMINAL_LATENCY[1]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2, RX_GT_NOMINAL_LATENCY[0]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2# SPEED_IS_10_1002default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2 SPEED_IS_1002default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2 GTX_CLK2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2% RX_CODE_GROUP0[9]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2% RX_CODE_GROUP0[8]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2% RX_CODE_GROUP0[7]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2% RX_CODE_GROUP0[6]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2% RX_CODE_GROUP0[5]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2% RX_CODE_GROUP0[4]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2% RX_CODE_GROUP0[3]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2% RX_CODE_GROUP0[2]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2% RX_CODE_GROUP0[1]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2% RX_CODE_GROUP0[0]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2% RX_CODE_GROUP1[9]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2% RX_CODE_GROUP1[8]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2% RX_CODE_GROUP1[7]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2% RX_CODE_GROUP1[6]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2% RX_CODE_GROUP1[5]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2% RX_CODE_GROUP1[4]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2% RX_CODE_GROUP1[3]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2% RX_CODE_GROUP1[2]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2% RX_CODE_GROUP1[1]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2% RX_CODE_GROUP1[0]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2 PMA_RX_CLK02default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2 PMA_RX_CLK12default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2 PHYAD[4]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2 PHYAD[3]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2 PHYAD[2]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2 PHYAD[1]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2 PHYAD[0]2default:defaultZ8-3331hpx ~ !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2 MDC2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2 MDIO_IN2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2' CONFIGURATION_VALID2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2, AN_ADV_CONFIG_VECTOR[15]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2, AN_ADV_CONFIG_VECTOR[14]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2, AN_ADV_CONFIG_VECTOR[13]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2, AN_ADV_CONFIG_VECTOR[12]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2, AN_ADV_CONFIG_VECTOR[11]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2, AN_ADV_CONFIG_VECTOR[10]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2+ AN_ADV_CONFIG_VECTOR[9]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2+ AN_ADV_CONFIG_VECTOR[8]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2+ AN_ADV_CONFIG_VECTOR[7]2default:defaultZ8-3331hpx  !design %s has unconnected port %s3331*oasys2 GPCS_PMA_GEN2default:default2+ AN_ADV_CONFIG_VECTOR[6]2default:defaultZ8-3331hpx  Message '%s' appears more than %s times and has been disabled. User can change this message limit to see more message instances. 14*common2 Synth 8-33312default:default2 1002default:defaultZ17-14hpx  %s *synth2 xFinished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 543.715 ; gain = 171.918 2default:defaulthp x  D %s *synth2,  Report Check Netlist: 2default:defaulthp x  u %s *synth2] I+------+------------------+-------+---------+-------+------------------+ 2default:defaulthp x  u %s *synth2] I| |Item |Errors |Warnings |Status |Description | 2default:defaulthp x  u %s *synth2] I+------+------------------+-------+---------+-------+------------------+ 2default:defaulthp x  u %s *synth2] I|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | 2default:defaulthp x  u %s *synth2] I+------+------------------+-------+---------+-------+------------------+ 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  M %s *synth25 !Start Handling Custom Attributes 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 543.715 ; gain = 171.918 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 543.715 ; gain = 171.918 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  g -Analyzing %s Unisim elements for replacement 17*netlist2 1402default:defaultZ29-17hpx j 2Unisim Transformation completed in %s CPU seconds 28*netlist2 02default:defaultZ29-28hpx X Loading part %s157*device2% xc7k420tffg1156-22default:defaultZ21-403hpx K )Preparing netlist for logic optimization 349*projectZ1-570hpx >  Processing XDC Constraints 244*projectZ1-262hpx = Initializing timing engine 348*projectZ1-569hpx  $Parsing XDC File [%s] for cell '%s' 848* designutils2 ~d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_ooc.xdc2default:default2 U0 2default:default8Z20-848hpx  -Finished Parsing XDC File [%s] for cell '%s' 847* designutils2 ~d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1_ooc.xdc2default:default2 U0 2default:default8Z20-847hpx  $Parsing XDC File [%s] for cell '%s' 848* designutils2 zd:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/gig_ethernet_pcs_pma_16_1_board.xdc2default:default2 U0 2default:default8Z20-848hpx  -Finished Parsing XDC File [%s] for cell '%s' 847* designutils2 zd:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/gig_ethernet_pcs_pma_16_1_board.xdc2default:default2 U0 2default:default8Z20-847hpx  $Parsing XDC File [%s] for cell '%s' 848* designutils2 zd:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1.xdc2default:default2 U0 2default:default8Z20-848hpx  -Finished Parsing XDC File [%s] for cell '%s' 847* designutils2 zd:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/gig_ethernet_pcs_pma_16_1.xdc2default:default2 U0 2default:default8Z20-847hpx  Parsing XDC File [%s] 179* designutils2v `D:/Design_collection/ngFECv0x43d/ngFEC_new.runs/gig_ethernet_pcs_pma_16_1_synth_1/dont_touch.xdc2default:default8Z20-179hpx  Finished Parsing XDC File [%s] 178* designutils2v `D:/Design_collection/ngFECv0x43d/ngFEC_new.runs/gig_ethernet_pcs_pma_16_1_synth_1/dont_touch.xdc2default:default8Z20-178hpx H &Completed Processing XDC Constraints 245*projectZ1-263hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2. Netlist sorting complete. 2default:default2 00:00:002default:default2 00:00:00.0012default:default2 971.7422default:default2 0.0002default:defaultZ17-268hp x   !Unisim Transformation Summary: %s111*project2  A total of 140 instances were transformed. FD => FDRE: 102 instances FDP => FDPE: 36 instances SRL16 => SRL16E: 2 instances 2default:defaultZ1-111hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2. Netlist sorting complete. 2default:default2 00:00:002default:default2 00:00:00.0022default:default2 971.8282default:default2 0.0002default:defaultZ17-268hp x   I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common24 Constraint Validation Runtime : 2default:default2 00:00:002default:default2 00:00:00.0462default:default2 973.3202default:default2 1.5782default:defaultZ17-268hp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 ~Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 973.320 ; gain = 601.523 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  V %s *synth2> *Start Loading Part and Timing Information 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  L %s *synth24 Loading part: xc7k420tffg1156-2 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 973.320 ; gain = 601.523 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  Z %s *synth2B .Start Applying 'set_property' XDC Constraints 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 973.320 ; gain = 601.523 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2# XMIT_CONFIG_INT2default:default2 22default:default2 52default:defaultZ8-5544hpx x 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 EXT_CODE2default:defaultZ8-5546hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2# XMIT_CONFIG_INT2default:default2 22default:default2 52default:defaultZ8-5544hpx x 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 EXT_CODE2default:defaultZ8-5546hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 CONFIG_DATA2default:default2 12default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 TX_CONFIG2default:default2 22default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 C1_OR_C22default:default2 22default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 TXDATA2default:default2 12default:default2 52default:defaultZ8-5544hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2 STATE_reg2default:default2 SYNCHRONISE2default:defaultZ8-802hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 NEXT_STATE2default:default2 12default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 NEXT_STATE2default:default2 12default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 NEXT_STATE2default:default2 12default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 NEXT_STATE2default:default2 12default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 NEXT_STATE2default:default2 12default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 NEXT_STATE2default:default2 12default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 NEXT_STATE2default:default2 12default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 NEXT_STATE2default:default2 12default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 NEXT_STATE2default:default2 12default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 NEXT_STATE2default:default2 22default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 NEXT_STATE2default:default2 22default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 NEXT_STATE2default:default2 22default:default2 52default:defaultZ8-5544hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2/ USE_ROCKET_IO.TX_RST_SM_reg2default:default2 GPCS_PMA_GEN2default:defaultZ8-802hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2B .USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg2default:default2 GPCS_PMA_GEN2default:defaultZ8-802hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2$ MGT_TX_RESET_INT2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 TX_RST_SM2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2$ MGT_RX_RESET_INT2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 RX_RST_SM2default:default2 42default:default2 52default:defaultZ8-5544hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2 tx_state_reg2default:default2< (gig_ethernet_pcs_pma_16_1_TX_STARTUP_FSM2default:defaultZ8-802hpx ~ 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2" init_wait_done2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2# init_wait_count2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2$ time_out_counter2default:defaultZ8-5546hpx | 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 time_out_2ms2default:defaultZ8-5546hpx ~ 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2" time_tlock_max2default:defaultZ8-5546hpx ~ 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2" time_out_500us2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2% wait_bypass_count2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2( time_out_wait_bypass2default:defaultZ8-5546hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2! refclk_stable2default:default2 322default:default2 252default:defaultZ8-5545hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2' refclk_stable_count2default:default2 322default:default2 252default:defaultZ8-5545hpx ~ 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2" wait_time_done2default:defaultZ8-5546hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 TXUSERRDY2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 gttxreset_i2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 MMCM_RESET2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2) tx_fsm_reset_done_int2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 CPLL_RESET2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2+ run_phase_alignment_int2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 tx_state2default:default2 12default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 tx_state2default:default2 12default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 tx_state2default:default2 12default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 tx_state2default:default2 12default:default2 52default:defaultZ8-5544hpx  merging register '%s' into '%s'3619*oasys2" CPLL_RESET_reg2default:default2" QPLL_RESET_reg2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_rx_startup_fsm.vhd2default:default2 5552default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2. recclk_mon_count_reset_reg2default:default2) adapt_count_reset_reg2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_rx_startup_fsm.vhd2default:default2 2992default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2# RXDFELFHOLD_reg2default:default2$ RXDFEAGCHOLD_reg2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_rx_startup_fsm.vhd2default:default2 5652default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2# RXLPMLFHOLD_reg2default:default2$ RXDFEAGCHOLD_reg2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_rx_startup_fsm.vhd2default:default2 5662default:default8@Z8-4471hpx  merging register '%s' into '%s'3619*oasys2# RXLPMHFHOLD_reg2default:default2$ RXDFEAGCHOLD_reg2default:default2 d:/Design_collection/ngFECv0x43d/ngFEC_new.srcs/sources_1/ip/gig_ethernet_pcs_pma_16_1/synth/transceiver/gig_ethernet_pcs_pma_16_1_rx_startup_fsm.vhd2default:default2 5672default:default8@Z8-4471hpx  3inferred FSM for state register '%s' in module '%s'802*oasys2 rx_state_reg2default:default2< (gig_ethernet_pcs_pma_16_1_RX_STARTUP_FSM2default:defaultZ8-802hpx ~ 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2" init_wait_done2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2# init_wait_count2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2$ time_out_counter2default:defaultZ8-5546hpx | 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 time_out_2ms2default:defaultZ8-5546hpx | 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 time_out_1us2default:defaultZ8-5546hpx ~ 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2" time_out_100us2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2% wait_bypass_count2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2( time_out_wait_bypass2default:defaultZ8-5546hpx ~ 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2" wait_time_done2default:defaultZ8-5546hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2% retry_counter_int2default:default2 22default:default2 52default:defaultZ8-5544hpx { 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2 adapt_count2default:defaultZ8-5546hpx ~ 8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2" time_out_adapt2default:defaultZ8-5546hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 gtrxreset_i2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 mmcm_reset_i2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2+ run_phase_alignment_int2default:default2 42default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 rx_state2default:default2 12default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 rx_state2default:default2 22default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 rx_state2default:default2 12default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 rx_state2default:default2 12default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 rx_state2default:default2 12default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2 rx_state2default:default2 12default:default2 52default:defaultZ8-5544hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2$ gt0_rx_cdrlocked2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2* gt0_rx_cdrlock_counter2default:defaultZ8-5546hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ loss_of_sync | 0000000000100 | 0000 2default:defaulthp x   %s *synth2s _ comma_detect_1 | 0010000000000 | 0001 2default:defaulthp x   %s *synth2s _ aquire_sync_1 | 0000000010000 | 0010 2default:defaulthp x   %s *synth2s _ comma_detect_2 | 0000000000001 | 0011 2default:defaulthp x   %s *synth2s _ aquire_sync_2 | 0000000000010 | 0100 2default:defaulthp x   %s *synth2s _ comma_detect_3 | 0000000001000 | 0101 2default:defaulthp x   %s *synth2s _ sync_acquired_1 | 1000000000000 | 0110 2default:defaulthp x   %s *synth2s _ sync_acquired_2 | 0001000000000 | 0111 2default:defaulthp x   %s *synth2s _ sync_acquired_2a | 0100000000000 | 1000 2default:defaulthp x   %s *synth2s _ sync_acquired_3 | 0000001000000 | 1001 2default:defaulthp x   %s *synth2s _ sync_acquired_3a | 0000100000000 | 1010 2default:defaulthp x   %s *synth2s _ sync_acquired_4 | 0000010000000 | 1011 2default:defaulthp x   %s *synth2s _ sync_acquired_4a | 0000000100000 | 1100 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2 STATE_reg2default:default2 one-hot2default:default2 SYNCHRONISE2default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ iSTATE7 | 000000000000001 | 0000 2default:defaulthp x   %s *synth2s _ iSTATE6 | 000000000000010 | 0001 2default:defaulthp x   %s *synth2s _ iSTATE2 | 000000000000100 | 0010 2default:defaulthp x   %s *synth2s _ iSTATE | 000000000001000 | 0011 2default:defaulthp x   %s *synth2s _ iSTATE0 | 000000000010000 | 0100 2default:defaulthp x   %s *synth2s _ iSTATE13 | 000000000100000 | 0101 2default:defaulthp x   %s *synth2s _ iSTATE11 | 000000001000000 | 0110 2default:defaulthp x   %s *synth2s _ iSTATE9 | 000000010000000 | 0111 2default:defaulthp x   %s *synth2s _ iSTATE10 | 000000100000000 | 1000 2default:defaulthp x   %s *synth2s _ iSTATE8 | 000001000000000 | 1001 2default:defaulthp x   %s *synth2s _ iSTATE5 | 000010000000000 | 1010 2default:defaulthp x   %s *synth2s _ iSTATE3 | 000100000000000 | 1011 2default:defaulthp x   %s *synth2s _ iSTATE4 | 001000000000000 | 1100 2default:defaulthp x   %s *synth2s _ iSTATE1 | 010000000000000 | 1101 2default:defaulthp x   %s *synth2s _ iSTATE12 | 100000000000000 | 1110 2default:defaulthp x  . %s *synth2 * 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2B .USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg2default:default2 one-hot2default:default2 GPCS_PMA_GEN2default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ iSTATE7 | 000000000000001 | 0000 2default:defaulthp x   %s *synth2s _ iSTATE6 | 000000000000010 | 0001 2default:defaulthp x   %s *synth2s _ iSTATE2 | 000000000000100 | 0010 2default:defaulthp x   %s *synth2s _ iSTATE | 000000000001000 | 0011 2default:defaulthp x   %s *synth2s _ iSTATE0 | 000000000010000 | 0100 2default:defaulthp x   %s *synth2s _ iSTATE13 | 000000000100000 | 0101 2default:defaulthp x   %s *synth2s _ iSTATE11 | 000000001000000 | 0110 2default:defaulthp x   %s *synth2s _ iSTATE9 | 000000010000000 | 0111 2default:defaulthp x   %s *synth2s _ iSTATE10 | 000000100000000 | 1000 2default:defaulthp x   %s *synth2s _ iSTATE8 | 000001000000000 | 1001 2default:defaulthp x   %s *synth2s _ iSTATE5 | 000010000000000 | 1010 2default:defaulthp x   %s *synth2s _ iSTATE3 | 000100000000000 | 1011 2default:defaulthp x   %s *synth2s _ iSTATE4 | 001000000000000 | 1100 2default:defaulthp x   %s *synth2s _ iSTATE1 | 010000000000000 | 1101 2default:defaulthp x   %s *synth2s _ iSTATE12 | 100000000000000 | 1110 2default:defaulthp x  . %s *synth2 * 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2/ USE_ROCKET_IO.TX_RST_SM_reg2default:default2 one-hot2default:default2 GPCS_PMA_GEN2default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ init | 0000 | 0000 2default:defaulthp x   %s *synth2s _ assert_all_resets | 0001 | 0001 2default:defaulthp x   %s *synth2s _ wait_for_pll_lock | 0010 | 0010 2default:defaulthp x   %s *synth2s _ release_pll_reset | 0011 | 0011 2default:defaulthp x   %s *synth2s _ wait_for_txoutclk | 0100 | 0100 2default:defaulthp x   %s *synth2s _ release_mmcm_reset | 0101 | 0101 2default:defaulthp x   %s *synth2s _ wait_for_txusrclk | 0110 | 0110 2default:defaulthp x   %s *synth2s _ wait_reset_done | 0111 | 0111 2default:defaulthp x   %s *synth2s _ do_phase_alignment | 1000 | 1000 2default:defaulthp x   %s *synth2s _ reset_fsm_done | 1001 | 1001 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2 tx_state_reg2default:default2 sequential2default:default2< (gig_ethernet_pcs_pma_16_1_TX_STARTUP_FSM2default:defaultZ8-3354hpx  %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2t ` State | New Encoding | Previous Encoding 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2s _ init | 0000 | 0000 2default:defaulthp x   %s *synth2s _ assert_all_resets | 0001 | 0001 2default:defaulthp x   %s *synth2s _ wait_for_pll_lock | 0010 | 0010 2default:defaulthp x   %s *synth2s _ release_pll_reset | 0011 | 0011 2default:defaulthp x   %s *synth2s _ verify_recclk_stable | 0100 | 0100 2default:defaulthp x   %s *synth2s _ release_mmcm_reset | 0101 | 0101 2default:defaulthp x   %s *synth2s _ wait_for_rxusrclk | 0110 | 0110 2default:defaulthp x   %s *synth2s _ wait_reset_done | 0111 | 0111 2default:defaulthp x   %s *synth2s _ do_phase_alignment | 1000 | 1000 2default:defaulthp x   %s *synth2s _ monitor_data_valid | 1001 | 1001 2default:defaulthp x   %s *synth2s _ fsm_done | 1010 | 1010 2default:defaulthp x   %s *synth2x d--------------------------------------------------------------------------------------------------- 2default:defaulthp x   Gencoded FSM with state register '%s' using encoding '%s' in module '%s'3353*oasys2 rx_state_reg2default:default2 sequential2default:default2< (gig_ethernet_pcs_pma_16_1_RX_STARTUP_FSM2default:defaultZ8-3354hpx ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 973.320 ; gain = 601.523 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  E %s *synth2-  Report RTL Partitions: 2default:defaulthp x  W %s *synth2? ++-+--------------+------------+----------+ 2default:defaulthp x  W %s *synth2? +| |RTL Partition |Replication |Instances | 2default:defaulthp x  W %s *synth2? ++-+--------------+------------+----------+ 2default:defaulthp x  W %s *synth2? ++-+--------------+------------+----------+ 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  L %s *synth24 Start RTL Component Statistics 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Adders := 4 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Adders := 4 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Adders := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Adders := 3 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 4 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 128 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 96 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 6 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 18 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 4 2default:defaulthp x  Z %s *synth2B . 6 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 4 2default:defaulthp x  Z %s *synth2B . 2 Bit Registers := 23 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 172 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 15 Input 15 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 13 Input 13 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 13 Bit Muxes := 18 2default:defaulthp x  Z %s *synth2B . 8 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 9 2default:defaulthp x  Z %s *synth2B . 3 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 10 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 10 2default:defaulthp x  Z %s *synth2B . 11 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 72 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 15 Input 1 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 10 Input 1 Bit Muxes := 17 2default:defaulthp x  Z %s *synth2B . 11 Input 1 Bit Muxes := 19 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  O %s *synth27 #Finished RTL Component Statistics 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  Y %s *synth2A -Start RTL Hierarchical Component Statistics 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  O %s *synth27 #Hierarchical RTL Component report 2default:defaulthp x  7 %s *synth2 Module TX 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Adders := 1 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 3 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 4 2default:defaulthp x  Z %s *synth2B . 2 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 22 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 8 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 5 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 10 2default:defaulthp x  Z %s *synth2B . 4 Input 1 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 5 Input 1 Bit Muxes := 1 2default:defaulthp x  @ %s *synth2( Module SYNCHRONISE 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 2 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 4 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 13 Input 13 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 13 Bit Muxes := 18 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  7 %s *synth2 Module RX 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  8 %s *synth2 +---XORs : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit XORs := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 6 2default:defaulthp x  Z %s *synth2B . 4 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 61 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 3 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 6 2default:defaulthp x  A %s *synth2) Module GPCS_PMA_GEN 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 5 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 2 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 22 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 15 Input 15 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B . 3 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 7 2default:defaulthp x  Z %s *synth2B . 15 Input 1 Bit Muxes := 2 2default:defaulthp x  ^ %s *synth2F 2Module gig_ethernet_pcs_pma_16_1_reset_wtd_timer 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 6 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 6 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  [ %s *synth2C /Module gig_ethernet_pcs_pma_16_1_cpll_railing 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 128 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 96 Bit Registers := 1 2default:defaulthp x  ] %s *synth2E 1Module gig_ethernet_pcs_pma_16_1_TX_STARTUP_FSM 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Adders := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Adders := 2 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 21 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 10 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 4 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 18 2default:defaulthp x  Z %s *synth2B . 10 Input 1 Bit Muxes := 17 2default:defaulthp x  ] %s *synth2E 1Module gig_ethernet_pcs_pma_16_1_RX_STARTUP_FSM 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  : %s *synth2" +---Adders : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Adders := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 7 Bit Adders := 2 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Adders := 1 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 7 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 2 Bit Registers := 1 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 23 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 11 Input 4 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 4 Bit Muxes := 6 2default:defaulthp x  Z %s *synth2B . 2 Input 2 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 22 2default:defaulthp x  Z %s *synth2B . 11 Input 1 Bit Muxes := 19 2default:defaulthp x  \ %s *synth2D 0Module gig_ethernet_pcs_pma_16_1_GTWIZARD_init 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 1 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 2 2default:defaulthp x  Z %s *synth2B .Module gig_ethernet_pcs_pma_16_1_transceiver 2default:defaulthp x  K %s *synth23 Detailed RTL Component Info : 2default:defaulthp x  = %s *synth2% +---Registers : 2default:defaulthp x  Z %s *synth2B . 16 Bit Registers := 4 2default:defaulthp x  Z %s *synth2B . 8 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 3 Bit Registers := 2 2default:defaulthp x  Z %s *synth2B . 2 Bit Registers := 19 2default:defaulthp x  Z %s *synth2B . 1 Bit Registers := 17 2default:defaulthp x  9 %s *synth2! +---Muxes : 2default:defaulthp x  Z %s *synth2B . 2 Input 8 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 3 Input 3 Bit Muxes := 1 2default:defaulthp x  Z %s *synth2B . 2 Input 1 Bit Muxes := 5 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  [ %s *synth2C /Finished RTL Hierarchical Component Statistics 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  H %s *synth20 Start Part Resource Summary 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2o [Part Resources: DSPs: 1680 (col length:160) BRAMs: 1670 (col length: RAMB18 160 RAMB36 80) 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  K %s *synth23 Finished Part Resource Summary 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  W %s *synth2? +Start Cross Boundary and Area Optimization 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ] %s *synth2E 1Warning: Parallel synthesis criteria is not met 2default:defaulthp x   [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2Y Egpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/XMIT_CONFIG_INT2default:default2 22default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2P gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/EXT_CODE2default:defaultZ8-5546hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2X Dtransceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/retry_counter_int2default:default2 22default:default2 52default:defaultZ8-5544hpx  [ROM "%s" won't be mapped to Block RAM because address size (%s) smaller than threshold (%s)3996*oasys2O ;transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/rx_state2default:default2 22default:default2 52default:defaultZ8-5544hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2V Btransceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_count2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2U Atransceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/init_wait_done2default:defaultZ8-5546hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2Z Ftransceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/refclk_stable_count2default:default2 322default:default2 252default:defaultZ8-5545hpx  ^ROM "%s" won't be mapped to RAM because address size (%s) is larger than maximum supported(%s)3997*oasys2T @transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/refclk_stable2default:default2 322default:default2 252default:defaultZ8-5545hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2U Atransceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_time_done2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2W Ctransceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/time_out_counter2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2S ?transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/time_out_2ms2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2U Atransceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/time_tlock_max2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2U Atransceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/time_out_500us2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2X Dtransceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/wait_bypass_count2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2[ Gtransceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/time_out_wait_bypass2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2V Btransceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_count2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2U Atransceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/init_wait_done2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2U Atransceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/wait_time_done2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2W Ctransceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_counter2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2S ?transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_2ms2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2U Atransceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_100us2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2S ?transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_1us2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2R >transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/adapt_count2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2U Atransceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_adapt2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2X Dtransceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/wait_bypass_count2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2[ Gtransceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/time_out_wait_bypass2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2L 8transceiver_inst/gtwizard_inst/U0/gt0_rx_cdrlock_counter2default:defaultZ8-5546hpx  8ROM "%s" won't be mapped to RAM because it is too sparse3998*oasys2F 2transceiver_inst/gtwizard_inst/U0/gt0_rx_cdrlocked2default:defaultZ8-5546hpx  "merging instance '%s' (%s) to '%s'3436*oasys2} iU0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/TX_CONFIG_reg[11]2default:default2 FDRE2default:default2} iU0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/TX_CONFIG_reg[15]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2| hU0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/TX_CONFIG_reg[3]2default:default2 FDRE2default:default2} iU0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/TX_CONFIG_reg[15]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2| hU0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/TX_CONFIG_reg[2]2default:default2 FDRE2default:default2} iU0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/TX_CONFIG_reg[15]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2} iU0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/TX_CONFIG_reg[10]2default:default2 FDRE2default:default2} iU0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/TX_CONFIG_reg[15]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2| hU0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/TX_CONFIG_reg[0]2default:default2 FDRE2default:default2} iU0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/TX_CONFIG_reg[15]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2| hU0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/TX_CONFIG_reg[8]2default:default2 FDRE2default:default2} iU0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/TX_CONFIG_reg[15]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2| hU0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/TX_CONFIG_reg[1]2default:default2 FDRE2default:default2} iU0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/TX_CONFIG_reg[15]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2| hU0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/TX_CONFIG_reg[9]2default:default2 FDRE2default:default2} iU0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/TX_CONFIG_reg[15]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2| hU0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/TX_CONFIG_reg[5]2default:default2 FDRE2default:default2} iU0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/TX_CONFIG_reg[15]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2} iU0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/TX_CONFIG_reg[13]2default:default2 FDRE2default:default2} iU0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/TX_CONFIG_reg[15]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2| hU0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/TX_CONFIG_reg[7]2default:default2 FDRE2default:default2} iU0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/TX_CONFIG_reg[15]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2} iU0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/TX_CONFIG_reg[15]2default:default2 FDRE2default:default2} iU0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/TX_CONFIG_reg[14]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2| hU0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/TX_CONFIG_reg[6]2default:default2 FDRE2default:default2} iU0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/TX_CONFIG_reg[14]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2} iU0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/TX_CONFIG_reg[14]2default:default2 FDRE2default:default2} iU0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/TX_CONFIG_reg[12]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2| hU0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/TX_CONFIG_reg[4]2default:default2 FDRE2default:default2} iU0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/TX_CONFIG_reg[12]2default:defaultZ8-3886hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2 kU0/gig_ethernet_pcs_pma_16_1_core/\gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/TX_CONFIG_reg[12] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2< (U0/\transceiver_inst/rxclkcorcnt_reg[2] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2k WU0/\transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/recclk_mon_restart_count_reg[0] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2k WU0/\transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/recclk_mon_restart_count_reg[1] 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2_ KU0/gig_ethernet_pcs_pma_16_1_core/\gpcs_pma_inst/DUPLEX_MODE_RSLVD_REG_reg 2default:defaultZ8-3333hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2\ HU0/\transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/RXDFEAGCHOLD_reg 2default:defaultZ8-3333hpx  "merging instance '%s' (%s) to '%s'3436*oasys2~ jU0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/CONFIG_DATA_reg[2]2default:default2 FDR2default:default2~ jU0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/CONFIG_DATA_reg[4]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2~ jU0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/CONFIG_DATA_reg[1]2default:default2 FDR2default:default2~ jU0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/CONFIG_DATA_reg[6]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2~ jU0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/CONFIG_DATA_reg[5]2default:default2 FDR2default:default2~ jU0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/CONFIG_DATA_reg[4]2default:defaultZ8-3886hpx  "merging instance '%s' (%s) to '%s'3436*oasys2~ jU0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/CONFIG_DATA_reg[7]2default:default2 FDR2default:default2~ jU0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/CONFIG_DATA_reg[4]2default:defaultZ8-3886hpx  6propagating constant %s across sequential element (%s)3333*oasys2 02default:default2[ GU0/gig_ethernet_pcs_pma_16_1_core/\gpcs_pma_inst/STATUS_VECTOR_reg[12] 2default:defaultZ8-3333hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2_ Kgpcs_pma_inst/FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[14]2default:default20 gig_ethernet_pcs_pma_v16_1_52default:defaultZ8-3332hpx  ESequential element (%s) is unused and will be removed from module %s.3332*oasys2L 8gpcs_pma_inst/FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[14]2default:default20 gig_ethernet_pcs_pma_v16_1_52default:defaultZ8-3332hpx ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:19 ; elapsed = 00:00:21 . Memory (MB): peak = 973.320 ; gain = 601.523 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  E %s *synth2-  Report RTL Partitions: 2default:defaulthp x  W %s *synth2? ++-+--------------+------------+----------+ 2default:defaulthp x  W %s *synth2? +| |RTL Partition |Replication |Instances | 2default:defaulthp x  W %s *synth2? ++-+--------------+------------+----------+ 2default:defaulthp x  W %s *synth2? ++-+--------------+------------+----------+ 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  R %s *synth2: &Start Applying XDC Timing Constraints 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 973.320 ; gain = 601.523 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  F %s *synth2. Start Timing Optimization 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   Ecannot merge instances %s and %s because of non-equivalent assertions139*oasys2s _U0/\transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_mmcm_lock_reclocked/data_sync_reg1 2default:default2s _U0/\transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_mmcm_lock_reclocked/data_sync_reg1 2default:defaultZ8-139hpx  Ecannot merge instances %s and %s because of non-equivalent assertions139*oasys2s _U0/\transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_mmcm_lock_reclocked/data_sync_reg1 2default:default2s _U0/\transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_mmcm_lock_reclocked/data_sync_reg1 2default:defaultZ8-139hpx  Ecannot merge instances %s and %s because of non-equivalent assertions139*oasys2h TU0/\transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_cplllock/data_sync_reg1 2default:default2h TU0/\transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_cplllock/data_sync_reg1 2default:defaultZ8-139hpx  Ecannot merge instances %s and %s because of non-equivalent assertions139*oasys2h TU0/\transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_cplllock/data_sync_reg1 2default:default2h TU0/\transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_cplllock/data_sync_reg1 2default:defaultZ8-139hpx  Ecannot merge instances %s and %s because of non-equivalent assertions139*oasys2s _U0/\transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_mmcm_lock_reclocked/data_sync_reg1 2default:default2s _U0/\transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_mmcm_lock_reclocked/data_sync_reg1 2default:defaultZ8-139hpx  Ecannot merge instances %s and %s because of non-equivalent assertions139*oasys2s _U0/\transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_mmcm_lock_reclocked/data_sync_reg1 2default:default2s _U0/\transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_mmcm_lock_reclocked/data_sync_reg1 2default:defaultZ8-139hpx  Ecannot merge instances %s and %s because of non-equivalent assertions139*oasys2h TU0/\transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_cplllock/data_sync_reg1 2default:default2h TU0/\transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_cplllock/data_sync_reg1 2default:defaultZ8-139hpx  Ecannot merge instances %s and %s because of non-equivalent assertions139*oasys2h TU0/\transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_cplllock/data_sync_reg1 2default:default2h TU0/\transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_cplllock/data_sync_reg1 2default:defaultZ8-139hpx ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 |Finished Timing Optimization : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 975.965 ; gain = 604.168 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  E %s *synth2-  Report RTL Partitions: 2default:defaulthp x  W %s *synth2? ++-+--------------+------------+----------+ 2default:defaulthp x  W %s *synth2? +| |RTL Partition |Replication |Instances | 2default:defaulthp x  W %s *synth2? ++-+--------------+------------+----------+ 2default:defaulthp x  W %s *synth2? ++-+--------------+------------+----------+ 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  E %s *synth2- Start Technology Mapping 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   Ecannot merge instances %s and %s because of non-equivalent assertions139*oasys2s _U0/\transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_mmcm_lock_reclocked/data_sync_reg1 2default:default2s _U0/\transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_mmcm_lock_reclocked/data_sync_reg1 2default:defaultZ8-139hpx  Ecannot merge instances %s and %s because of non-equivalent assertions139*oasys2s _U0/\transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_mmcm_lock_reclocked/data_sync_reg1 2default:default2s _U0/\transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_mmcm_lock_reclocked/data_sync_reg1 2default:defaultZ8-139hpx  Ecannot merge instances %s and %s because of non-equivalent assertions139*oasys2h TU0/\transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_cplllock/data_sync_reg1 2default:default2h TU0/\transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_cplllock/data_sync_reg1 2default:defaultZ8-139hpx  Ecannot merge instances %s and %s because of non-equivalent assertions139*oasys2h TU0/\transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_cplllock/data_sync_reg1 2default:default2h TU0/\transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_cplllock/data_sync_reg1 2default:defaultZ8-139hpx  "merging instance '%s' (%s) to '%s'3436*oasys2| hU0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/CONFIG_K28p5_reg2default:default2 FDR2default:default2~ jU0/gig_ethernet_pcs_pma_16_1_core/gpcs_pma_inst/IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER/CONFIG_DATA_reg[3]2default:defaultZ8-3886hpx  Ecannot merge instances %s and %s because of non-equivalent assertions139*oasys2s _U0/\transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_mmcm_lock_reclocked/data_sync_reg1 2default:default2s _U0/\transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_mmcm_lock_reclocked/data_sync_reg1 2default:defaultZ8-139hpx  Ecannot merge instances %s and %s because of non-equivalent assertions139*oasys2s _U0/\transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_mmcm_lock_reclocked/data_sync_reg1 2default:default2s _U0/\transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_mmcm_lock_reclocked/data_sync_reg1 2default:defaultZ8-139hpx  Ecannot merge instances %s and %s because of non-equivalent assertions139*oasys2h TU0/\transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_cplllock/data_sync_reg1 2default:default2h TU0/\transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_cplllock/data_sync_reg1 2default:defaultZ8-139hpx  Ecannot merge instances %s and %s because of non-equivalent assertions139*oasys2h TU0/\transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_cplllock/data_sync_reg1 2default:default2h TU0/\transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_cplllock/data_sync_reg1 2default:defaultZ8-139hpx  Ecannot merge instances %s and %s because of non-equivalent assertions139*oasys2s _U0/\transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_mmcm_lock_reclocked/data_sync_reg1 2default:default2s _U0/\transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_mmcm_lock_reclocked/data_sync_reg1 2default:defaultZ8-139hpx  Ecannot merge instances %s and %s because of non-equivalent assertions139*oasys2s _U0/\transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_mmcm_lock_reclocked/data_sync_reg1 2default:default2s _U0/\transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_mmcm_lock_reclocked/data_sync_reg1 2default:defaultZ8-139hpx  Ecannot merge instances %s and %s because of non-equivalent assertions139*oasys2h TU0/\transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_cplllock/data_sync_reg1 2default:default2h TU0/\transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_cplllock/data_sync_reg1 2default:defaultZ8-139hpx  Ecannot merge instances %s and %s because of non-equivalent assertions139*oasys2h TU0/\transceiver_inst/gtwizard_inst/U0/gt0_txresetfsm_i/sync_cplllock/data_sync_reg1 2default:default2h TU0/\transceiver_inst/gtwizard_inst/U0/gt0_rxresetfsm_i/sync_cplllock/data_sync_reg1 2default:defaultZ8-139hpx ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 {Finished Technology Mapping : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 978.938 ; gain = 607.141 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  E %s *synth2-  Report RTL Partitions: 2default:defaulthp x  W %s *synth2? ++-+--------------+------------+----------+ 2default:defaulthp x  W %s *synth2? +| |RTL Partition |Replication |Instances | 2default:defaulthp x  W %s *synth2? ++-+--------------+------------+----------+ 2default:defaulthp x  W %s *synth2? ++-+--------------+------------+----------+ 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ? %s *synth2' Start IO Insertion 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  Q %s *synth29 %Start Flattening Before IO Insertion 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  T %s *synth2< (Finished Flattening Before IO Insertion 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  H %s *synth20 Start Final Netlist Cleanup 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  K %s *synth23 Finished Final Netlist Cleanup 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 uFinished IO Insertion : Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 978.938 ; gain = 607.141 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  D %s *synth2,  Report Check Netlist: 2default:defaulthp x  u %s *synth2] I+------+------------------+-------+---------+-------+------------------+ 2default:defaulthp x  u %s *synth2] I| |Item |Errors |Warnings |Status |Description | 2default:defaulthp x  u %s *synth2] I+------+------------------+-------+---------+-------+------------------+ 2default:defaulthp x  u %s *synth2] I|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | 2default:defaulthp x  u %s *synth2] I+------+------------------+-------+---------+-------+------------------+ 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  O %s *synth27 #Start Renaming Generated Instances 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 Finished Renaming Generated Instances : Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 978.938 ; gain = 607.141 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  E %s *synth2-  Report RTL Partitions: 2default:defaulthp x  W %s *synth2? ++-+--------------+------------+----------+ 2default:defaulthp x  W %s *synth2? +| |RTL Partition |Replication |Instances | 2default:defaulthp x  W %s *synth2? ++-+--------------+------------+----------+ 2default:defaulthp x  W %s *synth2? ++-+--------------+------------+----------+ 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  L %s *synth24 Start Rebuilding User Hierarchy 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 978.938 ; gain = 607.141 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  K %s *synth23 Start Renaming Generated Ports 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 Finished Renaming Generated Ports : Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 978.938 ; gain = 607.141 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  M %s *synth25 !Start Handling Custom Attributes 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 Finished Handling Custom Attributes : Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 978.938 ; gain = 607.141 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  J %s *synth22 Start Renaming Generated Nets 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 Finished Renaming Generated Nets : Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 978.938 ; gain = 607.141 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  K %s *synth23  Static Shift Register Report: 2default:defaulthp x   %s *synth2 +--------------------------------+--------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ 2default:defaulthp x   %s *synth2 |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | 2default:defaulthp x   %s *synth2 +--------------------------------+--------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ 2default:defaulthp x   %s *synth2 |gig_ethernet_pcs_pma_v16_1_5 | gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg[7] | 5 | 8 | NO | NO | NO | 8 | 0 | 2default:defaulthp x   %s *synth2 |gig_ethernet_pcs_pma_16_1_block | transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[127] | 128 | 1 | NO | NO | YES | 0 | 4 | 2default:defaulthp x   %s *synth2 |gig_ethernet_pcs_pma_16_1_block | transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[95] | 96 | 1 | NO | NO | YES | 0 | 3 | 2default:defaulthp x   %s *synth2 +--------------------------------+--------------------------------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ 2default:defaulthp x   %s *synth2 --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  K %s *synth23 Start Writing Synthesis Report 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  A %s *synth2)  Report BlackBoxes: 2default:defaulthp x  J %s *synth22 +-+--------------+----------+ 2default:defaulthp x  J %s *synth22 | |BlackBox name |Instances | 2default:defaulthp x  J %s *synth22 +-+--------------+----------+ 2default:defaulthp x  J %s *synth22 +-+--------------+----------+ 2default:defaulthp x  A %s *synth2)  Report Cell Usage: 2default:defaulthp x  K %s *synth23 +------+--------------+------+ 2default:defaulthp x  K %s *synth23 | |Cell |Count | 2default:defaulthp x  K %s *synth23 +------+--------------+------+ 2default:defaulthp x  K %s *synth23 |1 |CARRY4 | 40| 2default:defaulthp x  K %s *synth23 |2 |GTXE2_CHANNEL | 1| 2default:defaulthp x  K %s *synth23 |3 |LUT1 | 27| 2default:defaulthp x  K %s *synth23 |4 |LUT2 | 75| 2default:defaulthp x  K %s *synth23 |5 |LUT3 | 84| 2default:defaulthp x  K %s *synth23 |6 |LUT4 | 61| 2default:defaulthp x  K %s *synth23 |7 |LUT5 | 63| 2default:defaulthp x  K %s *synth23 |8 |LUT6 | 117| 2default:defaulthp x  K %s *synth23 |9 |SRL16 | 2| 2default:defaulthp x  K %s *synth23 |10 |SRL16E | 8| 2default:defaulthp x  K %s *synth23 |11 |SRLC32E | 7| 2default:defaulthp x  K %s *synth23 |12 |FD | 102| 2default:defaulthp x  K %s *synth23 |13 |FDCE | 16| 2default:defaulthp x  K %s *synth23 |14 |FDP | 36| 2default:defaulthp x  K %s *synth23 |15 |FDPE | 4| 2default:defaulthp x  K %s *synth23 |16 |FDRE | 537| 2default:defaulthp x  K %s *synth23 |17 |FDSE | 23| 2default:defaulthp x  K %s *synth23 +------+--------------+------+ 2default:defaulthp x  E %s *synth2-  Report Instance Areas: 2default:defaulthp x   %s *synth2 p+------+--------------------------------------------------+--------------------------------------------+------+ 2default:defaulthp x   %s *synth2 p| |Instance |Module |Cells | 2default:defaulthp x   %s *synth2 p+------+--------------------------------------------------+--------------------------------------------+------+ 2default:defaulthp x   %s *synth2 p|1 |top | | 1203| 2default:defaulthp x   %s *synth2 p|2 | U0 |gig_ethernet_pcs_pma_16_1_block | 1203| 2default:defaulthp x   %s *synth2 p|3 | gig_ethernet_pcs_pma_16_1_core |gig_ethernet_pcs_pma_v16_1_5 | 433| 2default:defaulthp x   %s *synth2 p|4 | gpcs_pma_inst |GPCS_PMA_GEN | 433| 2default:defaulthp x   %s *synth2 p|5 | \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER |TX | 127| 2default:defaulthp x   %s *synth2 p|6 | \MGT_RESET.SYNC_ASYNC_RESET |reset_sync_block | 7| 2default:defaulthp x   %s *synth2 p|7 | \MGT_RESET.SYNC_ASYNC_RESET_RECCLK |reset_sync_block_17 | 7| 2default:defaulthp x   %s *synth2 p|8 | \MGT_RESET.SYNC_SOFT_RESET_RECCLK |reset_sync_block_18 | 6| 2default:defaulthp x   %s *synth2 p|9 | \RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK |RX | 141| 2default:defaulthp x   %s *synth2 p|10 | \RX_GMII_AT_TXOUTCLK.SYNCHRONISATION |SYNCHRONISE | 47| 2default:defaulthp x   %s *synth2 p|11 | SYNC_SIGNAL_DETECT |sync_block | 7| 2default:defaulthp x   %s *synth2 p|12 | sync_block_rx_reset_done |gig_ethernet_pcs_pma_16_1_sync_block | 6| 2default:defaulthp x   %s *synth2 p|13 | sync_block_tx_reset_done |gig_ethernet_pcs_pma_16_1_sync_block_0 | 7| 2default:defaulthp x   %s *synth2 p|14 | transceiver_inst |gig_ethernet_pcs_pma_16_1_transceiver | 757| 2default:defaulthp x   %s *synth2 p|15 | gtwizard_inst |gig_ethernet_pcs_pma_16_1_GTWIZARD | 531| 2default:defaulthp x   %s *synth2 p|16 | U0 |gig_ethernet_pcs_pma_16_1_GTWIZARD_init | 531| 2default:defaulthp x   %s *synth2 p|17 | gt0_rxresetfsm_i |gig_ethernet_pcs_pma_16_1_RX_STARTUP_FSM | 232| 2default:defaulthp x   %s *synth2 p|18 | sync_RXRESETDONE |gig_ethernet_pcs_pma_16_1_sync_block_10 | 6| 2default:defaulthp x   %s *synth2 p|19 | sync_cplllock |gig_ethernet_pcs_pma_16_1_sync_block_11 | 7| 2default:defaulthp x   %s *synth2 p|20 | sync_data_valid |gig_ethernet_pcs_pma_16_1_sync_block_12 | 21| 2default:defaulthp x   %s *synth2 p|21 | sync_mmcm_lock_reclocked |gig_ethernet_pcs_pma_16_1_sync_block_13 | 8| 2default:defaulthp x   %s *synth2 p|22 | sync_run_phase_alignment_int |gig_ethernet_pcs_pma_16_1_sync_block_14 | 6| 2default:defaulthp x   %s *synth2 p|23 | sync_time_out_wait_bypass |gig_ethernet_pcs_pma_16_1_sync_block_15 | 6| 2default:defaulthp x   %s *synth2 p|24 | sync_tx_fsm_reset_done_int |gig_ethernet_pcs_pma_16_1_sync_block_16 | 6| 2default:defaulthp x   %s *synth2 p|25 | gt0_txresetfsm_i |gig_ethernet_pcs_pma_16_1_TX_STARTUP_FSM | 263| 2default:defaulthp x   %s *synth2 p|26 | sync_TXRESETDONE |gig_ethernet_pcs_pma_16_1_sync_block_4 | 6| 2default:defaulthp x   %s *synth2 p|27 | sync_cplllock |gig_ethernet_pcs_pma_16_1_sync_block_5 | 11| 2default:defaulthp x   %s *synth2 p|28 | sync_mmcm_lock_reclocked |gig_ethernet_pcs_pma_16_1_sync_block_6 | 8| 2default:defaulthp x   %s *synth2 p|29 | sync_run_phase_alignment_int |gig_ethernet_pcs_pma_16_1_sync_block_7 | 6| 2default:defaulthp x   %s *synth2 p|30 | sync_time_out_wait_bypass |gig_ethernet_pcs_pma_16_1_sync_block_8 | 6| 2default:defaulthp x   %s *synth2 p|31 | sync_tx_fsm_reset_done_int |gig_ethernet_pcs_pma_16_1_sync_block_9 | 6| 2default:defaulthp x   %s *synth2 p|32 | gtwizard_i |gig_ethernet_pcs_pma_16_1_GTWIZARD_multi_gt | 11| 2default:defaulthp x   %s *synth2 p|33 | cpll_railing0_i |gig_ethernet_pcs_pma_16_1_cpll_railing | 10| 2default:defaulthp x   %s *synth2 p|34 | gt0_GTWIZARD_i |gig_ethernet_pcs_pma_16_1_GTWIZARD_GT | 1| 2default:defaulthp x   %s *synth2 p|35 | reclock_encommaalign |gig_ethernet_pcs_pma_16_1_reset_sync | 6| 2default:defaulthp x   %s *synth2 p|36 | reclock_rxreset |gig_ethernet_pcs_pma_16_1_reset_sync_1 | 6| 2default:defaulthp x   %s *synth2 p|37 | reclock_txreset |gig_ethernet_pcs_pma_16_1_reset_sync_2 | 6| 2default:defaulthp x   %s *synth2 p|38 | reset_wtd_timer |gig_ethernet_pcs_pma_16_1_reset_wtd_timer | 57| 2default:defaulthp x   %s *synth2 p|39 | sync_block_data_valid |gig_ethernet_pcs_pma_16_1_sync_block_3 | 6| 2default:defaulthp x   %s *synth2 p+------+--------------------------------------------------+--------------------------------------------+------+ 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x   %s *synth2 Finished Writing Synthesis Report : Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 978.938 ; gain = 607.141 2default:defaulthp x  ~ %s *synth2f R--------------------------------------------------------------------------------- 2default:defaulthp x  t %s *synth2\ HSynthesis finished with 0 errors, 0 critical warnings and 367 warnings. 2default:defaulthp x   %s *synth2 ~Synthesis Optimization Runtime : Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 978.938 ; gain = 177.535 2default:defaulthp x   %s *synth2 Synthesis Optimization Complete : Time (s): cpu = 00:00:29 ; elapsed = 00:00:31 . Memory (MB): peak = 978.938 ; gain = 607.141 2default:defaulthp x  B Translating synthesized netlist 350*projectZ1-571hpx g -Analyzing %s Unisim elements for replacement 17*netlist2 1802default:defaultZ29-17hpx j 2Unisim Transformation completed in %s CPU seconds 28*netlist2 02default:defaultZ29-28hpx K )Preparing netlist for logic optimization 349*projectZ1-570hpx u )Pushed %s inverter(s) to %s load pin(s). 98*opt2 02default:default2 02default:defaultZ31-138hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2. Netlist sorting complete. 2default:default2 00:00:002default:default2 00:00:00.0012default:default2 992.0082default:default2 0.0002default:defaultZ17-268hp x   !Unisim Transformation Summary: %s111*project2  A total of 140 instances were transformed. FD => FDRE: 102 instances FDP => FDPE: 36 instances SRL16 => SRL16E: 2 instances 2default:defaultZ1-111hpx U Releasing license: %s 83*common2 Synthesis2default:defaultZ17-83hpx  G%s Infos, %s Warnings, %s Critical Warnings and %s Errors encountered. 28* vivadotcl2 2472default:default2 1302default:default2 02default:default2 02default:defaultZ4-41hpx ^ %s completed successfully 29* vivadotcl2 synth_design2default:defaultZ4-42hpx  I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2" synth_design: 2default:default2 00:00:322default:default2 00:00:352default:default2 992.0082default:default2 629.0432default:defaultZ17-268hp x   I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s  268*common2. Netlist sorting complete. 2default:default2 00:00:002default:default2 00:00:002default:default2 992.0082default:default2 0.0002default:defaultZ17-268hp x  K "No constraints selected for write.1103* constraintsZ18-5210hpx  The %s '%s' has been generated. 621*common2 checkpoint2default:default2 oD:/Design_collection/ngFECv0x43d/ngFEC_new.runs/gig_ethernet_pcs_pma_16_1_synth_1/gig_ethernet_pcs_pma_16_1.dcp2default:defaultZ17-1381hpx