-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -- Date : Sat Apr 18 12:30:30 2020 -- Host : baby running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ gig_ethernet_pcs_pma_16_1_sim_netlist.vhdl -- Design : gig_ethernet_pcs_pma_16_1 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7k420tffg1156-2 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_GTWIZARD_GT is port ( cplllock : out STD_LOGIC; gt0_cpllrefclklost_i : out STD_LOGIC; txn : out STD_LOGIC; txp : out STD_LOGIC; rxoutclk : out STD_LOGIC; independent_clock_bufg_0 : out STD_LOGIC; txoutclk : out STD_LOGIC; independent_clock_bufg_1 : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 1 downto 0 ); TXBUFSTATUS : out STD_LOGIC_VECTOR ( 0 to 0 ); RXBUFSTATUS : out STD_LOGIC_VECTOR ( 0 to 0 ); independent_clock_bufg_2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); independent_clock_bufg_3 : out STD_LOGIC_VECTOR ( 1 downto 0 ); independent_clock_bufg_4 : out STD_LOGIC_VECTOR ( 1 downto 0 ); independent_clock_bufg_5 : out STD_LOGIC_VECTOR ( 1 downto 0 ); independent_clock_bufg_6 : out STD_LOGIC_VECTOR ( 1 downto 0 ); independent_clock_bufg : in STD_LOGIC; cpll_pd0_i : in STD_LOGIC; cpllreset_in : in STD_LOGIC; gtrefclk_bufg : in STD_LOGIC; gtrefclk : in STD_LOGIC; gt0_gtrxreset_in1_out : in STD_LOGIC; gt0_gttxreset_in0_out : in STD_LOGIC; rxn : in STD_LOGIC; rxp : in STD_LOGIC; gt0_qplloutclk_in : in STD_LOGIC; gt0_qplloutrefclk_in : in STD_LOGIC; reset_out : in STD_LOGIC; reset : in STD_LOGIC; gt0_rxuserrdy_t : in STD_LOGIC; userclk : in STD_LOGIC; TXPD : in STD_LOGIC_VECTOR ( 0 to 0 ); gt0_txuserrdy_t : in STD_LOGIC; RXPD : in STD_LOGIC_VECTOR ( 0 to 0 ); Q : in STD_LOGIC_VECTOR ( 15 downto 0 ); data_sync_reg1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); data_sync_reg1_0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); data_sync_reg1_1 : in STD_LOGIC_VECTOR ( 1 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_GTWIZARD_GT; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_GTWIZARD_GT is signal gtxe2_i_n_0 : STD_LOGIC; signal gtxe2_i_n_10 : STD_LOGIC; signal gtxe2_i_n_16 : STD_LOGIC; signal gtxe2_i_n_170 : STD_LOGIC; signal gtxe2_i_n_171 : STD_LOGIC; signal gtxe2_i_n_172 : STD_LOGIC; signal gtxe2_i_n_173 : STD_LOGIC; signal gtxe2_i_n_174 : STD_LOGIC; signal gtxe2_i_n_175 : STD_LOGIC; signal gtxe2_i_n_176 : STD_LOGIC; signal gtxe2_i_n_177 : STD_LOGIC; signal gtxe2_i_n_178 : STD_LOGIC; signal gtxe2_i_n_179 : STD_LOGIC; signal gtxe2_i_n_180 : STD_LOGIC; signal gtxe2_i_n_181 : STD_LOGIC; signal gtxe2_i_n_182 : STD_LOGIC; signal gtxe2_i_n_183 : STD_LOGIC; signal gtxe2_i_n_184 : STD_LOGIC; signal gtxe2_i_n_27 : STD_LOGIC; signal gtxe2_i_n_3 : STD_LOGIC; signal gtxe2_i_n_38 : STD_LOGIC; signal gtxe2_i_n_39 : STD_LOGIC; signal gtxe2_i_n_4 : STD_LOGIC; signal gtxe2_i_n_46 : STD_LOGIC; signal gtxe2_i_n_47 : STD_LOGIC; signal gtxe2_i_n_48 : STD_LOGIC; signal gtxe2_i_n_49 : STD_LOGIC; signal gtxe2_i_n_50 : STD_LOGIC; signal gtxe2_i_n_51 : STD_LOGIC; signal gtxe2_i_n_52 : STD_LOGIC; signal gtxe2_i_n_53 : STD_LOGIC; signal gtxe2_i_n_54 : STD_LOGIC; signal gtxe2_i_n_55 : STD_LOGIC; signal gtxe2_i_n_56 : STD_LOGIC; signal gtxe2_i_n_57 : STD_LOGIC; signal gtxe2_i_n_58 : STD_LOGIC; signal gtxe2_i_n_59 : STD_LOGIC; signal gtxe2_i_n_60 : STD_LOGIC; signal gtxe2_i_n_61 : STD_LOGIC; signal gtxe2_i_n_81 : STD_LOGIC; signal gtxe2_i_n_83 : STD_LOGIC; signal gtxe2_i_n_84 : STD_LOGIC; signal gtxe2_i_n_9 : STD_LOGIC; signal NLW_gtxe2_i_GTREFCLKMONITOR_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_PHYSTATUS_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_RXCDRLOCK_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_RXCHANBONDSEQ_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_RXCHANISALIGNED_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_RXCHANREALIGN_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_RXCOMINITDET_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_RXCOMSASDET_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_RXCOMWAKEDET_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_RXDATAVALID_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_RXDLYSRESETDONE_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_RXELECIDLE_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_RXHEADERVALID_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_RXOUTCLKFABRIC_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_RXOUTCLKPCS_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_RXPHALIGNDONE_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_RXQPISENN_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_RXQPISENP_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_RXRATEDONE_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_RXSTARTOFSEQ_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_RXVALID_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_TXCOMFINISH_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_TXDLYSRESETDONE_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_TXGEARBOXREADY_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_TXPHALIGNDONE_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_TXPHINITDONE_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_TXQPISENN_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_TXQPISENP_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_TXRATEDONE_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_PCSRSVDOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); signal NLW_gtxe2_i_RXCHARISCOMMA_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 ); signal NLW_gtxe2_i_RXCHARISK_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 ); signal NLW_gtxe2_i_RXCHBONDO_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_gtxe2_i_RXDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 16 ); signal NLW_gtxe2_i_RXDISPERR_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 ); signal NLW_gtxe2_i_RXHEADER_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_gtxe2_i_RXNOTINTABLE_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 ); signal NLW_gtxe2_i_RXPHMONITOR_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_gtxe2_i_RXPHSLIPMONITOR_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_gtxe2_i_RXSTATUS_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_gtxe2_i_TSTOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 ); attribute box_type : string; attribute box_type of gtxe2_i : label is "PRIMITIVE"; begin gtxe2_i: unisim.vcomponents.GTXE2_CHANNEL generic map( ALIGN_COMMA_DOUBLE => "FALSE", ALIGN_COMMA_ENABLE => B"0001111111", ALIGN_COMMA_WORD => 2, ALIGN_MCOMMA_DET => "TRUE", ALIGN_MCOMMA_VALUE => B"1010000011", ALIGN_PCOMMA_DET => "TRUE", ALIGN_PCOMMA_VALUE => B"0101111100", CBCC_DATA_SOURCE_SEL => "DECODED", CHAN_BOND_KEEP_ALIGN => "FALSE", CHAN_BOND_MAX_SKEW => 1, CHAN_BOND_SEQ_1_1 => B"0000000000", CHAN_BOND_SEQ_1_2 => B"0000000000", CHAN_BOND_SEQ_1_3 => B"0000000000", CHAN_BOND_SEQ_1_4 => B"0000000000", CHAN_BOND_SEQ_1_ENABLE => B"1111", CHAN_BOND_SEQ_2_1 => B"0000000000", CHAN_BOND_SEQ_2_2 => B"0000000000", CHAN_BOND_SEQ_2_3 => B"0000000000", CHAN_BOND_SEQ_2_4 => B"0000000000", CHAN_BOND_SEQ_2_ENABLE => B"1111", CHAN_BOND_SEQ_2_USE => "FALSE", CHAN_BOND_SEQ_LEN => 1, CLK_CORRECT_USE => "TRUE", CLK_COR_KEEP_IDLE => "FALSE", CLK_COR_MAX_LAT => 36, CLK_COR_MIN_LAT => 33, CLK_COR_PRECEDENCE => "TRUE", CLK_COR_REPEAT_WAIT => 0, CLK_COR_SEQ_1_1 => B"0110111100", CLK_COR_SEQ_1_2 => B"0001010000", CLK_COR_SEQ_1_3 => B"0000000000", CLK_COR_SEQ_1_4 => B"0000000000", CLK_COR_SEQ_1_ENABLE => B"1111", CLK_COR_SEQ_2_1 => B"0110111100", CLK_COR_SEQ_2_2 => B"0010110101", CLK_COR_SEQ_2_3 => B"0000000000", CLK_COR_SEQ_2_4 => B"0000000000", CLK_COR_SEQ_2_ENABLE => B"1111", CLK_COR_SEQ_2_USE => "TRUE", CLK_COR_SEQ_LEN => 2, CPLL_CFG => X"BC07DC", CPLL_FBDIV => 4, CPLL_FBDIV_45 => 5, CPLL_INIT_CFG => X"00001E", CPLL_LOCK_CFG => X"01E8", CPLL_REFCLK_DIV => 1, DEC_MCOMMA_DETECT => "TRUE", DEC_PCOMMA_DETECT => "TRUE", DEC_VALID_COMMA_ONLY => "FALSE", DMONITOR_CFG => X"000A00", ES_CONTROL => B"000000", ES_ERRDET_EN => "FALSE", ES_EYE_SCAN_EN => "TRUE", ES_HORZ_OFFSET => X"000", ES_PMA_CFG => B"0000000000", ES_PRESCALE => B"00000", ES_QUALIFIER => X"00000000000000000000", ES_QUAL_MASK => X"00000000000000000000", ES_SDATA_MASK => X"00000000000000000000", ES_VERT_OFFSET => B"000000000", FTS_DESKEW_SEQ_ENABLE => B"1111", FTS_LANE_DESKEW_CFG => B"1111", FTS_LANE_DESKEW_EN => "FALSE", GEARBOX_MODE => B"000", IS_CPLLLOCKDETCLK_INVERTED => '0', IS_DRPCLK_INVERTED => '0', IS_GTGREFCLK_INVERTED => '0', IS_RXUSRCLK2_INVERTED => '0', IS_RXUSRCLK_INVERTED => '0', IS_TXPHDLYTSTCLK_INVERTED => '0', IS_TXUSRCLK2_INVERTED => '0', IS_TXUSRCLK_INVERTED => '0', OUTREFCLK_SEL_INV => B"11", PCS_PCIE_EN => "FALSE", PCS_RSVD_ATTR => X"000000000000", PD_TRANS_TIME_FROM_P2 => X"03C", PD_TRANS_TIME_NONE_P2 => X"19", PD_TRANS_TIME_TO_P2 => X"64", PMA_RSV => X"00018480", PMA_RSV2 => X"2050", PMA_RSV3 => B"00", PMA_RSV4 => X"00000000", RXBUFRESET_TIME => B"00001", RXBUF_ADDR_MODE => "FULL", RXBUF_EIDLE_HI_CNT => B"1000", RXBUF_EIDLE_LO_CNT => B"0000", RXBUF_EN => "TRUE", RXBUF_RESET_ON_CB_CHANGE => "TRUE", RXBUF_RESET_ON_COMMAALIGN => "FALSE", RXBUF_RESET_ON_EIDLE => "FALSE", RXBUF_RESET_ON_RATE_CHANGE => "TRUE", RXBUF_THRESH_OVFLW => 61, RXBUF_THRESH_OVRD => "FALSE", RXBUF_THRESH_UNDFLW => 8, RXCDRFREQRESET_TIME => B"00001", RXCDRPHRESET_TIME => B"00001", RXCDR_CFG => X"03000023FF10100020", RXCDR_FR_RESET_ON_EIDLE => '0', RXCDR_HOLD_DURING_EIDLE => '0', RXCDR_LOCK_CFG => B"010101", RXCDR_PH_RESET_ON_EIDLE => '0', RXDFELPMRESET_TIME => B"0001111", RXDLY_CFG => X"001F", RXDLY_LCFG => X"030", RXDLY_TAP_CFG => X"0000", RXGEARBOX_EN => "FALSE", RXISCANRESET_TIME => B"00001", RXLPM_HF_CFG => B"00000011110000", RXLPM_LF_CFG => B"00000011110000", RXOOB_CFG => B"0000110", RXOUT_DIV => 4, RXPCSRESET_TIME => B"00001", RXPHDLY_CFG => X"084020", RXPH_CFG => X"000000", RXPH_MONITOR_SEL => B"00000", RXPMARESET_TIME => B"00011", RXPRBS_ERR_LOOPBACK => '0', RXSLIDE_AUTO_WAIT => 7, RXSLIDE_MODE => "OFF", RX_BIAS_CFG => B"000000000100", RX_BUFFER_CFG => B"000000", RX_CLK25_DIV => 5, RX_CLKMUX_PD => '1', RX_CM_SEL => B"11", RX_CM_TRIM => B"010", RX_DATA_WIDTH => 20, RX_DDI_SEL => B"000000", RX_DEBUG_CFG => B"000000000000", RX_DEFER_RESET_BUF_EN => "TRUE", RX_DFE_GAIN_CFG => X"020FEA", RX_DFE_H2_CFG => B"000000000000", RX_DFE_H3_CFG => B"000001000000", RX_DFE_H4_CFG => B"00011110000", RX_DFE_H5_CFG => B"00011100000", RX_DFE_KL_CFG => B"0000011111110", RX_DFE_KL_CFG2 => X"301148AC", RX_DFE_LPM_CFG => X"0904", RX_DFE_LPM_HOLD_DURING_EIDLE => '0', RX_DFE_UT_CFG => B"10001111000000000", RX_DFE_VP_CFG => B"00011111100000011", RX_DFE_XYD_CFG => B"0000000000000", RX_DISPERR_SEQ_MATCH => "TRUE", RX_INT_DATAWIDTH => 0, RX_OS_CFG => B"0000010000000", RX_SIG_VALID_DLY => 10, RX_XCLK_SEL => "RXREC", SAS_MAX_COM => 64, SAS_MIN_COM => 36, SATA_BURST_SEQ_LEN => B"0101", SATA_BURST_VAL => B"100", SATA_CPLL_CFG => "VCO_3000MHZ", SATA_EIDLE_VAL => B"100", SATA_MAX_BURST => 8, SATA_MAX_INIT => 21, SATA_MAX_WAKE => 7, SATA_MIN_BURST => 4, SATA_MIN_INIT => 12, SATA_MIN_WAKE => 4, SHOW_REALIGN_COMMA => "TRUE", SIM_CPLLREFCLK_SEL => B"001", SIM_RECEIVER_DETECT_PASS => "TRUE", SIM_RESET_SPEEDUP => "TRUE", SIM_TX_EIDLE_DRIVE_LEVEL => "X", SIM_VERSION => "4.0", TERM_RCAL_CFG => B"10000", TERM_RCAL_OVRD => '0', TRANS_TIME_RATE => X"0E", TST_RSV => X"00000000", TXBUF_EN => "TRUE", TXBUF_RESET_ON_RATE_CHANGE => "TRUE", TXDLY_CFG => X"001F", TXDLY_LCFG => X"030", TXDLY_TAP_CFG => X"0000", TXGEARBOX_EN => "FALSE", TXOUT_DIV => 4, TXPCSRESET_TIME => B"00001", TXPHDLY_CFG => X"084020", TXPH_CFG => X"0780", TXPH_MONITOR_SEL => B"00000", TXPMARESET_TIME => B"00001", TX_CLK25_DIV => 5, TX_CLKMUX_PD => '1', TX_DATA_WIDTH => 20, TX_DEEMPH0 => B"00000", TX_DEEMPH1 => B"00000", TX_DRIVE_MODE => "DIRECT", TX_EIDLE_ASSERT_DELAY => B"110", TX_EIDLE_DEASSERT_DELAY => B"100", TX_INT_DATAWIDTH => 0, TX_LOOPBACK_DRIVE_HIZ => "FALSE", TX_MAINCURSOR_SEL => '0', TX_MARGIN_FULL_0 => B"1001110", TX_MARGIN_FULL_1 => B"1001001", TX_MARGIN_FULL_2 => B"1000101", TX_MARGIN_FULL_3 => B"1000010", TX_MARGIN_FULL_4 => B"1000000", TX_MARGIN_LOW_0 => B"1000110", TX_MARGIN_LOW_1 => B"1000100", TX_MARGIN_LOW_2 => B"1000010", TX_MARGIN_LOW_3 => B"1000000", TX_MARGIN_LOW_4 => B"1000000", TX_PREDRIVER_MODE => '0', TX_QPI_STATUS_EN => '0', TX_RXDETECT_CFG => X"1832", TX_RXDETECT_REF => B"100", TX_XCLK_SEL => "TXOUT", UCODEER_CLR => '0' ) port map ( CFGRESET => '0', CLKRSVD(3 downto 0) => B"0000", CPLLFBCLKLOST => gtxe2_i_n_0, CPLLLOCK => cplllock, CPLLLOCKDETCLK => independent_clock_bufg, CPLLLOCKEN => '1', CPLLPD => cpll_pd0_i, CPLLREFCLKLOST => gt0_cpllrefclklost_i, CPLLREFCLKSEL(2 downto 0) => B"001", CPLLRESET => cpllreset_in, DMONITOROUT(7) => gtxe2_i_n_177, DMONITOROUT(6) => gtxe2_i_n_178, DMONITOROUT(5) => gtxe2_i_n_179, DMONITOROUT(4) => gtxe2_i_n_180, DMONITOROUT(3) => gtxe2_i_n_181, DMONITOROUT(2) => gtxe2_i_n_182, DMONITOROUT(1) => gtxe2_i_n_183, DMONITOROUT(0) => gtxe2_i_n_184, DRPADDR(8 downto 0) => B"000000000", DRPCLK => gtrefclk_bufg, DRPDI(15 downto 0) => B"0000000000000000", DRPDO(15) => gtxe2_i_n_46, DRPDO(14) => gtxe2_i_n_47, DRPDO(13) => gtxe2_i_n_48, DRPDO(12) => gtxe2_i_n_49, DRPDO(11) => gtxe2_i_n_50, DRPDO(10) => gtxe2_i_n_51, DRPDO(9) => gtxe2_i_n_52, DRPDO(8) => gtxe2_i_n_53, DRPDO(7) => gtxe2_i_n_54, DRPDO(6) => gtxe2_i_n_55, DRPDO(5) => gtxe2_i_n_56, DRPDO(4) => gtxe2_i_n_57, DRPDO(3) => gtxe2_i_n_58, DRPDO(2) => gtxe2_i_n_59, DRPDO(1) => gtxe2_i_n_60, DRPDO(0) => gtxe2_i_n_61, DRPEN => '0', DRPRDY => gtxe2_i_n_3, DRPWE => '0', EYESCANDATAERROR => gtxe2_i_n_4, EYESCANMODE => '0', EYESCANRESET => '0', EYESCANTRIGGER => '0', GTGREFCLK => '0', GTNORTHREFCLK0 => '0', GTNORTHREFCLK1 => '0', GTREFCLK0 => gtrefclk, GTREFCLK1 => '0', GTREFCLKMONITOR => NLW_gtxe2_i_GTREFCLKMONITOR_UNCONNECTED, GTRESETSEL => '0', GTRSVD(15 downto 0) => B"0000000000000000", GTRXRESET => gt0_gtrxreset_in1_out, GTSOUTHREFCLK0 => '0', GTSOUTHREFCLK1 => '0', GTTXRESET => gt0_gttxreset_in0_out, GTXRXN => rxn, GTXRXP => rxp, GTXTXN => txn, GTXTXP => txp, LOOPBACK(2 downto 0) => B"000", PCSRSVDIN(15 downto 0) => B"0000000000000000", PCSRSVDIN2(4 downto 0) => B"00000", PCSRSVDOUT(15 downto 0) => NLW_gtxe2_i_PCSRSVDOUT_UNCONNECTED(15 downto 0), PHYSTATUS => NLW_gtxe2_i_PHYSTATUS_UNCONNECTED, PMARSVDIN(4 downto 0) => B"00000", PMARSVDIN2(4 downto 0) => B"00000", QPLLCLK => gt0_qplloutclk_in, QPLLREFCLK => gt0_qplloutrefclk_in, RESETOVRD => '0', RX8B10BEN => '1', RXBUFRESET => '0', RXBUFSTATUS(2) => RXBUFSTATUS(0), RXBUFSTATUS(1) => gtxe2_i_n_83, RXBUFSTATUS(0) => gtxe2_i_n_84, RXBYTEISALIGNED => gtxe2_i_n_9, RXBYTEREALIGN => gtxe2_i_n_10, RXCDRFREQRESET => '0', RXCDRHOLD => '0', RXCDRLOCK => NLW_gtxe2_i_RXCDRLOCK_UNCONNECTED, RXCDROVRDEN => '0', RXCDRRESET => '0', RXCDRRESETRSV => '0', RXCHANBONDSEQ => NLW_gtxe2_i_RXCHANBONDSEQ_UNCONNECTED, RXCHANISALIGNED => NLW_gtxe2_i_RXCHANISALIGNED_UNCONNECTED, RXCHANREALIGN => NLW_gtxe2_i_RXCHANREALIGN_UNCONNECTED, RXCHARISCOMMA(7 downto 2) => NLW_gtxe2_i_RXCHARISCOMMA_UNCONNECTED(7 downto 2), RXCHARISCOMMA(1 downto 0) => independent_clock_bufg_3(1 downto 0), RXCHARISK(7 downto 2) => NLW_gtxe2_i_RXCHARISK_UNCONNECTED(7 downto 2), RXCHARISK(1 downto 0) => independent_clock_bufg_4(1 downto 0), RXCHBONDEN => '0', RXCHBONDI(4 downto 0) => B"00000", RXCHBONDLEVEL(2 downto 0) => B"000", RXCHBONDMASTER => '0', RXCHBONDO(4 downto 0) => NLW_gtxe2_i_RXCHBONDO_UNCONNECTED(4 downto 0), RXCHBONDSLAVE => '0', RXCLKCORCNT(1 downto 0) => D(1 downto 0), RXCOMINITDET => NLW_gtxe2_i_RXCOMINITDET_UNCONNECTED, RXCOMMADET => gtxe2_i_n_16, RXCOMMADETEN => '1', RXCOMSASDET => NLW_gtxe2_i_RXCOMSASDET_UNCONNECTED, RXCOMWAKEDET => NLW_gtxe2_i_RXCOMWAKEDET_UNCONNECTED, RXDATA(63 downto 16) => NLW_gtxe2_i_RXDATA_UNCONNECTED(63 downto 16), RXDATA(15 downto 0) => independent_clock_bufg_2(15 downto 0), RXDATAVALID => NLW_gtxe2_i_RXDATAVALID_UNCONNECTED, RXDDIEN => '0', RXDFEAGCHOLD => '0', RXDFEAGCOVRDEN => '0', RXDFECM1EN => '0', RXDFELFHOLD => '0', RXDFELFOVRDEN => '0', RXDFELPMRESET => '0', RXDFETAP2HOLD => '0', RXDFETAP2OVRDEN => '0', RXDFETAP3HOLD => '0', RXDFETAP3OVRDEN => '0', RXDFETAP4HOLD => '0', RXDFETAP4OVRDEN => '0', RXDFETAP5HOLD => '0', RXDFETAP5OVRDEN => '0', RXDFEUTHOLD => '0', RXDFEUTOVRDEN => '0', RXDFEVPHOLD => '0', RXDFEVPOVRDEN => '0', RXDFEVSEN => '0', RXDFEXYDEN => '1', RXDFEXYDHOLD => '0', RXDFEXYDOVRDEN => '0', RXDISPERR(7 downto 2) => NLW_gtxe2_i_RXDISPERR_UNCONNECTED(7 downto 2), RXDISPERR(1 downto 0) => independent_clock_bufg_5(1 downto 0), RXDLYBYPASS => '1', RXDLYEN => '0', RXDLYOVRDEN => '0', RXDLYSRESET => '0', RXDLYSRESETDONE => NLW_gtxe2_i_RXDLYSRESETDONE_UNCONNECTED, RXELECIDLE => NLW_gtxe2_i_RXELECIDLE_UNCONNECTED, RXELECIDLEMODE(1 downto 0) => B"11", RXGEARBOXSLIP => '0', RXHEADER(2 downto 0) => NLW_gtxe2_i_RXHEADER_UNCONNECTED(2 downto 0), RXHEADERVALID => NLW_gtxe2_i_RXHEADERVALID_UNCONNECTED, RXLPMEN => '1', RXLPMHFHOLD => '0', RXLPMHFOVRDEN => '0', RXLPMLFHOLD => '0', RXLPMLFKLOVRDEN => '0', RXMCOMMAALIGNEN => reset_out, RXMONITOROUT(6) => gtxe2_i_n_170, RXMONITOROUT(5) => gtxe2_i_n_171, RXMONITOROUT(4) => gtxe2_i_n_172, RXMONITOROUT(3) => gtxe2_i_n_173, RXMONITOROUT(2) => gtxe2_i_n_174, RXMONITOROUT(1) => gtxe2_i_n_175, RXMONITOROUT(0) => gtxe2_i_n_176, RXMONITORSEL(1 downto 0) => B"00", RXNOTINTABLE(7 downto 2) => NLW_gtxe2_i_RXNOTINTABLE_UNCONNECTED(7 downto 2), RXNOTINTABLE(1 downto 0) => independent_clock_bufg_6(1 downto 0), RXOOBRESET => '0', RXOSHOLD => '0', RXOSOVRDEN => '0', RXOUTCLK => rxoutclk, RXOUTCLKFABRIC => NLW_gtxe2_i_RXOUTCLKFABRIC_UNCONNECTED, RXOUTCLKPCS => NLW_gtxe2_i_RXOUTCLKPCS_UNCONNECTED, RXOUTCLKSEL(2 downto 0) => B"010", RXPCOMMAALIGNEN => reset_out, RXPCSRESET => reset, RXPD(1) => RXPD(0), RXPD(0) => RXPD(0), RXPHALIGN => '0', RXPHALIGNDONE => NLW_gtxe2_i_RXPHALIGNDONE_UNCONNECTED, RXPHALIGNEN => '0', RXPHDLYPD => '0', RXPHDLYRESET => '0', RXPHMONITOR(4 downto 0) => NLW_gtxe2_i_RXPHMONITOR_UNCONNECTED(4 downto 0), RXPHOVRDEN => '0', RXPHSLIPMONITOR(4 downto 0) => NLW_gtxe2_i_RXPHSLIPMONITOR_UNCONNECTED(4 downto 0), RXPMARESET => '0', RXPOLARITY => '0', RXPRBSCNTRESET => '0', RXPRBSERR => gtxe2_i_n_27, RXPRBSSEL(2 downto 0) => B"000", RXQPIEN => '0', RXQPISENN => NLW_gtxe2_i_RXQPISENN_UNCONNECTED, RXQPISENP => NLW_gtxe2_i_RXQPISENP_UNCONNECTED, RXRATE(2 downto 0) => B"000", RXRATEDONE => NLW_gtxe2_i_RXRATEDONE_UNCONNECTED, RXRESETDONE => independent_clock_bufg_0, RXSLIDE => '0', RXSTARTOFSEQ => NLW_gtxe2_i_RXSTARTOFSEQ_UNCONNECTED, RXSTATUS(2 downto 0) => NLW_gtxe2_i_RXSTATUS_UNCONNECTED(2 downto 0), RXSYSCLKSEL(1 downto 0) => B"00", RXUSERRDY => gt0_rxuserrdy_t, RXUSRCLK => userclk, RXUSRCLK2 => userclk, RXVALID => NLW_gtxe2_i_RXVALID_UNCONNECTED, SETERRSTATUS => '0', TSTIN(19 downto 0) => B"11111111111111111111", TSTOUT(9 downto 0) => NLW_gtxe2_i_TSTOUT_UNCONNECTED(9 downto 0), TX8B10BBYPASS(7 downto 0) => B"00000000", TX8B10BEN => '1', TXBUFDIFFCTRL(2 downto 0) => B"100", TXBUFSTATUS(1) => TXBUFSTATUS(0), TXBUFSTATUS(0) => gtxe2_i_n_81, TXCHARDISPMODE(7 downto 2) => B"000000", TXCHARDISPMODE(1 downto 0) => data_sync_reg1(1 downto 0), TXCHARDISPVAL(7 downto 2) => B"000000", TXCHARDISPVAL(1 downto 0) => data_sync_reg1_0(1 downto 0), TXCHARISK(7 downto 2) => B"000000", TXCHARISK(1 downto 0) => data_sync_reg1_1(1 downto 0), TXCOMFINISH => NLW_gtxe2_i_TXCOMFINISH_UNCONNECTED, TXCOMINIT => '0', TXCOMSAS => '0', TXCOMWAKE => '0', TXDATA(63 downto 16) => B"000000000000000000000000000000000000000000000000", TXDATA(15 downto 0) => Q(15 downto 0), TXDEEMPH => '0', TXDETECTRX => '0', TXDIFFCTRL(3 downto 0) => B"1000", TXDIFFPD => '0', TXDLYBYPASS => '1', TXDLYEN => '0', TXDLYHOLD => '0', TXDLYOVRDEN => '0', TXDLYSRESET => '0', TXDLYSRESETDONE => NLW_gtxe2_i_TXDLYSRESETDONE_UNCONNECTED, TXDLYUPDOWN => '0', TXELECIDLE => TXPD(0), TXGEARBOXREADY => NLW_gtxe2_i_TXGEARBOXREADY_UNCONNECTED, TXHEADER(2 downto 0) => B"000", TXINHIBIT => '0', TXMAINCURSOR(6 downto 0) => B"0000000", TXMARGIN(2 downto 0) => B"000", TXOUTCLK => txoutclk, TXOUTCLKFABRIC => gtxe2_i_n_38, TXOUTCLKPCS => gtxe2_i_n_39, TXOUTCLKSEL(2 downto 0) => B"100", TXPCSRESET => '0', TXPD(1) => TXPD(0), TXPD(0) => TXPD(0), TXPDELECIDLEMODE => '0', TXPHALIGN => '0', TXPHALIGNDONE => NLW_gtxe2_i_TXPHALIGNDONE_UNCONNECTED, TXPHALIGNEN => '0', TXPHDLYPD => '0', TXPHDLYRESET => '0', TXPHDLYTSTCLK => '0', TXPHINIT => '0', TXPHINITDONE => NLW_gtxe2_i_TXPHINITDONE_UNCONNECTED, TXPHOVRDEN => '0', TXPISOPD => '0', TXPMARESET => '0', TXPOLARITY => '0', TXPOSTCURSOR(4 downto 0) => B"00000", TXPOSTCURSORINV => '0', TXPRBSFORCEERR => '0', TXPRBSSEL(2 downto 0) => B"000", TXPRECURSOR(4 downto 0) => B"00000", TXPRECURSORINV => '0', TXQPIBIASEN => '0', TXQPISENN => NLW_gtxe2_i_TXQPISENN_UNCONNECTED, TXQPISENP => NLW_gtxe2_i_TXQPISENP_UNCONNECTED, TXQPISTRONGPDOWN => '0', TXQPIWEAKPUP => '0', TXRATE(2 downto 0) => B"000", TXRATEDONE => NLW_gtxe2_i_TXRATEDONE_UNCONNECTED, TXRESETDONE => independent_clock_bufg_1, TXSEQUENCE(6 downto 0) => B"0000000", TXSTARTSEQ => '0', TXSWING => '0', TXSYSCLKSEL(1 downto 0) => B"00", TXUSERRDY => gt0_txuserrdy_t, TXUSRCLK => userclk, TXUSRCLK2 => userclk ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_cpll_railing is port ( cpll_pd0_i : out STD_LOGIC; cpllreset_in : out STD_LOGIC; gtrefclk_bufg : in STD_LOGIC; gt0_cpllreset_t : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_cpll_railing; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_cpll_railing is signal cpll_reset_out : STD_LOGIC; signal \cpllpd_wait_reg[31]_srl32_n_1\ : STD_LOGIC; signal \cpllpd_wait_reg[63]_srl32_n_1\ : STD_LOGIC; signal \cpllpd_wait_reg[94]_srl31_n_0\ : STD_LOGIC; signal \cpllreset_wait_reg[126]_srl31_n_0\ : STD_LOGIC; signal \cpllreset_wait_reg[31]_srl32_n_1\ : STD_LOGIC; signal \cpllreset_wait_reg[63]_srl32_n_1\ : STD_LOGIC; signal \cpllreset_wait_reg[95]_srl32_n_1\ : STD_LOGIC; signal \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC; signal \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC; signal \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC; signal \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC; signal \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\ : STD_LOGIC; attribute srl_bus_name : string; attribute srl_bus_name of \cpllpd_wait_reg[31]_srl32\ : label is "U0/\transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg "; attribute srl_name : string; attribute srl_name of \cpllpd_wait_reg[31]_srl32\ : label is "U0/\transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32 "; attribute srl_bus_name of \cpllpd_wait_reg[63]_srl32\ : label is "U0/\transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg "; attribute srl_name of \cpllpd_wait_reg[63]_srl32\ : label is "U0/\transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32 "; attribute srl_bus_name of \cpllpd_wait_reg[94]_srl31\ : label is "U0/\transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg "; attribute srl_name of \cpllpd_wait_reg[94]_srl31\ : label is "U0/\transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31 "; attribute equivalent_register_removal : string; attribute equivalent_register_removal of \cpllpd_wait_reg[95]\ : label is "no"; attribute srl_bus_name of \cpllreset_wait_reg[126]_srl31\ : label is "U0/\transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg "; attribute srl_name of \cpllreset_wait_reg[126]_srl31\ : label is "U0/\transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31 "; attribute equivalent_register_removal of \cpllreset_wait_reg[127]\ : label is "no"; attribute srl_bus_name of \cpllreset_wait_reg[31]_srl32\ : label is "U0/\transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg "; attribute srl_name of \cpllreset_wait_reg[31]_srl32\ : label is "U0/\transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[31]_srl32 "; attribute srl_bus_name of \cpllreset_wait_reg[63]_srl32\ : label is "U0/\transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg "; attribute srl_name of \cpllreset_wait_reg[63]_srl32\ : label is "U0/\transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32 "; attribute srl_bus_name of \cpllreset_wait_reg[95]_srl32\ : label is "U0/\transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg "; attribute srl_name of \cpllreset_wait_reg[95]_srl32\ : label is "U0/\transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32 "; begin \cpllpd_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"FFFFFFFF" ) port map ( A(4 downto 0) => B"11111", CE => '1', CLK => gtrefclk_bufg, D => '0', Q => \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\, Q31 => \cpllpd_wait_reg[31]_srl32_n_1\ ); \cpllpd_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"FFFFFFFF" ) port map ( A(4 downto 0) => B"11111", CE => '1', CLK => gtrefclk_bufg, D => \cpllpd_wait_reg[31]_srl32_n_1\, Q => \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\, Q31 => \cpllpd_wait_reg[63]_srl32_n_1\ ); \cpllpd_wait_reg[94]_srl31\: unisim.vcomponents.SRLC32E generic map( INIT => X"7FFFFFFF" ) port map ( A(4 downto 0) => B"11110", CE => '1', CLK => gtrefclk_bufg, D => \cpllpd_wait_reg[63]_srl32_n_1\, Q => \cpllpd_wait_reg[94]_srl31_n_0\, Q31 => \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\ ); \cpllpd_wait_reg[95]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => gtrefclk_bufg, CE => '1', D => \cpllpd_wait_reg[94]_srl31_n_0\, Q => cpll_pd0_i, R => '0' ); \cpllreset_wait_reg[126]_srl31\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => B"11110", CE => '1', CLK => gtrefclk_bufg, D => \cpllreset_wait_reg[95]_srl32_n_1\, Q => \cpllreset_wait_reg[126]_srl31_n_0\, Q31 => \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\ ); \cpllreset_wait_reg[127]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => gtrefclk_bufg, CE => '1', D => \cpllreset_wait_reg[126]_srl31_n_0\, Q => cpll_reset_out, R => '0' ); \cpllreset_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"000000FF" ) port map ( A(4 downto 0) => B"11111", CE => '1', CLK => gtrefclk_bufg, D => '0', Q => \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\, Q31 => \cpllreset_wait_reg[31]_srl32_n_1\ ); \cpllreset_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => B"11111", CE => '1', CLK => gtrefclk_bufg, D => \cpllreset_wait_reg[31]_srl32_n_1\, Q => \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\, Q31 => \cpllreset_wait_reg[63]_srl32_n_1\ ); \cpllreset_wait_reg[95]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => B"11111", CE => '1', CLK => gtrefclk_bufg, D => \cpllreset_wait_reg[63]_srl32_n_1\, Q => \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\, Q31 => \cpllreset_wait_reg[95]_srl32_n_1\ ); gtxe2_i_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => cpll_reset_out, I1 => gt0_cpllreset_t, O => cpllreset_in ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_reset_sync is port ( reset_out : out STD_LOGIC; userclk : in STD_LOGIC; enablealign : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_reset_sync; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_reset_sync is signal reset_sync_reg1 : STD_LOGIC; signal reset_sync_reg2 : STD_LOGIC; signal reset_sync_reg3 : STD_LOGIC; signal reset_sync_reg4 : STD_LOGIC; signal reset_sync_reg5 : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of reset_sync1 : label is std.standard.true; attribute SHREG_EXTRACT : string; attribute SHREG_EXTRACT of reset_sync1 : label is "no"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of reset_sync1 : label is "FDP"; attribute box_type : string; attribute box_type of reset_sync1 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync2 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync2 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync2 : label is "FDP"; attribute box_type of reset_sync2 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync3 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync3 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync3 : label is "FDP"; attribute box_type of reset_sync3 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync4 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync4 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync4 : label is "FDP"; attribute box_type of reset_sync4 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync5 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync5 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync5 : label is "FDP"; attribute box_type of reset_sync5 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync6 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync6 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync6 : label is "FDP"; attribute box_type of reset_sync6 : label is "PRIMITIVE"; begin reset_sync1: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => userclk, CE => '1', D => '0', PRE => enablealign, Q => reset_sync_reg1 ); reset_sync2: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => userclk, CE => '1', D => reset_sync_reg1, PRE => enablealign, Q => reset_sync_reg2 ); reset_sync3: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => userclk, CE => '1', D => reset_sync_reg2, PRE => enablealign, Q => reset_sync_reg3 ); reset_sync4: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => userclk, CE => '1', D => reset_sync_reg3, PRE => enablealign, Q => reset_sync_reg4 ); reset_sync5: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => userclk, CE => '1', D => reset_sync_reg4, PRE => enablealign, Q => reset_sync_reg5 ); reset_sync6: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => userclk, CE => '1', D => reset_sync_reg5, PRE => '0', Q => reset_out ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_reset_sync_1 is port ( reset_out : out STD_LOGIC; independent_clock_bufg : in STD_LOGIC; reset_sync5_0 : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_reset_sync_1 : entity is "gig_ethernet_pcs_pma_16_1_reset_sync"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_reset_sync_1; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_reset_sync_1 is signal reset_sync_reg1 : STD_LOGIC; signal reset_sync_reg2 : STD_LOGIC; signal reset_sync_reg3 : STD_LOGIC; signal reset_sync_reg4 : STD_LOGIC; signal reset_sync_reg5 : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of reset_sync1 : label is std.standard.true; attribute SHREG_EXTRACT : string; attribute SHREG_EXTRACT of reset_sync1 : label is "no"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of reset_sync1 : label is "FDP"; attribute box_type : string; attribute box_type of reset_sync1 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync2 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync2 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync2 : label is "FDP"; attribute box_type of reset_sync2 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync3 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync3 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync3 : label is "FDP"; attribute box_type of reset_sync3 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync4 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync4 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync4 : label is "FDP"; attribute box_type of reset_sync4 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync5 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync5 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync5 : label is "FDP"; attribute box_type of reset_sync5 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync6 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync6 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync6 : label is "FDP"; attribute box_type of reset_sync6 : label is "PRIMITIVE"; begin reset_sync1: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => independent_clock_bufg, CE => '1', D => '0', PRE => reset_sync5_0(0), Q => reset_sync_reg1 ); reset_sync2: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => independent_clock_bufg, CE => '1', D => reset_sync_reg1, PRE => reset_sync5_0(0), Q => reset_sync_reg2 ); reset_sync3: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => independent_clock_bufg, CE => '1', D => reset_sync_reg2, PRE => reset_sync5_0(0), Q => reset_sync_reg3 ); reset_sync4: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => independent_clock_bufg, CE => '1', D => reset_sync_reg3, PRE => reset_sync5_0(0), Q => reset_sync_reg4 ); reset_sync5: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => independent_clock_bufg, CE => '1', D => reset_sync_reg4, PRE => reset_sync5_0(0), Q => reset_sync_reg5 ); reset_sync6: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => independent_clock_bufg, CE => '1', D => reset_sync_reg5, PRE => '0', Q => reset_out ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_reset_sync_2 is port ( reset_out : out STD_LOGIC; independent_clock_bufg : in STD_LOGIC; SR : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_reset_sync_2 : entity is "gig_ethernet_pcs_pma_16_1_reset_sync"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_reset_sync_2; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_reset_sync_2 is signal reset_sync_reg1 : STD_LOGIC; signal reset_sync_reg2 : STD_LOGIC; signal reset_sync_reg3 : STD_LOGIC; signal reset_sync_reg4 : STD_LOGIC; signal reset_sync_reg5 : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of reset_sync1 : label is std.standard.true; attribute SHREG_EXTRACT : string; attribute SHREG_EXTRACT of reset_sync1 : label is "no"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of reset_sync1 : label is "FDP"; attribute box_type : string; attribute box_type of reset_sync1 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync2 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync2 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync2 : label is "FDP"; attribute box_type of reset_sync2 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync3 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync3 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync3 : label is "FDP"; attribute box_type of reset_sync3 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync4 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync4 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync4 : label is "FDP"; attribute box_type of reset_sync4 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync5 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync5 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync5 : label is "FDP"; attribute box_type of reset_sync5 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync6 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync6 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync6 : label is "FDP"; attribute box_type of reset_sync6 : label is "PRIMITIVE"; begin reset_sync1: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => independent_clock_bufg, CE => '1', D => '0', PRE => SR(0), Q => reset_sync_reg1 ); reset_sync2: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => independent_clock_bufg, CE => '1', D => reset_sync_reg1, PRE => SR(0), Q => reset_sync_reg2 ); reset_sync3: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => independent_clock_bufg, CE => '1', D => reset_sync_reg2, PRE => SR(0), Q => reset_sync_reg3 ); reset_sync4: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => independent_clock_bufg, CE => '1', D => reset_sync_reg3, PRE => SR(0), Q => reset_sync_reg4 ); reset_sync5: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => independent_clock_bufg, CE => '1', D => reset_sync_reg4, PRE => SR(0), Q => reset_sync_reg5 ); reset_sync6: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => independent_clock_bufg, CE => '1', D => reset_sync_reg5, PRE => '0', Q => reset_out ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_reset_wtd_timer is port ( reset : out STD_LOGIC; independent_clock_bufg : in STD_LOGIC; data_out : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_reset_wtd_timer; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_reset_wtd_timer is signal \counter_stg1[5]_i_1_n_0\ : STD_LOGIC; signal \counter_stg1[5]_i_3_n_0\ : STD_LOGIC; signal \counter_stg1_reg__0\ : STD_LOGIC_VECTOR ( 5 to 5 ); signal \counter_stg1_reg__0__0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); signal \counter_stg2[0]_i_3_n_0\ : STD_LOGIC; signal counter_stg2_reg : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \counter_stg2_reg[0]_i_2_n_0\ : STD_LOGIC; signal \counter_stg2_reg[0]_i_2_n_1\ : STD_LOGIC; signal \counter_stg2_reg[0]_i_2_n_2\ : STD_LOGIC; signal \counter_stg2_reg[0]_i_2_n_3\ : STD_LOGIC; signal \counter_stg2_reg[0]_i_2_n_4\ : STD_LOGIC; signal \counter_stg2_reg[0]_i_2_n_5\ : STD_LOGIC; signal \counter_stg2_reg[0]_i_2_n_6\ : STD_LOGIC; signal \counter_stg2_reg[0]_i_2_n_7\ : STD_LOGIC; signal \counter_stg2_reg[4]_i_1_n_0\ : STD_LOGIC; signal \counter_stg2_reg[4]_i_1_n_1\ : STD_LOGIC; signal \counter_stg2_reg[4]_i_1_n_2\ : STD_LOGIC; signal \counter_stg2_reg[4]_i_1_n_3\ : STD_LOGIC; signal \counter_stg2_reg[4]_i_1_n_4\ : STD_LOGIC; signal \counter_stg2_reg[4]_i_1_n_5\ : STD_LOGIC; signal \counter_stg2_reg[4]_i_1_n_6\ : STD_LOGIC; signal \counter_stg2_reg[4]_i_1_n_7\ : STD_LOGIC; signal \counter_stg2_reg[8]_i_1_n_1\ : STD_LOGIC; signal \counter_stg2_reg[8]_i_1_n_2\ : STD_LOGIC; signal \counter_stg2_reg[8]_i_1_n_3\ : STD_LOGIC; signal \counter_stg2_reg[8]_i_1_n_4\ : STD_LOGIC; signal \counter_stg2_reg[8]_i_1_n_5\ : STD_LOGIC; signal \counter_stg2_reg[8]_i_1_n_6\ : STD_LOGIC; signal \counter_stg2_reg[8]_i_1_n_7\ : STD_LOGIC; signal counter_stg30 : STD_LOGIC; signal \counter_stg3[0]_i_3_n_0\ : STD_LOGIC; signal \counter_stg3[0]_i_4_n_0\ : STD_LOGIC; signal \counter_stg3[0]_i_5_n_0\ : STD_LOGIC; signal counter_stg3_reg : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \counter_stg3_reg[0]_i_2_n_0\ : STD_LOGIC; signal \counter_stg3_reg[0]_i_2_n_1\ : STD_LOGIC; signal \counter_stg3_reg[0]_i_2_n_2\ : STD_LOGIC; signal \counter_stg3_reg[0]_i_2_n_3\ : STD_LOGIC; signal \counter_stg3_reg[0]_i_2_n_4\ : STD_LOGIC; signal \counter_stg3_reg[0]_i_2_n_5\ : STD_LOGIC; signal \counter_stg3_reg[0]_i_2_n_6\ : STD_LOGIC; signal \counter_stg3_reg[0]_i_2_n_7\ : STD_LOGIC; signal \counter_stg3_reg[4]_i_1_n_0\ : STD_LOGIC; signal \counter_stg3_reg[4]_i_1_n_1\ : STD_LOGIC; signal \counter_stg3_reg[4]_i_1_n_2\ : STD_LOGIC; signal \counter_stg3_reg[4]_i_1_n_3\ : STD_LOGIC; signal \counter_stg3_reg[4]_i_1_n_4\ : STD_LOGIC; signal \counter_stg3_reg[4]_i_1_n_5\ : STD_LOGIC; signal \counter_stg3_reg[4]_i_1_n_6\ : STD_LOGIC; signal \counter_stg3_reg[4]_i_1_n_7\ : STD_LOGIC; signal \counter_stg3_reg[8]_i_1_n_1\ : STD_LOGIC; signal \counter_stg3_reg[8]_i_1_n_2\ : STD_LOGIC; signal \counter_stg3_reg[8]_i_1_n_3\ : STD_LOGIC; signal \counter_stg3_reg[8]_i_1_n_4\ : STD_LOGIC; signal \counter_stg3_reg[8]_i_1_n_5\ : STD_LOGIC; signal \counter_stg3_reg[8]_i_1_n_6\ : STD_LOGIC; signal \counter_stg3_reg[8]_i_1_n_7\ : STD_LOGIC; signal eqOp : STD_LOGIC; signal plusOp : STD_LOGIC_VECTOR ( 5 downto 0 ); signal reset0 : STD_LOGIC; signal reset_i_2_n_0 : STD_LOGIC; signal reset_i_3_n_0 : STD_LOGIC; signal reset_i_4_n_0 : STD_LOGIC; signal reset_i_5_n_0 : STD_LOGIC; signal reset_i_6_n_0 : STD_LOGIC; signal \NLW_counter_stg2_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); signal \NLW_counter_stg3_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \counter_stg1[0]_i_1\ : label is "soft_lutpair76"; attribute SOFT_HLUTNM of \counter_stg1[1]_i_1\ : label is "soft_lutpair76"; attribute SOFT_HLUTNM of \counter_stg1[2]_i_1\ : label is "soft_lutpair75"; attribute SOFT_HLUTNM of \counter_stg1[3]_i_1\ : label is "soft_lutpair75"; attribute SOFT_HLUTNM of \counter_stg1[4]_i_1\ : label is "soft_lutpair74"; attribute SOFT_HLUTNM of \counter_stg1[5]_i_3\ : label is "soft_lutpair74"; begin \counter_stg1[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \counter_stg1_reg__0__0\(0), O => plusOp(0) ); \counter_stg1[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \counter_stg1_reg__0__0\(0), I1 => \counter_stg1_reg__0__0\(1), O => plusOp(1) ); \counter_stg1[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \counter_stg1_reg__0__0\(1), I1 => \counter_stg1_reg__0__0\(0), I2 => \counter_stg1_reg__0__0\(2), O => plusOp(2) ); \counter_stg1[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \counter_stg1_reg__0__0\(2), I1 => \counter_stg1_reg__0__0\(0), I2 => \counter_stg1_reg__0__0\(1), I3 => \counter_stg1_reg__0__0\(3), O => plusOp(3) ); \counter_stg1[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \counter_stg1_reg__0__0\(3), I1 => \counter_stg1_reg__0__0\(1), I2 => \counter_stg1_reg__0__0\(0), I3 => \counter_stg1_reg__0__0\(2), I4 => \counter_stg1_reg__0__0\(4), O => plusOp(4) ); \counter_stg1[5]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFF2000" ) port map ( I0 => reset_i_2_n_0, I1 => counter_stg3_reg(0), I2 => reset_i_3_n_0, I3 => \counter_stg1[5]_i_3_n_0\, I4 => data_out, O => \counter_stg1[5]_i_1_n_0\ ); \counter_stg1[5]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \counter_stg1_reg__0__0\(4), I1 => \counter_stg1_reg__0__0\(2), I2 => \counter_stg1_reg__0__0\(0), I3 => \counter_stg1_reg__0__0\(1), I4 => \counter_stg1_reg__0__0\(3), I5 => \counter_stg1_reg__0\(5), O => plusOp(5) ); \counter_stg1[5]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"80000000" ) port map ( I0 => \counter_stg1_reg__0__0\(3), I1 => \counter_stg1_reg__0__0\(1), I2 => \counter_stg1_reg__0__0\(0), I3 => \counter_stg1_reg__0__0\(2), I4 => \counter_stg1_reg__0__0\(4), O => \counter_stg1[5]_i_3_n_0\ ); \counter_stg1_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => plusOp(0), Q => \counter_stg1_reg__0__0\(0), R => \counter_stg1[5]_i_1_n_0\ ); \counter_stg1_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => plusOp(1), Q => \counter_stg1_reg__0__0\(1), R => \counter_stg1[5]_i_1_n_0\ ); \counter_stg1_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => plusOp(2), Q => \counter_stg1_reg__0__0\(2), R => \counter_stg1[5]_i_1_n_0\ ); \counter_stg1_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => plusOp(3), Q => \counter_stg1_reg__0__0\(3), R => \counter_stg1[5]_i_1_n_0\ ); \counter_stg1_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => plusOp(4), Q => \counter_stg1_reg__0__0\(4), R => \counter_stg1[5]_i_1_n_0\ ); \counter_stg1_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => plusOp(5), Q => \counter_stg1_reg__0\(5), R => \counter_stg1[5]_i_1_n_0\ ); \counter_stg2[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => \counter_stg1_reg__0__0\(4), I1 => \counter_stg1_reg__0__0\(2), I2 => \counter_stg1_reg__0__0\(0), I3 => \counter_stg1_reg__0__0\(1), I4 => \counter_stg1_reg__0__0\(3), I5 => \counter_stg1_reg__0\(5), O => eqOp ); \counter_stg2[0]_i_3\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => counter_stg2_reg(0), O => \counter_stg2[0]_i_3_n_0\ ); \counter_stg2_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => eqOp, D => \counter_stg2_reg[0]_i_2_n_7\, Q => counter_stg2_reg(0), R => \counter_stg1[5]_i_1_n_0\ ); \counter_stg2_reg[0]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \counter_stg2_reg[0]_i_2_n_0\, CO(2) => \counter_stg2_reg[0]_i_2_n_1\, CO(1) => \counter_stg2_reg[0]_i_2_n_2\, CO(0) => \counter_stg2_reg[0]_i_2_n_3\, CYINIT => '0', DI(3 downto 0) => B"0001", O(3) => \counter_stg2_reg[0]_i_2_n_4\, O(2) => \counter_stg2_reg[0]_i_2_n_5\, O(1) => \counter_stg2_reg[0]_i_2_n_6\, O(0) => \counter_stg2_reg[0]_i_2_n_7\, S(3 downto 1) => counter_stg2_reg(3 downto 1), S(0) => \counter_stg2[0]_i_3_n_0\ ); \counter_stg2_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => eqOp, D => \counter_stg2_reg[8]_i_1_n_5\, Q => counter_stg2_reg(10), R => \counter_stg1[5]_i_1_n_0\ ); \counter_stg2_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => eqOp, D => \counter_stg2_reg[8]_i_1_n_4\, Q => counter_stg2_reg(11), R => \counter_stg1[5]_i_1_n_0\ ); \counter_stg2_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => eqOp, D => \counter_stg2_reg[0]_i_2_n_6\, Q => counter_stg2_reg(1), R => \counter_stg1[5]_i_1_n_0\ ); \counter_stg2_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => eqOp, D => \counter_stg2_reg[0]_i_2_n_5\, Q => counter_stg2_reg(2), R => \counter_stg1[5]_i_1_n_0\ ); \counter_stg2_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => eqOp, D => \counter_stg2_reg[0]_i_2_n_4\, Q => counter_stg2_reg(3), R => \counter_stg1[5]_i_1_n_0\ ); \counter_stg2_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => eqOp, D => \counter_stg2_reg[4]_i_1_n_7\, Q => counter_stg2_reg(4), R => \counter_stg1[5]_i_1_n_0\ ); \counter_stg2_reg[4]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \counter_stg2_reg[0]_i_2_n_0\, CO(3) => \counter_stg2_reg[4]_i_1_n_0\, CO(2) => \counter_stg2_reg[4]_i_1_n_1\, CO(1) => \counter_stg2_reg[4]_i_1_n_2\, CO(0) => \counter_stg2_reg[4]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \counter_stg2_reg[4]_i_1_n_4\, O(2) => \counter_stg2_reg[4]_i_1_n_5\, O(1) => \counter_stg2_reg[4]_i_1_n_6\, O(0) => \counter_stg2_reg[4]_i_1_n_7\, S(3 downto 0) => counter_stg2_reg(7 downto 4) ); \counter_stg2_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => eqOp, D => \counter_stg2_reg[4]_i_1_n_6\, Q => counter_stg2_reg(5), R => \counter_stg1[5]_i_1_n_0\ ); \counter_stg2_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => eqOp, D => \counter_stg2_reg[4]_i_1_n_5\, Q => counter_stg2_reg(6), R => \counter_stg1[5]_i_1_n_0\ ); \counter_stg2_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => eqOp, D => \counter_stg2_reg[4]_i_1_n_4\, Q => counter_stg2_reg(7), R => \counter_stg1[5]_i_1_n_0\ ); \counter_stg2_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => eqOp, D => \counter_stg2_reg[8]_i_1_n_7\, Q => counter_stg2_reg(8), R => \counter_stg1[5]_i_1_n_0\ ); \counter_stg2_reg[8]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \counter_stg2_reg[4]_i_1_n_0\, CO(3) => \NLW_counter_stg2_reg[8]_i_1_CO_UNCONNECTED\(3), CO(2) => \counter_stg2_reg[8]_i_1_n_1\, CO(1) => \counter_stg2_reg[8]_i_1_n_2\, CO(0) => \counter_stg2_reg[8]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \counter_stg2_reg[8]_i_1_n_4\, O(2) => \counter_stg2_reg[8]_i_1_n_5\, O(1) => \counter_stg2_reg[8]_i_1_n_6\, O(0) => \counter_stg2_reg[8]_i_1_n_7\, S(3 downto 0) => counter_stg2_reg(11 downto 8) ); \counter_stg2_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => eqOp, D => \counter_stg2_reg[8]_i_1_n_6\, Q => counter_stg2_reg(9), R => \counter_stg1[5]_i_1_n_0\ ); \counter_stg3[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"8000" ) port map ( I0 => \counter_stg3[0]_i_3_n_0\, I1 => \counter_stg3[0]_i_4_n_0\, I2 => counter_stg2_reg(0), I3 => \counter_stg1[5]_i_3_n_0\, O => counter_stg30 ); \counter_stg3[0]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => counter_stg2_reg(3), I1 => counter_stg2_reg(4), I2 => counter_stg2_reg(1), I3 => counter_stg2_reg(2), I4 => counter_stg2_reg(6), I5 => counter_stg2_reg(5), O => \counter_stg3[0]_i_3_n_0\ ); \counter_stg3[0]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => counter_stg2_reg(9), I1 => counter_stg2_reg(10), I2 => counter_stg2_reg(7), I3 => counter_stg2_reg(8), I4 => \counter_stg1_reg__0\(5), I5 => counter_stg2_reg(11), O => \counter_stg3[0]_i_4_n_0\ ); \counter_stg3[0]_i_5\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => counter_stg3_reg(0), O => \counter_stg3[0]_i_5_n_0\ ); \counter_stg3_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => counter_stg30, D => \counter_stg3_reg[0]_i_2_n_7\, Q => counter_stg3_reg(0), R => \counter_stg1[5]_i_1_n_0\ ); \counter_stg3_reg[0]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \counter_stg3_reg[0]_i_2_n_0\, CO(2) => \counter_stg3_reg[0]_i_2_n_1\, CO(1) => \counter_stg3_reg[0]_i_2_n_2\, CO(0) => \counter_stg3_reg[0]_i_2_n_3\, CYINIT => '0', DI(3 downto 0) => B"0001", O(3) => \counter_stg3_reg[0]_i_2_n_4\, O(2) => \counter_stg3_reg[0]_i_2_n_5\, O(1) => \counter_stg3_reg[0]_i_2_n_6\, O(0) => \counter_stg3_reg[0]_i_2_n_7\, S(3 downto 1) => counter_stg3_reg(3 downto 1), S(0) => \counter_stg3[0]_i_5_n_0\ ); \counter_stg3_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => counter_stg30, D => \counter_stg3_reg[8]_i_1_n_5\, Q => counter_stg3_reg(10), R => \counter_stg1[5]_i_1_n_0\ ); \counter_stg3_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => counter_stg30, D => \counter_stg3_reg[8]_i_1_n_4\, Q => counter_stg3_reg(11), R => \counter_stg1[5]_i_1_n_0\ ); \counter_stg3_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => counter_stg30, D => \counter_stg3_reg[0]_i_2_n_6\, Q => counter_stg3_reg(1), R => \counter_stg1[5]_i_1_n_0\ ); \counter_stg3_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => counter_stg30, D => \counter_stg3_reg[0]_i_2_n_5\, Q => counter_stg3_reg(2), R => \counter_stg1[5]_i_1_n_0\ ); \counter_stg3_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => counter_stg30, D => \counter_stg3_reg[0]_i_2_n_4\, Q => counter_stg3_reg(3), R => \counter_stg1[5]_i_1_n_0\ ); \counter_stg3_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => counter_stg30, D => \counter_stg3_reg[4]_i_1_n_7\, Q => counter_stg3_reg(4), R => \counter_stg1[5]_i_1_n_0\ ); \counter_stg3_reg[4]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \counter_stg3_reg[0]_i_2_n_0\, CO(3) => \counter_stg3_reg[4]_i_1_n_0\, CO(2) => \counter_stg3_reg[4]_i_1_n_1\, CO(1) => \counter_stg3_reg[4]_i_1_n_2\, CO(0) => \counter_stg3_reg[4]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \counter_stg3_reg[4]_i_1_n_4\, O(2) => \counter_stg3_reg[4]_i_1_n_5\, O(1) => \counter_stg3_reg[4]_i_1_n_6\, O(0) => \counter_stg3_reg[4]_i_1_n_7\, S(3 downto 0) => counter_stg3_reg(7 downto 4) ); \counter_stg3_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => counter_stg30, D => \counter_stg3_reg[4]_i_1_n_6\, Q => counter_stg3_reg(5), R => \counter_stg1[5]_i_1_n_0\ ); \counter_stg3_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => counter_stg30, D => \counter_stg3_reg[4]_i_1_n_5\, Q => counter_stg3_reg(6), R => \counter_stg1[5]_i_1_n_0\ ); \counter_stg3_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => counter_stg30, D => \counter_stg3_reg[4]_i_1_n_4\, Q => counter_stg3_reg(7), R => \counter_stg1[5]_i_1_n_0\ ); \counter_stg3_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => counter_stg30, D => \counter_stg3_reg[8]_i_1_n_7\, Q => counter_stg3_reg(8), R => \counter_stg1[5]_i_1_n_0\ ); \counter_stg3_reg[8]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \counter_stg3_reg[4]_i_1_n_0\, CO(3) => \NLW_counter_stg3_reg[8]_i_1_CO_UNCONNECTED\(3), CO(2) => \counter_stg3_reg[8]_i_1_n_1\, CO(1) => \counter_stg3_reg[8]_i_1_n_2\, CO(0) => \counter_stg3_reg[8]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \counter_stg3_reg[8]_i_1_n_4\, O(2) => \counter_stg3_reg[8]_i_1_n_5\, O(1) => \counter_stg3_reg[8]_i_1_n_6\, O(0) => \counter_stg3_reg[8]_i_1_n_7\, S(3 downto 0) => counter_stg3_reg(11 downto 8) ); \counter_stg3_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => counter_stg30, D => \counter_stg3_reg[8]_i_1_n_6\, Q => counter_stg3_reg(9), R => \counter_stg1[5]_i_1_n_0\ ); reset_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"20" ) port map ( I0 => reset_i_2_n_0, I1 => counter_stg3_reg(0), I2 => reset_i_3_n_0, O => reset0 ); reset_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000001000000000" ) port map ( I0 => counter_stg3_reg(9), I1 => counter_stg3_reg(10), I2 => counter_stg3_reg(7), I3 => counter_stg3_reg(8), I4 => counter_stg2_reg(0), I5 => counter_stg3_reg(11), O => reset_i_2_n_0 ); reset_i_3: unisim.vcomponents.LUT3 generic map( INIT => X"80" ) port map ( I0 => reset_i_4_n_0, I1 => reset_i_5_n_0, I2 => reset_i_6_n_0, O => reset_i_3_n_0 ); reset_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000008" ) port map ( I0 => counter_stg2_reg(3), I1 => counter_stg2_reg(4), I2 => counter_stg2_reg(1), I3 => counter_stg2_reg(2), I4 => counter_stg2_reg(6), I5 => counter_stg2_reg(5), O => reset_i_4_n_0 ); reset_i_5: unisim.vcomponents.LUT6 generic map( INIT => X"0020000000000000" ) port map ( I0 => counter_stg2_reg(10), I1 => counter_stg2_reg(9), I2 => counter_stg2_reg(8), I3 => counter_stg2_reg(7), I4 => \counter_stg1_reg__0\(5), I5 => counter_stg2_reg(11), O => reset_i_5_n_0 ); reset_i_6: unisim.vcomponents.LUT6 generic map( INIT => X"0002000000000000" ) port map ( I0 => counter_stg3_reg(4), I1 => counter_stg3_reg(3), I2 => counter_stg3_reg(1), I3 => counter_stg3_reg(2), I4 => counter_stg3_reg(6), I5 => counter_stg3_reg(5), O => reset_i_6_n_0 ); reset_reg: unisim.vcomponents.FDRE port map ( C => independent_clock_bufg, CE => '1', D => reset0, Q => reset, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block is port ( data_out : out STD_LOGIC; data_in : in STD_LOGIC; userclk2 : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block is signal data_sync1 : STD_LOGIC; signal data_sync2 : STD_LOGIC; signal data_sync3 : STD_LOGIC; signal data_sync4 : STD_LOGIC; signal data_sync5 : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true; attribute SHREG_EXTRACT : string; attribute SHREG_EXTRACT of data_sync_reg1 : label is "no"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD"; attribute box_type : string; attribute box_type of data_sync_reg1 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg2 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD"; attribute box_type of data_sync_reg2 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg3 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD"; attribute box_type of data_sync_reg3 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg4 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD"; attribute box_type of data_sync_reg4 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg5 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD"; attribute box_type of data_sync_reg5 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg6 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD"; attribute box_type of data_sync_reg6 : label is "PRIMITIVE"; begin data_sync_reg1: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => data_in, Q => data_sync1, R => '0' ); data_sync_reg2: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => data_sync1, Q => data_sync2, R => '0' ); data_sync_reg3: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => data_sync2, Q => data_sync3, R => '0' ); data_sync_reg4: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => data_sync3, Q => data_sync4, R => '0' ); data_sync_reg5: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => data_sync4, Q => data_sync5, R => '0' ); data_sync_reg6: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => data_sync5, Q => data_out, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_0 is port ( resetdone : out STD_LOGIC; resetdone_0 : in STD_LOGIC; data_in : in STD_LOGIC; userclk2 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_0 : entity is "gig_ethernet_pcs_pma_16_1_sync_block"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_0; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_0 is signal data_out : STD_LOGIC; signal data_sync1 : STD_LOGIC; signal data_sync2 : STD_LOGIC; signal data_sync3 : STD_LOGIC; signal data_sync4 : STD_LOGIC; signal data_sync5 : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true; attribute SHREG_EXTRACT : string; attribute SHREG_EXTRACT of data_sync_reg1 : label is "no"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD"; attribute box_type : string; attribute box_type of data_sync_reg1 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg2 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD"; attribute box_type of data_sync_reg2 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg3 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD"; attribute box_type of data_sync_reg3 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg4 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD"; attribute box_type of data_sync_reg4 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg5 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD"; attribute box_type of data_sync_reg5 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg6 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD"; attribute box_type of data_sync_reg6 : label is "PRIMITIVE"; begin data_sync_reg1: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => data_in, Q => data_sync1, R => '0' ); data_sync_reg2: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => data_sync1, Q => data_sync2, R => '0' ); data_sync_reg3: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => data_sync2, Q => data_sync3, R => '0' ); data_sync_reg4: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => data_sync3, Q => data_sync4, R => '0' ); data_sync_reg5: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => data_sync4, Q => data_sync5, R => '0' ); data_sync_reg6: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => data_sync5, Q => data_out, R => '0' ); resetdone_INST_0: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => data_out, I1 => resetdone_0, O => resetdone ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_10 is port ( data_out : out STD_LOGIC; data_sync_reg1_0 : in STD_LOGIC; independent_clock_bufg : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_10 : entity is "gig_ethernet_pcs_pma_16_1_sync_block"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_10; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_10 is signal data_sync1 : STD_LOGIC; signal data_sync2 : STD_LOGIC; signal data_sync3 : STD_LOGIC; signal data_sync4 : STD_LOGIC; signal data_sync5 : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true; attribute SHREG_EXTRACT : string; attribute SHREG_EXTRACT of data_sync_reg1 : label is "no"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD"; attribute box_type : string; attribute box_type of data_sync_reg1 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg2 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD"; attribute box_type of data_sync_reg2 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg3 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD"; attribute box_type of data_sync_reg3 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg4 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD"; attribute box_type of data_sync_reg4 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg5 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD"; attribute box_type of data_sync_reg5 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg6 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD"; attribute box_type of data_sync_reg6 : label is "PRIMITIVE"; begin data_sync_reg1: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync_reg1_0, Q => data_sync1, R => '0' ); data_sync_reg2: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync1, Q => data_sync2, R => '0' ); data_sync_reg3: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync2, Q => data_sync3, R => '0' ); data_sync_reg4: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync3, Q => data_sync4, R => '0' ); data_sync_reg5: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync4, Q => data_sync5, R => '0' ); data_sync_reg6: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync5, Q => data_out, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_11 is port ( \FSM_sequential_rx_state_reg[1]\ : out STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); rxresetdone_s3 : in STD_LOGIC; cplllock : in STD_LOGIC; independent_clock_bufg : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_11 : entity is "gig_ethernet_pcs_pma_16_1_sync_block"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_11; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_11 is signal cplllock_sync : STD_LOGIC; signal data_sync1 : STD_LOGIC; signal data_sync2 : STD_LOGIC; signal data_sync3 : STD_LOGIC; signal data_sync4 : STD_LOGIC; signal data_sync5 : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true; attribute SHREG_EXTRACT : string; attribute SHREG_EXTRACT of data_sync_reg1 : label is "no"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD"; attribute box_type : string; attribute box_type of data_sync_reg1 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg2 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD"; attribute box_type of data_sync_reg2 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg3 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD"; attribute box_type of data_sync_reg3 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg4 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD"; attribute box_type of data_sync_reg4 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg5 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD"; attribute box_type of data_sync_reg5 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg6 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD"; attribute box_type of data_sync_reg6 : label is "PRIMITIVE"; begin \FSM_sequential_rx_state[3]_i_5\: unisim.vcomponents.LUT5 generic map( INIT => X"008F0080" ) port map ( I0 => Q(0), I1 => rxresetdone_s3, I2 => Q(1), I3 => Q(2), I4 => cplllock_sync, O => \FSM_sequential_rx_state_reg[1]\ ); data_sync_reg1: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => cplllock, Q => data_sync1, R => '0' ); data_sync_reg2: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync1, Q => data_sync2, R => '0' ); data_sync_reg3: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync2, Q => data_sync3, R => '0' ); data_sync_reg4: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync3, Q => data_sync4, R => '0' ); data_sync_reg5: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync4, Q => data_sync5, R => '0' ); data_sync_reg6: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync5, Q => cplllock_sync, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_12 is port ( D : out STD_LOGIC_VECTOR ( 2 downto 0 ); E : out STD_LOGIC_VECTOR ( 0 to 0 ); \FSM_sequential_rx_state_reg[1]\ : out STD_LOGIC; rx_fsm_reset_done_int_reg : out STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 3 downto 0 ); \FSM_sequential_rx_state_reg[1]_0\ : in STD_LOGIC; rx_fsm_reset_done_int_reg_0 : in STD_LOGIC; rx_fsm_reset_done_int_reg_1 : in STD_LOGIC; reset_time_out_reg : in STD_LOGIC; \FSM_sequential_rx_state_reg[0]\ : in STD_LOGIC; reset_time_out_reg_0 : in STD_LOGIC; \FSM_sequential_rx_state_reg[0]_0\ : in STD_LOGIC; \FSM_sequential_rx_state_reg[0]_1\ : in STD_LOGIC; mmcm_lock_reclocked : in STD_LOGIC; \FSM_sequential_rx_state_reg[0]_2\ : in STD_LOGIC; time_out_wait_bypass_s3 : in STD_LOGIC; \FSM_sequential_rx_state_reg[3]\ : in STD_LOGIC; \FSM_sequential_rx_state_reg[0]_3\ : in STD_LOGIC; rx_fsm_reset_done_int_reg_2 : in STD_LOGIC; rx_fsm_reset_done_int_reg_3 : in STD_LOGIC; reset_time_out_reg_1 : in STD_LOGIC; reset_time_out_reg_2 : in STD_LOGIC; data_in : in STD_LOGIC; data_out : in STD_LOGIC; independent_clock_bufg : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_12 : entity is "gig_ethernet_pcs_pma_16_1_sync_block"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_12; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_12 is signal \FSM_sequential_rx_state[0]_i_3_n_0\ : STD_LOGIC; signal \FSM_sequential_rx_state[1]_i_2_n_0\ : STD_LOGIC; signal \FSM_sequential_rx_state[3]_i_4_n_0\ : STD_LOGIC; signal \FSM_sequential_rx_state[3]_i_6_n_0\ : STD_LOGIC; signal \FSM_sequential_rx_state[3]_i_8_n_0\ : STD_LOGIC; signal data_sync1 : STD_LOGIC; signal data_sync2 : STD_LOGIC; signal data_sync3 : STD_LOGIC; signal data_sync4 : STD_LOGIC; signal data_sync5 : STD_LOGIC; signal data_valid_sync : STD_LOGIC; signal reset_time_out_i_2_n_0 : STD_LOGIC; signal rx_fsm_reset_done_int : STD_LOGIC; signal rx_fsm_reset_done_int_i_3_n_0 : STD_LOGIC; signal rx_fsm_reset_done_int_i_4_n_0 : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \FSM_sequential_rx_state[0]_i_3\ : label is "soft_lutpair42"; attribute SOFT_HLUTNM of \FSM_sequential_rx_state[3]_i_8\ : label is "soft_lutpair42"; attribute ASYNC_REG : boolean; attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true; attribute SHREG_EXTRACT : string; attribute SHREG_EXTRACT of data_sync_reg1 : label is "no"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD"; attribute box_type : string; attribute box_type of data_sync_reg1 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg2 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD"; attribute box_type of data_sync_reg2 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg3 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD"; attribute box_type of data_sync_reg3 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg4 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD"; attribute box_type of data_sync_reg4 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg5 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD"; attribute box_type of data_sync_reg5 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg6 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD"; attribute box_type of data_sync_reg6 : label is "PRIMITIVE"; begin \FSM_sequential_rx_state[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFEFEFEF" ) port map ( I0 => \FSM_sequential_rx_state_reg[0]_2\, I1 => \FSM_sequential_rx_state[0]_i_3_n_0\, I2 => Q(0), I3 => Q(1), I4 => Q(3), O => D(0) ); \FSM_sequential_rx_state[0]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"0200" ) port map ( I0 => Q(3), I1 => reset_time_out_reg, I2 => data_valid_sync, I3 => rx_fsm_reset_done_int_reg_1, O => \FSM_sequential_rx_state[0]_i_3_n_0\ ); \FSM_sequential_rx_state[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF24200400" ) port map ( I0 => Q(0), I1 => Q(1), I2 => Q(3), I3 => Q(2), I4 => \FSM_sequential_rx_state[1]_i_2_n_0\, I5 => \FSM_sequential_rx_state_reg[1]_0\, O => D(1) ); \FSM_sequential_rx_state[1]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => data_valid_sync, I1 => rx_fsm_reset_done_int_reg_1, O => \FSM_sequential_rx_state[1]_i_2_n_0\ ); \FSM_sequential_rx_state[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFEEE" ) port map ( I0 => \FSM_sequential_rx_state_reg[0]\, I1 => \FSM_sequential_rx_state[3]_i_4_n_0\, I2 => Q(0), I3 => reset_time_out_reg_0, I4 => \FSM_sequential_rx_state[3]_i_6_n_0\, I5 => \FSM_sequential_rx_state_reg[0]_0\, O => E(0) ); \FSM_sequential_rx_state[3]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFCCC0C4C4" ) port map ( I0 => time_out_wait_bypass_s3, I1 => Q(3), I2 => Q(1), I3 => \FSM_sequential_rx_state[3]_i_8_n_0\, I4 => Q(0), I5 => \FSM_sequential_rx_state_reg[3]\, O => D(2) ); \FSM_sequential_rx_state[3]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAAAAAAEFEA" ) port map ( I0 => \FSM_sequential_rx_state[0]_i_3_n_0\, I1 => \FSM_sequential_rx_state_reg[0]_1\, I2 => Q(2), I3 => \FSM_sequential_rx_state_reg[0]_3\, I4 => Q(0), I5 => Q(1), O => \FSM_sequential_rx_state[3]_i_4_n_0\ ); \FSM_sequential_rx_state[3]_i_6\: unisim.vcomponents.LUT5 generic map( INIT => X"0CE20CCC" ) port map ( I0 => mmcm_lock_reclocked, I1 => Q(3), I2 => data_valid_sync, I3 => Q(1), I4 => Q(0), O => \FSM_sequential_rx_state[3]_i_6_n_0\ ); \FSM_sequential_rx_state[3]_i_8\: unisim.vcomponents.LUT3 generic map( INIT => X"FD" ) port map ( I0 => rx_fsm_reset_done_int_reg_1, I1 => data_valid_sync, I2 => reset_time_out_reg, O => \FSM_sequential_rx_state[3]_i_8_n_0\ ); data_sync_reg1: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_out, Q => data_sync1, R => '0' ); data_sync_reg2: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync1, Q => data_sync2, R => '0' ); data_sync_reg3: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync2, Q => data_sync3, R => '0' ); data_sync_reg4: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync3, Q => data_sync4, R => '0' ); data_sync_reg5: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync4, Q => data_sync5, R => '0' ); data_sync_reg6: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync5, Q => data_valid_sync, R => '0' ); \reset_time_out_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"EEEFFFFFEEEF0000" ) port map ( I0 => reset_time_out_i_2_n_0, I1 => reset_time_out_reg_0, I2 => reset_time_out_reg_1, I3 => Q(1), I4 => reset_time_out_reg_2, I5 => reset_time_out_reg, O => \FSM_sequential_rx_state_reg[1]\ ); reset_time_out_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0FF30E0E0FF30202" ) port map ( I0 => \FSM_sequential_rx_state_reg[0]_1\, I1 => Q(0), I2 => Q(1), I3 => data_valid_sync, I4 => Q(3), I5 => mmcm_lock_reclocked, O => reset_time_out_i_2_n_0 ); rx_fsm_reset_done_int_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"ABA8" ) port map ( I0 => rx_fsm_reset_done_int, I1 => rx_fsm_reset_done_int_i_3_n_0, I2 => rx_fsm_reset_done_int_i_4_n_0, I3 => data_in, O => rx_fsm_reset_done_int_reg ); rx_fsm_reset_done_int_i_2: unisim.vcomponents.LUT5 generic map( INIT => X"00040000" ) port map ( I0 => Q(0), I1 => data_valid_sync, I2 => Q(2), I3 => reset_time_out_reg, I4 => rx_fsm_reset_done_int_reg_2, O => rx_fsm_reset_done_int ); rx_fsm_reset_done_int_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"0400040004040400" ) port map ( I0 => rx_fsm_reset_done_int_reg_0, I1 => Q(3), I2 => Q(2), I3 => data_valid_sync, I4 => rx_fsm_reset_done_int_reg_1, I5 => reset_time_out_reg, O => rx_fsm_reset_done_int_i_3_n_0 ); rx_fsm_reset_done_int_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"0008000808080008" ) port map ( I0 => rx_fsm_reset_done_int_reg_3, I1 => Q(1), I2 => Q(0), I3 => data_valid_sync, I4 => rx_fsm_reset_done_int_reg_2, I5 => reset_time_out_reg, O => rx_fsm_reset_done_int_i_4_n_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_13 is port ( SR : out STD_LOGIC_VECTOR ( 0 to 0 ); mmcm_lock_reclocked_reg : out STD_LOGIC; mmcm_lock_reclocked : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); mmcm_lock_reclocked_reg_0 : in STD_LOGIC; mmcm_locked : in STD_LOGIC; independent_clock_bufg : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_13 : entity is "gig_ethernet_pcs_pma_16_1_sync_block"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_13; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_13 is signal data_sync1 : STD_LOGIC; signal data_sync2 : STD_LOGIC; signal data_sync3 : STD_LOGIC; signal data_sync4 : STD_LOGIC; signal data_sync5 : STD_LOGIC; signal mmcm_lock_i : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true; attribute SHREG_EXTRACT : string; attribute SHREG_EXTRACT of data_sync_reg1 : label is "no"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD"; attribute box_type : string; attribute box_type of data_sync_reg1 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg2 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD"; attribute box_type of data_sync_reg2 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg3 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD"; attribute box_type of data_sync_reg3 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg4 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD"; attribute box_type of data_sync_reg4 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg5 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD"; attribute box_type of data_sync_reg5 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg6 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD"; attribute box_type of data_sync_reg6 : label is "PRIMITIVE"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \mmcm_lock_count[7]_i_1__0\ : label is "soft_lutpair43"; attribute SOFT_HLUTNM of \mmcm_lock_reclocked_i_1__0\ : label is "soft_lutpair43"; begin data_sync_reg1: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => mmcm_locked, Q => data_sync1, R => '0' ); data_sync_reg2: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync1, Q => data_sync2, R => '0' ); data_sync_reg3: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync2, Q => data_sync3, R => '0' ); data_sync_reg4: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync3, Q => data_sync4, R => '0' ); data_sync_reg5: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync4, Q => data_sync5, R => '0' ); data_sync_reg6: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync5, Q => mmcm_lock_i, R => '0' ); \mmcm_lock_count[7]_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => mmcm_lock_i, O => SR(0) ); \mmcm_lock_reclocked_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"AAEA0000" ) port map ( I0 => mmcm_lock_reclocked, I1 => Q(1), I2 => Q(0), I3 => mmcm_lock_reclocked_reg_0, I4 => mmcm_lock_i, O => mmcm_lock_reclocked_reg ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_14 is port ( data_out : out STD_LOGIC; data_in : in STD_LOGIC; userclk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_14 : entity is "gig_ethernet_pcs_pma_16_1_sync_block"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_14; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_14 is signal data_sync1 : STD_LOGIC; signal data_sync2 : STD_LOGIC; signal data_sync3 : STD_LOGIC; signal data_sync4 : STD_LOGIC; signal data_sync5 : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true; attribute SHREG_EXTRACT : string; attribute SHREG_EXTRACT of data_sync_reg1 : label is "no"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD"; attribute box_type : string; attribute box_type of data_sync_reg1 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg2 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD"; attribute box_type of data_sync_reg2 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg3 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD"; attribute box_type of data_sync_reg3 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg4 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD"; attribute box_type of data_sync_reg4 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg5 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD"; attribute box_type of data_sync_reg5 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg6 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD"; attribute box_type of data_sync_reg6 : label is "PRIMITIVE"; begin data_sync_reg1: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk, CE => '1', D => data_in, Q => data_sync1, R => '0' ); data_sync_reg2: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk, CE => '1', D => data_sync1, Q => data_sync2, R => '0' ); data_sync_reg3: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk, CE => '1', D => data_sync2, Q => data_sync3, R => '0' ); data_sync_reg4: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk, CE => '1', D => data_sync3, Q => data_sync4, R => '0' ); data_sync_reg5: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk, CE => '1', D => data_sync4, Q => data_sync5, R => '0' ); data_sync_reg6: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk, CE => '1', D => data_sync5, Q => data_out, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_15 is port ( data_out : out STD_LOGIC; data_in : in STD_LOGIC; independent_clock_bufg : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_15 : entity is "gig_ethernet_pcs_pma_16_1_sync_block"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_15; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_15 is signal data_sync1 : STD_LOGIC; signal data_sync2 : STD_LOGIC; signal data_sync3 : STD_LOGIC; signal data_sync4 : STD_LOGIC; signal data_sync5 : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true; attribute SHREG_EXTRACT : string; attribute SHREG_EXTRACT of data_sync_reg1 : label is "no"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD"; attribute box_type : string; attribute box_type of data_sync_reg1 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg2 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD"; attribute box_type of data_sync_reg2 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg3 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD"; attribute box_type of data_sync_reg3 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg4 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD"; attribute box_type of data_sync_reg4 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg5 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD"; attribute box_type of data_sync_reg5 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg6 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD"; attribute box_type of data_sync_reg6 : label is "PRIMITIVE"; begin data_sync_reg1: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_in, Q => data_sync1, R => '0' ); data_sync_reg2: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync1, Q => data_sync2, R => '0' ); data_sync_reg3: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync2, Q => data_sync3, R => '0' ); data_sync_reg4: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync3, Q => data_sync4, R => '0' ); data_sync_reg5: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync4, Q => data_sync5, R => '0' ); data_sync_reg6: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync5, Q => data_out, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_16 is port ( data_out : out STD_LOGIC; data_in : in STD_LOGIC; userclk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_16 : entity is "gig_ethernet_pcs_pma_16_1_sync_block"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_16; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_16 is signal data_sync1 : STD_LOGIC; signal data_sync2 : STD_LOGIC; signal data_sync3 : STD_LOGIC; signal data_sync4 : STD_LOGIC; signal data_sync5 : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true; attribute SHREG_EXTRACT : string; attribute SHREG_EXTRACT of data_sync_reg1 : label is "no"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD"; attribute box_type : string; attribute box_type of data_sync_reg1 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg2 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD"; attribute box_type of data_sync_reg2 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg3 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD"; attribute box_type of data_sync_reg3 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg4 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD"; attribute box_type of data_sync_reg4 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg5 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD"; attribute box_type of data_sync_reg5 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg6 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD"; attribute box_type of data_sync_reg6 : label is "PRIMITIVE"; begin data_sync_reg1: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk, CE => '1', D => data_in, Q => data_sync1, R => '0' ); data_sync_reg2: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk, CE => '1', D => data_sync1, Q => data_sync2, R => '0' ); data_sync_reg3: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk, CE => '1', D => data_sync2, Q => data_sync3, R => '0' ); data_sync_reg4: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk, CE => '1', D => data_sync3, Q => data_sync4, R => '0' ); data_sync_reg5: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk, CE => '1', D => data_sync4, Q => data_sync5, R => '0' ); data_sync_reg6: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk, CE => '1', D => data_sync5, Q => data_out, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_3 is port ( data_out : out STD_LOGIC; status_vector : in STD_LOGIC_VECTOR ( 0 to 0 ); independent_clock_bufg : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_3 : entity is "gig_ethernet_pcs_pma_16_1_sync_block"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_3; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_3 is signal data_sync1 : STD_LOGIC; signal data_sync2 : STD_LOGIC; signal data_sync3 : STD_LOGIC; signal data_sync4 : STD_LOGIC; signal data_sync5 : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true; attribute SHREG_EXTRACT : string; attribute SHREG_EXTRACT of data_sync_reg1 : label is "no"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD"; attribute box_type : string; attribute box_type of data_sync_reg1 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg2 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD"; attribute box_type of data_sync_reg2 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg3 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD"; attribute box_type of data_sync_reg3 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg4 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD"; attribute box_type of data_sync_reg4 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg5 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD"; attribute box_type of data_sync_reg5 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg6 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD"; attribute box_type of data_sync_reg6 : label is "PRIMITIVE"; begin data_sync_reg1: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => status_vector(0), Q => data_sync1, R => '0' ); data_sync_reg2: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync1, Q => data_sync2, R => '0' ); data_sync_reg3: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync2, Q => data_sync3, R => '0' ); data_sync_reg4: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync3, Q => data_sync4, R => '0' ); data_sync_reg5: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync4, Q => data_sync5, R => '0' ); data_sync_reg6: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync5, Q => data_out, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_4 is port ( data_out : out STD_LOGIC; data_sync_reg1_0 : in STD_LOGIC; independent_clock_bufg : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_4 : entity is "gig_ethernet_pcs_pma_16_1_sync_block"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_4; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_4 is signal data_sync1 : STD_LOGIC; signal data_sync2 : STD_LOGIC; signal data_sync3 : STD_LOGIC; signal data_sync4 : STD_LOGIC; signal data_sync5 : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true; attribute SHREG_EXTRACT : string; attribute SHREG_EXTRACT of data_sync_reg1 : label is "no"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD"; attribute box_type : string; attribute box_type of data_sync_reg1 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg2 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD"; attribute box_type of data_sync_reg2 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg3 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD"; attribute box_type of data_sync_reg3 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg4 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD"; attribute box_type of data_sync_reg4 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg5 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD"; attribute box_type of data_sync_reg5 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg6 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD"; attribute box_type of data_sync_reg6 : label is "PRIMITIVE"; begin data_sync_reg1: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync_reg1_0, Q => data_sync1, R => '0' ); data_sync_reg2: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync1, Q => data_sync2, R => '0' ); data_sync_reg3: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync2, Q => data_sync3, R => '0' ); data_sync_reg4: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync3, Q => data_sync4, R => '0' ); data_sync_reg5: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync4, Q => data_sync5, R => '0' ); data_sync_reg6: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync5, Q => data_out, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_5 is port ( E : out STD_LOGIC_VECTOR ( 0 to 0 ); reset_time_out_reg : out STD_LOGIC; \FSM_sequential_tx_state_reg[0]\ : in STD_LOGIC; \FSM_sequential_tx_state_reg[0]_0\ : in STD_LOGIC; \FSM_sequential_tx_state_reg[0]_1\ : in STD_LOGIC; \FSM_sequential_tx_state_reg[0]_2\ : in STD_LOGIC; \FSM_sequential_tx_state_reg[0]_3\ : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 3 downto 0 ); reset_time_out_reg_0 : in STD_LOGIC; mmcm_lock_reclocked : in STD_LOGIC; \FSM_sequential_tx_state_reg[0]_4\ : in STD_LOGIC; \FSM_sequential_tx_state_reg[0]_5\ : in STD_LOGIC; \FSM_sequential_tx_state_reg[0]_6\ : in STD_LOGIC; reset_time_out_reg_1 : in STD_LOGIC; reset_time_out : in STD_LOGIC; cplllock : in STD_LOGIC; independent_clock_bufg : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_5 : entity is "gig_ethernet_pcs_pma_16_1_sync_block"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_5; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_5 is signal \FSM_sequential_tx_state[3]_i_5_n_0\ : STD_LOGIC; signal cplllock_sync : STD_LOGIC; signal data_sync1 : STD_LOGIC; signal data_sync2 : STD_LOGIC; signal data_sync3 : STD_LOGIC; signal data_sync4 : STD_LOGIC; signal data_sync5 : STD_LOGIC; signal \reset_time_out_i_3__0_n_0\ : STD_LOGIC; signal \reset_time_out_i_4__0_n_0\ : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true; attribute SHREG_EXTRACT : string; attribute SHREG_EXTRACT of data_sync_reg1 : label is "no"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD"; attribute box_type : string; attribute box_type of data_sync_reg1 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg2 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD"; attribute box_type of data_sync_reg2 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg3 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD"; attribute box_type of data_sync_reg3 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg4 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD"; attribute box_type of data_sync_reg4 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg5 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD"; attribute box_type of data_sync_reg5 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg6 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD"; attribute box_type of data_sync_reg6 : label is "PRIMITIVE"; begin \FSM_sequential_tx_state[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFEFFFEFFFE" ) port map ( I0 => \FSM_sequential_tx_state_reg[0]\, I1 => \FSM_sequential_tx_state_reg[0]_0\, I2 => \FSM_sequential_tx_state[3]_i_5_n_0\, I3 => \FSM_sequential_tx_state_reg[0]_1\, I4 => \FSM_sequential_tx_state_reg[0]_2\, I5 => \FSM_sequential_tx_state_reg[0]_3\, O => E(0) ); \FSM_sequential_tx_state[3]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000F00008" ) port map ( I0 => \FSM_sequential_tx_state_reg[0]_4\, I1 => \FSM_sequential_tx_state_reg[0]_5\, I2 => cplllock_sync, I3 => Q(2), I4 => Q(1), I5 => \FSM_sequential_tx_state_reg[0]_6\, O => \FSM_sequential_tx_state[3]_i_5_n_0\ ); data_sync_reg1: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => cplllock, Q => data_sync1, R => '0' ); data_sync_reg2: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync1, Q => data_sync2, R => '0' ); data_sync_reg3: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync2, Q => data_sync3, R => '0' ); data_sync_reg4: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync3, Q => data_sync4, R => '0' ); data_sync_reg5: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync4, Q => data_sync5, R => '0' ); data_sync_reg6: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync5, Q => cplllock_sync, R => '0' ); reset_time_out_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"EFE0" ) port map ( I0 => reset_time_out_reg_1, I1 => \reset_time_out_i_3__0_n_0\, I2 => \reset_time_out_i_4__0_n_0\, I3 => reset_time_out, O => reset_time_out_reg ); \reset_time_out_i_3__0\: unisim.vcomponents.LUT6 generic map( INIT => X"020002000F000200" ) port map ( I0 => cplllock_sync, I1 => Q(2), I2 => Q(3), I3 => Q(0), I4 => mmcm_lock_reclocked, I5 => Q(1), O => \reset_time_out_i_3__0_n_0\ ); \reset_time_out_i_4__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0505FF040505F504" ) port map ( I0 => Q(1), I1 => reset_time_out_reg_0, I2 => Q(2), I3 => Q(0), I4 => Q(3), I5 => cplllock_sync, O => \reset_time_out_i_4__0_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_6 is port ( SR : out STD_LOGIC_VECTOR ( 0 to 0 ); mmcm_lock_reclocked_reg : out STD_LOGIC; mmcm_lock_reclocked : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); mmcm_lock_reclocked_reg_0 : in STD_LOGIC; mmcm_locked : in STD_LOGIC; independent_clock_bufg : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_6 : entity is "gig_ethernet_pcs_pma_16_1_sync_block"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_6; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_6 is signal data_sync1 : STD_LOGIC; signal data_sync2 : STD_LOGIC; signal data_sync3 : STD_LOGIC; signal data_sync4 : STD_LOGIC; signal data_sync5 : STD_LOGIC; signal mmcm_lock_i : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true; attribute SHREG_EXTRACT : string; attribute SHREG_EXTRACT of data_sync_reg1 : label is "no"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD"; attribute box_type : string; attribute box_type of data_sync_reg1 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg2 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD"; attribute box_type of data_sync_reg2 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg3 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD"; attribute box_type of data_sync_reg3 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg4 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD"; attribute box_type of data_sync_reg4 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg5 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD"; attribute box_type of data_sync_reg5 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg6 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD"; attribute box_type of data_sync_reg6 : label is "PRIMITIVE"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \mmcm_lock_count[7]_i_1\ : label is "soft_lutpair58"; attribute SOFT_HLUTNM of mmcm_lock_reclocked_i_1 : label is "soft_lutpair58"; begin data_sync_reg1: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => mmcm_locked, Q => data_sync1, R => '0' ); data_sync_reg2: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync1, Q => data_sync2, R => '0' ); data_sync_reg3: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync2, Q => data_sync3, R => '0' ); data_sync_reg4: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync3, Q => data_sync4, R => '0' ); data_sync_reg5: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync4, Q => data_sync5, R => '0' ); data_sync_reg6: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync5, Q => mmcm_lock_i, R => '0' ); \mmcm_lock_count[7]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => mmcm_lock_i, O => SR(0) ); mmcm_lock_reclocked_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"AAEA0000" ) port map ( I0 => mmcm_lock_reclocked, I1 => Q(1), I2 => Q(0), I3 => mmcm_lock_reclocked_reg_0, I4 => mmcm_lock_i, O => mmcm_lock_reclocked_reg ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_7 is port ( data_out : out STD_LOGIC; data_in : in STD_LOGIC; userclk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_7 : entity is "gig_ethernet_pcs_pma_16_1_sync_block"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_7; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_7 is signal data_sync1 : STD_LOGIC; signal data_sync2 : STD_LOGIC; signal data_sync3 : STD_LOGIC; signal data_sync4 : STD_LOGIC; signal data_sync5 : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true; attribute SHREG_EXTRACT : string; attribute SHREG_EXTRACT of data_sync_reg1 : label is "no"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD"; attribute box_type : string; attribute box_type of data_sync_reg1 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg2 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD"; attribute box_type of data_sync_reg2 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg3 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD"; attribute box_type of data_sync_reg3 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg4 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD"; attribute box_type of data_sync_reg4 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg5 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD"; attribute box_type of data_sync_reg5 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg6 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD"; attribute box_type of data_sync_reg6 : label is "PRIMITIVE"; begin data_sync_reg1: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk, CE => '1', D => data_in, Q => data_sync1, R => '0' ); data_sync_reg2: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk, CE => '1', D => data_sync1, Q => data_sync2, R => '0' ); data_sync_reg3: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk, CE => '1', D => data_sync2, Q => data_sync3, R => '0' ); data_sync_reg4: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk, CE => '1', D => data_sync3, Q => data_sync4, R => '0' ); data_sync_reg5: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk, CE => '1', D => data_sync4, Q => data_sync5, R => '0' ); data_sync_reg6: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk, CE => '1', D => data_sync5, Q => data_out, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_8 is port ( data_out : out STD_LOGIC; data_in : in STD_LOGIC; independent_clock_bufg : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_8 : entity is "gig_ethernet_pcs_pma_16_1_sync_block"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_8; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_8 is signal data_sync1 : STD_LOGIC; signal data_sync2 : STD_LOGIC; signal data_sync3 : STD_LOGIC; signal data_sync4 : STD_LOGIC; signal data_sync5 : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true; attribute SHREG_EXTRACT : string; attribute SHREG_EXTRACT of data_sync_reg1 : label is "no"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD"; attribute box_type : string; attribute box_type of data_sync_reg1 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg2 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD"; attribute box_type of data_sync_reg2 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg3 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD"; attribute box_type of data_sync_reg3 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg4 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD"; attribute box_type of data_sync_reg4 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg5 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD"; attribute box_type of data_sync_reg5 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg6 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD"; attribute box_type of data_sync_reg6 : label is "PRIMITIVE"; begin data_sync_reg1: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_in, Q => data_sync1, R => '0' ); data_sync_reg2: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync1, Q => data_sync2, R => '0' ); data_sync_reg3: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync2, Q => data_sync3, R => '0' ); data_sync_reg4: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync3, Q => data_sync4, R => '0' ); data_sync_reg5: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync4, Q => data_sync5, R => '0' ); data_sync_reg6: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => data_sync5, Q => data_out, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_9 is port ( data_out : out STD_LOGIC; data_in : in STD_LOGIC; userclk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_9 : entity is "gig_ethernet_pcs_pma_16_1_sync_block"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_9; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_9 is signal data_sync1 : STD_LOGIC; signal data_sync2 : STD_LOGIC; signal data_sync3 : STD_LOGIC; signal data_sync4 : STD_LOGIC; signal data_sync5 : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true; attribute SHREG_EXTRACT : string; attribute SHREG_EXTRACT of data_sync_reg1 : label is "no"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD"; attribute box_type : string; attribute box_type of data_sync_reg1 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg2 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD"; attribute box_type of data_sync_reg2 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg3 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD"; attribute box_type of data_sync_reg3 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg4 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD"; attribute box_type of data_sync_reg4 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg5 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD"; attribute box_type of data_sync_reg5 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg6 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD"; attribute box_type of data_sync_reg6 : label is "PRIMITIVE"; begin data_sync_reg1: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk, CE => '1', D => data_in, Q => data_sync1, R => '0' ); data_sync_reg2: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk, CE => '1', D => data_sync1, Q => data_sync2, R => '0' ); data_sync_reg3: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk, CE => '1', D => data_sync2, Q => data_sync3, R => '0' ); data_sync_reg4: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk, CE => '1', D => data_sync3, Q => data_sync4, R => '0' ); data_sync_reg5: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk, CE => '1', D => data_sync4, Q => data_sync5, R => '0' ); data_sync_reg6: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk, CE => '1', D => data_sync5, Q => data_out, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_RX is port ( S2 : out STD_LOGIC; gmii_rx_er : out STD_LOGIC; status_vector : out STD_LOGIC_VECTOR ( 2 downto 0 ); gmii_rx_dv : out STD_LOGIC; \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCHARISK_INT_reg\ : out STD_LOGIC; FALSE_NIT_reg_0 : out STD_LOGIC; gmii_rxd : out STD_LOGIC_VECTOR ( 7 downto 0 ); Q : in STD_LOGIC_VECTOR ( 7 downto 0 ); userclk2 : in STD_LOGIC; RUDI_I_reg_0 : in STD_LOGIC; I0 : in STD_LOGIC; SYNC_STATUS_REG0 : in STD_LOGIC; RXCHARISK_REG1_reg_0 : in STD_LOGIC; RXSYNC_STATUS : in STD_LOGIC; RXNOTINTABLE_INT : in STD_LOGIC; D : in STD_LOGIC; CGBAD_reg_0 : in STD_LOGIC; RXEVEN0_out : in STD_LOGIC; SR : in STD_LOGIC_VECTOR ( 0 to 0 ); RX_ER_reg_0 : in STD_LOGIC; C_HDR_REMOVED_REG_reg_0 : in STD_LOGIC_VECTOR ( 1 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_RX; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_RX is signal C : STD_LOGIC; signal C0 : STD_LOGIC; signal CGBAD : STD_LOGIC; signal CGBAD_REG1 : STD_LOGIC; signal CGBAD_REG2 : STD_LOGIC; signal CGBAD_REG3 : STD_LOGIC; signal C_HDR_REMOVED : STD_LOGIC; signal C_HDR_REMOVED_REG : STD_LOGIC; signal C_REG1 : STD_LOGIC; signal C_REG2 : STD_LOGIC; signal C_REG3 : STD_LOGIC; signal D0p0 : STD_LOGIC; signal D0p0_REG : STD_LOGIC; signal D0p0_REG_i_2_n_0 : STD_LOGIC; signal EOP : STD_LOGIC; signal EOP0 : STD_LOGIC; signal EOP_REG1 : STD_LOGIC; signal EOP_REG10 : STD_LOGIC; signal EOP_i_2_n_0 : STD_LOGIC; signal EXTEND : STD_LOGIC; signal EXTEND_ERR : STD_LOGIC; signal EXTEND_ERR0 : STD_LOGIC; signal EXTEND_REG1 : STD_LOGIC; signal EXTEND_REG2 : STD_LOGIC; signal EXTEND_REG3 : STD_LOGIC; signal EXTEND_i_1_n_0 : STD_LOGIC; signal EXT_ILLEGAL_K : STD_LOGIC; signal EXT_ILLEGAL_K0 : STD_LOGIC; signal EXT_ILLEGAL_K_REG1 : STD_LOGIC; signal EXT_ILLEGAL_K_REG2 : STD_LOGIC; signal FALSE_CARRIER : STD_LOGIC; signal FALSE_CARRIER0 : STD_LOGIC; signal FALSE_CARRIER_REG1 : STD_LOGIC; signal FALSE_CARRIER_REG2 : STD_LOGIC; signal FALSE_CARRIER_REG3 : STD_LOGIC; signal FALSE_CARRIER_i_1_n_0 : STD_LOGIC; signal FALSE_CARRIER_i_3_n_0 : STD_LOGIC; signal FALSE_DATA : STD_LOGIC; signal FALSE_DATA0 : STD_LOGIC; signal FALSE_DATA_i_2_n_0 : STD_LOGIC; signal FALSE_DATA_i_3_n_0 : STD_LOGIC; signal FALSE_DATA_i_4_n_0 : STD_LOGIC; signal FALSE_DATA_i_5_n_0 : STD_LOGIC; signal FALSE_DATA_i_6_n_0 : STD_LOGIC; signal FALSE_K : STD_LOGIC; signal FALSE_K0 : STD_LOGIC; signal FALSE_K_i_2_n_0 : STD_LOGIC; signal FALSE_K_i_3_n_0 : STD_LOGIC; signal FALSE_NIT : STD_LOGIC; signal FALSE_NIT0 : STD_LOGIC; signal FALSE_NIT_i_2_n_0 : STD_LOGIC; signal FALSE_NIT_i_3_n_0 : STD_LOGIC; signal FROM_RX_CX : STD_LOGIC; signal FROM_RX_CX0 : STD_LOGIC; signal I : STD_LOGIC; signal \IDLE_REG_reg_n_0_[0]\ : STD_LOGIC; signal \IDLE_REG_reg_n_0_[2]\ : STD_LOGIC; signal ILLEGAL_K : STD_LOGIC; signal ILLEGAL_K0 : STD_LOGIC; signal ILLEGAL_K_REG1 : STD_LOGIC; signal ILLEGAL_K_REG2 : STD_LOGIC; signal I_REG_reg_n_0 : STD_LOGIC; signal I_i_4_n_0 : STD_LOGIC; signal I_i_5_n_0 : STD_LOGIC; signal I_i_6_n_0 : STD_LOGIC; signal I_i_7_n_0 : STD_LOGIC; signal K23p7 : STD_LOGIC; signal K28p5 : STD_LOGIC; signal K28p5_REG1 : STD_LOGIC; signal K29p7 : STD_LOGIC; signal R : STD_LOGIC; signal RECEIVE : STD_LOGIC; signal RECEIVE_i_1_n_0 : STD_LOGIC; signal \RUDI_C0__0\ : STD_LOGIC; signal RUDI_I0 : STD_LOGIC; signal RXCHARISK_REG1 : STD_LOGIC; signal RXDATA_REG5 : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \RXD[0]_i_1_n_0\ : STD_LOGIC; signal \RXD[1]_i_1_n_0\ : STD_LOGIC; signal \RXD[2]_i_1_n_0\ : STD_LOGIC; signal \RXD[3]_i_1_n_0\ : STD_LOGIC; signal \RXD[4]_i_1_n_0\ : STD_LOGIC; signal \RXD[5]_i_1_n_0\ : STD_LOGIC; signal \RXD[6]_i_1_n_0\ : STD_LOGIC; signal \RXD[7]_i_1_n_0\ : STD_LOGIC; signal RX_CONFIG_VALID_INT : STD_LOGIC; signal RX_CONFIG_VALID_INT0 : STD_LOGIC; signal RX_CONFIG_VALID_INT_i_2_n_0 : STD_LOGIC; signal \RX_CONFIG_VALID_REG_reg_n_0_[0]\ : STD_LOGIC; signal \RX_CONFIG_VALID_REG_reg_n_0_[3]\ : STD_LOGIC; signal RX_DATA_ERROR : STD_LOGIC; signal RX_DATA_ERROR0 : STD_LOGIC; signal RX_DATA_ERROR_i_2_n_0 : STD_LOGIC; signal RX_DATA_ERROR_i_3_n_0 : STD_LOGIC; signal RX_DATA_ERROR_i_4_n_0 : STD_LOGIC; signal RX_DV0 : STD_LOGIC; signal RX_DV_i_1_n_0 : STD_LOGIC; signal RX_ER0 : STD_LOGIC; signal RX_ER_i_2_n_0 : STD_LOGIC; signal RX_INVALID_i_2_n_0 : STD_LOGIC; signal R_REG1 : STD_LOGIC; signal R_i_2_n_0 : STD_LOGIC; signal S : STD_LOGIC; signal S0 : STD_LOGIC; signal \^s2\ : STD_LOGIC; signal SOP : STD_LOGIC; signal SOP0 : STD_LOGIC; signal SOP_REG1 : STD_LOGIC; signal SOP_REG2 : STD_LOGIC; signal SOP_REG3 : STD_LOGIC; signal SYNC_STATUS_REG : STD_LOGIC; signal T : STD_LOGIC; signal T_REG1 : STD_LOGIC; signal T_REG2 : STD_LOGIC; signal \^use_rocket_io.no_1588.reclock_mgt_signals_txoutclk.rxcharisk_int_reg\ : STD_LOGIC; signal WAIT_FOR_K : STD_LOGIC; signal WAIT_FOR_K_i_1_n_0 : STD_LOGIC; signal \^gmii_rx_dv\ : STD_LOGIC; signal p_0_in1_in : STD_LOGIC; signal p_0_in2_in : STD_LOGIC; signal p_1_in : STD_LOGIC; signal \^status_vector\ : STD_LOGIC_VECTOR ( 2 downto 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of D0p0_REG_i_1 : label is "soft_lutpair34"; attribute SOFT_HLUTNM of EXT_ILLEGAL_K_i_1 : label is "soft_lutpair26"; attribute SOFT_HLUTNM of FALSE_DATA_i_4 : label is "soft_lutpair24"; attribute SOFT_HLUTNM of FALSE_DATA_i_5 : label is "soft_lutpair28"; attribute SOFT_HLUTNM of FALSE_DATA_i_6 : label is "soft_lutpair36"; attribute SOFT_HLUTNM of FALSE_K_i_1 : label is "soft_lutpair32"; attribute SOFT_HLUTNM of FALSE_K_i_3 : label is "soft_lutpair36"; attribute SOFT_HLUTNM of FALSE_NIT_i_1 : label is "soft_lutpair32"; attribute SOFT_HLUTNM of ILLEGAL_K_i_1 : label is "soft_lutpair35"; attribute SOFT_HLUTNM of I_i_4 : label is "soft_lutpair33"; attribute SOFT_HLUTNM of I_i_5 : label is "soft_lutpair24"; attribute SOFT_HLUTNM of I_i_6 : label is "soft_lutpair34"; attribute SOFT_HLUTNM of I_i_7 : label is "soft_lutpair33"; attribute srl_bus_name : string; attribute srl_bus_name of \RXDATA_REG5_reg[0]_srl5\ : label is "U0/gig_ethernet_pcs_pma_16_1_core/\gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg "; attribute srl_name : string; attribute srl_name of \RXDATA_REG5_reg[0]_srl5\ : label is "U0/gig_ethernet_pcs_pma_16_1_core/\gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg[0]_srl5 "; attribute srl_bus_name of \RXDATA_REG5_reg[1]_srl5\ : label is "U0/gig_ethernet_pcs_pma_16_1_core/\gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg "; attribute srl_name of \RXDATA_REG5_reg[1]_srl5\ : label is "U0/gig_ethernet_pcs_pma_16_1_core/\gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg[1]_srl5 "; attribute srl_bus_name of \RXDATA_REG5_reg[2]_srl5\ : label is "U0/gig_ethernet_pcs_pma_16_1_core/\gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg "; attribute srl_name of \RXDATA_REG5_reg[2]_srl5\ : label is "U0/gig_ethernet_pcs_pma_16_1_core/\gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg[2]_srl5 "; attribute srl_bus_name of \RXDATA_REG5_reg[3]_srl5\ : label is "U0/gig_ethernet_pcs_pma_16_1_core/\gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg "; attribute srl_name of \RXDATA_REG5_reg[3]_srl5\ : label is "U0/gig_ethernet_pcs_pma_16_1_core/\gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg[3]_srl5 "; attribute srl_bus_name of \RXDATA_REG5_reg[4]_srl5\ : label is "U0/gig_ethernet_pcs_pma_16_1_core/\gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg "; attribute srl_name of \RXDATA_REG5_reg[4]_srl5\ : label is "U0/gig_ethernet_pcs_pma_16_1_core/\gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg[4]_srl5 "; attribute srl_bus_name of \RXDATA_REG5_reg[5]_srl5\ : label is "U0/gig_ethernet_pcs_pma_16_1_core/\gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg "; attribute srl_name of \RXDATA_REG5_reg[5]_srl5\ : label is "U0/gig_ethernet_pcs_pma_16_1_core/\gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg[5]_srl5 "; attribute srl_bus_name of \RXDATA_REG5_reg[6]_srl5\ : label is "U0/gig_ethernet_pcs_pma_16_1_core/\gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg "; attribute srl_name of \RXDATA_REG5_reg[6]_srl5\ : label is "U0/gig_ethernet_pcs_pma_16_1_core/\gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg[6]_srl5 "; attribute srl_bus_name of \RXDATA_REG5_reg[7]_srl5\ : label is "U0/gig_ethernet_pcs_pma_16_1_core/\gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg "; attribute srl_name of \RXDATA_REG5_reg[7]_srl5\ : label is "U0/gig_ethernet_pcs_pma_16_1_core/\gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg[7]_srl5 "; attribute SOFT_HLUTNM of \RXD[0]_i_1\ : label is "soft_lutpair30"; attribute SOFT_HLUTNM of \RXD[1]_i_1\ : label is "soft_lutpair29"; attribute SOFT_HLUTNM of \RXD[3]_i_1\ : label is "soft_lutpair30"; attribute SOFT_HLUTNM of \RXD[4]_i_1\ : label is "soft_lutpair25"; attribute SOFT_HLUTNM of \RXD[5]_i_1\ : label is "soft_lutpair31"; attribute SOFT_HLUTNM of \RXD[6]_i_1\ : label is "soft_lutpair31"; attribute SOFT_HLUTNM of \RXD[7]_i_1\ : label is "soft_lutpair29"; attribute SOFT_HLUTNM of RX_CONFIG_VALID_INT_i_2 : label is "soft_lutpair35"; attribute SOFT_HLUTNM of RX_DATA_ERROR_i_3 : label is "soft_lutpair26"; attribute SOFT_HLUTNM of RX_ER_i_2 : label is "soft_lutpair25"; attribute SOFT_HLUTNM of R_i_1 : label is "soft_lutpair27"; attribute SOFT_HLUTNM of R_i_2 : label is "soft_lutpair28"; attribute SOFT_HLUTNM of \T_i_1__0\ : label is "soft_lutpair27"; begin S2 <= \^s2\; \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCHARISK_INT_reg\ <= \^use_rocket_io.no_1588.reclock_mgt_signals_txoutclk.rxcharisk_int_reg\; gmii_rx_dv <= \^gmii_rx_dv\; status_vector(2 downto 0) <= \^status_vector\(2 downto 0); CGBAD_REG1_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => CGBAD, Q => CGBAD_REG1, R => '0' ); CGBAD_REG2_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => CGBAD_REG1, Q => CGBAD_REG2, R => '0' ); CGBAD_REG3_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => CGBAD_REG2, Q => CGBAD_REG3, R => RUDI_I_reg_0 ); CGBAD_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"FE" ) port map ( I0 => RXNOTINTABLE_INT, I1 => D, I2 => CGBAD_reg_0, O => \^s2\ ); CGBAD_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \^s2\, Q => CGBAD, R => RUDI_I_reg_0 ); C_HDR_REMOVED_REG_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"08" ) port map ( I0 => C_HDR_REMOVED_REG_reg_0(0), I1 => C_REG2, I2 => C_HDR_REMOVED_REG_reg_0(1), O => C_HDR_REMOVED ); C_HDR_REMOVED_REG_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => C_HDR_REMOVED, Q => C_HDR_REMOVED_REG, R => '0' ); C_REG1_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => C, Q => C_REG1, R => '0' ); C_REG2_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => C_REG1, Q => C_REG2, R => '0' ); C_REG3_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => C_REG2, Q => C_REG3, R => '0' ); C_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => K28p5_REG1, I1 => \^use_rocket_io.no_1588.reclock_mgt_signals_txoutclk.rxcharisk_int_reg\, O => C0 ); C_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => C0, Q => C, R => '0' ); D0p0_REG_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"0002" ) port map ( I0 => D0p0_REG_i_2_n_0, I1 => Q(0), I2 => Q(1), I3 => Q(7), O => D0p0 ); D0p0_REG_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000001" ) port map ( I0 => Q(4), I1 => Q(2), I2 => Q(3), I3 => RXCHARISK_REG1_reg_0, I4 => Q(6), I5 => Q(5), O => D0p0_REG_i_2_n_0 ); D0p0_REG_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => D0p0, Q => D0p0_REG, R => '0' ); EOP_REG1_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"EA" ) port map ( I0 => EOP, I1 => EXTEND, I2 => EXTEND_REG1, O => EOP_REG10 ); EOP_REG1_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => EOP_REG10, Q => EOP_REG1, R => RUDI_I_reg_0 ); EOP_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF88888000" ) port map ( I0 => T_REG2, I1 => R_REG1, I2 => K28p5_REG1, I3 => RXEVEN0_out, I4 => R, I5 => EOP_i_2_n_0, O => EOP0 ); EOP_i_2: unisim.vcomponents.LUT5 generic map( INIT => X"F8888888" ) port map ( I0 => I_REG_reg_n_0, I1 => K28p5_REG1, I2 => C_REG1, I3 => D0p0_REG, I4 => RXEVEN0_out, O => EOP_i_2_n_0 ); EOP_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => EOP0, Q => EOP, R => RUDI_I_reg_0 ); EXTEND_ERR_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"EA" ) port map ( I0 => EXT_ILLEGAL_K_REG2, I1 => CGBAD_REG3, I2 => EXTEND_REG3, O => EXTEND_ERR0 ); EXTEND_ERR_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => EXTEND_ERR0, Q => EXTEND_ERR, R => SYNC_STATUS_REG0 ); EXTEND_REG1_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => EXTEND, Q => EXTEND_REG1, R => '0' ); EXTEND_REG2_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => EXTEND_REG1, Q => EXTEND_REG2, R => '0' ); EXTEND_REG3_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => EXTEND_REG2, Q => EXTEND_REG3, R => '0' ); EXTEND_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"808080FF80808080" ) port map ( I0 => R_REG1, I1 => R, I2 => RECEIVE, I3 => RX_DATA_ERROR_i_3_n_0, I4 => S, I5 => EXTEND, O => EXTEND_i_1_n_0 ); EXTEND_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => EXTEND_i_1_n_0, Q => EXTEND, R => SYNC_STATUS_REG0 ); EXT_ILLEGAL_K_REG1_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => EXT_ILLEGAL_K, Q => EXT_ILLEGAL_K_REG1, R => SYNC_STATUS_REG0 ); EXT_ILLEGAL_K_REG2_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => EXT_ILLEGAL_K_REG1, Q => EXT_ILLEGAL_K_REG2, R => SYNC_STATUS_REG0 ); EXT_ILLEGAL_K_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"00000700" ) port map ( I0 => K28p5_REG1, I1 => RXEVEN0_out, I2 => S, I3 => EXTEND_REG1, I4 => R, O => EXT_ILLEGAL_K0 ); EXT_ILLEGAL_K_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => EXT_ILLEGAL_K0, Q => EXT_ILLEGAL_K, R => SYNC_STATUS_REG0 ); FALSE_CARRIER_REG1_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => FALSE_CARRIER, Q => FALSE_CARRIER_REG1, R => '0' ); FALSE_CARRIER_REG2_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => FALSE_CARRIER_REG1, Q => FALSE_CARRIER_REG2, R => '0' ); FALSE_CARRIER_REG3_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => FALSE_CARRIER_REG2, Q => FALSE_CARRIER_REG3, R => SYNC_STATUS_REG0 ); FALSE_CARRIER_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"F7F0" ) port map ( I0 => RXEVEN0_out, I1 => K28p5_REG1, I2 => FALSE_CARRIER0, I3 => FALSE_CARRIER, O => FALSE_CARRIER_i_1_n_0 ); FALSE_CARRIER_i_2: unisim.vcomponents.LUT5 generic map( INIT => X"00001000" ) port map ( I0 => K28p5_REG1, I1 => S, I2 => RXSYNC_STATUS, I3 => I_REG_reg_n_0, I4 => FALSE_CARRIER_i_3_n_0, O => FALSE_CARRIER0 ); FALSE_CARRIER_i_3: unisim.vcomponents.LUT3 generic map( INIT => X"FE" ) port map ( I0 => FALSE_NIT, I1 => FALSE_K, I2 => FALSE_DATA, O => FALSE_CARRIER_i_3_n_0 ); FALSE_CARRIER_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => FALSE_CARRIER_i_1_n_0, Q => FALSE_CARRIER, R => SYNC_STATUS_REG0 ); FALSE_DATA_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"000E" ) port map ( I0 => FALSE_DATA_i_2_n_0, I1 => FALSE_DATA_i_3_n_0, I2 => RXNOTINTABLE_INT, I3 => RXCHARISK_REG1_reg_0, O => FALSE_DATA0 ); FALSE_DATA_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000008000808080" ) port map ( I0 => FALSE_DATA_i_4_n_0, I1 => Q(1), I2 => Q(0), I3 => Q(3), I4 => Q(2), I5 => Q(4), O => FALSE_DATA_i_2_n_0 ); FALSE_DATA_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"0000004040000000" ) port map ( I0 => FALSE_DATA_i_5_n_0, I1 => Q(2), I2 => Q(7), I3 => Q(1), I4 => Q(0), I5 => FALSE_DATA_i_6_n_0, O => FALSE_DATA_i_3_n_0 ); FALSE_DATA_i_4: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) port map ( I0 => Q(7), I1 => Q(6), I2 => Q(5), O => FALSE_DATA_i_4_n_0 ); FALSE_DATA_i_5: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => Q(6), I1 => Q(5), O => FALSE_DATA_i_5_n_0 ); FALSE_DATA_i_6: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => Q(4), I1 => Q(3), O => FALSE_DATA_i_6_n_0 ); FALSE_DATA_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => FALSE_DATA0, Q => FALSE_DATA, R => RUDI_I_reg_0 ); FALSE_K_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"0009" ) port map ( I0 => Q(5), I1 => Q(6), I2 => RXNOTINTABLE_INT, I3 => FALSE_K_i_2_n_0, O => FALSE_K0 ); FALSE_K_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFF7F" ) port map ( I0 => RXCHARISK_REG1_reg_0, I1 => Q(4), I2 => Q(7), I3 => FALSE_K_i_3_n_0, I4 => Q(0), I5 => Q(1), O => FALSE_K_i_2_n_0 ); FALSE_K_i_3: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => Q(2), I1 => Q(3), O => FALSE_K_i_3_n_0 ); FALSE_K_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => FALSE_K0, Q => FALSE_K, R => RUDI_I_reg_0 ); FALSE_NIT_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => RXNOTINTABLE_INT, I1 => FALSE_NIT_i_2_n_0, O => FALSE_NIT0 ); FALSE_NIT_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"F55F5FFC5FFCFCCF" ) port map ( I0 => D0p0_REG_i_2_n_0, I1 => FALSE_NIT_i_3_n_0, I2 => Q(0), I3 => Q(1), I4 => Q(7), I5 => D, O => FALSE_NIT_i_2_n_0 ); FALSE_NIT_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFFFFFFFFFF" ) port map ( I0 => Q(3), I1 => Q(2), I2 => RXCHARISK_REG1_reg_0, I3 => Q(4), I4 => Q(6), I5 => Q(5), O => FALSE_NIT_i_3_n_0 ); FALSE_NIT_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => FALSE_NIT0, Q => FALSE_NIT, R => RUDI_I_reg_0 ); FROM_RX_CX_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFE0FFEEEEE0E0" ) port map ( I0 => C_REG1, I1 => C_REG2, I2 => RXCHARISK_REG1, I3 => RX_DATA_ERROR_i_3_n_0, I4 => CGBAD, I5 => C_REG3, O => FROM_RX_CX0 ); FROM_RX_CX_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => FROM_RX_CX0, Q => FROM_RX_CX, R => SYNC_STATUS_REG0 ); \IDLE_REG_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => I_REG_reg_n_0, Q => \IDLE_REG_reg_n_0_[0]\, R => RUDI_I_reg_0 ); \IDLE_REG_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \IDLE_REG_reg_n_0_[0]\, Q => p_0_in1_in, R => RUDI_I_reg_0 ); \IDLE_REG_reg[2]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => p_0_in1_in, Q => \IDLE_REG_reg_n_0_[2]\, R => RUDI_I_reg_0 ); ILLEGAL_K_REG1_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => ILLEGAL_K, Q => ILLEGAL_K_REG1, R => SYNC_STATUS_REG0 ); ILLEGAL_K_REG2_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => ILLEGAL_K_REG1, Q => ILLEGAL_K_REG2, R => SYNC_STATUS_REG0 ); ILLEGAL_K_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"0010" ) port map ( I0 => R, I1 => K28p5_REG1, I2 => RXCHARISK_REG1, I3 => T, O => ILLEGAL_K0 ); ILLEGAL_K_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => ILLEGAL_K0, Q => ILLEGAL_K, R => SYNC_STATUS_REG0 ); I_REG_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => I, Q => I_REG_reg_n_0, R => '0' ); I_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"FBFBFBFBFBFBFBAA" ) port map ( I0 => RXCHARISK_REG1_reg_0, I1 => I_i_4_n_0, I2 => I_i_5_n_0, I3 => I_i_6_n_0, I4 => FALSE_DATA_i_5_n_0, I5 => I_i_7_n_0, O => \^use_rocket_io.no_1588.reclock_mgt_signals_txoutclk.rxcharisk_int_reg\ ); I_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"0000000001FFFFFF" ) port map ( I0 => FALSE_NIT, I1 => FALSE_K, I2 => FALSE_DATA, I3 => RXSYNC_STATUS, I4 => I_REG_reg_n_0, I5 => K28p5_REG1, O => FALSE_NIT_reg_0 ); I_i_4: unisim.vcomponents.LUT3 generic map( INIT => X"01" ) port map ( I0 => Q(3), I1 => Q(2), I2 => Q(4), O => I_i_4_n_0 ); I_i_5: unisim.vcomponents.LUT5 generic map( INIT => X"FFFBFFFF" ) port map ( I0 => Q(5), I1 => Q(6), I2 => Q(7), I3 => Q(0), I4 => Q(1), O => I_i_5_n_0 ); I_i_6: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => Q(4), I1 => Q(7), O => I_i_6_n_0 ); I_i_7: unisim.vcomponents.LUT4 generic map( INIT => X"FFDF" ) port map ( I0 => Q(2), I1 => Q(3), I2 => Q(0), I3 => Q(1), O => I_i_7_n_0 ); I_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => I0, Q => I, R => '0' ); K28p5_REG1_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => Q(5), I1 => Q(6), I2 => FALSE_K_i_2_n_0, O => K28p5 ); K28p5_REG1_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => K28p5, Q => K28p5_REG1, R => '0' ); RECEIVE_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"DC" ) port map ( I0 => EOP, I1 => SOP_REG2, I2 => RECEIVE, O => RECEIVE_i_1_n_0 ); RECEIVE_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => RECEIVE_i_1_n_0, Q => RECEIVE, R => SYNC_STATUS_REG0 ); RUDI_C0: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => p_0_in2_in, I1 => \RX_CONFIG_VALID_REG_reg_n_0_[3]\, I2 => p_1_in, I3 => \RX_CONFIG_VALID_REG_reg_n_0_[0]\, O => \RUDI_C0__0\ ); RUDI_C_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \RUDI_C0__0\, Q => \^status_vector\(0), R => RUDI_I_reg_0 ); RUDI_I_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \IDLE_REG_reg_n_0_[2]\, I1 => p_0_in1_in, O => RUDI_I0 ); RUDI_I_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => RUDI_I0, Q => \^status_vector\(1), R => RUDI_I_reg_0 ); RXCHARISK_REG1_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => RXCHARISK_REG1_reg_0, Q => RXCHARISK_REG1, R => '0' ); \RXDATA_REG5_reg[0]_srl5\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '0', A2 => '1', A3 => '0', CE => '1', CLK => userclk2, D => Q(0), Q => RXDATA_REG5(0) ); \RXDATA_REG5_reg[1]_srl5\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '0', A2 => '1', A3 => '0', CE => '1', CLK => userclk2, D => Q(1), Q => RXDATA_REG5(1) ); \RXDATA_REG5_reg[2]_srl5\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '0', A2 => '1', A3 => '0', CE => '1', CLK => userclk2, D => Q(2), Q => RXDATA_REG5(2) ); \RXDATA_REG5_reg[3]_srl5\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '0', A2 => '1', A3 => '0', CE => '1', CLK => userclk2, D => Q(3), Q => RXDATA_REG5(3) ); \RXDATA_REG5_reg[4]_srl5\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '0', A2 => '1', A3 => '0', CE => '1', CLK => userclk2, D => Q(4), Q => RXDATA_REG5(4) ); \RXDATA_REG5_reg[5]_srl5\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '0', A2 => '1', A3 => '0', CE => '1', CLK => userclk2, D => Q(5), Q => RXDATA_REG5(5) ); \RXDATA_REG5_reg[6]_srl5\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '0', A2 => '1', A3 => '0', CE => '1', CLK => userclk2, D => Q(6), Q => RXDATA_REG5(6) ); \RXDATA_REG5_reg[7]_srl5\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '0', A2 => '1', A3 => '0', CE => '1', CLK => userclk2, D => Q(7), Q => RXDATA_REG5(7) ); \RXD[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"BBBA" ) port map ( I0 => SOP_REG3, I1 => FALSE_CARRIER_REG3, I2 => EXTEND_REG1, I3 => RXDATA_REG5(0), O => \RXD[0]_i_1_n_0\ ); \RXD[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"5554" ) port map ( I0 => SOP_REG3, I1 => FALSE_CARRIER_REG3, I2 => EXTEND_REG1, I3 => RXDATA_REG5(1), O => \RXD[1]_i_1_n_0\ ); \RXD[2]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => RXDATA_REG5(2), I1 => FALSE_CARRIER_REG3, I2 => EXTEND_REG1, I3 => SOP_REG3, O => \RXD[2]_i_1_n_0\ ); \RXD[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"5554" ) port map ( I0 => SOP_REG3, I1 => FALSE_CARRIER_REG3, I2 => EXTEND_REG1, I3 => RXDATA_REG5(3), O => \RXD[3]_i_1_n_0\ ); \RXD[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"BABBBAAA" ) port map ( I0 => SOP_REG3, I1 => FALSE_CARRIER_REG3, I2 => EXTEND_ERR, I3 => EXTEND_REG1, I4 => RXDATA_REG5(4), O => \RXD[4]_i_1_n_0\ ); \RXD[5]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0002" ) port map ( I0 => RXDATA_REG5(5), I1 => FALSE_CARRIER_REG3, I2 => EXTEND_REG1, I3 => SOP_REG3, O => \RXD[5]_i_1_n_0\ ); \RXD[6]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"ABAA" ) port map ( I0 => SOP_REG3, I1 => FALSE_CARRIER_REG3, I2 => EXTEND_REG1, I3 => RXDATA_REG5(6), O => \RXD[6]_i_1_n_0\ ); \RXD[7]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0002" ) port map ( I0 => RXDATA_REG5(7), I1 => FALSE_CARRIER_REG3, I2 => EXTEND_REG1, I3 => SOP_REG3, O => \RXD[7]_i_1_n_0\ ); \RXD_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \RXD[0]_i_1_n_0\, Q => gmii_rxd(0), R => SR(0) ); \RXD_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \RXD[1]_i_1_n_0\, Q => gmii_rxd(1), R => SR(0) ); \RXD_reg[2]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \RXD[2]_i_1_n_0\, Q => gmii_rxd(2), R => SR(0) ); \RXD_reg[3]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \RXD[3]_i_1_n_0\, Q => gmii_rxd(3), R => SR(0) ); \RXD_reg[4]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \RXD[4]_i_1_n_0\, Q => gmii_rxd(4), R => SR(0) ); \RXD_reg[5]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \RXD[5]_i_1_n_0\, Q => gmii_rxd(5), R => SR(0) ); \RXD_reg[6]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \RXD[6]_i_1_n_0\, Q => gmii_rxd(6), R => SR(0) ); \RXD_reg[7]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \RXD[7]_i_1_n_0\, Q => gmii_rxd(7), R => SR(0) ); RX_CONFIG_VALID_INT_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0010001000100000" ) port map ( I0 => \^s2\, I1 => RX_CONFIG_VALID_INT_i_2_n_0, I2 => RXSYNC_STATUS, I3 => RXCHARISK_REG1_reg_0, I4 => C_REG1, I5 => C_HDR_REMOVED_REG, O => RX_CONFIG_VALID_INT0 ); RX_CONFIG_VALID_INT_i_2: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => RXCHARISK_REG1, I1 => CGBAD, O => RX_CONFIG_VALID_INT_i_2_n_0 ); RX_CONFIG_VALID_INT_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => RX_CONFIG_VALID_INT0, Q => RX_CONFIG_VALID_INT, R => RUDI_I_reg_0 ); \RX_CONFIG_VALID_REG_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => RX_CONFIG_VALID_INT, Q => \RX_CONFIG_VALID_REG_reg_n_0_[0]\, R => RUDI_I_reg_0 ); \RX_CONFIG_VALID_REG_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \RX_CONFIG_VALID_REG_reg_n_0_[0]\, Q => p_0_in2_in, R => RUDI_I_reg_0 ); \RX_CONFIG_VALID_REG_reg[2]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => p_0_in2_in, Q => p_1_in, R => RUDI_I_reg_0 ); \RX_CONFIG_VALID_REG_reg[3]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => p_1_in, Q => \RX_CONFIG_VALID_REG_reg_n_0_[3]\, R => RUDI_I_reg_0 ); RX_DATA_ERROR_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"888AAAAA88888888" ) port map ( I0 => RECEIVE, I1 => RX_DATA_ERROR_i_2_n_0, I2 => R, I3 => RX_DATA_ERROR_i_3_n_0, I4 => R_REG1, I5 => T_REG2, O => RX_DATA_ERROR0 ); RX_DATA_ERROR_i_2: unisim.vcomponents.LUT5 generic map( INIT => X"FFFF4544" ) port map ( I0 => R_REG1, I1 => K28p5_REG1, I2 => T_REG1, I3 => R, I4 => RX_DATA_ERROR_i_4_n_0, O => RX_DATA_ERROR_i_2_n_0 ); RX_DATA_ERROR_i_3: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => K28p5_REG1, I1 => RXEVEN0_out, O => RX_DATA_ERROR_i_3_n_0 ); RX_DATA_ERROR_i_4: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => CGBAD_REG3, I1 => I_REG_reg_n_0, I2 => ILLEGAL_K_REG2, I3 => C_REG1, O => RX_DATA_ERROR_i_4_n_0 ); RX_DATA_ERROR_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => RX_DATA_ERROR0, Q => RX_DATA_ERROR, R => SYNC_STATUS_REG0 ); RX_DV_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"AAFEAAAA" ) port map ( I0 => RX_DV0, I1 => RXSYNC_STATUS, I2 => RECEIVE, I3 => EOP_REG1, I4 => \^gmii_rx_dv\, O => RX_DV_i_1_n_0 ); RX_DV_i_2: unisim.vcomponents.LUT4 generic map( INIT => X"1000" ) port map ( I0 => RX_ER_reg_0, I1 => SR(0), I2 => SOP_REG3, I3 => RXSYNC_STATUS, O => RX_DV0 ); RX_DV_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => RX_DV_i_1_n_0, Q => \^gmii_rx_dv\, R => RUDI_I_reg_0 ); RX_ER_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"000E000F000E0000" ) port map ( I0 => RX_DATA_ERROR, I1 => RX_ER_i_2_n_0, I2 => SR(0), I3 => RX_ER_reg_0, I4 => RXSYNC_STATUS, I5 => RECEIVE, O => RX_ER0 ); RX_ER_i_2: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => FALSE_CARRIER_REG3, I1 => EXTEND_REG1, O => RX_ER_i_2_n_0 ); RX_ER_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => RX_ER0, Q => gmii_rx_er, R => RUDI_I_reg_0 ); RX_INVALID_i_2: unisim.vcomponents.LUT3 generic map( INIT => X"DC" ) port map ( I0 => K28p5_REG1, I1 => FROM_RX_CX, I2 => \^status_vector\(2), O => RX_INVALID_i_2_n_0 ); RX_INVALID_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => RX_INVALID_i_2_n_0, Q => \^status_vector\(2), R => SYNC_STATUS_REG0 ); R_REG1_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => R, Q => R_REG1, R => '0' ); R_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"00800000" ) port map ( I0 => R_i_2_n_0, I1 => Q(0), I2 => Q(1), I3 => Q(3), I4 => Q(2), O => K23p7 ); R_i_2: unisim.vcomponents.LUT5 generic map( INIT => X"80000000" ) port map ( I0 => Q(5), I1 => Q(6), I2 => RXCHARISK_REG1_reg_0, I3 => Q(4), I4 => Q(7), O => R_i_2_n_0 ); R_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => K23p7, Q => R, R => '0' ); SOP_REG1_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => SOP, Q => SOP_REG1, R => '0' ); SOP_REG2_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => SOP_REG1, Q => SOP_REG2, R => '0' ); SOP_REG3_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => SOP_REG2, Q => SOP_REG3, R => '0' ); SOP_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"00E00000" ) port map ( I0 => EXTEND, I1 => I_REG_reg_n_0, I2 => S, I3 => WAIT_FOR_K, I4 => RXSYNC_STATUS, O => SOP0 ); SOP_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => SOP0, Q => SOP, R => RUDI_I_reg_0 ); SYNC_STATUS_REG_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => '1', Q => SYNC_STATUS_REG, R => SYNC_STATUS_REG0 ); S_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000008000" ) port map ( I0 => R_i_2_n_0, I1 => Q(1), I2 => Q(0), I3 => Q(3), I4 => Q(2), I5 => \^s2\, O => S0 ); S_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => S0, Q => S, R => '0' ); T_REG1_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => T, Q => T_REG1, R => '0' ); T_REG2_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => T_REG1, Q => T_REG2, R => '0' ); \T_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"00800000" ) port map ( I0 => R_i_2_n_0, I1 => Q(2), I2 => Q(3), I3 => Q(1), I4 => Q(0), O => K29p7 ); T_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => K29p7, Q => T, R => '0' ); WAIT_FOR_K_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"7F0F" ) port map ( I0 => RXEVEN0_out, I1 => K28p5_REG1, I2 => SYNC_STATUS_REG, I3 => WAIT_FOR_K, O => WAIT_FOR_K_i_1_n_0 ); WAIT_FOR_K_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => WAIT_FOR_K_i_1_n_0, Q => WAIT_FOR_K, R => SYNC_STATUS_REG0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SYNCHRONISE is port ( RXEVEN0_out : out STD_LOGIC; RXSYNC_STATUS : out STD_LOGIC; enablealign : out STD_LOGIC; SYNC_STATUS_REG0 : out STD_LOGIC; I0 : out STD_LOGIC; STATUS_VECTOR_0_PRE0 : out STD_LOGIC; SIGNAL_DETECT_MOD : in STD_LOGIC; userclk2 : in STD_LOGIC; EVEN_reg_0 : in STD_LOGIC; \FSM_onehot_STATE_reg[1]_0\ : in STD_LOGIC; CONFIGURATION_VECTOR_REG : in STD_LOGIC_VECTOR ( 0 to 0 ); \FSM_onehot_STATE_reg[2]_0\ : in STD_LOGIC; S2 : in STD_LOGIC; RXNOTINTABLE_INT : in STD_LOGIC; D : in STD_LOGIC; \FSM_onehot_STATE_reg[0]_0\ : in STD_LOGIC; I_reg : in STD_LOGIC; I_reg_0 : in STD_LOGIC; reset_done : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SYNCHRONISE; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SYNCHRONISE is signal ENCOMMAALIGN_i_1_n_0 : STD_LOGIC; signal ENCOMMAALIGN_i_2_n_0 : STD_LOGIC; signal EVEN_i_1_n_0 : STD_LOGIC; signal \FSM_onehot_STATE[0]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_STATE[10]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_STATE[11]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_STATE[12]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_STATE[12]_i_2_n_0\ : STD_LOGIC; signal \FSM_onehot_STATE[12]_i_3_n_0\ : STD_LOGIC; signal \FSM_onehot_STATE[1]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_STATE[2]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_STATE[2]_i_2_n_0\ : STD_LOGIC; signal \FSM_onehot_STATE[2]_i_3_n_0\ : STD_LOGIC; signal \FSM_onehot_STATE[3]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_STATE[4]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_STATE[5]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_STATE[6]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_STATE[7]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_STATE[8]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_STATE[9]_i_1_n_0\ : STD_LOGIC; signal \FSM_onehot_STATE_reg_n_0_[0]\ : STD_LOGIC; signal \FSM_onehot_STATE_reg_n_0_[10]\ : STD_LOGIC; signal \FSM_onehot_STATE_reg_n_0_[11]\ : STD_LOGIC; signal \FSM_onehot_STATE_reg_n_0_[12]\ : STD_LOGIC; signal \FSM_onehot_STATE_reg_n_0_[1]\ : STD_LOGIC; signal \FSM_onehot_STATE_reg_n_0_[2]\ : STD_LOGIC; signal \FSM_onehot_STATE_reg_n_0_[4]\ : STD_LOGIC; signal \FSM_onehot_STATE_reg_n_0_[5]\ : STD_LOGIC; signal \FSM_onehot_STATE_reg_n_0_[6]\ : STD_LOGIC; signal \FSM_onehot_STATE_reg_n_0_[8]\ : STD_LOGIC; signal \FSM_onehot_STATE_reg_n_0_[9]\ : STD_LOGIC; signal GOOD_CGS : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \GOOD_CGS[0]_i_1_n_0\ : STD_LOGIC; signal \GOOD_CGS[1]_i_1_n_0\ : STD_LOGIC; signal \GOOD_CGS[1]_i_2_n_0\ : STD_LOGIC; signal \^rxeven0_out\ : STD_LOGIC; signal \^rxsync_status\ : STD_LOGIC; signal SIGNAL_DETECT_REG : STD_LOGIC; signal SYNC_STATUS0 : STD_LOGIC; signal SYNC_STATUS_i_1_n_0 : STD_LOGIC; signal \^enablealign\ : STD_LOGIC; signal p_0_in : STD_LOGIC; signal p_1_in : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of EVEN_i_1 : label is "soft_lutpair41"; attribute SOFT_HLUTNM of \FSM_onehot_STATE[11]_i_1\ : label is "soft_lutpair37"; attribute SOFT_HLUTNM of \FSM_onehot_STATE[12]_i_3\ : label is "soft_lutpair37"; attribute SOFT_HLUTNM of \FSM_onehot_STATE[2]_i_3\ : label is "soft_lutpair38"; attribute SOFT_HLUTNM of \FSM_onehot_STATE[5]_i_1\ : label is "soft_lutpair38"; attribute SOFT_HLUTNM of \FSM_onehot_STATE[7]_i_1\ : label is "soft_lutpair39"; attribute SOFT_HLUTNM of \FSM_onehot_STATE[8]_i_1\ : label is "soft_lutpair39"; attribute FSM_ENCODED_STATES : string; attribute FSM_ENCODED_STATES of \FSM_onehot_STATE_reg[0]\ : label is "comma_detect_2:0000000000001,aquire_sync_2:0000000000010,aquire_sync_1:0000000010000,sync_acquired_4:0000010000000,sync_acquired_4a:0000000100000,sync_acquired_3a:0000100000000,comma_detect_1:0010000000000,loss_of_sync:0000000000100,sync_acquired_2:0001000000000,sync_acquired_3:0000001000000,sync_acquired_2a:0100000000000,sync_acquired_1:1000000000000,comma_detect_3:0000000001000"; attribute FSM_ENCODED_STATES of \FSM_onehot_STATE_reg[10]\ : label is "comma_detect_2:0000000000001,aquire_sync_2:0000000000010,aquire_sync_1:0000000010000,sync_acquired_4:0000010000000,sync_acquired_4a:0000000100000,sync_acquired_3a:0000100000000,comma_detect_1:0010000000000,loss_of_sync:0000000000100,sync_acquired_2:0001000000000,sync_acquired_3:0000001000000,sync_acquired_2a:0100000000000,sync_acquired_1:1000000000000,comma_detect_3:0000000001000"; attribute FSM_ENCODED_STATES of \FSM_onehot_STATE_reg[11]\ : label is "comma_detect_2:0000000000001,aquire_sync_2:0000000000010,aquire_sync_1:0000000010000,sync_acquired_4:0000010000000,sync_acquired_4a:0000000100000,sync_acquired_3a:0000100000000,comma_detect_1:0010000000000,loss_of_sync:0000000000100,sync_acquired_2:0001000000000,sync_acquired_3:0000001000000,sync_acquired_2a:0100000000000,sync_acquired_1:1000000000000,comma_detect_3:0000000001000"; attribute FSM_ENCODED_STATES of \FSM_onehot_STATE_reg[12]\ : label is "comma_detect_2:0000000000001,aquire_sync_2:0000000000010,aquire_sync_1:0000000010000,sync_acquired_4:0000010000000,sync_acquired_4a:0000000100000,sync_acquired_3a:0000100000000,comma_detect_1:0010000000000,loss_of_sync:0000000000100,sync_acquired_2:0001000000000,sync_acquired_3:0000001000000,sync_acquired_2a:0100000000000,sync_acquired_1:1000000000000,comma_detect_3:0000000001000"; attribute FSM_ENCODED_STATES of \FSM_onehot_STATE_reg[1]\ : label is "comma_detect_2:0000000000001,aquire_sync_2:0000000000010,aquire_sync_1:0000000010000,sync_acquired_4:0000010000000,sync_acquired_4a:0000000100000,sync_acquired_3a:0000100000000,comma_detect_1:0010000000000,loss_of_sync:0000000000100,sync_acquired_2:0001000000000,sync_acquired_3:0000001000000,sync_acquired_2a:0100000000000,sync_acquired_1:1000000000000,comma_detect_3:0000000001000"; attribute FSM_ENCODED_STATES of \FSM_onehot_STATE_reg[2]\ : label is "comma_detect_2:0000000000001,aquire_sync_2:0000000000010,aquire_sync_1:0000000010000,sync_acquired_4:0000010000000,sync_acquired_4a:0000000100000,sync_acquired_3a:0000100000000,comma_detect_1:0010000000000,loss_of_sync:0000000000100,sync_acquired_2:0001000000000,sync_acquired_3:0000001000000,sync_acquired_2a:0100000000000,sync_acquired_1:1000000000000,comma_detect_3:0000000001000"; attribute FSM_ENCODED_STATES of \FSM_onehot_STATE_reg[3]\ : label is "comma_detect_2:0000000000001,aquire_sync_2:0000000000010,aquire_sync_1:0000000010000,sync_acquired_4:0000010000000,sync_acquired_4a:0000000100000,sync_acquired_3a:0000100000000,comma_detect_1:0010000000000,loss_of_sync:0000000000100,sync_acquired_2:0001000000000,sync_acquired_3:0000001000000,sync_acquired_2a:0100000000000,sync_acquired_1:1000000000000,comma_detect_3:0000000001000"; attribute FSM_ENCODED_STATES of \FSM_onehot_STATE_reg[4]\ : label is "comma_detect_2:0000000000001,aquire_sync_2:0000000000010,aquire_sync_1:0000000010000,sync_acquired_4:0000010000000,sync_acquired_4a:0000000100000,sync_acquired_3a:0000100000000,comma_detect_1:0010000000000,loss_of_sync:0000000000100,sync_acquired_2:0001000000000,sync_acquired_3:0000001000000,sync_acquired_2a:0100000000000,sync_acquired_1:1000000000000,comma_detect_3:0000000001000"; attribute FSM_ENCODED_STATES of \FSM_onehot_STATE_reg[5]\ : label is "comma_detect_2:0000000000001,aquire_sync_2:0000000000010,aquire_sync_1:0000000010000,sync_acquired_4:0000010000000,sync_acquired_4a:0000000100000,sync_acquired_3a:0000100000000,comma_detect_1:0010000000000,loss_of_sync:0000000000100,sync_acquired_2:0001000000000,sync_acquired_3:0000001000000,sync_acquired_2a:0100000000000,sync_acquired_1:1000000000000,comma_detect_3:0000000001000"; attribute FSM_ENCODED_STATES of \FSM_onehot_STATE_reg[6]\ : label is "comma_detect_2:0000000000001,aquire_sync_2:0000000000010,aquire_sync_1:0000000010000,sync_acquired_4:0000010000000,sync_acquired_4a:0000000100000,sync_acquired_3a:0000100000000,comma_detect_1:0010000000000,loss_of_sync:0000000000100,sync_acquired_2:0001000000000,sync_acquired_3:0000001000000,sync_acquired_2a:0100000000000,sync_acquired_1:1000000000000,comma_detect_3:0000000001000"; attribute FSM_ENCODED_STATES of \FSM_onehot_STATE_reg[7]\ : label is "comma_detect_2:0000000000001,aquire_sync_2:0000000000010,aquire_sync_1:0000000010000,sync_acquired_4:0000010000000,sync_acquired_4a:0000000100000,sync_acquired_3a:0000100000000,comma_detect_1:0010000000000,loss_of_sync:0000000000100,sync_acquired_2:0001000000000,sync_acquired_3:0000001000000,sync_acquired_2a:0100000000000,sync_acquired_1:1000000000000,comma_detect_3:0000000001000"; attribute FSM_ENCODED_STATES of \FSM_onehot_STATE_reg[8]\ : label is "comma_detect_2:0000000000001,aquire_sync_2:0000000000010,aquire_sync_1:0000000010000,sync_acquired_4:0000010000000,sync_acquired_4a:0000000100000,sync_acquired_3a:0000100000000,comma_detect_1:0010000000000,loss_of_sync:0000000000100,sync_acquired_2:0001000000000,sync_acquired_3:0000001000000,sync_acquired_2a:0100000000000,sync_acquired_1:1000000000000,comma_detect_3:0000000001000"; attribute FSM_ENCODED_STATES of \FSM_onehot_STATE_reg[9]\ : label is "comma_detect_2:0000000000001,aquire_sync_2:0000000000010,aquire_sync_1:0000000010000,sync_acquired_4:0000010000000,sync_acquired_4a:0000000100000,sync_acquired_3a:0000100000000,comma_detect_1:0010000000000,loss_of_sync:0000000000100,sync_acquired_2:0001000000000,sync_acquired_3:0000001000000,sync_acquired_2a:0100000000000,sync_acquired_1:1000000000000,comma_detect_3:0000000001000"; attribute SOFT_HLUTNM of \GOOD_CGS[1]_i_2\ : label is "soft_lutpair40"; attribute SOFT_HLUTNM of RX_INVALID_i_1 : label is "soft_lutpair40"; attribute SOFT_HLUTNM of STATUS_VECTOR_0_PRE_i_1 : label is "soft_lutpair41"; begin RXEVEN0_out <= \^rxeven0_out\; RXSYNC_STATUS <= \^rxsync_status\; enablealign <= \^enablealign\; ENCOMMAALIGN_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"00000000FFFEEEEE" ) port map ( I0 => \^enablealign\, I1 => \FSM_onehot_STATE_reg_n_0_[2]\, I2 => p_1_in, I3 => \FSM_onehot_STATE_reg_n_0_[5]\, I4 => ENCOMMAALIGN_i_2_n_0, I5 => SYNC_STATUS0, O => ENCOMMAALIGN_i_1_n_0 ); ENCOMMAALIGN_i_2: unisim.vcomponents.LUT5 generic map( INIT => X"FFFEFFFC" ) port map ( I0 => \FSM_onehot_STATE_reg[1]_0\, I1 => RXNOTINTABLE_INT, I2 => D, I3 => \FSM_onehot_STATE_reg[0]_0\, I4 => \^rxeven0_out\, O => ENCOMMAALIGN_i_2_n_0 ); ENCOMMAALIGN_i_3: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => p_0_in, I1 => ENCOMMAALIGN_i_2_n_0, I2 => \FSM_onehot_STATE_reg[2]_0\, O => SYNC_STATUS0 ); ENCOMMAALIGN_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => ENCOMMAALIGN_i_1_n_0, Q => \^enablealign\, R => '0' ); EVEN_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"4F" ) port map ( I0 => \^rxsync_status\, I1 => \FSM_onehot_STATE_reg[1]_0\, I2 => \^rxeven0_out\, O => EVEN_i_1_n_0 ); EVEN_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => EVEN_i_1_n_0, Q => \^rxeven0_out\, R => EVEN_reg_0 ); \FSM_onehot_STATE[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000200000000" ) port map ( I0 => \FSM_onehot_STATE_reg_n_0_[4]\, I1 => \^rxeven0_out\, I2 => \FSM_onehot_STATE_reg[0]_0\, I3 => D, I4 => RXNOTINTABLE_INT, I5 => \FSM_onehot_STATE_reg[1]_0\, O => \FSM_onehot_STATE[0]_i_1_n_0\ ); \FSM_onehot_STATE[10]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \FSM_onehot_STATE_reg[1]_0\, I1 => \FSM_onehot_STATE_reg_n_0_[2]\, O => \FSM_onehot_STATE[10]_i_1_n_0\ ); \FSM_onehot_STATE[11]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"54554444" ) port map ( I0 => ENCOMMAALIGN_i_2_n_0, I1 => \FSM_onehot_STATE_reg_n_0_[9]\, I2 => GOOD_CGS(0), I3 => GOOD_CGS(1), I4 => \FSM_onehot_STATE_reg_n_0_[11]\, O => \FSM_onehot_STATE[11]_i_1_n_0\ ); \FSM_onehot_STATE[12]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AB" ) port map ( I0 => EVEN_reg_0, I1 => SIGNAL_DETECT_REG, I2 => CONFIGURATION_VECTOR_REG(0), O => \FSM_onehot_STATE[12]_i_1_n_0\ ); \FSM_onehot_STATE[12]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"00000000FFF4F4F4" ) port map ( I0 => \FSM_onehot_STATE_reg[2]_0\, I1 => p_0_in, I2 => \FSM_onehot_STATE_reg_n_0_[12]\, I3 => \FSM_onehot_STATE[12]_i_3_n_0\, I4 => \FSM_onehot_STATE_reg_n_0_[11]\, I5 => ENCOMMAALIGN_i_2_n_0, O => \FSM_onehot_STATE[12]_i_2_n_0\ ); \FSM_onehot_STATE[12]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => GOOD_CGS(1), I1 => GOOD_CGS(0), O => \FSM_onehot_STATE[12]_i_3_n_0\ ); \FSM_onehot_STATE[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"000300BB000000AA" ) port map ( I0 => \FSM_onehot_STATE_reg_n_0_[1]\, I1 => \FSM_onehot_STATE_reg[2]_0\, I2 => \^rxeven0_out\, I3 => S2, I4 => \FSM_onehot_STATE_reg[1]_0\, I5 => \FSM_onehot_STATE_reg_n_0_[0]\, O => \FSM_onehot_STATE[1]_i_1_n_0\ ); \FSM_onehot_STATE[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFEFEFE00" ) port map ( I0 => \FSM_onehot_STATE_reg_n_0_[10]\, I1 => \FSM_onehot_STATE_reg_n_0_[0]\, I2 => p_0_in, I3 => \FSM_onehot_STATE_reg[2]_0\, I4 => ENCOMMAALIGN_i_2_n_0, I5 => \FSM_onehot_STATE[2]_i_2_n_0\, O => \FSM_onehot_STATE[2]_i_1_n_0\ ); \FSM_onehot_STATE[2]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFF4F44444444" ) port map ( I0 => \FSM_onehot_STATE_reg[1]_0\, I1 => \FSM_onehot_STATE_reg_n_0_[2]\, I2 => \FSM_onehot_STATE[2]_i_3_n_0\, I3 => \FSM_onehot_STATE_reg_n_0_[1]\, I4 => \FSM_onehot_STATE_reg_n_0_[4]\, I5 => ENCOMMAALIGN_i_2_n_0, O => \FSM_onehot_STATE[2]_i_2_n_0\ ); \FSM_onehot_STATE[2]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => p_1_in, I1 => \FSM_onehot_STATE_reg_n_0_[5]\, O => \FSM_onehot_STATE[2]_i_3_n_0\ ); \FSM_onehot_STATE[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000200000000" ) port map ( I0 => \FSM_onehot_STATE_reg_n_0_[1]\, I1 => \^rxeven0_out\, I2 => \FSM_onehot_STATE_reg[0]_0\, I3 => D, I4 => RXNOTINTABLE_INT, I5 => \FSM_onehot_STATE_reg[1]_0\, O => \FSM_onehot_STATE[3]_i_1_n_0\ ); \FSM_onehot_STATE[4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"000010FF00001050" ) port map ( I0 => \FSM_onehot_STATE_reg[2]_0\, I1 => \^rxeven0_out\, I2 => \FSM_onehot_STATE_reg_n_0_[10]\, I3 => \FSM_onehot_STATE_reg[1]_0\, I4 => S2, I5 => \FSM_onehot_STATE_reg_n_0_[4]\, O => \FSM_onehot_STATE[4]_i_1_n_0\ ); \FSM_onehot_STATE[5]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"54554444" ) port map ( I0 => ENCOMMAALIGN_i_2_n_0, I1 => p_1_in, I2 => GOOD_CGS(0), I3 => GOOD_CGS(1), I4 => \FSM_onehot_STATE_reg_n_0_[5]\, O => \FSM_onehot_STATE[5]_i_1_n_0\ ); \FSM_onehot_STATE[6]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFF0040404040" ) port map ( I0 => GOOD_CGS(0), I1 => GOOD_CGS(1), I2 => \FSM_onehot_STATE_reg_n_0_[5]\, I3 => \FSM_onehot_STATE_reg_n_0_[9]\, I4 => \FSM_onehot_STATE_reg_n_0_[11]\, I5 => ENCOMMAALIGN_i_2_n_0, O => \FSM_onehot_STATE[6]_i_1_n_0\ ); \FSM_onehot_STATE[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"A8" ) port map ( I0 => ENCOMMAALIGN_i_2_n_0, I1 => \FSM_onehot_STATE_reg_n_0_[8]\, I2 => \FSM_onehot_STATE_reg_n_0_[6]\, O => \FSM_onehot_STATE[7]_i_1_n_0\ ); \FSM_onehot_STATE[8]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"54554444" ) port map ( I0 => ENCOMMAALIGN_i_2_n_0, I1 => \FSM_onehot_STATE_reg_n_0_[6]\, I2 => GOOD_CGS(0), I3 => GOOD_CGS(1), I4 => \FSM_onehot_STATE_reg_n_0_[8]\, O => \FSM_onehot_STATE[8]_i_1_n_0\ ); \FSM_onehot_STATE[9]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"8B888888" ) port map ( I0 => \FSM_onehot_STATE_reg_n_0_[12]\, I1 => ENCOMMAALIGN_i_2_n_0, I2 => GOOD_CGS(0), I3 => GOOD_CGS(1), I4 => \FSM_onehot_STATE_reg_n_0_[8]\, O => \FSM_onehot_STATE[9]_i_1_n_0\ ); \FSM_onehot_STATE_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \FSM_onehot_STATE[0]_i_1_n_0\, Q => \FSM_onehot_STATE_reg_n_0_[0]\, R => \FSM_onehot_STATE[12]_i_1_n_0\ ); \FSM_onehot_STATE_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \FSM_onehot_STATE[10]_i_1_n_0\, Q => \FSM_onehot_STATE_reg_n_0_[10]\, R => \FSM_onehot_STATE[12]_i_1_n_0\ ); \FSM_onehot_STATE_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \FSM_onehot_STATE[11]_i_1_n_0\, Q => \FSM_onehot_STATE_reg_n_0_[11]\, R => \FSM_onehot_STATE[12]_i_1_n_0\ ); \FSM_onehot_STATE_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \FSM_onehot_STATE[12]_i_2_n_0\, Q => \FSM_onehot_STATE_reg_n_0_[12]\, R => \FSM_onehot_STATE[12]_i_1_n_0\ ); \FSM_onehot_STATE_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \FSM_onehot_STATE[1]_i_1_n_0\, Q => \FSM_onehot_STATE_reg_n_0_[1]\, R => \FSM_onehot_STATE[12]_i_1_n_0\ ); \FSM_onehot_STATE_reg[2]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => userclk2, CE => '1', D => \FSM_onehot_STATE[2]_i_1_n_0\, Q => \FSM_onehot_STATE_reg_n_0_[2]\, S => \FSM_onehot_STATE[12]_i_1_n_0\ ); \FSM_onehot_STATE_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \FSM_onehot_STATE[3]_i_1_n_0\, Q => p_0_in, R => \FSM_onehot_STATE[12]_i_1_n_0\ ); \FSM_onehot_STATE_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \FSM_onehot_STATE[4]_i_1_n_0\, Q => \FSM_onehot_STATE_reg_n_0_[4]\, R => \FSM_onehot_STATE[12]_i_1_n_0\ ); \FSM_onehot_STATE_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \FSM_onehot_STATE[5]_i_1_n_0\, Q => \FSM_onehot_STATE_reg_n_0_[5]\, R => \FSM_onehot_STATE[12]_i_1_n_0\ ); \FSM_onehot_STATE_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \FSM_onehot_STATE[6]_i_1_n_0\, Q => \FSM_onehot_STATE_reg_n_0_[6]\, R => \FSM_onehot_STATE[12]_i_1_n_0\ ); \FSM_onehot_STATE_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \FSM_onehot_STATE[7]_i_1_n_0\, Q => p_1_in, R => \FSM_onehot_STATE[12]_i_1_n_0\ ); \FSM_onehot_STATE_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \FSM_onehot_STATE[8]_i_1_n_0\, Q => \FSM_onehot_STATE_reg_n_0_[8]\, R => \FSM_onehot_STATE[12]_i_1_n_0\ ); \FSM_onehot_STATE_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \FSM_onehot_STATE[9]_i_1_n_0\, Q => \FSM_onehot_STATE_reg_n_0_[9]\, R => \FSM_onehot_STATE[12]_i_1_n_0\ ); \GOOD_CGS[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000009" ) port map ( I0 => GOOD_CGS(0), I1 => ENCOMMAALIGN_i_2_n_0, I2 => p_1_in, I3 => \FSM_onehot_STATE_reg_n_0_[9]\, I4 => EVEN_reg_0, I5 => \FSM_onehot_STATE_reg_n_0_[6]\, O => \GOOD_CGS[0]_i_1_n_0\ ); \GOOD_CGS[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"009A" ) port map ( I0 => GOOD_CGS(1), I1 => ENCOMMAALIGN_i_2_n_0, I2 => GOOD_CGS(0), I3 => \GOOD_CGS[1]_i_2_n_0\, O => \GOOD_CGS[1]_i_1_n_0\ ); \GOOD_CGS[1]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => \FSM_onehot_STATE_reg_n_0_[6]\, I1 => EVEN_reg_0, I2 => \FSM_onehot_STATE_reg_n_0_[9]\, I3 => p_1_in, O => \GOOD_CGS[1]_i_2_n_0\ ); \GOOD_CGS_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \GOOD_CGS[0]_i_1_n_0\, Q => GOOD_CGS(0), R => '0' ); \GOOD_CGS_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \GOOD_CGS[1]_i_1_n_0\, Q => GOOD_CGS(1), R => '0' ); I_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"20220000" ) port map ( I0 => I_reg, I1 => I_reg_0, I2 => \^rxsync_status\, I3 => \FSM_onehot_STATE_reg[2]_0\, I4 => \^rxeven0_out\, O => I0 ); RX_INVALID_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => EVEN_reg_0, I1 => \^rxsync_status\, O => SYNC_STATUS_REG0 ); SIGNAL_DETECT_REG_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => SIGNAL_DETECT_MOD, Q => SIGNAL_DETECT_REG, R => '0' ); STATUS_VECTOR_0_PRE_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^rxsync_status\, I1 => reset_done, O => STATUS_VECTOR_0_PRE0 ); SYNC_STATUS_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF0000222A" ) port map ( I0 => \^rxsync_status\, I1 => ENCOMMAALIGN_i_2_n_0, I2 => \FSM_onehot_STATE_reg_n_0_[5]\, I3 => p_1_in, I4 => \FSM_onehot_STATE_reg_n_0_[2]\, I5 => SYNC_STATUS0, O => SYNC_STATUS_i_1_n_0 ); SYNC_STATUS_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => SYNC_STATUS_i_1_n_0, Q => \^rxsync_status\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_TX is port ( \USE_ROCKET_IO.MGT_TX_RESET_INT_reg\ : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 3 downto 0 ); \CODE_GRP_CNT_reg[0]_0\ : out STD_LOGIC; \CODE_GRP_CNT_reg[0]_1\ : out STD_LOGIC; \NO_QSGMII_DATA.TXCHARISK_reg_0\ : out STD_LOGIC; \NO_QSGMII_DATA.TXCHARISK_reg_1\ : out STD_LOGIC; \NO_QSGMII_DATA.TXDATA_reg[2]_0\ : out STD_LOGIC; \NO_QSGMII_DATA.TXDATA_reg[3]_0\ : out STD_LOGIC; \NO_QSGMII_DATA.TXDATA_reg[5]_0\ : out STD_LOGIC; \NO_QSGMII_DATA.TXDATA_reg[7]_0\ : out STD_LOGIC; \NO_QSGMII_CHAR.TXCHARDISPVAL_reg_0\ : out STD_LOGIC; \NO_QSGMII_DATA.TXDATA_reg[7]_1\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); gmii_tx_en : in STD_LOGIC; userclk2 : in STD_LOGIC; \NO_QSGMII_DATA.TXDATA_reg[4]_0\ : in STD_LOGIC; gmii_tx_er : in STD_LOGIC; CONFIGURATION_VECTOR_REG : in STD_LOGIC_VECTOR ( 0 to 0 ); gmii_txd : in STD_LOGIC_VECTOR ( 7 downto 0 ); SR : in STD_LOGIC_VECTOR ( 0 to 0 ); rxcharisk : in STD_LOGIC_VECTOR ( 0 to 0 ); rxchariscomma : in STD_LOGIC_VECTOR ( 0 to 0 ); rxdata : in STD_LOGIC_VECTOR ( 7 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_TX; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_TX is signal C1_OR_C2_i_1_n_0 : STD_LOGIC; signal C1_OR_C2_reg_n_0 : STD_LOGIC; signal CODE_GRPISK : STD_LOGIC; signal CODE_GRPISK_i_1_n_0 : STD_LOGIC; signal CODE_GRPISK_i_2_n_0 : STD_LOGIC; signal \CODE_GRP[0]_i_1_n_0\ : STD_LOGIC; signal \CODE_GRP[0]_i_2_n_0\ : STD_LOGIC; signal \CODE_GRP[1]_i_1_n_0\ : STD_LOGIC; signal \CODE_GRP[1]_i_2_n_0\ : STD_LOGIC; signal \CODE_GRP[1]_i_3_n_0\ : STD_LOGIC; signal \CODE_GRP[2]_i_1_n_0\ : STD_LOGIC; signal \CODE_GRP[2]_i_2_n_0\ : STD_LOGIC; signal \CODE_GRP[3]_i_1_n_0\ : STD_LOGIC; signal \CODE_GRP[3]_i_2_n_0\ : STD_LOGIC; signal \CODE_GRP[4]_i_1_n_0\ : STD_LOGIC; signal \CODE_GRP[5]_i_1_n_0\ : STD_LOGIC; signal \CODE_GRP[6]_i_1_n_0\ : STD_LOGIC; signal \CODE_GRP[6]_i_2_n_0\ : STD_LOGIC; signal \CODE_GRP[6]_i_3_n_0\ : STD_LOGIC; signal \CODE_GRP[7]_i_1_n_0\ : STD_LOGIC; signal \CODE_GRP[7]_i_2_n_0\ : STD_LOGIC; signal \CODE_GRP_CNT_reg_n_0_[1]\ : STD_LOGIC; signal \CODE_GRP_reg_n_0_[0]\ : STD_LOGIC; signal CONFIG_DATA : STD_LOGIC_VECTOR ( 6 downto 0 ); signal \CONFIG_DATA_reg_n_0_[0]\ : STD_LOGIC; signal \CONFIG_DATA_reg_n_0_[3]\ : STD_LOGIC; signal \CONFIG_DATA_reg_n_0_[4]\ : STD_LOGIC; signal \CONFIG_DATA_reg_n_0_[6]\ : STD_LOGIC; signal DISPARITY : STD_LOGIC; signal INSERT_IDLE : STD_LOGIC; signal INSERT_IDLE_i_1_n_0 : STD_LOGIC; signal INSERT_IDLE_reg_n_0 : STD_LOGIC; signal K28p5 : STD_LOGIC; signal K28p5_i_1_n_0 : STD_LOGIC; signal \NO_QSGMII_CHAR.TXCHARDISPVAL_i_1_n_0\ : STD_LOGIC; signal \NO_QSGMII_DATA.TXDATA[0]_i_1_n_0\ : STD_LOGIC; signal \NO_QSGMII_DATA.TXDATA[2]_i_1_n_0\ : STD_LOGIC; signal \NO_QSGMII_DATA.TXDATA[4]_i_1_n_0\ : STD_LOGIC; signal \NO_QSGMII_DATA.TXDATA[5]_i_1_n_0\ : STD_LOGIC; signal \NO_QSGMII_DATA.TXDATA[6]_i_1_n_0\ : STD_LOGIC; signal \NO_QSGMII_DATA.TXDATA[7]_i_1_n_0\ : STD_LOGIC; signal \NO_QSGMII_DISP.DISPARITY_i_1_n_0\ : STD_LOGIC; signal \NO_QSGMII_DISP.DISPARITY_i_2_n_0\ : STD_LOGIC; signal \NO_QSGMII_DISP.DISPARITY_i_3_n_0\ : STD_LOGIC; signal R : STD_LOGIC; signal \R_i_1__0_n_0\ : STD_LOGIC; signal S : STD_LOGIC; signal S0 : STD_LOGIC; signal SYNC_DISPARITY_i_1_n_0 : STD_LOGIC; signal SYNC_DISPARITY_reg_n_0 : STD_LOGIC; signal T : STD_LOGIC; signal T0 : STD_LOGIC; signal TRIGGER_S : STD_LOGIC; signal TRIGGER_S0 : STD_LOGIC; signal TRIGGER_T : STD_LOGIC; signal TXCHARDISPMODE_INT : STD_LOGIC; signal TXCHARDISPVAL : STD_LOGIC; signal TXCHARISK_INT : STD_LOGIC; signal TXDATA : STD_LOGIC_VECTOR ( 7 downto 0 ); signal TXD_REG1 : STD_LOGIC_VECTOR ( 7 downto 0 ); signal TX_EN_REG1 : STD_LOGIC; signal TX_ER_REG1 : STD_LOGIC; signal TX_EVEN : STD_LOGIC; signal TX_PACKET : STD_LOGIC; signal TX_PACKET_REG1 : STD_LOGIC; signal TX_PACKET_i_1_n_0 : STD_LOGIC; signal V : STD_LOGIC; signal V_i_1_n_0 : STD_LOGIC; signal V_i_2_n_0 : STD_LOGIC; signal V_i_3_n_0 : STD_LOGIC; signal V_i_4_n_0 : STD_LOGIC; signal V_i_5_n_0 : STD_LOGIC; signal V_i_6_n_0 : STD_LOGIC; signal XMIT_CONFIG_INT : STD_LOGIC; signal XMIT_CONFIG_INT_i_1_n_0 : STD_LOGIC; signal XMIT_DATA_INT_i_1_n_0 : STD_LOGIC; signal XMIT_DATA_INT_reg_n_0 : STD_LOGIC; signal p_0_in : STD_LOGIC; signal p_0_in16_in : STD_LOGIC; signal p_0_in35_in : STD_LOGIC; signal p_10_out : STD_LOGIC; signal p_1_in : STD_LOGIC; signal p_1_in1_in : STD_LOGIC; signal p_1_in34_in : STD_LOGIC; signal p_33_in : STD_LOGIC; signal p_45_in : STD_LOGIC; signal plusOp : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of C1_OR_C2_i_1 : label is "soft_lutpair9"; attribute SOFT_HLUTNM of CODE_GRPISK_i_1 : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \CODE_GRP[0]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \CODE_GRP[0]_i_2\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \CODE_GRP[1]_i_2\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \CODE_GRP[1]_i_3\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \CODE_GRP[2]_i_2\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \CODE_GRP[6]_i_2\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \CODE_GRP[6]_i_3\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \CODE_GRP[7]_i_2\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \CODE_GRP_CNT[0]_i_1\ : label is "soft_lutpair23"; attribute SOFT_HLUTNM of \CODE_GRP_CNT[1]_i_1\ : label is "soft_lutpair21"; attribute SOFT_HLUTNM of \CONFIG_DATA[0]_i_1\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of \CONFIG_DATA[3]_i_1\ : label is "soft_lutpair22"; attribute SOFT_HLUTNM of \CONFIG_DATA[4]_i_1\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \CONFIG_DATA[6]_i_1\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of INSERT_IDLE_i_1 : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \NO_QSGMII_CHAR.TXCHARDISPMODE_i_1\ : label is "soft_lutpair23"; attribute SOFT_HLUTNM of \NO_QSGMII_CHAR.TXCHARDISPVAL_i_1\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \NO_QSGMII_DATA.TXDATA[4]_i_1\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \NO_QSGMII_DATA.TXDATA[6]_i_1\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of SYNC_DISPARITY_i_1 : label is "soft_lutpair6"; attribute SOFT_HLUTNM of TRIGGER_S_i_1 : label is "soft_lutpair4"; attribute SOFT_HLUTNM of TRIGGER_T_i_1 : label is "soft_lutpair4"; attribute SOFT_HLUTNM of TX_PACKET_i_1 : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCHARISCOMMA_INT_i_1\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCHARISK_INT_i_1\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT[1]_i_1\ : label is "soft_lutpair20"; attribute SOFT_HLUTNM of \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT[2]_i_1\ : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT[3]_i_1\ : label is "soft_lutpair16"; attribute SOFT_HLUTNM of \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT[4]_i_1\ : label is "soft_lutpair20"; attribute SOFT_HLUTNM of \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT[5]_i_1\ : label is "soft_lutpair17"; attribute SOFT_HLUTNM of \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT[6]_i_1\ : label is "soft_lutpair19"; attribute SOFT_HLUTNM of \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT[7]_i_1\ : label is "soft_lutpair18"; attribute SOFT_HLUTNM of \USE_ROCKET_IO.TXCHARDISPMODE_i_1\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \USE_ROCKET_IO.TXCHARDISPVAL_i_1\ : label is "soft_lutpair19"; attribute SOFT_HLUTNM of \USE_ROCKET_IO.TXCHARISK_i_1\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \USE_ROCKET_IO.TXDATA[0]_i_1\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \USE_ROCKET_IO.TXDATA[1]_i_1\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \USE_ROCKET_IO.TXDATA[2]_i_1\ : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \USE_ROCKET_IO.TXDATA[3]_i_1\ : label is "soft_lutpair16"; attribute SOFT_HLUTNM of \USE_ROCKET_IO.TXDATA[4]_i_1\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \USE_ROCKET_IO.TXDATA[5]_i_1\ : label is "soft_lutpair17"; attribute SOFT_HLUTNM of \USE_ROCKET_IO.TXDATA[6]_i_1\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \USE_ROCKET_IO.TXDATA[7]_i_1\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \USE_ROCKET_IO.TXDATA[7]_i_2\ : label is "soft_lutpair18"; attribute SOFT_HLUTNM of XMIT_CONFIG_INT_i_1 : label is "soft_lutpair21"; attribute SOFT_HLUTNM of XMIT_DATA_INT_i_1 : label is "soft_lutpair22"; begin C1_OR_C2_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"3F80" ) port map ( I0 => XMIT_CONFIG_INT, I1 => TX_EVEN, I2 => \CODE_GRP_CNT_reg_n_0_[1]\, I3 => C1_OR_C2_reg_n_0, O => C1_OR_C2_i_1_n_0 ); C1_OR_C2_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => C1_OR_C2_i_1_n_0, Q => C1_OR_C2_reg_n_0, R => \NO_QSGMII_DATA.TXDATA_reg[4]_0\ ); CODE_GRPISK_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"2F20" ) port map ( I0 => TX_EVEN, I1 => \CODE_GRP_CNT_reg_n_0_[1]\, I2 => XMIT_CONFIG_INT, I3 => CODE_GRPISK_i_2_n_0, O => CODE_GRPISK_i_1_n_0 ); CODE_GRPISK_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFEFFFF" ) port map ( I0 => V, I1 => R, I2 => T, I3 => S, I4 => TX_PACKET, I5 => SR(0), O => CODE_GRPISK_i_2_n_0 ); CODE_GRPISK_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => CODE_GRPISK_i_1_n_0, Q => CODE_GRPISK, R => '0' ); \CODE_GRP[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AAFFAA03" ) port map ( I0 => \CONFIG_DATA_reg_n_0_[0]\, I1 => \CODE_GRP[0]_i_2_n_0\, I2 => V, I3 => XMIT_CONFIG_INT, I4 => S, O => \CODE_GRP[0]_i_1_n_0\ ); \CODE_GRP[0]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"0007" ) port map ( I0 => TXD_REG1(0), I1 => TX_PACKET, I2 => R, I3 => T, O => \CODE_GRP[0]_i_2_n_0\ ); \CODE_GRP[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"00005555FFC05555" ) port map ( I0 => \CODE_GRP[1]_i_2_n_0\, I1 => TXD_REG1(1), I2 => TX_PACKET, I3 => R, I4 => \CODE_GRP[1]_i_3_n_0\, I5 => T, O => \CODE_GRP[1]_i_1_n_0\ ); \CODE_GRP[1]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => XMIT_CONFIG_INT, I1 => \CONFIG_DATA_reg_n_0_[6]\, O => \CODE_GRP[1]_i_2_n_0\ ); \CODE_GRP[1]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"01" ) port map ( I0 => V, I1 => XMIT_CONFIG_INT, I2 => S, O => \CODE_GRP[1]_i_3_n_0\ ); \CODE_GRP[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAA0000FFCF" ) port map ( I0 => \CONFIG_DATA_reg_n_0_[4]\, I1 => \CODE_GRP[2]_i_2_n_0\, I2 => TX_PACKET, I3 => TXD_REG1(2), I4 => S, I5 => XMIT_CONFIG_INT, O => \CODE_GRP[2]_i_1_n_0\ ); \CODE_GRP[2]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"FE" ) port map ( I0 => V, I1 => R, I2 => T, O => \CODE_GRP[2]_i_2_n_0\ ); \CODE_GRP[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"FFD0" ) port map ( I0 => TX_PACKET, I1 => TXD_REG1(3), I2 => \CODE_GRP[6]_i_3_n_0\, I3 => \CODE_GRP[3]_i_2_n_0\, O => \CODE_GRP[3]_i_1_n_0\ ); \CODE_GRP[3]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"AAFFAAFFAAFFAAFC" ) port map ( I0 => \CONFIG_DATA_reg_n_0_[3]\, I1 => SR(0), I2 => S, I3 => XMIT_CONFIG_INT, I4 => V, I5 => T, O => \CODE_GRP[3]_i_2_n_0\ ); \CODE_GRP[4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFF808080" ) port map ( I0 => \CODE_GRP[6]_i_3_n_0\, I1 => TXD_REG1(4), I2 => TX_PACKET, I3 => XMIT_CONFIG_INT, I4 => \CONFIG_DATA_reg_n_0_[4]\, I5 => \CODE_GRP[7]_i_2_n_0\, O => \CODE_GRP[4]_i_1_n_0\ ); \CODE_GRP[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFF808080" ) port map ( I0 => \CODE_GRP[6]_i_3_n_0\, I1 => TXD_REG1(5), I2 => TX_PACKET, I3 => XMIT_CONFIG_INT, I4 => \CONFIG_DATA_reg_n_0_[4]\, I5 => \CODE_GRP[7]_i_2_n_0\, O => \CODE_GRP[5]_i_1_n_0\ ); \CODE_GRP[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => SR(0), I1 => XMIT_CONFIG_INT, O => \CODE_GRP[6]_i_1_n_0\ ); \CODE_GRP[6]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"B000BBBB" ) port map ( I0 => \CONFIG_DATA_reg_n_0_[6]\, I1 => XMIT_CONFIG_INT, I2 => TX_PACKET, I3 => TXD_REG1(6), I4 => \CODE_GRP[6]_i_3_n_0\, O => \CODE_GRP[6]_i_2_n_0\ ); \CODE_GRP[6]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"00000001" ) port map ( I0 => XMIT_CONFIG_INT, I1 => S, I2 => T, I3 => R, I4 => V, O => \CODE_GRP[6]_i_3_n_0\ ); \CODE_GRP[7]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFF808080" ) port map ( I0 => \CODE_GRP[6]_i_3_n_0\, I1 => TXD_REG1(7), I2 => TX_PACKET, I3 => XMIT_CONFIG_INT, I4 => \CONFIG_DATA_reg_n_0_[4]\, I5 => \CODE_GRP[7]_i_2_n_0\, O => \CODE_GRP[7]_i_1_n_0\ ); \CODE_GRP[7]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"0000FFFB" ) port map ( I0 => SR(0), I1 => TX_PACKET, I2 => S, I3 => \CODE_GRP[2]_i_2_n_0\, I4 => XMIT_CONFIG_INT, O => \CODE_GRP[7]_i_2_n_0\ ); \CODE_GRP_CNT[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => TX_EVEN, O => plusOp(0) ); \CODE_GRP_CNT[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => TX_EVEN, I1 => \CODE_GRP_CNT_reg_n_0_[1]\, O => plusOp(1) ); \CODE_GRP_CNT_reg[0]\: unisim.vcomponents.FDSE port map ( C => userclk2, CE => '1', D => plusOp(0), Q => TX_EVEN, S => \NO_QSGMII_DATA.TXDATA_reg[4]_0\ ); \CODE_GRP_CNT_reg[1]\: unisim.vcomponents.FDSE port map ( C => userclk2, CE => '1', D => plusOp(1), Q => \CODE_GRP_CNT_reg_n_0_[1]\, S => \NO_QSGMII_DATA.TXDATA_reg[4]_0\ ); \CODE_GRP_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \CODE_GRP[0]_i_1_n_0\, Q => \CODE_GRP_reg_n_0_[0]\, R => \CODE_GRP[6]_i_1_n_0\ ); \CODE_GRP_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \CODE_GRP[1]_i_1_n_0\, Q => p_1_in, R => \CODE_GRP[6]_i_1_n_0\ ); \CODE_GRP_reg[2]\: unisim.vcomponents.FDSE port map ( C => userclk2, CE => '1', D => \CODE_GRP[2]_i_1_n_0\, Q => p_0_in16_in, S => \CODE_GRP[6]_i_1_n_0\ ); \CODE_GRP_reg[3]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \CODE_GRP[3]_i_1_n_0\, Q => p_0_in, R => '0' ); \CODE_GRP_reg[4]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \CODE_GRP[4]_i_1_n_0\, Q => p_1_in1_in, R => '0' ); \CODE_GRP_reg[5]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \CODE_GRP[5]_i_1_n_0\, Q => p_1_in34_in, R => '0' ); \CODE_GRP_reg[6]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \CODE_GRP[6]_i_2_n_0\, Q => p_33_in, R => \CODE_GRP[6]_i_1_n_0\ ); \CODE_GRP_reg[7]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \CODE_GRP[7]_i_1_n_0\, Q => p_0_in35_in, R => '0' ); \CONFIG_DATA[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) port map ( I0 => \CODE_GRP_CNT_reg_n_0_[1]\, I1 => TX_EVEN, I2 => C1_OR_C2_reg_n_0, O => CONFIG_DATA(0) ); \CONFIG_DATA[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => TX_EVEN, I1 => \CODE_GRP_CNT_reg_n_0_[1]\, O => CONFIG_DATA(3) ); \CONFIG_DATA[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"13" ) port map ( I0 => TX_EVEN, I1 => \CODE_GRP_CNT_reg_n_0_[1]\, I2 => C1_OR_C2_reg_n_0, O => CONFIG_DATA(4) ); \CONFIG_DATA[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"20" ) port map ( I0 => C1_OR_C2_reg_n_0, I1 => \CODE_GRP_CNT_reg_n_0_[1]\, I2 => TX_EVEN, O => CONFIG_DATA(6) ); \CONFIG_DATA_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => CONFIG_DATA(0), Q => \CONFIG_DATA_reg_n_0_[0]\, R => \NO_QSGMII_DATA.TXDATA_reg[4]_0\ ); \CONFIG_DATA_reg[3]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => CONFIG_DATA(3), Q => \CONFIG_DATA_reg_n_0_[3]\, R => \NO_QSGMII_DATA.TXDATA_reg[4]_0\ ); \CONFIG_DATA_reg[4]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => CONFIG_DATA(4), Q => \CONFIG_DATA_reg_n_0_[4]\, R => \NO_QSGMII_DATA.TXDATA_reg[4]_0\ ); \CONFIG_DATA_reg[6]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => CONFIG_DATA(6), Q => \CONFIG_DATA_reg_n_0_[6]\, R => \NO_QSGMII_DATA.TXDATA_reg[4]_0\ ); INSERT_IDLE_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"0000FF01" ) port map ( I0 => TX_PACKET, I1 => \CODE_GRP[2]_i_2_n_0\, I2 => S, I3 => SR(0), I4 => XMIT_CONFIG_INT, O => INSERT_IDLE_i_1_n_0 ); INSERT_IDLE_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => INSERT_IDLE_i_1_n_0, Q => INSERT_IDLE_reg_n_0, R => '0' ); K28p5_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => XMIT_CONFIG_INT, I1 => \CONFIG_DATA_reg_n_0_[3]\, O => K28p5_i_1_n_0 ); K28p5_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => K28p5_i_1_n_0, Q => K28p5, R => '0' ); \NO_QSGMII_CHAR.TXCHARDISPMODE_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => SYNC_DISPARITY_reg_n_0, I1 => TX_EVEN, O => p_10_out ); \NO_QSGMII_CHAR.TXCHARDISPMODE_reg\: unisim.vcomponents.FDSE port map ( C => userclk2, CE => '1', D => p_10_out, Q => TXCHARDISPMODE_INT, S => \NO_QSGMII_DATA.TXDATA_reg[4]_0\ ); \NO_QSGMII_CHAR.TXCHARDISPVAL_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"40" ) port map ( I0 => TX_EVEN, I1 => SYNC_DISPARITY_reg_n_0, I2 => DISPARITY, O => \NO_QSGMII_CHAR.TXCHARDISPVAL_i_1_n_0\ ); \NO_QSGMII_CHAR.TXCHARDISPVAL_reg\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \NO_QSGMII_CHAR.TXCHARDISPVAL_i_1_n_0\, Q => TXCHARDISPVAL, R => \NO_QSGMII_DATA.TXDATA_reg[4]_0\ ); \NO_QSGMII_DATA.TXCHARISK_reg\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => CODE_GRPISK, Q => TXCHARISK_INT, R => \NO_QSGMII_DATA.TXDATA[5]_i_1_n_0\ ); \NO_QSGMII_DATA.TXDATA[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"23332000" ) port map ( I0 => DISPARITY, I1 => \NO_QSGMII_DATA.TXDATA_reg[4]_0\, I2 => TX_EVEN, I3 => INSERT_IDLE_reg_n_0, I4 => \CODE_GRP_reg_n_0_[0]\, O => \NO_QSGMII_DATA.TXDATA[0]_i_1_n_0\ ); \NO_QSGMII_DATA.TXDATA[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"23332000" ) port map ( I0 => DISPARITY, I1 => \NO_QSGMII_DATA.TXDATA_reg[4]_0\, I2 => TX_EVEN, I3 => INSERT_IDLE_reg_n_0, I4 => p_0_in16_in, O => \NO_QSGMII_DATA.TXDATA[2]_i_1_n_0\ ); \NO_QSGMII_DATA.TXDATA[4]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F40" ) port map ( I0 => DISPARITY, I1 => INSERT_IDLE_reg_n_0, I2 => TX_EVEN, I3 => p_1_in1_in, O => \NO_QSGMII_DATA.TXDATA[4]_i_1_n_0\ ); \NO_QSGMII_DATA.TXDATA[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"EA" ) port map ( I0 => \NO_QSGMII_DATA.TXDATA_reg[4]_0\, I1 => TX_EVEN, I2 => INSERT_IDLE_reg_n_0, O => \NO_QSGMII_DATA.TXDATA[5]_i_1_n_0\ ); \NO_QSGMII_DATA.TXDATA[6]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"5540" ) port map ( I0 => \NO_QSGMII_DATA.TXDATA_reg[4]_0\, I1 => INSERT_IDLE_reg_n_0, I2 => TX_EVEN, I3 => p_33_in, O => \NO_QSGMII_DATA.TXDATA[6]_i_1_n_0\ ); \NO_QSGMII_DATA.TXDATA[7]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"23332000" ) port map ( I0 => DISPARITY, I1 => \NO_QSGMII_DATA.TXDATA_reg[4]_0\, I2 => TX_EVEN, I3 => INSERT_IDLE_reg_n_0, I4 => p_0_in35_in, O => \NO_QSGMII_DATA.TXDATA[7]_i_1_n_0\ ); \NO_QSGMII_DATA.TXDATA_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \NO_QSGMII_DATA.TXDATA[0]_i_1_n_0\, Q => TXDATA(0), R => '0' ); \NO_QSGMII_DATA.TXDATA_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => p_1_in, Q => TXDATA(1), R => \NO_QSGMII_DATA.TXDATA[5]_i_1_n_0\ ); \NO_QSGMII_DATA.TXDATA_reg[2]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \NO_QSGMII_DATA.TXDATA[2]_i_1_n_0\, Q => TXDATA(2), R => '0' ); \NO_QSGMII_DATA.TXDATA_reg[3]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => p_0_in, Q => TXDATA(3), R => \NO_QSGMII_DATA.TXDATA[5]_i_1_n_0\ ); \NO_QSGMII_DATA.TXDATA_reg[4]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \NO_QSGMII_DATA.TXDATA[4]_i_1_n_0\, Q => TXDATA(4), R => \NO_QSGMII_DATA.TXDATA_reg[4]_0\ ); \NO_QSGMII_DATA.TXDATA_reg[5]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => p_1_in34_in, Q => TXDATA(5), R => \NO_QSGMII_DATA.TXDATA[5]_i_1_n_0\ ); \NO_QSGMII_DATA.TXDATA_reg[6]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \NO_QSGMII_DATA.TXDATA[6]_i_1_n_0\, Q => TXDATA(6), R => '0' ); \NO_QSGMII_DATA.TXDATA_reg[7]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \NO_QSGMII_DATA.TXDATA[7]_i_1_n_0\, Q => TXDATA(7), R => '0' ); \NO_QSGMII_DISP.DISPARITY_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0009090900F6F6F6" ) port map ( I0 => \NO_QSGMII_DISP.DISPARITY_i_2_n_0\, I1 => \NO_QSGMII_DISP.DISPARITY_i_3_n_0\, I2 => K28p5, I3 => TX_EVEN, I4 => INSERT_IDLE_reg_n_0, I5 => DISPARITY, O => \NO_QSGMII_DISP.DISPARITY_i_1_n_0\ ); \NO_QSGMII_DISP.DISPARITY_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"167E7EE8" ) port map ( I0 => p_1_in, I1 => \CODE_GRP_reg_n_0_[0]\, I2 => p_0_in16_in, I3 => p_0_in, I4 => p_1_in1_in, O => \NO_QSGMII_DISP.DISPARITY_i_2_n_0\ ); \NO_QSGMII_DISP.DISPARITY_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"7C" ) port map ( I0 => p_0_in35_in, I1 => p_33_in, I2 => p_1_in34_in, O => \NO_QSGMII_DISP.DISPARITY_i_3_n_0\ ); \NO_QSGMII_DISP.DISPARITY_reg\: unisim.vcomponents.FDSE port map ( C => userclk2, CE => '1', D => \NO_QSGMII_DISP.DISPARITY_i_1_n_0\, Q => DISPARITY, S => \NO_QSGMII_DATA.TXDATA_reg[4]_0\ ); \R_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"DDDCCCCC" ) port map ( I0 => S, I1 => T, I2 => TX_ER_REG1, I3 => TX_EVEN, I4 => R, O => \R_i_1__0_n_0\ ); R_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \R_i_1__0_n_0\, Q => R, R => \NO_QSGMII_DATA.TXDATA_reg[4]_0\ ); SYNC_DISPARITY_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"2F20" ) port map ( I0 => TX_EVEN, I1 => \CODE_GRP_CNT_reg_n_0_[1]\, I2 => XMIT_CONFIG_INT, I3 => INSERT_IDLE, O => SYNC_DISPARITY_i_1_n_0 ); SYNC_DISPARITY_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAAAAAAAAAB" ) port map ( I0 => SR(0), I1 => S, I2 => T, I3 => R, I4 => V, I5 => TX_PACKET, O => INSERT_IDLE ); SYNC_DISPARITY_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => SYNC_DISPARITY_i_1_n_0, Q => SYNC_DISPARITY_reg_n_0, R => '0' ); \S_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"8888A8AA88888888" ) port map ( I0 => XMIT_DATA_INT_reg_n_0, I1 => TRIGGER_S, I2 => TX_ER_REG1, I3 => TX_EVEN, I4 => TX_EN_REG1, I5 => gmii_tx_en, O => S0 ); S_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => S0, Q => S, R => \NO_QSGMII_DATA.TXDATA_reg[4]_0\ ); TRIGGER_S_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"0400" ) port map ( I0 => TX_EN_REG1, I1 => gmii_tx_en, I2 => TX_ER_REG1, I3 => TX_EVEN, O => TRIGGER_S0 ); TRIGGER_S_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => TRIGGER_S0, Q => TRIGGER_S, R => \NO_QSGMII_DATA.TXDATA_reg[4]_0\ ); TRIGGER_T_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => TX_EN_REG1, I1 => gmii_tx_en, O => p_45_in ); TRIGGER_T_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => p_45_in, Q => TRIGGER_T, R => \NO_QSGMII_DATA.TXDATA_reg[4]_0\ ); \TXD_REG1_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => gmii_txd(0), Q => TXD_REG1(0), R => '0' ); \TXD_REG1_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => gmii_txd(1), Q => TXD_REG1(1), R => '0' ); \TXD_REG1_reg[2]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => gmii_txd(2), Q => TXD_REG1(2), R => '0' ); \TXD_REG1_reg[3]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => gmii_txd(3), Q => TXD_REG1(3), R => '0' ); \TXD_REG1_reg[4]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => gmii_txd(4), Q => TXD_REG1(4), R => '0' ); \TXD_REG1_reg[5]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => gmii_txd(5), Q => TXD_REG1(5), R => '0' ); \TXD_REG1_reg[6]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => gmii_txd(6), Q => TXD_REG1(6), R => '0' ); \TXD_REG1_reg[7]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => gmii_txd(7), Q => TXD_REG1(7), R => '0' ); TX_EN_REG1_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => gmii_tx_en, Q => TX_EN_REG1, R => '0' ); TX_ER_REG1_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => gmii_tx_er, Q => TX_ER_REG1, R => '0' ); TX_PACKET_REG1_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => TX_PACKET, Q => TX_PACKET_REG1, R => \NO_QSGMII_DATA.TXDATA_reg[4]_0\ ); TX_PACKET_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"DC" ) port map ( I0 => T, I1 => S, I2 => TX_PACKET, O => TX_PACKET_i_1_n_0 ); TX_PACKET_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => TX_PACKET_i_1_n_0, Q => TX_PACKET, R => \NO_QSGMII_DATA.TXDATA_reg[4]_0\ ); T_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"88888888FFF88888" ) port map ( I0 => TRIGGER_T, I1 => V, I2 => S, I3 => TX_PACKET, I4 => TX_EN_REG1, I5 => gmii_tx_en, O => T0 ); T_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => T0, Q => T, R => \NO_QSGMII_DATA.TXDATA_reg[4]_0\ ); \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCHARISCOMMA_INT_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => TXCHARISK_INT, I1 => CONFIGURATION_VECTOR_REG(0), I2 => rxchariscomma(0), O => \NO_QSGMII_DATA.TXCHARISK_reg_1\ ); \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCHARISK_INT_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => TXCHARISK_INT, I1 => CONFIGURATION_VECTOR_REG(0), I2 => rxcharisk(0), O => \NO_QSGMII_DATA.TXCHARISK_reg_0\ ); \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => TXDATA(0), I1 => CONFIGURATION_VECTOR_REG(0), I2 => rxdata(0), O => \NO_QSGMII_DATA.TXDATA_reg[7]_1\(0) ); \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => TXDATA(1), I1 => CONFIGURATION_VECTOR_REG(0), I2 => rxdata(1), O => \NO_QSGMII_DATA.TXDATA_reg[7]_1\(1) ); \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => TXDATA(2), I1 => CONFIGURATION_VECTOR_REG(0), I2 => rxdata(2), O => \NO_QSGMII_DATA.TXDATA_reg[7]_1\(2) ); \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => TXDATA(3), I1 => CONFIGURATION_VECTOR_REG(0), I2 => rxdata(3), O => \NO_QSGMII_DATA.TXDATA_reg[7]_1\(3) ); \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => TXDATA(4), I1 => CONFIGURATION_VECTOR_REG(0), I2 => rxdata(4), O => \NO_QSGMII_DATA.TXDATA_reg[7]_1\(4) ); \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => TXDATA(5), I1 => CONFIGURATION_VECTOR_REG(0), I2 => rxdata(5), O => \NO_QSGMII_DATA.TXDATA_reg[7]_1\(5) ); \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => TXDATA(6), I1 => CONFIGURATION_VECTOR_REG(0), I2 => rxdata(6), O => \NO_QSGMII_DATA.TXDATA_reg[7]_1\(6) ); \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => TXDATA(7), I1 => CONFIGURATION_VECTOR_REG(0), I2 => rxdata(7), O => \NO_QSGMII_DATA.TXDATA_reg[7]_1\(7) ); \USE_ROCKET_IO.TXCHARDISPMODE_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => TX_EVEN, I1 => CONFIGURATION_VECTOR_REG(0), I2 => TXCHARDISPMODE_INT, O => \CODE_GRP_CNT_reg[0]_0\ ); \USE_ROCKET_IO.TXCHARDISPVAL_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => TXCHARDISPVAL, I1 => CONFIGURATION_VECTOR_REG(0), I2 => \NO_QSGMII_DATA.TXDATA_reg[4]_0\, O => \NO_QSGMII_CHAR.TXCHARDISPVAL_reg_0\ ); \USE_ROCKET_IO.TXCHARISK_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => TX_EVEN, I1 => CONFIGURATION_VECTOR_REG(0), I2 => TXCHARISK_INT, O => \CODE_GRP_CNT_reg[0]_1\ ); \USE_ROCKET_IO.TXDATA[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => TXDATA(0), I1 => CONFIGURATION_VECTOR_REG(0), I2 => \NO_QSGMII_DATA.TXDATA_reg[4]_0\, O => D(0) ); \USE_ROCKET_IO.TXDATA[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => TXDATA(1), I1 => CONFIGURATION_VECTOR_REG(0), I2 => \NO_QSGMII_DATA.TXDATA_reg[4]_0\, O => D(1) ); \USE_ROCKET_IO.TXDATA[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => TXDATA(2), I1 => CONFIGURATION_VECTOR_REG(0), I2 => \NO_QSGMII_DATA.TXDATA_reg[4]_0\, O => \NO_QSGMII_DATA.TXDATA_reg[2]_0\ ); \USE_ROCKET_IO.TXDATA[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => TXDATA(3), I1 => CONFIGURATION_VECTOR_REG(0), I2 => \NO_QSGMII_DATA.TXDATA_reg[4]_0\, O => \NO_QSGMII_DATA.TXDATA_reg[3]_0\ ); \USE_ROCKET_IO.TXDATA[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"54" ) port map ( I0 => \NO_QSGMII_DATA.TXDATA_reg[4]_0\, I1 => TXDATA(4), I2 => CONFIGURATION_VECTOR_REG(0), O => D(2) ); \USE_ROCKET_IO.TXDATA[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => TXDATA(5), I1 => CONFIGURATION_VECTOR_REG(0), I2 => \NO_QSGMII_DATA.TXDATA_reg[4]_0\, O => \NO_QSGMII_DATA.TXDATA_reg[5]_0\ ); \USE_ROCKET_IO.TXDATA[6]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0074" ) port map ( I0 => TX_EVEN, I1 => CONFIGURATION_VECTOR_REG(0), I2 => TXDATA(6), I3 => \NO_QSGMII_DATA.TXDATA_reg[4]_0\, O => D(3) ); \USE_ROCKET_IO.TXDATA[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"40" ) port map ( I0 => \NO_QSGMII_DATA.TXDATA_reg[4]_0\, I1 => CONFIGURATION_VECTOR_REG(0), I2 => TX_EVEN, O => \USE_ROCKET_IO.MGT_TX_RESET_INT_reg\ ); \USE_ROCKET_IO.TXDATA[7]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => TXDATA(7), I1 => CONFIGURATION_VECTOR_REG(0), I2 => \NO_QSGMII_DATA.TXDATA_reg[4]_0\, O => \NO_QSGMII_DATA.TXDATA_reg[7]_0\ ); V_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"EA" ) port map ( I0 => V_i_2_n_0, I1 => S, I2 => V, O => V_i_1_n_0 ); V_i_2: unisim.vcomponents.LUT5 generic map( INIT => X"8A888A8A" ) port map ( I0 => XMIT_DATA_INT_reg_n_0, I1 => V_i_3_n_0, I2 => V_i_4_n_0, I3 => V_i_5_n_0, I4 => V_i_6_n_0, O => V_i_2_n_0 ); V_i_3: unisim.vcomponents.LUT3 generic map( INIT => X"08" ) port map ( I0 => TX_EN_REG1, I1 => TX_ER_REG1, I2 => TX_PACKET_REG1, O => V_i_3_n_0 ); V_i_4: unisim.vcomponents.LUT3 generic map( INIT => X"5D" ) port map ( I0 => gmii_tx_er, I1 => gmii_tx_en, I2 => TX_PACKET, O => V_i_4_n_0 ); V_i_5: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFDFFFFFFFFFF" ) port map ( I0 => gmii_txd(0), I1 => gmii_txd(5), I2 => gmii_tx_en, I3 => gmii_txd(3), I4 => gmii_txd(6), I5 => gmii_txd(1), O => V_i_5_n_0 ); V_i_6: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) port map ( I0 => gmii_txd(4), I1 => gmii_txd(2), I2 => gmii_txd(7), O => V_i_6_n_0 ); V_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => V_i_1_n_0, Q => V, R => \NO_QSGMII_DATA.TXDATA_reg[4]_0\ ); XMIT_CONFIG_INT_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"E0" ) port map ( I0 => TX_EVEN, I1 => \CODE_GRP_CNT_reg_n_0_[1]\, I2 => XMIT_CONFIG_INT, O => XMIT_CONFIG_INT_i_1_n_0 ); XMIT_CONFIG_INT_reg: unisim.vcomponents.FDSE port map ( C => userclk2, CE => '1', D => XMIT_CONFIG_INT_i_1_n_0, Q => XMIT_CONFIG_INT, S => \NO_QSGMII_DATA.TXDATA_reg[4]_0\ ); XMIT_DATA_INT_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"F1" ) port map ( I0 => \CODE_GRP_CNT_reg_n_0_[1]\, I1 => TX_EVEN, I2 => XMIT_DATA_INT_reg_n_0, O => XMIT_DATA_INT_i_1_n_0 ); XMIT_DATA_INT_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => XMIT_DATA_INT_i_1_n_0, Q => XMIT_DATA_INT_reg_n_0, R => \NO_QSGMII_DATA.TXDATA_reg[4]_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_sync_block is port ( reset_sync6_0 : out STD_LOGIC; dcm_locked : in STD_LOGIC; userclk2 : in STD_LOGIC; reset : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_sync_block; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_sync_block is signal reset_out : STD_LOGIC; signal reset_sync_reg1 : STD_LOGIC; signal reset_sync_reg2 : STD_LOGIC; signal reset_sync_reg3 : STD_LOGIC; signal reset_sync_reg4 : STD_LOGIC; signal reset_sync_reg5 : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of reset_sync1 : label is std.standard.true; attribute SHREG_EXTRACT : string; attribute SHREG_EXTRACT of reset_sync1 : label is "no"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of reset_sync1 : label is "FDP"; attribute box_type : string; attribute box_type of reset_sync1 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync2 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync2 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync2 : label is "FDP"; attribute box_type of reset_sync2 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync3 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync3 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync3 : label is "FDP"; attribute box_type of reset_sync3 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync4 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync4 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync4 : label is "FDP"; attribute box_type of reset_sync4 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync5 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync5 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync5 : label is "FDP"; attribute box_type of reset_sync5 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync6 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync6 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync6 : label is "FDP"; attribute box_type of reset_sync6 : label is "PRIMITIVE"; begin \MGT_RESET.RESET_INT_PIPE_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => reset_out, I1 => dcm_locked, O => reset_sync6_0 ); reset_sync1: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => userclk2, CE => '1', D => '0', PRE => reset, Q => reset_sync_reg1 ); reset_sync2: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => userclk2, CE => '1', D => reset_sync_reg1, PRE => reset, Q => reset_sync_reg2 ); reset_sync3: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => userclk2, CE => '1', D => reset_sync_reg2, PRE => reset, Q => reset_sync_reg3 ); reset_sync4: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => userclk2, CE => '1', D => reset_sync_reg3, PRE => reset, Q => reset_sync_reg4 ); reset_sync5: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => userclk2, CE => '1', D => reset_sync_reg4, PRE => reset, Q => reset_sync_reg5 ); reset_sync6: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => userclk2, CE => '1', D => reset_sync_reg5, PRE => '0', Q => reset_out ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_sync_block_17 is port ( p_6_out : out STD_LOGIC; dcm_locked : in STD_LOGIC; reset_out : in STD_LOGIC; reset : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_sync_block_17 : entity is "reset_sync_block"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_sync_block_17; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_sync_block_17 is signal RESET_REG_RXRECCLK : STD_LOGIC; signal reset_sync_reg1 : STD_LOGIC; signal reset_sync_reg2 : STD_LOGIC; signal reset_sync_reg3 : STD_LOGIC; signal reset_sync_reg4 : STD_LOGIC; signal reset_sync_reg5 : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of reset_sync1 : label is std.standard.true; attribute SHREG_EXTRACT : string; attribute SHREG_EXTRACT of reset_sync1 : label is "no"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of reset_sync1 : label is "FDP"; attribute box_type : string; attribute box_type of reset_sync1 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync2 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync2 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync2 : label is "FDP"; attribute box_type of reset_sync2 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync3 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync3 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync3 : label is "FDP"; attribute box_type of reset_sync3 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync4 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync4 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync4 : label is "FDP"; attribute box_type of reset_sync4 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync5 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync5 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync5 : label is "FDP"; attribute box_type of reset_sync5 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync6 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync6 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync6 : label is "FDP"; attribute box_type of reset_sync6 : label is "PRIMITIVE"; begin \MGT_RESET.RESET_INT_PIPE_RXRECCLK_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"FD" ) port map ( I0 => dcm_locked, I1 => RESET_REG_RXRECCLK, I2 => reset_out, O => p_6_out ); reset_sync1: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => '0', CE => '1', D => '0', PRE => reset, Q => reset_sync_reg1 ); reset_sync2: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => '0', CE => '1', D => reset_sync_reg1, PRE => reset, Q => reset_sync_reg2 ); reset_sync3: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => '0', CE => '1', D => reset_sync_reg2, PRE => reset, Q => reset_sync_reg3 ); reset_sync4: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => '0', CE => '1', D => reset_sync_reg3, PRE => reset, Q => reset_sync_reg4 ); reset_sync5: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => '0', CE => '1', D => reset_sync_reg4, PRE => reset, Q => reset_sync_reg5 ); reset_sync6: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => '0', CE => '1', D => reset_sync_reg5, PRE => '0', Q => RESET_REG_RXRECCLK ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_sync_block_18 is port ( reset_out : out STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_sync_block_18 : entity is "reset_sync_block"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_sync_block_18; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_sync_block_18 is signal reset_sync_reg1 : STD_LOGIC; signal reset_sync_reg2 : STD_LOGIC; signal reset_sync_reg3 : STD_LOGIC; signal reset_sync_reg4 : STD_LOGIC; signal reset_sync_reg5 : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of reset_sync1 : label is std.standard.true; attribute SHREG_EXTRACT : string; attribute SHREG_EXTRACT of reset_sync1 : label is "no"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of reset_sync1 : label is "FDP"; attribute box_type : string; attribute box_type of reset_sync1 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync2 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync2 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync2 : label is "FDP"; attribute box_type of reset_sync2 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync3 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync3 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync3 : label is "FDP"; attribute box_type of reset_sync3 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync4 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync4 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync4 : label is "FDP"; attribute box_type of reset_sync4 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync5 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync5 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync5 : label is "FDP"; attribute box_type of reset_sync5 : label is "PRIMITIVE"; attribute ASYNC_REG of reset_sync6 : label is std.standard.true; attribute SHREG_EXTRACT of reset_sync6 : label is "no"; attribute XILINX_LEGACY_PRIM of reset_sync6 : label is "FDP"; attribute box_type of reset_sync6 : label is "PRIMITIVE"; begin reset_sync1: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => '0', CE => '1', D => '0', PRE => '0', Q => reset_sync_reg1 ); reset_sync2: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => '0', CE => '1', D => reset_sync_reg1, PRE => '0', Q => reset_sync_reg2 ); reset_sync3: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => '0', CE => '1', D => reset_sync_reg2, PRE => '0', Q => reset_sync_reg3 ); reset_sync4: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => '0', CE => '1', D => reset_sync_reg3, PRE => '0', Q => reset_sync_reg4 ); reset_sync5: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => '0', CE => '1', D => reset_sync_reg4, PRE => '0', Q => reset_sync_reg5 ); reset_sync6: unisim.vcomponents.FDPE generic map( INIT => '1' ) port map ( C => '0', CE => '1', D => reset_sync_reg5, PRE => '0', Q => reset_out ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sync_block is port ( SIGNAL_DETECT_MOD : out STD_LOGIC; SIGNAL_DETECT_REG_reg : in STD_LOGIC; signal_detect : in STD_LOGIC; userclk2 : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sync_block; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sync_block is signal data_out : STD_LOGIC; signal data_sync1 : STD_LOGIC; signal data_sync2 : STD_LOGIC; signal data_sync3 : STD_LOGIC; signal data_sync4 : STD_LOGIC; signal data_sync5 : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true; attribute SHREG_EXTRACT : string; attribute SHREG_EXTRACT of data_sync_reg1 : label is "no"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD"; attribute box_type : string; attribute box_type of data_sync_reg1 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg2 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD"; attribute box_type of data_sync_reg2 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg3 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD"; attribute box_type of data_sync_reg3 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg4 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD"; attribute box_type of data_sync_reg4 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg5 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD"; attribute box_type of data_sync_reg5 : label is "PRIMITIVE"; attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true; attribute SHREG_EXTRACT of data_sync_reg6 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD"; attribute box_type of data_sync_reg6 : label is "PRIMITIVE"; begin SIGNAL_DETECT_REG_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => data_out, I1 => SIGNAL_DETECT_REG_reg, O => SIGNAL_DETECT_MOD ); data_sync_reg1: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => signal_detect, Q => data_sync1, R => '0' ); data_sync_reg2: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => data_sync1, Q => data_sync2, R => '0' ); data_sync_reg3: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => data_sync2, Q => data_sync3, R => '0' ); data_sync_reg4: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => data_sync3, Q => data_sync4, R => '0' ); data_sync_reg5: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => data_sync4, Q => data_sync5, R => '0' ); data_sync_reg6: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => data_sync5, Q => data_out, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_GTWIZARD_multi_gt is port ( cplllock : out STD_LOGIC; gt0_cpllrefclklost_i : out STD_LOGIC; txn : out STD_LOGIC; txp : out STD_LOGIC; rxoutclk : out STD_LOGIC; independent_clock_bufg_0 : out STD_LOGIC; txoutclk : out STD_LOGIC; independent_clock_bufg_1 : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 1 downto 0 ); TXBUFSTATUS : out STD_LOGIC_VECTOR ( 0 to 0 ); RXBUFSTATUS : out STD_LOGIC_VECTOR ( 0 to 0 ); independent_clock_bufg_2 : out STD_LOGIC_VECTOR ( 15 downto 0 ); independent_clock_bufg_3 : out STD_LOGIC_VECTOR ( 1 downto 0 ); independent_clock_bufg_4 : out STD_LOGIC_VECTOR ( 1 downto 0 ); independent_clock_bufg_5 : out STD_LOGIC_VECTOR ( 1 downto 0 ); independent_clock_bufg_6 : out STD_LOGIC_VECTOR ( 1 downto 0 ); gtrefclk_bufg : in STD_LOGIC; independent_clock_bufg : in STD_LOGIC; gtrefclk : in STD_LOGIC; gt0_gtrxreset_in1_out : in STD_LOGIC; gt0_gttxreset_in0_out : in STD_LOGIC; rxn : in STD_LOGIC; rxp : in STD_LOGIC; gt0_qplloutclk_in : in STD_LOGIC; gt0_qplloutrefclk_in : in STD_LOGIC; reset_out : in STD_LOGIC; reset : in STD_LOGIC; gt0_rxuserrdy_t : in STD_LOGIC; userclk : in STD_LOGIC; TXPD : in STD_LOGIC_VECTOR ( 0 to 0 ); gt0_txuserrdy_t : in STD_LOGIC; RXPD : in STD_LOGIC_VECTOR ( 0 to 0 ); Q : in STD_LOGIC_VECTOR ( 15 downto 0 ); data_sync_reg1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); data_sync_reg1_0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); data_sync_reg1_1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); gt0_cpllreset_t : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_GTWIZARD_multi_gt; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_GTWIZARD_multi_gt is signal cpll_pd0_i : STD_LOGIC; signal cpllreset_in : STD_LOGIC; begin cpll_railing0_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_cpll_railing port map ( cpll_pd0_i => cpll_pd0_i, cpllreset_in => cpllreset_in, gt0_cpllreset_t => gt0_cpllreset_t, gtrefclk_bufg => gtrefclk_bufg ); gt0_GTWIZARD_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_GTWIZARD_GT port map ( D(1 downto 0) => D(1 downto 0), Q(15 downto 0) => Q(15 downto 0), RXBUFSTATUS(0) => RXBUFSTATUS(0), RXPD(0) => RXPD(0), TXBUFSTATUS(0) => TXBUFSTATUS(0), TXPD(0) => TXPD(0), cpll_pd0_i => cpll_pd0_i, cplllock => cplllock, cpllreset_in => cpllreset_in, data_sync_reg1(1 downto 0) => data_sync_reg1(1 downto 0), data_sync_reg1_0(1 downto 0) => data_sync_reg1_0(1 downto 0), data_sync_reg1_1(1 downto 0) => data_sync_reg1_1(1 downto 0), gt0_cpllrefclklost_i => gt0_cpllrefclklost_i, gt0_gtrxreset_in1_out => gt0_gtrxreset_in1_out, gt0_gttxreset_in0_out => gt0_gttxreset_in0_out, gt0_qplloutclk_in => gt0_qplloutclk_in, gt0_qplloutrefclk_in => gt0_qplloutrefclk_in, gt0_rxuserrdy_t => gt0_rxuserrdy_t, gt0_txuserrdy_t => gt0_txuserrdy_t, gtrefclk => gtrefclk, gtrefclk_bufg => gtrefclk_bufg, independent_clock_bufg => independent_clock_bufg, independent_clock_bufg_0 => independent_clock_bufg_0, independent_clock_bufg_1 => independent_clock_bufg_1, independent_clock_bufg_2(15 downto 0) => independent_clock_bufg_2(15 downto 0), independent_clock_bufg_3(1 downto 0) => independent_clock_bufg_3(1 downto 0), independent_clock_bufg_4(1 downto 0) => independent_clock_bufg_4(1 downto 0), independent_clock_bufg_5(1 downto 0) => independent_clock_bufg_5(1 downto 0), independent_clock_bufg_6(1 downto 0) => independent_clock_bufg_6(1 downto 0), reset => reset, reset_out => reset_out, rxn => rxn, rxoutclk => rxoutclk, rxp => rxp, txn => txn, txoutclk => txoutclk, txp => txp, userclk => userclk ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_RX_STARTUP_FSM is port ( data_in : out STD_LOGIC; gt0_rxuserrdy_t : out STD_LOGIC; gt0_gtrxreset_in1_out : out STD_LOGIC; gt0_rx_cdrlocked_reg : out STD_LOGIC; independent_clock_bufg : in STD_LOGIC; userclk : in STD_LOGIC; pma_reset : in STD_LOGIC; gt0_rx_cdrlocked_reg_0 : in STD_LOGIC; gt0_rx_cdrlock_counter_reg_0_sp_1 : in STD_LOGIC; gt0_rx_cdrlocked_reg_1 : in STD_LOGIC; gt0_rx_cdrlock_counter_reg : in STD_LOGIC_VECTOR ( 1 downto 0 ); gt0_rx_cdrlocked_reg_2 : in STD_LOGIC; data_sync_reg1 : in STD_LOGIC; mmcm_locked : in STD_LOGIC; data_out : in STD_LOGIC; cplllock : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_RX_STARTUP_FSM; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_RX_STARTUP_FSM is signal \FSM_sequential_rx_state[0]_i_2_n_0\ : STD_LOGIC; signal \FSM_sequential_rx_state[1]_i_3_n_0\ : STD_LOGIC; signal \FSM_sequential_rx_state[2]_i_1_n_0\ : STD_LOGIC; signal \FSM_sequential_rx_state[2]_i_2_n_0\ : STD_LOGIC; signal \FSM_sequential_rx_state[3]_i_10_n_0\ : STD_LOGIC; signal \FSM_sequential_rx_state[3]_i_3_n_0\ : STD_LOGIC; signal \FSM_sequential_rx_state[3]_i_7_n_0\ : STD_LOGIC; signal \FSM_sequential_rx_state[3]_i_9_n_0\ : STD_LOGIC; signal GTRXRESET : STD_LOGIC; signal RXUSERRDY_i_1_n_0 : STD_LOGIC; signal check_tlock_max_i_1_n_0 : STD_LOGIC; signal check_tlock_max_reg_n_0 : STD_LOGIC; signal \^data_in\ : STD_LOGIC; signal data_out_0 : STD_LOGIC; signal \^gt0_gtrxreset_in1_out\ : STD_LOGIC; signal gt0_rx_cdrlock_counter_reg_0_sn_1 : STD_LOGIC; signal \^gt0_rxuserrdy_t\ : STD_LOGIC; signal gtrxreset_i_i_1_n_0 : STD_LOGIC; signal \init_wait_count[0]_i_1__0_n_0\ : STD_LOGIC; signal \init_wait_count[6]_i_1__0_n_0\ : STD_LOGIC; signal \init_wait_count[6]_i_3__0_n_0\ : STD_LOGIC; signal \init_wait_count_reg__0\ : STD_LOGIC_VECTOR ( 6 downto 0 ); signal \init_wait_done_i_1__0_n_0\ : STD_LOGIC; signal init_wait_done_reg_n_0 : STD_LOGIC; signal \mmcm_lock_count[2]_i_1__0_n_0\ : STD_LOGIC; signal \mmcm_lock_count[3]_i_1__0_n_0\ : STD_LOGIC; signal \mmcm_lock_count[4]_i_1__0_n_0\ : STD_LOGIC; signal \mmcm_lock_count[5]_i_1__0_n_0\ : STD_LOGIC; signal \mmcm_lock_count[6]_i_1__0_n_0\ : STD_LOGIC; signal \mmcm_lock_count[7]_i_2__0_n_0\ : STD_LOGIC; signal \mmcm_lock_count[7]_i_3__0_n_0\ : STD_LOGIC; signal \mmcm_lock_count[7]_i_4__0_n_0\ : STD_LOGIC; signal \mmcm_lock_count_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal mmcm_lock_reclocked : STD_LOGIC; signal \p_0_in__2\ : STD_LOGIC_VECTOR ( 6 downto 1 ); signal \p_0_in__3\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal reset_time_out_i_3_n_0 : STD_LOGIC; signal reset_time_out_i_4_n_0 : STD_LOGIC; signal reset_time_out_reg_n_0 : STD_LOGIC; signal \run_phase_alignment_int_i_1__0_n_0\ : STD_LOGIC; signal run_phase_alignment_int_reg_n_0 : STD_LOGIC; signal run_phase_alignment_int_s3_reg_n_0 : STD_LOGIC; signal rx_fsm_reset_done_int_i_5_n_0 : STD_LOGIC; signal rx_fsm_reset_done_int_i_6_n_0 : STD_LOGIC; signal rx_fsm_reset_done_int_s2 : STD_LOGIC; signal rx_fsm_reset_done_int_s3 : STD_LOGIC; signal rx_state : STD_LOGIC_VECTOR ( 3 downto 0 ); signal rxresetdone_s2 : STD_LOGIC; signal rxresetdone_s3 : STD_LOGIC; signal sync_cplllock_n_0 : STD_LOGIC; signal sync_data_valid_n_0 : STD_LOGIC; signal sync_data_valid_n_1 : STD_LOGIC; signal sync_data_valid_n_2 : STD_LOGIC; signal sync_data_valid_n_3 : STD_LOGIC; signal sync_data_valid_n_4 : STD_LOGIC; signal sync_data_valid_n_5 : STD_LOGIC; signal sync_mmcm_lock_reclocked_n_0 : STD_LOGIC; signal sync_mmcm_lock_reclocked_n_1 : STD_LOGIC; signal time_out_100us_i_1_n_0 : STD_LOGIC; signal time_out_100us_i_2_n_0 : STD_LOGIC; signal time_out_100us_i_3_n_0 : STD_LOGIC; signal time_out_100us_reg_n_0 : STD_LOGIC; signal time_out_1us_i_1_n_0 : STD_LOGIC; signal time_out_1us_i_2_n_0 : STD_LOGIC; signal time_out_1us_i_3_n_0 : STD_LOGIC; signal time_out_1us_reg_n_0 : STD_LOGIC; signal time_out_2ms_i_1_n_0 : STD_LOGIC; signal \time_out_2ms_i_2__0_n_0\ : STD_LOGIC; signal time_out_2ms_reg_n_0 : STD_LOGIC; signal time_out_counter : STD_LOGIC; signal \time_out_counter[0]_i_3_n_0\ : STD_LOGIC; signal \time_out_counter[0]_i_4_n_0\ : STD_LOGIC; signal \time_out_counter[0]_i_5_n_0\ : STD_LOGIC; signal time_out_counter_reg : STD_LOGIC_VECTOR ( 18 downto 0 ); signal \time_out_counter_reg[0]_i_2__0_n_0\ : STD_LOGIC; signal \time_out_counter_reg[0]_i_2__0_n_1\ : STD_LOGIC; signal \time_out_counter_reg[0]_i_2__0_n_2\ : STD_LOGIC; signal \time_out_counter_reg[0]_i_2__0_n_3\ : STD_LOGIC; signal \time_out_counter_reg[0]_i_2__0_n_4\ : STD_LOGIC; signal \time_out_counter_reg[0]_i_2__0_n_5\ : STD_LOGIC; signal \time_out_counter_reg[0]_i_2__0_n_6\ : STD_LOGIC; signal \time_out_counter_reg[0]_i_2__0_n_7\ : STD_LOGIC; signal \time_out_counter_reg[12]_i_1__0_n_0\ : STD_LOGIC; signal \time_out_counter_reg[12]_i_1__0_n_1\ : STD_LOGIC; signal \time_out_counter_reg[12]_i_1__0_n_2\ : STD_LOGIC; signal \time_out_counter_reg[12]_i_1__0_n_3\ : STD_LOGIC; signal \time_out_counter_reg[12]_i_1__0_n_4\ : STD_LOGIC; signal \time_out_counter_reg[12]_i_1__0_n_5\ : STD_LOGIC; signal \time_out_counter_reg[12]_i_1__0_n_6\ : STD_LOGIC; signal \time_out_counter_reg[12]_i_1__0_n_7\ : STD_LOGIC; signal \time_out_counter_reg[16]_i_1__0_n_2\ : STD_LOGIC; signal \time_out_counter_reg[16]_i_1__0_n_3\ : STD_LOGIC; signal \time_out_counter_reg[16]_i_1__0_n_5\ : STD_LOGIC; signal \time_out_counter_reg[16]_i_1__0_n_6\ : STD_LOGIC; signal \time_out_counter_reg[16]_i_1__0_n_7\ : STD_LOGIC; signal \time_out_counter_reg[4]_i_1__0_n_0\ : STD_LOGIC; signal \time_out_counter_reg[4]_i_1__0_n_1\ : STD_LOGIC; signal \time_out_counter_reg[4]_i_1__0_n_2\ : STD_LOGIC; signal \time_out_counter_reg[4]_i_1__0_n_3\ : STD_LOGIC; signal \time_out_counter_reg[4]_i_1__0_n_4\ : STD_LOGIC; signal \time_out_counter_reg[4]_i_1__0_n_5\ : STD_LOGIC; signal \time_out_counter_reg[4]_i_1__0_n_6\ : STD_LOGIC; signal \time_out_counter_reg[4]_i_1__0_n_7\ : STD_LOGIC; signal \time_out_counter_reg[8]_i_1__0_n_0\ : STD_LOGIC; signal \time_out_counter_reg[8]_i_1__0_n_1\ : STD_LOGIC; signal \time_out_counter_reg[8]_i_1__0_n_2\ : STD_LOGIC; signal \time_out_counter_reg[8]_i_1__0_n_3\ : STD_LOGIC; signal \time_out_counter_reg[8]_i_1__0_n_4\ : STD_LOGIC; signal \time_out_counter_reg[8]_i_1__0_n_5\ : STD_LOGIC; signal \time_out_counter_reg[8]_i_1__0_n_6\ : STD_LOGIC; signal \time_out_counter_reg[8]_i_1__0_n_7\ : STD_LOGIC; signal \time_out_wait_bypass_i_1__0_n_0\ : STD_LOGIC; signal time_out_wait_bypass_reg_n_0 : STD_LOGIC; signal time_out_wait_bypass_s2 : STD_LOGIC; signal time_out_wait_bypass_s3 : STD_LOGIC; signal time_tlock_max : STD_LOGIC; signal time_tlock_max1 : STD_LOGIC; signal \time_tlock_max1_carry__0_i_1_n_0\ : STD_LOGIC; signal \time_tlock_max1_carry__0_i_2_n_0\ : STD_LOGIC; signal \time_tlock_max1_carry__0_i_3_n_0\ : STD_LOGIC; signal \time_tlock_max1_carry__0_i_4_n_0\ : STD_LOGIC; signal \time_tlock_max1_carry__0_i_5_n_0\ : STD_LOGIC; signal \time_tlock_max1_carry__0_i_6_n_0\ : STD_LOGIC; signal \time_tlock_max1_carry__0_n_0\ : STD_LOGIC; signal \time_tlock_max1_carry__0_n_1\ : STD_LOGIC; signal \time_tlock_max1_carry__0_n_2\ : STD_LOGIC; signal \time_tlock_max1_carry__0_n_3\ : STD_LOGIC; signal \time_tlock_max1_carry__1_i_1_n_0\ : STD_LOGIC; signal \time_tlock_max1_carry__1_i_2_n_0\ : STD_LOGIC; signal \time_tlock_max1_carry__1_i_3_n_0\ : STD_LOGIC; signal \time_tlock_max1_carry__1_n_3\ : STD_LOGIC; signal time_tlock_max1_carry_i_1_n_0 : STD_LOGIC; signal time_tlock_max1_carry_i_2_n_0 : STD_LOGIC; signal time_tlock_max1_carry_i_3_n_0 : STD_LOGIC; signal time_tlock_max1_carry_i_4_n_0 : STD_LOGIC; signal time_tlock_max1_carry_i_5_n_0 : STD_LOGIC; signal time_tlock_max1_carry_i_6_n_0 : STD_LOGIC; signal time_tlock_max1_carry_i_7_n_0 : STD_LOGIC; signal time_tlock_max1_carry_i_8_n_0 : STD_LOGIC; signal time_tlock_max1_carry_n_0 : STD_LOGIC; signal time_tlock_max1_carry_n_1 : STD_LOGIC; signal time_tlock_max1_carry_n_2 : STD_LOGIC; signal time_tlock_max1_carry_n_3 : STD_LOGIC; signal time_tlock_max_i_1_n_0 : STD_LOGIC; signal \wait_bypass_count[0]_i_1__0_n_0\ : STD_LOGIC; signal \wait_bypass_count[0]_i_2__0_n_0\ : STD_LOGIC; signal \wait_bypass_count[0]_i_4__0_n_0\ : STD_LOGIC; signal \wait_bypass_count[0]_i_5__0_n_0\ : STD_LOGIC; signal \wait_bypass_count[0]_i_6__0_n_0\ : STD_LOGIC; signal \wait_bypass_count[0]_i_7__0_n_0\ : STD_LOGIC; signal wait_bypass_count_reg : STD_LOGIC_VECTOR ( 12 downto 0 ); signal \wait_bypass_count_reg[0]_i_3__0_n_0\ : STD_LOGIC; signal \wait_bypass_count_reg[0]_i_3__0_n_1\ : STD_LOGIC; signal \wait_bypass_count_reg[0]_i_3__0_n_2\ : STD_LOGIC; signal \wait_bypass_count_reg[0]_i_3__0_n_3\ : STD_LOGIC; signal \wait_bypass_count_reg[0]_i_3__0_n_4\ : STD_LOGIC; signal \wait_bypass_count_reg[0]_i_3__0_n_5\ : STD_LOGIC; signal \wait_bypass_count_reg[0]_i_3__0_n_6\ : STD_LOGIC; signal \wait_bypass_count_reg[0]_i_3__0_n_7\ : STD_LOGIC; signal \wait_bypass_count_reg[12]_i_1__0_n_7\ : STD_LOGIC; signal \wait_bypass_count_reg[4]_i_1__0_n_0\ : STD_LOGIC; signal \wait_bypass_count_reg[4]_i_1__0_n_1\ : STD_LOGIC; signal \wait_bypass_count_reg[4]_i_1__0_n_2\ : STD_LOGIC; signal \wait_bypass_count_reg[4]_i_1__0_n_3\ : STD_LOGIC; signal \wait_bypass_count_reg[4]_i_1__0_n_4\ : STD_LOGIC; signal \wait_bypass_count_reg[4]_i_1__0_n_5\ : STD_LOGIC; signal \wait_bypass_count_reg[4]_i_1__0_n_6\ : STD_LOGIC; signal \wait_bypass_count_reg[4]_i_1__0_n_7\ : STD_LOGIC; signal \wait_bypass_count_reg[8]_i_1__0_n_0\ : STD_LOGIC; signal \wait_bypass_count_reg[8]_i_1__0_n_1\ : STD_LOGIC; signal \wait_bypass_count_reg[8]_i_1__0_n_2\ : STD_LOGIC; signal \wait_bypass_count_reg[8]_i_1__0_n_3\ : STD_LOGIC; signal \wait_bypass_count_reg[8]_i_1__0_n_4\ : STD_LOGIC; signal \wait_bypass_count_reg[8]_i_1__0_n_5\ : STD_LOGIC; signal \wait_bypass_count_reg[8]_i_1__0_n_6\ : STD_LOGIC; signal \wait_bypass_count_reg[8]_i_1__0_n_7\ : STD_LOGIC; signal \wait_time_cnt0__0\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \wait_time_cnt[1]_i_1__0_n_0\ : STD_LOGIC; signal \wait_time_cnt[2]_i_1__0_n_0\ : STD_LOGIC; signal \wait_time_cnt[3]_i_1__0_n_0\ : STD_LOGIC; signal \wait_time_cnt[4]_i_1__0_n_0\ : STD_LOGIC; signal \wait_time_cnt[5]_i_1__0_n_0\ : STD_LOGIC; signal \wait_time_cnt[6]_i_1_n_0\ : STD_LOGIC; signal \wait_time_cnt[6]_i_2__0_n_0\ : STD_LOGIC; signal \wait_time_cnt[6]_i_3__0_n_0\ : STD_LOGIC; signal \wait_time_cnt[6]_i_4__0_n_0\ : STD_LOGIC; signal \wait_time_cnt_reg__0\ : STD_LOGIC_VECTOR ( 6 downto 0 ); signal \NLW_time_out_counter_reg[16]_i_1__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_time_out_counter_reg[16]_i_1__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); signal NLW_time_tlock_max1_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_time_tlock_max1_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_time_tlock_max1_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_time_tlock_max1_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_wait_bypass_count_reg[12]_i_1__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_wait_bypass_count_reg[12]_i_1__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \FSM_sequential_rx_state[2]_i_2\ : label is "soft_lutpair54"; attribute SOFT_HLUTNM of \FSM_sequential_rx_state[3]_i_10\ : label is "soft_lutpair51"; attribute SOFT_HLUTNM of \FSM_sequential_rx_state[3]_i_9\ : label is "soft_lutpair47"; attribute FSM_ENCODED_STATES : string; attribute FSM_ENCODED_STATES of \FSM_sequential_rx_state_reg[0]\ : label is "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101"; attribute FSM_ENCODED_STATES of \FSM_sequential_rx_state_reg[1]\ : label is "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101"; attribute FSM_ENCODED_STATES of \FSM_sequential_rx_state_reg[2]\ : label is "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101"; attribute FSM_ENCODED_STATES of \FSM_sequential_rx_state_reg[3]\ : label is "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101"; attribute SOFT_HLUTNM of \init_wait_count[1]_i_1__0\ : label is "soft_lutpair50"; attribute SOFT_HLUTNM of \init_wait_count[2]_i_1__0\ : label is "soft_lutpair53"; attribute SOFT_HLUTNM of \init_wait_count[3]_i_1__0\ : label is "soft_lutpair49"; attribute SOFT_HLUTNM of \init_wait_count[4]_i_1__0\ : label is "soft_lutpair49"; attribute SOFT_HLUTNM of \init_wait_count[6]_i_2__0\ : label is "soft_lutpair50"; attribute SOFT_HLUTNM of \init_wait_count[6]_i_3__0\ : label is "soft_lutpair53"; attribute SOFT_HLUTNM of \mmcm_lock_count[1]_i_1__0\ : label is "soft_lutpair55"; attribute SOFT_HLUTNM of \mmcm_lock_count[2]_i_1__0\ : label is "soft_lutpair55"; attribute SOFT_HLUTNM of \mmcm_lock_count[3]_i_1__0\ : label is "soft_lutpair44"; attribute SOFT_HLUTNM of \mmcm_lock_count[4]_i_1__0\ : label is "soft_lutpair44"; attribute SOFT_HLUTNM of \mmcm_lock_count[6]_i_1__0\ : label is "soft_lutpair56"; attribute SOFT_HLUTNM of \mmcm_lock_count[7]_i_3__0\ : label is "soft_lutpair56"; attribute SOFT_HLUTNM of reset_time_out_i_3 : label is "soft_lutpair46"; attribute SOFT_HLUTNM of reset_time_out_i_4 : label is "soft_lutpair45"; attribute SOFT_HLUTNM of \run_phase_alignment_int_i_1__0\ : label is "soft_lutpair46"; attribute SOFT_HLUTNM of rx_fsm_reset_done_int_i_5 : label is "soft_lutpair47"; attribute SOFT_HLUTNM of rx_fsm_reset_done_int_i_6 : label is "soft_lutpair45"; attribute SOFT_HLUTNM of time_out_1us_i_2 : label is "soft_lutpair52"; attribute SOFT_HLUTNM of time_out_2ms_i_1 : label is "soft_lutpair51"; attribute SOFT_HLUTNM of \time_out_2ms_i_2__0\ : label is "soft_lutpair52"; attribute SOFT_HLUTNM of time_tlock_max_i_1 : label is "soft_lutpair54"; attribute SOFT_HLUTNM of \wait_time_cnt[0]_i_1__0\ : label is "soft_lutpair57"; attribute SOFT_HLUTNM of \wait_time_cnt[1]_i_1__0\ : label is "soft_lutpair57"; attribute SOFT_HLUTNM of \wait_time_cnt[3]_i_1__0\ : label is "soft_lutpair48"; attribute SOFT_HLUTNM of \wait_time_cnt[4]_i_1__0\ : label is "soft_lutpair48"; begin data_in <= \^data_in\; gt0_gtrxreset_in1_out <= \^gt0_gtrxreset_in1_out\; gt0_rx_cdrlock_counter_reg_0_sn_1 <= gt0_rx_cdrlock_counter_reg_0_sp_1; gt0_rxuserrdy_t <= \^gt0_rxuserrdy_t\; \FSM_sequential_rx_state[0]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"2222AAAA00000C00" ) port map ( I0 => time_out_2ms_reg_n_0, I1 => rx_state(2), I2 => rx_state(3), I3 => time_tlock_max, I4 => reset_time_out_reg_n_0, I5 => rx_state(1), O => \FSM_sequential_rx_state[0]_i_2_n_0\ ); \FSM_sequential_rx_state[1]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"0000AABF000F0000" ) port map ( I0 => reset_time_out_reg_n_0, I1 => time_tlock_max, I2 => rx_state(2), I3 => rx_state(3), I4 => rx_state(1), I5 => rx_state(0), O => \FSM_sequential_rx_state[1]_i_3_n_0\ ); \FSM_sequential_rx_state[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000050FF2200" ) port map ( I0 => rx_state(1), I1 => time_out_2ms_reg_n_0, I2 => \FSM_sequential_rx_state[2]_i_2_n_0\, I3 => rx_state(0), I4 => rx_state(2), I5 => rx_state(3), O => \FSM_sequential_rx_state[2]_i_1_n_0\ ); \FSM_sequential_rx_state[2]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => reset_time_out_reg_n_0, I1 => time_tlock_max, O => \FSM_sequential_rx_state[2]_i_2_n_0\ ); \FSM_sequential_rx_state[3]_i_10\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => reset_time_out_reg_n_0, I1 => time_out_2ms_reg_n_0, O => \FSM_sequential_rx_state[3]_i_10_n_0\ ); \FSM_sequential_rx_state[3]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000050005300" ) port map ( I0 => \FSM_sequential_rx_state[3]_i_10_n_0\, I1 => \wait_time_cnt[6]_i_4__0_n_0\, I2 => rx_state(0), I3 => rx_state(1), I4 => \wait_time_cnt_reg__0\(6), I5 => rx_state(3), O => \FSM_sequential_rx_state[3]_i_3_n_0\ ); \FSM_sequential_rx_state[3]_i_7\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000023002F00" ) port map ( I0 => time_out_2ms_reg_n_0, I1 => rx_state(2), I2 => rx_state(1), I3 => rx_state(0), I4 => \FSM_sequential_rx_state[2]_i_2_n_0\, I5 => rx_state(3), O => \FSM_sequential_rx_state[3]_i_7_n_0\ ); \FSM_sequential_rx_state[3]_i_9\: unisim.vcomponents.LUT5 generic map( INIT => X"80800080" ) port map ( I0 => rx_state(0), I1 => rx_state(1), I2 => rx_state(2), I3 => time_out_2ms_reg_n_0, I4 => reset_time_out_reg_n_0, O => \FSM_sequential_rx_state[3]_i_9_n_0\ ); \FSM_sequential_rx_state_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => sync_data_valid_n_3, D => sync_data_valid_n_2, Q => rx_state(0), R => pma_reset ); \FSM_sequential_rx_state_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => sync_data_valid_n_3, D => sync_data_valid_n_1, Q => rx_state(1), R => pma_reset ); \FSM_sequential_rx_state_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => sync_data_valid_n_3, D => \FSM_sequential_rx_state[2]_i_1_n_0\, Q => rx_state(2), R => pma_reset ); \FSM_sequential_rx_state_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => sync_data_valid_n_3, D => sync_data_valid_n_0, Q => rx_state(3), R => pma_reset ); RXUSERRDY_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"FFFB4000" ) port map ( I0 => rx_state(3), I1 => rx_state(0), I2 => rx_state(2), I3 => rx_state(1), I4 => \^gt0_rxuserrdy_t\, O => RXUSERRDY_i_1_n_0 ); RXUSERRDY_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => RXUSERRDY_i_1_n_0, Q => \^gt0_rxuserrdy_t\, R => pma_reset ); check_tlock_max_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"FFFB0008" ) port map ( I0 => rx_state(2), I1 => rx_state(0), I2 => rx_state(1), I3 => rx_state(3), I4 => check_tlock_max_reg_n_0, O => check_tlock_max_i_1_n_0 ); check_tlock_max_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => check_tlock_max_i_1_n_0, Q => check_tlock_max_reg_n_0, R => pma_reset ); gt0_rx_cdrlocked_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"00000000AAAEAAAA" ) port map ( I0 => gt0_rx_cdrlocked_reg_0, I1 => gt0_rx_cdrlocked_reg_1, I2 => gt0_rx_cdrlock_counter_reg(0), I3 => gt0_rx_cdrlock_counter_reg(1), I4 => gt0_rx_cdrlocked_reg_2, I5 => \^gt0_gtrxreset_in1_out\, O => gt0_rx_cdrlocked_reg ); gtrxreset_i_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"FFEF0100" ) port map ( I0 => rx_state(3), I1 => rx_state(1), I2 => rx_state(2), I3 => rx_state(0), I4 => GTRXRESET, O => gtrxreset_i_i_1_n_0 ); gtrxreset_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => gtrxreset_i_i_1_n_0, Q => GTRXRESET, R => pma_reset ); gtxe2_i_i_2: unisim.vcomponents.LUT3 generic map( INIT => X"F8" ) port map ( I0 => \^data_in\, I1 => gt0_rx_cdrlock_counter_reg_0_sn_1, I2 => GTRXRESET, O => \^gt0_gtrxreset_in1_out\ ); \init_wait_count[0]_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \init_wait_count_reg__0\(0), O => \init_wait_count[0]_i_1__0_n_0\ ); \init_wait_count[1]_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \init_wait_count_reg__0\(0), I1 => \init_wait_count_reg__0\(1), O => \p_0_in__2\(1) ); \init_wait_count[2]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \init_wait_count_reg__0\(1), I1 => \init_wait_count_reg__0\(0), I2 => \init_wait_count_reg__0\(2), O => \p_0_in__2\(2) ); \init_wait_count[3]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \init_wait_count_reg__0\(1), I1 => \init_wait_count_reg__0\(2), I2 => \init_wait_count_reg__0\(0), I3 => \init_wait_count_reg__0\(3), O => \p_0_in__2\(3) ); \init_wait_count[4]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \init_wait_count_reg__0\(2), I1 => \init_wait_count_reg__0\(1), I2 => \init_wait_count_reg__0\(3), I3 => \init_wait_count_reg__0\(0), I4 => \init_wait_count_reg__0\(4), O => \p_0_in__2\(4) ); \init_wait_count[5]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \init_wait_count_reg__0\(2), I1 => \init_wait_count_reg__0\(1), I2 => \init_wait_count_reg__0\(3), I3 => \init_wait_count_reg__0\(0), I4 => \init_wait_count_reg__0\(4), I5 => \init_wait_count_reg__0\(5), O => \p_0_in__2\(5) ); \init_wait_count[6]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FEFF" ) port map ( I0 => \init_wait_count[6]_i_3__0_n_0\, I1 => \init_wait_count_reg__0\(0), I2 => \init_wait_count_reg__0\(4), I3 => \init_wait_count_reg__0\(6), O => \init_wait_count[6]_i_1__0_n_0\ ); \init_wait_count[6]_i_2__0\: unisim.vcomponents.LUT4 generic map( INIT => X"BF40" ) port map ( I0 => \init_wait_count[6]_i_3__0_n_0\, I1 => \init_wait_count_reg__0\(0), I2 => \init_wait_count_reg__0\(4), I3 => \init_wait_count_reg__0\(6), O => \p_0_in__2\(6) ); \init_wait_count[6]_i_3__0\: unisim.vcomponents.LUT4 generic map( INIT => X"7FFF" ) port map ( I0 => \init_wait_count_reg__0\(3), I1 => \init_wait_count_reg__0\(1), I2 => \init_wait_count_reg__0\(2), I3 => \init_wait_count_reg__0\(5), O => \init_wait_count[6]_i_3__0_n_0\ ); \init_wait_count_reg[0]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \init_wait_count[6]_i_1__0_n_0\, CLR => pma_reset, D => \init_wait_count[0]_i_1__0_n_0\, Q => \init_wait_count_reg__0\(0) ); \init_wait_count_reg[1]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \init_wait_count[6]_i_1__0_n_0\, CLR => pma_reset, D => \p_0_in__2\(1), Q => \init_wait_count_reg__0\(1) ); \init_wait_count_reg[2]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \init_wait_count[6]_i_1__0_n_0\, CLR => pma_reset, D => \p_0_in__2\(2), Q => \init_wait_count_reg__0\(2) ); \init_wait_count_reg[3]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \init_wait_count[6]_i_1__0_n_0\, CLR => pma_reset, D => \p_0_in__2\(3), Q => \init_wait_count_reg__0\(3) ); \init_wait_count_reg[4]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \init_wait_count[6]_i_1__0_n_0\, CLR => pma_reset, D => \p_0_in__2\(4), Q => \init_wait_count_reg__0\(4) ); \init_wait_count_reg[5]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \init_wait_count[6]_i_1__0_n_0\, CLR => pma_reset, D => \p_0_in__2\(5), Q => \init_wait_count_reg__0\(5) ); \init_wait_count_reg[6]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \init_wait_count[6]_i_1__0_n_0\, CLR => pma_reset, D => \p_0_in__2\(6), Q => \init_wait_count_reg__0\(6) ); \init_wait_done_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFF0010" ) port map ( I0 => \init_wait_count[6]_i_3__0_n_0\, I1 => \init_wait_count_reg__0\(4), I2 => \init_wait_count_reg__0\(6), I3 => \init_wait_count_reg__0\(0), I4 => init_wait_done_reg_n_0, O => \init_wait_done_i_1__0_n_0\ ); init_wait_done_reg: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', CLR => pma_reset, D => \init_wait_done_i_1__0_n_0\, Q => init_wait_done_reg_n_0 ); \mmcm_lock_count[0]_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \mmcm_lock_count_reg__0\(0), O => \p_0_in__3\(0) ); \mmcm_lock_count[1]_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \mmcm_lock_count_reg__0\(0), I1 => \mmcm_lock_count_reg__0\(1), O => \p_0_in__3\(1) ); \mmcm_lock_count[2]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \mmcm_lock_count_reg__0\(1), I1 => \mmcm_lock_count_reg__0\(0), I2 => \mmcm_lock_count_reg__0\(2), O => \mmcm_lock_count[2]_i_1__0_n_0\ ); \mmcm_lock_count[3]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \mmcm_lock_count_reg__0\(2), I1 => \mmcm_lock_count_reg__0\(0), I2 => \mmcm_lock_count_reg__0\(1), I3 => \mmcm_lock_count_reg__0\(3), O => \mmcm_lock_count[3]_i_1__0_n_0\ ); \mmcm_lock_count[4]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \mmcm_lock_count_reg__0\(3), I1 => \mmcm_lock_count_reg__0\(1), I2 => \mmcm_lock_count_reg__0\(0), I3 => \mmcm_lock_count_reg__0\(2), I4 => \mmcm_lock_count_reg__0\(4), O => \mmcm_lock_count[4]_i_1__0_n_0\ ); \mmcm_lock_count[5]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \mmcm_lock_count_reg__0\(4), I1 => \mmcm_lock_count_reg__0\(2), I2 => \mmcm_lock_count_reg__0\(0), I3 => \mmcm_lock_count_reg__0\(1), I4 => \mmcm_lock_count_reg__0\(3), I5 => \mmcm_lock_count_reg__0\(5), O => \mmcm_lock_count[5]_i_1__0_n_0\ ); \mmcm_lock_count[6]_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \mmcm_lock_count[7]_i_4__0_n_0\, I1 => \mmcm_lock_count_reg__0\(6), O => \mmcm_lock_count[6]_i_1__0_n_0\ ); \mmcm_lock_count[7]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"BF" ) port map ( I0 => \mmcm_lock_count[7]_i_4__0_n_0\, I1 => \mmcm_lock_count_reg__0\(6), I2 => \mmcm_lock_count_reg__0\(7), O => \mmcm_lock_count[7]_i_2__0_n_0\ ); \mmcm_lock_count[7]_i_3__0\: unisim.vcomponents.LUT3 generic map( INIT => X"D2" ) port map ( I0 => \mmcm_lock_count_reg__0\(6), I1 => \mmcm_lock_count[7]_i_4__0_n_0\, I2 => \mmcm_lock_count_reg__0\(7), O => \mmcm_lock_count[7]_i_3__0_n_0\ ); \mmcm_lock_count[7]_i_4__0\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFFFFFFFFFF" ) port map ( I0 => \mmcm_lock_count_reg__0\(4), I1 => \mmcm_lock_count_reg__0\(2), I2 => \mmcm_lock_count_reg__0\(0), I3 => \mmcm_lock_count_reg__0\(1), I4 => \mmcm_lock_count_reg__0\(3), I5 => \mmcm_lock_count_reg__0\(5), O => \mmcm_lock_count[7]_i_4__0_n_0\ ); \mmcm_lock_count_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \mmcm_lock_count[7]_i_2__0_n_0\, D => \p_0_in__3\(0), Q => \mmcm_lock_count_reg__0\(0), R => sync_mmcm_lock_reclocked_n_0 ); \mmcm_lock_count_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \mmcm_lock_count[7]_i_2__0_n_0\, D => \p_0_in__3\(1), Q => \mmcm_lock_count_reg__0\(1), R => sync_mmcm_lock_reclocked_n_0 ); \mmcm_lock_count_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \mmcm_lock_count[7]_i_2__0_n_0\, D => \mmcm_lock_count[2]_i_1__0_n_0\, Q => \mmcm_lock_count_reg__0\(2), R => sync_mmcm_lock_reclocked_n_0 ); \mmcm_lock_count_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \mmcm_lock_count[7]_i_2__0_n_0\, D => \mmcm_lock_count[3]_i_1__0_n_0\, Q => \mmcm_lock_count_reg__0\(3), R => sync_mmcm_lock_reclocked_n_0 ); \mmcm_lock_count_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \mmcm_lock_count[7]_i_2__0_n_0\, D => \mmcm_lock_count[4]_i_1__0_n_0\, Q => \mmcm_lock_count_reg__0\(4), R => sync_mmcm_lock_reclocked_n_0 ); \mmcm_lock_count_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \mmcm_lock_count[7]_i_2__0_n_0\, D => \mmcm_lock_count[5]_i_1__0_n_0\, Q => \mmcm_lock_count_reg__0\(5), R => sync_mmcm_lock_reclocked_n_0 ); \mmcm_lock_count_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \mmcm_lock_count[7]_i_2__0_n_0\, D => \mmcm_lock_count[6]_i_1__0_n_0\, Q => \mmcm_lock_count_reg__0\(6), R => sync_mmcm_lock_reclocked_n_0 ); \mmcm_lock_count_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \mmcm_lock_count[7]_i_2__0_n_0\, D => \mmcm_lock_count[7]_i_3__0_n_0\, Q => \mmcm_lock_count_reg__0\(7), R => sync_mmcm_lock_reclocked_n_0 ); mmcm_lock_reclocked_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => sync_mmcm_lock_reclocked_n_1, Q => mmcm_lock_reclocked, R => '0' ); reset_time_out_i_3: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => rx_state(2), I1 => rx_state(3), O => reset_time_out_i_3_n_0 ); reset_time_out_i_4: unisim.vcomponents.LUT5 generic map( INIT => X"34347674" ) port map ( I0 => rx_state(2), I1 => rx_state(3), I2 => rx_state(0), I3 => gt0_rx_cdrlocked_reg_0, I4 => rx_state(1), O => reset_time_out_i_4_n_0 ); reset_time_out_reg: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => sync_data_valid_n_4, Q => reset_time_out_reg_n_0, S => pma_reset ); \run_phase_alignment_int_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"FEFF0010" ) port map ( I0 => rx_state(2), I1 => rx_state(1), I2 => rx_state(3), I3 => rx_state(0), I4 => run_phase_alignment_int_reg_n_0, O => \run_phase_alignment_int_i_1__0_n_0\ ); run_phase_alignment_int_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => \run_phase_alignment_int_i_1__0_n_0\, Q => run_phase_alignment_int_reg_n_0, R => pma_reset ); run_phase_alignment_int_s3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk, CE => '1', D => data_out_0, Q => run_phase_alignment_int_s3_reg_n_0, R => '0' ); rx_fsm_reset_done_int_i_5: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => rx_state(1), I1 => rx_state(0), O => rx_fsm_reset_done_int_i_5_n_0 ); rx_fsm_reset_done_int_i_6: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => rx_state(3), I1 => rx_state(2), O => rx_fsm_reset_done_int_i_6_n_0 ); rx_fsm_reset_done_int_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => sync_data_valid_n_5, Q => \^data_in\, R => pma_reset ); rx_fsm_reset_done_int_s3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk, CE => '1', D => rx_fsm_reset_done_int_s2, Q => rx_fsm_reset_done_int_s3, R => '0' ); rxresetdone_s3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => rxresetdone_s2, Q => rxresetdone_s3, R => '0' ); sync_RXRESETDONE: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_10 port map ( data_out => rxresetdone_s2, data_sync_reg1_0 => data_sync_reg1, independent_clock_bufg => independent_clock_bufg ); sync_cplllock: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_11 port map ( \FSM_sequential_rx_state_reg[1]\ => sync_cplllock_n_0, Q(2 downto 0) => rx_state(3 downto 1), cplllock => cplllock, independent_clock_bufg => independent_clock_bufg, rxresetdone_s3 => rxresetdone_s3 ); sync_data_valid: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_12 port map ( D(2) => sync_data_valid_n_0, D(1) => sync_data_valid_n_1, D(0) => sync_data_valid_n_2, E(0) => sync_data_valid_n_3, \FSM_sequential_rx_state_reg[0]\ => \FSM_sequential_rx_state[3]_i_3_n_0\, \FSM_sequential_rx_state_reg[0]_0\ => \FSM_sequential_rx_state[3]_i_7_n_0\, \FSM_sequential_rx_state_reg[0]_1\ => gt0_rx_cdrlocked_reg_0, \FSM_sequential_rx_state_reg[0]_2\ => \FSM_sequential_rx_state[0]_i_2_n_0\, \FSM_sequential_rx_state_reg[0]_3\ => init_wait_done_reg_n_0, \FSM_sequential_rx_state_reg[1]\ => sync_data_valid_n_4, \FSM_sequential_rx_state_reg[1]_0\ => \FSM_sequential_rx_state[1]_i_3_n_0\, \FSM_sequential_rx_state_reg[3]\ => \FSM_sequential_rx_state[3]_i_9_n_0\, Q(3 downto 0) => rx_state(3 downto 0), data_in => \^data_in\, data_out => data_out, independent_clock_bufg => independent_clock_bufg, mmcm_lock_reclocked => mmcm_lock_reclocked, reset_time_out_reg => reset_time_out_reg_n_0, reset_time_out_reg_0 => sync_cplllock_n_0, reset_time_out_reg_1 => reset_time_out_i_3_n_0, reset_time_out_reg_2 => reset_time_out_i_4_n_0, rx_fsm_reset_done_int_reg => sync_data_valid_n_5, rx_fsm_reset_done_int_reg_0 => rx_fsm_reset_done_int_i_5_n_0, rx_fsm_reset_done_int_reg_1 => time_out_100us_reg_n_0, rx_fsm_reset_done_int_reg_2 => time_out_1us_reg_n_0, rx_fsm_reset_done_int_reg_3 => rx_fsm_reset_done_int_i_6_n_0, time_out_wait_bypass_s3 => time_out_wait_bypass_s3 ); sync_mmcm_lock_reclocked: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_13 port map ( Q(1 downto 0) => \mmcm_lock_count_reg__0\(7 downto 6), SR(0) => sync_mmcm_lock_reclocked_n_0, independent_clock_bufg => independent_clock_bufg, mmcm_lock_reclocked => mmcm_lock_reclocked, mmcm_lock_reclocked_reg => sync_mmcm_lock_reclocked_n_1, mmcm_lock_reclocked_reg_0 => \mmcm_lock_count[7]_i_4__0_n_0\, mmcm_locked => mmcm_locked ); sync_run_phase_alignment_int: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_14 port map ( data_in => run_phase_alignment_int_reg_n_0, data_out => data_out_0, userclk => userclk ); sync_time_out_wait_bypass: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_15 port map ( data_in => time_out_wait_bypass_reg_n_0, data_out => time_out_wait_bypass_s2, independent_clock_bufg => independent_clock_bufg ); sync_tx_fsm_reset_done_int: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_16 port map ( data_in => \^data_in\, data_out => rx_fsm_reset_done_int_s2, userclk => userclk ); time_out_100us_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF00000100" ) port map ( I0 => \time_out_counter[0]_i_4_n_0\, I1 => time_out_counter_reg(17), I2 => time_out_counter_reg(16), I3 => time_out_100us_i_2_n_0, I4 => time_out_100us_i_3_n_0, I5 => time_out_100us_reg_n_0, O => time_out_100us_i_1_n_0 ); time_out_100us_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000002000000000" ) port map ( I0 => time_out_counter_reg(10), I1 => time_out_counter_reg(12), I2 => time_out_counter_reg(5), I3 => time_out_counter_reg(7), I4 => time_out_counter_reg(18), I5 => time_out_counter_reg(14), O => time_out_100us_i_2_n_0 ); time_out_100us_i_3: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFFFE" ) port map ( I0 => time_out_counter_reg(4), I1 => time_out_counter_reg(0), I2 => time_out_counter_reg(1), I3 => time_out_counter_reg(15), I4 => time_out_counter_reg(13), O => time_out_100us_i_3_n_0 ); time_out_100us_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => time_out_100us_i_1_n_0, Q => time_out_100us_reg_n_0, R => reset_time_out_reg_n_0 ); time_out_1us_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF00100000" ) port map ( I0 => \time_out_counter[0]_i_3_n_0\, I1 => time_out_1us_i_2_n_0, I2 => time_out_counter_reg(3), I3 => time_out_counter_reg(2), I4 => time_out_1us_i_3_n_0, I5 => time_out_1us_reg_n_0, O => time_out_1us_i_1_n_0 ); time_out_1us_i_2: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => time_out_counter_reg(16), I1 => time_out_counter_reg(17), O => time_out_1us_i_2_n_0 ); time_out_1us_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000010" ) port map ( I0 => time_out_counter_reg(9), I1 => time_out_counter_reg(11), I2 => time_out_counter_reg(6), I3 => time_out_counter_reg(8), I4 => time_out_counter_reg(18), I5 => time_out_counter_reg(12), O => time_out_1us_i_3_n_0 ); time_out_1us_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => time_out_1us_i_1_n_0, Q => time_out_1us_reg_n_0, R => reset_time_out_reg_n_0 ); time_out_2ms_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"FF04" ) port map ( I0 => \time_out_counter[0]_i_3_n_0\, I1 => \time_out_2ms_i_2__0_n_0\, I2 => \time_out_counter[0]_i_4_n_0\, I3 => time_out_2ms_reg_n_0, O => time_out_2ms_i_1_n_0 ); \time_out_2ms_i_2__0\: unisim.vcomponents.LUT4 generic map( INIT => X"4000" ) port map ( I0 => time_out_counter_reg(16), I1 => time_out_counter_reg(12), I2 => time_out_counter_reg(18), I3 => time_out_counter_reg(17), O => \time_out_2ms_i_2__0_n_0\ ); time_out_2ms_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => time_out_2ms_i_1_n_0, Q => time_out_2ms_reg_n_0, R => reset_time_out_reg_n_0 ); \time_out_counter[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFBFFF" ) port map ( I0 => time_out_counter_reg(16), I1 => time_out_counter_reg(12), I2 => time_out_counter_reg(18), I3 => time_out_counter_reg(17), I4 => \time_out_counter[0]_i_3_n_0\, I5 => \time_out_counter[0]_i_4_n_0\, O => time_out_counter ); \time_out_counter[0]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFEFF" ) port map ( I0 => time_out_counter_reg(10), I1 => time_out_counter_reg(14), I2 => time_out_counter_reg(5), I3 => time_out_counter_reg(7), I4 => time_out_100us_i_3_n_0, O => \time_out_counter[0]_i_3_n_0\ ); \time_out_counter[0]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFEFFFFFF" ) port map ( I0 => time_out_counter_reg(2), I1 => time_out_counter_reg(3), I2 => time_out_counter_reg(8), I3 => time_out_counter_reg(9), I4 => time_out_counter_reg(11), I5 => time_out_counter_reg(6), O => \time_out_counter[0]_i_4_n_0\ ); \time_out_counter[0]_i_5\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => time_out_counter_reg(0), O => \time_out_counter[0]_i_5_n_0\ ); \time_out_counter_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => time_out_counter, D => \time_out_counter_reg[0]_i_2__0_n_7\, Q => time_out_counter_reg(0), R => reset_time_out_reg_n_0 ); \time_out_counter_reg[0]_i_2__0\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \time_out_counter_reg[0]_i_2__0_n_0\, CO(2) => \time_out_counter_reg[0]_i_2__0_n_1\, CO(1) => \time_out_counter_reg[0]_i_2__0_n_2\, CO(0) => \time_out_counter_reg[0]_i_2__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0001", O(3) => \time_out_counter_reg[0]_i_2__0_n_4\, O(2) => \time_out_counter_reg[0]_i_2__0_n_5\, O(1) => \time_out_counter_reg[0]_i_2__0_n_6\, O(0) => \time_out_counter_reg[0]_i_2__0_n_7\, S(3 downto 1) => time_out_counter_reg(3 downto 1), S(0) => \time_out_counter[0]_i_5_n_0\ ); \time_out_counter_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => time_out_counter, D => \time_out_counter_reg[8]_i_1__0_n_5\, Q => time_out_counter_reg(10), R => reset_time_out_reg_n_0 ); \time_out_counter_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => time_out_counter, D => \time_out_counter_reg[8]_i_1__0_n_4\, Q => time_out_counter_reg(11), R => reset_time_out_reg_n_0 ); \time_out_counter_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => time_out_counter, D => \time_out_counter_reg[12]_i_1__0_n_7\, Q => time_out_counter_reg(12), R => reset_time_out_reg_n_0 ); \time_out_counter_reg[12]_i_1__0\: unisim.vcomponents.CARRY4 port map ( CI => \time_out_counter_reg[8]_i_1__0_n_0\, CO(3) => \time_out_counter_reg[12]_i_1__0_n_0\, CO(2) => \time_out_counter_reg[12]_i_1__0_n_1\, CO(1) => \time_out_counter_reg[12]_i_1__0_n_2\, CO(0) => \time_out_counter_reg[12]_i_1__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \time_out_counter_reg[12]_i_1__0_n_4\, O(2) => \time_out_counter_reg[12]_i_1__0_n_5\, O(1) => \time_out_counter_reg[12]_i_1__0_n_6\, O(0) => \time_out_counter_reg[12]_i_1__0_n_7\, S(3 downto 0) => time_out_counter_reg(15 downto 12) ); \time_out_counter_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => time_out_counter, D => \time_out_counter_reg[12]_i_1__0_n_6\, Q => time_out_counter_reg(13), R => reset_time_out_reg_n_0 ); \time_out_counter_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => time_out_counter, D => \time_out_counter_reg[12]_i_1__0_n_5\, Q => time_out_counter_reg(14), R => reset_time_out_reg_n_0 ); \time_out_counter_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => time_out_counter, D => \time_out_counter_reg[12]_i_1__0_n_4\, Q => time_out_counter_reg(15), R => reset_time_out_reg_n_0 ); \time_out_counter_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => time_out_counter, D => \time_out_counter_reg[16]_i_1__0_n_7\, Q => time_out_counter_reg(16), R => reset_time_out_reg_n_0 ); \time_out_counter_reg[16]_i_1__0\: unisim.vcomponents.CARRY4 port map ( CI => \time_out_counter_reg[12]_i_1__0_n_0\, CO(3 downto 2) => \NLW_time_out_counter_reg[16]_i_1__0_CO_UNCONNECTED\(3 downto 2), CO(1) => \time_out_counter_reg[16]_i_1__0_n_2\, CO(0) => \time_out_counter_reg[16]_i_1__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \NLW_time_out_counter_reg[16]_i_1__0_O_UNCONNECTED\(3), O(2) => \time_out_counter_reg[16]_i_1__0_n_5\, O(1) => \time_out_counter_reg[16]_i_1__0_n_6\, O(0) => \time_out_counter_reg[16]_i_1__0_n_7\, S(3) => '0', S(2 downto 0) => time_out_counter_reg(18 downto 16) ); \time_out_counter_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => time_out_counter, D => \time_out_counter_reg[16]_i_1__0_n_6\, Q => time_out_counter_reg(17), R => reset_time_out_reg_n_0 ); \time_out_counter_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => time_out_counter, D => \time_out_counter_reg[16]_i_1__0_n_5\, Q => time_out_counter_reg(18), R => reset_time_out_reg_n_0 ); \time_out_counter_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => time_out_counter, D => \time_out_counter_reg[0]_i_2__0_n_6\, Q => time_out_counter_reg(1), R => reset_time_out_reg_n_0 ); \time_out_counter_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => time_out_counter, D => \time_out_counter_reg[0]_i_2__0_n_5\, Q => time_out_counter_reg(2), R => reset_time_out_reg_n_0 ); \time_out_counter_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => time_out_counter, D => \time_out_counter_reg[0]_i_2__0_n_4\, Q => time_out_counter_reg(3), R => reset_time_out_reg_n_0 ); \time_out_counter_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => time_out_counter, D => \time_out_counter_reg[4]_i_1__0_n_7\, Q => time_out_counter_reg(4), R => reset_time_out_reg_n_0 ); \time_out_counter_reg[4]_i_1__0\: unisim.vcomponents.CARRY4 port map ( CI => \time_out_counter_reg[0]_i_2__0_n_0\, CO(3) => \time_out_counter_reg[4]_i_1__0_n_0\, CO(2) => \time_out_counter_reg[4]_i_1__0_n_1\, CO(1) => \time_out_counter_reg[4]_i_1__0_n_2\, CO(0) => \time_out_counter_reg[4]_i_1__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \time_out_counter_reg[4]_i_1__0_n_4\, O(2) => \time_out_counter_reg[4]_i_1__0_n_5\, O(1) => \time_out_counter_reg[4]_i_1__0_n_6\, O(0) => \time_out_counter_reg[4]_i_1__0_n_7\, S(3 downto 0) => time_out_counter_reg(7 downto 4) ); \time_out_counter_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => time_out_counter, D => \time_out_counter_reg[4]_i_1__0_n_6\, Q => time_out_counter_reg(5), R => reset_time_out_reg_n_0 ); \time_out_counter_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => time_out_counter, D => \time_out_counter_reg[4]_i_1__0_n_5\, Q => time_out_counter_reg(6), R => reset_time_out_reg_n_0 ); \time_out_counter_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => time_out_counter, D => \time_out_counter_reg[4]_i_1__0_n_4\, Q => time_out_counter_reg(7), R => reset_time_out_reg_n_0 ); \time_out_counter_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => time_out_counter, D => \time_out_counter_reg[8]_i_1__0_n_7\, Q => time_out_counter_reg(8), R => reset_time_out_reg_n_0 ); \time_out_counter_reg[8]_i_1__0\: unisim.vcomponents.CARRY4 port map ( CI => \time_out_counter_reg[4]_i_1__0_n_0\, CO(3) => \time_out_counter_reg[8]_i_1__0_n_0\, CO(2) => \time_out_counter_reg[8]_i_1__0_n_1\, CO(1) => \time_out_counter_reg[8]_i_1__0_n_2\, CO(0) => \time_out_counter_reg[8]_i_1__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \time_out_counter_reg[8]_i_1__0_n_4\, O(2) => \time_out_counter_reg[8]_i_1__0_n_5\, O(1) => \time_out_counter_reg[8]_i_1__0_n_6\, O(0) => \time_out_counter_reg[8]_i_1__0_n_7\, S(3 downto 0) => time_out_counter_reg(11 downto 8) ); \time_out_counter_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => time_out_counter, D => \time_out_counter_reg[8]_i_1__0_n_6\, Q => time_out_counter_reg(9), R => reset_time_out_reg_n_0 ); \time_out_wait_bypass_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"AB00" ) port map ( I0 => time_out_wait_bypass_reg_n_0, I1 => rx_fsm_reset_done_int_s3, I2 => \wait_bypass_count[0]_i_4__0_n_0\, I3 => run_phase_alignment_int_s3_reg_n_0, O => \time_out_wait_bypass_i_1__0_n_0\ ); time_out_wait_bypass_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk, CE => '1', D => \time_out_wait_bypass_i_1__0_n_0\, Q => time_out_wait_bypass_reg_n_0, R => '0' ); time_out_wait_bypass_s3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => time_out_wait_bypass_s2, Q => time_out_wait_bypass_s3, R => '0' ); time_tlock_max1_carry: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => time_tlock_max1_carry_n_0, CO(2) => time_tlock_max1_carry_n_1, CO(1) => time_tlock_max1_carry_n_2, CO(0) => time_tlock_max1_carry_n_3, CYINIT => '0', DI(3) => time_tlock_max1_carry_i_1_n_0, DI(2) => time_tlock_max1_carry_i_2_n_0, DI(1) => time_tlock_max1_carry_i_3_n_0, DI(0) => time_tlock_max1_carry_i_4_n_0, O(3 downto 0) => NLW_time_tlock_max1_carry_O_UNCONNECTED(3 downto 0), S(3) => time_tlock_max1_carry_i_5_n_0, S(2) => time_tlock_max1_carry_i_6_n_0, S(1) => time_tlock_max1_carry_i_7_n_0, S(0) => time_tlock_max1_carry_i_8_n_0 ); \time_tlock_max1_carry__0\: unisim.vcomponents.CARRY4 port map ( CI => time_tlock_max1_carry_n_0, CO(3) => \time_tlock_max1_carry__0_n_0\, CO(2) => \time_tlock_max1_carry__0_n_1\, CO(1) => \time_tlock_max1_carry__0_n_2\, CO(0) => \time_tlock_max1_carry__0_n_3\, CYINIT => '0', DI(3) => time_out_counter_reg(15), DI(2) => \time_tlock_max1_carry__0_i_1_n_0\, DI(1) => '0', DI(0) => \time_tlock_max1_carry__0_i_2_n_0\, O(3 downto 0) => \NLW_time_tlock_max1_carry__0_O_UNCONNECTED\(3 downto 0), S(3) => \time_tlock_max1_carry__0_i_3_n_0\, S(2) => \time_tlock_max1_carry__0_i_4_n_0\, S(1) => \time_tlock_max1_carry__0_i_5_n_0\, S(0) => \time_tlock_max1_carry__0_i_6_n_0\ ); \time_tlock_max1_carry__0_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => time_out_counter_reg(13), I1 => time_out_counter_reg(12), O => \time_tlock_max1_carry__0_i_1_n_0\ ); \time_tlock_max1_carry__0_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => time_out_counter_reg(8), I1 => time_out_counter_reg(9), O => \time_tlock_max1_carry__0_i_2_n_0\ ); \time_tlock_max1_carry__0_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => time_out_counter_reg(14), I1 => time_out_counter_reg(15), O => \time_tlock_max1_carry__0_i_3_n_0\ ); \time_tlock_max1_carry__0_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => time_out_counter_reg(12), I1 => time_out_counter_reg(13), O => \time_tlock_max1_carry__0_i_4_n_0\ ); \time_tlock_max1_carry__0_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => time_out_counter_reg(10), I1 => time_out_counter_reg(11), O => \time_tlock_max1_carry__0_i_5_n_0\ ); \time_tlock_max1_carry__0_i_6\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => time_out_counter_reg(9), I1 => time_out_counter_reg(8), O => \time_tlock_max1_carry__0_i_6_n_0\ ); \time_tlock_max1_carry__1\: unisim.vcomponents.CARRY4 port map ( CI => \time_tlock_max1_carry__0_n_0\, CO(3 downto 2) => \NLW_time_tlock_max1_carry__1_CO_UNCONNECTED\(3 downto 2), CO(1) => time_tlock_max1, CO(0) => \time_tlock_max1_carry__1_n_3\, CYINIT => '0', DI(3 downto 2) => B"00", DI(1) => time_out_counter_reg(18), DI(0) => \time_tlock_max1_carry__1_i_1_n_0\, O(3 downto 0) => \NLW_time_tlock_max1_carry__1_O_UNCONNECTED\(3 downto 0), S(3 downto 2) => B"00", S(1) => \time_tlock_max1_carry__1_i_2_n_0\, S(0) => \time_tlock_max1_carry__1_i_3_n_0\ ); \time_tlock_max1_carry__1_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => time_out_counter_reg(16), I1 => time_out_counter_reg(17), O => \time_tlock_max1_carry__1_i_1_n_0\ ); \time_tlock_max1_carry__1_i_2\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => time_out_counter_reg(18), O => \time_tlock_max1_carry__1_i_2_n_0\ ); \time_tlock_max1_carry__1_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => time_out_counter_reg(17), I1 => time_out_counter_reg(16), O => \time_tlock_max1_carry__1_i_3_n_0\ ); time_tlock_max1_carry_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => time_out_counter_reg(7), I1 => time_out_counter_reg(6), O => time_tlock_max1_carry_i_1_n_0 ); time_tlock_max1_carry_i_2: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => time_out_counter_reg(5), I1 => time_out_counter_reg(4), O => time_tlock_max1_carry_i_2_n_0 ); time_tlock_max1_carry_i_3: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => time_out_counter_reg(2), I1 => time_out_counter_reg(3), O => time_tlock_max1_carry_i_3_n_0 ); time_tlock_max1_carry_i_4: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => time_out_counter_reg(0), I1 => time_out_counter_reg(1), O => time_tlock_max1_carry_i_4_n_0 ); time_tlock_max1_carry_i_5: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => time_out_counter_reg(6), I1 => time_out_counter_reg(7), O => time_tlock_max1_carry_i_5_n_0 ); time_tlock_max1_carry_i_6: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => time_out_counter_reg(5), I1 => time_out_counter_reg(4), O => time_tlock_max1_carry_i_6_n_0 ); time_tlock_max1_carry_i_7: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => time_out_counter_reg(3), I1 => time_out_counter_reg(2), O => time_tlock_max1_carry_i_7_n_0 ); time_tlock_max1_carry_i_8: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => time_out_counter_reg(1), I1 => time_out_counter_reg(0), O => time_tlock_max1_carry_i_8_n_0 ); time_tlock_max_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"F8" ) port map ( I0 => check_tlock_max_reg_n_0, I1 => time_tlock_max1, I2 => time_tlock_max, O => time_tlock_max_i_1_n_0 ); time_tlock_max_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => time_tlock_max_i_1_n_0, Q => time_tlock_max, R => reset_time_out_reg_n_0 ); \wait_bypass_count[0]_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => run_phase_alignment_int_s3_reg_n_0, O => \wait_bypass_count[0]_i_1__0_n_0\ ); \wait_bypass_count[0]_i_2__0\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \wait_bypass_count[0]_i_4__0_n_0\, I1 => rx_fsm_reset_done_int_s3, O => \wait_bypass_count[0]_i_2__0_n_0\ ); \wait_bypass_count[0]_i_4__0\: unisim.vcomponents.LUT5 generic map( INIT => X"BFFFFFFF" ) port map ( I0 => \wait_bypass_count[0]_i_6__0_n_0\, I1 => wait_bypass_count_reg(1), I2 => wait_bypass_count_reg(8), I3 => wait_bypass_count_reg(0), I4 => \wait_bypass_count[0]_i_7__0_n_0\, O => \wait_bypass_count[0]_i_4__0_n_0\ ); \wait_bypass_count[0]_i_5__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => wait_bypass_count_reg(0), O => \wait_bypass_count[0]_i_5__0_n_0\ ); \wait_bypass_count[0]_i_6__0\: unisim.vcomponents.LUT4 generic map( INIT => X"EFFF" ) port map ( I0 => wait_bypass_count_reg(3), I1 => wait_bypass_count_reg(5), I2 => wait_bypass_count_reg(9), I3 => wait_bypass_count_reg(7), O => \wait_bypass_count[0]_i_6__0_n_0\ ); \wait_bypass_count[0]_i_7__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000008" ) port map ( I0 => wait_bypass_count_reg(2), I1 => wait_bypass_count_reg(12), I2 => wait_bypass_count_reg(4), I3 => wait_bypass_count_reg(10), I4 => wait_bypass_count_reg(6), I5 => wait_bypass_count_reg(11), O => \wait_bypass_count[0]_i_7__0_n_0\ ); \wait_bypass_count_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => \wait_bypass_count[0]_i_2__0_n_0\, D => \wait_bypass_count_reg[0]_i_3__0_n_7\, Q => wait_bypass_count_reg(0), R => \wait_bypass_count[0]_i_1__0_n_0\ ); \wait_bypass_count_reg[0]_i_3__0\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \wait_bypass_count_reg[0]_i_3__0_n_0\, CO(2) => \wait_bypass_count_reg[0]_i_3__0_n_1\, CO(1) => \wait_bypass_count_reg[0]_i_3__0_n_2\, CO(0) => \wait_bypass_count_reg[0]_i_3__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0001", O(3) => \wait_bypass_count_reg[0]_i_3__0_n_4\, O(2) => \wait_bypass_count_reg[0]_i_3__0_n_5\, O(1) => \wait_bypass_count_reg[0]_i_3__0_n_6\, O(0) => \wait_bypass_count_reg[0]_i_3__0_n_7\, S(3 downto 1) => wait_bypass_count_reg(3 downto 1), S(0) => \wait_bypass_count[0]_i_5__0_n_0\ ); \wait_bypass_count_reg[10]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => \wait_bypass_count[0]_i_2__0_n_0\, D => \wait_bypass_count_reg[8]_i_1__0_n_5\, Q => wait_bypass_count_reg(10), R => \wait_bypass_count[0]_i_1__0_n_0\ ); \wait_bypass_count_reg[11]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => \wait_bypass_count[0]_i_2__0_n_0\, D => \wait_bypass_count_reg[8]_i_1__0_n_4\, Q => wait_bypass_count_reg(11), R => \wait_bypass_count[0]_i_1__0_n_0\ ); \wait_bypass_count_reg[12]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => \wait_bypass_count[0]_i_2__0_n_0\, D => \wait_bypass_count_reg[12]_i_1__0_n_7\, Q => wait_bypass_count_reg(12), R => \wait_bypass_count[0]_i_1__0_n_0\ ); \wait_bypass_count_reg[12]_i_1__0\: unisim.vcomponents.CARRY4 port map ( CI => \wait_bypass_count_reg[8]_i_1__0_n_0\, CO(3 downto 0) => \NLW_wait_bypass_count_reg[12]_i_1__0_CO_UNCONNECTED\(3 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 1) => \NLW_wait_bypass_count_reg[12]_i_1__0_O_UNCONNECTED\(3 downto 1), O(0) => \wait_bypass_count_reg[12]_i_1__0_n_7\, S(3 downto 1) => B"000", S(0) => wait_bypass_count_reg(12) ); \wait_bypass_count_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => \wait_bypass_count[0]_i_2__0_n_0\, D => \wait_bypass_count_reg[0]_i_3__0_n_6\, Q => wait_bypass_count_reg(1), R => \wait_bypass_count[0]_i_1__0_n_0\ ); \wait_bypass_count_reg[2]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => \wait_bypass_count[0]_i_2__0_n_0\, D => \wait_bypass_count_reg[0]_i_3__0_n_5\, Q => wait_bypass_count_reg(2), R => \wait_bypass_count[0]_i_1__0_n_0\ ); \wait_bypass_count_reg[3]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => \wait_bypass_count[0]_i_2__0_n_0\, D => \wait_bypass_count_reg[0]_i_3__0_n_4\, Q => wait_bypass_count_reg(3), R => \wait_bypass_count[0]_i_1__0_n_0\ ); \wait_bypass_count_reg[4]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => \wait_bypass_count[0]_i_2__0_n_0\, D => \wait_bypass_count_reg[4]_i_1__0_n_7\, Q => wait_bypass_count_reg(4), R => \wait_bypass_count[0]_i_1__0_n_0\ ); \wait_bypass_count_reg[4]_i_1__0\: unisim.vcomponents.CARRY4 port map ( CI => \wait_bypass_count_reg[0]_i_3__0_n_0\, CO(3) => \wait_bypass_count_reg[4]_i_1__0_n_0\, CO(2) => \wait_bypass_count_reg[4]_i_1__0_n_1\, CO(1) => \wait_bypass_count_reg[4]_i_1__0_n_2\, CO(0) => \wait_bypass_count_reg[4]_i_1__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \wait_bypass_count_reg[4]_i_1__0_n_4\, O(2) => \wait_bypass_count_reg[4]_i_1__0_n_5\, O(1) => \wait_bypass_count_reg[4]_i_1__0_n_6\, O(0) => \wait_bypass_count_reg[4]_i_1__0_n_7\, S(3 downto 0) => wait_bypass_count_reg(7 downto 4) ); \wait_bypass_count_reg[5]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => \wait_bypass_count[0]_i_2__0_n_0\, D => \wait_bypass_count_reg[4]_i_1__0_n_6\, Q => wait_bypass_count_reg(5), R => \wait_bypass_count[0]_i_1__0_n_0\ ); \wait_bypass_count_reg[6]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => \wait_bypass_count[0]_i_2__0_n_0\, D => \wait_bypass_count_reg[4]_i_1__0_n_5\, Q => wait_bypass_count_reg(6), R => \wait_bypass_count[0]_i_1__0_n_0\ ); \wait_bypass_count_reg[7]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => \wait_bypass_count[0]_i_2__0_n_0\, D => \wait_bypass_count_reg[4]_i_1__0_n_4\, Q => wait_bypass_count_reg(7), R => \wait_bypass_count[0]_i_1__0_n_0\ ); \wait_bypass_count_reg[8]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => \wait_bypass_count[0]_i_2__0_n_0\, D => \wait_bypass_count_reg[8]_i_1__0_n_7\, Q => wait_bypass_count_reg(8), R => \wait_bypass_count[0]_i_1__0_n_0\ ); \wait_bypass_count_reg[8]_i_1__0\: unisim.vcomponents.CARRY4 port map ( CI => \wait_bypass_count_reg[4]_i_1__0_n_0\, CO(3) => \wait_bypass_count_reg[8]_i_1__0_n_0\, CO(2) => \wait_bypass_count_reg[8]_i_1__0_n_1\, CO(1) => \wait_bypass_count_reg[8]_i_1__0_n_2\, CO(0) => \wait_bypass_count_reg[8]_i_1__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \wait_bypass_count_reg[8]_i_1__0_n_4\, O(2) => \wait_bypass_count_reg[8]_i_1__0_n_5\, O(1) => \wait_bypass_count_reg[8]_i_1__0_n_6\, O(0) => \wait_bypass_count_reg[8]_i_1__0_n_7\, S(3 downto 0) => wait_bypass_count_reg(11 downto 8) ); \wait_bypass_count_reg[9]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => \wait_bypass_count[0]_i_2__0_n_0\, D => \wait_bypass_count_reg[8]_i_1__0_n_6\, Q => wait_bypass_count_reg(9), R => \wait_bypass_count[0]_i_1__0_n_0\ ); \wait_time_cnt[0]_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \wait_time_cnt_reg__0\(0), O => \wait_time_cnt0__0\(0) ); \wait_time_cnt[1]_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \wait_time_cnt_reg__0\(0), I1 => \wait_time_cnt_reg__0\(1), O => \wait_time_cnt[1]_i_1__0_n_0\ ); \wait_time_cnt[2]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"E1" ) port map ( I0 => \wait_time_cnt_reg__0\(1), I1 => \wait_time_cnt_reg__0\(0), I2 => \wait_time_cnt_reg__0\(2), O => \wait_time_cnt[2]_i_1__0_n_0\ ); \wait_time_cnt[3]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FE01" ) port map ( I0 => \wait_time_cnt_reg__0\(2), I1 => \wait_time_cnt_reg__0\(0), I2 => \wait_time_cnt_reg__0\(1), I3 => \wait_time_cnt_reg__0\(3), O => \wait_time_cnt[3]_i_1__0_n_0\ ); \wait_time_cnt[4]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0001" ) port map ( I0 => \wait_time_cnt_reg__0\(3), I1 => \wait_time_cnt_reg__0\(1), I2 => \wait_time_cnt_reg__0\(0), I3 => \wait_time_cnt_reg__0\(2), I4 => \wait_time_cnt_reg__0\(4), O => \wait_time_cnt[4]_i_1__0_n_0\ ); \wait_time_cnt[5]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFE00000001" ) port map ( I0 => \wait_time_cnt_reg__0\(4), I1 => \wait_time_cnt_reg__0\(2), I2 => \wait_time_cnt_reg__0\(0), I3 => \wait_time_cnt_reg__0\(1), I4 => \wait_time_cnt_reg__0\(3), I5 => \wait_time_cnt_reg__0\(5), O => \wait_time_cnt[5]_i_1__0_n_0\ ); \wait_time_cnt[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => rx_state(0), I1 => rx_state(1), I2 => rx_state(3), O => \wait_time_cnt[6]_i_1_n_0\ ); \wait_time_cnt[6]_i_2__0\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \wait_time_cnt[6]_i_4__0_n_0\, I1 => \wait_time_cnt_reg__0\(6), O => \wait_time_cnt[6]_i_2__0_n_0\ ); \wait_time_cnt[6]_i_3__0\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \wait_time_cnt[6]_i_4__0_n_0\, I1 => \wait_time_cnt_reg__0\(6), O => \wait_time_cnt[6]_i_3__0_n_0\ ); \wait_time_cnt[6]_i_4__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFE" ) port map ( I0 => \wait_time_cnt_reg__0\(4), I1 => \wait_time_cnt_reg__0\(2), I2 => \wait_time_cnt_reg__0\(0), I3 => \wait_time_cnt_reg__0\(1), I4 => \wait_time_cnt_reg__0\(3), I5 => \wait_time_cnt_reg__0\(5), O => \wait_time_cnt[6]_i_4__0_n_0\ ); \wait_time_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => independent_clock_bufg, CE => \wait_time_cnt[6]_i_2__0_n_0\, D => \wait_time_cnt0__0\(0), Q => \wait_time_cnt_reg__0\(0), R => \wait_time_cnt[6]_i_1_n_0\ ); \wait_time_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => independent_clock_bufg, CE => \wait_time_cnt[6]_i_2__0_n_0\, D => \wait_time_cnt[1]_i_1__0_n_0\, Q => \wait_time_cnt_reg__0\(1), R => \wait_time_cnt[6]_i_1_n_0\ ); \wait_time_cnt_reg[2]\: unisim.vcomponents.FDSE port map ( C => independent_clock_bufg, CE => \wait_time_cnt[6]_i_2__0_n_0\, D => \wait_time_cnt[2]_i_1__0_n_0\, Q => \wait_time_cnt_reg__0\(2), S => \wait_time_cnt[6]_i_1_n_0\ ); \wait_time_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => independent_clock_bufg, CE => \wait_time_cnt[6]_i_2__0_n_0\, D => \wait_time_cnt[3]_i_1__0_n_0\, Q => \wait_time_cnt_reg__0\(3), R => \wait_time_cnt[6]_i_1_n_0\ ); \wait_time_cnt_reg[4]\: unisim.vcomponents.FDRE port map ( C => independent_clock_bufg, CE => \wait_time_cnt[6]_i_2__0_n_0\, D => \wait_time_cnt[4]_i_1__0_n_0\, Q => \wait_time_cnt_reg__0\(4), R => \wait_time_cnt[6]_i_1_n_0\ ); \wait_time_cnt_reg[5]\: unisim.vcomponents.FDSE port map ( C => independent_clock_bufg, CE => \wait_time_cnt[6]_i_2__0_n_0\, D => \wait_time_cnt[5]_i_1__0_n_0\, Q => \wait_time_cnt_reg__0\(5), S => \wait_time_cnt[6]_i_1_n_0\ ); \wait_time_cnt_reg[6]\: unisim.vcomponents.FDSE port map ( C => independent_clock_bufg, CE => \wait_time_cnt[6]_i_2__0_n_0\, D => \wait_time_cnt[6]_i_3__0_n_0\, Q => \wait_time_cnt_reg__0\(6), S => \wait_time_cnt[6]_i_1_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_TX_STARTUP_FSM is port ( mmcm_reset : out STD_LOGIC; gt0_cpllreset_t : out STD_LOGIC; data_in : out STD_LOGIC; gt0_txuserrdy_t : out STD_LOGIC; gt0_gttxreset_in0_out : out STD_LOGIC; independent_clock_bufg : in STD_LOGIC; userclk : in STD_LOGIC; pma_reset : in STD_LOGIC; data_sync_reg1 : in STD_LOGIC; gt0_cpllrefclklost_i : in STD_LOGIC; data_sync_reg1_0 : in STD_LOGIC; mmcm_locked : in STD_LOGIC; cplllock : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_TX_STARTUP_FSM; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_TX_STARTUP_FSM is signal CPLL_RESET_i_1_n_0 : STD_LOGIC; signal CPLL_RESET_i_2_n_0 : STD_LOGIC; signal \FSM_sequential_tx_state[0]_i_1_n_0\ : STD_LOGIC; signal \FSM_sequential_tx_state[0]_i_2_n_0\ : STD_LOGIC; signal \FSM_sequential_tx_state[0]_i_3_n_0\ : STD_LOGIC; signal \FSM_sequential_tx_state[1]_i_1_n_0\ : STD_LOGIC; signal \FSM_sequential_tx_state[2]_i_1_n_0\ : STD_LOGIC; signal \FSM_sequential_tx_state[2]_i_2_n_0\ : STD_LOGIC; signal \FSM_sequential_tx_state[3]_i_2_n_0\ : STD_LOGIC; signal \FSM_sequential_tx_state[3]_i_3_n_0\ : STD_LOGIC; signal \FSM_sequential_tx_state[3]_i_4_n_0\ : STD_LOGIC; signal \FSM_sequential_tx_state[3]_i_6_n_0\ : STD_LOGIC; signal \FSM_sequential_tx_state[3]_i_7_n_0\ : STD_LOGIC; signal \FSM_sequential_tx_state[3]_i_8_n_0\ : STD_LOGIC; signal GTTXRESET : STD_LOGIC; signal MMCM_RESET_i_1_n_0 : STD_LOGIC; signal TXUSERRDY_i_1_n_0 : STD_LOGIC; signal clear : STD_LOGIC; signal \^data_in\ : STD_LOGIC; signal data_out : STD_LOGIC; signal \^gt0_cpllreset_t\ : STD_LOGIC; signal \^gt0_txuserrdy_t\ : STD_LOGIC; signal gttxreset_i_i_1_n_0 : STD_LOGIC; signal \init_wait_count[0]_i_1_n_0\ : STD_LOGIC; signal \init_wait_count[6]_i_1_n_0\ : STD_LOGIC; signal \init_wait_count[6]_i_3_n_0\ : STD_LOGIC; signal \init_wait_count_reg__0\ : STD_LOGIC_VECTOR ( 6 downto 0 ); signal init_wait_done_i_1_n_0 : STD_LOGIC; signal init_wait_done_reg_n_0 : STD_LOGIC; signal \mmcm_lock_count[2]_i_1_n_0\ : STD_LOGIC; signal \mmcm_lock_count[3]_i_1_n_0\ : STD_LOGIC; signal \mmcm_lock_count[4]_i_1_n_0\ : STD_LOGIC; signal \mmcm_lock_count[5]_i_1_n_0\ : STD_LOGIC; signal \mmcm_lock_count[6]_i_1_n_0\ : STD_LOGIC; signal \mmcm_lock_count[7]_i_2_n_0\ : STD_LOGIC; signal \mmcm_lock_count[7]_i_3_n_0\ : STD_LOGIC; signal \mmcm_lock_count[7]_i_4_n_0\ : STD_LOGIC; signal \mmcm_lock_count_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal mmcm_lock_reclocked : STD_LOGIC; signal \^mmcm_reset\ : STD_LOGIC; signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 6 downto 1 ); signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal pll_reset_asserted_i_1_n_0 : STD_LOGIC; signal pll_reset_asserted_i_2_n_0 : STD_LOGIC; signal pll_reset_asserted_reg_n_0 : STD_LOGIC; signal refclk_stable_count : STD_LOGIC; signal \refclk_stable_count[0]_i_3_n_0\ : STD_LOGIC; signal \refclk_stable_count[0]_i_4_n_0\ : STD_LOGIC; signal \refclk_stable_count[0]_i_5_n_0\ : STD_LOGIC; signal \refclk_stable_count[0]_i_6_n_0\ : STD_LOGIC; signal \refclk_stable_count[0]_i_7_n_0\ : STD_LOGIC; signal \refclk_stable_count[0]_i_8_n_0\ : STD_LOGIC; signal \refclk_stable_count[0]_i_9_n_0\ : STD_LOGIC; signal refclk_stable_count_reg : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \refclk_stable_count_reg[0]_i_2_n_0\ : STD_LOGIC; signal \refclk_stable_count_reg[0]_i_2_n_1\ : STD_LOGIC; signal \refclk_stable_count_reg[0]_i_2_n_2\ : STD_LOGIC; signal \refclk_stable_count_reg[0]_i_2_n_3\ : STD_LOGIC; signal \refclk_stable_count_reg[0]_i_2_n_4\ : STD_LOGIC; signal \refclk_stable_count_reg[0]_i_2_n_5\ : STD_LOGIC; signal \refclk_stable_count_reg[0]_i_2_n_6\ : STD_LOGIC; signal \refclk_stable_count_reg[0]_i_2_n_7\ : STD_LOGIC; signal \refclk_stable_count_reg[12]_i_1_n_0\ : STD_LOGIC; signal \refclk_stable_count_reg[12]_i_1_n_1\ : STD_LOGIC; signal \refclk_stable_count_reg[12]_i_1_n_2\ : STD_LOGIC; signal \refclk_stable_count_reg[12]_i_1_n_3\ : STD_LOGIC; signal \refclk_stable_count_reg[12]_i_1_n_4\ : STD_LOGIC; signal \refclk_stable_count_reg[12]_i_1_n_5\ : STD_LOGIC; signal \refclk_stable_count_reg[12]_i_1_n_6\ : STD_LOGIC; signal \refclk_stable_count_reg[12]_i_1_n_7\ : STD_LOGIC; signal \refclk_stable_count_reg[16]_i_1_n_0\ : STD_LOGIC; signal \refclk_stable_count_reg[16]_i_1_n_1\ : STD_LOGIC; signal \refclk_stable_count_reg[16]_i_1_n_2\ : STD_LOGIC; signal \refclk_stable_count_reg[16]_i_1_n_3\ : STD_LOGIC; signal \refclk_stable_count_reg[16]_i_1_n_4\ : STD_LOGIC; signal \refclk_stable_count_reg[16]_i_1_n_5\ : STD_LOGIC; signal \refclk_stable_count_reg[16]_i_1_n_6\ : STD_LOGIC; signal \refclk_stable_count_reg[16]_i_1_n_7\ : STD_LOGIC; signal \refclk_stable_count_reg[20]_i_1_n_0\ : STD_LOGIC; signal \refclk_stable_count_reg[20]_i_1_n_1\ : STD_LOGIC; signal \refclk_stable_count_reg[20]_i_1_n_2\ : STD_LOGIC; signal \refclk_stable_count_reg[20]_i_1_n_3\ : STD_LOGIC; signal \refclk_stable_count_reg[20]_i_1_n_4\ : STD_LOGIC; signal \refclk_stable_count_reg[20]_i_1_n_5\ : STD_LOGIC; signal \refclk_stable_count_reg[20]_i_1_n_6\ : STD_LOGIC; signal \refclk_stable_count_reg[20]_i_1_n_7\ : STD_LOGIC; signal \refclk_stable_count_reg[24]_i_1_n_0\ : STD_LOGIC; signal \refclk_stable_count_reg[24]_i_1_n_1\ : STD_LOGIC; signal \refclk_stable_count_reg[24]_i_1_n_2\ : STD_LOGIC; signal \refclk_stable_count_reg[24]_i_1_n_3\ : STD_LOGIC; signal \refclk_stable_count_reg[24]_i_1_n_4\ : STD_LOGIC; signal \refclk_stable_count_reg[24]_i_1_n_5\ : STD_LOGIC; signal \refclk_stable_count_reg[24]_i_1_n_6\ : STD_LOGIC; signal \refclk_stable_count_reg[24]_i_1_n_7\ : STD_LOGIC; signal \refclk_stable_count_reg[28]_i_1_n_1\ : STD_LOGIC; signal \refclk_stable_count_reg[28]_i_1_n_2\ : STD_LOGIC; signal \refclk_stable_count_reg[28]_i_1_n_3\ : STD_LOGIC; signal \refclk_stable_count_reg[28]_i_1_n_4\ : STD_LOGIC; signal \refclk_stable_count_reg[28]_i_1_n_5\ : STD_LOGIC; signal \refclk_stable_count_reg[28]_i_1_n_6\ : STD_LOGIC; signal \refclk_stable_count_reg[28]_i_1_n_7\ : STD_LOGIC; signal \refclk_stable_count_reg[4]_i_1_n_0\ : STD_LOGIC; signal \refclk_stable_count_reg[4]_i_1_n_1\ : STD_LOGIC; signal \refclk_stable_count_reg[4]_i_1_n_2\ : STD_LOGIC; signal \refclk_stable_count_reg[4]_i_1_n_3\ : STD_LOGIC; signal \refclk_stable_count_reg[4]_i_1_n_4\ : STD_LOGIC; signal \refclk_stable_count_reg[4]_i_1_n_5\ : STD_LOGIC; signal \refclk_stable_count_reg[4]_i_1_n_6\ : STD_LOGIC; signal \refclk_stable_count_reg[4]_i_1_n_7\ : STD_LOGIC; signal \refclk_stable_count_reg[8]_i_1_n_0\ : STD_LOGIC; signal \refclk_stable_count_reg[8]_i_1_n_1\ : STD_LOGIC; signal \refclk_stable_count_reg[8]_i_1_n_2\ : STD_LOGIC; signal \refclk_stable_count_reg[8]_i_1_n_3\ : STD_LOGIC; signal \refclk_stable_count_reg[8]_i_1_n_4\ : STD_LOGIC; signal \refclk_stable_count_reg[8]_i_1_n_5\ : STD_LOGIC; signal \refclk_stable_count_reg[8]_i_1_n_6\ : STD_LOGIC; signal \refclk_stable_count_reg[8]_i_1_n_7\ : STD_LOGIC; signal refclk_stable_i_1_n_0 : STD_LOGIC; signal refclk_stable_i_2_n_0 : STD_LOGIC; signal refclk_stable_i_3_n_0 : STD_LOGIC; signal refclk_stable_i_4_n_0 : STD_LOGIC; signal refclk_stable_i_5_n_0 : STD_LOGIC; signal refclk_stable_i_6_n_0 : STD_LOGIC; signal refclk_stable_reg_n_0 : STD_LOGIC; signal reset_time_out : STD_LOGIC; signal \reset_time_out_i_2__0_n_0\ : STD_LOGIC; signal run_phase_alignment_int_i_1_n_0 : STD_LOGIC; signal run_phase_alignment_int_reg_n_0 : STD_LOGIC; signal run_phase_alignment_int_s3 : STD_LOGIC; signal sel : STD_LOGIC; signal sync_cplllock_n_0 : STD_LOGIC; signal sync_cplllock_n_1 : STD_LOGIC; signal sync_mmcm_lock_reclocked_n_0 : STD_LOGIC; signal sync_mmcm_lock_reclocked_n_1 : STD_LOGIC; signal \time_out_2ms_i_1__0_n_0\ : STD_LOGIC; signal time_out_2ms_i_2_n_0 : STD_LOGIC; signal time_out_2ms_reg_n_0 : STD_LOGIC; signal time_out_500us_i_1_n_0 : STD_LOGIC; signal time_out_500us_i_2_n_0 : STD_LOGIC; signal time_out_500us_reg_n_0 : STD_LOGIC; signal time_out_counter : STD_LOGIC; signal \time_out_counter[0]_i_3__0_n_0\ : STD_LOGIC; signal \time_out_counter[0]_i_4__0_n_0\ : STD_LOGIC; signal \time_out_counter[0]_i_5__0_n_0\ : STD_LOGIC; signal \time_out_counter[0]_i_6_n_0\ : STD_LOGIC; signal \time_out_counter[0]_i_7_n_0\ : STD_LOGIC; signal \time_out_counter[0]_i_8_n_0\ : STD_LOGIC; signal time_out_counter_reg : STD_LOGIC_VECTOR ( 18 downto 0 ); signal \time_out_counter_reg[0]_i_2_n_0\ : STD_LOGIC; signal \time_out_counter_reg[0]_i_2_n_1\ : STD_LOGIC; signal \time_out_counter_reg[0]_i_2_n_2\ : STD_LOGIC; signal \time_out_counter_reg[0]_i_2_n_3\ : STD_LOGIC; signal \time_out_counter_reg[0]_i_2_n_4\ : STD_LOGIC; signal \time_out_counter_reg[0]_i_2_n_5\ : STD_LOGIC; signal \time_out_counter_reg[0]_i_2_n_6\ : STD_LOGIC; signal \time_out_counter_reg[0]_i_2_n_7\ : STD_LOGIC; signal \time_out_counter_reg[12]_i_1_n_0\ : STD_LOGIC; signal \time_out_counter_reg[12]_i_1_n_1\ : STD_LOGIC; signal \time_out_counter_reg[12]_i_1_n_2\ : STD_LOGIC; signal \time_out_counter_reg[12]_i_1_n_3\ : STD_LOGIC; signal \time_out_counter_reg[12]_i_1_n_4\ : STD_LOGIC; signal \time_out_counter_reg[12]_i_1_n_5\ : STD_LOGIC; signal \time_out_counter_reg[12]_i_1_n_6\ : STD_LOGIC; signal \time_out_counter_reg[12]_i_1_n_7\ : STD_LOGIC; signal \time_out_counter_reg[16]_i_1_n_2\ : STD_LOGIC; signal \time_out_counter_reg[16]_i_1_n_3\ : STD_LOGIC; signal \time_out_counter_reg[16]_i_1_n_5\ : STD_LOGIC; signal \time_out_counter_reg[16]_i_1_n_6\ : STD_LOGIC; signal \time_out_counter_reg[16]_i_1_n_7\ : STD_LOGIC; signal \time_out_counter_reg[4]_i_1_n_0\ : STD_LOGIC; signal \time_out_counter_reg[4]_i_1_n_1\ : STD_LOGIC; signal \time_out_counter_reg[4]_i_1_n_2\ : STD_LOGIC; signal \time_out_counter_reg[4]_i_1_n_3\ : STD_LOGIC; signal \time_out_counter_reg[4]_i_1_n_4\ : STD_LOGIC; signal \time_out_counter_reg[4]_i_1_n_5\ : STD_LOGIC; signal \time_out_counter_reg[4]_i_1_n_6\ : STD_LOGIC; signal \time_out_counter_reg[4]_i_1_n_7\ : STD_LOGIC; signal \time_out_counter_reg[8]_i_1_n_0\ : STD_LOGIC; signal \time_out_counter_reg[8]_i_1_n_1\ : STD_LOGIC; signal \time_out_counter_reg[8]_i_1_n_2\ : STD_LOGIC; signal \time_out_counter_reg[8]_i_1_n_3\ : STD_LOGIC; signal \time_out_counter_reg[8]_i_1_n_4\ : STD_LOGIC; signal \time_out_counter_reg[8]_i_1_n_5\ : STD_LOGIC; signal \time_out_counter_reg[8]_i_1_n_6\ : STD_LOGIC; signal \time_out_counter_reg[8]_i_1_n_7\ : STD_LOGIC; signal time_out_wait_bypass_i_1_n_0 : STD_LOGIC; signal time_out_wait_bypass_reg_n_0 : STD_LOGIC; signal time_out_wait_bypass_s2 : STD_LOGIC; signal time_out_wait_bypass_s3 : STD_LOGIC; signal \time_tlock_max_i_1__0_n_0\ : STD_LOGIC; signal time_tlock_max_i_2_n_0 : STD_LOGIC; signal time_tlock_max_i_3_n_0 : STD_LOGIC; signal time_tlock_max_reg_n_0 : STD_LOGIC; signal tx_fsm_reset_done_int_i_1_n_0 : STD_LOGIC; signal tx_fsm_reset_done_int_s2 : STD_LOGIC; signal tx_fsm_reset_done_int_s3 : STD_LOGIC; signal tx_state : STD_LOGIC_VECTOR ( 3 downto 0 ); signal txresetdone_s2 : STD_LOGIC; signal txresetdone_s3 : STD_LOGIC; signal \wait_bypass_count[0]_i_2_n_0\ : STD_LOGIC; signal \wait_bypass_count[0]_i_4_n_0\ : STD_LOGIC; signal \wait_bypass_count[0]_i_5_n_0\ : STD_LOGIC; signal \wait_bypass_count[0]_i_6_n_0\ : STD_LOGIC; signal \wait_bypass_count[0]_i_7_n_0\ : STD_LOGIC; signal \wait_bypass_count[0]_i_8_n_0\ : STD_LOGIC; signal wait_bypass_count_reg : STD_LOGIC_VECTOR ( 16 downto 0 ); signal \wait_bypass_count_reg[0]_i_3_n_0\ : STD_LOGIC; signal \wait_bypass_count_reg[0]_i_3_n_1\ : STD_LOGIC; signal \wait_bypass_count_reg[0]_i_3_n_2\ : STD_LOGIC; signal \wait_bypass_count_reg[0]_i_3_n_3\ : STD_LOGIC; signal \wait_bypass_count_reg[0]_i_3_n_4\ : STD_LOGIC; signal \wait_bypass_count_reg[0]_i_3_n_5\ : STD_LOGIC; signal \wait_bypass_count_reg[0]_i_3_n_6\ : STD_LOGIC; signal \wait_bypass_count_reg[0]_i_3_n_7\ : STD_LOGIC; signal \wait_bypass_count_reg[12]_i_1_n_0\ : STD_LOGIC; signal \wait_bypass_count_reg[12]_i_1_n_1\ : STD_LOGIC; signal \wait_bypass_count_reg[12]_i_1_n_2\ : STD_LOGIC; signal \wait_bypass_count_reg[12]_i_1_n_3\ : STD_LOGIC; signal \wait_bypass_count_reg[12]_i_1_n_4\ : STD_LOGIC; signal \wait_bypass_count_reg[12]_i_1_n_5\ : STD_LOGIC; signal \wait_bypass_count_reg[12]_i_1_n_6\ : STD_LOGIC; signal \wait_bypass_count_reg[12]_i_1_n_7\ : STD_LOGIC; signal \wait_bypass_count_reg[16]_i_1_n_7\ : STD_LOGIC; signal \wait_bypass_count_reg[4]_i_1_n_0\ : STD_LOGIC; signal \wait_bypass_count_reg[4]_i_1_n_1\ : STD_LOGIC; signal \wait_bypass_count_reg[4]_i_1_n_2\ : STD_LOGIC; signal \wait_bypass_count_reg[4]_i_1_n_3\ : STD_LOGIC; signal \wait_bypass_count_reg[4]_i_1_n_4\ : STD_LOGIC; signal \wait_bypass_count_reg[4]_i_1_n_5\ : STD_LOGIC; signal \wait_bypass_count_reg[4]_i_1_n_6\ : STD_LOGIC; signal \wait_bypass_count_reg[4]_i_1_n_7\ : STD_LOGIC; signal \wait_bypass_count_reg[8]_i_1_n_0\ : STD_LOGIC; signal \wait_bypass_count_reg[8]_i_1_n_1\ : STD_LOGIC; signal \wait_bypass_count_reg[8]_i_1_n_2\ : STD_LOGIC; signal \wait_bypass_count_reg[8]_i_1_n_3\ : STD_LOGIC; signal \wait_bypass_count_reg[8]_i_1_n_4\ : STD_LOGIC; signal \wait_bypass_count_reg[8]_i_1_n_5\ : STD_LOGIC; signal \wait_bypass_count_reg[8]_i_1_n_6\ : STD_LOGIC; signal \wait_bypass_count_reg[8]_i_1_n_7\ : STD_LOGIC; signal wait_time_cnt0 : STD_LOGIC_VECTOR ( 0 to 0 ); signal wait_time_cnt0_0 : STD_LOGIC; signal \wait_time_cnt[1]_i_1_n_0\ : STD_LOGIC; signal \wait_time_cnt[2]_i_1_n_0\ : STD_LOGIC; signal \wait_time_cnt[3]_i_1_n_0\ : STD_LOGIC; signal \wait_time_cnt[4]_i_1_n_0\ : STD_LOGIC; signal \wait_time_cnt[5]_i_1_n_0\ : STD_LOGIC; signal \wait_time_cnt[6]_i_3_n_0\ : STD_LOGIC; signal \wait_time_cnt[6]_i_4_n_0\ : STD_LOGIC; signal \wait_time_cnt_reg__0\ : STD_LOGIC_VECTOR ( 6 downto 0 ); signal \NLW_refclk_stable_count_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); signal \NLW_time_out_counter_reg[16]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_time_out_counter_reg[16]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); signal \NLW_wait_bypass_count_reg[16]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_wait_bypass_count_reg[16]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of CPLL_RESET_i_2 : label is "soft_lutpair65"; attribute SOFT_HLUTNM of \FSM_sequential_tx_state[0]_i_2\ : label is "soft_lutpair62"; attribute SOFT_HLUTNM of \FSM_sequential_tx_state[0]_i_3\ : label is "soft_lutpair66"; attribute SOFT_HLUTNM of \FSM_sequential_tx_state[1]_i_1\ : label is "soft_lutpair61"; attribute SOFT_HLUTNM of \FSM_sequential_tx_state[3]_i_2\ : label is "soft_lutpair62"; attribute SOFT_HLUTNM of \FSM_sequential_tx_state[3]_i_7\ : label is "soft_lutpair59"; attribute SOFT_HLUTNM of \FSM_sequential_tx_state[3]_i_8\ : label is "soft_lutpair61"; attribute FSM_ENCODED_STATES : string; attribute FSM_ENCODED_STATES of \FSM_sequential_tx_state_reg[0]\ : label is "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101"; attribute FSM_ENCODED_STATES of \FSM_sequential_tx_state_reg[1]\ : label is "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101"; attribute FSM_ENCODED_STATES of \FSM_sequential_tx_state_reg[2]\ : label is "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101"; attribute FSM_ENCODED_STATES of \FSM_sequential_tx_state_reg[3]\ : label is "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101"; attribute SOFT_HLUTNM of MMCM_RESET_i_1 : label is "soft_lutpair59"; attribute SOFT_HLUTNM of TXUSERRDY_i_1 : label is "soft_lutpair64"; attribute SOFT_HLUTNM of gttxreset_i_i_1 : label is "soft_lutpair65"; attribute SOFT_HLUTNM of \init_wait_count[1]_i_1\ : label is "soft_lutpair69"; attribute SOFT_HLUTNM of \init_wait_count[2]_i_1\ : label is "soft_lutpair70"; attribute SOFT_HLUTNM of \init_wait_count[3]_i_1\ : label is "soft_lutpair63"; attribute SOFT_HLUTNM of \init_wait_count[4]_i_1\ : label is "soft_lutpair63"; attribute SOFT_HLUTNM of \init_wait_count[6]_i_2\ : label is "soft_lutpair69"; attribute SOFT_HLUTNM of \init_wait_count[6]_i_3\ : label is "soft_lutpair70"; attribute SOFT_HLUTNM of \mmcm_lock_count[1]_i_1\ : label is "soft_lutpair71"; attribute SOFT_HLUTNM of \mmcm_lock_count[2]_i_1\ : label is "soft_lutpair71"; attribute SOFT_HLUTNM of \mmcm_lock_count[3]_i_1\ : label is "soft_lutpair68"; attribute SOFT_HLUTNM of \mmcm_lock_count[4]_i_1\ : label is "soft_lutpair68"; attribute SOFT_HLUTNM of \mmcm_lock_count[6]_i_1\ : label is "soft_lutpair72"; attribute SOFT_HLUTNM of \mmcm_lock_count[7]_i_3\ : label is "soft_lutpair72"; attribute SOFT_HLUTNM of pll_reset_asserted_i_2 : label is "soft_lutpair64"; attribute SOFT_HLUTNM of \time_out_counter[0]_i_7\ : label is "soft_lutpair60"; attribute SOFT_HLUTNM of time_tlock_max_i_3 : label is "soft_lutpair60"; attribute SOFT_HLUTNM of tx_fsm_reset_done_int_i_1 : label is "soft_lutpair66"; attribute SOFT_HLUTNM of \wait_time_cnt[0]_i_1\ : label is "soft_lutpair73"; attribute SOFT_HLUTNM of \wait_time_cnt[1]_i_1\ : label is "soft_lutpair73"; attribute SOFT_HLUTNM of \wait_time_cnt[3]_i_1\ : label is "soft_lutpair67"; attribute SOFT_HLUTNM of \wait_time_cnt[4]_i_1\ : label is "soft_lutpair67"; begin data_in <= \^data_in\; gt0_cpllreset_t <= \^gt0_cpllreset_t\; gt0_txuserrdy_t <= \^gt0_txuserrdy_t\; mmcm_reset <= \^mmcm_reset\; CPLL_RESET_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFF1F0000001F" ) port map ( I0 => pll_reset_asserted_reg_n_0, I1 => gt0_cpllrefclklost_i, I2 => refclk_stable_reg_n_0, I3 => CPLL_RESET_i_2_n_0, I4 => \FSM_sequential_tx_state[0]_i_3_n_0\, I5 => \^gt0_cpllreset_t\, O => CPLL_RESET_i_1_n_0 ); CPLL_RESET_i_2: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => tx_state(1), I1 => tx_state(2), O => CPLL_RESET_i_2_n_0 ); CPLL_RESET_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => CPLL_RESET_i_1_n_0, Q => \^gt0_cpllreset_t\, R => pma_reset ); \FSM_sequential_tx_state[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F3FFF3F0F5F0F5F0" ) port map ( I0 => \FSM_sequential_tx_state[2]_i_2_n_0\, I1 => \FSM_sequential_tx_state[0]_i_2_n_0\, I2 => \FSM_sequential_tx_state[0]_i_3_n_0\, I3 => tx_state(2), I4 => time_out_2ms_reg_n_0, I5 => tx_state(1), O => \FSM_sequential_tx_state[0]_i_1_n_0\ ); \FSM_sequential_tx_state[0]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => reset_time_out, I1 => time_out_500us_reg_n_0, O => \FSM_sequential_tx_state[0]_i_2_n_0\ ); \FSM_sequential_tx_state[0]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => tx_state(3), I1 => tx_state(0), O => \FSM_sequential_tx_state[0]_i_3_n_0\ ); \FSM_sequential_tx_state[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"005A001A" ) port map ( I0 => tx_state(1), I1 => tx_state(2), I2 => tx_state(0), I3 => tx_state(3), I4 => \FSM_sequential_tx_state[2]_i_2_n_0\, O => \FSM_sequential_tx_state[1]_i_1_n_0\ ); \FSM_sequential_tx_state[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"04000C0C06020C0C" ) port map ( I0 => tx_state(1), I1 => tx_state(2), I2 => tx_state(3), I3 => \FSM_sequential_tx_state[2]_i_2_n_0\, I4 => tx_state(0), I5 => time_out_2ms_reg_n_0, O => \FSM_sequential_tx_state[2]_i_1_n_0\ ); \FSM_sequential_tx_state[2]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"FD" ) port map ( I0 => time_tlock_max_reg_n_0, I1 => reset_time_out, I2 => mmcm_lock_reclocked, O => \FSM_sequential_tx_state[2]_i_2_n_0\ ); \FSM_sequential_tx_state[3]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"F4FF4444" ) port map ( I0 => time_out_wait_bypass_s3, I1 => tx_state(3), I2 => reset_time_out, I3 => time_out_500us_reg_n_0, I4 => \FSM_sequential_tx_state[3]_i_8_n_0\, O => \FSM_sequential_tx_state[3]_i_2_n_0\ ); \FSM_sequential_tx_state[3]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"00BA000000000000" ) port map ( I0 => txresetdone_s3, I1 => reset_time_out, I2 => time_out_500us_reg_n_0, I3 => \FSM_sequential_tx_state[0]_i_3_n_0\, I4 => tx_state(2), I5 => tx_state(1), O => \FSM_sequential_tx_state[3]_i_3_n_0\ ); \FSM_sequential_tx_state[3]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000300FF00AA" ) port map ( I0 => init_wait_done_reg_n_0, I1 => \wait_time_cnt[6]_i_4_n_0\, I2 => \wait_time_cnt_reg__0\(6), I3 => tx_state(0), I4 => tx_state(3), I5 => CPLL_RESET_i_2_n_0, O => \FSM_sequential_tx_state[3]_i_4_n_0\ ); \FSM_sequential_tx_state[3]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"0404040400040000" ) port map ( I0 => tx_state(1), I1 => tx_state(2), I2 => \FSM_sequential_tx_state[0]_i_3_n_0\, I3 => reset_time_out, I4 => time_tlock_max_reg_n_0, I5 => mmcm_lock_reclocked, O => \FSM_sequential_tx_state[3]_i_6_n_0\ ); \FSM_sequential_tx_state[3]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"1000" ) port map ( I0 => tx_state(2), I1 => tx_state(3), I2 => tx_state(0), I3 => tx_state(1), O => \FSM_sequential_tx_state[3]_i_7_n_0\ ); \FSM_sequential_tx_state[3]_i_8\: unisim.vcomponents.LUT4 generic map( INIT => X"4000" ) port map ( I0 => tx_state(3), I1 => tx_state(0), I2 => tx_state(2), I3 => tx_state(1), O => \FSM_sequential_tx_state[3]_i_8_n_0\ ); \FSM_sequential_tx_state_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => sync_cplllock_n_0, D => \FSM_sequential_tx_state[0]_i_1_n_0\, Q => tx_state(0), R => pma_reset ); \FSM_sequential_tx_state_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => sync_cplllock_n_0, D => \FSM_sequential_tx_state[1]_i_1_n_0\, Q => tx_state(1), R => pma_reset ); \FSM_sequential_tx_state_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => sync_cplllock_n_0, D => \FSM_sequential_tx_state[2]_i_1_n_0\, Q => tx_state(2), R => pma_reset ); \FSM_sequential_tx_state_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => sync_cplllock_n_0, D => \FSM_sequential_tx_state[3]_i_2_n_0\, Q => tx_state(3), R => pma_reset ); MMCM_RESET_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"FFF70004" ) port map ( I0 => tx_state(2), I1 => tx_state(0), I2 => tx_state(3), I3 => tx_state(1), I4 => \^mmcm_reset\, O => MMCM_RESET_i_1_n_0 ); MMCM_RESET_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => independent_clock_bufg, CE => '1', D => MMCM_RESET_i_1_n_0, Q => \^mmcm_reset\, R => pma_reset ); TXUSERRDY_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"FFFD2000" ) port map ( I0 => tx_state(0), I1 => tx_state(3), I2 => tx_state(2), I3 => tx_state(1), I4 => \^gt0_txuserrdy_t\, O => TXUSERRDY_i_1_n_0 ); TXUSERRDY_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => TXUSERRDY_i_1_n_0, Q => \^gt0_txuserrdy_t\, R => pma_reset ); gttxreset_i_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"FFEF0100" ) port map ( I0 => tx_state(3), I1 => tx_state(1), I2 => tx_state(2), I3 => tx_state(0), I4 => GTTXRESET, O => gttxreset_i_i_1_n_0 ); gttxreset_i_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => gttxreset_i_i_1_n_0, Q => GTTXRESET, R => pma_reset ); gtxe2_i_i_3: unisim.vcomponents.LUT3 generic map( INIT => X"EA" ) port map ( I0 => GTTXRESET, I1 => \^data_in\, I2 => data_sync_reg1, O => gt0_gttxreset_in0_out ); \init_wait_count[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \init_wait_count_reg__0\(0), O => \init_wait_count[0]_i_1_n_0\ ); \init_wait_count[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \init_wait_count_reg__0\(0), I1 => \init_wait_count_reg__0\(1), O => \p_0_in__0\(1) ); \init_wait_count[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \init_wait_count_reg__0\(0), I1 => \init_wait_count_reg__0\(1), I2 => \init_wait_count_reg__0\(2), O => \p_0_in__0\(2) ); \init_wait_count[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \init_wait_count_reg__0\(1), I1 => \init_wait_count_reg__0\(2), I2 => \init_wait_count_reg__0\(0), I3 => \init_wait_count_reg__0\(3), O => \p_0_in__0\(3) ); \init_wait_count[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \init_wait_count_reg__0\(2), I1 => \init_wait_count_reg__0\(1), I2 => \init_wait_count_reg__0\(3), I3 => \init_wait_count_reg__0\(0), I4 => \init_wait_count_reg__0\(4), O => \p_0_in__0\(4) ); \init_wait_count[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \init_wait_count_reg__0\(2), I1 => \init_wait_count_reg__0\(1), I2 => \init_wait_count_reg__0\(3), I3 => \init_wait_count_reg__0\(0), I4 => \init_wait_count_reg__0\(4), I5 => \init_wait_count_reg__0\(5), O => \p_0_in__0\(5) ); \init_wait_count[6]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"FEFF" ) port map ( I0 => \init_wait_count[6]_i_3_n_0\, I1 => \init_wait_count_reg__0\(0), I2 => \init_wait_count_reg__0\(4), I3 => \init_wait_count_reg__0\(6), O => \init_wait_count[6]_i_1_n_0\ ); \init_wait_count[6]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"BF40" ) port map ( I0 => \init_wait_count[6]_i_3_n_0\, I1 => \init_wait_count_reg__0\(0), I2 => \init_wait_count_reg__0\(4), I3 => \init_wait_count_reg__0\(6), O => \p_0_in__0\(6) ); \init_wait_count[6]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"7FFF" ) port map ( I0 => \init_wait_count_reg__0\(3), I1 => \init_wait_count_reg__0\(1), I2 => \init_wait_count_reg__0\(2), I3 => \init_wait_count_reg__0\(5), O => \init_wait_count[6]_i_3_n_0\ ); \init_wait_count_reg[0]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \init_wait_count[6]_i_1_n_0\, CLR => pma_reset, D => \init_wait_count[0]_i_1_n_0\, Q => \init_wait_count_reg__0\(0) ); \init_wait_count_reg[1]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \init_wait_count[6]_i_1_n_0\, CLR => pma_reset, D => \p_0_in__0\(1), Q => \init_wait_count_reg__0\(1) ); \init_wait_count_reg[2]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \init_wait_count[6]_i_1_n_0\, CLR => pma_reset, D => \p_0_in__0\(2), Q => \init_wait_count_reg__0\(2) ); \init_wait_count_reg[3]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \init_wait_count[6]_i_1_n_0\, CLR => pma_reset, D => \p_0_in__0\(3), Q => \init_wait_count_reg__0\(3) ); \init_wait_count_reg[4]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \init_wait_count[6]_i_1_n_0\, CLR => pma_reset, D => \p_0_in__0\(4), Q => \init_wait_count_reg__0\(4) ); \init_wait_count_reg[5]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \init_wait_count[6]_i_1_n_0\, CLR => pma_reset, D => \p_0_in__0\(5), Q => \init_wait_count_reg__0\(5) ); \init_wait_count_reg[6]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \init_wait_count[6]_i_1_n_0\, CLR => pma_reset, D => \p_0_in__0\(6), Q => \init_wait_count_reg__0\(6) ); init_wait_done_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"FFFF0010" ) port map ( I0 => \init_wait_count[6]_i_3_n_0\, I1 => \init_wait_count_reg__0\(4), I2 => \init_wait_count_reg__0\(6), I3 => \init_wait_count_reg__0\(0), I4 => init_wait_done_reg_n_0, O => init_wait_done_i_1_n_0 ); init_wait_done_reg: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', CLR => pma_reset, D => init_wait_done_i_1_n_0, Q => init_wait_done_reg_n_0 ); \mmcm_lock_count[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \mmcm_lock_count_reg__0\(0), O => \p_0_in__1\(0) ); \mmcm_lock_count[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \mmcm_lock_count_reg__0\(0), I1 => \mmcm_lock_count_reg__0\(1), O => \p_0_in__1\(1) ); \mmcm_lock_count[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \mmcm_lock_count_reg__0\(1), I1 => \mmcm_lock_count_reg__0\(0), I2 => \mmcm_lock_count_reg__0\(2), O => \mmcm_lock_count[2]_i_1_n_0\ ); \mmcm_lock_count[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \mmcm_lock_count_reg__0\(2), I1 => \mmcm_lock_count_reg__0\(0), I2 => \mmcm_lock_count_reg__0\(1), I3 => \mmcm_lock_count_reg__0\(3), O => \mmcm_lock_count[3]_i_1_n_0\ ); \mmcm_lock_count[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \mmcm_lock_count_reg__0\(3), I1 => \mmcm_lock_count_reg__0\(1), I2 => \mmcm_lock_count_reg__0\(0), I3 => \mmcm_lock_count_reg__0\(2), I4 => \mmcm_lock_count_reg__0\(4), O => \mmcm_lock_count[4]_i_1_n_0\ ); \mmcm_lock_count[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \mmcm_lock_count_reg__0\(4), I1 => \mmcm_lock_count_reg__0\(2), I2 => \mmcm_lock_count_reg__0\(0), I3 => \mmcm_lock_count_reg__0\(1), I4 => \mmcm_lock_count_reg__0\(3), I5 => \mmcm_lock_count_reg__0\(5), O => \mmcm_lock_count[5]_i_1_n_0\ ); \mmcm_lock_count[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \mmcm_lock_count[7]_i_4_n_0\, I1 => \mmcm_lock_count_reg__0\(6), O => \mmcm_lock_count[6]_i_1_n_0\ ); \mmcm_lock_count[7]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"BF" ) port map ( I0 => \mmcm_lock_count[7]_i_4_n_0\, I1 => \mmcm_lock_count_reg__0\(6), I2 => \mmcm_lock_count_reg__0\(7), O => \mmcm_lock_count[7]_i_2_n_0\ ); \mmcm_lock_count[7]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"D2" ) port map ( I0 => \mmcm_lock_count_reg__0\(6), I1 => \mmcm_lock_count[7]_i_4_n_0\, I2 => \mmcm_lock_count_reg__0\(7), O => \mmcm_lock_count[7]_i_3_n_0\ ); \mmcm_lock_count[7]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFFFFFFFFFF" ) port map ( I0 => \mmcm_lock_count_reg__0\(4), I1 => \mmcm_lock_count_reg__0\(2), I2 => \mmcm_lock_count_reg__0\(0), I3 => \mmcm_lock_count_reg__0\(1), I4 => \mmcm_lock_count_reg__0\(3), I5 => \mmcm_lock_count_reg__0\(5), O => \mmcm_lock_count[7]_i_4_n_0\ ); \mmcm_lock_count_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \mmcm_lock_count[7]_i_2_n_0\, D => \p_0_in__1\(0), Q => \mmcm_lock_count_reg__0\(0), R => sync_mmcm_lock_reclocked_n_0 ); \mmcm_lock_count_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \mmcm_lock_count[7]_i_2_n_0\, D => \p_0_in__1\(1), Q => \mmcm_lock_count_reg__0\(1), R => sync_mmcm_lock_reclocked_n_0 ); \mmcm_lock_count_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \mmcm_lock_count[7]_i_2_n_0\, D => \mmcm_lock_count[2]_i_1_n_0\, Q => \mmcm_lock_count_reg__0\(2), R => sync_mmcm_lock_reclocked_n_0 ); \mmcm_lock_count_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \mmcm_lock_count[7]_i_2_n_0\, D => \mmcm_lock_count[3]_i_1_n_0\, Q => \mmcm_lock_count_reg__0\(3), R => sync_mmcm_lock_reclocked_n_0 ); \mmcm_lock_count_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \mmcm_lock_count[7]_i_2_n_0\, D => \mmcm_lock_count[4]_i_1_n_0\, Q => \mmcm_lock_count_reg__0\(4), R => sync_mmcm_lock_reclocked_n_0 ); \mmcm_lock_count_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \mmcm_lock_count[7]_i_2_n_0\, D => \mmcm_lock_count[5]_i_1_n_0\, Q => \mmcm_lock_count_reg__0\(5), R => sync_mmcm_lock_reclocked_n_0 ); \mmcm_lock_count_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \mmcm_lock_count[7]_i_2_n_0\, D => \mmcm_lock_count[6]_i_1_n_0\, Q => \mmcm_lock_count_reg__0\(6), R => sync_mmcm_lock_reclocked_n_0 ); \mmcm_lock_count_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \mmcm_lock_count[7]_i_2_n_0\, D => \mmcm_lock_count[7]_i_3_n_0\, Q => \mmcm_lock_count_reg__0\(7), R => sync_mmcm_lock_reclocked_n_0 ); mmcm_lock_reclocked_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => sync_mmcm_lock_reclocked_n_1, Q => mmcm_lock_reclocked, R => '0' ); pll_reset_asserted_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0000CD55CCCCCCCC" ) port map ( I0 => tx_state(3), I1 => pll_reset_asserted_reg_n_0, I2 => gt0_cpllrefclklost_i, I3 => refclk_stable_reg_n_0, I4 => tx_state(1), I5 => pll_reset_asserted_i_2_n_0, O => pll_reset_asserted_i_1_n_0 ); pll_reset_asserted_i_2: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => tx_state(0), I1 => tx_state(3), I2 => tx_state(2), O => pll_reset_asserted_i_2_n_0 ); pll_reset_asserted_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => pll_reset_asserted_i_1_n_0, Q => pll_reset_asserted_reg_n_0, R => pma_reset ); \refclk_stable_count[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFEFFFF" ) port map ( I0 => \refclk_stable_count[0]_i_3_n_0\, I1 => \refclk_stable_count[0]_i_4_n_0\, I2 => \refclk_stable_count[0]_i_5_n_0\, I3 => \refclk_stable_count[0]_i_6_n_0\, I4 => \refclk_stable_count[0]_i_7_n_0\, I5 => \refclk_stable_count[0]_i_8_n_0\, O => refclk_stable_count ); \refclk_stable_count[0]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFDFFFFFFFFFFFFF" ) port map ( I0 => refclk_stable_count_reg(13), I1 => refclk_stable_count_reg(12), I2 => refclk_stable_count_reg(10), I3 => refclk_stable_count_reg(11), I4 => refclk_stable_count_reg(9), I5 => refclk_stable_count_reg(8), O => \refclk_stable_count[0]_i_3_n_0\ ); \refclk_stable_count[0]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFDF" ) port map ( I0 => refclk_stable_count_reg(19), I1 => refclk_stable_count_reg(18), I2 => refclk_stable_count_reg(16), I3 => refclk_stable_count_reg(17), I4 => refclk_stable_count_reg(15), I5 => refclk_stable_count_reg(14), O => \refclk_stable_count[0]_i_4_n_0\ ); \refclk_stable_count[0]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFE" ) port map ( I0 => refclk_stable_count_reg(30), I1 => refclk_stable_count_reg(31), I2 => refclk_stable_count_reg(28), I3 => refclk_stable_count_reg(29), I4 => refclk_stable_count_reg(27), I5 => refclk_stable_count_reg(26), O => \refclk_stable_count[0]_i_5_n_0\ ); \refclk_stable_count[0]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFE" ) port map ( I0 => refclk_stable_count_reg(24), I1 => refclk_stable_count_reg(25), I2 => refclk_stable_count_reg(22), I3 => refclk_stable_count_reg(23), I4 => refclk_stable_count_reg(21), I5 => refclk_stable_count_reg(20), O => \refclk_stable_count[0]_i_6_n_0\ ); \refclk_stable_count[0]_i_7\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => refclk_stable_count_reg(0), I1 => refclk_stable_count_reg(1), O => \refclk_stable_count[0]_i_7_n_0\ ); \refclk_stable_count[0]_i_8\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFF7" ) port map ( I0 => refclk_stable_count_reg(6), I1 => refclk_stable_count_reg(7), I2 => refclk_stable_count_reg(4), I3 => refclk_stable_count_reg(5), I4 => refclk_stable_count_reg(3), I5 => refclk_stable_count_reg(2), O => \refclk_stable_count[0]_i_8_n_0\ ); \refclk_stable_count[0]_i_9\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => refclk_stable_count_reg(0), O => \refclk_stable_count[0]_i_9_n_0\ ); \refclk_stable_count_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => refclk_stable_count, D => \refclk_stable_count_reg[0]_i_2_n_7\, Q => refclk_stable_count_reg(0), R => '0' ); \refclk_stable_count_reg[0]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \refclk_stable_count_reg[0]_i_2_n_0\, CO(2) => \refclk_stable_count_reg[0]_i_2_n_1\, CO(1) => \refclk_stable_count_reg[0]_i_2_n_2\, CO(0) => \refclk_stable_count_reg[0]_i_2_n_3\, CYINIT => '0', DI(3 downto 0) => B"0001", O(3) => \refclk_stable_count_reg[0]_i_2_n_4\, O(2) => \refclk_stable_count_reg[0]_i_2_n_5\, O(1) => \refclk_stable_count_reg[0]_i_2_n_6\, O(0) => \refclk_stable_count_reg[0]_i_2_n_7\, S(3 downto 1) => refclk_stable_count_reg(3 downto 1), S(0) => \refclk_stable_count[0]_i_9_n_0\ ); \refclk_stable_count_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => refclk_stable_count, D => \refclk_stable_count_reg[8]_i_1_n_5\, Q => refclk_stable_count_reg(10), R => '0' ); \refclk_stable_count_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => refclk_stable_count, D => \refclk_stable_count_reg[8]_i_1_n_4\, Q => refclk_stable_count_reg(11), R => '0' ); \refclk_stable_count_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => refclk_stable_count, D => \refclk_stable_count_reg[12]_i_1_n_7\, Q => refclk_stable_count_reg(12), R => '0' ); \refclk_stable_count_reg[12]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \refclk_stable_count_reg[8]_i_1_n_0\, CO(3) => \refclk_stable_count_reg[12]_i_1_n_0\, CO(2) => \refclk_stable_count_reg[12]_i_1_n_1\, CO(1) => \refclk_stable_count_reg[12]_i_1_n_2\, CO(0) => \refclk_stable_count_reg[12]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \refclk_stable_count_reg[12]_i_1_n_4\, O(2) => \refclk_stable_count_reg[12]_i_1_n_5\, O(1) => \refclk_stable_count_reg[12]_i_1_n_6\, O(0) => \refclk_stable_count_reg[12]_i_1_n_7\, S(3 downto 0) => refclk_stable_count_reg(15 downto 12) ); \refclk_stable_count_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => refclk_stable_count, D => \refclk_stable_count_reg[12]_i_1_n_6\, Q => refclk_stable_count_reg(13), R => '0' ); \refclk_stable_count_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => refclk_stable_count, D => \refclk_stable_count_reg[12]_i_1_n_5\, Q => refclk_stable_count_reg(14), R => '0' ); \refclk_stable_count_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => refclk_stable_count, D => \refclk_stable_count_reg[12]_i_1_n_4\, Q => refclk_stable_count_reg(15), R => '0' ); \refclk_stable_count_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => refclk_stable_count, D => \refclk_stable_count_reg[16]_i_1_n_7\, Q => refclk_stable_count_reg(16), R => '0' ); \refclk_stable_count_reg[16]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \refclk_stable_count_reg[12]_i_1_n_0\, CO(3) => \refclk_stable_count_reg[16]_i_1_n_0\, CO(2) => \refclk_stable_count_reg[16]_i_1_n_1\, CO(1) => \refclk_stable_count_reg[16]_i_1_n_2\, CO(0) => \refclk_stable_count_reg[16]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \refclk_stable_count_reg[16]_i_1_n_4\, O(2) => \refclk_stable_count_reg[16]_i_1_n_5\, O(1) => \refclk_stable_count_reg[16]_i_1_n_6\, O(0) => \refclk_stable_count_reg[16]_i_1_n_7\, S(3 downto 0) => refclk_stable_count_reg(19 downto 16) ); \refclk_stable_count_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => refclk_stable_count, D => \refclk_stable_count_reg[16]_i_1_n_6\, Q => refclk_stable_count_reg(17), R => '0' ); \refclk_stable_count_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => refclk_stable_count, D => \refclk_stable_count_reg[16]_i_1_n_5\, Q => refclk_stable_count_reg(18), R => '0' ); \refclk_stable_count_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => refclk_stable_count, D => \refclk_stable_count_reg[16]_i_1_n_4\, Q => refclk_stable_count_reg(19), R => '0' ); \refclk_stable_count_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => refclk_stable_count, D => \refclk_stable_count_reg[0]_i_2_n_6\, Q => refclk_stable_count_reg(1), R => '0' ); \refclk_stable_count_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => refclk_stable_count, D => \refclk_stable_count_reg[20]_i_1_n_7\, Q => refclk_stable_count_reg(20), R => '0' ); \refclk_stable_count_reg[20]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \refclk_stable_count_reg[16]_i_1_n_0\, CO(3) => \refclk_stable_count_reg[20]_i_1_n_0\, CO(2) => \refclk_stable_count_reg[20]_i_1_n_1\, CO(1) => \refclk_stable_count_reg[20]_i_1_n_2\, CO(0) => \refclk_stable_count_reg[20]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \refclk_stable_count_reg[20]_i_1_n_4\, O(2) => \refclk_stable_count_reg[20]_i_1_n_5\, O(1) => \refclk_stable_count_reg[20]_i_1_n_6\, O(0) => \refclk_stable_count_reg[20]_i_1_n_7\, S(3 downto 0) => refclk_stable_count_reg(23 downto 20) ); \refclk_stable_count_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => refclk_stable_count, D => \refclk_stable_count_reg[20]_i_1_n_6\, Q => refclk_stable_count_reg(21), R => '0' ); \refclk_stable_count_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => refclk_stable_count, D => \refclk_stable_count_reg[20]_i_1_n_5\, Q => refclk_stable_count_reg(22), R => '0' ); \refclk_stable_count_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => refclk_stable_count, D => \refclk_stable_count_reg[20]_i_1_n_4\, Q => refclk_stable_count_reg(23), R => '0' ); \refclk_stable_count_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => refclk_stable_count, D => \refclk_stable_count_reg[24]_i_1_n_7\, Q => refclk_stable_count_reg(24), R => '0' ); \refclk_stable_count_reg[24]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \refclk_stable_count_reg[20]_i_1_n_0\, CO(3) => \refclk_stable_count_reg[24]_i_1_n_0\, CO(2) => \refclk_stable_count_reg[24]_i_1_n_1\, CO(1) => \refclk_stable_count_reg[24]_i_1_n_2\, CO(0) => \refclk_stable_count_reg[24]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \refclk_stable_count_reg[24]_i_1_n_4\, O(2) => \refclk_stable_count_reg[24]_i_1_n_5\, O(1) => \refclk_stable_count_reg[24]_i_1_n_6\, O(0) => \refclk_stable_count_reg[24]_i_1_n_7\, S(3 downto 0) => refclk_stable_count_reg(27 downto 24) ); \refclk_stable_count_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => refclk_stable_count, D => \refclk_stable_count_reg[24]_i_1_n_6\, Q => refclk_stable_count_reg(25), R => '0' ); \refclk_stable_count_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => refclk_stable_count, D => \refclk_stable_count_reg[24]_i_1_n_5\, Q => refclk_stable_count_reg(26), R => '0' ); \refclk_stable_count_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => refclk_stable_count, D => \refclk_stable_count_reg[24]_i_1_n_4\, Q => refclk_stable_count_reg(27), R => '0' ); \refclk_stable_count_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => refclk_stable_count, D => \refclk_stable_count_reg[28]_i_1_n_7\, Q => refclk_stable_count_reg(28), R => '0' ); \refclk_stable_count_reg[28]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \refclk_stable_count_reg[24]_i_1_n_0\, CO(3) => \NLW_refclk_stable_count_reg[28]_i_1_CO_UNCONNECTED\(3), CO(2) => \refclk_stable_count_reg[28]_i_1_n_1\, CO(1) => \refclk_stable_count_reg[28]_i_1_n_2\, CO(0) => \refclk_stable_count_reg[28]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \refclk_stable_count_reg[28]_i_1_n_4\, O(2) => \refclk_stable_count_reg[28]_i_1_n_5\, O(1) => \refclk_stable_count_reg[28]_i_1_n_6\, O(0) => \refclk_stable_count_reg[28]_i_1_n_7\, S(3 downto 0) => refclk_stable_count_reg(31 downto 28) ); \refclk_stable_count_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => refclk_stable_count, D => \refclk_stable_count_reg[28]_i_1_n_6\, Q => refclk_stable_count_reg(29), R => '0' ); \refclk_stable_count_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => refclk_stable_count, D => \refclk_stable_count_reg[0]_i_2_n_5\, Q => refclk_stable_count_reg(2), R => '0' ); \refclk_stable_count_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => refclk_stable_count, D => \refclk_stable_count_reg[28]_i_1_n_5\, Q => refclk_stable_count_reg(30), R => '0' ); \refclk_stable_count_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => refclk_stable_count, D => \refclk_stable_count_reg[28]_i_1_n_4\, Q => refclk_stable_count_reg(31), R => '0' ); \refclk_stable_count_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => refclk_stable_count, D => \refclk_stable_count_reg[0]_i_2_n_4\, Q => refclk_stable_count_reg(3), R => '0' ); \refclk_stable_count_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => refclk_stable_count, D => \refclk_stable_count_reg[4]_i_1_n_7\, Q => refclk_stable_count_reg(4), R => '0' ); \refclk_stable_count_reg[4]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \refclk_stable_count_reg[0]_i_2_n_0\, CO(3) => \refclk_stable_count_reg[4]_i_1_n_0\, CO(2) => \refclk_stable_count_reg[4]_i_1_n_1\, CO(1) => \refclk_stable_count_reg[4]_i_1_n_2\, CO(0) => \refclk_stable_count_reg[4]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \refclk_stable_count_reg[4]_i_1_n_4\, O(2) => \refclk_stable_count_reg[4]_i_1_n_5\, O(1) => \refclk_stable_count_reg[4]_i_1_n_6\, O(0) => \refclk_stable_count_reg[4]_i_1_n_7\, S(3 downto 0) => refclk_stable_count_reg(7 downto 4) ); \refclk_stable_count_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => refclk_stable_count, D => \refclk_stable_count_reg[4]_i_1_n_6\, Q => refclk_stable_count_reg(5), R => '0' ); \refclk_stable_count_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => refclk_stable_count, D => \refclk_stable_count_reg[4]_i_1_n_5\, Q => refclk_stable_count_reg(6), R => '0' ); \refclk_stable_count_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => refclk_stable_count, D => \refclk_stable_count_reg[4]_i_1_n_4\, Q => refclk_stable_count_reg(7), R => '0' ); \refclk_stable_count_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => refclk_stable_count, D => \refclk_stable_count_reg[8]_i_1_n_7\, Q => refclk_stable_count_reg(8), R => '0' ); \refclk_stable_count_reg[8]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \refclk_stable_count_reg[4]_i_1_n_0\, CO(3) => \refclk_stable_count_reg[8]_i_1_n_0\, CO(2) => \refclk_stable_count_reg[8]_i_1_n_1\, CO(1) => \refclk_stable_count_reg[8]_i_1_n_2\, CO(0) => \refclk_stable_count_reg[8]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \refclk_stable_count_reg[8]_i_1_n_4\, O(2) => \refclk_stable_count_reg[8]_i_1_n_5\, O(1) => \refclk_stable_count_reg[8]_i_1_n_6\, O(0) => \refclk_stable_count_reg[8]_i_1_n_7\, S(3 downto 0) => refclk_stable_count_reg(11 downto 8) ); \refclk_stable_count_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => refclk_stable_count, D => \refclk_stable_count_reg[8]_i_1_n_6\, Q => refclk_stable_count_reg(9), R => '0' ); refclk_stable_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => \refclk_stable_count[0]_i_7_n_0\, I1 => refclk_stable_i_2_n_0, I2 => refclk_stable_i_3_n_0, I3 => refclk_stable_i_4_n_0, I4 => refclk_stable_i_5_n_0, I5 => refclk_stable_i_6_n_0, O => refclk_stable_i_1_n_0 ); refclk_stable_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0001000000000000" ) port map ( I0 => refclk_stable_count_reg(4), I1 => refclk_stable_count_reg(5), I2 => refclk_stable_count_reg(2), I3 => refclk_stable_count_reg(3), I4 => refclk_stable_count_reg(7), I5 => refclk_stable_count_reg(6), O => refclk_stable_i_2_n_0 ); refclk_stable_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"0000200000000000" ) port map ( I0 => refclk_stable_count_reg(10), I1 => refclk_stable_count_reg(11), I2 => refclk_stable_count_reg(8), I3 => refclk_stable_count_reg(9), I4 => refclk_stable_count_reg(12), I5 => refclk_stable_count_reg(13), O => refclk_stable_i_3_n_0 ); refclk_stable_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"0000000200000000" ) port map ( I0 => refclk_stable_count_reg(16), I1 => refclk_stable_count_reg(17), I2 => refclk_stable_count_reg(14), I3 => refclk_stable_count_reg(15), I4 => refclk_stable_count_reg(18), I5 => refclk_stable_count_reg(19), O => refclk_stable_i_4_n_0 ); refclk_stable_i_5: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000001" ) port map ( I0 => refclk_stable_count_reg(22), I1 => refclk_stable_count_reg(23), I2 => refclk_stable_count_reg(20), I3 => refclk_stable_count_reg(21), I4 => refclk_stable_count_reg(25), I5 => refclk_stable_count_reg(24), O => refclk_stable_i_5_n_0 ); refclk_stable_i_6: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000001" ) port map ( I0 => refclk_stable_count_reg(28), I1 => refclk_stable_count_reg(29), I2 => refclk_stable_count_reg(26), I3 => refclk_stable_count_reg(27), I4 => refclk_stable_count_reg(31), I5 => refclk_stable_count_reg(30), O => refclk_stable_i_6_n_0 ); refclk_stable_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => refclk_stable_i_1_n_0, Q => refclk_stable_reg_n_0, R => '0' ); \reset_time_out_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"440000FF50505050" ) port map ( I0 => tx_state(3), I1 => txresetdone_s3, I2 => init_wait_done_reg_n_0, I3 => tx_state(1), I4 => tx_state(2), I5 => tx_state(0), O => \reset_time_out_i_2__0_n_0\ ); reset_time_out_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => sync_cplllock_n_1, Q => reset_time_out, R => pma_reset ); run_phase_alignment_int_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"FFFB0002" ) port map ( I0 => tx_state(3), I1 => tx_state(0), I2 => tx_state(2), I3 => tx_state(1), I4 => run_phase_alignment_int_reg_n_0, O => run_phase_alignment_int_i_1_n_0 ); run_phase_alignment_int_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => run_phase_alignment_int_i_1_n_0, Q => run_phase_alignment_int_reg_n_0, R => pma_reset ); run_phase_alignment_int_s3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk, CE => '1', D => data_out, Q => run_phase_alignment_int_s3, R => '0' ); sync_TXRESETDONE: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_4 port map ( data_out => txresetdone_s2, data_sync_reg1_0 => data_sync_reg1_0, independent_clock_bufg => independent_clock_bufg ); sync_cplllock: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_5 port map ( E(0) => sync_cplllock_n_0, \FSM_sequential_tx_state_reg[0]\ => \FSM_sequential_tx_state[3]_i_3_n_0\, \FSM_sequential_tx_state_reg[0]_0\ => \FSM_sequential_tx_state[3]_i_4_n_0\, \FSM_sequential_tx_state_reg[0]_1\ => \FSM_sequential_tx_state[3]_i_6_n_0\, \FSM_sequential_tx_state_reg[0]_2\ => time_out_2ms_reg_n_0, \FSM_sequential_tx_state_reg[0]_3\ => \FSM_sequential_tx_state[3]_i_7_n_0\, \FSM_sequential_tx_state_reg[0]_4\ => pll_reset_asserted_reg_n_0, \FSM_sequential_tx_state_reg[0]_5\ => refclk_stable_reg_n_0, \FSM_sequential_tx_state_reg[0]_6\ => \FSM_sequential_tx_state[0]_i_3_n_0\, Q(3 downto 0) => tx_state(3 downto 0), cplllock => cplllock, independent_clock_bufg => independent_clock_bufg, mmcm_lock_reclocked => mmcm_lock_reclocked, reset_time_out => reset_time_out, reset_time_out_reg => sync_cplllock_n_1, reset_time_out_reg_0 => init_wait_done_reg_n_0, reset_time_out_reg_1 => \reset_time_out_i_2__0_n_0\ ); sync_mmcm_lock_reclocked: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_6 port map ( Q(1 downto 0) => \mmcm_lock_count_reg__0\(7 downto 6), SR(0) => sync_mmcm_lock_reclocked_n_0, independent_clock_bufg => independent_clock_bufg, mmcm_lock_reclocked => mmcm_lock_reclocked, mmcm_lock_reclocked_reg => sync_mmcm_lock_reclocked_n_1, mmcm_lock_reclocked_reg_0 => \mmcm_lock_count[7]_i_4_n_0\, mmcm_locked => mmcm_locked ); sync_run_phase_alignment_int: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_7 port map ( data_in => run_phase_alignment_int_reg_n_0, data_out => data_out, userclk => userclk ); sync_time_out_wait_bypass: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_8 port map ( data_in => time_out_wait_bypass_reg_n_0, data_out => time_out_wait_bypass_s2, independent_clock_bufg => independent_clock_bufg ); sync_tx_fsm_reset_done_int: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_9 port map ( data_in => \^data_in\, data_out => tx_fsm_reset_done_int_s2, userclk => userclk ); \time_out_2ms_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"00AE" ) port map ( I0 => time_out_2ms_reg_n_0, I1 => time_out_2ms_i_2_n_0, I2 => \time_out_counter[0]_i_5__0_n_0\, I3 => reset_time_out, O => \time_out_2ms_i_1__0_n_0\ ); time_out_2ms_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000800" ) port map ( I0 => time_out_counter_reg(17), I1 => time_out_counter_reg(18), I2 => time_out_counter_reg(10), I3 => time_out_counter_reg(12), I4 => time_out_counter_reg(5), I5 => \time_out_counter[0]_i_3__0_n_0\, O => time_out_2ms_i_2_n_0 ); time_out_2ms_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => \time_out_2ms_i_1__0_n_0\, Q => time_out_2ms_reg_n_0, R => '0' ); time_out_500us_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"00000000AAAAEAAA" ) port map ( I0 => time_out_500us_reg_n_0, I1 => time_out_500us_i_2_n_0, I2 => time_out_counter_reg(5), I3 => time_out_counter_reg(10), I4 => \time_out_counter[0]_i_5__0_n_0\, I5 => reset_time_out, O => time_out_500us_i_1_n_0 ); time_out_500us_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000008" ) port map ( I0 => time_out_counter_reg(15), I1 => time_out_counter_reg(16), I2 => time_out_counter_reg(11), I3 => time_out_counter_reg(12), I4 => time_out_counter_reg(18), I5 => time_out_counter_reg(17), O => time_out_500us_i_2_n_0 ); time_out_500us_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => time_out_500us_i_1_n_0, Q => time_out_500us_reg_n_0, R => '0' ); \time_out_counter[0]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFBFFFF" ) port map ( I0 => \time_out_counter[0]_i_3__0_n_0\, I1 => \time_out_counter[0]_i_4__0_n_0\, I2 => \time_out_counter[0]_i_5__0_n_0\, I3 => time_out_counter_reg(10), I4 => time_out_counter_reg(12), I5 => time_out_counter_reg(5), O => time_out_counter ); \time_out_counter[0]_i_3__0\: unisim.vcomponents.LUT3 generic map( INIT => X"EF" ) port map ( I0 => time_out_counter_reg(16), I1 => time_out_counter_reg(15), I2 => time_out_counter_reg(11), O => \time_out_counter[0]_i_3__0_n_0\ ); \time_out_counter[0]_i_4__0\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => time_out_counter_reg(17), I1 => time_out_counter_reg(18), O => \time_out_counter[0]_i_4__0_n_0\ ); \time_out_counter[0]_i_5__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFD" ) port map ( I0 => time_out_counter_reg(7), I1 => time_out_counter_reg(14), I2 => \time_out_counter[0]_i_7_n_0\, I3 => \time_out_counter[0]_i_8_n_0\, O => \time_out_counter[0]_i_5__0_n_0\ ); \time_out_counter[0]_i_6\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => time_out_counter_reg(0), O => \time_out_counter[0]_i_6_n_0\ ); \time_out_counter[0]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => time_out_counter_reg(4), I1 => time_out_counter_reg(3), I2 => time_out_counter_reg(8), I3 => time_out_counter_reg(6), O => \time_out_counter[0]_i_7_n_0\ ); \time_out_counter[0]_i_8\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFFEF" ) port map ( I0 => time_out_counter_reg(0), I1 => time_out_counter_reg(13), I2 => time_out_counter_reg(9), I3 => time_out_counter_reg(2), I4 => time_out_counter_reg(1), O => \time_out_counter[0]_i_8_n_0\ ); \time_out_counter_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => time_out_counter, D => \time_out_counter_reg[0]_i_2_n_7\, Q => time_out_counter_reg(0), R => reset_time_out ); \time_out_counter_reg[0]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \time_out_counter_reg[0]_i_2_n_0\, CO(2) => \time_out_counter_reg[0]_i_2_n_1\, CO(1) => \time_out_counter_reg[0]_i_2_n_2\, CO(0) => \time_out_counter_reg[0]_i_2_n_3\, CYINIT => '0', DI(3 downto 0) => B"0001", O(3) => \time_out_counter_reg[0]_i_2_n_4\, O(2) => \time_out_counter_reg[0]_i_2_n_5\, O(1) => \time_out_counter_reg[0]_i_2_n_6\, O(0) => \time_out_counter_reg[0]_i_2_n_7\, S(3 downto 1) => time_out_counter_reg(3 downto 1), S(0) => \time_out_counter[0]_i_6_n_0\ ); \time_out_counter_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => time_out_counter, D => \time_out_counter_reg[8]_i_1_n_5\, Q => time_out_counter_reg(10), R => reset_time_out ); \time_out_counter_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => time_out_counter, D => \time_out_counter_reg[8]_i_1_n_4\, Q => time_out_counter_reg(11), R => reset_time_out ); \time_out_counter_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => time_out_counter, D => \time_out_counter_reg[12]_i_1_n_7\, Q => time_out_counter_reg(12), R => reset_time_out ); \time_out_counter_reg[12]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \time_out_counter_reg[8]_i_1_n_0\, CO(3) => \time_out_counter_reg[12]_i_1_n_0\, CO(2) => \time_out_counter_reg[12]_i_1_n_1\, CO(1) => \time_out_counter_reg[12]_i_1_n_2\, CO(0) => \time_out_counter_reg[12]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \time_out_counter_reg[12]_i_1_n_4\, O(2) => \time_out_counter_reg[12]_i_1_n_5\, O(1) => \time_out_counter_reg[12]_i_1_n_6\, O(0) => \time_out_counter_reg[12]_i_1_n_7\, S(3 downto 0) => time_out_counter_reg(15 downto 12) ); \time_out_counter_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => time_out_counter, D => \time_out_counter_reg[12]_i_1_n_6\, Q => time_out_counter_reg(13), R => reset_time_out ); \time_out_counter_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => time_out_counter, D => \time_out_counter_reg[12]_i_1_n_5\, Q => time_out_counter_reg(14), R => reset_time_out ); \time_out_counter_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => time_out_counter, D => \time_out_counter_reg[12]_i_1_n_4\, Q => time_out_counter_reg(15), R => reset_time_out ); \time_out_counter_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => time_out_counter, D => \time_out_counter_reg[16]_i_1_n_7\, Q => time_out_counter_reg(16), R => reset_time_out ); \time_out_counter_reg[16]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \time_out_counter_reg[12]_i_1_n_0\, CO(3 downto 2) => \NLW_time_out_counter_reg[16]_i_1_CO_UNCONNECTED\(3 downto 2), CO(1) => \time_out_counter_reg[16]_i_1_n_2\, CO(0) => \time_out_counter_reg[16]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \NLW_time_out_counter_reg[16]_i_1_O_UNCONNECTED\(3), O(2) => \time_out_counter_reg[16]_i_1_n_5\, O(1) => \time_out_counter_reg[16]_i_1_n_6\, O(0) => \time_out_counter_reg[16]_i_1_n_7\, S(3) => '0', S(2 downto 0) => time_out_counter_reg(18 downto 16) ); \time_out_counter_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => time_out_counter, D => \time_out_counter_reg[16]_i_1_n_6\, Q => time_out_counter_reg(17), R => reset_time_out ); \time_out_counter_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => time_out_counter, D => \time_out_counter_reg[16]_i_1_n_5\, Q => time_out_counter_reg(18), R => reset_time_out ); \time_out_counter_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => time_out_counter, D => \time_out_counter_reg[0]_i_2_n_6\, Q => time_out_counter_reg(1), R => reset_time_out ); \time_out_counter_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => time_out_counter, D => \time_out_counter_reg[0]_i_2_n_5\, Q => time_out_counter_reg(2), R => reset_time_out ); \time_out_counter_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => time_out_counter, D => \time_out_counter_reg[0]_i_2_n_4\, Q => time_out_counter_reg(3), R => reset_time_out ); \time_out_counter_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => time_out_counter, D => \time_out_counter_reg[4]_i_1_n_7\, Q => time_out_counter_reg(4), R => reset_time_out ); \time_out_counter_reg[4]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \time_out_counter_reg[0]_i_2_n_0\, CO(3) => \time_out_counter_reg[4]_i_1_n_0\, CO(2) => \time_out_counter_reg[4]_i_1_n_1\, CO(1) => \time_out_counter_reg[4]_i_1_n_2\, CO(0) => \time_out_counter_reg[4]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \time_out_counter_reg[4]_i_1_n_4\, O(2) => \time_out_counter_reg[4]_i_1_n_5\, O(1) => \time_out_counter_reg[4]_i_1_n_6\, O(0) => \time_out_counter_reg[4]_i_1_n_7\, S(3 downto 0) => time_out_counter_reg(7 downto 4) ); \time_out_counter_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => time_out_counter, D => \time_out_counter_reg[4]_i_1_n_6\, Q => time_out_counter_reg(5), R => reset_time_out ); \time_out_counter_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => time_out_counter, D => \time_out_counter_reg[4]_i_1_n_5\, Q => time_out_counter_reg(6), R => reset_time_out ); \time_out_counter_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => time_out_counter, D => \time_out_counter_reg[4]_i_1_n_4\, Q => time_out_counter_reg(7), R => reset_time_out ); \time_out_counter_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => time_out_counter, D => \time_out_counter_reg[8]_i_1_n_7\, Q => time_out_counter_reg(8), R => reset_time_out ); \time_out_counter_reg[8]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \time_out_counter_reg[4]_i_1_n_0\, CO(3) => \time_out_counter_reg[8]_i_1_n_0\, CO(2) => \time_out_counter_reg[8]_i_1_n_1\, CO(1) => \time_out_counter_reg[8]_i_1_n_2\, CO(0) => \time_out_counter_reg[8]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \time_out_counter_reg[8]_i_1_n_4\, O(2) => \time_out_counter_reg[8]_i_1_n_5\, O(1) => \time_out_counter_reg[8]_i_1_n_6\, O(0) => \time_out_counter_reg[8]_i_1_n_7\, S(3 downto 0) => time_out_counter_reg(11 downto 8) ); \time_out_counter_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => time_out_counter, D => \time_out_counter_reg[8]_i_1_n_6\, Q => time_out_counter_reg(9), R => reset_time_out ); time_out_wait_bypass_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"AB00" ) port map ( I0 => time_out_wait_bypass_reg_n_0, I1 => tx_fsm_reset_done_int_s3, I2 => \wait_bypass_count[0]_i_4_n_0\, I3 => run_phase_alignment_int_s3, O => time_out_wait_bypass_i_1_n_0 ); time_out_wait_bypass_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk, CE => '1', D => time_out_wait_bypass_i_1_n_0, Q => time_out_wait_bypass_reg_n_0, R => '0' ); time_out_wait_bypass_s3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => time_out_wait_bypass_s2, Q => time_out_wait_bypass_s3, R => '0' ); \time_tlock_max_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"00000000AAAAAAEA" ) port map ( I0 => time_tlock_max_reg_n_0, I1 => time_tlock_max_i_2_n_0, I2 => time_out_counter_reg(5), I3 => \time_out_counter[0]_i_3__0_n_0\, I4 => time_tlock_max_i_3_n_0, I5 => reset_time_out, O => \time_tlock_max_i_1__0_n_0\ ); time_tlock_max_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000020" ) port map ( I0 => time_out_counter_reg(14), I1 => time_out_counter_reg(12), I2 => time_out_counter_reg(10), I3 => time_out_counter_reg(7), I4 => time_out_counter_reg(18), I5 => time_out_counter_reg(17), O => time_tlock_max_i_2_n_0 ); time_tlock_max_i_3: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFFFE" ) port map ( I0 => \time_out_counter[0]_i_8_n_0\, I1 => time_out_counter_reg(6), I2 => time_out_counter_reg(8), I3 => time_out_counter_reg(3), I4 => time_out_counter_reg(4), O => time_tlock_max_i_3_n_0 ); time_tlock_max_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => \time_tlock_max_i_1__0_n_0\, Q => time_tlock_max_reg_n_0, R => '0' ); tx_fsm_reset_done_int_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"FFFF1000" ) port map ( I0 => tx_state(1), I1 => tx_state(2), I2 => tx_state(0), I3 => tx_state(3), I4 => \^data_in\, O => tx_fsm_reset_done_int_i_1_n_0 ); tx_fsm_reset_done_int_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => tx_fsm_reset_done_int_i_1_n_0, Q => \^data_in\, R => pma_reset ); tx_fsm_reset_done_int_s3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk, CE => '1', D => tx_fsm_reset_done_int_s2, Q => tx_fsm_reset_done_int_s3, R => '0' ); txresetdone_s3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => '1', D => txresetdone_s2, Q => txresetdone_s3, R => '0' ); \wait_bypass_count[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => run_phase_alignment_int_s3, O => clear ); \wait_bypass_count[0]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \wait_bypass_count[0]_i_4_n_0\, I1 => tx_fsm_reset_done_int_s3, O => \wait_bypass_count[0]_i_2_n_0\ ); \wait_bypass_count[0]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"FFEFFFFFFFFFFFFF" ) port map ( I0 => \wait_bypass_count[0]_i_6_n_0\, I1 => \wait_bypass_count[0]_i_7_n_0\, I2 => wait_bypass_count_reg(16), I3 => wait_bypass_count_reg(13), I4 => wait_bypass_count_reg(12), I5 => \wait_bypass_count[0]_i_8_n_0\, O => \wait_bypass_count[0]_i_4_n_0\ ); \wait_bypass_count[0]_i_5\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => wait_bypass_count_reg(0), O => \wait_bypass_count[0]_i_5_n_0\ ); \wait_bypass_count[0]_i_6\: unisim.vcomponents.LUT4 generic map( INIT => X"FFDF" ) port map ( I0 => wait_bypass_count_reg(4), I1 => wait_bypass_count_reg(15), I2 => wait_bypass_count_reg(14), I3 => wait_bypass_count_reg(10), O => \wait_bypass_count[0]_i_6_n_0\ ); \wait_bypass_count[0]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"FF7F" ) port map ( I0 => wait_bypass_count_reg(2), I1 => wait_bypass_count_reg(9), I2 => wait_bypass_count_reg(6), I3 => wait_bypass_count_reg(11), O => \wait_bypass_count[0]_i_7_n_0\ ); \wait_bypass_count[0]_i_8\: unisim.vcomponents.LUT6 generic map( INIT => X"0000800000000000" ) port map ( I0 => wait_bypass_count_reg(5), I1 => wait_bypass_count_reg(0), I2 => wait_bypass_count_reg(3), I3 => wait_bypass_count_reg(1), I4 => wait_bypass_count_reg(8), I5 => wait_bypass_count_reg(7), O => \wait_bypass_count[0]_i_8_n_0\ ); \wait_bypass_count_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => \wait_bypass_count[0]_i_2_n_0\, D => \wait_bypass_count_reg[0]_i_3_n_7\, Q => wait_bypass_count_reg(0), R => clear ); \wait_bypass_count_reg[0]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \wait_bypass_count_reg[0]_i_3_n_0\, CO(2) => \wait_bypass_count_reg[0]_i_3_n_1\, CO(1) => \wait_bypass_count_reg[0]_i_3_n_2\, CO(0) => \wait_bypass_count_reg[0]_i_3_n_3\, CYINIT => '0', DI(3 downto 0) => B"0001", O(3) => \wait_bypass_count_reg[0]_i_3_n_4\, O(2) => \wait_bypass_count_reg[0]_i_3_n_5\, O(1) => \wait_bypass_count_reg[0]_i_3_n_6\, O(0) => \wait_bypass_count_reg[0]_i_3_n_7\, S(3 downto 1) => wait_bypass_count_reg(3 downto 1), S(0) => \wait_bypass_count[0]_i_5_n_0\ ); \wait_bypass_count_reg[10]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => \wait_bypass_count[0]_i_2_n_0\, D => \wait_bypass_count_reg[8]_i_1_n_5\, Q => wait_bypass_count_reg(10), R => clear ); \wait_bypass_count_reg[11]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => \wait_bypass_count[0]_i_2_n_0\, D => \wait_bypass_count_reg[8]_i_1_n_4\, Q => wait_bypass_count_reg(11), R => clear ); \wait_bypass_count_reg[12]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => \wait_bypass_count[0]_i_2_n_0\, D => \wait_bypass_count_reg[12]_i_1_n_7\, Q => wait_bypass_count_reg(12), R => clear ); \wait_bypass_count_reg[12]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \wait_bypass_count_reg[8]_i_1_n_0\, CO(3) => \wait_bypass_count_reg[12]_i_1_n_0\, CO(2) => \wait_bypass_count_reg[12]_i_1_n_1\, CO(1) => \wait_bypass_count_reg[12]_i_1_n_2\, CO(0) => \wait_bypass_count_reg[12]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \wait_bypass_count_reg[12]_i_1_n_4\, O(2) => \wait_bypass_count_reg[12]_i_1_n_5\, O(1) => \wait_bypass_count_reg[12]_i_1_n_6\, O(0) => \wait_bypass_count_reg[12]_i_1_n_7\, S(3 downto 0) => wait_bypass_count_reg(15 downto 12) ); \wait_bypass_count_reg[13]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => \wait_bypass_count[0]_i_2_n_0\, D => \wait_bypass_count_reg[12]_i_1_n_6\, Q => wait_bypass_count_reg(13), R => clear ); \wait_bypass_count_reg[14]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => \wait_bypass_count[0]_i_2_n_0\, D => \wait_bypass_count_reg[12]_i_1_n_5\, Q => wait_bypass_count_reg(14), R => clear ); \wait_bypass_count_reg[15]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => \wait_bypass_count[0]_i_2_n_0\, D => \wait_bypass_count_reg[12]_i_1_n_4\, Q => wait_bypass_count_reg(15), R => clear ); \wait_bypass_count_reg[16]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => \wait_bypass_count[0]_i_2_n_0\, D => \wait_bypass_count_reg[16]_i_1_n_7\, Q => wait_bypass_count_reg(16), R => clear ); \wait_bypass_count_reg[16]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \wait_bypass_count_reg[12]_i_1_n_0\, CO(3 downto 0) => \NLW_wait_bypass_count_reg[16]_i_1_CO_UNCONNECTED\(3 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 1) => \NLW_wait_bypass_count_reg[16]_i_1_O_UNCONNECTED\(3 downto 1), O(0) => \wait_bypass_count_reg[16]_i_1_n_7\, S(3 downto 1) => B"000", S(0) => wait_bypass_count_reg(16) ); \wait_bypass_count_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => \wait_bypass_count[0]_i_2_n_0\, D => \wait_bypass_count_reg[0]_i_3_n_6\, Q => wait_bypass_count_reg(1), R => clear ); \wait_bypass_count_reg[2]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => \wait_bypass_count[0]_i_2_n_0\, D => \wait_bypass_count_reg[0]_i_3_n_5\, Q => wait_bypass_count_reg(2), R => clear ); \wait_bypass_count_reg[3]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => \wait_bypass_count[0]_i_2_n_0\, D => \wait_bypass_count_reg[0]_i_3_n_4\, Q => wait_bypass_count_reg(3), R => clear ); \wait_bypass_count_reg[4]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => \wait_bypass_count[0]_i_2_n_0\, D => \wait_bypass_count_reg[4]_i_1_n_7\, Q => wait_bypass_count_reg(4), R => clear ); \wait_bypass_count_reg[4]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \wait_bypass_count_reg[0]_i_3_n_0\, CO(3) => \wait_bypass_count_reg[4]_i_1_n_0\, CO(2) => \wait_bypass_count_reg[4]_i_1_n_1\, CO(1) => \wait_bypass_count_reg[4]_i_1_n_2\, CO(0) => \wait_bypass_count_reg[4]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \wait_bypass_count_reg[4]_i_1_n_4\, O(2) => \wait_bypass_count_reg[4]_i_1_n_5\, O(1) => \wait_bypass_count_reg[4]_i_1_n_6\, O(0) => \wait_bypass_count_reg[4]_i_1_n_7\, S(3 downto 0) => wait_bypass_count_reg(7 downto 4) ); \wait_bypass_count_reg[5]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => \wait_bypass_count[0]_i_2_n_0\, D => \wait_bypass_count_reg[4]_i_1_n_6\, Q => wait_bypass_count_reg(5), R => clear ); \wait_bypass_count_reg[6]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => \wait_bypass_count[0]_i_2_n_0\, D => \wait_bypass_count_reg[4]_i_1_n_5\, Q => wait_bypass_count_reg(6), R => clear ); \wait_bypass_count_reg[7]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => \wait_bypass_count[0]_i_2_n_0\, D => \wait_bypass_count_reg[4]_i_1_n_4\, Q => wait_bypass_count_reg(7), R => clear ); \wait_bypass_count_reg[8]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => \wait_bypass_count[0]_i_2_n_0\, D => \wait_bypass_count_reg[8]_i_1_n_7\, Q => wait_bypass_count_reg(8), R => clear ); \wait_bypass_count_reg[8]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \wait_bypass_count_reg[4]_i_1_n_0\, CO(3) => \wait_bypass_count_reg[8]_i_1_n_0\, CO(2) => \wait_bypass_count_reg[8]_i_1_n_1\, CO(1) => \wait_bypass_count_reg[8]_i_1_n_2\, CO(0) => \wait_bypass_count_reg[8]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \wait_bypass_count_reg[8]_i_1_n_4\, O(2) => \wait_bypass_count_reg[8]_i_1_n_5\, O(1) => \wait_bypass_count_reg[8]_i_1_n_6\, O(0) => \wait_bypass_count_reg[8]_i_1_n_7\, S(3 downto 0) => wait_bypass_count_reg(11 downto 8) ); \wait_bypass_count_reg[9]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => \wait_bypass_count[0]_i_2_n_0\, D => \wait_bypass_count_reg[8]_i_1_n_6\, Q => wait_bypass_count_reg(9), R => clear ); \wait_time_cnt[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \wait_time_cnt_reg__0\(0), O => wait_time_cnt0(0) ); \wait_time_cnt[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \wait_time_cnt_reg__0\(0), I1 => \wait_time_cnt_reg__0\(1), O => \wait_time_cnt[1]_i_1_n_0\ ); \wait_time_cnt[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"E1" ) port map ( I0 => \wait_time_cnt_reg__0\(1), I1 => \wait_time_cnt_reg__0\(0), I2 => \wait_time_cnt_reg__0\(2), O => \wait_time_cnt[2]_i_1_n_0\ ); \wait_time_cnt[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"FE01" ) port map ( I0 => \wait_time_cnt_reg__0\(2), I1 => \wait_time_cnt_reg__0\(0), I2 => \wait_time_cnt_reg__0\(1), I3 => \wait_time_cnt_reg__0\(3), O => \wait_time_cnt[3]_i_1_n_0\ ); \wait_time_cnt[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0001" ) port map ( I0 => \wait_time_cnt_reg__0\(3), I1 => \wait_time_cnt_reg__0\(1), I2 => \wait_time_cnt_reg__0\(0), I3 => \wait_time_cnt_reg__0\(2), I4 => \wait_time_cnt_reg__0\(4), O => \wait_time_cnt[4]_i_1_n_0\ ); \wait_time_cnt[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFE00000001" ) port map ( I0 => \wait_time_cnt_reg__0\(4), I1 => \wait_time_cnt_reg__0\(2), I2 => \wait_time_cnt_reg__0\(0), I3 => \wait_time_cnt_reg__0\(1), I4 => \wait_time_cnt_reg__0\(3), I5 => \wait_time_cnt_reg__0\(5), O => \wait_time_cnt[5]_i_1_n_0\ ); \wait_time_cnt[6]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"0700" ) port map ( I0 => tx_state(1), I1 => tx_state(2), I2 => tx_state(3), I3 => tx_state(0), O => wait_time_cnt0_0 ); \wait_time_cnt[6]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \wait_time_cnt[6]_i_4_n_0\, I1 => \wait_time_cnt_reg__0\(6), O => sel ); \wait_time_cnt[6]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \wait_time_cnt[6]_i_4_n_0\, I1 => \wait_time_cnt_reg__0\(6), O => \wait_time_cnt[6]_i_3_n_0\ ); \wait_time_cnt[6]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFE" ) port map ( I0 => \wait_time_cnt_reg__0\(4), I1 => \wait_time_cnt_reg__0\(2), I2 => \wait_time_cnt_reg__0\(0), I3 => \wait_time_cnt_reg__0\(1), I4 => \wait_time_cnt_reg__0\(3), I5 => \wait_time_cnt_reg__0\(5), O => \wait_time_cnt[6]_i_4_n_0\ ); \wait_time_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => independent_clock_bufg, CE => sel, D => wait_time_cnt0(0), Q => \wait_time_cnt_reg__0\(0), R => wait_time_cnt0_0 ); \wait_time_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => independent_clock_bufg, CE => sel, D => \wait_time_cnt[1]_i_1_n_0\, Q => \wait_time_cnt_reg__0\(1), R => wait_time_cnt0_0 ); \wait_time_cnt_reg[2]\: unisim.vcomponents.FDSE port map ( C => independent_clock_bufg, CE => sel, D => \wait_time_cnt[2]_i_1_n_0\, Q => \wait_time_cnt_reg__0\(2), S => wait_time_cnt0_0 ); \wait_time_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => independent_clock_bufg, CE => sel, D => \wait_time_cnt[3]_i_1_n_0\, Q => \wait_time_cnt_reg__0\(3), R => wait_time_cnt0_0 ); \wait_time_cnt_reg[4]\: unisim.vcomponents.FDRE port map ( C => independent_clock_bufg, CE => sel, D => \wait_time_cnt[4]_i_1_n_0\, Q => \wait_time_cnt_reg__0\(4), R => wait_time_cnt0_0 ); \wait_time_cnt_reg[5]\: unisim.vcomponents.FDSE port map ( C => independent_clock_bufg, CE => sel, D => \wait_time_cnt[5]_i_1_n_0\, Q => \wait_time_cnt_reg__0\(5), S => wait_time_cnt0_0 ); \wait_time_cnt_reg[6]\: unisim.vcomponents.FDSE port map ( C => independent_clock_bufg, CE => sel, D => \wait_time_cnt[6]_i_3_n_0\, Q => \wait_time_cnt_reg__0\(6), S => wait_time_cnt0_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPCS_PMA_GEN is port ( MGT_TX_RESET : out STD_LOGIC; status_vector : out STD_LOGIC_VECTOR ( 6 downto 0 ); \NO_MANAGEMENT.CONFIGURATION_VECTOR_REG_reg[3]_0\ : out STD_LOGIC; \NO_MANAGEMENT.CONFIGURATION_VECTOR_REG_reg[2]_0\ : out STD_LOGIC; MGT_RX_RESET : out STD_LOGIC; gmii_rxd : out STD_LOGIC_VECTOR ( 7 downto 0 ); gmii_rx_er : out STD_LOGIC; txchardispmode : out STD_LOGIC; txcharisk : out STD_LOGIC; txdata : out STD_LOGIC_VECTOR ( 7 downto 0 ); gmii_rx_dv : out STD_LOGIC; enablealign : out STD_LOGIC; txchardispval : out STD_LOGIC; userclk2 : in STD_LOGIC; dcm_locked : in STD_LOGIC; signal_detect : in STD_LOGIC; reset : in STD_LOGIC; gmii_tx_en : in STD_LOGIC; gmii_tx_er : in STD_LOGIC; configuration_vector : in STD_LOGIC_VECTOR ( 2 downto 0 ); gmii_txd : in STD_LOGIC_VECTOR ( 7 downto 0 ); rxnotintable : in STD_LOGIC_VECTOR ( 0 to 0 ); rxbufstatus : in STD_LOGIC_VECTOR ( 0 to 0 ); txbuferr : in STD_LOGIC; rxdisperr : in STD_LOGIC_VECTOR ( 0 to 0 ); rxclkcorcnt : in STD_LOGIC_VECTOR ( 1 downto 0 ); rxcharisk : in STD_LOGIC_VECTOR ( 0 to 0 ); rxchariscomma : in STD_LOGIC_VECTOR ( 0 to 0 ); reset_done : in STD_LOGIC; rxdata : in STD_LOGIC_VECTOR ( 7 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPCS_PMA_GEN; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPCS_PMA_GEN is signal CONFIGURATION_VECTOR_REG : STD_LOGIC_VECTOR ( 1 to 1 ); signal D : STD_LOGIC; signal \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[0]\ : STD_LOGIC; signal \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[10]\ : STD_LOGIC; signal \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[11]\ : STD_LOGIC; signal \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[12]\ : STD_LOGIC; signal \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[13]\ : STD_LOGIC; signal \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[1]\ : STD_LOGIC; signal \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[2]\ : STD_LOGIC; signal \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[3]\ : STD_LOGIC; signal \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[4]\ : STD_LOGIC; signal \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[5]\ : STD_LOGIC; signal \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[6]\ : STD_LOGIC; signal \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[7]\ : STD_LOGIC; signal \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[8]\ : STD_LOGIC; signal \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[9]\ : STD_LOGIC; signal \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[0]\ : STD_LOGIC; signal \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[10]\ : STD_LOGIC; signal \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[11]\ : STD_LOGIC; signal \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[12]\ : STD_LOGIC; signal \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[13]\ : STD_LOGIC; signal \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[1]\ : STD_LOGIC; signal \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[2]\ : STD_LOGIC; signal \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[3]\ : STD_LOGIC; signal \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[4]\ : STD_LOGIC; signal \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[5]\ : STD_LOGIC; signal \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[6]\ : STD_LOGIC; signal \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[7]\ : STD_LOGIC; signal \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[8]\ : STD_LOGIC; signal \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[9]\ : STD_LOGIC; signal I0 : STD_LOGIC; signal \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_0\ : STD_LOGIC; signal \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_1\ : STD_LOGIC; signal \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_10\ : STD_LOGIC; signal \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_11\ : STD_LOGIC; signal \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_12\ : STD_LOGIC; signal \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_13\ : STD_LOGIC; signal \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_14\ : STD_LOGIC; signal \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_15\ : STD_LOGIC; signal \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_16\ : STD_LOGIC; signal \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_17\ : STD_LOGIC; signal \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_18\ : STD_LOGIC; signal \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_19\ : STD_LOGIC; signal \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_2\ : STD_LOGIC; signal \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_20\ : STD_LOGIC; signal \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_21\ : STD_LOGIC; signal \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_3\ : STD_LOGIC; signal \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_4\ : STD_LOGIC; signal \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_5\ : STD_LOGIC; signal \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_6\ : STD_LOGIC; signal \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_7\ : STD_LOGIC; signal \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_8\ : STD_LOGIC; signal \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_9\ : STD_LOGIC; signal \MGT_RESET.SYNC_ASYNC_RESET_n_0\ : STD_LOGIC; signal \^mgt_rx_reset\ : STD_LOGIC; signal \MGT_RX_RESET_INT__0\ : STD_LOGIC; signal \^mgt_tx_reset\ : STD_LOGIC; signal \MGT_TX_RESET_INT__0\ : STD_LOGIC; signal \NO_MANAGEMENT.CONFIGURATION_VECTOR_REG[1]_i_1_n_0\ : STD_LOGIC; signal \NO_MANAGEMENT.CONFIGURATION_VECTOR_REG[2]_i_1_n_0\ : STD_LOGIC; signal \NO_MANAGEMENT.CONFIGURATION_VECTOR_REG[3]_i_1_n_0\ : STD_LOGIC; signal \^no_management.configuration_vector_reg_reg[2]_0\ : STD_LOGIC; signal \^no_management.configuration_vector_reg_reg[3]_0\ : STD_LOGIC; signal RESET_INT : STD_LOGIC; attribute async_reg : string; attribute async_reg of RESET_INT : signal is "true"; signal RESET_INT_PIPE : STD_LOGIC; attribute async_reg of RESET_INT_PIPE : signal is "true"; signal RESET_INT_PIPE_RXRECCLK : STD_LOGIC; attribute async_reg of RESET_INT_PIPE_RXRECCLK : signal is "true"; signal RESET_INT_RXRECCLK : STD_LOGIC; attribute async_reg of RESET_INT_RXRECCLK : signal is "true"; signal RXCLKCORCNT_INT : STD_LOGIC; signal RXDISPERR_SRL1_out : STD_LOGIC; signal RXEVEN0_out : STD_LOGIC; signal RXNOTINTABLE_INT : STD_LOGIC; signal RXNOTINTABLE_SRL0_out : STD_LOGIC; signal RXRECRESET : STD_LOGIC; attribute async_reg of RXRECRESET : signal is "true"; signal RXRECRESET_PIPE : STD_LOGIC; attribute async_reg of RXRECRESET_PIPE : signal is "true"; signal RXRECRESET_PIPE_1 : STD_LOGIC; attribute async_reg of RXRECRESET_PIPE_1 : signal is "true"; signal RXRECRESET_PIPE_2 : STD_LOGIC; attribute async_reg of RXRECRESET_PIPE_2 : signal is "true"; signal RXRECRESET_PIPE_3 : STD_LOGIC; attribute async_reg of RXRECRESET_PIPE_3 : signal is "true"; signal RXSYNC_STATUS : STD_LOGIC; signal \RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK_n_6\ : STD_LOGIC; signal \RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK_n_7\ : STD_LOGIC; signal S2 : STD_LOGIC; signal SIGNAL_DETECT_MOD : STD_LOGIC; signal SOFT_RESET_RXRECCLK : STD_LOGIC; signal SRESET : STD_LOGIC; attribute async_reg of SRESET : signal is "true"; signal SRESET_PIPE : STD_LOGIC; attribute async_reg of SRESET_PIPE : signal is "true"; signal STATUS_VECTOR_0_PRE : STD_LOGIC; signal STATUS_VECTOR_0_PRE0 : STD_LOGIC; signal SYNC_STATUS_REG : STD_LOGIC; signal SYNC_STATUS_REG0 : STD_LOGIC; signal TXBUFERR_INT : STD_LOGIC; signal \USE_ROCKET_IO.MGT_TX_RESET_INT_i_3_n_0\ : STD_LOGIC; signal \USE_ROCKET_IO.MGT_TX_RESET_INT_i_4_n_0\ : STD_LOGIC; signal \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXBUFSTATUS_INT_reg_n_0_[1]\ : STD_LOGIC; signal \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCHARISCOMMA_INT_reg_n_0\ : STD_LOGIC; signal \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCHARISK_INT_reg_n_0\ : STD_LOGIC; signal \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCLKCORCNT_INT_reg_n_0_[0]\ : STD_LOGIC; signal \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCLKCORCNT_INT_reg_n_0_[1]\ : STD_LOGIC; signal \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[0]\ : STD_LOGIC; signal \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[1]\ : STD_LOGIC; signal \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[2]\ : STD_LOGIC; signal \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[3]\ : STD_LOGIC; signal \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[4]\ : STD_LOGIC; signal \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[5]\ : STD_LOGIC; signal \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[6]\ : STD_LOGIC; signal \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[7]\ : STD_LOGIC; signal \USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.MGT_RX_RESET_INT_i_3_n_0\ : STD_LOGIC; signal \USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.MGT_RX_RESET_INT_i_4_n_0\ : STD_LOGIC; signal p_0_out : STD_LOGIC; signal p_1_out : STD_LOGIC; signal p_6_out : STD_LOGIC; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of \DELAY_ERROR_TXOUTCLK.DELAY_RXDISPERR\ : label is "SRL16"; attribute box_type : string; attribute box_type of \DELAY_ERROR_TXOUTCLK.DELAY_RXDISPERR\ : label is "PRIMITIVE"; attribute srl_name : string; attribute srl_name of \DELAY_ERROR_TXOUTCLK.DELAY_RXDISPERR\ : label is "U0/gig_ethernet_pcs_pma_16_1_core/\gpcs_pma_inst/DELAY_ERROR_TXOUTCLK.DELAY_RXDISPERR "; attribute XILINX_LEGACY_PRIM of \DELAY_ERROR_TXOUTCLK.DELAY_RXNOTINTABLE\ : label is "SRL16"; attribute box_type of \DELAY_ERROR_TXOUTCLK.DELAY_RXNOTINTABLE\ : label is "PRIMITIVE"; attribute srl_name of \DELAY_ERROR_TXOUTCLK.DELAY_RXNOTINTABLE\ : label is "U0/gig_ethernet_pcs_pma_16_1_core/\gpcs_pma_inst/DELAY_ERROR_TXOUTCLK.DELAY_RXNOTINTABLE "; attribute FSM_ENCODED_STATES : string; attribute FSM_ENCODED_STATES of \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[0]\ : label is "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000"; attribute FSM_ENCODED_STATES of \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[10]\ : label is "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000"; attribute FSM_ENCODED_STATES of \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[11]\ : label is "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000"; attribute FSM_ENCODED_STATES of \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[12]\ : label is "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000"; attribute FSM_ENCODED_STATES of \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[13]\ : label is "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000"; attribute FSM_ENCODED_STATES of \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[1]\ : label is "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000"; attribute FSM_ENCODED_STATES of \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[2]\ : label is "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000"; attribute FSM_ENCODED_STATES of \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[3]\ : label is "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000"; attribute FSM_ENCODED_STATES of \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[4]\ : label is "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000"; attribute FSM_ENCODED_STATES of \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[5]\ : label is "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000"; attribute FSM_ENCODED_STATES of \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[6]\ : label is "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000"; attribute FSM_ENCODED_STATES of \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[7]\ : label is "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000"; attribute FSM_ENCODED_STATES of \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[8]\ : label is "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000"; attribute FSM_ENCODED_STATES of \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[9]\ : label is "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000"; attribute FSM_ENCODED_STATES of \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[0]\ : label is "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000"; attribute FSM_ENCODED_STATES of \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[10]\ : label is "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000"; attribute FSM_ENCODED_STATES of \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[11]\ : label is "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000"; attribute FSM_ENCODED_STATES of \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[12]\ : label is "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000"; attribute FSM_ENCODED_STATES of \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[13]\ : label is "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000"; attribute FSM_ENCODED_STATES of \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[1]\ : label is "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000"; attribute FSM_ENCODED_STATES of \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[2]\ : label is "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000"; attribute FSM_ENCODED_STATES of \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[3]\ : label is "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000"; attribute FSM_ENCODED_STATES of \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[4]\ : label is "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000"; attribute FSM_ENCODED_STATES of \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[5]\ : label is "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000"; attribute FSM_ENCODED_STATES of \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[6]\ : label is "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000"; attribute FSM_ENCODED_STATES of \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[7]\ : label is "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000"; attribute FSM_ENCODED_STATES of \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[8]\ : label is "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000"; attribute FSM_ENCODED_STATES of \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[9]\ : label is "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \MGT_RESET.RESET_INT_PIPE_RXRECCLK_reg\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \MGT_RESET.RESET_INT_PIPE_RXRECCLK_reg\ : label is "yes"; attribute ASYNC_REG_boolean of \MGT_RESET.RESET_INT_PIPE_reg\ : label is std.standard.true; attribute KEEP of \MGT_RESET.RESET_INT_PIPE_reg\ : label is "yes"; attribute ASYNC_REG_boolean of \MGT_RESET.RESET_INT_RXRECCLK_reg\ : label is std.standard.true; attribute KEEP of \MGT_RESET.RESET_INT_RXRECCLK_reg\ : label is "yes"; attribute ASYNC_REG_boolean of \MGT_RESET.RESET_INT_reg\ : label is std.standard.true; attribute KEEP of \MGT_RESET.RESET_INT_reg\ : label is "yes"; attribute ASYNC_REG_boolean of \MGT_RESET.SRESET_PIPE_reg\ : label is std.standard.true; attribute KEEP of \MGT_RESET.SRESET_PIPE_reg\ : label is "yes"; attribute ASYNC_REG_boolean of \MGT_RESET.SRESET_reg\ : label is std.standard.true; attribute KEEP of \MGT_RESET.SRESET_reg\ : label is "yes"; begin MGT_RX_RESET <= \^mgt_rx_reset\; MGT_TX_RESET <= \^mgt_tx_reset\; \NO_MANAGEMENT.CONFIGURATION_VECTOR_REG_reg[2]_0\ <= \^no_management.configuration_vector_reg_reg[2]_0\; \NO_MANAGEMENT.CONFIGURATION_VECTOR_REG_reg[3]_0\ <= \^no_management.configuration_vector_reg_reg[3]_0\; \DELAY_ERROR_TXOUTCLK.DELAY_RXDISPERR\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => '0', A1 => '0', A2 => '1', A3 => '0', CE => '1', CLK => userclk2, D => D, Q => RXDISPERR_SRL1_out ); \DELAY_ERROR_TXOUTCLK.DELAY_RXNOTINTABLE\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => '0', A1 => '0', A2 => '1', A3 => '0', CE => '1', CLK => userclk2, D => RXNOTINTABLE_INT, Q => RXNOTINTABLE_SRL0_out ); \DELAY_ERROR_TXOUTCLK.RXDISPERR_REG_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => RXDISPERR_SRL1_out, Q => status_vector(5), R => '0' ); \DELAY_ERROR_TXOUTCLK.RXNOTINTABLE_REG_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => RXNOTINTABLE_SRL0_out, Q => status_vector(6), R => '0' ); \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => userclk2, CE => '1', D => '0', Q => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[0]\, S => p_0_out ); \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[9]\, Q => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[10]\, R => p_0_out ); \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[10]\, Q => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[11]\, R => p_0_out ); \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[11]\, Q => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[12]\, R => p_0_out ); \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[12]\, Q => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[13]\, R => p_0_out ); \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[0]\, Q => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[1]\, R => p_0_out ); \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[1]\, Q => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[2]\, R => p_0_out ); \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[2]\, Q => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[3]\, R => p_0_out ); \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[3]\, Q => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[4]\, R => p_0_out ); \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[4]\, Q => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[5]\, R => p_0_out ); \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[5]\, Q => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[6]\, R => p_0_out ); \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[6]\, Q => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[7]\, R => p_0_out ); \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[7]\, Q => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[8]\, R => p_0_out ); \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[8]\, Q => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[9]\, R => p_0_out ); \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => userclk2, CE => '1', D => '0', Q => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[0]\, S => p_1_out ); \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[9]\, Q => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[10]\, R => p_1_out ); \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[10]\, Q => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[11]\, R => p_1_out ); \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[11]\, Q => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[12]\, R => p_1_out ); \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[12]\, Q => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[13]\, R => p_1_out ); \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[0]\, Q => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[1]\, R => p_1_out ); \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[1]\, Q => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[2]\, R => p_1_out ); \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[2]\, Q => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[3]\, R => p_1_out ); \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[3]\, Q => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[4]\, R => p_1_out ); \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[4]\, Q => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[5]\, R => p_1_out ); \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[5]\, Q => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[6]\, R => p_1_out ); \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[6]\, Q => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[7]\, R => p_1_out ); \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[7]\, Q => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[8]\, R => p_1_out ); \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[8]\, Q => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[9]\, R => p_1_out ); \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_TX port map ( \CODE_GRP_CNT_reg[0]_0\ => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_5\, \CODE_GRP_CNT_reg[0]_1\ => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_6\, CONFIGURATION_VECTOR_REG(0) => CONFIGURATION_VECTOR_REG(1), D(3) => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_1\, D(2) => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_2\, D(1) => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_3\, D(0) => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_4\, \NO_QSGMII_CHAR.TXCHARDISPVAL_reg_0\ => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_13\, \NO_QSGMII_DATA.TXCHARISK_reg_0\ => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_7\, \NO_QSGMII_DATA.TXCHARISK_reg_1\ => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_8\, \NO_QSGMII_DATA.TXDATA_reg[2]_0\ => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_9\, \NO_QSGMII_DATA.TXDATA_reg[3]_0\ => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_10\, \NO_QSGMII_DATA.TXDATA_reg[4]_0\ => \^mgt_tx_reset\, \NO_QSGMII_DATA.TXDATA_reg[5]_0\ => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_11\, \NO_QSGMII_DATA.TXDATA_reg[7]_0\ => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_12\, \NO_QSGMII_DATA.TXDATA_reg[7]_1\(7) => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_14\, \NO_QSGMII_DATA.TXDATA_reg[7]_1\(6) => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_15\, \NO_QSGMII_DATA.TXDATA_reg[7]_1\(5) => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_16\, \NO_QSGMII_DATA.TXDATA_reg[7]_1\(4) => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_17\, \NO_QSGMII_DATA.TXDATA_reg[7]_1\(3) => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_18\, \NO_QSGMII_DATA.TXDATA_reg[7]_1\(2) => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_19\, \NO_QSGMII_DATA.TXDATA_reg[7]_1\(1) => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_20\, \NO_QSGMII_DATA.TXDATA_reg[7]_1\(0) => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_21\, SR(0) => \^no_management.configuration_vector_reg_reg[3]_0\, \USE_ROCKET_IO.MGT_TX_RESET_INT_reg\ => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_0\, gmii_tx_en => gmii_tx_en, gmii_tx_er => gmii_tx_er, gmii_txd(7 downto 0) => gmii_txd(7 downto 0), rxchariscomma(0) => rxchariscomma(0), rxcharisk(0) => rxcharisk(0), rxdata(7 downto 0) => rxdata(7 downto 0), userclk2 => userclk2 ); \MGT_RESET.RESET_INT_PIPE_RXRECCLK_reg\: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => '0', CE => '1', D => '0', PRE => p_6_out, Q => RESET_INT_PIPE_RXRECCLK ); \MGT_RESET.RESET_INT_PIPE_reg\: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => '0', PRE => \MGT_RESET.SYNC_ASYNC_RESET_n_0\, Q => RESET_INT_PIPE ); \MGT_RESET.RESET_INT_RXRECCLK_reg\: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => '0', CE => '1', D => RESET_INT_PIPE_RXRECCLK, PRE => p_6_out, Q => RESET_INT_RXRECCLK ); \MGT_RESET.RESET_INT_reg\: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => RESET_INT_PIPE, PRE => \MGT_RESET.SYNC_ASYNC_RESET_n_0\, Q => RESET_INT ); \MGT_RESET.SRESET_PIPE_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => RESET_INT, Q => SRESET_PIPE, R => '0' ); \MGT_RESET.SRESET_reg\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => SRESET_PIPE, Q => SRESET, S => RESET_INT ); \MGT_RESET.SYNC_ASYNC_RESET\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_sync_block port map ( dcm_locked => dcm_locked, reset => reset, reset_sync6_0 => \MGT_RESET.SYNC_ASYNC_RESET_n_0\, userclk2 => userclk2 ); \MGT_RESET.SYNC_ASYNC_RESET_RECCLK\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_sync_block_17 port map ( dcm_locked => dcm_locked, p_6_out => p_6_out, reset => reset, reset_out => SOFT_RESET_RXRECCLK ); \MGT_RESET.SYNC_SOFT_RESET_RECCLK\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_sync_block_18 port map ( reset_out => SOFT_RESET_RXRECCLK ); \NO_MANAGEMENT.CONFIGURATION_VECTOR_REG[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => configuration_vector(0), I1 => SRESET, O => \NO_MANAGEMENT.CONFIGURATION_VECTOR_REG[1]_i_1_n_0\ ); \NO_MANAGEMENT.CONFIGURATION_VECTOR_REG[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => configuration_vector(1), I1 => SRESET, O => \NO_MANAGEMENT.CONFIGURATION_VECTOR_REG[2]_i_1_n_0\ ); \NO_MANAGEMENT.CONFIGURATION_VECTOR_REG[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => configuration_vector(2), I1 => SRESET, O => \NO_MANAGEMENT.CONFIGURATION_VECTOR_REG[3]_i_1_n_0\ ); \NO_MANAGEMENT.CONFIGURATION_VECTOR_REG_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \NO_MANAGEMENT.CONFIGURATION_VECTOR_REG[1]_i_1_n_0\, Q => CONFIGURATION_VECTOR_REG(1), R => '0' ); \NO_MANAGEMENT.CONFIGURATION_VECTOR_REG_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \NO_MANAGEMENT.CONFIGURATION_VECTOR_REG[2]_i_1_n_0\, Q => \^no_management.configuration_vector_reg_reg[2]_0\, R => '0' ); \NO_MANAGEMENT.CONFIGURATION_VECTOR_REG_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \NO_MANAGEMENT.CONFIGURATION_VECTOR_REG[3]_i_1_n_0\, Q => \^no_management.configuration_vector_reg_reg[3]_0\, R => '0' ); \RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_RX port map ( CGBAD_reg_0 => \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXBUFSTATUS_INT_reg_n_0_[1]\, C_HDR_REMOVED_REG_reg_0(1) => \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCLKCORCNT_INT_reg_n_0_[1]\, C_HDR_REMOVED_REG_reg_0(0) => \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCLKCORCNT_INT_reg_n_0_[0]\, D => D, FALSE_NIT_reg_0 => \RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK_n_7\, I0 => I0, Q(7) => \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[7]\, Q(6) => \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[6]\, Q(5) => \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[5]\, Q(4) => \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[4]\, Q(3) => \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[3]\, Q(2) => \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[2]\, Q(1) => \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[1]\, Q(0) => \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[0]\, RUDI_I_reg_0 => \^mgt_rx_reset\, RXCHARISK_REG1_reg_0 => \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCHARISK_INT_reg_n_0\, RXEVEN0_out => RXEVEN0_out, RXNOTINTABLE_INT => RXNOTINTABLE_INT, RXSYNC_STATUS => RXSYNC_STATUS, RX_ER_reg_0 => \^no_management.configuration_vector_reg_reg[2]_0\, S2 => S2, SR(0) => \^no_management.configuration_vector_reg_reg[3]_0\, SYNC_STATUS_REG0 => SYNC_STATUS_REG0, \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCHARISK_INT_reg\ => \RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK_n_6\, gmii_rx_dv => gmii_rx_dv, gmii_rx_er => gmii_rx_er, gmii_rxd(7 downto 0) => gmii_rxd(7 downto 0), status_vector(2 downto 0) => status_vector(4 downto 2), userclk2 => userclk2 ); \RX_GMII_AT_TXOUTCLK.SYNCHRONISATION\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SYNCHRONISE port map ( CONFIGURATION_VECTOR_REG(0) => CONFIGURATION_VECTOR_REG(1), D => D, EVEN_reg_0 => \^mgt_rx_reset\, \FSM_onehot_STATE_reg[0]_0\ => \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXBUFSTATUS_INT_reg_n_0_[1]\, \FSM_onehot_STATE_reg[1]_0\ => \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCHARISCOMMA_INT_reg_n_0\, \FSM_onehot_STATE_reg[2]_0\ => \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCHARISK_INT_reg_n_0\, I0 => I0, I_reg => \RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK_n_6\, I_reg_0 => \RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK_n_7\, RXEVEN0_out => RXEVEN0_out, RXNOTINTABLE_INT => RXNOTINTABLE_INT, RXSYNC_STATUS => RXSYNC_STATUS, S2 => S2, SIGNAL_DETECT_MOD => SIGNAL_DETECT_MOD, STATUS_VECTOR_0_PRE0 => STATUS_VECTOR_0_PRE0, SYNC_STATUS_REG0 => SYNC_STATUS_REG0, enablealign => enablealign, reset_done => reset_done, userclk2 => userclk2 ); STATUS_VECTOR_0_PRE_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => STATUS_VECTOR_0_PRE0, Q => STATUS_VECTOR_0_PRE, R => '0' ); \STATUS_VECTOR_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => STATUS_VECTOR_0_PRE, Q => status_vector(0), R => '0' ); \STATUS_VECTOR_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => SYNC_STATUS_REG, Q => status_vector(1), R => '0' ); SYNC_SIGNAL_DETECT: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sync_block port map ( SIGNAL_DETECT_MOD => SIGNAL_DETECT_MOD, SIGNAL_DETECT_REG_reg => \^no_management.configuration_vector_reg_reg[2]_0\, signal_detect => signal_detect, userclk2 => userclk2 ); SYNC_STATUS_REG_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => RXSYNC_STATUS, Q => SYNC_STATUS_REG, R => '0' ); \USE_ROCKET_IO.MGT_TX_RESET_INT_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => RESET_INT, I1 => TXBUFERR_INT, O => p_1_out ); \USE_ROCKET_IO.MGT_TX_RESET_INT_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFE" ) port map ( I0 => \USE_ROCKET_IO.MGT_TX_RESET_INT_i_3_n_0\, I1 => \USE_ROCKET_IO.MGT_TX_RESET_INT_i_4_n_0\, I2 => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[6]\, I3 => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[7]\, I4 => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[4]\, I5 => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[5]\, O => \MGT_TX_RESET_INT__0\ ); \USE_ROCKET_IO.MGT_TX_RESET_INT_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFE" ) port map ( I0 => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[13]\, I1 => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[12]\, I2 => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[9]\, I3 => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[8]\, I4 => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[11]\, I5 => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[10]\, O => \USE_ROCKET_IO.MGT_TX_RESET_INT_i_3_n_0\ ); \USE_ROCKET_IO.MGT_TX_RESET_INT_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[2]\, I1 => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[3]\, I2 => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[0]\, I3 => \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[1]\, O => \USE_ROCKET_IO.MGT_TX_RESET_INT_i_4_n_0\ ); \USE_ROCKET_IO.MGT_TX_RESET_INT_reg\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \MGT_TX_RESET_INT__0\, Q => \^mgt_tx_reset\, S => p_1_out ); \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXBUFSTATUS_INT_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => rxbufstatus(0), Q => \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXBUFSTATUS_INT_reg_n_0_[1]\, R => RXCLKCORCNT_INT ); \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCHARISCOMMA_INT_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_8\, Q => \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCHARISCOMMA_INT_reg_n_0\, R => \^mgt_rx_reset\ ); \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCHARISK_INT_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_7\, Q => \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCHARISK_INT_reg_n_0\, R => \^mgt_rx_reset\ ); \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCLKCORCNT_INT_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => rxclkcorcnt(0), Q => \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCLKCORCNT_INT_reg_n_0_[0]\, R => RXCLKCORCNT_INT ); \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCLKCORCNT_INT_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => rxclkcorcnt(1), Q => \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCLKCORCNT_INT_reg_n_0_[1]\, R => RXCLKCORCNT_INT ); \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_21\, Q => \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[0]\, R => \^mgt_rx_reset\ ); \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_20\, Q => \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[1]\, R => \^mgt_rx_reset\ ); \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_19\, Q => \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[2]\, R => \^mgt_rx_reset\ ); \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_18\, Q => \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[3]\, R => \^mgt_rx_reset\ ); \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_17\, Q => \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[4]\, R => \^mgt_rx_reset\ ); \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_16\, Q => \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[5]\, R => \^mgt_rx_reset\ ); \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_15\, Q => \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[6]\, R => \^mgt_rx_reset\ ); \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_14\, Q => \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[7]\, R => \^mgt_rx_reset\ ); \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDISPERR_INT_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => rxdisperr(0), Q => D, R => RXCLKCORCNT_INT ); \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXNOTINTABLE_INT_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => CONFIGURATION_VECTOR_REG(1), I1 => \^mgt_rx_reset\, O => RXCLKCORCNT_INT ); \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXNOTINTABLE_INT_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => rxnotintable(0), Q => RXNOTINTABLE_INT, R => RXCLKCORCNT_INT ); \USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.MGT_RX_RESET_INT_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXBUFSTATUS_INT_reg_n_0_[1]\, I1 => RESET_INT, O => p_0_out ); \USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.MGT_RX_RESET_INT_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFE" ) port map ( I0 => \USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.MGT_RX_RESET_INT_i_3_n_0\, I1 => \USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.MGT_RX_RESET_INT_i_4_n_0\, I2 => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[6]\, I3 => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[7]\, I4 => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[4]\, I5 => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[5]\, O => \MGT_RX_RESET_INT__0\ ); \USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.MGT_RX_RESET_INT_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFE" ) port map ( I0 => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[13]\, I1 => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[12]\, I2 => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[9]\, I3 => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[8]\, I4 => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[11]\, I5 => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[10]\, O => \USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.MGT_RX_RESET_INT_i_3_n_0\ ); \USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.MGT_RX_RESET_INT_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[2]\, I1 => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[3]\, I2 => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[0]\, I3 => \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[1]\, O => \USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.MGT_RX_RESET_INT_i_4_n_0\ ); \USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.MGT_RX_RESET_INT_reg\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \MGT_RX_RESET_INT__0\, Q => \^mgt_rx_reset\, S => p_0_out ); \USE_ROCKET_IO.TXBUFERR_INT_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => txbuferr, Q => TXBUFERR_INT, R => \^mgt_tx_reset\ ); \USE_ROCKET_IO.TXCHARDISPMODE_reg\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_5\, Q => txchardispmode, R => \^mgt_tx_reset\ ); \USE_ROCKET_IO.TXCHARDISPVAL_reg\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_13\, Q => txchardispval, R => '0' ); \USE_ROCKET_IO.TXCHARISK_reg\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_6\, Q => txcharisk, R => \^mgt_tx_reset\ ); \USE_ROCKET_IO.TXDATA_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_4\, Q => txdata(0), R => '0' ); \USE_ROCKET_IO.TXDATA_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_3\, Q => txdata(1), R => '0' ); \USE_ROCKET_IO.TXDATA_reg[2]\: unisim.vcomponents.FDSE port map ( C => userclk2, CE => '1', D => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_9\, Q => txdata(2), S => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_0\ ); \USE_ROCKET_IO.TXDATA_reg[3]\: unisim.vcomponents.FDSE port map ( C => userclk2, CE => '1', D => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_10\, Q => txdata(3), S => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_0\ ); \USE_ROCKET_IO.TXDATA_reg[4]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_2\, Q => txdata(4), R => '0' ); \USE_ROCKET_IO.TXDATA_reg[5]\: unisim.vcomponents.FDSE port map ( C => userclk2, CE => '1', D => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_11\, Q => txdata(5), S => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_0\ ); \USE_ROCKET_IO.TXDATA_reg[6]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_1\, Q => txdata(6), R => '0' ); \USE_ROCKET_IO.TXDATA_reg[7]\: unisim.vcomponents.FDSE port map ( C => userclk2, CE => '1', D => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_12\, Q => txdata(7), S => \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_0\ ); i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '1', O => RXRECRESET ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '1', O => RXRECRESET_PIPE ); i_2: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '1', O => RXRECRESET_PIPE_1 ); i_3: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '1', O => RXRECRESET_PIPE_2 ); i_4: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '1', O => RXRECRESET_PIPE_3 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_GTWIZARD_init is port ( cplllock : out STD_LOGIC; txn : out STD_LOGIC; txp : out STD_LOGIC; rxoutclk : out STD_LOGIC; txoutclk : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 1 downto 0 ); TXBUFSTATUS : out STD_LOGIC_VECTOR ( 0 to 0 ); RXBUFSTATUS : out STD_LOGIC_VECTOR ( 0 to 0 ); independent_clock_bufg_0 : out STD_LOGIC_VECTOR ( 15 downto 0 ); independent_clock_bufg_1 : out STD_LOGIC_VECTOR ( 1 downto 0 ); independent_clock_bufg_2 : out STD_LOGIC_VECTOR ( 1 downto 0 ); independent_clock_bufg_3 : out STD_LOGIC_VECTOR ( 1 downto 0 ); independent_clock_bufg_4 : out STD_LOGIC_VECTOR ( 1 downto 0 ); mmcm_reset : out STD_LOGIC; data_in : out STD_LOGIC; rx_fsm_reset_done_int_reg : out STD_LOGIC; gtrefclk_bufg : in STD_LOGIC; independent_clock_bufg : in STD_LOGIC; gtrefclk : in STD_LOGIC; rxn : in STD_LOGIC; rxp : in STD_LOGIC; gt0_qplloutclk_in : in STD_LOGIC; gt0_qplloutrefclk_in : in STD_LOGIC; reset_out : in STD_LOGIC; reset : in STD_LOGIC; userclk : in STD_LOGIC; TXPD : in STD_LOGIC_VECTOR ( 0 to 0 ); RXPD : in STD_LOGIC_VECTOR ( 0 to 0 ); Q : in STD_LOGIC_VECTOR ( 15 downto 0 ); data_sync_reg1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); data_sync_reg1_0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); data_sync_reg1_1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); pma_reset : in STD_LOGIC; \gt0_rx_cdrlock_counter_reg[0]_0\ : in STD_LOGIC; data_sync_reg1_2 : in STD_LOGIC; mmcm_locked : in STD_LOGIC; data_out : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_GTWIZARD_init; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_GTWIZARD_init is signal \^cplllock\ : STD_LOGIC; signal gt0_cpllrefclklost_i : STD_LOGIC; signal gt0_cpllreset_t : STD_LOGIC; signal gt0_gtrxreset_in1_out : STD_LOGIC; signal gt0_gttxreset_in0_out : STD_LOGIC; signal \gt0_rx_cdrlock_counter[0]_i_1_n_0\ : STD_LOGIC; signal \gt0_rx_cdrlock_counter[0]_i_3_n_0\ : STD_LOGIC; signal \gt0_rx_cdrlock_counter[0]_i_4_n_0\ : STD_LOGIC; signal \gt0_rx_cdrlock_counter[0]_i_5_n_0\ : STD_LOGIC; signal gt0_rx_cdrlock_counter_reg : STD_LOGIC_VECTOR ( 13 downto 0 ); signal \gt0_rx_cdrlock_counter_reg[0]_i_2_n_0\ : STD_LOGIC; signal \gt0_rx_cdrlock_counter_reg[0]_i_2_n_1\ : STD_LOGIC; signal \gt0_rx_cdrlock_counter_reg[0]_i_2_n_2\ : STD_LOGIC; signal \gt0_rx_cdrlock_counter_reg[0]_i_2_n_3\ : STD_LOGIC; signal \gt0_rx_cdrlock_counter_reg[0]_i_2_n_4\ : STD_LOGIC; signal \gt0_rx_cdrlock_counter_reg[0]_i_2_n_5\ : STD_LOGIC; signal \gt0_rx_cdrlock_counter_reg[0]_i_2_n_6\ : STD_LOGIC; signal \gt0_rx_cdrlock_counter_reg[0]_i_2_n_7\ : STD_LOGIC; signal \gt0_rx_cdrlock_counter_reg[12]_i_1_n_3\ : STD_LOGIC; signal \gt0_rx_cdrlock_counter_reg[12]_i_1_n_6\ : STD_LOGIC; signal \gt0_rx_cdrlock_counter_reg[12]_i_1_n_7\ : STD_LOGIC; signal \gt0_rx_cdrlock_counter_reg[4]_i_1_n_0\ : STD_LOGIC; signal \gt0_rx_cdrlock_counter_reg[4]_i_1_n_1\ : STD_LOGIC; signal \gt0_rx_cdrlock_counter_reg[4]_i_1_n_2\ : STD_LOGIC; signal \gt0_rx_cdrlock_counter_reg[4]_i_1_n_3\ : STD_LOGIC; signal \gt0_rx_cdrlock_counter_reg[4]_i_1_n_4\ : STD_LOGIC; signal \gt0_rx_cdrlock_counter_reg[4]_i_1_n_5\ : STD_LOGIC; signal \gt0_rx_cdrlock_counter_reg[4]_i_1_n_6\ : STD_LOGIC; signal \gt0_rx_cdrlock_counter_reg[4]_i_1_n_7\ : STD_LOGIC; signal \gt0_rx_cdrlock_counter_reg[8]_i_1_n_0\ : STD_LOGIC; signal \gt0_rx_cdrlock_counter_reg[8]_i_1_n_1\ : STD_LOGIC; signal \gt0_rx_cdrlock_counter_reg[8]_i_1_n_2\ : STD_LOGIC; signal \gt0_rx_cdrlock_counter_reg[8]_i_1_n_3\ : STD_LOGIC; signal \gt0_rx_cdrlock_counter_reg[8]_i_1_n_4\ : STD_LOGIC; signal \gt0_rx_cdrlock_counter_reg[8]_i_1_n_5\ : STD_LOGIC; signal \gt0_rx_cdrlock_counter_reg[8]_i_1_n_6\ : STD_LOGIC; signal \gt0_rx_cdrlock_counter_reg[8]_i_1_n_7\ : STD_LOGIC; signal gt0_rx_cdrlocked_i_2_n_0 : STD_LOGIC; signal gt0_rx_cdrlocked_i_3_n_0 : STD_LOGIC; signal gt0_rx_cdrlocked_reg_n_0 : STD_LOGIC; signal gt0_rxresetfsm_i_n_3 : STD_LOGIC; signal gt0_rxuserrdy_t : STD_LOGIC; signal gt0_txuserrdy_t : STD_LOGIC; signal gtwizard_i_n_5 : STD_LOGIC; signal gtwizard_i_n_7 : STD_LOGIC; signal \NLW_gt0_rx_cdrlock_counter_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_gt0_rx_cdrlock_counter_reg[12]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); begin cplllock <= \^cplllock\; \gt0_rx_cdrlock_counter[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => \gt0_rx_cdrlock_counter[0]_i_3_n_0\, I1 => \gt0_rx_cdrlock_counter[0]_i_4_n_0\, I2 => gt0_rx_cdrlock_counter_reg(1), I3 => gt0_rx_cdrlock_counter_reg(0), O => \gt0_rx_cdrlock_counter[0]_i_1_n_0\ ); \gt0_rx_cdrlock_counter[0]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFDFFFFFFFFFFFFF" ) port map ( I0 => gt0_rx_cdrlock_counter_reg(13), I1 => gt0_rx_cdrlock_counter_reg(12), I2 => gt0_rx_cdrlock_counter_reg(10), I3 => gt0_rx_cdrlock_counter_reg(11), I4 => gt0_rx_cdrlock_counter_reg(9), I5 => gt0_rx_cdrlock_counter_reg(8), O => \gt0_rx_cdrlock_counter[0]_i_3_n_0\ ); \gt0_rx_cdrlock_counter[0]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFEF" ) port map ( I0 => gt0_rx_cdrlock_counter_reg(6), I1 => gt0_rx_cdrlock_counter_reg(7), I2 => gt0_rx_cdrlock_counter_reg(4), I3 => gt0_rx_cdrlock_counter_reg(5), I4 => gt0_rx_cdrlock_counter_reg(3), I5 => gt0_rx_cdrlock_counter_reg(2), O => \gt0_rx_cdrlock_counter[0]_i_4_n_0\ ); \gt0_rx_cdrlock_counter[0]_i_5\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => gt0_rx_cdrlock_counter_reg(0), O => \gt0_rx_cdrlock_counter[0]_i_5_n_0\ ); \gt0_rx_cdrlock_counter_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \gt0_rx_cdrlock_counter[0]_i_1_n_0\, D => \gt0_rx_cdrlock_counter_reg[0]_i_2_n_7\, Q => gt0_rx_cdrlock_counter_reg(0), R => gt0_gtrxreset_in1_out ); \gt0_rx_cdrlock_counter_reg[0]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \gt0_rx_cdrlock_counter_reg[0]_i_2_n_0\, CO(2) => \gt0_rx_cdrlock_counter_reg[0]_i_2_n_1\, CO(1) => \gt0_rx_cdrlock_counter_reg[0]_i_2_n_2\, CO(0) => \gt0_rx_cdrlock_counter_reg[0]_i_2_n_3\, CYINIT => '0', DI(3 downto 0) => B"0001", O(3) => \gt0_rx_cdrlock_counter_reg[0]_i_2_n_4\, O(2) => \gt0_rx_cdrlock_counter_reg[0]_i_2_n_5\, O(1) => \gt0_rx_cdrlock_counter_reg[0]_i_2_n_6\, O(0) => \gt0_rx_cdrlock_counter_reg[0]_i_2_n_7\, S(3 downto 1) => gt0_rx_cdrlock_counter_reg(3 downto 1), S(0) => \gt0_rx_cdrlock_counter[0]_i_5_n_0\ ); \gt0_rx_cdrlock_counter_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \gt0_rx_cdrlock_counter[0]_i_1_n_0\, D => \gt0_rx_cdrlock_counter_reg[8]_i_1_n_5\, Q => gt0_rx_cdrlock_counter_reg(10), R => gt0_gtrxreset_in1_out ); \gt0_rx_cdrlock_counter_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \gt0_rx_cdrlock_counter[0]_i_1_n_0\, D => \gt0_rx_cdrlock_counter_reg[8]_i_1_n_4\, Q => gt0_rx_cdrlock_counter_reg(11), R => gt0_gtrxreset_in1_out ); \gt0_rx_cdrlock_counter_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \gt0_rx_cdrlock_counter[0]_i_1_n_0\, D => \gt0_rx_cdrlock_counter_reg[12]_i_1_n_7\, Q => gt0_rx_cdrlock_counter_reg(12), R => gt0_gtrxreset_in1_out ); \gt0_rx_cdrlock_counter_reg[12]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \gt0_rx_cdrlock_counter_reg[8]_i_1_n_0\, CO(3 downto 1) => \NLW_gt0_rx_cdrlock_counter_reg[12]_i_1_CO_UNCONNECTED\(3 downto 1), CO(0) => \gt0_rx_cdrlock_counter_reg[12]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 2) => \NLW_gt0_rx_cdrlock_counter_reg[12]_i_1_O_UNCONNECTED\(3 downto 2), O(1) => \gt0_rx_cdrlock_counter_reg[12]_i_1_n_6\, O(0) => \gt0_rx_cdrlock_counter_reg[12]_i_1_n_7\, S(3 downto 2) => B"00", S(1 downto 0) => gt0_rx_cdrlock_counter_reg(13 downto 12) ); \gt0_rx_cdrlock_counter_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \gt0_rx_cdrlock_counter[0]_i_1_n_0\, D => \gt0_rx_cdrlock_counter_reg[12]_i_1_n_6\, Q => gt0_rx_cdrlock_counter_reg(13), R => gt0_gtrxreset_in1_out ); \gt0_rx_cdrlock_counter_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \gt0_rx_cdrlock_counter[0]_i_1_n_0\, D => \gt0_rx_cdrlock_counter_reg[0]_i_2_n_6\, Q => gt0_rx_cdrlock_counter_reg(1), R => gt0_gtrxreset_in1_out ); \gt0_rx_cdrlock_counter_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \gt0_rx_cdrlock_counter[0]_i_1_n_0\, D => \gt0_rx_cdrlock_counter_reg[0]_i_2_n_5\, Q => gt0_rx_cdrlock_counter_reg(2), R => gt0_gtrxreset_in1_out ); \gt0_rx_cdrlock_counter_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \gt0_rx_cdrlock_counter[0]_i_1_n_0\, D => \gt0_rx_cdrlock_counter_reg[0]_i_2_n_4\, Q => gt0_rx_cdrlock_counter_reg(3), R => gt0_gtrxreset_in1_out ); \gt0_rx_cdrlock_counter_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \gt0_rx_cdrlock_counter[0]_i_1_n_0\, D => \gt0_rx_cdrlock_counter_reg[4]_i_1_n_7\, Q => gt0_rx_cdrlock_counter_reg(4), R => gt0_gtrxreset_in1_out ); \gt0_rx_cdrlock_counter_reg[4]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \gt0_rx_cdrlock_counter_reg[0]_i_2_n_0\, CO(3) => \gt0_rx_cdrlock_counter_reg[4]_i_1_n_0\, CO(2) => \gt0_rx_cdrlock_counter_reg[4]_i_1_n_1\, CO(1) => \gt0_rx_cdrlock_counter_reg[4]_i_1_n_2\, CO(0) => \gt0_rx_cdrlock_counter_reg[4]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \gt0_rx_cdrlock_counter_reg[4]_i_1_n_4\, O(2) => \gt0_rx_cdrlock_counter_reg[4]_i_1_n_5\, O(1) => \gt0_rx_cdrlock_counter_reg[4]_i_1_n_6\, O(0) => \gt0_rx_cdrlock_counter_reg[4]_i_1_n_7\, S(3 downto 0) => gt0_rx_cdrlock_counter_reg(7 downto 4) ); \gt0_rx_cdrlock_counter_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \gt0_rx_cdrlock_counter[0]_i_1_n_0\, D => \gt0_rx_cdrlock_counter_reg[4]_i_1_n_6\, Q => gt0_rx_cdrlock_counter_reg(5), R => gt0_gtrxreset_in1_out ); \gt0_rx_cdrlock_counter_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \gt0_rx_cdrlock_counter[0]_i_1_n_0\, D => \gt0_rx_cdrlock_counter_reg[4]_i_1_n_5\, Q => gt0_rx_cdrlock_counter_reg(6), R => gt0_gtrxreset_in1_out ); \gt0_rx_cdrlock_counter_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \gt0_rx_cdrlock_counter[0]_i_1_n_0\, D => \gt0_rx_cdrlock_counter_reg[4]_i_1_n_4\, Q => gt0_rx_cdrlock_counter_reg(7), R => gt0_gtrxreset_in1_out ); \gt0_rx_cdrlock_counter_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \gt0_rx_cdrlock_counter[0]_i_1_n_0\, D => \gt0_rx_cdrlock_counter_reg[8]_i_1_n_7\, Q => gt0_rx_cdrlock_counter_reg(8), R => gt0_gtrxreset_in1_out ); \gt0_rx_cdrlock_counter_reg[8]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \gt0_rx_cdrlock_counter_reg[4]_i_1_n_0\, CO(3) => \gt0_rx_cdrlock_counter_reg[8]_i_1_n_0\, CO(2) => \gt0_rx_cdrlock_counter_reg[8]_i_1_n_1\, CO(1) => \gt0_rx_cdrlock_counter_reg[8]_i_1_n_2\, CO(0) => \gt0_rx_cdrlock_counter_reg[8]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \gt0_rx_cdrlock_counter_reg[8]_i_1_n_4\, O(2) => \gt0_rx_cdrlock_counter_reg[8]_i_1_n_5\, O(1) => \gt0_rx_cdrlock_counter_reg[8]_i_1_n_6\, O(0) => \gt0_rx_cdrlock_counter_reg[8]_i_1_n_7\, S(3 downto 0) => gt0_rx_cdrlock_counter_reg(11 downto 8) ); \gt0_rx_cdrlock_counter_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => independent_clock_bufg, CE => \gt0_rx_cdrlock_counter[0]_i_1_n_0\, D => \gt0_rx_cdrlock_counter_reg[8]_i_1_n_6\, Q => gt0_rx_cdrlock_counter_reg(9), R => gt0_gtrxreset_in1_out ); gt0_rx_cdrlocked_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000200000000000" ) port map ( I0 => gt0_rx_cdrlock_counter_reg(10), I1 => gt0_rx_cdrlock_counter_reg(11), I2 => gt0_rx_cdrlock_counter_reg(8), I3 => gt0_rx_cdrlock_counter_reg(9), I4 => gt0_rx_cdrlock_counter_reg(12), I5 => gt0_rx_cdrlock_counter_reg(13), O => gt0_rx_cdrlocked_i_2_n_0 ); gt0_rx_cdrlocked_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000002" ) port map ( I0 => gt0_rx_cdrlock_counter_reg(4), I1 => gt0_rx_cdrlock_counter_reg(5), I2 => gt0_rx_cdrlock_counter_reg(2), I3 => gt0_rx_cdrlock_counter_reg(3), I4 => gt0_rx_cdrlock_counter_reg(7), I5 => gt0_rx_cdrlock_counter_reg(6), O => gt0_rx_cdrlocked_i_3_n_0 ); gt0_rx_cdrlocked_reg: unisim.vcomponents.FDRE port map ( C => independent_clock_bufg, CE => '1', D => gt0_rxresetfsm_i_n_3, Q => gt0_rx_cdrlocked_reg_n_0, R => '0' ); gt0_rxresetfsm_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_RX_STARTUP_FSM port map ( cplllock => \^cplllock\, data_in => rx_fsm_reset_done_int_reg, data_out => data_out, data_sync_reg1 => gtwizard_i_n_5, gt0_gtrxreset_in1_out => gt0_gtrxreset_in1_out, gt0_rx_cdrlock_counter_reg(1 downto 0) => gt0_rx_cdrlock_counter_reg(1 downto 0), gt0_rx_cdrlock_counter_reg_0_sp_1 => \gt0_rx_cdrlock_counter_reg[0]_0\, gt0_rx_cdrlocked_reg => gt0_rxresetfsm_i_n_3, gt0_rx_cdrlocked_reg_0 => gt0_rx_cdrlocked_reg_n_0, gt0_rx_cdrlocked_reg_1 => gt0_rx_cdrlocked_i_2_n_0, gt0_rx_cdrlocked_reg_2 => gt0_rx_cdrlocked_i_3_n_0, gt0_rxuserrdy_t => gt0_rxuserrdy_t, independent_clock_bufg => independent_clock_bufg, mmcm_locked => mmcm_locked, pma_reset => pma_reset, userclk => userclk ); gt0_txresetfsm_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_TX_STARTUP_FSM port map ( cplllock => \^cplllock\, data_in => data_in, data_sync_reg1 => data_sync_reg1_2, data_sync_reg1_0 => gtwizard_i_n_7, gt0_cpllrefclklost_i => gt0_cpllrefclklost_i, gt0_cpllreset_t => gt0_cpllreset_t, gt0_gttxreset_in0_out => gt0_gttxreset_in0_out, gt0_txuserrdy_t => gt0_txuserrdy_t, independent_clock_bufg => independent_clock_bufg, mmcm_locked => mmcm_locked, mmcm_reset => mmcm_reset, pma_reset => pma_reset, userclk => userclk ); gtwizard_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_GTWIZARD_multi_gt port map ( D(1 downto 0) => D(1 downto 0), Q(15 downto 0) => Q(15 downto 0), RXBUFSTATUS(0) => RXBUFSTATUS(0), RXPD(0) => RXPD(0), TXBUFSTATUS(0) => TXBUFSTATUS(0), TXPD(0) => TXPD(0), cplllock => \^cplllock\, data_sync_reg1(1 downto 0) => data_sync_reg1(1 downto 0), data_sync_reg1_0(1 downto 0) => data_sync_reg1_0(1 downto 0), data_sync_reg1_1(1 downto 0) => data_sync_reg1_1(1 downto 0), gt0_cpllrefclklost_i => gt0_cpllrefclklost_i, gt0_cpllreset_t => gt0_cpllreset_t, gt0_gtrxreset_in1_out => gt0_gtrxreset_in1_out, gt0_gttxreset_in0_out => gt0_gttxreset_in0_out, gt0_qplloutclk_in => gt0_qplloutclk_in, gt0_qplloutrefclk_in => gt0_qplloutrefclk_in, gt0_rxuserrdy_t => gt0_rxuserrdy_t, gt0_txuserrdy_t => gt0_txuserrdy_t, gtrefclk => gtrefclk, gtrefclk_bufg => gtrefclk_bufg, independent_clock_bufg => independent_clock_bufg, independent_clock_bufg_0 => gtwizard_i_n_5, independent_clock_bufg_1 => gtwizard_i_n_7, independent_clock_bufg_2(15 downto 0) => independent_clock_bufg_0(15 downto 0), independent_clock_bufg_3(1 downto 0) => independent_clock_bufg_1(1 downto 0), independent_clock_bufg_4(1 downto 0) => independent_clock_bufg_2(1 downto 0), independent_clock_bufg_5(1 downto 0) => independent_clock_bufg_3(1 downto 0), independent_clock_bufg_6(1 downto 0) => independent_clock_bufg_4(1 downto 0), reset => reset, reset_out => reset_out, rxn => rxn, rxoutclk => rxoutclk, rxp => rxp, txn => txn, txoutclk => txoutclk, txp => txp, userclk => userclk ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_v16_1_5 is port ( reset : in STD_LOGIC; signal_detect : in STD_LOGIC; link_timer_value : in STD_LOGIC_VECTOR ( 9 downto 0 ); link_timer_basex : in STD_LOGIC_VECTOR ( 9 downto 0 ); link_timer_sgmii : in STD_LOGIC_VECTOR ( 9 downto 0 ); rx_gt_nominal_latency : in STD_LOGIC_VECTOR ( 15 downto 0 ); speed_is_10_100 : in STD_LOGIC; speed_is_100 : in STD_LOGIC; mgt_rx_reset : out STD_LOGIC; mgt_tx_reset : out STD_LOGIC; userclk : in STD_LOGIC; userclk2 : in STD_LOGIC; dcm_locked : in STD_LOGIC; rxbufstatus : in STD_LOGIC_VECTOR ( 1 downto 0 ); rxchariscomma : in STD_LOGIC_VECTOR ( 0 to 0 ); rxcharisk : in STD_LOGIC_VECTOR ( 0 to 0 ); rxclkcorcnt : in STD_LOGIC_VECTOR ( 2 downto 0 ); rxdata : in STD_LOGIC_VECTOR ( 7 downto 0 ); rxdisperr : in STD_LOGIC_VECTOR ( 0 to 0 ); rxnotintable : in STD_LOGIC_VECTOR ( 0 to 0 ); rxrundisp : in STD_LOGIC_VECTOR ( 0 to 0 ); txbuferr : in STD_LOGIC; powerdown : out STD_LOGIC; txchardispmode : out STD_LOGIC; txchardispval : out STD_LOGIC; txcharisk : out STD_LOGIC; txdata : out STD_LOGIC_VECTOR ( 7 downto 0 ); enablealign : out STD_LOGIC; gtx_clk : in STD_LOGIC; tx_code_group : out STD_LOGIC_VECTOR ( 9 downto 0 ); loc_ref : out STD_LOGIC; ewrap : out STD_LOGIC; rx_code_group0 : in STD_LOGIC_VECTOR ( 9 downto 0 ); rx_code_group1 : in STD_LOGIC_VECTOR ( 9 downto 0 ); pma_rx_clk0 : in STD_LOGIC; pma_rx_clk1 : in STD_LOGIC; en_cdet : out STD_LOGIC; gmii_txd : in STD_LOGIC_VECTOR ( 7 downto 0 ); gmii_tx_en : in STD_LOGIC; gmii_tx_er : in STD_LOGIC; gmii_rxd : out STD_LOGIC_VECTOR ( 7 downto 0 ); gmii_rx_dv : out STD_LOGIC; gmii_rx_er : out STD_LOGIC; gmii_isolate : out STD_LOGIC; an_interrupt : out STD_LOGIC; an_enable : out STD_LOGIC; speed_selection : out STD_LOGIC_VECTOR ( 1 downto 0 ); phyad : in STD_LOGIC_VECTOR ( 4 downto 0 ); mdc : in STD_LOGIC; mdio_in : in STD_LOGIC; mdio_out : out STD_LOGIC; mdio_tri : out STD_LOGIC; an_adv_config_vector : in STD_LOGIC_VECTOR ( 15 downto 0 ); an_adv_config_val : in STD_LOGIC; an_restart_config : in STD_LOGIC; configuration_vector : in STD_LOGIC_VECTOR ( 4 downto 0 ); configuration_valid : in STD_LOGIC; status_vector : out STD_LOGIC_VECTOR ( 15 downto 0 ); basex_or_sgmii : in STD_LOGIC; drp_dclk : in STD_LOGIC; drp_req : out STD_LOGIC; drp_gnt : in STD_LOGIC; drp_den : out STD_LOGIC; drp_dwe : out STD_LOGIC; drp_drdy : in STD_LOGIC; drp_daddr : out STD_LOGIC_VECTOR ( 9 downto 0 ); drp_di : out STD_LOGIC_VECTOR ( 15 downto 0 ); drp_do : in STD_LOGIC_VECTOR ( 15 downto 0 ); systemtimer_s_field : in STD_LOGIC_VECTOR ( 47 downto 0 ); systemtimer_ns_field : in STD_LOGIC_VECTOR ( 31 downto 0 ); correction_timer : in STD_LOGIC_VECTOR ( 63 downto 0 ); rxrecclk : in STD_LOGIC; rxphy_s_field : out STD_LOGIC_VECTOR ( 47 downto 0 ); rxphy_ns_field : out STD_LOGIC_VECTOR ( 31 downto 0 ); rxphy_correction_timer : out STD_LOGIC_VECTOR ( 63 downto 0 ); s_axi_aclk : in STD_LOGIC; s_axi_resetn : in STD_LOGIC; s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; reset_done : in STD_LOGIC ); attribute B_SHIFTER_ADDR : string; attribute B_SHIFTER_ADDR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_v16_1_5 : entity is "10'b0101001110"; attribute C_1588 : integer; attribute C_1588 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_v16_1_5 : entity is 0; attribute C_2_5G : string; attribute C_2_5G of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_v16_1_5 : entity is "FALSE"; attribute C_COMPONENT_NAME : string; attribute C_COMPONENT_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_v16_1_5 : entity is "gig_ethernet_pcs_pma_16_1"; attribute C_DYNAMIC_SWITCHING : string; attribute C_DYNAMIC_SWITCHING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_v16_1_5 : entity is "FALSE"; attribute C_ELABORATION_TRANSIENT_DIR : string; attribute C_ELABORATION_TRANSIENT_DIR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_v16_1_5 : entity is "BlankString"; attribute C_FAMILY : string; attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_v16_1_5 : entity is "kintex7"; attribute C_HAS_AN : string; attribute C_HAS_AN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_v16_1_5 : entity is "FALSE"; attribute C_HAS_AXIL : string; attribute C_HAS_AXIL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_v16_1_5 : entity is "FALSE"; attribute C_HAS_MDIO : string; attribute C_HAS_MDIO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_v16_1_5 : entity is "FALSE"; attribute C_HAS_TEMAC : string; attribute C_HAS_TEMAC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_v16_1_5 : entity is "TRUE"; attribute C_IS_SGMII : string; attribute C_IS_SGMII of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_v16_1_5 : entity is "FALSE"; attribute C_RX_GMII_CLK : string; attribute C_RX_GMII_CLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_v16_1_5 : entity is "TXOUTCLK"; attribute C_SGMII_FABRIC_BUFFER : string; attribute C_SGMII_FABRIC_BUFFER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_v16_1_5 : entity is "TRUE"; attribute C_SGMII_PHY_MODE : string; attribute C_SGMII_PHY_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_v16_1_5 : entity is "FALSE"; attribute C_USE_LVDS : string; attribute C_USE_LVDS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_v16_1_5 : entity is "FALSE"; attribute C_USE_TBI : string; attribute C_USE_TBI of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_v16_1_5 : entity is "FALSE"; attribute C_USE_TRANSCEIVER : string; attribute C_USE_TRANSCEIVER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_v16_1_5 : entity is "TRUE"; attribute GT_RX_BYTE_WIDTH : integer; attribute GT_RX_BYTE_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_v16_1_5 : entity is 1; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_v16_1_5 : entity is "yes"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_v16_1_5; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_v16_1_5 is signal \\ : STD_LOGIC; signal \^status_vector\ : STD_LOGIC_VECTOR ( 6 downto 0 ); begin an_enable <= \\; an_interrupt <= \\; drp_daddr(9) <= \\; drp_daddr(8) <= \\; drp_daddr(7) <= \\; drp_daddr(6) <= \\; drp_daddr(5) <= \\; drp_daddr(4) <= \\; drp_daddr(3) <= \\; drp_daddr(2) <= \\; drp_daddr(1) <= \\; drp_daddr(0) <= \\; drp_den <= \\; drp_di(15) <= \\; drp_di(14) <= \\; drp_di(13) <= \\; drp_di(12) <= \\; drp_di(11) <= \\; drp_di(10) <= \\; drp_di(9) <= \\; drp_di(8) <= \\; drp_di(7) <= \\; drp_di(6) <= \\; drp_di(5) <= \\; drp_di(4) <= \\; drp_di(3) <= \\; drp_di(2) <= \\; drp_di(1) <= \\; drp_di(0) <= \\; drp_dwe <= \\; drp_req <= \\; en_cdet <= \\; ewrap <= \\; loc_ref <= \\; mdio_out <= \\; mdio_tri <= \\; rxphy_correction_timer(63) <= \\; rxphy_correction_timer(62) <= \\; rxphy_correction_timer(61) <= \\; rxphy_correction_timer(60) <= \\; rxphy_correction_timer(59) <= \\; rxphy_correction_timer(58) <= \\; rxphy_correction_timer(57) <= \\; rxphy_correction_timer(56) <= \\; rxphy_correction_timer(55) <= \\; rxphy_correction_timer(54) <= \\; rxphy_correction_timer(53) <= \\; rxphy_correction_timer(52) <= \\; rxphy_correction_timer(51) <= \\; rxphy_correction_timer(50) <= \\; rxphy_correction_timer(49) <= \\; rxphy_correction_timer(48) <= \\; rxphy_correction_timer(47) <= \\; rxphy_correction_timer(46) <= \\; rxphy_correction_timer(45) <= \\; rxphy_correction_timer(44) <= \\; rxphy_correction_timer(43) <= \\; rxphy_correction_timer(42) <= \\; rxphy_correction_timer(41) <= \\; rxphy_correction_timer(40) <= \\; rxphy_correction_timer(39) <= \\; rxphy_correction_timer(38) <= \\; rxphy_correction_timer(37) <= \\; rxphy_correction_timer(36) <= \\; rxphy_correction_timer(35) <= \\; rxphy_correction_timer(34) <= \\; rxphy_correction_timer(33) <= \\; rxphy_correction_timer(32) <= \\; rxphy_correction_timer(31) <= \\; rxphy_correction_timer(30) <= \\; rxphy_correction_timer(29) <= \\; rxphy_correction_timer(28) <= \\; rxphy_correction_timer(27) <= \\; rxphy_correction_timer(26) <= \\; rxphy_correction_timer(25) <= \\; rxphy_correction_timer(24) <= \\; rxphy_correction_timer(23) <= \\; rxphy_correction_timer(22) <= \\; rxphy_correction_timer(21) <= \\; rxphy_correction_timer(20) <= \\; rxphy_correction_timer(19) <= \\; rxphy_correction_timer(18) <= \\; rxphy_correction_timer(17) <= \\; rxphy_correction_timer(16) <= \\; rxphy_correction_timer(15) <= \\; rxphy_correction_timer(14) <= \\; rxphy_correction_timer(13) <= \\; rxphy_correction_timer(12) <= \\; rxphy_correction_timer(11) <= \\; rxphy_correction_timer(10) <= \\; rxphy_correction_timer(9) <= \\; rxphy_correction_timer(8) <= \\; rxphy_correction_timer(7) <= \\; rxphy_correction_timer(6) <= \\; rxphy_correction_timer(5) <= \\; rxphy_correction_timer(4) <= \\; rxphy_correction_timer(3) <= \\; rxphy_correction_timer(2) <= \\; rxphy_correction_timer(1) <= \\; rxphy_correction_timer(0) <= \\; rxphy_ns_field(31) <= \\; rxphy_ns_field(30) <= \\; rxphy_ns_field(29) <= \\; rxphy_ns_field(28) <= \\; rxphy_ns_field(27) <= \\; rxphy_ns_field(26) <= \\; rxphy_ns_field(25) <= \\; rxphy_ns_field(24) <= \\; rxphy_ns_field(23) <= \\; rxphy_ns_field(22) <= \\; rxphy_ns_field(21) <= \\; rxphy_ns_field(20) <= \\; rxphy_ns_field(19) <= \\; rxphy_ns_field(18) <= \\; rxphy_ns_field(17) <= \\; rxphy_ns_field(16) <= \\; rxphy_ns_field(15) <= \\; rxphy_ns_field(14) <= \\; rxphy_ns_field(13) <= \\; rxphy_ns_field(12) <= \\; rxphy_ns_field(11) <= \\; rxphy_ns_field(10) <= \\; rxphy_ns_field(9) <= \\; rxphy_ns_field(8) <= \\; rxphy_ns_field(7) <= \\; rxphy_ns_field(6) <= \\; rxphy_ns_field(5) <= \\; rxphy_ns_field(4) <= \\; rxphy_ns_field(3) <= \\; rxphy_ns_field(2) <= \\; rxphy_ns_field(1) <= \\; rxphy_ns_field(0) <= \\; rxphy_s_field(47) <= \\; rxphy_s_field(46) <= \\; rxphy_s_field(45) <= \\; rxphy_s_field(44) <= \\; rxphy_s_field(43) <= \\; rxphy_s_field(42) <= \\; rxphy_s_field(41) <= \\; rxphy_s_field(40) <= \\; rxphy_s_field(39) <= \\; rxphy_s_field(38) <= \\; rxphy_s_field(37) <= \\; rxphy_s_field(36) <= \\; rxphy_s_field(35) <= \\; rxphy_s_field(34) <= \\; rxphy_s_field(33) <= \\; rxphy_s_field(32) <= \\; rxphy_s_field(31) <= \\; rxphy_s_field(30) <= \\; rxphy_s_field(29) <= \\; rxphy_s_field(28) <= \\; rxphy_s_field(27) <= \\; rxphy_s_field(26) <= \\; rxphy_s_field(25) <= \\; rxphy_s_field(24) <= \\; rxphy_s_field(23) <= \\; rxphy_s_field(22) <= \\; rxphy_s_field(21) <= \\; rxphy_s_field(20) <= \\; rxphy_s_field(19) <= \\; rxphy_s_field(18) <= \\; rxphy_s_field(17) <= \\; rxphy_s_field(16) <= \\; rxphy_s_field(15) <= \\; rxphy_s_field(14) <= \\; rxphy_s_field(13) <= \\; rxphy_s_field(12) <= \\; rxphy_s_field(11) <= \\; rxphy_s_field(10) <= \\; rxphy_s_field(9) <= \\; rxphy_s_field(8) <= \\; rxphy_s_field(7) <= \\; rxphy_s_field(6) <= \\; rxphy_s_field(5) <= \\; rxphy_s_field(4) <= \\; rxphy_s_field(3) <= \\; rxphy_s_field(2) <= \\; rxphy_s_field(1) <= \\; rxphy_s_field(0) <= \\; s_axi_arready <= \\; s_axi_awready <= \\; s_axi_bresp(1) <= \\; s_axi_bresp(0) <= \\; s_axi_bvalid <= \\; s_axi_rdata(31) <= \\; s_axi_rdata(30) <= \\; s_axi_rdata(29) <= \\; s_axi_rdata(28) <= \\; s_axi_rdata(27) <= \\; s_axi_rdata(26) <= \\; s_axi_rdata(25) <= \\; s_axi_rdata(24) <= \\; s_axi_rdata(23) <= \\; s_axi_rdata(22) <= \\; s_axi_rdata(21) <= \\; s_axi_rdata(20) <= \\; s_axi_rdata(19) <= \\; s_axi_rdata(18) <= \\; s_axi_rdata(17) <= \\; s_axi_rdata(16) <= \\; s_axi_rdata(15) <= \\; s_axi_rdata(14) <= \\; s_axi_rdata(13) <= \\; s_axi_rdata(12) <= \\; s_axi_rdata(11) <= \\; s_axi_rdata(10) <= \\; s_axi_rdata(9) <= \\; s_axi_rdata(8) <= \\; s_axi_rdata(7) <= \\; s_axi_rdata(6) <= \\; s_axi_rdata(5) <= \\; s_axi_rdata(4) <= \\; s_axi_rdata(3) <= \\; s_axi_rdata(2) <= \\; s_axi_rdata(1) <= \\; s_axi_rdata(0) <= \\; s_axi_rresp(1) <= \\; s_axi_rresp(0) <= \\; s_axi_rvalid <= \\; s_axi_wready <= \\; speed_selection(1) <= \\; speed_selection(0) <= \\; status_vector(15) <= \\; status_vector(14) <= \\; status_vector(13) <= \\; status_vector(12) <= \\; status_vector(11) <= \\; status_vector(10) <= \\; status_vector(9) <= \\; status_vector(8) <= \\; status_vector(7) <= \\; status_vector(6 downto 0) <= \^status_vector\(6 downto 0); tx_code_group(9) <= \\; tx_code_group(8) <= \\; tx_code_group(7) <= \\; tx_code_group(6) <= \\; tx_code_group(5) <= \\; tx_code_group(4) <= \\; tx_code_group(3) <= \\; tx_code_group(2) <= \\; tx_code_group(1) <= \\; tx_code_group(0) <= \\; GND: unisim.vcomponents.GND port map ( G => \\ ); gpcs_pma_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPCS_PMA_GEN port map ( MGT_RX_RESET => mgt_rx_reset, MGT_TX_RESET => mgt_tx_reset, \NO_MANAGEMENT.CONFIGURATION_VECTOR_REG_reg[2]_0\ => powerdown, \NO_MANAGEMENT.CONFIGURATION_VECTOR_REG_reg[3]_0\ => gmii_isolate, configuration_vector(2 downto 0) => configuration_vector(3 downto 1), dcm_locked => dcm_locked, enablealign => enablealign, gmii_rx_dv => gmii_rx_dv, gmii_rx_er => gmii_rx_er, gmii_rxd(7 downto 0) => gmii_rxd(7 downto 0), gmii_tx_en => gmii_tx_en, gmii_tx_er => gmii_tx_er, gmii_txd(7 downto 0) => gmii_txd(7 downto 0), reset => reset, reset_done => reset_done, rxbufstatus(0) => rxbufstatus(1), rxchariscomma(0) => rxchariscomma(0), rxcharisk(0) => rxcharisk(0), rxclkcorcnt(1 downto 0) => rxclkcorcnt(1 downto 0), rxdata(7 downto 0) => rxdata(7 downto 0), rxdisperr(0) => rxdisperr(0), rxnotintable(0) => rxnotintable(0), signal_detect => signal_detect, status_vector(6 downto 0) => \^status_vector\(6 downto 0), txbuferr => txbuferr, txchardispmode => txchardispmode, txchardispval => txchardispval, txcharisk => txcharisk, txdata(7 downto 0) => txdata(7 downto 0), userclk2 => userclk2 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_GTWIZARD is port ( cplllock : out STD_LOGIC; txn : out STD_LOGIC; txp : out STD_LOGIC; rxoutclk : out STD_LOGIC; txoutclk : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 1 downto 0 ); TXBUFSTATUS : out STD_LOGIC_VECTOR ( 0 to 0 ); RXBUFSTATUS : out STD_LOGIC_VECTOR ( 0 to 0 ); independent_clock_bufg_0 : out STD_LOGIC_VECTOR ( 15 downto 0 ); independent_clock_bufg_1 : out STD_LOGIC_VECTOR ( 1 downto 0 ); independent_clock_bufg_2 : out STD_LOGIC_VECTOR ( 1 downto 0 ); independent_clock_bufg_3 : out STD_LOGIC_VECTOR ( 1 downto 0 ); independent_clock_bufg_4 : out STD_LOGIC_VECTOR ( 1 downto 0 ); mmcm_reset : out STD_LOGIC; data_in : out STD_LOGIC; rx_fsm_reset_done_int_reg : out STD_LOGIC; gtrefclk_bufg : in STD_LOGIC; independent_clock_bufg : in STD_LOGIC; gtrefclk : in STD_LOGIC; rxn : in STD_LOGIC; rxp : in STD_LOGIC; gt0_qplloutclk_in : in STD_LOGIC; gt0_qplloutrefclk_in : in STD_LOGIC; reset_out : in STD_LOGIC; reset : in STD_LOGIC; userclk : in STD_LOGIC; TXPD : in STD_LOGIC_VECTOR ( 0 to 0 ); RXPD : in STD_LOGIC_VECTOR ( 0 to 0 ); Q : in STD_LOGIC_VECTOR ( 15 downto 0 ); data_sync_reg1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); data_sync_reg1_0 : in STD_LOGIC_VECTOR ( 1 downto 0 ); data_sync_reg1_1 : in STD_LOGIC_VECTOR ( 1 downto 0 ); pma_reset : in STD_LOGIC; \gt0_rx_cdrlock_counter_reg[0]\ : in STD_LOGIC; data_sync_reg1_2 : in STD_LOGIC; mmcm_locked : in STD_LOGIC; data_out : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_GTWIZARD; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_GTWIZARD is begin U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_GTWIZARD_init port map ( D(1 downto 0) => D(1 downto 0), Q(15 downto 0) => Q(15 downto 0), RXBUFSTATUS(0) => RXBUFSTATUS(0), RXPD(0) => RXPD(0), TXBUFSTATUS(0) => TXBUFSTATUS(0), TXPD(0) => TXPD(0), cplllock => cplllock, data_in => data_in, data_out => data_out, data_sync_reg1(1 downto 0) => data_sync_reg1(1 downto 0), data_sync_reg1_0(1 downto 0) => data_sync_reg1_0(1 downto 0), data_sync_reg1_1(1 downto 0) => data_sync_reg1_1(1 downto 0), data_sync_reg1_2 => data_sync_reg1_2, gt0_qplloutclk_in => gt0_qplloutclk_in, gt0_qplloutrefclk_in => gt0_qplloutrefclk_in, \gt0_rx_cdrlock_counter_reg[0]_0\ => \gt0_rx_cdrlock_counter_reg[0]\, gtrefclk => gtrefclk, gtrefclk_bufg => gtrefclk_bufg, independent_clock_bufg => independent_clock_bufg, independent_clock_bufg_0(15 downto 0) => independent_clock_bufg_0(15 downto 0), independent_clock_bufg_1(1 downto 0) => independent_clock_bufg_1(1 downto 0), independent_clock_bufg_2(1 downto 0) => independent_clock_bufg_2(1 downto 0), independent_clock_bufg_3(1 downto 0) => independent_clock_bufg_3(1 downto 0), independent_clock_bufg_4(1 downto 0) => independent_clock_bufg_4(1 downto 0), mmcm_locked => mmcm_locked, mmcm_reset => mmcm_reset, pma_reset => pma_reset, reset => reset, reset_out => reset_out, rx_fsm_reset_done_int_reg => rx_fsm_reset_done_int_reg, rxn => rxn, rxoutclk => rxoutclk, rxp => rxp, txn => txn, txoutclk => txoutclk, txp => txp, userclk => userclk ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_transceiver is port ( cplllock : out STD_LOGIC; txn : out STD_LOGIC; txp : out STD_LOGIC; rxoutclk : out STD_LOGIC; txoutclk : out STD_LOGIC; data_in : out STD_LOGIC; rx_fsm_reset_done_int_reg : out STD_LOGIC; rxchariscomma : out STD_LOGIC; rxcharisk : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 1 downto 0 ); \rxdata_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); rxdisperr : out STD_LOGIC; rxnotintable : out STD_LOGIC; rxbuferr : out STD_LOGIC; txbuferr : out STD_LOGIC; mmcm_reset : out STD_LOGIC; gtrefclk_bufg : in STD_LOGIC; status_vector : in STD_LOGIC_VECTOR ( 0 to 0 ); independent_clock_bufg : in STD_LOGIC; userclk : in STD_LOGIC; enablealign : in STD_LOGIC; SR : in STD_LOGIC_VECTOR ( 0 to 0 ); reset_sync5 : in STD_LOGIC_VECTOR ( 0 to 0 ); gtrefclk : in STD_LOGIC; rxn : in STD_LOGIC; rxp : in STD_LOGIC; gt0_qplloutclk_in : in STD_LOGIC; gt0_qplloutrefclk_in : in STD_LOGIC; mmcm_locked : in STD_LOGIC; pma_reset : in STD_LOGIC; userclk2 : in STD_LOGIC; powerdown : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 0 to 0 ); txchardispval_reg_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); \txdata_reg_reg[7]_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); txcharisk_reg_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_transceiver; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_transceiver is signal data_valid_reg2 : STD_LOGIC; signal encommaalign_int : STD_LOGIC; signal gtwizard_inst_n_7 : STD_LOGIC; signal gtwizard_inst_n_8 : STD_LOGIC; signal p_0_in : STD_LOGIC; signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 ); signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \p_1_in__1\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \p_1_in__2\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal reset : STD_LOGIC; signal rxchariscomma_double : STD_LOGIC_VECTOR ( 1 downto 0 ); signal rxchariscomma_i_1_n_0 : STD_LOGIC; signal rxchariscomma_int : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \rxchariscomma_reg__0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal rxcharisk_double : STD_LOGIC_VECTOR ( 1 downto 0 ); signal rxcharisk_i_1_n_0 : STD_LOGIC; signal rxcharisk_int : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \rxcharisk_reg__0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal rxclkcorcnt_double : STD_LOGIC_VECTOR ( 1 downto 0 ); signal rxclkcorcnt_int : STD_LOGIC_VECTOR ( 1 downto 0 ); signal rxclkcorcnt_reg : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \rxdata[0]_i_1_n_0\ : STD_LOGIC; signal \rxdata[1]_i_1_n_0\ : STD_LOGIC; signal \rxdata[2]_i_1_n_0\ : STD_LOGIC; signal \rxdata[3]_i_1_n_0\ : STD_LOGIC; signal \rxdata[4]_i_1_n_0\ : STD_LOGIC; signal \rxdata[5]_i_1_n_0\ : STD_LOGIC; signal \rxdata[6]_i_1_n_0\ : STD_LOGIC; signal \rxdata[7]_i_1_n_0\ : STD_LOGIC; signal rxdata_double : STD_LOGIC_VECTOR ( 15 downto 0 ); signal rxdata_int : STD_LOGIC_VECTOR ( 15 downto 0 ); signal rxdata_reg : STD_LOGIC_VECTOR ( 15 downto 0 ); signal rxdisperr_double : STD_LOGIC_VECTOR ( 1 downto 0 ); signal rxdisperr_i_1_n_0 : STD_LOGIC; signal rxdisperr_int : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \rxdisperr_reg__0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal rxnotintable_double : STD_LOGIC_VECTOR ( 1 downto 0 ); signal rxnotintable_i_1_n_0 : STD_LOGIC; signal rxnotintable_int : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \rxnotintable_reg__0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal rxpowerdown : STD_LOGIC; signal rxpowerdown_double : STD_LOGIC; signal \rxpowerdown_reg__0\ : STD_LOGIC; signal rxreset_int : STD_LOGIC; signal toggle : STD_LOGIC; signal toggle_i_1_n_0 : STD_LOGIC; signal txbufstatus_reg : STD_LOGIC_VECTOR ( 1 to 1 ); signal txchardispmode_double : STD_LOGIC_VECTOR ( 1 downto 0 ); signal txchardispmode_int : STD_LOGIC_VECTOR ( 1 downto 0 ); signal txchardispval_double : STD_LOGIC_VECTOR ( 1 downto 0 ); signal txchardispval_int : STD_LOGIC_VECTOR ( 1 downto 0 ); signal txcharisk_double : STD_LOGIC_VECTOR ( 1 downto 0 ); signal txcharisk_int : STD_LOGIC_VECTOR ( 1 downto 0 ); signal txdata_double : STD_LOGIC_VECTOR ( 15 downto 0 ); signal txdata_int : STD_LOGIC_VECTOR ( 15 downto 0 ); signal txpowerdown : STD_LOGIC; signal txpowerdown_double : STD_LOGIC; signal \txpowerdown_reg__0\ : STD_LOGIC; signal txreset_int : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of rxchariscomma_i_1 : label is "soft_lutpair81"; attribute SOFT_HLUTNM of rxcharisk_i_1 : label is "soft_lutpair81"; attribute SOFT_HLUTNM of \rxdata[0]_i_1\ : label is "soft_lutpair77"; attribute SOFT_HLUTNM of \rxdata[1]_i_1\ : label is "soft_lutpair77"; attribute SOFT_HLUTNM of \rxdata[2]_i_1\ : label is "soft_lutpair78"; attribute SOFT_HLUTNM of \rxdata[3]_i_1\ : label is "soft_lutpair78"; attribute SOFT_HLUTNM of \rxdata[4]_i_1\ : label is "soft_lutpair79"; attribute SOFT_HLUTNM of \rxdata[5]_i_1\ : label is "soft_lutpair79"; attribute SOFT_HLUTNM of \rxdata[6]_i_1\ : label is "soft_lutpair80"; attribute SOFT_HLUTNM of \rxdata[7]_i_1\ : label is "soft_lutpair80"; attribute SOFT_HLUTNM of rxdisperr_i_1 : label is "soft_lutpair82"; attribute SOFT_HLUTNM of rxnotintable_i_1 : label is "soft_lutpair82"; begin gtwizard_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_GTWIZARD port map ( D(1 downto 0) => rxclkcorcnt_int(1 downto 0), Q(15 downto 0) => txdata_int(15 downto 0), RXBUFSTATUS(0) => gtwizard_inst_n_8, RXPD(0) => rxpowerdown, TXBUFSTATUS(0) => gtwizard_inst_n_7, TXPD(0) => txpowerdown, cplllock => cplllock, data_in => data_in, data_out => data_valid_reg2, data_sync_reg1(1 downto 0) => txchardispmode_int(1 downto 0), data_sync_reg1_0(1 downto 0) => txchardispval_int(1 downto 0), data_sync_reg1_1(1 downto 0) => txcharisk_int(1 downto 0), data_sync_reg1_2 => txreset_int, gt0_qplloutclk_in => gt0_qplloutclk_in, gt0_qplloutrefclk_in => gt0_qplloutrefclk_in, \gt0_rx_cdrlock_counter_reg[0]\ => rxreset_int, gtrefclk => gtrefclk, gtrefclk_bufg => gtrefclk_bufg, independent_clock_bufg => independent_clock_bufg, independent_clock_bufg_0(15 downto 0) => rxdata_int(15 downto 0), independent_clock_bufg_1(1 downto 0) => rxchariscomma_int(1 downto 0), independent_clock_bufg_2(1 downto 0) => rxcharisk_int(1 downto 0), independent_clock_bufg_3(1 downto 0) => rxdisperr_int(1 downto 0), independent_clock_bufg_4(1 downto 0) => rxnotintable_int(1 downto 0), mmcm_locked => mmcm_locked, mmcm_reset => mmcm_reset, pma_reset => pma_reset, reset => reset, reset_out => encommaalign_int, rx_fsm_reset_done_int_reg => rx_fsm_reset_done_int_reg, rxn => rxn, rxoutclk => rxoutclk, rxp => rxp, txn => txn, txoutclk => txoutclk, txp => txp, userclk => userclk ); reclock_encommaalign: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_reset_sync port map ( enablealign => enablealign, reset_out => encommaalign_int, userclk => userclk ); reclock_rxreset: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_reset_sync_1 port map ( independent_clock_bufg => independent_clock_bufg, reset_out => rxreset_int, reset_sync5_0(0) => reset_sync5(0) ); reclock_txreset: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_reset_sync_2 port map ( SR(0) => SR(0), independent_clock_bufg => independent_clock_bufg, reset_out => txreset_int ); reset_wtd_timer: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_reset_wtd_timer port map ( data_out => data_valid_reg2, independent_clock_bufg => independent_clock_bufg, reset => reset ); rxbuferr_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => p_0_in, Q => rxbuferr, R => '0' ); \rxbufstatus_reg_reg[2]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => gtwizard_inst_n_8, Q => p_0_in, R => '0' ); \rxchariscomma_double_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => \rxchariscomma_reg__0\(0), Q => rxchariscomma_double(0), R => reset_sync5(0) ); \rxchariscomma_double_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => \rxchariscomma_reg__0\(1), Q => rxchariscomma_double(1), R => reset_sync5(0) ); rxchariscomma_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => rxchariscomma_double(1), I1 => toggle, I2 => rxchariscomma_double(0), O => rxchariscomma_i_1_n_0 ); rxchariscomma_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => rxchariscomma_i_1_n_0, Q => rxchariscomma, R => reset_sync5(0) ); \rxchariscomma_reg_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxchariscomma_int(0), Q => \rxchariscomma_reg__0\(0), R => '0' ); \rxchariscomma_reg_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxchariscomma_int(1), Q => \rxchariscomma_reg__0\(1), R => '0' ); \rxcharisk_double_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => \rxcharisk_reg__0\(0), Q => rxcharisk_double(0), R => reset_sync5(0) ); \rxcharisk_double_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => \rxcharisk_reg__0\(1), Q => rxcharisk_double(1), R => reset_sync5(0) ); rxcharisk_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => rxcharisk_double(1), I1 => toggle, I2 => rxcharisk_double(0), O => rxcharisk_i_1_n_0 ); rxcharisk_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => rxcharisk_i_1_n_0, Q => rxcharisk, R => reset_sync5(0) ); \rxcharisk_reg_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxcharisk_int(0), Q => \rxcharisk_reg__0\(0), R => '0' ); \rxcharisk_reg_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxcharisk_int(1), Q => \rxcharisk_reg__0\(1), R => '0' ); \rxclkcorcnt_double_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => rxclkcorcnt_reg(0), Q => rxclkcorcnt_double(0), R => reset_sync5(0) ); \rxclkcorcnt_double_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => rxclkcorcnt_reg(1), Q => rxclkcorcnt_double(1), R => reset_sync5(0) ); \rxclkcorcnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => rxclkcorcnt_double(0), Q => Q(0), R => reset_sync5(0) ); \rxclkcorcnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => rxclkcorcnt_double(1), Q => Q(1), R => reset_sync5(0) ); \rxclkcorcnt_reg_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxclkcorcnt_int(0), Q => rxclkcorcnt_reg(0), R => '0' ); \rxclkcorcnt_reg_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxclkcorcnt_int(1), Q => rxclkcorcnt_reg(1), R => '0' ); \rxdata[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => rxdata_double(8), I1 => toggle, I2 => rxdata_double(0), O => \rxdata[0]_i_1_n_0\ ); \rxdata[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => rxdata_double(9), I1 => toggle, I2 => rxdata_double(1), O => \rxdata[1]_i_1_n_0\ ); \rxdata[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => rxdata_double(10), I1 => toggle, I2 => rxdata_double(2), O => \rxdata[2]_i_1_n_0\ ); \rxdata[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => rxdata_double(11), I1 => toggle, I2 => rxdata_double(3), O => \rxdata[3]_i_1_n_0\ ); \rxdata[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => rxdata_double(12), I1 => toggle, I2 => rxdata_double(4), O => \rxdata[4]_i_1_n_0\ ); \rxdata[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => rxdata_double(13), I1 => toggle, I2 => rxdata_double(5), O => \rxdata[5]_i_1_n_0\ ); \rxdata[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => rxdata_double(14), I1 => toggle, I2 => rxdata_double(6), O => \rxdata[6]_i_1_n_0\ ); \rxdata[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => rxdata_double(15), I1 => toggle, I2 => rxdata_double(7), O => \rxdata[7]_i_1_n_0\ ); \rxdata_double_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => rxdata_reg(0), Q => rxdata_double(0), R => reset_sync5(0) ); \rxdata_double_reg[10]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => rxdata_reg(10), Q => rxdata_double(10), R => reset_sync5(0) ); \rxdata_double_reg[11]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => rxdata_reg(11), Q => rxdata_double(11), R => reset_sync5(0) ); \rxdata_double_reg[12]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => rxdata_reg(12), Q => rxdata_double(12), R => reset_sync5(0) ); \rxdata_double_reg[13]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => rxdata_reg(13), Q => rxdata_double(13), R => reset_sync5(0) ); \rxdata_double_reg[14]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => rxdata_reg(14), Q => rxdata_double(14), R => reset_sync5(0) ); \rxdata_double_reg[15]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => rxdata_reg(15), Q => rxdata_double(15), R => reset_sync5(0) ); \rxdata_double_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => rxdata_reg(1), Q => rxdata_double(1), R => reset_sync5(0) ); \rxdata_double_reg[2]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => rxdata_reg(2), Q => rxdata_double(2), R => reset_sync5(0) ); \rxdata_double_reg[3]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => rxdata_reg(3), Q => rxdata_double(3), R => reset_sync5(0) ); \rxdata_double_reg[4]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => rxdata_reg(4), Q => rxdata_double(4), R => reset_sync5(0) ); \rxdata_double_reg[5]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => rxdata_reg(5), Q => rxdata_double(5), R => reset_sync5(0) ); \rxdata_double_reg[6]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => rxdata_reg(6), Q => rxdata_double(6), R => reset_sync5(0) ); \rxdata_double_reg[7]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => rxdata_reg(7), Q => rxdata_double(7), R => reset_sync5(0) ); \rxdata_double_reg[8]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => rxdata_reg(8), Q => rxdata_double(8), R => reset_sync5(0) ); \rxdata_double_reg[9]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => rxdata_reg(9), Q => rxdata_double(9), R => reset_sync5(0) ); \rxdata_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \rxdata[0]_i_1_n_0\, Q => \rxdata_reg[7]_0\(0), R => reset_sync5(0) ); \rxdata_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \rxdata[1]_i_1_n_0\, Q => \rxdata_reg[7]_0\(1), R => reset_sync5(0) ); \rxdata_reg[2]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \rxdata[2]_i_1_n_0\, Q => \rxdata_reg[7]_0\(2), R => reset_sync5(0) ); \rxdata_reg[3]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \rxdata[3]_i_1_n_0\, Q => \rxdata_reg[7]_0\(3), R => reset_sync5(0) ); \rxdata_reg[4]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \rxdata[4]_i_1_n_0\, Q => \rxdata_reg[7]_0\(4), R => reset_sync5(0) ); \rxdata_reg[5]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \rxdata[5]_i_1_n_0\, Q => \rxdata_reg[7]_0\(5), R => reset_sync5(0) ); \rxdata_reg[6]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \rxdata[6]_i_1_n_0\, Q => \rxdata_reg[7]_0\(6), R => reset_sync5(0) ); \rxdata_reg[7]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \rxdata[7]_i_1_n_0\, Q => \rxdata_reg[7]_0\(7), R => reset_sync5(0) ); \rxdata_reg_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxdata_int(0), Q => rxdata_reg(0), R => '0' ); \rxdata_reg_reg[10]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxdata_int(10), Q => rxdata_reg(10), R => '0' ); \rxdata_reg_reg[11]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxdata_int(11), Q => rxdata_reg(11), R => '0' ); \rxdata_reg_reg[12]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxdata_int(12), Q => rxdata_reg(12), R => '0' ); \rxdata_reg_reg[13]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxdata_int(13), Q => rxdata_reg(13), R => '0' ); \rxdata_reg_reg[14]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxdata_int(14), Q => rxdata_reg(14), R => '0' ); \rxdata_reg_reg[15]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxdata_int(15), Q => rxdata_reg(15), R => '0' ); \rxdata_reg_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxdata_int(1), Q => rxdata_reg(1), R => '0' ); \rxdata_reg_reg[2]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxdata_int(2), Q => rxdata_reg(2), R => '0' ); \rxdata_reg_reg[3]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxdata_int(3), Q => rxdata_reg(3), R => '0' ); \rxdata_reg_reg[4]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxdata_int(4), Q => rxdata_reg(4), R => '0' ); \rxdata_reg_reg[5]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxdata_int(5), Q => rxdata_reg(5), R => '0' ); \rxdata_reg_reg[6]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxdata_int(6), Q => rxdata_reg(6), R => '0' ); \rxdata_reg_reg[7]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxdata_int(7), Q => rxdata_reg(7), R => '0' ); \rxdata_reg_reg[8]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxdata_int(8), Q => rxdata_reg(8), R => '0' ); \rxdata_reg_reg[9]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxdata_int(9), Q => rxdata_reg(9), R => '0' ); \rxdisperr_double_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => \rxdisperr_reg__0\(0), Q => rxdisperr_double(0), R => reset_sync5(0) ); \rxdisperr_double_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => \rxdisperr_reg__0\(1), Q => rxdisperr_double(1), R => reset_sync5(0) ); rxdisperr_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => rxdisperr_double(1), I1 => toggle, I2 => rxdisperr_double(0), O => rxdisperr_i_1_n_0 ); rxdisperr_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => rxdisperr_i_1_n_0, Q => rxdisperr, R => reset_sync5(0) ); \rxdisperr_reg_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxdisperr_int(0), Q => \rxdisperr_reg__0\(0), R => '0' ); \rxdisperr_reg_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxdisperr_int(1), Q => \rxdisperr_reg__0\(1), R => '0' ); \rxnotintable_double_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => \rxnotintable_reg__0\(0), Q => rxnotintable_double(0), R => reset_sync5(0) ); \rxnotintable_double_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle, D => \rxnotintable_reg__0\(1), Q => rxnotintable_double(1), R => reset_sync5(0) ); rxnotintable_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => rxnotintable_double(1), I1 => toggle, I2 => rxnotintable_double(0), O => rxnotintable_i_1_n_0 ); rxnotintable_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => rxnotintable_i_1_n_0, Q => rxnotintable, R => reset_sync5(0) ); \rxnotintable_reg_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxnotintable_int(0), Q => \rxnotintable_reg__0\(0), R => '0' ); \rxnotintable_reg_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => rxnotintable_int(1), Q => \rxnotintable_reg__0\(1), R => '0' ); rxpowerdown_double_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => toggle, D => \rxpowerdown_reg__0\, Q => rxpowerdown_double, R => reset_sync5(0) ); rxpowerdown_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk, CE => '1', D => rxpowerdown_double, Q => rxpowerdown, R => '0' ); rxpowerdown_reg_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => powerdown, Q => \rxpowerdown_reg__0\, R => reset_sync5(0) ); sync_block_data_valid: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_3 port map ( data_out => data_valid_reg2, independent_clock_bufg => independent_clock_bufg, status_vector(0) => status_vector(0) ); toggle_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => toggle, O => toggle_i_1_n_0 ); toggle_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => toggle_i_1_n_0, Q => toggle, R => SR(0) ); txbuferr_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => txbufstatus_reg(1), Q => txbuferr, R => '0' ); \txbufstatus_reg_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => gtwizard_inst_n_7, Q => txbufstatus_reg(1), R => '0' ); \txchardispmode_double_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => p_1_in(0), Q => txchardispmode_double(0), R => SR(0) ); \txchardispmode_double_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => D(0), Q => txchardispmode_double(1), R => SR(0) ); \txchardispmode_int_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txchardispmode_double(0), Q => txchardispmode_int(0), R => '0' ); \txchardispmode_int_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txchardispmode_double(1), Q => txchardispmode_int(1), R => '0' ); txchardispmode_reg_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => D(0), Q => p_1_in(0), R => SR(0) ); \txchardispval_double_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => \p_1_in__0\(0), Q => txchardispval_double(0), R => SR(0) ); \txchardispval_double_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => txchardispval_reg_reg_0(0), Q => txchardispval_double(1), R => SR(0) ); \txchardispval_int_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txchardispval_double(0), Q => txchardispval_int(0), R => '0' ); \txchardispval_int_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txchardispval_double(1), Q => txchardispval_int(1), R => '0' ); txchardispval_reg_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => txchardispval_reg_reg_0(0), Q => \p_1_in__0\(0), R => SR(0) ); \txcharisk_double_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => \p_1_in__2\(0), Q => txcharisk_double(0), R => SR(0) ); \txcharisk_double_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => txcharisk_reg_reg_0(0), Q => txcharisk_double(1), R => SR(0) ); \txcharisk_int_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txcharisk_double(0), Q => txcharisk_int(0), R => '0' ); \txcharisk_int_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txcharisk_double(1), Q => txcharisk_int(1), R => '0' ); txcharisk_reg_reg: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => txcharisk_reg_reg_0(0), Q => \p_1_in__2\(0), R => SR(0) ); \txdata_double_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => \p_1_in__1\(0), Q => txdata_double(0), R => SR(0) ); \txdata_double_reg[10]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => \txdata_reg_reg[7]_0\(2), Q => txdata_double(10), R => SR(0) ); \txdata_double_reg[11]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => \txdata_reg_reg[7]_0\(3), Q => txdata_double(11), R => SR(0) ); \txdata_double_reg[12]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => \txdata_reg_reg[7]_0\(4), Q => txdata_double(12), R => SR(0) ); \txdata_double_reg[13]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => \txdata_reg_reg[7]_0\(5), Q => txdata_double(13), R => SR(0) ); \txdata_double_reg[14]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => \txdata_reg_reg[7]_0\(6), Q => txdata_double(14), R => SR(0) ); \txdata_double_reg[15]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => \txdata_reg_reg[7]_0\(7), Q => txdata_double(15), R => SR(0) ); \txdata_double_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => \p_1_in__1\(1), Q => txdata_double(1), R => SR(0) ); \txdata_double_reg[2]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => \p_1_in__1\(2), Q => txdata_double(2), R => SR(0) ); \txdata_double_reg[3]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => \p_1_in__1\(3), Q => txdata_double(3), R => SR(0) ); \txdata_double_reg[4]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => \p_1_in__1\(4), Q => txdata_double(4), R => SR(0) ); \txdata_double_reg[5]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => \p_1_in__1\(5), Q => txdata_double(5), R => SR(0) ); \txdata_double_reg[6]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => \p_1_in__1\(6), Q => txdata_double(6), R => SR(0) ); \txdata_double_reg[7]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => \p_1_in__1\(7), Q => txdata_double(7), R => SR(0) ); \txdata_double_reg[8]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => \txdata_reg_reg[7]_0\(0), Q => txdata_double(8), R => SR(0) ); \txdata_double_reg[9]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => toggle_i_1_n_0, D => \txdata_reg_reg[7]_0\(1), Q => txdata_double(9), R => SR(0) ); \txdata_int_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txdata_double(0), Q => txdata_int(0), R => '0' ); \txdata_int_reg[10]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txdata_double(10), Q => txdata_int(10), R => '0' ); \txdata_int_reg[11]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txdata_double(11), Q => txdata_int(11), R => '0' ); \txdata_int_reg[12]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txdata_double(12), Q => txdata_int(12), R => '0' ); \txdata_int_reg[13]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txdata_double(13), Q => txdata_int(13), R => '0' ); \txdata_int_reg[14]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txdata_double(14), Q => txdata_int(14), R => '0' ); \txdata_int_reg[15]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txdata_double(15), Q => txdata_int(15), R => '0' ); \txdata_int_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txdata_double(1), Q => txdata_int(1), R => '0' ); \txdata_int_reg[2]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txdata_double(2), Q => txdata_int(2), R => '0' ); \txdata_int_reg[3]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txdata_double(3), Q => txdata_int(3), R => '0' ); \txdata_int_reg[4]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txdata_double(4), Q => txdata_int(4), R => '0' ); \txdata_int_reg[5]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txdata_double(5), Q => txdata_int(5), R => '0' ); \txdata_int_reg[6]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txdata_double(6), Q => txdata_int(6), R => '0' ); \txdata_int_reg[7]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txdata_double(7), Q => txdata_int(7), R => '0' ); \txdata_int_reg[8]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txdata_double(8), Q => txdata_int(8), R => '0' ); \txdata_int_reg[9]\: unisim.vcomponents.FDRE port map ( C => userclk, CE => '1', D => txdata_double(9), Q => txdata_int(9), R => '0' ); \txdata_reg_reg[0]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \txdata_reg_reg[7]_0\(0), Q => \p_1_in__1\(0), R => SR(0) ); \txdata_reg_reg[1]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \txdata_reg_reg[7]_0\(1), Q => \p_1_in__1\(1), R => SR(0) ); \txdata_reg_reg[2]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \txdata_reg_reg[7]_0\(2), Q => \p_1_in__1\(2), R => SR(0) ); \txdata_reg_reg[3]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \txdata_reg_reg[7]_0\(3), Q => \p_1_in__1\(3), R => SR(0) ); \txdata_reg_reg[4]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \txdata_reg_reg[7]_0\(4), Q => \p_1_in__1\(4), R => SR(0) ); \txdata_reg_reg[5]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \txdata_reg_reg[7]_0\(5), Q => \p_1_in__1\(5), R => SR(0) ); \txdata_reg_reg[6]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \txdata_reg_reg[7]_0\(6), Q => \p_1_in__1\(6), R => SR(0) ); \txdata_reg_reg[7]\: unisim.vcomponents.FDRE port map ( C => userclk2, CE => '1', D => \txdata_reg_reg[7]_0\(7), Q => \p_1_in__1\(7), R => SR(0) ); txpowerdown_double_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => \txpowerdown_reg__0\, Q => txpowerdown_double, R => SR(0) ); txpowerdown_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk, CE => '1', D => txpowerdown_double, Q => txpowerdown, R => '0' ); txpowerdown_reg_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => userclk2, CE => '1', D => powerdown, Q => \txpowerdown_reg__0\, R => SR(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_block is port ( gtrefclk : in STD_LOGIC; gtrefclk_bufg : in STD_LOGIC; txp : out STD_LOGIC; txn : out STD_LOGIC; rxp : in STD_LOGIC; rxn : in STD_LOGIC; txoutclk : out STD_LOGIC; rxoutclk : out STD_LOGIC; resetdone : out STD_LOGIC; cplllock : out STD_LOGIC; mmcm_reset : out STD_LOGIC; mmcm_locked : in STD_LOGIC; userclk : in STD_LOGIC; userclk2 : in STD_LOGIC; rxuserclk : in STD_LOGIC; rxuserclk2 : in STD_LOGIC; independent_clock_bufg : in STD_LOGIC; pma_reset : in STD_LOGIC; gmii_txd : in STD_LOGIC_VECTOR ( 7 downto 0 ); gmii_tx_en : in STD_LOGIC; gmii_tx_er : in STD_LOGIC; gmii_rxd : out STD_LOGIC_VECTOR ( 7 downto 0 ); gmii_rx_dv : out STD_LOGIC; gmii_rx_er : out STD_LOGIC; gmii_isolate : out STD_LOGIC; configuration_vector : in STD_LOGIC_VECTOR ( 4 downto 0 ); status_vector : out STD_LOGIC_VECTOR ( 15 downto 0 ); reset : in STD_LOGIC; signal_detect : in STD_LOGIC; gt0_qplloutclk_in : in STD_LOGIC; gt0_qplloutrefclk_in : in STD_LOGIC ); attribute EXAMPLE_SIMULATION : integer; attribute EXAMPLE_SIMULATION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_block : entity is 0; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_block : entity is "yes"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_block; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_block is signal \\ : STD_LOGIC; signal enablealign : STD_LOGIC; signal mgt_rx_reset : STD_LOGIC; signal mgt_tx_reset : STD_LOGIC; signal powerdown : STD_LOGIC; signal \^resetdone\ : STD_LOGIC; signal rx_reset_done_i : STD_LOGIC; signal rxbuferr : STD_LOGIC; signal rxchariscomma : STD_LOGIC; signal rxcharisk : STD_LOGIC; signal rxclkcorcnt : STD_LOGIC_VECTOR ( 1 downto 0 ); signal rxdata : STD_LOGIC_VECTOR ( 7 downto 0 ); signal rxdisperr : STD_LOGIC; signal rxnotintable : STD_LOGIC; signal \^status_vector\ : STD_LOGIC_VECTOR ( 6 downto 0 ); signal transceiver_inst_n_5 : STD_LOGIC; signal transceiver_inst_n_6 : STD_LOGIC; signal txbuferr : STD_LOGIC; signal txchardispmode : STD_LOGIC; signal txchardispval : STD_LOGIC; signal txcharisk : STD_LOGIC; signal txdata : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_gig_ethernet_pcs_pma_16_1_core_an_enable_UNCONNECTED : STD_LOGIC; signal NLW_gig_ethernet_pcs_pma_16_1_core_an_interrupt_UNCONNECTED : STD_LOGIC; signal NLW_gig_ethernet_pcs_pma_16_1_core_drp_den_UNCONNECTED : STD_LOGIC; signal NLW_gig_ethernet_pcs_pma_16_1_core_drp_dwe_UNCONNECTED : STD_LOGIC; signal NLW_gig_ethernet_pcs_pma_16_1_core_drp_req_UNCONNECTED : STD_LOGIC; signal NLW_gig_ethernet_pcs_pma_16_1_core_en_cdet_UNCONNECTED : STD_LOGIC; signal NLW_gig_ethernet_pcs_pma_16_1_core_ewrap_UNCONNECTED : STD_LOGIC; signal NLW_gig_ethernet_pcs_pma_16_1_core_loc_ref_UNCONNECTED : STD_LOGIC; signal NLW_gig_ethernet_pcs_pma_16_1_core_mdio_out_UNCONNECTED : STD_LOGIC; signal NLW_gig_ethernet_pcs_pma_16_1_core_mdio_tri_UNCONNECTED : STD_LOGIC; signal NLW_gig_ethernet_pcs_pma_16_1_core_s_axi_arready_UNCONNECTED : STD_LOGIC; signal NLW_gig_ethernet_pcs_pma_16_1_core_s_axi_awready_UNCONNECTED : STD_LOGIC; signal NLW_gig_ethernet_pcs_pma_16_1_core_s_axi_bvalid_UNCONNECTED : STD_LOGIC; signal NLW_gig_ethernet_pcs_pma_16_1_core_s_axi_rvalid_UNCONNECTED : STD_LOGIC; signal NLW_gig_ethernet_pcs_pma_16_1_core_s_axi_wready_UNCONNECTED : STD_LOGIC; signal NLW_gig_ethernet_pcs_pma_16_1_core_drp_daddr_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 ); signal NLW_gig_ethernet_pcs_pma_16_1_core_drp_di_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); signal NLW_gig_ethernet_pcs_pma_16_1_core_rxphy_correction_timer_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); signal NLW_gig_ethernet_pcs_pma_16_1_core_rxphy_ns_field_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_gig_ethernet_pcs_pma_16_1_core_rxphy_s_field_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 ); signal NLW_gig_ethernet_pcs_pma_16_1_core_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_gig_ethernet_pcs_pma_16_1_core_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_gig_ethernet_pcs_pma_16_1_core_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_gig_ethernet_pcs_pma_16_1_core_speed_selection_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_gig_ethernet_pcs_pma_16_1_core_status_vector_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 7 ); signal NLW_gig_ethernet_pcs_pma_16_1_core_tx_code_group_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 ); attribute B_SHIFTER_ADDR : string; attribute B_SHIFTER_ADDR of gig_ethernet_pcs_pma_16_1_core : label is "10'b0101001110"; attribute C_1588 : integer; attribute C_1588 of gig_ethernet_pcs_pma_16_1_core : label is 0; attribute C_2_5G : string; attribute C_2_5G of gig_ethernet_pcs_pma_16_1_core : label is "FALSE"; attribute C_COMPONENT_NAME : string; attribute C_COMPONENT_NAME of gig_ethernet_pcs_pma_16_1_core : label is "gig_ethernet_pcs_pma_16_1"; attribute C_DYNAMIC_SWITCHING : string; attribute C_DYNAMIC_SWITCHING of gig_ethernet_pcs_pma_16_1_core : label is "FALSE"; attribute C_ELABORATION_TRANSIENT_DIR : string; attribute C_ELABORATION_TRANSIENT_DIR of gig_ethernet_pcs_pma_16_1_core : label is "BlankString"; attribute C_FAMILY : string; attribute C_FAMILY of gig_ethernet_pcs_pma_16_1_core : label is "kintex7"; attribute C_HAS_AN : string; attribute C_HAS_AN of gig_ethernet_pcs_pma_16_1_core : label is "FALSE"; attribute C_HAS_AXIL : string; attribute C_HAS_AXIL of gig_ethernet_pcs_pma_16_1_core : label is "FALSE"; attribute C_HAS_MDIO : string; attribute C_HAS_MDIO of gig_ethernet_pcs_pma_16_1_core : label is "FALSE"; attribute C_HAS_TEMAC : string; attribute C_HAS_TEMAC of gig_ethernet_pcs_pma_16_1_core : label is "TRUE"; attribute C_IS_SGMII : string; attribute C_IS_SGMII of gig_ethernet_pcs_pma_16_1_core : label is "FALSE"; attribute C_RX_GMII_CLK : string; attribute C_RX_GMII_CLK of gig_ethernet_pcs_pma_16_1_core : label is "TXOUTCLK"; attribute C_SGMII_FABRIC_BUFFER : string; attribute C_SGMII_FABRIC_BUFFER of gig_ethernet_pcs_pma_16_1_core : label is "TRUE"; attribute C_SGMII_PHY_MODE : string; attribute C_SGMII_PHY_MODE of gig_ethernet_pcs_pma_16_1_core : label is "FALSE"; attribute C_USE_LVDS : string; attribute C_USE_LVDS of gig_ethernet_pcs_pma_16_1_core : label is "FALSE"; attribute C_USE_TBI : string; attribute C_USE_TBI of gig_ethernet_pcs_pma_16_1_core : label is "FALSE"; attribute C_USE_TRANSCEIVER : string; attribute C_USE_TRANSCEIVER of gig_ethernet_pcs_pma_16_1_core : label is "TRUE"; attribute GT_RX_BYTE_WIDTH : integer; attribute GT_RX_BYTE_WIDTH of gig_ethernet_pcs_pma_16_1_core : label is 1; attribute downgradeipidentifiedwarnings of gig_ethernet_pcs_pma_16_1_core : label is "yes"; begin resetdone <= \^resetdone\; status_vector(15) <= \\; status_vector(14) <= \\; status_vector(13) <= \\; status_vector(12) <= \\; status_vector(11) <= \\; status_vector(10) <= \\; status_vector(9) <= \\; status_vector(8) <= \\; status_vector(7) <= \\; status_vector(6 downto 0) <= \^status_vector\(6 downto 0); GND: unisim.vcomponents.GND port map ( G => \\ ); gig_ethernet_pcs_pma_16_1_core: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_v16_1_5 port map ( an_adv_config_val => '0', an_adv_config_vector(15 downto 0) => B"0000000000000000", an_enable => NLW_gig_ethernet_pcs_pma_16_1_core_an_enable_UNCONNECTED, an_interrupt => NLW_gig_ethernet_pcs_pma_16_1_core_an_interrupt_UNCONNECTED, an_restart_config => '0', basex_or_sgmii => '0', configuration_valid => '0', configuration_vector(4) => '0', configuration_vector(3 downto 1) => configuration_vector(3 downto 1), configuration_vector(0) => '0', correction_timer(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", dcm_locked => mmcm_locked, drp_daddr(9 downto 0) => NLW_gig_ethernet_pcs_pma_16_1_core_drp_daddr_UNCONNECTED(9 downto 0), drp_dclk => '0', drp_den => NLW_gig_ethernet_pcs_pma_16_1_core_drp_den_UNCONNECTED, drp_di(15 downto 0) => NLW_gig_ethernet_pcs_pma_16_1_core_drp_di_UNCONNECTED(15 downto 0), drp_do(15 downto 0) => B"0000000000000000", drp_drdy => '0', drp_dwe => NLW_gig_ethernet_pcs_pma_16_1_core_drp_dwe_UNCONNECTED, drp_gnt => '0', drp_req => NLW_gig_ethernet_pcs_pma_16_1_core_drp_req_UNCONNECTED, en_cdet => NLW_gig_ethernet_pcs_pma_16_1_core_en_cdet_UNCONNECTED, enablealign => enablealign, ewrap => NLW_gig_ethernet_pcs_pma_16_1_core_ewrap_UNCONNECTED, gmii_isolate => gmii_isolate, gmii_rx_dv => gmii_rx_dv, gmii_rx_er => gmii_rx_er, gmii_rxd(7 downto 0) => gmii_rxd(7 downto 0), gmii_tx_en => gmii_tx_en, gmii_tx_er => gmii_tx_er, gmii_txd(7 downto 0) => gmii_txd(7 downto 0), gtx_clk => '0', link_timer_basex(9 downto 0) => B"0000000000", link_timer_sgmii(9 downto 0) => B"0000000000", link_timer_value(9 downto 0) => B"0000000000", loc_ref => NLW_gig_ethernet_pcs_pma_16_1_core_loc_ref_UNCONNECTED, mdc => '0', mdio_in => '0', mdio_out => NLW_gig_ethernet_pcs_pma_16_1_core_mdio_out_UNCONNECTED, mdio_tri => NLW_gig_ethernet_pcs_pma_16_1_core_mdio_tri_UNCONNECTED, mgt_rx_reset => mgt_rx_reset, mgt_tx_reset => mgt_tx_reset, phyad(4 downto 0) => B"00000", pma_rx_clk0 => '0', pma_rx_clk1 => '0', powerdown => powerdown, reset => reset, reset_done => \^resetdone\, rx_code_group0(9 downto 0) => B"0000000000", rx_code_group1(9 downto 0) => B"0000000000", rx_gt_nominal_latency(15 downto 0) => B"0000000011111000", rxbufstatus(1) => rxbuferr, rxbufstatus(0) => '0', rxchariscomma(0) => rxchariscomma, rxcharisk(0) => rxcharisk, rxclkcorcnt(2) => '0', rxclkcorcnt(1 downto 0) => rxclkcorcnt(1 downto 0), rxdata(7 downto 0) => rxdata(7 downto 0), rxdisperr(0) => rxdisperr, rxnotintable(0) => rxnotintable, rxphy_correction_timer(63 downto 0) => NLW_gig_ethernet_pcs_pma_16_1_core_rxphy_correction_timer_UNCONNECTED(63 downto 0), rxphy_ns_field(31 downto 0) => NLW_gig_ethernet_pcs_pma_16_1_core_rxphy_ns_field_UNCONNECTED(31 downto 0), rxphy_s_field(47 downto 0) => NLW_gig_ethernet_pcs_pma_16_1_core_rxphy_s_field_UNCONNECTED(47 downto 0), rxrecclk => '0', rxrundisp(0) => '0', s_axi_aclk => '0', s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_arready => NLW_gig_ethernet_pcs_pma_16_1_core_s_axi_arready_UNCONNECTED, s_axi_arvalid => '0', s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_awready => NLW_gig_ethernet_pcs_pma_16_1_core_s_axi_awready_UNCONNECTED, s_axi_awvalid => '0', s_axi_bready => '0', s_axi_bresp(1 downto 0) => NLW_gig_ethernet_pcs_pma_16_1_core_s_axi_bresp_UNCONNECTED(1 downto 0), s_axi_bvalid => NLW_gig_ethernet_pcs_pma_16_1_core_s_axi_bvalid_UNCONNECTED, s_axi_rdata(31 downto 0) => NLW_gig_ethernet_pcs_pma_16_1_core_s_axi_rdata_UNCONNECTED(31 downto 0), s_axi_resetn => '0', s_axi_rready => '0', s_axi_rresp(1 downto 0) => NLW_gig_ethernet_pcs_pma_16_1_core_s_axi_rresp_UNCONNECTED(1 downto 0), s_axi_rvalid => NLW_gig_ethernet_pcs_pma_16_1_core_s_axi_rvalid_UNCONNECTED, s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000", s_axi_wready => NLW_gig_ethernet_pcs_pma_16_1_core_s_axi_wready_UNCONNECTED, s_axi_wvalid => '0', signal_detect => signal_detect, speed_is_100 => '0', speed_is_10_100 => '0', speed_selection(1 downto 0) => NLW_gig_ethernet_pcs_pma_16_1_core_speed_selection_UNCONNECTED(1 downto 0), status_vector(15 downto 7) => NLW_gig_ethernet_pcs_pma_16_1_core_status_vector_UNCONNECTED(15 downto 7), status_vector(6 downto 0) => \^status_vector\(6 downto 0), systemtimer_ns_field(31 downto 0) => B"00000000000000000000000000000000", systemtimer_s_field(47 downto 0) => B"000000000000000000000000000000000000000000000000", tx_code_group(9 downto 0) => NLW_gig_ethernet_pcs_pma_16_1_core_tx_code_group_UNCONNECTED(9 downto 0), txbuferr => txbuferr, txchardispmode => txchardispmode, txchardispval => txchardispval, txcharisk => txcharisk, txdata(7 downto 0) => txdata(7 downto 0), userclk => '0', userclk2 => userclk2 ); sync_block_rx_reset_done: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block port map ( data_in => transceiver_inst_n_6, data_out => rx_reset_done_i, userclk2 => userclk2 ); sync_block_tx_reset_done: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_0 port map ( data_in => transceiver_inst_n_5, resetdone => \^resetdone\, resetdone_0 => rx_reset_done_i, userclk2 => userclk2 ); transceiver_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_transceiver port map ( D(0) => txchardispmode, Q(1 downto 0) => rxclkcorcnt(1 downto 0), SR(0) => mgt_tx_reset, cplllock => cplllock, data_in => transceiver_inst_n_5, enablealign => enablealign, gt0_qplloutclk_in => gt0_qplloutclk_in, gt0_qplloutrefclk_in => gt0_qplloutrefclk_in, gtrefclk => gtrefclk, gtrefclk_bufg => gtrefclk_bufg, independent_clock_bufg => independent_clock_bufg, mmcm_locked => mmcm_locked, mmcm_reset => mmcm_reset, pma_reset => pma_reset, powerdown => powerdown, reset_sync5(0) => mgt_rx_reset, rx_fsm_reset_done_int_reg => transceiver_inst_n_6, rxbuferr => rxbuferr, rxchariscomma => rxchariscomma, rxcharisk => rxcharisk, \rxdata_reg[7]_0\(7 downto 0) => rxdata(7 downto 0), rxdisperr => rxdisperr, rxn => rxn, rxnotintable => rxnotintable, rxoutclk => rxoutclk, rxp => rxp, status_vector(0) => \^status_vector\(1), txbuferr => txbuferr, txchardispval_reg_reg_0(0) => txchardispval, txcharisk_reg_reg_0(0) => txcharisk, \txdata_reg_reg[7]_0\(7 downto 0) => txdata(7 downto 0), txn => txn, txoutclk => txoutclk, txp => txp, userclk => userclk, userclk2 => userclk2 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is port ( gtrefclk : in STD_LOGIC; gtrefclk_bufg : in STD_LOGIC; txp : out STD_LOGIC; txn : out STD_LOGIC; rxp : in STD_LOGIC; rxn : in STD_LOGIC; resetdone : out STD_LOGIC; cplllock : out STD_LOGIC; mmcm_reset : out STD_LOGIC; txoutclk : out STD_LOGIC; rxoutclk : out STD_LOGIC; userclk : in STD_LOGIC; userclk2 : in STD_LOGIC; rxuserclk : in STD_LOGIC; rxuserclk2 : in STD_LOGIC; pma_reset : in STD_LOGIC; mmcm_locked : in STD_LOGIC; independent_clock_bufg : in STD_LOGIC; gmii_txd : in STD_LOGIC_VECTOR ( 7 downto 0 ); gmii_tx_en : in STD_LOGIC; gmii_tx_er : in STD_LOGIC; gmii_rxd : out STD_LOGIC_VECTOR ( 7 downto 0 ); gmii_rx_dv : out STD_LOGIC; gmii_rx_er : out STD_LOGIC; gmii_isolate : out STD_LOGIC; configuration_vector : in STD_LOGIC_VECTOR ( 4 downto 0 ); status_vector : out STD_LOGIC_VECTOR ( 15 downto 0 ); reset : in STD_LOGIC; signal_detect : in STD_LOGIC; gt0_qplloutclk_in : in STD_LOGIC; gt0_qplloutrefclk_in : in STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; attribute EXAMPLE_SIMULATION : integer; attribute EXAMPLE_SIMULATION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is 0; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; attribute x_core_info : string; attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "gig_ethernet_pcs_pma_v16_1_5,Vivado 2018.3"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is attribute EXAMPLE_SIMULATION of U0 : label is 0; attribute downgradeipidentifiedwarnings of U0 : label is "yes"; begin U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_block port map ( configuration_vector(4 downto 0) => configuration_vector(4 downto 0), cplllock => cplllock, gmii_isolate => gmii_isolate, gmii_rx_dv => gmii_rx_dv, gmii_rx_er => gmii_rx_er, gmii_rxd(7 downto 0) => gmii_rxd(7 downto 0), gmii_tx_en => gmii_tx_en, gmii_tx_er => gmii_tx_er, gmii_txd(7 downto 0) => gmii_txd(7 downto 0), gt0_qplloutclk_in => gt0_qplloutclk_in, gt0_qplloutrefclk_in => gt0_qplloutrefclk_in, gtrefclk => gtrefclk, gtrefclk_bufg => gtrefclk_bufg, independent_clock_bufg => independent_clock_bufg, mmcm_locked => mmcm_locked, mmcm_reset => mmcm_reset, pma_reset => pma_reset, reset => reset, resetdone => resetdone, rxn => rxn, rxoutclk => rxoutclk, rxp => rxp, rxuserclk => rxuserclk, rxuserclk2 => rxuserclk2, signal_detect => signal_detect, status_vector(15 downto 0) => status_vector(15 downto 0), txn => txn, txoutclk => txoutclk, txp => txp, userclk => userclk, userclk2 => userclk2 ); end STRUCTURE;