// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 // Date : Sat Apr 18 12:30:30 2020 // Host : baby running 64-bit major release (build 9200) // Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix // decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ gig_ethernet_pcs_pma_16_1_sim_netlist.v // Design : gig_ethernet_pcs_pma_16_1 // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. // Device : xc7k420tffg1156-2 // -------------------------------------------------------------------------------- `timescale 1 ps / 1 ps (* EXAMPLE_SIMULATION = "0" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "gig_ethernet_pcs_pma_v16_1_5,Vivado 2018.3" *) (* NotValidForBitStream *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix (gtrefclk, gtrefclk_bufg, txp, txn, rxp, rxn, resetdone, cplllock, mmcm_reset, txoutclk, rxoutclk, userclk, userclk2, rxuserclk, rxuserclk2, pma_reset, mmcm_locked, independent_clock_bufg, gmii_txd, gmii_tx_en, gmii_tx_er, gmii_rxd, gmii_rx_dv, gmii_rx_er, gmii_isolate, configuration_vector, status_vector, reset, signal_detect, gt0_qplloutclk_in, gt0_qplloutrefclk_in); input gtrefclk; input gtrefclk_bufg; output txp; output txn; input rxp; input rxn; output resetdone; output cplllock; output mmcm_reset; output txoutclk; output rxoutclk; input userclk; input userclk2; input rxuserclk; input rxuserclk2; input pma_reset; input mmcm_locked; input independent_clock_bufg; input [7:0]gmii_txd; input gmii_tx_en; input gmii_tx_er; output [7:0]gmii_rxd; output gmii_rx_dv; output gmii_rx_er; output gmii_isolate; input [4:0]configuration_vector; output [15:0]status_vector; input reset; input signal_detect; input gt0_qplloutclk_in; input gt0_qplloutrefclk_in; wire [4:0]configuration_vector; wire cplllock; wire gmii_isolate; wire gmii_rx_dv; wire gmii_rx_er; wire [7:0]gmii_rxd; wire gmii_tx_en; wire gmii_tx_er; wire [7:0]gmii_txd; wire gt0_qplloutclk_in; wire gt0_qplloutrefclk_in; wire gtrefclk; wire gtrefclk_bufg; wire independent_clock_bufg; wire mmcm_locked; wire mmcm_reset; wire pma_reset; wire reset; wire resetdone; wire rxn; wire rxoutclk; wire rxp; wire rxuserclk; wire rxuserclk2; wire signal_detect; wire [15:0]status_vector; wire txn; wire txoutclk; wire txp; wire userclk; wire userclk2; (* EXAMPLE_SIMULATION = "0" *) (* downgradeipidentifiedwarnings = "yes" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_block U0 (.configuration_vector(configuration_vector), .cplllock(cplllock), .gmii_isolate(gmii_isolate), .gmii_rx_dv(gmii_rx_dv), .gmii_rx_er(gmii_rx_er), .gmii_rxd(gmii_rxd), .gmii_tx_en(gmii_tx_en), .gmii_tx_er(gmii_tx_er), .gmii_txd(gmii_txd), .gt0_qplloutclk_in(gt0_qplloutclk_in), .gt0_qplloutrefclk_in(gt0_qplloutrefclk_in), .gtrefclk(gtrefclk), .gtrefclk_bufg(gtrefclk_bufg), .independent_clock_bufg(independent_clock_bufg), .mmcm_locked(mmcm_locked), .mmcm_reset(mmcm_reset), .pma_reset(pma_reset), .reset(reset), .resetdone(resetdone), .rxn(rxn), .rxoutclk(rxoutclk), .rxp(rxp), .rxuserclk(rxuserclk), .rxuserclk2(rxuserclk2), .signal_detect(signal_detect), .status_vector(status_vector), .txn(txn), .txoutclk(txoutclk), .txp(txp), .userclk(userclk), .userclk2(userclk2)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_GTWIZARD (cplllock, txn, txp, rxoutclk, txoutclk, D, TXBUFSTATUS, RXBUFSTATUS, independent_clock_bufg_0, independent_clock_bufg_1, independent_clock_bufg_2, independent_clock_bufg_3, independent_clock_bufg_4, mmcm_reset, data_in, rx_fsm_reset_done_int_reg, gtrefclk_bufg, independent_clock_bufg, gtrefclk, rxn, rxp, gt0_qplloutclk_in, gt0_qplloutrefclk_in, reset_out, reset, userclk, TXPD, RXPD, Q, data_sync_reg1, data_sync_reg1_0, data_sync_reg1_1, pma_reset, \gt0_rx_cdrlock_counter_reg[0] , data_sync_reg1_2, mmcm_locked, data_out); output cplllock; output txn; output txp; output rxoutclk; output txoutclk; output [1:0]D; output [0:0]TXBUFSTATUS; output [0:0]RXBUFSTATUS; output [15:0]independent_clock_bufg_0; output [1:0]independent_clock_bufg_1; output [1:0]independent_clock_bufg_2; output [1:0]independent_clock_bufg_3; output [1:0]independent_clock_bufg_4; output mmcm_reset; output data_in; output rx_fsm_reset_done_int_reg; input gtrefclk_bufg; input independent_clock_bufg; input gtrefclk; input rxn; input rxp; input gt0_qplloutclk_in; input gt0_qplloutrefclk_in; input reset_out; input reset; input userclk; input [0:0]TXPD; input [0:0]RXPD; input [15:0]Q; input [1:0]data_sync_reg1; input [1:0]data_sync_reg1_0; input [1:0]data_sync_reg1_1; input pma_reset; input \gt0_rx_cdrlock_counter_reg[0] ; input data_sync_reg1_2; input mmcm_locked; input data_out; wire [1:0]D; wire [15:0]Q; wire [0:0]RXBUFSTATUS; wire [0:0]RXPD; wire [0:0]TXBUFSTATUS; wire [0:0]TXPD; wire cplllock; wire data_in; wire data_out; wire [1:0]data_sync_reg1; wire [1:0]data_sync_reg1_0; wire [1:0]data_sync_reg1_1; wire data_sync_reg1_2; wire gt0_qplloutclk_in; wire gt0_qplloutrefclk_in; wire \gt0_rx_cdrlock_counter_reg[0] ; wire gtrefclk; wire gtrefclk_bufg; wire independent_clock_bufg; wire [15:0]independent_clock_bufg_0; wire [1:0]independent_clock_bufg_1; wire [1:0]independent_clock_bufg_2; wire [1:0]independent_clock_bufg_3; wire [1:0]independent_clock_bufg_4; wire mmcm_locked; wire mmcm_reset; wire pma_reset; wire reset; wire reset_out; wire rx_fsm_reset_done_int_reg; wire rxn; wire rxoutclk; wire rxp; wire txn; wire txoutclk; wire txp; wire userclk; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_GTWIZARD_init U0 (.D(D), .Q(Q), .RXBUFSTATUS(RXBUFSTATUS), .RXPD(RXPD), .TXBUFSTATUS(TXBUFSTATUS), .TXPD(TXPD), .cplllock(cplllock), .data_in(data_in), .data_out(data_out), .data_sync_reg1(data_sync_reg1), .data_sync_reg1_0(data_sync_reg1_0), .data_sync_reg1_1(data_sync_reg1_1), .data_sync_reg1_2(data_sync_reg1_2), .gt0_qplloutclk_in(gt0_qplloutclk_in), .gt0_qplloutrefclk_in(gt0_qplloutrefclk_in), .\gt0_rx_cdrlock_counter_reg[0]_0 (\gt0_rx_cdrlock_counter_reg[0] ), .gtrefclk(gtrefclk), .gtrefclk_bufg(gtrefclk_bufg), .independent_clock_bufg(independent_clock_bufg), .independent_clock_bufg_0(independent_clock_bufg_0), .independent_clock_bufg_1(independent_clock_bufg_1), .independent_clock_bufg_2(independent_clock_bufg_2), .independent_clock_bufg_3(independent_clock_bufg_3), .independent_clock_bufg_4(independent_clock_bufg_4), .mmcm_locked(mmcm_locked), .mmcm_reset(mmcm_reset), .pma_reset(pma_reset), .reset(reset), .reset_out(reset_out), .rx_fsm_reset_done_int_reg(rx_fsm_reset_done_int_reg), .rxn(rxn), .rxoutclk(rxoutclk), .rxp(rxp), .txn(txn), .txoutclk(txoutclk), .txp(txp), .userclk(userclk)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_GTWIZARD_GT (cplllock, gt0_cpllrefclklost_i, txn, txp, rxoutclk, independent_clock_bufg_0, txoutclk, independent_clock_bufg_1, D, TXBUFSTATUS, RXBUFSTATUS, independent_clock_bufg_2, independent_clock_bufg_3, independent_clock_bufg_4, independent_clock_bufg_5, independent_clock_bufg_6, independent_clock_bufg, cpll_pd0_i, cpllreset_in, gtrefclk_bufg, gtrefclk, gt0_gtrxreset_in1_out, gt0_gttxreset_in0_out, rxn, rxp, gt0_qplloutclk_in, gt0_qplloutrefclk_in, reset_out, reset, gt0_rxuserrdy_t, userclk, TXPD, gt0_txuserrdy_t, RXPD, Q, data_sync_reg1, data_sync_reg1_0, data_sync_reg1_1); output cplllock; output gt0_cpllrefclklost_i; output txn; output txp; output rxoutclk; output independent_clock_bufg_0; output txoutclk; output independent_clock_bufg_1; output [1:0]D; output [0:0]TXBUFSTATUS; output [0:0]RXBUFSTATUS; output [15:0]independent_clock_bufg_2; output [1:0]independent_clock_bufg_3; output [1:0]independent_clock_bufg_4; output [1:0]independent_clock_bufg_5; output [1:0]independent_clock_bufg_6; input independent_clock_bufg; input cpll_pd0_i; input cpllreset_in; input gtrefclk_bufg; input gtrefclk; input gt0_gtrxreset_in1_out; input gt0_gttxreset_in0_out; input rxn; input rxp; input gt0_qplloutclk_in; input gt0_qplloutrefclk_in; input reset_out; input reset; input gt0_rxuserrdy_t; input userclk; input [0:0]TXPD; input gt0_txuserrdy_t; input [0:0]RXPD; input [15:0]Q; input [1:0]data_sync_reg1; input [1:0]data_sync_reg1_0; input [1:0]data_sync_reg1_1; wire [1:0]D; wire [15:0]Q; wire [0:0]RXBUFSTATUS; wire [0:0]RXPD; wire [0:0]TXBUFSTATUS; wire [0:0]TXPD; wire cpll_pd0_i; wire cplllock; wire cpllreset_in; wire [1:0]data_sync_reg1; wire [1:0]data_sync_reg1_0; wire [1:0]data_sync_reg1_1; wire gt0_cpllrefclklost_i; wire gt0_gtrxreset_in1_out; wire gt0_gttxreset_in0_out; wire gt0_qplloutclk_in; wire gt0_qplloutrefclk_in; wire gt0_rxuserrdy_t; wire gt0_txuserrdy_t; wire gtrefclk; wire gtrefclk_bufg; wire gtxe2_i_n_0; wire gtxe2_i_n_10; wire gtxe2_i_n_16; wire gtxe2_i_n_170; wire gtxe2_i_n_171; wire gtxe2_i_n_172; wire gtxe2_i_n_173; wire gtxe2_i_n_174; wire gtxe2_i_n_175; wire gtxe2_i_n_176; wire gtxe2_i_n_177; wire gtxe2_i_n_178; wire gtxe2_i_n_179; wire gtxe2_i_n_180; wire gtxe2_i_n_181; wire gtxe2_i_n_182; wire gtxe2_i_n_183; wire gtxe2_i_n_184; wire gtxe2_i_n_27; wire gtxe2_i_n_3; wire gtxe2_i_n_38; wire gtxe2_i_n_39; wire gtxe2_i_n_4; wire gtxe2_i_n_46; wire gtxe2_i_n_47; wire gtxe2_i_n_48; wire gtxe2_i_n_49; wire gtxe2_i_n_50; wire gtxe2_i_n_51; wire gtxe2_i_n_52; wire gtxe2_i_n_53; wire gtxe2_i_n_54; wire gtxe2_i_n_55; wire gtxe2_i_n_56; wire gtxe2_i_n_57; wire gtxe2_i_n_58; wire gtxe2_i_n_59; wire gtxe2_i_n_60; wire gtxe2_i_n_61; wire gtxe2_i_n_81; wire gtxe2_i_n_83; wire gtxe2_i_n_84; wire gtxe2_i_n_9; wire independent_clock_bufg; wire independent_clock_bufg_0; wire independent_clock_bufg_1; wire [15:0]independent_clock_bufg_2; wire [1:0]independent_clock_bufg_3; wire [1:0]independent_clock_bufg_4; wire [1:0]independent_clock_bufg_5; wire [1:0]independent_clock_bufg_6; wire reset; wire reset_out; wire rxn; wire rxoutclk; wire rxp; wire txn; wire txoutclk; wire txp; wire userclk; wire NLW_gtxe2_i_GTREFCLKMONITOR_UNCONNECTED; wire NLW_gtxe2_i_PHYSTATUS_UNCONNECTED; wire NLW_gtxe2_i_RXCDRLOCK_UNCONNECTED; wire NLW_gtxe2_i_RXCHANBONDSEQ_UNCONNECTED; wire NLW_gtxe2_i_RXCHANISALIGNED_UNCONNECTED; wire NLW_gtxe2_i_RXCHANREALIGN_UNCONNECTED; wire NLW_gtxe2_i_RXCOMINITDET_UNCONNECTED; wire NLW_gtxe2_i_RXCOMSASDET_UNCONNECTED; wire NLW_gtxe2_i_RXCOMWAKEDET_UNCONNECTED; wire NLW_gtxe2_i_RXDATAVALID_UNCONNECTED; wire NLW_gtxe2_i_RXDLYSRESETDONE_UNCONNECTED; wire NLW_gtxe2_i_RXELECIDLE_UNCONNECTED; wire NLW_gtxe2_i_RXHEADERVALID_UNCONNECTED; wire NLW_gtxe2_i_RXOUTCLKFABRIC_UNCONNECTED; wire NLW_gtxe2_i_RXOUTCLKPCS_UNCONNECTED; wire NLW_gtxe2_i_RXPHALIGNDONE_UNCONNECTED; wire NLW_gtxe2_i_RXQPISENN_UNCONNECTED; wire NLW_gtxe2_i_RXQPISENP_UNCONNECTED; wire NLW_gtxe2_i_RXRATEDONE_UNCONNECTED; wire NLW_gtxe2_i_RXSTARTOFSEQ_UNCONNECTED; wire NLW_gtxe2_i_RXVALID_UNCONNECTED; wire NLW_gtxe2_i_TXCOMFINISH_UNCONNECTED; wire NLW_gtxe2_i_TXDLYSRESETDONE_UNCONNECTED; wire NLW_gtxe2_i_TXGEARBOXREADY_UNCONNECTED; wire NLW_gtxe2_i_TXPHALIGNDONE_UNCONNECTED; wire NLW_gtxe2_i_TXPHINITDONE_UNCONNECTED; wire NLW_gtxe2_i_TXQPISENN_UNCONNECTED; wire NLW_gtxe2_i_TXQPISENP_UNCONNECTED; wire NLW_gtxe2_i_TXRATEDONE_UNCONNECTED; wire [15:0]NLW_gtxe2_i_PCSRSVDOUT_UNCONNECTED; wire [7:2]NLW_gtxe2_i_RXCHARISCOMMA_UNCONNECTED; wire [7:2]NLW_gtxe2_i_RXCHARISK_UNCONNECTED; wire [4:0]NLW_gtxe2_i_RXCHBONDO_UNCONNECTED; wire [63:16]NLW_gtxe2_i_RXDATA_UNCONNECTED; wire [7:2]NLW_gtxe2_i_RXDISPERR_UNCONNECTED; wire [2:0]NLW_gtxe2_i_RXHEADER_UNCONNECTED; wire [7:2]NLW_gtxe2_i_RXNOTINTABLE_UNCONNECTED; wire [4:0]NLW_gtxe2_i_RXPHMONITOR_UNCONNECTED; wire [4:0]NLW_gtxe2_i_RXPHSLIPMONITOR_UNCONNECTED; wire [2:0]NLW_gtxe2_i_RXSTATUS_UNCONNECTED; wire [9:0]NLW_gtxe2_i_TSTOUT_UNCONNECTED; (* box_type = "PRIMITIVE" *) GTXE2_CHANNEL #( .ALIGN_COMMA_DOUBLE("FALSE"), .ALIGN_COMMA_ENABLE(10'b0001111111), .ALIGN_COMMA_WORD(2), .ALIGN_MCOMMA_DET("TRUE"), .ALIGN_MCOMMA_VALUE(10'b1010000011), .ALIGN_PCOMMA_DET("TRUE"), .ALIGN_PCOMMA_VALUE(10'b0101111100), .CBCC_DATA_SOURCE_SEL("DECODED"), .CHAN_BOND_KEEP_ALIGN("FALSE"), .CHAN_BOND_MAX_SKEW(1), .CHAN_BOND_SEQ_1_1(10'b0000000000), .CHAN_BOND_SEQ_1_2(10'b0000000000), .CHAN_BOND_SEQ_1_3(10'b0000000000), .CHAN_BOND_SEQ_1_4(10'b0000000000), .CHAN_BOND_SEQ_1_ENABLE(4'b1111), .CHAN_BOND_SEQ_2_1(10'b0000000000), .CHAN_BOND_SEQ_2_2(10'b0000000000), .CHAN_BOND_SEQ_2_3(10'b0000000000), .CHAN_BOND_SEQ_2_4(10'b0000000000), .CHAN_BOND_SEQ_2_ENABLE(4'b1111), .CHAN_BOND_SEQ_2_USE("FALSE"), .CHAN_BOND_SEQ_LEN(1), .CLK_CORRECT_USE("TRUE"), .CLK_COR_KEEP_IDLE("FALSE"), .CLK_COR_MAX_LAT(36), .CLK_COR_MIN_LAT(33), .CLK_COR_PRECEDENCE("TRUE"), .CLK_COR_REPEAT_WAIT(0), .CLK_COR_SEQ_1_1(10'b0110111100), .CLK_COR_SEQ_1_2(10'b0001010000), .CLK_COR_SEQ_1_3(10'b0000000000), .CLK_COR_SEQ_1_4(10'b0000000000), .CLK_COR_SEQ_1_ENABLE(4'b1111), .CLK_COR_SEQ_2_1(10'b0110111100), .CLK_COR_SEQ_2_2(10'b0010110101), .CLK_COR_SEQ_2_3(10'b0000000000), .CLK_COR_SEQ_2_4(10'b0000000000), .CLK_COR_SEQ_2_ENABLE(4'b1111), .CLK_COR_SEQ_2_USE("TRUE"), .CLK_COR_SEQ_LEN(2), .CPLL_CFG(24'hBC07DC), .CPLL_FBDIV(4), .CPLL_FBDIV_45(5), .CPLL_INIT_CFG(24'h00001E), .CPLL_LOCK_CFG(16'h01E8), .CPLL_REFCLK_DIV(1), .DEC_MCOMMA_DETECT("TRUE"), .DEC_PCOMMA_DETECT("TRUE"), .DEC_VALID_COMMA_ONLY("FALSE"), .DMONITOR_CFG(24'h000A00), .ES_CONTROL(6'b000000), .ES_ERRDET_EN("FALSE"), .ES_EYE_SCAN_EN("TRUE"), .ES_HORZ_OFFSET(12'h000), .ES_PMA_CFG(10'b0000000000), .ES_PRESCALE(5'b00000), .ES_QUALIFIER(80'h00000000000000000000), .ES_QUAL_MASK(80'h00000000000000000000), .ES_SDATA_MASK(80'h00000000000000000000), .ES_VERT_OFFSET(9'b000000000), .FTS_DESKEW_SEQ_ENABLE(4'b1111), .FTS_LANE_DESKEW_CFG(4'b1111), .FTS_LANE_DESKEW_EN("FALSE"), .GEARBOX_MODE(3'b000), .IS_CPLLLOCKDETCLK_INVERTED(1'b0), .IS_DRPCLK_INVERTED(1'b0), .IS_GTGREFCLK_INVERTED(1'b0), .IS_RXUSRCLK2_INVERTED(1'b0), .IS_RXUSRCLK_INVERTED(1'b0), .IS_TXPHDLYTSTCLK_INVERTED(1'b0), .IS_TXUSRCLK2_INVERTED(1'b0), .IS_TXUSRCLK_INVERTED(1'b0), .OUTREFCLK_SEL_INV(2'b11), .PCS_PCIE_EN("FALSE"), .PCS_RSVD_ATTR(48'h000000000000), .PD_TRANS_TIME_FROM_P2(12'h03C), .PD_TRANS_TIME_NONE_P2(8'h19), .PD_TRANS_TIME_TO_P2(8'h64), .PMA_RSV(32'h00018480), .PMA_RSV2(16'h2050), .PMA_RSV3(2'b00), .PMA_RSV4(32'h00000000), .RXBUFRESET_TIME(5'b00001), .RXBUF_ADDR_MODE("FULL"), .RXBUF_EIDLE_HI_CNT(4'b1000), .RXBUF_EIDLE_LO_CNT(4'b0000), .RXBUF_EN("TRUE"), .RXBUF_RESET_ON_CB_CHANGE("TRUE"), .RXBUF_RESET_ON_COMMAALIGN("FALSE"), .RXBUF_RESET_ON_EIDLE("FALSE"), .RXBUF_RESET_ON_RATE_CHANGE("TRUE"), .RXBUF_THRESH_OVFLW(61), .RXBUF_THRESH_OVRD("FALSE"), .RXBUF_THRESH_UNDFLW(8), .RXCDRFREQRESET_TIME(5'b00001), .RXCDRPHRESET_TIME(5'b00001), .RXCDR_CFG(72'h03000023FF10100020), .RXCDR_FR_RESET_ON_EIDLE(1'b0), .RXCDR_HOLD_DURING_EIDLE(1'b0), .RXCDR_LOCK_CFG(6'b010101), .RXCDR_PH_RESET_ON_EIDLE(1'b0), .RXDFELPMRESET_TIME(7'b0001111), .RXDLY_CFG(16'h001F), .RXDLY_LCFG(9'h030), .RXDLY_TAP_CFG(16'h0000), .RXGEARBOX_EN("FALSE"), .RXISCANRESET_TIME(5'b00001), .RXLPM_HF_CFG(14'b00000011110000), .RXLPM_LF_CFG(14'b00000011110000), .RXOOB_CFG(7'b0000110), .RXOUT_DIV(4), .RXPCSRESET_TIME(5'b00001), .RXPHDLY_CFG(24'h084020), .RXPH_CFG(24'h000000), .RXPH_MONITOR_SEL(5'b00000), .RXPMARESET_TIME(5'b00011), .RXPRBS_ERR_LOOPBACK(1'b0), .RXSLIDE_AUTO_WAIT(7), .RXSLIDE_MODE("OFF"), .RX_BIAS_CFG(12'b000000000100), .RX_BUFFER_CFG(6'b000000), .RX_CLK25_DIV(5), .RX_CLKMUX_PD(1'b1), .RX_CM_SEL(2'b11), .RX_CM_TRIM(3'b010), .RX_DATA_WIDTH(20), .RX_DDI_SEL(6'b000000), .RX_DEBUG_CFG(12'b000000000000), .RX_DEFER_RESET_BUF_EN("TRUE"), .RX_DFE_GAIN_CFG(23'h020FEA), .RX_DFE_H2_CFG(12'b000000000000), .RX_DFE_H3_CFG(12'b000001000000), .RX_DFE_H4_CFG(11'b00011110000), .RX_DFE_H5_CFG(11'b00011100000), .RX_DFE_KL_CFG(13'b0000011111110), .RX_DFE_KL_CFG2(32'h301148AC), .RX_DFE_LPM_CFG(16'h0904), .RX_DFE_LPM_HOLD_DURING_EIDLE(1'b0), .RX_DFE_UT_CFG(17'b10001111000000000), .RX_DFE_VP_CFG(17'b00011111100000011), .RX_DFE_XYD_CFG(13'b0000000000000), .RX_DISPERR_SEQ_MATCH("TRUE"), .RX_INT_DATAWIDTH(0), .RX_OS_CFG(13'b0000010000000), .RX_SIG_VALID_DLY(10), .RX_XCLK_SEL("RXREC"), .SAS_MAX_COM(64), .SAS_MIN_COM(36), .SATA_BURST_SEQ_LEN(4'b0101), .SATA_BURST_VAL(3'b100), .SATA_CPLL_CFG("VCO_3000MHZ"), .SATA_EIDLE_VAL(3'b100), .SATA_MAX_BURST(8), .SATA_MAX_INIT(21), .SATA_MAX_WAKE(7), .SATA_MIN_BURST(4), .SATA_MIN_INIT(12), .SATA_MIN_WAKE(4), .SHOW_REALIGN_COMMA("TRUE"), .SIM_CPLLREFCLK_SEL(3'b001), .SIM_RECEIVER_DETECT_PASS("TRUE"), .SIM_RESET_SPEEDUP("TRUE"), .SIM_TX_EIDLE_DRIVE_LEVEL("X"), .SIM_VERSION("4.0"), .TERM_RCAL_CFG(5'b10000), .TERM_RCAL_OVRD(1'b0), .TRANS_TIME_RATE(8'h0E), .TST_RSV(32'h00000000), .TXBUF_EN("TRUE"), .TXBUF_RESET_ON_RATE_CHANGE("TRUE"), .TXDLY_CFG(16'h001F), .TXDLY_LCFG(9'h030), .TXDLY_TAP_CFG(16'h0000), .TXGEARBOX_EN("FALSE"), .TXOUT_DIV(4), .TXPCSRESET_TIME(5'b00001), .TXPHDLY_CFG(24'h084020), .TXPH_CFG(16'h0780), .TXPH_MONITOR_SEL(5'b00000), .TXPMARESET_TIME(5'b00001), .TX_CLK25_DIV(5), .TX_CLKMUX_PD(1'b1), .TX_DATA_WIDTH(20), .TX_DEEMPH0(5'b00000), .TX_DEEMPH1(5'b00000), .TX_DRIVE_MODE("DIRECT"), .TX_EIDLE_ASSERT_DELAY(3'b110), .TX_EIDLE_DEASSERT_DELAY(3'b100), .TX_INT_DATAWIDTH(0), .TX_LOOPBACK_DRIVE_HIZ("FALSE"), .TX_MAINCURSOR_SEL(1'b0), .TX_MARGIN_FULL_0(7'b1001110), .TX_MARGIN_FULL_1(7'b1001001), .TX_MARGIN_FULL_2(7'b1000101), .TX_MARGIN_FULL_3(7'b1000010), .TX_MARGIN_FULL_4(7'b1000000), .TX_MARGIN_LOW_0(7'b1000110), .TX_MARGIN_LOW_1(7'b1000100), .TX_MARGIN_LOW_2(7'b1000010), .TX_MARGIN_LOW_3(7'b1000000), .TX_MARGIN_LOW_4(7'b1000000), .TX_PREDRIVER_MODE(1'b0), .TX_QPI_STATUS_EN(1'b0), .TX_RXDETECT_CFG(14'h1832), .TX_RXDETECT_REF(3'b100), .TX_XCLK_SEL("TXOUT"), .UCODEER_CLR(1'b0)) gtxe2_i (.CFGRESET(1'b0), .CLKRSVD({1'b0,1'b0,1'b0,1'b0}), .CPLLFBCLKLOST(gtxe2_i_n_0), .CPLLLOCK(cplllock), .CPLLLOCKDETCLK(independent_clock_bufg), .CPLLLOCKEN(1'b1), .CPLLPD(cpll_pd0_i), .CPLLREFCLKLOST(gt0_cpllrefclklost_i), .CPLLREFCLKSEL({1'b0,1'b0,1'b1}), .CPLLRESET(cpllreset_in), .DMONITOROUT({gtxe2_i_n_177,gtxe2_i_n_178,gtxe2_i_n_179,gtxe2_i_n_180,gtxe2_i_n_181,gtxe2_i_n_182,gtxe2_i_n_183,gtxe2_i_n_184}), .DRPADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DRPCLK(gtrefclk_bufg), .DRPDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .DRPDO({gtxe2_i_n_46,gtxe2_i_n_47,gtxe2_i_n_48,gtxe2_i_n_49,gtxe2_i_n_50,gtxe2_i_n_51,gtxe2_i_n_52,gtxe2_i_n_53,gtxe2_i_n_54,gtxe2_i_n_55,gtxe2_i_n_56,gtxe2_i_n_57,gtxe2_i_n_58,gtxe2_i_n_59,gtxe2_i_n_60,gtxe2_i_n_61}), .DRPEN(1'b0), .DRPRDY(gtxe2_i_n_3), .DRPWE(1'b0), .EYESCANDATAERROR(gtxe2_i_n_4), .EYESCANMODE(1'b0), .EYESCANRESET(1'b0), .EYESCANTRIGGER(1'b0), .GTGREFCLK(1'b0), .GTNORTHREFCLK0(1'b0), .GTNORTHREFCLK1(1'b0), .GTREFCLK0(gtrefclk), .GTREFCLK1(1'b0), .GTREFCLKMONITOR(NLW_gtxe2_i_GTREFCLKMONITOR_UNCONNECTED), .GTRESETSEL(1'b0), .GTRSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .GTRXRESET(gt0_gtrxreset_in1_out), .GTSOUTHREFCLK0(1'b0), .GTSOUTHREFCLK1(1'b0), .GTTXRESET(gt0_gttxreset_in0_out), .GTXRXN(rxn), .GTXRXP(rxp), .GTXTXN(txn), .GTXTXP(txp), .LOOPBACK({1'b0,1'b0,1'b0}), .PCSRSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .PCSRSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}), .PCSRSVDOUT(NLW_gtxe2_i_PCSRSVDOUT_UNCONNECTED[15:0]), .PHYSTATUS(NLW_gtxe2_i_PHYSTATUS_UNCONNECTED), .PMARSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .PMARSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}), .QPLLCLK(gt0_qplloutclk_in), .QPLLREFCLK(gt0_qplloutrefclk_in), .RESETOVRD(1'b0), .RX8B10BEN(1'b1), .RXBUFRESET(1'b0), .RXBUFSTATUS({RXBUFSTATUS,gtxe2_i_n_83,gtxe2_i_n_84}), .RXBYTEISALIGNED(gtxe2_i_n_9), .RXBYTEREALIGN(gtxe2_i_n_10), .RXCDRFREQRESET(1'b0), .RXCDRHOLD(1'b0), .RXCDRLOCK(NLW_gtxe2_i_RXCDRLOCK_UNCONNECTED), .RXCDROVRDEN(1'b0), .RXCDRRESET(1'b0), .RXCDRRESETRSV(1'b0), .RXCHANBONDSEQ(NLW_gtxe2_i_RXCHANBONDSEQ_UNCONNECTED), .RXCHANISALIGNED(NLW_gtxe2_i_RXCHANISALIGNED_UNCONNECTED), .RXCHANREALIGN(NLW_gtxe2_i_RXCHANREALIGN_UNCONNECTED), .RXCHARISCOMMA({NLW_gtxe2_i_RXCHARISCOMMA_UNCONNECTED[7:2],independent_clock_bufg_3}), .RXCHARISK({NLW_gtxe2_i_RXCHARISK_UNCONNECTED[7:2],independent_clock_bufg_4}), .RXCHBONDEN(1'b0), .RXCHBONDI({1'b0,1'b0,1'b0,1'b0,1'b0}), .RXCHBONDLEVEL({1'b0,1'b0,1'b0}), .RXCHBONDMASTER(1'b0), .RXCHBONDO(NLW_gtxe2_i_RXCHBONDO_UNCONNECTED[4:0]), .RXCHBONDSLAVE(1'b0), .RXCLKCORCNT(D), .RXCOMINITDET(NLW_gtxe2_i_RXCOMINITDET_UNCONNECTED), .RXCOMMADET(gtxe2_i_n_16), .RXCOMMADETEN(1'b1), .RXCOMSASDET(NLW_gtxe2_i_RXCOMSASDET_UNCONNECTED), .RXCOMWAKEDET(NLW_gtxe2_i_RXCOMWAKEDET_UNCONNECTED), .RXDATA({NLW_gtxe2_i_RXDATA_UNCONNECTED[63:16],independent_clock_bufg_2}), .RXDATAVALID(NLW_gtxe2_i_RXDATAVALID_UNCONNECTED), .RXDDIEN(1'b0), .RXDFEAGCHOLD(1'b0), .RXDFEAGCOVRDEN(1'b0), .RXDFECM1EN(1'b0), .RXDFELFHOLD(1'b0), .RXDFELFOVRDEN(1'b0), .RXDFELPMRESET(1'b0), .RXDFETAP2HOLD(1'b0), .RXDFETAP2OVRDEN(1'b0), .RXDFETAP3HOLD(1'b0), .RXDFETAP3OVRDEN(1'b0), .RXDFETAP4HOLD(1'b0), .RXDFETAP4OVRDEN(1'b0), .RXDFETAP5HOLD(1'b0), .RXDFETAP5OVRDEN(1'b0), .RXDFEUTHOLD(1'b0), .RXDFEUTOVRDEN(1'b0), .RXDFEVPHOLD(1'b0), .RXDFEVPOVRDEN(1'b0), .RXDFEVSEN(1'b0), .RXDFEXYDEN(1'b1), .RXDFEXYDHOLD(1'b0), .RXDFEXYDOVRDEN(1'b0), .RXDISPERR({NLW_gtxe2_i_RXDISPERR_UNCONNECTED[7:2],independent_clock_bufg_5}), .RXDLYBYPASS(1'b1), .RXDLYEN(1'b0), .RXDLYOVRDEN(1'b0), .RXDLYSRESET(1'b0), .RXDLYSRESETDONE(NLW_gtxe2_i_RXDLYSRESETDONE_UNCONNECTED), .RXELECIDLE(NLW_gtxe2_i_RXELECIDLE_UNCONNECTED), .RXELECIDLEMODE({1'b1,1'b1}), .RXGEARBOXSLIP(1'b0), .RXHEADER(NLW_gtxe2_i_RXHEADER_UNCONNECTED[2:0]), .RXHEADERVALID(NLW_gtxe2_i_RXHEADERVALID_UNCONNECTED), .RXLPMEN(1'b1), .RXLPMHFHOLD(1'b0), .RXLPMHFOVRDEN(1'b0), .RXLPMLFHOLD(1'b0), .RXLPMLFKLOVRDEN(1'b0), .RXMCOMMAALIGNEN(reset_out), .RXMONITOROUT({gtxe2_i_n_170,gtxe2_i_n_171,gtxe2_i_n_172,gtxe2_i_n_173,gtxe2_i_n_174,gtxe2_i_n_175,gtxe2_i_n_176}), .RXMONITORSEL({1'b0,1'b0}), .RXNOTINTABLE({NLW_gtxe2_i_RXNOTINTABLE_UNCONNECTED[7:2],independent_clock_bufg_6}), .RXOOBRESET(1'b0), .RXOSHOLD(1'b0), .RXOSOVRDEN(1'b0), .RXOUTCLK(rxoutclk), .RXOUTCLKFABRIC(NLW_gtxe2_i_RXOUTCLKFABRIC_UNCONNECTED), .RXOUTCLKPCS(NLW_gtxe2_i_RXOUTCLKPCS_UNCONNECTED), .RXOUTCLKSEL({1'b0,1'b1,1'b0}), .RXPCOMMAALIGNEN(reset_out), .RXPCSRESET(reset), .RXPD({RXPD,RXPD}), .RXPHALIGN(1'b0), .RXPHALIGNDONE(NLW_gtxe2_i_RXPHALIGNDONE_UNCONNECTED), .RXPHALIGNEN(1'b0), .RXPHDLYPD(1'b0), .RXPHDLYRESET(1'b0), .RXPHMONITOR(NLW_gtxe2_i_RXPHMONITOR_UNCONNECTED[4:0]), .RXPHOVRDEN(1'b0), .RXPHSLIPMONITOR(NLW_gtxe2_i_RXPHSLIPMONITOR_UNCONNECTED[4:0]), .RXPMARESET(1'b0), .RXPOLARITY(1'b0), .RXPRBSCNTRESET(1'b0), .RXPRBSERR(gtxe2_i_n_27), .RXPRBSSEL({1'b0,1'b0,1'b0}), .RXQPIEN(1'b0), .RXQPISENN(NLW_gtxe2_i_RXQPISENN_UNCONNECTED), .RXQPISENP(NLW_gtxe2_i_RXQPISENP_UNCONNECTED), .RXRATE({1'b0,1'b0,1'b0}), .RXRATEDONE(NLW_gtxe2_i_RXRATEDONE_UNCONNECTED), .RXRESETDONE(independent_clock_bufg_0), .RXSLIDE(1'b0), .RXSTARTOFSEQ(NLW_gtxe2_i_RXSTARTOFSEQ_UNCONNECTED), .RXSTATUS(NLW_gtxe2_i_RXSTATUS_UNCONNECTED[2:0]), .RXSYSCLKSEL({1'b0,1'b0}), .RXUSERRDY(gt0_rxuserrdy_t), .RXUSRCLK(userclk), .RXUSRCLK2(userclk), .RXVALID(NLW_gtxe2_i_RXVALID_UNCONNECTED), .SETERRSTATUS(1'b0), .TSTIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), .TSTOUT(NLW_gtxe2_i_TSTOUT_UNCONNECTED[9:0]), .TX8B10BBYPASS({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .TX8B10BEN(1'b1), .TXBUFDIFFCTRL({1'b1,1'b0,1'b0}), .TXBUFSTATUS({TXBUFSTATUS,gtxe2_i_n_81}), .TXCHARDISPMODE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,data_sync_reg1}), .TXCHARDISPVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,data_sync_reg1_0}), .TXCHARISK({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,data_sync_reg1_1}), .TXCOMFINISH(NLW_gtxe2_i_TXCOMFINISH_UNCONNECTED), .TXCOMINIT(1'b0), .TXCOMSAS(1'b0), .TXCOMWAKE(1'b0), .TXDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,Q}), .TXDEEMPH(1'b0), .TXDETECTRX(1'b0), .TXDIFFCTRL({1'b1,1'b0,1'b0,1'b0}), .TXDIFFPD(1'b0), .TXDLYBYPASS(1'b1), .TXDLYEN(1'b0), .TXDLYHOLD(1'b0), .TXDLYOVRDEN(1'b0), .TXDLYSRESET(1'b0), .TXDLYSRESETDONE(NLW_gtxe2_i_TXDLYSRESETDONE_UNCONNECTED), .TXDLYUPDOWN(1'b0), .TXELECIDLE(TXPD), .TXGEARBOXREADY(NLW_gtxe2_i_TXGEARBOXREADY_UNCONNECTED), .TXHEADER({1'b0,1'b0,1'b0}), .TXINHIBIT(1'b0), .TXMAINCURSOR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .TXMARGIN({1'b0,1'b0,1'b0}), .TXOUTCLK(txoutclk), .TXOUTCLKFABRIC(gtxe2_i_n_38), .TXOUTCLKPCS(gtxe2_i_n_39), .TXOUTCLKSEL({1'b1,1'b0,1'b0}), .TXPCSRESET(1'b0), .TXPD({TXPD,TXPD}), .TXPDELECIDLEMODE(1'b0), .TXPHALIGN(1'b0), .TXPHALIGNDONE(NLW_gtxe2_i_TXPHALIGNDONE_UNCONNECTED), .TXPHALIGNEN(1'b0), .TXPHDLYPD(1'b0), .TXPHDLYRESET(1'b0), .TXPHDLYTSTCLK(1'b0), .TXPHINIT(1'b0), .TXPHINITDONE(NLW_gtxe2_i_TXPHINITDONE_UNCONNECTED), .TXPHOVRDEN(1'b0), .TXPISOPD(1'b0), .TXPMARESET(1'b0), .TXPOLARITY(1'b0), .TXPOSTCURSOR({1'b0,1'b0,1'b0,1'b0,1'b0}), .TXPOSTCURSORINV(1'b0), .TXPRBSFORCEERR(1'b0), .TXPRBSSEL({1'b0,1'b0,1'b0}), .TXPRECURSOR({1'b0,1'b0,1'b0,1'b0,1'b0}), .TXPRECURSORINV(1'b0), .TXQPIBIASEN(1'b0), .TXQPISENN(NLW_gtxe2_i_TXQPISENN_UNCONNECTED), .TXQPISENP(NLW_gtxe2_i_TXQPISENP_UNCONNECTED), .TXQPISTRONGPDOWN(1'b0), .TXQPIWEAKPUP(1'b0), .TXRATE({1'b0,1'b0,1'b0}), .TXRATEDONE(NLW_gtxe2_i_TXRATEDONE_UNCONNECTED), .TXRESETDONE(independent_clock_bufg_1), .TXSEQUENCE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .TXSTARTSEQ(1'b0), .TXSWING(1'b0), .TXSYSCLKSEL({1'b0,1'b0}), .TXUSERRDY(gt0_txuserrdy_t), .TXUSRCLK(userclk), .TXUSRCLK2(userclk)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_GTWIZARD_init (cplllock, txn, txp, rxoutclk, txoutclk, D, TXBUFSTATUS, RXBUFSTATUS, independent_clock_bufg_0, independent_clock_bufg_1, independent_clock_bufg_2, independent_clock_bufg_3, independent_clock_bufg_4, mmcm_reset, data_in, rx_fsm_reset_done_int_reg, gtrefclk_bufg, independent_clock_bufg, gtrefclk, rxn, rxp, gt0_qplloutclk_in, gt0_qplloutrefclk_in, reset_out, reset, userclk, TXPD, RXPD, Q, data_sync_reg1, data_sync_reg1_0, data_sync_reg1_1, pma_reset, \gt0_rx_cdrlock_counter_reg[0]_0 , data_sync_reg1_2, mmcm_locked, data_out); output cplllock; output txn; output txp; output rxoutclk; output txoutclk; output [1:0]D; output [0:0]TXBUFSTATUS; output [0:0]RXBUFSTATUS; output [15:0]independent_clock_bufg_0; output [1:0]independent_clock_bufg_1; output [1:0]independent_clock_bufg_2; output [1:0]independent_clock_bufg_3; output [1:0]independent_clock_bufg_4; output mmcm_reset; output data_in; output rx_fsm_reset_done_int_reg; input gtrefclk_bufg; input independent_clock_bufg; input gtrefclk; input rxn; input rxp; input gt0_qplloutclk_in; input gt0_qplloutrefclk_in; input reset_out; input reset; input userclk; input [0:0]TXPD; input [0:0]RXPD; input [15:0]Q; input [1:0]data_sync_reg1; input [1:0]data_sync_reg1_0; input [1:0]data_sync_reg1_1; input pma_reset; input \gt0_rx_cdrlock_counter_reg[0]_0 ; input data_sync_reg1_2; input mmcm_locked; input data_out; wire [1:0]D; wire [15:0]Q; wire [0:0]RXBUFSTATUS; wire [0:0]RXPD; wire [0:0]TXBUFSTATUS; wire [0:0]TXPD; wire cplllock; wire data_in; wire data_out; wire [1:0]data_sync_reg1; wire [1:0]data_sync_reg1_0; wire [1:0]data_sync_reg1_1; wire data_sync_reg1_2; wire gt0_cpllrefclklost_i; wire gt0_cpllreset_t; wire gt0_gtrxreset_in1_out; wire gt0_gttxreset_in0_out; wire gt0_qplloutclk_in; wire gt0_qplloutrefclk_in; wire \gt0_rx_cdrlock_counter[0]_i_1_n_0 ; wire \gt0_rx_cdrlock_counter[0]_i_3_n_0 ; wire \gt0_rx_cdrlock_counter[0]_i_4_n_0 ; wire \gt0_rx_cdrlock_counter[0]_i_5_n_0 ; wire [13:0]gt0_rx_cdrlock_counter_reg; wire \gt0_rx_cdrlock_counter_reg[0]_0 ; wire \gt0_rx_cdrlock_counter_reg[0]_i_2_n_0 ; wire \gt0_rx_cdrlock_counter_reg[0]_i_2_n_1 ; wire \gt0_rx_cdrlock_counter_reg[0]_i_2_n_2 ; wire \gt0_rx_cdrlock_counter_reg[0]_i_2_n_3 ; wire \gt0_rx_cdrlock_counter_reg[0]_i_2_n_4 ; wire \gt0_rx_cdrlock_counter_reg[0]_i_2_n_5 ; wire \gt0_rx_cdrlock_counter_reg[0]_i_2_n_6 ; wire \gt0_rx_cdrlock_counter_reg[0]_i_2_n_7 ; wire \gt0_rx_cdrlock_counter_reg[12]_i_1_n_3 ; wire \gt0_rx_cdrlock_counter_reg[12]_i_1_n_6 ; wire \gt0_rx_cdrlock_counter_reg[12]_i_1_n_7 ; wire \gt0_rx_cdrlock_counter_reg[4]_i_1_n_0 ; wire \gt0_rx_cdrlock_counter_reg[4]_i_1_n_1 ; wire \gt0_rx_cdrlock_counter_reg[4]_i_1_n_2 ; wire \gt0_rx_cdrlock_counter_reg[4]_i_1_n_3 ; wire \gt0_rx_cdrlock_counter_reg[4]_i_1_n_4 ; wire \gt0_rx_cdrlock_counter_reg[4]_i_1_n_5 ; wire \gt0_rx_cdrlock_counter_reg[4]_i_1_n_6 ; wire \gt0_rx_cdrlock_counter_reg[4]_i_1_n_7 ; wire \gt0_rx_cdrlock_counter_reg[8]_i_1_n_0 ; wire \gt0_rx_cdrlock_counter_reg[8]_i_1_n_1 ; wire \gt0_rx_cdrlock_counter_reg[8]_i_1_n_2 ; wire \gt0_rx_cdrlock_counter_reg[8]_i_1_n_3 ; wire \gt0_rx_cdrlock_counter_reg[8]_i_1_n_4 ; wire \gt0_rx_cdrlock_counter_reg[8]_i_1_n_5 ; wire \gt0_rx_cdrlock_counter_reg[8]_i_1_n_6 ; wire \gt0_rx_cdrlock_counter_reg[8]_i_1_n_7 ; wire gt0_rx_cdrlocked_i_2_n_0; wire gt0_rx_cdrlocked_i_3_n_0; wire gt0_rx_cdrlocked_reg_n_0; wire gt0_rxresetfsm_i_n_3; wire gt0_rxuserrdy_t; wire gt0_txuserrdy_t; wire gtrefclk; wire gtrefclk_bufg; wire gtwizard_i_n_5; wire gtwizard_i_n_7; wire independent_clock_bufg; wire [15:0]independent_clock_bufg_0; wire [1:0]independent_clock_bufg_1; wire [1:0]independent_clock_bufg_2; wire [1:0]independent_clock_bufg_3; wire [1:0]independent_clock_bufg_4; wire mmcm_locked; wire mmcm_reset; wire pma_reset; wire reset; wire reset_out; wire rx_fsm_reset_done_int_reg; wire rxn; wire rxoutclk; wire rxp; wire txn; wire txoutclk; wire txp; wire userclk; wire [3:1]\NLW_gt0_rx_cdrlock_counter_reg[12]_i_1_CO_UNCONNECTED ; wire [3:2]\NLW_gt0_rx_cdrlock_counter_reg[12]_i_1_O_UNCONNECTED ; LUT4 #( .INIT(16'hFFFE)) \gt0_rx_cdrlock_counter[0]_i_1 (.I0(\gt0_rx_cdrlock_counter[0]_i_3_n_0 ), .I1(\gt0_rx_cdrlock_counter[0]_i_4_n_0 ), .I2(gt0_rx_cdrlock_counter_reg[1]), .I3(gt0_rx_cdrlock_counter_reg[0]), .O(\gt0_rx_cdrlock_counter[0]_i_1_n_0 )); LUT6 #( .INIT(64'hFFDFFFFFFFFFFFFF)) \gt0_rx_cdrlock_counter[0]_i_3 (.I0(gt0_rx_cdrlock_counter_reg[13]), .I1(gt0_rx_cdrlock_counter_reg[12]), .I2(gt0_rx_cdrlock_counter_reg[10]), .I3(gt0_rx_cdrlock_counter_reg[11]), .I4(gt0_rx_cdrlock_counter_reg[9]), .I5(gt0_rx_cdrlock_counter_reg[8]), .O(\gt0_rx_cdrlock_counter[0]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFEF)) \gt0_rx_cdrlock_counter[0]_i_4 (.I0(gt0_rx_cdrlock_counter_reg[6]), .I1(gt0_rx_cdrlock_counter_reg[7]), .I2(gt0_rx_cdrlock_counter_reg[4]), .I3(gt0_rx_cdrlock_counter_reg[5]), .I4(gt0_rx_cdrlock_counter_reg[3]), .I5(gt0_rx_cdrlock_counter_reg[2]), .O(\gt0_rx_cdrlock_counter[0]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \gt0_rx_cdrlock_counter[0]_i_5 (.I0(gt0_rx_cdrlock_counter_reg[0]), .O(\gt0_rx_cdrlock_counter[0]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \gt0_rx_cdrlock_counter_reg[0] (.C(independent_clock_bufg), .CE(\gt0_rx_cdrlock_counter[0]_i_1_n_0 ), .D(\gt0_rx_cdrlock_counter_reg[0]_i_2_n_7 ), .Q(gt0_rx_cdrlock_counter_reg[0]), .R(gt0_gtrxreset_in1_out)); CARRY4 \gt0_rx_cdrlock_counter_reg[0]_i_2 (.CI(1'b0), .CO({\gt0_rx_cdrlock_counter_reg[0]_i_2_n_0 ,\gt0_rx_cdrlock_counter_reg[0]_i_2_n_1 ,\gt0_rx_cdrlock_counter_reg[0]_i_2_n_2 ,\gt0_rx_cdrlock_counter_reg[0]_i_2_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b1}), .O({\gt0_rx_cdrlock_counter_reg[0]_i_2_n_4 ,\gt0_rx_cdrlock_counter_reg[0]_i_2_n_5 ,\gt0_rx_cdrlock_counter_reg[0]_i_2_n_6 ,\gt0_rx_cdrlock_counter_reg[0]_i_2_n_7 }), .S({gt0_rx_cdrlock_counter_reg[3:1],\gt0_rx_cdrlock_counter[0]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \gt0_rx_cdrlock_counter_reg[10] (.C(independent_clock_bufg), .CE(\gt0_rx_cdrlock_counter[0]_i_1_n_0 ), .D(\gt0_rx_cdrlock_counter_reg[8]_i_1_n_5 ), .Q(gt0_rx_cdrlock_counter_reg[10]), .R(gt0_gtrxreset_in1_out)); FDRE #( .INIT(1'b0)) \gt0_rx_cdrlock_counter_reg[11] (.C(independent_clock_bufg), .CE(\gt0_rx_cdrlock_counter[0]_i_1_n_0 ), .D(\gt0_rx_cdrlock_counter_reg[8]_i_1_n_4 ), .Q(gt0_rx_cdrlock_counter_reg[11]), .R(gt0_gtrxreset_in1_out)); FDRE #( .INIT(1'b0)) \gt0_rx_cdrlock_counter_reg[12] (.C(independent_clock_bufg), .CE(\gt0_rx_cdrlock_counter[0]_i_1_n_0 ), .D(\gt0_rx_cdrlock_counter_reg[12]_i_1_n_7 ), .Q(gt0_rx_cdrlock_counter_reg[12]), .R(gt0_gtrxreset_in1_out)); CARRY4 \gt0_rx_cdrlock_counter_reg[12]_i_1 (.CI(\gt0_rx_cdrlock_counter_reg[8]_i_1_n_0 ), .CO({\NLW_gt0_rx_cdrlock_counter_reg[12]_i_1_CO_UNCONNECTED [3:1],\gt0_rx_cdrlock_counter_reg[12]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\NLW_gt0_rx_cdrlock_counter_reg[12]_i_1_O_UNCONNECTED [3:2],\gt0_rx_cdrlock_counter_reg[12]_i_1_n_6 ,\gt0_rx_cdrlock_counter_reg[12]_i_1_n_7 }), .S({1'b0,1'b0,gt0_rx_cdrlock_counter_reg[13:12]})); FDRE #( .INIT(1'b0)) \gt0_rx_cdrlock_counter_reg[13] (.C(independent_clock_bufg), .CE(\gt0_rx_cdrlock_counter[0]_i_1_n_0 ), .D(\gt0_rx_cdrlock_counter_reg[12]_i_1_n_6 ), .Q(gt0_rx_cdrlock_counter_reg[13]), .R(gt0_gtrxreset_in1_out)); FDRE #( .INIT(1'b0)) \gt0_rx_cdrlock_counter_reg[1] (.C(independent_clock_bufg), .CE(\gt0_rx_cdrlock_counter[0]_i_1_n_0 ), .D(\gt0_rx_cdrlock_counter_reg[0]_i_2_n_6 ), .Q(gt0_rx_cdrlock_counter_reg[1]), .R(gt0_gtrxreset_in1_out)); FDRE #( .INIT(1'b0)) \gt0_rx_cdrlock_counter_reg[2] (.C(independent_clock_bufg), .CE(\gt0_rx_cdrlock_counter[0]_i_1_n_0 ), .D(\gt0_rx_cdrlock_counter_reg[0]_i_2_n_5 ), .Q(gt0_rx_cdrlock_counter_reg[2]), .R(gt0_gtrxreset_in1_out)); FDRE #( .INIT(1'b0)) \gt0_rx_cdrlock_counter_reg[3] (.C(independent_clock_bufg), .CE(\gt0_rx_cdrlock_counter[0]_i_1_n_0 ), .D(\gt0_rx_cdrlock_counter_reg[0]_i_2_n_4 ), .Q(gt0_rx_cdrlock_counter_reg[3]), .R(gt0_gtrxreset_in1_out)); FDRE #( .INIT(1'b0)) \gt0_rx_cdrlock_counter_reg[4] (.C(independent_clock_bufg), .CE(\gt0_rx_cdrlock_counter[0]_i_1_n_0 ), .D(\gt0_rx_cdrlock_counter_reg[4]_i_1_n_7 ), .Q(gt0_rx_cdrlock_counter_reg[4]), .R(gt0_gtrxreset_in1_out)); CARRY4 \gt0_rx_cdrlock_counter_reg[4]_i_1 (.CI(\gt0_rx_cdrlock_counter_reg[0]_i_2_n_0 ), .CO({\gt0_rx_cdrlock_counter_reg[4]_i_1_n_0 ,\gt0_rx_cdrlock_counter_reg[4]_i_1_n_1 ,\gt0_rx_cdrlock_counter_reg[4]_i_1_n_2 ,\gt0_rx_cdrlock_counter_reg[4]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\gt0_rx_cdrlock_counter_reg[4]_i_1_n_4 ,\gt0_rx_cdrlock_counter_reg[4]_i_1_n_5 ,\gt0_rx_cdrlock_counter_reg[4]_i_1_n_6 ,\gt0_rx_cdrlock_counter_reg[4]_i_1_n_7 }), .S(gt0_rx_cdrlock_counter_reg[7:4])); FDRE #( .INIT(1'b0)) \gt0_rx_cdrlock_counter_reg[5] (.C(independent_clock_bufg), .CE(\gt0_rx_cdrlock_counter[0]_i_1_n_0 ), .D(\gt0_rx_cdrlock_counter_reg[4]_i_1_n_6 ), .Q(gt0_rx_cdrlock_counter_reg[5]), .R(gt0_gtrxreset_in1_out)); FDRE #( .INIT(1'b0)) \gt0_rx_cdrlock_counter_reg[6] (.C(independent_clock_bufg), .CE(\gt0_rx_cdrlock_counter[0]_i_1_n_0 ), .D(\gt0_rx_cdrlock_counter_reg[4]_i_1_n_5 ), .Q(gt0_rx_cdrlock_counter_reg[6]), .R(gt0_gtrxreset_in1_out)); FDRE #( .INIT(1'b0)) \gt0_rx_cdrlock_counter_reg[7] (.C(independent_clock_bufg), .CE(\gt0_rx_cdrlock_counter[0]_i_1_n_0 ), .D(\gt0_rx_cdrlock_counter_reg[4]_i_1_n_4 ), .Q(gt0_rx_cdrlock_counter_reg[7]), .R(gt0_gtrxreset_in1_out)); FDRE #( .INIT(1'b0)) \gt0_rx_cdrlock_counter_reg[8] (.C(independent_clock_bufg), .CE(\gt0_rx_cdrlock_counter[0]_i_1_n_0 ), .D(\gt0_rx_cdrlock_counter_reg[8]_i_1_n_7 ), .Q(gt0_rx_cdrlock_counter_reg[8]), .R(gt0_gtrxreset_in1_out)); CARRY4 \gt0_rx_cdrlock_counter_reg[8]_i_1 (.CI(\gt0_rx_cdrlock_counter_reg[4]_i_1_n_0 ), .CO({\gt0_rx_cdrlock_counter_reg[8]_i_1_n_0 ,\gt0_rx_cdrlock_counter_reg[8]_i_1_n_1 ,\gt0_rx_cdrlock_counter_reg[8]_i_1_n_2 ,\gt0_rx_cdrlock_counter_reg[8]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\gt0_rx_cdrlock_counter_reg[8]_i_1_n_4 ,\gt0_rx_cdrlock_counter_reg[8]_i_1_n_5 ,\gt0_rx_cdrlock_counter_reg[8]_i_1_n_6 ,\gt0_rx_cdrlock_counter_reg[8]_i_1_n_7 }), .S(gt0_rx_cdrlock_counter_reg[11:8])); FDRE #( .INIT(1'b0)) \gt0_rx_cdrlock_counter_reg[9] (.C(independent_clock_bufg), .CE(\gt0_rx_cdrlock_counter[0]_i_1_n_0 ), .D(\gt0_rx_cdrlock_counter_reg[8]_i_1_n_6 ), .Q(gt0_rx_cdrlock_counter_reg[9]), .R(gt0_gtrxreset_in1_out)); LUT6 #( .INIT(64'h0000200000000000)) gt0_rx_cdrlocked_i_2 (.I0(gt0_rx_cdrlock_counter_reg[10]), .I1(gt0_rx_cdrlock_counter_reg[11]), .I2(gt0_rx_cdrlock_counter_reg[8]), .I3(gt0_rx_cdrlock_counter_reg[9]), .I4(gt0_rx_cdrlock_counter_reg[12]), .I5(gt0_rx_cdrlock_counter_reg[13]), .O(gt0_rx_cdrlocked_i_2_n_0)); LUT6 #( .INIT(64'h0000000000000002)) gt0_rx_cdrlocked_i_3 (.I0(gt0_rx_cdrlock_counter_reg[4]), .I1(gt0_rx_cdrlock_counter_reg[5]), .I2(gt0_rx_cdrlock_counter_reg[2]), .I3(gt0_rx_cdrlock_counter_reg[3]), .I4(gt0_rx_cdrlock_counter_reg[7]), .I5(gt0_rx_cdrlock_counter_reg[6]), .O(gt0_rx_cdrlocked_i_3_n_0)); FDRE gt0_rx_cdrlocked_reg (.C(independent_clock_bufg), .CE(1'b1), .D(gt0_rxresetfsm_i_n_3), .Q(gt0_rx_cdrlocked_reg_n_0), .R(1'b0)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_RX_STARTUP_FSM gt0_rxresetfsm_i (.cplllock(cplllock), .data_in(rx_fsm_reset_done_int_reg), .data_out(data_out), .data_sync_reg1(gtwizard_i_n_5), .gt0_gtrxreset_in1_out(gt0_gtrxreset_in1_out), .gt0_rx_cdrlock_counter_reg(gt0_rx_cdrlock_counter_reg[1:0]), .gt0_rx_cdrlock_counter_reg_0_sp_1(\gt0_rx_cdrlock_counter_reg[0]_0 ), .gt0_rx_cdrlocked_reg(gt0_rxresetfsm_i_n_3), .gt0_rx_cdrlocked_reg_0(gt0_rx_cdrlocked_reg_n_0), .gt0_rx_cdrlocked_reg_1(gt0_rx_cdrlocked_i_2_n_0), .gt0_rx_cdrlocked_reg_2(gt0_rx_cdrlocked_i_3_n_0), .gt0_rxuserrdy_t(gt0_rxuserrdy_t), .independent_clock_bufg(independent_clock_bufg), .mmcm_locked(mmcm_locked), .pma_reset(pma_reset), .userclk(userclk)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_TX_STARTUP_FSM gt0_txresetfsm_i (.cplllock(cplllock), .data_in(data_in), .data_sync_reg1(data_sync_reg1_2), .data_sync_reg1_0(gtwizard_i_n_7), .gt0_cpllrefclklost_i(gt0_cpllrefclklost_i), .gt0_cpllreset_t(gt0_cpllreset_t), .gt0_gttxreset_in0_out(gt0_gttxreset_in0_out), .gt0_txuserrdy_t(gt0_txuserrdy_t), .independent_clock_bufg(independent_clock_bufg), .mmcm_locked(mmcm_locked), .mmcm_reset(mmcm_reset), .pma_reset(pma_reset), .userclk(userclk)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_GTWIZARD_multi_gt gtwizard_i (.D(D), .Q(Q), .RXBUFSTATUS(RXBUFSTATUS), .RXPD(RXPD), .TXBUFSTATUS(TXBUFSTATUS), .TXPD(TXPD), .cplllock(cplllock), .data_sync_reg1(data_sync_reg1), .data_sync_reg1_0(data_sync_reg1_0), .data_sync_reg1_1(data_sync_reg1_1), .gt0_cpllrefclklost_i(gt0_cpllrefclklost_i), .gt0_cpllreset_t(gt0_cpllreset_t), .gt0_gtrxreset_in1_out(gt0_gtrxreset_in1_out), .gt0_gttxreset_in0_out(gt0_gttxreset_in0_out), .gt0_qplloutclk_in(gt0_qplloutclk_in), .gt0_qplloutrefclk_in(gt0_qplloutrefclk_in), .gt0_rxuserrdy_t(gt0_rxuserrdy_t), .gt0_txuserrdy_t(gt0_txuserrdy_t), .gtrefclk(gtrefclk), .gtrefclk_bufg(gtrefclk_bufg), .independent_clock_bufg(independent_clock_bufg), .independent_clock_bufg_0(gtwizard_i_n_5), .independent_clock_bufg_1(gtwizard_i_n_7), .independent_clock_bufg_2(independent_clock_bufg_0), .independent_clock_bufg_3(independent_clock_bufg_1), .independent_clock_bufg_4(independent_clock_bufg_2), .independent_clock_bufg_5(independent_clock_bufg_3), .independent_clock_bufg_6(independent_clock_bufg_4), .reset(reset), .reset_out(reset_out), .rxn(rxn), .rxoutclk(rxoutclk), .rxp(rxp), .txn(txn), .txoutclk(txoutclk), .txp(txp), .userclk(userclk)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_GTWIZARD_multi_gt (cplllock, gt0_cpllrefclklost_i, txn, txp, rxoutclk, independent_clock_bufg_0, txoutclk, independent_clock_bufg_1, D, TXBUFSTATUS, RXBUFSTATUS, independent_clock_bufg_2, independent_clock_bufg_3, independent_clock_bufg_4, independent_clock_bufg_5, independent_clock_bufg_6, gtrefclk_bufg, independent_clock_bufg, gtrefclk, gt0_gtrxreset_in1_out, gt0_gttxreset_in0_out, rxn, rxp, gt0_qplloutclk_in, gt0_qplloutrefclk_in, reset_out, reset, gt0_rxuserrdy_t, userclk, TXPD, gt0_txuserrdy_t, RXPD, Q, data_sync_reg1, data_sync_reg1_0, data_sync_reg1_1, gt0_cpllreset_t); output cplllock; output gt0_cpllrefclklost_i; output txn; output txp; output rxoutclk; output independent_clock_bufg_0; output txoutclk; output independent_clock_bufg_1; output [1:0]D; output [0:0]TXBUFSTATUS; output [0:0]RXBUFSTATUS; output [15:0]independent_clock_bufg_2; output [1:0]independent_clock_bufg_3; output [1:0]independent_clock_bufg_4; output [1:0]independent_clock_bufg_5; output [1:0]independent_clock_bufg_6; input gtrefclk_bufg; input independent_clock_bufg; input gtrefclk; input gt0_gtrxreset_in1_out; input gt0_gttxreset_in0_out; input rxn; input rxp; input gt0_qplloutclk_in; input gt0_qplloutrefclk_in; input reset_out; input reset; input gt0_rxuserrdy_t; input userclk; input [0:0]TXPD; input gt0_txuserrdy_t; input [0:0]RXPD; input [15:0]Q; input [1:0]data_sync_reg1; input [1:0]data_sync_reg1_0; input [1:0]data_sync_reg1_1; input gt0_cpllreset_t; wire [1:0]D; wire [15:0]Q; wire [0:0]RXBUFSTATUS; wire [0:0]RXPD; wire [0:0]TXBUFSTATUS; wire [0:0]TXPD; wire cpll_pd0_i; wire cplllock; wire cpllreset_in; wire [1:0]data_sync_reg1; wire [1:0]data_sync_reg1_0; wire [1:0]data_sync_reg1_1; wire gt0_cpllrefclklost_i; wire gt0_cpllreset_t; wire gt0_gtrxreset_in1_out; wire gt0_gttxreset_in0_out; wire gt0_qplloutclk_in; wire gt0_qplloutrefclk_in; wire gt0_rxuserrdy_t; wire gt0_txuserrdy_t; wire gtrefclk; wire gtrefclk_bufg; wire independent_clock_bufg; wire independent_clock_bufg_0; wire independent_clock_bufg_1; wire [15:0]independent_clock_bufg_2; wire [1:0]independent_clock_bufg_3; wire [1:0]independent_clock_bufg_4; wire [1:0]independent_clock_bufg_5; wire [1:0]independent_clock_bufg_6; wire reset; wire reset_out; wire rxn; wire rxoutclk; wire rxp; wire txn; wire txoutclk; wire txp; wire userclk; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_cpll_railing cpll_railing0_i (.cpll_pd0_i(cpll_pd0_i), .cpllreset_in(cpllreset_in), .gt0_cpllreset_t(gt0_cpllreset_t), .gtrefclk_bufg(gtrefclk_bufg)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_GTWIZARD_GT gt0_GTWIZARD_i (.D(D), .Q(Q), .RXBUFSTATUS(RXBUFSTATUS), .RXPD(RXPD), .TXBUFSTATUS(TXBUFSTATUS), .TXPD(TXPD), .cpll_pd0_i(cpll_pd0_i), .cplllock(cplllock), .cpllreset_in(cpllreset_in), .data_sync_reg1(data_sync_reg1), .data_sync_reg1_0(data_sync_reg1_0), .data_sync_reg1_1(data_sync_reg1_1), .gt0_cpllrefclklost_i(gt0_cpllrefclklost_i), .gt0_gtrxreset_in1_out(gt0_gtrxreset_in1_out), .gt0_gttxreset_in0_out(gt0_gttxreset_in0_out), .gt0_qplloutclk_in(gt0_qplloutclk_in), .gt0_qplloutrefclk_in(gt0_qplloutrefclk_in), .gt0_rxuserrdy_t(gt0_rxuserrdy_t), .gt0_txuserrdy_t(gt0_txuserrdy_t), .gtrefclk(gtrefclk), .gtrefclk_bufg(gtrefclk_bufg), .independent_clock_bufg(independent_clock_bufg), .independent_clock_bufg_0(independent_clock_bufg_0), .independent_clock_bufg_1(independent_clock_bufg_1), .independent_clock_bufg_2(independent_clock_bufg_2), .independent_clock_bufg_3(independent_clock_bufg_3), .independent_clock_bufg_4(independent_clock_bufg_4), .independent_clock_bufg_5(independent_clock_bufg_5), .independent_clock_bufg_6(independent_clock_bufg_6), .reset(reset), .reset_out(reset_out), .rxn(rxn), .rxoutclk(rxoutclk), .rxp(rxp), .txn(txn), .txoutclk(txoutclk), .txp(txp), .userclk(userclk)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_RX_STARTUP_FSM (data_in, gt0_rxuserrdy_t, gt0_gtrxreset_in1_out, gt0_rx_cdrlocked_reg, independent_clock_bufg, userclk, pma_reset, gt0_rx_cdrlocked_reg_0, gt0_rx_cdrlock_counter_reg_0_sp_1, gt0_rx_cdrlocked_reg_1, gt0_rx_cdrlock_counter_reg, gt0_rx_cdrlocked_reg_2, data_sync_reg1, mmcm_locked, data_out, cplllock); output data_in; output gt0_rxuserrdy_t; output gt0_gtrxreset_in1_out; output gt0_rx_cdrlocked_reg; input independent_clock_bufg; input userclk; input pma_reset; input gt0_rx_cdrlocked_reg_0; input gt0_rx_cdrlock_counter_reg_0_sp_1; input gt0_rx_cdrlocked_reg_1; input [1:0]gt0_rx_cdrlock_counter_reg; input gt0_rx_cdrlocked_reg_2; input data_sync_reg1; input mmcm_locked; input data_out; input cplllock; wire \FSM_sequential_rx_state[0]_i_2_n_0 ; wire \FSM_sequential_rx_state[1]_i_3_n_0 ; wire \FSM_sequential_rx_state[2]_i_1_n_0 ; wire \FSM_sequential_rx_state[2]_i_2_n_0 ; wire \FSM_sequential_rx_state[3]_i_10_n_0 ; wire \FSM_sequential_rx_state[3]_i_3_n_0 ; wire \FSM_sequential_rx_state[3]_i_7_n_0 ; wire \FSM_sequential_rx_state[3]_i_9_n_0 ; wire GTRXRESET; wire RXUSERRDY_i_1_n_0; wire check_tlock_max_i_1_n_0; wire check_tlock_max_reg_n_0; wire cplllock; wire data_in; wire data_out; wire data_out_0; wire data_sync_reg1; wire gt0_gtrxreset_in1_out; wire [1:0]gt0_rx_cdrlock_counter_reg; wire gt0_rx_cdrlock_counter_reg_0_sn_1; wire gt0_rx_cdrlocked_reg; wire gt0_rx_cdrlocked_reg_0; wire gt0_rx_cdrlocked_reg_1; wire gt0_rx_cdrlocked_reg_2; wire gt0_rxuserrdy_t; wire gtrxreset_i_i_1_n_0; wire independent_clock_bufg; wire \init_wait_count[0]_i_1__0_n_0 ; wire \init_wait_count[6]_i_1__0_n_0 ; wire \init_wait_count[6]_i_3__0_n_0 ; wire [6:0]init_wait_count_reg__0; wire init_wait_done_i_1__0_n_0; wire init_wait_done_reg_n_0; wire \mmcm_lock_count[2]_i_1__0_n_0 ; wire \mmcm_lock_count[3]_i_1__0_n_0 ; wire \mmcm_lock_count[4]_i_1__0_n_0 ; wire \mmcm_lock_count[5]_i_1__0_n_0 ; wire \mmcm_lock_count[6]_i_1__0_n_0 ; wire \mmcm_lock_count[7]_i_2__0_n_0 ; wire \mmcm_lock_count[7]_i_3__0_n_0 ; wire \mmcm_lock_count[7]_i_4__0_n_0 ; wire [7:0]mmcm_lock_count_reg__0; wire mmcm_lock_reclocked; wire mmcm_locked; wire [6:1]p_0_in__2; wire [1:0]p_0_in__3; wire pma_reset; wire reset_time_out_i_3_n_0; wire reset_time_out_i_4_n_0; wire reset_time_out_reg_n_0; wire run_phase_alignment_int_i_1__0_n_0; wire run_phase_alignment_int_reg_n_0; wire run_phase_alignment_int_s3_reg_n_0; wire rx_fsm_reset_done_int_i_5_n_0; wire rx_fsm_reset_done_int_i_6_n_0; wire rx_fsm_reset_done_int_s2; wire rx_fsm_reset_done_int_s3; wire [3:0]rx_state; wire rxresetdone_s2; wire rxresetdone_s3; wire sync_cplllock_n_0; wire sync_data_valid_n_0; wire sync_data_valid_n_1; wire sync_data_valid_n_2; wire sync_data_valid_n_3; wire sync_data_valid_n_4; wire sync_data_valid_n_5; wire sync_mmcm_lock_reclocked_n_0; wire sync_mmcm_lock_reclocked_n_1; wire time_out_100us_i_1_n_0; wire time_out_100us_i_2_n_0; wire time_out_100us_i_3_n_0; wire time_out_100us_reg_n_0; wire time_out_1us_i_1_n_0; wire time_out_1us_i_2_n_0; wire time_out_1us_i_3_n_0; wire time_out_1us_reg_n_0; wire time_out_2ms_i_1_n_0; wire time_out_2ms_i_2__0_n_0; wire time_out_2ms_reg_n_0; wire time_out_counter; wire \time_out_counter[0]_i_3_n_0 ; wire \time_out_counter[0]_i_4_n_0 ; wire \time_out_counter[0]_i_5_n_0 ; wire [18:0]time_out_counter_reg; wire \time_out_counter_reg[0]_i_2__0_n_0 ; wire \time_out_counter_reg[0]_i_2__0_n_1 ; wire \time_out_counter_reg[0]_i_2__0_n_2 ; wire \time_out_counter_reg[0]_i_2__0_n_3 ; wire \time_out_counter_reg[0]_i_2__0_n_4 ; wire \time_out_counter_reg[0]_i_2__0_n_5 ; wire \time_out_counter_reg[0]_i_2__0_n_6 ; wire \time_out_counter_reg[0]_i_2__0_n_7 ; wire \time_out_counter_reg[12]_i_1__0_n_0 ; wire \time_out_counter_reg[12]_i_1__0_n_1 ; wire \time_out_counter_reg[12]_i_1__0_n_2 ; wire \time_out_counter_reg[12]_i_1__0_n_3 ; wire \time_out_counter_reg[12]_i_1__0_n_4 ; wire \time_out_counter_reg[12]_i_1__0_n_5 ; wire \time_out_counter_reg[12]_i_1__0_n_6 ; wire \time_out_counter_reg[12]_i_1__0_n_7 ; wire \time_out_counter_reg[16]_i_1__0_n_2 ; wire \time_out_counter_reg[16]_i_1__0_n_3 ; wire \time_out_counter_reg[16]_i_1__0_n_5 ; wire \time_out_counter_reg[16]_i_1__0_n_6 ; wire \time_out_counter_reg[16]_i_1__0_n_7 ; wire \time_out_counter_reg[4]_i_1__0_n_0 ; wire \time_out_counter_reg[4]_i_1__0_n_1 ; wire \time_out_counter_reg[4]_i_1__0_n_2 ; wire \time_out_counter_reg[4]_i_1__0_n_3 ; wire \time_out_counter_reg[4]_i_1__0_n_4 ; wire \time_out_counter_reg[4]_i_1__0_n_5 ; wire \time_out_counter_reg[4]_i_1__0_n_6 ; wire \time_out_counter_reg[4]_i_1__0_n_7 ; wire \time_out_counter_reg[8]_i_1__0_n_0 ; wire \time_out_counter_reg[8]_i_1__0_n_1 ; wire \time_out_counter_reg[8]_i_1__0_n_2 ; wire \time_out_counter_reg[8]_i_1__0_n_3 ; wire \time_out_counter_reg[8]_i_1__0_n_4 ; wire \time_out_counter_reg[8]_i_1__0_n_5 ; wire \time_out_counter_reg[8]_i_1__0_n_6 ; wire \time_out_counter_reg[8]_i_1__0_n_7 ; wire time_out_wait_bypass_i_1__0_n_0; wire time_out_wait_bypass_reg_n_0; wire time_out_wait_bypass_s2; wire time_out_wait_bypass_s3; wire time_tlock_max; wire time_tlock_max1; wire time_tlock_max1_carry__0_i_1_n_0; wire time_tlock_max1_carry__0_i_2_n_0; wire time_tlock_max1_carry__0_i_3_n_0; wire time_tlock_max1_carry__0_i_4_n_0; wire time_tlock_max1_carry__0_i_5_n_0; wire time_tlock_max1_carry__0_i_6_n_0; wire time_tlock_max1_carry__0_n_0; wire time_tlock_max1_carry__0_n_1; wire time_tlock_max1_carry__0_n_2; wire time_tlock_max1_carry__0_n_3; wire time_tlock_max1_carry__1_i_1_n_0; wire time_tlock_max1_carry__1_i_2_n_0; wire time_tlock_max1_carry__1_i_3_n_0; wire time_tlock_max1_carry__1_n_3; wire time_tlock_max1_carry_i_1_n_0; wire time_tlock_max1_carry_i_2_n_0; wire time_tlock_max1_carry_i_3_n_0; wire time_tlock_max1_carry_i_4_n_0; wire time_tlock_max1_carry_i_5_n_0; wire time_tlock_max1_carry_i_6_n_0; wire time_tlock_max1_carry_i_7_n_0; wire time_tlock_max1_carry_i_8_n_0; wire time_tlock_max1_carry_n_0; wire time_tlock_max1_carry_n_1; wire time_tlock_max1_carry_n_2; wire time_tlock_max1_carry_n_3; wire time_tlock_max_i_1_n_0; wire userclk; wire \wait_bypass_count[0]_i_1__0_n_0 ; wire \wait_bypass_count[0]_i_2__0_n_0 ; wire \wait_bypass_count[0]_i_4__0_n_0 ; wire \wait_bypass_count[0]_i_5__0_n_0 ; wire \wait_bypass_count[0]_i_6__0_n_0 ; wire \wait_bypass_count[0]_i_7__0_n_0 ; wire [12:0]wait_bypass_count_reg; wire \wait_bypass_count_reg[0]_i_3__0_n_0 ; wire \wait_bypass_count_reg[0]_i_3__0_n_1 ; wire \wait_bypass_count_reg[0]_i_3__0_n_2 ; wire \wait_bypass_count_reg[0]_i_3__0_n_3 ; wire \wait_bypass_count_reg[0]_i_3__0_n_4 ; wire \wait_bypass_count_reg[0]_i_3__0_n_5 ; wire \wait_bypass_count_reg[0]_i_3__0_n_6 ; wire \wait_bypass_count_reg[0]_i_3__0_n_7 ; wire \wait_bypass_count_reg[12]_i_1__0_n_7 ; wire \wait_bypass_count_reg[4]_i_1__0_n_0 ; wire \wait_bypass_count_reg[4]_i_1__0_n_1 ; wire \wait_bypass_count_reg[4]_i_1__0_n_2 ; wire \wait_bypass_count_reg[4]_i_1__0_n_3 ; wire \wait_bypass_count_reg[4]_i_1__0_n_4 ; wire \wait_bypass_count_reg[4]_i_1__0_n_5 ; wire \wait_bypass_count_reg[4]_i_1__0_n_6 ; wire \wait_bypass_count_reg[4]_i_1__0_n_7 ; wire \wait_bypass_count_reg[8]_i_1__0_n_0 ; wire \wait_bypass_count_reg[8]_i_1__0_n_1 ; wire \wait_bypass_count_reg[8]_i_1__0_n_2 ; wire \wait_bypass_count_reg[8]_i_1__0_n_3 ; wire \wait_bypass_count_reg[8]_i_1__0_n_4 ; wire \wait_bypass_count_reg[8]_i_1__0_n_5 ; wire \wait_bypass_count_reg[8]_i_1__0_n_6 ; wire \wait_bypass_count_reg[8]_i_1__0_n_7 ; wire [0:0]wait_time_cnt0__0; wire \wait_time_cnt[1]_i_1__0_n_0 ; wire \wait_time_cnt[2]_i_1__0_n_0 ; wire \wait_time_cnt[3]_i_1__0_n_0 ; wire \wait_time_cnt[4]_i_1__0_n_0 ; wire \wait_time_cnt[5]_i_1__0_n_0 ; wire \wait_time_cnt[6]_i_1_n_0 ; wire \wait_time_cnt[6]_i_2__0_n_0 ; wire \wait_time_cnt[6]_i_3__0_n_0 ; wire \wait_time_cnt[6]_i_4__0_n_0 ; wire [6:0]wait_time_cnt_reg__0; wire [3:2]\NLW_time_out_counter_reg[16]_i_1__0_CO_UNCONNECTED ; wire [3:3]\NLW_time_out_counter_reg[16]_i_1__0_O_UNCONNECTED ; wire [3:0]NLW_time_tlock_max1_carry_O_UNCONNECTED; wire [3:0]NLW_time_tlock_max1_carry__0_O_UNCONNECTED; wire [3:2]NLW_time_tlock_max1_carry__1_CO_UNCONNECTED; wire [3:0]NLW_time_tlock_max1_carry__1_O_UNCONNECTED; wire [3:0]\NLW_wait_bypass_count_reg[12]_i_1__0_CO_UNCONNECTED ; wire [3:1]\NLW_wait_bypass_count_reg[12]_i_1__0_O_UNCONNECTED ; assign gt0_rx_cdrlock_counter_reg_0_sn_1 = gt0_rx_cdrlock_counter_reg_0_sp_1; LUT6 #( .INIT(64'h2222AAAA00000C00)) \FSM_sequential_rx_state[0]_i_2 (.I0(time_out_2ms_reg_n_0), .I1(rx_state[2]), .I2(rx_state[3]), .I3(time_tlock_max), .I4(reset_time_out_reg_n_0), .I5(rx_state[1]), .O(\FSM_sequential_rx_state[0]_i_2_n_0 )); LUT6 #( .INIT(64'h0000AABF000F0000)) \FSM_sequential_rx_state[1]_i_3 (.I0(reset_time_out_reg_n_0), .I1(time_tlock_max), .I2(rx_state[2]), .I3(rx_state[3]), .I4(rx_state[1]), .I5(rx_state[0]), .O(\FSM_sequential_rx_state[1]_i_3_n_0 )); LUT6 #( .INIT(64'h0000000050FF2200)) \FSM_sequential_rx_state[2]_i_1 (.I0(rx_state[1]), .I1(time_out_2ms_reg_n_0), .I2(\FSM_sequential_rx_state[2]_i_2_n_0 ), .I3(rx_state[0]), .I4(rx_state[2]), .I5(rx_state[3]), .O(\FSM_sequential_rx_state[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair54" *) LUT2 #( .INIT(4'hB)) \FSM_sequential_rx_state[2]_i_2 (.I0(reset_time_out_reg_n_0), .I1(time_tlock_max), .O(\FSM_sequential_rx_state[2]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair51" *) LUT2 #( .INIT(4'hB)) \FSM_sequential_rx_state[3]_i_10 (.I0(reset_time_out_reg_n_0), .I1(time_out_2ms_reg_n_0), .O(\FSM_sequential_rx_state[3]_i_10_n_0 )); LUT6 #( .INIT(64'h0000000050005300)) \FSM_sequential_rx_state[3]_i_3 (.I0(\FSM_sequential_rx_state[3]_i_10_n_0 ), .I1(\wait_time_cnt[6]_i_4__0_n_0 ), .I2(rx_state[0]), .I3(rx_state[1]), .I4(wait_time_cnt_reg__0[6]), .I5(rx_state[3]), .O(\FSM_sequential_rx_state[3]_i_3_n_0 )); LUT6 #( .INIT(64'h0000000023002F00)) \FSM_sequential_rx_state[3]_i_7 (.I0(time_out_2ms_reg_n_0), .I1(rx_state[2]), .I2(rx_state[1]), .I3(rx_state[0]), .I4(\FSM_sequential_rx_state[2]_i_2_n_0 ), .I5(rx_state[3]), .O(\FSM_sequential_rx_state[3]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair47" *) LUT5 #( .INIT(32'h80800080)) \FSM_sequential_rx_state[3]_i_9 (.I0(rx_state[0]), .I1(rx_state[1]), .I2(rx_state[2]), .I3(time_out_2ms_reg_n_0), .I4(reset_time_out_reg_n_0), .O(\FSM_sequential_rx_state[3]_i_9_n_0 )); (* FSM_ENCODED_STATES = "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *) FDRE #( .INIT(1'b0)) \FSM_sequential_rx_state_reg[0] (.C(independent_clock_bufg), .CE(sync_data_valid_n_3), .D(sync_data_valid_n_2), .Q(rx_state[0]), .R(pma_reset)); (* FSM_ENCODED_STATES = "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *) FDRE #( .INIT(1'b0)) \FSM_sequential_rx_state_reg[1] (.C(independent_clock_bufg), .CE(sync_data_valid_n_3), .D(sync_data_valid_n_1), .Q(rx_state[1]), .R(pma_reset)); (* FSM_ENCODED_STATES = "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *) FDRE #( .INIT(1'b0)) \FSM_sequential_rx_state_reg[2] (.C(independent_clock_bufg), .CE(sync_data_valid_n_3), .D(\FSM_sequential_rx_state[2]_i_1_n_0 ), .Q(rx_state[2]), .R(pma_reset)); (* FSM_ENCODED_STATES = "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *) FDRE #( .INIT(1'b0)) \FSM_sequential_rx_state_reg[3] (.C(independent_clock_bufg), .CE(sync_data_valid_n_3), .D(sync_data_valid_n_0), .Q(rx_state[3]), .R(pma_reset)); LUT5 #( .INIT(32'hFFFB4000)) RXUSERRDY_i_1 (.I0(rx_state[3]), .I1(rx_state[0]), .I2(rx_state[2]), .I3(rx_state[1]), .I4(gt0_rxuserrdy_t), .O(RXUSERRDY_i_1_n_0)); FDRE #( .INIT(1'b0)) RXUSERRDY_reg (.C(independent_clock_bufg), .CE(1'b1), .D(RXUSERRDY_i_1_n_0), .Q(gt0_rxuserrdy_t), .R(pma_reset)); LUT5 #( .INIT(32'hFFFB0008)) check_tlock_max_i_1 (.I0(rx_state[2]), .I1(rx_state[0]), .I2(rx_state[1]), .I3(rx_state[3]), .I4(check_tlock_max_reg_n_0), .O(check_tlock_max_i_1_n_0)); FDRE #( .INIT(1'b0)) check_tlock_max_reg (.C(independent_clock_bufg), .CE(1'b1), .D(check_tlock_max_i_1_n_0), .Q(check_tlock_max_reg_n_0), .R(pma_reset)); LUT6 #( .INIT(64'h00000000AAAEAAAA)) gt0_rx_cdrlocked_i_1 (.I0(gt0_rx_cdrlocked_reg_0), .I1(gt0_rx_cdrlocked_reg_1), .I2(gt0_rx_cdrlock_counter_reg[0]), .I3(gt0_rx_cdrlock_counter_reg[1]), .I4(gt0_rx_cdrlocked_reg_2), .I5(gt0_gtrxreset_in1_out), .O(gt0_rx_cdrlocked_reg)); LUT5 #( .INIT(32'hFFEF0100)) gtrxreset_i_i_1 (.I0(rx_state[3]), .I1(rx_state[1]), .I2(rx_state[2]), .I3(rx_state[0]), .I4(GTRXRESET), .O(gtrxreset_i_i_1_n_0)); FDRE #( .INIT(1'b0)) gtrxreset_i_reg (.C(independent_clock_bufg), .CE(1'b1), .D(gtrxreset_i_i_1_n_0), .Q(GTRXRESET), .R(pma_reset)); LUT3 #( .INIT(8'hF8)) gtxe2_i_i_2 (.I0(data_in), .I1(gt0_rx_cdrlock_counter_reg_0_sn_1), .I2(GTRXRESET), .O(gt0_gtrxreset_in1_out)); LUT1 #( .INIT(2'h1)) \init_wait_count[0]_i_1__0 (.I0(init_wait_count_reg__0[0]), .O(\init_wait_count[0]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair50" *) LUT2 #( .INIT(4'h6)) \init_wait_count[1]_i_1__0 (.I0(init_wait_count_reg__0[0]), .I1(init_wait_count_reg__0[1]), .O(p_0_in__2[1])); (* SOFT_HLUTNM = "soft_lutpair53" *) LUT3 #( .INIT(8'h78)) \init_wait_count[2]_i_1__0 (.I0(init_wait_count_reg__0[1]), .I1(init_wait_count_reg__0[0]), .I2(init_wait_count_reg__0[2]), .O(p_0_in__2[2])); (* SOFT_HLUTNM = "soft_lutpair49" *) LUT4 #( .INIT(16'h7F80)) \init_wait_count[3]_i_1__0 (.I0(init_wait_count_reg__0[1]), .I1(init_wait_count_reg__0[2]), .I2(init_wait_count_reg__0[0]), .I3(init_wait_count_reg__0[3]), .O(p_0_in__2[3])); (* SOFT_HLUTNM = "soft_lutpair49" *) LUT5 #( .INIT(32'h7FFF8000)) \init_wait_count[4]_i_1__0 (.I0(init_wait_count_reg__0[2]), .I1(init_wait_count_reg__0[1]), .I2(init_wait_count_reg__0[3]), .I3(init_wait_count_reg__0[0]), .I4(init_wait_count_reg__0[4]), .O(p_0_in__2[4])); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \init_wait_count[5]_i_1__0 (.I0(init_wait_count_reg__0[2]), .I1(init_wait_count_reg__0[1]), .I2(init_wait_count_reg__0[3]), .I3(init_wait_count_reg__0[0]), .I4(init_wait_count_reg__0[4]), .I5(init_wait_count_reg__0[5]), .O(p_0_in__2[5])); LUT4 #( .INIT(16'hFEFF)) \init_wait_count[6]_i_1__0 (.I0(\init_wait_count[6]_i_3__0_n_0 ), .I1(init_wait_count_reg__0[0]), .I2(init_wait_count_reg__0[4]), .I3(init_wait_count_reg__0[6]), .O(\init_wait_count[6]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair50" *) LUT4 #( .INIT(16'hBF40)) \init_wait_count[6]_i_2__0 (.I0(\init_wait_count[6]_i_3__0_n_0 ), .I1(init_wait_count_reg__0[0]), .I2(init_wait_count_reg__0[4]), .I3(init_wait_count_reg__0[6]), .O(p_0_in__2[6])); (* SOFT_HLUTNM = "soft_lutpair53" *) LUT4 #( .INIT(16'h7FFF)) \init_wait_count[6]_i_3__0 (.I0(init_wait_count_reg__0[3]), .I1(init_wait_count_reg__0[1]), .I2(init_wait_count_reg__0[2]), .I3(init_wait_count_reg__0[5]), .O(\init_wait_count[6]_i_3__0_n_0 )); FDCE #( .INIT(1'b0)) \init_wait_count_reg[0] (.C(independent_clock_bufg), .CE(\init_wait_count[6]_i_1__0_n_0 ), .CLR(pma_reset), .D(\init_wait_count[0]_i_1__0_n_0 ), .Q(init_wait_count_reg__0[0])); FDCE #( .INIT(1'b0)) \init_wait_count_reg[1] (.C(independent_clock_bufg), .CE(\init_wait_count[6]_i_1__0_n_0 ), .CLR(pma_reset), .D(p_0_in__2[1]), .Q(init_wait_count_reg__0[1])); FDCE #( .INIT(1'b0)) \init_wait_count_reg[2] (.C(independent_clock_bufg), .CE(\init_wait_count[6]_i_1__0_n_0 ), .CLR(pma_reset), .D(p_0_in__2[2]), .Q(init_wait_count_reg__0[2])); FDCE #( .INIT(1'b0)) \init_wait_count_reg[3] (.C(independent_clock_bufg), .CE(\init_wait_count[6]_i_1__0_n_0 ), .CLR(pma_reset), .D(p_0_in__2[3]), .Q(init_wait_count_reg__0[3])); FDCE #( .INIT(1'b0)) \init_wait_count_reg[4] (.C(independent_clock_bufg), .CE(\init_wait_count[6]_i_1__0_n_0 ), .CLR(pma_reset), .D(p_0_in__2[4]), .Q(init_wait_count_reg__0[4])); FDCE #( .INIT(1'b0)) \init_wait_count_reg[5] (.C(independent_clock_bufg), .CE(\init_wait_count[6]_i_1__0_n_0 ), .CLR(pma_reset), .D(p_0_in__2[5]), .Q(init_wait_count_reg__0[5])); FDCE #( .INIT(1'b0)) \init_wait_count_reg[6] (.C(independent_clock_bufg), .CE(\init_wait_count[6]_i_1__0_n_0 ), .CLR(pma_reset), .D(p_0_in__2[6]), .Q(init_wait_count_reg__0[6])); LUT5 #( .INIT(32'hFFFF0010)) init_wait_done_i_1__0 (.I0(\init_wait_count[6]_i_3__0_n_0 ), .I1(init_wait_count_reg__0[4]), .I2(init_wait_count_reg__0[6]), .I3(init_wait_count_reg__0[0]), .I4(init_wait_done_reg_n_0), .O(init_wait_done_i_1__0_n_0)); FDCE #( .INIT(1'b0)) init_wait_done_reg (.C(independent_clock_bufg), .CE(1'b1), .CLR(pma_reset), .D(init_wait_done_i_1__0_n_0), .Q(init_wait_done_reg_n_0)); LUT1 #( .INIT(2'h1)) \mmcm_lock_count[0]_i_1__0 (.I0(mmcm_lock_count_reg__0[0]), .O(p_0_in__3[0])); (* SOFT_HLUTNM = "soft_lutpair55" *) LUT2 #( .INIT(4'h6)) \mmcm_lock_count[1]_i_1__0 (.I0(mmcm_lock_count_reg__0[0]), .I1(mmcm_lock_count_reg__0[1]), .O(p_0_in__3[1])); (* SOFT_HLUTNM = "soft_lutpair55" *) LUT3 #( .INIT(8'h78)) \mmcm_lock_count[2]_i_1__0 (.I0(mmcm_lock_count_reg__0[1]), .I1(mmcm_lock_count_reg__0[0]), .I2(mmcm_lock_count_reg__0[2]), .O(\mmcm_lock_count[2]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair44" *) LUT4 #( .INIT(16'h7F80)) \mmcm_lock_count[3]_i_1__0 (.I0(mmcm_lock_count_reg__0[2]), .I1(mmcm_lock_count_reg__0[0]), .I2(mmcm_lock_count_reg__0[1]), .I3(mmcm_lock_count_reg__0[3]), .O(\mmcm_lock_count[3]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair44" *) LUT5 #( .INIT(32'h7FFF8000)) \mmcm_lock_count[4]_i_1__0 (.I0(mmcm_lock_count_reg__0[3]), .I1(mmcm_lock_count_reg__0[1]), .I2(mmcm_lock_count_reg__0[0]), .I3(mmcm_lock_count_reg__0[2]), .I4(mmcm_lock_count_reg__0[4]), .O(\mmcm_lock_count[4]_i_1__0_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \mmcm_lock_count[5]_i_1__0 (.I0(mmcm_lock_count_reg__0[4]), .I1(mmcm_lock_count_reg__0[2]), .I2(mmcm_lock_count_reg__0[0]), .I3(mmcm_lock_count_reg__0[1]), .I4(mmcm_lock_count_reg__0[3]), .I5(mmcm_lock_count_reg__0[5]), .O(\mmcm_lock_count[5]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair56" *) LUT2 #( .INIT(4'h9)) \mmcm_lock_count[6]_i_1__0 (.I0(\mmcm_lock_count[7]_i_4__0_n_0 ), .I1(mmcm_lock_count_reg__0[6]), .O(\mmcm_lock_count[6]_i_1__0_n_0 )); LUT3 #( .INIT(8'hBF)) \mmcm_lock_count[7]_i_2__0 (.I0(\mmcm_lock_count[7]_i_4__0_n_0 ), .I1(mmcm_lock_count_reg__0[6]), .I2(mmcm_lock_count_reg__0[7]), .O(\mmcm_lock_count[7]_i_2__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair56" *) LUT3 #( .INIT(8'hD2)) \mmcm_lock_count[7]_i_3__0 (.I0(mmcm_lock_count_reg__0[6]), .I1(\mmcm_lock_count[7]_i_4__0_n_0 ), .I2(mmcm_lock_count_reg__0[7]), .O(\mmcm_lock_count[7]_i_3__0_n_0 )); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) \mmcm_lock_count[7]_i_4__0 (.I0(mmcm_lock_count_reg__0[4]), .I1(mmcm_lock_count_reg__0[2]), .I2(mmcm_lock_count_reg__0[0]), .I3(mmcm_lock_count_reg__0[1]), .I4(mmcm_lock_count_reg__0[3]), .I5(mmcm_lock_count_reg__0[5]), .O(\mmcm_lock_count[7]_i_4__0_n_0 )); FDRE #( .INIT(1'b0)) \mmcm_lock_count_reg[0] (.C(independent_clock_bufg), .CE(\mmcm_lock_count[7]_i_2__0_n_0 ), .D(p_0_in__3[0]), .Q(mmcm_lock_count_reg__0[0]), .R(sync_mmcm_lock_reclocked_n_0)); FDRE #( .INIT(1'b0)) \mmcm_lock_count_reg[1] (.C(independent_clock_bufg), .CE(\mmcm_lock_count[7]_i_2__0_n_0 ), .D(p_0_in__3[1]), .Q(mmcm_lock_count_reg__0[1]), .R(sync_mmcm_lock_reclocked_n_0)); FDRE #( .INIT(1'b0)) \mmcm_lock_count_reg[2] (.C(independent_clock_bufg), .CE(\mmcm_lock_count[7]_i_2__0_n_0 ), .D(\mmcm_lock_count[2]_i_1__0_n_0 ), .Q(mmcm_lock_count_reg__0[2]), .R(sync_mmcm_lock_reclocked_n_0)); FDRE #( .INIT(1'b0)) \mmcm_lock_count_reg[3] (.C(independent_clock_bufg), .CE(\mmcm_lock_count[7]_i_2__0_n_0 ), .D(\mmcm_lock_count[3]_i_1__0_n_0 ), .Q(mmcm_lock_count_reg__0[3]), .R(sync_mmcm_lock_reclocked_n_0)); FDRE #( .INIT(1'b0)) \mmcm_lock_count_reg[4] (.C(independent_clock_bufg), .CE(\mmcm_lock_count[7]_i_2__0_n_0 ), .D(\mmcm_lock_count[4]_i_1__0_n_0 ), .Q(mmcm_lock_count_reg__0[4]), .R(sync_mmcm_lock_reclocked_n_0)); FDRE #( .INIT(1'b0)) \mmcm_lock_count_reg[5] (.C(independent_clock_bufg), .CE(\mmcm_lock_count[7]_i_2__0_n_0 ), .D(\mmcm_lock_count[5]_i_1__0_n_0 ), .Q(mmcm_lock_count_reg__0[5]), .R(sync_mmcm_lock_reclocked_n_0)); FDRE #( .INIT(1'b0)) \mmcm_lock_count_reg[6] (.C(independent_clock_bufg), .CE(\mmcm_lock_count[7]_i_2__0_n_0 ), .D(\mmcm_lock_count[6]_i_1__0_n_0 ), .Q(mmcm_lock_count_reg__0[6]), .R(sync_mmcm_lock_reclocked_n_0)); FDRE #( .INIT(1'b0)) \mmcm_lock_count_reg[7] (.C(independent_clock_bufg), .CE(\mmcm_lock_count[7]_i_2__0_n_0 ), .D(\mmcm_lock_count[7]_i_3__0_n_0 ), .Q(mmcm_lock_count_reg__0[7]), .R(sync_mmcm_lock_reclocked_n_0)); FDRE #( .INIT(1'b0)) mmcm_lock_reclocked_reg (.C(independent_clock_bufg), .CE(1'b1), .D(sync_mmcm_lock_reclocked_n_1), .Q(mmcm_lock_reclocked), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair46" *) LUT2 #( .INIT(4'hE)) reset_time_out_i_3 (.I0(rx_state[2]), .I1(rx_state[3]), .O(reset_time_out_i_3_n_0)); (* SOFT_HLUTNM = "soft_lutpair45" *) LUT5 #( .INIT(32'h34347674)) reset_time_out_i_4 (.I0(rx_state[2]), .I1(rx_state[3]), .I2(rx_state[0]), .I3(gt0_rx_cdrlocked_reg_0), .I4(rx_state[1]), .O(reset_time_out_i_4_n_0)); FDSE #( .INIT(1'b0)) reset_time_out_reg (.C(independent_clock_bufg), .CE(1'b1), .D(sync_data_valid_n_4), .Q(reset_time_out_reg_n_0), .S(pma_reset)); (* SOFT_HLUTNM = "soft_lutpair46" *) LUT5 #( .INIT(32'hFEFF0010)) run_phase_alignment_int_i_1__0 (.I0(rx_state[2]), .I1(rx_state[1]), .I2(rx_state[3]), .I3(rx_state[0]), .I4(run_phase_alignment_int_reg_n_0), .O(run_phase_alignment_int_i_1__0_n_0)); FDRE #( .INIT(1'b0)) run_phase_alignment_int_reg (.C(independent_clock_bufg), .CE(1'b1), .D(run_phase_alignment_int_i_1__0_n_0), .Q(run_phase_alignment_int_reg_n_0), .R(pma_reset)); FDRE #( .INIT(1'b0)) run_phase_alignment_int_s3_reg (.C(userclk), .CE(1'b1), .D(data_out_0), .Q(run_phase_alignment_int_s3_reg_n_0), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair47" *) LUT2 #( .INIT(4'hB)) rx_fsm_reset_done_int_i_5 (.I0(rx_state[1]), .I1(rx_state[0]), .O(rx_fsm_reset_done_int_i_5_n_0)); (* SOFT_HLUTNM = "soft_lutpair45" *) LUT2 #( .INIT(4'h2)) rx_fsm_reset_done_int_i_6 (.I0(rx_state[3]), .I1(rx_state[2]), .O(rx_fsm_reset_done_int_i_6_n_0)); FDRE #( .INIT(1'b0)) rx_fsm_reset_done_int_reg (.C(independent_clock_bufg), .CE(1'b1), .D(sync_data_valid_n_5), .Q(data_in), .R(pma_reset)); FDRE #( .INIT(1'b0)) rx_fsm_reset_done_int_s3_reg (.C(userclk), .CE(1'b1), .D(rx_fsm_reset_done_int_s2), .Q(rx_fsm_reset_done_int_s3), .R(1'b0)); FDRE #( .INIT(1'b0)) rxresetdone_s3_reg (.C(independent_clock_bufg), .CE(1'b1), .D(rxresetdone_s2), .Q(rxresetdone_s3), .R(1'b0)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_10 sync_RXRESETDONE (.data_out(rxresetdone_s2), .data_sync_reg1_0(data_sync_reg1), .independent_clock_bufg(independent_clock_bufg)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_11 sync_cplllock (.\FSM_sequential_rx_state_reg[1] (sync_cplllock_n_0), .Q(rx_state[3:1]), .cplllock(cplllock), .independent_clock_bufg(independent_clock_bufg), .rxresetdone_s3(rxresetdone_s3)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_12 sync_data_valid (.D({sync_data_valid_n_0,sync_data_valid_n_1,sync_data_valid_n_2}), .E(sync_data_valid_n_3), .\FSM_sequential_rx_state_reg[0] (\FSM_sequential_rx_state[3]_i_3_n_0 ), .\FSM_sequential_rx_state_reg[0]_0 (\FSM_sequential_rx_state[3]_i_7_n_0 ), .\FSM_sequential_rx_state_reg[0]_1 (gt0_rx_cdrlocked_reg_0), .\FSM_sequential_rx_state_reg[0]_2 (\FSM_sequential_rx_state[0]_i_2_n_0 ), .\FSM_sequential_rx_state_reg[0]_3 (init_wait_done_reg_n_0), .\FSM_sequential_rx_state_reg[1] (sync_data_valid_n_4), .\FSM_sequential_rx_state_reg[1]_0 (\FSM_sequential_rx_state[1]_i_3_n_0 ), .\FSM_sequential_rx_state_reg[3] (\FSM_sequential_rx_state[3]_i_9_n_0 ), .Q(rx_state), .data_in(data_in), .data_out(data_out), .independent_clock_bufg(independent_clock_bufg), .mmcm_lock_reclocked(mmcm_lock_reclocked), .reset_time_out_reg(reset_time_out_reg_n_0), .reset_time_out_reg_0(sync_cplllock_n_0), .reset_time_out_reg_1(reset_time_out_i_3_n_0), .reset_time_out_reg_2(reset_time_out_i_4_n_0), .rx_fsm_reset_done_int_reg(sync_data_valid_n_5), .rx_fsm_reset_done_int_reg_0(rx_fsm_reset_done_int_i_5_n_0), .rx_fsm_reset_done_int_reg_1(time_out_100us_reg_n_0), .rx_fsm_reset_done_int_reg_2(time_out_1us_reg_n_0), .rx_fsm_reset_done_int_reg_3(rx_fsm_reset_done_int_i_6_n_0), .time_out_wait_bypass_s3(time_out_wait_bypass_s3)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_13 sync_mmcm_lock_reclocked (.Q(mmcm_lock_count_reg__0[7:6]), .SR(sync_mmcm_lock_reclocked_n_0), .independent_clock_bufg(independent_clock_bufg), .mmcm_lock_reclocked(mmcm_lock_reclocked), .mmcm_lock_reclocked_reg(sync_mmcm_lock_reclocked_n_1), .mmcm_lock_reclocked_reg_0(\mmcm_lock_count[7]_i_4__0_n_0 ), .mmcm_locked(mmcm_locked)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_14 sync_run_phase_alignment_int (.data_in(run_phase_alignment_int_reg_n_0), .data_out(data_out_0), .userclk(userclk)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_15 sync_time_out_wait_bypass (.data_in(time_out_wait_bypass_reg_n_0), .data_out(time_out_wait_bypass_s2), .independent_clock_bufg(independent_clock_bufg)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_16 sync_tx_fsm_reset_done_int (.data_in(data_in), .data_out(rx_fsm_reset_done_int_s2), .userclk(userclk)); LUT6 #( .INIT(64'hFFFFFFFF00000100)) time_out_100us_i_1 (.I0(\time_out_counter[0]_i_4_n_0 ), .I1(time_out_counter_reg[17]), .I2(time_out_counter_reg[16]), .I3(time_out_100us_i_2_n_0), .I4(time_out_100us_i_3_n_0), .I5(time_out_100us_reg_n_0), .O(time_out_100us_i_1_n_0)); LUT6 #( .INIT(64'h0000002000000000)) time_out_100us_i_2 (.I0(time_out_counter_reg[10]), .I1(time_out_counter_reg[12]), .I2(time_out_counter_reg[5]), .I3(time_out_counter_reg[7]), .I4(time_out_counter_reg[18]), .I5(time_out_counter_reg[14]), .O(time_out_100us_i_2_n_0)); LUT5 #( .INIT(32'hFFFFFFFE)) time_out_100us_i_3 (.I0(time_out_counter_reg[4]), .I1(time_out_counter_reg[0]), .I2(time_out_counter_reg[1]), .I3(time_out_counter_reg[15]), .I4(time_out_counter_reg[13]), .O(time_out_100us_i_3_n_0)); FDRE #( .INIT(1'b0)) time_out_100us_reg (.C(independent_clock_bufg), .CE(1'b1), .D(time_out_100us_i_1_n_0), .Q(time_out_100us_reg_n_0), .R(reset_time_out_reg_n_0)); LUT6 #( .INIT(64'hFFFFFFFF00100000)) time_out_1us_i_1 (.I0(\time_out_counter[0]_i_3_n_0 ), .I1(time_out_1us_i_2_n_0), .I2(time_out_counter_reg[3]), .I3(time_out_counter_reg[2]), .I4(time_out_1us_i_3_n_0), .I5(time_out_1us_reg_n_0), .O(time_out_1us_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair52" *) LUT2 #( .INIT(4'hE)) time_out_1us_i_2 (.I0(time_out_counter_reg[16]), .I1(time_out_counter_reg[17]), .O(time_out_1us_i_2_n_0)); LUT6 #( .INIT(64'h0000000000000010)) time_out_1us_i_3 (.I0(time_out_counter_reg[9]), .I1(time_out_counter_reg[11]), .I2(time_out_counter_reg[6]), .I3(time_out_counter_reg[8]), .I4(time_out_counter_reg[18]), .I5(time_out_counter_reg[12]), .O(time_out_1us_i_3_n_0)); FDRE #( .INIT(1'b0)) time_out_1us_reg (.C(independent_clock_bufg), .CE(1'b1), .D(time_out_1us_i_1_n_0), .Q(time_out_1us_reg_n_0), .R(reset_time_out_reg_n_0)); (* SOFT_HLUTNM = "soft_lutpair51" *) LUT4 #( .INIT(16'hFF04)) time_out_2ms_i_1 (.I0(\time_out_counter[0]_i_3_n_0 ), .I1(time_out_2ms_i_2__0_n_0), .I2(\time_out_counter[0]_i_4_n_0 ), .I3(time_out_2ms_reg_n_0), .O(time_out_2ms_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair52" *) LUT4 #( .INIT(16'h4000)) time_out_2ms_i_2__0 (.I0(time_out_counter_reg[16]), .I1(time_out_counter_reg[12]), .I2(time_out_counter_reg[18]), .I3(time_out_counter_reg[17]), .O(time_out_2ms_i_2__0_n_0)); FDRE #( .INIT(1'b0)) time_out_2ms_reg (.C(independent_clock_bufg), .CE(1'b1), .D(time_out_2ms_i_1_n_0), .Q(time_out_2ms_reg_n_0), .R(reset_time_out_reg_n_0)); LUT6 #( .INIT(64'hFFFFFFFFFFFFBFFF)) \time_out_counter[0]_i_1 (.I0(time_out_counter_reg[16]), .I1(time_out_counter_reg[12]), .I2(time_out_counter_reg[18]), .I3(time_out_counter_reg[17]), .I4(\time_out_counter[0]_i_3_n_0 ), .I5(\time_out_counter[0]_i_4_n_0 ), .O(time_out_counter)); LUT5 #( .INIT(32'hFFFFFEFF)) \time_out_counter[0]_i_3 (.I0(time_out_counter_reg[10]), .I1(time_out_counter_reg[14]), .I2(time_out_counter_reg[5]), .I3(time_out_counter_reg[7]), .I4(time_out_100us_i_3_n_0), .O(\time_out_counter[0]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFEFFFFFF)) \time_out_counter[0]_i_4 (.I0(time_out_counter_reg[2]), .I1(time_out_counter_reg[3]), .I2(time_out_counter_reg[8]), .I3(time_out_counter_reg[9]), .I4(time_out_counter_reg[11]), .I5(time_out_counter_reg[6]), .O(\time_out_counter[0]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \time_out_counter[0]_i_5 (.I0(time_out_counter_reg[0]), .O(\time_out_counter[0]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \time_out_counter_reg[0] (.C(independent_clock_bufg), .CE(time_out_counter), .D(\time_out_counter_reg[0]_i_2__0_n_7 ), .Q(time_out_counter_reg[0]), .R(reset_time_out_reg_n_0)); CARRY4 \time_out_counter_reg[0]_i_2__0 (.CI(1'b0), .CO({\time_out_counter_reg[0]_i_2__0_n_0 ,\time_out_counter_reg[0]_i_2__0_n_1 ,\time_out_counter_reg[0]_i_2__0_n_2 ,\time_out_counter_reg[0]_i_2__0_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b1}), .O({\time_out_counter_reg[0]_i_2__0_n_4 ,\time_out_counter_reg[0]_i_2__0_n_5 ,\time_out_counter_reg[0]_i_2__0_n_6 ,\time_out_counter_reg[0]_i_2__0_n_7 }), .S({time_out_counter_reg[3:1],\time_out_counter[0]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \time_out_counter_reg[10] (.C(independent_clock_bufg), .CE(time_out_counter), .D(\time_out_counter_reg[8]_i_1__0_n_5 ), .Q(time_out_counter_reg[10]), .R(reset_time_out_reg_n_0)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[11] (.C(independent_clock_bufg), .CE(time_out_counter), .D(\time_out_counter_reg[8]_i_1__0_n_4 ), .Q(time_out_counter_reg[11]), .R(reset_time_out_reg_n_0)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[12] (.C(independent_clock_bufg), .CE(time_out_counter), .D(\time_out_counter_reg[12]_i_1__0_n_7 ), .Q(time_out_counter_reg[12]), .R(reset_time_out_reg_n_0)); CARRY4 \time_out_counter_reg[12]_i_1__0 (.CI(\time_out_counter_reg[8]_i_1__0_n_0 ), .CO({\time_out_counter_reg[12]_i_1__0_n_0 ,\time_out_counter_reg[12]_i_1__0_n_1 ,\time_out_counter_reg[12]_i_1__0_n_2 ,\time_out_counter_reg[12]_i_1__0_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\time_out_counter_reg[12]_i_1__0_n_4 ,\time_out_counter_reg[12]_i_1__0_n_5 ,\time_out_counter_reg[12]_i_1__0_n_6 ,\time_out_counter_reg[12]_i_1__0_n_7 }), .S(time_out_counter_reg[15:12])); FDRE #( .INIT(1'b0)) \time_out_counter_reg[13] (.C(independent_clock_bufg), .CE(time_out_counter), .D(\time_out_counter_reg[12]_i_1__0_n_6 ), .Q(time_out_counter_reg[13]), .R(reset_time_out_reg_n_0)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[14] (.C(independent_clock_bufg), .CE(time_out_counter), .D(\time_out_counter_reg[12]_i_1__0_n_5 ), .Q(time_out_counter_reg[14]), .R(reset_time_out_reg_n_0)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[15] (.C(independent_clock_bufg), .CE(time_out_counter), .D(\time_out_counter_reg[12]_i_1__0_n_4 ), .Q(time_out_counter_reg[15]), .R(reset_time_out_reg_n_0)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[16] (.C(independent_clock_bufg), .CE(time_out_counter), .D(\time_out_counter_reg[16]_i_1__0_n_7 ), .Q(time_out_counter_reg[16]), .R(reset_time_out_reg_n_0)); CARRY4 \time_out_counter_reg[16]_i_1__0 (.CI(\time_out_counter_reg[12]_i_1__0_n_0 ), .CO({\NLW_time_out_counter_reg[16]_i_1__0_CO_UNCONNECTED [3:2],\time_out_counter_reg[16]_i_1__0_n_2 ,\time_out_counter_reg[16]_i_1__0_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\NLW_time_out_counter_reg[16]_i_1__0_O_UNCONNECTED [3],\time_out_counter_reg[16]_i_1__0_n_5 ,\time_out_counter_reg[16]_i_1__0_n_6 ,\time_out_counter_reg[16]_i_1__0_n_7 }), .S({1'b0,time_out_counter_reg[18:16]})); FDRE #( .INIT(1'b0)) \time_out_counter_reg[17] (.C(independent_clock_bufg), .CE(time_out_counter), .D(\time_out_counter_reg[16]_i_1__0_n_6 ), .Q(time_out_counter_reg[17]), .R(reset_time_out_reg_n_0)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[18] (.C(independent_clock_bufg), .CE(time_out_counter), .D(\time_out_counter_reg[16]_i_1__0_n_5 ), .Q(time_out_counter_reg[18]), .R(reset_time_out_reg_n_0)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[1] (.C(independent_clock_bufg), .CE(time_out_counter), .D(\time_out_counter_reg[0]_i_2__0_n_6 ), .Q(time_out_counter_reg[1]), .R(reset_time_out_reg_n_0)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[2] (.C(independent_clock_bufg), .CE(time_out_counter), .D(\time_out_counter_reg[0]_i_2__0_n_5 ), .Q(time_out_counter_reg[2]), .R(reset_time_out_reg_n_0)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[3] (.C(independent_clock_bufg), .CE(time_out_counter), .D(\time_out_counter_reg[0]_i_2__0_n_4 ), .Q(time_out_counter_reg[3]), .R(reset_time_out_reg_n_0)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[4] (.C(independent_clock_bufg), .CE(time_out_counter), .D(\time_out_counter_reg[4]_i_1__0_n_7 ), .Q(time_out_counter_reg[4]), .R(reset_time_out_reg_n_0)); CARRY4 \time_out_counter_reg[4]_i_1__0 (.CI(\time_out_counter_reg[0]_i_2__0_n_0 ), .CO({\time_out_counter_reg[4]_i_1__0_n_0 ,\time_out_counter_reg[4]_i_1__0_n_1 ,\time_out_counter_reg[4]_i_1__0_n_2 ,\time_out_counter_reg[4]_i_1__0_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\time_out_counter_reg[4]_i_1__0_n_4 ,\time_out_counter_reg[4]_i_1__0_n_5 ,\time_out_counter_reg[4]_i_1__0_n_6 ,\time_out_counter_reg[4]_i_1__0_n_7 }), .S(time_out_counter_reg[7:4])); FDRE #( .INIT(1'b0)) \time_out_counter_reg[5] (.C(independent_clock_bufg), .CE(time_out_counter), .D(\time_out_counter_reg[4]_i_1__0_n_6 ), .Q(time_out_counter_reg[5]), .R(reset_time_out_reg_n_0)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[6] (.C(independent_clock_bufg), .CE(time_out_counter), .D(\time_out_counter_reg[4]_i_1__0_n_5 ), .Q(time_out_counter_reg[6]), .R(reset_time_out_reg_n_0)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[7] (.C(independent_clock_bufg), .CE(time_out_counter), .D(\time_out_counter_reg[4]_i_1__0_n_4 ), .Q(time_out_counter_reg[7]), .R(reset_time_out_reg_n_0)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[8] (.C(independent_clock_bufg), .CE(time_out_counter), .D(\time_out_counter_reg[8]_i_1__0_n_7 ), .Q(time_out_counter_reg[8]), .R(reset_time_out_reg_n_0)); CARRY4 \time_out_counter_reg[8]_i_1__0 (.CI(\time_out_counter_reg[4]_i_1__0_n_0 ), .CO({\time_out_counter_reg[8]_i_1__0_n_0 ,\time_out_counter_reg[8]_i_1__0_n_1 ,\time_out_counter_reg[8]_i_1__0_n_2 ,\time_out_counter_reg[8]_i_1__0_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\time_out_counter_reg[8]_i_1__0_n_4 ,\time_out_counter_reg[8]_i_1__0_n_5 ,\time_out_counter_reg[8]_i_1__0_n_6 ,\time_out_counter_reg[8]_i_1__0_n_7 }), .S(time_out_counter_reg[11:8])); FDRE #( .INIT(1'b0)) \time_out_counter_reg[9] (.C(independent_clock_bufg), .CE(time_out_counter), .D(\time_out_counter_reg[8]_i_1__0_n_6 ), .Q(time_out_counter_reg[9]), .R(reset_time_out_reg_n_0)); LUT4 #( .INIT(16'hAB00)) time_out_wait_bypass_i_1__0 (.I0(time_out_wait_bypass_reg_n_0), .I1(rx_fsm_reset_done_int_s3), .I2(\wait_bypass_count[0]_i_4__0_n_0 ), .I3(run_phase_alignment_int_s3_reg_n_0), .O(time_out_wait_bypass_i_1__0_n_0)); FDRE #( .INIT(1'b0)) time_out_wait_bypass_reg (.C(userclk), .CE(1'b1), .D(time_out_wait_bypass_i_1__0_n_0), .Q(time_out_wait_bypass_reg_n_0), .R(1'b0)); FDRE #( .INIT(1'b0)) time_out_wait_bypass_s3_reg (.C(independent_clock_bufg), .CE(1'b1), .D(time_out_wait_bypass_s2), .Q(time_out_wait_bypass_s3), .R(1'b0)); CARRY4 time_tlock_max1_carry (.CI(1'b0), .CO({time_tlock_max1_carry_n_0,time_tlock_max1_carry_n_1,time_tlock_max1_carry_n_2,time_tlock_max1_carry_n_3}), .CYINIT(1'b0), .DI({time_tlock_max1_carry_i_1_n_0,time_tlock_max1_carry_i_2_n_0,time_tlock_max1_carry_i_3_n_0,time_tlock_max1_carry_i_4_n_0}), .O(NLW_time_tlock_max1_carry_O_UNCONNECTED[3:0]), .S({time_tlock_max1_carry_i_5_n_0,time_tlock_max1_carry_i_6_n_0,time_tlock_max1_carry_i_7_n_0,time_tlock_max1_carry_i_8_n_0})); CARRY4 time_tlock_max1_carry__0 (.CI(time_tlock_max1_carry_n_0), .CO({time_tlock_max1_carry__0_n_0,time_tlock_max1_carry__0_n_1,time_tlock_max1_carry__0_n_2,time_tlock_max1_carry__0_n_3}), .CYINIT(1'b0), .DI({time_out_counter_reg[15],time_tlock_max1_carry__0_i_1_n_0,1'b0,time_tlock_max1_carry__0_i_2_n_0}), .O(NLW_time_tlock_max1_carry__0_O_UNCONNECTED[3:0]), .S({time_tlock_max1_carry__0_i_3_n_0,time_tlock_max1_carry__0_i_4_n_0,time_tlock_max1_carry__0_i_5_n_0,time_tlock_max1_carry__0_i_6_n_0})); LUT2 #( .INIT(4'hE)) time_tlock_max1_carry__0_i_1 (.I0(time_out_counter_reg[13]), .I1(time_out_counter_reg[12]), .O(time_tlock_max1_carry__0_i_1_n_0)); LUT2 #( .INIT(4'h8)) time_tlock_max1_carry__0_i_2 (.I0(time_out_counter_reg[8]), .I1(time_out_counter_reg[9]), .O(time_tlock_max1_carry__0_i_2_n_0)); LUT2 #( .INIT(4'h2)) time_tlock_max1_carry__0_i_3 (.I0(time_out_counter_reg[14]), .I1(time_out_counter_reg[15]), .O(time_tlock_max1_carry__0_i_3_n_0)); LUT2 #( .INIT(4'h1)) time_tlock_max1_carry__0_i_4 (.I0(time_out_counter_reg[12]), .I1(time_out_counter_reg[13]), .O(time_tlock_max1_carry__0_i_4_n_0)); LUT2 #( .INIT(4'h8)) time_tlock_max1_carry__0_i_5 (.I0(time_out_counter_reg[10]), .I1(time_out_counter_reg[11]), .O(time_tlock_max1_carry__0_i_5_n_0)); LUT2 #( .INIT(4'h2)) time_tlock_max1_carry__0_i_6 (.I0(time_out_counter_reg[9]), .I1(time_out_counter_reg[8]), .O(time_tlock_max1_carry__0_i_6_n_0)); CARRY4 time_tlock_max1_carry__1 (.CI(time_tlock_max1_carry__0_n_0), .CO({NLW_time_tlock_max1_carry__1_CO_UNCONNECTED[3:2],time_tlock_max1,time_tlock_max1_carry__1_n_3}), .CYINIT(1'b0), .DI({1'b0,1'b0,time_out_counter_reg[18],time_tlock_max1_carry__1_i_1_n_0}), .O(NLW_time_tlock_max1_carry__1_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,time_tlock_max1_carry__1_i_2_n_0,time_tlock_max1_carry__1_i_3_n_0})); LUT2 #( .INIT(4'hE)) time_tlock_max1_carry__1_i_1 (.I0(time_out_counter_reg[16]), .I1(time_out_counter_reg[17]), .O(time_tlock_max1_carry__1_i_1_n_0)); LUT1 #( .INIT(2'h1)) time_tlock_max1_carry__1_i_2 (.I0(time_out_counter_reg[18]), .O(time_tlock_max1_carry__1_i_2_n_0)); LUT2 #( .INIT(4'h1)) time_tlock_max1_carry__1_i_3 (.I0(time_out_counter_reg[17]), .I1(time_out_counter_reg[16]), .O(time_tlock_max1_carry__1_i_3_n_0)); LUT2 #( .INIT(4'hE)) time_tlock_max1_carry_i_1 (.I0(time_out_counter_reg[7]), .I1(time_out_counter_reg[6]), .O(time_tlock_max1_carry_i_1_n_0)); LUT2 #( .INIT(4'h8)) time_tlock_max1_carry_i_2 (.I0(time_out_counter_reg[5]), .I1(time_out_counter_reg[4]), .O(time_tlock_max1_carry_i_2_n_0)); LUT2 #( .INIT(4'hE)) time_tlock_max1_carry_i_3 (.I0(time_out_counter_reg[2]), .I1(time_out_counter_reg[3]), .O(time_tlock_max1_carry_i_3_n_0)); LUT2 #( .INIT(4'hE)) time_tlock_max1_carry_i_4 (.I0(time_out_counter_reg[0]), .I1(time_out_counter_reg[1]), .O(time_tlock_max1_carry_i_4_n_0)); LUT2 #( .INIT(4'h1)) time_tlock_max1_carry_i_5 (.I0(time_out_counter_reg[6]), .I1(time_out_counter_reg[7]), .O(time_tlock_max1_carry_i_5_n_0)); LUT2 #( .INIT(4'h2)) time_tlock_max1_carry_i_6 (.I0(time_out_counter_reg[5]), .I1(time_out_counter_reg[4]), .O(time_tlock_max1_carry_i_6_n_0)); LUT2 #( .INIT(4'h1)) time_tlock_max1_carry_i_7 (.I0(time_out_counter_reg[3]), .I1(time_out_counter_reg[2]), .O(time_tlock_max1_carry_i_7_n_0)); LUT2 #( .INIT(4'h1)) time_tlock_max1_carry_i_8 (.I0(time_out_counter_reg[1]), .I1(time_out_counter_reg[0]), .O(time_tlock_max1_carry_i_8_n_0)); (* SOFT_HLUTNM = "soft_lutpair54" *) LUT3 #( .INIT(8'hF8)) time_tlock_max_i_1 (.I0(check_tlock_max_reg_n_0), .I1(time_tlock_max1), .I2(time_tlock_max), .O(time_tlock_max_i_1_n_0)); FDRE #( .INIT(1'b0)) time_tlock_max_reg (.C(independent_clock_bufg), .CE(1'b1), .D(time_tlock_max_i_1_n_0), .Q(time_tlock_max), .R(reset_time_out_reg_n_0)); LUT1 #( .INIT(2'h1)) \wait_bypass_count[0]_i_1__0 (.I0(run_phase_alignment_int_s3_reg_n_0), .O(\wait_bypass_count[0]_i_1__0_n_0 )); LUT2 #( .INIT(4'h2)) \wait_bypass_count[0]_i_2__0 (.I0(\wait_bypass_count[0]_i_4__0_n_0 ), .I1(rx_fsm_reset_done_int_s3), .O(\wait_bypass_count[0]_i_2__0_n_0 )); LUT5 #( .INIT(32'hBFFFFFFF)) \wait_bypass_count[0]_i_4__0 (.I0(\wait_bypass_count[0]_i_6__0_n_0 ), .I1(wait_bypass_count_reg[1]), .I2(wait_bypass_count_reg[8]), .I3(wait_bypass_count_reg[0]), .I4(\wait_bypass_count[0]_i_7__0_n_0 ), .O(\wait_bypass_count[0]_i_4__0_n_0 )); LUT1 #( .INIT(2'h1)) \wait_bypass_count[0]_i_5__0 (.I0(wait_bypass_count_reg[0]), .O(\wait_bypass_count[0]_i_5__0_n_0 )); LUT4 #( .INIT(16'hEFFF)) \wait_bypass_count[0]_i_6__0 (.I0(wait_bypass_count_reg[3]), .I1(wait_bypass_count_reg[5]), .I2(wait_bypass_count_reg[9]), .I3(wait_bypass_count_reg[7]), .O(\wait_bypass_count[0]_i_6__0_n_0 )); LUT6 #( .INIT(64'h0000000000000008)) \wait_bypass_count[0]_i_7__0 (.I0(wait_bypass_count_reg[2]), .I1(wait_bypass_count_reg[12]), .I2(wait_bypass_count_reg[4]), .I3(wait_bypass_count_reg[10]), .I4(wait_bypass_count_reg[6]), .I5(wait_bypass_count_reg[11]), .O(\wait_bypass_count[0]_i_7__0_n_0 )); FDRE \wait_bypass_count_reg[0] (.C(userclk), .CE(\wait_bypass_count[0]_i_2__0_n_0 ), .D(\wait_bypass_count_reg[0]_i_3__0_n_7 ), .Q(wait_bypass_count_reg[0]), .R(\wait_bypass_count[0]_i_1__0_n_0 )); CARRY4 \wait_bypass_count_reg[0]_i_3__0 (.CI(1'b0), .CO({\wait_bypass_count_reg[0]_i_3__0_n_0 ,\wait_bypass_count_reg[0]_i_3__0_n_1 ,\wait_bypass_count_reg[0]_i_3__0_n_2 ,\wait_bypass_count_reg[0]_i_3__0_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b1}), .O({\wait_bypass_count_reg[0]_i_3__0_n_4 ,\wait_bypass_count_reg[0]_i_3__0_n_5 ,\wait_bypass_count_reg[0]_i_3__0_n_6 ,\wait_bypass_count_reg[0]_i_3__0_n_7 }), .S({wait_bypass_count_reg[3:1],\wait_bypass_count[0]_i_5__0_n_0 })); FDRE \wait_bypass_count_reg[10] (.C(userclk), .CE(\wait_bypass_count[0]_i_2__0_n_0 ), .D(\wait_bypass_count_reg[8]_i_1__0_n_5 ), .Q(wait_bypass_count_reg[10]), .R(\wait_bypass_count[0]_i_1__0_n_0 )); FDRE \wait_bypass_count_reg[11] (.C(userclk), .CE(\wait_bypass_count[0]_i_2__0_n_0 ), .D(\wait_bypass_count_reg[8]_i_1__0_n_4 ), .Q(wait_bypass_count_reg[11]), .R(\wait_bypass_count[0]_i_1__0_n_0 )); FDRE \wait_bypass_count_reg[12] (.C(userclk), .CE(\wait_bypass_count[0]_i_2__0_n_0 ), .D(\wait_bypass_count_reg[12]_i_1__0_n_7 ), .Q(wait_bypass_count_reg[12]), .R(\wait_bypass_count[0]_i_1__0_n_0 )); CARRY4 \wait_bypass_count_reg[12]_i_1__0 (.CI(\wait_bypass_count_reg[8]_i_1__0_n_0 ), .CO(\NLW_wait_bypass_count_reg[12]_i_1__0_CO_UNCONNECTED [3:0]), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\NLW_wait_bypass_count_reg[12]_i_1__0_O_UNCONNECTED [3:1],\wait_bypass_count_reg[12]_i_1__0_n_7 }), .S({1'b0,1'b0,1'b0,wait_bypass_count_reg[12]})); FDRE \wait_bypass_count_reg[1] (.C(userclk), .CE(\wait_bypass_count[0]_i_2__0_n_0 ), .D(\wait_bypass_count_reg[0]_i_3__0_n_6 ), .Q(wait_bypass_count_reg[1]), .R(\wait_bypass_count[0]_i_1__0_n_0 )); FDRE \wait_bypass_count_reg[2] (.C(userclk), .CE(\wait_bypass_count[0]_i_2__0_n_0 ), .D(\wait_bypass_count_reg[0]_i_3__0_n_5 ), .Q(wait_bypass_count_reg[2]), .R(\wait_bypass_count[0]_i_1__0_n_0 )); FDRE \wait_bypass_count_reg[3] (.C(userclk), .CE(\wait_bypass_count[0]_i_2__0_n_0 ), .D(\wait_bypass_count_reg[0]_i_3__0_n_4 ), .Q(wait_bypass_count_reg[3]), .R(\wait_bypass_count[0]_i_1__0_n_0 )); FDRE \wait_bypass_count_reg[4] (.C(userclk), .CE(\wait_bypass_count[0]_i_2__0_n_0 ), .D(\wait_bypass_count_reg[4]_i_1__0_n_7 ), .Q(wait_bypass_count_reg[4]), .R(\wait_bypass_count[0]_i_1__0_n_0 )); CARRY4 \wait_bypass_count_reg[4]_i_1__0 (.CI(\wait_bypass_count_reg[0]_i_3__0_n_0 ), .CO({\wait_bypass_count_reg[4]_i_1__0_n_0 ,\wait_bypass_count_reg[4]_i_1__0_n_1 ,\wait_bypass_count_reg[4]_i_1__0_n_2 ,\wait_bypass_count_reg[4]_i_1__0_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\wait_bypass_count_reg[4]_i_1__0_n_4 ,\wait_bypass_count_reg[4]_i_1__0_n_5 ,\wait_bypass_count_reg[4]_i_1__0_n_6 ,\wait_bypass_count_reg[4]_i_1__0_n_7 }), .S(wait_bypass_count_reg[7:4])); FDRE \wait_bypass_count_reg[5] (.C(userclk), .CE(\wait_bypass_count[0]_i_2__0_n_0 ), .D(\wait_bypass_count_reg[4]_i_1__0_n_6 ), .Q(wait_bypass_count_reg[5]), .R(\wait_bypass_count[0]_i_1__0_n_0 )); FDRE \wait_bypass_count_reg[6] (.C(userclk), .CE(\wait_bypass_count[0]_i_2__0_n_0 ), .D(\wait_bypass_count_reg[4]_i_1__0_n_5 ), .Q(wait_bypass_count_reg[6]), .R(\wait_bypass_count[0]_i_1__0_n_0 )); FDRE \wait_bypass_count_reg[7] (.C(userclk), .CE(\wait_bypass_count[0]_i_2__0_n_0 ), .D(\wait_bypass_count_reg[4]_i_1__0_n_4 ), .Q(wait_bypass_count_reg[7]), .R(\wait_bypass_count[0]_i_1__0_n_0 )); FDRE \wait_bypass_count_reg[8] (.C(userclk), .CE(\wait_bypass_count[0]_i_2__0_n_0 ), .D(\wait_bypass_count_reg[8]_i_1__0_n_7 ), .Q(wait_bypass_count_reg[8]), .R(\wait_bypass_count[0]_i_1__0_n_0 )); CARRY4 \wait_bypass_count_reg[8]_i_1__0 (.CI(\wait_bypass_count_reg[4]_i_1__0_n_0 ), .CO({\wait_bypass_count_reg[8]_i_1__0_n_0 ,\wait_bypass_count_reg[8]_i_1__0_n_1 ,\wait_bypass_count_reg[8]_i_1__0_n_2 ,\wait_bypass_count_reg[8]_i_1__0_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\wait_bypass_count_reg[8]_i_1__0_n_4 ,\wait_bypass_count_reg[8]_i_1__0_n_5 ,\wait_bypass_count_reg[8]_i_1__0_n_6 ,\wait_bypass_count_reg[8]_i_1__0_n_7 }), .S(wait_bypass_count_reg[11:8])); FDRE \wait_bypass_count_reg[9] (.C(userclk), .CE(\wait_bypass_count[0]_i_2__0_n_0 ), .D(\wait_bypass_count_reg[8]_i_1__0_n_6 ), .Q(wait_bypass_count_reg[9]), .R(\wait_bypass_count[0]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair57" *) LUT1 #( .INIT(2'h1)) \wait_time_cnt[0]_i_1__0 (.I0(wait_time_cnt_reg__0[0]), .O(wait_time_cnt0__0)); (* SOFT_HLUTNM = "soft_lutpair57" *) LUT2 #( .INIT(4'h9)) \wait_time_cnt[1]_i_1__0 (.I0(wait_time_cnt_reg__0[0]), .I1(wait_time_cnt_reg__0[1]), .O(\wait_time_cnt[1]_i_1__0_n_0 )); LUT3 #( .INIT(8'hE1)) \wait_time_cnt[2]_i_1__0 (.I0(wait_time_cnt_reg__0[1]), .I1(wait_time_cnt_reg__0[0]), .I2(wait_time_cnt_reg__0[2]), .O(\wait_time_cnt[2]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair48" *) LUT4 #( .INIT(16'hFE01)) \wait_time_cnt[3]_i_1__0 (.I0(wait_time_cnt_reg__0[2]), .I1(wait_time_cnt_reg__0[0]), .I2(wait_time_cnt_reg__0[1]), .I3(wait_time_cnt_reg__0[3]), .O(\wait_time_cnt[3]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair48" *) LUT5 #( .INIT(32'hFFFE0001)) \wait_time_cnt[4]_i_1__0 (.I0(wait_time_cnt_reg__0[3]), .I1(wait_time_cnt_reg__0[1]), .I2(wait_time_cnt_reg__0[0]), .I3(wait_time_cnt_reg__0[2]), .I4(wait_time_cnt_reg__0[4]), .O(\wait_time_cnt[4]_i_1__0_n_0 )); LUT6 #( .INIT(64'hFFFFFFFE00000001)) \wait_time_cnt[5]_i_1__0 (.I0(wait_time_cnt_reg__0[4]), .I1(wait_time_cnt_reg__0[2]), .I2(wait_time_cnt_reg__0[0]), .I3(wait_time_cnt_reg__0[1]), .I4(wait_time_cnt_reg__0[3]), .I5(wait_time_cnt_reg__0[5]), .O(\wait_time_cnt[5]_i_1__0_n_0 )); LUT3 #( .INIT(8'h02)) \wait_time_cnt[6]_i_1 (.I0(rx_state[0]), .I1(rx_state[1]), .I2(rx_state[3]), .O(\wait_time_cnt[6]_i_1_n_0 )); LUT2 #( .INIT(4'hE)) \wait_time_cnt[6]_i_2__0 (.I0(\wait_time_cnt[6]_i_4__0_n_0 ), .I1(wait_time_cnt_reg__0[6]), .O(\wait_time_cnt[6]_i_2__0_n_0 )); LUT2 #( .INIT(4'h9)) \wait_time_cnt[6]_i_3__0 (.I0(\wait_time_cnt[6]_i_4__0_n_0 ), .I1(wait_time_cnt_reg__0[6]), .O(\wait_time_cnt[6]_i_3__0_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \wait_time_cnt[6]_i_4__0 (.I0(wait_time_cnt_reg__0[4]), .I1(wait_time_cnt_reg__0[2]), .I2(wait_time_cnt_reg__0[0]), .I3(wait_time_cnt_reg__0[1]), .I4(wait_time_cnt_reg__0[3]), .I5(wait_time_cnt_reg__0[5]), .O(\wait_time_cnt[6]_i_4__0_n_0 )); FDRE \wait_time_cnt_reg[0] (.C(independent_clock_bufg), .CE(\wait_time_cnt[6]_i_2__0_n_0 ), .D(wait_time_cnt0__0), .Q(wait_time_cnt_reg__0[0]), .R(\wait_time_cnt[6]_i_1_n_0 )); FDRE \wait_time_cnt_reg[1] (.C(independent_clock_bufg), .CE(\wait_time_cnt[6]_i_2__0_n_0 ), .D(\wait_time_cnt[1]_i_1__0_n_0 ), .Q(wait_time_cnt_reg__0[1]), .R(\wait_time_cnt[6]_i_1_n_0 )); FDSE \wait_time_cnt_reg[2] (.C(independent_clock_bufg), .CE(\wait_time_cnt[6]_i_2__0_n_0 ), .D(\wait_time_cnt[2]_i_1__0_n_0 ), .Q(wait_time_cnt_reg__0[2]), .S(\wait_time_cnt[6]_i_1_n_0 )); FDRE \wait_time_cnt_reg[3] (.C(independent_clock_bufg), .CE(\wait_time_cnt[6]_i_2__0_n_0 ), .D(\wait_time_cnt[3]_i_1__0_n_0 ), .Q(wait_time_cnt_reg__0[3]), .R(\wait_time_cnt[6]_i_1_n_0 )); FDRE \wait_time_cnt_reg[4] (.C(independent_clock_bufg), .CE(\wait_time_cnt[6]_i_2__0_n_0 ), .D(\wait_time_cnt[4]_i_1__0_n_0 ), .Q(wait_time_cnt_reg__0[4]), .R(\wait_time_cnt[6]_i_1_n_0 )); FDSE \wait_time_cnt_reg[5] (.C(independent_clock_bufg), .CE(\wait_time_cnt[6]_i_2__0_n_0 ), .D(\wait_time_cnt[5]_i_1__0_n_0 ), .Q(wait_time_cnt_reg__0[5]), .S(\wait_time_cnt[6]_i_1_n_0 )); FDSE \wait_time_cnt_reg[6] (.C(independent_clock_bufg), .CE(\wait_time_cnt[6]_i_2__0_n_0 ), .D(\wait_time_cnt[6]_i_3__0_n_0 ), .Q(wait_time_cnt_reg__0[6]), .S(\wait_time_cnt[6]_i_1_n_0 )); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_TX_STARTUP_FSM (mmcm_reset, gt0_cpllreset_t, data_in, gt0_txuserrdy_t, gt0_gttxreset_in0_out, independent_clock_bufg, userclk, pma_reset, data_sync_reg1, gt0_cpllrefclklost_i, data_sync_reg1_0, mmcm_locked, cplllock); output mmcm_reset; output gt0_cpllreset_t; output data_in; output gt0_txuserrdy_t; output gt0_gttxreset_in0_out; input independent_clock_bufg; input userclk; input pma_reset; input data_sync_reg1; input gt0_cpllrefclklost_i; input data_sync_reg1_0; input mmcm_locked; input cplllock; wire CPLL_RESET_i_1_n_0; wire CPLL_RESET_i_2_n_0; wire \FSM_sequential_tx_state[0]_i_1_n_0 ; wire \FSM_sequential_tx_state[0]_i_2_n_0 ; wire \FSM_sequential_tx_state[0]_i_3_n_0 ; wire \FSM_sequential_tx_state[1]_i_1_n_0 ; wire \FSM_sequential_tx_state[2]_i_1_n_0 ; wire \FSM_sequential_tx_state[2]_i_2_n_0 ; wire \FSM_sequential_tx_state[3]_i_2_n_0 ; wire \FSM_sequential_tx_state[3]_i_3_n_0 ; wire \FSM_sequential_tx_state[3]_i_4_n_0 ; wire \FSM_sequential_tx_state[3]_i_6_n_0 ; wire \FSM_sequential_tx_state[3]_i_7_n_0 ; wire \FSM_sequential_tx_state[3]_i_8_n_0 ; wire GTTXRESET; wire MMCM_RESET_i_1_n_0; wire TXUSERRDY_i_1_n_0; wire clear; wire cplllock; wire data_in; wire data_out; wire data_sync_reg1; wire data_sync_reg1_0; wire gt0_cpllrefclklost_i; wire gt0_cpllreset_t; wire gt0_gttxreset_in0_out; wire gt0_txuserrdy_t; wire gttxreset_i_i_1_n_0; wire independent_clock_bufg; wire \init_wait_count[0]_i_1_n_0 ; wire \init_wait_count[6]_i_1_n_0 ; wire \init_wait_count[6]_i_3_n_0 ; wire [6:0]init_wait_count_reg__0; wire init_wait_done_i_1_n_0; wire init_wait_done_reg_n_0; wire \mmcm_lock_count[2]_i_1_n_0 ; wire \mmcm_lock_count[3]_i_1_n_0 ; wire \mmcm_lock_count[4]_i_1_n_0 ; wire \mmcm_lock_count[5]_i_1_n_0 ; wire \mmcm_lock_count[6]_i_1_n_0 ; wire \mmcm_lock_count[7]_i_2_n_0 ; wire \mmcm_lock_count[7]_i_3_n_0 ; wire \mmcm_lock_count[7]_i_4_n_0 ; wire [7:0]mmcm_lock_count_reg__0; wire mmcm_lock_reclocked; wire mmcm_locked; wire mmcm_reset; wire [6:1]p_0_in__0; wire [1:0]p_0_in__1; wire pll_reset_asserted_i_1_n_0; wire pll_reset_asserted_i_2_n_0; wire pll_reset_asserted_reg_n_0; wire pma_reset; wire refclk_stable_count; wire \refclk_stable_count[0]_i_3_n_0 ; wire \refclk_stable_count[0]_i_4_n_0 ; wire \refclk_stable_count[0]_i_5_n_0 ; wire \refclk_stable_count[0]_i_6_n_0 ; wire \refclk_stable_count[0]_i_7_n_0 ; wire \refclk_stable_count[0]_i_8_n_0 ; wire \refclk_stable_count[0]_i_9_n_0 ; wire [31:0]refclk_stable_count_reg; wire \refclk_stable_count_reg[0]_i_2_n_0 ; wire \refclk_stable_count_reg[0]_i_2_n_1 ; wire \refclk_stable_count_reg[0]_i_2_n_2 ; wire \refclk_stable_count_reg[0]_i_2_n_3 ; wire \refclk_stable_count_reg[0]_i_2_n_4 ; wire \refclk_stable_count_reg[0]_i_2_n_5 ; wire \refclk_stable_count_reg[0]_i_2_n_6 ; wire \refclk_stable_count_reg[0]_i_2_n_7 ; wire \refclk_stable_count_reg[12]_i_1_n_0 ; wire \refclk_stable_count_reg[12]_i_1_n_1 ; wire \refclk_stable_count_reg[12]_i_1_n_2 ; wire \refclk_stable_count_reg[12]_i_1_n_3 ; wire \refclk_stable_count_reg[12]_i_1_n_4 ; wire \refclk_stable_count_reg[12]_i_1_n_5 ; wire \refclk_stable_count_reg[12]_i_1_n_6 ; wire \refclk_stable_count_reg[12]_i_1_n_7 ; wire \refclk_stable_count_reg[16]_i_1_n_0 ; wire \refclk_stable_count_reg[16]_i_1_n_1 ; wire \refclk_stable_count_reg[16]_i_1_n_2 ; wire \refclk_stable_count_reg[16]_i_1_n_3 ; wire \refclk_stable_count_reg[16]_i_1_n_4 ; wire \refclk_stable_count_reg[16]_i_1_n_5 ; wire \refclk_stable_count_reg[16]_i_1_n_6 ; wire \refclk_stable_count_reg[16]_i_1_n_7 ; wire \refclk_stable_count_reg[20]_i_1_n_0 ; wire \refclk_stable_count_reg[20]_i_1_n_1 ; wire \refclk_stable_count_reg[20]_i_1_n_2 ; wire \refclk_stable_count_reg[20]_i_1_n_3 ; wire \refclk_stable_count_reg[20]_i_1_n_4 ; wire \refclk_stable_count_reg[20]_i_1_n_5 ; wire \refclk_stable_count_reg[20]_i_1_n_6 ; wire \refclk_stable_count_reg[20]_i_1_n_7 ; wire \refclk_stable_count_reg[24]_i_1_n_0 ; wire \refclk_stable_count_reg[24]_i_1_n_1 ; wire \refclk_stable_count_reg[24]_i_1_n_2 ; wire \refclk_stable_count_reg[24]_i_1_n_3 ; wire \refclk_stable_count_reg[24]_i_1_n_4 ; wire \refclk_stable_count_reg[24]_i_1_n_5 ; wire \refclk_stable_count_reg[24]_i_1_n_6 ; wire \refclk_stable_count_reg[24]_i_1_n_7 ; wire \refclk_stable_count_reg[28]_i_1_n_1 ; wire \refclk_stable_count_reg[28]_i_1_n_2 ; wire \refclk_stable_count_reg[28]_i_1_n_3 ; wire \refclk_stable_count_reg[28]_i_1_n_4 ; wire \refclk_stable_count_reg[28]_i_1_n_5 ; wire \refclk_stable_count_reg[28]_i_1_n_6 ; wire \refclk_stable_count_reg[28]_i_1_n_7 ; wire \refclk_stable_count_reg[4]_i_1_n_0 ; wire \refclk_stable_count_reg[4]_i_1_n_1 ; wire \refclk_stable_count_reg[4]_i_1_n_2 ; wire \refclk_stable_count_reg[4]_i_1_n_3 ; wire \refclk_stable_count_reg[4]_i_1_n_4 ; wire \refclk_stable_count_reg[4]_i_1_n_5 ; wire \refclk_stable_count_reg[4]_i_1_n_6 ; wire \refclk_stable_count_reg[4]_i_1_n_7 ; wire \refclk_stable_count_reg[8]_i_1_n_0 ; wire \refclk_stable_count_reg[8]_i_1_n_1 ; wire \refclk_stable_count_reg[8]_i_1_n_2 ; wire \refclk_stable_count_reg[8]_i_1_n_3 ; wire \refclk_stable_count_reg[8]_i_1_n_4 ; wire \refclk_stable_count_reg[8]_i_1_n_5 ; wire \refclk_stable_count_reg[8]_i_1_n_6 ; wire \refclk_stable_count_reg[8]_i_1_n_7 ; wire refclk_stable_i_1_n_0; wire refclk_stable_i_2_n_0; wire refclk_stable_i_3_n_0; wire refclk_stable_i_4_n_0; wire refclk_stable_i_5_n_0; wire refclk_stable_i_6_n_0; wire refclk_stable_reg_n_0; wire reset_time_out; wire reset_time_out_i_2__0_n_0; wire run_phase_alignment_int_i_1_n_0; wire run_phase_alignment_int_reg_n_0; wire run_phase_alignment_int_s3; wire sel; wire sync_cplllock_n_0; wire sync_cplllock_n_1; wire sync_mmcm_lock_reclocked_n_0; wire sync_mmcm_lock_reclocked_n_1; wire time_out_2ms_i_1__0_n_0; wire time_out_2ms_i_2_n_0; wire time_out_2ms_reg_n_0; wire time_out_500us_i_1_n_0; wire time_out_500us_i_2_n_0; wire time_out_500us_reg_n_0; wire time_out_counter; wire \time_out_counter[0]_i_3__0_n_0 ; wire \time_out_counter[0]_i_4__0_n_0 ; wire \time_out_counter[0]_i_5__0_n_0 ; wire \time_out_counter[0]_i_6_n_0 ; wire \time_out_counter[0]_i_7_n_0 ; wire \time_out_counter[0]_i_8_n_0 ; wire [18:0]time_out_counter_reg; wire \time_out_counter_reg[0]_i_2_n_0 ; wire \time_out_counter_reg[0]_i_2_n_1 ; wire \time_out_counter_reg[0]_i_2_n_2 ; wire \time_out_counter_reg[0]_i_2_n_3 ; wire \time_out_counter_reg[0]_i_2_n_4 ; wire \time_out_counter_reg[0]_i_2_n_5 ; wire \time_out_counter_reg[0]_i_2_n_6 ; wire \time_out_counter_reg[0]_i_2_n_7 ; wire \time_out_counter_reg[12]_i_1_n_0 ; wire \time_out_counter_reg[12]_i_1_n_1 ; wire \time_out_counter_reg[12]_i_1_n_2 ; wire \time_out_counter_reg[12]_i_1_n_3 ; wire \time_out_counter_reg[12]_i_1_n_4 ; wire \time_out_counter_reg[12]_i_1_n_5 ; wire \time_out_counter_reg[12]_i_1_n_6 ; wire \time_out_counter_reg[12]_i_1_n_7 ; wire \time_out_counter_reg[16]_i_1_n_2 ; wire \time_out_counter_reg[16]_i_1_n_3 ; wire \time_out_counter_reg[16]_i_1_n_5 ; wire \time_out_counter_reg[16]_i_1_n_6 ; wire \time_out_counter_reg[16]_i_1_n_7 ; wire \time_out_counter_reg[4]_i_1_n_0 ; wire \time_out_counter_reg[4]_i_1_n_1 ; wire \time_out_counter_reg[4]_i_1_n_2 ; wire \time_out_counter_reg[4]_i_1_n_3 ; wire \time_out_counter_reg[4]_i_1_n_4 ; wire \time_out_counter_reg[4]_i_1_n_5 ; wire \time_out_counter_reg[4]_i_1_n_6 ; wire \time_out_counter_reg[4]_i_1_n_7 ; wire \time_out_counter_reg[8]_i_1_n_0 ; wire \time_out_counter_reg[8]_i_1_n_1 ; wire \time_out_counter_reg[8]_i_1_n_2 ; wire \time_out_counter_reg[8]_i_1_n_3 ; wire \time_out_counter_reg[8]_i_1_n_4 ; wire \time_out_counter_reg[8]_i_1_n_5 ; wire \time_out_counter_reg[8]_i_1_n_6 ; wire \time_out_counter_reg[8]_i_1_n_7 ; wire time_out_wait_bypass_i_1_n_0; wire time_out_wait_bypass_reg_n_0; wire time_out_wait_bypass_s2; wire time_out_wait_bypass_s3; wire time_tlock_max_i_1__0_n_0; wire time_tlock_max_i_2_n_0; wire time_tlock_max_i_3_n_0; wire time_tlock_max_reg_n_0; wire tx_fsm_reset_done_int_i_1_n_0; wire tx_fsm_reset_done_int_s2; wire tx_fsm_reset_done_int_s3; wire [3:0]tx_state; wire txresetdone_s2; wire txresetdone_s3; wire userclk; wire \wait_bypass_count[0]_i_2_n_0 ; wire \wait_bypass_count[0]_i_4_n_0 ; wire \wait_bypass_count[0]_i_5_n_0 ; wire \wait_bypass_count[0]_i_6_n_0 ; wire \wait_bypass_count[0]_i_7_n_0 ; wire \wait_bypass_count[0]_i_8_n_0 ; wire [16:0]wait_bypass_count_reg; wire \wait_bypass_count_reg[0]_i_3_n_0 ; wire \wait_bypass_count_reg[0]_i_3_n_1 ; wire \wait_bypass_count_reg[0]_i_3_n_2 ; wire \wait_bypass_count_reg[0]_i_3_n_3 ; wire \wait_bypass_count_reg[0]_i_3_n_4 ; wire \wait_bypass_count_reg[0]_i_3_n_5 ; wire \wait_bypass_count_reg[0]_i_3_n_6 ; wire \wait_bypass_count_reg[0]_i_3_n_7 ; wire \wait_bypass_count_reg[12]_i_1_n_0 ; wire \wait_bypass_count_reg[12]_i_1_n_1 ; wire \wait_bypass_count_reg[12]_i_1_n_2 ; wire \wait_bypass_count_reg[12]_i_1_n_3 ; wire \wait_bypass_count_reg[12]_i_1_n_4 ; wire \wait_bypass_count_reg[12]_i_1_n_5 ; wire \wait_bypass_count_reg[12]_i_1_n_6 ; wire \wait_bypass_count_reg[12]_i_1_n_7 ; wire \wait_bypass_count_reg[16]_i_1_n_7 ; wire \wait_bypass_count_reg[4]_i_1_n_0 ; wire \wait_bypass_count_reg[4]_i_1_n_1 ; wire \wait_bypass_count_reg[4]_i_1_n_2 ; wire \wait_bypass_count_reg[4]_i_1_n_3 ; wire \wait_bypass_count_reg[4]_i_1_n_4 ; wire \wait_bypass_count_reg[4]_i_1_n_5 ; wire \wait_bypass_count_reg[4]_i_1_n_6 ; wire \wait_bypass_count_reg[4]_i_1_n_7 ; wire \wait_bypass_count_reg[8]_i_1_n_0 ; wire \wait_bypass_count_reg[8]_i_1_n_1 ; wire \wait_bypass_count_reg[8]_i_1_n_2 ; wire \wait_bypass_count_reg[8]_i_1_n_3 ; wire \wait_bypass_count_reg[8]_i_1_n_4 ; wire \wait_bypass_count_reg[8]_i_1_n_5 ; wire \wait_bypass_count_reg[8]_i_1_n_6 ; wire \wait_bypass_count_reg[8]_i_1_n_7 ; wire [0:0]wait_time_cnt0; wire wait_time_cnt0_0; wire \wait_time_cnt[1]_i_1_n_0 ; wire \wait_time_cnt[2]_i_1_n_0 ; wire \wait_time_cnt[3]_i_1_n_0 ; wire \wait_time_cnt[4]_i_1_n_0 ; wire \wait_time_cnt[5]_i_1_n_0 ; wire \wait_time_cnt[6]_i_3_n_0 ; wire \wait_time_cnt[6]_i_4_n_0 ; wire [6:0]wait_time_cnt_reg__0; wire [3:3]\NLW_refclk_stable_count_reg[28]_i_1_CO_UNCONNECTED ; wire [3:2]\NLW_time_out_counter_reg[16]_i_1_CO_UNCONNECTED ; wire [3:3]\NLW_time_out_counter_reg[16]_i_1_O_UNCONNECTED ; wire [3:0]\NLW_wait_bypass_count_reg[16]_i_1_CO_UNCONNECTED ; wire [3:1]\NLW_wait_bypass_count_reg[16]_i_1_O_UNCONNECTED ; LUT6 #( .INIT(64'hFFFFFF1F0000001F)) CPLL_RESET_i_1 (.I0(pll_reset_asserted_reg_n_0), .I1(gt0_cpllrefclklost_i), .I2(refclk_stable_reg_n_0), .I3(CPLL_RESET_i_2_n_0), .I4(\FSM_sequential_tx_state[0]_i_3_n_0 ), .I5(gt0_cpllreset_t), .O(CPLL_RESET_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair65" *) LUT2 #( .INIT(4'hE)) CPLL_RESET_i_2 (.I0(tx_state[1]), .I1(tx_state[2]), .O(CPLL_RESET_i_2_n_0)); FDRE #( .INIT(1'b0)) CPLL_RESET_reg (.C(independent_clock_bufg), .CE(1'b1), .D(CPLL_RESET_i_1_n_0), .Q(gt0_cpllreset_t), .R(pma_reset)); LUT6 #( .INIT(64'hF3FFF3F0F5F0F5F0)) \FSM_sequential_tx_state[0]_i_1 (.I0(\FSM_sequential_tx_state[2]_i_2_n_0 ), .I1(\FSM_sequential_tx_state[0]_i_2_n_0 ), .I2(\FSM_sequential_tx_state[0]_i_3_n_0 ), .I3(tx_state[2]), .I4(time_out_2ms_reg_n_0), .I5(tx_state[1]), .O(\FSM_sequential_tx_state[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair62" *) LUT2 #( .INIT(4'hB)) \FSM_sequential_tx_state[0]_i_2 (.I0(reset_time_out), .I1(time_out_500us_reg_n_0), .O(\FSM_sequential_tx_state[0]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair66" *) LUT2 #( .INIT(4'hB)) \FSM_sequential_tx_state[0]_i_3 (.I0(tx_state[3]), .I1(tx_state[0]), .O(\FSM_sequential_tx_state[0]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair61" *) LUT5 #( .INIT(32'h005A001A)) \FSM_sequential_tx_state[1]_i_1 (.I0(tx_state[1]), .I1(tx_state[2]), .I2(tx_state[0]), .I3(tx_state[3]), .I4(\FSM_sequential_tx_state[2]_i_2_n_0 ), .O(\FSM_sequential_tx_state[1]_i_1_n_0 )); LUT6 #( .INIT(64'h04000C0C06020C0C)) \FSM_sequential_tx_state[2]_i_1 (.I0(tx_state[1]), .I1(tx_state[2]), .I2(tx_state[3]), .I3(\FSM_sequential_tx_state[2]_i_2_n_0 ), .I4(tx_state[0]), .I5(time_out_2ms_reg_n_0), .O(\FSM_sequential_tx_state[2]_i_1_n_0 )); LUT3 #( .INIT(8'hFD)) \FSM_sequential_tx_state[2]_i_2 (.I0(time_tlock_max_reg_n_0), .I1(reset_time_out), .I2(mmcm_lock_reclocked), .O(\FSM_sequential_tx_state[2]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair62" *) LUT5 #( .INIT(32'hF4FF4444)) \FSM_sequential_tx_state[3]_i_2 (.I0(time_out_wait_bypass_s3), .I1(tx_state[3]), .I2(reset_time_out), .I3(time_out_500us_reg_n_0), .I4(\FSM_sequential_tx_state[3]_i_8_n_0 ), .O(\FSM_sequential_tx_state[3]_i_2_n_0 )); LUT6 #( .INIT(64'h00BA000000000000)) \FSM_sequential_tx_state[3]_i_3 (.I0(txresetdone_s3), .I1(reset_time_out), .I2(time_out_500us_reg_n_0), .I3(\FSM_sequential_tx_state[0]_i_3_n_0 ), .I4(tx_state[2]), .I5(tx_state[1]), .O(\FSM_sequential_tx_state[3]_i_3_n_0 )); LUT6 #( .INIT(64'h0000000300FF00AA)) \FSM_sequential_tx_state[3]_i_4 (.I0(init_wait_done_reg_n_0), .I1(\wait_time_cnt[6]_i_4_n_0 ), .I2(wait_time_cnt_reg__0[6]), .I3(tx_state[0]), .I4(tx_state[3]), .I5(CPLL_RESET_i_2_n_0), .O(\FSM_sequential_tx_state[3]_i_4_n_0 )); LUT6 #( .INIT(64'h0404040400040000)) \FSM_sequential_tx_state[3]_i_6 (.I0(tx_state[1]), .I1(tx_state[2]), .I2(\FSM_sequential_tx_state[0]_i_3_n_0 ), .I3(reset_time_out), .I4(time_tlock_max_reg_n_0), .I5(mmcm_lock_reclocked), .O(\FSM_sequential_tx_state[3]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair59" *) LUT4 #( .INIT(16'h1000)) \FSM_sequential_tx_state[3]_i_7 (.I0(tx_state[2]), .I1(tx_state[3]), .I2(tx_state[0]), .I3(tx_state[1]), .O(\FSM_sequential_tx_state[3]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair61" *) LUT4 #( .INIT(16'h4000)) \FSM_sequential_tx_state[3]_i_8 (.I0(tx_state[3]), .I1(tx_state[0]), .I2(tx_state[2]), .I3(tx_state[1]), .O(\FSM_sequential_tx_state[3]_i_8_n_0 )); (* FSM_ENCODED_STATES = "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *) FDRE #( .INIT(1'b0)) \FSM_sequential_tx_state_reg[0] (.C(independent_clock_bufg), .CE(sync_cplllock_n_0), .D(\FSM_sequential_tx_state[0]_i_1_n_0 ), .Q(tx_state[0]), .R(pma_reset)); (* FSM_ENCODED_STATES = "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *) FDRE #( .INIT(1'b0)) \FSM_sequential_tx_state_reg[1] (.C(independent_clock_bufg), .CE(sync_cplllock_n_0), .D(\FSM_sequential_tx_state[1]_i_1_n_0 ), .Q(tx_state[1]), .R(pma_reset)); (* FSM_ENCODED_STATES = "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *) FDRE #( .INIT(1'b0)) \FSM_sequential_tx_state_reg[2] (.C(independent_clock_bufg), .CE(sync_cplllock_n_0), .D(\FSM_sequential_tx_state[2]_i_1_n_0 ), .Q(tx_state[2]), .R(pma_reset)); (* FSM_ENCODED_STATES = "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *) FDRE #( .INIT(1'b0)) \FSM_sequential_tx_state_reg[3] (.C(independent_clock_bufg), .CE(sync_cplllock_n_0), .D(\FSM_sequential_tx_state[3]_i_2_n_0 ), .Q(tx_state[3]), .R(pma_reset)); (* SOFT_HLUTNM = "soft_lutpair59" *) LUT5 #( .INIT(32'hFFF70004)) MMCM_RESET_i_1 (.I0(tx_state[2]), .I1(tx_state[0]), .I2(tx_state[3]), .I3(tx_state[1]), .I4(mmcm_reset), .O(MMCM_RESET_i_1_n_0)); FDRE #( .INIT(1'b1)) MMCM_RESET_reg (.C(independent_clock_bufg), .CE(1'b1), .D(MMCM_RESET_i_1_n_0), .Q(mmcm_reset), .R(pma_reset)); (* SOFT_HLUTNM = "soft_lutpair64" *) LUT5 #( .INIT(32'hFFFD2000)) TXUSERRDY_i_1 (.I0(tx_state[0]), .I1(tx_state[3]), .I2(tx_state[2]), .I3(tx_state[1]), .I4(gt0_txuserrdy_t), .O(TXUSERRDY_i_1_n_0)); FDRE #( .INIT(1'b0)) TXUSERRDY_reg (.C(independent_clock_bufg), .CE(1'b1), .D(TXUSERRDY_i_1_n_0), .Q(gt0_txuserrdy_t), .R(pma_reset)); (* SOFT_HLUTNM = "soft_lutpair65" *) LUT5 #( .INIT(32'hFFEF0100)) gttxreset_i_i_1 (.I0(tx_state[3]), .I1(tx_state[1]), .I2(tx_state[2]), .I3(tx_state[0]), .I4(GTTXRESET), .O(gttxreset_i_i_1_n_0)); FDRE #( .INIT(1'b0)) gttxreset_i_reg (.C(independent_clock_bufg), .CE(1'b1), .D(gttxreset_i_i_1_n_0), .Q(GTTXRESET), .R(pma_reset)); LUT3 #( .INIT(8'hEA)) gtxe2_i_i_3 (.I0(GTTXRESET), .I1(data_in), .I2(data_sync_reg1), .O(gt0_gttxreset_in0_out)); LUT1 #( .INIT(2'h1)) \init_wait_count[0]_i_1 (.I0(init_wait_count_reg__0[0]), .O(\init_wait_count[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair69" *) LUT2 #( .INIT(4'h6)) \init_wait_count[1]_i_1 (.I0(init_wait_count_reg__0[0]), .I1(init_wait_count_reg__0[1]), .O(p_0_in__0[1])); (* SOFT_HLUTNM = "soft_lutpair70" *) LUT3 #( .INIT(8'h78)) \init_wait_count[2]_i_1 (.I0(init_wait_count_reg__0[0]), .I1(init_wait_count_reg__0[1]), .I2(init_wait_count_reg__0[2]), .O(p_0_in__0[2])); (* SOFT_HLUTNM = "soft_lutpair63" *) LUT4 #( .INIT(16'h7F80)) \init_wait_count[3]_i_1 (.I0(init_wait_count_reg__0[1]), .I1(init_wait_count_reg__0[2]), .I2(init_wait_count_reg__0[0]), .I3(init_wait_count_reg__0[3]), .O(p_0_in__0[3])); (* SOFT_HLUTNM = "soft_lutpair63" *) LUT5 #( .INIT(32'h7FFF8000)) \init_wait_count[4]_i_1 (.I0(init_wait_count_reg__0[2]), .I1(init_wait_count_reg__0[1]), .I2(init_wait_count_reg__0[3]), .I3(init_wait_count_reg__0[0]), .I4(init_wait_count_reg__0[4]), .O(p_0_in__0[4])); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \init_wait_count[5]_i_1 (.I0(init_wait_count_reg__0[2]), .I1(init_wait_count_reg__0[1]), .I2(init_wait_count_reg__0[3]), .I3(init_wait_count_reg__0[0]), .I4(init_wait_count_reg__0[4]), .I5(init_wait_count_reg__0[5]), .O(p_0_in__0[5])); LUT4 #( .INIT(16'hFEFF)) \init_wait_count[6]_i_1 (.I0(\init_wait_count[6]_i_3_n_0 ), .I1(init_wait_count_reg__0[0]), .I2(init_wait_count_reg__0[4]), .I3(init_wait_count_reg__0[6]), .O(\init_wait_count[6]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair69" *) LUT4 #( .INIT(16'hBF40)) \init_wait_count[6]_i_2 (.I0(\init_wait_count[6]_i_3_n_0 ), .I1(init_wait_count_reg__0[0]), .I2(init_wait_count_reg__0[4]), .I3(init_wait_count_reg__0[6]), .O(p_0_in__0[6])); (* SOFT_HLUTNM = "soft_lutpair70" *) LUT4 #( .INIT(16'h7FFF)) \init_wait_count[6]_i_3 (.I0(init_wait_count_reg__0[3]), .I1(init_wait_count_reg__0[1]), .I2(init_wait_count_reg__0[2]), .I3(init_wait_count_reg__0[5]), .O(\init_wait_count[6]_i_3_n_0 )); FDCE #( .INIT(1'b0)) \init_wait_count_reg[0] (.C(independent_clock_bufg), .CE(\init_wait_count[6]_i_1_n_0 ), .CLR(pma_reset), .D(\init_wait_count[0]_i_1_n_0 ), .Q(init_wait_count_reg__0[0])); FDCE #( .INIT(1'b0)) \init_wait_count_reg[1] (.C(independent_clock_bufg), .CE(\init_wait_count[6]_i_1_n_0 ), .CLR(pma_reset), .D(p_0_in__0[1]), .Q(init_wait_count_reg__0[1])); FDCE #( .INIT(1'b0)) \init_wait_count_reg[2] (.C(independent_clock_bufg), .CE(\init_wait_count[6]_i_1_n_0 ), .CLR(pma_reset), .D(p_0_in__0[2]), .Q(init_wait_count_reg__0[2])); FDCE #( .INIT(1'b0)) \init_wait_count_reg[3] (.C(independent_clock_bufg), .CE(\init_wait_count[6]_i_1_n_0 ), .CLR(pma_reset), .D(p_0_in__0[3]), .Q(init_wait_count_reg__0[3])); FDCE #( .INIT(1'b0)) \init_wait_count_reg[4] (.C(independent_clock_bufg), .CE(\init_wait_count[6]_i_1_n_0 ), .CLR(pma_reset), .D(p_0_in__0[4]), .Q(init_wait_count_reg__0[4])); FDCE #( .INIT(1'b0)) \init_wait_count_reg[5] (.C(independent_clock_bufg), .CE(\init_wait_count[6]_i_1_n_0 ), .CLR(pma_reset), .D(p_0_in__0[5]), .Q(init_wait_count_reg__0[5])); FDCE #( .INIT(1'b0)) \init_wait_count_reg[6] (.C(independent_clock_bufg), .CE(\init_wait_count[6]_i_1_n_0 ), .CLR(pma_reset), .D(p_0_in__0[6]), .Q(init_wait_count_reg__0[6])); LUT5 #( .INIT(32'hFFFF0010)) init_wait_done_i_1 (.I0(\init_wait_count[6]_i_3_n_0 ), .I1(init_wait_count_reg__0[4]), .I2(init_wait_count_reg__0[6]), .I3(init_wait_count_reg__0[0]), .I4(init_wait_done_reg_n_0), .O(init_wait_done_i_1_n_0)); FDCE #( .INIT(1'b0)) init_wait_done_reg (.C(independent_clock_bufg), .CE(1'b1), .CLR(pma_reset), .D(init_wait_done_i_1_n_0), .Q(init_wait_done_reg_n_0)); LUT1 #( .INIT(2'h1)) \mmcm_lock_count[0]_i_1 (.I0(mmcm_lock_count_reg__0[0]), .O(p_0_in__1[0])); (* SOFT_HLUTNM = "soft_lutpair71" *) LUT2 #( .INIT(4'h6)) \mmcm_lock_count[1]_i_1 (.I0(mmcm_lock_count_reg__0[0]), .I1(mmcm_lock_count_reg__0[1]), .O(p_0_in__1[1])); (* SOFT_HLUTNM = "soft_lutpair71" *) LUT3 #( .INIT(8'h78)) \mmcm_lock_count[2]_i_1 (.I0(mmcm_lock_count_reg__0[1]), .I1(mmcm_lock_count_reg__0[0]), .I2(mmcm_lock_count_reg__0[2]), .O(\mmcm_lock_count[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair68" *) LUT4 #( .INIT(16'h7F80)) \mmcm_lock_count[3]_i_1 (.I0(mmcm_lock_count_reg__0[2]), .I1(mmcm_lock_count_reg__0[0]), .I2(mmcm_lock_count_reg__0[1]), .I3(mmcm_lock_count_reg__0[3]), .O(\mmcm_lock_count[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair68" *) LUT5 #( .INIT(32'h7FFF8000)) \mmcm_lock_count[4]_i_1 (.I0(mmcm_lock_count_reg__0[3]), .I1(mmcm_lock_count_reg__0[1]), .I2(mmcm_lock_count_reg__0[0]), .I3(mmcm_lock_count_reg__0[2]), .I4(mmcm_lock_count_reg__0[4]), .O(\mmcm_lock_count[4]_i_1_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \mmcm_lock_count[5]_i_1 (.I0(mmcm_lock_count_reg__0[4]), .I1(mmcm_lock_count_reg__0[2]), .I2(mmcm_lock_count_reg__0[0]), .I3(mmcm_lock_count_reg__0[1]), .I4(mmcm_lock_count_reg__0[3]), .I5(mmcm_lock_count_reg__0[5]), .O(\mmcm_lock_count[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair72" *) LUT2 #( .INIT(4'h9)) \mmcm_lock_count[6]_i_1 (.I0(\mmcm_lock_count[7]_i_4_n_0 ), .I1(mmcm_lock_count_reg__0[6]), .O(\mmcm_lock_count[6]_i_1_n_0 )); LUT3 #( .INIT(8'hBF)) \mmcm_lock_count[7]_i_2 (.I0(\mmcm_lock_count[7]_i_4_n_0 ), .I1(mmcm_lock_count_reg__0[6]), .I2(mmcm_lock_count_reg__0[7]), .O(\mmcm_lock_count[7]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair72" *) LUT3 #( .INIT(8'hD2)) \mmcm_lock_count[7]_i_3 (.I0(mmcm_lock_count_reg__0[6]), .I1(\mmcm_lock_count[7]_i_4_n_0 ), .I2(mmcm_lock_count_reg__0[7]), .O(\mmcm_lock_count[7]_i_3_n_0 )); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) \mmcm_lock_count[7]_i_4 (.I0(mmcm_lock_count_reg__0[4]), .I1(mmcm_lock_count_reg__0[2]), .I2(mmcm_lock_count_reg__0[0]), .I3(mmcm_lock_count_reg__0[1]), .I4(mmcm_lock_count_reg__0[3]), .I5(mmcm_lock_count_reg__0[5]), .O(\mmcm_lock_count[7]_i_4_n_0 )); FDRE #( .INIT(1'b0)) \mmcm_lock_count_reg[0] (.C(independent_clock_bufg), .CE(\mmcm_lock_count[7]_i_2_n_0 ), .D(p_0_in__1[0]), .Q(mmcm_lock_count_reg__0[0]), .R(sync_mmcm_lock_reclocked_n_0)); FDRE #( .INIT(1'b0)) \mmcm_lock_count_reg[1] (.C(independent_clock_bufg), .CE(\mmcm_lock_count[7]_i_2_n_0 ), .D(p_0_in__1[1]), .Q(mmcm_lock_count_reg__0[1]), .R(sync_mmcm_lock_reclocked_n_0)); FDRE #( .INIT(1'b0)) \mmcm_lock_count_reg[2] (.C(independent_clock_bufg), .CE(\mmcm_lock_count[7]_i_2_n_0 ), .D(\mmcm_lock_count[2]_i_1_n_0 ), .Q(mmcm_lock_count_reg__0[2]), .R(sync_mmcm_lock_reclocked_n_0)); FDRE #( .INIT(1'b0)) \mmcm_lock_count_reg[3] (.C(independent_clock_bufg), .CE(\mmcm_lock_count[7]_i_2_n_0 ), .D(\mmcm_lock_count[3]_i_1_n_0 ), .Q(mmcm_lock_count_reg__0[3]), .R(sync_mmcm_lock_reclocked_n_0)); FDRE #( .INIT(1'b0)) \mmcm_lock_count_reg[4] (.C(independent_clock_bufg), .CE(\mmcm_lock_count[7]_i_2_n_0 ), .D(\mmcm_lock_count[4]_i_1_n_0 ), .Q(mmcm_lock_count_reg__0[4]), .R(sync_mmcm_lock_reclocked_n_0)); FDRE #( .INIT(1'b0)) \mmcm_lock_count_reg[5] (.C(independent_clock_bufg), .CE(\mmcm_lock_count[7]_i_2_n_0 ), .D(\mmcm_lock_count[5]_i_1_n_0 ), .Q(mmcm_lock_count_reg__0[5]), .R(sync_mmcm_lock_reclocked_n_0)); FDRE #( .INIT(1'b0)) \mmcm_lock_count_reg[6] (.C(independent_clock_bufg), .CE(\mmcm_lock_count[7]_i_2_n_0 ), .D(\mmcm_lock_count[6]_i_1_n_0 ), .Q(mmcm_lock_count_reg__0[6]), .R(sync_mmcm_lock_reclocked_n_0)); FDRE #( .INIT(1'b0)) \mmcm_lock_count_reg[7] (.C(independent_clock_bufg), .CE(\mmcm_lock_count[7]_i_2_n_0 ), .D(\mmcm_lock_count[7]_i_3_n_0 ), .Q(mmcm_lock_count_reg__0[7]), .R(sync_mmcm_lock_reclocked_n_0)); FDRE #( .INIT(1'b0)) mmcm_lock_reclocked_reg (.C(independent_clock_bufg), .CE(1'b1), .D(sync_mmcm_lock_reclocked_n_1), .Q(mmcm_lock_reclocked), .R(1'b0)); LUT6 #( .INIT(64'h0000CD55CCCCCCCC)) pll_reset_asserted_i_1 (.I0(tx_state[3]), .I1(pll_reset_asserted_reg_n_0), .I2(gt0_cpllrefclklost_i), .I3(refclk_stable_reg_n_0), .I4(tx_state[1]), .I5(pll_reset_asserted_i_2_n_0), .O(pll_reset_asserted_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair64" *) LUT3 #( .INIT(8'h02)) pll_reset_asserted_i_2 (.I0(tx_state[0]), .I1(tx_state[3]), .I2(tx_state[2]), .O(pll_reset_asserted_i_2_n_0)); FDRE #( .INIT(1'b0)) pll_reset_asserted_reg (.C(independent_clock_bufg), .CE(1'b1), .D(pll_reset_asserted_i_1_n_0), .Q(pll_reset_asserted_reg_n_0), .R(pma_reset)); LUT6 #( .INIT(64'hFFFFFFFFFFFEFFFF)) \refclk_stable_count[0]_i_1 (.I0(\refclk_stable_count[0]_i_3_n_0 ), .I1(\refclk_stable_count[0]_i_4_n_0 ), .I2(\refclk_stable_count[0]_i_5_n_0 ), .I3(\refclk_stable_count[0]_i_6_n_0 ), .I4(\refclk_stable_count[0]_i_7_n_0 ), .I5(\refclk_stable_count[0]_i_8_n_0 ), .O(refclk_stable_count)); LUT6 #( .INIT(64'hFFDFFFFFFFFFFFFF)) \refclk_stable_count[0]_i_3 (.I0(refclk_stable_count_reg[13]), .I1(refclk_stable_count_reg[12]), .I2(refclk_stable_count_reg[10]), .I3(refclk_stable_count_reg[11]), .I4(refclk_stable_count_reg[9]), .I5(refclk_stable_count_reg[8]), .O(\refclk_stable_count[0]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFDF)) \refclk_stable_count[0]_i_4 (.I0(refclk_stable_count_reg[19]), .I1(refclk_stable_count_reg[18]), .I2(refclk_stable_count_reg[16]), .I3(refclk_stable_count_reg[17]), .I4(refclk_stable_count_reg[15]), .I5(refclk_stable_count_reg[14]), .O(\refclk_stable_count[0]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \refclk_stable_count[0]_i_5 (.I0(refclk_stable_count_reg[30]), .I1(refclk_stable_count_reg[31]), .I2(refclk_stable_count_reg[28]), .I3(refclk_stable_count_reg[29]), .I4(refclk_stable_count_reg[27]), .I5(refclk_stable_count_reg[26]), .O(\refclk_stable_count[0]_i_5_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \refclk_stable_count[0]_i_6 (.I0(refclk_stable_count_reg[24]), .I1(refclk_stable_count_reg[25]), .I2(refclk_stable_count_reg[22]), .I3(refclk_stable_count_reg[23]), .I4(refclk_stable_count_reg[21]), .I5(refclk_stable_count_reg[20]), .O(\refclk_stable_count[0]_i_6_n_0 )); LUT2 #( .INIT(4'h1)) \refclk_stable_count[0]_i_7 (.I0(refclk_stable_count_reg[0]), .I1(refclk_stable_count_reg[1]), .O(\refclk_stable_count[0]_i_7_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFF7)) \refclk_stable_count[0]_i_8 (.I0(refclk_stable_count_reg[6]), .I1(refclk_stable_count_reg[7]), .I2(refclk_stable_count_reg[4]), .I3(refclk_stable_count_reg[5]), .I4(refclk_stable_count_reg[3]), .I5(refclk_stable_count_reg[2]), .O(\refclk_stable_count[0]_i_8_n_0 )); LUT1 #( .INIT(2'h1)) \refclk_stable_count[0]_i_9 (.I0(refclk_stable_count_reg[0]), .O(\refclk_stable_count[0]_i_9_n_0 )); FDRE #( .INIT(1'b0)) \refclk_stable_count_reg[0] (.C(independent_clock_bufg), .CE(refclk_stable_count), .D(\refclk_stable_count_reg[0]_i_2_n_7 ), .Q(refclk_stable_count_reg[0]), .R(1'b0)); CARRY4 \refclk_stable_count_reg[0]_i_2 (.CI(1'b0), .CO({\refclk_stable_count_reg[0]_i_2_n_0 ,\refclk_stable_count_reg[0]_i_2_n_1 ,\refclk_stable_count_reg[0]_i_2_n_2 ,\refclk_stable_count_reg[0]_i_2_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b1}), .O({\refclk_stable_count_reg[0]_i_2_n_4 ,\refclk_stable_count_reg[0]_i_2_n_5 ,\refclk_stable_count_reg[0]_i_2_n_6 ,\refclk_stable_count_reg[0]_i_2_n_7 }), .S({refclk_stable_count_reg[3:1],\refclk_stable_count[0]_i_9_n_0 })); FDRE #( .INIT(1'b0)) \refclk_stable_count_reg[10] (.C(independent_clock_bufg), .CE(refclk_stable_count), .D(\refclk_stable_count_reg[8]_i_1_n_5 ), .Q(refclk_stable_count_reg[10]), .R(1'b0)); FDRE #( .INIT(1'b0)) \refclk_stable_count_reg[11] (.C(independent_clock_bufg), .CE(refclk_stable_count), .D(\refclk_stable_count_reg[8]_i_1_n_4 ), .Q(refclk_stable_count_reg[11]), .R(1'b0)); FDRE #( .INIT(1'b0)) \refclk_stable_count_reg[12] (.C(independent_clock_bufg), .CE(refclk_stable_count), .D(\refclk_stable_count_reg[12]_i_1_n_7 ), .Q(refclk_stable_count_reg[12]), .R(1'b0)); CARRY4 \refclk_stable_count_reg[12]_i_1 (.CI(\refclk_stable_count_reg[8]_i_1_n_0 ), .CO({\refclk_stable_count_reg[12]_i_1_n_0 ,\refclk_stable_count_reg[12]_i_1_n_1 ,\refclk_stable_count_reg[12]_i_1_n_2 ,\refclk_stable_count_reg[12]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\refclk_stable_count_reg[12]_i_1_n_4 ,\refclk_stable_count_reg[12]_i_1_n_5 ,\refclk_stable_count_reg[12]_i_1_n_6 ,\refclk_stable_count_reg[12]_i_1_n_7 }), .S(refclk_stable_count_reg[15:12])); FDRE #( .INIT(1'b0)) \refclk_stable_count_reg[13] (.C(independent_clock_bufg), .CE(refclk_stable_count), .D(\refclk_stable_count_reg[12]_i_1_n_6 ), .Q(refclk_stable_count_reg[13]), .R(1'b0)); FDRE #( .INIT(1'b0)) \refclk_stable_count_reg[14] (.C(independent_clock_bufg), .CE(refclk_stable_count), .D(\refclk_stable_count_reg[12]_i_1_n_5 ), .Q(refclk_stable_count_reg[14]), .R(1'b0)); FDRE #( .INIT(1'b0)) \refclk_stable_count_reg[15] (.C(independent_clock_bufg), .CE(refclk_stable_count), .D(\refclk_stable_count_reg[12]_i_1_n_4 ), .Q(refclk_stable_count_reg[15]), .R(1'b0)); FDRE #( .INIT(1'b0)) \refclk_stable_count_reg[16] (.C(independent_clock_bufg), .CE(refclk_stable_count), .D(\refclk_stable_count_reg[16]_i_1_n_7 ), .Q(refclk_stable_count_reg[16]), .R(1'b0)); CARRY4 \refclk_stable_count_reg[16]_i_1 (.CI(\refclk_stable_count_reg[12]_i_1_n_0 ), .CO({\refclk_stable_count_reg[16]_i_1_n_0 ,\refclk_stable_count_reg[16]_i_1_n_1 ,\refclk_stable_count_reg[16]_i_1_n_2 ,\refclk_stable_count_reg[16]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\refclk_stable_count_reg[16]_i_1_n_4 ,\refclk_stable_count_reg[16]_i_1_n_5 ,\refclk_stable_count_reg[16]_i_1_n_6 ,\refclk_stable_count_reg[16]_i_1_n_7 }), .S(refclk_stable_count_reg[19:16])); FDRE #( .INIT(1'b0)) \refclk_stable_count_reg[17] (.C(independent_clock_bufg), .CE(refclk_stable_count), .D(\refclk_stable_count_reg[16]_i_1_n_6 ), .Q(refclk_stable_count_reg[17]), .R(1'b0)); FDRE #( .INIT(1'b0)) \refclk_stable_count_reg[18] (.C(independent_clock_bufg), .CE(refclk_stable_count), .D(\refclk_stable_count_reg[16]_i_1_n_5 ), .Q(refclk_stable_count_reg[18]), .R(1'b0)); FDRE #( .INIT(1'b0)) \refclk_stable_count_reg[19] (.C(independent_clock_bufg), .CE(refclk_stable_count), .D(\refclk_stable_count_reg[16]_i_1_n_4 ), .Q(refclk_stable_count_reg[19]), .R(1'b0)); FDRE #( .INIT(1'b0)) \refclk_stable_count_reg[1] (.C(independent_clock_bufg), .CE(refclk_stable_count), .D(\refclk_stable_count_reg[0]_i_2_n_6 ), .Q(refclk_stable_count_reg[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \refclk_stable_count_reg[20] (.C(independent_clock_bufg), .CE(refclk_stable_count), .D(\refclk_stable_count_reg[20]_i_1_n_7 ), .Q(refclk_stable_count_reg[20]), .R(1'b0)); CARRY4 \refclk_stable_count_reg[20]_i_1 (.CI(\refclk_stable_count_reg[16]_i_1_n_0 ), .CO({\refclk_stable_count_reg[20]_i_1_n_0 ,\refclk_stable_count_reg[20]_i_1_n_1 ,\refclk_stable_count_reg[20]_i_1_n_2 ,\refclk_stable_count_reg[20]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\refclk_stable_count_reg[20]_i_1_n_4 ,\refclk_stable_count_reg[20]_i_1_n_5 ,\refclk_stable_count_reg[20]_i_1_n_6 ,\refclk_stable_count_reg[20]_i_1_n_7 }), .S(refclk_stable_count_reg[23:20])); FDRE #( .INIT(1'b0)) \refclk_stable_count_reg[21] (.C(independent_clock_bufg), .CE(refclk_stable_count), .D(\refclk_stable_count_reg[20]_i_1_n_6 ), .Q(refclk_stable_count_reg[21]), .R(1'b0)); FDRE #( .INIT(1'b0)) \refclk_stable_count_reg[22] (.C(independent_clock_bufg), .CE(refclk_stable_count), .D(\refclk_stable_count_reg[20]_i_1_n_5 ), .Q(refclk_stable_count_reg[22]), .R(1'b0)); FDRE #( .INIT(1'b0)) \refclk_stable_count_reg[23] (.C(independent_clock_bufg), .CE(refclk_stable_count), .D(\refclk_stable_count_reg[20]_i_1_n_4 ), .Q(refclk_stable_count_reg[23]), .R(1'b0)); FDRE #( .INIT(1'b0)) \refclk_stable_count_reg[24] (.C(independent_clock_bufg), .CE(refclk_stable_count), .D(\refclk_stable_count_reg[24]_i_1_n_7 ), .Q(refclk_stable_count_reg[24]), .R(1'b0)); CARRY4 \refclk_stable_count_reg[24]_i_1 (.CI(\refclk_stable_count_reg[20]_i_1_n_0 ), .CO({\refclk_stable_count_reg[24]_i_1_n_0 ,\refclk_stable_count_reg[24]_i_1_n_1 ,\refclk_stable_count_reg[24]_i_1_n_2 ,\refclk_stable_count_reg[24]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\refclk_stable_count_reg[24]_i_1_n_4 ,\refclk_stable_count_reg[24]_i_1_n_5 ,\refclk_stable_count_reg[24]_i_1_n_6 ,\refclk_stable_count_reg[24]_i_1_n_7 }), .S(refclk_stable_count_reg[27:24])); FDRE #( .INIT(1'b0)) \refclk_stable_count_reg[25] (.C(independent_clock_bufg), .CE(refclk_stable_count), .D(\refclk_stable_count_reg[24]_i_1_n_6 ), .Q(refclk_stable_count_reg[25]), .R(1'b0)); FDRE #( .INIT(1'b0)) \refclk_stable_count_reg[26] (.C(independent_clock_bufg), .CE(refclk_stable_count), .D(\refclk_stable_count_reg[24]_i_1_n_5 ), .Q(refclk_stable_count_reg[26]), .R(1'b0)); FDRE #( .INIT(1'b0)) \refclk_stable_count_reg[27] (.C(independent_clock_bufg), .CE(refclk_stable_count), .D(\refclk_stable_count_reg[24]_i_1_n_4 ), .Q(refclk_stable_count_reg[27]), .R(1'b0)); FDRE #( .INIT(1'b0)) \refclk_stable_count_reg[28] (.C(independent_clock_bufg), .CE(refclk_stable_count), .D(\refclk_stable_count_reg[28]_i_1_n_7 ), .Q(refclk_stable_count_reg[28]), .R(1'b0)); CARRY4 \refclk_stable_count_reg[28]_i_1 (.CI(\refclk_stable_count_reg[24]_i_1_n_0 ), .CO({\NLW_refclk_stable_count_reg[28]_i_1_CO_UNCONNECTED [3],\refclk_stable_count_reg[28]_i_1_n_1 ,\refclk_stable_count_reg[28]_i_1_n_2 ,\refclk_stable_count_reg[28]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\refclk_stable_count_reg[28]_i_1_n_4 ,\refclk_stable_count_reg[28]_i_1_n_5 ,\refclk_stable_count_reg[28]_i_1_n_6 ,\refclk_stable_count_reg[28]_i_1_n_7 }), .S(refclk_stable_count_reg[31:28])); FDRE #( .INIT(1'b0)) \refclk_stable_count_reg[29] (.C(independent_clock_bufg), .CE(refclk_stable_count), .D(\refclk_stable_count_reg[28]_i_1_n_6 ), .Q(refclk_stable_count_reg[29]), .R(1'b0)); FDRE #( .INIT(1'b0)) \refclk_stable_count_reg[2] (.C(independent_clock_bufg), .CE(refclk_stable_count), .D(\refclk_stable_count_reg[0]_i_2_n_5 ), .Q(refclk_stable_count_reg[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \refclk_stable_count_reg[30] (.C(independent_clock_bufg), .CE(refclk_stable_count), .D(\refclk_stable_count_reg[28]_i_1_n_5 ), .Q(refclk_stable_count_reg[30]), .R(1'b0)); FDRE #( .INIT(1'b0)) \refclk_stable_count_reg[31] (.C(independent_clock_bufg), .CE(refclk_stable_count), .D(\refclk_stable_count_reg[28]_i_1_n_4 ), .Q(refclk_stable_count_reg[31]), .R(1'b0)); FDRE #( .INIT(1'b0)) \refclk_stable_count_reg[3] (.C(independent_clock_bufg), .CE(refclk_stable_count), .D(\refclk_stable_count_reg[0]_i_2_n_4 ), .Q(refclk_stable_count_reg[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \refclk_stable_count_reg[4] (.C(independent_clock_bufg), .CE(refclk_stable_count), .D(\refclk_stable_count_reg[4]_i_1_n_7 ), .Q(refclk_stable_count_reg[4]), .R(1'b0)); CARRY4 \refclk_stable_count_reg[4]_i_1 (.CI(\refclk_stable_count_reg[0]_i_2_n_0 ), .CO({\refclk_stable_count_reg[4]_i_1_n_0 ,\refclk_stable_count_reg[4]_i_1_n_1 ,\refclk_stable_count_reg[4]_i_1_n_2 ,\refclk_stable_count_reg[4]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\refclk_stable_count_reg[4]_i_1_n_4 ,\refclk_stable_count_reg[4]_i_1_n_5 ,\refclk_stable_count_reg[4]_i_1_n_6 ,\refclk_stable_count_reg[4]_i_1_n_7 }), .S(refclk_stable_count_reg[7:4])); FDRE #( .INIT(1'b0)) \refclk_stable_count_reg[5] (.C(independent_clock_bufg), .CE(refclk_stable_count), .D(\refclk_stable_count_reg[4]_i_1_n_6 ), .Q(refclk_stable_count_reg[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \refclk_stable_count_reg[6] (.C(independent_clock_bufg), .CE(refclk_stable_count), .D(\refclk_stable_count_reg[4]_i_1_n_5 ), .Q(refclk_stable_count_reg[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \refclk_stable_count_reg[7] (.C(independent_clock_bufg), .CE(refclk_stable_count), .D(\refclk_stable_count_reg[4]_i_1_n_4 ), .Q(refclk_stable_count_reg[7]), .R(1'b0)); FDRE #( .INIT(1'b0)) \refclk_stable_count_reg[8] (.C(independent_clock_bufg), .CE(refclk_stable_count), .D(\refclk_stable_count_reg[8]_i_1_n_7 ), .Q(refclk_stable_count_reg[8]), .R(1'b0)); CARRY4 \refclk_stable_count_reg[8]_i_1 (.CI(\refclk_stable_count_reg[4]_i_1_n_0 ), .CO({\refclk_stable_count_reg[8]_i_1_n_0 ,\refclk_stable_count_reg[8]_i_1_n_1 ,\refclk_stable_count_reg[8]_i_1_n_2 ,\refclk_stable_count_reg[8]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\refclk_stable_count_reg[8]_i_1_n_4 ,\refclk_stable_count_reg[8]_i_1_n_5 ,\refclk_stable_count_reg[8]_i_1_n_6 ,\refclk_stable_count_reg[8]_i_1_n_7 }), .S(refclk_stable_count_reg[11:8])); FDRE #( .INIT(1'b0)) \refclk_stable_count_reg[9] (.C(independent_clock_bufg), .CE(refclk_stable_count), .D(\refclk_stable_count_reg[8]_i_1_n_6 ), .Q(refclk_stable_count_reg[9]), .R(1'b0)); LUT6 #( .INIT(64'h8000000000000000)) refclk_stable_i_1 (.I0(\refclk_stable_count[0]_i_7_n_0 ), .I1(refclk_stable_i_2_n_0), .I2(refclk_stable_i_3_n_0), .I3(refclk_stable_i_4_n_0), .I4(refclk_stable_i_5_n_0), .I5(refclk_stable_i_6_n_0), .O(refclk_stable_i_1_n_0)); LUT6 #( .INIT(64'h0001000000000000)) refclk_stable_i_2 (.I0(refclk_stable_count_reg[4]), .I1(refclk_stable_count_reg[5]), .I2(refclk_stable_count_reg[2]), .I3(refclk_stable_count_reg[3]), .I4(refclk_stable_count_reg[7]), .I5(refclk_stable_count_reg[6]), .O(refclk_stable_i_2_n_0)); LUT6 #( .INIT(64'h0000200000000000)) refclk_stable_i_3 (.I0(refclk_stable_count_reg[10]), .I1(refclk_stable_count_reg[11]), .I2(refclk_stable_count_reg[8]), .I3(refclk_stable_count_reg[9]), .I4(refclk_stable_count_reg[12]), .I5(refclk_stable_count_reg[13]), .O(refclk_stable_i_3_n_0)); LUT6 #( .INIT(64'h0000000200000000)) refclk_stable_i_4 (.I0(refclk_stable_count_reg[16]), .I1(refclk_stable_count_reg[17]), .I2(refclk_stable_count_reg[14]), .I3(refclk_stable_count_reg[15]), .I4(refclk_stable_count_reg[18]), .I5(refclk_stable_count_reg[19]), .O(refclk_stable_i_4_n_0)); LUT6 #( .INIT(64'h0000000000000001)) refclk_stable_i_5 (.I0(refclk_stable_count_reg[22]), .I1(refclk_stable_count_reg[23]), .I2(refclk_stable_count_reg[20]), .I3(refclk_stable_count_reg[21]), .I4(refclk_stable_count_reg[25]), .I5(refclk_stable_count_reg[24]), .O(refclk_stable_i_5_n_0)); LUT6 #( .INIT(64'h0000000000000001)) refclk_stable_i_6 (.I0(refclk_stable_count_reg[28]), .I1(refclk_stable_count_reg[29]), .I2(refclk_stable_count_reg[26]), .I3(refclk_stable_count_reg[27]), .I4(refclk_stable_count_reg[31]), .I5(refclk_stable_count_reg[30]), .O(refclk_stable_i_6_n_0)); FDRE #( .INIT(1'b0)) refclk_stable_reg (.C(independent_clock_bufg), .CE(1'b1), .D(refclk_stable_i_1_n_0), .Q(refclk_stable_reg_n_0), .R(1'b0)); LUT6 #( .INIT(64'h440000FF50505050)) reset_time_out_i_2__0 (.I0(tx_state[3]), .I1(txresetdone_s3), .I2(init_wait_done_reg_n_0), .I3(tx_state[1]), .I4(tx_state[2]), .I5(tx_state[0]), .O(reset_time_out_i_2__0_n_0)); FDRE #( .INIT(1'b0)) reset_time_out_reg (.C(independent_clock_bufg), .CE(1'b1), .D(sync_cplllock_n_1), .Q(reset_time_out), .R(pma_reset)); LUT5 #( .INIT(32'hFFFB0002)) run_phase_alignment_int_i_1 (.I0(tx_state[3]), .I1(tx_state[0]), .I2(tx_state[2]), .I3(tx_state[1]), .I4(run_phase_alignment_int_reg_n_0), .O(run_phase_alignment_int_i_1_n_0)); FDRE #( .INIT(1'b0)) run_phase_alignment_int_reg (.C(independent_clock_bufg), .CE(1'b1), .D(run_phase_alignment_int_i_1_n_0), .Q(run_phase_alignment_int_reg_n_0), .R(pma_reset)); FDRE #( .INIT(1'b0)) run_phase_alignment_int_s3_reg (.C(userclk), .CE(1'b1), .D(data_out), .Q(run_phase_alignment_int_s3), .R(1'b0)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_4 sync_TXRESETDONE (.data_out(txresetdone_s2), .data_sync_reg1_0(data_sync_reg1_0), .independent_clock_bufg(independent_clock_bufg)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_5 sync_cplllock (.E(sync_cplllock_n_0), .\FSM_sequential_tx_state_reg[0] (\FSM_sequential_tx_state[3]_i_3_n_0 ), .\FSM_sequential_tx_state_reg[0]_0 (\FSM_sequential_tx_state[3]_i_4_n_0 ), .\FSM_sequential_tx_state_reg[0]_1 (\FSM_sequential_tx_state[3]_i_6_n_0 ), .\FSM_sequential_tx_state_reg[0]_2 (time_out_2ms_reg_n_0), .\FSM_sequential_tx_state_reg[0]_3 (\FSM_sequential_tx_state[3]_i_7_n_0 ), .\FSM_sequential_tx_state_reg[0]_4 (pll_reset_asserted_reg_n_0), .\FSM_sequential_tx_state_reg[0]_5 (refclk_stable_reg_n_0), .\FSM_sequential_tx_state_reg[0]_6 (\FSM_sequential_tx_state[0]_i_3_n_0 ), .Q(tx_state), .cplllock(cplllock), .independent_clock_bufg(independent_clock_bufg), .mmcm_lock_reclocked(mmcm_lock_reclocked), .reset_time_out(reset_time_out), .reset_time_out_reg(sync_cplllock_n_1), .reset_time_out_reg_0(init_wait_done_reg_n_0), .reset_time_out_reg_1(reset_time_out_i_2__0_n_0)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_6 sync_mmcm_lock_reclocked (.Q(mmcm_lock_count_reg__0[7:6]), .SR(sync_mmcm_lock_reclocked_n_0), .independent_clock_bufg(independent_clock_bufg), .mmcm_lock_reclocked(mmcm_lock_reclocked), .mmcm_lock_reclocked_reg(sync_mmcm_lock_reclocked_n_1), .mmcm_lock_reclocked_reg_0(\mmcm_lock_count[7]_i_4_n_0 ), .mmcm_locked(mmcm_locked)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_7 sync_run_phase_alignment_int (.data_in(run_phase_alignment_int_reg_n_0), .data_out(data_out), .userclk(userclk)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_8 sync_time_out_wait_bypass (.data_in(time_out_wait_bypass_reg_n_0), .data_out(time_out_wait_bypass_s2), .independent_clock_bufg(independent_clock_bufg)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_9 sync_tx_fsm_reset_done_int (.data_in(data_in), .data_out(tx_fsm_reset_done_int_s2), .userclk(userclk)); LUT4 #( .INIT(16'h00AE)) time_out_2ms_i_1__0 (.I0(time_out_2ms_reg_n_0), .I1(time_out_2ms_i_2_n_0), .I2(\time_out_counter[0]_i_5__0_n_0 ), .I3(reset_time_out), .O(time_out_2ms_i_1__0_n_0)); LUT6 #( .INIT(64'h0000000000000800)) time_out_2ms_i_2 (.I0(time_out_counter_reg[17]), .I1(time_out_counter_reg[18]), .I2(time_out_counter_reg[10]), .I3(time_out_counter_reg[12]), .I4(time_out_counter_reg[5]), .I5(\time_out_counter[0]_i_3__0_n_0 ), .O(time_out_2ms_i_2_n_0)); FDRE #( .INIT(1'b0)) time_out_2ms_reg (.C(independent_clock_bufg), .CE(1'b1), .D(time_out_2ms_i_1__0_n_0), .Q(time_out_2ms_reg_n_0), .R(1'b0)); LUT6 #( .INIT(64'h00000000AAAAEAAA)) time_out_500us_i_1 (.I0(time_out_500us_reg_n_0), .I1(time_out_500us_i_2_n_0), .I2(time_out_counter_reg[5]), .I3(time_out_counter_reg[10]), .I4(\time_out_counter[0]_i_5__0_n_0 ), .I5(reset_time_out), .O(time_out_500us_i_1_n_0)); LUT6 #( .INIT(64'h0000000000000008)) time_out_500us_i_2 (.I0(time_out_counter_reg[15]), .I1(time_out_counter_reg[16]), .I2(time_out_counter_reg[11]), .I3(time_out_counter_reg[12]), .I4(time_out_counter_reg[18]), .I5(time_out_counter_reg[17]), .O(time_out_500us_i_2_n_0)); FDRE #( .INIT(1'b0)) time_out_500us_reg (.C(independent_clock_bufg), .CE(1'b1), .D(time_out_500us_i_1_n_0), .Q(time_out_500us_reg_n_0), .R(1'b0)); LUT6 #( .INIT(64'hFFFFFFFFFFFBFFFF)) \time_out_counter[0]_i_1__0 (.I0(\time_out_counter[0]_i_3__0_n_0 ), .I1(\time_out_counter[0]_i_4__0_n_0 ), .I2(\time_out_counter[0]_i_5__0_n_0 ), .I3(time_out_counter_reg[10]), .I4(time_out_counter_reg[12]), .I5(time_out_counter_reg[5]), .O(time_out_counter)); LUT3 #( .INIT(8'hEF)) \time_out_counter[0]_i_3__0 (.I0(time_out_counter_reg[16]), .I1(time_out_counter_reg[15]), .I2(time_out_counter_reg[11]), .O(\time_out_counter[0]_i_3__0_n_0 )); LUT2 #( .INIT(4'h8)) \time_out_counter[0]_i_4__0 (.I0(time_out_counter_reg[17]), .I1(time_out_counter_reg[18]), .O(\time_out_counter[0]_i_4__0_n_0 )); LUT4 #( .INIT(16'hFFFD)) \time_out_counter[0]_i_5__0 (.I0(time_out_counter_reg[7]), .I1(time_out_counter_reg[14]), .I2(\time_out_counter[0]_i_7_n_0 ), .I3(\time_out_counter[0]_i_8_n_0 ), .O(\time_out_counter[0]_i_5__0_n_0 )); LUT1 #( .INIT(2'h1)) \time_out_counter[0]_i_6 (.I0(time_out_counter_reg[0]), .O(\time_out_counter[0]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair60" *) LUT4 #( .INIT(16'hFFFE)) \time_out_counter[0]_i_7 (.I0(time_out_counter_reg[4]), .I1(time_out_counter_reg[3]), .I2(time_out_counter_reg[8]), .I3(time_out_counter_reg[6]), .O(\time_out_counter[0]_i_7_n_0 )); LUT5 #( .INIT(32'hFFFFFFEF)) \time_out_counter[0]_i_8 (.I0(time_out_counter_reg[0]), .I1(time_out_counter_reg[13]), .I2(time_out_counter_reg[9]), .I3(time_out_counter_reg[2]), .I4(time_out_counter_reg[1]), .O(\time_out_counter[0]_i_8_n_0 )); FDRE #( .INIT(1'b0)) \time_out_counter_reg[0] (.C(independent_clock_bufg), .CE(time_out_counter), .D(\time_out_counter_reg[0]_i_2_n_7 ), .Q(time_out_counter_reg[0]), .R(reset_time_out)); CARRY4 \time_out_counter_reg[0]_i_2 (.CI(1'b0), .CO({\time_out_counter_reg[0]_i_2_n_0 ,\time_out_counter_reg[0]_i_2_n_1 ,\time_out_counter_reg[0]_i_2_n_2 ,\time_out_counter_reg[0]_i_2_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b1}), .O({\time_out_counter_reg[0]_i_2_n_4 ,\time_out_counter_reg[0]_i_2_n_5 ,\time_out_counter_reg[0]_i_2_n_6 ,\time_out_counter_reg[0]_i_2_n_7 }), .S({time_out_counter_reg[3:1],\time_out_counter[0]_i_6_n_0 })); FDRE #( .INIT(1'b0)) \time_out_counter_reg[10] (.C(independent_clock_bufg), .CE(time_out_counter), .D(\time_out_counter_reg[8]_i_1_n_5 ), .Q(time_out_counter_reg[10]), .R(reset_time_out)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[11] (.C(independent_clock_bufg), .CE(time_out_counter), .D(\time_out_counter_reg[8]_i_1_n_4 ), .Q(time_out_counter_reg[11]), .R(reset_time_out)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[12] (.C(independent_clock_bufg), .CE(time_out_counter), .D(\time_out_counter_reg[12]_i_1_n_7 ), .Q(time_out_counter_reg[12]), .R(reset_time_out)); CARRY4 \time_out_counter_reg[12]_i_1 (.CI(\time_out_counter_reg[8]_i_1_n_0 ), .CO({\time_out_counter_reg[12]_i_1_n_0 ,\time_out_counter_reg[12]_i_1_n_1 ,\time_out_counter_reg[12]_i_1_n_2 ,\time_out_counter_reg[12]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\time_out_counter_reg[12]_i_1_n_4 ,\time_out_counter_reg[12]_i_1_n_5 ,\time_out_counter_reg[12]_i_1_n_6 ,\time_out_counter_reg[12]_i_1_n_7 }), .S(time_out_counter_reg[15:12])); FDRE #( .INIT(1'b0)) \time_out_counter_reg[13] (.C(independent_clock_bufg), .CE(time_out_counter), .D(\time_out_counter_reg[12]_i_1_n_6 ), .Q(time_out_counter_reg[13]), .R(reset_time_out)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[14] (.C(independent_clock_bufg), .CE(time_out_counter), .D(\time_out_counter_reg[12]_i_1_n_5 ), .Q(time_out_counter_reg[14]), .R(reset_time_out)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[15] (.C(independent_clock_bufg), .CE(time_out_counter), .D(\time_out_counter_reg[12]_i_1_n_4 ), .Q(time_out_counter_reg[15]), .R(reset_time_out)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[16] (.C(independent_clock_bufg), .CE(time_out_counter), .D(\time_out_counter_reg[16]_i_1_n_7 ), .Q(time_out_counter_reg[16]), .R(reset_time_out)); CARRY4 \time_out_counter_reg[16]_i_1 (.CI(\time_out_counter_reg[12]_i_1_n_0 ), .CO({\NLW_time_out_counter_reg[16]_i_1_CO_UNCONNECTED [3:2],\time_out_counter_reg[16]_i_1_n_2 ,\time_out_counter_reg[16]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\NLW_time_out_counter_reg[16]_i_1_O_UNCONNECTED [3],\time_out_counter_reg[16]_i_1_n_5 ,\time_out_counter_reg[16]_i_1_n_6 ,\time_out_counter_reg[16]_i_1_n_7 }), .S({1'b0,time_out_counter_reg[18:16]})); FDRE #( .INIT(1'b0)) \time_out_counter_reg[17] (.C(independent_clock_bufg), .CE(time_out_counter), .D(\time_out_counter_reg[16]_i_1_n_6 ), .Q(time_out_counter_reg[17]), .R(reset_time_out)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[18] (.C(independent_clock_bufg), .CE(time_out_counter), .D(\time_out_counter_reg[16]_i_1_n_5 ), .Q(time_out_counter_reg[18]), .R(reset_time_out)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[1] (.C(independent_clock_bufg), .CE(time_out_counter), .D(\time_out_counter_reg[0]_i_2_n_6 ), .Q(time_out_counter_reg[1]), .R(reset_time_out)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[2] (.C(independent_clock_bufg), .CE(time_out_counter), .D(\time_out_counter_reg[0]_i_2_n_5 ), .Q(time_out_counter_reg[2]), .R(reset_time_out)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[3] (.C(independent_clock_bufg), .CE(time_out_counter), .D(\time_out_counter_reg[0]_i_2_n_4 ), .Q(time_out_counter_reg[3]), .R(reset_time_out)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[4] (.C(independent_clock_bufg), .CE(time_out_counter), .D(\time_out_counter_reg[4]_i_1_n_7 ), .Q(time_out_counter_reg[4]), .R(reset_time_out)); CARRY4 \time_out_counter_reg[4]_i_1 (.CI(\time_out_counter_reg[0]_i_2_n_0 ), .CO({\time_out_counter_reg[4]_i_1_n_0 ,\time_out_counter_reg[4]_i_1_n_1 ,\time_out_counter_reg[4]_i_1_n_2 ,\time_out_counter_reg[4]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\time_out_counter_reg[4]_i_1_n_4 ,\time_out_counter_reg[4]_i_1_n_5 ,\time_out_counter_reg[4]_i_1_n_6 ,\time_out_counter_reg[4]_i_1_n_7 }), .S(time_out_counter_reg[7:4])); FDRE #( .INIT(1'b0)) \time_out_counter_reg[5] (.C(independent_clock_bufg), .CE(time_out_counter), .D(\time_out_counter_reg[4]_i_1_n_6 ), .Q(time_out_counter_reg[5]), .R(reset_time_out)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[6] (.C(independent_clock_bufg), .CE(time_out_counter), .D(\time_out_counter_reg[4]_i_1_n_5 ), .Q(time_out_counter_reg[6]), .R(reset_time_out)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[7] (.C(independent_clock_bufg), .CE(time_out_counter), .D(\time_out_counter_reg[4]_i_1_n_4 ), .Q(time_out_counter_reg[7]), .R(reset_time_out)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[8] (.C(independent_clock_bufg), .CE(time_out_counter), .D(\time_out_counter_reg[8]_i_1_n_7 ), .Q(time_out_counter_reg[8]), .R(reset_time_out)); CARRY4 \time_out_counter_reg[8]_i_1 (.CI(\time_out_counter_reg[4]_i_1_n_0 ), .CO({\time_out_counter_reg[8]_i_1_n_0 ,\time_out_counter_reg[8]_i_1_n_1 ,\time_out_counter_reg[8]_i_1_n_2 ,\time_out_counter_reg[8]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\time_out_counter_reg[8]_i_1_n_4 ,\time_out_counter_reg[8]_i_1_n_5 ,\time_out_counter_reg[8]_i_1_n_6 ,\time_out_counter_reg[8]_i_1_n_7 }), .S(time_out_counter_reg[11:8])); FDRE #( .INIT(1'b0)) \time_out_counter_reg[9] (.C(independent_clock_bufg), .CE(time_out_counter), .D(\time_out_counter_reg[8]_i_1_n_6 ), .Q(time_out_counter_reg[9]), .R(reset_time_out)); LUT4 #( .INIT(16'hAB00)) time_out_wait_bypass_i_1 (.I0(time_out_wait_bypass_reg_n_0), .I1(tx_fsm_reset_done_int_s3), .I2(\wait_bypass_count[0]_i_4_n_0 ), .I3(run_phase_alignment_int_s3), .O(time_out_wait_bypass_i_1_n_0)); FDRE #( .INIT(1'b0)) time_out_wait_bypass_reg (.C(userclk), .CE(1'b1), .D(time_out_wait_bypass_i_1_n_0), .Q(time_out_wait_bypass_reg_n_0), .R(1'b0)); FDRE #( .INIT(1'b0)) time_out_wait_bypass_s3_reg (.C(independent_clock_bufg), .CE(1'b1), .D(time_out_wait_bypass_s2), .Q(time_out_wait_bypass_s3), .R(1'b0)); LUT6 #( .INIT(64'h00000000AAAAAAEA)) time_tlock_max_i_1__0 (.I0(time_tlock_max_reg_n_0), .I1(time_tlock_max_i_2_n_0), .I2(time_out_counter_reg[5]), .I3(\time_out_counter[0]_i_3__0_n_0 ), .I4(time_tlock_max_i_3_n_0), .I5(reset_time_out), .O(time_tlock_max_i_1__0_n_0)); LUT6 #( .INIT(64'h0000000000000020)) time_tlock_max_i_2 (.I0(time_out_counter_reg[14]), .I1(time_out_counter_reg[12]), .I2(time_out_counter_reg[10]), .I3(time_out_counter_reg[7]), .I4(time_out_counter_reg[18]), .I5(time_out_counter_reg[17]), .O(time_tlock_max_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair60" *) LUT5 #( .INIT(32'hFFFFFFFE)) time_tlock_max_i_3 (.I0(\time_out_counter[0]_i_8_n_0 ), .I1(time_out_counter_reg[6]), .I2(time_out_counter_reg[8]), .I3(time_out_counter_reg[3]), .I4(time_out_counter_reg[4]), .O(time_tlock_max_i_3_n_0)); FDRE #( .INIT(1'b0)) time_tlock_max_reg (.C(independent_clock_bufg), .CE(1'b1), .D(time_tlock_max_i_1__0_n_0), .Q(time_tlock_max_reg_n_0), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair66" *) LUT5 #( .INIT(32'hFFFF1000)) tx_fsm_reset_done_int_i_1 (.I0(tx_state[1]), .I1(tx_state[2]), .I2(tx_state[0]), .I3(tx_state[3]), .I4(data_in), .O(tx_fsm_reset_done_int_i_1_n_0)); FDRE #( .INIT(1'b0)) tx_fsm_reset_done_int_reg (.C(independent_clock_bufg), .CE(1'b1), .D(tx_fsm_reset_done_int_i_1_n_0), .Q(data_in), .R(pma_reset)); FDRE #( .INIT(1'b0)) tx_fsm_reset_done_int_s3_reg (.C(userclk), .CE(1'b1), .D(tx_fsm_reset_done_int_s2), .Q(tx_fsm_reset_done_int_s3), .R(1'b0)); FDRE #( .INIT(1'b0)) txresetdone_s3_reg (.C(independent_clock_bufg), .CE(1'b1), .D(txresetdone_s2), .Q(txresetdone_s3), .R(1'b0)); LUT1 #( .INIT(2'h1)) \wait_bypass_count[0]_i_1 (.I0(run_phase_alignment_int_s3), .O(clear)); LUT2 #( .INIT(4'h2)) \wait_bypass_count[0]_i_2 (.I0(\wait_bypass_count[0]_i_4_n_0 ), .I1(tx_fsm_reset_done_int_s3), .O(\wait_bypass_count[0]_i_2_n_0 )); LUT6 #( .INIT(64'hFFEFFFFFFFFFFFFF)) \wait_bypass_count[0]_i_4 (.I0(\wait_bypass_count[0]_i_6_n_0 ), .I1(\wait_bypass_count[0]_i_7_n_0 ), .I2(wait_bypass_count_reg[16]), .I3(wait_bypass_count_reg[13]), .I4(wait_bypass_count_reg[12]), .I5(\wait_bypass_count[0]_i_8_n_0 ), .O(\wait_bypass_count[0]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \wait_bypass_count[0]_i_5 (.I0(wait_bypass_count_reg[0]), .O(\wait_bypass_count[0]_i_5_n_0 )); LUT4 #( .INIT(16'hFFDF)) \wait_bypass_count[0]_i_6 (.I0(wait_bypass_count_reg[4]), .I1(wait_bypass_count_reg[15]), .I2(wait_bypass_count_reg[14]), .I3(wait_bypass_count_reg[10]), .O(\wait_bypass_count[0]_i_6_n_0 )); LUT4 #( .INIT(16'hFF7F)) \wait_bypass_count[0]_i_7 (.I0(wait_bypass_count_reg[2]), .I1(wait_bypass_count_reg[9]), .I2(wait_bypass_count_reg[6]), .I3(wait_bypass_count_reg[11]), .O(\wait_bypass_count[0]_i_7_n_0 )); LUT6 #( .INIT(64'h0000800000000000)) \wait_bypass_count[0]_i_8 (.I0(wait_bypass_count_reg[5]), .I1(wait_bypass_count_reg[0]), .I2(wait_bypass_count_reg[3]), .I3(wait_bypass_count_reg[1]), .I4(wait_bypass_count_reg[8]), .I5(wait_bypass_count_reg[7]), .O(\wait_bypass_count[0]_i_8_n_0 )); FDRE \wait_bypass_count_reg[0] (.C(userclk), .CE(\wait_bypass_count[0]_i_2_n_0 ), .D(\wait_bypass_count_reg[0]_i_3_n_7 ), .Q(wait_bypass_count_reg[0]), .R(clear)); CARRY4 \wait_bypass_count_reg[0]_i_3 (.CI(1'b0), .CO({\wait_bypass_count_reg[0]_i_3_n_0 ,\wait_bypass_count_reg[0]_i_3_n_1 ,\wait_bypass_count_reg[0]_i_3_n_2 ,\wait_bypass_count_reg[0]_i_3_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b1}), .O({\wait_bypass_count_reg[0]_i_3_n_4 ,\wait_bypass_count_reg[0]_i_3_n_5 ,\wait_bypass_count_reg[0]_i_3_n_6 ,\wait_bypass_count_reg[0]_i_3_n_7 }), .S({wait_bypass_count_reg[3:1],\wait_bypass_count[0]_i_5_n_0 })); FDRE \wait_bypass_count_reg[10] (.C(userclk), .CE(\wait_bypass_count[0]_i_2_n_0 ), .D(\wait_bypass_count_reg[8]_i_1_n_5 ), .Q(wait_bypass_count_reg[10]), .R(clear)); FDRE \wait_bypass_count_reg[11] (.C(userclk), .CE(\wait_bypass_count[0]_i_2_n_0 ), .D(\wait_bypass_count_reg[8]_i_1_n_4 ), .Q(wait_bypass_count_reg[11]), .R(clear)); FDRE \wait_bypass_count_reg[12] (.C(userclk), .CE(\wait_bypass_count[0]_i_2_n_0 ), .D(\wait_bypass_count_reg[12]_i_1_n_7 ), .Q(wait_bypass_count_reg[12]), .R(clear)); CARRY4 \wait_bypass_count_reg[12]_i_1 (.CI(\wait_bypass_count_reg[8]_i_1_n_0 ), .CO({\wait_bypass_count_reg[12]_i_1_n_0 ,\wait_bypass_count_reg[12]_i_1_n_1 ,\wait_bypass_count_reg[12]_i_1_n_2 ,\wait_bypass_count_reg[12]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\wait_bypass_count_reg[12]_i_1_n_4 ,\wait_bypass_count_reg[12]_i_1_n_5 ,\wait_bypass_count_reg[12]_i_1_n_6 ,\wait_bypass_count_reg[12]_i_1_n_7 }), .S(wait_bypass_count_reg[15:12])); FDRE \wait_bypass_count_reg[13] (.C(userclk), .CE(\wait_bypass_count[0]_i_2_n_0 ), .D(\wait_bypass_count_reg[12]_i_1_n_6 ), .Q(wait_bypass_count_reg[13]), .R(clear)); FDRE \wait_bypass_count_reg[14] (.C(userclk), .CE(\wait_bypass_count[0]_i_2_n_0 ), .D(\wait_bypass_count_reg[12]_i_1_n_5 ), .Q(wait_bypass_count_reg[14]), .R(clear)); FDRE \wait_bypass_count_reg[15] (.C(userclk), .CE(\wait_bypass_count[0]_i_2_n_0 ), .D(\wait_bypass_count_reg[12]_i_1_n_4 ), .Q(wait_bypass_count_reg[15]), .R(clear)); FDRE \wait_bypass_count_reg[16] (.C(userclk), .CE(\wait_bypass_count[0]_i_2_n_0 ), .D(\wait_bypass_count_reg[16]_i_1_n_7 ), .Q(wait_bypass_count_reg[16]), .R(clear)); CARRY4 \wait_bypass_count_reg[16]_i_1 (.CI(\wait_bypass_count_reg[12]_i_1_n_0 ), .CO(\NLW_wait_bypass_count_reg[16]_i_1_CO_UNCONNECTED [3:0]), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\NLW_wait_bypass_count_reg[16]_i_1_O_UNCONNECTED [3:1],\wait_bypass_count_reg[16]_i_1_n_7 }), .S({1'b0,1'b0,1'b0,wait_bypass_count_reg[16]})); FDRE \wait_bypass_count_reg[1] (.C(userclk), .CE(\wait_bypass_count[0]_i_2_n_0 ), .D(\wait_bypass_count_reg[0]_i_3_n_6 ), .Q(wait_bypass_count_reg[1]), .R(clear)); FDRE \wait_bypass_count_reg[2] (.C(userclk), .CE(\wait_bypass_count[0]_i_2_n_0 ), .D(\wait_bypass_count_reg[0]_i_3_n_5 ), .Q(wait_bypass_count_reg[2]), .R(clear)); FDRE \wait_bypass_count_reg[3] (.C(userclk), .CE(\wait_bypass_count[0]_i_2_n_0 ), .D(\wait_bypass_count_reg[0]_i_3_n_4 ), .Q(wait_bypass_count_reg[3]), .R(clear)); FDRE \wait_bypass_count_reg[4] (.C(userclk), .CE(\wait_bypass_count[0]_i_2_n_0 ), .D(\wait_bypass_count_reg[4]_i_1_n_7 ), .Q(wait_bypass_count_reg[4]), .R(clear)); CARRY4 \wait_bypass_count_reg[4]_i_1 (.CI(\wait_bypass_count_reg[0]_i_3_n_0 ), .CO({\wait_bypass_count_reg[4]_i_1_n_0 ,\wait_bypass_count_reg[4]_i_1_n_1 ,\wait_bypass_count_reg[4]_i_1_n_2 ,\wait_bypass_count_reg[4]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\wait_bypass_count_reg[4]_i_1_n_4 ,\wait_bypass_count_reg[4]_i_1_n_5 ,\wait_bypass_count_reg[4]_i_1_n_6 ,\wait_bypass_count_reg[4]_i_1_n_7 }), .S(wait_bypass_count_reg[7:4])); FDRE \wait_bypass_count_reg[5] (.C(userclk), .CE(\wait_bypass_count[0]_i_2_n_0 ), .D(\wait_bypass_count_reg[4]_i_1_n_6 ), .Q(wait_bypass_count_reg[5]), .R(clear)); FDRE \wait_bypass_count_reg[6] (.C(userclk), .CE(\wait_bypass_count[0]_i_2_n_0 ), .D(\wait_bypass_count_reg[4]_i_1_n_5 ), .Q(wait_bypass_count_reg[6]), .R(clear)); FDRE \wait_bypass_count_reg[7] (.C(userclk), .CE(\wait_bypass_count[0]_i_2_n_0 ), .D(\wait_bypass_count_reg[4]_i_1_n_4 ), .Q(wait_bypass_count_reg[7]), .R(clear)); FDRE \wait_bypass_count_reg[8] (.C(userclk), .CE(\wait_bypass_count[0]_i_2_n_0 ), .D(\wait_bypass_count_reg[8]_i_1_n_7 ), .Q(wait_bypass_count_reg[8]), .R(clear)); CARRY4 \wait_bypass_count_reg[8]_i_1 (.CI(\wait_bypass_count_reg[4]_i_1_n_0 ), .CO({\wait_bypass_count_reg[8]_i_1_n_0 ,\wait_bypass_count_reg[8]_i_1_n_1 ,\wait_bypass_count_reg[8]_i_1_n_2 ,\wait_bypass_count_reg[8]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\wait_bypass_count_reg[8]_i_1_n_4 ,\wait_bypass_count_reg[8]_i_1_n_5 ,\wait_bypass_count_reg[8]_i_1_n_6 ,\wait_bypass_count_reg[8]_i_1_n_7 }), .S(wait_bypass_count_reg[11:8])); FDRE \wait_bypass_count_reg[9] (.C(userclk), .CE(\wait_bypass_count[0]_i_2_n_0 ), .D(\wait_bypass_count_reg[8]_i_1_n_6 ), .Q(wait_bypass_count_reg[9]), .R(clear)); (* SOFT_HLUTNM = "soft_lutpair73" *) LUT1 #( .INIT(2'h1)) \wait_time_cnt[0]_i_1 (.I0(wait_time_cnt_reg__0[0]), .O(wait_time_cnt0)); (* SOFT_HLUTNM = "soft_lutpair73" *) LUT2 #( .INIT(4'h9)) \wait_time_cnt[1]_i_1 (.I0(wait_time_cnt_reg__0[0]), .I1(wait_time_cnt_reg__0[1]), .O(\wait_time_cnt[1]_i_1_n_0 )); LUT3 #( .INIT(8'hE1)) \wait_time_cnt[2]_i_1 (.I0(wait_time_cnt_reg__0[1]), .I1(wait_time_cnt_reg__0[0]), .I2(wait_time_cnt_reg__0[2]), .O(\wait_time_cnt[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair67" *) LUT4 #( .INIT(16'hFE01)) \wait_time_cnt[3]_i_1 (.I0(wait_time_cnt_reg__0[2]), .I1(wait_time_cnt_reg__0[0]), .I2(wait_time_cnt_reg__0[1]), .I3(wait_time_cnt_reg__0[3]), .O(\wait_time_cnt[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair67" *) LUT5 #( .INIT(32'hFFFE0001)) \wait_time_cnt[4]_i_1 (.I0(wait_time_cnt_reg__0[3]), .I1(wait_time_cnt_reg__0[1]), .I2(wait_time_cnt_reg__0[0]), .I3(wait_time_cnt_reg__0[2]), .I4(wait_time_cnt_reg__0[4]), .O(\wait_time_cnt[4]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFE00000001)) \wait_time_cnt[5]_i_1 (.I0(wait_time_cnt_reg__0[4]), .I1(wait_time_cnt_reg__0[2]), .I2(wait_time_cnt_reg__0[0]), .I3(wait_time_cnt_reg__0[1]), .I4(wait_time_cnt_reg__0[3]), .I5(wait_time_cnt_reg__0[5]), .O(\wait_time_cnt[5]_i_1_n_0 )); LUT4 #( .INIT(16'h0700)) \wait_time_cnt[6]_i_1__0 (.I0(tx_state[1]), .I1(tx_state[2]), .I2(tx_state[3]), .I3(tx_state[0]), .O(wait_time_cnt0_0)); LUT2 #( .INIT(4'hE)) \wait_time_cnt[6]_i_2 (.I0(\wait_time_cnt[6]_i_4_n_0 ), .I1(wait_time_cnt_reg__0[6]), .O(sel)); LUT2 #( .INIT(4'h9)) \wait_time_cnt[6]_i_3 (.I0(\wait_time_cnt[6]_i_4_n_0 ), .I1(wait_time_cnt_reg__0[6]), .O(\wait_time_cnt[6]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \wait_time_cnt[6]_i_4 (.I0(wait_time_cnt_reg__0[4]), .I1(wait_time_cnt_reg__0[2]), .I2(wait_time_cnt_reg__0[0]), .I3(wait_time_cnt_reg__0[1]), .I4(wait_time_cnt_reg__0[3]), .I5(wait_time_cnt_reg__0[5]), .O(\wait_time_cnt[6]_i_4_n_0 )); FDRE \wait_time_cnt_reg[0] (.C(independent_clock_bufg), .CE(sel), .D(wait_time_cnt0), .Q(wait_time_cnt_reg__0[0]), .R(wait_time_cnt0_0)); FDRE \wait_time_cnt_reg[1] (.C(independent_clock_bufg), .CE(sel), .D(\wait_time_cnt[1]_i_1_n_0 ), .Q(wait_time_cnt_reg__0[1]), .R(wait_time_cnt0_0)); FDSE \wait_time_cnt_reg[2] (.C(independent_clock_bufg), .CE(sel), .D(\wait_time_cnt[2]_i_1_n_0 ), .Q(wait_time_cnt_reg__0[2]), .S(wait_time_cnt0_0)); FDRE \wait_time_cnt_reg[3] (.C(independent_clock_bufg), .CE(sel), .D(\wait_time_cnt[3]_i_1_n_0 ), .Q(wait_time_cnt_reg__0[3]), .R(wait_time_cnt0_0)); FDRE \wait_time_cnt_reg[4] (.C(independent_clock_bufg), .CE(sel), .D(\wait_time_cnt[4]_i_1_n_0 ), .Q(wait_time_cnt_reg__0[4]), .R(wait_time_cnt0_0)); FDSE \wait_time_cnt_reg[5] (.C(independent_clock_bufg), .CE(sel), .D(\wait_time_cnt[5]_i_1_n_0 ), .Q(wait_time_cnt_reg__0[5]), .S(wait_time_cnt0_0)); FDSE \wait_time_cnt_reg[6] (.C(independent_clock_bufg), .CE(sel), .D(\wait_time_cnt[6]_i_3_n_0 ), .Q(wait_time_cnt_reg__0[6]), .S(wait_time_cnt0_0)); endmodule (* EXAMPLE_SIMULATION = "0" *) (* downgradeipidentifiedwarnings = "yes" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_block (gtrefclk, gtrefclk_bufg, txp, txn, rxp, rxn, txoutclk, rxoutclk, resetdone, cplllock, mmcm_reset, mmcm_locked, userclk, userclk2, rxuserclk, rxuserclk2, independent_clock_bufg, pma_reset, gmii_txd, gmii_tx_en, gmii_tx_er, gmii_rxd, gmii_rx_dv, gmii_rx_er, gmii_isolate, configuration_vector, status_vector, reset, signal_detect, gt0_qplloutclk_in, gt0_qplloutrefclk_in); input gtrefclk; input gtrefclk_bufg; output txp; output txn; input rxp; input rxn; output txoutclk; output rxoutclk; output resetdone; output cplllock; output mmcm_reset; input mmcm_locked; input userclk; input userclk2; input rxuserclk; input rxuserclk2; input independent_clock_bufg; input pma_reset; input [7:0]gmii_txd; input gmii_tx_en; input gmii_tx_er; output [7:0]gmii_rxd; output gmii_rx_dv; output gmii_rx_er; output gmii_isolate; input [4:0]configuration_vector; output [15:0]status_vector; input reset; input signal_detect; input gt0_qplloutclk_in; input gt0_qplloutrefclk_in; wire \ ; wire [4:0]configuration_vector; wire cplllock; wire enablealign; wire gmii_isolate; wire gmii_rx_dv; wire gmii_rx_er; wire [7:0]gmii_rxd; wire gmii_tx_en; wire gmii_tx_er; wire [7:0]gmii_txd; wire gt0_qplloutclk_in; wire gt0_qplloutrefclk_in; wire gtrefclk; wire gtrefclk_bufg; wire independent_clock_bufg; wire mgt_rx_reset; wire mgt_tx_reset; wire mmcm_locked; wire mmcm_reset; wire pma_reset; wire powerdown; wire reset; wire resetdone; wire rx_reset_done_i; wire rxbuferr; wire rxchariscomma; wire rxcharisk; wire [1:0]rxclkcorcnt; wire [7:0]rxdata; wire rxdisperr; wire rxn; wire rxnotintable; wire rxoutclk; wire rxp; wire signal_detect; wire [6:0]\^status_vector ; wire transceiver_inst_n_5; wire transceiver_inst_n_6; wire txbuferr; wire txchardispmode; wire txchardispval; wire txcharisk; wire [7:0]txdata; wire txn; wire txoutclk; wire txp; wire userclk; wire userclk2; wire NLW_gig_ethernet_pcs_pma_16_1_core_an_enable_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_16_1_core_an_interrupt_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_16_1_core_drp_den_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_16_1_core_drp_dwe_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_16_1_core_drp_req_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_16_1_core_en_cdet_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_16_1_core_ewrap_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_16_1_core_loc_ref_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_16_1_core_mdio_out_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_16_1_core_mdio_tri_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_16_1_core_s_axi_arready_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_16_1_core_s_axi_awready_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_16_1_core_s_axi_bvalid_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_16_1_core_s_axi_rvalid_UNCONNECTED; wire NLW_gig_ethernet_pcs_pma_16_1_core_s_axi_wready_UNCONNECTED; wire [9:0]NLW_gig_ethernet_pcs_pma_16_1_core_drp_daddr_UNCONNECTED; wire [15:0]NLW_gig_ethernet_pcs_pma_16_1_core_drp_di_UNCONNECTED; wire [63:0]NLW_gig_ethernet_pcs_pma_16_1_core_rxphy_correction_timer_UNCONNECTED; wire [31:0]NLW_gig_ethernet_pcs_pma_16_1_core_rxphy_ns_field_UNCONNECTED; wire [47:0]NLW_gig_ethernet_pcs_pma_16_1_core_rxphy_s_field_UNCONNECTED; wire [1:0]NLW_gig_ethernet_pcs_pma_16_1_core_s_axi_bresp_UNCONNECTED; wire [31:0]NLW_gig_ethernet_pcs_pma_16_1_core_s_axi_rdata_UNCONNECTED; wire [1:0]NLW_gig_ethernet_pcs_pma_16_1_core_s_axi_rresp_UNCONNECTED; wire [1:0]NLW_gig_ethernet_pcs_pma_16_1_core_speed_selection_UNCONNECTED; wire [15:7]NLW_gig_ethernet_pcs_pma_16_1_core_status_vector_UNCONNECTED; wire [9:0]NLW_gig_ethernet_pcs_pma_16_1_core_tx_code_group_UNCONNECTED; assign status_vector[15] = \ ; assign status_vector[14] = \ ; assign status_vector[13] = \ ; assign status_vector[12] = \ ; assign status_vector[11] = \ ; assign status_vector[10] = \ ; assign status_vector[9] = \ ; assign status_vector[8] = \ ; assign status_vector[7] = \ ; assign status_vector[6:0] = \^status_vector [6:0]; GND GND (.G(\ )); (* B_SHIFTER_ADDR = "10'b0101001110" *) (* C_1588 = "0" *) (* C_2_5G = "FALSE" *) (* C_COMPONENT_NAME = "gig_ethernet_pcs_pma_16_1" *) (* C_DYNAMIC_SWITCHING = "FALSE" *) (* C_ELABORATION_TRANSIENT_DIR = "BlankString" *) (* C_FAMILY = "kintex7" *) (* C_HAS_AN = "FALSE" *) (* C_HAS_AXIL = "FALSE" *) (* C_HAS_MDIO = "FALSE" *) (* C_HAS_TEMAC = "TRUE" *) (* C_IS_SGMII = "FALSE" *) (* C_RX_GMII_CLK = "TXOUTCLK" *) (* C_SGMII_FABRIC_BUFFER = "TRUE" *) (* C_SGMII_PHY_MODE = "FALSE" *) (* C_USE_LVDS = "FALSE" *) (* C_USE_TBI = "FALSE" *) (* C_USE_TRANSCEIVER = "TRUE" *) (* GT_RX_BYTE_WIDTH = "1" *) (* downgradeipidentifiedwarnings = "yes" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_v16_1_5 gig_ethernet_pcs_pma_16_1_core (.an_adv_config_val(1'b0), .an_adv_config_vector({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .an_enable(NLW_gig_ethernet_pcs_pma_16_1_core_an_enable_UNCONNECTED), .an_interrupt(NLW_gig_ethernet_pcs_pma_16_1_core_an_interrupt_UNCONNECTED), .an_restart_config(1'b0), .basex_or_sgmii(1'b0), .configuration_valid(1'b0), .configuration_vector({1'b0,configuration_vector[3:1],1'b0}), .correction_timer({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .dcm_locked(mmcm_locked), .drp_daddr(NLW_gig_ethernet_pcs_pma_16_1_core_drp_daddr_UNCONNECTED[9:0]), .drp_dclk(1'b0), .drp_den(NLW_gig_ethernet_pcs_pma_16_1_core_drp_den_UNCONNECTED), .drp_di(NLW_gig_ethernet_pcs_pma_16_1_core_drp_di_UNCONNECTED[15:0]), .drp_do({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .drp_drdy(1'b0), .drp_dwe(NLW_gig_ethernet_pcs_pma_16_1_core_drp_dwe_UNCONNECTED), .drp_gnt(1'b0), .drp_req(NLW_gig_ethernet_pcs_pma_16_1_core_drp_req_UNCONNECTED), .en_cdet(NLW_gig_ethernet_pcs_pma_16_1_core_en_cdet_UNCONNECTED), .enablealign(enablealign), .ewrap(NLW_gig_ethernet_pcs_pma_16_1_core_ewrap_UNCONNECTED), .gmii_isolate(gmii_isolate), .gmii_rx_dv(gmii_rx_dv), .gmii_rx_er(gmii_rx_er), .gmii_rxd(gmii_rxd), .gmii_tx_en(gmii_tx_en), .gmii_tx_er(gmii_tx_er), .gmii_txd(gmii_txd), .gtx_clk(1'b0), .link_timer_basex({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .link_timer_sgmii({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .link_timer_value({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .loc_ref(NLW_gig_ethernet_pcs_pma_16_1_core_loc_ref_UNCONNECTED), .mdc(1'b0), .mdio_in(1'b0), .mdio_out(NLW_gig_ethernet_pcs_pma_16_1_core_mdio_out_UNCONNECTED), .mdio_tri(NLW_gig_ethernet_pcs_pma_16_1_core_mdio_tri_UNCONNECTED), .mgt_rx_reset(mgt_rx_reset), .mgt_tx_reset(mgt_tx_reset), .phyad({1'b0,1'b0,1'b0,1'b0,1'b0}), .pma_rx_clk0(1'b0), .pma_rx_clk1(1'b0), .powerdown(powerdown), .reset(reset), .reset_done(resetdone), .rx_code_group0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .rx_code_group1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .rx_gt_nominal_latency({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,1'b1,1'b1,1'b1,1'b1,1'b0,1'b0,1'b0}), .rxbufstatus({rxbuferr,1'b0}), .rxchariscomma(rxchariscomma), .rxcharisk(rxcharisk), .rxclkcorcnt({1'b0,rxclkcorcnt}), .rxdata(rxdata), .rxdisperr(rxdisperr), .rxnotintable(rxnotintable), .rxphy_correction_timer(NLW_gig_ethernet_pcs_pma_16_1_core_rxphy_correction_timer_UNCONNECTED[63:0]), .rxphy_ns_field(NLW_gig_ethernet_pcs_pma_16_1_core_rxphy_ns_field_UNCONNECTED[31:0]), .rxphy_s_field(NLW_gig_ethernet_pcs_pma_16_1_core_rxphy_s_field_UNCONNECTED[47:0]), .rxrecclk(1'b0), .rxrundisp(1'b0), .s_axi_aclk(1'b0), .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_arready(NLW_gig_ethernet_pcs_pma_16_1_core_s_axi_arready_UNCONNECTED), .s_axi_arvalid(1'b0), .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_awready(NLW_gig_ethernet_pcs_pma_16_1_core_s_axi_awready_UNCONNECTED), .s_axi_awvalid(1'b0), .s_axi_bready(1'b0), .s_axi_bresp(NLW_gig_ethernet_pcs_pma_16_1_core_s_axi_bresp_UNCONNECTED[1:0]), .s_axi_bvalid(NLW_gig_ethernet_pcs_pma_16_1_core_s_axi_bvalid_UNCONNECTED), .s_axi_rdata(NLW_gig_ethernet_pcs_pma_16_1_core_s_axi_rdata_UNCONNECTED[31:0]), .s_axi_resetn(1'b0), .s_axi_rready(1'b0), .s_axi_rresp(NLW_gig_ethernet_pcs_pma_16_1_core_s_axi_rresp_UNCONNECTED[1:0]), .s_axi_rvalid(NLW_gig_ethernet_pcs_pma_16_1_core_s_axi_rvalid_UNCONNECTED), .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_wready(NLW_gig_ethernet_pcs_pma_16_1_core_s_axi_wready_UNCONNECTED), .s_axi_wvalid(1'b0), .signal_detect(signal_detect), .speed_is_100(1'b0), .speed_is_10_100(1'b0), .speed_selection(NLW_gig_ethernet_pcs_pma_16_1_core_speed_selection_UNCONNECTED[1:0]), .status_vector({NLW_gig_ethernet_pcs_pma_16_1_core_status_vector_UNCONNECTED[15:7],\^status_vector }), .systemtimer_ns_field({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .systemtimer_s_field({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .tx_code_group(NLW_gig_ethernet_pcs_pma_16_1_core_tx_code_group_UNCONNECTED[9:0]), .txbuferr(txbuferr), .txchardispmode(txchardispmode), .txchardispval(txchardispval), .txcharisk(txcharisk), .txdata(txdata), .userclk(1'b0), .userclk2(userclk2)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block sync_block_rx_reset_done (.data_in(transceiver_inst_n_6), .data_out(rx_reset_done_i), .userclk2(userclk2)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_0 sync_block_tx_reset_done (.data_in(transceiver_inst_n_5), .resetdone(resetdone), .resetdone_0(rx_reset_done_i), .userclk2(userclk2)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_transceiver transceiver_inst (.D(txchardispmode), .Q(rxclkcorcnt), .SR(mgt_tx_reset), .cplllock(cplllock), .data_in(transceiver_inst_n_5), .enablealign(enablealign), .gt0_qplloutclk_in(gt0_qplloutclk_in), .gt0_qplloutrefclk_in(gt0_qplloutrefclk_in), .gtrefclk(gtrefclk), .gtrefclk_bufg(gtrefclk_bufg), .independent_clock_bufg(independent_clock_bufg), .mmcm_locked(mmcm_locked), .mmcm_reset(mmcm_reset), .pma_reset(pma_reset), .powerdown(powerdown), .reset_sync5(mgt_rx_reset), .rx_fsm_reset_done_int_reg(transceiver_inst_n_6), .rxbuferr(rxbuferr), .rxchariscomma(rxchariscomma), .rxcharisk(rxcharisk), .\rxdata_reg[7]_0 (rxdata), .rxdisperr(rxdisperr), .rxn(rxn), .rxnotintable(rxnotintable), .rxoutclk(rxoutclk), .rxp(rxp), .status_vector(\^status_vector [1]), .txbuferr(txbuferr), .txchardispval_reg_reg_0(txchardispval), .txcharisk_reg_reg_0(txcharisk), .\txdata_reg_reg[7]_0 (txdata), .txn(txn), .txoutclk(txoutclk), .txp(txp), .userclk(userclk), .userclk2(userclk2)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_cpll_railing (cpll_pd0_i, cpllreset_in, gtrefclk_bufg, gt0_cpllreset_t); output cpll_pd0_i; output cpllreset_in; input gtrefclk_bufg; input gt0_cpllreset_t; wire cpll_pd0_i; wire cpll_reset_out; wire \cpllpd_wait_reg[31]_srl32_n_1 ; wire \cpllpd_wait_reg[63]_srl32_n_1 ; wire \cpllpd_wait_reg[94]_srl31_n_0 ; wire cpllreset_in; wire \cpllreset_wait_reg[126]_srl31_n_0 ; wire \cpllreset_wait_reg[31]_srl32_n_1 ; wire \cpllreset_wait_reg[63]_srl32_n_1 ; wire \cpllreset_wait_reg[95]_srl32_n_1 ; wire gt0_cpllreset_t; wire gtrefclk_bufg; wire \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ; wire \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ; wire \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ; wire \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ; wire \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ; wire \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ; wire \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ; (* srl_bus_name = "U0/\transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg " *) (* srl_name = "U0/\transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32 " *) SRLC32E #( .INIT(32'hFFFFFFFF)) \cpllpd_wait_reg[31]_srl32 (.A({1'b1,1'b1,1'b1,1'b1,1'b1}), .CE(1'b1), .CLK(gtrefclk_bufg), .D(1'b0), .Q(\NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ), .Q31(\cpllpd_wait_reg[31]_srl32_n_1 )); (* srl_bus_name = "U0/\transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg " *) (* srl_name = "U0/\transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32 " *) SRLC32E #( .INIT(32'hFFFFFFFF)) \cpllpd_wait_reg[63]_srl32 (.A({1'b1,1'b1,1'b1,1'b1,1'b1}), .CE(1'b1), .CLK(gtrefclk_bufg), .D(\cpllpd_wait_reg[31]_srl32_n_1 ), .Q(\NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ), .Q31(\cpllpd_wait_reg[63]_srl32_n_1 )); (* srl_bus_name = "U0/\transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg " *) (* srl_name = "U0/\transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31 " *) SRLC32E #( .INIT(32'h7FFFFFFF)) \cpllpd_wait_reg[94]_srl31 (.A({1'b1,1'b1,1'b1,1'b1,1'b0}), .CE(1'b1), .CLK(gtrefclk_bufg), .D(\cpllpd_wait_reg[63]_srl32_n_1 ), .Q(\cpllpd_wait_reg[94]_srl31_n_0 ), .Q31(\NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED )); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b1)) \cpllpd_wait_reg[95] (.C(gtrefclk_bufg), .CE(1'b1), .D(\cpllpd_wait_reg[94]_srl31_n_0 ), .Q(cpll_pd0_i), .R(1'b0)); (* srl_bus_name = "U0/\transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg " *) (* srl_name = "U0/\transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31 " *) SRLC32E #( .INIT(32'h00000000)) \cpllreset_wait_reg[126]_srl31 (.A({1'b1,1'b1,1'b1,1'b1,1'b0}), .CE(1'b1), .CLK(gtrefclk_bufg), .D(\cpllreset_wait_reg[95]_srl32_n_1 ), .Q(\cpllreset_wait_reg[126]_srl31_n_0 ), .Q31(\NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED )); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \cpllreset_wait_reg[127] (.C(gtrefclk_bufg), .CE(1'b1), .D(\cpllreset_wait_reg[126]_srl31_n_0 ), .Q(cpll_reset_out), .R(1'b0)); (* srl_bus_name = "U0/\transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg " *) (* srl_name = "U0/\transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[31]_srl32 " *) SRLC32E #( .INIT(32'h000000FF)) \cpllreset_wait_reg[31]_srl32 (.A({1'b1,1'b1,1'b1,1'b1,1'b1}), .CE(1'b1), .CLK(gtrefclk_bufg), .D(1'b0), .Q(\NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ), .Q31(\cpllreset_wait_reg[31]_srl32_n_1 )); (* srl_bus_name = "U0/\transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg " *) (* srl_name = "U0/\transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \cpllreset_wait_reg[63]_srl32 (.A({1'b1,1'b1,1'b1,1'b1,1'b1}), .CE(1'b1), .CLK(gtrefclk_bufg), .D(\cpllreset_wait_reg[31]_srl32_n_1 ), .Q(\NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ), .Q31(\cpllreset_wait_reg[63]_srl32_n_1 )); (* srl_bus_name = "U0/\transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg " *) (* srl_name = "U0/\transceiver_inst/gtwizard_inst/U0/gtwizard_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \cpllreset_wait_reg[95]_srl32 (.A({1'b1,1'b1,1'b1,1'b1,1'b1}), .CE(1'b1), .CLK(gtrefclk_bufg), .D(\cpllreset_wait_reg[63]_srl32_n_1 ), .Q(\NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ), .Q31(\cpllreset_wait_reg[95]_srl32_n_1 )); LUT2 #( .INIT(4'hE)) gtxe2_i_i_1 (.I0(cpll_reset_out), .I1(gt0_cpllreset_t), .O(cpllreset_in)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_reset_sync (reset_out, userclk, enablealign); output reset_out; input userclk; input enablealign; wire enablealign; wire reset_out; wire reset_sync_reg1; wire reset_sync_reg2; wire reset_sync_reg3; wire reset_sync_reg4; wire reset_sync_reg5; wire userclk; (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync1 (.C(userclk), .CE(1'b1), .D(1'b0), .PRE(enablealign), .Q(reset_sync_reg1)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync2 (.C(userclk), .CE(1'b1), .D(reset_sync_reg1), .PRE(enablealign), .Q(reset_sync_reg2)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync3 (.C(userclk), .CE(1'b1), .D(reset_sync_reg2), .PRE(enablealign), .Q(reset_sync_reg3)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync4 (.C(userclk), .CE(1'b1), .D(reset_sync_reg3), .PRE(enablealign), .Q(reset_sync_reg4)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync5 (.C(userclk), .CE(1'b1), .D(reset_sync_reg4), .PRE(enablealign), .Q(reset_sync_reg5)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync6 (.C(userclk), .CE(1'b1), .D(reset_sync_reg5), .PRE(1'b0), .Q(reset_out)); endmodule (* ORIG_REF_NAME = "gig_ethernet_pcs_pma_16_1_reset_sync" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_reset_sync_1 (reset_out, independent_clock_bufg, reset_sync5_0); output reset_out; input independent_clock_bufg; input [0:0]reset_sync5_0; wire independent_clock_bufg; wire reset_out; wire [0:0]reset_sync5_0; wire reset_sync_reg1; wire reset_sync_reg2; wire reset_sync_reg3; wire reset_sync_reg4; wire reset_sync_reg5; (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync1 (.C(independent_clock_bufg), .CE(1'b1), .D(1'b0), .PRE(reset_sync5_0), .Q(reset_sync_reg1)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync2 (.C(independent_clock_bufg), .CE(1'b1), .D(reset_sync_reg1), .PRE(reset_sync5_0), .Q(reset_sync_reg2)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync3 (.C(independent_clock_bufg), .CE(1'b1), .D(reset_sync_reg2), .PRE(reset_sync5_0), .Q(reset_sync_reg3)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync4 (.C(independent_clock_bufg), .CE(1'b1), .D(reset_sync_reg3), .PRE(reset_sync5_0), .Q(reset_sync_reg4)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync5 (.C(independent_clock_bufg), .CE(1'b1), .D(reset_sync_reg4), .PRE(reset_sync5_0), .Q(reset_sync_reg5)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync6 (.C(independent_clock_bufg), .CE(1'b1), .D(reset_sync_reg5), .PRE(1'b0), .Q(reset_out)); endmodule (* ORIG_REF_NAME = "gig_ethernet_pcs_pma_16_1_reset_sync" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_reset_sync_2 (reset_out, independent_clock_bufg, SR); output reset_out; input independent_clock_bufg; input [0:0]SR; wire [0:0]SR; wire independent_clock_bufg; wire reset_out; wire reset_sync_reg1; wire reset_sync_reg2; wire reset_sync_reg3; wire reset_sync_reg4; wire reset_sync_reg5; (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync1 (.C(independent_clock_bufg), .CE(1'b1), .D(1'b0), .PRE(SR), .Q(reset_sync_reg1)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync2 (.C(independent_clock_bufg), .CE(1'b1), .D(reset_sync_reg1), .PRE(SR), .Q(reset_sync_reg2)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync3 (.C(independent_clock_bufg), .CE(1'b1), .D(reset_sync_reg2), .PRE(SR), .Q(reset_sync_reg3)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync4 (.C(independent_clock_bufg), .CE(1'b1), .D(reset_sync_reg3), .PRE(SR), .Q(reset_sync_reg4)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync5 (.C(independent_clock_bufg), .CE(1'b1), .D(reset_sync_reg4), .PRE(SR), .Q(reset_sync_reg5)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync6 (.C(independent_clock_bufg), .CE(1'b1), .D(reset_sync_reg5), .PRE(1'b0), .Q(reset_out)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_reset_wtd_timer (reset, independent_clock_bufg, data_out); output reset; input independent_clock_bufg; input data_out; wire \counter_stg1[5]_i_1_n_0 ; wire \counter_stg1[5]_i_3_n_0 ; wire [5:5]counter_stg1_reg__0; wire [4:0]counter_stg1_reg__0__0; wire \counter_stg2[0]_i_3_n_0 ; wire [11:0]counter_stg2_reg; wire \counter_stg2_reg[0]_i_2_n_0 ; wire \counter_stg2_reg[0]_i_2_n_1 ; wire \counter_stg2_reg[0]_i_2_n_2 ; wire \counter_stg2_reg[0]_i_2_n_3 ; wire \counter_stg2_reg[0]_i_2_n_4 ; wire \counter_stg2_reg[0]_i_2_n_5 ; wire \counter_stg2_reg[0]_i_2_n_6 ; wire \counter_stg2_reg[0]_i_2_n_7 ; wire \counter_stg2_reg[4]_i_1_n_0 ; wire \counter_stg2_reg[4]_i_1_n_1 ; wire \counter_stg2_reg[4]_i_1_n_2 ; wire \counter_stg2_reg[4]_i_1_n_3 ; wire \counter_stg2_reg[4]_i_1_n_4 ; wire \counter_stg2_reg[4]_i_1_n_5 ; wire \counter_stg2_reg[4]_i_1_n_6 ; wire \counter_stg2_reg[4]_i_1_n_7 ; wire \counter_stg2_reg[8]_i_1_n_1 ; wire \counter_stg2_reg[8]_i_1_n_2 ; wire \counter_stg2_reg[8]_i_1_n_3 ; wire \counter_stg2_reg[8]_i_1_n_4 ; wire \counter_stg2_reg[8]_i_1_n_5 ; wire \counter_stg2_reg[8]_i_1_n_6 ; wire \counter_stg2_reg[8]_i_1_n_7 ; wire counter_stg30; wire \counter_stg3[0]_i_3_n_0 ; wire \counter_stg3[0]_i_4_n_0 ; wire \counter_stg3[0]_i_5_n_0 ; wire [11:0]counter_stg3_reg; wire \counter_stg3_reg[0]_i_2_n_0 ; wire \counter_stg3_reg[0]_i_2_n_1 ; wire \counter_stg3_reg[0]_i_2_n_2 ; wire \counter_stg3_reg[0]_i_2_n_3 ; wire \counter_stg3_reg[0]_i_2_n_4 ; wire \counter_stg3_reg[0]_i_2_n_5 ; wire \counter_stg3_reg[0]_i_2_n_6 ; wire \counter_stg3_reg[0]_i_2_n_7 ; wire \counter_stg3_reg[4]_i_1_n_0 ; wire \counter_stg3_reg[4]_i_1_n_1 ; wire \counter_stg3_reg[4]_i_1_n_2 ; wire \counter_stg3_reg[4]_i_1_n_3 ; wire \counter_stg3_reg[4]_i_1_n_4 ; wire \counter_stg3_reg[4]_i_1_n_5 ; wire \counter_stg3_reg[4]_i_1_n_6 ; wire \counter_stg3_reg[4]_i_1_n_7 ; wire \counter_stg3_reg[8]_i_1_n_1 ; wire \counter_stg3_reg[8]_i_1_n_2 ; wire \counter_stg3_reg[8]_i_1_n_3 ; wire \counter_stg3_reg[8]_i_1_n_4 ; wire \counter_stg3_reg[8]_i_1_n_5 ; wire \counter_stg3_reg[8]_i_1_n_6 ; wire \counter_stg3_reg[8]_i_1_n_7 ; wire data_out; wire eqOp; wire independent_clock_bufg; wire [5:0]plusOp; wire reset; wire reset0; wire reset_i_2_n_0; wire reset_i_3_n_0; wire reset_i_4_n_0; wire reset_i_5_n_0; wire reset_i_6_n_0; wire [3:3]\NLW_counter_stg2_reg[8]_i_1_CO_UNCONNECTED ; wire [3:3]\NLW_counter_stg3_reg[8]_i_1_CO_UNCONNECTED ; (* SOFT_HLUTNM = "soft_lutpair76" *) LUT1 #( .INIT(2'h1)) \counter_stg1[0]_i_1 (.I0(counter_stg1_reg__0__0[0]), .O(plusOp[0])); (* SOFT_HLUTNM = "soft_lutpair76" *) LUT2 #( .INIT(4'h6)) \counter_stg1[1]_i_1 (.I0(counter_stg1_reg__0__0[0]), .I1(counter_stg1_reg__0__0[1]), .O(plusOp[1])); (* SOFT_HLUTNM = "soft_lutpair75" *) LUT3 #( .INIT(8'h78)) \counter_stg1[2]_i_1 (.I0(counter_stg1_reg__0__0[1]), .I1(counter_stg1_reg__0__0[0]), .I2(counter_stg1_reg__0__0[2]), .O(plusOp[2])); (* SOFT_HLUTNM = "soft_lutpair75" *) LUT4 #( .INIT(16'h7F80)) \counter_stg1[3]_i_1 (.I0(counter_stg1_reg__0__0[2]), .I1(counter_stg1_reg__0__0[0]), .I2(counter_stg1_reg__0__0[1]), .I3(counter_stg1_reg__0__0[3]), .O(plusOp[3])); (* SOFT_HLUTNM = "soft_lutpair74" *) LUT5 #( .INIT(32'h7FFF8000)) \counter_stg1[4]_i_1 (.I0(counter_stg1_reg__0__0[3]), .I1(counter_stg1_reg__0__0[1]), .I2(counter_stg1_reg__0__0[0]), .I3(counter_stg1_reg__0__0[2]), .I4(counter_stg1_reg__0__0[4]), .O(plusOp[4])); LUT5 #( .INIT(32'hFFFF2000)) \counter_stg1[5]_i_1 (.I0(reset_i_2_n_0), .I1(counter_stg3_reg[0]), .I2(reset_i_3_n_0), .I3(\counter_stg1[5]_i_3_n_0 ), .I4(data_out), .O(\counter_stg1[5]_i_1_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \counter_stg1[5]_i_2 (.I0(counter_stg1_reg__0__0[4]), .I1(counter_stg1_reg__0__0[2]), .I2(counter_stg1_reg__0__0[0]), .I3(counter_stg1_reg__0__0[1]), .I4(counter_stg1_reg__0__0[3]), .I5(counter_stg1_reg__0), .O(plusOp[5])); (* SOFT_HLUTNM = "soft_lutpair74" *) LUT5 #( .INIT(32'h80000000)) \counter_stg1[5]_i_3 (.I0(counter_stg1_reg__0__0[3]), .I1(counter_stg1_reg__0__0[1]), .I2(counter_stg1_reg__0__0[0]), .I3(counter_stg1_reg__0__0[2]), .I4(counter_stg1_reg__0__0[4]), .O(\counter_stg1[5]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \counter_stg1_reg[0] (.C(independent_clock_bufg), .CE(1'b1), .D(plusOp[0]), .Q(counter_stg1_reg__0__0[0]), .R(\counter_stg1[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \counter_stg1_reg[1] (.C(independent_clock_bufg), .CE(1'b1), .D(plusOp[1]), .Q(counter_stg1_reg__0__0[1]), .R(\counter_stg1[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \counter_stg1_reg[2] (.C(independent_clock_bufg), .CE(1'b1), .D(plusOp[2]), .Q(counter_stg1_reg__0__0[2]), .R(\counter_stg1[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \counter_stg1_reg[3] (.C(independent_clock_bufg), .CE(1'b1), .D(plusOp[3]), .Q(counter_stg1_reg__0__0[3]), .R(\counter_stg1[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \counter_stg1_reg[4] (.C(independent_clock_bufg), .CE(1'b1), .D(plusOp[4]), .Q(counter_stg1_reg__0__0[4]), .R(\counter_stg1[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \counter_stg1_reg[5] (.C(independent_clock_bufg), .CE(1'b1), .D(plusOp[5]), .Q(counter_stg1_reg__0), .R(\counter_stg1[5]_i_1_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \counter_stg2[0]_i_1 (.I0(counter_stg1_reg__0__0[4]), .I1(counter_stg1_reg__0__0[2]), .I2(counter_stg1_reg__0__0[0]), .I3(counter_stg1_reg__0__0[1]), .I4(counter_stg1_reg__0__0[3]), .I5(counter_stg1_reg__0), .O(eqOp)); LUT1 #( .INIT(2'h1)) \counter_stg2[0]_i_3 (.I0(counter_stg2_reg[0]), .O(\counter_stg2[0]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \counter_stg2_reg[0] (.C(independent_clock_bufg), .CE(eqOp), .D(\counter_stg2_reg[0]_i_2_n_7 ), .Q(counter_stg2_reg[0]), .R(\counter_stg1[5]_i_1_n_0 )); CARRY4 \counter_stg2_reg[0]_i_2 (.CI(1'b0), .CO({\counter_stg2_reg[0]_i_2_n_0 ,\counter_stg2_reg[0]_i_2_n_1 ,\counter_stg2_reg[0]_i_2_n_2 ,\counter_stg2_reg[0]_i_2_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b1}), .O({\counter_stg2_reg[0]_i_2_n_4 ,\counter_stg2_reg[0]_i_2_n_5 ,\counter_stg2_reg[0]_i_2_n_6 ,\counter_stg2_reg[0]_i_2_n_7 }), .S({counter_stg2_reg[3:1],\counter_stg2[0]_i_3_n_0 })); FDRE #( .INIT(1'b0)) \counter_stg2_reg[10] (.C(independent_clock_bufg), .CE(eqOp), .D(\counter_stg2_reg[8]_i_1_n_5 ), .Q(counter_stg2_reg[10]), .R(\counter_stg1[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \counter_stg2_reg[11] (.C(independent_clock_bufg), .CE(eqOp), .D(\counter_stg2_reg[8]_i_1_n_4 ), .Q(counter_stg2_reg[11]), .R(\counter_stg1[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \counter_stg2_reg[1] (.C(independent_clock_bufg), .CE(eqOp), .D(\counter_stg2_reg[0]_i_2_n_6 ), .Q(counter_stg2_reg[1]), .R(\counter_stg1[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \counter_stg2_reg[2] (.C(independent_clock_bufg), .CE(eqOp), .D(\counter_stg2_reg[0]_i_2_n_5 ), .Q(counter_stg2_reg[2]), .R(\counter_stg1[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \counter_stg2_reg[3] (.C(independent_clock_bufg), .CE(eqOp), .D(\counter_stg2_reg[0]_i_2_n_4 ), .Q(counter_stg2_reg[3]), .R(\counter_stg1[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \counter_stg2_reg[4] (.C(independent_clock_bufg), .CE(eqOp), .D(\counter_stg2_reg[4]_i_1_n_7 ), .Q(counter_stg2_reg[4]), .R(\counter_stg1[5]_i_1_n_0 )); CARRY4 \counter_stg2_reg[4]_i_1 (.CI(\counter_stg2_reg[0]_i_2_n_0 ), .CO({\counter_stg2_reg[4]_i_1_n_0 ,\counter_stg2_reg[4]_i_1_n_1 ,\counter_stg2_reg[4]_i_1_n_2 ,\counter_stg2_reg[4]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\counter_stg2_reg[4]_i_1_n_4 ,\counter_stg2_reg[4]_i_1_n_5 ,\counter_stg2_reg[4]_i_1_n_6 ,\counter_stg2_reg[4]_i_1_n_7 }), .S(counter_stg2_reg[7:4])); FDRE #( .INIT(1'b0)) \counter_stg2_reg[5] (.C(independent_clock_bufg), .CE(eqOp), .D(\counter_stg2_reg[4]_i_1_n_6 ), .Q(counter_stg2_reg[5]), .R(\counter_stg1[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \counter_stg2_reg[6] (.C(independent_clock_bufg), .CE(eqOp), .D(\counter_stg2_reg[4]_i_1_n_5 ), .Q(counter_stg2_reg[6]), .R(\counter_stg1[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \counter_stg2_reg[7] (.C(independent_clock_bufg), .CE(eqOp), .D(\counter_stg2_reg[4]_i_1_n_4 ), .Q(counter_stg2_reg[7]), .R(\counter_stg1[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \counter_stg2_reg[8] (.C(independent_clock_bufg), .CE(eqOp), .D(\counter_stg2_reg[8]_i_1_n_7 ), .Q(counter_stg2_reg[8]), .R(\counter_stg1[5]_i_1_n_0 )); CARRY4 \counter_stg2_reg[8]_i_1 (.CI(\counter_stg2_reg[4]_i_1_n_0 ), .CO({\NLW_counter_stg2_reg[8]_i_1_CO_UNCONNECTED [3],\counter_stg2_reg[8]_i_1_n_1 ,\counter_stg2_reg[8]_i_1_n_2 ,\counter_stg2_reg[8]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\counter_stg2_reg[8]_i_1_n_4 ,\counter_stg2_reg[8]_i_1_n_5 ,\counter_stg2_reg[8]_i_1_n_6 ,\counter_stg2_reg[8]_i_1_n_7 }), .S(counter_stg2_reg[11:8])); FDRE #( .INIT(1'b0)) \counter_stg2_reg[9] (.C(independent_clock_bufg), .CE(eqOp), .D(\counter_stg2_reg[8]_i_1_n_6 ), .Q(counter_stg2_reg[9]), .R(\counter_stg1[5]_i_1_n_0 )); LUT4 #( .INIT(16'h8000)) \counter_stg3[0]_i_1 (.I0(\counter_stg3[0]_i_3_n_0 ), .I1(\counter_stg3[0]_i_4_n_0 ), .I2(counter_stg2_reg[0]), .I3(\counter_stg1[5]_i_3_n_0 ), .O(counter_stg30)); LUT6 #( .INIT(64'h8000000000000000)) \counter_stg3[0]_i_3 (.I0(counter_stg2_reg[3]), .I1(counter_stg2_reg[4]), .I2(counter_stg2_reg[1]), .I3(counter_stg2_reg[2]), .I4(counter_stg2_reg[6]), .I5(counter_stg2_reg[5]), .O(\counter_stg3[0]_i_3_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \counter_stg3[0]_i_4 (.I0(counter_stg2_reg[9]), .I1(counter_stg2_reg[10]), .I2(counter_stg2_reg[7]), .I3(counter_stg2_reg[8]), .I4(counter_stg1_reg__0), .I5(counter_stg2_reg[11]), .O(\counter_stg3[0]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \counter_stg3[0]_i_5 (.I0(counter_stg3_reg[0]), .O(\counter_stg3[0]_i_5_n_0 )); FDRE #( .INIT(1'b0)) \counter_stg3_reg[0] (.C(independent_clock_bufg), .CE(counter_stg30), .D(\counter_stg3_reg[0]_i_2_n_7 ), .Q(counter_stg3_reg[0]), .R(\counter_stg1[5]_i_1_n_0 )); CARRY4 \counter_stg3_reg[0]_i_2 (.CI(1'b0), .CO({\counter_stg3_reg[0]_i_2_n_0 ,\counter_stg3_reg[0]_i_2_n_1 ,\counter_stg3_reg[0]_i_2_n_2 ,\counter_stg3_reg[0]_i_2_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b1}), .O({\counter_stg3_reg[0]_i_2_n_4 ,\counter_stg3_reg[0]_i_2_n_5 ,\counter_stg3_reg[0]_i_2_n_6 ,\counter_stg3_reg[0]_i_2_n_7 }), .S({counter_stg3_reg[3:1],\counter_stg3[0]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \counter_stg3_reg[10] (.C(independent_clock_bufg), .CE(counter_stg30), .D(\counter_stg3_reg[8]_i_1_n_5 ), .Q(counter_stg3_reg[10]), .R(\counter_stg1[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \counter_stg3_reg[11] (.C(independent_clock_bufg), .CE(counter_stg30), .D(\counter_stg3_reg[8]_i_1_n_4 ), .Q(counter_stg3_reg[11]), .R(\counter_stg1[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \counter_stg3_reg[1] (.C(independent_clock_bufg), .CE(counter_stg30), .D(\counter_stg3_reg[0]_i_2_n_6 ), .Q(counter_stg3_reg[1]), .R(\counter_stg1[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \counter_stg3_reg[2] (.C(independent_clock_bufg), .CE(counter_stg30), .D(\counter_stg3_reg[0]_i_2_n_5 ), .Q(counter_stg3_reg[2]), .R(\counter_stg1[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \counter_stg3_reg[3] (.C(independent_clock_bufg), .CE(counter_stg30), .D(\counter_stg3_reg[0]_i_2_n_4 ), .Q(counter_stg3_reg[3]), .R(\counter_stg1[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \counter_stg3_reg[4] (.C(independent_clock_bufg), .CE(counter_stg30), .D(\counter_stg3_reg[4]_i_1_n_7 ), .Q(counter_stg3_reg[4]), .R(\counter_stg1[5]_i_1_n_0 )); CARRY4 \counter_stg3_reg[4]_i_1 (.CI(\counter_stg3_reg[0]_i_2_n_0 ), .CO({\counter_stg3_reg[4]_i_1_n_0 ,\counter_stg3_reg[4]_i_1_n_1 ,\counter_stg3_reg[4]_i_1_n_2 ,\counter_stg3_reg[4]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\counter_stg3_reg[4]_i_1_n_4 ,\counter_stg3_reg[4]_i_1_n_5 ,\counter_stg3_reg[4]_i_1_n_6 ,\counter_stg3_reg[4]_i_1_n_7 }), .S(counter_stg3_reg[7:4])); FDRE #( .INIT(1'b0)) \counter_stg3_reg[5] (.C(independent_clock_bufg), .CE(counter_stg30), .D(\counter_stg3_reg[4]_i_1_n_6 ), .Q(counter_stg3_reg[5]), .R(\counter_stg1[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \counter_stg3_reg[6] (.C(independent_clock_bufg), .CE(counter_stg30), .D(\counter_stg3_reg[4]_i_1_n_5 ), .Q(counter_stg3_reg[6]), .R(\counter_stg1[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \counter_stg3_reg[7] (.C(independent_clock_bufg), .CE(counter_stg30), .D(\counter_stg3_reg[4]_i_1_n_4 ), .Q(counter_stg3_reg[7]), .R(\counter_stg1[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \counter_stg3_reg[8] (.C(independent_clock_bufg), .CE(counter_stg30), .D(\counter_stg3_reg[8]_i_1_n_7 ), .Q(counter_stg3_reg[8]), .R(\counter_stg1[5]_i_1_n_0 )); CARRY4 \counter_stg3_reg[8]_i_1 (.CI(\counter_stg3_reg[4]_i_1_n_0 ), .CO({\NLW_counter_stg3_reg[8]_i_1_CO_UNCONNECTED [3],\counter_stg3_reg[8]_i_1_n_1 ,\counter_stg3_reg[8]_i_1_n_2 ,\counter_stg3_reg[8]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\counter_stg3_reg[8]_i_1_n_4 ,\counter_stg3_reg[8]_i_1_n_5 ,\counter_stg3_reg[8]_i_1_n_6 ,\counter_stg3_reg[8]_i_1_n_7 }), .S(counter_stg3_reg[11:8])); FDRE #( .INIT(1'b0)) \counter_stg3_reg[9] (.C(independent_clock_bufg), .CE(counter_stg30), .D(\counter_stg3_reg[8]_i_1_n_6 ), .Q(counter_stg3_reg[9]), .R(\counter_stg1[5]_i_1_n_0 )); LUT3 #( .INIT(8'h20)) reset_i_1 (.I0(reset_i_2_n_0), .I1(counter_stg3_reg[0]), .I2(reset_i_3_n_0), .O(reset0)); LUT6 #( .INIT(64'h0000001000000000)) reset_i_2 (.I0(counter_stg3_reg[9]), .I1(counter_stg3_reg[10]), .I2(counter_stg3_reg[7]), .I3(counter_stg3_reg[8]), .I4(counter_stg2_reg[0]), .I5(counter_stg3_reg[11]), .O(reset_i_2_n_0)); LUT3 #( .INIT(8'h80)) reset_i_3 (.I0(reset_i_4_n_0), .I1(reset_i_5_n_0), .I2(reset_i_6_n_0), .O(reset_i_3_n_0)); LUT6 #( .INIT(64'h0000000000000008)) reset_i_4 (.I0(counter_stg2_reg[3]), .I1(counter_stg2_reg[4]), .I2(counter_stg2_reg[1]), .I3(counter_stg2_reg[2]), .I4(counter_stg2_reg[6]), .I5(counter_stg2_reg[5]), .O(reset_i_4_n_0)); LUT6 #( .INIT(64'h0020000000000000)) reset_i_5 (.I0(counter_stg2_reg[10]), .I1(counter_stg2_reg[9]), .I2(counter_stg2_reg[8]), .I3(counter_stg2_reg[7]), .I4(counter_stg1_reg__0), .I5(counter_stg2_reg[11]), .O(reset_i_5_n_0)); LUT6 #( .INIT(64'h0002000000000000)) reset_i_6 (.I0(counter_stg3_reg[4]), .I1(counter_stg3_reg[3]), .I2(counter_stg3_reg[1]), .I3(counter_stg3_reg[2]), .I4(counter_stg3_reg[6]), .I5(counter_stg3_reg[5]), .O(reset_i_6_n_0)); FDRE reset_reg (.C(independent_clock_bufg), .CE(1'b1), .D(reset0), .Q(reset), .R(1'b0)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block (data_out, data_in, userclk2); output data_out; input data_in; input userclk2; wire data_in; wire data_out; wire data_sync1; wire data_sync2; wire data_sync3; wire data_sync4; wire data_sync5; wire userclk2; (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg1 (.C(userclk2), .CE(1'b1), .D(data_in), .Q(data_sync1), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg2 (.C(userclk2), .CE(1'b1), .D(data_sync1), .Q(data_sync2), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg3 (.C(userclk2), .CE(1'b1), .D(data_sync2), .Q(data_sync3), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg4 (.C(userclk2), .CE(1'b1), .D(data_sync3), .Q(data_sync4), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg5 (.C(userclk2), .CE(1'b1), .D(data_sync4), .Q(data_sync5), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg6 (.C(userclk2), .CE(1'b1), .D(data_sync5), .Q(data_out), .R(1'b0)); endmodule (* ORIG_REF_NAME = "gig_ethernet_pcs_pma_16_1_sync_block" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_0 (resetdone, resetdone_0, data_in, userclk2); output resetdone; input resetdone_0; input data_in; input userclk2; wire data_in; wire data_out; wire data_sync1; wire data_sync2; wire data_sync3; wire data_sync4; wire data_sync5; wire resetdone; wire resetdone_0; wire userclk2; (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg1 (.C(userclk2), .CE(1'b1), .D(data_in), .Q(data_sync1), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg2 (.C(userclk2), .CE(1'b1), .D(data_sync1), .Q(data_sync2), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg3 (.C(userclk2), .CE(1'b1), .D(data_sync2), .Q(data_sync3), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg4 (.C(userclk2), .CE(1'b1), .D(data_sync3), .Q(data_sync4), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg5 (.C(userclk2), .CE(1'b1), .D(data_sync4), .Q(data_sync5), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg6 (.C(userclk2), .CE(1'b1), .D(data_sync5), .Q(data_out), .R(1'b0)); LUT2 #( .INIT(4'h8)) resetdone_INST_0 (.I0(data_out), .I1(resetdone_0), .O(resetdone)); endmodule (* ORIG_REF_NAME = "gig_ethernet_pcs_pma_16_1_sync_block" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_10 (data_out, data_sync_reg1_0, independent_clock_bufg); output data_out; input data_sync_reg1_0; input independent_clock_bufg; wire data_out; wire data_sync1; wire data_sync2; wire data_sync3; wire data_sync4; wire data_sync5; wire data_sync_reg1_0; wire independent_clock_bufg; (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg1 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync_reg1_0), .Q(data_sync1), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg2 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync1), .Q(data_sync2), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg3 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync2), .Q(data_sync3), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg4 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync3), .Q(data_sync4), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg5 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync4), .Q(data_sync5), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg6 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync5), .Q(data_out), .R(1'b0)); endmodule (* ORIG_REF_NAME = "gig_ethernet_pcs_pma_16_1_sync_block" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_11 (\FSM_sequential_rx_state_reg[1] , Q, rxresetdone_s3, cplllock, independent_clock_bufg); output \FSM_sequential_rx_state_reg[1] ; input [2:0]Q; input rxresetdone_s3; input cplllock; input independent_clock_bufg; wire \FSM_sequential_rx_state_reg[1] ; wire [2:0]Q; wire cplllock; wire cplllock_sync; wire data_sync1; wire data_sync2; wire data_sync3; wire data_sync4; wire data_sync5; wire independent_clock_bufg; wire rxresetdone_s3; LUT5 #( .INIT(32'h008F0080)) \FSM_sequential_rx_state[3]_i_5 (.I0(Q[0]), .I1(rxresetdone_s3), .I2(Q[1]), .I3(Q[2]), .I4(cplllock_sync), .O(\FSM_sequential_rx_state_reg[1] )); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg1 (.C(independent_clock_bufg), .CE(1'b1), .D(cplllock), .Q(data_sync1), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg2 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync1), .Q(data_sync2), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg3 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync2), .Q(data_sync3), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg4 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync3), .Q(data_sync4), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg5 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync4), .Q(data_sync5), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg6 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync5), .Q(cplllock_sync), .R(1'b0)); endmodule (* ORIG_REF_NAME = "gig_ethernet_pcs_pma_16_1_sync_block" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_12 (D, E, \FSM_sequential_rx_state_reg[1] , rx_fsm_reset_done_int_reg, Q, \FSM_sequential_rx_state_reg[1]_0 , rx_fsm_reset_done_int_reg_0, rx_fsm_reset_done_int_reg_1, reset_time_out_reg, \FSM_sequential_rx_state_reg[0] , reset_time_out_reg_0, \FSM_sequential_rx_state_reg[0]_0 , \FSM_sequential_rx_state_reg[0]_1 , mmcm_lock_reclocked, \FSM_sequential_rx_state_reg[0]_2 , time_out_wait_bypass_s3, \FSM_sequential_rx_state_reg[3] , \FSM_sequential_rx_state_reg[0]_3 , rx_fsm_reset_done_int_reg_2, rx_fsm_reset_done_int_reg_3, reset_time_out_reg_1, reset_time_out_reg_2, data_in, data_out, independent_clock_bufg); output [2:0]D; output [0:0]E; output \FSM_sequential_rx_state_reg[1] ; output rx_fsm_reset_done_int_reg; input [3:0]Q; input \FSM_sequential_rx_state_reg[1]_0 ; input rx_fsm_reset_done_int_reg_0; input rx_fsm_reset_done_int_reg_1; input reset_time_out_reg; input \FSM_sequential_rx_state_reg[0] ; input reset_time_out_reg_0; input \FSM_sequential_rx_state_reg[0]_0 ; input \FSM_sequential_rx_state_reg[0]_1 ; input mmcm_lock_reclocked; input \FSM_sequential_rx_state_reg[0]_2 ; input time_out_wait_bypass_s3; input \FSM_sequential_rx_state_reg[3] ; input \FSM_sequential_rx_state_reg[0]_3 ; input rx_fsm_reset_done_int_reg_2; input rx_fsm_reset_done_int_reg_3; input reset_time_out_reg_1; input reset_time_out_reg_2; input data_in; input data_out; input independent_clock_bufg; wire [2:0]D; wire [0:0]E; wire \FSM_sequential_rx_state[0]_i_3_n_0 ; wire \FSM_sequential_rx_state[1]_i_2_n_0 ; wire \FSM_sequential_rx_state[3]_i_4_n_0 ; wire \FSM_sequential_rx_state[3]_i_6_n_0 ; wire \FSM_sequential_rx_state[3]_i_8_n_0 ; wire \FSM_sequential_rx_state_reg[0] ; wire \FSM_sequential_rx_state_reg[0]_0 ; wire \FSM_sequential_rx_state_reg[0]_1 ; wire \FSM_sequential_rx_state_reg[0]_2 ; wire \FSM_sequential_rx_state_reg[0]_3 ; wire \FSM_sequential_rx_state_reg[1] ; wire \FSM_sequential_rx_state_reg[1]_0 ; wire \FSM_sequential_rx_state_reg[3] ; wire [3:0]Q; wire data_in; wire data_out; wire data_sync1; wire data_sync2; wire data_sync3; wire data_sync4; wire data_sync5; wire data_valid_sync; wire independent_clock_bufg; wire mmcm_lock_reclocked; wire reset_time_out_i_2_n_0; wire reset_time_out_reg; wire reset_time_out_reg_0; wire reset_time_out_reg_1; wire reset_time_out_reg_2; wire rx_fsm_reset_done_int; wire rx_fsm_reset_done_int_i_3_n_0; wire rx_fsm_reset_done_int_i_4_n_0; wire rx_fsm_reset_done_int_reg; wire rx_fsm_reset_done_int_reg_0; wire rx_fsm_reset_done_int_reg_1; wire rx_fsm_reset_done_int_reg_2; wire rx_fsm_reset_done_int_reg_3; wire time_out_wait_bypass_s3; LUT5 #( .INIT(32'hFFEFEFEF)) \FSM_sequential_rx_state[0]_i_1 (.I0(\FSM_sequential_rx_state_reg[0]_2 ), .I1(\FSM_sequential_rx_state[0]_i_3_n_0 ), .I2(Q[0]), .I3(Q[1]), .I4(Q[3]), .O(D[0])); (* SOFT_HLUTNM = "soft_lutpair42" *) LUT4 #( .INIT(16'h0200)) \FSM_sequential_rx_state[0]_i_3 (.I0(Q[3]), .I1(reset_time_out_reg), .I2(data_valid_sync), .I3(rx_fsm_reset_done_int_reg_1), .O(\FSM_sequential_rx_state[0]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF24200400)) \FSM_sequential_rx_state[1]_i_1 (.I0(Q[0]), .I1(Q[1]), .I2(Q[3]), .I3(Q[2]), .I4(\FSM_sequential_rx_state[1]_i_2_n_0 ), .I5(\FSM_sequential_rx_state_reg[1]_0 ), .O(D[1])); LUT2 #( .INIT(4'hB)) \FSM_sequential_rx_state[1]_i_2 (.I0(data_valid_sync), .I1(rx_fsm_reset_done_int_reg_1), .O(\FSM_sequential_rx_state[1]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFEEE)) \FSM_sequential_rx_state[3]_i_1 (.I0(\FSM_sequential_rx_state_reg[0] ), .I1(\FSM_sequential_rx_state[3]_i_4_n_0 ), .I2(Q[0]), .I3(reset_time_out_reg_0), .I4(\FSM_sequential_rx_state[3]_i_6_n_0 ), .I5(\FSM_sequential_rx_state_reg[0]_0 ), .O(E)); LUT6 #( .INIT(64'hFFFFFFFFCCC0C4C4)) \FSM_sequential_rx_state[3]_i_2 (.I0(time_out_wait_bypass_s3), .I1(Q[3]), .I2(Q[1]), .I3(\FSM_sequential_rx_state[3]_i_8_n_0 ), .I4(Q[0]), .I5(\FSM_sequential_rx_state_reg[3] ), .O(D[2])); LUT6 #( .INIT(64'hAAAAAAAAAAAAEFEA)) \FSM_sequential_rx_state[3]_i_4 (.I0(\FSM_sequential_rx_state[0]_i_3_n_0 ), .I1(\FSM_sequential_rx_state_reg[0]_1 ), .I2(Q[2]), .I3(\FSM_sequential_rx_state_reg[0]_3 ), .I4(Q[0]), .I5(Q[1]), .O(\FSM_sequential_rx_state[3]_i_4_n_0 )); LUT5 #( .INIT(32'h0CE20CCC)) \FSM_sequential_rx_state[3]_i_6 (.I0(mmcm_lock_reclocked), .I1(Q[3]), .I2(data_valid_sync), .I3(Q[1]), .I4(Q[0]), .O(\FSM_sequential_rx_state[3]_i_6_n_0 )); (* SOFT_HLUTNM = "soft_lutpair42" *) LUT3 #( .INIT(8'hFD)) \FSM_sequential_rx_state[3]_i_8 (.I0(rx_fsm_reset_done_int_reg_1), .I1(data_valid_sync), .I2(reset_time_out_reg), .O(\FSM_sequential_rx_state[3]_i_8_n_0 )); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg1 (.C(independent_clock_bufg), .CE(1'b1), .D(data_out), .Q(data_sync1), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg2 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync1), .Q(data_sync2), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg3 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync2), .Q(data_sync3), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg4 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync3), .Q(data_sync4), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg5 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync4), .Q(data_sync5), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg6 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync5), .Q(data_valid_sync), .R(1'b0)); LUT6 #( .INIT(64'hEEEFFFFFEEEF0000)) reset_time_out_i_1__0 (.I0(reset_time_out_i_2_n_0), .I1(reset_time_out_reg_0), .I2(reset_time_out_reg_1), .I3(Q[1]), .I4(reset_time_out_reg_2), .I5(reset_time_out_reg), .O(\FSM_sequential_rx_state_reg[1] )); LUT6 #( .INIT(64'h0FF30E0E0FF30202)) reset_time_out_i_2 (.I0(\FSM_sequential_rx_state_reg[0]_1 ), .I1(Q[0]), .I2(Q[1]), .I3(data_valid_sync), .I4(Q[3]), .I5(mmcm_lock_reclocked), .O(reset_time_out_i_2_n_0)); LUT4 #( .INIT(16'hABA8)) rx_fsm_reset_done_int_i_1 (.I0(rx_fsm_reset_done_int), .I1(rx_fsm_reset_done_int_i_3_n_0), .I2(rx_fsm_reset_done_int_i_4_n_0), .I3(data_in), .O(rx_fsm_reset_done_int_reg)); LUT5 #( .INIT(32'h00040000)) rx_fsm_reset_done_int_i_2 (.I0(Q[0]), .I1(data_valid_sync), .I2(Q[2]), .I3(reset_time_out_reg), .I4(rx_fsm_reset_done_int_reg_2), .O(rx_fsm_reset_done_int)); LUT6 #( .INIT(64'h0400040004040400)) rx_fsm_reset_done_int_i_3 (.I0(rx_fsm_reset_done_int_reg_0), .I1(Q[3]), .I2(Q[2]), .I3(data_valid_sync), .I4(rx_fsm_reset_done_int_reg_1), .I5(reset_time_out_reg), .O(rx_fsm_reset_done_int_i_3_n_0)); LUT6 #( .INIT(64'h0008000808080008)) rx_fsm_reset_done_int_i_4 (.I0(rx_fsm_reset_done_int_reg_3), .I1(Q[1]), .I2(Q[0]), .I3(data_valid_sync), .I4(rx_fsm_reset_done_int_reg_2), .I5(reset_time_out_reg), .O(rx_fsm_reset_done_int_i_4_n_0)); endmodule (* ORIG_REF_NAME = "gig_ethernet_pcs_pma_16_1_sync_block" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_13 (SR, mmcm_lock_reclocked_reg, mmcm_lock_reclocked, Q, mmcm_lock_reclocked_reg_0, mmcm_locked, independent_clock_bufg); output [0:0]SR; output mmcm_lock_reclocked_reg; input mmcm_lock_reclocked; input [1:0]Q; input mmcm_lock_reclocked_reg_0; input mmcm_locked; input independent_clock_bufg; wire [1:0]Q; wire [0:0]SR; wire data_sync1; wire data_sync2; wire data_sync3; wire data_sync4; wire data_sync5; wire independent_clock_bufg; wire mmcm_lock_i; wire mmcm_lock_reclocked; wire mmcm_lock_reclocked_reg; wire mmcm_lock_reclocked_reg_0; wire mmcm_locked; (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg1 (.C(independent_clock_bufg), .CE(1'b1), .D(mmcm_locked), .Q(data_sync1), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg2 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync1), .Q(data_sync2), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg3 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync2), .Q(data_sync3), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg4 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync3), .Q(data_sync4), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg5 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync4), .Q(data_sync5), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg6 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync5), .Q(mmcm_lock_i), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair43" *) LUT1 #( .INIT(2'h1)) \mmcm_lock_count[7]_i_1__0 (.I0(mmcm_lock_i), .O(SR)); (* SOFT_HLUTNM = "soft_lutpair43" *) LUT5 #( .INIT(32'hAAEA0000)) mmcm_lock_reclocked_i_1__0 (.I0(mmcm_lock_reclocked), .I1(Q[1]), .I2(Q[0]), .I3(mmcm_lock_reclocked_reg_0), .I4(mmcm_lock_i), .O(mmcm_lock_reclocked_reg)); endmodule (* ORIG_REF_NAME = "gig_ethernet_pcs_pma_16_1_sync_block" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_14 (data_out, data_in, userclk); output data_out; input data_in; input userclk; wire data_in; wire data_out; wire data_sync1; wire data_sync2; wire data_sync3; wire data_sync4; wire data_sync5; wire userclk; (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg1 (.C(userclk), .CE(1'b1), .D(data_in), .Q(data_sync1), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg2 (.C(userclk), .CE(1'b1), .D(data_sync1), .Q(data_sync2), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg3 (.C(userclk), .CE(1'b1), .D(data_sync2), .Q(data_sync3), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg4 (.C(userclk), .CE(1'b1), .D(data_sync3), .Q(data_sync4), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg5 (.C(userclk), .CE(1'b1), .D(data_sync4), .Q(data_sync5), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg6 (.C(userclk), .CE(1'b1), .D(data_sync5), .Q(data_out), .R(1'b0)); endmodule (* ORIG_REF_NAME = "gig_ethernet_pcs_pma_16_1_sync_block" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_15 (data_out, data_in, independent_clock_bufg); output data_out; input data_in; input independent_clock_bufg; wire data_in; wire data_out; wire data_sync1; wire data_sync2; wire data_sync3; wire data_sync4; wire data_sync5; wire independent_clock_bufg; (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg1 (.C(independent_clock_bufg), .CE(1'b1), .D(data_in), .Q(data_sync1), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg2 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync1), .Q(data_sync2), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg3 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync2), .Q(data_sync3), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg4 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync3), .Q(data_sync4), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg5 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync4), .Q(data_sync5), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg6 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync5), .Q(data_out), .R(1'b0)); endmodule (* ORIG_REF_NAME = "gig_ethernet_pcs_pma_16_1_sync_block" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_16 (data_out, data_in, userclk); output data_out; input data_in; input userclk; wire data_in; wire data_out; wire data_sync1; wire data_sync2; wire data_sync3; wire data_sync4; wire data_sync5; wire userclk; (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg1 (.C(userclk), .CE(1'b1), .D(data_in), .Q(data_sync1), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg2 (.C(userclk), .CE(1'b1), .D(data_sync1), .Q(data_sync2), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg3 (.C(userclk), .CE(1'b1), .D(data_sync2), .Q(data_sync3), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg4 (.C(userclk), .CE(1'b1), .D(data_sync3), .Q(data_sync4), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg5 (.C(userclk), .CE(1'b1), .D(data_sync4), .Q(data_sync5), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg6 (.C(userclk), .CE(1'b1), .D(data_sync5), .Q(data_out), .R(1'b0)); endmodule (* ORIG_REF_NAME = "gig_ethernet_pcs_pma_16_1_sync_block" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_3 (data_out, status_vector, independent_clock_bufg); output data_out; input [0:0]status_vector; input independent_clock_bufg; wire data_out; wire data_sync1; wire data_sync2; wire data_sync3; wire data_sync4; wire data_sync5; wire independent_clock_bufg; wire [0:0]status_vector; (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg1 (.C(independent_clock_bufg), .CE(1'b1), .D(status_vector), .Q(data_sync1), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg2 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync1), .Q(data_sync2), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg3 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync2), .Q(data_sync3), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg4 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync3), .Q(data_sync4), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg5 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync4), .Q(data_sync5), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg6 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync5), .Q(data_out), .R(1'b0)); endmodule (* ORIG_REF_NAME = "gig_ethernet_pcs_pma_16_1_sync_block" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_4 (data_out, data_sync_reg1_0, independent_clock_bufg); output data_out; input data_sync_reg1_0; input independent_clock_bufg; wire data_out; wire data_sync1; wire data_sync2; wire data_sync3; wire data_sync4; wire data_sync5; wire data_sync_reg1_0; wire independent_clock_bufg; (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg1 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync_reg1_0), .Q(data_sync1), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg2 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync1), .Q(data_sync2), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg3 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync2), .Q(data_sync3), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg4 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync3), .Q(data_sync4), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg5 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync4), .Q(data_sync5), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg6 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync5), .Q(data_out), .R(1'b0)); endmodule (* ORIG_REF_NAME = "gig_ethernet_pcs_pma_16_1_sync_block" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_5 (E, reset_time_out_reg, \FSM_sequential_tx_state_reg[0] , \FSM_sequential_tx_state_reg[0]_0 , \FSM_sequential_tx_state_reg[0]_1 , \FSM_sequential_tx_state_reg[0]_2 , \FSM_sequential_tx_state_reg[0]_3 , Q, reset_time_out_reg_0, mmcm_lock_reclocked, \FSM_sequential_tx_state_reg[0]_4 , \FSM_sequential_tx_state_reg[0]_5 , \FSM_sequential_tx_state_reg[0]_6 , reset_time_out_reg_1, reset_time_out, cplllock, independent_clock_bufg); output [0:0]E; output reset_time_out_reg; input \FSM_sequential_tx_state_reg[0] ; input \FSM_sequential_tx_state_reg[0]_0 ; input \FSM_sequential_tx_state_reg[0]_1 ; input \FSM_sequential_tx_state_reg[0]_2 ; input \FSM_sequential_tx_state_reg[0]_3 ; input [3:0]Q; input reset_time_out_reg_0; input mmcm_lock_reclocked; input \FSM_sequential_tx_state_reg[0]_4 ; input \FSM_sequential_tx_state_reg[0]_5 ; input \FSM_sequential_tx_state_reg[0]_6 ; input reset_time_out_reg_1; input reset_time_out; input cplllock; input independent_clock_bufg; wire [0:0]E; wire \FSM_sequential_tx_state[3]_i_5_n_0 ; wire \FSM_sequential_tx_state_reg[0] ; wire \FSM_sequential_tx_state_reg[0]_0 ; wire \FSM_sequential_tx_state_reg[0]_1 ; wire \FSM_sequential_tx_state_reg[0]_2 ; wire \FSM_sequential_tx_state_reg[0]_3 ; wire \FSM_sequential_tx_state_reg[0]_4 ; wire \FSM_sequential_tx_state_reg[0]_5 ; wire \FSM_sequential_tx_state_reg[0]_6 ; wire [3:0]Q; wire cplllock; wire cplllock_sync; wire data_sync1; wire data_sync2; wire data_sync3; wire data_sync4; wire data_sync5; wire independent_clock_bufg; wire mmcm_lock_reclocked; wire reset_time_out; wire reset_time_out_i_3__0_n_0; wire reset_time_out_i_4__0_n_0; wire reset_time_out_reg; wire reset_time_out_reg_0; wire reset_time_out_reg_1; LUT6 #( .INIT(64'hFFFFFFFEFFFEFFFE)) \FSM_sequential_tx_state[3]_i_1 (.I0(\FSM_sequential_tx_state_reg[0] ), .I1(\FSM_sequential_tx_state_reg[0]_0 ), .I2(\FSM_sequential_tx_state[3]_i_5_n_0 ), .I3(\FSM_sequential_tx_state_reg[0]_1 ), .I4(\FSM_sequential_tx_state_reg[0]_2 ), .I5(\FSM_sequential_tx_state_reg[0]_3 ), .O(E)); LUT6 #( .INIT(64'h0000000000F00008)) \FSM_sequential_tx_state[3]_i_5 (.I0(\FSM_sequential_tx_state_reg[0]_4 ), .I1(\FSM_sequential_tx_state_reg[0]_5 ), .I2(cplllock_sync), .I3(Q[2]), .I4(Q[1]), .I5(\FSM_sequential_tx_state_reg[0]_6 ), .O(\FSM_sequential_tx_state[3]_i_5_n_0 )); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg1 (.C(independent_clock_bufg), .CE(1'b1), .D(cplllock), .Q(data_sync1), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg2 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync1), .Q(data_sync2), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg3 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync2), .Q(data_sync3), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg4 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync3), .Q(data_sync4), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg5 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync4), .Q(data_sync5), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg6 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync5), .Q(cplllock_sync), .R(1'b0)); LUT4 #( .INIT(16'hEFE0)) reset_time_out_i_1 (.I0(reset_time_out_reg_1), .I1(reset_time_out_i_3__0_n_0), .I2(reset_time_out_i_4__0_n_0), .I3(reset_time_out), .O(reset_time_out_reg)); LUT6 #( .INIT(64'h020002000F000200)) reset_time_out_i_3__0 (.I0(cplllock_sync), .I1(Q[2]), .I2(Q[3]), .I3(Q[0]), .I4(mmcm_lock_reclocked), .I5(Q[1]), .O(reset_time_out_i_3__0_n_0)); LUT6 #( .INIT(64'h0505FF040505F504)) reset_time_out_i_4__0 (.I0(Q[1]), .I1(reset_time_out_reg_0), .I2(Q[2]), .I3(Q[0]), .I4(Q[3]), .I5(cplllock_sync), .O(reset_time_out_i_4__0_n_0)); endmodule (* ORIG_REF_NAME = "gig_ethernet_pcs_pma_16_1_sync_block" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_6 (SR, mmcm_lock_reclocked_reg, mmcm_lock_reclocked, Q, mmcm_lock_reclocked_reg_0, mmcm_locked, independent_clock_bufg); output [0:0]SR; output mmcm_lock_reclocked_reg; input mmcm_lock_reclocked; input [1:0]Q; input mmcm_lock_reclocked_reg_0; input mmcm_locked; input independent_clock_bufg; wire [1:0]Q; wire [0:0]SR; wire data_sync1; wire data_sync2; wire data_sync3; wire data_sync4; wire data_sync5; wire independent_clock_bufg; wire mmcm_lock_i; wire mmcm_lock_reclocked; wire mmcm_lock_reclocked_reg; wire mmcm_lock_reclocked_reg_0; wire mmcm_locked; (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg1 (.C(independent_clock_bufg), .CE(1'b1), .D(mmcm_locked), .Q(data_sync1), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg2 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync1), .Q(data_sync2), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg3 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync2), .Q(data_sync3), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg4 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync3), .Q(data_sync4), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg5 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync4), .Q(data_sync5), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg6 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync5), .Q(mmcm_lock_i), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair58" *) LUT1 #( .INIT(2'h1)) \mmcm_lock_count[7]_i_1 (.I0(mmcm_lock_i), .O(SR)); (* SOFT_HLUTNM = "soft_lutpair58" *) LUT5 #( .INIT(32'hAAEA0000)) mmcm_lock_reclocked_i_1 (.I0(mmcm_lock_reclocked), .I1(Q[1]), .I2(Q[0]), .I3(mmcm_lock_reclocked_reg_0), .I4(mmcm_lock_i), .O(mmcm_lock_reclocked_reg)); endmodule (* ORIG_REF_NAME = "gig_ethernet_pcs_pma_16_1_sync_block" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_7 (data_out, data_in, userclk); output data_out; input data_in; input userclk; wire data_in; wire data_out; wire data_sync1; wire data_sync2; wire data_sync3; wire data_sync4; wire data_sync5; wire userclk; (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg1 (.C(userclk), .CE(1'b1), .D(data_in), .Q(data_sync1), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg2 (.C(userclk), .CE(1'b1), .D(data_sync1), .Q(data_sync2), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg3 (.C(userclk), .CE(1'b1), .D(data_sync2), .Q(data_sync3), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg4 (.C(userclk), .CE(1'b1), .D(data_sync3), .Q(data_sync4), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg5 (.C(userclk), .CE(1'b1), .D(data_sync4), .Q(data_sync5), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg6 (.C(userclk), .CE(1'b1), .D(data_sync5), .Q(data_out), .R(1'b0)); endmodule (* ORIG_REF_NAME = "gig_ethernet_pcs_pma_16_1_sync_block" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_8 (data_out, data_in, independent_clock_bufg); output data_out; input data_in; input independent_clock_bufg; wire data_in; wire data_out; wire data_sync1; wire data_sync2; wire data_sync3; wire data_sync4; wire data_sync5; wire independent_clock_bufg; (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg1 (.C(independent_clock_bufg), .CE(1'b1), .D(data_in), .Q(data_sync1), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg2 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync1), .Q(data_sync2), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg3 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync2), .Q(data_sync3), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg4 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync3), .Q(data_sync4), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg5 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync4), .Q(data_sync5), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg6 (.C(independent_clock_bufg), .CE(1'b1), .D(data_sync5), .Q(data_out), .R(1'b0)); endmodule (* ORIG_REF_NAME = "gig_ethernet_pcs_pma_16_1_sync_block" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_9 (data_out, data_in, userclk); output data_out; input data_in; input userclk; wire data_in; wire data_out; wire data_sync1; wire data_sync2; wire data_sync3; wire data_sync4; wire data_sync5; wire userclk; (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg1 (.C(userclk), .CE(1'b1), .D(data_in), .Q(data_sync1), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg2 (.C(userclk), .CE(1'b1), .D(data_sync1), .Q(data_sync2), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg3 (.C(userclk), .CE(1'b1), .D(data_sync2), .Q(data_sync3), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg4 (.C(userclk), .CE(1'b1), .D(data_sync3), .Q(data_sync4), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg5 (.C(userclk), .CE(1'b1), .D(data_sync4), .Q(data_sync5), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg6 (.C(userclk), .CE(1'b1), .D(data_sync5), .Q(data_out), .R(1'b0)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_transceiver (cplllock, txn, txp, rxoutclk, txoutclk, data_in, rx_fsm_reset_done_int_reg, rxchariscomma, rxcharisk, Q, \rxdata_reg[7]_0 , rxdisperr, rxnotintable, rxbuferr, txbuferr, mmcm_reset, gtrefclk_bufg, status_vector, independent_clock_bufg, userclk, enablealign, SR, reset_sync5, gtrefclk, rxn, rxp, gt0_qplloutclk_in, gt0_qplloutrefclk_in, mmcm_locked, pma_reset, userclk2, powerdown, D, txchardispval_reg_reg_0, \txdata_reg_reg[7]_0 , txcharisk_reg_reg_0); output cplllock; output txn; output txp; output rxoutclk; output txoutclk; output data_in; output rx_fsm_reset_done_int_reg; output rxchariscomma; output rxcharisk; output [1:0]Q; output [7:0]\rxdata_reg[7]_0 ; output rxdisperr; output rxnotintable; output rxbuferr; output txbuferr; output mmcm_reset; input gtrefclk_bufg; input [0:0]status_vector; input independent_clock_bufg; input userclk; input enablealign; input [0:0]SR; input [0:0]reset_sync5; input gtrefclk; input rxn; input rxp; input gt0_qplloutclk_in; input gt0_qplloutrefclk_in; input mmcm_locked; input pma_reset; input userclk2; input powerdown; input [0:0]D; input [0:0]txchardispval_reg_reg_0; input [7:0]\txdata_reg_reg[7]_0 ; input [0:0]txcharisk_reg_reg_0; wire [0:0]D; wire [1:0]Q; wire [0:0]SR; wire cplllock; wire data_in; wire data_valid_reg2; wire enablealign; wire encommaalign_int; wire gt0_qplloutclk_in; wire gt0_qplloutrefclk_in; wire gtrefclk; wire gtrefclk_bufg; wire gtwizard_inst_n_7; wire gtwizard_inst_n_8; wire independent_clock_bufg; wire mmcm_locked; wire mmcm_reset; wire p_0_in; wire [0:0]p_1_in; wire [0:0]p_1_in__0; wire [7:0]p_1_in__1; wire [0:0]p_1_in__2; wire pma_reset; wire powerdown; wire reset; wire [0:0]reset_sync5; wire rx_fsm_reset_done_int_reg; wire rxbuferr; wire rxchariscomma; wire [1:0]rxchariscomma_double; wire rxchariscomma_i_1_n_0; wire [1:0]rxchariscomma_int; wire [1:0]rxchariscomma_reg__0; wire rxcharisk; wire [1:0]rxcharisk_double; wire rxcharisk_i_1_n_0; wire [1:0]rxcharisk_int; wire [1:0]rxcharisk_reg__0; wire [1:0]rxclkcorcnt_double; wire [1:0]rxclkcorcnt_int; wire [1:0]rxclkcorcnt_reg; wire \rxdata[0]_i_1_n_0 ; wire \rxdata[1]_i_1_n_0 ; wire \rxdata[2]_i_1_n_0 ; wire \rxdata[3]_i_1_n_0 ; wire \rxdata[4]_i_1_n_0 ; wire \rxdata[5]_i_1_n_0 ; wire \rxdata[6]_i_1_n_0 ; wire \rxdata[7]_i_1_n_0 ; wire [15:0]rxdata_double; wire [15:0]rxdata_int; wire [15:0]rxdata_reg; wire [7:0]\rxdata_reg[7]_0 ; wire rxdisperr; wire [1:0]rxdisperr_double; wire rxdisperr_i_1_n_0; wire [1:0]rxdisperr_int; wire [1:0]rxdisperr_reg__0; wire rxn; wire rxnotintable; wire [1:0]rxnotintable_double; wire rxnotintable_i_1_n_0; wire [1:0]rxnotintable_int; wire [1:0]rxnotintable_reg__0; wire rxoutclk; wire rxp; wire rxpowerdown; wire rxpowerdown_double; wire rxpowerdown_reg__0; wire rxreset_int; wire [0:0]status_vector; wire toggle; wire toggle_i_1_n_0; wire txbuferr; wire [1:1]txbufstatus_reg; wire [1:0]txchardispmode_double; wire [1:0]txchardispmode_int; wire [1:0]txchardispval_double; wire [1:0]txchardispval_int; wire [0:0]txchardispval_reg_reg_0; wire [1:0]txcharisk_double; wire [1:0]txcharisk_int; wire [0:0]txcharisk_reg_reg_0; wire [15:0]txdata_double; wire [15:0]txdata_int; wire [7:0]\txdata_reg_reg[7]_0 ; wire txn; wire txoutclk; wire txp; wire txpowerdown; wire txpowerdown_double; wire txpowerdown_reg__0; wire txreset_int; wire userclk; wire userclk2; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_GTWIZARD gtwizard_inst (.D(rxclkcorcnt_int), .Q(txdata_int), .RXBUFSTATUS(gtwizard_inst_n_8), .RXPD(rxpowerdown), .TXBUFSTATUS(gtwizard_inst_n_7), .TXPD(txpowerdown), .cplllock(cplllock), .data_in(data_in), .data_out(data_valid_reg2), .data_sync_reg1(txchardispmode_int), .data_sync_reg1_0(txchardispval_int), .data_sync_reg1_1(txcharisk_int), .data_sync_reg1_2(txreset_int), .gt0_qplloutclk_in(gt0_qplloutclk_in), .gt0_qplloutrefclk_in(gt0_qplloutrefclk_in), .\gt0_rx_cdrlock_counter_reg[0] (rxreset_int), .gtrefclk(gtrefclk), .gtrefclk_bufg(gtrefclk_bufg), .independent_clock_bufg(independent_clock_bufg), .independent_clock_bufg_0(rxdata_int), .independent_clock_bufg_1(rxchariscomma_int), .independent_clock_bufg_2(rxcharisk_int), .independent_clock_bufg_3(rxdisperr_int), .independent_clock_bufg_4(rxnotintable_int), .mmcm_locked(mmcm_locked), .mmcm_reset(mmcm_reset), .pma_reset(pma_reset), .reset(reset), .reset_out(encommaalign_int), .rx_fsm_reset_done_int_reg(rx_fsm_reset_done_int_reg), .rxn(rxn), .rxoutclk(rxoutclk), .rxp(rxp), .txn(txn), .txoutclk(txoutclk), .txp(txp), .userclk(userclk)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_reset_sync reclock_encommaalign (.enablealign(enablealign), .reset_out(encommaalign_int), .userclk(userclk)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_reset_sync_1 reclock_rxreset (.independent_clock_bufg(independent_clock_bufg), .reset_out(rxreset_int), .reset_sync5_0(reset_sync5)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_reset_sync_2 reclock_txreset (.SR(SR), .independent_clock_bufg(independent_clock_bufg), .reset_out(txreset_int)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_reset_wtd_timer reset_wtd_timer (.data_out(data_valid_reg2), .independent_clock_bufg(independent_clock_bufg), .reset(reset)); FDRE rxbuferr_reg (.C(userclk2), .CE(1'b1), .D(p_0_in), .Q(rxbuferr), .R(1'b0)); FDRE \rxbufstatus_reg_reg[2] (.C(userclk), .CE(1'b1), .D(gtwizard_inst_n_8), .Q(p_0_in), .R(1'b0)); FDRE \rxchariscomma_double_reg[0] (.C(userclk2), .CE(toggle), .D(rxchariscomma_reg__0[0]), .Q(rxchariscomma_double[0]), .R(reset_sync5)); FDRE \rxchariscomma_double_reg[1] (.C(userclk2), .CE(toggle), .D(rxchariscomma_reg__0[1]), .Q(rxchariscomma_double[1]), .R(reset_sync5)); (* SOFT_HLUTNM = "soft_lutpair81" *) LUT3 #( .INIT(8'hB8)) rxchariscomma_i_1 (.I0(rxchariscomma_double[1]), .I1(toggle), .I2(rxchariscomma_double[0]), .O(rxchariscomma_i_1_n_0)); FDRE rxchariscomma_reg (.C(userclk2), .CE(1'b1), .D(rxchariscomma_i_1_n_0), .Q(rxchariscomma), .R(reset_sync5)); FDRE \rxchariscomma_reg_reg[0] (.C(userclk), .CE(1'b1), .D(rxchariscomma_int[0]), .Q(rxchariscomma_reg__0[0]), .R(1'b0)); FDRE \rxchariscomma_reg_reg[1] (.C(userclk), .CE(1'b1), .D(rxchariscomma_int[1]), .Q(rxchariscomma_reg__0[1]), .R(1'b0)); FDRE \rxcharisk_double_reg[0] (.C(userclk2), .CE(toggle), .D(rxcharisk_reg__0[0]), .Q(rxcharisk_double[0]), .R(reset_sync5)); FDRE \rxcharisk_double_reg[1] (.C(userclk2), .CE(toggle), .D(rxcharisk_reg__0[1]), .Q(rxcharisk_double[1]), .R(reset_sync5)); (* SOFT_HLUTNM = "soft_lutpair81" *) LUT3 #( .INIT(8'hB8)) rxcharisk_i_1 (.I0(rxcharisk_double[1]), .I1(toggle), .I2(rxcharisk_double[0]), .O(rxcharisk_i_1_n_0)); FDRE rxcharisk_reg (.C(userclk2), .CE(1'b1), .D(rxcharisk_i_1_n_0), .Q(rxcharisk), .R(reset_sync5)); FDRE \rxcharisk_reg_reg[0] (.C(userclk), .CE(1'b1), .D(rxcharisk_int[0]), .Q(rxcharisk_reg__0[0]), .R(1'b0)); FDRE \rxcharisk_reg_reg[1] (.C(userclk), .CE(1'b1), .D(rxcharisk_int[1]), .Q(rxcharisk_reg__0[1]), .R(1'b0)); FDRE \rxclkcorcnt_double_reg[0] (.C(userclk2), .CE(toggle), .D(rxclkcorcnt_reg[0]), .Q(rxclkcorcnt_double[0]), .R(reset_sync5)); FDRE \rxclkcorcnt_double_reg[1] (.C(userclk2), .CE(toggle), .D(rxclkcorcnt_reg[1]), .Q(rxclkcorcnt_double[1]), .R(reset_sync5)); FDRE \rxclkcorcnt_reg[0] (.C(userclk2), .CE(1'b1), .D(rxclkcorcnt_double[0]), .Q(Q[0]), .R(reset_sync5)); FDRE \rxclkcorcnt_reg[1] (.C(userclk2), .CE(1'b1), .D(rxclkcorcnt_double[1]), .Q(Q[1]), .R(reset_sync5)); FDRE \rxclkcorcnt_reg_reg[0] (.C(userclk), .CE(1'b1), .D(rxclkcorcnt_int[0]), .Q(rxclkcorcnt_reg[0]), .R(1'b0)); FDRE \rxclkcorcnt_reg_reg[1] (.C(userclk), .CE(1'b1), .D(rxclkcorcnt_int[1]), .Q(rxclkcorcnt_reg[1]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair77" *) LUT3 #( .INIT(8'hB8)) \rxdata[0]_i_1 (.I0(rxdata_double[8]), .I1(toggle), .I2(rxdata_double[0]), .O(\rxdata[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair77" *) LUT3 #( .INIT(8'hB8)) \rxdata[1]_i_1 (.I0(rxdata_double[9]), .I1(toggle), .I2(rxdata_double[1]), .O(\rxdata[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair78" *) LUT3 #( .INIT(8'hB8)) \rxdata[2]_i_1 (.I0(rxdata_double[10]), .I1(toggle), .I2(rxdata_double[2]), .O(\rxdata[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair78" *) LUT3 #( .INIT(8'hB8)) \rxdata[3]_i_1 (.I0(rxdata_double[11]), .I1(toggle), .I2(rxdata_double[3]), .O(\rxdata[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair79" *) LUT3 #( .INIT(8'hB8)) \rxdata[4]_i_1 (.I0(rxdata_double[12]), .I1(toggle), .I2(rxdata_double[4]), .O(\rxdata[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair79" *) LUT3 #( .INIT(8'hB8)) \rxdata[5]_i_1 (.I0(rxdata_double[13]), .I1(toggle), .I2(rxdata_double[5]), .O(\rxdata[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair80" *) LUT3 #( .INIT(8'hB8)) \rxdata[6]_i_1 (.I0(rxdata_double[14]), .I1(toggle), .I2(rxdata_double[6]), .O(\rxdata[6]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair80" *) LUT3 #( .INIT(8'hB8)) \rxdata[7]_i_1 (.I0(rxdata_double[15]), .I1(toggle), .I2(rxdata_double[7]), .O(\rxdata[7]_i_1_n_0 )); FDRE \rxdata_double_reg[0] (.C(userclk2), .CE(toggle), .D(rxdata_reg[0]), .Q(rxdata_double[0]), .R(reset_sync5)); FDRE \rxdata_double_reg[10] (.C(userclk2), .CE(toggle), .D(rxdata_reg[10]), .Q(rxdata_double[10]), .R(reset_sync5)); FDRE \rxdata_double_reg[11] (.C(userclk2), .CE(toggle), .D(rxdata_reg[11]), .Q(rxdata_double[11]), .R(reset_sync5)); FDRE \rxdata_double_reg[12] (.C(userclk2), .CE(toggle), .D(rxdata_reg[12]), .Q(rxdata_double[12]), .R(reset_sync5)); FDRE \rxdata_double_reg[13] (.C(userclk2), .CE(toggle), .D(rxdata_reg[13]), .Q(rxdata_double[13]), .R(reset_sync5)); FDRE \rxdata_double_reg[14] (.C(userclk2), .CE(toggle), .D(rxdata_reg[14]), .Q(rxdata_double[14]), .R(reset_sync5)); FDRE \rxdata_double_reg[15] (.C(userclk2), .CE(toggle), .D(rxdata_reg[15]), .Q(rxdata_double[15]), .R(reset_sync5)); FDRE \rxdata_double_reg[1] (.C(userclk2), .CE(toggle), .D(rxdata_reg[1]), .Q(rxdata_double[1]), .R(reset_sync5)); FDRE \rxdata_double_reg[2] (.C(userclk2), .CE(toggle), .D(rxdata_reg[2]), .Q(rxdata_double[2]), .R(reset_sync5)); FDRE \rxdata_double_reg[3] (.C(userclk2), .CE(toggle), .D(rxdata_reg[3]), .Q(rxdata_double[3]), .R(reset_sync5)); FDRE \rxdata_double_reg[4] (.C(userclk2), .CE(toggle), .D(rxdata_reg[4]), .Q(rxdata_double[4]), .R(reset_sync5)); FDRE \rxdata_double_reg[5] (.C(userclk2), .CE(toggle), .D(rxdata_reg[5]), .Q(rxdata_double[5]), .R(reset_sync5)); FDRE \rxdata_double_reg[6] (.C(userclk2), .CE(toggle), .D(rxdata_reg[6]), .Q(rxdata_double[6]), .R(reset_sync5)); FDRE \rxdata_double_reg[7] (.C(userclk2), .CE(toggle), .D(rxdata_reg[7]), .Q(rxdata_double[7]), .R(reset_sync5)); FDRE \rxdata_double_reg[8] (.C(userclk2), .CE(toggle), .D(rxdata_reg[8]), .Q(rxdata_double[8]), .R(reset_sync5)); FDRE \rxdata_double_reg[9] (.C(userclk2), .CE(toggle), .D(rxdata_reg[9]), .Q(rxdata_double[9]), .R(reset_sync5)); FDRE \rxdata_reg[0] (.C(userclk2), .CE(1'b1), .D(\rxdata[0]_i_1_n_0 ), .Q(\rxdata_reg[7]_0 [0]), .R(reset_sync5)); FDRE \rxdata_reg[1] (.C(userclk2), .CE(1'b1), .D(\rxdata[1]_i_1_n_0 ), .Q(\rxdata_reg[7]_0 [1]), .R(reset_sync5)); FDRE \rxdata_reg[2] (.C(userclk2), .CE(1'b1), .D(\rxdata[2]_i_1_n_0 ), .Q(\rxdata_reg[7]_0 [2]), .R(reset_sync5)); FDRE \rxdata_reg[3] (.C(userclk2), .CE(1'b1), .D(\rxdata[3]_i_1_n_0 ), .Q(\rxdata_reg[7]_0 [3]), .R(reset_sync5)); FDRE \rxdata_reg[4] (.C(userclk2), .CE(1'b1), .D(\rxdata[4]_i_1_n_0 ), .Q(\rxdata_reg[7]_0 [4]), .R(reset_sync5)); FDRE \rxdata_reg[5] (.C(userclk2), .CE(1'b1), .D(\rxdata[5]_i_1_n_0 ), .Q(\rxdata_reg[7]_0 [5]), .R(reset_sync5)); FDRE \rxdata_reg[6] (.C(userclk2), .CE(1'b1), .D(\rxdata[6]_i_1_n_0 ), .Q(\rxdata_reg[7]_0 [6]), .R(reset_sync5)); FDRE \rxdata_reg[7] (.C(userclk2), .CE(1'b1), .D(\rxdata[7]_i_1_n_0 ), .Q(\rxdata_reg[7]_0 [7]), .R(reset_sync5)); FDRE \rxdata_reg_reg[0] (.C(userclk), .CE(1'b1), .D(rxdata_int[0]), .Q(rxdata_reg[0]), .R(1'b0)); FDRE \rxdata_reg_reg[10] (.C(userclk), .CE(1'b1), .D(rxdata_int[10]), .Q(rxdata_reg[10]), .R(1'b0)); FDRE \rxdata_reg_reg[11] (.C(userclk), .CE(1'b1), .D(rxdata_int[11]), .Q(rxdata_reg[11]), .R(1'b0)); FDRE \rxdata_reg_reg[12] (.C(userclk), .CE(1'b1), .D(rxdata_int[12]), .Q(rxdata_reg[12]), .R(1'b0)); FDRE \rxdata_reg_reg[13] (.C(userclk), .CE(1'b1), .D(rxdata_int[13]), .Q(rxdata_reg[13]), .R(1'b0)); FDRE \rxdata_reg_reg[14] (.C(userclk), .CE(1'b1), .D(rxdata_int[14]), .Q(rxdata_reg[14]), .R(1'b0)); FDRE \rxdata_reg_reg[15] (.C(userclk), .CE(1'b1), .D(rxdata_int[15]), .Q(rxdata_reg[15]), .R(1'b0)); FDRE \rxdata_reg_reg[1] (.C(userclk), .CE(1'b1), .D(rxdata_int[1]), .Q(rxdata_reg[1]), .R(1'b0)); FDRE \rxdata_reg_reg[2] (.C(userclk), .CE(1'b1), .D(rxdata_int[2]), .Q(rxdata_reg[2]), .R(1'b0)); FDRE \rxdata_reg_reg[3] (.C(userclk), .CE(1'b1), .D(rxdata_int[3]), .Q(rxdata_reg[3]), .R(1'b0)); FDRE \rxdata_reg_reg[4] (.C(userclk), .CE(1'b1), .D(rxdata_int[4]), .Q(rxdata_reg[4]), .R(1'b0)); FDRE \rxdata_reg_reg[5] (.C(userclk), .CE(1'b1), .D(rxdata_int[5]), .Q(rxdata_reg[5]), .R(1'b0)); FDRE \rxdata_reg_reg[6] (.C(userclk), .CE(1'b1), .D(rxdata_int[6]), .Q(rxdata_reg[6]), .R(1'b0)); FDRE \rxdata_reg_reg[7] (.C(userclk), .CE(1'b1), .D(rxdata_int[7]), .Q(rxdata_reg[7]), .R(1'b0)); FDRE \rxdata_reg_reg[8] (.C(userclk), .CE(1'b1), .D(rxdata_int[8]), .Q(rxdata_reg[8]), .R(1'b0)); FDRE \rxdata_reg_reg[9] (.C(userclk), .CE(1'b1), .D(rxdata_int[9]), .Q(rxdata_reg[9]), .R(1'b0)); FDRE \rxdisperr_double_reg[0] (.C(userclk2), .CE(toggle), .D(rxdisperr_reg__0[0]), .Q(rxdisperr_double[0]), .R(reset_sync5)); FDRE \rxdisperr_double_reg[1] (.C(userclk2), .CE(toggle), .D(rxdisperr_reg__0[1]), .Q(rxdisperr_double[1]), .R(reset_sync5)); (* SOFT_HLUTNM = "soft_lutpair82" *) LUT3 #( .INIT(8'hB8)) rxdisperr_i_1 (.I0(rxdisperr_double[1]), .I1(toggle), .I2(rxdisperr_double[0]), .O(rxdisperr_i_1_n_0)); FDRE rxdisperr_reg (.C(userclk2), .CE(1'b1), .D(rxdisperr_i_1_n_0), .Q(rxdisperr), .R(reset_sync5)); FDRE \rxdisperr_reg_reg[0] (.C(userclk), .CE(1'b1), .D(rxdisperr_int[0]), .Q(rxdisperr_reg__0[0]), .R(1'b0)); FDRE \rxdisperr_reg_reg[1] (.C(userclk), .CE(1'b1), .D(rxdisperr_int[1]), .Q(rxdisperr_reg__0[1]), .R(1'b0)); FDRE \rxnotintable_double_reg[0] (.C(userclk2), .CE(toggle), .D(rxnotintable_reg__0[0]), .Q(rxnotintable_double[0]), .R(reset_sync5)); FDRE \rxnotintable_double_reg[1] (.C(userclk2), .CE(toggle), .D(rxnotintable_reg__0[1]), .Q(rxnotintable_double[1]), .R(reset_sync5)); (* SOFT_HLUTNM = "soft_lutpair82" *) LUT3 #( .INIT(8'hB8)) rxnotintable_i_1 (.I0(rxnotintable_double[1]), .I1(toggle), .I2(rxnotintable_double[0]), .O(rxnotintable_i_1_n_0)); FDRE rxnotintable_reg (.C(userclk2), .CE(1'b1), .D(rxnotintable_i_1_n_0), .Q(rxnotintable), .R(reset_sync5)); FDRE \rxnotintable_reg_reg[0] (.C(userclk), .CE(1'b1), .D(rxnotintable_int[0]), .Q(rxnotintable_reg__0[0]), .R(1'b0)); FDRE \rxnotintable_reg_reg[1] (.C(userclk), .CE(1'b1), .D(rxnotintable_int[1]), .Q(rxnotintable_reg__0[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) rxpowerdown_double_reg (.C(userclk2), .CE(toggle), .D(rxpowerdown_reg__0), .Q(rxpowerdown_double), .R(reset_sync5)); FDRE #( .INIT(1'b0)) rxpowerdown_reg (.C(userclk), .CE(1'b1), .D(rxpowerdown_double), .Q(rxpowerdown), .R(1'b0)); FDRE #( .INIT(1'b0)) rxpowerdown_reg_reg (.C(userclk2), .CE(1'b1), .D(powerdown), .Q(rxpowerdown_reg__0), .R(reset_sync5)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_16_1_sync_block_3 sync_block_data_valid (.data_out(data_valid_reg2), .independent_clock_bufg(independent_clock_bufg), .status_vector(status_vector)); LUT1 #( .INIT(2'h1)) toggle_i_1 (.I0(toggle), .O(toggle_i_1_n_0)); FDRE toggle_reg (.C(userclk2), .CE(1'b1), .D(toggle_i_1_n_0), .Q(toggle), .R(SR)); FDRE txbuferr_reg (.C(userclk2), .CE(1'b1), .D(txbufstatus_reg), .Q(txbuferr), .R(1'b0)); FDRE \txbufstatus_reg_reg[1] (.C(userclk), .CE(1'b1), .D(gtwizard_inst_n_7), .Q(txbufstatus_reg), .R(1'b0)); FDRE \txchardispmode_double_reg[0] (.C(userclk2), .CE(toggle_i_1_n_0), .D(p_1_in), .Q(txchardispmode_double[0]), .R(SR)); FDRE \txchardispmode_double_reg[1] (.C(userclk2), .CE(toggle_i_1_n_0), .D(D), .Q(txchardispmode_double[1]), .R(SR)); FDRE \txchardispmode_int_reg[0] (.C(userclk), .CE(1'b1), .D(txchardispmode_double[0]), .Q(txchardispmode_int[0]), .R(1'b0)); FDRE \txchardispmode_int_reg[1] (.C(userclk), .CE(1'b1), .D(txchardispmode_double[1]), .Q(txchardispmode_int[1]), .R(1'b0)); FDRE txchardispmode_reg_reg (.C(userclk2), .CE(1'b1), .D(D), .Q(p_1_in), .R(SR)); FDRE \txchardispval_double_reg[0] (.C(userclk2), .CE(toggle_i_1_n_0), .D(p_1_in__0), .Q(txchardispval_double[0]), .R(SR)); FDRE \txchardispval_double_reg[1] (.C(userclk2), .CE(toggle_i_1_n_0), .D(txchardispval_reg_reg_0), .Q(txchardispval_double[1]), .R(SR)); FDRE \txchardispval_int_reg[0] (.C(userclk), .CE(1'b1), .D(txchardispval_double[0]), .Q(txchardispval_int[0]), .R(1'b0)); FDRE \txchardispval_int_reg[1] (.C(userclk), .CE(1'b1), .D(txchardispval_double[1]), .Q(txchardispval_int[1]), .R(1'b0)); FDRE txchardispval_reg_reg (.C(userclk2), .CE(1'b1), .D(txchardispval_reg_reg_0), .Q(p_1_in__0), .R(SR)); FDRE \txcharisk_double_reg[0] (.C(userclk2), .CE(toggle_i_1_n_0), .D(p_1_in__2), .Q(txcharisk_double[0]), .R(SR)); FDRE \txcharisk_double_reg[1] (.C(userclk2), .CE(toggle_i_1_n_0), .D(txcharisk_reg_reg_0), .Q(txcharisk_double[1]), .R(SR)); FDRE \txcharisk_int_reg[0] (.C(userclk), .CE(1'b1), .D(txcharisk_double[0]), .Q(txcharisk_int[0]), .R(1'b0)); FDRE \txcharisk_int_reg[1] (.C(userclk), .CE(1'b1), .D(txcharisk_double[1]), .Q(txcharisk_int[1]), .R(1'b0)); FDRE txcharisk_reg_reg (.C(userclk2), .CE(1'b1), .D(txcharisk_reg_reg_0), .Q(p_1_in__2), .R(SR)); FDRE \txdata_double_reg[0] (.C(userclk2), .CE(toggle_i_1_n_0), .D(p_1_in__1[0]), .Q(txdata_double[0]), .R(SR)); FDRE \txdata_double_reg[10] (.C(userclk2), .CE(toggle_i_1_n_0), .D(\txdata_reg_reg[7]_0 [2]), .Q(txdata_double[10]), .R(SR)); FDRE \txdata_double_reg[11] (.C(userclk2), .CE(toggle_i_1_n_0), .D(\txdata_reg_reg[7]_0 [3]), .Q(txdata_double[11]), .R(SR)); FDRE \txdata_double_reg[12] (.C(userclk2), .CE(toggle_i_1_n_0), .D(\txdata_reg_reg[7]_0 [4]), .Q(txdata_double[12]), .R(SR)); FDRE \txdata_double_reg[13] (.C(userclk2), .CE(toggle_i_1_n_0), .D(\txdata_reg_reg[7]_0 [5]), .Q(txdata_double[13]), .R(SR)); FDRE \txdata_double_reg[14] (.C(userclk2), .CE(toggle_i_1_n_0), .D(\txdata_reg_reg[7]_0 [6]), .Q(txdata_double[14]), .R(SR)); FDRE \txdata_double_reg[15] (.C(userclk2), .CE(toggle_i_1_n_0), .D(\txdata_reg_reg[7]_0 [7]), .Q(txdata_double[15]), .R(SR)); FDRE \txdata_double_reg[1] (.C(userclk2), .CE(toggle_i_1_n_0), .D(p_1_in__1[1]), .Q(txdata_double[1]), .R(SR)); FDRE \txdata_double_reg[2] (.C(userclk2), .CE(toggle_i_1_n_0), .D(p_1_in__1[2]), .Q(txdata_double[2]), .R(SR)); FDRE \txdata_double_reg[3] (.C(userclk2), .CE(toggle_i_1_n_0), .D(p_1_in__1[3]), .Q(txdata_double[3]), .R(SR)); FDRE \txdata_double_reg[4] (.C(userclk2), .CE(toggle_i_1_n_0), .D(p_1_in__1[4]), .Q(txdata_double[4]), .R(SR)); FDRE \txdata_double_reg[5] (.C(userclk2), .CE(toggle_i_1_n_0), .D(p_1_in__1[5]), .Q(txdata_double[5]), .R(SR)); FDRE \txdata_double_reg[6] (.C(userclk2), .CE(toggle_i_1_n_0), .D(p_1_in__1[6]), .Q(txdata_double[6]), .R(SR)); FDRE \txdata_double_reg[7] (.C(userclk2), .CE(toggle_i_1_n_0), .D(p_1_in__1[7]), .Q(txdata_double[7]), .R(SR)); FDRE \txdata_double_reg[8] (.C(userclk2), .CE(toggle_i_1_n_0), .D(\txdata_reg_reg[7]_0 [0]), .Q(txdata_double[8]), .R(SR)); FDRE \txdata_double_reg[9] (.C(userclk2), .CE(toggle_i_1_n_0), .D(\txdata_reg_reg[7]_0 [1]), .Q(txdata_double[9]), .R(SR)); FDRE \txdata_int_reg[0] (.C(userclk), .CE(1'b1), .D(txdata_double[0]), .Q(txdata_int[0]), .R(1'b0)); FDRE \txdata_int_reg[10] (.C(userclk), .CE(1'b1), .D(txdata_double[10]), .Q(txdata_int[10]), .R(1'b0)); FDRE \txdata_int_reg[11] (.C(userclk), .CE(1'b1), .D(txdata_double[11]), .Q(txdata_int[11]), .R(1'b0)); FDRE \txdata_int_reg[12] (.C(userclk), .CE(1'b1), .D(txdata_double[12]), .Q(txdata_int[12]), .R(1'b0)); FDRE \txdata_int_reg[13] (.C(userclk), .CE(1'b1), .D(txdata_double[13]), .Q(txdata_int[13]), .R(1'b0)); FDRE \txdata_int_reg[14] (.C(userclk), .CE(1'b1), .D(txdata_double[14]), .Q(txdata_int[14]), .R(1'b0)); FDRE \txdata_int_reg[15] (.C(userclk), .CE(1'b1), .D(txdata_double[15]), .Q(txdata_int[15]), .R(1'b0)); FDRE \txdata_int_reg[1] (.C(userclk), .CE(1'b1), .D(txdata_double[1]), .Q(txdata_int[1]), .R(1'b0)); FDRE \txdata_int_reg[2] (.C(userclk), .CE(1'b1), .D(txdata_double[2]), .Q(txdata_int[2]), .R(1'b0)); FDRE \txdata_int_reg[3] (.C(userclk), .CE(1'b1), .D(txdata_double[3]), .Q(txdata_int[3]), .R(1'b0)); FDRE \txdata_int_reg[4] (.C(userclk), .CE(1'b1), .D(txdata_double[4]), .Q(txdata_int[4]), .R(1'b0)); FDRE \txdata_int_reg[5] (.C(userclk), .CE(1'b1), .D(txdata_double[5]), .Q(txdata_int[5]), .R(1'b0)); FDRE \txdata_int_reg[6] (.C(userclk), .CE(1'b1), .D(txdata_double[6]), .Q(txdata_int[6]), .R(1'b0)); FDRE \txdata_int_reg[7] (.C(userclk), .CE(1'b1), .D(txdata_double[7]), .Q(txdata_int[7]), .R(1'b0)); FDRE \txdata_int_reg[8] (.C(userclk), .CE(1'b1), .D(txdata_double[8]), .Q(txdata_int[8]), .R(1'b0)); FDRE \txdata_int_reg[9] (.C(userclk), .CE(1'b1), .D(txdata_double[9]), .Q(txdata_int[9]), .R(1'b0)); FDRE \txdata_reg_reg[0] (.C(userclk2), .CE(1'b1), .D(\txdata_reg_reg[7]_0 [0]), .Q(p_1_in__1[0]), .R(SR)); FDRE \txdata_reg_reg[1] (.C(userclk2), .CE(1'b1), .D(\txdata_reg_reg[7]_0 [1]), .Q(p_1_in__1[1]), .R(SR)); FDRE \txdata_reg_reg[2] (.C(userclk2), .CE(1'b1), .D(\txdata_reg_reg[7]_0 [2]), .Q(p_1_in__1[2]), .R(SR)); FDRE \txdata_reg_reg[3] (.C(userclk2), .CE(1'b1), .D(\txdata_reg_reg[7]_0 [3]), .Q(p_1_in__1[3]), .R(SR)); FDRE \txdata_reg_reg[4] (.C(userclk2), .CE(1'b1), .D(\txdata_reg_reg[7]_0 [4]), .Q(p_1_in__1[4]), .R(SR)); FDRE \txdata_reg_reg[5] (.C(userclk2), .CE(1'b1), .D(\txdata_reg_reg[7]_0 [5]), .Q(p_1_in__1[5]), .R(SR)); FDRE \txdata_reg_reg[6] (.C(userclk2), .CE(1'b1), .D(\txdata_reg_reg[7]_0 [6]), .Q(p_1_in__1[6]), .R(SR)); FDRE \txdata_reg_reg[7] (.C(userclk2), .CE(1'b1), .D(\txdata_reg_reg[7]_0 [7]), .Q(p_1_in__1[7]), .R(SR)); FDRE #( .INIT(1'b0)) txpowerdown_double_reg (.C(userclk2), .CE(1'b1), .D(txpowerdown_reg__0), .Q(txpowerdown_double), .R(SR)); FDRE #( .INIT(1'b0)) txpowerdown_reg (.C(userclk), .CE(1'b1), .D(txpowerdown_double), .Q(txpowerdown), .R(1'b0)); FDRE #( .INIT(1'b0)) txpowerdown_reg_reg (.C(userclk2), .CE(1'b1), .D(powerdown), .Q(txpowerdown_reg__0), .R(SR)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPCS_PMA_GEN (MGT_TX_RESET, status_vector, \NO_MANAGEMENT.CONFIGURATION_VECTOR_REG_reg[3]_0 , \NO_MANAGEMENT.CONFIGURATION_VECTOR_REG_reg[2]_0 , MGT_RX_RESET, gmii_rxd, gmii_rx_er, txchardispmode, txcharisk, txdata, gmii_rx_dv, enablealign, txchardispval, userclk2, dcm_locked, signal_detect, reset, gmii_tx_en, gmii_tx_er, configuration_vector, gmii_txd, rxnotintable, rxbufstatus, txbuferr, rxdisperr, rxclkcorcnt, rxcharisk, rxchariscomma, reset_done, rxdata); output MGT_TX_RESET; output [6:0]status_vector; output \NO_MANAGEMENT.CONFIGURATION_VECTOR_REG_reg[3]_0 ; output \NO_MANAGEMENT.CONFIGURATION_VECTOR_REG_reg[2]_0 ; output MGT_RX_RESET; output [7:0]gmii_rxd; output gmii_rx_er; output txchardispmode; output txcharisk; output [7:0]txdata; output gmii_rx_dv; output enablealign; output txchardispval; input userclk2; input dcm_locked; input signal_detect; input reset; input gmii_tx_en; input gmii_tx_er; input [2:0]configuration_vector; input [7:0]gmii_txd; input [0:0]rxnotintable; input [0:0]rxbufstatus; input txbuferr; input [0:0]rxdisperr; input [1:0]rxclkcorcnt; input [0:0]rxcharisk; input [0:0]rxchariscomma; input reset_done; input [7:0]rxdata; wire [1:1]CONFIGURATION_VECTOR_REG; wire D; wire \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[0] ; wire \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[10] ; wire \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[11] ; wire \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[12] ; wire \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[13] ; wire \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[1] ; wire \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[2] ; wire \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[3] ; wire \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[4] ; wire \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[5] ; wire \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[6] ; wire \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[7] ; wire \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[8] ; wire \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[9] ; wire \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[0] ; wire \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[10] ; wire \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[11] ; wire \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[12] ; wire \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[13] ; wire \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[1] ; wire \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[2] ; wire \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[3] ; wire \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[4] ; wire \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[5] ; wire \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[6] ; wire \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[7] ; wire \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[8] ; wire \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[9] ; wire I0; wire \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_0 ; wire \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_1 ; wire \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_10 ; wire \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_11 ; wire \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_12 ; wire \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_13 ; wire \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_14 ; wire \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_15 ; wire \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_16 ; wire \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_17 ; wire \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_18 ; wire \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_19 ; wire \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_2 ; wire \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_20 ; wire \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_21 ; wire \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_3 ; wire \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_4 ; wire \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_5 ; wire \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_6 ; wire \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_7 ; wire \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_8 ; wire \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_9 ; wire \MGT_RESET.SYNC_ASYNC_RESET_n_0 ; wire MGT_RX_RESET; wire MGT_RX_RESET_INT__0; wire MGT_TX_RESET; wire MGT_TX_RESET_INT__0; wire \NO_MANAGEMENT.CONFIGURATION_VECTOR_REG[1]_i_1_n_0 ; wire \NO_MANAGEMENT.CONFIGURATION_VECTOR_REG[2]_i_1_n_0 ; wire \NO_MANAGEMENT.CONFIGURATION_VECTOR_REG[3]_i_1_n_0 ; wire \NO_MANAGEMENT.CONFIGURATION_VECTOR_REG_reg[2]_0 ; wire \NO_MANAGEMENT.CONFIGURATION_VECTOR_REG_reg[3]_0 ; (* async_reg = "true" *) wire RESET_INT; (* async_reg = "true" *) wire RESET_INT_PIPE; (* async_reg = "true" *) wire RESET_INT_PIPE_RXRECCLK; (* async_reg = "true" *) wire RESET_INT_RXRECCLK; wire RXCLKCORCNT_INT; wire RXDISPERR_SRL1_out; wire RXEVEN0_out; wire RXNOTINTABLE_INT; wire RXNOTINTABLE_SRL0_out; (* async_reg = "true" *) wire RXRECRESET; (* async_reg = "true" *) wire RXRECRESET_PIPE; (* async_reg = "true" *) wire RXRECRESET_PIPE_1; (* async_reg = "true" *) wire RXRECRESET_PIPE_2; (* async_reg = "true" *) wire RXRECRESET_PIPE_3; wire RXSYNC_STATUS; wire \RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK_n_6 ; wire \RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK_n_7 ; wire S2; wire SIGNAL_DETECT_MOD; wire SOFT_RESET_RXRECCLK; (* async_reg = "true" *) wire SRESET; (* async_reg = "true" *) wire SRESET_PIPE; wire STATUS_VECTOR_0_PRE; wire STATUS_VECTOR_0_PRE0; wire SYNC_STATUS_REG; wire SYNC_STATUS_REG0; wire TXBUFERR_INT; wire \USE_ROCKET_IO.MGT_TX_RESET_INT_i_3_n_0 ; wire \USE_ROCKET_IO.MGT_TX_RESET_INT_i_4_n_0 ; wire \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXBUFSTATUS_INT_reg_n_0_[1] ; wire \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCHARISCOMMA_INT_reg_n_0 ; wire \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCHARISK_INT_reg_n_0 ; wire \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCLKCORCNT_INT_reg_n_0_[0] ; wire \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCLKCORCNT_INT_reg_n_0_[1] ; wire \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[0] ; wire \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[1] ; wire \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[2] ; wire \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[3] ; wire \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[4] ; wire \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[5] ; wire \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[6] ; wire \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[7] ; wire \USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.MGT_RX_RESET_INT_i_3_n_0 ; wire \USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.MGT_RX_RESET_INT_i_4_n_0 ; wire [2:0]configuration_vector; wire dcm_locked; wire enablealign; wire gmii_rx_dv; wire gmii_rx_er; wire [7:0]gmii_rxd; wire gmii_tx_en; wire gmii_tx_er; wire [7:0]gmii_txd; wire p_0_out; wire p_1_out; wire p_6_out; wire reset; wire reset_done; wire [0:0]rxbufstatus; wire [0:0]rxchariscomma; wire [0:0]rxcharisk; wire [1:0]rxclkcorcnt; wire [7:0]rxdata; wire [0:0]rxdisperr; wire [0:0]rxnotintable; wire signal_detect; wire [6:0]status_vector; wire txbuferr; wire txchardispmode; wire txchardispval; wire txcharisk; wire [7:0]txdata; wire userclk2; (* XILINX_LEGACY_PRIM = "SRL16" *) (* box_type = "PRIMITIVE" *) (* srl_name = "U0/gig_ethernet_pcs_pma_16_1_core/\gpcs_pma_inst/DELAY_ERROR_TXOUTCLK.DELAY_RXDISPERR " *) SRL16E #( .INIT(16'h0000)) \DELAY_ERROR_TXOUTCLK.DELAY_RXDISPERR (.A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .CE(1'b1), .CLK(userclk2), .D(D), .Q(RXDISPERR_SRL1_out)); (* XILINX_LEGACY_PRIM = "SRL16" *) (* box_type = "PRIMITIVE" *) (* srl_name = "U0/gig_ethernet_pcs_pma_16_1_core/\gpcs_pma_inst/DELAY_ERROR_TXOUTCLK.DELAY_RXNOTINTABLE " *) SRL16E #( .INIT(16'h0000)) \DELAY_ERROR_TXOUTCLK.DELAY_RXNOTINTABLE (.A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .CE(1'b1), .CLK(userclk2), .D(RXNOTINTABLE_INT), .Q(RXNOTINTABLE_SRL0_out)); FDRE #( .INIT(1'b0)) \DELAY_ERROR_TXOUTCLK.RXDISPERR_REG_reg (.C(userclk2), .CE(1'b1), .D(RXDISPERR_SRL1_out), .Q(status_vector[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \DELAY_ERROR_TXOUTCLK.RXNOTINTABLE_REG_reg (.C(userclk2), .CE(1'b1), .D(RXNOTINTABLE_SRL0_out), .Q(status_vector[6]), .R(1'b0)); (* FSM_ENCODED_STATES = "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000" *) FDSE #( .INIT(1'b1)) \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[0] (.C(userclk2), .CE(1'b1), .D(1'b0), .Q(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[0] ), .S(p_0_out)); (* FSM_ENCODED_STATES = "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[10] (.C(userclk2), .CE(1'b1), .D(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[9] ), .Q(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[10] ), .R(p_0_out)); (* FSM_ENCODED_STATES = "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[11] (.C(userclk2), .CE(1'b1), .D(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[10] ), .Q(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[11] ), .R(p_0_out)); (* FSM_ENCODED_STATES = "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[12] (.C(userclk2), .CE(1'b1), .D(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[11] ), .Q(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[12] ), .R(p_0_out)); (* FSM_ENCODED_STATES = "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[13] (.C(userclk2), .CE(1'b1), .D(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[12] ), .Q(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[13] ), .R(p_0_out)); (* FSM_ENCODED_STATES = "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[1] (.C(userclk2), .CE(1'b1), .D(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[0] ), .Q(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[1] ), .R(p_0_out)); (* FSM_ENCODED_STATES = "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[2] (.C(userclk2), .CE(1'b1), .D(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[1] ), .Q(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[2] ), .R(p_0_out)); (* FSM_ENCODED_STATES = "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[3] (.C(userclk2), .CE(1'b1), .D(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[2] ), .Q(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[3] ), .R(p_0_out)); (* FSM_ENCODED_STATES = "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[4] (.C(userclk2), .CE(1'b1), .D(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[3] ), .Q(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[4] ), .R(p_0_out)); (* FSM_ENCODED_STATES = "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[5] (.C(userclk2), .CE(1'b1), .D(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[4] ), .Q(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[5] ), .R(p_0_out)); (* FSM_ENCODED_STATES = "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[6] (.C(userclk2), .CE(1'b1), .D(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[5] ), .Q(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[6] ), .R(p_0_out)); (* FSM_ENCODED_STATES = "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[7] (.C(userclk2), .CE(1'b1), .D(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[6] ), .Q(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[7] ), .R(p_0_out)); (* FSM_ENCODED_STATES = "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[8] (.C(userclk2), .CE(1'b1), .D(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[7] ), .Q(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[8] ), .R(p_0_out)); (* FSM_ENCODED_STATES = "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg[9] (.C(userclk2), .CE(1'b1), .D(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[8] ), .Q(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[9] ), .R(p_0_out)); (* FSM_ENCODED_STATES = "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000" *) FDSE #( .INIT(1'b1)) \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[0] (.C(userclk2), .CE(1'b1), .D(1'b0), .Q(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[0] ), .S(p_1_out)); (* FSM_ENCODED_STATES = "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[10] (.C(userclk2), .CE(1'b1), .D(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[9] ), .Q(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[10] ), .R(p_1_out)); (* FSM_ENCODED_STATES = "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[11] (.C(userclk2), .CE(1'b1), .D(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[10] ), .Q(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[11] ), .R(p_1_out)); (* FSM_ENCODED_STATES = "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[12] (.C(userclk2), .CE(1'b1), .D(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[11] ), .Q(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[12] ), .R(p_1_out)); (* FSM_ENCODED_STATES = "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[13] (.C(userclk2), .CE(1'b1), .D(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[12] ), .Q(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[13] ), .R(p_1_out)); (* FSM_ENCODED_STATES = "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[1] (.C(userclk2), .CE(1'b1), .D(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[0] ), .Q(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[1] ), .R(p_1_out)); (* FSM_ENCODED_STATES = "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[2] (.C(userclk2), .CE(1'b1), .D(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[1] ), .Q(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[2] ), .R(p_1_out)); (* FSM_ENCODED_STATES = "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[3] (.C(userclk2), .CE(1'b1), .D(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[2] ), .Q(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[3] ), .R(p_1_out)); (* FSM_ENCODED_STATES = "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[4] (.C(userclk2), .CE(1'b1), .D(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[3] ), .Q(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[4] ), .R(p_1_out)); (* FSM_ENCODED_STATES = "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[5] (.C(userclk2), .CE(1'b1), .D(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[4] ), .Q(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[5] ), .R(p_1_out)); (* FSM_ENCODED_STATES = "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[6] (.C(userclk2), .CE(1'b1), .D(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[5] ), .Q(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[6] ), .R(p_1_out)); (* FSM_ENCODED_STATES = "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[7] (.C(userclk2), .CE(1'b1), .D(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[6] ), .Q(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[7] ), .R(p_1_out)); (* FSM_ENCODED_STATES = "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[8] (.C(userclk2), .CE(1'b1), .D(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[7] ), .Q(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[8] ), .R(p_1_out)); (* FSM_ENCODED_STATES = "iSTATE:000000000001000,iSTATE0:000000000010000,iSTATE1:010000000000000,iSTATE2:000000000000100,iSTATE3:000100000000000,iSTATE4:001000000000000,iSTATE5:000010000000000,iSTATE6:000000000000010,iSTATE7:000000000000001,iSTATE8:000001000000000,iSTATE9:000000010000000,iSTATE10:000000100000000,iSTATE11:000000001000000,iSTATE12:100000000000000,iSTATE13:000000000100000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg[9] (.C(userclk2), .CE(1'b1), .D(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[8] ), .Q(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[9] ), .R(p_1_out)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_TX \IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER (.\CODE_GRP_CNT_reg[0]_0 (\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_5 ), .\CODE_GRP_CNT_reg[0]_1 (\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_6 ), .CONFIGURATION_VECTOR_REG(CONFIGURATION_VECTOR_REG), .D({\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_1 ,\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_2 ,\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_3 ,\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_4 }), .\NO_QSGMII_CHAR.TXCHARDISPVAL_reg_0 (\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_13 ), .\NO_QSGMII_DATA.TXCHARISK_reg_0 (\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_7 ), .\NO_QSGMII_DATA.TXCHARISK_reg_1 (\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_8 ), .\NO_QSGMII_DATA.TXDATA_reg[2]_0 (\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_9 ), .\NO_QSGMII_DATA.TXDATA_reg[3]_0 (\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_10 ), .\NO_QSGMII_DATA.TXDATA_reg[4]_0 (MGT_TX_RESET), .\NO_QSGMII_DATA.TXDATA_reg[5]_0 (\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_11 ), .\NO_QSGMII_DATA.TXDATA_reg[7]_0 (\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_12 ), .\NO_QSGMII_DATA.TXDATA_reg[7]_1 ({\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_14 ,\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_15 ,\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_16 ,\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_17 ,\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_18 ,\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_19 ,\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_20 ,\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_21 }), .SR(\NO_MANAGEMENT.CONFIGURATION_VECTOR_REG_reg[3]_0 ), .\USE_ROCKET_IO.MGT_TX_RESET_INT_reg (\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_0 ), .gmii_tx_en(gmii_tx_en), .gmii_tx_er(gmii_tx_er), .gmii_txd(gmii_txd), .rxchariscomma(rxchariscomma), .rxcharisk(rxcharisk), .rxdata(rxdata), .userclk2(userclk2)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) \MGT_RESET.RESET_INT_PIPE_RXRECCLK_reg (.C(1'b0), .CE(1'b1), .D(1'b0), .PRE(p_6_out), .Q(RESET_INT_PIPE_RXRECCLK)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) \MGT_RESET.RESET_INT_PIPE_reg (.C(userclk2), .CE(1'b1), .D(1'b0), .PRE(\MGT_RESET.SYNC_ASYNC_RESET_n_0 ), .Q(RESET_INT_PIPE)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) \MGT_RESET.RESET_INT_RXRECCLK_reg (.C(1'b0), .CE(1'b1), .D(RESET_INT_PIPE_RXRECCLK), .PRE(p_6_out), .Q(RESET_INT_RXRECCLK)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) \MGT_RESET.RESET_INT_reg (.C(userclk2), .CE(1'b1), .D(RESET_INT_PIPE), .PRE(\MGT_RESET.SYNC_ASYNC_RESET_n_0 ), .Q(RESET_INT)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \MGT_RESET.SRESET_PIPE_reg (.C(userclk2), .CE(1'b1), .D(RESET_INT), .Q(SRESET_PIPE), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDSE #( .INIT(1'b0)) \MGT_RESET.SRESET_reg (.C(userclk2), .CE(1'b1), .D(SRESET_PIPE), .Q(SRESET), .S(RESET_INT)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_sync_block \MGT_RESET.SYNC_ASYNC_RESET (.dcm_locked(dcm_locked), .reset(reset), .reset_sync6_0(\MGT_RESET.SYNC_ASYNC_RESET_n_0 ), .userclk2(userclk2)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_sync_block_17 \MGT_RESET.SYNC_ASYNC_RESET_RECCLK (.dcm_locked(dcm_locked), .p_6_out(p_6_out), .reset(reset), .reset_out(SOFT_RESET_RXRECCLK)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_sync_block_18 \MGT_RESET.SYNC_SOFT_RESET_RECCLK (.reset_out(SOFT_RESET_RXRECCLK)); LUT2 #( .INIT(4'h2)) \NO_MANAGEMENT.CONFIGURATION_VECTOR_REG[1]_i_1 (.I0(configuration_vector[0]), .I1(SRESET), .O(\NO_MANAGEMENT.CONFIGURATION_VECTOR_REG[1]_i_1_n_0 )); LUT2 #( .INIT(4'h2)) \NO_MANAGEMENT.CONFIGURATION_VECTOR_REG[2]_i_1 (.I0(configuration_vector[1]), .I1(SRESET), .O(\NO_MANAGEMENT.CONFIGURATION_VECTOR_REG[2]_i_1_n_0 )); LUT2 #( .INIT(4'h2)) \NO_MANAGEMENT.CONFIGURATION_VECTOR_REG[3]_i_1 (.I0(configuration_vector[2]), .I1(SRESET), .O(\NO_MANAGEMENT.CONFIGURATION_VECTOR_REG[3]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \NO_MANAGEMENT.CONFIGURATION_VECTOR_REG_reg[1] (.C(userclk2), .CE(1'b1), .D(\NO_MANAGEMENT.CONFIGURATION_VECTOR_REG[1]_i_1_n_0 ), .Q(CONFIGURATION_VECTOR_REG), .R(1'b0)); FDRE #( .INIT(1'b0)) \NO_MANAGEMENT.CONFIGURATION_VECTOR_REG_reg[2] (.C(userclk2), .CE(1'b1), .D(\NO_MANAGEMENT.CONFIGURATION_VECTOR_REG[2]_i_1_n_0 ), .Q(\NO_MANAGEMENT.CONFIGURATION_VECTOR_REG_reg[2]_0 ), .R(1'b0)); FDRE #( .INIT(1'b0)) \NO_MANAGEMENT.CONFIGURATION_VECTOR_REG_reg[3] (.C(userclk2), .CE(1'b1), .D(\NO_MANAGEMENT.CONFIGURATION_VECTOR_REG[3]_i_1_n_0 ), .Q(\NO_MANAGEMENT.CONFIGURATION_VECTOR_REG_reg[3]_0 ), .R(1'b0)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_RX \RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK (.CGBAD_reg_0(\USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXBUFSTATUS_INT_reg_n_0_[1] ), .C_HDR_REMOVED_REG_reg_0({\USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCLKCORCNT_INT_reg_n_0_[1] ,\USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCLKCORCNT_INT_reg_n_0_[0] }), .D(D), .FALSE_NIT_reg_0(\RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK_n_7 ), .I0(I0), .Q({\USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[7] ,\USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[6] ,\USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[5] ,\USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[4] ,\USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[3] ,\USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[2] ,\USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[1] ,\USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[0] }), .RUDI_I_reg_0(MGT_RX_RESET), .RXCHARISK_REG1_reg_0(\USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCHARISK_INT_reg_n_0 ), .RXEVEN0_out(RXEVEN0_out), .RXNOTINTABLE_INT(RXNOTINTABLE_INT), .RXSYNC_STATUS(RXSYNC_STATUS), .RX_ER_reg_0(\NO_MANAGEMENT.CONFIGURATION_VECTOR_REG_reg[2]_0 ), .S2(S2), .SR(\NO_MANAGEMENT.CONFIGURATION_VECTOR_REG_reg[3]_0 ), .SYNC_STATUS_REG0(SYNC_STATUS_REG0), .\USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCHARISK_INT_reg (\RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK_n_6 ), .gmii_rx_dv(gmii_rx_dv), .gmii_rx_er(gmii_rx_er), .gmii_rxd(gmii_rxd), .status_vector(status_vector[4:2]), .userclk2(userclk2)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SYNCHRONISE \RX_GMII_AT_TXOUTCLK.SYNCHRONISATION (.CONFIGURATION_VECTOR_REG(CONFIGURATION_VECTOR_REG), .D(D), .EVEN_reg_0(MGT_RX_RESET), .\FSM_onehot_STATE_reg[0]_0 (\USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXBUFSTATUS_INT_reg_n_0_[1] ), .\FSM_onehot_STATE_reg[1]_0 (\USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCHARISCOMMA_INT_reg_n_0 ), .\FSM_onehot_STATE_reg[2]_0 (\USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCHARISK_INT_reg_n_0 ), .I0(I0), .I_reg(\RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK_n_6 ), .I_reg_0(\RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK_n_7 ), .RXEVEN0_out(RXEVEN0_out), .RXNOTINTABLE_INT(RXNOTINTABLE_INT), .RXSYNC_STATUS(RXSYNC_STATUS), .S2(S2), .SIGNAL_DETECT_MOD(SIGNAL_DETECT_MOD), .STATUS_VECTOR_0_PRE0(STATUS_VECTOR_0_PRE0), .SYNC_STATUS_REG0(SYNC_STATUS_REG0), .enablealign(enablealign), .reset_done(reset_done), .userclk2(userclk2)); FDRE #( .INIT(1'b0)) STATUS_VECTOR_0_PRE_reg (.C(userclk2), .CE(1'b1), .D(STATUS_VECTOR_0_PRE0), .Q(STATUS_VECTOR_0_PRE), .R(1'b0)); FDRE \STATUS_VECTOR_reg[0] (.C(userclk2), .CE(1'b1), .D(STATUS_VECTOR_0_PRE), .Q(status_vector[0]), .R(1'b0)); FDRE \STATUS_VECTOR_reg[1] (.C(userclk2), .CE(1'b1), .D(SYNC_STATUS_REG), .Q(status_vector[1]), .R(1'b0)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sync_block SYNC_SIGNAL_DETECT (.SIGNAL_DETECT_MOD(SIGNAL_DETECT_MOD), .SIGNAL_DETECT_REG_reg(\NO_MANAGEMENT.CONFIGURATION_VECTOR_REG_reg[2]_0 ), .signal_detect(signal_detect), .userclk2(userclk2)); FDRE #( .INIT(1'b0)) SYNC_STATUS_REG_reg (.C(userclk2), .CE(1'b1), .D(RXSYNC_STATUS), .Q(SYNC_STATUS_REG), .R(1'b0)); LUT2 #( .INIT(4'hE)) \USE_ROCKET_IO.MGT_TX_RESET_INT_i_1 (.I0(RESET_INT), .I1(TXBUFERR_INT), .O(p_1_out)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \USE_ROCKET_IO.MGT_TX_RESET_INT_i_2 (.I0(\USE_ROCKET_IO.MGT_TX_RESET_INT_i_3_n_0 ), .I1(\USE_ROCKET_IO.MGT_TX_RESET_INT_i_4_n_0 ), .I2(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[6] ), .I3(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[7] ), .I4(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[4] ), .I5(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[5] ), .O(MGT_TX_RESET_INT__0)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \USE_ROCKET_IO.MGT_TX_RESET_INT_i_3 (.I0(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[13] ), .I1(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[12] ), .I2(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[9] ), .I3(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[8] ), .I4(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[11] ), .I5(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[10] ), .O(\USE_ROCKET_IO.MGT_TX_RESET_INT_i_3_n_0 )); LUT4 #( .INIT(16'hFFFE)) \USE_ROCKET_IO.MGT_TX_RESET_INT_i_4 (.I0(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[2] ), .I1(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[3] ), .I2(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[0] ), .I3(\FSM_onehot_USE_ROCKET_IO.TX_RST_SM_reg_n_0_[1] ), .O(\USE_ROCKET_IO.MGT_TX_RESET_INT_i_4_n_0 )); FDSE #( .INIT(1'b0)) \USE_ROCKET_IO.MGT_TX_RESET_INT_reg (.C(userclk2), .CE(1'b1), .D(MGT_TX_RESET_INT__0), .Q(MGT_TX_RESET), .S(p_1_out)); FDRE #( .INIT(1'b0)) \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXBUFSTATUS_INT_reg[1] (.C(userclk2), .CE(1'b1), .D(rxbufstatus), .Q(\USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXBUFSTATUS_INT_reg_n_0_[1] ), .R(RXCLKCORCNT_INT)); FDRE #( .INIT(1'b0)) \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCHARISCOMMA_INT_reg (.C(userclk2), .CE(1'b1), .D(\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_8 ), .Q(\USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCHARISCOMMA_INT_reg_n_0 ), .R(MGT_RX_RESET)); FDRE #( .INIT(1'b0)) \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCHARISK_INT_reg (.C(userclk2), .CE(1'b1), .D(\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_7 ), .Q(\USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCHARISK_INT_reg_n_0 ), .R(MGT_RX_RESET)); FDRE #( .INIT(1'b0)) \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCLKCORCNT_INT_reg[0] (.C(userclk2), .CE(1'b1), .D(rxclkcorcnt[0]), .Q(\USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCLKCORCNT_INT_reg_n_0_[0] ), .R(RXCLKCORCNT_INT)); FDRE #( .INIT(1'b0)) \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCLKCORCNT_INT_reg[1] (.C(userclk2), .CE(1'b1), .D(rxclkcorcnt[1]), .Q(\USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCLKCORCNT_INT_reg_n_0_[1] ), .R(RXCLKCORCNT_INT)); FDRE #( .INIT(1'b0)) \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg[0] (.C(userclk2), .CE(1'b1), .D(\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_21 ), .Q(\USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[0] ), .R(MGT_RX_RESET)); FDRE #( .INIT(1'b0)) \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg[1] (.C(userclk2), .CE(1'b1), .D(\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_20 ), .Q(\USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[1] ), .R(MGT_RX_RESET)); FDRE #( .INIT(1'b0)) \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg[2] (.C(userclk2), .CE(1'b1), .D(\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_19 ), .Q(\USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[2] ), .R(MGT_RX_RESET)); FDRE #( .INIT(1'b0)) \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg[3] (.C(userclk2), .CE(1'b1), .D(\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_18 ), .Q(\USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[3] ), .R(MGT_RX_RESET)); FDRE #( .INIT(1'b0)) \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg[4] (.C(userclk2), .CE(1'b1), .D(\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_17 ), .Q(\USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[4] ), .R(MGT_RX_RESET)); FDRE #( .INIT(1'b0)) \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg[5] (.C(userclk2), .CE(1'b1), .D(\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_16 ), .Q(\USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[5] ), .R(MGT_RX_RESET)); FDRE #( .INIT(1'b0)) \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg[6] (.C(userclk2), .CE(1'b1), .D(\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_15 ), .Q(\USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[6] ), .R(MGT_RX_RESET)); FDRE #( .INIT(1'b0)) \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg[7] (.C(userclk2), .CE(1'b1), .D(\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_14 ), .Q(\USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT_reg_n_0_[7] ), .R(MGT_RX_RESET)); FDRE #( .INIT(1'b0)) \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDISPERR_INT_reg (.C(userclk2), .CE(1'b1), .D(rxdisperr), .Q(D), .R(RXCLKCORCNT_INT)); LUT2 #( .INIT(4'hE)) \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXNOTINTABLE_INT_i_1 (.I0(CONFIGURATION_VECTOR_REG), .I1(MGT_RX_RESET), .O(RXCLKCORCNT_INT)); FDRE #( .INIT(1'b0)) \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXNOTINTABLE_INT_reg (.C(userclk2), .CE(1'b1), .D(rxnotintable), .Q(RXNOTINTABLE_INT), .R(RXCLKCORCNT_INT)); LUT2 #( .INIT(4'hE)) \USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.MGT_RX_RESET_INT_i_1 (.I0(\USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXBUFSTATUS_INT_reg_n_0_[1] ), .I1(RESET_INT), .O(p_0_out)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.MGT_RX_RESET_INT_i_2 (.I0(\USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.MGT_RX_RESET_INT_i_3_n_0 ), .I1(\USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.MGT_RX_RESET_INT_i_4_n_0 ), .I2(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[6] ), .I3(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[7] ), .I4(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[4] ), .I5(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[5] ), .O(MGT_RX_RESET_INT__0)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.MGT_RX_RESET_INT_i_3 (.I0(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[13] ), .I1(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[12] ), .I2(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[9] ), .I3(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[8] ), .I4(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[11] ), .I5(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[10] ), .O(\USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.MGT_RX_RESET_INT_i_3_n_0 )); LUT4 #( .INIT(16'hFFFE)) \USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.MGT_RX_RESET_INT_i_4 (.I0(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[2] ), .I1(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[3] ), .I2(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[0] ), .I3(\FSM_onehot_USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.RX_RST_SM_reg_n_0_[1] ), .O(\USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.MGT_RX_RESET_INT_i_4_n_0 )); FDSE #( .INIT(1'b0)) \USE_ROCKET_IO.RX_RST_SM_TXOUTCLK.MGT_RX_RESET_INT_reg (.C(userclk2), .CE(1'b1), .D(MGT_RX_RESET_INT__0), .Q(MGT_RX_RESET), .S(p_0_out)); FDRE #( .INIT(1'b0)) \USE_ROCKET_IO.TXBUFERR_INT_reg (.C(userclk2), .CE(1'b1), .D(txbuferr), .Q(TXBUFERR_INT), .R(MGT_TX_RESET)); FDRE \USE_ROCKET_IO.TXCHARDISPMODE_reg (.C(userclk2), .CE(1'b1), .D(\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_5 ), .Q(txchardispmode), .R(MGT_TX_RESET)); FDRE \USE_ROCKET_IO.TXCHARDISPVAL_reg (.C(userclk2), .CE(1'b1), .D(\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_13 ), .Q(txchardispval), .R(1'b0)); FDRE \USE_ROCKET_IO.TXCHARISK_reg (.C(userclk2), .CE(1'b1), .D(\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_6 ), .Q(txcharisk), .R(MGT_TX_RESET)); FDRE \USE_ROCKET_IO.TXDATA_reg[0] (.C(userclk2), .CE(1'b1), .D(\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_4 ), .Q(txdata[0]), .R(1'b0)); FDRE \USE_ROCKET_IO.TXDATA_reg[1] (.C(userclk2), .CE(1'b1), .D(\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_3 ), .Q(txdata[1]), .R(1'b0)); FDSE \USE_ROCKET_IO.TXDATA_reg[2] (.C(userclk2), .CE(1'b1), .D(\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_9 ), .Q(txdata[2]), .S(\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_0 )); FDSE \USE_ROCKET_IO.TXDATA_reg[3] (.C(userclk2), .CE(1'b1), .D(\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_10 ), .Q(txdata[3]), .S(\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_0 )); FDRE \USE_ROCKET_IO.TXDATA_reg[4] (.C(userclk2), .CE(1'b1), .D(\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_2 ), .Q(txdata[4]), .R(1'b0)); FDSE \USE_ROCKET_IO.TXDATA_reg[5] (.C(userclk2), .CE(1'b1), .D(\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_11 ), .Q(txdata[5]), .S(\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_0 )); FDRE \USE_ROCKET_IO.TXDATA_reg[6] (.C(userclk2), .CE(1'b1), .D(\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_1 ), .Q(txdata[6]), .R(1'b0)); FDSE \USE_ROCKET_IO.TXDATA_reg[7] (.C(userclk2), .CE(1'b1), .D(\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_12 ), .Q(txdata[7]), .S(\IS_2_5G_DISABLED_PRE_SHRINK.TRANSMITTER_n_0 )); LUT1 #( .INIT(2'h2)) i_0 (.I0(1'b1), .O(RXRECRESET)); LUT1 #( .INIT(2'h2)) i_1 (.I0(1'b1), .O(RXRECRESET_PIPE)); LUT1 #( .INIT(2'h2)) i_2 (.I0(1'b1), .O(RXRECRESET_PIPE_1)); LUT1 #( .INIT(2'h2)) i_3 (.I0(1'b1), .O(RXRECRESET_PIPE_2)); LUT1 #( .INIT(2'h2)) i_4 (.I0(1'b1), .O(RXRECRESET_PIPE_3)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_RX (S2, gmii_rx_er, status_vector, gmii_rx_dv, \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCHARISK_INT_reg , FALSE_NIT_reg_0, gmii_rxd, Q, userclk2, RUDI_I_reg_0, I0, SYNC_STATUS_REG0, RXCHARISK_REG1_reg_0, RXSYNC_STATUS, RXNOTINTABLE_INT, D, CGBAD_reg_0, RXEVEN0_out, SR, RX_ER_reg_0, C_HDR_REMOVED_REG_reg_0); output S2; output gmii_rx_er; output [2:0]status_vector; output gmii_rx_dv; output \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCHARISK_INT_reg ; output FALSE_NIT_reg_0; output [7:0]gmii_rxd; input [7:0]Q; input userclk2; input RUDI_I_reg_0; input I0; input SYNC_STATUS_REG0; input RXCHARISK_REG1_reg_0; input RXSYNC_STATUS; input RXNOTINTABLE_INT; input D; input CGBAD_reg_0; input RXEVEN0_out; input [0:0]SR; input RX_ER_reg_0; input [1:0]C_HDR_REMOVED_REG_reg_0; wire C; wire C0; wire CGBAD; wire CGBAD_REG1; wire CGBAD_REG2; wire CGBAD_REG3; wire CGBAD_reg_0; wire C_HDR_REMOVED; wire C_HDR_REMOVED_REG; wire [1:0]C_HDR_REMOVED_REG_reg_0; wire C_REG1; wire C_REG2; wire C_REG3; wire D; wire D0p0; wire D0p0_REG; wire D0p0_REG_i_2_n_0; wire EOP; wire EOP0; wire EOP_REG1; wire EOP_REG10; wire EOP_i_2_n_0; wire EXTEND; wire EXTEND_ERR; wire EXTEND_ERR0; wire EXTEND_REG1; wire EXTEND_REG2; wire EXTEND_REG3; wire EXTEND_i_1_n_0; wire EXT_ILLEGAL_K; wire EXT_ILLEGAL_K0; wire EXT_ILLEGAL_K_REG1; wire EXT_ILLEGAL_K_REG2; wire FALSE_CARRIER; wire FALSE_CARRIER0; wire FALSE_CARRIER_REG1; wire FALSE_CARRIER_REG2; wire FALSE_CARRIER_REG3; wire FALSE_CARRIER_i_1_n_0; wire FALSE_CARRIER_i_3_n_0; wire FALSE_DATA; wire FALSE_DATA0; wire FALSE_DATA_i_2_n_0; wire FALSE_DATA_i_3_n_0; wire FALSE_DATA_i_4_n_0; wire FALSE_DATA_i_5_n_0; wire FALSE_DATA_i_6_n_0; wire FALSE_K; wire FALSE_K0; wire FALSE_K_i_2_n_0; wire FALSE_K_i_3_n_0; wire FALSE_NIT; wire FALSE_NIT0; wire FALSE_NIT_i_2_n_0; wire FALSE_NIT_i_3_n_0; wire FALSE_NIT_reg_0; wire FROM_RX_CX; wire FROM_RX_CX0; wire I; wire I0; wire \IDLE_REG_reg_n_0_[0] ; wire \IDLE_REG_reg_n_0_[2] ; wire ILLEGAL_K; wire ILLEGAL_K0; wire ILLEGAL_K_REG1; wire ILLEGAL_K_REG2; wire I_REG_reg_n_0; wire I_i_4_n_0; wire I_i_5_n_0; wire I_i_6_n_0; wire I_i_7_n_0; wire K23p7; wire K28p5; wire K28p5_REG1; wire K29p7; wire [7:0]Q; wire R; wire RECEIVE; wire RECEIVE_i_1_n_0; wire RUDI_C0__0; wire RUDI_I0; wire RUDI_I_reg_0; wire RXCHARISK_REG1; wire RXCHARISK_REG1_reg_0; wire [7:0]RXDATA_REG5; wire \RXD[0]_i_1_n_0 ; wire \RXD[1]_i_1_n_0 ; wire \RXD[2]_i_1_n_0 ; wire \RXD[3]_i_1_n_0 ; wire \RXD[4]_i_1_n_0 ; wire \RXD[5]_i_1_n_0 ; wire \RXD[6]_i_1_n_0 ; wire \RXD[7]_i_1_n_0 ; wire RXEVEN0_out; wire RXNOTINTABLE_INT; wire RXSYNC_STATUS; wire RX_CONFIG_VALID_INT; wire RX_CONFIG_VALID_INT0; wire RX_CONFIG_VALID_INT_i_2_n_0; wire \RX_CONFIG_VALID_REG_reg_n_0_[0] ; wire \RX_CONFIG_VALID_REG_reg_n_0_[3] ; wire RX_DATA_ERROR; wire RX_DATA_ERROR0; wire RX_DATA_ERROR_i_2_n_0; wire RX_DATA_ERROR_i_3_n_0; wire RX_DATA_ERROR_i_4_n_0; wire RX_DV0; wire RX_DV_i_1_n_0; wire RX_ER0; wire RX_ER_i_2_n_0; wire RX_ER_reg_0; wire RX_INVALID_i_2_n_0; wire R_REG1; wire R_i_2_n_0; wire S; wire S0; wire S2; wire SOP; wire SOP0; wire SOP_REG1; wire SOP_REG2; wire SOP_REG3; wire [0:0]SR; wire SYNC_STATUS_REG; wire SYNC_STATUS_REG0; wire T; wire T_REG1; wire T_REG2; wire \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCHARISK_INT_reg ; wire WAIT_FOR_K; wire WAIT_FOR_K_i_1_n_0; wire gmii_rx_dv; wire gmii_rx_er; wire [7:0]gmii_rxd; wire p_0_in1_in; wire p_0_in2_in; wire p_1_in; wire [2:0]status_vector; wire userclk2; FDRE CGBAD_REG1_reg (.C(userclk2), .CE(1'b1), .D(CGBAD), .Q(CGBAD_REG1), .R(1'b0)); FDRE CGBAD_REG2_reg (.C(userclk2), .CE(1'b1), .D(CGBAD_REG1), .Q(CGBAD_REG2), .R(1'b0)); FDRE CGBAD_REG3_reg (.C(userclk2), .CE(1'b1), .D(CGBAD_REG2), .Q(CGBAD_REG3), .R(RUDI_I_reg_0)); LUT3 #( .INIT(8'hFE)) CGBAD_i_1 (.I0(RXNOTINTABLE_INT), .I1(D), .I2(CGBAD_reg_0), .O(S2)); FDRE CGBAD_reg (.C(userclk2), .CE(1'b1), .D(S2), .Q(CGBAD), .R(RUDI_I_reg_0)); LUT3 #( .INIT(8'h08)) C_HDR_REMOVED_REG_i_1 (.I0(C_HDR_REMOVED_REG_reg_0[0]), .I1(C_REG2), .I2(C_HDR_REMOVED_REG_reg_0[1]), .O(C_HDR_REMOVED)); FDRE C_HDR_REMOVED_REG_reg (.C(userclk2), .CE(1'b1), .D(C_HDR_REMOVED), .Q(C_HDR_REMOVED_REG), .R(1'b0)); FDRE C_REG1_reg (.C(userclk2), .CE(1'b1), .D(C), .Q(C_REG1), .R(1'b0)); FDRE C_REG2_reg (.C(userclk2), .CE(1'b1), .D(C_REG1), .Q(C_REG2), .R(1'b0)); FDRE C_REG3_reg (.C(userclk2), .CE(1'b1), .D(C_REG2), .Q(C_REG3), .R(1'b0)); LUT2 #( .INIT(4'h2)) C_i_1 (.I0(K28p5_REG1), .I1(\USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCHARISK_INT_reg ), .O(C0)); FDRE C_reg (.C(userclk2), .CE(1'b1), .D(C0), .Q(C), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair34" *) LUT4 #( .INIT(16'h0002)) D0p0_REG_i_1 (.I0(D0p0_REG_i_2_n_0), .I1(Q[0]), .I2(Q[1]), .I3(Q[7]), .O(D0p0)); LUT6 #( .INIT(64'h0000000000000001)) D0p0_REG_i_2 (.I0(Q[4]), .I1(Q[2]), .I2(Q[3]), .I3(RXCHARISK_REG1_reg_0), .I4(Q[6]), .I5(Q[5]), .O(D0p0_REG_i_2_n_0)); FDRE D0p0_REG_reg (.C(userclk2), .CE(1'b1), .D(D0p0), .Q(D0p0_REG), .R(1'b0)); LUT3 #( .INIT(8'hEA)) EOP_REG1_i_1 (.I0(EOP), .I1(EXTEND), .I2(EXTEND_REG1), .O(EOP_REG10)); FDRE EOP_REG1_reg (.C(userclk2), .CE(1'b1), .D(EOP_REG10), .Q(EOP_REG1), .R(RUDI_I_reg_0)); LUT6 #( .INIT(64'hFFFFFFFF88888000)) EOP_i_1 (.I0(T_REG2), .I1(R_REG1), .I2(K28p5_REG1), .I3(RXEVEN0_out), .I4(R), .I5(EOP_i_2_n_0), .O(EOP0)); LUT5 #( .INIT(32'hF8888888)) EOP_i_2 (.I0(I_REG_reg_n_0), .I1(K28p5_REG1), .I2(C_REG1), .I3(D0p0_REG), .I4(RXEVEN0_out), .O(EOP_i_2_n_0)); FDRE EOP_reg (.C(userclk2), .CE(1'b1), .D(EOP0), .Q(EOP), .R(RUDI_I_reg_0)); LUT3 #( .INIT(8'hEA)) EXTEND_ERR_i_1 (.I0(EXT_ILLEGAL_K_REG2), .I1(CGBAD_REG3), .I2(EXTEND_REG3), .O(EXTEND_ERR0)); FDRE EXTEND_ERR_reg (.C(userclk2), .CE(1'b1), .D(EXTEND_ERR0), .Q(EXTEND_ERR), .R(SYNC_STATUS_REG0)); FDRE EXTEND_REG1_reg (.C(userclk2), .CE(1'b1), .D(EXTEND), .Q(EXTEND_REG1), .R(1'b0)); FDRE EXTEND_REG2_reg (.C(userclk2), .CE(1'b1), .D(EXTEND_REG1), .Q(EXTEND_REG2), .R(1'b0)); FDRE EXTEND_REG3_reg (.C(userclk2), .CE(1'b1), .D(EXTEND_REG2), .Q(EXTEND_REG3), .R(1'b0)); LUT6 #( .INIT(64'h808080FF80808080)) EXTEND_i_1 (.I0(R_REG1), .I1(R), .I2(RECEIVE), .I3(RX_DATA_ERROR_i_3_n_0), .I4(S), .I5(EXTEND), .O(EXTEND_i_1_n_0)); FDRE EXTEND_reg (.C(userclk2), .CE(1'b1), .D(EXTEND_i_1_n_0), .Q(EXTEND), .R(SYNC_STATUS_REG0)); FDRE EXT_ILLEGAL_K_REG1_reg (.C(userclk2), .CE(1'b1), .D(EXT_ILLEGAL_K), .Q(EXT_ILLEGAL_K_REG1), .R(SYNC_STATUS_REG0)); FDRE EXT_ILLEGAL_K_REG2_reg (.C(userclk2), .CE(1'b1), .D(EXT_ILLEGAL_K_REG1), .Q(EXT_ILLEGAL_K_REG2), .R(SYNC_STATUS_REG0)); (* SOFT_HLUTNM = "soft_lutpair26" *) LUT5 #( .INIT(32'h00000700)) EXT_ILLEGAL_K_i_1 (.I0(K28p5_REG1), .I1(RXEVEN0_out), .I2(S), .I3(EXTEND_REG1), .I4(R), .O(EXT_ILLEGAL_K0)); FDRE EXT_ILLEGAL_K_reg (.C(userclk2), .CE(1'b1), .D(EXT_ILLEGAL_K0), .Q(EXT_ILLEGAL_K), .R(SYNC_STATUS_REG0)); FDRE FALSE_CARRIER_REG1_reg (.C(userclk2), .CE(1'b1), .D(FALSE_CARRIER), .Q(FALSE_CARRIER_REG1), .R(1'b0)); FDRE FALSE_CARRIER_REG2_reg (.C(userclk2), .CE(1'b1), .D(FALSE_CARRIER_REG1), .Q(FALSE_CARRIER_REG2), .R(1'b0)); FDRE FALSE_CARRIER_REG3_reg (.C(userclk2), .CE(1'b1), .D(FALSE_CARRIER_REG2), .Q(FALSE_CARRIER_REG3), .R(SYNC_STATUS_REG0)); LUT4 #( .INIT(16'hF7F0)) FALSE_CARRIER_i_1 (.I0(RXEVEN0_out), .I1(K28p5_REG1), .I2(FALSE_CARRIER0), .I3(FALSE_CARRIER), .O(FALSE_CARRIER_i_1_n_0)); LUT5 #( .INIT(32'h00001000)) FALSE_CARRIER_i_2 (.I0(K28p5_REG1), .I1(S), .I2(RXSYNC_STATUS), .I3(I_REG_reg_n_0), .I4(FALSE_CARRIER_i_3_n_0), .O(FALSE_CARRIER0)); LUT3 #( .INIT(8'hFE)) FALSE_CARRIER_i_3 (.I0(FALSE_NIT), .I1(FALSE_K), .I2(FALSE_DATA), .O(FALSE_CARRIER_i_3_n_0)); FDRE FALSE_CARRIER_reg (.C(userclk2), .CE(1'b1), .D(FALSE_CARRIER_i_1_n_0), .Q(FALSE_CARRIER), .R(SYNC_STATUS_REG0)); LUT4 #( .INIT(16'h000E)) FALSE_DATA_i_1 (.I0(FALSE_DATA_i_2_n_0), .I1(FALSE_DATA_i_3_n_0), .I2(RXNOTINTABLE_INT), .I3(RXCHARISK_REG1_reg_0), .O(FALSE_DATA0)); LUT6 #( .INIT(64'h0000008000808080)) FALSE_DATA_i_2 (.I0(FALSE_DATA_i_4_n_0), .I1(Q[1]), .I2(Q[0]), .I3(Q[3]), .I4(Q[2]), .I5(Q[4]), .O(FALSE_DATA_i_2_n_0)); LUT6 #( .INIT(64'h0000004040000000)) FALSE_DATA_i_3 (.I0(FALSE_DATA_i_5_n_0), .I1(Q[2]), .I2(Q[7]), .I3(Q[1]), .I4(Q[0]), .I5(FALSE_DATA_i_6_n_0), .O(FALSE_DATA_i_3_n_0)); (* SOFT_HLUTNM = "soft_lutpair24" *) LUT3 #( .INIT(8'h04)) FALSE_DATA_i_4 (.I0(Q[7]), .I1(Q[6]), .I2(Q[5]), .O(FALSE_DATA_i_4_n_0)); (* SOFT_HLUTNM = "soft_lutpair28" *) LUT2 #( .INIT(4'hB)) FALSE_DATA_i_5 (.I0(Q[6]), .I1(Q[5]), .O(FALSE_DATA_i_5_n_0)); (* SOFT_HLUTNM = "soft_lutpair36" *) LUT2 #( .INIT(4'hE)) FALSE_DATA_i_6 (.I0(Q[4]), .I1(Q[3]), .O(FALSE_DATA_i_6_n_0)); FDRE FALSE_DATA_reg (.C(userclk2), .CE(1'b1), .D(FALSE_DATA0), .Q(FALSE_DATA), .R(RUDI_I_reg_0)); (* SOFT_HLUTNM = "soft_lutpair32" *) LUT4 #( .INIT(16'h0009)) FALSE_K_i_1 (.I0(Q[5]), .I1(Q[6]), .I2(RXNOTINTABLE_INT), .I3(FALSE_K_i_2_n_0), .O(FALSE_K0)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFF7F)) FALSE_K_i_2 (.I0(RXCHARISK_REG1_reg_0), .I1(Q[4]), .I2(Q[7]), .I3(FALSE_K_i_3_n_0), .I4(Q[0]), .I5(Q[1]), .O(FALSE_K_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair36" *) LUT2 #( .INIT(4'h7)) FALSE_K_i_3 (.I0(Q[2]), .I1(Q[3]), .O(FALSE_K_i_3_n_0)); FDRE FALSE_K_reg (.C(userclk2), .CE(1'b1), .D(FALSE_K0), .Q(FALSE_K), .R(RUDI_I_reg_0)); (* SOFT_HLUTNM = "soft_lutpair32" *) LUT2 #( .INIT(4'h2)) FALSE_NIT_i_1 (.I0(RXNOTINTABLE_INT), .I1(FALSE_NIT_i_2_n_0), .O(FALSE_NIT0)); LUT6 #( .INIT(64'hF55F5FFC5FFCFCCF)) FALSE_NIT_i_2 (.I0(D0p0_REG_i_2_n_0), .I1(FALSE_NIT_i_3_n_0), .I2(Q[0]), .I3(Q[1]), .I4(Q[7]), .I5(D), .O(FALSE_NIT_i_2_n_0)); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) FALSE_NIT_i_3 (.I0(Q[3]), .I1(Q[2]), .I2(RXCHARISK_REG1_reg_0), .I3(Q[4]), .I4(Q[6]), .I5(Q[5]), .O(FALSE_NIT_i_3_n_0)); FDRE FALSE_NIT_reg (.C(userclk2), .CE(1'b1), .D(FALSE_NIT0), .Q(FALSE_NIT), .R(RUDI_I_reg_0)); LUT6 #( .INIT(64'hFFFFE0FFEEEEE0E0)) FROM_RX_CX_i_1 (.I0(C_REG1), .I1(C_REG2), .I2(RXCHARISK_REG1), .I3(RX_DATA_ERROR_i_3_n_0), .I4(CGBAD), .I5(C_REG3), .O(FROM_RX_CX0)); FDRE FROM_RX_CX_reg (.C(userclk2), .CE(1'b1), .D(FROM_RX_CX0), .Q(FROM_RX_CX), .R(SYNC_STATUS_REG0)); FDRE \IDLE_REG_reg[0] (.C(userclk2), .CE(1'b1), .D(I_REG_reg_n_0), .Q(\IDLE_REG_reg_n_0_[0] ), .R(RUDI_I_reg_0)); FDRE \IDLE_REG_reg[1] (.C(userclk2), .CE(1'b1), .D(\IDLE_REG_reg_n_0_[0] ), .Q(p_0_in1_in), .R(RUDI_I_reg_0)); FDRE \IDLE_REG_reg[2] (.C(userclk2), .CE(1'b1), .D(p_0_in1_in), .Q(\IDLE_REG_reg_n_0_[2] ), .R(RUDI_I_reg_0)); FDRE ILLEGAL_K_REG1_reg (.C(userclk2), .CE(1'b1), .D(ILLEGAL_K), .Q(ILLEGAL_K_REG1), .R(SYNC_STATUS_REG0)); FDRE ILLEGAL_K_REG2_reg (.C(userclk2), .CE(1'b1), .D(ILLEGAL_K_REG1), .Q(ILLEGAL_K_REG2), .R(SYNC_STATUS_REG0)); (* SOFT_HLUTNM = "soft_lutpair35" *) LUT4 #( .INIT(16'h0010)) ILLEGAL_K_i_1 (.I0(R), .I1(K28p5_REG1), .I2(RXCHARISK_REG1), .I3(T), .O(ILLEGAL_K0)); FDRE ILLEGAL_K_reg (.C(userclk2), .CE(1'b1), .D(ILLEGAL_K0), .Q(ILLEGAL_K), .R(SYNC_STATUS_REG0)); FDRE I_REG_reg (.C(userclk2), .CE(1'b1), .D(I), .Q(I_REG_reg_n_0), .R(1'b0)); LUT6 #( .INIT(64'hFBFBFBFBFBFBFBAA)) I_i_2 (.I0(RXCHARISK_REG1_reg_0), .I1(I_i_4_n_0), .I2(I_i_5_n_0), .I3(I_i_6_n_0), .I4(FALSE_DATA_i_5_n_0), .I5(I_i_7_n_0), .O(\USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCHARISK_INT_reg )); LUT6 #( .INIT(64'h0000000001FFFFFF)) I_i_3 (.I0(FALSE_NIT), .I1(FALSE_K), .I2(FALSE_DATA), .I3(RXSYNC_STATUS), .I4(I_REG_reg_n_0), .I5(K28p5_REG1), .O(FALSE_NIT_reg_0)); (* SOFT_HLUTNM = "soft_lutpair33" *) LUT3 #( .INIT(8'h01)) I_i_4 (.I0(Q[3]), .I1(Q[2]), .I2(Q[4]), .O(I_i_4_n_0)); (* SOFT_HLUTNM = "soft_lutpair24" *) LUT5 #( .INIT(32'hFFFBFFFF)) I_i_5 (.I0(Q[5]), .I1(Q[6]), .I2(Q[7]), .I3(Q[0]), .I4(Q[1]), .O(I_i_5_n_0)); (* SOFT_HLUTNM = "soft_lutpair34" *) LUT2 #( .INIT(4'h7)) I_i_6 (.I0(Q[4]), .I1(Q[7]), .O(I_i_6_n_0)); (* SOFT_HLUTNM = "soft_lutpair33" *) LUT4 #( .INIT(16'hFFDF)) I_i_7 (.I0(Q[2]), .I1(Q[3]), .I2(Q[0]), .I3(Q[1]), .O(I_i_7_n_0)); FDRE I_reg (.C(userclk2), .CE(1'b1), .D(I0), .Q(I), .R(1'b0)); LUT3 #( .INIT(8'h02)) K28p5_REG1_i_1 (.I0(Q[5]), .I1(Q[6]), .I2(FALSE_K_i_2_n_0), .O(K28p5)); FDRE K28p5_REG1_reg (.C(userclk2), .CE(1'b1), .D(K28p5), .Q(K28p5_REG1), .R(1'b0)); LUT3 #( .INIT(8'hDC)) RECEIVE_i_1 (.I0(EOP), .I1(SOP_REG2), .I2(RECEIVE), .O(RECEIVE_i_1_n_0)); FDRE RECEIVE_reg (.C(userclk2), .CE(1'b1), .D(RECEIVE_i_1_n_0), .Q(RECEIVE), .R(SYNC_STATUS_REG0)); LUT4 #( .INIT(16'hFFFE)) RUDI_C0 (.I0(p_0_in2_in), .I1(\RX_CONFIG_VALID_REG_reg_n_0_[3] ), .I2(p_1_in), .I3(\RX_CONFIG_VALID_REG_reg_n_0_[0] ), .O(RUDI_C0__0)); FDRE RUDI_C_reg (.C(userclk2), .CE(1'b1), .D(RUDI_C0__0), .Q(status_vector[0]), .R(RUDI_I_reg_0)); LUT2 #( .INIT(4'hE)) RUDI_I_i_1 (.I0(\IDLE_REG_reg_n_0_[2] ), .I1(p_0_in1_in), .O(RUDI_I0)); FDRE RUDI_I_reg (.C(userclk2), .CE(1'b1), .D(RUDI_I0), .Q(status_vector[1]), .R(RUDI_I_reg_0)); FDRE RXCHARISK_REG1_reg (.C(userclk2), .CE(1'b1), .D(RXCHARISK_REG1_reg_0), .Q(RXCHARISK_REG1), .R(1'b0)); (* srl_bus_name = "U0/gig_ethernet_pcs_pma_16_1_core/\gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg " *) (* srl_name = "U0/gig_ethernet_pcs_pma_16_1_core/\gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg[0]_srl5 " *) SRL16E \RXDATA_REG5_reg[0]_srl5 (.A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .CE(1'b1), .CLK(userclk2), .D(Q[0]), .Q(RXDATA_REG5[0])); (* srl_bus_name = "U0/gig_ethernet_pcs_pma_16_1_core/\gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg " *) (* srl_name = "U0/gig_ethernet_pcs_pma_16_1_core/\gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg[1]_srl5 " *) SRL16E \RXDATA_REG5_reg[1]_srl5 (.A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .CE(1'b1), .CLK(userclk2), .D(Q[1]), .Q(RXDATA_REG5[1])); (* srl_bus_name = "U0/gig_ethernet_pcs_pma_16_1_core/\gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg " *) (* srl_name = "U0/gig_ethernet_pcs_pma_16_1_core/\gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg[2]_srl5 " *) SRL16E \RXDATA_REG5_reg[2]_srl5 (.A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .CE(1'b1), .CLK(userclk2), .D(Q[2]), .Q(RXDATA_REG5[2])); (* srl_bus_name = "U0/gig_ethernet_pcs_pma_16_1_core/\gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg " *) (* srl_name = "U0/gig_ethernet_pcs_pma_16_1_core/\gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg[3]_srl5 " *) SRL16E \RXDATA_REG5_reg[3]_srl5 (.A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .CE(1'b1), .CLK(userclk2), .D(Q[3]), .Q(RXDATA_REG5[3])); (* srl_bus_name = "U0/gig_ethernet_pcs_pma_16_1_core/\gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg " *) (* srl_name = "U0/gig_ethernet_pcs_pma_16_1_core/\gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg[4]_srl5 " *) SRL16E \RXDATA_REG5_reg[4]_srl5 (.A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .CE(1'b1), .CLK(userclk2), .D(Q[4]), .Q(RXDATA_REG5[4])); (* srl_bus_name = "U0/gig_ethernet_pcs_pma_16_1_core/\gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg " *) (* srl_name = "U0/gig_ethernet_pcs_pma_16_1_core/\gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg[5]_srl5 " *) SRL16E \RXDATA_REG5_reg[5]_srl5 (.A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .CE(1'b1), .CLK(userclk2), .D(Q[5]), .Q(RXDATA_REG5[5])); (* srl_bus_name = "U0/gig_ethernet_pcs_pma_16_1_core/\gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg " *) (* srl_name = "U0/gig_ethernet_pcs_pma_16_1_core/\gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg[6]_srl5 " *) SRL16E \RXDATA_REG5_reg[6]_srl5 (.A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .CE(1'b1), .CLK(userclk2), .D(Q[6]), .Q(RXDATA_REG5[6])); (* srl_bus_name = "U0/gig_ethernet_pcs_pma_16_1_core/\gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg " *) (* srl_name = "U0/gig_ethernet_pcs_pma_16_1_core/\gpcs_pma_inst/RX_GMII_AT_TXOUTCLK.RECEIVER_TXOUTCLK/RXDATA_REG5_reg[7]_srl5 " *) SRL16E \RXDATA_REG5_reg[7]_srl5 (.A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .CE(1'b1), .CLK(userclk2), .D(Q[7]), .Q(RXDATA_REG5[7])); (* SOFT_HLUTNM = "soft_lutpair30" *) LUT4 #( .INIT(16'hBBBA)) \RXD[0]_i_1 (.I0(SOP_REG3), .I1(FALSE_CARRIER_REG3), .I2(EXTEND_REG1), .I3(RXDATA_REG5[0]), .O(\RXD[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair29" *) LUT4 #( .INIT(16'h5554)) \RXD[1]_i_1 (.I0(SOP_REG3), .I1(FALSE_CARRIER_REG3), .I2(EXTEND_REG1), .I3(RXDATA_REG5[1]), .O(\RXD[1]_i_1_n_0 )); LUT4 #( .INIT(16'hFFFE)) \RXD[2]_i_1 (.I0(RXDATA_REG5[2]), .I1(FALSE_CARRIER_REG3), .I2(EXTEND_REG1), .I3(SOP_REG3), .O(\RXD[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair30" *) LUT4 #( .INIT(16'h5554)) \RXD[3]_i_1 (.I0(SOP_REG3), .I1(FALSE_CARRIER_REG3), .I2(EXTEND_REG1), .I3(RXDATA_REG5[3]), .O(\RXD[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair25" *) LUT5 #( .INIT(32'hBABBBAAA)) \RXD[4]_i_1 (.I0(SOP_REG3), .I1(FALSE_CARRIER_REG3), .I2(EXTEND_ERR), .I3(EXTEND_REG1), .I4(RXDATA_REG5[4]), .O(\RXD[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair31" *) LUT4 #( .INIT(16'h0002)) \RXD[5]_i_1 (.I0(RXDATA_REG5[5]), .I1(FALSE_CARRIER_REG3), .I2(EXTEND_REG1), .I3(SOP_REG3), .O(\RXD[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair31" *) LUT4 #( .INIT(16'hABAA)) \RXD[6]_i_1 (.I0(SOP_REG3), .I1(FALSE_CARRIER_REG3), .I2(EXTEND_REG1), .I3(RXDATA_REG5[6]), .O(\RXD[6]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair29" *) LUT4 #( .INIT(16'h0002)) \RXD[7]_i_1 (.I0(RXDATA_REG5[7]), .I1(FALSE_CARRIER_REG3), .I2(EXTEND_REG1), .I3(SOP_REG3), .O(\RXD[7]_i_1_n_0 )); FDRE \RXD_reg[0] (.C(userclk2), .CE(1'b1), .D(\RXD[0]_i_1_n_0 ), .Q(gmii_rxd[0]), .R(SR)); FDRE \RXD_reg[1] (.C(userclk2), .CE(1'b1), .D(\RXD[1]_i_1_n_0 ), .Q(gmii_rxd[1]), .R(SR)); FDRE \RXD_reg[2] (.C(userclk2), .CE(1'b1), .D(\RXD[2]_i_1_n_0 ), .Q(gmii_rxd[2]), .R(SR)); FDRE \RXD_reg[3] (.C(userclk2), .CE(1'b1), .D(\RXD[3]_i_1_n_0 ), .Q(gmii_rxd[3]), .R(SR)); FDRE \RXD_reg[4] (.C(userclk2), .CE(1'b1), .D(\RXD[4]_i_1_n_0 ), .Q(gmii_rxd[4]), .R(SR)); FDRE \RXD_reg[5] (.C(userclk2), .CE(1'b1), .D(\RXD[5]_i_1_n_0 ), .Q(gmii_rxd[5]), .R(SR)); FDRE \RXD_reg[6] (.C(userclk2), .CE(1'b1), .D(\RXD[6]_i_1_n_0 ), .Q(gmii_rxd[6]), .R(SR)); FDRE \RXD_reg[7] (.C(userclk2), .CE(1'b1), .D(\RXD[7]_i_1_n_0 ), .Q(gmii_rxd[7]), .R(SR)); LUT6 #( .INIT(64'h0010001000100000)) RX_CONFIG_VALID_INT_i_1 (.I0(S2), .I1(RX_CONFIG_VALID_INT_i_2_n_0), .I2(RXSYNC_STATUS), .I3(RXCHARISK_REG1_reg_0), .I4(C_REG1), .I5(C_HDR_REMOVED_REG), .O(RX_CONFIG_VALID_INT0)); (* SOFT_HLUTNM = "soft_lutpair35" *) LUT2 #( .INIT(4'hE)) RX_CONFIG_VALID_INT_i_2 (.I0(RXCHARISK_REG1), .I1(CGBAD), .O(RX_CONFIG_VALID_INT_i_2_n_0)); FDRE RX_CONFIG_VALID_INT_reg (.C(userclk2), .CE(1'b1), .D(RX_CONFIG_VALID_INT0), .Q(RX_CONFIG_VALID_INT), .R(RUDI_I_reg_0)); FDRE \RX_CONFIG_VALID_REG_reg[0] (.C(userclk2), .CE(1'b1), .D(RX_CONFIG_VALID_INT), .Q(\RX_CONFIG_VALID_REG_reg_n_0_[0] ), .R(RUDI_I_reg_0)); FDRE \RX_CONFIG_VALID_REG_reg[1] (.C(userclk2), .CE(1'b1), .D(\RX_CONFIG_VALID_REG_reg_n_0_[0] ), .Q(p_0_in2_in), .R(RUDI_I_reg_0)); FDRE \RX_CONFIG_VALID_REG_reg[2] (.C(userclk2), .CE(1'b1), .D(p_0_in2_in), .Q(p_1_in), .R(RUDI_I_reg_0)); FDRE \RX_CONFIG_VALID_REG_reg[3] (.C(userclk2), .CE(1'b1), .D(p_1_in), .Q(\RX_CONFIG_VALID_REG_reg_n_0_[3] ), .R(RUDI_I_reg_0)); LUT6 #( .INIT(64'h888AAAAA88888888)) RX_DATA_ERROR_i_1 (.I0(RECEIVE), .I1(RX_DATA_ERROR_i_2_n_0), .I2(R), .I3(RX_DATA_ERROR_i_3_n_0), .I4(R_REG1), .I5(T_REG2), .O(RX_DATA_ERROR0)); LUT5 #( .INIT(32'hFFFF4544)) RX_DATA_ERROR_i_2 (.I0(R_REG1), .I1(K28p5_REG1), .I2(T_REG1), .I3(R), .I4(RX_DATA_ERROR_i_4_n_0), .O(RX_DATA_ERROR_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair26" *) LUT2 #( .INIT(4'h8)) RX_DATA_ERROR_i_3 (.I0(K28p5_REG1), .I1(RXEVEN0_out), .O(RX_DATA_ERROR_i_3_n_0)); LUT4 #( .INIT(16'hFFFE)) RX_DATA_ERROR_i_4 (.I0(CGBAD_REG3), .I1(I_REG_reg_n_0), .I2(ILLEGAL_K_REG2), .I3(C_REG1), .O(RX_DATA_ERROR_i_4_n_0)); FDRE RX_DATA_ERROR_reg (.C(userclk2), .CE(1'b1), .D(RX_DATA_ERROR0), .Q(RX_DATA_ERROR), .R(SYNC_STATUS_REG0)); LUT5 #( .INIT(32'hAAFEAAAA)) RX_DV_i_1 (.I0(RX_DV0), .I1(RXSYNC_STATUS), .I2(RECEIVE), .I3(EOP_REG1), .I4(gmii_rx_dv), .O(RX_DV_i_1_n_0)); LUT4 #( .INIT(16'h1000)) RX_DV_i_2 (.I0(RX_ER_reg_0), .I1(SR), .I2(SOP_REG3), .I3(RXSYNC_STATUS), .O(RX_DV0)); FDRE #( .INIT(1'b0)) RX_DV_reg (.C(userclk2), .CE(1'b1), .D(RX_DV_i_1_n_0), .Q(gmii_rx_dv), .R(RUDI_I_reg_0)); LUT6 #( .INIT(64'h000E000F000E0000)) RX_ER_i_1 (.I0(RX_DATA_ERROR), .I1(RX_ER_i_2_n_0), .I2(SR), .I3(RX_ER_reg_0), .I4(RXSYNC_STATUS), .I5(RECEIVE), .O(RX_ER0)); (* SOFT_HLUTNM = "soft_lutpair25" *) LUT2 #( .INIT(4'hE)) RX_ER_i_2 (.I0(FALSE_CARRIER_REG3), .I1(EXTEND_REG1), .O(RX_ER_i_2_n_0)); FDRE #( .INIT(1'b0)) RX_ER_reg (.C(userclk2), .CE(1'b1), .D(RX_ER0), .Q(gmii_rx_er), .R(RUDI_I_reg_0)); LUT3 #( .INIT(8'hDC)) RX_INVALID_i_2 (.I0(K28p5_REG1), .I1(FROM_RX_CX), .I2(status_vector[2]), .O(RX_INVALID_i_2_n_0)); FDRE RX_INVALID_reg (.C(userclk2), .CE(1'b1), .D(RX_INVALID_i_2_n_0), .Q(status_vector[2]), .R(SYNC_STATUS_REG0)); FDRE R_REG1_reg (.C(userclk2), .CE(1'b1), .D(R), .Q(R_REG1), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair27" *) LUT5 #( .INIT(32'h00800000)) R_i_1 (.I0(R_i_2_n_0), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[2]), .O(K23p7)); (* SOFT_HLUTNM = "soft_lutpair28" *) LUT5 #( .INIT(32'h80000000)) R_i_2 (.I0(Q[5]), .I1(Q[6]), .I2(RXCHARISK_REG1_reg_0), .I3(Q[4]), .I4(Q[7]), .O(R_i_2_n_0)); FDRE R_reg (.C(userclk2), .CE(1'b1), .D(K23p7), .Q(R), .R(1'b0)); FDRE SOP_REG1_reg (.C(userclk2), .CE(1'b1), .D(SOP), .Q(SOP_REG1), .R(1'b0)); FDRE SOP_REG2_reg (.C(userclk2), .CE(1'b1), .D(SOP_REG1), .Q(SOP_REG2), .R(1'b0)); FDRE SOP_REG3_reg (.C(userclk2), .CE(1'b1), .D(SOP_REG2), .Q(SOP_REG3), .R(1'b0)); LUT5 #( .INIT(32'h00E00000)) SOP_i_1 (.I0(EXTEND), .I1(I_REG_reg_n_0), .I2(S), .I3(WAIT_FOR_K), .I4(RXSYNC_STATUS), .O(SOP0)); FDRE SOP_reg (.C(userclk2), .CE(1'b1), .D(SOP0), .Q(SOP), .R(RUDI_I_reg_0)); FDRE SYNC_STATUS_REG_reg (.C(userclk2), .CE(1'b1), .D(1'b1), .Q(SYNC_STATUS_REG), .R(SYNC_STATUS_REG0)); LUT6 #( .INIT(64'h0000000000008000)) S_i_1 (.I0(R_i_2_n_0), .I1(Q[1]), .I2(Q[0]), .I3(Q[3]), .I4(Q[2]), .I5(S2), .O(S0)); FDRE S_reg (.C(userclk2), .CE(1'b1), .D(S0), .Q(S), .R(1'b0)); FDRE T_REG1_reg (.C(userclk2), .CE(1'b1), .D(T), .Q(T_REG1), .R(1'b0)); FDRE T_REG2_reg (.C(userclk2), .CE(1'b1), .D(T_REG1), .Q(T_REG2), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair27" *) LUT5 #( .INIT(32'h00800000)) T_i_1__0 (.I0(R_i_2_n_0), .I1(Q[2]), .I2(Q[3]), .I3(Q[1]), .I4(Q[0]), .O(K29p7)); FDRE T_reg (.C(userclk2), .CE(1'b1), .D(K29p7), .Q(T), .R(1'b0)); LUT4 #( .INIT(16'h7F0F)) WAIT_FOR_K_i_1 (.I0(RXEVEN0_out), .I1(K28p5_REG1), .I2(SYNC_STATUS_REG), .I3(WAIT_FOR_K), .O(WAIT_FOR_K_i_1_n_0)); FDRE WAIT_FOR_K_reg (.C(userclk2), .CE(1'b1), .D(WAIT_FOR_K_i_1_n_0), .Q(WAIT_FOR_K), .R(SYNC_STATUS_REG0)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SYNCHRONISE (RXEVEN0_out, RXSYNC_STATUS, enablealign, SYNC_STATUS_REG0, I0, STATUS_VECTOR_0_PRE0, SIGNAL_DETECT_MOD, userclk2, EVEN_reg_0, \FSM_onehot_STATE_reg[1]_0 , CONFIGURATION_VECTOR_REG, \FSM_onehot_STATE_reg[2]_0 , S2, RXNOTINTABLE_INT, D, \FSM_onehot_STATE_reg[0]_0 , I_reg, I_reg_0, reset_done); output RXEVEN0_out; output RXSYNC_STATUS; output enablealign; output SYNC_STATUS_REG0; output I0; output STATUS_VECTOR_0_PRE0; input SIGNAL_DETECT_MOD; input userclk2; input EVEN_reg_0; input \FSM_onehot_STATE_reg[1]_0 ; input [0:0]CONFIGURATION_VECTOR_REG; input \FSM_onehot_STATE_reg[2]_0 ; input S2; input RXNOTINTABLE_INT; input D; input \FSM_onehot_STATE_reg[0]_0 ; input I_reg; input I_reg_0; input reset_done; wire [0:0]CONFIGURATION_VECTOR_REG; wire D; wire ENCOMMAALIGN_i_1_n_0; wire ENCOMMAALIGN_i_2_n_0; wire EVEN_i_1_n_0; wire EVEN_reg_0; wire \FSM_onehot_STATE[0]_i_1_n_0 ; wire \FSM_onehot_STATE[10]_i_1_n_0 ; wire \FSM_onehot_STATE[11]_i_1_n_0 ; wire \FSM_onehot_STATE[12]_i_1_n_0 ; wire \FSM_onehot_STATE[12]_i_2_n_0 ; wire \FSM_onehot_STATE[12]_i_3_n_0 ; wire \FSM_onehot_STATE[1]_i_1_n_0 ; wire \FSM_onehot_STATE[2]_i_1_n_0 ; wire \FSM_onehot_STATE[2]_i_2_n_0 ; wire \FSM_onehot_STATE[2]_i_3_n_0 ; wire \FSM_onehot_STATE[3]_i_1_n_0 ; wire \FSM_onehot_STATE[4]_i_1_n_0 ; wire \FSM_onehot_STATE[5]_i_1_n_0 ; wire \FSM_onehot_STATE[6]_i_1_n_0 ; wire \FSM_onehot_STATE[7]_i_1_n_0 ; wire \FSM_onehot_STATE[8]_i_1_n_0 ; wire \FSM_onehot_STATE[9]_i_1_n_0 ; wire \FSM_onehot_STATE_reg[0]_0 ; wire \FSM_onehot_STATE_reg[1]_0 ; wire \FSM_onehot_STATE_reg[2]_0 ; wire \FSM_onehot_STATE_reg_n_0_[0] ; wire \FSM_onehot_STATE_reg_n_0_[10] ; wire \FSM_onehot_STATE_reg_n_0_[11] ; wire \FSM_onehot_STATE_reg_n_0_[12] ; wire \FSM_onehot_STATE_reg_n_0_[1] ; wire \FSM_onehot_STATE_reg_n_0_[2] ; wire \FSM_onehot_STATE_reg_n_0_[4] ; wire \FSM_onehot_STATE_reg_n_0_[5] ; wire \FSM_onehot_STATE_reg_n_0_[6] ; wire \FSM_onehot_STATE_reg_n_0_[8] ; wire \FSM_onehot_STATE_reg_n_0_[9] ; wire [1:0]GOOD_CGS; wire \GOOD_CGS[0]_i_1_n_0 ; wire \GOOD_CGS[1]_i_1_n_0 ; wire \GOOD_CGS[1]_i_2_n_0 ; wire I0; wire I_reg; wire I_reg_0; wire RXEVEN0_out; wire RXNOTINTABLE_INT; wire RXSYNC_STATUS; wire S2; wire SIGNAL_DETECT_MOD; wire SIGNAL_DETECT_REG; wire STATUS_VECTOR_0_PRE0; wire SYNC_STATUS0; wire SYNC_STATUS_REG0; wire SYNC_STATUS_i_1_n_0; wire enablealign; wire p_0_in; wire p_1_in; wire reset_done; wire userclk2; LUT6 #( .INIT(64'h00000000FFFEEEEE)) ENCOMMAALIGN_i_1 (.I0(enablealign), .I1(\FSM_onehot_STATE_reg_n_0_[2] ), .I2(p_1_in), .I3(\FSM_onehot_STATE_reg_n_0_[5] ), .I4(ENCOMMAALIGN_i_2_n_0), .I5(SYNC_STATUS0), .O(ENCOMMAALIGN_i_1_n_0)); LUT5 #( .INIT(32'hFFFEFFFC)) ENCOMMAALIGN_i_2 (.I0(\FSM_onehot_STATE_reg[1]_0 ), .I1(RXNOTINTABLE_INT), .I2(D), .I3(\FSM_onehot_STATE_reg[0]_0 ), .I4(RXEVEN0_out), .O(ENCOMMAALIGN_i_2_n_0)); LUT3 #( .INIT(8'h02)) ENCOMMAALIGN_i_3 (.I0(p_0_in), .I1(ENCOMMAALIGN_i_2_n_0), .I2(\FSM_onehot_STATE_reg[2]_0 ), .O(SYNC_STATUS0)); FDRE ENCOMMAALIGN_reg (.C(userclk2), .CE(1'b1), .D(ENCOMMAALIGN_i_1_n_0), .Q(enablealign), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair41" *) LUT3 #( .INIT(8'h4F)) EVEN_i_1 (.I0(RXSYNC_STATUS), .I1(\FSM_onehot_STATE_reg[1]_0 ), .I2(RXEVEN0_out), .O(EVEN_i_1_n_0)); FDRE EVEN_reg (.C(userclk2), .CE(1'b1), .D(EVEN_i_1_n_0), .Q(RXEVEN0_out), .R(EVEN_reg_0)); LUT6 #( .INIT(64'h0000000200000000)) \FSM_onehot_STATE[0]_i_1 (.I0(\FSM_onehot_STATE_reg_n_0_[4] ), .I1(RXEVEN0_out), .I2(\FSM_onehot_STATE_reg[0]_0 ), .I3(D), .I4(RXNOTINTABLE_INT), .I5(\FSM_onehot_STATE_reg[1]_0 ), .O(\FSM_onehot_STATE[0]_i_1_n_0 )); LUT2 #( .INIT(4'h8)) \FSM_onehot_STATE[10]_i_1 (.I0(\FSM_onehot_STATE_reg[1]_0 ), .I1(\FSM_onehot_STATE_reg_n_0_[2] ), .O(\FSM_onehot_STATE[10]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair37" *) LUT5 #( .INIT(32'h54554444)) \FSM_onehot_STATE[11]_i_1 (.I0(ENCOMMAALIGN_i_2_n_0), .I1(\FSM_onehot_STATE_reg_n_0_[9] ), .I2(GOOD_CGS[0]), .I3(GOOD_CGS[1]), .I4(\FSM_onehot_STATE_reg_n_0_[11] ), .O(\FSM_onehot_STATE[11]_i_1_n_0 )); LUT3 #( .INIT(8'hAB)) \FSM_onehot_STATE[12]_i_1 (.I0(EVEN_reg_0), .I1(SIGNAL_DETECT_REG), .I2(CONFIGURATION_VECTOR_REG), .O(\FSM_onehot_STATE[12]_i_1_n_0 )); LUT6 #( .INIT(64'h00000000FFF4F4F4)) \FSM_onehot_STATE[12]_i_2 (.I0(\FSM_onehot_STATE_reg[2]_0 ), .I1(p_0_in), .I2(\FSM_onehot_STATE_reg_n_0_[12] ), .I3(\FSM_onehot_STATE[12]_i_3_n_0 ), .I4(\FSM_onehot_STATE_reg_n_0_[11] ), .I5(ENCOMMAALIGN_i_2_n_0), .O(\FSM_onehot_STATE[12]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair37" *) LUT2 #( .INIT(4'h2)) \FSM_onehot_STATE[12]_i_3 (.I0(GOOD_CGS[1]), .I1(GOOD_CGS[0]), .O(\FSM_onehot_STATE[12]_i_3_n_0 )); LUT6 #( .INIT(64'h000300BB000000AA)) \FSM_onehot_STATE[1]_i_1 (.I0(\FSM_onehot_STATE_reg_n_0_[1] ), .I1(\FSM_onehot_STATE_reg[2]_0 ), .I2(RXEVEN0_out), .I3(S2), .I4(\FSM_onehot_STATE_reg[1]_0 ), .I5(\FSM_onehot_STATE_reg_n_0_[0] ), .O(\FSM_onehot_STATE[1]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFEFEFE00)) \FSM_onehot_STATE[2]_i_1 (.I0(\FSM_onehot_STATE_reg_n_0_[10] ), .I1(\FSM_onehot_STATE_reg_n_0_[0] ), .I2(p_0_in), .I3(\FSM_onehot_STATE_reg[2]_0 ), .I4(ENCOMMAALIGN_i_2_n_0), .I5(\FSM_onehot_STATE[2]_i_2_n_0 ), .O(\FSM_onehot_STATE[2]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFF4F44444444)) \FSM_onehot_STATE[2]_i_2 (.I0(\FSM_onehot_STATE_reg[1]_0 ), .I1(\FSM_onehot_STATE_reg_n_0_[2] ), .I2(\FSM_onehot_STATE[2]_i_3_n_0 ), .I3(\FSM_onehot_STATE_reg_n_0_[1] ), .I4(\FSM_onehot_STATE_reg_n_0_[4] ), .I5(ENCOMMAALIGN_i_2_n_0), .O(\FSM_onehot_STATE[2]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair38" *) LUT2 #( .INIT(4'h1)) \FSM_onehot_STATE[2]_i_3 (.I0(p_1_in), .I1(\FSM_onehot_STATE_reg_n_0_[5] ), .O(\FSM_onehot_STATE[2]_i_3_n_0 )); LUT6 #( .INIT(64'h0000000200000000)) \FSM_onehot_STATE[3]_i_1 (.I0(\FSM_onehot_STATE_reg_n_0_[1] ), .I1(RXEVEN0_out), .I2(\FSM_onehot_STATE_reg[0]_0 ), .I3(D), .I4(RXNOTINTABLE_INT), .I5(\FSM_onehot_STATE_reg[1]_0 ), .O(\FSM_onehot_STATE[3]_i_1_n_0 )); LUT6 #( .INIT(64'h000010FF00001050)) \FSM_onehot_STATE[4]_i_1 (.I0(\FSM_onehot_STATE_reg[2]_0 ), .I1(RXEVEN0_out), .I2(\FSM_onehot_STATE_reg_n_0_[10] ), .I3(\FSM_onehot_STATE_reg[1]_0 ), .I4(S2), .I5(\FSM_onehot_STATE_reg_n_0_[4] ), .O(\FSM_onehot_STATE[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair38" *) LUT5 #( .INIT(32'h54554444)) \FSM_onehot_STATE[5]_i_1 (.I0(ENCOMMAALIGN_i_2_n_0), .I1(p_1_in), .I2(GOOD_CGS[0]), .I3(GOOD_CGS[1]), .I4(\FSM_onehot_STATE_reg_n_0_[5] ), .O(\FSM_onehot_STATE[5]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFF0040404040)) \FSM_onehot_STATE[6]_i_1 (.I0(GOOD_CGS[0]), .I1(GOOD_CGS[1]), .I2(\FSM_onehot_STATE_reg_n_0_[5] ), .I3(\FSM_onehot_STATE_reg_n_0_[9] ), .I4(\FSM_onehot_STATE_reg_n_0_[11] ), .I5(ENCOMMAALIGN_i_2_n_0), .O(\FSM_onehot_STATE[6]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair39" *) LUT3 #( .INIT(8'hA8)) \FSM_onehot_STATE[7]_i_1 (.I0(ENCOMMAALIGN_i_2_n_0), .I1(\FSM_onehot_STATE_reg_n_0_[8] ), .I2(\FSM_onehot_STATE_reg_n_0_[6] ), .O(\FSM_onehot_STATE[7]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair39" *) LUT5 #( .INIT(32'h54554444)) \FSM_onehot_STATE[8]_i_1 (.I0(ENCOMMAALIGN_i_2_n_0), .I1(\FSM_onehot_STATE_reg_n_0_[6] ), .I2(GOOD_CGS[0]), .I3(GOOD_CGS[1]), .I4(\FSM_onehot_STATE_reg_n_0_[8] ), .O(\FSM_onehot_STATE[8]_i_1_n_0 )); LUT5 #( .INIT(32'h8B888888)) \FSM_onehot_STATE[9]_i_1 (.I0(\FSM_onehot_STATE_reg_n_0_[12] ), .I1(ENCOMMAALIGN_i_2_n_0), .I2(GOOD_CGS[0]), .I3(GOOD_CGS[1]), .I4(\FSM_onehot_STATE_reg_n_0_[8] ), .O(\FSM_onehot_STATE[9]_i_1_n_0 )); (* FSM_ENCODED_STATES = "comma_detect_2:0000000000001,aquire_sync_2:0000000000010,aquire_sync_1:0000000010000,sync_acquired_4:0000010000000,sync_acquired_4a:0000000100000,sync_acquired_3a:0000100000000,comma_detect_1:0010000000000,loss_of_sync:0000000000100,sync_acquired_2:0001000000000,sync_acquired_3:0000001000000,sync_acquired_2a:0100000000000,sync_acquired_1:1000000000000,comma_detect_3:0000000001000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_STATE_reg[0] (.C(userclk2), .CE(1'b1), .D(\FSM_onehot_STATE[0]_i_1_n_0 ), .Q(\FSM_onehot_STATE_reg_n_0_[0] ), .R(\FSM_onehot_STATE[12]_i_1_n_0 )); (* FSM_ENCODED_STATES = "comma_detect_2:0000000000001,aquire_sync_2:0000000000010,aquire_sync_1:0000000010000,sync_acquired_4:0000010000000,sync_acquired_4a:0000000100000,sync_acquired_3a:0000100000000,comma_detect_1:0010000000000,loss_of_sync:0000000000100,sync_acquired_2:0001000000000,sync_acquired_3:0000001000000,sync_acquired_2a:0100000000000,sync_acquired_1:1000000000000,comma_detect_3:0000000001000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_STATE_reg[10] (.C(userclk2), .CE(1'b1), .D(\FSM_onehot_STATE[10]_i_1_n_0 ), .Q(\FSM_onehot_STATE_reg_n_0_[10] ), .R(\FSM_onehot_STATE[12]_i_1_n_0 )); (* FSM_ENCODED_STATES = "comma_detect_2:0000000000001,aquire_sync_2:0000000000010,aquire_sync_1:0000000010000,sync_acquired_4:0000010000000,sync_acquired_4a:0000000100000,sync_acquired_3a:0000100000000,comma_detect_1:0010000000000,loss_of_sync:0000000000100,sync_acquired_2:0001000000000,sync_acquired_3:0000001000000,sync_acquired_2a:0100000000000,sync_acquired_1:1000000000000,comma_detect_3:0000000001000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_STATE_reg[11] (.C(userclk2), .CE(1'b1), .D(\FSM_onehot_STATE[11]_i_1_n_0 ), .Q(\FSM_onehot_STATE_reg_n_0_[11] ), .R(\FSM_onehot_STATE[12]_i_1_n_0 )); (* FSM_ENCODED_STATES = "comma_detect_2:0000000000001,aquire_sync_2:0000000000010,aquire_sync_1:0000000010000,sync_acquired_4:0000010000000,sync_acquired_4a:0000000100000,sync_acquired_3a:0000100000000,comma_detect_1:0010000000000,loss_of_sync:0000000000100,sync_acquired_2:0001000000000,sync_acquired_3:0000001000000,sync_acquired_2a:0100000000000,sync_acquired_1:1000000000000,comma_detect_3:0000000001000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_STATE_reg[12] (.C(userclk2), .CE(1'b1), .D(\FSM_onehot_STATE[12]_i_2_n_0 ), .Q(\FSM_onehot_STATE_reg_n_0_[12] ), .R(\FSM_onehot_STATE[12]_i_1_n_0 )); (* FSM_ENCODED_STATES = "comma_detect_2:0000000000001,aquire_sync_2:0000000000010,aquire_sync_1:0000000010000,sync_acquired_4:0000010000000,sync_acquired_4a:0000000100000,sync_acquired_3a:0000100000000,comma_detect_1:0010000000000,loss_of_sync:0000000000100,sync_acquired_2:0001000000000,sync_acquired_3:0000001000000,sync_acquired_2a:0100000000000,sync_acquired_1:1000000000000,comma_detect_3:0000000001000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_STATE_reg[1] (.C(userclk2), .CE(1'b1), .D(\FSM_onehot_STATE[1]_i_1_n_0 ), .Q(\FSM_onehot_STATE_reg_n_0_[1] ), .R(\FSM_onehot_STATE[12]_i_1_n_0 )); (* FSM_ENCODED_STATES = "comma_detect_2:0000000000001,aquire_sync_2:0000000000010,aquire_sync_1:0000000010000,sync_acquired_4:0000010000000,sync_acquired_4a:0000000100000,sync_acquired_3a:0000100000000,comma_detect_1:0010000000000,loss_of_sync:0000000000100,sync_acquired_2:0001000000000,sync_acquired_3:0000001000000,sync_acquired_2a:0100000000000,sync_acquired_1:1000000000000,comma_detect_3:0000000001000" *) FDSE #( .INIT(1'b1)) \FSM_onehot_STATE_reg[2] (.C(userclk2), .CE(1'b1), .D(\FSM_onehot_STATE[2]_i_1_n_0 ), .Q(\FSM_onehot_STATE_reg_n_0_[2] ), .S(\FSM_onehot_STATE[12]_i_1_n_0 )); (* FSM_ENCODED_STATES = "comma_detect_2:0000000000001,aquire_sync_2:0000000000010,aquire_sync_1:0000000010000,sync_acquired_4:0000010000000,sync_acquired_4a:0000000100000,sync_acquired_3a:0000100000000,comma_detect_1:0010000000000,loss_of_sync:0000000000100,sync_acquired_2:0001000000000,sync_acquired_3:0000001000000,sync_acquired_2a:0100000000000,sync_acquired_1:1000000000000,comma_detect_3:0000000001000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_STATE_reg[3] (.C(userclk2), .CE(1'b1), .D(\FSM_onehot_STATE[3]_i_1_n_0 ), .Q(p_0_in), .R(\FSM_onehot_STATE[12]_i_1_n_0 )); (* FSM_ENCODED_STATES = "comma_detect_2:0000000000001,aquire_sync_2:0000000000010,aquire_sync_1:0000000010000,sync_acquired_4:0000010000000,sync_acquired_4a:0000000100000,sync_acquired_3a:0000100000000,comma_detect_1:0010000000000,loss_of_sync:0000000000100,sync_acquired_2:0001000000000,sync_acquired_3:0000001000000,sync_acquired_2a:0100000000000,sync_acquired_1:1000000000000,comma_detect_3:0000000001000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_STATE_reg[4] (.C(userclk2), .CE(1'b1), .D(\FSM_onehot_STATE[4]_i_1_n_0 ), .Q(\FSM_onehot_STATE_reg_n_0_[4] ), .R(\FSM_onehot_STATE[12]_i_1_n_0 )); (* FSM_ENCODED_STATES = "comma_detect_2:0000000000001,aquire_sync_2:0000000000010,aquire_sync_1:0000000010000,sync_acquired_4:0000010000000,sync_acquired_4a:0000000100000,sync_acquired_3a:0000100000000,comma_detect_1:0010000000000,loss_of_sync:0000000000100,sync_acquired_2:0001000000000,sync_acquired_3:0000001000000,sync_acquired_2a:0100000000000,sync_acquired_1:1000000000000,comma_detect_3:0000000001000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_STATE_reg[5] (.C(userclk2), .CE(1'b1), .D(\FSM_onehot_STATE[5]_i_1_n_0 ), .Q(\FSM_onehot_STATE_reg_n_0_[5] ), .R(\FSM_onehot_STATE[12]_i_1_n_0 )); (* FSM_ENCODED_STATES = "comma_detect_2:0000000000001,aquire_sync_2:0000000000010,aquire_sync_1:0000000010000,sync_acquired_4:0000010000000,sync_acquired_4a:0000000100000,sync_acquired_3a:0000100000000,comma_detect_1:0010000000000,loss_of_sync:0000000000100,sync_acquired_2:0001000000000,sync_acquired_3:0000001000000,sync_acquired_2a:0100000000000,sync_acquired_1:1000000000000,comma_detect_3:0000000001000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_STATE_reg[6] (.C(userclk2), .CE(1'b1), .D(\FSM_onehot_STATE[6]_i_1_n_0 ), .Q(\FSM_onehot_STATE_reg_n_0_[6] ), .R(\FSM_onehot_STATE[12]_i_1_n_0 )); (* FSM_ENCODED_STATES = "comma_detect_2:0000000000001,aquire_sync_2:0000000000010,aquire_sync_1:0000000010000,sync_acquired_4:0000010000000,sync_acquired_4a:0000000100000,sync_acquired_3a:0000100000000,comma_detect_1:0010000000000,loss_of_sync:0000000000100,sync_acquired_2:0001000000000,sync_acquired_3:0000001000000,sync_acquired_2a:0100000000000,sync_acquired_1:1000000000000,comma_detect_3:0000000001000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_STATE_reg[7] (.C(userclk2), .CE(1'b1), .D(\FSM_onehot_STATE[7]_i_1_n_0 ), .Q(p_1_in), .R(\FSM_onehot_STATE[12]_i_1_n_0 )); (* FSM_ENCODED_STATES = "comma_detect_2:0000000000001,aquire_sync_2:0000000000010,aquire_sync_1:0000000010000,sync_acquired_4:0000010000000,sync_acquired_4a:0000000100000,sync_acquired_3a:0000100000000,comma_detect_1:0010000000000,loss_of_sync:0000000000100,sync_acquired_2:0001000000000,sync_acquired_3:0000001000000,sync_acquired_2a:0100000000000,sync_acquired_1:1000000000000,comma_detect_3:0000000001000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_STATE_reg[8] (.C(userclk2), .CE(1'b1), .D(\FSM_onehot_STATE[8]_i_1_n_0 ), .Q(\FSM_onehot_STATE_reg_n_0_[8] ), .R(\FSM_onehot_STATE[12]_i_1_n_0 )); (* FSM_ENCODED_STATES = "comma_detect_2:0000000000001,aquire_sync_2:0000000000010,aquire_sync_1:0000000010000,sync_acquired_4:0000010000000,sync_acquired_4a:0000000100000,sync_acquired_3a:0000100000000,comma_detect_1:0010000000000,loss_of_sync:0000000000100,sync_acquired_2:0001000000000,sync_acquired_3:0000001000000,sync_acquired_2a:0100000000000,sync_acquired_1:1000000000000,comma_detect_3:0000000001000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_STATE_reg[9] (.C(userclk2), .CE(1'b1), .D(\FSM_onehot_STATE[9]_i_1_n_0 ), .Q(\FSM_onehot_STATE_reg_n_0_[9] ), .R(\FSM_onehot_STATE[12]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000009)) \GOOD_CGS[0]_i_1 (.I0(GOOD_CGS[0]), .I1(ENCOMMAALIGN_i_2_n_0), .I2(p_1_in), .I3(\FSM_onehot_STATE_reg_n_0_[9] ), .I4(EVEN_reg_0), .I5(\FSM_onehot_STATE_reg_n_0_[6] ), .O(\GOOD_CGS[0]_i_1_n_0 )); LUT4 #( .INIT(16'h009A)) \GOOD_CGS[1]_i_1 (.I0(GOOD_CGS[1]), .I1(ENCOMMAALIGN_i_2_n_0), .I2(GOOD_CGS[0]), .I3(\GOOD_CGS[1]_i_2_n_0 ), .O(\GOOD_CGS[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair40" *) LUT4 #( .INIT(16'hFFFE)) \GOOD_CGS[1]_i_2 (.I0(\FSM_onehot_STATE_reg_n_0_[6] ), .I1(EVEN_reg_0), .I2(\FSM_onehot_STATE_reg_n_0_[9] ), .I3(p_1_in), .O(\GOOD_CGS[1]_i_2_n_0 )); FDRE \GOOD_CGS_reg[0] (.C(userclk2), .CE(1'b1), .D(\GOOD_CGS[0]_i_1_n_0 ), .Q(GOOD_CGS[0]), .R(1'b0)); FDRE \GOOD_CGS_reg[1] (.C(userclk2), .CE(1'b1), .D(\GOOD_CGS[1]_i_1_n_0 ), .Q(GOOD_CGS[1]), .R(1'b0)); LUT5 #( .INIT(32'h20220000)) I_i_1 (.I0(I_reg), .I1(I_reg_0), .I2(RXSYNC_STATUS), .I3(\FSM_onehot_STATE_reg[2]_0 ), .I4(RXEVEN0_out), .O(I0)); (* SOFT_HLUTNM = "soft_lutpair40" *) LUT2 #( .INIT(4'hB)) RX_INVALID_i_1 (.I0(EVEN_reg_0), .I1(RXSYNC_STATUS), .O(SYNC_STATUS_REG0)); FDRE SIGNAL_DETECT_REG_reg (.C(userclk2), .CE(1'b1), .D(SIGNAL_DETECT_MOD), .Q(SIGNAL_DETECT_REG), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair41" *) LUT2 #( .INIT(4'h8)) STATUS_VECTOR_0_PRE_i_1 (.I0(RXSYNC_STATUS), .I1(reset_done), .O(STATUS_VECTOR_0_PRE0)); LUT6 #( .INIT(64'hFFFFFFFF0000222A)) SYNC_STATUS_i_1 (.I0(RXSYNC_STATUS), .I1(ENCOMMAALIGN_i_2_n_0), .I2(\FSM_onehot_STATE_reg_n_0_[5] ), .I3(p_1_in), .I4(\FSM_onehot_STATE_reg_n_0_[2] ), .I5(SYNC_STATUS0), .O(SYNC_STATUS_i_1_n_0)); FDRE #( .INIT(1'b0)) SYNC_STATUS_reg (.C(userclk2), .CE(1'b1), .D(SYNC_STATUS_i_1_n_0), .Q(RXSYNC_STATUS), .R(1'b0)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_TX (\USE_ROCKET_IO.MGT_TX_RESET_INT_reg , D, \CODE_GRP_CNT_reg[0]_0 , \CODE_GRP_CNT_reg[0]_1 , \NO_QSGMII_DATA.TXCHARISK_reg_0 , \NO_QSGMII_DATA.TXCHARISK_reg_1 , \NO_QSGMII_DATA.TXDATA_reg[2]_0 , \NO_QSGMII_DATA.TXDATA_reg[3]_0 , \NO_QSGMII_DATA.TXDATA_reg[5]_0 , \NO_QSGMII_DATA.TXDATA_reg[7]_0 , \NO_QSGMII_CHAR.TXCHARDISPVAL_reg_0 , \NO_QSGMII_DATA.TXDATA_reg[7]_1 , gmii_tx_en, userclk2, \NO_QSGMII_DATA.TXDATA_reg[4]_0 , gmii_tx_er, CONFIGURATION_VECTOR_REG, gmii_txd, SR, rxcharisk, rxchariscomma, rxdata); output \USE_ROCKET_IO.MGT_TX_RESET_INT_reg ; output [3:0]D; output \CODE_GRP_CNT_reg[0]_0 ; output \CODE_GRP_CNT_reg[0]_1 ; output \NO_QSGMII_DATA.TXCHARISK_reg_0 ; output \NO_QSGMII_DATA.TXCHARISK_reg_1 ; output \NO_QSGMII_DATA.TXDATA_reg[2]_0 ; output \NO_QSGMII_DATA.TXDATA_reg[3]_0 ; output \NO_QSGMII_DATA.TXDATA_reg[5]_0 ; output \NO_QSGMII_DATA.TXDATA_reg[7]_0 ; output \NO_QSGMII_CHAR.TXCHARDISPVAL_reg_0 ; output [7:0]\NO_QSGMII_DATA.TXDATA_reg[7]_1 ; input gmii_tx_en; input userclk2; input \NO_QSGMII_DATA.TXDATA_reg[4]_0 ; input gmii_tx_er; input [0:0]CONFIGURATION_VECTOR_REG; input [7:0]gmii_txd; input [0:0]SR; input [0:0]rxcharisk; input [0:0]rxchariscomma; input [7:0]rxdata; wire C1_OR_C2_i_1_n_0; wire C1_OR_C2_reg_n_0; wire CODE_GRPISK; wire CODE_GRPISK_i_1_n_0; wire CODE_GRPISK_i_2_n_0; wire \CODE_GRP[0]_i_1_n_0 ; wire \CODE_GRP[0]_i_2_n_0 ; wire \CODE_GRP[1]_i_1_n_0 ; wire \CODE_GRP[1]_i_2_n_0 ; wire \CODE_GRP[1]_i_3_n_0 ; wire \CODE_GRP[2]_i_1_n_0 ; wire \CODE_GRP[2]_i_2_n_0 ; wire \CODE_GRP[3]_i_1_n_0 ; wire \CODE_GRP[3]_i_2_n_0 ; wire \CODE_GRP[4]_i_1_n_0 ; wire \CODE_GRP[5]_i_1_n_0 ; wire \CODE_GRP[6]_i_1_n_0 ; wire \CODE_GRP[6]_i_2_n_0 ; wire \CODE_GRP[6]_i_3_n_0 ; wire \CODE_GRP[7]_i_1_n_0 ; wire \CODE_GRP[7]_i_2_n_0 ; wire \CODE_GRP_CNT_reg[0]_0 ; wire \CODE_GRP_CNT_reg[0]_1 ; wire \CODE_GRP_CNT_reg_n_0_[1] ; wire \CODE_GRP_reg_n_0_[0] ; wire [0:0]CONFIGURATION_VECTOR_REG; wire [6:0]CONFIG_DATA; wire \CONFIG_DATA_reg_n_0_[0] ; wire \CONFIG_DATA_reg_n_0_[3] ; wire \CONFIG_DATA_reg_n_0_[4] ; wire \CONFIG_DATA_reg_n_0_[6] ; wire [3:0]D; wire DISPARITY; wire INSERT_IDLE; wire INSERT_IDLE_i_1_n_0; wire INSERT_IDLE_reg_n_0; wire K28p5; wire K28p5_i_1_n_0; wire \NO_QSGMII_CHAR.TXCHARDISPVAL_i_1_n_0 ; wire \NO_QSGMII_CHAR.TXCHARDISPVAL_reg_0 ; wire \NO_QSGMII_DATA.TXCHARISK_reg_0 ; wire \NO_QSGMII_DATA.TXCHARISK_reg_1 ; wire \NO_QSGMII_DATA.TXDATA[0]_i_1_n_0 ; wire \NO_QSGMII_DATA.TXDATA[2]_i_1_n_0 ; wire \NO_QSGMII_DATA.TXDATA[4]_i_1_n_0 ; wire \NO_QSGMII_DATA.TXDATA[5]_i_1_n_0 ; wire \NO_QSGMII_DATA.TXDATA[6]_i_1_n_0 ; wire \NO_QSGMII_DATA.TXDATA[7]_i_1_n_0 ; wire \NO_QSGMII_DATA.TXDATA_reg[2]_0 ; wire \NO_QSGMII_DATA.TXDATA_reg[3]_0 ; wire \NO_QSGMII_DATA.TXDATA_reg[4]_0 ; wire \NO_QSGMII_DATA.TXDATA_reg[5]_0 ; wire \NO_QSGMII_DATA.TXDATA_reg[7]_0 ; wire [7:0]\NO_QSGMII_DATA.TXDATA_reg[7]_1 ; wire \NO_QSGMII_DISP.DISPARITY_i_1_n_0 ; wire \NO_QSGMII_DISP.DISPARITY_i_2_n_0 ; wire \NO_QSGMII_DISP.DISPARITY_i_3_n_0 ; wire R; wire R_i_1__0_n_0; wire S; wire S0; wire [0:0]SR; wire SYNC_DISPARITY_i_1_n_0; wire SYNC_DISPARITY_reg_n_0; wire T; wire T0; wire TRIGGER_S; wire TRIGGER_S0; wire TRIGGER_T; wire TXCHARDISPMODE_INT; wire TXCHARDISPVAL; wire TXCHARISK_INT; wire [7:0]TXDATA; wire [7:0]TXD_REG1; wire TX_EN_REG1; wire TX_ER_REG1; wire TX_EVEN; wire TX_PACKET; wire TX_PACKET_REG1; wire TX_PACKET_i_1_n_0; wire \USE_ROCKET_IO.MGT_TX_RESET_INT_reg ; wire V; wire V_i_1_n_0; wire V_i_2_n_0; wire V_i_3_n_0; wire V_i_4_n_0; wire V_i_5_n_0; wire V_i_6_n_0; wire XMIT_CONFIG_INT; wire XMIT_CONFIG_INT_i_1_n_0; wire XMIT_DATA_INT_i_1_n_0; wire XMIT_DATA_INT_reg_n_0; wire gmii_tx_en; wire gmii_tx_er; wire [7:0]gmii_txd; wire p_0_in; wire p_0_in16_in; wire p_0_in35_in; wire p_10_out; wire p_1_in; wire p_1_in1_in; wire p_1_in34_in; wire p_33_in; wire p_45_in; wire [1:0]plusOp; wire [0:0]rxchariscomma; wire [0:0]rxcharisk; wire [7:0]rxdata; wire userclk2; (* SOFT_HLUTNM = "soft_lutpair9" *) LUT4 #( .INIT(16'h3F80)) C1_OR_C2_i_1 (.I0(XMIT_CONFIG_INT), .I1(TX_EVEN), .I2(\CODE_GRP_CNT_reg_n_0_[1] ), .I3(C1_OR_C2_reg_n_0), .O(C1_OR_C2_i_1_n_0)); FDRE C1_OR_C2_reg (.C(userclk2), .CE(1'b1), .D(C1_OR_C2_i_1_n_0), .Q(C1_OR_C2_reg_n_0), .R(\NO_QSGMII_DATA.TXDATA_reg[4]_0 )); (* SOFT_HLUTNM = "soft_lutpair6" *) LUT4 #( .INIT(16'h2F20)) CODE_GRPISK_i_1 (.I0(TX_EVEN), .I1(\CODE_GRP_CNT_reg_n_0_[1] ), .I2(XMIT_CONFIG_INT), .I3(CODE_GRPISK_i_2_n_0), .O(CODE_GRPISK_i_1_n_0)); LUT6 #( .INIT(64'hFFFFFFFFFFFEFFFF)) CODE_GRPISK_i_2 (.I0(V), .I1(R), .I2(T), .I3(S), .I4(TX_PACKET), .I5(SR), .O(CODE_GRPISK_i_2_n_0)); FDRE CODE_GRPISK_reg (.C(userclk2), .CE(1'b1), .D(CODE_GRPISK_i_1_n_0), .Q(CODE_GRPISK), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1" *) LUT5 #( .INIT(32'hAAFFAA03)) \CODE_GRP[0]_i_1 (.I0(\CONFIG_DATA_reg_n_0_[0] ), .I1(\CODE_GRP[0]_i_2_n_0 ), .I2(V), .I3(XMIT_CONFIG_INT), .I4(S), .O(\CODE_GRP[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair5" *) LUT4 #( .INIT(16'h0007)) \CODE_GRP[0]_i_2 (.I0(TXD_REG1[0]), .I1(TX_PACKET), .I2(R), .I3(T), .O(\CODE_GRP[0]_i_2_n_0 )); LUT6 #( .INIT(64'h00005555FFC05555)) \CODE_GRP[1]_i_1 (.I0(\CODE_GRP[1]_i_2_n_0 ), .I1(TXD_REG1[1]), .I2(TX_PACKET), .I3(R), .I4(\CODE_GRP[1]_i_3_n_0 ), .I5(T), .O(\CODE_GRP[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair0" *) LUT2 #( .INIT(4'h2)) \CODE_GRP[1]_i_2 (.I0(XMIT_CONFIG_INT), .I1(\CONFIG_DATA_reg_n_0_[6] ), .O(\CODE_GRP[1]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair1" *) LUT3 #( .INIT(8'h01)) \CODE_GRP[1]_i_3 (.I0(V), .I1(XMIT_CONFIG_INT), .I2(S), .O(\CODE_GRP[1]_i_3_n_0 )); LUT6 #( .INIT(64'hAAAAAAAA0000FFCF)) \CODE_GRP[2]_i_1 (.I0(\CONFIG_DATA_reg_n_0_[4] ), .I1(\CODE_GRP[2]_i_2_n_0 ), .I2(TX_PACKET), .I3(TXD_REG1[2]), .I4(S), .I5(XMIT_CONFIG_INT), .O(\CODE_GRP[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair2" *) LUT3 #( .INIT(8'hFE)) \CODE_GRP[2]_i_2 (.I0(V), .I1(R), .I2(T), .O(\CODE_GRP[2]_i_2_n_0 )); LUT4 #( .INIT(16'hFFD0)) \CODE_GRP[3]_i_1 (.I0(TX_PACKET), .I1(TXD_REG1[3]), .I2(\CODE_GRP[6]_i_3_n_0 ), .I3(\CODE_GRP[3]_i_2_n_0 ), .O(\CODE_GRP[3]_i_1_n_0 )); LUT6 #( .INIT(64'hAAFFAAFFAAFFAAFC)) \CODE_GRP[3]_i_2 (.I0(\CONFIG_DATA_reg_n_0_[3] ), .I1(SR), .I2(S), .I3(XMIT_CONFIG_INT), .I4(V), .I5(T), .O(\CODE_GRP[3]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFF808080)) \CODE_GRP[4]_i_1 (.I0(\CODE_GRP[6]_i_3_n_0 ), .I1(TXD_REG1[4]), .I2(TX_PACKET), .I3(XMIT_CONFIG_INT), .I4(\CONFIG_DATA_reg_n_0_[4] ), .I5(\CODE_GRP[7]_i_2_n_0 ), .O(\CODE_GRP[4]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFF808080)) \CODE_GRP[5]_i_1 (.I0(\CODE_GRP[6]_i_3_n_0 ), .I1(TXD_REG1[5]), .I2(TX_PACKET), .I3(XMIT_CONFIG_INT), .I4(\CONFIG_DATA_reg_n_0_[4] ), .I5(\CODE_GRP[7]_i_2_n_0 ), .O(\CODE_GRP[5]_i_1_n_0 )); LUT2 #( .INIT(4'h2)) \CODE_GRP[6]_i_1 (.I0(SR), .I1(XMIT_CONFIG_INT), .O(\CODE_GRP[6]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair0" *) LUT5 #( .INIT(32'hB000BBBB)) \CODE_GRP[6]_i_2 (.I0(\CONFIG_DATA_reg_n_0_[6] ), .I1(XMIT_CONFIG_INT), .I2(TX_PACKET), .I3(TXD_REG1[6]), .I4(\CODE_GRP[6]_i_3_n_0 ), .O(\CODE_GRP[6]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair2" *) LUT5 #( .INIT(32'h00000001)) \CODE_GRP[6]_i_3 (.I0(XMIT_CONFIG_INT), .I1(S), .I2(T), .I3(R), .I4(V), .O(\CODE_GRP[6]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFF808080)) \CODE_GRP[7]_i_1 (.I0(\CODE_GRP[6]_i_3_n_0 ), .I1(TXD_REG1[7]), .I2(TX_PACKET), .I3(XMIT_CONFIG_INT), .I4(\CONFIG_DATA_reg_n_0_[4] ), .I5(\CODE_GRP[7]_i_2_n_0 ), .O(\CODE_GRP[7]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair3" *) LUT5 #( .INIT(32'h0000FFFB)) \CODE_GRP[7]_i_2 (.I0(SR), .I1(TX_PACKET), .I2(S), .I3(\CODE_GRP[2]_i_2_n_0 ), .I4(XMIT_CONFIG_INT), .O(\CODE_GRP[7]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair23" *) LUT1 #( .INIT(2'h1)) \CODE_GRP_CNT[0]_i_1 (.I0(TX_EVEN), .O(plusOp[0])); (* SOFT_HLUTNM = "soft_lutpair21" *) LUT2 #( .INIT(4'h6)) \CODE_GRP_CNT[1]_i_1 (.I0(TX_EVEN), .I1(\CODE_GRP_CNT_reg_n_0_[1] ), .O(plusOp[1])); FDSE \CODE_GRP_CNT_reg[0] (.C(userclk2), .CE(1'b1), .D(plusOp[0]), .Q(TX_EVEN), .S(\NO_QSGMII_DATA.TXDATA_reg[4]_0 )); FDSE \CODE_GRP_CNT_reg[1] (.C(userclk2), .CE(1'b1), .D(plusOp[1]), .Q(\CODE_GRP_CNT_reg_n_0_[1] ), .S(\NO_QSGMII_DATA.TXDATA_reg[4]_0 )); FDRE \CODE_GRP_reg[0] (.C(userclk2), .CE(1'b1), .D(\CODE_GRP[0]_i_1_n_0 ), .Q(\CODE_GRP_reg_n_0_[0] ), .R(\CODE_GRP[6]_i_1_n_0 )); FDRE \CODE_GRP_reg[1] (.C(userclk2), .CE(1'b1), .D(\CODE_GRP[1]_i_1_n_0 ), .Q(p_1_in), .R(\CODE_GRP[6]_i_1_n_0 )); FDSE \CODE_GRP_reg[2] (.C(userclk2), .CE(1'b1), .D(\CODE_GRP[2]_i_1_n_0 ), .Q(p_0_in16_in), .S(\CODE_GRP[6]_i_1_n_0 )); FDRE \CODE_GRP_reg[3] (.C(userclk2), .CE(1'b1), .D(\CODE_GRP[3]_i_1_n_0 ), .Q(p_0_in), .R(1'b0)); FDRE \CODE_GRP_reg[4] (.C(userclk2), .CE(1'b1), .D(\CODE_GRP[4]_i_1_n_0 ), .Q(p_1_in1_in), .R(1'b0)); FDRE \CODE_GRP_reg[5] (.C(userclk2), .CE(1'b1), .D(\CODE_GRP[5]_i_1_n_0 ), .Q(p_1_in34_in), .R(1'b0)); FDRE \CODE_GRP_reg[6] (.C(userclk2), .CE(1'b1), .D(\CODE_GRP[6]_i_2_n_0 ), .Q(p_33_in), .R(\CODE_GRP[6]_i_1_n_0 )); FDRE \CODE_GRP_reg[7] (.C(userclk2), .CE(1'b1), .D(\CODE_GRP[7]_i_1_n_0 ), .Q(p_0_in35_in), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair9" *) LUT3 #( .INIT(8'h04)) \CONFIG_DATA[0]_i_1 (.I0(\CODE_GRP_CNT_reg_n_0_[1] ), .I1(TX_EVEN), .I2(C1_OR_C2_reg_n_0), .O(CONFIG_DATA[0])); (* SOFT_HLUTNM = "soft_lutpair22" *) LUT2 #( .INIT(4'h1)) \CONFIG_DATA[3]_i_1 (.I0(TX_EVEN), .I1(\CODE_GRP_CNT_reg_n_0_[1] ), .O(CONFIG_DATA[3])); (* SOFT_HLUTNM = "soft_lutpair12" *) LUT3 #( .INIT(8'h13)) \CONFIG_DATA[4]_i_1 (.I0(TX_EVEN), .I1(\CODE_GRP_CNT_reg_n_0_[1] ), .I2(C1_OR_C2_reg_n_0), .O(CONFIG_DATA[4])); (* SOFT_HLUTNM = "soft_lutpair12" *) LUT3 #( .INIT(8'h20)) \CONFIG_DATA[6]_i_1 (.I0(C1_OR_C2_reg_n_0), .I1(\CODE_GRP_CNT_reg_n_0_[1] ), .I2(TX_EVEN), .O(CONFIG_DATA[6])); FDRE \CONFIG_DATA_reg[0] (.C(userclk2), .CE(1'b1), .D(CONFIG_DATA[0]), .Q(\CONFIG_DATA_reg_n_0_[0] ), .R(\NO_QSGMII_DATA.TXDATA_reg[4]_0 )); FDRE \CONFIG_DATA_reg[3] (.C(userclk2), .CE(1'b1), .D(CONFIG_DATA[3]), .Q(\CONFIG_DATA_reg_n_0_[3] ), .R(\NO_QSGMII_DATA.TXDATA_reg[4]_0 )); FDRE \CONFIG_DATA_reg[4] (.C(userclk2), .CE(1'b1), .D(CONFIG_DATA[4]), .Q(\CONFIG_DATA_reg_n_0_[4] ), .R(\NO_QSGMII_DATA.TXDATA_reg[4]_0 )); FDRE \CONFIG_DATA_reg[6] (.C(userclk2), .CE(1'b1), .D(CONFIG_DATA[6]), .Q(\CONFIG_DATA_reg_n_0_[6] ), .R(\NO_QSGMII_DATA.TXDATA_reg[4]_0 )); (* SOFT_HLUTNM = "soft_lutpair3" *) LUT5 #( .INIT(32'h0000FF01)) INSERT_IDLE_i_1 (.I0(TX_PACKET), .I1(\CODE_GRP[2]_i_2_n_0 ), .I2(S), .I3(SR), .I4(XMIT_CONFIG_INT), .O(INSERT_IDLE_i_1_n_0)); FDRE INSERT_IDLE_reg (.C(userclk2), .CE(1'b1), .D(INSERT_IDLE_i_1_n_0), .Q(INSERT_IDLE_reg_n_0), .R(1'b0)); LUT2 #( .INIT(4'h8)) K28p5_i_1 (.I0(XMIT_CONFIG_INT), .I1(\CONFIG_DATA_reg_n_0_[3] ), .O(K28p5_i_1_n_0)); FDRE K28p5_reg (.C(userclk2), .CE(1'b1), .D(K28p5_i_1_n_0), .Q(K28p5), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair23" *) LUT2 #( .INIT(4'h2)) \NO_QSGMII_CHAR.TXCHARDISPMODE_i_1 (.I0(SYNC_DISPARITY_reg_n_0), .I1(TX_EVEN), .O(p_10_out)); FDSE \NO_QSGMII_CHAR.TXCHARDISPMODE_reg (.C(userclk2), .CE(1'b1), .D(p_10_out), .Q(TXCHARDISPMODE_INT), .S(\NO_QSGMII_DATA.TXDATA_reg[4]_0 )); (* SOFT_HLUTNM = "soft_lutpair10" *) LUT3 #( .INIT(8'h40)) \NO_QSGMII_CHAR.TXCHARDISPVAL_i_1 (.I0(TX_EVEN), .I1(SYNC_DISPARITY_reg_n_0), .I2(DISPARITY), .O(\NO_QSGMII_CHAR.TXCHARDISPVAL_i_1_n_0 )); FDRE \NO_QSGMII_CHAR.TXCHARDISPVAL_reg (.C(userclk2), .CE(1'b1), .D(\NO_QSGMII_CHAR.TXCHARDISPVAL_i_1_n_0 ), .Q(TXCHARDISPVAL), .R(\NO_QSGMII_DATA.TXDATA_reg[4]_0 )); FDRE \NO_QSGMII_DATA.TXCHARISK_reg (.C(userclk2), .CE(1'b1), .D(CODE_GRPISK), .Q(TXCHARISK_INT), .R(\NO_QSGMII_DATA.TXDATA[5]_i_1_n_0 )); LUT5 #( .INIT(32'h23332000)) \NO_QSGMII_DATA.TXDATA[0]_i_1 (.I0(DISPARITY), .I1(\NO_QSGMII_DATA.TXDATA_reg[4]_0 ), .I2(TX_EVEN), .I3(INSERT_IDLE_reg_n_0), .I4(\CODE_GRP_reg_n_0_[0] ), .O(\NO_QSGMII_DATA.TXDATA[0]_i_1_n_0 )); LUT5 #( .INIT(32'h23332000)) \NO_QSGMII_DATA.TXDATA[2]_i_1 (.I0(DISPARITY), .I1(\NO_QSGMII_DATA.TXDATA_reg[4]_0 ), .I2(TX_EVEN), .I3(INSERT_IDLE_reg_n_0), .I4(p_0_in16_in), .O(\NO_QSGMII_DATA.TXDATA[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair10" *) LUT4 #( .INIT(16'h7F40)) \NO_QSGMII_DATA.TXDATA[4]_i_1 (.I0(DISPARITY), .I1(INSERT_IDLE_reg_n_0), .I2(TX_EVEN), .I3(p_1_in1_in), .O(\NO_QSGMII_DATA.TXDATA[4]_i_1_n_0 )); LUT3 #( .INIT(8'hEA)) \NO_QSGMII_DATA.TXDATA[5]_i_1 (.I0(\NO_QSGMII_DATA.TXDATA_reg[4]_0 ), .I1(TX_EVEN), .I2(INSERT_IDLE_reg_n_0), .O(\NO_QSGMII_DATA.TXDATA[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair7" *) LUT4 #( .INIT(16'h5540)) \NO_QSGMII_DATA.TXDATA[6]_i_1 (.I0(\NO_QSGMII_DATA.TXDATA_reg[4]_0 ), .I1(INSERT_IDLE_reg_n_0), .I2(TX_EVEN), .I3(p_33_in), .O(\NO_QSGMII_DATA.TXDATA[6]_i_1_n_0 )); LUT5 #( .INIT(32'h23332000)) \NO_QSGMII_DATA.TXDATA[7]_i_1 (.I0(DISPARITY), .I1(\NO_QSGMII_DATA.TXDATA_reg[4]_0 ), .I2(TX_EVEN), .I3(INSERT_IDLE_reg_n_0), .I4(p_0_in35_in), .O(\NO_QSGMII_DATA.TXDATA[7]_i_1_n_0 )); FDRE \NO_QSGMII_DATA.TXDATA_reg[0] (.C(userclk2), .CE(1'b1), .D(\NO_QSGMII_DATA.TXDATA[0]_i_1_n_0 ), .Q(TXDATA[0]), .R(1'b0)); FDRE \NO_QSGMII_DATA.TXDATA_reg[1] (.C(userclk2), .CE(1'b1), .D(p_1_in), .Q(TXDATA[1]), .R(\NO_QSGMII_DATA.TXDATA[5]_i_1_n_0 )); FDRE \NO_QSGMII_DATA.TXDATA_reg[2] (.C(userclk2), .CE(1'b1), .D(\NO_QSGMII_DATA.TXDATA[2]_i_1_n_0 ), .Q(TXDATA[2]), .R(1'b0)); FDRE \NO_QSGMII_DATA.TXDATA_reg[3] (.C(userclk2), .CE(1'b1), .D(p_0_in), .Q(TXDATA[3]), .R(\NO_QSGMII_DATA.TXDATA[5]_i_1_n_0 )); FDRE \NO_QSGMII_DATA.TXDATA_reg[4] (.C(userclk2), .CE(1'b1), .D(\NO_QSGMII_DATA.TXDATA[4]_i_1_n_0 ), .Q(TXDATA[4]), .R(\NO_QSGMII_DATA.TXDATA_reg[4]_0 )); FDRE \NO_QSGMII_DATA.TXDATA_reg[5] (.C(userclk2), .CE(1'b1), .D(p_1_in34_in), .Q(TXDATA[5]), .R(\NO_QSGMII_DATA.TXDATA[5]_i_1_n_0 )); FDRE \NO_QSGMII_DATA.TXDATA_reg[6] (.C(userclk2), .CE(1'b1), .D(\NO_QSGMII_DATA.TXDATA[6]_i_1_n_0 ), .Q(TXDATA[6]), .R(1'b0)); FDRE \NO_QSGMII_DATA.TXDATA_reg[7] (.C(userclk2), .CE(1'b1), .D(\NO_QSGMII_DATA.TXDATA[7]_i_1_n_0 ), .Q(TXDATA[7]), .R(1'b0)); LUT6 #( .INIT(64'h0009090900F6F6F6)) \NO_QSGMII_DISP.DISPARITY_i_1 (.I0(\NO_QSGMII_DISP.DISPARITY_i_2_n_0 ), .I1(\NO_QSGMII_DISP.DISPARITY_i_3_n_0 ), .I2(K28p5), .I3(TX_EVEN), .I4(INSERT_IDLE_reg_n_0), .I5(DISPARITY), .O(\NO_QSGMII_DISP.DISPARITY_i_1_n_0 )); LUT5 #( .INIT(32'h167E7EE8)) \NO_QSGMII_DISP.DISPARITY_i_2 (.I0(p_1_in), .I1(\CODE_GRP_reg_n_0_[0] ), .I2(p_0_in16_in), .I3(p_0_in), .I4(p_1_in1_in), .O(\NO_QSGMII_DISP.DISPARITY_i_2_n_0 )); LUT3 #( .INIT(8'h7C)) \NO_QSGMII_DISP.DISPARITY_i_3 (.I0(p_0_in35_in), .I1(p_33_in), .I2(p_1_in34_in), .O(\NO_QSGMII_DISP.DISPARITY_i_3_n_0 )); FDSE \NO_QSGMII_DISP.DISPARITY_reg (.C(userclk2), .CE(1'b1), .D(\NO_QSGMII_DISP.DISPARITY_i_1_n_0 ), .Q(DISPARITY), .S(\NO_QSGMII_DATA.TXDATA_reg[4]_0 )); LUT5 #( .INIT(32'hDDDCCCCC)) R_i_1__0 (.I0(S), .I1(T), .I2(TX_ER_REG1), .I3(TX_EVEN), .I4(R), .O(R_i_1__0_n_0)); FDRE R_reg (.C(userclk2), .CE(1'b1), .D(R_i_1__0_n_0), .Q(R), .R(\NO_QSGMII_DATA.TXDATA_reg[4]_0 )); (* SOFT_HLUTNM = "soft_lutpair6" *) LUT4 #( .INIT(16'h2F20)) SYNC_DISPARITY_i_1 (.I0(TX_EVEN), .I1(\CODE_GRP_CNT_reg_n_0_[1] ), .I2(XMIT_CONFIG_INT), .I3(INSERT_IDLE), .O(SYNC_DISPARITY_i_1_n_0)); LUT6 #( .INIT(64'hAAAAAAAAAAAAAAAB)) SYNC_DISPARITY_i_2 (.I0(SR), .I1(S), .I2(T), .I3(R), .I4(V), .I5(TX_PACKET), .O(INSERT_IDLE)); FDRE SYNC_DISPARITY_reg (.C(userclk2), .CE(1'b1), .D(SYNC_DISPARITY_i_1_n_0), .Q(SYNC_DISPARITY_reg_n_0), .R(1'b0)); LUT6 #( .INIT(64'h8888A8AA88888888)) S_i_1__0 (.I0(XMIT_DATA_INT_reg_n_0), .I1(TRIGGER_S), .I2(TX_ER_REG1), .I3(TX_EVEN), .I4(TX_EN_REG1), .I5(gmii_tx_en), .O(S0)); FDRE S_reg (.C(userclk2), .CE(1'b1), .D(S0), .Q(S), .R(\NO_QSGMII_DATA.TXDATA_reg[4]_0 )); (* SOFT_HLUTNM = "soft_lutpair4" *) LUT4 #( .INIT(16'h0400)) TRIGGER_S_i_1 (.I0(TX_EN_REG1), .I1(gmii_tx_en), .I2(TX_ER_REG1), .I3(TX_EVEN), .O(TRIGGER_S0)); FDRE TRIGGER_S_reg (.C(userclk2), .CE(1'b1), .D(TRIGGER_S0), .Q(TRIGGER_S), .R(\NO_QSGMII_DATA.TXDATA_reg[4]_0 )); (* SOFT_HLUTNM = "soft_lutpair4" *) LUT2 #( .INIT(4'h2)) TRIGGER_T_i_1 (.I0(TX_EN_REG1), .I1(gmii_tx_en), .O(p_45_in)); FDRE TRIGGER_T_reg (.C(userclk2), .CE(1'b1), .D(p_45_in), .Q(TRIGGER_T), .R(\NO_QSGMII_DATA.TXDATA_reg[4]_0 )); FDRE \TXD_REG1_reg[0] (.C(userclk2), .CE(1'b1), .D(gmii_txd[0]), .Q(TXD_REG1[0]), .R(1'b0)); FDRE \TXD_REG1_reg[1] (.C(userclk2), .CE(1'b1), .D(gmii_txd[1]), .Q(TXD_REG1[1]), .R(1'b0)); FDRE \TXD_REG1_reg[2] (.C(userclk2), .CE(1'b1), .D(gmii_txd[2]), .Q(TXD_REG1[2]), .R(1'b0)); FDRE \TXD_REG1_reg[3] (.C(userclk2), .CE(1'b1), .D(gmii_txd[3]), .Q(TXD_REG1[3]), .R(1'b0)); FDRE \TXD_REG1_reg[4] (.C(userclk2), .CE(1'b1), .D(gmii_txd[4]), .Q(TXD_REG1[4]), .R(1'b0)); FDRE \TXD_REG1_reg[5] (.C(userclk2), .CE(1'b1), .D(gmii_txd[5]), .Q(TXD_REG1[5]), .R(1'b0)); FDRE \TXD_REG1_reg[6] (.C(userclk2), .CE(1'b1), .D(gmii_txd[6]), .Q(TXD_REG1[6]), .R(1'b0)); FDRE \TXD_REG1_reg[7] (.C(userclk2), .CE(1'b1), .D(gmii_txd[7]), .Q(TXD_REG1[7]), .R(1'b0)); FDRE TX_EN_REG1_reg (.C(userclk2), .CE(1'b1), .D(gmii_tx_en), .Q(TX_EN_REG1), .R(1'b0)); FDRE TX_ER_REG1_reg (.C(userclk2), .CE(1'b1), .D(gmii_tx_er), .Q(TX_ER_REG1), .R(1'b0)); FDRE TX_PACKET_REG1_reg (.C(userclk2), .CE(1'b1), .D(TX_PACKET), .Q(TX_PACKET_REG1), .R(\NO_QSGMII_DATA.TXDATA_reg[4]_0 )); (* SOFT_HLUTNM = "soft_lutpair5" *) LUT3 #( .INIT(8'hDC)) TX_PACKET_i_1 (.I0(T), .I1(S), .I2(TX_PACKET), .O(TX_PACKET_i_1_n_0)); FDRE TX_PACKET_reg (.C(userclk2), .CE(1'b1), .D(TX_PACKET_i_1_n_0), .Q(TX_PACKET), .R(\NO_QSGMII_DATA.TXDATA_reg[4]_0 )); LUT6 #( .INIT(64'h88888888FFF88888)) T_i_1 (.I0(TRIGGER_T), .I1(V), .I2(S), .I3(TX_PACKET), .I4(TX_EN_REG1), .I5(gmii_tx_en), .O(T0)); FDRE T_reg (.C(userclk2), .CE(1'b1), .D(T0), .Q(T), .R(\NO_QSGMII_DATA.TXDATA_reg[4]_0 )); (* SOFT_HLUTNM = "soft_lutpair14" *) LUT3 #( .INIT(8'hB8)) \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCHARISCOMMA_INT_i_1 (.I0(TXCHARISK_INT), .I1(CONFIGURATION_VECTOR_REG), .I2(rxchariscomma), .O(\NO_QSGMII_DATA.TXCHARISK_reg_1 )); (* SOFT_HLUTNM = "soft_lutpair13" *) LUT3 #( .INIT(8'hB8)) \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXCHARISK_INT_i_1 (.I0(TXCHARISK_INT), .I1(CONFIGURATION_VECTOR_REG), .I2(rxcharisk), .O(\NO_QSGMII_DATA.TXCHARISK_reg_0 )); LUT3 #( .INIT(8'hB8)) \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT[0]_i_1 (.I0(TXDATA[0]), .I1(CONFIGURATION_VECTOR_REG), .I2(rxdata[0]), .O(\NO_QSGMII_DATA.TXDATA_reg[7]_1 [0])); (* SOFT_HLUTNM = "soft_lutpair20" *) LUT3 #( .INIT(8'hB8)) \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT[1]_i_1 (.I0(TXDATA[1]), .I1(CONFIGURATION_VECTOR_REG), .I2(rxdata[1]), .O(\NO_QSGMII_DATA.TXDATA_reg[7]_1 [1])); (* SOFT_HLUTNM = "soft_lutpair15" *) LUT3 #( .INIT(8'hB8)) \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT[2]_i_1 (.I0(TXDATA[2]), .I1(CONFIGURATION_VECTOR_REG), .I2(rxdata[2]), .O(\NO_QSGMII_DATA.TXDATA_reg[7]_1 [2])); (* SOFT_HLUTNM = "soft_lutpair16" *) LUT3 #( .INIT(8'hB8)) \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT[3]_i_1 (.I0(TXDATA[3]), .I1(CONFIGURATION_VECTOR_REG), .I2(rxdata[3]), .O(\NO_QSGMII_DATA.TXDATA_reg[7]_1 [3])); (* SOFT_HLUTNM = "soft_lutpair20" *) LUT3 #( .INIT(8'hB8)) \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT[4]_i_1 (.I0(TXDATA[4]), .I1(CONFIGURATION_VECTOR_REG), .I2(rxdata[4]), .O(\NO_QSGMII_DATA.TXDATA_reg[7]_1 [4])); (* SOFT_HLUTNM = "soft_lutpair17" *) LUT3 #( .INIT(8'hB8)) \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT[5]_i_1 (.I0(TXDATA[5]), .I1(CONFIGURATION_VECTOR_REG), .I2(rxdata[5]), .O(\NO_QSGMII_DATA.TXDATA_reg[7]_1 [5])); (* SOFT_HLUTNM = "soft_lutpair19" *) LUT3 #( .INIT(8'hB8)) \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT[6]_i_1 (.I0(TXDATA[6]), .I1(CONFIGURATION_VECTOR_REG), .I2(rxdata[6]), .O(\NO_QSGMII_DATA.TXDATA_reg[7]_1 [6])); (* SOFT_HLUTNM = "soft_lutpair18" *) LUT3 #( .INIT(8'hB8)) \USE_ROCKET_IO.NO_1588.RECLOCK_MGT_SIGNALS_TXOUTCLK.RXDATA_INT[7]_i_1 (.I0(TXDATA[7]), .I1(CONFIGURATION_VECTOR_REG), .I2(rxdata[7]), .O(\NO_QSGMII_DATA.TXDATA_reg[7]_1 [7])); (* SOFT_HLUTNM = "soft_lutpair8" *) LUT3 #( .INIT(8'hB8)) \USE_ROCKET_IO.TXCHARDISPMODE_i_1 (.I0(TX_EVEN), .I1(CONFIGURATION_VECTOR_REG), .I2(TXCHARDISPMODE_INT), .O(\CODE_GRP_CNT_reg[0]_0 )); (* SOFT_HLUTNM = "soft_lutpair19" *) LUT3 #( .INIT(8'h02)) \USE_ROCKET_IO.TXCHARDISPVAL_i_1 (.I0(TXCHARDISPVAL), .I1(CONFIGURATION_VECTOR_REG), .I2(\NO_QSGMII_DATA.TXDATA_reg[4]_0 ), .O(\NO_QSGMII_CHAR.TXCHARDISPVAL_reg_0 )); (* SOFT_HLUTNM = "soft_lutpair13" *) LUT3 #( .INIT(8'hB8)) \USE_ROCKET_IO.TXCHARISK_i_1 (.I0(TX_EVEN), .I1(CONFIGURATION_VECTOR_REG), .I2(TXCHARISK_INT), .O(\CODE_GRP_CNT_reg[0]_1 )); (* SOFT_HLUTNM = "soft_lutpair11" *) LUT3 #( .INIT(8'h02)) \USE_ROCKET_IO.TXDATA[0]_i_1 (.I0(TXDATA[0]), .I1(CONFIGURATION_VECTOR_REG), .I2(\NO_QSGMII_DATA.TXDATA_reg[4]_0 ), .O(D[0])); (* SOFT_HLUTNM = "soft_lutpair14" *) LUT3 #( .INIT(8'h02)) \USE_ROCKET_IO.TXDATA[1]_i_1 (.I0(TXDATA[1]), .I1(CONFIGURATION_VECTOR_REG), .I2(\NO_QSGMII_DATA.TXDATA_reg[4]_0 ), .O(D[1])); (* SOFT_HLUTNM = "soft_lutpair15" *) LUT3 #( .INIT(8'h02)) \USE_ROCKET_IO.TXDATA[2]_i_1 (.I0(TXDATA[2]), .I1(CONFIGURATION_VECTOR_REG), .I2(\NO_QSGMII_DATA.TXDATA_reg[4]_0 ), .O(\NO_QSGMII_DATA.TXDATA_reg[2]_0 )); (* SOFT_HLUTNM = "soft_lutpair16" *) LUT3 #( .INIT(8'h02)) \USE_ROCKET_IO.TXDATA[3]_i_1 (.I0(TXDATA[3]), .I1(CONFIGURATION_VECTOR_REG), .I2(\NO_QSGMII_DATA.TXDATA_reg[4]_0 ), .O(\NO_QSGMII_DATA.TXDATA_reg[3]_0 )); (* SOFT_HLUTNM = "soft_lutpair11" *) LUT3 #( .INIT(8'h54)) \USE_ROCKET_IO.TXDATA[4]_i_1 (.I0(\NO_QSGMII_DATA.TXDATA_reg[4]_0 ), .I1(TXDATA[4]), .I2(CONFIGURATION_VECTOR_REG), .O(D[2])); (* SOFT_HLUTNM = "soft_lutpair17" *) LUT3 #( .INIT(8'h02)) \USE_ROCKET_IO.TXDATA[5]_i_1 (.I0(TXDATA[5]), .I1(CONFIGURATION_VECTOR_REG), .I2(\NO_QSGMII_DATA.TXDATA_reg[4]_0 ), .O(\NO_QSGMII_DATA.TXDATA_reg[5]_0 )); (* SOFT_HLUTNM = "soft_lutpair8" *) LUT4 #( .INIT(16'h0074)) \USE_ROCKET_IO.TXDATA[6]_i_1 (.I0(TX_EVEN), .I1(CONFIGURATION_VECTOR_REG), .I2(TXDATA[6]), .I3(\NO_QSGMII_DATA.TXDATA_reg[4]_0 ), .O(D[3])); (* SOFT_HLUTNM = "soft_lutpair7" *) LUT3 #( .INIT(8'h40)) \USE_ROCKET_IO.TXDATA[7]_i_1 (.I0(\NO_QSGMII_DATA.TXDATA_reg[4]_0 ), .I1(CONFIGURATION_VECTOR_REG), .I2(TX_EVEN), .O(\USE_ROCKET_IO.MGT_TX_RESET_INT_reg )); (* SOFT_HLUTNM = "soft_lutpair18" *) LUT3 #( .INIT(8'h02)) \USE_ROCKET_IO.TXDATA[7]_i_2 (.I0(TXDATA[7]), .I1(CONFIGURATION_VECTOR_REG), .I2(\NO_QSGMII_DATA.TXDATA_reg[4]_0 ), .O(\NO_QSGMII_DATA.TXDATA_reg[7]_0 )); LUT3 #( .INIT(8'hEA)) V_i_1 (.I0(V_i_2_n_0), .I1(S), .I2(V), .O(V_i_1_n_0)); LUT5 #( .INIT(32'h8A888A8A)) V_i_2 (.I0(XMIT_DATA_INT_reg_n_0), .I1(V_i_3_n_0), .I2(V_i_4_n_0), .I3(V_i_5_n_0), .I4(V_i_6_n_0), .O(V_i_2_n_0)); LUT3 #( .INIT(8'h08)) V_i_3 (.I0(TX_EN_REG1), .I1(TX_ER_REG1), .I2(TX_PACKET_REG1), .O(V_i_3_n_0)); LUT3 #( .INIT(8'h5D)) V_i_4 (.I0(gmii_tx_er), .I1(gmii_tx_en), .I2(TX_PACKET), .O(V_i_4_n_0)); LUT6 #( .INIT(64'hFFFFFDFFFFFFFFFF)) V_i_5 (.I0(gmii_txd[0]), .I1(gmii_txd[5]), .I2(gmii_tx_en), .I3(gmii_txd[3]), .I4(gmii_txd[6]), .I5(gmii_txd[1]), .O(V_i_5_n_0)); LUT3 #( .INIT(8'h04)) V_i_6 (.I0(gmii_txd[4]), .I1(gmii_txd[2]), .I2(gmii_txd[7]), .O(V_i_6_n_0)); FDRE V_reg (.C(userclk2), .CE(1'b1), .D(V_i_1_n_0), .Q(V), .R(\NO_QSGMII_DATA.TXDATA_reg[4]_0 )); (* SOFT_HLUTNM = "soft_lutpair21" *) LUT3 #( .INIT(8'hE0)) XMIT_CONFIG_INT_i_1 (.I0(TX_EVEN), .I1(\CODE_GRP_CNT_reg_n_0_[1] ), .I2(XMIT_CONFIG_INT), .O(XMIT_CONFIG_INT_i_1_n_0)); FDSE XMIT_CONFIG_INT_reg (.C(userclk2), .CE(1'b1), .D(XMIT_CONFIG_INT_i_1_n_0), .Q(XMIT_CONFIG_INT), .S(\NO_QSGMII_DATA.TXDATA_reg[4]_0 )); (* SOFT_HLUTNM = "soft_lutpair22" *) LUT3 #( .INIT(8'hF1)) XMIT_DATA_INT_i_1 (.I0(\CODE_GRP_CNT_reg_n_0_[1] ), .I1(TX_EVEN), .I2(XMIT_DATA_INT_reg_n_0), .O(XMIT_DATA_INT_i_1_n_0)); FDRE XMIT_DATA_INT_reg (.C(userclk2), .CE(1'b1), .D(XMIT_DATA_INT_i_1_n_0), .Q(XMIT_DATA_INT_reg_n_0), .R(\NO_QSGMII_DATA.TXDATA_reg[4]_0 )); endmodule (* B_SHIFTER_ADDR = "10'b0101001110" *) (* C_1588 = "0" *) (* C_2_5G = "FALSE" *) (* C_COMPONENT_NAME = "gig_ethernet_pcs_pma_16_1" *) (* C_DYNAMIC_SWITCHING = "FALSE" *) (* C_ELABORATION_TRANSIENT_DIR = "BlankString" *) (* C_FAMILY = "kintex7" *) (* C_HAS_AN = "FALSE" *) (* C_HAS_AXIL = "FALSE" *) (* C_HAS_MDIO = "FALSE" *) (* C_HAS_TEMAC = "TRUE" *) (* C_IS_SGMII = "FALSE" *) (* C_RX_GMII_CLK = "TXOUTCLK" *) (* C_SGMII_FABRIC_BUFFER = "TRUE" *) (* C_SGMII_PHY_MODE = "FALSE" *) (* C_USE_LVDS = "FALSE" *) (* C_USE_TBI = "FALSE" *) (* C_USE_TRANSCEIVER = "TRUE" *) (* GT_RX_BYTE_WIDTH = "1" *) (* downgradeipidentifiedwarnings = "yes" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_gig_ethernet_pcs_pma_v16_1_5 (reset, signal_detect, link_timer_value, link_timer_basex, link_timer_sgmii, rx_gt_nominal_latency, speed_is_10_100, speed_is_100, mgt_rx_reset, mgt_tx_reset, userclk, userclk2, dcm_locked, rxbufstatus, rxchariscomma, rxcharisk, rxclkcorcnt, rxdata, rxdisperr, rxnotintable, rxrundisp, txbuferr, powerdown, txchardispmode, txchardispval, txcharisk, txdata, enablealign, gtx_clk, tx_code_group, loc_ref, ewrap, rx_code_group0, rx_code_group1, pma_rx_clk0, pma_rx_clk1, en_cdet, gmii_txd, gmii_tx_en, gmii_tx_er, gmii_rxd, gmii_rx_dv, gmii_rx_er, gmii_isolate, an_interrupt, an_enable, speed_selection, phyad, mdc, mdio_in, mdio_out, mdio_tri, an_adv_config_vector, an_adv_config_val, an_restart_config, configuration_vector, configuration_valid, status_vector, basex_or_sgmii, drp_dclk, drp_req, drp_gnt, drp_den, drp_dwe, drp_drdy, drp_daddr, drp_di, drp_do, systemtimer_s_field, systemtimer_ns_field, correction_timer, rxrecclk, rxphy_s_field, rxphy_ns_field, rxphy_correction_timer, s_axi_aclk, s_axi_resetn, s_axi_awaddr, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wvalid, s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, reset_done); input reset; input signal_detect; input [9:0]link_timer_value; input [9:0]link_timer_basex; input [9:0]link_timer_sgmii; input [15:0]rx_gt_nominal_latency; input speed_is_10_100; input speed_is_100; output mgt_rx_reset; output mgt_tx_reset; input userclk; input userclk2; input dcm_locked; input [1:0]rxbufstatus; input [0:0]rxchariscomma; input [0:0]rxcharisk; input [2:0]rxclkcorcnt; input [7:0]rxdata; input [0:0]rxdisperr; input [0:0]rxnotintable; input [0:0]rxrundisp; input txbuferr; output powerdown; output txchardispmode; output txchardispval; output txcharisk; output [7:0]txdata; output enablealign; input gtx_clk; output [9:0]tx_code_group; output loc_ref; output ewrap; input [9:0]rx_code_group0; input [9:0]rx_code_group1; input pma_rx_clk0; input pma_rx_clk1; output en_cdet; input [7:0]gmii_txd; input gmii_tx_en; input gmii_tx_er; output [7:0]gmii_rxd; output gmii_rx_dv; output gmii_rx_er; output gmii_isolate; output an_interrupt; output an_enable; output [1:0]speed_selection; input [4:0]phyad; input mdc; input mdio_in; output mdio_out; output mdio_tri; input [15:0]an_adv_config_vector; input an_adv_config_val; input an_restart_config; input [4:0]configuration_vector; input configuration_valid; output [15:0]status_vector; input basex_or_sgmii; input drp_dclk; output drp_req; input drp_gnt; output drp_den; output drp_dwe; input drp_drdy; output [9:0]drp_daddr; output [15:0]drp_di; input [15:0]drp_do; input [47:0]systemtimer_s_field; input [31:0]systemtimer_ns_field; input [63:0]correction_timer; input rxrecclk; output [47:0]rxphy_s_field; output [31:0]rxphy_ns_field; output [63:0]rxphy_correction_timer; input s_axi_aclk; input s_axi_resetn; input [31:0]s_axi_awaddr; input s_axi_awvalid; output s_axi_awready; input [31:0]s_axi_wdata; input s_axi_wvalid; output s_axi_wready; output [1:0]s_axi_bresp; output s_axi_bvalid; input s_axi_bready; input [31:0]s_axi_araddr; input s_axi_arvalid; output s_axi_arready; output [31:0]s_axi_rdata; output [1:0]s_axi_rresp; output s_axi_rvalid; input s_axi_rready; input reset_done; wire \ ; wire [4:0]configuration_vector; wire dcm_locked; wire enablealign; wire gmii_isolate; wire gmii_rx_dv; wire gmii_rx_er; wire [7:0]gmii_rxd; wire gmii_tx_en; wire gmii_tx_er; wire [7:0]gmii_txd; wire mgt_rx_reset; wire mgt_tx_reset; wire powerdown; wire reset; wire reset_done; wire [1:0]rxbufstatus; wire [0:0]rxchariscomma; wire [0:0]rxcharisk; wire [2:0]rxclkcorcnt; wire [7:0]rxdata; wire [0:0]rxdisperr; wire [0:0]rxnotintable; wire signal_detect; wire [6:0]\^status_vector ; wire txbuferr; wire txchardispmode; wire txchardispval; wire txcharisk; wire [7:0]txdata; wire userclk2; assign an_enable = \ ; assign an_interrupt = \ ; assign drp_daddr[9] = \ ; assign drp_daddr[8] = \ ; assign drp_daddr[7] = \ ; assign drp_daddr[6] = \ ; assign drp_daddr[5] = \ ; assign drp_daddr[4] = \ ; assign drp_daddr[3] = \ ; assign drp_daddr[2] = \ ; assign drp_daddr[1] = \ ; assign drp_daddr[0] = \ ; assign drp_den = \ ; assign drp_di[15] = \ ; assign drp_di[14] = \ ; assign drp_di[13] = \ ; assign drp_di[12] = \ ; assign drp_di[11] = \ ; assign drp_di[10] = \ ; assign drp_di[9] = \ ; assign drp_di[8] = \ ; assign drp_di[7] = \ ; assign drp_di[6] = \ ; assign drp_di[5] = \ ; assign drp_di[4] = \ ; assign drp_di[3] = \ ; assign drp_di[2] = \ ; assign drp_di[1] = \ ; assign drp_di[0] = \ ; assign drp_dwe = \ ; assign drp_req = \ ; assign en_cdet = \ ; assign ewrap = \ ; assign loc_ref = \ ; assign mdio_out = \ ; assign mdio_tri = \ ; assign rxphy_correction_timer[63] = \ ; assign rxphy_correction_timer[62] = \ ; assign rxphy_correction_timer[61] = \ ; assign rxphy_correction_timer[60] = \ ; assign rxphy_correction_timer[59] = \ ; assign rxphy_correction_timer[58] = \ ; assign rxphy_correction_timer[57] = \ ; assign rxphy_correction_timer[56] = \ ; assign rxphy_correction_timer[55] = \ ; assign rxphy_correction_timer[54] = \ ; assign rxphy_correction_timer[53] = \ ; assign rxphy_correction_timer[52] = \ ; assign rxphy_correction_timer[51] = \ ; assign rxphy_correction_timer[50] = \ ; assign rxphy_correction_timer[49] = \ ; assign rxphy_correction_timer[48] = \ ; assign rxphy_correction_timer[47] = \ ; assign rxphy_correction_timer[46] = \ ; assign rxphy_correction_timer[45] = \ ; assign rxphy_correction_timer[44] = \ ; assign rxphy_correction_timer[43] = \ ; assign rxphy_correction_timer[42] = \ ; assign rxphy_correction_timer[41] = \ ; assign rxphy_correction_timer[40] = \ ; assign rxphy_correction_timer[39] = \ ; assign rxphy_correction_timer[38] = \ ; assign rxphy_correction_timer[37] = \ ; assign rxphy_correction_timer[36] = \ ; assign rxphy_correction_timer[35] = \ ; assign rxphy_correction_timer[34] = \ ; assign rxphy_correction_timer[33] = \ ; assign rxphy_correction_timer[32] = \ ; assign rxphy_correction_timer[31] = \ ; assign rxphy_correction_timer[30] = \ ; assign rxphy_correction_timer[29] = \ ; assign rxphy_correction_timer[28] = \ ; assign rxphy_correction_timer[27] = \ ; assign rxphy_correction_timer[26] = \ ; assign rxphy_correction_timer[25] = \ ; assign rxphy_correction_timer[24] = \ ; assign rxphy_correction_timer[23] = \ ; assign rxphy_correction_timer[22] = \ ; assign rxphy_correction_timer[21] = \ ; assign rxphy_correction_timer[20] = \ ; assign rxphy_correction_timer[19] = \ ; assign rxphy_correction_timer[18] = \ ; assign rxphy_correction_timer[17] = \ ; assign rxphy_correction_timer[16] = \ ; assign rxphy_correction_timer[15] = \ ; assign rxphy_correction_timer[14] = \ ; assign rxphy_correction_timer[13] = \ ; assign rxphy_correction_timer[12] = \ ; assign rxphy_correction_timer[11] = \ ; assign rxphy_correction_timer[10] = \ ; assign rxphy_correction_timer[9] = \ ; assign rxphy_correction_timer[8] = \ ; assign rxphy_correction_timer[7] = \ ; assign rxphy_correction_timer[6] = \ ; assign rxphy_correction_timer[5] = \ ; assign rxphy_correction_timer[4] = \ ; assign rxphy_correction_timer[3] = \ ; assign rxphy_correction_timer[2] = \ ; assign rxphy_correction_timer[1] = \ ; assign rxphy_correction_timer[0] = \ ; assign rxphy_ns_field[31] = \ ; assign rxphy_ns_field[30] = \ ; assign rxphy_ns_field[29] = \ ; assign rxphy_ns_field[28] = \ ; assign rxphy_ns_field[27] = \ ; assign rxphy_ns_field[26] = \ ; assign rxphy_ns_field[25] = \ ; assign rxphy_ns_field[24] = \ ; assign rxphy_ns_field[23] = \ ; assign rxphy_ns_field[22] = \ ; assign rxphy_ns_field[21] = \ ; assign rxphy_ns_field[20] = \ ; assign rxphy_ns_field[19] = \ ; assign rxphy_ns_field[18] = \ ; assign rxphy_ns_field[17] = \ ; assign rxphy_ns_field[16] = \ ; assign rxphy_ns_field[15] = \ ; assign rxphy_ns_field[14] = \ ; assign rxphy_ns_field[13] = \ ; assign rxphy_ns_field[12] = \ ; assign rxphy_ns_field[11] = \ ; assign rxphy_ns_field[10] = \ ; assign rxphy_ns_field[9] = \ ; assign rxphy_ns_field[8] = \ ; assign rxphy_ns_field[7] = \ ; assign rxphy_ns_field[6] = \ ; assign rxphy_ns_field[5] = \ ; assign rxphy_ns_field[4] = \ ; assign rxphy_ns_field[3] = \ ; assign rxphy_ns_field[2] = \ ; assign rxphy_ns_field[1] = \ ; assign rxphy_ns_field[0] = \ ; assign rxphy_s_field[47] = \ ; assign rxphy_s_field[46] = \ ; assign rxphy_s_field[45] = \ ; assign rxphy_s_field[44] = \ ; assign rxphy_s_field[43] = \ ; assign rxphy_s_field[42] = \ ; assign rxphy_s_field[41] = \ ; assign rxphy_s_field[40] = \ ; assign rxphy_s_field[39] = \ ; assign rxphy_s_field[38] = \ ; assign rxphy_s_field[37] = \ ; assign rxphy_s_field[36] = \ ; assign rxphy_s_field[35] = \ ; assign rxphy_s_field[34] = \ ; assign rxphy_s_field[33] = \ ; assign rxphy_s_field[32] = \ ; assign rxphy_s_field[31] = \ ; assign rxphy_s_field[30] = \ ; assign rxphy_s_field[29] = \ ; assign rxphy_s_field[28] = \ ; assign rxphy_s_field[27] = \ ; assign rxphy_s_field[26] = \ ; assign rxphy_s_field[25] = \ ; assign rxphy_s_field[24] = \ ; assign rxphy_s_field[23] = \ ; assign rxphy_s_field[22] = \ ; assign rxphy_s_field[21] = \ ; assign rxphy_s_field[20] = \ ; assign rxphy_s_field[19] = \ ; assign rxphy_s_field[18] = \ ; assign rxphy_s_field[17] = \ ; assign rxphy_s_field[16] = \ ; assign rxphy_s_field[15] = \ ; assign rxphy_s_field[14] = \ ; assign rxphy_s_field[13] = \ ; assign rxphy_s_field[12] = \ ; assign rxphy_s_field[11] = \ ; assign rxphy_s_field[10] = \ ; assign rxphy_s_field[9] = \ ; assign rxphy_s_field[8] = \ ; assign rxphy_s_field[7] = \ ; assign rxphy_s_field[6] = \ ; assign rxphy_s_field[5] = \ ; assign rxphy_s_field[4] = \ ; assign rxphy_s_field[3] = \ ; assign rxphy_s_field[2] = \ ; assign rxphy_s_field[1] = \ ; assign rxphy_s_field[0] = \ ; assign s_axi_arready = \ ; assign s_axi_awready = \ ; assign s_axi_bresp[1] = \ ; assign s_axi_bresp[0] = \ ; assign s_axi_bvalid = \ ; assign s_axi_rdata[31] = \ ; assign s_axi_rdata[30] = \ ; assign s_axi_rdata[29] = \ ; assign s_axi_rdata[28] = \ ; assign s_axi_rdata[27] = \ ; assign s_axi_rdata[26] = \ ; assign s_axi_rdata[25] = \ ; assign s_axi_rdata[24] = \ ; assign s_axi_rdata[23] = \ ; assign s_axi_rdata[22] = \ ; assign s_axi_rdata[21] = \ ; assign s_axi_rdata[20] = \ ; assign s_axi_rdata[19] = \ ; assign s_axi_rdata[18] = \ ; assign s_axi_rdata[17] = \ ; assign s_axi_rdata[16] = \ ; assign s_axi_rdata[15] = \ ; assign s_axi_rdata[14] = \ ; assign s_axi_rdata[13] = \ ; assign s_axi_rdata[12] = \ ; assign s_axi_rdata[11] = \ ; assign s_axi_rdata[10] = \ ; assign s_axi_rdata[9] = \ ; assign s_axi_rdata[8] = \ ; assign s_axi_rdata[7] = \ ; assign s_axi_rdata[6] = \ ; assign s_axi_rdata[5] = \ ; assign s_axi_rdata[4] = \ ; assign s_axi_rdata[3] = \ ; assign s_axi_rdata[2] = \ ; assign s_axi_rdata[1] = \ ; assign s_axi_rdata[0] = \ ; assign s_axi_rresp[1] = \ ; assign s_axi_rresp[0] = \ ; assign s_axi_rvalid = \ ; assign s_axi_wready = \ ; assign speed_selection[1] = \ ; assign speed_selection[0] = \ ; assign status_vector[15] = \ ; assign status_vector[14] = \ ; assign status_vector[13] = \ ; assign status_vector[12] = \ ; assign status_vector[11] = \ ; assign status_vector[10] = \ ; assign status_vector[9] = \ ; assign status_vector[8] = \ ; assign status_vector[7] = \ ; assign status_vector[6:0] = \^status_vector [6:0]; assign tx_code_group[9] = \ ; assign tx_code_group[8] = \ ; assign tx_code_group[7] = \ ; assign tx_code_group[6] = \ ; assign tx_code_group[5] = \ ; assign tx_code_group[4] = \ ; assign tx_code_group[3] = \ ; assign tx_code_group[2] = \ ; assign tx_code_group[1] = \ ; assign tx_code_group[0] = \ ; GND GND (.G(\ )); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPCS_PMA_GEN gpcs_pma_inst (.MGT_RX_RESET(mgt_rx_reset), .MGT_TX_RESET(mgt_tx_reset), .\NO_MANAGEMENT.CONFIGURATION_VECTOR_REG_reg[2]_0 (powerdown), .\NO_MANAGEMENT.CONFIGURATION_VECTOR_REG_reg[3]_0 (gmii_isolate), .configuration_vector(configuration_vector[3:1]), .dcm_locked(dcm_locked), .enablealign(enablealign), .gmii_rx_dv(gmii_rx_dv), .gmii_rx_er(gmii_rx_er), .gmii_rxd(gmii_rxd), .gmii_tx_en(gmii_tx_en), .gmii_tx_er(gmii_tx_er), .gmii_txd(gmii_txd), .reset(reset), .reset_done(reset_done), .rxbufstatus(rxbufstatus[1]), .rxchariscomma(rxchariscomma), .rxcharisk(rxcharisk), .rxclkcorcnt(rxclkcorcnt[1:0]), .rxdata(rxdata), .rxdisperr(rxdisperr), .rxnotintable(rxnotintable), .signal_detect(signal_detect), .status_vector(\^status_vector ), .txbuferr(txbuferr), .txchardispmode(txchardispmode), .txchardispval(txchardispval), .txcharisk(txcharisk), .txdata(txdata), .userclk2(userclk2)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_sync_block (reset_sync6_0, dcm_locked, userclk2, reset); output reset_sync6_0; input dcm_locked; input userclk2; input reset; wire dcm_locked; wire reset; wire reset_out; wire reset_sync6_0; wire reset_sync_reg1; wire reset_sync_reg2; wire reset_sync_reg3; wire reset_sync_reg4; wire reset_sync_reg5; wire userclk2; LUT2 #( .INIT(4'hB)) \MGT_RESET.RESET_INT_PIPE_i_1 (.I0(reset_out), .I1(dcm_locked), .O(reset_sync6_0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync1 (.C(userclk2), .CE(1'b1), .D(1'b0), .PRE(reset), .Q(reset_sync_reg1)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync2 (.C(userclk2), .CE(1'b1), .D(reset_sync_reg1), .PRE(reset), .Q(reset_sync_reg2)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync3 (.C(userclk2), .CE(1'b1), .D(reset_sync_reg2), .PRE(reset), .Q(reset_sync_reg3)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync4 (.C(userclk2), .CE(1'b1), .D(reset_sync_reg3), .PRE(reset), .Q(reset_sync_reg4)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync5 (.C(userclk2), .CE(1'b1), .D(reset_sync_reg4), .PRE(reset), .Q(reset_sync_reg5)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync6 (.C(userclk2), .CE(1'b1), .D(reset_sync_reg5), .PRE(1'b0), .Q(reset_out)); endmodule (* ORIG_REF_NAME = "reset_sync_block" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_sync_block_17 (p_6_out, dcm_locked, reset_out, reset); output p_6_out; input dcm_locked; input reset_out; input reset; wire RESET_REG_RXRECCLK; wire dcm_locked; wire p_6_out; wire reset; wire reset_out; wire reset_sync_reg1; wire reset_sync_reg2; wire reset_sync_reg3; wire reset_sync_reg4; wire reset_sync_reg5; LUT3 #( .INIT(8'hFD)) \MGT_RESET.RESET_INT_PIPE_RXRECCLK_i_1 (.I0(dcm_locked), .I1(RESET_REG_RXRECCLK), .I2(reset_out), .O(p_6_out)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync1 (.C(1'b0), .CE(1'b1), .D(1'b0), .PRE(reset), .Q(reset_sync_reg1)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync2 (.C(1'b0), .CE(1'b1), .D(reset_sync_reg1), .PRE(reset), .Q(reset_sync_reg2)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync3 (.C(1'b0), .CE(1'b1), .D(reset_sync_reg2), .PRE(reset), .Q(reset_sync_reg3)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync4 (.C(1'b0), .CE(1'b1), .D(reset_sync_reg3), .PRE(reset), .Q(reset_sync_reg4)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync5 (.C(1'b0), .CE(1'b1), .D(reset_sync_reg4), .PRE(reset), .Q(reset_sync_reg5)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync6 (.C(1'b0), .CE(1'b1), .D(reset_sync_reg5), .PRE(1'b0), .Q(RESET_REG_RXRECCLK)); endmodule (* ORIG_REF_NAME = "reset_sync_block" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_sync_block_18 (reset_out); output reset_out; wire reset_out; wire reset_sync_reg1; wire reset_sync_reg2; wire reset_sync_reg3; wire reset_sync_reg4; wire reset_sync_reg5; (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync1 (.C(1'b0), .CE(1'b1), .D(1'b0), .PRE(1'b0), .Q(reset_sync_reg1)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync2 (.C(1'b0), .CE(1'b1), .D(reset_sync_reg1), .PRE(1'b0), .Q(reset_sync_reg2)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync3 (.C(1'b0), .CE(1'b1), .D(reset_sync_reg2), .PRE(1'b0), .Q(reset_sync_reg3)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync4 (.C(1'b0), .CE(1'b1), .D(reset_sync_reg3), .PRE(1'b0), .Q(reset_sync_reg4)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync5 (.C(1'b0), .CE(1'b1), .D(reset_sync_reg4), .PRE(1'b0), .Q(reset_sync_reg5)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FDP" *) (* box_type = "PRIMITIVE" *) FDPE #( .INIT(1'b1)) reset_sync6 (.C(1'b0), .CE(1'b1), .D(reset_sync_reg5), .PRE(1'b0), .Q(reset_out)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sync_block (SIGNAL_DETECT_MOD, SIGNAL_DETECT_REG_reg, signal_detect, userclk2); output SIGNAL_DETECT_MOD; input SIGNAL_DETECT_REG_reg; input signal_detect; input userclk2; wire SIGNAL_DETECT_MOD; wire SIGNAL_DETECT_REG_reg; wire data_out; wire data_sync1; wire data_sync2; wire data_sync3; wire data_sync4; wire data_sync5; wire signal_detect; wire userclk2; LUT2 #( .INIT(4'h2)) SIGNAL_DETECT_REG_i_1 (.I0(data_out), .I1(SIGNAL_DETECT_REG_reg), .O(SIGNAL_DETECT_MOD)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg1 (.C(userclk2), .CE(1'b1), .D(signal_detect), .Q(data_sync1), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg2 (.C(userclk2), .CE(1'b1), .D(data_sync1), .Q(data_sync2), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg3 (.C(userclk2), .CE(1'b1), .D(data_sync2), .Q(data_sync3), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg4 (.C(userclk2), .CE(1'b1), .D(data_sync3), .Q(data_sync4), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg5 (.C(userclk2), .CE(1'b1), .D(data_sync4), .Q(data_sync5), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg6 (.C(userclk2), .CE(1'b1), .D(data_sync5), .Q(data_out), .R(1'b0)); endmodule `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (strong1, weak0) GSR = GSR_int; assign (strong1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif