-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -- Date : Mon Mar 23 14:57:50 2020 -- Host : baby running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ aurora_64b66b_0_sim_netlist.vhdl -- Design : aurora_64b66b_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7k420tffg1156-2 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_BLOCK_SYNC_SM is port ( D : out STD_LOGIC_VECTOR ( 0 to 0 ); blocksync_out_i : out STD_LOGIC; SR : in STD_LOGIC_VECTOR ( 0 to 0 ); \out\ : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); rxheadervalid_i : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_BLOCK_SYNC_SM; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_BLOCK_SYNC_SM is signal BLOCKSYNC_OUT_i_1_n_0 : STD_LOGIC; signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal RXGEARBOXSLIP_OUT_i_2_n_0 : STD_LOGIC; signal RXGEARBOXSLIP_OUT_i_3_n_0 : STD_LOGIC; signal RXGEARBOXSLIP_OUT_i_4_n_0 : STD_LOGIC; signal RXGEARBOXSLIP_OUT_i_5_n_0 : STD_LOGIC; signal RXGEARBOXSLIP_OUT_i_6_n_0 : STD_LOGIC; signal begin_r : STD_LOGIC; signal \begin_r_i_2__0_n_0\ : STD_LOGIC; signal \^blocksync_out_i\ : STD_LOGIC; signal next_begin_c : STD_LOGIC; signal next_sh_invalid_c : STD_LOGIC; signal next_sh_valid_c : STD_LOGIC; signal next_slip_c : STD_LOGIC; signal next_sync_done_c : STD_LOGIC; signal next_test_sh_c : STD_LOGIC; signal \p_0_in__5\ : STD_LOGIC_VECTOR ( 9 downto 0 ); signal p_1_in : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \sh_count_equals_max_i__14\ : STD_LOGIC; signal \sh_invalid_cnt_equals_zero_i__4\ : STD_LOGIC; signal sh_valid_r_i_2_n_0 : STD_LOGIC; signal \slip_count_i[15]_i_1_n_0\ : STD_LOGIC; signal \slip_count_i_reg_n_0_[0]\ : STD_LOGIC; signal \slip_count_i_reg_n_0_[10]\ : STD_LOGIC; signal \slip_count_i_reg_n_0_[11]\ : STD_LOGIC; signal \slip_count_i_reg_n_0_[12]\ : STD_LOGIC; signal \slip_count_i_reg_n_0_[13]\ : STD_LOGIC; signal \slip_count_i_reg_n_0_[14]\ : STD_LOGIC; signal \slip_count_i_reg_n_0_[1]\ : STD_LOGIC; signal \slip_count_i_reg_n_0_[2]\ : STD_LOGIC; signal \slip_count_i_reg_n_0_[3]\ : STD_LOGIC; signal \slip_count_i_reg_n_0_[4]\ : STD_LOGIC; signal \slip_count_i_reg_n_0_[5]\ : STD_LOGIC; signal \slip_count_i_reg_n_0_[6]\ : STD_LOGIC; signal \slip_count_i_reg_n_0_[7]\ : STD_LOGIC; signal \slip_count_i_reg_n_0_[8]\ : STD_LOGIC; signal \slip_count_i_reg_n_0_[9]\ : STD_LOGIC; signal slip_done_i : STD_LOGIC; signal slip_pulse_i : STD_LOGIC; signal slip_r_i_2_n_0 : STD_LOGIC; signal sync_done_r : STD_LOGIC; signal sync_done_r_i_3_n_0 : STD_LOGIC; signal sync_done_r_i_5_n_0 : STD_LOGIC; signal sync_done_r_i_6_n_0 : STD_LOGIC; signal sync_done_r_i_7_n_0 : STD_LOGIC; signal sync_done_r_i_8_n_0 : STD_LOGIC; signal sync_done_r_i_9_n_0 : STD_LOGIC; signal sync_header_count_i0 : STD_LOGIC; signal \sync_header_count_i[0]_i_3_n_0\ : STD_LOGIC; signal sync_header_count_i_reg : STD_LOGIC_VECTOR ( 15 downto 0 ); signal \sync_header_count_i_reg[0]_i_2_n_0\ : STD_LOGIC; signal \sync_header_count_i_reg[0]_i_2_n_1\ : STD_LOGIC; signal \sync_header_count_i_reg[0]_i_2_n_2\ : STD_LOGIC; signal \sync_header_count_i_reg[0]_i_2_n_3\ : STD_LOGIC; signal \sync_header_count_i_reg[0]_i_2_n_4\ : STD_LOGIC; signal \sync_header_count_i_reg[0]_i_2_n_5\ : STD_LOGIC; signal \sync_header_count_i_reg[0]_i_2_n_6\ : STD_LOGIC; signal \sync_header_count_i_reg[0]_i_2_n_7\ : STD_LOGIC; signal \sync_header_count_i_reg[12]_i_1_n_1\ : STD_LOGIC; signal \sync_header_count_i_reg[12]_i_1_n_2\ : STD_LOGIC; signal \sync_header_count_i_reg[12]_i_1_n_3\ : STD_LOGIC; signal \sync_header_count_i_reg[12]_i_1_n_4\ : STD_LOGIC; signal \sync_header_count_i_reg[12]_i_1_n_5\ : STD_LOGIC; signal \sync_header_count_i_reg[12]_i_1_n_6\ : STD_LOGIC; signal \sync_header_count_i_reg[12]_i_1_n_7\ : STD_LOGIC; signal \sync_header_count_i_reg[4]_i_1_n_0\ : STD_LOGIC; signal \sync_header_count_i_reg[4]_i_1_n_1\ : STD_LOGIC; signal \sync_header_count_i_reg[4]_i_1_n_2\ : STD_LOGIC; signal \sync_header_count_i_reg[4]_i_1_n_3\ : STD_LOGIC; signal \sync_header_count_i_reg[4]_i_1_n_4\ : STD_LOGIC; signal \sync_header_count_i_reg[4]_i_1_n_5\ : STD_LOGIC; signal \sync_header_count_i_reg[4]_i_1_n_6\ : STD_LOGIC; signal \sync_header_count_i_reg[4]_i_1_n_7\ : STD_LOGIC; signal \sync_header_count_i_reg[8]_i_1_n_0\ : STD_LOGIC; signal \sync_header_count_i_reg[8]_i_1_n_1\ : STD_LOGIC; signal \sync_header_count_i_reg[8]_i_1_n_2\ : STD_LOGIC; signal \sync_header_count_i_reg[8]_i_1_n_3\ : STD_LOGIC; signal \sync_header_count_i_reg[8]_i_1_n_4\ : STD_LOGIC; signal \sync_header_count_i_reg[8]_i_1_n_5\ : STD_LOGIC; signal \sync_header_count_i_reg[8]_i_1_n_6\ : STD_LOGIC; signal \sync_header_count_i_reg[8]_i_1_n_7\ : STD_LOGIC; signal \sync_header_invalid_count_i[9]_i_2_n_0\ : STD_LOGIC; signal \sync_header_invalid_count_i_reg__0\ : STD_LOGIC_VECTOR ( 9 downto 0 ); signal system_reset_r : STD_LOGIC; signal system_reset_r2 : STD_LOGIC; signal test_sh_r : STD_LOGIC; signal test_sh_r_i_2_n_0 : STD_LOGIC; signal \NLW_sync_header_count_i_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of RXGEARBOXSLIP_OUT_i_2 : label is "soft_lutpair3"; attribute SOFT_HLUTNM of RXGEARBOXSLIP_OUT_i_6 : label is "soft_lutpair0"; attribute SOFT_HLUTNM of sync_done_r_i_2 : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \sync_header_invalid_count_i[1]_i_1\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of \sync_header_invalid_count_i[2]_i_1\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of \sync_header_invalid_count_i[3]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \sync_header_invalid_count_i[4]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \sync_header_invalid_count_i[6]_i_1\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \sync_header_invalid_count_i[7]_i_1\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \sync_header_invalid_count_i[8]_i_1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \sync_header_invalid_count_i[9]_i_1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of test_sh_r_i_2 : label is "soft_lutpair3"; begin D(0) <= \^d\(0); blocksync_out_i <= \^blocksync_out_i\; BLOCKSYNC_OUT_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"1110" ) port map ( I0 => p_1_in(1), I1 => system_reset_r2, I2 => \^blocksync_out_i\, I3 => sync_done_r, O => BLOCKSYNC_OUT_i_1_n_0 ); BLOCKSYNC_OUT_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => BLOCKSYNC_OUT_i_1_n_0, Q => \^blocksync_out_i\, R => '0' ); RXGEARBOXSLIP_OUT_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAA20000000" ) port map ( I0 => RXGEARBOXSLIP_OUT_i_2_n_0, I1 => \sh_invalid_cnt_equals_zero_i__4\, I2 => RXGEARBOXSLIP_OUT_i_3_n_0, I3 => p_1_in(3), I4 => \sh_count_equals_max_i__14\, I5 => RXGEARBOXSLIP_OUT_i_4_n_0, O => slip_pulse_i ); RXGEARBOXSLIP_OUT_i_2: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => slip_r_i_2_n_0, I1 => p_1_in(1), O => RXGEARBOXSLIP_OUT_i_2_n_0 ); RXGEARBOXSLIP_OUT_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"00010000FFFFFFFF" ) port map ( I0 => \sync_header_invalid_count_i_reg__0\(1), I1 => \sync_header_invalid_count_i_reg__0\(0), I2 => \sync_header_invalid_count_i_reg__0\(3), I3 => \sync_header_invalid_count_i_reg__0\(2), I4 => RXGEARBOXSLIP_OUT_i_5_n_0, I5 => \^blocksync_out_i\, O => RXGEARBOXSLIP_OUT_i_3_n_0 ); RXGEARBOXSLIP_OUT_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"80AAFFFF80AA80AA" ) port map ( I0 => p_1_in(2), I1 => RXGEARBOXSLIP_OUT_i_6_n_0, I2 => RXGEARBOXSLIP_OUT_i_5_n_0, I3 => \^blocksync_out_i\, I4 => slip_done_i, I5 => p_1_in(1), O => RXGEARBOXSLIP_OUT_i_4_n_0 ); RXGEARBOXSLIP_OUT_i_5: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000002" ) port map ( I0 => \sync_header_invalid_count_i_reg__0\(4), I1 => \sync_header_invalid_count_i_reg__0\(5), I2 => \sync_header_invalid_count_i_reg__0\(6), I3 => \sync_header_invalid_count_i_reg__0\(7), I4 => \sync_header_invalid_count_i_reg__0\(9), I5 => \sync_header_invalid_count_i_reg__0\(8), O => RXGEARBOXSLIP_OUT_i_5_n_0 ); RXGEARBOXSLIP_OUT_i_6: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => \sync_header_invalid_count_i_reg__0\(1), I1 => \sync_header_invalid_count_i_reg__0\(0), I2 => \sync_header_invalid_count_i_reg__0\(3), I3 => \sync_header_invalid_count_i_reg__0\(2), O => RXGEARBOXSLIP_OUT_i_6_n_0 ); RXGEARBOXSLIP_OUT_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => slip_pulse_i, Q => \^d\(0), R => '0' ); \begin_r_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAAFFBAAAAA" ) port map ( I0 => \begin_r_i_2__0_n_0\, I1 => \sh_invalid_cnt_equals_zero_i__4\, I2 => p_1_in(3), I3 => p_1_in(2), I4 => \sh_count_equals_max_i__14\, I5 => RXGEARBOXSLIP_OUT_i_3_n_0, O => next_begin_c ); \begin_r_i_2__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FDDD" ) port map ( I0 => slip_r_i_2_n_0, I1 => sync_done_r, I2 => slip_done_i, I3 => p_1_in(1), O => \begin_r_i_2__0_n_0\ ); begin_r_reg: unisim.vcomponents.FDSE port map ( C => \out\, CE => '1', D => next_begin_c, Q => begin_r, S => system_reset_r2 ); sh_invalid_r_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000900000" ) port map ( I0 => Q(1), I1 => Q(0), I2 => sh_valid_r_i_2_n_0, I3 => sync_done_r, I4 => test_sh_r, I5 => p_1_in(1), O => next_sh_invalid_c ); sh_invalid_r_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => next_sh_invalid_c, Q => p_1_in(2), R => system_reset_r2 ); sh_valid_r_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000600000" ) port map ( I0 => Q(1), I1 => Q(0), I2 => sh_valid_r_i_2_n_0, I3 => sync_done_r, I4 => test_sh_r, I5 => p_1_in(1), O => next_sh_valid_c ); sh_valid_r_i_2: unisim.vcomponents.LUT4 generic map( INIT => X"0004" ) port map ( I0 => begin_r, I1 => rxheadervalid_i, I2 => p_1_in(2), I3 => p_1_in(3), O => sh_valid_r_i_2_n_0 ); sh_valid_r_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => next_sh_valid_c, Q => p_1_in(3), R => system_reset_r2 ); \slip_count_i[15]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => p_1_in(1), O => \slip_count_i[15]_i_1_n_0\ ); \slip_count_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \^d\(0), Q => \slip_count_i_reg_n_0_[0]\, R => \slip_count_i[15]_i_1_n_0\ ); \slip_count_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \slip_count_i_reg_n_0_[9]\, Q => \slip_count_i_reg_n_0_[10]\, R => \slip_count_i[15]_i_1_n_0\ ); \slip_count_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \slip_count_i_reg_n_0_[10]\, Q => \slip_count_i_reg_n_0_[11]\, R => \slip_count_i[15]_i_1_n_0\ ); \slip_count_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \slip_count_i_reg_n_0_[11]\, Q => \slip_count_i_reg_n_0_[12]\, R => \slip_count_i[15]_i_1_n_0\ ); \slip_count_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \slip_count_i_reg_n_0_[12]\, Q => \slip_count_i_reg_n_0_[13]\, R => \slip_count_i[15]_i_1_n_0\ ); \slip_count_i_reg[14]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \slip_count_i_reg_n_0_[13]\, Q => \slip_count_i_reg_n_0_[14]\, R => \slip_count_i[15]_i_1_n_0\ ); \slip_count_i_reg[15]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \slip_count_i_reg_n_0_[14]\, Q => slip_done_i, R => \slip_count_i[15]_i_1_n_0\ ); \slip_count_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \slip_count_i_reg_n_0_[0]\, Q => \slip_count_i_reg_n_0_[1]\, R => \slip_count_i[15]_i_1_n_0\ ); \slip_count_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \slip_count_i_reg_n_0_[1]\, Q => \slip_count_i_reg_n_0_[2]\, R => \slip_count_i[15]_i_1_n_0\ ); \slip_count_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \slip_count_i_reg_n_0_[2]\, Q => \slip_count_i_reg_n_0_[3]\, R => \slip_count_i[15]_i_1_n_0\ ); \slip_count_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \slip_count_i_reg_n_0_[3]\, Q => \slip_count_i_reg_n_0_[4]\, R => \slip_count_i[15]_i_1_n_0\ ); \slip_count_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \slip_count_i_reg_n_0_[4]\, Q => \slip_count_i_reg_n_0_[5]\, R => \slip_count_i[15]_i_1_n_0\ ); \slip_count_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \slip_count_i_reg_n_0_[5]\, Q => \slip_count_i_reg_n_0_[6]\, R => \slip_count_i[15]_i_1_n_0\ ); \slip_count_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \slip_count_i_reg_n_0_[6]\, Q => \slip_count_i_reg_n_0_[7]\, R => \slip_count_i[15]_i_1_n_0\ ); \slip_count_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \slip_count_i_reg_n_0_[7]\, Q => \slip_count_i_reg_n_0_[8]\, R => \slip_count_i[15]_i_1_n_0\ ); \slip_count_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \slip_count_i_reg_n_0_[8]\, Q => \slip_count_i_reg_n_0_[9]\, R => \slip_count_i[15]_i_1_n_0\ ); slip_r_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAA20000000" ) port map ( I0 => slip_r_i_2_n_0, I1 => \sh_invalid_cnt_equals_zero_i__4\, I2 => RXGEARBOXSLIP_OUT_i_3_n_0, I3 => p_1_in(3), I4 => \sh_count_equals_max_i__14\, I5 => RXGEARBOXSLIP_OUT_i_4_n_0, O => next_slip_c ); slip_r_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000000100010116" ) port map ( I0 => sync_done_r, I1 => p_1_in(1), I2 => p_1_in(2), I3 => p_1_in(3), I4 => test_sh_r, I5 => begin_r, O => slip_r_i_2_n_0 ); slip_r_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => next_slip_c, Q => p_1_in(1), R => system_reset_r2 ); sync_done_r_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"80" ) port map ( I0 => \sh_invalid_cnt_equals_zero_i__4\, I1 => sync_done_r_i_3_n_0, I2 => \sh_count_equals_max_i__14\, O => next_sync_done_c ); sync_done_r_i_2: unisim.vcomponents.LUT5 generic map( INIT => X"00000002" ) port map ( I0 => sync_done_r_i_5_n_0, I1 => \sync_header_invalid_count_i_reg__0\(2), I2 => \sync_header_invalid_count_i_reg__0\(3), I3 => \sync_header_invalid_count_i_reg__0\(0), I4 => \sync_header_invalid_count_i_reg__0\(1), O => \sh_invalid_cnt_equals_zero_i__4\ ); sync_done_r_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000002" ) port map ( I0 => p_1_in(3), I1 => p_1_in(2), I2 => sync_done_r, I3 => p_1_in(1), I4 => begin_r, I5 => test_sh_r, O => sync_done_r_i_3_n_0 ); sync_done_r_i_4: unisim.vcomponents.LUT4 generic map( INIT => X"8000" ) port map ( I0 => sync_done_r_i_6_n_0, I1 => sync_done_r_i_7_n_0, I2 => sync_done_r_i_8_n_0, I3 => sync_done_r_i_9_n_0, O => \sh_count_equals_max_i__14\ ); sync_done_r_i_5: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000001" ) port map ( I0 => \sync_header_invalid_count_i_reg__0\(4), I1 => \sync_header_invalid_count_i_reg__0\(5), I2 => \sync_header_invalid_count_i_reg__0\(6), I3 => \sync_header_invalid_count_i_reg__0\(7), I4 => \sync_header_invalid_count_i_reg__0\(9), I5 => \sync_header_invalid_count_i_reg__0\(8), O => sync_done_r_i_5_n_0 ); sync_done_r_i_6: unisim.vcomponents.LUT4 generic map( INIT => X"0400" ) port map ( I0 => sync_header_count_i_reg(7), I1 => sync_header_count_i_reg(6), I2 => sync_header_count_i_reg(4), I3 => sync_header_count_i_reg(5), O => sync_done_r_i_6_n_0 ); sync_done_r_i_7: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => sync_header_count_i_reg(1), I1 => sync_header_count_i_reg(0), I2 => sync_header_count_i_reg(3), I3 => sync_header_count_i_reg(2), O => sync_done_r_i_7_n_0 ); sync_done_r_i_8: unisim.vcomponents.LUT4 generic map( INIT => X"0400" ) port map ( I0 => sync_header_count_i_reg(10), I1 => sync_header_count_i_reg(11), I2 => sync_header_count_i_reg(8), I3 => sync_header_count_i_reg(9), O => sync_done_r_i_8_n_0 ); sync_done_r_i_9: unisim.vcomponents.LUT4 generic map( INIT => X"0800" ) port map ( I0 => sync_header_count_i_reg(15), I1 => sync_header_count_i_reg(14), I2 => sync_header_count_i_reg(12), I3 => sync_header_count_i_reg(13), O => sync_done_r_i_9_n_0 ); sync_done_r_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => next_sync_done_c, Q => sync_done_r, R => system_reset_r2 ); \sync_header_count_i[0]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => p_1_in(3), I1 => p_1_in(2), O => sync_header_count_i0 ); \sync_header_count_i[0]_i_3\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => sync_header_count_i_reg(0), O => \sync_header_count_i[0]_i_3_n_0\ ); \sync_header_count_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => sync_header_count_i0, D => \sync_header_count_i_reg[0]_i_2_n_7\, Q => sync_header_count_i_reg(0), R => begin_r ); \sync_header_count_i_reg[0]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \sync_header_count_i_reg[0]_i_2_n_0\, CO(2) => \sync_header_count_i_reg[0]_i_2_n_1\, CO(1) => \sync_header_count_i_reg[0]_i_2_n_2\, CO(0) => \sync_header_count_i_reg[0]_i_2_n_3\, CYINIT => '0', DI(3 downto 0) => B"0001", O(3) => \sync_header_count_i_reg[0]_i_2_n_4\, O(2) => \sync_header_count_i_reg[0]_i_2_n_5\, O(1) => \sync_header_count_i_reg[0]_i_2_n_6\, O(0) => \sync_header_count_i_reg[0]_i_2_n_7\, S(3 downto 1) => sync_header_count_i_reg(3 downto 1), S(0) => \sync_header_count_i[0]_i_3_n_0\ ); \sync_header_count_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => sync_header_count_i0, D => \sync_header_count_i_reg[8]_i_1_n_5\, Q => sync_header_count_i_reg(10), R => begin_r ); \sync_header_count_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => sync_header_count_i0, D => \sync_header_count_i_reg[8]_i_1_n_4\, Q => sync_header_count_i_reg(11), R => begin_r ); \sync_header_count_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => sync_header_count_i0, D => \sync_header_count_i_reg[12]_i_1_n_7\, Q => sync_header_count_i_reg(12), R => begin_r ); \sync_header_count_i_reg[12]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \sync_header_count_i_reg[8]_i_1_n_0\, CO(3) => \NLW_sync_header_count_i_reg[12]_i_1_CO_UNCONNECTED\(3), CO(2) => \sync_header_count_i_reg[12]_i_1_n_1\, CO(1) => \sync_header_count_i_reg[12]_i_1_n_2\, CO(0) => \sync_header_count_i_reg[12]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \sync_header_count_i_reg[12]_i_1_n_4\, O(2) => \sync_header_count_i_reg[12]_i_1_n_5\, O(1) => \sync_header_count_i_reg[12]_i_1_n_6\, O(0) => \sync_header_count_i_reg[12]_i_1_n_7\, S(3 downto 0) => sync_header_count_i_reg(15 downto 12) ); \sync_header_count_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => sync_header_count_i0, D => \sync_header_count_i_reg[12]_i_1_n_6\, Q => sync_header_count_i_reg(13), R => begin_r ); \sync_header_count_i_reg[14]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => sync_header_count_i0, D => \sync_header_count_i_reg[12]_i_1_n_5\, Q => sync_header_count_i_reg(14), R => begin_r ); \sync_header_count_i_reg[15]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => sync_header_count_i0, D => \sync_header_count_i_reg[12]_i_1_n_4\, Q => sync_header_count_i_reg(15), R => begin_r ); \sync_header_count_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => sync_header_count_i0, D => \sync_header_count_i_reg[0]_i_2_n_6\, Q => sync_header_count_i_reg(1), R => begin_r ); \sync_header_count_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => sync_header_count_i0, D => \sync_header_count_i_reg[0]_i_2_n_5\, Q => sync_header_count_i_reg(2), R => begin_r ); \sync_header_count_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => sync_header_count_i0, D => \sync_header_count_i_reg[0]_i_2_n_4\, Q => sync_header_count_i_reg(3), R => begin_r ); \sync_header_count_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => sync_header_count_i0, D => \sync_header_count_i_reg[4]_i_1_n_7\, Q => sync_header_count_i_reg(4), R => begin_r ); \sync_header_count_i_reg[4]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \sync_header_count_i_reg[0]_i_2_n_0\, CO(3) => \sync_header_count_i_reg[4]_i_1_n_0\, CO(2) => \sync_header_count_i_reg[4]_i_1_n_1\, CO(1) => \sync_header_count_i_reg[4]_i_1_n_2\, CO(0) => \sync_header_count_i_reg[4]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \sync_header_count_i_reg[4]_i_1_n_4\, O(2) => \sync_header_count_i_reg[4]_i_1_n_5\, O(1) => \sync_header_count_i_reg[4]_i_1_n_6\, O(0) => \sync_header_count_i_reg[4]_i_1_n_7\, S(3 downto 0) => sync_header_count_i_reg(7 downto 4) ); \sync_header_count_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => sync_header_count_i0, D => \sync_header_count_i_reg[4]_i_1_n_6\, Q => sync_header_count_i_reg(5), R => begin_r ); \sync_header_count_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => sync_header_count_i0, D => \sync_header_count_i_reg[4]_i_1_n_5\, Q => sync_header_count_i_reg(6), R => begin_r ); \sync_header_count_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => sync_header_count_i0, D => \sync_header_count_i_reg[4]_i_1_n_4\, Q => sync_header_count_i_reg(7), R => begin_r ); \sync_header_count_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => sync_header_count_i0, D => \sync_header_count_i_reg[8]_i_1_n_7\, Q => sync_header_count_i_reg(8), R => begin_r ); \sync_header_count_i_reg[8]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \sync_header_count_i_reg[4]_i_1_n_0\, CO(3) => \sync_header_count_i_reg[8]_i_1_n_0\, CO(2) => \sync_header_count_i_reg[8]_i_1_n_1\, CO(1) => \sync_header_count_i_reg[8]_i_1_n_2\, CO(0) => \sync_header_count_i_reg[8]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \sync_header_count_i_reg[8]_i_1_n_4\, O(2) => \sync_header_count_i_reg[8]_i_1_n_5\, O(1) => \sync_header_count_i_reg[8]_i_1_n_6\, O(0) => \sync_header_count_i_reg[8]_i_1_n_7\, S(3 downto 0) => sync_header_count_i_reg(11 downto 8) ); \sync_header_count_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => sync_header_count_i0, D => \sync_header_count_i_reg[8]_i_1_n_6\, Q => sync_header_count_i_reg(9), R => begin_r ); \sync_header_invalid_count_i[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \sync_header_invalid_count_i_reg__0\(0), O => \p_0_in__5\(0) ); \sync_header_invalid_count_i[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \sync_header_invalid_count_i_reg__0\(0), I1 => \sync_header_invalid_count_i_reg__0\(1), O => \p_0_in__5\(1) ); \sync_header_invalid_count_i[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \sync_header_invalid_count_i_reg__0\(0), I1 => \sync_header_invalid_count_i_reg__0\(1), I2 => \sync_header_invalid_count_i_reg__0\(2), O => \p_0_in__5\(2) ); \sync_header_invalid_count_i[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \sync_header_invalid_count_i_reg__0\(2), I1 => \sync_header_invalid_count_i_reg__0\(1), I2 => \sync_header_invalid_count_i_reg__0\(0), I3 => \sync_header_invalid_count_i_reg__0\(3), O => \p_0_in__5\(3) ); \sync_header_invalid_count_i[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \sync_header_invalid_count_i_reg__0\(3), I1 => \sync_header_invalid_count_i_reg__0\(0), I2 => \sync_header_invalid_count_i_reg__0\(1), I3 => \sync_header_invalid_count_i_reg__0\(2), I4 => \sync_header_invalid_count_i_reg__0\(4), O => \p_0_in__5\(4) ); \sync_header_invalid_count_i[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \sync_header_invalid_count_i_reg__0\(2), I1 => \sync_header_invalid_count_i_reg__0\(1), I2 => \sync_header_invalid_count_i_reg__0\(0), I3 => \sync_header_invalid_count_i_reg__0\(3), I4 => \sync_header_invalid_count_i_reg__0\(4), I5 => \sync_header_invalid_count_i_reg__0\(5), O => \p_0_in__5\(5) ); \sync_header_invalid_count_i[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"9" ) port map ( I0 => \sync_header_invalid_count_i[9]_i_2_n_0\, I1 => \sync_header_invalid_count_i_reg__0\(6), O => \p_0_in__5\(6) ); \sync_header_invalid_count_i[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"D2" ) port map ( I0 => \sync_header_invalid_count_i_reg__0\(6), I1 => \sync_header_invalid_count_i[9]_i_2_n_0\, I2 => \sync_header_invalid_count_i_reg__0\(7), O => \p_0_in__5\(7) ); \sync_header_invalid_count_i[8]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"DF20" ) port map ( I0 => \sync_header_invalid_count_i_reg__0\(7), I1 => \sync_header_invalid_count_i[9]_i_2_n_0\, I2 => \sync_header_invalid_count_i_reg__0\(6), I3 => \sync_header_invalid_count_i_reg__0\(8), O => \p_0_in__5\(8) ); \sync_header_invalid_count_i[9]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"F7FF0800" ) port map ( I0 => \sync_header_invalid_count_i_reg__0\(8), I1 => \sync_header_invalid_count_i_reg__0\(6), I2 => \sync_header_invalid_count_i[9]_i_2_n_0\, I3 => \sync_header_invalid_count_i_reg__0\(7), I4 => \sync_header_invalid_count_i_reg__0\(9), O => \p_0_in__5\(9) ); \sync_header_invalid_count_i[9]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFFFFFFFFFF" ) port map ( I0 => \sync_header_invalid_count_i_reg__0\(2), I1 => \sync_header_invalid_count_i_reg__0\(1), I2 => \sync_header_invalid_count_i_reg__0\(0), I3 => \sync_header_invalid_count_i_reg__0\(3), I4 => \sync_header_invalid_count_i_reg__0\(4), I5 => \sync_header_invalid_count_i_reg__0\(5), O => \sync_header_invalid_count_i[9]_i_2_n_0\ ); \sync_header_invalid_count_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => p_1_in(2), D => \p_0_in__5\(0), Q => \sync_header_invalid_count_i_reg__0\(0), R => begin_r ); \sync_header_invalid_count_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => p_1_in(2), D => \p_0_in__5\(1), Q => \sync_header_invalid_count_i_reg__0\(1), R => begin_r ); \sync_header_invalid_count_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => p_1_in(2), D => \p_0_in__5\(2), Q => \sync_header_invalid_count_i_reg__0\(2), R => begin_r ); \sync_header_invalid_count_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => p_1_in(2), D => \p_0_in__5\(3), Q => \sync_header_invalid_count_i_reg__0\(3), R => begin_r ); \sync_header_invalid_count_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => p_1_in(2), D => \p_0_in__5\(4), Q => \sync_header_invalid_count_i_reg__0\(4), R => begin_r ); \sync_header_invalid_count_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => p_1_in(2), D => \p_0_in__5\(5), Q => \sync_header_invalid_count_i_reg__0\(5), R => begin_r ); \sync_header_invalid_count_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => p_1_in(2), D => \p_0_in__5\(6), Q => \sync_header_invalid_count_i_reg__0\(6), R => begin_r ); \sync_header_invalid_count_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => p_1_in(2), D => \p_0_in__5\(7), Q => \sync_header_invalid_count_i_reg__0\(7), R => begin_r ); \sync_header_invalid_count_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => p_1_in(2), D => \p_0_in__5\(8), Q => \sync_header_invalid_count_i_reg__0\(8), R => begin_r ); \sync_header_invalid_count_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => p_1_in(2), D => \p_0_in__5\(9), Q => \sync_header_invalid_count_i_reg__0\(9), R => begin_r ); system_reset_r2_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => system_reset_r, Q => system_reset_r2, R => '0' ); system_reset_r_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => SR(0), Q => system_reset_r, R => '0' ); test_sh_r_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAAFFBAAAAA" ) port map ( I0 => test_sh_r_i_2_n_0, I1 => RXGEARBOXSLIP_OUT_i_3_n_0, I2 => p_1_in(2), I3 => p_1_in(3), I4 => slip_r_i_2_n_0, I5 => \sh_count_equals_max_i__14\, O => next_test_sh_c ); test_sh_r_i_2: unisim.vcomponents.LUT4 generic map( INIT => X"F020" ) port map ( I0 => test_sh_r, I1 => rxheadervalid_i, I2 => slip_r_i_2_n_0, I3 => begin_r, O => test_sh_r_i_2_n_0 ); test_sh_r_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => next_test_sh_c, Q => test_sh_r, R => system_reset_r2 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_CHANNEL_BOND_GEN is port ( gen_ch_bond_int_reg_0 : out STD_LOGIC; \out\ : in STD_LOGIC; TXDATAVALID_IN : in STD_LOGIC; \free_count_r_reg[4]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ); gen_ch_bond_int_reg_1 : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_CHANNEL_BOND_GEN; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_CHANNEL_BOND_GEN is signal data_v_r : STD_LOGIC; signal \free_count_r[0]_i_1_n_0\ : STD_LOGIC; signal \free_count_r[0]_i_3_n_0\ : STD_LOGIC; signal \free_count_r_reg__0\ : STD_LOGIC_VECTOR ( 0 to 4 ); signal gen_ch_bond_int_i_1_n_0 : STD_LOGIC; signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 4 downto 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \free_count_r[0]_i_2\ : label is "soft_lutpair96"; attribute SOFT_HLUTNM of \free_count_r[0]_i_3\ : label is "soft_lutpair96"; attribute SOFT_HLUTNM of \free_count_r[1]_i_1\ : label is "soft_lutpair97"; attribute SOFT_HLUTNM of \free_count_r[2]_i_1\ : label is "soft_lutpair97"; attribute SOFT_HLUTNM of \free_count_r[3]_i_1\ : label is "soft_lutpair98"; attribute SOFT_HLUTNM of \free_count_r[4]_i_1\ : label is "soft_lutpair98"; begin data_v_r_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => TXDATAVALID_IN, Q => data_v_r, R => '0' ); \free_count_r[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"FF20" ) port map ( I0 => data_v_r, I1 => \free_count_r_reg__0\(0), I2 => \free_count_r[0]_i_3_n_0\, I3 => \free_count_r_reg[4]_0\(0), O => \free_count_r[0]_i_1_n_0\ ); \free_count_r[0]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \free_count_r_reg__0\(1), I1 => \free_count_r_reg__0\(3), I2 => \free_count_r_reg__0\(4), I3 => \free_count_r_reg__0\(2), I4 => \free_count_r_reg__0\(0), O => \p_0_in__1\(4) ); \free_count_r[0]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"0400" ) port map ( I0 => \free_count_r_reg__0\(3), I1 => \free_count_r_reg__0\(4), I2 => \free_count_r_reg__0\(2), I3 => \free_count_r_reg__0\(1), O => \free_count_r[0]_i_3_n_0\ ); \free_count_r[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \free_count_r_reg__0\(2), I1 => \free_count_r_reg__0\(4), I2 => \free_count_r_reg__0\(3), I3 => \free_count_r_reg__0\(1), O => \p_0_in__1\(3) ); \free_count_r[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \free_count_r_reg__0\(3), I1 => \free_count_r_reg__0\(4), I2 => \free_count_r_reg__0\(2), O => \p_0_in__1\(2) ); \free_count_r[3]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \free_count_r_reg__0\(4), I1 => \free_count_r_reg__0\(3), O => \p_0_in__1\(1) ); \free_count_r[4]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \free_count_r_reg__0\(4), O => \p_0_in__1\(0) ); \free_count_r_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => data_v_r, D => \p_0_in__1\(4), Q => \free_count_r_reg__0\(0), R => \free_count_r[0]_i_1_n_0\ ); \free_count_r_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => data_v_r, D => \p_0_in__1\(3), Q => \free_count_r_reg__0\(1), R => \free_count_r[0]_i_1_n_0\ ); \free_count_r_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => data_v_r, D => \p_0_in__1\(2), Q => \free_count_r_reg__0\(2), R => \free_count_r[0]_i_1_n_0\ ); \free_count_r_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => data_v_r, D => \p_0_in__1\(1), Q => \free_count_r_reg__0\(3), R => \free_count_r[0]_i_1_n_0\ ); \free_count_r_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => data_v_r, D => \p_0_in__1\(0), Q => \free_count_r_reg__0\(4), R => \free_count_r[0]_i_1_n_0\ ); gen_ch_bond_int_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000020" ) port map ( I0 => \free_count_r_reg__0\(1), I1 => \free_count_r_reg__0\(2), I2 => \free_count_r_reg__0\(4), I3 => \free_count_r_reg__0\(3), I4 => gen_ch_bond_int_reg_1, I5 => \free_count_r_reg__0\(0), O => gen_ch_bond_int_i_1_n_0 ); gen_ch_bond_int_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => gen_ch_bond_int_i_1_n_0, Q => gen_ch_bond_int_reg_0, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_CHANNEL_ERR_DETECT is port ( hard_err : out STD_LOGIC; hard_err_i : in STD_LOGIC; \out\ : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_CHANNEL_ERR_DETECT; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_CHANNEL_ERR_DETECT is begin CHANNEL_HARD_ERR_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => hard_err_i, Q => hard_err, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_CHANNEL_INIT_SM is port ( SR : out STD_LOGIC_VECTOR ( 0 to 0 ); wait_for_lane_up_r_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 ); CHANNEL_UP_RX_IF_reg_0 : out STD_LOGIC; CHANNEL_UP_TX_IF_reg_0 : out STD_LOGIC; gen_ch_bond_int_reg : out STD_LOGIC; CHANNEL_UP_RX_IF_reg_1 : out STD_LOGIC; gen_cc_flop_0_i : out STD_LOGIC_VECTOR ( 1 downto 0 ); E : out STD_LOGIC_VECTOR ( 0 to 0 ); CHANNEL_UP_RX_IF_reg_2 : out STD_LOGIC; R0 : out STD_LOGIC; reset_lanes_c : in STD_LOGIC; \out\ : in STD_LOGIC; wait_for_lane_up_r_reg_1 : in STD_LOGIC; remote_ready_i : in STD_LOGIC; RX_IDLE : in STD_LOGIC; CHANNEL_UP_RX_IF_reg_3 : in STD_LOGIC_VECTOR ( 0 to 0 ); \TX_DATA_reg[63]\ : in STD_LOGIC; \TX_DATA_reg[63]_0\ : in STD_LOGIC; gen_cc_i : in STD_LOGIC; tx_pe_data_v_i : in STD_LOGIC; ready_r_reg_0 : in STD_LOGIC; rx_pe_data_v_i : in STD_LOGIC; rst_pma_init_usrclk : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 1 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_CHANNEL_INIT_SM; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_CHANNEL_INIT_SM is signal \^channel_up_rx_if_reg_0\ : STD_LOGIC; signal \^channel_up_tx_if_reg_0\ : STD_LOGIC; signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \TX_DATA[55]_i_4_n_0\ : STD_LOGIC; signal \TX_DATA[63]_i_2_n_0\ : STD_LOGIC; signal any_idles_r : STD_LOGIC; signal chan_bond_timeout_val : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of chan_bond_timeout_val : signal is "true"; signal channel_up_c : STD_LOGIC; signal idle_xmit_cntr : STD_LOGIC; signal \idle_xmit_cntr[0]_i_2_n_0\ : STD_LOGIC; signal \idle_xmit_cntr[0]_i_3_n_0\ : STD_LOGIC; signal \idle_xmit_cntr[0]_i_4_n_0\ : STD_LOGIC; signal \idle_xmit_cntr[1]_i_1_n_0\ : STD_LOGIC; signal \idle_xmit_cntr[2]_i_1_n_0\ : STD_LOGIC; signal \idle_xmit_cntr[3]_i_1_n_0\ : STD_LOGIC; signal \idle_xmit_cntr[4]_i_1_n_0\ : STD_LOGIC; signal \idle_xmit_cntr[5]_i_1_n_0\ : STD_LOGIC; signal \idle_xmit_cntr_reg_n_0_[0]\ : STD_LOGIC; signal \idle_xmit_cntr_reg_n_0_[1]\ : STD_LOGIC; signal \idle_xmit_cntr_reg_n_0_[2]\ : STD_LOGIC; signal \idle_xmit_cntr_reg_n_0_[3]\ : STD_LOGIC; signal \idle_xmit_cntr_reg_n_0_[4]\ : STD_LOGIC; signal \idle_xmit_cntr_reg_n_0_[5]\ : STD_LOGIC; signal ready_r : STD_LOGIC; signal \ready_r_i_1__0_n_0\ : STD_LOGIC; signal remote_ready_r : STD_LOGIC; signal \^wait_for_lane_up_r_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal wait_for_remote_r : STD_LOGIC; signal wait_for_remote_r_i_1_n_0 : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \RX_D[0]_i_1\ : label is "soft_lutpair99"; attribute SOFT_HLUTNM of RX_SRC_RDY_N_inv_i_1 : label is "soft_lutpair99"; attribute SOFT_HLUTNM of \TX_DATA[63]_i_2\ : label is "soft_lutpair100"; attribute SOFT_HLUTNM of gen_cc_flop_0_i_i_1 : label is "soft_lutpair100"; attribute BOX_TYPE : string; attribute BOX_TYPE of reset_lanes_flop_0_i : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of reset_lanes_flop_0_i : label is "FD"; begin CHANNEL_UP_RX_IF_reg_0 <= \^channel_up_rx_if_reg_0\; CHANNEL_UP_TX_IF_reg_0 <= \^channel_up_tx_if_reg_0\; SR(0) <= \^sr\(0); wait_for_lane_up_r_reg_0(0) <= \^wait_for_lane_up_r_reg_0\(0); CHANNEL_UP_RX_IF_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => remote_ready_r, Q => \^channel_up_rx_if_reg_0\, R => CHANNEL_UP_RX_IF_reg_3(0) ); CHANNEL_UP_TX_IF_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"00404040" ) port map ( I0 => \^wait_for_lane_up_r_reg_0\(0), I1 => remote_ready_r, I2 => ready_r, I3 => wait_for_remote_r, I4 => \idle_xmit_cntr[0]_i_3_n_0\, O => channel_up_c ); CHANNEL_UP_TX_IF_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => channel_up_c, Q => \^channel_up_tx_if_reg_0\, R => CHANNEL_UP_RX_IF_reg_3(0) ); DO_CC_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^channel_up_rx_if_reg_0\, O => CHANNEL_UP_RX_IF_reg_2 ); \RX_D[0]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^channel_up_rx_if_reg_0\, I1 => rx_pe_data_v_i, O => E(0) ); RX_SRC_RDY_N_inv_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"08" ) port map ( I0 => \^channel_up_rx_if_reg_0\, I1 => rx_pe_data_v_i, I2 => \^sr\(0), O => CHANNEL_UP_RX_IF_reg_1 ); \TX_DATA[54]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"000A000A000E000A" ) port map ( I0 => \TX_DATA_reg[63]_0\, I1 => \^channel_up_tx_if_reg_0\, I2 => rst_pma_init_usrclk, I3 => gen_cc_i, I4 => Q(0), I5 => \TX_DATA[55]_i_4_n_0\, O => gen_cc_flop_0_i(0) ); \TX_DATA[55]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"0A0A0A0A0A0E0A0A" ) port map ( I0 => gen_cc_i, I1 => \^channel_up_tx_if_reg_0\, I2 => rst_pma_init_usrclk, I3 => \TX_DATA_reg[63]_0\, I4 => Q(1), I5 => \TX_DATA[55]_i_4_n_0\, O => gen_cc_flop_0_i(1) ); \TX_DATA[55]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \^wait_for_lane_up_r_reg_0\(0), I1 => tx_pe_data_v_i, O => \TX_DATA[55]_i_4_n_0\ ); \TX_DATA[63]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAA8AAAAAAAAAA" ) port map ( I0 => \TX_DATA_reg[63]\, I1 => \TX_DATA_reg[63]_0\, I2 => gen_cc_i, I3 => tx_pe_data_v_i, I4 => \^wait_for_lane_up_r_reg_0\(0), I5 => \TX_DATA[63]_i_2_n_0\, O => gen_ch_bond_int_reg ); \TX_DATA[63]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^channel_up_tx_if_reg_0\, I1 => rst_pma_init_usrclk, O => \TX_DATA[63]_i_2_n_0\ ); any_idles_r_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => RX_IDLE, Q => any_idles_r, R => '0' ); gen_cc_flop_0_i_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^channel_up_tx_if_reg_0\, O => R0 ); i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '1', O => chan_bond_timeout_val(8) ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '1', O => chan_bond_timeout_val(7) ); i_2: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '1', O => chan_bond_timeout_val(6) ); i_3: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '1', O => chan_bond_timeout_val(5) ); i_4: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '1', O => chan_bond_timeout_val(4) ); i_5: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => chan_bond_timeout_val(3) ); i_6: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '1', O => chan_bond_timeout_val(2) ); i_7: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => chan_bond_timeout_val(1) ); i_8: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => chan_bond_timeout_val(0) ); \idle_xmit_cntr[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFC8FF" ) port map ( I0 => \idle_xmit_cntr_reg_n_0_[5]\, I1 => wait_for_remote_r, I2 => any_idles_r, I3 => \idle_xmit_cntr[0]_i_3_n_0\, I4 => \idle_xmit_cntr[0]_i_4_n_0\, O => idle_xmit_cntr ); \idle_xmit_cntr[0]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF80000000" ) port map ( I0 => \idle_xmit_cntr_reg_n_0_[3]\, I1 => \idle_xmit_cntr_reg_n_0_[5]\, I2 => \idle_xmit_cntr_reg_n_0_[4]\, I3 => \idle_xmit_cntr_reg_n_0_[2]\, I4 => \idle_xmit_cntr_reg_n_0_[1]\, I5 => \idle_xmit_cntr_reg_n_0_[0]\, O => \idle_xmit_cntr[0]_i_2_n_0\ ); \idle_xmit_cntr[0]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFFFFFFFFFF" ) port map ( I0 => \idle_xmit_cntr_reg_n_0_[0]\, I1 => \idle_xmit_cntr_reg_n_0_[1]\, I2 => \idle_xmit_cntr_reg_n_0_[2]\, I3 => \idle_xmit_cntr_reg_n_0_[4]\, I4 => \idle_xmit_cntr_reg_n_0_[5]\, I5 => \idle_xmit_cntr_reg_n_0_[3]\, O => \idle_xmit_cntr[0]_i_3_n_0\ ); \idle_xmit_cntr[0]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFF0000FFFE0000" ) port map ( I0 => \idle_xmit_cntr_reg_n_0_[4]\, I1 => \idle_xmit_cntr_reg_n_0_[1]\, I2 => \idle_xmit_cntr_reg_n_0_[0]\, I3 => \idle_xmit_cntr_reg_n_0_[2]\, I4 => wait_for_remote_r, I5 => \idle_xmit_cntr_reg_n_0_[3]\, O => \idle_xmit_cntr[0]_i_4_n_0\ ); \idle_xmit_cntr[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"EAAAAAAA6AAAAAAA" ) port map ( I0 => \idle_xmit_cntr_reg_n_0_[1]\, I1 => \idle_xmit_cntr_reg_n_0_[3]\, I2 => \idle_xmit_cntr_reg_n_0_[5]\, I3 => \idle_xmit_cntr_reg_n_0_[4]\, I4 => \idle_xmit_cntr_reg_n_0_[2]\, I5 => \idle_xmit_cntr_reg_n_0_[0]\, O => \idle_xmit_cntr[1]_i_1_n_0\ ); \idle_xmit_cntr[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"EAAA6AAA6AAA6AAA" ) port map ( I0 => \idle_xmit_cntr_reg_n_0_[2]\, I1 => \idle_xmit_cntr_reg_n_0_[4]\, I2 => \idle_xmit_cntr_reg_n_0_[5]\, I3 => \idle_xmit_cntr_reg_n_0_[3]\, I4 => \idle_xmit_cntr_reg_n_0_[1]\, I5 => \idle_xmit_cntr_reg_n_0_[0]\, O => \idle_xmit_cntr[2]_i_1_n_0\ ); \idle_xmit_cntr[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"EA6A6A6A6A6A6A6A" ) port map ( I0 => \idle_xmit_cntr_reg_n_0_[3]\, I1 => \idle_xmit_cntr_reg_n_0_[5]\, I2 => \idle_xmit_cntr_reg_n_0_[4]\, I3 => \idle_xmit_cntr_reg_n_0_[2]\, I4 => \idle_xmit_cntr_reg_n_0_[0]\, I5 => \idle_xmit_cntr_reg_n_0_[1]\, O => \idle_xmit_cntr[3]_i_1_n_0\ ); \idle_xmit_cntr[4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"D5555555AAAAAAAA" ) port map ( I0 => \idle_xmit_cntr_reg_n_0_[5]\, I1 => \idle_xmit_cntr_reg_n_0_[1]\, I2 => \idle_xmit_cntr_reg_n_0_[0]\, I3 => \idle_xmit_cntr_reg_n_0_[2]\, I4 => \idle_xmit_cntr_reg_n_0_[3]\, I5 => \idle_xmit_cntr_reg_n_0_[4]\, O => \idle_xmit_cntr[4]_i_1_n_0\ ); \idle_xmit_cntr[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"80000000FFFFFFFF" ) port map ( I0 => \idle_xmit_cntr_reg_n_0_[1]\, I1 => \idle_xmit_cntr_reg_n_0_[0]\, I2 => \idle_xmit_cntr_reg_n_0_[2]\, I3 => \idle_xmit_cntr_reg_n_0_[3]\, I4 => \idle_xmit_cntr_reg_n_0_[4]\, I5 => \idle_xmit_cntr_reg_n_0_[5]\, O => \idle_xmit_cntr[5]_i_1_n_0\ ); \idle_xmit_cntr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => idle_xmit_cntr, D => \idle_xmit_cntr[0]_i_2_n_0\, Q => \idle_xmit_cntr_reg_n_0_[0]\, R => \^wait_for_lane_up_r_reg_0\(0) ); \idle_xmit_cntr_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => idle_xmit_cntr, D => \idle_xmit_cntr[1]_i_1_n_0\, Q => \idle_xmit_cntr_reg_n_0_[1]\, R => \^wait_for_lane_up_r_reg_0\(0) ); \idle_xmit_cntr_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => idle_xmit_cntr, D => \idle_xmit_cntr[2]_i_1_n_0\, Q => \idle_xmit_cntr_reg_n_0_[2]\, R => \^wait_for_lane_up_r_reg_0\(0) ); \idle_xmit_cntr_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => idle_xmit_cntr, D => \idle_xmit_cntr[3]_i_1_n_0\, Q => \idle_xmit_cntr_reg_n_0_[3]\, R => \^wait_for_lane_up_r_reg_0\(0) ); \idle_xmit_cntr_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => idle_xmit_cntr, D => \idle_xmit_cntr[4]_i_1_n_0\, Q => \idle_xmit_cntr_reg_n_0_[4]\, R => \^wait_for_lane_up_r_reg_0\(0) ); \idle_xmit_cntr_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => idle_xmit_cntr, D => \idle_xmit_cntr[5]_i_1_n_0\, Q => \idle_xmit_cntr_reg_n_0_[5]\, R => \^wait_for_lane_up_r_reg_0\(0) ); \ready_r_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"00000000CC080000" ) port map ( I0 => wait_for_remote_r, I1 => remote_ready_r, I2 => \idle_xmit_cntr[0]_i_3_n_0\, I3 => ready_r, I4 => ready_r_reg_0, I5 => CHANNEL_UP_RX_IF_reg_3(0), O => \ready_r_i_1__0_n_0\ ); ready_r_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => \ready_r_i_1__0_n_0\, Q => ready_r, R => '0' ); remote_ready_r_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => remote_ready_i, Q => remote_ready_r, R => '0' ); reset_lanes_flop_0_i: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => reset_lanes_c, Q => \^sr\(0), R => '0' ); wait_for_lane_up_r_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wait_for_lane_up_r_reg_1, Q => \^wait_for_lane_up_r_reg_0\(0), R => '0' ); wait_for_remote_r_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"00000000EAEAFFEE" ) port map ( I0 => \^wait_for_lane_up_r_reg_0\(0), I1 => wait_for_remote_r, I2 => \idle_xmit_cntr[0]_i_3_n_0\, I3 => ready_r, I4 => remote_ready_r, I5 => wait_for_lane_up_r_reg_1, O => wait_for_remote_r_i_1_n_0 ); wait_for_remote_r_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wait_for_remote_r_i_1_n_0, Q => wait_for_remote_r, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_CLOCK_MODULE is port ( in0 : out STD_LOGIC; sync_clk_i_0 : out STD_LOGIC; user_clk_i_0 : out STD_LOGIC; INIT_CLK_i : out STD_LOGIC; mmcm_not_locked_out : out STD_LOGIC; tx_out_clk : in STD_LOGIC; init_clk : in STD_LOGIC; mmcm_lock_sync_reg : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_CLOCK_MODULE; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_CLOCK_MODULE is signal clk_in_i : STD_LOGIC; signal clk_not_locked_i : STD_LOGIC; attribute RTL_KEEP : string; attribute RTL_KEEP of clk_not_locked_i : signal is "true"; signal clkfbout : STD_LOGIC; signal \^in0\ : STD_LOGIC; signal sync_clk_i : STD_LOGIC; signal user_clk_i : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); attribute BOX_TYPE : string; attribute BOX_TYPE of initclk_bufg_i : label is "PRIMITIVE"; attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE"; attribute BOX_TYPE of sync_clock_net_i : label is "PRIMITIVE"; attribute BOX_TYPE of txout_clock_net_i : label is "PRIMITIVE"; attribute BOX_TYPE of user_clk_net_i : label is "PRIMITIVE"; begin clk_not_locked_i <= mmcm_lock_sync_reg; in0 <= \^in0\; initclk_bufg_i: unisim.vcomponents.BUFG port map ( I => init_clk, O => INIT_CLK_i ); mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV generic map( BANDWIDTH => "OPTIMIZED", CLKFBOUT_MULT_F => 7.000000, CLKFBOUT_PHASE => 0.000000, CLKFBOUT_USE_FINE_PS => false, CLKIN1_PERIOD => 6.400000, CLKIN2_PERIOD => 0.000000, CLKOUT0_DIVIDE_F => 14.000000, CLKOUT0_DUTY_CYCLE => 0.500000, CLKOUT0_PHASE => 0.000000, CLKOUT0_USE_FINE_PS => false, CLKOUT1_DIVIDE => 7, CLKOUT1_DUTY_CYCLE => 0.500000, CLKOUT1_PHASE => 0.000000, CLKOUT1_USE_FINE_PS => false, CLKOUT2_DIVIDE => 10, CLKOUT2_DUTY_CYCLE => 0.500000, CLKOUT2_PHASE => 0.000000, CLKOUT2_USE_FINE_PS => false, CLKOUT3_DIVIDE => 8, CLKOUT3_DUTY_CYCLE => 0.500000, CLKOUT3_PHASE => 0.000000, CLKOUT3_USE_FINE_PS => false, CLKOUT4_CASCADE => false, CLKOUT4_DIVIDE => 1, CLKOUT4_DUTY_CYCLE => 0.500000, CLKOUT4_PHASE => 0.000000, CLKOUT4_USE_FINE_PS => false, CLKOUT5_DIVIDE => 1, CLKOUT5_DUTY_CYCLE => 0.500000, CLKOUT5_PHASE => 0.000000, CLKOUT5_USE_FINE_PS => false, CLKOUT6_DIVIDE => 1, CLKOUT6_DUTY_CYCLE => 0.500000, CLKOUT6_PHASE => 0.000000, CLKOUT6_USE_FINE_PS => false, COMPENSATION => "INTERNAL", DIVCLK_DIVIDE => 1, IS_CLKINSEL_INVERTED => '0', IS_PSEN_INVERTED => '0', IS_PSINCDEC_INVERTED => '0', IS_PWRDWN_INVERTED => '0', IS_RST_INVERTED => '0', REF_JITTER1 => 0.010000, REF_JITTER2 => 0.010000, SS_EN => "FALSE", SS_MODE => "CENTER_HIGH", SS_MOD_PERIOD => 10000, STARTUP_WAIT => false ) port map ( CLKFBIN => clkfbout, CLKFBOUT => clkfbout, CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED, CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED, CLKIN1 => clk_in_i, CLKIN2 => '0', CLKINSEL => '1', CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED, CLKOUT0 => user_clk_i, CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED, CLKOUT1 => sync_clk_i, CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED, CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED, CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED, CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED, CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED, CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED, CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED, CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED, DADDR(6 downto 0) => B"0000000", DCLK => '0', DEN => '0', DI(15 downto 0) => B"0000000000000000", DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0), DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED, DWE => '0', LOCKED => \^in0\, PSCLK => '0', PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED, PSEN => '0', PSINCDEC => '0', PWRDWN => '0', RST => clk_not_locked_i ); mmcm_not_locked_out_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^in0\, O => mmcm_not_locked_out ); sync_clock_net_i: unisim.vcomponents.BUFG port map ( I => sync_clk_i, O => sync_clk_i_0 ); txout_clock_net_i: unisim.vcomponents.BUFG port map ( I => tx_out_clk, O => clk_in_i ); user_clk_net_i: unisim.vcomponents.BUFG port map ( I => user_clk_i, O => user_clk_i_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_DESCRAMBLER_64B66B is port ( D : out STD_LOGIC_VECTOR ( 1 downto 0 ); CC_detect : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 31 downto 0 ); CB_detect0 : out STD_LOGIC; \descrambler_reg[39]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 ); in0 : in STD_LOGIC; CC_detect_dlyd1 : in STD_LOGIC; rxdatavalid_to_fifo_i : in STD_LOGIC; CB_detect_dlyd0p5 : in STD_LOGIC; CB_detect_dlyd0p5_reg : in STD_LOGIC_VECTOR ( 1 downto 0 ); E : in STD_LOGIC_VECTOR ( 0 to 0 ); \out\ : in STD_LOGIC; \descrambler_reg[31]_0\ : in STD_LOGIC_VECTOR ( 31 downto 0 ); \unscrambled_data_i_reg[13]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_DESCRAMBLER_64B66B; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_DESCRAMBLER_64B66B is signal CC_detect_dlyd1_i_2_n_0 : STD_LOGIC; signal CC_detect_dlyd1_i_3_n_0 : STD_LOGIC; signal CC_detect_dlyd1_i_4_n_0 : STD_LOGIC; signal CC_detect_dlyd1_i_5_n_0 : STD_LOGIC; signal CC_detect_pulse_r_i_2_n_0 : STD_LOGIC; signal \^q\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \descrambler[57]_i_1_n_0\ : STD_LOGIC; signal \^descrambler_reg[39]_0\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \descrambler_reg_n_0_[40]\ : STD_LOGIC; signal \descrambler_reg_n_0_[41]\ : STD_LOGIC; signal \descrambler_reg_n_0_[42]\ : STD_LOGIC; signal \descrambler_reg_n_0_[43]\ : STD_LOGIC; signal \descrambler_reg_n_0_[44]\ : STD_LOGIC; signal \descrambler_reg_n_0_[45]\ : STD_LOGIC; signal \descrambler_reg_n_0_[46]\ : STD_LOGIC; signal \descrambler_reg_n_0_[47]\ : STD_LOGIC; signal \descrambler_reg_n_0_[48]\ : STD_LOGIC; signal \descrambler_reg_n_0_[49]\ : STD_LOGIC; signal \descrambler_reg_n_0_[50]\ : STD_LOGIC; signal \descrambler_reg_n_0_[51]\ : STD_LOGIC; signal \descrambler_reg_n_0_[52]\ : STD_LOGIC; signal \descrambler_reg_n_0_[53]\ : STD_LOGIC; signal \descrambler_reg_n_0_[54]\ : STD_LOGIC; signal \descrambler_reg_n_0_[55]\ : STD_LOGIC; signal \descrambler_reg_n_0_[56]\ : STD_LOGIC; signal \descrambler_reg_n_0_[57]\ : STD_LOGIC; signal p_100_in : STD_LOGIC; signal p_67_in : STD_LOGIC; signal p_69_in : STD_LOGIC; signal p_73_in : STD_LOGIC; signal p_75_in : STD_LOGIC; signal p_78_in : STD_LOGIC; signal p_80_in : STD_LOGIC; signal p_84_in : STD_LOGIC; signal p_86_in : STD_LOGIC; signal p_89_in : STD_LOGIC; signal p_91_in : STD_LOGIC; signal p_95_in : STD_LOGIC; signal p_97_in : STD_LOGIC; signal poly : STD_LOGIC_VECTOR ( 57 downto 32 ); signal tempData : STD_LOGIC_VECTOR ( 0 to 17 ); signal unscrambled_data_i0 : STD_LOGIC; signal unscrambled_data_i012_out : STD_LOGIC; signal unscrambled_data_i016_out : STD_LOGIC; signal unscrambled_data_i020_out : STD_LOGIC; signal unscrambled_data_i024_out : STD_LOGIC; signal unscrambled_data_i028_out : STD_LOGIC; signal unscrambled_data_i032_out : STD_LOGIC; signal unscrambled_data_i036_out : STD_LOGIC; signal unscrambled_data_i040_out : STD_LOGIC; signal unscrambled_data_i044_out : STD_LOGIC; signal unscrambled_data_i048_out : STD_LOGIC; signal unscrambled_data_i04_out : STD_LOGIC; signal unscrambled_data_i08_out : STD_LOGIC; signal \wdth_conv_1stage[38]_i_2_n_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of CC_detect_pulse_r_i_1 : label is "soft_lutpair21"; attribute SOFT_HLUTNM of CC_detect_pulse_r_i_2 : label is "soft_lutpair20"; attribute SOFT_HLUTNM of \unscrambled_data_i[0]_i_1\ : label is "soft_lutpair22"; attribute SOFT_HLUTNM of \unscrambled_data_i[10]_i_1\ : label is "soft_lutpair32"; attribute SOFT_HLUTNM of \unscrambled_data_i[11]_i_1\ : label is "soft_lutpair33"; attribute SOFT_HLUTNM of \unscrambled_data_i[12]_i_1\ : label is "soft_lutpair34"; attribute SOFT_HLUTNM of \unscrambled_data_i[19]_i_1\ : label is "soft_lutpair22"; attribute SOFT_HLUTNM of \unscrambled_data_i[1]_i_1\ : label is "soft_lutpair23"; attribute SOFT_HLUTNM of \unscrambled_data_i[20]_i_1\ : label is "soft_lutpair23"; attribute SOFT_HLUTNM of \unscrambled_data_i[21]_i_1\ : label is "soft_lutpair24"; attribute SOFT_HLUTNM of \unscrambled_data_i[22]_i_1\ : label is "soft_lutpair25"; attribute SOFT_HLUTNM of \unscrambled_data_i[23]_i_1\ : label is "soft_lutpair26"; attribute SOFT_HLUTNM of \unscrambled_data_i[24]_i_1\ : label is "soft_lutpair27"; attribute SOFT_HLUTNM of \unscrambled_data_i[25]_i_1\ : label is "soft_lutpair28"; attribute SOFT_HLUTNM of \unscrambled_data_i[26]_i_1\ : label is "soft_lutpair29"; attribute SOFT_HLUTNM of \unscrambled_data_i[27]_i_1\ : label is "soft_lutpair30"; attribute SOFT_HLUTNM of \unscrambled_data_i[28]_i_1\ : label is "soft_lutpair31"; attribute SOFT_HLUTNM of \unscrambled_data_i[29]_i_1\ : label is "soft_lutpair32"; attribute SOFT_HLUTNM of \unscrambled_data_i[2]_i_1\ : label is "soft_lutpair24"; attribute SOFT_HLUTNM of \unscrambled_data_i[30]_i_1\ : label is "soft_lutpair33"; attribute SOFT_HLUTNM of \unscrambled_data_i[31]_i_1\ : label is "soft_lutpair34"; attribute SOFT_HLUTNM of \unscrambled_data_i[3]_i_1\ : label is "soft_lutpair25"; attribute SOFT_HLUTNM of \unscrambled_data_i[4]_i_1\ : label is "soft_lutpair26"; attribute SOFT_HLUTNM of \unscrambled_data_i[5]_i_1\ : label is "soft_lutpair27"; attribute SOFT_HLUTNM of \unscrambled_data_i[6]_i_1\ : label is "soft_lutpair28"; attribute SOFT_HLUTNM of \unscrambled_data_i[7]_i_1\ : label is "soft_lutpair29"; attribute SOFT_HLUTNM of \unscrambled_data_i[8]_i_1\ : label is "soft_lutpair30"; attribute SOFT_HLUTNM of \unscrambled_data_i[9]_i_1\ : label is "soft_lutpair31"; attribute SOFT_HLUTNM of \wdth_conv_1stage[38]_i_1\ : label is "soft_lutpair21"; attribute SOFT_HLUTNM of \wdth_conv_1stage[38]_i_2\ : label is "soft_lutpair20"; begin Q(31 downto 0) <= \^q\(31 downto 0); \descrambler_reg[39]_0\(1 downto 0) <= \^descrambler_reg[39]_0\(1 downto 0); CB_detect_dlyd0p5_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000200000" ) port map ( I0 => CC_detect_dlyd1_i_2_n_0, I1 => CC_detect_dlyd1_i_4_n_0, I2 => \^q\(22), I3 => \^q\(23), I4 => rxdatavalid_to_fifo_i, I5 => CC_detect_dlyd1_i_3_n_0, O => CB_detect0 ); CC_detect_dlyd1_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000200000" ) port map ( I0 => CC_detect_dlyd1_i_2_n_0, I1 => CC_detect_dlyd1_i_3_n_0, I2 => rxdatavalid_to_fifo_i, I3 => \^q\(22), I4 => \^q\(23), I5 => CC_detect_dlyd1_i_4_n_0, O => CC_detect ); CC_detect_dlyd1_i_2: unisim.vcomponents.LUT5 generic map( INIT => X"00000001" ) port map ( I0 => \^q\(24), I1 => \^q\(26), I2 => \^q\(16), I3 => \^q\(20), I4 => CC_detect_dlyd1_i_5_n_0, O => CC_detect_dlyd1_i_2_n_0 ); CC_detect_dlyd1_i_3: unisim.vcomponents.LUT4 generic map( INIT => X"FF7F" ) port map ( I0 => \^q\(28), I1 => CB_detect_dlyd0p5_reg(1), I2 => \^q\(29), I3 => CB_detect_dlyd0p5_reg(0), O => CC_detect_dlyd1_i_3_n_0 ); CC_detect_dlyd1_i_4: unisim.vcomponents.LUT4 generic map( INIT => X"FFF7" ) port map ( I0 => \^q\(27), I1 => \^q\(30), I2 => \^q\(19), I3 => \^q\(21), O => CC_detect_dlyd1_i_4_n_0 ); CC_detect_dlyd1_i_5: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => \^q\(18), I1 => \^q\(25), I2 => \^q\(31), I3 => \^q\(17), O => CC_detect_dlyd1_i_5_n_0 ); CC_detect_pulse_r_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) port map ( I0 => CC_detect_pulse_r_i_2_n_0, I1 => CC_detect_dlyd1_i_2_n_0, I2 => CC_detect_dlyd1, O => D(1) ); CC_detect_pulse_r_i_2: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFBFF" ) port map ( I0 => CC_detect_dlyd1_i_4_n_0, I1 => \^q\(23), I2 => \^q\(22), I3 => rxdatavalid_to_fifo_i, I4 => CC_detect_dlyd1_i_3_n_0, O => CC_detect_pulse_r_i_2_n_0 ); \descrambler[57]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => in0, O => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[0]\: unisim.vcomponents.FDSE port map ( C => \out\, CE => E(0), D => \descrambler_reg[31]_0\(0), Q => poly(32), S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[10]\: unisim.vcomponents.FDSE port map ( C => \out\, CE => E(0), D => \descrambler_reg[31]_0\(10), Q => poly(42), S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[11]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => \descrambler_reg[31]_0\(11), Q => poly(43), R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[12]\: unisim.vcomponents.FDSE port map ( C => \out\, CE => E(0), D => \descrambler_reg[31]_0\(12), Q => poly(44), S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[13]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => \descrambler_reg[31]_0\(13), Q => poly(45), R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[14]\: unisim.vcomponents.FDSE port map ( C => \out\, CE => E(0), D => \descrambler_reg[31]_0\(14), Q => poly(46), S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[15]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => \descrambler_reg[31]_0\(15), Q => poly(47), R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[16]\: unisim.vcomponents.FDSE port map ( C => \out\, CE => E(0), D => \descrambler_reg[31]_0\(16), Q => poly(48), S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[17]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => \descrambler_reg[31]_0\(17), Q => poly(49), R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[18]\: unisim.vcomponents.FDSE port map ( C => \out\, CE => E(0), D => \descrambler_reg[31]_0\(18), Q => poly(50), S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[19]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => \descrambler_reg[31]_0\(19), Q => poly(51), R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[1]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => \descrambler_reg[31]_0\(1), Q => poly(33), R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[20]\: unisim.vcomponents.FDSE port map ( C => \out\, CE => E(0), D => \descrambler_reg[31]_0\(20), Q => \^descrambler_reg[39]_0\(0), S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[21]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => \descrambler_reg[31]_0\(21), Q => poly(53), R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[22]\: unisim.vcomponents.FDSE port map ( C => \out\, CE => E(0), D => \descrambler_reg[31]_0\(22), Q => poly(54), S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[23]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => \descrambler_reg[31]_0\(23), Q => poly(55), R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[24]\: unisim.vcomponents.FDSE port map ( C => \out\, CE => E(0), D => \descrambler_reg[31]_0\(24), Q => poly(56), S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[25]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => \descrambler_reg[31]_0\(25), Q => poly(57), R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[26]\: unisim.vcomponents.FDSE port map ( C => \out\, CE => E(0), D => \descrambler_reg[31]_0\(26), Q => p_67_in, S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[27]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => \descrambler_reg[31]_0\(27), Q => p_69_in, R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[28]\: unisim.vcomponents.FDSE port map ( C => \out\, CE => E(0), D => \descrambler_reg[31]_0\(28), Q => p_73_in, S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[29]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => \descrambler_reg[31]_0\(29), Q => p_75_in, R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[2]\: unisim.vcomponents.FDSE port map ( C => \out\, CE => E(0), D => \descrambler_reg[31]_0\(2), Q => poly(34), S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[30]\: unisim.vcomponents.FDSE port map ( C => \out\, CE => E(0), D => \descrambler_reg[31]_0\(30), Q => p_78_in, S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[31]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => \descrambler_reg[31]_0\(31), Q => p_80_in, R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[32]\: unisim.vcomponents.FDSE port map ( C => \out\, CE => E(0), D => poly(32), Q => p_84_in, S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[33]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => poly(33), Q => p_86_in, R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[34]\: unisim.vcomponents.FDSE port map ( C => \out\, CE => E(0), D => poly(34), Q => p_89_in, S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[35]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => poly(35), Q => p_91_in, R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[36]\: unisim.vcomponents.FDSE port map ( C => \out\, CE => E(0), D => poly(36), Q => p_95_in, S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[37]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => poly(37), Q => p_97_in, R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[38]\: unisim.vcomponents.FDSE port map ( C => \out\, CE => E(0), D => poly(38), Q => p_100_in, S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[39]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => poly(39), Q => \^descrambler_reg[39]_0\(1), R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[3]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => \descrambler_reg[31]_0\(3), Q => poly(35), R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[40]\: unisim.vcomponents.FDSE port map ( C => \out\, CE => E(0), D => poly(40), Q => \descrambler_reg_n_0_[40]\, S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[41]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => poly(41), Q => \descrambler_reg_n_0_[41]\, R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[42]\: unisim.vcomponents.FDSE port map ( C => \out\, CE => E(0), D => poly(42), Q => \descrambler_reg_n_0_[42]\, S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[43]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => poly(43), Q => \descrambler_reg_n_0_[43]\, R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[44]\: unisim.vcomponents.FDSE port map ( C => \out\, CE => E(0), D => poly(44), Q => \descrambler_reg_n_0_[44]\, S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[45]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => poly(45), Q => \descrambler_reg_n_0_[45]\, R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[46]\: unisim.vcomponents.FDSE port map ( C => \out\, CE => E(0), D => poly(46), Q => \descrambler_reg_n_0_[46]\, S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[47]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => poly(47), Q => \descrambler_reg_n_0_[47]\, R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[48]\: unisim.vcomponents.FDSE port map ( C => \out\, CE => E(0), D => poly(48), Q => \descrambler_reg_n_0_[48]\, S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[49]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => poly(49), Q => \descrambler_reg_n_0_[49]\, R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[4]\: unisim.vcomponents.FDSE port map ( C => \out\, CE => E(0), D => \descrambler_reg[31]_0\(4), Q => poly(36), S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[50]\: unisim.vcomponents.FDSE port map ( C => \out\, CE => E(0), D => poly(50), Q => \descrambler_reg_n_0_[50]\, S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[51]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => poly(51), Q => \descrambler_reg_n_0_[51]\, R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[52]\: unisim.vcomponents.FDSE port map ( C => \out\, CE => E(0), D => \^descrambler_reg[39]_0\(0), Q => \descrambler_reg_n_0_[52]\, S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[53]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => poly(53), Q => \descrambler_reg_n_0_[53]\, R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[54]\: unisim.vcomponents.FDSE port map ( C => \out\, CE => E(0), D => poly(54), Q => \descrambler_reg_n_0_[54]\, S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[55]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => poly(55), Q => \descrambler_reg_n_0_[55]\, R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[56]\: unisim.vcomponents.FDSE port map ( C => \out\, CE => E(0), D => poly(56), Q => \descrambler_reg_n_0_[56]\, S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[57]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => poly(57), Q => \descrambler_reg_n_0_[57]\, R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[5]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => \descrambler_reg[31]_0\(5), Q => poly(37), R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[6]\: unisim.vcomponents.FDSE port map ( C => \out\, CE => E(0), D => \descrambler_reg[31]_0\(6), Q => poly(38), S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[7]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => \descrambler_reg[31]_0\(7), Q => poly(39), R => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[8]\: unisim.vcomponents.FDSE port map ( C => \out\, CE => E(0), D => \descrambler_reg[31]_0\(8), Q => poly(40), S => \descrambler[57]_i_1_n_0\ ); \descrambler_reg[9]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => \descrambler_reg[31]_0\(9), Q => poly(41), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => poly(39), I1 => \descrambler_reg[31]_0\(0), I2 => p_67_in, O => unscrambled_data_i0 ); \unscrambled_data_i[10]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => poly(49), I1 => \descrambler_reg[31]_0\(10), I2 => p_95_in, O => unscrambled_data_i040_out ); \unscrambled_data_i[11]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => poly(50), I1 => \descrambler_reg[31]_0\(11), I2 => p_97_in, O => unscrambled_data_i044_out ); \unscrambled_data_i[12]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => poly(51), I1 => \descrambler_reg[31]_0\(12), I2 => p_100_in, O => unscrambled_data_i048_out ); \unscrambled_data_i[14]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => poly(53), I1 => \descrambler_reg[31]_0\(14), I2 => \descrambler_reg_n_0_[40]\, O => tempData(17) ); \unscrambled_data_i[15]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => poly(54), I1 => \descrambler_reg[31]_0\(15), I2 => \descrambler_reg_n_0_[41]\, O => tempData(16) ); \unscrambled_data_i[16]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => poly(55), I1 => \descrambler_reg[31]_0\(16), I2 => \descrambler_reg_n_0_[42]\, O => tempData(15) ); \unscrambled_data_i[17]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => poly(56), I1 => \descrambler_reg[31]_0\(17), I2 => \descrambler_reg_n_0_[43]\, O => tempData(14) ); \unscrambled_data_i[18]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => poly(57), I1 => \descrambler_reg[31]_0\(18), I2 => \descrambler_reg_n_0_[44]\, O => tempData(13) ); \unscrambled_data_i[19]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_67_in, I1 => \descrambler_reg[31]_0\(19), I2 => \descrambler_reg_n_0_[45]\, O => tempData(12) ); \unscrambled_data_i[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => poly(40), I1 => \descrambler_reg[31]_0\(1), I2 => p_69_in, O => unscrambled_data_i04_out ); \unscrambled_data_i[20]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_69_in, I1 => \descrambler_reg[31]_0\(20), I2 => \descrambler_reg_n_0_[46]\, O => tempData(11) ); \unscrambled_data_i[21]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_73_in, I1 => \descrambler_reg[31]_0\(21), I2 => \descrambler_reg_n_0_[47]\, O => tempData(10) ); \unscrambled_data_i[22]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_75_in, I1 => \descrambler_reg[31]_0\(22), I2 => \descrambler_reg_n_0_[48]\, O => tempData(9) ); \unscrambled_data_i[23]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_78_in, I1 => \descrambler_reg[31]_0\(23), I2 => \descrambler_reg_n_0_[49]\, O => tempData(8) ); \unscrambled_data_i[24]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_80_in, I1 => \descrambler_reg[31]_0\(24), I2 => \descrambler_reg_n_0_[50]\, O => tempData(7) ); \unscrambled_data_i[25]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_84_in, I1 => \descrambler_reg[31]_0\(25), I2 => \descrambler_reg_n_0_[51]\, O => tempData(6) ); \unscrambled_data_i[26]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_86_in, I1 => \descrambler_reg[31]_0\(26), I2 => \descrambler_reg_n_0_[52]\, O => tempData(5) ); \unscrambled_data_i[27]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_89_in, I1 => \descrambler_reg[31]_0\(27), I2 => \descrambler_reg_n_0_[53]\, O => tempData(4) ); \unscrambled_data_i[28]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_91_in, I1 => \descrambler_reg[31]_0\(28), I2 => \descrambler_reg_n_0_[54]\, O => tempData(3) ); \unscrambled_data_i[29]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_95_in, I1 => \descrambler_reg[31]_0\(29), I2 => \descrambler_reg_n_0_[55]\, O => tempData(2) ); \unscrambled_data_i[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => poly(41), I1 => \descrambler_reg[31]_0\(2), I2 => p_73_in, O => unscrambled_data_i08_out ); \unscrambled_data_i[30]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_97_in, I1 => \descrambler_reg[31]_0\(30), I2 => \descrambler_reg_n_0_[56]\, O => tempData(1) ); \unscrambled_data_i[31]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_100_in, I1 => \descrambler_reg[31]_0\(31), I2 => \descrambler_reg_n_0_[57]\, O => tempData(0) ); \unscrambled_data_i[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => poly(42), I1 => \descrambler_reg[31]_0\(3), I2 => p_75_in, O => unscrambled_data_i012_out ); \unscrambled_data_i[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => poly(43), I1 => \descrambler_reg[31]_0\(4), I2 => p_78_in, O => unscrambled_data_i016_out ); \unscrambled_data_i[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => poly(44), I1 => \descrambler_reg[31]_0\(5), I2 => p_80_in, O => unscrambled_data_i020_out ); \unscrambled_data_i[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => poly(45), I1 => \descrambler_reg[31]_0\(6), I2 => p_84_in, O => unscrambled_data_i024_out ); \unscrambled_data_i[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => poly(46), I1 => \descrambler_reg[31]_0\(7), I2 => p_86_in, O => unscrambled_data_i028_out ); \unscrambled_data_i[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => poly(47), I1 => \descrambler_reg[31]_0\(8), I2 => p_89_in, O => unscrambled_data_i032_out ); \unscrambled_data_i[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => poly(48), I1 => \descrambler_reg[31]_0\(9), I2 => p_91_in, O => unscrambled_data_i036_out ); \unscrambled_data_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => unscrambled_data_i0, Q => \^q\(0), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => unscrambled_data_i040_out, Q => \^q\(10), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => unscrambled_data_i044_out, Q => \^q\(11), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => unscrambled_data_i048_out, Q => \^q\(12), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => \unscrambled_data_i_reg[13]_0\(0), Q => \^q\(13), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[14]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => tempData(17), Q => \^q\(14), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[15]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => tempData(16), Q => \^q\(15), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[16]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => tempData(15), Q => \^q\(16), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[17]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => tempData(14), Q => \^q\(17), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[18]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => tempData(13), Q => \^q\(18), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[19]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => tempData(12), Q => \^q\(19), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => unscrambled_data_i04_out, Q => \^q\(1), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[20]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => tempData(11), Q => \^q\(20), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[21]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => tempData(10), Q => \^q\(21), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[22]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => tempData(9), Q => \^q\(22), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[23]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => tempData(8), Q => \^q\(23), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[24]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => tempData(7), Q => \^q\(24), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[25]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => tempData(6), Q => \^q\(25), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[26]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => tempData(5), Q => \^q\(26), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[27]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => tempData(4), Q => \^q\(27), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[28]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => tempData(3), Q => \^q\(28), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[29]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => tempData(2), Q => \^q\(29), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => unscrambled_data_i08_out, Q => \^q\(2), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[30]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => tempData(1), Q => \^q\(30), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[31]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => tempData(0), Q => \^q\(31), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => unscrambled_data_i012_out, Q => \^q\(3), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => unscrambled_data_i016_out, Q => \^q\(4), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => unscrambled_data_i020_out, Q => \^q\(5), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => unscrambled_data_i024_out, Q => \^q\(6), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => unscrambled_data_i028_out, Q => \^q\(7), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => unscrambled_data_i032_out, Q => \^q\(8), R => \descrambler[57]_i_1_n_0\ ); \unscrambled_data_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => unscrambled_data_i036_out, Q => \^q\(9), R => \descrambler[57]_i_1_n_0\ ); \wdth_conv_1stage[38]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"BA" ) port map ( I0 => CB_detect_dlyd0p5, I1 => \wdth_conv_1stage[38]_i_2_n_0\, I2 => CC_detect_dlyd1_i_2_n_0, O => D(0) ); \wdth_conv_1stage[38]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFBFF" ) port map ( I0 => CC_detect_dlyd1_i_3_n_0, I1 => rxdatavalid_to_fifo_i, I2 => \^q\(23), I3 => \^q\(22), I4 => CC_detect_dlyd1_i_4_n_0, O => \wdth_conv_1stage[38]_i_2_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_ERR_DETECT is port ( hard_err_i : out STD_LOGIC; SOFT_ERR_reg_0 : out STD_LOGIC; SOFT_ERR_reg_1 : in STD_LOGIC; \out\ : in STD_LOGIC; HARD_ERR_reg_0 : in STD_LOGIC; channel_up_tx_if : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_ERR_DETECT; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_ERR_DETECT is signal soft_err_i : STD_LOGIC; begin HARD_ERR_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => HARD_ERR_reg_0, Q => hard_err_i, R => '0' ); SOFT_ERR_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => SOFT_ERR_reg_1, Q => soft_err_i, R => '0' ); soft_err_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => soft_err_i, I1 => channel_up_tx_if, O => SOFT_ERR_reg_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_GTX is port ( in0 : out STD_LOGIC; drprdy_out : out STD_LOGIC; txn : out STD_LOGIC; txp : out STD_LOGIC; pre_rxdatavalid_i : out STD_LOGIC; pre_rxheadervalid_i : out STD_LOGIC; rxrecclk_from_gtx_i : out STD_LOGIC; \cpllpd_wait_reg[95]_0\ : out STD_LOGIC; tx_out_clk : out STD_LOGIC; \cpllpd_wait_reg[95]_1\ : out STD_LOGIC; drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); TXBUFSTATUS : out STD_LOGIC_VECTOR ( 0 to 0 ); RXBUFSTATUS : out STD_LOGIC_VECTOR ( 0 to 0 ); RXHEADER : out STD_LOGIC_VECTOR ( 1 downto 0 ); RXDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); ack_flag : out STD_LOGIC; ack_flag_reg_0 : in STD_LOGIC; drp_clk_in : in STD_LOGIC; drpen_in : in STD_LOGIC; drpwe_in : in STD_LOGIC; refclk1_in : in STD_LOGIC; SR : in STD_LOGIC_VECTOR ( 0 to 0 ); gttxreset_t : in STD_LOGIC; rxn : in STD_LOGIC; rxp : in STD_LOGIC; gt_qpllclk_quad1_out : in STD_LOGIC; gt_qpllrefclk_quad1_out : in STD_LOGIC; gt_rxcdrovrden_in : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 0 to 0 ); \out\ : in STD_LOGIC; rxuserrdy_t : in STD_LOGIC; s_level_out_d1_aurora_64b66b_0_cdc_to_reg : in STD_LOGIC; txuserrdy_t : in STD_LOGIC; s_level_out_d1_aurora_64b66b_0_cdc_to_reg_0 : in STD_LOGIC; s_level_out_d1_aurora_64b66b_0_cdc_to_reg_1 : in STD_LOGIC; drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); loopback : in STD_LOGIC_VECTOR ( 2 downto 0 ); Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); SCRAMBLED_DATA_OUT : in STD_LOGIC_VECTOR ( 63 downto 0 ); s_level_out_d1_aurora_64b66b_0_cdc_to_reg_2 : in STD_LOGIC_VECTOR ( 6 downto 0 ); drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 ); flag2_reg_0 : in STD_LOGIC; gt_cpllreset_i : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_GTX; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_GTX is signal \^ack_flag\ : STD_LOGIC; signal ack_flag_i_1_n_0 : STD_LOGIC; signal ack_sync1 : STD_LOGIC; signal ack_sync2 : STD_LOGIC; signal ack_sync3 : STD_LOGIC; signal ack_sync4 : STD_LOGIC; signal ack_sync5 : STD_LOGIC; signal ack_sync6 : STD_LOGIC; signal cpll_pd_i : STD_LOGIC; signal \cpll_reset_i__0\ : STD_LOGIC; signal \cpllpd_wait_reg[31]_srl32_n_1\ : STD_LOGIC; signal \cpllpd_wait_reg[63]_srl32_n_1\ : STD_LOGIC; signal \cpllpd_wait_reg[94]_srl31_n_0\ : STD_LOGIC; signal cpllreset_ovrd_i : STD_LOGIC; signal \cpllreset_wait_reg[126]_srl31_n_0\ : STD_LOGIC; signal \cpllreset_wait_reg[31]_srl32_n_1\ : STD_LOGIC; signal \cpllreset_wait_reg[63]_srl32_n_1\ : STD_LOGIC; signal \cpllreset_wait_reg[95]_srl32_n_1\ : STD_LOGIC; signal data_sync1 : STD_LOGIC; signal data_sync2 : STD_LOGIC; signal data_sync3 : STD_LOGIC; signal data_sync4 : STD_LOGIC; signal data_sync5 : STD_LOGIC; signal data_sync6 : STD_LOGIC; signal flag : STD_LOGIC; signal flag2 : STD_LOGIC; signal flag_i_1_n_0 : STD_LOGIC; signal gt_cpllrefclklost_i : STD_LOGIC; signal gtxe2_i_n_0 : STD_LOGIC; signal gtxe2_i_n_11 : STD_LOGIC; signal gtxe2_i_n_170 : STD_LOGIC; signal gtxe2_i_n_171 : STD_LOGIC; signal gtxe2_i_n_172 : STD_LOGIC; signal gtxe2_i_n_173 : STD_LOGIC; signal gtxe2_i_n_174 : STD_LOGIC; signal gtxe2_i_n_175 : STD_LOGIC; signal gtxe2_i_n_176 : STD_LOGIC; signal gtxe2_i_n_177 : STD_LOGIC; signal gtxe2_i_n_178 : STD_LOGIC; signal gtxe2_i_n_179 : STD_LOGIC; signal gtxe2_i_n_180 : STD_LOGIC; signal gtxe2_i_n_181 : STD_LOGIC; signal gtxe2_i_n_182 : STD_LOGIC; signal gtxe2_i_n_183 : STD_LOGIC; signal gtxe2_i_n_184 : STD_LOGIC; signal gtxe2_i_n_27 : STD_LOGIC; signal gtxe2_i_n_38 : STD_LOGIC; signal gtxe2_i_n_39 : STD_LOGIC; signal gtxe2_i_n_4 : STD_LOGIC; signal gtxe2_i_n_81 : STD_LOGIC; signal gtxe2_i_n_83 : STD_LOGIC; signal gtxe2_i_n_84 : STD_LOGIC; signal \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC; signal \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC; signal \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC; signal \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC; signal \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\ : STD_LOGIC; signal NLW_gtxe2_i_GTREFCLKMONITOR_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_PHYSTATUS_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_RXBYTEISALIGNED_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_RXBYTEREALIGN_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_RXCHANBONDSEQ_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_RXCHANISALIGNED_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_RXCHANREALIGN_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_RXCOMINITDET_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_RXCOMMADET_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_RXCOMSASDET_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_RXCOMWAKEDET_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_RXDLYSRESETDONE_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_RXELECIDLE_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_RXOUTCLKFABRIC_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_RXOUTCLKPCS_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_RXPHALIGNDONE_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_RXQPISENN_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_RXQPISENP_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_RXRATEDONE_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_RXSTARTOFSEQ_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_RXVALID_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_TXCOMFINISH_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_TXDLYSRESETDONE_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_TXGEARBOXREADY_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_TXPHALIGNDONE_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_TXPHINITDONE_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_TXQPISENN_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_TXQPISENP_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_TXRATEDONE_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_i_PCSRSVDOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); signal NLW_gtxe2_i_RXCHARISCOMMA_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_gtxe2_i_RXCHARISK_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_gtxe2_i_RXCHBONDO_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_gtxe2_i_RXCLKCORCNT_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_gtxe2_i_RXDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 32 ); signal NLW_gtxe2_i_RXDISPERR_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_gtxe2_i_RXHEADER_UNCONNECTED : STD_LOGIC_VECTOR ( 2 to 2 ); signal NLW_gtxe2_i_RXNOTINTABLE_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_gtxe2_i_RXPHMONITOR_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_gtxe2_i_RXPHSLIPMONITOR_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_gtxe2_i_RXSTATUS_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_gtxe2_i_TSTOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 ); attribute ASYNC_REG : boolean; attribute ASYNC_REG of ack_sync_reg1 : label is std.standard.true; attribute BOX_TYPE : string; attribute BOX_TYPE of ack_sync_reg1 : label is "PRIMITIVE"; attribute SHREG_EXTRACT : string; attribute SHREG_EXTRACT of ack_sync_reg1 : label is "no"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of ack_sync_reg1 : label is "FD"; attribute ASYNC_REG of ack_sync_reg2 : label is std.standard.true; attribute BOX_TYPE of ack_sync_reg2 : label is "PRIMITIVE"; attribute SHREG_EXTRACT of ack_sync_reg2 : label is "no"; attribute XILINX_LEGACY_PRIM of ack_sync_reg2 : label is "FD"; attribute ASYNC_REG of ack_sync_reg3 : label is std.standard.true; attribute BOX_TYPE of ack_sync_reg3 : label is "PRIMITIVE"; attribute SHREG_EXTRACT of ack_sync_reg3 : label is "no"; attribute XILINX_LEGACY_PRIM of ack_sync_reg3 : label is "FD"; attribute ASYNC_REG of ack_sync_reg4 : label is std.standard.true; attribute BOX_TYPE of ack_sync_reg4 : label is "PRIMITIVE"; attribute SHREG_EXTRACT of ack_sync_reg4 : label is "no"; attribute XILINX_LEGACY_PRIM of ack_sync_reg4 : label is "FD"; attribute ASYNC_REG of ack_sync_reg5 : label is std.standard.true; attribute BOX_TYPE of ack_sync_reg5 : label is "PRIMITIVE"; attribute SHREG_EXTRACT of ack_sync_reg5 : label is "no"; attribute XILINX_LEGACY_PRIM of ack_sync_reg5 : label is "FD"; attribute ASYNC_REG of ack_sync_reg6 : label is std.standard.true; attribute BOX_TYPE of ack_sync_reg6 : label is "PRIMITIVE"; attribute SHREG_EXTRACT of ack_sync_reg6 : label is "no"; attribute XILINX_LEGACY_PRIM of ack_sync_reg6 : label is "FD"; attribute srl_bus_name : string; attribute srl_bus_name of \cpllpd_wait_reg[31]_srl32\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gtx_inst/cpllpd_wait_reg "; attribute srl_name : string; attribute srl_name of \cpllpd_wait_reg[31]_srl32\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gtx_inst/cpllpd_wait_reg[31]_srl32 "; attribute srl_bus_name of \cpllpd_wait_reg[63]_srl32\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gtx_inst/cpllpd_wait_reg "; attribute srl_name of \cpllpd_wait_reg[63]_srl32\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gtx_inst/cpllpd_wait_reg[63]_srl32 "; attribute srl_bus_name of \cpllpd_wait_reg[94]_srl31\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gtx_inst/cpllpd_wait_reg "; attribute srl_name of \cpllpd_wait_reg[94]_srl31\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gtx_inst/cpllpd_wait_reg[94]_srl31 "; attribute equivalent_register_removal : string; attribute equivalent_register_removal of \cpllpd_wait_reg[95]\ : label is "no"; attribute srl_bus_name of \cpllreset_wait_reg[126]_srl31\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gtx_inst/cpllreset_wait_reg "; attribute srl_name of \cpllreset_wait_reg[126]_srl31\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gtx_inst/cpllreset_wait_reg[126]_srl31 "; attribute equivalent_register_removal of \cpllreset_wait_reg[127]\ : label is "no"; attribute srl_bus_name of \cpllreset_wait_reg[31]_srl32\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gtx_inst/cpllreset_wait_reg "; attribute srl_name of \cpllreset_wait_reg[31]_srl32\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gtx_inst/cpllreset_wait_reg[31]_srl32 "; attribute srl_bus_name of \cpllreset_wait_reg[63]_srl32\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gtx_inst/cpllreset_wait_reg "; attribute srl_name of \cpllreset_wait_reg[63]_srl32\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gtx_inst/cpllreset_wait_reg[63]_srl32 "; attribute srl_bus_name of \cpllreset_wait_reg[95]_srl32\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gtx_inst/cpllreset_wait_reg "; attribute srl_name of \cpllreset_wait_reg[95]_srl32\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/aurora_64b66b_0_multi_gt_i/aurora_64b66b_0_gtx_inst/cpllreset_wait_reg[95]_srl32 "; attribute ASYNC_REG of data_sync_reg1 : label is std.standard.true; attribute BOX_TYPE of data_sync_reg1 : label is "PRIMITIVE"; attribute SHREG_EXTRACT of data_sync_reg1 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg1 : label is "FD"; attribute ASYNC_REG of data_sync_reg2 : label is std.standard.true; attribute BOX_TYPE of data_sync_reg2 : label is "PRIMITIVE"; attribute SHREG_EXTRACT of data_sync_reg2 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg2 : label is "FD"; attribute ASYNC_REG of data_sync_reg3 : label is std.standard.true; attribute BOX_TYPE of data_sync_reg3 : label is "PRIMITIVE"; attribute SHREG_EXTRACT of data_sync_reg3 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg3 : label is "FD"; attribute ASYNC_REG of data_sync_reg4 : label is std.standard.true; attribute BOX_TYPE of data_sync_reg4 : label is "PRIMITIVE"; attribute SHREG_EXTRACT of data_sync_reg4 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg4 : label is "FD"; attribute ASYNC_REG of data_sync_reg5 : label is std.standard.true; attribute BOX_TYPE of data_sync_reg5 : label is "PRIMITIVE"; attribute SHREG_EXTRACT of data_sync_reg5 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg5 : label is "FD"; attribute ASYNC_REG of data_sync_reg6 : label is std.standard.true; attribute BOX_TYPE of data_sync_reg6 : label is "PRIMITIVE"; attribute SHREG_EXTRACT of data_sync_reg6 : label is "no"; attribute XILINX_LEGACY_PRIM of data_sync_reg6 : label is "FD"; attribute BOX_TYPE of gtxe2_i : label is "PRIMITIVE"; begin ack_flag <= \^ack_flag\; ack_flag_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"FF90" ) port map ( I0 => ack_sync6, I1 => ack_sync5, I2 => \^ack_flag\, I3 => flag2, O => ack_flag_i_1_n_0 ); ack_flag_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ack_flag_reg_0, CE => '1', D => ack_flag_i_1_n_0, Q => \^ack_flag\, R => '0' ); ack_sync_reg1: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ack_flag_reg_0, CE => '1', D => data_sync6, Q => ack_sync1, R => '0' ); ack_sync_reg2: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ack_flag_reg_0, CE => '1', D => ack_sync1, Q => ack_sync2, R => '0' ); ack_sync_reg3: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ack_flag_reg_0, CE => '1', D => ack_sync2, Q => ack_sync3, R => '0' ); ack_sync_reg4: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ack_flag_reg_0, CE => '1', D => ack_sync3, Q => ack_sync4, R => '0' ); ack_sync_reg5: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ack_flag_reg_0, CE => '1', D => ack_sync4, Q => ack_sync5, R => '0' ); ack_sync_reg6: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ack_flag_reg_0, CE => '1', D => ack_sync5, Q => ack_sync6, R => '0' ); cpll_reset_i: unisim.vcomponents.LUT3 generic map( INIT => X"F6" ) port map ( I0 => data_sync5, I1 => data_sync6, I2 => cpllreset_ovrd_i, O => \cpll_reset_i__0\ ); \cpllpd_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"FFFFFFFF" ) port map ( A(4 downto 0) => B"11111", CE => '1', CLK => refclk1_in, D => '0', Q => \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\, Q31 => \cpllpd_wait_reg[31]_srl32_n_1\ ); \cpllpd_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"FFFFFFFF" ) port map ( A(4 downto 0) => B"11111", CE => '1', CLK => refclk1_in, D => \cpllpd_wait_reg[31]_srl32_n_1\, Q => \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\, Q31 => \cpllpd_wait_reg[63]_srl32_n_1\ ); \cpllpd_wait_reg[94]_srl31\: unisim.vcomponents.SRLC32E generic map( INIT => X"7FFFFFFF" ) port map ( A(4 downto 0) => B"11110", CE => '1', CLK => refclk1_in, D => \cpllpd_wait_reg[63]_srl32_n_1\, Q => \cpllpd_wait_reg[94]_srl31_n_0\, Q31 => \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\ ); \cpllpd_wait_reg[95]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => refclk1_in, CE => '1', D => \cpllpd_wait_reg[94]_srl31_n_0\, Q => cpll_pd_i, R => '0' ); \cpllreset_wait_reg[126]_srl31\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => B"11110", CE => '1', CLK => refclk1_in, D => \cpllreset_wait_reg[95]_srl32_n_1\, Q => \cpllreset_wait_reg[126]_srl31_n_0\, Q31 => \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\ ); \cpllreset_wait_reg[127]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => refclk1_in, CE => '1', D => \cpllreset_wait_reg[126]_srl31_n_0\, Q => cpllreset_ovrd_i, R => '0' ); \cpllreset_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"000000FF" ) port map ( A(4 downto 0) => B"11111", CE => '1', CLK => refclk1_in, D => '0', Q => \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\, Q31 => \cpllreset_wait_reg[31]_srl32_n_1\ ); \cpllreset_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => B"11111", CE => '1', CLK => refclk1_in, D => \cpllreset_wait_reg[31]_srl32_n_1\, Q => \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\, Q31 => \cpllreset_wait_reg[63]_srl32_n_1\ ); \cpllreset_wait_reg[95]_srl32\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => B"11111", CE => '1', CLK => refclk1_in, D => \cpllreset_wait_reg[63]_srl32_n_1\, Q => \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\, Q31 => \cpllreset_wait_reg[95]_srl32_n_1\ ); data_sync_reg1: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => refclk1_in, CE => '1', D => flag, Q => data_sync1, R => '0' ); data_sync_reg2: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => refclk1_in, CE => '1', D => data_sync1, Q => data_sync2, R => '0' ); data_sync_reg3: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => refclk1_in, CE => '1', D => data_sync2, Q => data_sync3, R => '0' ); data_sync_reg4: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => refclk1_in, CE => '1', D => data_sync3, Q => data_sync4, R => '0' ); data_sync_reg5: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => refclk1_in, CE => '1', D => data_sync4, Q => data_sync5, R => '0' ); data_sync_reg6: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => refclk1_in, CE => '1', D => data_sync5, Q => data_sync6, R => '0' ); flag2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ack_flag_reg_0, CE => '1', D => flag2_reg_0, Q => flag2, R => '0' ); flag_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"B4" ) port map ( I0 => \^ack_flag\, I1 => gt_cpllreset_i, I2 => flag, O => flag_i_1_n_0 ); flag_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => ack_flag_reg_0, CE => '1', D => flag_i_1_n_0, Q => flag, R => '0' ); gtxe2_i: unisim.vcomponents.GTXE2_CHANNEL generic map( ALIGN_COMMA_DOUBLE => "FALSE", ALIGN_COMMA_ENABLE => B"1111111111", ALIGN_COMMA_WORD => 1, ALIGN_MCOMMA_DET => "FALSE", ALIGN_MCOMMA_VALUE => B"1010000011", ALIGN_PCOMMA_DET => "FALSE", ALIGN_PCOMMA_VALUE => B"0101111100", CBCC_DATA_SOURCE_SEL => "ENCODED", CHAN_BOND_KEEP_ALIGN => "FALSE", CHAN_BOND_MAX_SKEW => 1, CHAN_BOND_SEQ_1_1 => B"0000000000", CHAN_BOND_SEQ_1_2 => B"0000000000", CHAN_BOND_SEQ_1_3 => B"0000000000", CHAN_BOND_SEQ_1_4 => B"0000000000", CHAN_BOND_SEQ_1_ENABLE => B"1111", CHAN_BOND_SEQ_2_1 => B"0000000000", CHAN_BOND_SEQ_2_2 => B"0000000000", CHAN_BOND_SEQ_2_3 => B"0000000000", CHAN_BOND_SEQ_2_4 => B"0000000000", CHAN_BOND_SEQ_2_ENABLE => B"1111", CHAN_BOND_SEQ_2_USE => "FALSE", CHAN_BOND_SEQ_LEN => 1, CLK_CORRECT_USE => "FALSE", CLK_COR_KEEP_IDLE => "FALSE", CLK_COR_MAX_LAT => 19, CLK_COR_MIN_LAT => 15, CLK_COR_PRECEDENCE => "TRUE", CLK_COR_REPEAT_WAIT => 0, CLK_COR_SEQ_1_1 => B"0100000000", CLK_COR_SEQ_1_2 => B"0000000000", CLK_COR_SEQ_1_3 => B"0000000000", CLK_COR_SEQ_1_4 => B"0000000000", CLK_COR_SEQ_1_ENABLE => B"1111", CLK_COR_SEQ_2_1 => B"0100000000", CLK_COR_SEQ_2_2 => B"0000000000", CLK_COR_SEQ_2_3 => B"0000000000", CLK_COR_SEQ_2_4 => B"0000000000", CLK_COR_SEQ_2_ENABLE => B"1111", CLK_COR_SEQ_2_USE => "FALSE", CLK_COR_SEQ_LEN => 1, CPLL_CFG => X"BC07DC", CPLL_FBDIV => 4, CPLL_FBDIV_45 => 4, CPLL_INIT_CFG => X"00001E", CPLL_LOCK_CFG => X"01E8", CPLL_REFCLK_DIV => 1, DEC_MCOMMA_DETECT => "FALSE", DEC_PCOMMA_DETECT => "FALSE", DEC_VALID_COMMA_ONLY => "FALSE", DMONITOR_CFG => X"000A00", ES_CONTROL => B"000000", ES_ERRDET_EN => "FALSE", ES_EYE_SCAN_EN => "TRUE", ES_HORZ_OFFSET => X"000", ES_PMA_CFG => B"0000000000", ES_PRESCALE => B"00000", ES_QUALIFIER => X"00000000000000000000", ES_QUAL_MASK => X"00000000000000000000", ES_SDATA_MASK => X"00000000000000000000", ES_VERT_OFFSET => B"000000000", FTS_DESKEW_SEQ_ENABLE => B"1111", FTS_LANE_DESKEW_CFG => B"1111", FTS_LANE_DESKEW_EN => "FALSE", GEARBOX_MODE => B"001", IS_CPLLLOCKDETCLK_INVERTED => '0', IS_DRPCLK_INVERTED => '0', IS_GTGREFCLK_INVERTED => '0', IS_RXUSRCLK2_INVERTED => '0', IS_RXUSRCLK_INVERTED => '0', IS_TXPHDLYTSTCLK_INVERTED => '0', IS_TXUSRCLK2_INVERTED => '0', IS_TXUSRCLK_INVERTED => '0', OUTREFCLK_SEL_INV => B"11", PCS_PCIE_EN => "FALSE", PCS_RSVD_ATTR => X"000000000000", PD_TRANS_TIME_FROM_P2 => X"03C", PD_TRANS_TIME_NONE_P2 => X"19", PD_TRANS_TIME_TO_P2 => X"64", PMA_RSV => X"00018480", PMA_RSV2 => X"2050", PMA_RSV3 => B"00", PMA_RSV4 => X"00000000", RXBUFRESET_TIME => B"00001", RXBUF_ADDR_MODE => "FAST", RXBUF_EIDLE_HI_CNT => B"1000", RXBUF_EIDLE_LO_CNT => B"0000", RXBUF_EN => "TRUE", RXBUF_RESET_ON_CB_CHANGE => "TRUE", RXBUF_RESET_ON_COMMAALIGN => "FALSE", RXBUF_RESET_ON_EIDLE => "FALSE", RXBUF_RESET_ON_RATE_CHANGE => "TRUE", RXBUF_THRESH_OVFLW => 61, RXBUF_THRESH_OVRD => "FALSE", RXBUF_THRESH_UNDFLW => 4, RXCDRFREQRESET_TIME => B"00001", RXCDRPHRESET_TIME => B"00001", RXCDR_CFG => X"03000023FF20400020", RXCDR_FR_RESET_ON_EIDLE => '0', RXCDR_HOLD_DURING_EIDLE => '0', RXCDR_LOCK_CFG => B"010101", RXCDR_PH_RESET_ON_EIDLE => '0', RXDFELPMRESET_TIME => B"0001111", RXDLY_CFG => X"001F", RXDLY_LCFG => X"030", RXDLY_TAP_CFG => X"0000", RXGEARBOX_EN => "TRUE", RXISCANRESET_TIME => B"00001", RXLPM_HF_CFG => B"00000011110000", RXLPM_LF_CFG => B"00000011110000", RXOOB_CFG => B"0000110", RXOUT_DIV => 1, RXPCSRESET_TIME => B"00001", RXPHDLY_CFG => X"084020", RXPH_CFG => X"000000", RXPH_MONITOR_SEL => B"00000", RXPMARESET_TIME => B"00011", RXPRBS_ERR_LOOPBACK => '0', RXSLIDE_AUTO_WAIT => 7, RXSLIDE_MODE => "OFF", RX_BIAS_CFG => B"000000000100", RX_BUFFER_CFG => B"000000", RX_CLK25_DIV => 7, RX_CLKMUX_PD => '1', RX_CM_SEL => B"11", RX_CM_TRIM => B"010", RX_DATA_WIDTH => 32, RX_DDI_SEL => B"000000", RX_DEBUG_CFG => B"000000000000", RX_DEFER_RESET_BUF_EN => "TRUE", RX_DFE_GAIN_CFG => X"020FEA", RX_DFE_H2_CFG => B"000000000000", RX_DFE_H3_CFG => B"000001000000", RX_DFE_H4_CFG => B"00011110000", RX_DFE_H5_CFG => B"00011100000", RX_DFE_KL_CFG => B"0000011111110", RX_DFE_KL_CFG2 => X"301148AC", RX_DFE_LPM_CFG => X"0954", RX_DFE_LPM_HOLD_DURING_EIDLE => '0', RX_DFE_UT_CFG => B"10001111000000000", RX_DFE_VP_CFG => B"00011111100000011", RX_DFE_XYD_CFG => B"0000000000000", RX_DISPERR_SEQ_MATCH => "FALSE", RX_INT_DATAWIDTH => 1, RX_OS_CFG => B"0000010000000", RX_SIG_VALID_DLY => 10, RX_XCLK_SEL => "RXREC", SAS_MAX_COM => 64, SAS_MIN_COM => 36, SATA_BURST_SEQ_LEN => B"0101", SATA_BURST_VAL => B"100", SATA_CPLL_CFG => "VCO_3000MHZ", SATA_EIDLE_VAL => B"100", SATA_MAX_BURST => 8, SATA_MAX_INIT => 21, SATA_MAX_WAKE => 7, SATA_MIN_BURST => 4, SATA_MIN_INIT => 12, SATA_MIN_WAKE => 4, SHOW_REALIGN_COMMA => "FALSE", SIM_CPLLREFCLK_SEL => B"001", SIM_RECEIVER_DETECT_PASS => "TRUE", SIM_RESET_SPEEDUP => "TRUE", SIM_TX_EIDLE_DRIVE_LEVEL => "X", SIM_VERSION => "4.0", TERM_RCAL_CFG => B"10000", TERM_RCAL_OVRD => '0', TRANS_TIME_RATE => X"0E", TST_RSV => X"00000000", TXBUF_EN => "TRUE", TXBUF_RESET_ON_RATE_CHANGE => "TRUE", TXDLY_CFG => X"001F", TXDLY_LCFG => X"030", TXDLY_TAP_CFG => X"0000", TXGEARBOX_EN => "TRUE", TXOUT_DIV => 1, TXPCSRESET_TIME => B"00001", TXPHDLY_CFG => X"084020", TXPH_CFG => X"0780", TXPH_MONITOR_SEL => B"00000", TXPMARESET_TIME => B"00001", TX_CLK25_DIV => 7, TX_CLKMUX_PD => '1', TX_DATA_WIDTH => 64, TX_DEEMPH0 => B"00000", TX_DEEMPH1 => B"00000", TX_DRIVE_MODE => "DIRECT", TX_EIDLE_ASSERT_DELAY => B"110", TX_EIDLE_DEASSERT_DELAY => B"100", TX_INT_DATAWIDTH => 1, TX_LOOPBACK_DRIVE_HIZ => "FALSE", TX_MAINCURSOR_SEL => '0', TX_MARGIN_FULL_0 => B"1001110", TX_MARGIN_FULL_1 => B"1001001", TX_MARGIN_FULL_2 => B"1000101", TX_MARGIN_FULL_3 => B"1000010", TX_MARGIN_FULL_4 => B"1000000", TX_MARGIN_LOW_0 => B"1000110", TX_MARGIN_LOW_1 => B"1000100", TX_MARGIN_LOW_2 => B"1000010", TX_MARGIN_LOW_3 => B"1000000", TX_MARGIN_LOW_4 => B"1000000", TX_PREDRIVER_MODE => '0', TX_QPI_STATUS_EN => '0', TX_RXDETECT_CFG => X"1832", TX_RXDETECT_REF => B"100", TX_XCLK_SEL => "TXOUT", UCODEER_CLR => '0' ) port map ( CFGRESET => '0', CLKRSVD(3 downto 0) => B"0000", CPLLFBCLKLOST => gtxe2_i_n_0, CPLLLOCK => in0, CPLLLOCKDETCLK => ack_flag_reg_0, CPLLLOCKEN => '1', CPLLPD => cpll_pd_i, CPLLREFCLKLOST => gt_cpllrefclklost_i, CPLLREFCLKSEL(2 downto 0) => B"001", CPLLRESET => \cpll_reset_i__0\, DMONITOROUT(7) => gtxe2_i_n_177, DMONITOROUT(6) => gtxe2_i_n_178, DMONITOROUT(5) => gtxe2_i_n_179, DMONITOROUT(4) => gtxe2_i_n_180, DMONITOROUT(3) => gtxe2_i_n_181, DMONITOROUT(2) => gtxe2_i_n_182, DMONITOROUT(1) => gtxe2_i_n_183, DMONITOROUT(0) => gtxe2_i_n_184, DRPADDR(8 downto 0) => drpaddr_in(8 downto 0), DRPCLK => drp_clk_in, DRPDI(15 downto 0) => drpdi_in(15 downto 0), DRPDO(15 downto 0) => drpdo_out(15 downto 0), DRPEN => drpen_in, DRPRDY => drprdy_out, DRPWE => drpwe_in, EYESCANDATAERROR => gtxe2_i_n_4, EYESCANMODE => '0', EYESCANRESET => '0', EYESCANTRIGGER => '0', GTGREFCLK => '0', GTNORTHREFCLK0 => '0', GTNORTHREFCLK1 => '0', GTREFCLK0 => refclk1_in, GTREFCLK1 => '0', GTREFCLKMONITOR => NLW_gtxe2_i_GTREFCLKMONITOR_UNCONNECTED, GTRESETSEL => '0', GTRSVD(15 downto 0) => B"0000000000000000", GTRXRESET => SR(0), GTSOUTHREFCLK0 => '0', GTSOUTHREFCLK1 => '0', GTTXRESET => gttxreset_t, GTXRXN => rxn, GTXRXP => rxp, GTXTXN => txn, GTXTXP => txp, LOOPBACK(2 downto 0) => loopback(2 downto 0), PCSRSVDIN(15 downto 0) => B"0000000000000000", PCSRSVDIN2(4 downto 0) => B"00000", PCSRSVDOUT(15 downto 0) => NLW_gtxe2_i_PCSRSVDOUT_UNCONNECTED(15 downto 0), PHYSTATUS => NLW_gtxe2_i_PHYSTATUS_UNCONNECTED, PMARSVDIN(4 downto 0) => B"00000", PMARSVDIN2(4 downto 0) => B"00000", QPLLCLK => gt_qpllclk_quad1_out, QPLLREFCLK => gt_qpllrefclk_quad1_out, RESETOVRD => '0', RX8B10BEN => '0', RXBUFRESET => '0', RXBUFSTATUS(2) => RXBUFSTATUS(0), RXBUFSTATUS(1) => gtxe2_i_n_83, RXBUFSTATUS(0) => gtxe2_i_n_84, RXBYTEISALIGNED => NLW_gtxe2_i_RXBYTEISALIGNED_UNCONNECTED, RXBYTEREALIGN => NLW_gtxe2_i_RXBYTEREALIGN_UNCONNECTED, RXCDRFREQRESET => '0', RXCDRHOLD => '0', RXCDRLOCK => gtxe2_i_n_11, RXCDROVRDEN => gt_rxcdrovrden_in, RXCDRRESET => '0', RXCDRRESETRSV => '0', RXCHANBONDSEQ => NLW_gtxe2_i_RXCHANBONDSEQ_UNCONNECTED, RXCHANISALIGNED => NLW_gtxe2_i_RXCHANISALIGNED_UNCONNECTED, RXCHANREALIGN => NLW_gtxe2_i_RXCHANREALIGN_UNCONNECTED, RXCHARISCOMMA(7 downto 0) => NLW_gtxe2_i_RXCHARISCOMMA_UNCONNECTED(7 downto 0), RXCHARISK(7 downto 0) => NLW_gtxe2_i_RXCHARISK_UNCONNECTED(7 downto 0), RXCHBONDEN => '0', RXCHBONDI(4 downto 0) => B"00000", RXCHBONDLEVEL(2 downto 0) => B"000", RXCHBONDMASTER => '0', RXCHBONDO(4 downto 0) => NLW_gtxe2_i_RXCHBONDO_UNCONNECTED(4 downto 0), RXCHBONDSLAVE => '0', RXCLKCORCNT(1 downto 0) => NLW_gtxe2_i_RXCLKCORCNT_UNCONNECTED(1 downto 0), RXCOMINITDET => NLW_gtxe2_i_RXCOMINITDET_UNCONNECTED, RXCOMMADET => NLW_gtxe2_i_RXCOMMADET_UNCONNECTED, RXCOMMADETEN => '0', RXCOMSASDET => NLW_gtxe2_i_RXCOMSASDET_UNCONNECTED, RXCOMWAKEDET => NLW_gtxe2_i_RXCOMWAKEDET_UNCONNECTED, RXDATA(63 downto 32) => NLW_gtxe2_i_RXDATA_UNCONNECTED(63 downto 32), RXDATA(31 downto 0) => RXDATA(31 downto 0), RXDATAVALID => pre_rxdatavalid_i, RXDDIEN => '0', RXDFEAGCHOLD => '0', RXDFEAGCOVRDEN => '0', RXDFECM1EN => '0', RXDFELFHOLD => '0', RXDFELFOVRDEN => '1', RXDFELPMRESET => '0', RXDFETAP2HOLD => '0', RXDFETAP2OVRDEN => '0', RXDFETAP3HOLD => '0', RXDFETAP3OVRDEN => '0', RXDFETAP4HOLD => '0', RXDFETAP4OVRDEN => '0', RXDFETAP5HOLD => '0', RXDFETAP5OVRDEN => '0', RXDFEUTHOLD => '0', RXDFEUTOVRDEN => '0', RXDFEVPHOLD => '0', RXDFEVPOVRDEN => '0', RXDFEVSEN => '0', RXDFEXYDEN => '1', RXDFEXYDHOLD => '0', RXDFEXYDOVRDEN => '0', RXDISPERR(7 downto 0) => NLW_gtxe2_i_RXDISPERR_UNCONNECTED(7 downto 0), RXDLYBYPASS => '1', RXDLYEN => '0', RXDLYOVRDEN => '0', RXDLYSRESET => '0', RXDLYSRESETDONE => NLW_gtxe2_i_RXDLYSRESETDONE_UNCONNECTED, RXELECIDLE => NLW_gtxe2_i_RXELECIDLE_UNCONNECTED, RXELECIDLEMODE(1 downto 0) => B"11", RXGEARBOXSLIP => D(0), RXHEADER(2) => NLW_gtxe2_i_RXHEADER_UNCONNECTED(2), RXHEADER(1 downto 0) => RXHEADER(1 downto 0), RXHEADERVALID => pre_rxheadervalid_i, RXLPMEN => '0', RXLPMHFHOLD => '0', RXLPMHFOVRDEN => '0', RXLPMLFHOLD => '0', RXLPMLFKLOVRDEN => '0', RXMCOMMAALIGNEN => '0', RXMONITOROUT(6) => gtxe2_i_n_170, RXMONITOROUT(5) => gtxe2_i_n_171, RXMONITOROUT(4) => gtxe2_i_n_172, RXMONITOROUT(3) => gtxe2_i_n_173, RXMONITOROUT(2) => gtxe2_i_n_174, RXMONITOROUT(1) => gtxe2_i_n_175, RXMONITOROUT(0) => gtxe2_i_n_176, RXMONITORSEL(1 downto 0) => B"00", RXNOTINTABLE(7 downto 0) => NLW_gtxe2_i_RXNOTINTABLE_UNCONNECTED(7 downto 0), RXOOBRESET => '0', RXOSHOLD => '0', RXOSOVRDEN => '0', RXOUTCLK => rxrecclk_from_gtx_i, RXOUTCLKFABRIC => NLW_gtxe2_i_RXOUTCLKFABRIC_UNCONNECTED, RXOUTCLKPCS => NLW_gtxe2_i_RXOUTCLKPCS_UNCONNECTED, RXOUTCLKSEL(2 downto 0) => B"010", RXPCOMMAALIGNEN => '0', RXPCSRESET => '0', RXPD(1 downto 0) => B"00", RXPHALIGN => '0', RXPHALIGNDONE => NLW_gtxe2_i_RXPHALIGNDONE_UNCONNECTED, RXPHALIGNEN => '0', RXPHDLYPD => '0', RXPHDLYRESET => '0', RXPHMONITOR(4 downto 0) => NLW_gtxe2_i_RXPHMONITOR_UNCONNECTED(4 downto 0), RXPHOVRDEN => '0', RXPHSLIPMONITOR(4 downto 0) => NLW_gtxe2_i_RXPHSLIPMONITOR_UNCONNECTED(4 downto 0), RXPMARESET => '0', RXPOLARITY => \out\, RXPRBSCNTRESET => '0', RXPRBSERR => gtxe2_i_n_27, RXPRBSSEL(2 downto 0) => B"000", RXQPIEN => '0', RXQPISENN => NLW_gtxe2_i_RXQPISENN_UNCONNECTED, RXQPISENP => NLW_gtxe2_i_RXQPISENP_UNCONNECTED, RXRATE(2 downto 0) => B"000", RXRATEDONE => NLW_gtxe2_i_RXRATEDONE_UNCONNECTED, RXRESETDONE => \cpllpd_wait_reg[95]_0\, RXSLIDE => '0', RXSTARTOFSEQ => NLW_gtxe2_i_RXSTARTOFSEQ_UNCONNECTED, RXSTATUS(2 downto 0) => NLW_gtxe2_i_RXSTATUS_UNCONNECTED(2 downto 0), RXSYSCLKSEL(1 downto 0) => B"00", RXUSERRDY => rxuserrdy_t, RXUSRCLK => s_level_out_d1_aurora_64b66b_0_cdc_to_reg, RXUSRCLK2 => s_level_out_d1_aurora_64b66b_0_cdc_to_reg, RXVALID => NLW_gtxe2_i_RXVALID_UNCONNECTED, SETERRSTATUS => '0', TSTIN(19 downto 0) => B"11111111111111111111", TSTOUT(9 downto 0) => NLW_gtxe2_i_TSTOUT_UNCONNECTED(9 downto 0), TX8B10BBYPASS(7 downto 0) => B"00000000", TX8B10BEN => '0', TXBUFDIFFCTRL(2 downto 0) => B"100", TXBUFSTATUS(1) => TXBUFSTATUS(0), TXBUFSTATUS(0) => gtxe2_i_n_81, TXCHARDISPMODE(7 downto 0) => B"00000000", TXCHARDISPVAL(7 downto 0) => B"00000000", TXCHARISK(7 downto 0) => B"00000000", TXCOMFINISH => NLW_gtxe2_i_TXCOMFINISH_UNCONNECTED, TXCOMINIT => '0', TXCOMSAS => '0', TXCOMWAKE => '0', TXDATA(63 downto 0) => SCRAMBLED_DATA_OUT(63 downto 0), TXDEEMPH => '0', TXDETECTRX => '0', TXDIFFCTRL(3 downto 0) => B"1000", TXDIFFPD => '0', TXDLYBYPASS => '1', TXDLYEN => '0', TXDLYHOLD => '0', TXDLYOVRDEN => '0', TXDLYSRESET => '0', TXDLYSRESETDONE => NLW_gtxe2_i_TXDLYSRESETDONE_UNCONNECTED, TXDLYUPDOWN => '0', TXELECIDLE => '0', TXGEARBOXREADY => NLW_gtxe2_i_TXGEARBOXREADY_UNCONNECTED, TXHEADER(2) => '0', TXHEADER(1 downto 0) => Q(1 downto 0), TXINHIBIT => '0', TXMAINCURSOR(6 downto 0) => B"0000000", TXMARGIN(2 downto 0) => B"000", TXOUTCLK => tx_out_clk, TXOUTCLKFABRIC => gtxe2_i_n_38, TXOUTCLKPCS => gtxe2_i_n_39, TXOUTCLKSEL(2 downto 0) => B"010", TXPCSRESET => '0', TXPD(1 downto 0) => B"00", TXPDELECIDLEMODE => '0', TXPHALIGN => '0', TXPHALIGNDONE => NLW_gtxe2_i_TXPHALIGNDONE_UNCONNECTED, TXPHALIGNEN => '0', TXPHDLYPD => '0', TXPHDLYRESET => '0', TXPHDLYTSTCLK => '0', TXPHINIT => '0', TXPHINITDONE => NLW_gtxe2_i_TXPHINITDONE_UNCONNECTED, TXPHOVRDEN => '0', TXPISOPD => '0', TXPMARESET => '0', TXPOLARITY => '0', TXPOSTCURSOR(4 downto 0) => B"00000", TXPOSTCURSORINV => '0', TXPRBSFORCEERR => '0', TXPRBSSEL(2 downto 0) => B"000", TXPRECURSOR(4 downto 0) => B"00000", TXPRECURSORINV => '0', TXQPIBIASEN => '0', TXQPISENN => NLW_gtxe2_i_TXQPISENN_UNCONNECTED, TXQPISENP => NLW_gtxe2_i_TXQPISENP_UNCONNECTED, TXQPISTRONGPDOWN => '0', TXQPIWEAKPUP => '0', TXRATE(2 downto 0) => B"000", TXRATEDONE => NLW_gtxe2_i_TXRATEDONE_UNCONNECTED, TXRESETDONE => \cpllpd_wait_reg[95]_1\, TXSEQUENCE(6 downto 0) => s_level_out_d1_aurora_64b66b_0_cdc_to_reg_2(6 downto 0), TXSTARTSEQ => '0', TXSWING => '0', TXSYSCLKSEL(1 downto 0) => B"00", TXUSERRDY => txuserrdy_t, TXUSRCLK => s_level_out_d1_aurora_64b66b_0_cdc_to_reg_0, TXUSRCLK2 => s_level_out_d1_aurora_64b66b_0_cdc_to_reg_1 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_RX_STREAM_DATAPATH is port ( m_axi_rx_tvalid : out STD_LOGIC; m_axi_rx_tdata : out STD_LOGIC_VECTOR ( 0 to 63 ); RX_SRC_RDY_N_reg_inv_0 : in STD_LOGIC; \out\ : in STD_LOGIC; SR : in STD_LOGIC_VECTOR ( 0 to 0 ); E : in STD_LOGIC_VECTOR ( 0 to 0 ); D : in STD_LOGIC_VECTOR ( 63 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_RX_STREAM_DATAPATH; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_RX_STREAM_DATAPATH is begin \RX_D_reg[0]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(63), Q => m_axi_rx_tdata(0), R => SR(0) ); \RX_D_reg[10]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(53), Q => m_axi_rx_tdata(10), R => SR(0) ); \RX_D_reg[11]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(52), Q => m_axi_rx_tdata(11), R => SR(0) ); \RX_D_reg[12]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(51), Q => m_axi_rx_tdata(12), R => SR(0) ); \RX_D_reg[13]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(50), Q => m_axi_rx_tdata(13), R => SR(0) ); \RX_D_reg[14]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(49), Q => m_axi_rx_tdata(14), R => SR(0) ); \RX_D_reg[15]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(48), Q => m_axi_rx_tdata(15), R => SR(0) ); \RX_D_reg[16]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(47), Q => m_axi_rx_tdata(16), R => SR(0) ); \RX_D_reg[17]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(46), Q => m_axi_rx_tdata(17), R => SR(0) ); \RX_D_reg[18]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(45), Q => m_axi_rx_tdata(18), R => SR(0) ); \RX_D_reg[19]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(44), Q => m_axi_rx_tdata(19), R => SR(0) ); \RX_D_reg[1]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(62), Q => m_axi_rx_tdata(1), R => SR(0) ); \RX_D_reg[20]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(43), Q => m_axi_rx_tdata(20), R => SR(0) ); \RX_D_reg[21]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(42), Q => m_axi_rx_tdata(21), R => SR(0) ); \RX_D_reg[22]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(41), Q => m_axi_rx_tdata(22), R => SR(0) ); \RX_D_reg[23]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(40), Q => m_axi_rx_tdata(23), R => SR(0) ); \RX_D_reg[24]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(39), Q => m_axi_rx_tdata(24), R => SR(0) ); \RX_D_reg[25]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(38), Q => m_axi_rx_tdata(25), R => SR(0) ); \RX_D_reg[26]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(37), Q => m_axi_rx_tdata(26), R => SR(0) ); \RX_D_reg[27]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(36), Q => m_axi_rx_tdata(27), R => SR(0) ); \RX_D_reg[28]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(35), Q => m_axi_rx_tdata(28), R => SR(0) ); \RX_D_reg[29]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(34), Q => m_axi_rx_tdata(29), R => SR(0) ); \RX_D_reg[2]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(61), Q => m_axi_rx_tdata(2), R => SR(0) ); \RX_D_reg[30]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(33), Q => m_axi_rx_tdata(30), R => SR(0) ); \RX_D_reg[31]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(32), Q => m_axi_rx_tdata(31), R => SR(0) ); \RX_D_reg[32]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(31), Q => m_axi_rx_tdata(32), R => SR(0) ); \RX_D_reg[33]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(30), Q => m_axi_rx_tdata(33), R => SR(0) ); \RX_D_reg[34]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(29), Q => m_axi_rx_tdata(34), R => SR(0) ); \RX_D_reg[35]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(28), Q => m_axi_rx_tdata(35), R => SR(0) ); \RX_D_reg[36]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(27), Q => m_axi_rx_tdata(36), R => SR(0) ); \RX_D_reg[37]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(26), Q => m_axi_rx_tdata(37), R => SR(0) ); \RX_D_reg[38]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(25), Q => m_axi_rx_tdata(38), R => SR(0) ); \RX_D_reg[39]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(24), Q => m_axi_rx_tdata(39), R => SR(0) ); \RX_D_reg[3]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(60), Q => m_axi_rx_tdata(3), R => SR(0) ); \RX_D_reg[40]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(23), Q => m_axi_rx_tdata(40), R => SR(0) ); \RX_D_reg[41]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(22), Q => m_axi_rx_tdata(41), R => SR(0) ); \RX_D_reg[42]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(21), Q => m_axi_rx_tdata(42), R => SR(0) ); \RX_D_reg[43]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(20), Q => m_axi_rx_tdata(43), R => SR(0) ); \RX_D_reg[44]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(19), Q => m_axi_rx_tdata(44), R => SR(0) ); \RX_D_reg[45]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(18), Q => m_axi_rx_tdata(45), R => SR(0) ); \RX_D_reg[46]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(17), Q => m_axi_rx_tdata(46), R => SR(0) ); \RX_D_reg[47]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(16), Q => m_axi_rx_tdata(47), R => SR(0) ); \RX_D_reg[48]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(15), Q => m_axi_rx_tdata(48), R => SR(0) ); \RX_D_reg[49]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(14), Q => m_axi_rx_tdata(49), R => SR(0) ); \RX_D_reg[4]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(59), Q => m_axi_rx_tdata(4), R => SR(0) ); \RX_D_reg[50]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(13), Q => m_axi_rx_tdata(50), R => SR(0) ); \RX_D_reg[51]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(12), Q => m_axi_rx_tdata(51), R => SR(0) ); \RX_D_reg[52]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(11), Q => m_axi_rx_tdata(52), R => SR(0) ); \RX_D_reg[53]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(10), Q => m_axi_rx_tdata(53), R => SR(0) ); \RX_D_reg[54]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(9), Q => m_axi_rx_tdata(54), R => SR(0) ); \RX_D_reg[55]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(8), Q => m_axi_rx_tdata(55), R => SR(0) ); \RX_D_reg[56]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(7), Q => m_axi_rx_tdata(56), R => SR(0) ); \RX_D_reg[57]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(6), Q => m_axi_rx_tdata(57), R => SR(0) ); \RX_D_reg[58]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(5), Q => m_axi_rx_tdata(58), R => SR(0) ); \RX_D_reg[59]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(4), Q => m_axi_rx_tdata(59), R => SR(0) ); \RX_D_reg[5]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(58), Q => m_axi_rx_tdata(5), R => SR(0) ); \RX_D_reg[60]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(3), Q => m_axi_rx_tdata(60), R => SR(0) ); \RX_D_reg[61]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(2), Q => m_axi_rx_tdata(61), R => SR(0) ); \RX_D_reg[62]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(1), Q => m_axi_rx_tdata(62), R => SR(0) ); \RX_D_reg[63]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(0), Q => m_axi_rx_tdata(63), R => SR(0) ); \RX_D_reg[6]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(57), Q => m_axi_rx_tdata(6), R => SR(0) ); \RX_D_reg[7]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(56), Q => m_axi_rx_tdata(7), R => SR(0) ); \RX_D_reg[8]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(55), Q => m_axi_rx_tdata(8), R => SR(0) ); \RX_D_reg[9]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => E(0), D => D(54), Q => m_axi_rx_tdata(9), R => SR(0) ); RX_SRC_RDY_N_reg_inv: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => RX_SRC_RDY_N_reg_inv_0, Q => m_axi_rx_tvalid, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_SCRAMBLER_64B66B is port ( \txseq_counter_i_reg[0]\ : out STD_LOGIC; scrambler : out STD_LOGIC_VECTOR ( 11 downto 0 ); \SCRAMBLED_DATA_OUT_reg[63]_0\ : out STD_LOGIC_VECTOR ( 63 downto 0 ); Q : in STD_LOGIC_VECTOR ( 6 downto 0 ); tx_data_i : in STD_LOGIC_VECTOR ( 57 downto 0 ); \out\ : in STD_LOGIC; tempData : in STD_LOGIC_VECTOR ( 5 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_SCRAMBLER_64B66B; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_SCRAMBLER_64B66B is signal data_valid_i : STD_LOGIC; signal p_101_in : STD_LOGIC; signal p_105_in : STD_LOGIC; signal p_109_in : STD_LOGIC; signal p_113_in : STD_LOGIC; signal p_117_in : STD_LOGIC; signal p_121_in : STD_LOGIC; signal p_125_in : STD_LOGIC; signal p_129_in : STD_LOGIC; signal p_133_in : STD_LOGIC; signal p_137_in : STD_LOGIC; signal p_141_in : STD_LOGIC; signal p_145_in : STD_LOGIC; signal p_149_in : STD_LOGIC; signal p_177_in : STD_LOGIC; signal p_181_in : STD_LOGIC; signal p_185_in : STD_LOGIC; signal p_189_in : STD_LOGIC; signal p_193_in : STD_LOGIC; signal p_197_in : STD_LOGIC; signal p_201_in : STD_LOGIC; signal p_205_in : STD_LOGIC; signal p_209_in : STD_LOGIC; signal p_213_in : STD_LOGIC; signal p_217_in : STD_LOGIC; signal p_221_in : STD_LOGIC; signal p_225_in : STD_LOGIC; signal p_229_in : STD_LOGIC; signal p_233_in : STD_LOGIC; signal p_237_in : STD_LOGIC; signal p_241_in : STD_LOGIC; signal p_245_in : STD_LOGIC; signal p_249_in : STD_LOGIC; signal p_97_in : STD_LOGIC; signal \^scrambler\ : STD_LOGIC_VECTOR ( 11 downto 0 ); signal \scrambler_reg_n_0_[39]\ : STD_LOGIC; signal \scrambler_reg_n_0_[40]\ : STD_LOGIC; signal \scrambler_reg_n_0_[41]\ : STD_LOGIC; signal \scrambler_reg_n_0_[42]\ : STD_LOGIC; signal \scrambler_reg_n_0_[43]\ : STD_LOGIC; signal \scrambler_reg_n_0_[44]\ : STD_LOGIC; signal \scrambler_reg_n_0_[45]\ : STD_LOGIC; signal \scrambler_reg_n_0_[46]\ : STD_LOGIC; signal \scrambler_reg_n_0_[47]\ : STD_LOGIC; signal \scrambler_reg_n_0_[48]\ : STD_LOGIC; signal \scrambler_reg_n_0_[49]\ : STD_LOGIC; signal \scrambler_reg_n_0_[50]\ : STD_LOGIC; signal \scrambler_reg_n_0_[51]\ : STD_LOGIC; signal tempData0100_out : STD_LOGIC; signal tempData0104_out : STD_LOGIC; signal tempData0108_out : STD_LOGIC; signal tempData0112_out : STD_LOGIC; signal tempData0116_out : STD_LOGIC; signal tempData0120_out : STD_LOGIC; signal tempData0124_out : STD_LOGIC; signal tempData0128_out : STD_LOGIC; signal tempData0132_out : STD_LOGIC; signal tempData0136_out : STD_LOGIC; signal tempData0140_out : STD_LOGIC; signal tempData0144_out : STD_LOGIC; signal tempData0148_out : STD_LOGIC; signal tempData0152_out : STD_LOGIC; signal tempData0156_out : STD_LOGIC; signal tempData0160_out : STD_LOGIC; signal tempData0164_out : STD_LOGIC; signal tempData0168_out : STD_LOGIC; signal tempData0172_out : STD_LOGIC; signal tempData0176_out : STD_LOGIC; signal tempData0180_out : STD_LOGIC; signal tempData0184_out : STD_LOGIC; signal tempData0188_out : STD_LOGIC; signal tempData0192_out : STD_LOGIC; signal tempData0196_out : STD_LOGIC; signal tempData0200_out : STD_LOGIC; signal tempData0204_out : STD_LOGIC; signal tempData0208_out : STD_LOGIC; signal tempData0212_out : STD_LOGIC; signal tempData0216_out : STD_LOGIC; signal tempData0220_out : STD_LOGIC; signal tempData0224_out : STD_LOGIC; signal tempData0228_out : STD_LOGIC; signal tempData0232_out : STD_LOGIC; signal tempData0236_out : STD_LOGIC; signal tempData0240_out : STD_LOGIC; signal tempData0244_out : STD_LOGIC; signal tempData0248_out : STD_LOGIC; signal tempData024_out : STD_LOGIC; signal tempData0252_out : STD_LOGIC; signal tempData028_out : STD_LOGIC; signal tempData032_out : STD_LOGIC; signal tempData036_out : STD_LOGIC; signal tempData040_out : STD_LOGIC; signal tempData044_out : STD_LOGIC; signal tempData048_out : STD_LOGIC; signal tempData052_out : STD_LOGIC; signal tempData056_out : STD_LOGIC; signal tempData060_out : STD_LOGIC; signal tempData064_out : STD_LOGIC; signal tempData068_out : STD_LOGIC; signal tempData072_out : STD_LOGIC; signal tempData076_out : STD_LOGIC; signal tempData080_out : STD_LOGIC; signal tempData084_out : STD_LOGIC; signal tempData088_out : STD_LOGIC; signal tempData092_out : STD_LOGIC; signal tempData096_out : STD_LOGIC; signal \^txseq_counter_i_reg[0]\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \SCRAMBLED_DATA_OUT[58]_i_1\ : label is "soft_lutpair54"; attribute SOFT_HLUTNM of \SCRAMBLED_DATA_OUT[59]_i_1\ : label is "soft_lutpair55"; attribute SOFT_HLUTNM of \SCRAMBLED_DATA_OUT[60]_i_1\ : label is "soft_lutpair56"; attribute SOFT_HLUTNM of \SCRAMBLED_DATA_OUT[61]_i_1\ : label is "soft_lutpair57"; attribute SOFT_HLUTNM of \SCRAMBLED_DATA_OUT[62]_i_1\ : label is "soft_lutpair58"; attribute SOFT_HLUTNM of \SCRAMBLED_DATA_OUT[63]_i_1\ : label is "soft_lutpair59"; attribute SOFT_HLUTNM of \scrambler[10]_i_1\ : label is "soft_lutpair45"; attribute SOFT_HLUTNM of \scrambler[11]_i_1\ : label is "soft_lutpair46"; attribute SOFT_HLUTNM of \scrambler[12]_i_1\ : label is "soft_lutpair47"; attribute SOFT_HLUTNM of \scrambler[13]_i_1\ : label is "soft_lutpair48"; attribute SOFT_HLUTNM of \scrambler[14]_i_1\ : label is "soft_lutpair49"; attribute SOFT_HLUTNM of \scrambler[15]_i_1\ : label is "soft_lutpair50"; attribute SOFT_HLUTNM of \scrambler[16]_i_1\ : label is "soft_lutpair51"; attribute SOFT_HLUTNM of \scrambler[17]_i_1\ : label is "soft_lutpair52"; attribute SOFT_HLUTNM of \scrambler[18]_i_1\ : label is "soft_lutpair53"; attribute SOFT_HLUTNM of \scrambler[19]_i_1\ : label is "soft_lutpair54"; attribute SOFT_HLUTNM of \scrambler[20]_i_1\ : label is "soft_lutpair55"; attribute SOFT_HLUTNM of \scrambler[21]_i_1\ : label is "soft_lutpair56"; attribute SOFT_HLUTNM of \scrambler[22]_i_1\ : label is "soft_lutpair57"; attribute SOFT_HLUTNM of \scrambler[23]_i_1\ : label is "soft_lutpair58"; attribute SOFT_HLUTNM of \scrambler[24]_i_1\ : label is "soft_lutpair59"; attribute SOFT_HLUTNM of \scrambler[25]_i_1\ : label is "soft_lutpair60"; attribute SOFT_HLUTNM of \scrambler[44]_i_1\ : label is "soft_lutpair60"; attribute SOFT_HLUTNM of \scrambler[45]_i_1\ : label is "soft_lutpair41"; attribute SOFT_HLUTNM of \scrambler[46]_i_1\ : label is "soft_lutpair42"; attribute SOFT_HLUTNM of \scrambler[47]_i_1\ : label is "soft_lutpair43"; attribute SOFT_HLUTNM of \scrambler[48]_i_1\ : label is "soft_lutpair44"; attribute SOFT_HLUTNM of \scrambler[49]_i_1\ : label is "soft_lutpair45"; attribute SOFT_HLUTNM of \scrambler[50]_i_1\ : label is "soft_lutpair46"; attribute SOFT_HLUTNM of \scrambler[51]_i_1\ : label is "soft_lutpair47"; attribute SOFT_HLUTNM of \scrambler[52]_i_1\ : label is "soft_lutpair48"; attribute SOFT_HLUTNM of \scrambler[53]_i_1\ : label is "soft_lutpair49"; attribute SOFT_HLUTNM of \scrambler[54]_i_1\ : label is "soft_lutpair50"; attribute SOFT_HLUTNM of \scrambler[55]_i_1\ : label is "soft_lutpair51"; attribute SOFT_HLUTNM of \scrambler[56]_i_1\ : label is "soft_lutpair52"; attribute SOFT_HLUTNM of \scrambler[57]_i_2\ : label is "soft_lutpair53"; attribute SOFT_HLUTNM of \scrambler[6]_i_1\ : label is "soft_lutpair41"; attribute SOFT_HLUTNM of \scrambler[7]_i_1\ : label is "soft_lutpair42"; attribute SOFT_HLUTNM of \scrambler[8]_i_1\ : label is "soft_lutpair43"; attribute SOFT_HLUTNM of \scrambler[9]_i_1\ : label is "soft_lutpair44"; begin scrambler(11 downto 0) <= \^scrambler\(11 downto 0); \txseq_counter_i_reg[0]\ <= \^txseq_counter_i_reg[0]\; \SCRAMBLED_DATA_OUT[58]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_229_in, I1 => tx_data_i(52), I2 => \^scrambler\(6), O => tempData0232_out ); \SCRAMBLED_DATA_OUT[59]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_233_in, I1 => tx_data_i(53), I2 => \^scrambler\(7), O => tempData0236_out ); \SCRAMBLED_DATA_OUT[60]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_237_in, I1 => tx_data_i(54), I2 => \^scrambler\(8), O => tempData0240_out ); \SCRAMBLED_DATA_OUT[61]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_241_in, I1 => tx_data_i(55), I2 => \^scrambler\(9), O => tempData0244_out ); \SCRAMBLED_DATA_OUT[62]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_245_in, I1 => tx_data_i(56), I2 => \^scrambler\(10), O => tempData0248_out ); \SCRAMBLED_DATA_OUT[63]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_249_in, I1 => tx_data_i(57), I2 => \^scrambler\(11), O => tempData0252_out ); \SCRAMBLED_DATA_OUT_reg[0]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData(0), Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(0), R => '0' ); \SCRAMBLED_DATA_OUT_reg[10]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData040_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(10), R => '0' ); \SCRAMBLED_DATA_OUT_reg[11]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData044_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(11), R => '0' ); \SCRAMBLED_DATA_OUT_reg[12]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData048_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(12), R => '0' ); \SCRAMBLED_DATA_OUT_reg[13]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData052_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(13), R => '0' ); \SCRAMBLED_DATA_OUT_reg[14]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData056_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(14), R => '0' ); \SCRAMBLED_DATA_OUT_reg[15]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData060_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(15), R => '0' ); \SCRAMBLED_DATA_OUT_reg[16]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData064_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(16), R => '0' ); \SCRAMBLED_DATA_OUT_reg[17]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData068_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(17), R => '0' ); \SCRAMBLED_DATA_OUT_reg[18]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData072_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(18), R => '0' ); \SCRAMBLED_DATA_OUT_reg[19]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData076_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(19), R => '0' ); \SCRAMBLED_DATA_OUT_reg[1]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData(1), Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(1), R => '0' ); \SCRAMBLED_DATA_OUT_reg[20]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData080_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(20), R => '0' ); \SCRAMBLED_DATA_OUT_reg[21]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData084_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(21), R => '0' ); \SCRAMBLED_DATA_OUT_reg[22]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData088_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(22), R => '0' ); \SCRAMBLED_DATA_OUT_reg[23]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData092_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(23), R => '0' ); \SCRAMBLED_DATA_OUT_reg[24]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData096_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(24), R => '0' ); \SCRAMBLED_DATA_OUT_reg[25]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData0100_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(25), R => '0' ); \SCRAMBLED_DATA_OUT_reg[26]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData0104_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(26), R => '0' ); \SCRAMBLED_DATA_OUT_reg[27]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData0108_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(27), R => '0' ); \SCRAMBLED_DATA_OUT_reg[28]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData0112_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(28), R => '0' ); \SCRAMBLED_DATA_OUT_reg[29]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData0116_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(29), R => '0' ); \SCRAMBLED_DATA_OUT_reg[2]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData(2), Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(2), R => '0' ); \SCRAMBLED_DATA_OUT_reg[30]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData0120_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(30), R => '0' ); \SCRAMBLED_DATA_OUT_reg[31]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData0124_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(31), R => '0' ); \SCRAMBLED_DATA_OUT_reg[32]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData0128_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(32), R => '0' ); \SCRAMBLED_DATA_OUT_reg[33]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData0132_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(33), R => '0' ); \SCRAMBLED_DATA_OUT_reg[34]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData0136_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(34), R => '0' ); \SCRAMBLED_DATA_OUT_reg[35]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData0140_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(35), R => '0' ); \SCRAMBLED_DATA_OUT_reg[36]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData0144_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(36), R => '0' ); \SCRAMBLED_DATA_OUT_reg[37]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData0148_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(37), R => '0' ); \SCRAMBLED_DATA_OUT_reg[38]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData0152_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(38), R => '0' ); \SCRAMBLED_DATA_OUT_reg[39]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData0156_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(39), R => '0' ); \SCRAMBLED_DATA_OUT_reg[3]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData(3), Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(3), R => '0' ); \SCRAMBLED_DATA_OUT_reg[40]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData0160_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(40), R => '0' ); \SCRAMBLED_DATA_OUT_reg[41]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData0164_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(41), R => '0' ); \SCRAMBLED_DATA_OUT_reg[42]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData0168_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(42), R => '0' ); \SCRAMBLED_DATA_OUT_reg[43]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData0172_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(43), R => '0' ); \SCRAMBLED_DATA_OUT_reg[44]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData0176_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(44), R => '0' ); \SCRAMBLED_DATA_OUT_reg[45]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData0180_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(45), R => '0' ); \SCRAMBLED_DATA_OUT_reg[46]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData0184_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(46), R => '0' ); \SCRAMBLED_DATA_OUT_reg[47]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData0188_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(47), R => '0' ); \SCRAMBLED_DATA_OUT_reg[48]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData0192_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(48), R => '0' ); \SCRAMBLED_DATA_OUT_reg[49]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData0196_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(49), R => '0' ); \SCRAMBLED_DATA_OUT_reg[4]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData(4), Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(4), R => '0' ); \SCRAMBLED_DATA_OUT_reg[50]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData0200_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(50), R => '0' ); \SCRAMBLED_DATA_OUT_reg[51]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData0204_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(51), R => '0' ); \SCRAMBLED_DATA_OUT_reg[52]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData0208_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(52), R => '0' ); \SCRAMBLED_DATA_OUT_reg[53]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData0212_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(53), R => '0' ); \SCRAMBLED_DATA_OUT_reg[54]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData0216_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(54), R => '0' ); \SCRAMBLED_DATA_OUT_reg[55]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData0220_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(55), R => '0' ); \SCRAMBLED_DATA_OUT_reg[56]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData0224_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(56), R => '0' ); \SCRAMBLED_DATA_OUT_reg[57]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData0228_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(57), R => '0' ); \SCRAMBLED_DATA_OUT_reg[58]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData0232_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(58), R => '0' ); \SCRAMBLED_DATA_OUT_reg[59]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData0236_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(59), R => '0' ); \SCRAMBLED_DATA_OUT_reg[5]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData(5), Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(5), R => '0' ); \SCRAMBLED_DATA_OUT_reg[60]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData0240_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(60), R => '0' ); \SCRAMBLED_DATA_OUT_reg[61]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData0244_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(61), R => '0' ); \SCRAMBLED_DATA_OUT_reg[62]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData0248_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(62), R => '0' ); \SCRAMBLED_DATA_OUT_reg[63]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData0252_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(63), R => '0' ); \SCRAMBLED_DATA_OUT_reg[6]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData024_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(6), R => '0' ); \SCRAMBLED_DATA_OUT_reg[7]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData028_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(7), R => '0' ); \SCRAMBLED_DATA_OUT_reg[8]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData032_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(8), R => '0' ); \SCRAMBLED_DATA_OUT_reg[9]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => data_valid_i, D => tempData036_out, Q => \SCRAMBLED_DATA_OUT_reg[63]_0\(9), R => '0' ); \scrambler[10]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \scrambler_reg_n_0_[43]\, I1 => tx_data_i(43), I2 => p_193_in, I3 => tx_data_i(4), I4 => p_113_in, O => tempData040_out ); \scrambler[11]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \scrambler_reg_n_0_[44]\, I1 => tx_data_i(44), I2 => p_197_in, I3 => tx_data_i(5), I4 => p_117_in, O => tempData044_out ); \scrambler[12]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \scrambler_reg_n_0_[45]\, I1 => tx_data_i(45), I2 => p_201_in, I3 => tx_data_i(6), I4 => p_121_in, O => tempData048_out ); \scrambler[13]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \scrambler_reg_n_0_[46]\, I1 => tx_data_i(46), I2 => p_205_in, I3 => tx_data_i(7), I4 => p_125_in, O => tempData052_out ); \scrambler[14]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \scrambler_reg_n_0_[47]\, I1 => tx_data_i(47), I2 => p_209_in, I3 => tx_data_i(8), I4 => p_129_in, O => tempData056_out ); \scrambler[15]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \scrambler_reg_n_0_[48]\, I1 => tx_data_i(48), I2 => p_213_in, I3 => tx_data_i(9), I4 => p_133_in, O => tempData060_out ); \scrambler[16]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \scrambler_reg_n_0_[49]\, I1 => tx_data_i(49), I2 => p_217_in, I3 => tx_data_i(10), I4 => p_137_in, O => tempData064_out ); \scrambler[17]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \scrambler_reg_n_0_[50]\, I1 => tx_data_i(50), I2 => p_221_in, I3 => tx_data_i(11), I4 => p_141_in, O => tempData068_out ); \scrambler[18]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \scrambler_reg_n_0_[51]\, I1 => tx_data_i(51), I2 => p_225_in, I3 => tx_data_i(12), I4 => p_145_in, O => tempData072_out ); \scrambler[19]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \^scrambler\(6), I1 => tx_data_i(52), I2 => p_229_in, I3 => tx_data_i(13), I4 => p_149_in, O => tempData076_out ); \scrambler[20]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \^scrambler\(7), I1 => tx_data_i(53), I2 => p_233_in, I3 => tx_data_i(14), I4 => \^scrambler\(0), O => tempData080_out ); \scrambler[21]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \^scrambler\(8), I1 => tx_data_i(54), I2 => p_237_in, I3 => tx_data_i(15), I4 => \^scrambler\(1), O => tempData084_out ); \scrambler[22]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \^scrambler\(9), I1 => tx_data_i(55), I2 => p_241_in, I3 => tx_data_i(16), I4 => \^scrambler\(2), O => tempData088_out ); \scrambler[23]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \^scrambler\(10), I1 => tx_data_i(56), I2 => p_245_in, I3 => tx_data_i(17), I4 => \^scrambler\(3), O => tempData092_out ); \scrambler[24]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \^scrambler\(11), I1 => tx_data_i(57), I2 => p_249_in, I3 => tx_data_i(18), I4 => \^scrambler\(4), O => tempData096_out ); \scrambler[25]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_97_in, I1 => tx_data_i(19), I2 => \^scrambler\(5), O => tempData0100_out ); \scrambler[26]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_101_in, I1 => tx_data_i(20), I2 => p_177_in, O => tempData0104_out ); \scrambler[27]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_105_in, I1 => tx_data_i(21), I2 => p_181_in, O => tempData0108_out ); \scrambler[28]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_109_in, I1 => tx_data_i(22), I2 => p_185_in, O => tempData0112_out ); \scrambler[29]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_113_in, I1 => tx_data_i(23), I2 => p_189_in, O => tempData0116_out ); \scrambler[30]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_117_in, I1 => tx_data_i(24), I2 => p_193_in, O => tempData0120_out ); \scrambler[31]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_121_in, I1 => tx_data_i(25), I2 => p_197_in, O => tempData0124_out ); \scrambler[32]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_125_in, I1 => tx_data_i(26), I2 => p_201_in, O => tempData0128_out ); \scrambler[33]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_129_in, I1 => tx_data_i(27), I2 => p_205_in, O => tempData0132_out ); \scrambler[34]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_133_in, I1 => tx_data_i(28), I2 => p_209_in, O => tempData0136_out ); \scrambler[35]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_137_in, I1 => tx_data_i(29), I2 => p_213_in, O => tempData0140_out ); \scrambler[36]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_141_in, I1 => tx_data_i(30), I2 => p_217_in, O => tempData0144_out ); \scrambler[37]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_145_in, I1 => tx_data_i(31), I2 => p_221_in, O => tempData0148_out ); \scrambler[38]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_149_in, I1 => tx_data_i(32), I2 => p_225_in, O => tempData0152_out ); \scrambler[39]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \^scrambler\(0), I1 => tx_data_i(33), I2 => p_229_in, O => tempData0156_out ); \scrambler[40]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \^scrambler\(1), I1 => tx_data_i(34), I2 => p_233_in, O => tempData0160_out ); \scrambler[41]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \^scrambler\(2), I1 => tx_data_i(35), I2 => p_237_in, O => tempData0164_out ); \scrambler[42]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \^scrambler\(3), I1 => tx_data_i(36), I2 => p_241_in, O => tempData0168_out ); \scrambler[43]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \^scrambler\(4), I1 => tx_data_i(37), I2 => p_245_in, O => tempData0172_out ); \scrambler[44]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => \^scrambler\(5), I1 => tx_data_i(38), I2 => p_249_in, O => tempData0176_out ); \scrambler[45]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_177_in, I1 => tx_data_i(39), I2 => \scrambler_reg_n_0_[39]\, O => tempData0180_out ); \scrambler[46]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_181_in, I1 => tx_data_i(40), I2 => \scrambler_reg_n_0_[40]\, O => tempData0184_out ); \scrambler[47]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_185_in, I1 => tx_data_i(41), I2 => \scrambler_reg_n_0_[41]\, O => tempData0188_out ); \scrambler[48]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_189_in, I1 => tx_data_i(42), I2 => \scrambler_reg_n_0_[42]\, O => tempData0192_out ); \scrambler[49]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_193_in, I1 => tx_data_i(43), I2 => \scrambler_reg_n_0_[43]\, O => tempData0196_out ); \scrambler[50]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_197_in, I1 => tx_data_i(44), I2 => \scrambler_reg_n_0_[44]\, O => tempData0200_out ); \scrambler[51]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_201_in, I1 => tx_data_i(45), I2 => \scrambler_reg_n_0_[45]\, O => tempData0204_out ); \scrambler[52]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_205_in, I1 => tx_data_i(46), I2 => \scrambler_reg_n_0_[46]\, O => tempData0208_out ); \scrambler[53]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_209_in, I1 => tx_data_i(47), I2 => \scrambler_reg_n_0_[47]\, O => tempData0212_out ); \scrambler[54]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_213_in, I1 => tx_data_i(48), I2 => \scrambler_reg_n_0_[48]\, O => tempData0216_out ); \scrambler[55]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_217_in, I1 => tx_data_i(49), I2 => \scrambler_reg_n_0_[49]\, O => tempData0220_out ); \scrambler[56]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_221_in, I1 => tx_data_i(50), I2 => \scrambler_reg_n_0_[50]\, O => tempData0224_out ); \scrambler[57]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FEFFFFFFFFFFFFFF" ) port map ( I0 => Q(6), I1 => \^txseq_counter_i_reg[0]\, I2 => Q(5), I3 => Q(3), I4 => Q(2), I5 => Q(4), O => data_valid_i ); \scrambler[57]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => p_225_in, I1 => tx_data_i(51), I2 => \scrambler_reg_n_0_[51]\, O => tempData0228_out ); \scrambler[57]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => Q(0), I1 => Q(1), O => \^txseq_counter_i_reg[0]\ ); \scrambler[6]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \scrambler_reg_n_0_[39]\, I1 => tx_data_i(39), I2 => p_177_in, I3 => tx_data_i(0), I4 => p_97_in, O => tempData024_out ); \scrambler[7]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \scrambler_reg_n_0_[40]\, I1 => tx_data_i(40), I2 => p_181_in, I3 => tx_data_i(1), I4 => p_101_in, O => tempData028_out ); \scrambler[8]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \scrambler_reg_n_0_[41]\, I1 => tx_data_i(41), I2 => p_185_in, I3 => tx_data_i(2), I4 => p_105_in, O => tempData032_out ); \scrambler[9]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \scrambler_reg_n_0_[42]\, I1 => tx_data_i(42), I2 => p_189_in, I3 => tx_data_i(3), I4 => p_109_in, O => tempData036_out ); \scrambler_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => data_valid_i, D => tempData(0), Q => p_97_in, R => '0' ); \scrambler_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => data_valid_i, D => tempData040_out, Q => p_137_in, R => '0' ); \scrambler_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => data_valid_i, D => tempData044_out, Q => p_141_in, R => '0' ); \scrambler_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => data_valid_i, D => tempData048_out, Q => p_145_in, R => '0' ); \scrambler_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => data_valid_i, D => tempData052_out, Q => p_149_in, R => '0' ); \scrambler_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => data_valid_i, D => tempData056_out, Q => \^scrambler\(0), R => '0' ); \scrambler_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => data_valid_i, D => tempData060_out, Q => \^scrambler\(1), R => '0' ); \scrambler_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => data_valid_i, D => tempData064_out, Q => \^scrambler\(2), R => '0' ); \scrambler_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => data_valid_i, D => tempData068_out, Q => \^scrambler\(3), R => '0' ); \scrambler_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => data_valid_i, D => tempData072_out, Q => \^scrambler\(4), R => '0' ); \scrambler_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => data_valid_i, D => tempData076_out, Q => \^scrambler\(5), R => '0' ); \scrambler_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => data_valid_i, D => tempData(1), Q => p_101_in, R => '0' ); \scrambler_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => data_valid_i, D => tempData080_out, Q => p_177_in, R => '0' ); \scrambler_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => data_valid_i, D => tempData084_out, Q => p_181_in, R => '0' ); \scrambler_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => data_valid_i, D => tempData088_out, Q => p_185_in, R => '0' ); \scrambler_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => data_valid_i, D => tempData092_out, Q => p_189_in, R => '0' ); \scrambler_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => data_valid_i, D => tempData096_out, Q => p_193_in, R => '0' ); \scrambler_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => data_valid_i, D => tempData0100_out, Q => p_197_in, R => '0' ); \scrambler_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => data_valid_i, D => tempData0104_out, Q => p_201_in, R => '0' ); \scrambler_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => data_valid_i, D => tempData0108_out, Q => p_205_in, R => '0' ); \scrambler_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => data_valid_i, D => tempData0112_out, Q => p_209_in, R => '0' ); \scrambler_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => data_valid_i, D => tempData0116_out, Q => p_213_in, R => '0' ); \scrambler_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => data_valid_i, D => tempData(2), Q => p_105_in, R => '0' ); \scrambler_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => data_valid_i, D => tempData0120_out, Q => p_217_in, R => '0' ); \scrambler_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => data_valid_i, D => tempData0124_out, Q => p_221_in, R => '0' ); \scrambler_reg[32]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => data_valid_i, D => tempData0128_out, Q => p_225_in, R => '0' ); \scrambler_reg[33]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => data_valid_i, D => tempData0132_out, Q => p_229_in, R => '0' ); \scrambler_reg[34]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => data_valid_i, D => tempData0136_out, Q => p_233_in, R => '0' ); \scrambler_reg[35]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => data_valid_i, D => tempData0140_out, Q => p_237_in, R => '0' ); \scrambler_reg[36]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => data_valid_i, D => tempData0144_out, Q => p_241_in, R => '0' ); \scrambler_reg[37]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => data_valid_i, D => tempData0148_out, Q => p_245_in, R => '0' ); \scrambler_reg[38]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => data_valid_i, D => tempData0152_out, Q => p_249_in, R => '0' ); \scrambler_reg[39]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => data_valid_i, D => tempData0156_out, Q => \scrambler_reg_n_0_[39]\, R => '0' ); \scrambler_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => data_valid_i, D => tempData(3), Q => p_109_in, R => '0' ); \scrambler_reg[40]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => data_valid_i, D => tempData0160_out, Q => \scrambler_reg_n_0_[40]\, R => '0' ); \scrambler_reg[41]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => data_valid_i, D => tempData0164_out, Q => \scrambler_reg_n_0_[41]\, R => '0' ); \scrambler_reg[42]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => data_valid_i, D => tempData0168_out, Q => \scrambler_reg_n_0_[42]\, R => '0' ); \scrambler_reg[43]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => data_valid_i, D => tempData0172_out, Q => \scrambler_reg_n_0_[43]\, R => '0' ); \scrambler_reg[44]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => data_valid_i, D => tempData0176_out, Q => \scrambler_reg_n_0_[44]\, R => '0' ); \scrambler_reg[45]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => data_valid_i, D => tempData0180_out, Q => \scrambler_reg_n_0_[45]\, R => '0' ); \scrambler_reg[46]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => data_valid_i, D => tempData0184_out, Q => \scrambler_reg_n_0_[46]\, R => '0' ); \scrambler_reg[47]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => data_valid_i, D => tempData0188_out, Q => \scrambler_reg_n_0_[47]\, R => '0' ); \scrambler_reg[48]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => data_valid_i, D => tempData0192_out, Q => \scrambler_reg_n_0_[48]\, R => '0' ); \scrambler_reg[49]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => data_valid_i, D => tempData0196_out, Q => \scrambler_reg_n_0_[49]\, R => '0' ); \scrambler_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => data_valid_i, D => tempData(4), Q => p_113_in, R => '0' ); \scrambler_reg[50]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => data_valid_i, D => tempData0200_out, Q => \scrambler_reg_n_0_[50]\, R => '0' ); \scrambler_reg[51]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => data_valid_i, D => tempData0204_out, Q => \scrambler_reg_n_0_[51]\, R => '0' ); \scrambler_reg[52]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => data_valid_i, D => tempData0208_out, Q => \^scrambler\(6), R => '0' ); \scrambler_reg[53]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => data_valid_i, D => tempData0212_out, Q => \^scrambler\(7), R => '0' ); \scrambler_reg[54]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => data_valid_i, D => tempData0216_out, Q => \^scrambler\(8), R => '0' ); \scrambler_reg[55]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => data_valid_i, D => tempData0220_out, Q => \^scrambler\(9), R => '0' ); \scrambler_reg[56]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => data_valid_i, D => tempData0224_out, Q => \^scrambler\(10), R => '0' ); \scrambler_reg[57]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => data_valid_i, D => tempData0228_out, Q => \^scrambler\(11), R => '0' ); \scrambler_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => data_valid_i, D => tempData(5), Q => p_117_in, R => '0' ); \scrambler_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => data_valid_i, D => tempData024_out, Q => p_121_in, R => '0' ); \scrambler_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => data_valid_i, D => tempData028_out, Q => p_125_in, R => '0' ); \scrambler_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => data_valid_i, D => tempData032_out, Q => p_129_in, R => '0' ); \scrambler_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => data_valid_i, D => tempData036_out, Q => p_133_in, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_STANDARD_CC_MODULE is port ( DO_CC_reg_0 : out STD_LOGIC; Q : out STD_LOGIC; do_cc_r_reg0 : out STD_LOGIC; SR : in STD_LOGIC; \out\ : in STD_LOGIC; do_cc_r : in STD_LOGIC; TXDATAVALID_IN : in STD_LOGIC; channel_up_tx_if : in STD_LOGIC; \count_16d_srl_r_reg[0]_0\ : in STD_LOGIC; extend_cc_r : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_STANDARD_CC_MODULE; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_STANDARD_CC_MODULE is signal DO_CC0_n_0 : STD_LOGIC; signal DO_CC_i_2_n_0 : STD_LOGIC; signal \^q\ : STD_LOGIC; signal \cc_count_r_reg_n_0_[5]\ : STD_LOGIC; signal count_13d_flop_r : STD_LOGIC; signal count_13d_flop_r_i_1_n_0 : STD_LOGIC; signal count_13d_flop_r_i_2_n_0 : STD_LOGIC; signal count_13d_flop_r_i_3_n_0 : STD_LOGIC; signal \count_13d_srl_r_reg_n_0_[0]\ : STD_LOGIC; signal \count_13d_srl_r_reg_n_0_[10]\ : STD_LOGIC; signal \count_13d_srl_r_reg_n_0_[11]\ : STD_LOGIC; signal \count_13d_srl_r_reg_n_0_[1]\ : STD_LOGIC; signal \count_13d_srl_r_reg_n_0_[2]\ : STD_LOGIC; signal \count_13d_srl_r_reg_n_0_[3]\ : STD_LOGIC; signal \count_13d_srl_r_reg_n_0_[4]\ : STD_LOGIC; signal \count_13d_srl_r_reg_n_0_[5]\ : STD_LOGIC; signal \count_13d_srl_r_reg_n_0_[6]\ : STD_LOGIC; signal \count_13d_srl_r_reg_n_0_[7]\ : STD_LOGIC; signal \count_13d_srl_r_reg_n_0_[8]\ : STD_LOGIC; signal \count_13d_srl_r_reg_n_0_[9]\ : STD_LOGIC; signal count_16d_flop_r : STD_LOGIC; signal count_16d_flop_r0 : STD_LOGIC; signal count_16d_flop_r_i_1_n_0 : STD_LOGIC; signal count_16d_flop_r_i_3_n_0 : STD_LOGIC; signal count_16d_flop_r_i_4_n_0 : STD_LOGIC; signal \count_16d_srl_r[0]_i_1_n_0\ : STD_LOGIC; signal \count_16d_srl_r_reg_n_0_[0]\ : STD_LOGIC; signal \count_16d_srl_r_reg_n_0_[10]\ : STD_LOGIC; signal \count_16d_srl_r_reg_n_0_[11]\ : STD_LOGIC; signal \count_16d_srl_r_reg_n_0_[12]\ : STD_LOGIC; signal \count_16d_srl_r_reg_n_0_[13]\ : STD_LOGIC; signal \count_16d_srl_r_reg_n_0_[14]\ : STD_LOGIC; signal \count_16d_srl_r_reg_n_0_[1]\ : STD_LOGIC; signal \count_16d_srl_r_reg_n_0_[2]\ : STD_LOGIC; signal \count_16d_srl_r_reg_n_0_[3]\ : STD_LOGIC; signal \count_16d_srl_r_reg_n_0_[4]\ : STD_LOGIC; signal \count_16d_srl_r_reg_n_0_[5]\ : STD_LOGIC; signal \count_16d_srl_r_reg_n_0_[6]\ : STD_LOGIC; signal \count_16d_srl_r_reg_n_0_[7]\ : STD_LOGIC; signal \count_16d_srl_r_reg_n_0_[8]\ : STD_LOGIC; signal \count_16d_srl_r_reg_n_0_[9]\ : STD_LOGIC; signal count_24d_flop_r : STD_LOGIC; signal count_24d_flop_r0 : STD_LOGIC; signal count_24d_flop_r_i_1_n_0 : STD_LOGIC; signal count_24d_flop_r_i_3_n_0 : STD_LOGIC; signal count_24d_flop_r_i_4_n_0 : STD_LOGIC; signal count_24d_flop_r_i_5_n_0 : STD_LOGIC; signal count_24d_flop_r_i_6_n_0 : STD_LOGIC; signal count_24d_srl_r0 : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[0]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[10]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[11]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[12]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[13]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[14]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[15]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[16]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[17]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[18]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[19]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[1]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[20]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[21]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[22]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[2]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[3]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[4]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[5]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[6]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[7]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[8]\ : STD_LOGIC; signal \count_24d_srl_r_reg_n_0_[9]\ : STD_LOGIC; signal p_1_in : STD_LOGIC_VECTOR ( 4 downto 0 ); signal p_2_out : STD_LOGIC_VECTOR ( 5 to 5 ); signal reset_r : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of do_cc_r_i_1 : label is "soft_lutpair101"; attribute SOFT_HLUTNM of tx_dst_rdy_n_r_i_1 : label is "soft_lutpair101"; begin Q <= \^q\; DO_CC0: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFE" ) port map ( I0 => p_1_in(0), I1 => \cc_count_r_reg_n_0_[5]\, I2 => p_1_in(3), I3 => p_1_in(4), I4 => p_1_in(1), I5 => p_1_in(2), O => DO_CC0_n_0 ); DO_CC_i_2: unisim.vcomponents.LUT5 generic map( INIT => X"FEEEEEEE" ) port map ( I0 => DO_CC0_n_0, I1 => reset_r, I2 => \count_13d_srl_r_reg_n_0_[11]\, I3 => \count_16d_srl_r_reg_n_0_[14]\, I4 => \count_24d_srl_r_reg_n_0_[22]\, O => DO_CC_i_2_n_0 ); DO_CC_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => DO_CC_i_2_n_0, Q => \^q\, R => SR ); \cc_count_r[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"80FF" ) port map ( I0 => \count_24d_srl_r_reg_n_0_[22]\, I1 => \count_16d_srl_r_reg_n_0_[14]\, I2 => \count_13d_srl_r_reg_n_0_[11]\, I3 => \count_16d_srl_r_reg[0]_0\, O => p_2_out(5) ); \cc_count_r_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => p_2_out(5), Q => p_1_in(4), R => '0' ); \cc_count_r_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => p_1_in(4), Q => p_1_in(3), R => '0' ); \cc_count_r_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => p_1_in(3), Q => p_1_in(2), R => '0' ); \cc_count_r_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => p_1_in(2), Q => p_1_in(1), R => '0' ); \cc_count_r_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => p_1_in(1), Q => p_1_in(0), R => '0' ); \cc_count_r_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => p_1_in(0), Q => \cc_count_r_reg_n_0_[5]\, R => '0' ); count_13d_flop_r_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"EAAA" ) port map ( I0 => \count_13d_srl_r_reg_n_0_[11]\, I1 => count_13d_flop_r_i_2_n_0, I2 => count_13d_flop_r_i_3_n_0, I3 => reset_r, O => count_13d_flop_r_i_1_n_0 ); count_13d_flop_r_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000001" ) port map ( I0 => \count_13d_srl_r_reg_n_0_[9]\, I1 => \count_13d_srl_r_reg_n_0_[8]\, I2 => \count_13d_srl_r_reg_n_0_[11]\, I3 => \count_13d_srl_r_reg_n_0_[10]\, I4 => \count_13d_srl_r_reg_n_0_[6]\, I5 => \count_13d_srl_r_reg_n_0_[7]\, O => count_13d_flop_r_i_2_n_0 ); count_13d_flop_r_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000001" ) port map ( I0 => \count_13d_srl_r_reg_n_0_[3]\, I1 => \count_13d_srl_r_reg_n_0_[2]\, I2 => \count_13d_srl_r_reg_n_0_[5]\, I3 => \count_13d_srl_r_reg_n_0_[4]\, I4 => \count_13d_srl_r_reg_n_0_[0]\, I5 => \count_13d_srl_r_reg_n_0_[1]\, O => count_13d_flop_r_i_3_n_0 ); count_13d_flop_r_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => count_13d_flop_r_i_1_n_0, Q => count_13d_flop_r, R => SR ); \count_13d_srl_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => count_13d_flop_r, Q => \count_13d_srl_r_reg_n_0_[0]\, R => '0' ); \count_13d_srl_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \count_13d_srl_r_reg_n_0_[9]\, Q => \count_13d_srl_r_reg_n_0_[10]\, R => '0' ); \count_13d_srl_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \count_13d_srl_r_reg_n_0_[10]\, Q => \count_13d_srl_r_reg_n_0_[11]\, R => '0' ); \count_13d_srl_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \count_13d_srl_r_reg_n_0_[0]\, Q => \count_13d_srl_r_reg_n_0_[1]\, R => '0' ); \count_13d_srl_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \count_13d_srl_r_reg_n_0_[1]\, Q => \count_13d_srl_r_reg_n_0_[2]\, R => '0' ); \count_13d_srl_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \count_13d_srl_r_reg_n_0_[2]\, Q => \count_13d_srl_r_reg_n_0_[3]\, R => '0' ); \count_13d_srl_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \count_13d_srl_r_reg_n_0_[3]\, Q => \count_13d_srl_r_reg_n_0_[4]\, R => '0' ); \count_13d_srl_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \count_13d_srl_r_reg_n_0_[4]\, Q => \count_13d_srl_r_reg_n_0_[5]\, R => '0' ); \count_13d_srl_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \count_13d_srl_r_reg_n_0_[5]\, Q => \count_13d_srl_r_reg_n_0_[6]\, R => '0' ); \count_13d_srl_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \count_13d_srl_r_reg_n_0_[6]\, Q => \count_13d_srl_r_reg_n_0_[7]\, R => '0' ); \count_13d_srl_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \count_13d_srl_r_reg_n_0_[7]\, Q => \count_13d_srl_r_reg_n_0_[8]\, R => '0' ); \count_13d_srl_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \count_13d_srl_r_reg_n_0_[8]\, Q => \count_13d_srl_r_reg_n_0_[9]\, R => '0' ); count_16d_flop_r_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"FBF8" ) port map ( I0 => \count_16d_srl_r_reg_n_0_[14]\, I1 => \count_13d_srl_r_reg_n_0_[11]\, I2 => count_16d_flop_r0, I3 => count_16d_flop_r, O => count_16d_flop_r_i_1_n_0 ); count_16d_flop_r_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000002000000000" ) port map ( I0 => count_16d_flop_r_i_3_n_0, I1 => \count_16d_srl_r_reg_n_0_[14]\, I2 => reset_r, I3 => \count_16d_srl_r_reg_n_0_[12]\, I4 => \count_16d_srl_r_reg_n_0_[13]\, I5 => count_16d_flop_r_i_4_n_0, O => count_16d_flop_r0 ); count_16d_flop_r_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000001" ) port map ( I0 => \count_16d_srl_r_reg_n_0_[3]\, I1 => \count_16d_srl_r_reg_n_0_[2]\, I2 => \count_16d_srl_r_reg_n_0_[5]\, I3 => \count_16d_srl_r_reg_n_0_[4]\, I4 => \count_16d_srl_r_reg_n_0_[0]\, I5 => \count_16d_srl_r_reg_n_0_[1]\, O => count_16d_flop_r_i_3_n_0 ); count_16d_flop_r_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000001" ) port map ( I0 => \count_16d_srl_r_reg_n_0_[9]\, I1 => \count_16d_srl_r_reg_n_0_[8]\, I2 => \count_16d_srl_r_reg_n_0_[11]\, I3 => \count_16d_srl_r_reg_n_0_[10]\, I4 => \count_16d_srl_r_reg_n_0_[6]\, I5 => \count_16d_srl_r_reg_n_0_[7]\, O => count_16d_flop_r_i_4_n_0 ); count_16d_flop_r_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => count_16d_flop_r_i_1_n_0, Q => count_16d_flop_r, R => SR ); \count_16d_srl_r[0]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \count_13d_srl_r_reg_n_0_[11]\, I1 => \count_16d_srl_r_reg[0]_0\, O => \count_16d_srl_r[0]_i_1_n_0\ ); \count_16d_srl_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => \count_16d_srl_r[0]_i_1_n_0\, D => count_16d_flop_r, Q => \count_16d_srl_r_reg_n_0_[0]\, R => '0' ); \count_16d_srl_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => \count_16d_srl_r[0]_i_1_n_0\, D => \count_16d_srl_r_reg_n_0_[9]\, Q => \count_16d_srl_r_reg_n_0_[10]\, R => '0' ); \count_16d_srl_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => \count_16d_srl_r[0]_i_1_n_0\, D => \count_16d_srl_r_reg_n_0_[10]\, Q => \count_16d_srl_r_reg_n_0_[11]\, R => '0' ); \count_16d_srl_r_reg[12]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => \count_16d_srl_r[0]_i_1_n_0\, D => \count_16d_srl_r_reg_n_0_[11]\, Q => \count_16d_srl_r_reg_n_0_[12]\, R => '0' ); \count_16d_srl_r_reg[13]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => \count_16d_srl_r[0]_i_1_n_0\, D => \count_16d_srl_r_reg_n_0_[12]\, Q => \count_16d_srl_r_reg_n_0_[13]\, R => '0' ); \count_16d_srl_r_reg[14]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => \count_16d_srl_r[0]_i_1_n_0\, D => \count_16d_srl_r_reg_n_0_[13]\, Q => \count_16d_srl_r_reg_n_0_[14]\, R => '0' ); \count_16d_srl_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => \count_16d_srl_r[0]_i_1_n_0\, D => \count_16d_srl_r_reg_n_0_[0]\, Q => \count_16d_srl_r_reg_n_0_[1]\, R => '0' ); \count_16d_srl_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => \count_16d_srl_r[0]_i_1_n_0\, D => \count_16d_srl_r_reg_n_0_[1]\, Q => \count_16d_srl_r_reg_n_0_[2]\, R => '0' ); \count_16d_srl_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => \count_16d_srl_r[0]_i_1_n_0\, D => \count_16d_srl_r_reg_n_0_[2]\, Q => \count_16d_srl_r_reg_n_0_[3]\, R => '0' ); \count_16d_srl_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => \count_16d_srl_r[0]_i_1_n_0\, D => \count_16d_srl_r_reg_n_0_[3]\, Q => \count_16d_srl_r_reg_n_0_[4]\, R => '0' ); \count_16d_srl_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => \count_16d_srl_r[0]_i_1_n_0\, D => \count_16d_srl_r_reg_n_0_[4]\, Q => \count_16d_srl_r_reg_n_0_[5]\, R => '0' ); \count_16d_srl_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => \count_16d_srl_r[0]_i_1_n_0\, D => \count_16d_srl_r_reg_n_0_[5]\, Q => \count_16d_srl_r_reg_n_0_[6]\, R => '0' ); \count_16d_srl_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => \count_16d_srl_r[0]_i_1_n_0\, D => \count_16d_srl_r_reg_n_0_[6]\, Q => \count_16d_srl_r_reg_n_0_[7]\, R => '0' ); \count_16d_srl_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => \count_16d_srl_r[0]_i_1_n_0\, D => \count_16d_srl_r_reg_n_0_[7]\, Q => \count_16d_srl_r_reg_n_0_[8]\, R => '0' ); \count_16d_srl_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => \count_16d_srl_r[0]_i_1_n_0\, D => \count_16d_srl_r_reg_n_0_[8]\, Q => \count_16d_srl_r_reg_n_0_[9]\, R => '0' ); count_24d_flop_r_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"FFBFFF80" ) port map ( I0 => \count_24d_srl_r_reg_n_0_[22]\, I1 => \count_13d_srl_r_reg_n_0_[11]\, I2 => \count_16d_srl_r_reg_n_0_[14]\, I3 => count_24d_flop_r0, I4 => count_24d_flop_r, O => count_24d_flop_r_i_1_n_0 ); count_24d_flop_r_i_2: unisim.vcomponents.LUT4 generic map( INIT => X"8000" ) port map ( I0 => count_24d_flop_r_i_3_n_0, I1 => count_24d_flop_r_i_4_n_0, I2 => count_24d_flop_r_i_5_n_0, I3 => count_24d_flop_r_i_6_n_0, O => count_24d_flop_r0 ); count_24d_flop_r_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000001" ) port map ( I0 => \count_24d_srl_r_reg_n_0_[9]\, I1 => \count_24d_srl_r_reg_n_0_[8]\, I2 => \count_24d_srl_r_reg_n_0_[11]\, I3 => \count_24d_srl_r_reg_n_0_[10]\, I4 => \count_24d_srl_r_reg_n_0_[6]\, I5 => \count_24d_srl_r_reg_n_0_[7]\, O => count_24d_flop_r_i_3_n_0 ); count_24d_flop_r_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000010" ) port map ( I0 => \count_24d_srl_r_reg_n_0_[21]\, I1 => \count_24d_srl_r_reg_n_0_[20]\, I2 => reset_r, I3 => \count_24d_srl_r_reg_n_0_[22]\, I4 => \count_24d_srl_r_reg_n_0_[18]\, I5 => \count_24d_srl_r_reg_n_0_[19]\, O => count_24d_flop_r_i_4_n_0 ); count_24d_flop_r_i_5: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000001" ) port map ( I0 => \count_24d_srl_r_reg_n_0_[15]\, I1 => \count_24d_srl_r_reg_n_0_[14]\, I2 => \count_24d_srl_r_reg_n_0_[17]\, I3 => \count_24d_srl_r_reg_n_0_[16]\, I4 => \count_24d_srl_r_reg_n_0_[12]\, I5 => \count_24d_srl_r_reg_n_0_[13]\, O => count_24d_flop_r_i_5_n_0 ); count_24d_flop_r_i_6: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000001" ) port map ( I0 => \count_24d_srl_r_reg_n_0_[3]\, I1 => \count_24d_srl_r_reg_n_0_[2]\, I2 => \count_24d_srl_r_reg_n_0_[5]\, I3 => \count_24d_srl_r_reg_n_0_[4]\, I4 => \count_24d_srl_r_reg_n_0_[0]\, I5 => \count_24d_srl_r_reg_n_0_[1]\, O => count_24d_flop_r_i_6_n_0 ); count_24d_flop_r_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => count_24d_flop_r_i_1_n_0, Q => count_24d_flop_r, R => SR ); \count_24d_srl_r[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"8F" ) port map ( I0 => \count_13d_srl_r_reg_n_0_[11]\, I1 => \count_16d_srl_r_reg_n_0_[14]\, I2 => \count_16d_srl_r_reg[0]_0\, O => count_24d_srl_r0 ); \count_24d_srl_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => count_24d_srl_r0, D => count_24d_flop_r, Q => \count_24d_srl_r_reg_n_0_[0]\, R => '0' ); \count_24d_srl_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[9]\, Q => \count_24d_srl_r_reg_n_0_[10]\, R => '0' ); \count_24d_srl_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[10]\, Q => \count_24d_srl_r_reg_n_0_[11]\, R => '0' ); \count_24d_srl_r_reg[12]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[11]\, Q => \count_24d_srl_r_reg_n_0_[12]\, R => '0' ); \count_24d_srl_r_reg[13]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[12]\, Q => \count_24d_srl_r_reg_n_0_[13]\, R => '0' ); \count_24d_srl_r_reg[14]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[13]\, Q => \count_24d_srl_r_reg_n_0_[14]\, R => '0' ); \count_24d_srl_r_reg[15]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[14]\, Q => \count_24d_srl_r_reg_n_0_[15]\, R => '0' ); \count_24d_srl_r_reg[16]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[15]\, Q => \count_24d_srl_r_reg_n_0_[16]\, R => '0' ); \count_24d_srl_r_reg[17]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[16]\, Q => \count_24d_srl_r_reg_n_0_[17]\, R => '0' ); \count_24d_srl_r_reg[18]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[17]\, Q => \count_24d_srl_r_reg_n_0_[18]\, R => '0' ); \count_24d_srl_r_reg[19]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[18]\, Q => \count_24d_srl_r_reg_n_0_[19]\, R => '0' ); \count_24d_srl_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[0]\, Q => \count_24d_srl_r_reg_n_0_[1]\, R => '0' ); \count_24d_srl_r_reg[20]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[19]\, Q => \count_24d_srl_r_reg_n_0_[20]\, R => '0' ); \count_24d_srl_r_reg[21]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[20]\, Q => \count_24d_srl_r_reg_n_0_[21]\, R => '0' ); \count_24d_srl_r_reg[22]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[21]\, Q => \count_24d_srl_r_reg_n_0_[22]\, R => '0' ); \count_24d_srl_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[1]\, Q => \count_24d_srl_r_reg_n_0_[2]\, R => '0' ); \count_24d_srl_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[2]\, Q => \count_24d_srl_r_reg_n_0_[3]\, R => '0' ); \count_24d_srl_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[3]\, Q => \count_24d_srl_r_reg_n_0_[4]\, R => '0' ); \count_24d_srl_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[4]\, Q => \count_24d_srl_r_reg_n_0_[5]\, R => '0' ); \count_24d_srl_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[5]\, Q => \count_24d_srl_r_reg_n_0_[6]\, R => '0' ); \count_24d_srl_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[6]\, Q => \count_24d_srl_r_reg_n_0_[7]\, R => '0' ); \count_24d_srl_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[7]\, Q => \count_24d_srl_r_reg_n_0_[8]\, R => '0' ); \count_24d_srl_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => count_24d_srl_r0, D => \count_24d_srl_r_reg_n_0_[8]\, Q => \count_24d_srl_r_reg_n_0_[9]\, R => '0' ); do_cc_r_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^q\, I1 => extend_cc_r, O => do_cc_r_reg0 ); reset_r_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => SR, Q => reset_r, R => '0' ); tx_dst_rdy_n_r_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"EFFF" ) port map ( I0 => \^q\, I1 => do_cc_r, I2 => TXDATAVALID_IN, I3 => channel_up_tx_if, O => DO_CC_reg_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_SYM_DEC is port ( rx_pe_data_v_i : out STD_LOGIC; illegal_btf_i : out STD_LOGIC; RX_IDLE : out STD_LOGIC; remote_ready_i : out STD_LOGIC; \RX_PE_DATA_reg[0]_0\ : out STD_LOGIC_VECTOR ( 63 downto 0 ); rxdatavalid_i : in STD_LOGIC; \out\ : in STD_LOGIC; SR : in STD_LOGIC_VECTOR ( 0 to 0 ); \RX_DATA_REG_reg[0]_0\ : in STD_LOGIC; RX_HEADER_1_REG_reg_0 : in STD_LOGIC_VECTOR ( 65 downto 0 ); \rx_na_idles_cntr_reg[0]_0\ : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_SYM_DEC; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_SYM_DEC is signal ILLEGAL_BTF0 : STD_LOGIC; signal ILLEGAL_BTF_i_2_n_0 : STD_LOGIC; signal ILLEGAL_BTF_i_3_n_0 : STD_LOGIC; signal ILLEGAL_BTF_i_4_n_0 : STD_LOGIC; signal ILLEGAL_BTF_i_5_n_0 : STD_LOGIC; signal RXDATAVALID_IN_REG : STD_LOGIC; signal RX_IDLE_i_2_n_0 : STD_LOGIC; signal RX_NA_IDLE : STD_LOGIC; signal RX_NA_IDLE_i_2_n_0 : STD_LOGIC; signal p_0_in : STD_LOGIC_VECTOR ( 15 downto 0 ); signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); signal remote_rdy_cntr : STD_LOGIC_VECTOR ( 0 to 2 ); signal \remote_rdy_cntr[0]_i_1_n_0\ : STD_LOGIC; signal \remote_rdy_cntr[0]_i_2_n_0\ : STD_LOGIC; signal \remote_rdy_cntr[0]_i_3_n_0\ : STD_LOGIC; signal \remote_rdy_cntr[1]_i_1_n_0\ : STD_LOGIC; signal \remote_rdy_cntr[2]_i_1_n_0\ : STD_LOGIC; signal remote_ready_det : STD_LOGIC; signal remote_ready_det0 : STD_LOGIC; signal rx_idle_c : STD_LOGIC; signal rx_na_idle_c : STD_LOGIC; signal \rx_na_idles_cntr[4]_i_1_n_0\ : STD_LOGIC; signal \rx_na_idles_cntr_reg__0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); signal rxdata_s : STD_LOGIC_VECTOR ( 63 downto 16 ); signal sync_header_c : STD_LOGIC_VECTOR ( 0 to 1 ); signal valid_d : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of ILLEGAL_BTF_i_3 : label is "soft_lutpair90"; attribute SOFT_HLUTNM of RX_NA_IDLE_i_2 : label is "soft_lutpair90"; attribute SOFT_HLUTNM of \remote_rdy_cntr[0]_i_1\ : label is "soft_lutpair87"; attribute SOFT_HLUTNM of \remote_rdy_cntr[0]_i_3\ : label is "soft_lutpair88"; attribute SOFT_HLUTNM of \remote_rdy_cntr[1]_i_1\ : label is "soft_lutpair87"; attribute SOFT_HLUTNM of \remote_rdy_cntr[2]_i_1\ : label is "soft_lutpair89"; attribute SOFT_HLUTNM of remote_ready_r_i_1 : label is "soft_lutpair89"; attribute SOFT_HLUTNM of \rx_na_idles_cntr[0]_i_1\ : label is "soft_lutpair92"; attribute SOFT_HLUTNM of \rx_na_idles_cntr[1]_i_1\ : label is "soft_lutpair92"; attribute SOFT_HLUTNM of \rx_na_idles_cntr[2]_i_1\ : label is "soft_lutpair91"; attribute SOFT_HLUTNM of \rx_na_idles_cntr[3]_i_1\ : label is "soft_lutpair91"; attribute SOFT_HLUTNM of \rx_na_idles_cntr[4]_i_2\ : label is "soft_lutpair88"; begin ILLEGAL_BTF_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFEF0000EEEB0000" ) port map ( I0 => ILLEGAL_BTF_i_2_n_0, I1 => p_0_in(6), I2 => p_0_in(4), I3 => p_0_in(7), I4 => ILLEGAL_BTF_i_3_n_0, I5 => p_0_in(5), O => ILLEGAL_BTF0 ); ILLEGAL_BTF_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFEFF" ) port map ( I0 => ILLEGAL_BTF_i_4_n_0, I1 => p_0_in(9), I2 => p_0_in(8), I3 => p_0_in(11), I4 => p_0_in(10), I5 => ILLEGAL_BTF_i_5_n_0, O => ILLEGAL_BTF_i_2_n_0 ); ILLEGAL_BTF_i_3: unisim.vcomponents.LUT4 generic map( INIT => X"0800" ) port map ( I0 => RXDATAVALID_IN_REG, I1 => sync_header_c(0), I2 => sync_header_c(1), I3 => \rx_na_idles_cntr_reg[0]_0\, O => ILLEGAL_BTF_i_3_n_0 ); ILLEGAL_BTF_i_4: unisim.vcomponents.LUT4 generic map( INIT => X"FF7F" ) port map ( I0 => p_0_in(13), I1 => p_0_in(12), I2 => p_0_in(14), I3 => p_0_in(15), O => ILLEGAL_BTF_i_4_n_0 ); ILLEGAL_BTF_i_5: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => p_0_in(1), I1 => p_0_in(0), I2 => p_0_in(3), I3 => p_0_in(2), O => ILLEGAL_BTF_i_5_n_0 ); ILLEGAL_BTF_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => ILLEGAL_BTF0, Q => illegal_btf_i, R => SR(0) ); RXDATAVALID_IN_REG_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => rxdatavalid_i, Q => RXDATAVALID_IN_REG, R => '0' ); \RX_DATA_REG_reg[0]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(0), Q => rxdata_s(56), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[10]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(10), Q => rxdata_s(50), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[11]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(11), Q => rxdata_s(51), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[12]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(12), Q => rxdata_s(52), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[13]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(13), Q => rxdata_s(53), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[14]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(14), Q => rxdata_s(54), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[15]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(15), Q => rxdata_s(55), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[16]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(16), Q => rxdata_s(40), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[17]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(17), Q => rxdata_s(41), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[18]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(18), Q => rxdata_s(42), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[19]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(19), Q => rxdata_s(43), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[1]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(1), Q => rxdata_s(57), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[20]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(20), Q => rxdata_s(44), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[21]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(21), Q => rxdata_s(45), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[22]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(22), Q => rxdata_s(46), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[23]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(23), Q => rxdata_s(47), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[24]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(24), Q => rxdata_s(32), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[25]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(25), Q => rxdata_s(33), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[26]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(26), Q => rxdata_s(34), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[27]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(27), Q => rxdata_s(35), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[28]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(28), Q => rxdata_s(36), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[29]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(29), Q => rxdata_s(37), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[2]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(2), Q => rxdata_s(58), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[30]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(30), Q => rxdata_s(38), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[31]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(31), Q => rxdata_s(39), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[32]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(32), Q => rxdata_s(24), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[33]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(33), Q => rxdata_s(25), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[34]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(34), Q => rxdata_s(26), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[35]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(35), Q => rxdata_s(27), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[36]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(36), Q => rxdata_s(28), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[37]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(37), Q => rxdata_s(29), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[38]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(38), Q => rxdata_s(30), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[39]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(39), Q => rxdata_s(31), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[3]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(3), Q => rxdata_s(59), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[40]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(40), Q => rxdata_s(16), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[41]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(41), Q => rxdata_s(17), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[42]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(42), Q => rxdata_s(18), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[43]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(43), Q => rxdata_s(19), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[44]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(44), Q => rxdata_s(20), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[45]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(45), Q => rxdata_s(21), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[46]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(46), Q => rxdata_s(22), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[47]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(47), Q => rxdata_s(23), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[48]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(48), Q => p_0_in(0), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[49]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(49), Q => p_0_in(1), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[4]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(4), Q => rxdata_s(60), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[50]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(50), Q => p_0_in(2), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[51]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(51), Q => p_0_in(3), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[52]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(52), Q => p_0_in(4), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[53]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(53), Q => p_0_in(5), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[54]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(54), Q => p_0_in(6), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[55]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(55), Q => p_0_in(7), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[56]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(56), Q => p_0_in(8), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[57]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(57), Q => p_0_in(9), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[58]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(58), Q => p_0_in(10), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[59]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(59), Q => p_0_in(11), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[5]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(5), Q => rxdata_s(61), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[60]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(60), Q => p_0_in(12), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[61]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(61), Q => p_0_in(13), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[62]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(62), Q => p_0_in(14), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[63]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(63), Q => p_0_in(15), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[6]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(6), Q => rxdata_s(62), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[7]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(7), Q => rxdata_s(63), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[8]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(8), Q => rxdata_s(48), R => \RX_DATA_REG_reg[0]_0\ ); \RX_DATA_REG_reg[9]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(9), Q => rxdata_s(49), R => \RX_DATA_REG_reg[0]_0\ ); RX_HEADER_0_REG_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(64), Q => sync_header_c(1), R => \RX_DATA_REG_reg[0]_0\ ); RX_HEADER_1_REG_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => RX_HEADER_1_REG_reg_0(65), Q => sync_header_c(0), R => \RX_DATA_REG_reg[0]_0\ ); RX_IDLE_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000100000" ) port map ( I0 => RX_IDLE_i_2_n_0, I1 => p_0_in(5), I2 => p_0_in(4), I3 => sync_header_c(1), I4 => sync_header_c(0), I5 => ILLEGAL_BTF_i_2_n_0, O => rx_idle_c ); RX_IDLE_i_2: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => p_0_in(6), I1 => p_0_in(7), O => RX_IDLE_i_2_n_0 ); RX_IDLE_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => rx_idle_c, Q => RX_IDLE, R => SR(0) ); RX_NA_IDLE_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000080" ) port map ( I0 => RX_NA_IDLE_i_2_n_0, I1 => p_0_in(5), I2 => p_0_in(4), I3 => p_0_in(7), I4 => p_0_in(6), I5 => ILLEGAL_BTF_i_2_n_0, O => rx_na_idle_c ); RX_NA_IDLE_i_2: unisim.vcomponents.LUT3 generic map( INIT => X"40" ) port map ( I0 => sync_header_c(1), I1 => sync_header_c(0), I2 => RXDATAVALID_IN_REG, O => RX_NA_IDLE_i_2_n_0 ); RX_NA_IDLE_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => rx_na_idle_c, Q => RX_NA_IDLE, R => SR(0) ); RX_PE_DATA_V_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"40" ) port map ( I0 => sync_header_c(0), I1 => RXDATAVALID_IN_REG, I2 => sync_header_c(1), O => valid_d ); RX_PE_DATA_V_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => valid_d, Q => rx_pe_data_v_i, R => SR(0) ); \RX_PE_DATA_reg[0]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(63), Q => \RX_PE_DATA_reg[0]_0\(63), R => SR(0) ); \RX_PE_DATA_reg[10]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(53), Q => \RX_PE_DATA_reg[0]_0\(53), R => SR(0) ); \RX_PE_DATA_reg[11]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(52), Q => \RX_PE_DATA_reg[0]_0\(52), R => SR(0) ); \RX_PE_DATA_reg[12]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(51), Q => \RX_PE_DATA_reg[0]_0\(51), R => SR(0) ); \RX_PE_DATA_reg[13]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(50), Q => \RX_PE_DATA_reg[0]_0\(50), R => SR(0) ); \RX_PE_DATA_reg[14]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(49), Q => \RX_PE_DATA_reg[0]_0\(49), R => SR(0) ); \RX_PE_DATA_reg[15]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(48), Q => \RX_PE_DATA_reg[0]_0\(48), R => SR(0) ); \RX_PE_DATA_reg[16]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(47), Q => \RX_PE_DATA_reg[0]_0\(47), R => SR(0) ); \RX_PE_DATA_reg[17]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(46), Q => \RX_PE_DATA_reg[0]_0\(46), R => SR(0) ); \RX_PE_DATA_reg[18]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(45), Q => \RX_PE_DATA_reg[0]_0\(45), R => SR(0) ); \RX_PE_DATA_reg[19]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(44), Q => \RX_PE_DATA_reg[0]_0\(44), R => SR(0) ); \RX_PE_DATA_reg[1]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(62), Q => \RX_PE_DATA_reg[0]_0\(62), R => SR(0) ); \RX_PE_DATA_reg[20]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(43), Q => \RX_PE_DATA_reg[0]_0\(43), R => SR(0) ); \RX_PE_DATA_reg[21]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(42), Q => \RX_PE_DATA_reg[0]_0\(42), R => SR(0) ); \RX_PE_DATA_reg[22]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(41), Q => \RX_PE_DATA_reg[0]_0\(41), R => SR(0) ); \RX_PE_DATA_reg[23]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(40), Q => \RX_PE_DATA_reg[0]_0\(40), R => SR(0) ); \RX_PE_DATA_reg[24]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(39), Q => \RX_PE_DATA_reg[0]_0\(39), R => SR(0) ); \RX_PE_DATA_reg[25]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(38), Q => \RX_PE_DATA_reg[0]_0\(38), R => SR(0) ); \RX_PE_DATA_reg[26]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(37), Q => \RX_PE_DATA_reg[0]_0\(37), R => SR(0) ); \RX_PE_DATA_reg[27]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(36), Q => \RX_PE_DATA_reg[0]_0\(36), R => SR(0) ); \RX_PE_DATA_reg[28]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(35), Q => \RX_PE_DATA_reg[0]_0\(35), R => SR(0) ); \RX_PE_DATA_reg[29]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(34), Q => \RX_PE_DATA_reg[0]_0\(34), R => SR(0) ); \RX_PE_DATA_reg[2]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(61), Q => \RX_PE_DATA_reg[0]_0\(61), R => SR(0) ); \RX_PE_DATA_reg[30]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(33), Q => \RX_PE_DATA_reg[0]_0\(33), R => SR(0) ); \RX_PE_DATA_reg[31]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(32), Q => \RX_PE_DATA_reg[0]_0\(32), R => SR(0) ); \RX_PE_DATA_reg[32]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(31), Q => \RX_PE_DATA_reg[0]_0\(31), R => SR(0) ); \RX_PE_DATA_reg[33]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(30), Q => \RX_PE_DATA_reg[0]_0\(30), R => SR(0) ); \RX_PE_DATA_reg[34]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(29), Q => \RX_PE_DATA_reg[0]_0\(29), R => SR(0) ); \RX_PE_DATA_reg[35]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(28), Q => \RX_PE_DATA_reg[0]_0\(28), R => SR(0) ); \RX_PE_DATA_reg[36]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(27), Q => \RX_PE_DATA_reg[0]_0\(27), R => SR(0) ); \RX_PE_DATA_reg[37]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(26), Q => \RX_PE_DATA_reg[0]_0\(26), R => SR(0) ); \RX_PE_DATA_reg[38]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(25), Q => \RX_PE_DATA_reg[0]_0\(25), R => SR(0) ); \RX_PE_DATA_reg[39]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(24), Q => \RX_PE_DATA_reg[0]_0\(24), R => SR(0) ); \RX_PE_DATA_reg[3]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(60), Q => \RX_PE_DATA_reg[0]_0\(60), R => SR(0) ); \RX_PE_DATA_reg[40]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(23), Q => \RX_PE_DATA_reg[0]_0\(23), R => SR(0) ); \RX_PE_DATA_reg[41]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(22), Q => \RX_PE_DATA_reg[0]_0\(22), R => SR(0) ); \RX_PE_DATA_reg[42]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(21), Q => \RX_PE_DATA_reg[0]_0\(21), R => SR(0) ); \RX_PE_DATA_reg[43]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(20), Q => \RX_PE_DATA_reg[0]_0\(20), R => SR(0) ); \RX_PE_DATA_reg[44]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(19), Q => \RX_PE_DATA_reg[0]_0\(19), R => SR(0) ); \RX_PE_DATA_reg[45]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(18), Q => \RX_PE_DATA_reg[0]_0\(18), R => SR(0) ); \RX_PE_DATA_reg[46]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(17), Q => \RX_PE_DATA_reg[0]_0\(17), R => SR(0) ); \RX_PE_DATA_reg[47]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(16), Q => \RX_PE_DATA_reg[0]_0\(16), R => SR(0) ); \RX_PE_DATA_reg[48]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => p_0_in(7), Q => \RX_PE_DATA_reg[0]_0\(15), R => SR(0) ); \RX_PE_DATA_reg[49]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => p_0_in(6), Q => \RX_PE_DATA_reg[0]_0\(14), R => SR(0) ); \RX_PE_DATA_reg[4]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(59), Q => \RX_PE_DATA_reg[0]_0\(59), R => SR(0) ); \RX_PE_DATA_reg[50]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => p_0_in(5), Q => \RX_PE_DATA_reg[0]_0\(13), R => SR(0) ); \RX_PE_DATA_reg[51]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => p_0_in(4), Q => \RX_PE_DATA_reg[0]_0\(12), R => SR(0) ); \RX_PE_DATA_reg[52]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => p_0_in(3), Q => \RX_PE_DATA_reg[0]_0\(11), R => SR(0) ); \RX_PE_DATA_reg[53]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => p_0_in(2), Q => \RX_PE_DATA_reg[0]_0\(10), R => SR(0) ); \RX_PE_DATA_reg[54]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => p_0_in(1), Q => \RX_PE_DATA_reg[0]_0\(9), R => SR(0) ); \RX_PE_DATA_reg[55]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => p_0_in(0), Q => \RX_PE_DATA_reg[0]_0\(8), R => SR(0) ); \RX_PE_DATA_reg[56]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => p_0_in(15), Q => \RX_PE_DATA_reg[0]_0\(7), R => SR(0) ); \RX_PE_DATA_reg[57]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => p_0_in(14), Q => \RX_PE_DATA_reg[0]_0\(6), R => SR(0) ); \RX_PE_DATA_reg[58]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => p_0_in(13), Q => \RX_PE_DATA_reg[0]_0\(5), R => SR(0) ); \RX_PE_DATA_reg[59]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => p_0_in(12), Q => \RX_PE_DATA_reg[0]_0\(4), R => SR(0) ); \RX_PE_DATA_reg[5]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(58), Q => \RX_PE_DATA_reg[0]_0\(58), R => SR(0) ); \RX_PE_DATA_reg[60]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => p_0_in(11), Q => \RX_PE_DATA_reg[0]_0\(3), R => SR(0) ); \RX_PE_DATA_reg[61]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => p_0_in(10), Q => \RX_PE_DATA_reg[0]_0\(2), R => SR(0) ); \RX_PE_DATA_reg[62]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => p_0_in(9), Q => \RX_PE_DATA_reg[0]_0\(1), R => SR(0) ); \RX_PE_DATA_reg[63]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => p_0_in(8), Q => \RX_PE_DATA_reg[0]_0\(0), R => SR(0) ); \RX_PE_DATA_reg[6]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(57), Q => \RX_PE_DATA_reg[0]_0\(57), R => SR(0) ); \RX_PE_DATA_reg[7]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(56), Q => \RX_PE_DATA_reg[0]_0\(56), R => SR(0) ); \RX_PE_DATA_reg[8]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(55), Q => \RX_PE_DATA_reg[0]_0\(55), R => SR(0) ); \RX_PE_DATA_reg[9]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => valid_d, D => rxdata_s(54), Q => \RX_PE_DATA_reg[0]_0\(54), R => SR(0) ); \remote_rdy_cntr[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"0000FF80" ) port map ( I0 => remote_ready_det, I1 => remote_rdy_cntr(1), I2 => remote_rdy_cntr(2), I3 => remote_rdy_cntr(0), I4 => \remote_rdy_cntr[0]_i_2_n_0\, O => \remote_rdy_cntr[0]_i_1_n_0\ ); \remote_rdy_cntr[0]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"00004000FFFFFFFF" ) port map ( I0 => \remote_rdy_cntr[0]_i_3_n_0\, I1 => remote_rdy_cntr(0), I2 => remote_rdy_cntr(2), I3 => remote_rdy_cntr(1), I4 => \rx_na_idles_cntr_reg__0\(4), I5 => \rx_na_idles_cntr_reg[0]_0\, O => \remote_rdy_cntr[0]_i_2_n_0\ ); \remote_rdy_cntr[0]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"7FFF" ) port map ( I0 => \rx_na_idles_cntr_reg__0\(2), I1 => \rx_na_idles_cntr_reg__0\(0), I2 => \rx_na_idles_cntr_reg__0\(1), I3 => \rx_na_idles_cntr_reg__0\(3), O => \remote_rdy_cntr[0]_i_3_n_0\ ); \remote_rdy_cntr[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"0000EC6C" ) port map ( I0 => remote_ready_det, I1 => remote_rdy_cntr(1), I2 => remote_rdy_cntr(2), I3 => remote_rdy_cntr(0), I4 => \remote_rdy_cntr[0]_i_2_n_0\, O => \remote_rdy_cntr[1]_i_1_n_0\ ); \remote_rdy_cntr[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"0000D5AA" ) port map ( I0 => remote_rdy_cntr(2), I1 => remote_rdy_cntr(0), I2 => remote_rdy_cntr(1), I3 => remote_ready_det, I4 => \remote_rdy_cntr[0]_i_2_n_0\, O => \remote_rdy_cntr[2]_i_1_n_0\ ); \remote_rdy_cntr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => \remote_rdy_cntr[0]_i_1_n_0\, Q => remote_rdy_cntr(0), R => '0' ); \remote_rdy_cntr_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => \remote_rdy_cntr[1]_i_1_n_0\, Q => remote_rdy_cntr(1), R => '0' ); \remote_rdy_cntr_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => \remote_rdy_cntr[2]_i_1_n_0\, Q => remote_rdy_cntr(2), R => '0' ); remote_ready_det_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000020" ) port map ( I0 => ILLEGAL_BTF_i_3_n_0, I1 => p_0_in(5), I2 => p_0_in(4), I3 => p_0_in(7), I4 => p_0_in(6), I5 => ILLEGAL_BTF_i_2_n_0, O => remote_ready_det0 ); remote_ready_det_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => remote_ready_det0, Q => remote_ready_det, R => SR(0) ); remote_ready_r_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"80" ) port map ( I0 => remote_rdy_cntr(0), I1 => remote_rdy_cntr(2), I2 => remote_rdy_cntr(1), O => remote_ready_i ); \rx_na_idles_cntr[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \rx_na_idles_cntr_reg__0\(0), O => \p_0_in__0\(0) ); \rx_na_idles_cntr[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \rx_na_idles_cntr_reg__0\(0), I1 => \rx_na_idles_cntr_reg__0\(1), O => \p_0_in__0\(1) ); \rx_na_idles_cntr[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \rx_na_idles_cntr_reg__0\(1), I1 => \rx_na_idles_cntr_reg__0\(0), I2 => \rx_na_idles_cntr_reg__0\(2), O => \p_0_in__0\(2) ); \rx_na_idles_cntr[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \rx_na_idles_cntr_reg__0\(2), I1 => \rx_na_idles_cntr_reg__0\(0), I2 => \rx_na_idles_cntr_reg__0\(1), I3 => \rx_na_idles_cntr_reg__0\(3), O => \p_0_in__0\(3) ); \rx_na_idles_cntr[4]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7FFF" ) port map ( I0 => remote_rdy_cntr(0), I1 => remote_rdy_cntr(2), I2 => remote_rdy_cntr(1), I3 => \rx_na_idles_cntr_reg[0]_0\, O => \rx_na_idles_cntr[4]_i_1_n_0\ ); \rx_na_idles_cntr[4]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \rx_na_idles_cntr_reg__0\(3), I1 => \rx_na_idles_cntr_reg__0\(1), I2 => \rx_na_idles_cntr_reg__0\(0), I3 => \rx_na_idles_cntr_reg__0\(2), I4 => \rx_na_idles_cntr_reg__0\(4), O => \p_0_in__0\(4) ); \rx_na_idles_cntr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => RX_NA_IDLE, D => \p_0_in__0\(0), Q => \rx_na_idles_cntr_reg__0\(0), R => \rx_na_idles_cntr[4]_i_1_n_0\ ); \rx_na_idles_cntr_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => RX_NA_IDLE, D => \p_0_in__0\(1), Q => \rx_na_idles_cntr_reg__0\(1), R => \rx_na_idles_cntr[4]_i_1_n_0\ ); \rx_na_idles_cntr_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => RX_NA_IDLE, D => \p_0_in__0\(2), Q => \rx_na_idles_cntr_reg__0\(2), R => \rx_na_idles_cntr[4]_i_1_n_0\ ); \rx_na_idles_cntr_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => RX_NA_IDLE, D => \p_0_in__0\(3), Q => \rx_na_idles_cntr_reg__0\(3), R => \rx_na_idles_cntr[4]_i_1_n_0\ ); \rx_na_idles_cntr_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => RX_NA_IDLE, D => \p_0_in__0\(4), Q => \rx_na_idles_cntr_reg__0\(4), R => \rx_na_idles_cntr[4]_i_1_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_TX_STREAM_CONTROL_SM is port ( gen_cc_i : out STD_LOGIC; do_cc_r : out STD_LOGIC; extend_cc_r : out STD_LOGIC; s_axi_tx_tready : out STD_LOGIC; s_axi_tx_tvalid_0 : out STD_LOGIC; gen_cc_flop_0_i_0 : out STD_LOGIC; R0 : in STD_LOGIC; \out\ : in STD_LOGIC; do_cc_r_reg0 : in STD_LOGIC; tx_dst_rdy_n_r_reg_0 : in STD_LOGIC; extend_cc_r_reg_0 : in STD_LOGIC; s_axi_tx_tvalid : in STD_LOGIC; gen_ch_bond_i : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_TX_STREAM_CONTROL_SM; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_TX_STREAM_CONTROL_SM is signal \^do_cc_r\ : STD_LOGIC; signal \^gen_cc_i\ : STD_LOGIC; signal tx_dst_rdy_n_i : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of TX_PE_DATA_V_i_1 : label is "soft_lutpair102"; attribute BOX_TYPE : string; attribute BOX_TYPE of gen_cc_flop_0_i : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of gen_cc_flop_0_i : label is "FDR"; attribute SOFT_HLUTNM of s_axi_tx_tready_INST_0 : label is "soft_lutpair102"; begin do_cc_r <= \^do_cc_r\; gen_cc_i <= \^gen_cc_i\; \TX_DATA[53]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^gen_cc_i\, I1 => gen_ch_bond_i, O => gen_cc_flop_0_i_0 ); TX_PE_DATA_V_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => s_axi_tx_tvalid, I1 => tx_dst_rdy_n_i, O => s_axi_tx_tvalid_0 ); do_cc_r_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => do_cc_r_reg0, Q => \^do_cc_r\, R => '0' ); extend_cc_r_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => extend_cc_r_reg_0, Q => extend_cc_r, R => '0' ); gen_cc_flop_0_i: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => \^do_cc_r\, Q => \^gen_cc_i\, R => R0 ); s_axi_tx_tready_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => tx_dst_rdy_n_i, O => s_axi_tx_tready ); tx_dst_rdy_n_r_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => tx_dst_rdy_n_r_reg_0, Q => tx_dst_rdy_n_i, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_TX_STREAM_DATAPATH is port ( tx_pe_data_v_i : out STD_LOGIC; wait_for_lane_up_r_reg : out STD_LOGIC_VECTOR ( 1 downto 0 ); Q : out STD_LOGIC_VECTOR ( 61 downto 0 ); TX_PE_DATA_V_reg_0 : in STD_LOGIC; \out\ : in STD_LOGIC; gen_na_idles_i : in STD_LOGIC; \TX_DATA_reg[53]\ : in STD_LOGIC; rst_pma_init_usrclk : in STD_LOGIC; channel_up_tx_if : in STD_LOGIC; s_axi_tx_tdata : in STD_LOGIC_VECTOR ( 0 to 63 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_TX_STREAM_DATAPATH; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_TX_STREAM_DATAPATH is signal TX_PE_DATA : STD_LOGIC_VECTOR ( 50 to 51 ); signal \^tx_pe_data_v_i\ : STD_LOGIC; begin tx_pe_data_v_i <= \^tx_pe_data_v_i\; \TX_DATA[52]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"000F000D000D000D" ) port map ( I0 => \^tx_pe_data_v_i\, I1 => gen_na_idles_i, I2 => \TX_DATA_reg[53]\, I3 => rst_pma_init_usrclk, I4 => channel_up_tx_if, I5 => TX_PE_DATA(51), O => wait_for_lane_up_r_reg(0) ); \TX_DATA[53]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000322200002222" ) port map ( I0 => gen_na_idles_i, I1 => \TX_DATA_reg[53]\, I2 => \^tx_pe_data_v_i\, I3 => TX_PE_DATA(50), I4 => rst_pma_init_usrclk, I5 => channel_up_tx_if, O => wait_for_lane_up_r_reg(1) ); TX_PE_DATA_V_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => TX_PE_DATA_V_reg_0, Q => \^tx_pe_data_v_i\, R => '0' ); \TX_PE_DATA_reg[0]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(0), Q => Q(61), R => '0' ); \TX_PE_DATA_reg[10]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(10), Q => Q(51), R => '0' ); \TX_PE_DATA_reg[11]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(11), Q => Q(50), R => '0' ); \TX_PE_DATA_reg[12]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(12), Q => Q(49), R => '0' ); \TX_PE_DATA_reg[13]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(13), Q => Q(48), R => '0' ); \TX_PE_DATA_reg[14]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(14), Q => Q(47), R => '0' ); \TX_PE_DATA_reg[15]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(15), Q => Q(46), R => '0' ); \TX_PE_DATA_reg[16]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(16), Q => Q(45), R => '0' ); \TX_PE_DATA_reg[17]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(17), Q => Q(44), R => '0' ); \TX_PE_DATA_reg[18]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(18), Q => Q(43), R => '0' ); \TX_PE_DATA_reg[19]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(19), Q => Q(42), R => '0' ); \TX_PE_DATA_reg[1]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(1), Q => Q(60), R => '0' ); \TX_PE_DATA_reg[20]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(20), Q => Q(41), R => '0' ); \TX_PE_DATA_reg[21]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(21), Q => Q(40), R => '0' ); \TX_PE_DATA_reg[22]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(22), Q => Q(39), R => '0' ); \TX_PE_DATA_reg[23]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(23), Q => Q(38), R => '0' ); \TX_PE_DATA_reg[24]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(24), Q => Q(37), R => '0' ); \TX_PE_DATA_reg[25]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(25), Q => Q(36), R => '0' ); \TX_PE_DATA_reg[26]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(26), Q => Q(35), R => '0' ); \TX_PE_DATA_reg[27]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(27), Q => Q(34), R => '0' ); \TX_PE_DATA_reg[28]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(28), Q => Q(33), R => '0' ); \TX_PE_DATA_reg[29]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(29), Q => Q(32), R => '0' ); \TX_PE_DATA_reg[2]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(2), Q => Q(59), R => '0' ); \TX_PE_DATA_reg[30]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(30), Q => Q(31), R => '0' ); \TX_PE_DATA_reg[31]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(31), Q => Q(30), R => '0' ); \TX_PE_DATA_reg[32]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(32), Q => Q(29), R => '0' ); \TX_PE_DATA_reg[33]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(33), Q => Q(28), R => '0' ); \TX_PE_DATA_reg[34]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(34), Q => Q(27), R => '0' ); \TX_PE_DATA_reg[35]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(35), Q => Q(26), R => '0' ); \TX_PE_DATA_reg[36]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(36), Q => Q(25), R => '0' ); \TX_PE_DATA_reg[37]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(37), Q => Q(24), R => '0' ); \TX_PE_DATA_reg[38]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(38), Q => Q(23), R => '0' ); \TX_PE_DATA_reg[39]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(39), Q => Q(22), R => '0' ); \TX_PE_DATA_reg[3]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(3), Q => Q(58), R => '0' ); \TX_PE_DATA_reg[40]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(40), Q => Q(21), R => '0' ); \TX_PE_DATA_reg[41]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(41), Q => Q(20), R => '0' ); \TX_PE_DATA_reg[42]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(42), Q => Q(19), R => '0' ); \TX_PE_DATA_reg[43]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(43), Q => Q(18), R => '0' ); \TX_PE_DATA_reg[44]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(44), Q => Q(17), R => '0' ); \TX_PE_DATA_reg[45]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(45), Q => Q(16), R => '0' ); \TX_PE_DATA_reg[46]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(46), Q => Q(15), R => '0' ); \TX_PE_DATA_reg[47]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(47), Q => Q(14), R => '0' ); \TX_PE_DATA_reg[48]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(48), Q => Q(13), R => '0' ); \TX_PE_DATA_reg[49]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(49), Q => Q(12), R => '0' ); \TX_PE_DATA_reg[4]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(4), Q => Q(57), R => '0' ); \TX_PE_DATA_reg[50]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(50), Q => TX_PE_DATA(50), R => '0' ); \TX_PE_DATA_reg[51]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(51), Q => TX_PE_DATA(51), R => '0' ); \TX_PE_DATA_reg[52]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(52), Q => Q(11), R => '0' ); \TX_PE_DATA_reg[53]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(53), Q => Q(10), R => '0' ); \TX_PE_DATA_reg[54]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(54), Q => Q(9), R => '0' ); \TX_PE_DATA_reg[55]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(55), Q => Q(8), R => '0' ); \TX_PE_DATA_reg[56]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(56), Q => Q(7), R => '0' ); \TX_PE_DATA_reg[57]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(57), Q => Q(6), R => '0' ); \TX_PE_DATA_reg[58]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(58), Q => Q(5), R => '0' ); \TX_PE_DATA_reg[59]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(59), Q => Q(4), R => '0' ); \TX_PE_DATA_reg[5]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(5), Q => Q(56), R => '0' ); \TX_PE_DATA_reg[60]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(60), Q => Q(3), R => '0' ); \TX_PE_DATA_reg[61]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(61), Q => Q(2), R => '0' ); \TX_PE_DATA_reg[62]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(62), Q => Q(1), R => '0' ); \TX_PE_DATA_reg[63]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(63), Q => Q(0), R => '0' ); \TX_PE_DATA_reg[6]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(6), Q => Q(55), R => '0' ); \TX_PE_DATA_reg[7]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(7), Q => Q(54), R => '0' ); \TX_PE_DATA_reg[8]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(8), Q => Q(53), R => '0' ); \TX_PE_DATA_reg[9]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_axi_tx_tdata(9), Q => Q(52), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync is port ( next_ready_c : out STD_LOGIC; next_begin_c : out STD_LOGIC; SYSTEM_RESET_reg : out STD_LOGIC; s_level_out_d1_aurora_64b66b_0_cdc_to_reg_0 : in STD_LOGIC; \out\ : in STD_LOGIC; ready_r_reg : in STD_LOGIC; rx_lossofsync_i : in STD_LOGIC; ready_r : in STD_LOGIC; align_r : in STD_LOGIC; polarity_r : in STD_LOGIC; rx_polarity_dlyd_i : in STD_LOGIC; reset_lanes_i : in STD_LOGIC; begin_r_reg : in STD_LOGIC; SR : in STD_LOGIC_VECTOR ( 0 to 0 ); rx_polarity_r_reg : in STD_LOGIC; prev_rx_polarity_r : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync is signal begin_r_i_2_n_0 : STD_LOGIC; signal p_level_in_int : STD_LOGIC; signal ready_r_i_3_n_0 : STD_LOGIC; signal s_level_out_bus_d1_aurora_64b66b_0_cdc_to : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg : string; attribute async_reg of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_bus_d2 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d2 : signal is "true"; attribute shift_extract of s_level_out_bus_d2 : signal is "{no}"; signal s_level_out_bus_d3 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d3 : signal is "true"; attribute shift_extract of s_level_out_bus_d3 : signal is "{no}"; signal s_level_out_bus_d4 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d4 : signal is "true"; attribute shift_extract of s_level_out_bus_d4 : signal is "{no}"; signal s_level_out_bus_d5 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d5 : signal is "true"; attribute shift_extract of s_level_out_bus_d5 : signal is "{no}"; signal s_level_out_bus_d6 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d6 : signal is "true"; attribute shift_extract of s_level_out_bus_d6 : signal is "{no}"; signal s_level_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_d2 : STD_LOGIC; attribute async_reg of s_level_out_d2 : signal is "true"; attribute shift_extract of s_level_out_d2 : signal is "{no}"; signal s_level_out_d3 : STD_LOGIC; attribute async_reg of s_level_out_d3 : signal is "true"; attribute shift_extract of s_level_out_d3 : signal is "{no}"; signal s_level_out_d4 : STD_LOGIC; attribute async_reg of s_level_out_d4 : signal is "true"; attribute shift_extract of s_level_out_d4 : signal is "{no}"; signal s_level_out_d5 : STD_LOGIC; attribute async_reg of s_level_out_d5 : signal is "true"; attribute shift_extract of s_level_out_d5 : signal is "{no}"; signal s_level_out_d6 : STD_LOGIC; attribute async_reg of s_level_out_d6 : signal is "true"; attribute shift_extract of s_level_out_d6 : signal is "{no}"; signal s_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_out_d2 : STD_LOGIC; attribute async_reg of s_out_d2 : signal is "true"; attribute shift_extract of s_out_d2 : signal is "{no}"; signal s_out_d3 : STD_LOGIC; attribute async_reg of s_out_d3 : signal is "true"; attribute shift_extract of s_out_d3 : signal is "{no}"; signal s_out_d4 : STD_LOGIC; attribute async_reg of s_out_d4 : signal is "true"; attribute shift_extract of s_out_d4 : signal is "{no}"; signal s_out_d5 : STD_LOGIC; attribute async_reg of s_out_d5 : signal is "true"; attribute shift_extract of s_out_d5 : signal is "{no}"; signal s_out_d6 : STD_LOGIC; attribute async_reg of s_out_d6 : signal is "true"; attribute shift_extract of s_out_d6 : signal is "{no}"; signal s_out_d7 : STD_LOGIC; attribute async_reg of s_out_d7 : signal is "true"; attribute shift_extract of s_out_d7 : signal is "{no}"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d2_reg : label is std.standard.true; attribute KEEP of s_level_out_d2_reg : label is "yes"; attribute shift_extract of s_level_out_d2_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d3_reg : label is std.standard.true; attribute KEEP of s_level_out_d3_reg : label is "yes"; attribute shift_extract of s_level_out_d3_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d4_reg : label is std.standard.true; attribute KEEP of s_level_out_d4_reg : label is "yes"; attribute shift_extract of s_level_out_d4_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d5_reg : label is std.standard.true; attribute KEEP of s_level_out_d5_reg : label is "yes"; attribute shift_extract of s_level_out_d5_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d6_reg : label is std.standard.true; attribute KEEP of s_level_out_d6_reg : label is "yes"; attribute shift_extract of s_level_out_d6_reg : label is "{no}"; begin p_level_in_int <= s_level_out_d1_aurora_64b66b_0_cdc_to_reg_0; begin_r_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFCA0A0" ) port map ( I0 => rx_lossofsync_i, I1 => polarity_r, I2 => ready_r, I3 => align_r, I4 => reset_lanes_i, I5 => begin_r_i_2_n_0, O => next_begin_c ); begin_r_i_2: unisim.vcomponents.LUT4 generic map( INIT => X"80FF" ) port map ( I0 => s_level_out_d2, I1 => rx_polarity_dlyd_i, I2 => polarity_r, I3 => begin_r_reg, O => begin_r_i_2_n_0 ); i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d1_aurora_64b66b_0_cdc_to ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d2 ); i_10: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(28) ); i_100: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(2) ); i_101: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(1) ); i_102: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(0) ); i_103: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(31) ); i_104: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(30) ); i_105: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(29) ); i_106: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(28) ); i_107: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(27) ); i_108: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(26) ); i_109: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(25) ); i_11: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(27) ); i_110: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(24) ); i_111: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(23) ); i_112: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(22) ); i_113: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(21) ); i_114: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(20) ); i_115: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(19) ); i_116: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(18) ); i_117: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(17) ); i_118: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(16) ); i_119: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(15) ); i_12: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(26) ); i_120: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(14) ); i_121: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(13) ); i_122: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(12) ); i_123: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(11) ); i_124: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(10) ); i_125: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(9) ); i_126: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(8) ); i_127: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(7) ); i_128: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(6) ); i_129: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(5) ); i_13: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(25) ); i_130: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(4) ); i_131: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(3) ); i_132: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(2) ); i_133: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(1) ); i_134: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(0) ); i_135: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(31) ); i_136: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(30) ); i_137: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(29) ); i_138: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(28) ); i_139: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(27) ); i_14: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(24) ); i_140: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(26) ); i_141: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(25) ); i_142: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(24) ); i_143: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(23) ); i_144: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(22) ); i_145: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(21) ); i_146: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(20) ); i_147: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(19) ); i_148: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(18) ); i_149: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(17) ); i_15: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(23) ); i_150: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(16) ); i_151: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(15) ); i_152: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(14) ); i_153: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(13) ); i_154: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(12) ); i_155: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(11) ); i_156: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(10) ); i_157: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(9) ); i_158: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(8) ); i_159: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(7) ); i_16: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(22) ); i_160: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(6) ); i_161: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(5) ); i_162: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(4) ); i_163: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(3) ); i_164: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(2) ); i_165: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(1) ); i_166: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(0) ); i_167: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(31) ); i_168: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(30) ); i_169: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(29) ); i_17: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(21) ); i_170: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(28) ); i_171: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(27) ); i_172: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(26) ); i_173: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(25) ); i_174: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(24) ); i_175: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(23) ); i_176: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(22) ); i_177: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(21) ); i_178: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(20) ); i_179: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(19) ); i_18: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(20) ); i_180: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(18) ); i_181: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(17) ); i_182: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(16) ); i_183: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(15) ); i_184: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(14) ); i_185: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(13) ); i_186: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(12) ); i_187: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(11) ); i_188: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(10) ); i_189: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(9) ); i_19: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(19) ); i_190: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(8) ); i_191: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(7) ); i_192: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(6) ); i_193: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(5) ); i_194: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(4) ); i_195: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(3) ); i_196: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(2) ); i_197: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(1) ); i_198: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(0) ); i_2: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d3 ); i_20: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(18) ); i_21: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(17) ); i_22: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(16) ); i_23: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(15) ); i_24: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(14) ); i_25: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(13) ); i_26: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(12) ); i_27: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(11) ); i_28: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(10) ); i_29: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(9) ); i_3: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d4 ); i_30: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(8) ); i_31: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(7) ); i_32: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(6) ); i_33: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(5) ); i_34: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(4) ); i_35: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(3) ); i_36: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(2) ); i_37: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(1) ); i_38: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(0) ); i_39: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(31) ); i_4: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d5 ); i_40: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(30) ); i_41: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(29) ); i_42: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(28) ); i_43: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(27) ); i_44: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(26) ); i_45: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(25) ); i_46: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(24) ); i_47: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(23) ); i_48: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(22) ); i_49: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(21) ); i_5: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d6 ); i_50: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(20) ); i_51: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(19) ); i_52: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(18) ); i_53: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(17) ); i_54: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(16) ); i_55: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(15) ); i_56: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(14) ); i_57: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(13) ); i_58: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(12) ); i_59: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(11) ); i_6: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d7 ); i_60: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(10) ); i_61: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(9) ); i_62: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(8) ); i_63: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(7) ); i_64: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(6) ); i_65: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(5) ); i_66: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(4) ); i_67: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(3) ); i_68: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(2) ); i_69: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(1) ); i_7: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(31) ); i_70: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(0) ); i_71: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(31) ); i_72: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(30) ); i_73: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(29) ); i_74: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(28) ); i_75: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(27) ); i_76: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(26) ); i_77: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(25) ); i_78: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(24) ); i_79: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(23) ); i_8: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(30) ); i_80: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(22) ); i_81: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(21) ); i_82: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(20) ); i_83: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(19) ); i_84: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(18) ); i_85: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(17) ); i_86: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(16) ); i_87: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(15) ); i_88: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(14) ); i_89: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(13) ); i_9: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(29) ); i_90: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(12) ); i_91: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(11) ); i_92: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(10) ); i_93: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(9) ); i_94: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(8) ); i_95: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(7) ); i_96: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(6) ); i_97: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(5) ); i_98: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(4) ); i_99: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(3) ); ready_r_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"8888888888888C88" ) port map ( I0 => ready_r_i_3_n_0, I1 => ready_r_reg, I2 => rx_lossofsync_i, I3 => ready_r, I4 => align_r, I5 => polarity_r, O => next_ready_c ); ready_r_i_3: unisim.vcomponents.LUT5 generic map( INIT => X"00000040" ) port map ( I0 => s_level_out_d2, I1 => rx_polarity_dlyd_i, I2 => polarity_r, I3 => align_r, I4 => ready_r, O => ready_r_i_3_n_0 ); rx_polarity_r_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"0454" ) port map ( I0 => SR(0), I1 => rx_polarity_r_reg, I2 => s_level_out_d2, I3 => prev_rx_polarity_r, O => SYSTEM_RESET_reg ); s_level_out_d1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => p_level_in_int, Q => s_level_out_d1_aurora_64b66b_0_cdc_to, R => '0' ); s_level_out_d2_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_level_out_d1_aurora_64b66b_0_cdc_to, Q => s_level_out_d2, R => '0' ); s_level_out_d3_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); s_level_out_d4_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_level_out_d3, Q => s_level_out_d4, R => '0' ); s_level_out_d5_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_level_out_d4, Q => s_level_out_d5, R => '0' ); s_level_out_d6_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_level_out_d5, Q => s_level_out_d6, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync_6 is port ( rxheadervalid_i_reg : out STD_LOGIC; s_level_out_d1_aurora_64b66b_0_cdc_to_reg_0 : in STD_LOGIC; \out\ : in STD_LOGIC; rxheadervalid_i : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); RX_NEG_OUT_reg : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync_6 : entity is "aurora_64b66b_0_cdc_sync"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync_6; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync_6 is signal p_level_in_int : STD_LOGIC; signal s_level_out_bus_d1_aurora_64b66b_0_cdc_to : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg : string; attribute async_reg of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_bus_d2 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d2 : signal is "true"; attribute shift_extract of s_level_out_bus_d2 : signal is "{no}"; signal s_level_out_bus_d3 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d3 : signal is "true"; attribute shift_extract of s_level_out_bus_d3 : signal is "{no}"; signal s_level_out_bus_d4 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d4 : signal is "true"; attribute shift_extract of s_level_out_bus_d4 : signal is "{no}"; signal s_level_out_bus_d5 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d5 : signal is "true"; attribute shift_extract of s_level_out_bus_d5 : signal is "{no}"; signal s_level_out_bus_d6 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d6 : signal is "true"; attribute shift_extract of s_level_out_bus_d6 : signal is "{no}"; signal s_level_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_d2 : STD_LOGIC; attribute async_reg of s_level_out_d2 : signal is "true"; attribute shift_extract of s_level_out_d2 : signal is "{no}"; signal s_level_out_d3 : STD_LOGIC; attribute async_reg of s_level_out_d3 : signal is "true"; attribute shift_extract of s_level_out_d3 : signal is "{no}"; signal s_level_out_d4 : STD_LOGIC; attribute async_reg of s_level_out_d4 : signal is "true"; attribute shift_extract of s_level_out_d4 : signal is "{no}"; signal s_level_out_d5 : STD_LOGIC; attribute async_reg of s_level_out_d5 : signal is "true"; attribute shift_extract of s_level_out_d5 : signal is "{no}"; signal s_level_out_d6 : STD_LOGIC; attribute async_reg of s_level_out_d6 : signal is "true"; attribute shift_extract of s_level_out_d6 : signal is "{no}"; signal s_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_out_d2 : STD_LOGIC; attribute async_reg of s_out_d2 : signal is "true"; attribute shift_extract of s_out_d2 : signal is "{no}"; signal s_out_d3 : STD_LOGIC; attribute async_reg of s_out_d3 : signal is "true"; attribute shift_extract of s_out_d3 : signal is "{no}"; signal s_out_d4 : STD_LOGIC; attribute async_reg of s_out_d4 : signal is "true"; attribute shift_extract of s_out_d4 : signal is "{no}"; signal s_out_d5 : STD_LOGIC; attribute async_reg of s_out_d5 : signal is "true"; attribute shift_extract of s_out_d5 : signal is "{no}"; signal s_out_d6 : STD_LOGIC; attribute async_reg of s_out_d6 : signal is "true"; attribute shift_extract of s_out_d6 : signal is "{no}"; signal s_out_d7 : STD_LOGIC; attribute async_reg of s_out_d7 : signal is "true"; attribute shift_extract of s_out_d7 : signal is "{no}"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d2_reg : label is std.standard.true; attribute KEEP of s_level_out_d2_reg : label is "yes"; attribute shift_extract of s_level_out_d2_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d3_reg : label is std.standard.true; attribute KEEP of s_level_out_d3_reg : label is "yes"; attribute shift_extract of s_level_out_d3_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d4_reg : label is std.standard.true; attribute KEEP of s_level_out_d4_reg : label is "yes"; attribute shift_extract of s_level_out_d4_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d5_reg : label is std.standard.true; attribute KEEP of s_level_out_d5_reg : label is "yes"; attribute shift_extract of s_level_out_d5_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d6_reg : label is std.standard.true; attribute KEEP of s_level_out_d6_reg : label is "yes"; attribute shift_extract of s_level_out_d6_reg : label is "{no}"; begin p_level_in_int <= s_level_out_d1_aurora_64b66b_0_cdc_to_reg_0; RX_NEG_OUT_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"FF200000" ) port map ( I0 => rxheadervalid_i, I1 => Q(1), I2 => Q(0), I3 => RX_NEG_OUT_reg, I4 => s_level_out_d2, O => rxheadervalid_i_reg ); i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d1_aurora_64b66b_0_cdc_to ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d2 ); i_10: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(28) ); i_100: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(2) ); i_101: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(1) ); i_102: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(0) ); i_103: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(31) ); i_104: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(30) ); i_105: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(29) ); i_106: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(28) ); i_107: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(27) ); i_108: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(26) ); i_109: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(25) ); i_11: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(27) ); i_110: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(24) ); i_111: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(23) ); i_112: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(22) ); i_113: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(21) ); i_114: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(20) ); i_115: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(19) ); i_116: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(18) ); i_117: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(17) ); i_118: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(16) ); i_119: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(15) ); i_12: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(26) ); i_120: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(14) ); i_121: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(13) ); i_122: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(12) ); i_123: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(11) ); i_124: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(10) ); i_125: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(9) ); i_126: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(8) ); i_127: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(7) ); i_128: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(6) ); i_129: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(5) ); i_13: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(25) ); i_130: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(4) ); i_131: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(3) ); i_132: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(2) ); i_133: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(1) ); i_134: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(0) ); i_135: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(31) ); i_136: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(30) ); i_137: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(29) ); i_138: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(28) ); i_139: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(27) ); i_14: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(24) ); i_140: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(26) ); i_141: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(25) ); i_142: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(24) ); i_143: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(23) ); i_144: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(22) ); i_145: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(21) ); i_146: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(20) ); i_147: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(19) ); i_148: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(18) ); i_149: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(17) ); i_15: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(23) ); i_150: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(16) ); i_151: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(15) ); i_152: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(14) ); i_153: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(13) ); i_154: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(12) ); i_155: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(11) ); i_156: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(10) ); i_157: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(9) ); i_158: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(8) ); i_159: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(7) ); i_16: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(22) ); i_160: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(6) ); i_161: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(5) ); i_162: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(4) ); i_163: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(3) ); i_164: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(2) ); i_165: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(1) ); i_166: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(0) ); i_167: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(31) ); i_168: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(30) ); i_169: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(29) ); i_17: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(21) ); i_170: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(28) ); i_171: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(27) ); i_172: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(26) ); i_173: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(25) ); i_174: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(24) ); i_175: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(23) ); i_176: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(22) ); i_177: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(21) ); i_178: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(20) ); i_179: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(19) ); i_18: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(20) ); i_180: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(18) ); i_181: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(17) ); i_182: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(16) ); i_183: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(15) ); i_184: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(14) ); i_185: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(13) ); i_186: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(12) ); i_187: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(11) ); i_188: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(10) ); i_189: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(9) ); i_19: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(19) ); i_190: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(8) ); i_191: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(7) ); i_192: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(6) ); i_193: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(5) ); i_194: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(4) ); i_195: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(3) ); i_196: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(2) ); i_197: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(1) ); i_198: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(0) ); i_2: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d3 ); i_20: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(18) ); i_21: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(17) ); i_22: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(16) ); i_23: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(15) ); i_24: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(14) ); i_25: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(13) ); i_26: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(12) ); i_27: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(11) ); i_28: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(10) ); i_29: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(9) ); i_3: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d4 ); i_30: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(8) ); i_31: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(7) ); i_32: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(6) ); i_33: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(5) ); i_34: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(4) ); i_35: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(3) ); i_36: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(2) ); i_37: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(1) ); i_38: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(0) ); i_39: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(31) ); i_4: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d5 ); i_40: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(30) ); i_41: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(29) ); i_42: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(28) ); i_43: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(27) ); i_44: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(26) ); i_45: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(25) ); i_46: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(24) ); i_47: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(23) ); i_48: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(22) ); i_49: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(21) ); i_5: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d6 ); i_50: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(20) ); i_51: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(19) ); i_52: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(18) ); i_53: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(17) ); i_54: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(16) ); i_55: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(15) ); i_56: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(14) ); i_57: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(13) ); i_58: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(12) ); i_59: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(11) ); i_6: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d7 ); i_60: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(10) ); i_61: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(9) ); i_62: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(8) ); i_63: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(7) ); i_64: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(6) ); i_65: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(5) ); i_66: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(4) ); i_67: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(3) ); i_68: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(2) ); i_69: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(1) ); i_7: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(31) ); i_70: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(0) ); i_71: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(31) ); i_72: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(30) ); i_73: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(29) ); i_74: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(28) ); i_75: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(27) ); i_76: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(26) ); i_77: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(25) ); i_78: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(24) ); i_79: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(23) ); i_8: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(30) ); i_80: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(22) ); i_81: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(21) ); i_82: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(20) ); i_83: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(19) ); i_84: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(18) ); i_85: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(17) ); i_86: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(16) ); i_87: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(15) ); i_88: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(14) ); i_89: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(13) ); i_9: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(29) ); i_90: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(12) ); i_91: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(11) ); i_92: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(10) ); i_93: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(9) ); i_94: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(8) ); i_95: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(7) ); i_96: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(6) ); i_97: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(5) ); i_98: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(4) ); i_99: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(3) ); s_level_out_d1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => p_level_in_int, Q => s_level_out_d1_aurora_64b66b_0_cdc_to, R => '0' ); s_level_out_d2_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_level_out_d1_aurora_64b66b_0_cdc_to, Q => s_level_out_d2, R => '0' ); s_level_out_d3_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); s_level_out_d4_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_level_out_d3, Q => s_level_out_d4, R => '0' ); s_level_out_d5_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_level_out_d4, Q => s_level_out_d5, R => '0' ); s_level_out_d6_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => s_level_out_d5, Q => s_level_out_d6, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized0\ is port ( \out\ : out STD_LOGIC; RXBUFSTATUS : in STD_LOGIC_VECTOR ( 0 to 0 ); p_level_in_d1_cdc_from_reg_0 : in STD_LOGIC; s_level_out_d6_reg_0 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized0\ : entity is "aurora_64b66b_0_cdc_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized0\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized0\ is signal p_level_in_int : STD_LOGIC; signal s_level_out_bus_d1_aurora_64b66b_0_cdc_to : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg : string; attribute async_reg of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_bus_d2 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d2 : signal is "true"; attribute shift_extract of s_level_out_bus_d2 : signal is "{no}"; signal s_level_out_bus_d3 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d3 : signal is "true"; attribute shift_extract of s_level_out_bus_d3 : signal is "{no}"; signal s_level_out_bus_d4 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d4 : signal is "true"; attribute shift_extract of s_level_out_bus_d4 : signal is "{no}"; signal s_level_out_bus_d5 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d5 : signal is "true"; attribute shift_extract of s_level_out_bus_d5 : signal is "{no}"; signal s_level_out_bus_d6 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d6 : signal is "true"; attribute shift_extract of s_level_out_bus_d6 : signal is "{no}"; signal s_level_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_d2 : STD_LOGIC; attribute async_reg of s_level_out_d2 : signal is "true"; attribute shift_extract of s_level_out_d2 : signal is "{no}"; signal s_level_out_d3 : STD_LOGIC; attribute async_reg of s_level_out_d3 : signal is "true"; attribute shift_extract of s_level_out_d3 : signal is "{no}"; signal s_level_out_d4 : STD_LOGIC; attribute async_reg of s_level_out_d4 : signal is "true"; attribute shift_extract of s_level_out_d4 : signal is "{no}"; signal s_level_out_d5 : STD_LOGIC; attribute async_reg of s_level_out_d5 : signal is "true"; attribute shift_extract of s_level_out_d5 : signal is "{no}"; signal s_level_out_d6 : STD_LOGIC; attribute async_reg of s_level_out_d6 : signal is "true"; attribute shift_extract of s_level_out_d6 : signal is "{no}"; signal s_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_out_d2 : STD_LOGIC; attribute async_reg of s_out_d2 : signal is "true"; attribute shift_extract of s_out_d2 : signal is "{no}"; signal s_out_d3 : STD_LOGIC; attribute async_reg of s_out_d3 : signal is "true"; attribute shift_extract of s_out_d3 : signal is "{no}"; signal s_out_d4 : STD_LOGIC; attribute async_reg of s_out_d4 : signal is "true"; attribute shift_extract of s_out_d4 : signal is "{no}"; signal s_out_d5 : STD_LOGIC; attribute async_reg of s_out_d5 : signal is "true"; attribute shift_extract of s_out_d5 : signal is "{no}"; signal s_out_d6 : STD_LOGIC; attribute async_reg of s_out_d6 : signal is "true"; attribute shift_extract of s_out_d6 : signal is "{no}"; signal s_out_d7 : STD_LOGIC; attribute async_reg of s_out_d7 : signal is "true"; attribute shift_extract of s_out_d7 : signal is "{no}"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d2_reg : label is std.standard.true; attribute KEEP of s_level_out_d2_reg : label is "yes"; attribute shift_extract of s_level_out_d2_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d3_reg : label is std.standard.true; attribute KEEP of s_level_out_d3_reg : label is "yes"; attribute shift_extract of s_level_out_d3_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d4_reg : label is std.standard.true; attribute KEEP of s_level_out_d4_reg : label is "yes"; attribute shift_extract of s_level_out_d4_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d5_reg : label is std.standard.true; attribute KEEP of s_level_out_d5_reg : label is "yes"; attribute shift_extract of s_level_out_d5_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d6_reg : label is std.standard.true; attribute KEEP of s_level_out_d6_reg : label is "yes"; attribute shift_extract of s_level_out_d6_reg : label is "{no}"; begin \out\ <= s_level_out_d5; i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d1_aurora_64b66b_0_cdc_to ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d2 ); i_10: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(28) ); i_100: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(2) ); i_101: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(1) ); i_102: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(0) ); i_103: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(31) ); i_104: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(30) ); i_105: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(29) ); i_106: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(28) ); i_107: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(27) ); i_108: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(26) ); i_109: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(25) ); i_11: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(27) ); i_110: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(24) ); i_111: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(23) ); i_112: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(22) ); i_113: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(21) ); i_114: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(20) ); i_115: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(19) ); i_116: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(18) ); i_117: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(17) ); i_118: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(16) ); i_119: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(15) ); i_12: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(26) ); i_120: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(14) ); i_121: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(13) ); i_122: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(12) ); i_123: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(11) ); i_124: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(10) ); i_125: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(9) ); i_126: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(8) ); i_127: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(7) ); i_128: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(6) ); i_129: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(5) ); i_13: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(25) ); i_130: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(4) ); i_131: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(3) ); i_132: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(2) ); i_133: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(1) ); i_134: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(0) ); i_135: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(31) ); i_136: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(30) ); i_137: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(29) ); i_138: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(28) ); i_139: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(27) ); i_14: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(24) ); i_140: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(26) ); i_141: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(25) ); i_142: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(24) ); i_143: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(23) ); i_144: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(22) ); i_145: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(21) ); i_146: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(20) ); i_147: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(19) ); i_148: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(18) ); i_149: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(17) ); i_15: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(23) ); i_150: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(16) ); i_151: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(15) ); i_152: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(14) ); i_153: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(13) ); i_154: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(12) ); i_155: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(11) ); i_156: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(10) ); i_157: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(9) ); i_158: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(8) ); i_159: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(7) ); i_16: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(22) ); i_160: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(6) ); i_161: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(5) ); i_162: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(4) ); i_163: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(3) ); i_164: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(2) ); i_165: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(1) ); i_166: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(0) ); i_167: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(31) ); i_168: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(30) ); i_169: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(29) ); i_17: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(21) ); i_170: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(28) ); i_171: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(27) ); i_172: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(26) ); i_173: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(25) ); i_174: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(24) ); i_175: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(23) ); i_176: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(22) ); i_177: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(21) ); i_178: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(20) ); i_179: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(19) ); i_18: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(20) ); i_180: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(18) ); i_181: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(17) ); i_182: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(16) ); i_183: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(15) ); i_184: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(14) ); i_185: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(13) ); i_186: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(12) ); i_187: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(11) ); i_188: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(10) ); i_189: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(9) ); i_19: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(19) ); i_190: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(8) ); i_191: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(7) ); i_192: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(6) ); i_193: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(5) ); i_194: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(4) ); i_195: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(3) ); i_196: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(2) ); i_197: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(1) ); i_198: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(0) ); i_2: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d3 ); i_20: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(18) ); i_21: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(17) ); i_22: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(16) ); i_23: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(15) ); i_24: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(14) ); i_25: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(13) ); i_26: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(12) ); i_27: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(11) ); i_28: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(10) ); i_29: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(9) ); i_3: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d4 ); i_30: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(8) ); i_31: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(7) ); i_32: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(6) ); i_33: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(5) ); i_34: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(4) ); i_35: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(3) ); i_36: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(2) ); i_37: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(1) ); i_38: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(0) ); i_39: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(31) ); i_4: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d5 ); i_40: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(30) ); i_41: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(29) ); i_42: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(28) ); i_43: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(27) ); i_44: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(26) ); i_45: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(25) ); i_46: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(24) ); i_47: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(23) ); i_48: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(22) ); i_49: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(21) ); i_5: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d6 ); i_50: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(20) ); i_51: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(19) ); i_52: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(18) ); i_53: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(17) ); i_54: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(16) ); i_55: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(15) ); i_56: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(14) ); i_57: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(13) ); i_58: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(12) ); i_59: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(11) ); i_6: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d7 ); i_60: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(10) ); i_61: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(9) ); i_62: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(8) ); i_63: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(7) ); i_64: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(6) ); i_65: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(5) ); i_66: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(4) ); i_67: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(3) ); i_68: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(2) ); i_69: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(1) ); i_7: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(31) ); i_70: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(0) ); i_71: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(31) ); i_72: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(30) ); i_73: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(29) ); i_74: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(28) ); i_75: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(27) ); i_76: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(26) ); i_77: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(25) ); i_78: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(24) ); i_79: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(23) ); i_8: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(30) ); i_80: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(22) ); i_81: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(21) ); i_82: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(20) ); i_83: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(19) ); i_84: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(18) ); i_85: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(17) ); i_86: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(16) ); i_87: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(15) ); i_88: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(14) ); i_89: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(13) ); i_9: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(29) ); i_90: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(12) ); i_91: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(11) ); i_92: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(10) ); i_93: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(9) ); i_94: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(8) ); i_95: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(7) ); i_96: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(6) ); i_97: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(5) ); i_98: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(4) ); i_99: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(3) ); p_level_in_d1_cdc_from_reg: unisim.vcomponents.FDRE port map ( C => p_level_in_d1_cdc_from_reg_0, CE => '1', D => RXBUFSTATUS(0), Q => p_level_in_int, R => '0' ); s_level_out_d1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg_0, CE => '1', D => p_level_in_int, Q => s_level_out_d1_aurora_64b66b_0_cdc_to, R => '0' ); s_level_out_d2_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg_0, CE => '1', D => s_level_out_d1_aurora_64b66b_0_cdc_to, Q => s_level_out_d2, R => '0' ); s_level_out_d3_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg_0, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); s_level_out_d4_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg_0, CE => '1', D => s_level_out_d3, Q => s_level_out_d4, R => '0' ); s_level_out_d5_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg_0, CE => '1', D => s_level_out_d4, Q => s_level_out_d5, R => '0' ); s_level_out_d6_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg_0, CE => '1', D => s_level_out_d5, Q => s_level_out_d6, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized1\ is port ( \out\ : out STD_LOGIC; gt_pll_lock : out STD_LOGIC; in0 : in STD_LOGIC; s_level_out_d5_reg_0 : in STD_LOGIC; mmcm_reset_i : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized1\ : entity is "aurora_64b66b_0_cdc_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized1\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized1\ is signal p_level_in_int : STD_LOGIC; signal s_level_out_bus_d1_aurora_64b66b_0_cdc_to : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg : string; attribute async_reg of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_bus_d2 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d2 : signal is "true"; attribute shift_extract of s_level_out_bus_d2 : signal is "{no}"; signal s_level_out_bus_d3 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d3 : signal is "true"; attribute shift_extract of s_level_out_bus_d3 : signal is "{no}"; signal s_level_out_bus_d4 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d4 : signal is "true"; attribute shift_extract of s_level_out_bus_d4 : signal is "{no}"; signal s_level_out_bus_d5 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d5 : signal is "true"; attribute shift_extract of s_level_out_bus_d5 : signal is "{no}"; signal s_level_out_bus_d6 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d6 : signal is "true"; attribute shift_extract of s_level_out_bus_d6 : signal is "{no}"; signal s_level_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_d2 : STD_LOGIC; attribute async_reg of s_level_out_d2 : signal is "true"; attribute shift_extract of s_level_out_d2 : signal is "{no}"; signal s_level_out_d3 : STD_LOGIC; attribute async_reg of s_level_out_d3 : signal is "true"; attribute shift_extract of s_level_out_d3 : signal is "{no}"; signal s_level_out_d4 : STD_LOGIC; attribute async_reg of s_level_out_d4 : signal is "true"; attribute shift_extract of s_level_out_d4 : signal is "{no}"; signal s_level_out_d5 : STD_LOGIC; attribute async_reg of s_level_out_d5 : signal is "true"; attribute shift_extract of s_level_out_d5 : signal is "{no}"; signal s_level_out_d6 : STD_LOGIC; attribute async_reg of s_level_out_d6 : signal is "true"; attribute shift_extract of s_level_out_d6 : signal is "{no}"; signal s_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_out_d2 : STD_LOGIC; attribute async_reg of s_out_d2 : signal is "true"; attribute shift_extract of s_out_d2 : signal is "{no}"; signal s_out_d3 : STD_LOGIC; attribute async_reg of s_out_d3 : signal is "true"; attribute shift_extract of s_out_d3 : signal is "{no}"; signal s_out_d4 : STD_LOGIC; attribute async_reg of s_out_d4 : signal is "true"; attribute shift_extract of s_out_d4 : signal is "{no}"; signal s_out_d5 : STD_LOGIC; attribute async_reg of s_out_d5 : signal is "true"; attribute shift_extract of s_out_d5 : signal is "{no}"; signal s_out_d6 : STD_LOGIC; attribute async_reg of s_out_d6 : signal is "true"; attribute shift_extract of s_out_d6 : signal is "{no}"; signal s_out_d7 : STD_LOGIC; attribute async_reg of s_out_d7 : signal is "true"; attribute shift_extract of s_out_d7 : signal is "{no}"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d2_reg : label is std.standard.true; attribute KEEP of s_level_out_d2_reg : label is "yes"; attribute shift_extract of s_level_out_d2_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d3_reg : label is std.standard.true; attribute KEEP of s_level_out_d3_reg : label is "yes"; attribute shift_extract of s_level_out_d3_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d4_reg : label is std.standard.true; attribute KEEP of s_level_out_d4_reg : label is "yes"; attribute shift_extract of s_level_out_d4_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d5_reg : label is std.standard.true; attribute KEEP of s_level_out_d5_reg : label is "yes"; attribute shift_extract of s_level_out_d5_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d6_reg : label is std.standard.true; attribute KEEP of s_level_out_d6_reg : label is "yes"; attribute shift_extract of s_level_out_d6_reg : label is "{no}"; begin \out\ <= s_level_out_d5; p_level_in_int <= in0; gt_pll_lock_INST_0: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => s_level_out_d5, I1 => mmcm_reset_i, O => gt_pll_lock ); i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d1_aurora_64b66b_0_cdc_to ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d2 ); i_10: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(28) ); i_100: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(2) ); i_101: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(1) ); i_102: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(0) ); i_103: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(31) ); i_104: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(30) ); i_105: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(29) ); i_106: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(28) ); i_107: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(27) ); i_108: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(26) ); i_109: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(25) ); i_11: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(27) ); i_110: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(24) ); i_111: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(23) ); i_112: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(22) ); i_113: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(21) ); i_114: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(20) ); i_115: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(19) ); i_116: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(18) ); i_117: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(17) ); i_118: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(16) ); i_119: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(15) ); i_12: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(26) ); i_120: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(14) ); i_121: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(13) ); i_122: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(12) ); i_123: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(11) ); i_124: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(10) ); i_125: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(9) ); i_126: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(8) ); i_127: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(7) ); i_128: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(6) ); i_129: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(5) ); i_13: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(25) ); i_130: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(4) ); i_131: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(3) ); i_132: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(2) ); i_133: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(1) ); i_134: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(0) ); i_135: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(31) ); i_136: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(30) ); i_137: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(29) ); i_138: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(28) ); i_139: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(27) ); i_14: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(24) ); i_140: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(26) ); i_141: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(25) ); i_142: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(24) ); i_143: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(23) ); i_144: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(22) ); i_145: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(21) ); i_146: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(20) ); i_147: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(19) ); i_148: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(18) ); i_149: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(17) ); i_15: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(23) ); i_150: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(16) ); i_151: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(15) ); i_152: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(14) ); i_153: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(13) ); i_154: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(12) ); i_155: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(11) ); i_156: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(10) ); i_157: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(9) ); i_158: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(8) ); i_159: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(7) ); i_16: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(22) ); i_160: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(6) ); i_161: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(5) ); i_162: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(4) ); i_163: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(3) ); i_164: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(2) ); i_165: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(1) ); i_166: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(0) ); i_167: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(31) ); i_168: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(30) ); i_169: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(29) ); i_17: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(21) ); i_170: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(28) ); i_171: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(27) ); i_172: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(26) ); i_173: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(25) ); i_174: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(24) ); i_175: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(23) ); i_176: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(22) ); i_177: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(21) ); i_178: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(20) ); i_179: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(19) ); i_18: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(20) ); i_180: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(18) ); i_181: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(17) ); i_182: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(16) ); i_183: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(15) ); i_184: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(14) ); i_185: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(13) ); i_186: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(12) ); i_187: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(11) ); i_188: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(10) ); i_189: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(9) ); i_19: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(19) ); i_190: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(8) ); i_191: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(7) ); i_192: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(6) ); i_193: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(5) ); i_194: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(4) ); i_195: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(3) ); i_196: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(2) ); i_197: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(1) ); i_198: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(0) ); i_2: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d3 ); i_20: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(18) ); i_21: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(17) ); i_22: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(16) ); i_23: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(15) ); i_24: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(14) ); i_25: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(13) ); i_26: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(12) ); i_27: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(11) ); i_28: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(10) ); i_29: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(9) ); i_3: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d4 ); i_30: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(8) ); i_31: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(7) ); i_32: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(6) ); i_33: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(5) ); i_34: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(4) ); i_35: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(3) ); i_36: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(2) ); i_37: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(1) ); i_38: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(0) ); i_39: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(31) ); i_4: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d5 ); i_40: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(30) ); i_41: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(29) ); i_42: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(28) ); i_43: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(27) ); i_44: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(26) ); i_45: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(25) ); i_46: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(24) ); i_47: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(23) ); i_48: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(22) ); i_49: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(21) ); i_5: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d6 ); i_50: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(20) ); i_51: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(19) ); i_52: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(18) ); i_53: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(17) ); i_54: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(16) ); i_55: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(15) ); i_56: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(14) ); i_57: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(13) ); i_58: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(12) ); i_59: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(11) ); i_6: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d7 ); i_60: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(10) ); i_61: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(9) ); i_62: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(8) ); i_63: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(7) ); i_64: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(6) ); i_65: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(5) ); i_66: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(4) ); i_67: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(3) ); i_68: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(2) ); i_69: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(1) ); i_7: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(31) ); i_70: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(0) ); i_71: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(31) ); i_72: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(30) ); i_73: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(29) ); i_74: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(28) ); i_75: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(27) ); i_76: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(26) ); i_77: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(25) ); i_78: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(24) ); i_79: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(23) ); i_8: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(30) ); i_80: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(22) ); i_81: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(21) ); i_82: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(20) ); i_83: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(19) ); i_84: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(18) ); i_85: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(17) ); i_86: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(16) ); i_87: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(15) ); i_88: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(14) ); i_89: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(13) ); i_9: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(29) ); i_90: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(12) ); i_91: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(11) ); i_92: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(10) ); i_93: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(9) ); i_94: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(8) ); i_95: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(7) ); i_96: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(6) ); i_97: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(5) ); i_98: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(4) ); i_99: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(3) ); s_level_out_d1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_0, CE => '1', D => p_level_in_int, Q => s_level_out_d1_aurora_64b66b_0_cdc_to, R => '0' ); s_level_out_d2_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_0, CE => '1', D => s_level_out_d1_aurora_64b66b_0_cdc_to, Q => s_level_out_d2, R => '0' ); s_level_out_d3_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_0, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); s_level_out_d4_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_0, CE => '1', D => s_level_out_d3, Q => s_level_out_d4, R => '0' ); s_level_out_d5_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_0, CE => '1', D => s_level_out_d4, Q => s_level_out_d5, R => '0' ); s_level_out_d6_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_0, CE => '1', D => s_level_out_d5, Q => s_level_out_d6, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized1_26\ is port ( \cb_bit_err_ext_cnt_reg[3]\ : out STD_LOGIC; s_level_out_d5_reg_0 : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 3 downto 0 ); reset_cbcc_comb_reg : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized1_26\ : entity is "aurora_64b66b_0_cdc_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized1_26\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized1_26\ is signal p_level_in_int : STD_LOGIC; signal s_level_out_bus_d1_aurora_64b66b_0_cdc_to : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg : string; attribute async_reg of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_bus_d2 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d2 : signal is "true"; attribute shift_extract of s_level_out_bus_d2 : signal is "{no}"; signal s_level_out_bus_d3 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d3 : signal is "true"; attribute shift_extract of s_level_out_bus_d3 : signal is "{no}"; signal s_level_out_bus_d4 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d4 : signal is "true"; attribute shift_extract of s_level_out_bus_d4 : signal is "{no}"; signal s_level_out_bus_d5 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d5 : signal is "true"; attribute shift_extract of s_level_out_bus_d5 : signal is "{no}"; signal s_level_out_bus_d6 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d6 : signal is "true"; attribute shift_extract of s_level_out_bus_d6 : signal is "{no}"; signal s_level_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_d2 : STD_LOGIC; attribute async_reg of s_level_out_d2 : signal is "true"; attribute shift_extract of s_level_out_d2 : signal is "{no}"; signal s_level_out_d3 : STD_LOGIC; attribute async_reg of s_level_out_d3 : signal is "true"; attribute shift_extract of s_level_out_d3 : signal is "{no}"; signal s_level_out_d4 : STD_LOGIC; attribute async_reg of s_level_out_d4 : signal is "true"; attribute shift_extract of s_level_out_d4 : signal is "{no}"; signal s_level_out_d5 : STD_LOGIC; attribute async_reg of s_level_out_d5 : signal is "true"; attribute shift_extract of s_level_out_d5 : signal is "{no}"; signal s_level_out_d6 : STD_LOGIC; attribute async_reg of s_level_out_d6 : signal is "true"; attribute shift_extract of s_level_out_d6 : signal is "{no}"; signal s_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_out_d2 : STD_LOGIC; attribute async_reg of s_out_d2 : signal is "true"; attribute shift_extract of s_out_d2 : signal is "{no}"; signal s_out_d3 : STD_LOGIC; attribute async_reg of s_out_d3 : signal is "true"; attribute shift_extract of s_out_d3 : signal is "{no}"; signal s_out_d4 : STD_LOGIC; attribute async_reg of s_out_d4 : signal is "true"; attribute shift_extract of s_out_d4 : signal is "{no}"; signal s_out_d5 : STD_LOGIC; attribute async_reg of s_out_d5 : signal is "true"; attribute shift_extract of s_out_d5 : signal is "{no}"; signal s_out_d6 : STD_LOGIC; attribute async_reg of s_out_d6 : signal is "true"; attribute shift_extract of s_out_d6 : signal is "{no}"; signal s_out_d7 : STD_LOGIC; attribute async_reg of s_out_d7 : signal is "true"; attribute shift_extract of s_out_d7 : signal is "{no}"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d2_reg : label is std.standard.true; attribute KEEP of s_level_out_d2_reg : label is "yes"; attribute shift_extract of s_level_out_d2_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d3_reg : label is std.standard.true; attribute KEEP of s_level_out_d3_reg : label is "yes"; attribute shift_extract of s_level_out_d3_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d4_reg : label is std.standard.true; attribute KEEP of s_level_out_d4_reg : label is "yes"; attribute shift_extract of s_level_out_d4_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d5_reg : label is std.standard.true; attribute KEEP of s_level_out_d5_reg : label is "yes"; attribute shift_extract of s_level_out_d5_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d6_reg : label is std.standard.true; attribute KEEP of s_level_out_d6_reg : label is "yes"; attribute shift_extract of s_level_out_d6_reg : label is "{no}"; begin i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => p_level_in_int ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d1_aurora_64b66b_0_cdc_to ); i_10: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(29) ); i_100: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(3) ); i_101: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(2) ); i_102: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(1) ); i_103: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(0) ); i_104: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(31) ); i_105: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(30) ); i_106: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(29) ); i_107: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(28) ); i_108: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(27) ); i_109: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(26) ); i_11: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(28) ); i_110: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(25) ); i_111: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(24) ); i_112: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(23) ); i_113: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(22) ); i_114: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(21) ); i_115: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(20) ); i_116: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(19) ); i_117: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(18) ); i_118: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(17) ); i_119: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(16) ); i_12: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(27) ); i_120: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(15) ); i_121: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(14) ); i_122: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(13) ); i_123: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(12) ); i_124: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(11) ); i_125: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(10) ); i_126: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(9) ); i_127: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(8) ); i_128: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(7) ); i_129: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(6) ); i_13: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(26) ); i_130: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(5) ); i_131: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(4) ); i_132: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(3) ); i_133: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(2) ); i_134: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(1) ); i_135: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(0) ); i_136: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(31) ); i_137: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(30) ); i_138: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(29) ); i_139: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(28) ); i_14: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(25) ); i_140: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(27) ); i_141: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(26) ); i_142: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(25) ); i_143: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(24) ); i_144: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(23) ); i_145: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(22) ); i_146: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(21) ); i_147: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(20) ); i_148: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(19) ); i_149: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(18) ); i_15: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(24) ); i_150: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(17) ); i_151: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(16) ); i_152: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(15) ); i_153: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(14) ); i_154: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(13) ); i_155: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(12) ); i_156: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(11) ); i_157: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(10) ); i_158: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(9) ); i_159: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(8) ); i_16: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(23) ); i_160: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(7) ); i_161: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(6) ); i_162: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(5) ); i_163: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(4) ); i_164: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(3) ); i_165: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(2) ); i_166: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(1) ); i_167: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(0) ); i_168: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(31) ); i_169: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(30) ); i_17: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(22) ); i_170: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(29) ); i_171: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(28) ); i_172: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(27) ); i_173: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(26) ); i_174: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(25) ); i_175: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(24) ); i_176: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(23) ); i_177: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(22) ); i_178: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(21) ); i_179: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(20) ); i_18: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(21) ); i_180: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(19) ); i_181: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(18) ); i_182: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(17) ); i_183: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(16) ); i_184: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(15) ); i_185: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(14) ); i_186: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(13) ); i_187: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(12) ); i_188: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(11) ); i_189: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(10) ); i_19: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(20) ); i_190: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(9) ); i_191: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(8) ); i_192: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(7) ); i_193: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(6) ); i_194: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(5) ); i_195: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(4) ); i_196: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(3) ); i_197: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(2) ); i_198: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(1) ); i_199: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(0) ); i_2: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d2 ); i_20: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(19) ); i_21: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(18) ); i_22: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(17) ); i_23: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(16) ); i_24: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(15) ); i_25: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(14) ); i_26: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(13) ); i_27: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(12) ); i_28: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(11) ); i_29: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(10) ); i_3: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d3 ); i_30: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(9) ); i_31: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(8) ); i_32: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(7) ); i_33: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(6) ); i_34: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(5) ); i_35: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(4) ); i_36: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(3) ); i_37: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(2) ); i_38: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(1) ); i_39: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(0) ); i_4: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d4 ); i_40: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(31) ); i_41: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(30) ); i_42: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(29) ); i_43: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(28) ); i_44: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(27) ); i_45: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(26) ); i_46: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(25) ); i_47: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(24) ); i_48: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(23) ); i_49: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(22) ); i_5: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d5 ); i_50: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(21) ); i_51: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(20) ); i_52: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(19) ); i_53: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(18) ); i_54: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(17) ); i_55: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(16) ); i_56: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(15) ); i_57: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(14) ); i_58: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(13) ); i_59: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(12) ); i_6: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d6 ); i_60: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(11) ); i_61: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(10) ); i_62: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(9) ); i_63: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(8) ); i_64: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(7) ); i_65: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(6) ); i_66: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(5) ); i_67: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(4) ); i_68: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(3) ); i_69: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(2) ); i_7: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d7 ); i_70: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(1) ); i_71: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(0) ); i_72: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(31) ); i_73: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(30) ); i_74: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(29) ); i_75: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(28) ); i_76: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(27) ); i_77: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(26) ); i_78: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(25) ); i_79: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(24) ); i_8: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(31) ); i_80: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(23) ); i_81: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(22) ); i_82: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(21) ); i_83: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(20) ); i_84: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(19) ); i_85: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(18) ); i_86: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(17) ); i_87: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(16) ); i_88: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(15) ); i_89: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(14) ); i_9: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(30) ); i_90: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(13) ); i_91: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(12) ); i_92: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(11) ); i_93: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(10) ); i_94: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(9) ); i_95: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(8) ); i_96: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(7) ); i_97: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(6) ); i_98: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(5) ); i_99: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(4) ); reset_cbcc_comb_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFE" ) port map ( I0 => Q(3), I1 => Q(2), I2 => Q(0), I3 => Q(1), I4 => s_level_out_d5, I5 => reset_cbcc_comb_reg(0), O => \cb_bit_err_ext_cnt_reg[3]\ ); s_level_out_d1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_0, CE => '1', D => p_level_in_int, Q => s_level_out_d1_aurora_64b66b_0_cdc_to, R => '0' ); s_level_out_d2_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_0, CE => '1', D => s_level_out_d1_aurora_64b66b_0_cdc_to, Q => s_level_out_d2, R => '0' ); s_level_out_d3_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_0, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); s_level_out_d4_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_0, CE => '1', D => s_level_out_d3, Q => s_level_out_d4, R => '0' ); s_level_out_d5_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_0, CE => '1', D => s_level_out_d4, Q => s_level_out_d5, R => '0' ); s_level_out_d6_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d5_reg_0, CE => '1', D => s_level_out_d5, Q => s_level_out_d6, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized1_34\ is port ( s_level_out_d5_reg_0 : out STD_LOGIC; in0 : in STD_LOGIC; s_level_out_d6_reg_0 : in STD_LOGIC; CC_RXLOSSOFSYNC_OUT_reg : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized1_34\ : entity is "aurora_64b66b_0_cdc_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized1_34\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized1_34\ is signal p_level_in_int : STD_LOGIC; signal s_level_out_bus_d1_aurora_64b66b_0_cdc_to : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg : string; attribute async_reg of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_bus_d2 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d2 : signal is "true"; attribute shift_extract of s_level_out_bus_d2 : signal is "{no}"; signal s_level_out_bus_d3 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d3 : signal is "true"; attribute shift_extract of s_level_out_bus_d3 : signal is "{no}"; signal s_level_out_bus_d4 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d4 : signal is "true"; attribute shift_extract of s_level_out_bus_d4 : signal is "{no}"; signal s_level_out_bus_d5 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d5 : signal is "true"; attribute shift_extract of s_level_out_bus_d5 : signal is "{no}"; signal s_level_out_bus_d6 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d6 : signal is "true"; attribute shift_extract of s_level_out_bus_d6 : signal is "{no}"; signal s_level_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_d2 : STD_LOGIC; attribute async_reg of s_level_out_d2 : signal is "true"; attribute shift_extract of s_level_out_d2 : signal is "{no}"; signal s_level_out_d3 : STD_LOGIC; attribute async_reg of s_level_out_d3 : signal is "true"; attribute shift_extract of s_level_out_d3 : signal is "{no}"; signal s_level_out_d4 : STD_LOGIC; attribute async_reg of s_level_out_d4 : signal is "true"; attribute shift_extract of s_level_out_d4 : signal is "{no}"; signal s_level_out_d5 : STD_LOGIC; attribute async_reg of s_level_out_d5 : signal is "true"; attribute shift_extract of s_level_out_d5 : signal is "{no}"; signal s_level_out_d6 : STD_LOGIC; attribute async_reg of s_level_out_d6 : signal is "true"; attribute shift_extract of s_level_out_d6 : signal is "{no}"; signal s_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_out_d2 : STD_LOGIC; attribute async_reg of s_out_d2 : signal is "true"; attribute shift_extract of s_out_d2 : signal is "{no}"; signal s_out_d3 : STD_LOGIC; attribute async_reg of s_out_d3 : signal is "true"; attribute shift_extract of s_out_d3 : signal is "{no}"; signal s_out_d4 : STD_LOGIC; attribute async_reg of s_out_d4 : signal is "true"; attribute shift_extract of s_out_d4 : signal is "{no}"; signal s_out_d5 : STD_LOGIC; attribute async_reg of s_out_d5 : signal is "true"; attribute shift_extract of s_out_d5 : signal is "{no}"; signal s_out_d6 : STD_LOGIC; attribute async_reg of s_out_d6 : signal is "true"; attribute shift_extract of s_out_d6 : signal is "{no}"; signal s_out_d7 : STD_LOGIC; attribute async_reg of s_out_d7 : signal is "true"; attribute shift_extract of s_out_d7 : signal is "{no}"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d2_reg : label is std.standard.true; attribute KEEP of s_level_out_d2_reg : label is "yes"; attribute shift_extract of s_level_out_d2_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d3_reg : label is std.standard.true; attribute KEEP of s_level_out_d3_reg : label is "yes"; attribute shift_extract of s_level_out_d3_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d4_reg : label is std.standard.true; attribute KEEP of s_level_out_d4_reg : label is "yes"; attribute shift_extract of s_level_out_d4_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d5_reg : label is std.standard.true; attribute KEEP of s_level_out_d5_reg : label is "yes"; attribute shift_extract of s_level_out_d5_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d6_reg : label is std.standard.true; attribute KEEP of s_level_out_d6_reg : label is "yes"; attribute shift_extract of s_level_out_d6_reg : label is "{no}"; begin p_level_in_int <= in0; CC_RXLOSSOFSYNC_OUT_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"D" ) port map ( I0 => s_level_out_d5, I1 => CC_RXLOSSOFSYNC_OUT_reg, O => s_level_out_d5_reg_0 ); i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d1_aurora_64b66b_0_cdc_to ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d2 ); i_10: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(28) ); i_100: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(2) ); i_101: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(1) ); i_102: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(0) ); i_103: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(31) ); i_104: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(30) ); i_105: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(29) ); i_106: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(28) ); i_107: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(27) ); i_108: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(26) ); i_109: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(25) ); i_11: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(27) ); i_110: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(24) ); i_111: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(23) ); i_112: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(22) ); i_113: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(21) ); i_114: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(20) ); i_115: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(19) ); i_116: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(18) ); i_117: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(17) ); i_118: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(16) ); i_119: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(15) ); i_12: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(26) ); i_120: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(14) ); i_121: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(13) ); i_122: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(12) ); i_123: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(11) ); i_124: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(10) ); i_125: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(9) ); i_126: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(8) ); i_127: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(7) ); i_128: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(6) ); i_129: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(5) ); i_13: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(25) ); i_130: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(4) ); i_131: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(3) ); i_132: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(2) ); i_133: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(1) ); i_134: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(0) ); i_135: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(31) ); i_136: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(30) ); i_137: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(29) ); i_138: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(28) ); i_139: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(27) ); i_14: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(24) ); i_140: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(26) ); i_141: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(25) ); i_142: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(24) ); i_143: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(23) ); i_144: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(22) ); i_145: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(21) ); i_146: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(20) ); i_147: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(19) ); i_148: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(18) ); i_149: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(17) ); i_15: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(23) ); i_150: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(16) ); i_151: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(15) ); i_152: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(14) ); i_153: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(13) ); i_154: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(12) ); i_155: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(11) ); i_156: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(10) ); i_157: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(9) ); i_158: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(8) ); i_159: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(7) ); i_16: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(22) ); i_160: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(6) ); i_161: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(5) ); i_162: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(4) ); i_163: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(3) ); i_164: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(2) ); i_165: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(1) ); i_166: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(0) ); i_167: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(31) ); i_168: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(30) ); i_169: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(29) ); i_17: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(21) ); i_170: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(28) ); i_171: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(27) ); i_172: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(26) ); i_173: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(25) ); i_174: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(24) ); i_175: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(23) ); i_176: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(22) ); i_177: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(21) ); i_178: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(20) ); i_179: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(19) ); i_18: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(20) ); i_180: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(18) ); i_181: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(17) ); i_182: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(16) ); i_183: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(15) ); i_184: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(14) ); i_185: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(13) ); i_186: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(12) ); i_187: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(11) ); i_188: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(10) ); i_189: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(9) ); i_19: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(19) ); i_190: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(8) ); i_191: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(7) ); i_192: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(6) ); i_193: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(5) ); i_194: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(4) ); i_195: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(3) ); i_196: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(2) ); i_197: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(1) ); i_198: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(0) ); i_2: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d3 ); i_20: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(18) ); i_21: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(17) ); i_22: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(16) ); i_23: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(15) ); i_24: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(14) ); i_25: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(13) ); i_26: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(12) ); i_27: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(11) ); i_28: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(10) ); i_29: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(9) ); i_3: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d4 ); i_30: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(8) ); i_31: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(7) ); i_32: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(6) ); i_33: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(5) ); i_34: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(4) ); i_35: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(3) ); i_36: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(2) ); i_37: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(1) ); i_38: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(0) ); i_39: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(31) ); i_4: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d5 ); i_40: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(30) ); i_41: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(29) ); i_42: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(28) ); i_43: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(27) ); i_44: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(26) ); i_45: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(25) ); i_46: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(24) ); i_47: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(23) ); i_48: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(22) ); i_49: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(21) ); i_5: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d6 ); i_50: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(20) ); i_51: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(19) ); i_52: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(18) ); i_53: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(17) ); i_54: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(16) ); i_55: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(15) ); i_56: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(14) ); i_57: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(13) ); i_58: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(12) ); i_59: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(11) ); i_6: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d7 ); i_60: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(10) ); i_61: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(9) ); i_62: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(8) ); i_63: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(7) ); i_64: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(6) ); i_65: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(5) ); i_66: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(4) ); i_67: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(3) ); i_68: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(2) ); i_69: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(1) ); i_7: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(31) ); i_70: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(0) ); i_71: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(31) ); i_72: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(30) ); i_73: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(29) ); i_74: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(28) ); i_75: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(27) ); i_76: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(26) ); i_77: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(25) ); i_78: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(24) ); i_79: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(23) ); i_8: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(30) ); i_80: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(22) ); i_81: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(21) ); i_82: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(20) ); i_83: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(19) ); i_84: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(18) ); i_85: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(17) ); i_86: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(16) ); i_87: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(15) ); i_88: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(14) ); i_89: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(13) ); i_9: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(29) ); i_90: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(12) ); i_91: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(11) ); i_92: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(10) ); i_93: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(9) ); i_94: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(8) ); i_95: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(7) ); i_96: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(6) ); i_97: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(5) ); i_98: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(4) ); i_99: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(3) ); s_level_out_d1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg_0, CE => '1', D => p_level_in_int, Q => s_level_out_d1_aurora_64b66b_0_cdc_to, R => '0' ); s_level_out_d2_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg_0, CE => '1', D => s_level_out_d1_aurora_64b66b_0_cdc_to, Q => s_level_out_d2, R => '0' ); s_level_out_d3_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg_0, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); s_level_out_d4_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg_0, CE => '1', D => s_level_out_d3, Q => s_level_out_d4, R => '0' ); s_level_out_d5_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg_0, CE => '1', D => s_level_out_d4, Q => s_level_out_d5, R => '0' ); s_level_out_d6_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg_0, CE => '1', D => s_level_out_d5, Q => s_level_out_d6, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized1_7\ is port ( hard_err_rst_int_reg : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); in0 : in STD_LOGIC; s_level_out_d6_reg_0 : in STD_LOGIC; hard_err_rst_int : in STD_LOGIC; hard_err_rst_int_reg_0 : in STD_LOGIC; hard_err_rst_int_reg_1 : in STD_LOGIC; hard_err_rst_int_reg_2 : in STD_LOGIC; SR : in STD_LOGIC_VECTOR ( 0 to 0 ); Q : in STD_LOGIC_VECTOR ( 5 downto 0 ); \hard_err_cntr_r_reg[0]\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized1_7\ : entity is "aurora_64b66b_0_cdc_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized1_7\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized1_7\ is signal hard_err_cntr_r1 : STD_LOGIC; signal p_level_in_int : STD_LOGIC; signal s_level_out_bus_d1_aurora_64b66b_0_cdc_to : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg : string; attribute async_reg of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_bus_d2 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d2 : signal is "true"; attribute shift_extract of s_level_out_bus_d2 : signal is "{no}"; signal s_level_out_bus_d3 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d3 : signal is "true"; attribute shift_extract of s_level_out_bus_d3 : signal is "{no}"; signal s_level_out_bus_d4 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d4 : signal is "true"; attribute shift_extract of s_level_out_bus_d4 : signal is "{no}"; signal s_level_out_bus_d5 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d5 : signal is "true"; attribute shift_extract of s_level_out_bus_d5 : signal is "{no}"; signal s_level_out_bus_d6 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d6 : signal is "true"; attribute shift_extract of s_level_out_bus_d6 : signal is "{no}"; signal s_level_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_d2 : STD_LOGIC; attribute async_reg of s_level_out_d2 : signal is "true"; attribute shift_extract of s_level_out_d2 : signal is "{no}"; signal s_level_out_d3 : STD_LOGIC; attribute async_reg of s_level_out_d3 : signal is "true"; attribute shift_extract of s_level_out_d3 : signal is "{no}"; signal s_level_out_d4 : STD_LOGIC; attribute async_reg of s_level_out_d4 : signal is "true"; attribute shift_extract of s_level_out_d4 : signal is "{no}"; signal s_level_out_d5 : STD_LOGIC; attribute async_reg of s_level_out_d5 : signal is "true"; attribute shift_extract of s_level_out_d5 : signal is "{no}"; signal s_level_out_d6 : STD_LOGIC; attribute async_reg of s_level_out_d6 : signal is "true"; attribute shift_extract of s_level_out_d6 : signal is "{no}"; signal s_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_out_d2 : STD_LOGIC; attribute async_reg of s_out_d2 : signal is "true"; attribute shift_extract of s_out_d2 : signal is "{no}"; signal s_out_d3 : STD_LOGIC; attribute async_reg of s_out_d3 : signal is "true"; attribute shift_extract of s_out_d3 : signal is "{no}"; signal s_out_d4 : STD_LOGIC; attribute async_reg of s_out_d4 : signal is "true"; attribute shift_extract of s_out_d4 : signal is "{no}"; signal s_out_d5 : STD_LOGIC; attribute async_reg of s_out_d5 : signal is "true"; attribute shift_extract of s_out_d5 : signal is "{no}"; signal s_out_d6 : STD_LOGIC; attribute async_reg of s_out_d6 : signal is "true"; attribute shift_extract of s_out_d6 : signal is "{no}"; signal s_out_d7 : STD_LOGIC; attribute async_reg of s_out_d7 : signal is "true"; attribute shift_extract of s_out_d7 : signal is "{no}"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d2_reg : label is std.standard.true; attribute KEEP of s_level_out_d2_reg : label is "yes"; attribute shift_extract of s_level_out_d2_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d3_reg : label is std.standard.true; attribute KEEP of s_level_out_d3_reg : label is "yes"; attribute shift_extract of s_level_out_d3_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d4_reg : label is std.standard.true; attribute KEEP of s_level_out_d4_reg : label is "yes"; attribute shift_extract of s_level_out_d4_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d5_reg : label is std.standard.true; attribute KEEP of s_level_out_d5_reg : label is "yes"; attribute shift_extract of s_level_out_d5_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d6_reg : label is std.standard.true; attribute KEEP of s_level_out_d6_reg : label is "yes"; attribute shift_extract of s_level_out_d6_reg : label is "{no}"; begin p_level_in_int <= in0; \hard_err_cntr_r[7]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAA2AAAAAAA" ) port map ( I0 => hard_err_cntr_r1, I1 => Q(4), I2 => Q(3), I3 => Q(5), I4 => Q(2), I5 => \hard_err_cntr_r_reg[0]\, O => E(0) ); \hard_err_cntr_r[7]_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => hard_err_rst_int_reg_1, I1 => Q(0), I2 => Q(1), I3 => s_level_out_d5, O => hard_err_cntr_r1 ); hard_err_rst_int_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"00000000FF020F02" ) port map ( I0 => hard_err_rst_int, I1 => s_level_out_d5, I2 => hard_err_rst_int_reg_0, I3 => hard_err_rst_int_reg_1, I4 => hard_err_rst_int_reg_2, I5 => SR(0), O => hard_err_rst_int_reg ); i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d1_aurora_64b66b_0_cdc_to ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d2 ); i_10: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(28) ); i_100: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(2) ); i_101: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(1) ); i_102: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(0) ); i_103: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(31) ); i_104: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(30) ); i_105: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(29) ); i_106: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(28) ); i_107: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(27) ); i_108: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(26) ); i_109: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(25) ); i_11: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(27) ); i_110: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(24) ); i_111: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(23) ); i_112: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(22) ); i_113: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(21) ); i_114: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(20) ); i_115: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(19) ); i_116: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(18) ); i_117: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(17) ); i_118: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(16) ); i_119: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(15) ); i_12: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(26) ); i_120: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(14) ); i_121: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(13) ); i_122: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(12) ); i_123: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(11) ); i_124: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(10) ); i_125: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(9) ); i_126: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(8) ); i_127: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(7) ); i_128: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(6) ); i_129: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(5) ); i_13: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(25) ); i_130: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(4) ); i_131: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(3) ); i_132: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(2) ); i_133: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(1) ); i_134: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(0) ); i_135: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(31) ); i_136: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(30) ); i_137: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(29) ); i_138: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(28) ); i_139: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(27) ); i_14: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(24) ); i_140: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(26) ); i_141: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(25) ); i_142: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(24) ); i_143: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(23) ); i_144: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(22) ); i_145: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(21) ); i_146: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(20) ); i_147: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(19) ); i_148: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(18) ); i_149: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(17) ); i_15: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(23) ); i_150: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(16) ); i_151: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(15) ); i_152: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(14) ); i_153: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(13) ); i_154: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(12) ); i_155: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(11) ); i_156: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(10) ); i_157: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(9) ); i_158: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(8) ); i_159: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(7) ); i_16: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(22) ); i_160: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(6) ); i_161: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(5) ); i_162: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(4) ); i_163: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(3) ); i_164: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(2) ); i_165: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(1) ); i_166: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(0) ); i_167: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(31) ); i_168: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(30) ); i_169: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(29) ); i_17: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(21) ); i_170: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(28) ); i_171: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(27) ); i_172: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(26) ); i_173: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(25) ); i_174: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(24) ); i_175: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(23) ); i_176: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(22) ); i_177: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(21) ); i_178: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(20) ); i_179: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(19) ); i_18: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(20) ); i_180: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(18) ); i_181: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(17) ); i_182: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(16) ); i_183: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(15) ); i_184: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(14) ); i_185: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(13) ); i_186: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(12) ); i_187: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(11) ); i_188: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(10) ); i_189: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(9) ); i_19: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(19) ); i_190: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(8) ); i_191: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(7) ); i_192: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(6) ); i_193: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(5) ); i_194: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(4) ); i_195: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(3) ); i_196: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(2) ); i_197: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(1) ); i_198: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(0) ); i_2: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d3 ); i_20: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(18) ); i_21: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(17) ); i_22: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(16) ); i_23: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(15) ); i_24: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(14) ); i_25: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(13) ); i_26: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(12) ); i_27: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(11) ); i_28: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(10) ); i_29: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(9) ); i_3: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d4 ); i_30: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(8) ); i_31: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(7) ); i_32: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(6) ); i_33: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(5) ); i_34: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(4) ); i_35: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(3) ); i_36: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(2) ); i_37: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(1) ); i_38: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(0) ); i_39: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(31) ); i_4: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d5 ); i_40: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(30) ); i_41: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(29) ); i_42: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(28) ); i_43: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(27) ); i_44: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(26) ); i_45: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(25) ); i_46: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(24) ); i_47: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(23) ); i_48: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(22) ); i_49: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(21) ); i_5: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d6 ); i_50: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(20) ); i_51: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(19) ); i_52: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(18) ); i_53: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(17) ); i_54: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(16) ); i_55: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(15) ); i_56: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(14) ); i_57: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(13) ); i_58: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(12) ); i_59: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(11) ); i_6: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d7 ); i_60: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(10) ); i_61: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(9) ); i_62: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(8) ); i_63: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(7) ); i_64: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(6) ); i_65: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(5) ); i_66: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(4) ); i_67: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(3) ); i_68: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(2) ); i_69: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(1) ); i_7: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(31) ); i_70: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(0) ); i_71: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(31) ); i_72: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(30) ); i_73: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(29) ); i_74: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(28) ); i_75: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(27) ); i_76: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(26) ); i_77: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(25) ); i_78: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(24) ); i_79: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(23) ); i_8: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(30) ); i_80: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(22) ); i_81: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(21) ); i_82: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(20) ); i_83: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(19) ); i_84: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(18) ); i_85: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(17) ); i_86: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(16) ); i_87: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(15) ); i_88: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(14) ); i_89: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(13) ); i_9: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(29) ); i_90: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(12) ); i_91: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(11) ); i_92: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(10) ); i_93: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(9) ); i_94: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(8) ); i_95: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(7) ); i_96: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(6) ); i_97: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(5) ); i_98: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(4) ); i_99: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(3) ); s_level_out_d1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg_0, CE => '1', D => p_level_in_int, Q => s_level_out_d1_aurora_64b66b_0_cdc_to, R => '0' ); s_level_out_d2_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg_0, CE => '1', D => s_level_out_d1_aurora_64b66b_0_cdc_to, Q => s_level_out_d2, R => '0' ); s_level_out_d3_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg_0, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); s_level_out_d4_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg_0, CE => '1', D => s_level_out_d3, Q => s_level_out_d4, R => '0' ); s_level_out_d5_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg_0, CE => '1', D => s_level_out_d4, Q => s_level_out_d5, R => '0' ); s_level_out_d6_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg_0, CE => '1', D => s_level_out_d5, Q => s_level_out_d6, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized2\ is port ( \out\ : out STD_LOGIC; s_level_out_d1_aurora_64b66b_0_cdc_to_reg_0 : in STD_LOGIC; s_level_out_d6_reg_0 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized2\ : entity is "aurora_64b66b_0_cdc_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized2\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized2\ is signal p_level_in_int : STD_LOGIC; signal s_level_out_bus_d1_aurora_64b66b_0_cdc_to : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg : string; attribute async_reg of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_bus_d2 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d2 : signal is "true"; attribute shift_extract of s_level_out_bus_d2 : signal is "{no}"; signal s_level_out_bus_d3 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d3 : signal is "true"; attribute shift_extract of s_level_out_bus_d3 : signal is "{no}"; signal s_level_out_bus_d4 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d4 : signal is "true"; attribute shift_extract of s_level_out_bus_d4 : signal is "{no}"; signal s_level_out_bus_d5 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d5 : signal is "true"; attribute shift_extract of s_level_out_bus_d5 : signal is "{no}"; signal s_level_out_bus_d6 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d6 : signal is "true"; attribute shift_extract of s_level_out_bus_d6 : signal is "{no}"; signal s_level_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_d2 : STD_LOGIC; attribute async_reg of s_level_out_d2 : signal is "true"; attribute shift_extract of s_level_out_d2 : signal is "{no}"; signal s_level_out_d3 : STD_LOGIC; attribute async_reg of s_level_out_d3 : signal is "true"; attribute shift_extract of s_level_out_d3 : signal is "{no}"; signal s_level_out_d4 : STD_LOGIC; attribute async_reg of s_level_out_d4 : signal is "true"; attribute shift_extract of s_level_out_d4 : signal is "{no}"; signal s_level_out_d5 : STD_LOGIC; attribute async_reg of s_level_out_d5 : signal is "true"; attribute shift_extract of s_level_out_d5 : signal is "{no}"; signal s_level_out_d6 : STD_LOGIC; attribute async_reg of s_level_out_d6 : signal is "true"; attribute shift_extract of s_level_out_d6 : signal is "{no}"; signal s_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_out_d2 : STD_LOGIC; attribute async_reg of s_out_d2 : signal is "true"; attribute shift_extract of s_out_d2 : signal is "{no}"; signal s_out_d3 : STD_LOGIC; attribute async_reg of s_out_d3 : signal is "true"; attribute shift_extract of s_out_d3 : signal is "{no}"; signal s_out_d4 : STD_LOGIC; attribute async_reg of s_out_d4 : signal is "true"; attribute shift_extract of s_out_d4 : signal is "{no}"; signal s_out_d5 : STD_LOGIC; attribute async_reg of s_out_d5 : signal is "true"; attribute shift_extract of s_out_d5 : signal is "{no}"; signal s_out_d6 : STD_LOGIC; attribute async_reg of s_out_d6 : signal is "true"; attribute shift_extract of s_out_d6 : signal is "{no}"; signal s_out_d7 : STD_LOGIC; attribute async_reg of s_out_d7 : signal is "true"; attribute shift_extract of s_out_d7 : signal is "{no}"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d2_reg : label is std.standard.true; attribute KEEP of s_level_out_d2_reg : label is "yes"; attribute shift_extract of s_level_out_d2_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d3_reg : label is std.standard.true; attribute KEEP of s_level_out_d3_reg : label is "yes"; attribute shift_extract of s_level_out_d3_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d4_reg : label is std.standard.true; attribute KEEP of s_level_out_d4_reg : label is "yes"; attribute shift_extract of s_level_out_d4_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d5_reg : label is std.standard.true; attribute KEEP of s_level_out_d5_reg : label is "yes"; attribute shift_extract of s_level_out_d5_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d6_reg : label is std.standard.true; attribute KEEP of s_level_out_d6_reg : label is "yes"; attribute shift_extract of s_level_out_d6_reg : label is "{no}"; begin \out\ <= s_level_out_d3; p_level_in_int <= s_level_out_d1_aurora_64b66b_0_cdc_to_reg_0; i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d1_aurora_64b66b_0_cdc_to ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d2 ); i_10: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(28) ); i_100: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(2) ); i_101: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(1) ); i_102: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(0) ); i_103: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(31) ); i_104: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(30) ); i_105: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(29) ); i_106: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(28) ); i_107: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(27) ); i_108: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(26) ); i_109: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(25) ); i_11: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(27) ); i_110: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(24) ); i_111: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(23) ); i_112: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(22) ); i_113: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(21) ); i_114: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(20) ); i_115: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(19) ); i_116: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(18) ); i_117: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(17) ); i_118: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(16) ); i_119: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(15) ); i_12: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(26) ); i_120: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(14) ); i_121: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(13) ); i_122: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(12) ); i_123: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(11) ); i_124: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(10) ); i_125: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(9) ); i_126: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(8) ); i_127: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(7) ); i_128: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(6) ); i_129: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(5) ); i_13: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(25) ); i_130: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(4) ); i_131: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(3) ); i_132: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(2) ); i_133: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(1) ); i_134: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(0) ); i_135: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(31) ); i_136: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(30) ); i_137: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(29) ); i_138: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(28) ); i_139: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(27) ); i_14: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(24) ); i_140: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(26) ); i_141: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(25) ); i_142: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(24) ); i_143: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(23) ); i_144: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(22) ); i_145: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(21) ); i_146: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(20) ); i_147: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(19) ); i_148: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(18) ); i_149: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(17) ); i_15: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(23) ); i_150: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(16) ); i_151: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(15) ); i_152: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(14) ); i_153: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(13) ); i_154: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(12) ); i_155: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(11) ); i_156: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(10) ); i_157: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(9) ); i_158: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(8) ); i_159: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(7) ); i_16: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(22) ); i_160: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(6) ); i_161: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(5) ); i_162: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(4) ); i_163: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(3) ); i_164: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(2) ); i_165: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(1) ); i_166: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(0) ); i_167: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(31) ); i_168: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(30) ); i_169: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(29) ); i_17: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(21) ); i_170: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(28) ); i_171: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(27) ); i_172: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(26) ); i_173: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(25) ); i_174: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(24) ); i_175: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(23) ); i_176: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(22) ); i_177: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(21) ); i_178: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(20) ); i_179: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(19) ); i_18: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(20) ); i_180: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(18) ); i_181: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(17) ); i_182: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(16) ); i_183: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(15) ); i_184: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(14) ); i_185: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(13) ); i_186: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(12) ); i_187: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(11) ); i_188: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(10) ); i_189: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(9) ); i_19: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(19) ); i_190: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(8) ); i_191: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(7) ); i_192: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(6) ); i_193: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(5) ); i_194: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(4) ); i_195: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(3) ); i_196: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(2) ); i_197: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(1) ); i_198: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(0) ); i_2: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d3 ); i_20: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(18) ); i_21: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(17) ); i_22: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(16) ); i_23: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(15) ); i_24: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(14) ); i_25: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(13) ); i_26: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(12) ); i_27: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(11) ); i_28: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(10) ); i_29: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(9) ); i_3: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d4 ); i_30: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(8) ); i_31: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(7) ); i_32: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(6) ); i_33: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(5) ); i_34: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(4) ); i_35: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(3) ); i_36: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(2) ); i_37: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(1) ); i_38: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(0) ); i_39: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(31) ); i_4: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d5 ); i_40: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(30) ); i_41: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(29) ); i_42: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(28) ); i_43: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(27) ); i_44: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(26) ); i_45: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(25) ); i_46: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(24) ); i_47: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(23) ); i_48: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(22) ); i_49: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(21) ); i_5: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d6 ); i_50: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(20) ); i_51: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(19) ); i_52: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(18) ); i_53: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(17) ); i_54: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(16) ); i_55: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(15) ); i_56: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(14) ); i_57: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(13) ); i_58: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(12) ); i_59: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(11) ); i_6: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d7 ); i_60: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(10) ); i_61: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(9) ); i_62: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(8) ); i_63: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(7) ); i_64: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(6) ); i_65: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(5) ); i_66: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(4) ); i_67: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(3) ); i_68: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(2) ); i_69: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(1) ); i_7: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(31) ); i_70: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(0) ); i_71: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(31) ); i_72: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(30) ); i_73: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(29) ); i_74: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(28) ); i_75: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(27) ); i_76: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(26) ); i_77: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(25) ); i_78: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(24) ); i_79: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(23) ); i_8: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(30) ); i_80: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(22) ); i_81: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(21) ); i_82: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(20) ); i_83: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(19) ); i_84: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(18) ); i_85: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(17) ); i_86: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(16) ); i_87: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(15) ); i_88: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(14) ); i_89: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(13) ); i_9: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(29) ); i_90: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(12) ); i_91: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(11) ); i_92: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(10) ); i_93: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(9) ); i_94: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(8) ); i_95: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(7) ); i_96: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(6) ); i_97: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(5) ); i_98: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(4) ); i_99: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(3) ); s_level_out_d1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg_0, CE => '1', D => p_level_in_int, Q => s_level_out_d1_aurora_64b66b_0_cdc_to, R => '0' ); s_level_out_d2_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg_0, CE => '1', D => s_level_out_d1_aurora_64b66b_0_cdc_to, Q => s_level_out_d2, R => '0' ); s_level_out_d3_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg_0, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); s_level_out_d4_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg_0, CE => '1', D => s_level_out_d3, Q => s_level_out_d4, R => '0' ); s_level_out_d5_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg_0, CE => '1', D => s_level_out_d4, Q => s_level_out_d5, R => '0' ); s_level_out_d6_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg_0, CE => '1', D => s_level_out_d5, Q => s_level_out_d6, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized3\ is port ( cbcc_reset_cbstg2_rd_clk : in STD_LOGIC; overflow_flag_c : in STD_LOGIC; s_level_out_d6_reg_0 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized3\ : entity is "aurora_64b66b_0_cdc_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized3\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized3\ is signal s_level_out_bus_d1_aurora_64b66b_0_cdc_to : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg : string; attribute async_reg of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_bus_d2 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d2 : signal is "true"; attribute shift_extract of s_level_out_bus_d2 : signal is "{no}"; signal s_level_out_bus_d3 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d3 : signal is "true"; attribute shift_extract of s_level_out_bus_d3 : signal is "{no}"; signal s_level_out_bus_d4 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d4 : signal is "true"; attribute shift_extract of s_level_out_bus_d4 : signal is "{no}"; signal s_level_out_bus_d5 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d5 : signal is "true"; attribute shift_extract of s_level_out_bus_d5 : signal is "{no}"; signal s_level_out_bus_d6 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d6 : signal is "true"; attribute shift_extract of s_level_out_bus_d6 : signal is "{no}"; signal s_level_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_d2 : STD_LOGIC; attribute async_reg of s_level_out_d2 : signal is "true"; attribute shift_extract of s_level_out_d2 : signal is "{no}"; signal s_level_out_d3 : STD_LOGIC; attribute async_reg of s_level_out_d3 : signal is "true"; attribute shift_extract of s_level_out_d3 : signal is "{no}"; signal s_level_out_d4 : STD_LOGIC; attribute async_reg of s_level_out_d4 : signal is "true"; attribute shift_extract of s_level_out_d4 : signal is "{no}"; signal s_level_out_d5 : STD_LOGIC; attribute async_reg of s_level_out_d5 : signal is "true"; attribute shift_extract of s_level_out_d5 : signal is "{no}"; signal s_level_out_d6 : STD_LOGIC; attribute async_reg of s_level_out_d6 : signal is "true"; attribute shift_extract of s_level_out_d6 : signal is "{no}"; signal s_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_out_d2 : STD_LOGIC; attribute async_reg of s_out_d2 : signal is "true"; attribute shift_extract of s_out_d2 : signal is "{no}"; signal s_out_d3 : STD_LOGIC; attribute async_reg of s_out_d3 : signal is "true"; attribute shift_extract of s_out_d3 : signal is "{no}"; signal s_out_d4 : STD_LOGIC; attribute async_reg of s_out_d4 : signal is "true"; attribute shift_extract of s_out_d4 : signal is "{no}"; signal s_out_d5 : STD_LOGIC; attribute async_reg of s_out_d5 : signal is "true"; attribute shift_extract of s_out_d5 : signal is "{no}"; signal s_out_d6 : STD_LOGIC; attribute async_reg of s_out_d6 : signal is "true"; attribute shift_extract of s_out_d6 : signal is "{no}"; signal s_out_d7 : STD_LOGIC; attribute async_reg of s_out_d7 : signal is "true"; attribute shift_extract of s_out_d7 : signal is "{no}"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d2_reg : label is std.standard.true; attribute KEEP of s_level_out_d2_reg : label is "yes"; attribute shift_extract of s_level_out_d2_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d3_reg : label is std.standard.true; attribute KEEP of s_level_out_d3_reg : label is "yes"; attribute shift_extract of s_level_out_d3_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d4_reg : label is std.standard.true; attribute KEEP of s_level_out_d4_reg : label is "yes"; attribute shift_extract of s_level_out_d4_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d5_reg : label is std.standard.true; attribute KEEP of s_level_out_d5_reg : label is "yes"; attribute shift_extract of s_level_out_d5_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d6_reg : label is std.standard.true; attribute KEEP of s_level_out_d6_reg : label is "yes"; attribute shift_extract of s_level_out_d6_reg : label is "{no}"; begin i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d1_aurora_64b66b_0_cdc_to ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d2 ); i_10: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(28) ); i_100: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(2) ); i_101: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(1) ); i_102: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(0) ); i_103: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(31) ); i_104: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(30) ); i_105: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(29) ); i_106: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(28) ); i_107: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(27) ); i_108: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(26) ); i_109: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(25) ); i_11: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(27) ); i_110: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(24) ); i_111: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(23) ); i_112: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(22) ); i_113: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(21) ); i_114: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(20) ); i_115: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(19) ); i_116: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(18) ); i_117: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(17) ); i_118: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(16) ); i_119: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(15) ); i_12: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(26) ); i_120: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(14) ); i_121: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(13) ); i_122: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(12) ); i_123: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(11) ); i_124: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(10) ); i_125: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(9) ); i_126: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(8) ); i_127: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(7) ); i_128: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(6) ); i_129: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(5) ); i_13: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(25) ); i_130: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(4) ); i_131: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(3) ); i_132: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(2) ); i_133: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(1) ); i_134: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(0) ); i_135: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(31) ); i_136: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(30) ); i_137: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(29) ); i_138: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(28) ); i_139: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(27) ); i_14: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(24) ); i_140: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(26) ); i_141: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(25) ); i_142: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(24) ); i_143: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(23) ); i_144: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(22) ); i_145: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(21) ); i_146: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(20) ); i_147: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(19) ); i_148: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(18) ); i_149: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(17) ); i_15: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(23) ); i_150: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(16) ); i_151: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(15) ); i_152: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(14) ); i_153: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(13) ); i_154: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(12) ); i_155: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(11) ); i_156: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(10) ); i_157: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(9) ); i_158: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(8) ); i_159: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(7) ); i_16: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(22) ); i_160: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(6) ); i_161: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(5) ); i_162: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(4) ); i_163: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(3) ); i_164: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(2) ); i_165: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(1) ); i_166: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(0) ); i_167: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(31) ); i_168: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(30) ); i_169: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(29) ); i_17: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(21) ); i_170: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(28) ); i_171: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(27) ); i_172: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(26) ); i_173: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(25) ); i_174: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(24) ); i_175: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(23) ); i_176: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(22) ); i_177: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(21) ); i_178: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(20) ); i_179: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(19) ); i_18: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(20) ); i_180: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(18) ); i_181: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(17) ); i_182: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(16) ); i_183: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(15) ); i_184: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(14) ); i_185: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(13) ); i_186: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(12) ); i_187: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(11) ); i_188: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(10) ); i_189: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(9) ); i_19: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(19) ); i_190: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(8) ); i_191: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(7) ); i_192: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(6) ); i_193: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(5) ); i_194: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(4) ); i_195: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(3) ); i_196: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(2) ); i_197: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(1) ); i_198: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(0) ); i_2: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d3 ); i_20: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(18) ); i_21: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(17) ); i_22: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(16) ); i_23: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(15) ); i_24: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(14) ); i_25: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(13) ); i_26: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(12) ); i_27: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(11) ); i_28: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(10) ); i_29: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(9) ); i_3: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d4 ); i_30: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(8) ); i_31: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(7) ); i_32: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(6) ); i_33: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(5) ); i_34: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(4) ); i_35: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(3) ); i_36: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(2) ); i_37: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(1) ); i_38: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(0) ); i_39: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(31) ); i_4: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d5 ); i_40: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(30) ); i_41: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(29) ); i_42: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(28) ); i_43: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(27) ); i_44: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(26) ); i_45: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(25) ); i_46: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(24) ); i_47: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(23) ); i_48: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(22) ); i_49: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(21) ); i_5: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d6 ); i_50: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(20) ); i_51: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(19) ); i_52: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(18) ); i_53: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(17) ); i_54: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(16) ); i_55: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(15) ); i_56: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(14) ); i_57: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(13) ); i_58: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(12) ); i_59: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(11) ); i_6: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d7 ); i_60: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(10) ); i_61: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(9) ); i_62: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(8) ); i_63: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(7) ); i_64: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(6) ); i_65: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(5) ); i_66: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(4) ); i_67: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(3) ); i_68: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(2) ); i_69: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(1) ); i_7: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(31) ); i_70: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(0) ); i_71: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(31) ); i_72: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(30) ); i_73: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(29) ); i_74: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(28) ); i_75: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(27) ); i_76: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(26) ); i_77: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(25) ); i_78: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(24) ); i_79: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(23) ); i_8: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(30) ); i_80: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(22) ); i_81: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(21) ); i_82: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(20) ); i_83: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(19) ); i_84: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(18) ); i_85: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(17) ); i_86: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(16) ); i_87: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(15) ); i_88: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(14) ); i_89: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(13) ); i_9: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(29) ); i_90: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(12) ); i_91: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(11) ); i_92: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(10) ); i_93: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(9) ); i_94: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(8) ); i_95: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(7) ); i_96: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(6) ); i_97: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(5) ); i_98: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(4) ); i_99: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(3) ); s_level_out_d1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg_0, CE => '1', D => overflow_flag_c, Q => s_level_out_d1_aurora_64b66b_0_cdc_to, R => cbcc_reset_cbstg2_rd_clk ); s_level_out_d2_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg_0, CE => '1', D => s_level_out_d1_aurora_64b66b_0_cdc_to, Q => s_level_out_d2, R => cbcc_reset_cbstg2_rd_clk ); s_level_out_d3_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg_0, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => cbcc_reset_cbstg2_rd_clk ); s_level_out_d4_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg_0, CE => '1', D => s_level_out_d3, Q => s_level_out_d4, R => cbcc_reset_cbstg2_rd_clk ); s_level_out_d5_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg_0, CE => '1', D => s_level_out_d4, Q => s_level_out_d5, R => cbcc_reset_cbstg2_rd_clk ); s_level_out_d6_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg_0, CE => '1', D => s_level_out_d5, Q => s_level_out_d6, R => cbcc_reset_cbstg2_rd_clk ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized3_35\ is port ( \out\ : out STD_LOGIC; cbcc_fifo_reset_rd_clk : in STD_LOGIC; wr_err_c : in STD_LOGIC; s_level_out_d6_reg_0 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized3_35\ : entity is "aurora_64b66b_0_cdc_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized3_35\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized3_35\ is signal s_level_out_bus_d1_aurora_64b66b_0_cdc_to : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg : string; attribute async_reg of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of s_level_out_bus_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_bus_d2 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d2 : signal is "true"; attribute shift_extract of s_level_out_bus_d2 : signal is "{no}"; signal s_level_out_bus_d3 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d3 : signal is "true"; attribute shift_extract of s_level_out_bus_d3 : signal is "{no}"; signal s_level_out_bus_d4 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d4 : signal is "true"; attribute shift_extract of s_level_out_bus_d4 : signal is "{no}"; signal s_level_out_bus_d5 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d5 : signal is "true"; attribute shift_extract of s_level_out_bus_d5 : signal is "{no}"; signal s_level_out_bus_d6 : STD_LOGIC_VECTOR ( 31 downto 0 ); attribute async_reg of s_level_out_bus_d6 : signal is "true"; attribute shift_extract of s_level_out_bus_d6 : signal is "{no}"; signal s_level_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_level_out_d2 : STD_LOGIC; attribute async_reg of s_level_out_d2 : signal is "true"; attribute shift_extract of s_level_out_d2 : signal is "{no}"; signal s_level_out_d3 : STD_LOGIC; attribute async_reg of s_level_out_d3 : signal is "true"; attribute shift_extract of s_level_out_d3 : signal is "{no}"; signal s_level_out_d4 : STD_LOGIC; attribute async_reg of s_level_out_d4 : signal is "true"; attribute shift_extract of s_level_out_d4 : signal is "{no}"; signal s_level_out_d5 : STD_LOGIC; attribute async_reg of s_level_out_d5 : signal is "true"; attribute shift_extract of s_level_out_d5 : signal is "{no}"; signal s_level_out_d6 : STD_LOGIC; attribute async_reg of s_level_out_d6 : signal is "true"; attribute shift_extract of s_level_out_d6 : signal is "{no}"; signal s_out_d1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg of s_out_d1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract of s_out_d1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal s_out_d2 : STD_LOGIC; attribute async_reg of s_out_d2 : signal is "true"; attribute shift_extract of s_out_d2 : signal is "{no}"; signal s_out_d3 : STD_LOGIC; attribute async_reg of s_out_d3 : signal is "true"; attribute shift_extract of s_out_d3 : signal is "{no}"; signal s_out_d4 : STD_LOGIC; attribute async_reg of s_out_d4 : signal is "true"; attribute shift_extract of s_out_d4 : signal is "{no}"; signal s_out_d5 : STD_LOGIC; attribute async_reg of s_out_d5 : signal is "true"; attribute shift_extract of s_out_d5 : signal is "{no}"; signal s_out_d6 : STD_LOGIC; attribute async_reg of s_out_d6 : signal is "true"; attribute shift_extract of s_out_d6 : signal is "{no}"; signal s_out_d7 : STD_LOGIC; attribute async_reg of s_out_d7 : signal is "true"; attribute shift_extract of s_out_d7 : signal is "{no}"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of s_level_out_d1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d2_reg : label is std.standard.true; attribute KEEP of s_level_out_d2_reg : label is "yes"; attribute shift_extract of s_level_out_d2_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d3_reg : label is std.standard.true; attribute KEEP of s_level_out_d3_reg : label is "yes"; attribute shift_extract of s_level_out_d3_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d4_reg : label is std.standard.true; attribute KEEP of s_level_out_d4_reg : label is "yes"; attribute shift_extract of s_level_out_d4_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d5_reg : label is std.standard.true; attribute KEEP of s_level_out_d5_reg : label is "yes"; attribute shift_extract of s_level_out_d5_reg : label is "{no}"; attribute ASYNC_REG_boolean of s_level_out_d6_reg : label is std.standard.true; attribute KEEP of s_level_out_d6_reg : label is "yes"; attribute shift_extract of s_level_out_d6_reg : label is "{no}"; begin \out\ <= s_level_out_d5; i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d1_aurora_64b66b_0_cdc_to ); i_1: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d2 ); i_10: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(28) ); i_100: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(2) ); i_101: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(1) ); i_102: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(0) ); i_103: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(31) ); i_104: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(30) ); i_105: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(29) ); i_106: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(28) ); i_107: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(27) ); i_108: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(26) ); i_109: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(25) ); i_11: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(27) ); i_110: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(24) ); i_111: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(23) ); i_112: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(22) ); i_113: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(21) ); i_114: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(20) ); i_115: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(19) ); i_116: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(18) ); i_117: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(17) ); i_118: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(16) ); i_119: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(15) ); i_12: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(26) ); i_120: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(14) ); i_121: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(13) ); i_122: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(12) ); i_123: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(11) ); i_124: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(10) ); i_125: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(9) ); i_126: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(8) ); i_127: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(7) ); i_128: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(6) ); i_129: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(5) ); i_13: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(25) ); i_130: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(4) ); i_131: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(3) ); i_132: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(2) ); i_133: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(1) ); i_134: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d4(0) ); i_135: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(31) ); i_136: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(30) ); i_137: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(29) ); i_138: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(28) ); i_139: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(27) ); i_14: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(24) ); i_140: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(26) ); i_141: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(25) ); i_142: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(24) ); i_143: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(23) ); i_144: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(22) ); i_145: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(21) ); i_146: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(20) ); i_147: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(19) ); i_148: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(18) ); i_149: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(17) ); i_15: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(23) ); i_150: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(16) ); i_151: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(15) ); i_152: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(14) ); i_153: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(13) ); i_154: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(12) ); i_155: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(11) ); i_156: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(10) ); i_157: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(9) ); i_158: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(8) ); i_159: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(7) ); i_16: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(22) ); i_160: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(6) ); i_161: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(5) ); i_162: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(4) ); i_163: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(3) ); i_164: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(2) ); i_165: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(1) ); i_166: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d5(0) ); i_167: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(31) ); i_168: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(30) ); i_169: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(29) ); i_17: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(21) ); i_170: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(28) ); i_171: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(27) ); i_172: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(26) ); i_173: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(25) ); i_174: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(24) ); i_175: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(23) ); i_176: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(22) ); i_177: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(21) ); i_178: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(20) ); i_179: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(19) ); i_18: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(20) ); i_180: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(18) ); i_181: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(17) ); i_182: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(16) ); i_183: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(15) ); i_184: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(14) ); i_185: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(13) ); i_186: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(12) ); i_187: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(11) ); i_188: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(10) ); i_189: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(9) ); i_19: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(19) ); i_190: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(8) ); i_191: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(7) ); i_192: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(6) ); i_193: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(5) ); i_194: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(4) ); i_195: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(3) ); i_196: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(2) ); i_197: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(1) ); i_198: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d6(0) ); i_2: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d3 ); i_20: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(18) ); i_21: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(17) ); i_22: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(16) ); i_23: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(15) ); i_24: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(14) ); i_25: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(13) ); i_26: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(12) ); i_27: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(11) ); i_28: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(10) ); i_29: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(9) ); i_3: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d4 ); i_30: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(8) ); i_31: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(7) ); i_32: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(6) ); i_33: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(5) ); i_34: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(4) ); i_35: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(3) ); i_36: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(2) ); i_37: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(1) ); i_38: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(0) ); i_39: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(31) ); i_4: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d5 ); i_40: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(30) ); i_41: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(29) ); i_42: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(28) ); i_43: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(27) ); i_44: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(26) ); i_45: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(25) ); i_46: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(24) ); i_47: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(23) ); i_48: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(22) ); i_49: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(21) ); i_5: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d6 ); i_50: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(20) ); i_51: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(19) ); i_52: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(18) ); i_53: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(17) ); i_54: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(16) ); i_55: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(15) ); i_56: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(14) ); i_57: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(13) ); i_58: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(12) ); i_59: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(11) ); i_6: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_out_d7 ); i_60: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(10) ); i_61: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(9) ); i_62: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(8) ); i_63: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(7) ); i_64: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(6) ); i_65: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(5) ); i_66: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(4) ); i_67: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(3) ); i_68: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(2) ); i_69: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(1) ); i_7: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(31) ); i_70: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d2(0) ); i_71: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(31) ); i_72: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(30) ); i_73: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(29) ); i_74: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(28) ); i_75: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(27) ); i_76: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(26) ); i_77: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(25) ); i_78: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(24) ); i_79: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(23) ); i_8: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(30) ); i_80: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(22) ); i_81: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(21) ); i_82: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(20) ); i_83: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(19) ); i_84: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(18) ); i_85: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(17) ); i_86: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(16) ); i_87: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(15) ); i_88: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(14) ); i_89: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(13) ); i_9: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d1_aurora_64b66b_0_cdc_to(29) ); i_90: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(12) ); i_91: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(11) ); i_92: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(10) ); i_93: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(9) ); i_94: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(8) ); i_95: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(7) ); i_96: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(6) ); i_97: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(5) ); i_98: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(4) ); i_99: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => s_level_out_bus_d3(3) ); s_level_out_d1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg_0, CE => '1', D => wr_err_c, Q => s_level_out_d1_aurora_64b66b_0_cdc_to, R => cbcc_fifo_reset_rd_clk ); s_level_out_d2_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg_0, CE => '1', D => s_level_out_d1_aurora_64b66b_0_cdc_to, Q => s_level_out_d2, R => cbcc_fifo_reset_rd_clk ); s_level_out_d3_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg_0, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => cbcc_fifo_reset_rd_clk ); s_level_out_d4_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg_0, CE => '1', D => s_level_out_d3, Q => s_level_out_d4, R => cbcc_fifo_reset_rd_clk ); s_level_out_d5_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg_0, CE => '1', D => s_level_out_d4, Q => s_level_out_d5, R => cbcc_fifo_reset_rd_clk ); s_level_out_d6_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg_0, CE => '1', D => s_level_out_d5, Q => s_level_out_d6, R => cbcc_fifo_reset_rd_clk ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_common_logic_cbcc is port ( cb_bit_err_out : out STD_LOGIC; in0 : out STD_LOGIC; master_do_rd_en_i : out STD_LOGIC; all_vld_btf_flag_i : out STD_LOGIC; cbcc_fifo_reset_wr_clk : in STD_LOGIC; \out\ : in STD_LOGIC; all_vld_btf_out_reg_0 : in STD_LOGIC; START_CB_WRITES_OUT : in STD_LOGIC; cbcc_fifo_reset_rd_clk : in STD_LOGIC; master_do_rd_en_out_reg_0 : in STD_LOGIC; master_do_rd_en_out_reg_1 : in STD_LOGIC; ANY_VLD_BTF_FLAG : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_common_logic_cbcc; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_common_logic_cbcc is signal second_cb_write_failed : STD_LOGIC; begin all_start_cb_writes_out_reg: unisim.vcomponents.FDRE port map ( C => all_vld_btf_out_reg_0, CE => '1', D => START_CB_WRITES_OUT, Q => in0, R => cbcc_fifo_reset_wr_clk ); all_vld_btf_out_reg: unisim.vcomponents.FDRE port map ( C => all_vld_btf_out_reg_0, CE => '1', D => ANY_VLD_BTF_FLAG, Q => all_vld_btf_flag_i, R => cbcc_fifo_reset_wr_clk ); cb_bit_err_out_reg: unisim.vcomponents.FDRE port map ( C => all_vld_btf_out_reg_0, CE => '1', D => second_cb_write_failed, Q => cb_bit_err_out, R => cbcc_fifo_reset_wr_clk ); master_do_rd_en_out_reg: unisim.vcomponents.FDRE port map ( C => master_do_rd_en_out_reg_1, CE => '1', D => master_do_rd_en_out_reg_0, Q => master_do_rd_en_i, R => cbcc_fifo_reset_rd_clk ); second_cb_write_failed_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => all_vld_btf_out_reg_0, CE => '1', D => \out\, Q => second_cb_write_failed, R => cbcc_fifo_reset_wr_clk ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_common_wrapper is port ( gt_qpllclk_quad1_out : out STD_LOGIC; gt_qpllrefclk_quad1_out : out STD_LOGIC; drp_clk_in : in STD_LOGIC; refclk1_in : in STD_LOGIC; \out\ : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_common_wrapper; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_common_wrapper is signal gtxe2_common_i_n_0 : STD_LOGIC; signal gtxe2_common_i_n_10 : STD_LOGIC; signal gtxe2_common_i_n_11 : STD_LOGIC; signal gtxe2_common_i_n_12 : STD_LOGIC; signal gtxe2_common_i_n_13 : STD_LOGIC; signal gtxe2_common_i_n_14 : STD_LOGIC; signal gtxe2_common_i_n_15 : STD_LOGIC; signal gtxe2_common_i_n_16 : STD_LOGIC; signal gtxe2_common_i_n_17 : STD_LOGIC; signal gtxe2_common_i_n_18 : STD_LOGIC; signal gtxe2_common_i_n_19 : STD_LOGIC; signal gtxe2_common_i_n_2 : STD_LOGIC; signal gtxe2_common_i_n_20 : STD_LOGIC; signal gtxe2_common_i_n_21 : STD_LOGIC; signal gtxe2_common_i_n_22 : STD_LOGIC; signal gtxe2_common_i_n_5 : STD_LOGIC; signal gtxe2_common_i_n_7 : STD_LOGIC; signal gtxe2_common_i_n_8 : STD_LOGIC; signal gtxe2_common_i_n_9 : STD_LOGIC; signal NLW_gtxe2_common_i_QPLLFBCLKLOST_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_common_i_REFCLKOUTMONITOR_UNCONNECTED : STD_LOGIC; signal NLW_gtxe2_common_i_QPLLDMONITOR_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); attribute BOX_TYPE : string; attribute BOX_TYPE of gtxe2_common_i : label is "PRIMITIVE"; begin gtxe2_common_i: unisim.vcomponents.GTXE2_COMMON generic map( BIAS_CFG => X"0000040000001000", COMMON_CFG => X"00000000", IS_DRPCLK_INVERTED => '0', IS_GTGREFCLK_INVERTED => '0', IS_QPLLLOCKDETCLK_INVERTED => '0', QPLL_CFG => X"06801C1", QPLL_CLKOUT_CFG => B"0000", QPLL_COARSE_FREQ_OVRD => B"010000", QPLL_COARSE_FREQ_OVRD_EN => '0', QPLL_CP => B"0000011111", QPLL_CP_MONITOR_EN => '0', QPLL_DMONITOR_SEL => '0', QPLL_FBDIV => B"0000100000", QPLL_FBDIV_MONITOR_EN => '0', QPLL_FBDIV_RATIO => '1', QPLL_INIT_CFG => X"000006", QPLL_LOCK_CFG => X"21E8", QPLL_LPF => B"1111", QPLL_REFCLK_DIV => 1, SIM_QPLLREFCLK_SEL => B"001", SIM_RESET_SPEEDUP => "TRUE", SIM_VERSION => "4.0" ) port map ( BGBYPASSB => '1', BGMONITORENB => '1', BGPDB => '1', BGRCALOVRD(4 downto 0) => B"11111", DRPADDR(7 downto 0) => B"00000000", DRPCLK => drp_clk_in, DRPDI(15 downto 0) => B"0000000000000000", DRPDO(15) => gtxe2_common_i_n_7, DRPDO(14) => gtxe2_common_i_n_8, DRPDO(13) => gtxe2_common_i_n_9, DRPDO(12) => gtxe2_common_i_n_10, DRPDO(11) => gtxe2_common_i_n_11, DRPDO(10) => gtxe2_common_i_n_12, DRPDO(9) => gtxe2_common_i_n_13, DRPDO(8) => gtxe2_common_i_n_14, DRPDO(7) => gtxe2_common_i_n_15, DRPDO(6) => gtxe2_common_i_n_16, DRPDO(5) => gtxe2_common_i_n_17, DRPDO(4) => gtxe2_common_i_n_18, DRPDO(3) => gtxe2_common_i_n_19, DRPDO(2) => gtxe2_common_i_n_20, DRPDO(1) => gtxe2_common_i_n_21, DRPDO(0) => gtxe2_common_i_n_22, DRPEN => '0', DRPRDY => gtxe2_common_i_n_0, DRPWE => '0', GTGREFCLK => '0', GTNORTHREFCLK0 => '0', GTNORTHREFCLK1 => '0', GTREFCLK0 => refclk1_in, GTREFCLK1 => '0', GTSOUTHREFCLK0 => '0', GTSOUTHREFCLK1 => '0', PMARSVD(7 downto 0) => B"00000000", QPLLDMONITOR(7 downto 0) => NLW_gtxe2_common_i_QPLLDMONITOR_UNCONNECTED(7 downto 0), QPLLFBCLKLOST => NLW_gtxe2_common_i_QPLLFBCLKLOST_UNCONNECTED, QPLLLOCK => gtxe2_common_i_n_2, QPLLLOCKDETCLK => \out\, QPLLLOCKEN => '1', QPLLOUTCLK => gt_qpllclk_quad1_out, QPLLOUTREFCLK => gt_qpllrefclk_quad1_out, QPLLOUTRESET => '0', QPLLPD => '1', QPLLREFCLKLOST => gtxe2_common_i_n_5, QPLLREFCLKSEL(2 downto 0) => B"001", QPLLRESET => '0', QPLLRSVD1(15 downto 0) => B"0000000000000000", QPLLRSVD2(4 downto 0) => B"11111", RCALENB => '1', REFCLKOUTMONITOR => NLW_gtxe2_common_i_REFCLKOUTMONITOR_UNCONNECTED ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync is port ( D : out STD_LOGIC_VECTOR ( 0 to 0 ); pma_init : in STD_LOGIC; \out\ : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => pma_init, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg4_reg_n_0, Q => D(0), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_0 is port ( D : out STD_LOGIC_VECTOR ( 0 to 0 ); reset_pb : in STD_LOGIC; \out\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_0 : entity is "aurora_64b66b_0_rst_sync"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_0; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_0 is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => reset_pb, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg3, Q => stg4, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg4, Q => D(0), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_1 is port ( SS : out STD_LOGIC_VECTOR ( 0 to 0 ); in0 : in STD_LOGIC; \out\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_1 : entity is "aurora_64b66b_0_rst_sync"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_1; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_1 is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => in0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg4_reg_n_0, Q => SS(0), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_2 is port ( link_reset_sync : out STD_LOGIC; link_reset_out : in STD_LOGIC; \out\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_2 : entity is "aurora_64b66b_0_rst_sync"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_2; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_2 is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => link_reset_out, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg4_reg_n_0, Q => link_reset_sync, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_22 is port ( rx_reset_r3 : out STD_LOGIC; in0 : in STD_LOGIC; stg5_reg_0 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_22 : entity is "aurora_64b66b_0_rst_sync"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_22; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_22 is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg5_reg_0, CE => '1', D => in0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg5_reg_0, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg5_reg_0, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg5_reg_0, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg5_reg_0, CE => '1', D => stg4_reg_n_0, Q => rx_reset_r3, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_24 is port ( stg5_reg_0 : out STD_LOGIC; SR : in STD_LOGIC_VECTOR ( 0 to 0 ); stg4_reg_0 : in STD_LOGIC; rx_reset_r3 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_24 : entity is "aurora_64b66b_0_rst_sync"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_24; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_24 is signal reset_r3 : STD_LOGIC; signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin FABRIC_PCS_RESET_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => reset_r3, I1 => rx_reset_r3, O => stg5_reg_0 ); stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg4_reg_0, CE => '1', D => SR(0), Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg4_reg_0, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg4_reg_0, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg4_reg_0, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg4_reg_0, CE => '1', D => stg4_reg_n_0, Q => reset_r3, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_3 is port ( power_down_sync : out STD_LOGIC; power_down : in STD_LOGIC; \out\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_3 : entity is "aurora_64b66b_0_rst_sync"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_3; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_3 is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => power_down, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg4_reg_n_0, Q => power_down_sync, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_4 is port ( fsm_resetdone_sync : out STD_LOGIC; stg1_aurora_64b66b_0_cdc_to_reg_0 : in STD_LOGIC; \out\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_4 : entity is "aurora_64b66b_0_rst_sync"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_4; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_4 is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg1_aurora_64b66b_0_cdc_to_reg_0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg4_reg_n_0, Q => fsm_resetdone_sync, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_5 is port ( stg5_reg_0 : out STD_LOGIC; TX_HEADER_1_reg : out STD_LOGIC; stg5_reg_1 : out STD_LOGIC; stg5_reg_2 : out STD_LOGIC; stg5_reg_3 : out STD_LOGIC; stg5_reg_4 : out STD_LOGIC; stg5_reg_5 : out STD_LOGIC; stg1_aurora_64b66b_0_cdc_to_reg_0 : in STD_LOGIC; \out\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 1 downto 0 ); txdatavalid_symgen_i : in STD_LOGIC; gen_na_idles_i : in STD_LOGIC; tx_pe_data_v_i : in STD_LOGIC; TX_HEADER_1_reg_0 : in STD_LOGIC; channel_up_tx_if : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 3 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_5 : entity is "aurora_64b66b_0_rst_sync"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_5; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_5 is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; signal \^stg5_reg_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \TX_DATA[59]_i_1\ : label is "soft_lutpair93"; attribute SOFT_HLUTNM of \TX_DATA[60]_i_1\ : label is "soft_lutpair93"; attribute SOFT_HLUTNM of \TX_DATA[61]_i_1\ : label is "soft_lutpair94"; attribute SOFT_HLUTNM of \TX_DATA[62]_i_2\ : label is "soft_lutpair94"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin stg5_reg_0 <= \^stg5_reg_0\; \TX_DATA[59]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"40" ) port map ( I0 => \^stg5_reg_0\, I1 => channel_up_tx_if, I2 => Q(0), O => stg5_reg_2 ); \TX_DATA[60]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"40" ) port map ( I0 => \^stg5_reg_0\, I1 => channel_up_tx_if, I2 => Q(1), O => stg5_reg_3 ); \TX_DATA[61]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"40" ) port map ( I0 => \^stg5_reg_0\, I1 => channel_up_tx_if, I2 => Q(2), O => stg5_reg_4 ); \TX_DATA[62]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"40" ) port map ( I0 => \^stg5_reg_0\, I1 => channel_up_tx_if, I2 => Q(3), O => stg5_reg_5 ); TX_HEADER_0_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0000050044444444" ) port map ( I0 => \^stg5_reg_0\, I1 => D(0), I2 => TX_HEADER_1_reg_0, I3 => tx_pe_data_v_i, I4 => gen_na_idles_i, I5 => txdatavalid_symgen_i, O => stg5_reg_1 ); TX_HEADER_1_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"00000000EEEEE2EE" ) port map ( I0 => D(1), I1 => txdatavalid_symgen_i, I2 => gen_na_idles_i, I3 => tx_pe_data_v_i, I4 => TX_HEADER_1_reg_0, I5 => \^stg5_reg_0\, O => TX_HEADER_1_reg ); stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg1_aurora_64b66b_0_cdc_to_reg_0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg4_reg_n_0, Q => \^stg5_reg_0\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0\ is port ( \FSM_onehot_cdr_reset_fsm_r_reg[2]\ : out STD_LOGIC; \FSM_onehot_cdr_reset_fsm_r_reg[2]_0\ : out STD_LOGIC; \FSM_onehot_cdr_reset_fsm_r_reg[0]\ : out STD_LOGIC; in0 : in STD_LOGIC; stg4_reg_0 : in STD_LOGIC; allow_block_sync_propagation : in STD_LOGIC; \FSM_onehot_cdr_reset_fsm_r_reg[2]_1\ : in STD_LOGIC; \FSM_onehot_cdr_reset_fsm_r_reg[2]_2\ : in STD_LOGIC; cdr_reset_fsm_lnkreset : in STD_LOGIC; p_2_in : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0\ is signal blocksync_all_lanes_instableclk : STD_LOGIC; signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin \FSM_onehot_cdr_reset_fsm_r[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF00020202" ) port map ( I0 => \FSM_onehot_cdr_reset_fsm_r_reg[2]_1\, I1 => allow_block_sync_propagation, I2 => blocksync_all_lanes_instableclk, I3 => \FSM_onehot_cdr_reset_fsm_r_reg[2]_2\, I4 => cdr_reset_fsm_lnkreset, I5 => p_2_in, O => \FSM_onehot_cdr_reset_fsm_r_reg[0]\ ); \FSM_onehot_cdr_reset_fsm_r[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"00000000CCDDC8C8" ) port map ( I0 => allow_block_sync_propagation, I1 => \FSM_onehot_cdr_reset_fsm_r_reg[2]_1\, I2 => blocksync_all_lanes_instableclk, I3 => \FSM_onehot_cdr_reset_fsm_r_reg[2]_2\, I4 => cdr_reset_fsm_lnkreset, I5 => p_2_in, O => \FSM_onehot_cdr_reset_fsm_r_reg[2]_0\ ); \FSM_onehot_cdr_reset_fsm_r[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"00000000FFEAAAAA" ) port map ( I0 => allow_block_sync_propagation, I1 => \FSM_onehot_cdr_reset_fsm_r_reg[2]_1\, I2 => blocksync_all_lanes_instableclk, I3 => \FSM_onehot_cdr_reset_fsm_r_reg[2]_2\, I4 => cdr_reset_fsm_lnkreset, I5 => p_2_in, O => \FSM_onehot_cdr_reset_fsm_r_reg[2]\ ); stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg4_reg_0, CE => '1', D => in0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg4_reg_0, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg4_reg_0, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg4_reg_0, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg4_reg_0, CE => '1', D => stg4_reg_n_0, Q => blocksync_all_lanes_instableclk, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_10\ is port ( SR : out STD_LOGIC_VECTOR ( 0 to 0 ); in0 : in STD_LOGIC; \out\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_10\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_10\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_10\ is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => in0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg4_reg_n_0, Q => SR(0), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_11\ is port ( reset_initclk : out STD_LOGIC; stg5_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 ); SR : in STD_LOGIC_VECTOR ( 0 to 0 ); stg5_reg_1 : in STD_LOGIC; \out\ : in STD_LOGIC; \hard_err_cntr_r_reg[7]\ : in STD_LOGIC; \hard_err_cntr_r_reg[7]_0\ : in STD_LOGIC; \hard_err_cntr_r_reg[7]_1\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_11\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_11\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_11\ is signal \^reset_initclk\ : STD_LOGIC; signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin reset_initclk <= \^reset_initclk\; \hard_err_cntr_r[7]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFF45" ) port map ( I0 => \out\, I1 => \^reset_initclk\, I2 => \hard_err_cntr_r_reg[7]\, I3 => \hard_err_cntr_r_reg[7]_0\, I4 => \hard_err_cntr_r_reg[7]_1\, O => stg5_reg_0(0) ); stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg5_reg_1, CE => '1', D => SR(0), Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg5_reg_1, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg5_reg_1, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg5_reg_1, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg5_reg_1, CE => '1', D => stg4_reg_n_0, Q => \^reset_initclk\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_12\ is port ( in0 : out STD_LOGIC; stg1_aurora_64b66b_0_cdc_to_reg_0 : in STD_LOGIC; stg4_reg_0 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_12\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_12\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_12\ is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg4_reg_0, CE => '1', D => stg1_aurora_64b66b_0_cdc_to_reg_0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg4_reg_0, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg4_reg_0, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg4_reg_0, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg4_reg_0, CE => '1', D => stg4_reg_n_0, Q => in0, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_27\ is port ( stg5_reg_0 : out STD_LOGIC; in0 : in STD_LOGIC; \out\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_27\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_27\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_27\ is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => in0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg4_reg_n_0, Q => stg5_reg_0, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_28\ is port ( stg5_reg_0 : out STD_LOGIC; stg1_aurora_64b66b_0_cdc_to_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 ); \out\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_28\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_28\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_28\ is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg1_aurora_64b66b_0_cdc_to_reg_0(0), Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg4_reg_n_0, Q => stg5_reg_0, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_29\ is port ( stg5_reg_0 : out STD_LOGIC; in0 : in STD_LOGIC; stg5_reg_1 : in STD_LOGIC; stg1_aurora_64b66b_0_cdc_to_reg_0 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_29\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_29\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_29\ is signal fifo_reset_wr_sync3 : STD_LOGIC; signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin prmry_in_inferred_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => fifo_reset_wr_sync3, I1 => stg1_aurora_64b66b_0_cdc_to_reg_0, O => stg5_reg_0 ); stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg5_reg_1, CE => '1', D => in0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg5_reg_1, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg5_reg_1, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg5_reg_1, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg5_reg_1, CE => '1', D => stg4_reg_n_0, Q => fifo_reset_wr_sync3, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_30\ is port ( stg3_reg_0 : out STD_LOGIC; in0 : in STD_LOGIC; \out\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_30\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_30\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_30\ is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute srl_name : string; attribute srl_name of stg5_reg_srl2 : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/common_reset_cbcc_i/u_rst_sync_reset_rd_clk/stg5_reg_srl2 "; begin stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => in0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg2, Q => stg3, R => '0' ); stg5_reg_srl2: unisim.vcomponents.SRL16E generic map( INIT => X"0003" ) port map ( A0 => '1', A1 => '0', A2 => '0', A3 => '0', CE => '1', CLK => \out\, D => stg3, Q => stg3_reg_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_32\ is port ( stg3_reg_0 : out STD_LOGIC; in0 : in STD_LOGIC; stg2_reg_0 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_32\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_32\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_32\ is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute srl_name : string; attribute srl_name of stg5_reg_srl2 : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/common_reset_cbcc_i/u_rst_sync_reset_wr_clk/stg5_reg_srl2 "; begin stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg2_reg_0, CE => '1', D => in0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg2_reg_0, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg2_reg_0, CE => '1', D => stg2, Q => stg3, R => '0' ); stg5_reg_srl2: unisim.vcomponents.SRL16E generic map( INIT => X"0003" ) port map ( A0 => '1', A1 => '0', A2 => '0', A3 => '0', CE => '1', CLK => stg2_reg_0, D => stg3, Q => stg3_reg_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_33\ is port ( stg5_reg_0 : out STD_LOGIC; rd_stg1_reg : out STD_LOGIC; stg1_aurora_64b66b_0_cdc_to_reg_0 : in STD_LOGIC; \out\ : in STD_LOGIC; rd_stg1 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_33\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_33\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_33\ is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; signal \^stg5_reg_0\ : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin stg5_reg_0 <= \^stg5_reg_0\; cbcc_reset_cbstg2_rd_clk_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => rd_stg1, I1 => \^stg5_reg_0\, O => rd_stg1_reg ); stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg1_aurora_64b66b_0_cdc_to_reg_0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg4_reg_n_0, Q => \^stg5_reg_0\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_36\ is port ( stg3_reg_0 : out STD_LOGIC; in0 : in STD_LOGIC; stg3_reg_1 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_36\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_36\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_36\ is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute srl_name : string; attribute srl_name of stg5_reg_srl2 : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/u_rst_sync_btf_sync/stg5_reg_srl2 "; begin stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg3_reg_1, CE => '1', D => in0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg3_reg_1, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg3_reg_1, CE => '1', D => stg2, Q => stg3, R => '0' ); stg5_reg_srl2: unisim.vcomponents.SRL16E generic map( INIT => X"0003" ) port map ( A0 => '1', A1 => '0', A2 => '0', A3 => '0', CE => '1', CLK => stg3_reg_1, D => stg3, Q => stg3_reg_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_8\ is port ( rxlossofsync_out_i : out STD_LOGIC; stg1_aurora_64b66b_0_cdc_to_reg_0 : in STD_LOGIC; \out\ : in STD_LOGIC; blocksync_out_i : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_8\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_8\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_8\ is signal allow_block_sync_propagation_inrxclk : STD_LOGIC; signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin rxlossofsync_out_q_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => allow_block_sync_propagation_inrxclk, I1 => blocksync_out_i, O => rxlossofsync_out_i ); stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg1_aurora_64b66b_0_cdc_to_reg_0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg4_reg_n_0, Q => allow_block_sync_propagation_inrxclk, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_9\ is port ( fsm_resetdone_to_new_gtx_rx_comb : out STD_LOGIC; stg1_aurora_64b66b_0_cdc_to_reg_0 : in STD_LOGIC; \out\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_9\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_9\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_9\ is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg1_aurora_64b66b_0_cdc_to_reg_0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg4_reg_n_0, Q => fsm_resetdone_to_new_gtx_rx_comb, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1\ is port ( \tx_state_reg[6]\ : out STD_LOGIC; stg5_reg_0 : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 0 to 0 ); init_wait_done_reg : out STD_LOGIC; \tx_state_reg[1]\ : out STD_LOGIC; \tx_state_reg[7]\ : out STD_LOGIC; \out\ : in STD_LOGIC; stg5_reg_1 : in STD_LOGIC; reset_time_out_reg : in STD_LOGIC_VECTOR ( 6 downto 0 ); reset_time_out_reg_0 : in STD_LOGIC; reset_time_out : in STD_LOGIC; \tx_state_reg[3]\ : in STD_LOGIC; time_out_2ms : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 4 downto 0 ); \tx_state_reg[3]_0\ : in STD_LOGIC; reset_time_out_reg_1 : in STD_LOGIC; reset_time_out_reg_2 : in STD_LOGIC; reset_time_out_reg_3 : in STD_LOGIC; reset_time_out_reg_4 : in STD_LOGIC; sel : in STD_LOGIC; \tx_state_reg[0]\ : in STD_LOGIC; \tx_state_reg[0]_0\ : in STD_LOGIC; \tx_state_reg[0]_1\ : in STD_LOGIC; init_wait_done : in STD_LOGIC; \tx_state_reg[3]_1\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1\ is signal reset_time_out_i_2_n_0 : STD_LOGIC; signal reset_time_out_i_4_n_0 : STD_LOGIC; signal reset_time_out_i_5_n_0 : STD_LOGIC; signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; signal stg5_reg_n_0 : STD_LOGIC; signal \tx_state[0]_i_2_n_0\ : STD_LOGIC; signal \tx_state[0]_i_5_n_0\ : STD_LOGIC; signal \^tx_state_reg[1]\ : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \tx_state[0]_i_5\ : label is "soft_lutpair61"; attribute SOFT_HLUTNM of \tx_state[5]_i_7\ : label is "soft_lutpair61"; begin \tx_state_reg[1]\ <= \^tx_state_reg[1]\; reset_time_out_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FEFFFEFE02000202" ) port map ( I0 => reset_time_out_i_2_n_0, I1 => reset_time_out_reg(5), I2 => reset_time_out_reg(6), I3 => reset_time_out_reg_0, I4 => reset_time_out_i_4_n_0, I5 => reset_time_out, O => \tx_state_reg[6]\ ); reset_time_out_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000000045450045" ) port map ( I0 => reset_time_out_i_5_n_0, I1 => reset_time_out_reg_1, I2 => reset_time_out_reg(3), I3 => reset_time_out_reg(2), I4 => reset_time_out_reg_2, I5 => reset_time_out_reg_3, O => reset_time_out_i_2_n_0 ); reset_time_out_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFCFDFC" ) port map ( I0 => stg5_reg_n_0, I1 => reset_time_out_reg(4), I2 => reset_time_out_reg(2), I3 => reset_time_out_reg(1), I4 => reset_time_out_reg(0), I5 => reset_time_out_reg_4, O => reset_time_out_i_4_n_0 ); reset_time_out_i_5: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => reset_time_out_reg(1), I1 => stg5_reg_n_0, O => reset_time_out_i_5_n_0 ); stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_1, CE => '1', D => \out\, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_1, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_1, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_1, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_1, CE => '1', D => stg4_reg_n_0, Q => stg5_reg_n_0, R => '0' ); \tx_state[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFF8F8FFF8" ) port map ( I0 => Q(0), I1 => sel, I2 => \tx_state[0]_i_2_n_0\, I3 => \tx_state_reg[0]\, I4 => \tx_state_reg[0]_0\, I5 => \tx_state_reg[0]_1\, O => D(0) ); \tx_state[0]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"00002320" ) port map ( I0 => init_wait_done, I1 => \tx_state_reg[3]_0\, I2 => \tx_state_reg[3]\, I3 => \tx_state[0]_i_5_n_0\, I4 => \tx_state_reg[3]_1\, O => \tx_state[0]_i_2_n_0\ ); \tx_state[0]_i_5\: unisim.vcomponents.LUT3 generic map( INIT => X"BA" ) port map ( I0 => time_out_2ms, I1 => stg5_reg_n_0, I2 => Q(0), O => \tx_state[0]_i_5_n_0\ ); \tx_state[1]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"55555455" ) port map ( I0 => \tx_state_reg[3]\, I1 => stg5_reg_n_0, I2 => time_out_2ms, I3 => Q(1), I4 => \tx_state_reg[3]_0\, O => stg5_reg_0 ); \tx_state[5]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"0000000D" ) port map ( I0 => \tx_state_reg[3]\, I1 => init_wait_done, I2 => \tx_state_reg[3]_0\, I3 => \^tx_state_reg[1]\, I4 => \tx_state_reg[3]_1\, O => init_wait_done_reg ); \tx_state[5]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"000E" ) port map ( I0 => Q(1), I1 => Q(3), I2 => time_out_2ms, I3 => stg5_reg_n_0, O => \^tx_state_reg[1]\ ); \tx_state[6]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFEFFFF" ) port map ( I0 => Q(4), I1 => Q(2), I2 => Q(0), I3 => Q(3), I4 => stg5_reg_n_0, I5 => time_out_2ms, O => \tx_state_reg[7]\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_13\ is port ( stg5_reg_0 : out STD_LOGIC; clear : out STD_LOGIC; in0 : in STD_LOGIC; stg4_reg_0 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_13\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_13\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_13\ is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; signal \^stg5_reg_0\ : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin stg5_reg_0 <= \^stg5_reg_0\; stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => '1', D => in0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => '1', D => stg4_reg_n_0, Q => \^stg5_reg_0\, R => '0' ); \wait_bypass_count[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^stg5_reg_0\, O => clear ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_14\ is port ( D : out STD_LOGIC_VECTOR ( 5 downto 0 ); stg5_reg_0 : out STD_LOGIC; \tx_state_reg[7]\ : out STD_LOGIC; in0 : in STD_LOGIC; stg4_reg_0 : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 6 downto 0 ); \tx_state_reg[1]\ : in STD_LOGIC; \tx_state_reg[1]_0\ : in STD_LOGIC; \tx_state_reg[1]_1\ : in STD_LOGIC; \tx_state_reg[1]_2\ : in STD_LOGIC; \tx_state_reg[1]_3\ : in STD_LOGIC; \tx_state_reg[2]\ : in STD_LOGIC; \tx_state_reg[2]_0\ : in STD_LOGIC; \tx_state_reg[2]_1\ : in STD_LOGIC; \tx_state_reg[2]_2\ : in STD_LOGIC; \tx_state_reg[2]_3\ : in STD_LOGIC; \tx_state_reg[2]_4\ : in STD_LOGIC; \tx_state_reg[2]_5\ : in STD_LOGIC; \tx_state_reg[2]_6\ : in STD_LOGIC; \tx_state_reg[2]_7\ : in STD_LOGIC; \tx_state_reg[6]\ : in STD_LOGIC; sel : in STD_LOGIC; \tx_state_reg[6]_0\ : in STD_LOGIC; \tx_state_reg[4]\ : in STD_LOGIC; \tx_state_reg[5]\ : in STD_LOGIC; \tx_state_reg[5]_0\ : in STD_LOGIC; \tx_state_reg[5]_1\ : in STD_LOGIC; \tx_state_reg[5]_2\ : in STD_LOGIC; \tx_state_reg[7]_0\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_14\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_14\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_14\ is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; signal \^stg5_reg_0\ : STD_LOGIC; signal stg5_reg_n_0 : STD_LOGIC; signal \tx_state[1]_i_2_n_0\ : STD_LOGIC; signal \tx_state[2]_i_3_n_0\ : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin stg5_reg_0 <= \^stg5_reg_0\; stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => '1', D => in0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => '1', D => stg4_reg_n_0, Q => stg5_reg_n_0, R => '0' ); \tx_state[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"C0C0E0E0C0CFEFEF" ) port map ( I0 => \tx_state[1]_i_2_n_0\, I1 => \tx_state_reg[1]\, I2 => \tx_state_reg[1]_0\, I3 => \tx_state_reg[1]_1\, I4 => \tx_state_reg[1]_2\, I5 => \tx_state_reg[1]_3\, O => D(0) ); \tx_state[1]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"0001FFFF" ) port map ( I0 => Q(5), I1 => Q(1), I2 => Q(3), I3 => Q(2), I4 => stg5_reg_n_0, O => \tx_state[1]_i_2_n_0\ ); \tx_state[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"005D005D0000005D" ) port map ( I0 => \tx_state_reg[2]\, I1 => \tx_state_reg[2]_0\, I2 => \tx_state[2]_i_3_n_0\, I3 => \tx_state_reg[2]_1\, I4 => \tx_state_reg[2]_2\, I5 => \tx_state_reg[2]_3\, O => D(1) ); \tx_state[2]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"00020000AAAAAAAA" ) port map ( I0 => \tx_state_reg[1]_0\, I1 => \tx_state_reg[2]_4\, I2 => \tx_state_reg[2]_5\, I3 => \tx_state_reg[2]_6\, I4 => \tx_state_reg[2]_7\, I5 => \tx_state[1]_i_2_n_0\, O => \tx_state[2]_i_3_n_0\ ); \tx_state[3]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"0000FFFE" ) port map ( I0 => Q(6), I1 => Q(3), I2 => Q(5), I3 => Q(0), I4 => stg5_reg_n_0, O => \tx_state_reg[7]\ ); \tx_state[4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"00000000F7FF5555" ) port map ( I0 => \tx_state_reg[2]\, I1 => \tx_state_reg[1]_0\, I2 => \tx_state_reg[6]\, I3 => stg5_reg_n_0, I4 => sel, I5 => \tx_state_reg[4]\, O => D(2) ); \tx_state[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0003000200000002" ) port map ( I0 => \tx_state_reg[5]\, I1 => \^stg5_reg_0\, I2 => \tx_state_reg[5]_0\, I3 => \tx_state_reg[5]_1\, I4 => \tx_state_reg[5]_2\, I5 => Q(4), O => D(3) ); \tx_state[5]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"0800" ) port map ( I0 => \tx_state_reg[2]\, I1 => \tx_state_reg[1]_0\, I2 => \tx_state_reg[6]\, I3 => stg5_reg_n_0, O => \^stg5_reg_0\ ); \tx_state[6]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"4700000047030303" ) port map ( I0 => stg5_reg_n_0, I1 => \tx_state_reg[1]_0\, I2 => \tx_state_reg[6]\, I3 => Q(5), I4 => sel, I5 => \tx_state_reg[6]_0\, O => D(4) ); \tx_state[7]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"A200FF0000000000" ) port map ( I0 => sel, I1 => stg5_reg_n_0, I2 => \tx_state_reg[6]\, I3 => \tx_state_reg[1]_0\, I4 => \tx_state_reg[2]\, I5 => \tx_state_reg[7]_0\, O => D(5) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_15\ is port ( time_out_wait_bypass_reg : out STD_LOGIC; stg5_reg_0 : out STD_LOGIC; stg1_aurora_64b66b_0_cdc_to_reg_0 : in STD_LOGIC; stg4_reg_0 : in STD_LOGIC; in0 : in STD_LOGIC; time_out_wait_bypass_reg_0 : in STD_LOGIC; time_out_wait_bypass_reg_1 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_15\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_15\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_15\ is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; signal stg5_reg_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \time_out_wait_bypass_i_1__0\ : label is "soft_lutpair62"; attribute SOFT_HLUTNM of \wait_bypass_count[0]_i_2\ : label is "soft_lutpair62"; begin stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => '1', D => stg1_aurora_64b66b_0_cdc_to_reg_0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => '1', D => stg4_reg_n_0, Q => stg5_reg_n_0, R => '0' ); \time_out_wait_bypass_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"AB00" ) port map ( I0 => in0, I1 => time_out_wait_bypass_reg_0, I2 => stg5_reg_n_0, I3 => time_out_wait_bypass_reg_1, O => time_out_wait_bypass_reg ); \wait_bypass_count[0]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => time_out_wait_bypass_reg_0, I1 => stg5_reg_n_0, O => stg5_reg_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_16\ is port ( stg5_reg_0 : out STD_LOGIC; \out\ : in STD_LOGIC; stg4_reg_0 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_16\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_16\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_16\ is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => '1', D => \out\, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => '1', D => stg4_reg_n_0, Q => stg5_reg_0, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_17\ is port ( stg5_reg_0 : out STD_LOGIC; mmcm_lock_r2_reg : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 0 to 0 ); \tx_state_reg[3]\ : out STD_LOGIC; time_out_500us_reg : out STD_LOGIC; \tx_state_reg[4]\ : out STD_LOGIC; stg5_reg_1 : out STD_LOGIC; stg1_aurora_64b66b_0_cdc_to_reg_0 : in STD_LOGIC; stg5_reg_2 : in STD_LOGIC; \tx_state_reg[2]\ : in STD_LOGIC; \tx_state_reg[3]_0\ : in STD_LOGIC; \tx_state_reg[2]_0\ : in STD_LOGIC; \out\ : in STD_LOGIC; \tx_state_reg[5]\ : in STD_LOGIC; \tx_state_reg[3]_1\ : in STD_LOGIC; \tx_state_reg[3]_2\ : in STD_LOGIC; \tx_state_reg[3]_3\ : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 3 downto 0 ); \tx_state_reg[2]_1\ : in STD_LOGIC; \tx_state_reg[2]_2\ : in STD_LOGIC; time_out_500us : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_17\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_17\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_17\ is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; signal \^stg5_reg_0\ : STD_LOGIC; signal \tx_state[3]_i_2_n_0\ : STD_LOGIC; signal \tx_state[5]_i_8_n_0\ : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \tx_state[1]_i_3\ : label is "soft_lutpair63"; attribute SOFT_HLUTNM of \tx_state[3]_i_2\ : label is "soft_lutpair63"; begin stg5_reg_0 <= \^stg5_reg_0\; stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_2, CE => '1', D => stg1_aurora_64b66b_0_cdc_to_reg_0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_2, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_2, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_2, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_2, CE => '1', D => stg4_reg_n_0, Q => \^stg5_reg_0\, R => '0' ); \tx_state[0]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF0045FFFF" ) port map ( I0 => time_out_500us, I1 => \^stg5_reg_0\, I2 => Q(0), I3 => \tx_state_reg[2]_0\, I4 => \tx_state_reg[3]_0\, I5 => \tx_state_reg[2]\, O => time_out_500us_reg ); \tx_state[1]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"0004" ) port map ( I0 => \^stg5_reg_0\, I1 => Q(1), I2 => time_out_500us, I3 => \tx_state_reg[2]\, O => stg5_reg_1 ); \tx_state[2]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"000000004F004FFF" ) port map ( I0 => \tx_state_reg[2]_0\, I1 => \tx_state[5]_i_8_n_0\, I2 => \tx_state_reg[2]_1\, I3 => \tx_state_reg[3]_0\, I4 => \tx_state_reg[2]_2\, I5 => \tx_state_reg[2]\, O => \tx_state_reg[3]\ ); \tx_state[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0E0A0F00000A0000" ) port map ( I0 => \tx_state[3]_i_2_n_0\, I1 => \tx_state_reg[3]_1\, I2 => \tx_state_reg[3]_2\, I3 => \tx_state_reg[3]_3\, I4 => \tx_state_reg[3]_0\, I5 => Q(2), O => D(0) ); \tx_state[3]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"AAAB" ) port map ( I0 => \tx_state_reg[2]_0\, I1 => \^stg5_reg_0\, I2 => time_out_500us, I3 => \tx_state_reg[2]\, O => \tx_state[3]_i_2_n_0\ ); \tx_state[4]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF5F515F5F" ) port map ( I0 => Q(3), I1 => \^stg5_reg_0\, I2 => \tx_state_reg[2]\, I3 => time_out_500us, I4 => \tx_state_reg[3]_0\, I5 => \tx_state_reg[2]_0\, O => \tx_state_reg[4]\ ); \tx_state[5]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"4444440440404000" ) port map ( I0 => \tx_state_reg[2]\, I1 => \tx_state_reg[3]_0\, I2 => \tx_state_reg[2]_0\, I3 => \out\, I4 => \tx_state_reg[5]\, I5 => \tx_state[5]_i_8_n_0\, O => mmcm_lock_r2_reg ); \tx_state[5]_i_8\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^stg5_reg_0\, I1 => time_out_500us, O => \tx_state[5]_i_8_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_18\ is port ( stg5_reg_0 : out STD_LOGIC; \rx_state_reg[3]\ : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 1 downto 0 ); stg4_reg_0 : in STD_LOGIC; reset_time_out_reg : in STD_LOGIC; \out\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); reset_time_out_reg_0 : in STD_LOGIC; reset_time_out_reg_1 : in STD_LOGIC; reset_time_out_reg_2 : in STD_LOGIC; reset_time_out_reg_3 : in STD_LOGIC; reset_time_out_reg_4 : in STD_LOGIC; reset_time_out_reg_5 : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); \rx_state_reg[4]\ : in STD_LOGIC; \rx_state_reg[4]_0\ : in STD_LOGIC; \rx_state_reg[4]_1\ : in STD_LOGIC; time_tlock_max : in STD_LOGIC; \rx_state_reg[4]_2\ : in STD_LOGIC; \rx_state_reg[4]_3\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_18\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_18\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_18\ is signal n_0_0 : STD_LOGIC; signal \reset_time_out_i_2__0_n_0\ : STD_LOGIC; signal \rx_state[4]_i_2_n_0\ : STD_LOGIC; signal \rx_state[5]_i_2_n_0\ : STD_LOGIC; signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; signal \^stg5_reg_0\ : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin stg5_reg_0 <= \^stg5_reg_0\; i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '1', O => n_0_0 ); \reset_time_out_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"BBBABBBB888A8888" ) port map ( I0 => \reset_time_out_i_2__0_n_0\, I1 => reset_time_out_reg, I2 => \out\(1), I3 => reset_time_out_reg_0, I4 => reset_time_out_reg_1, I5 => reset_time_out_reg_2, O => \rx_state_reg[3]\ ); \reset_time_out_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"000000000000D0DD" ) port map ( I0 => \out\(0), I1 => reset_time_out_reg_3, I2 => \^stg5_reg_0\, I3 => \out\(1), I4 => reset_time_out_reg_4, I5 => reset_time_out_reg_5, O => \reset_time_out_i_2__0_n_0\ ); \rx_state[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"8888888B" ) port map ( I0 => Q(0), I1 => Q(2), I2 => \rx_state_reg[4]\, I3 => \rx_state[4]_i_2_n_0\, I4 => \rx_state_reg[4]_0\, O => D(0) ); \rx_state[4]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"DDDDDFDFDD00DFDF" ) port map ( I0 => \rx_state_reg[4]_1\, I1 => time_tlock_max, I2 => \^stg5_reg_0\, I3 => \rx_state_reg[4]_2\, I4 => Q(0), I5 => \rx_state_reg[4]_3\, O => \rx_state[4]_i_2_n_0\ ); \rx_state[5]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"8888888B" ) port map ( I0 => Q(1), I1 => Q(2), I2 => \rx_state_reg[4]\, I3 => \rx_state[5]_i_2_n_0\, I4 => \rx_state_reg[4]_0\, O => D(1) ); \rx_state[5]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"EFE0FFF0EFE0FFFF" ) port map ( I0 => time_tlock_max, I1 => \^stg5_reg_0\, I2 => \rx_state_reg[4]_1\, I3 => \rx_state_reg[4]_3\, I4 => Q(1), I5 => \rx_state_reg[4]_2\, O => \rx_state[5]_i_2_n_0\ ); stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => '1', D => n_0_0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => '1', D => stg4_reg_n_0, Q => \^stg5_reg_0\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_19\ is port ( stg5_reg_0 : out STD_LOGIC; stg5_reg_1 : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 2 downto 0 ); \out\ : in STD_LOGIC; stg4_reg_0 : in STD_LOGIC; \reset_time_out_i_2__0\ : in STD_LOGIC_VECTOR ( 1 downto 0 ); \reset_time_out_i_2__0_0\ : in STD_LOGIC; \rx_state_reg[3]\ : in STD_LOGIC; \rx_state_reg[3]_0\ : in STD_LOGIC; \rx_state_reg[1]\ : in STD_LOGIC; \rx_state_reg[1]_0\ : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 3 downto 0 ); \rx_state_reg[1]_1\ : in STD_LOGIC; \rx_state_reg[2]\ : in STD_LOGIC; \rx_state_reg[0]\ : in STD_LOGIC; \rx_state_reg[0]_0\ : in STD_LOGIC; \rx_state_reg[0]_1\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_19\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_19\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_19\ is signal \rx_state[0]_i_3_n_0\ : STD_LOGIC; signal \rx_state[1]_i_2_n_0\ : STD_LOGIC; signal \rx_state[2]_i_2_n_0\ : STD_LOGIC; signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; signal stg5_reg_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin \reset_time_out_i_7__0\: unisim.vcomponents.LUT4 generic map( INIT => X"4F44" ) port map ( I0 => stg5_reg_n_0, I1 => \reset_time_out_i_2__0\(1), I2 => \reset_time_out_i_2__0_0\, I3 => \reset_time_out_i_2__0\(0), O => stg5_reg_0 ); \rx_state[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"BBBBBBB8" ) port map ( I0 => Q(0), I1 => Q(3), I2 => \rx_state_reg[0]\, I3 => \rx_state[0]_i_3_n_0\, I4 => \rx_state_reg[0]_0\, O => D(0) ); \rx_state[0]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"88880080A8A8A0A0" ) port map ( I0 => \rx_state_reg[0]_1\, I1 => \rx_state_reg[3]\, I2 => Q(0), I3 => stg5_reg_n_0, I4 => \rx_state_reg[3]_0\, I5 => \rx_state_reg[2]\, O => \rx_state[0]_i_3_n_0\ ); \rx_state[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"B3BFB3B3A0A0A0A0" ) port map ( I0 => Q(1), I1 => \rx_state[1]_i_2_n_0\, I2 => Q(3), I3 => \rx_state_reg[1]\, I4 => \rx_state_reg[1]_1\, I5 => \rx_state_reg[1]_0\, O => D(1) ); \rx_state[1]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"FFF3BBBB" ) port map ( I0 => \rx_state_reg[2]\, I1 => Q(1), I2 => \rx_state_reg[3]_0\, I3 => stg5_reg_n_0, I4 => \rx_state_reg[3]\, O => \rx_state[1]_i_2_n_0\ ); \rx_state[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"8F888888" ) port map ( I0 => Q(3), I1 => Q(2), I2 => \rx_state[2]_i_2_n_0\, I3 => \rx_state_reg[1]_0\, I4 => \rx_state_reg[1]\, O => D(2) ); \rx_state[2]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"DDDDD0DDDDDDDDDD" ) port map ( I0 => Q(2), I1 => \rx_state_reg[2]\, I2 => \rx_state_reg[3]_0\, I3 => stg5_reg_n_0, I4 => Q(3), I5 => \rx_state_reg[3]\, O => \rx_state[2]_i_2_n_0\ ); \rx_state[3]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"A8FFFFFF" ) port map ( I0 => \rx_state_reg[3]\, I1 => stg5_reg_n_0, I2 => \rx_state_reg[3]_0\, I3 => \rx_state_reg[1]\, I4 => \rx_state_reg[1]_0\, O => stg5_reg_1 ); stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => '1', D => \out\, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => '1', D => stg4_reg_n_0, Q => stg5_reg_n_0, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_20\ is port ( SR : out STD_LOGIC; in0 : in STD_LOGIC; stg5_reg_0 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_20\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_20\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_20\ is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; signal stg5_reg_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => '1', D => in0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => '1', D => stg4_reg_n_0, Q => stg5_reg_n_0, R => '0' ); time_out_wait_bypass_i_1: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => stg5_reg_n_0, O => SR ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_21\ is port ( stg5_reg_0 : out STD_LOGIC; stg5_reg_1 : out STD_LOGIC; stg1_aurora_64b66b_0_cdc_to_reg_0 : in STD_LOGIC; stg5_reg_2 : in STD_LOGIC; \wait_bypass_count_reg[0]\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_21\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_21\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_21\ is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; signal stg5_reg_n_0 : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of time_out_wait_bypass_i_2 : label is "soft_lutpair35"; attribute SOFT_HLUTNM of \wait_bypass_count[0]_i_1__0\ : label is "soft_lutpair35"; begin stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_2, CE => '1', D => stg1_aurora_64b66b_0_cdc_to_reg_0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_2, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_2, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_2, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_2, CE => '1', D => stg4_reg_n_0, Q => stg5_reg_n_0, R => '0' ); time_out_wait_bypass_i_2: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => stg5_reg_n_0, O => stg5_reg_0 ); \wait_bypass_count[0]_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \wait_bypass_count_reg[0]\, I1 => stg5_reg_n_0, O => stg5_reg_1 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_23\ is port ( stg5_reg_0 : out STD_LOGIC; time_tlock_max_reg : out STD_LOGIC; \rx_state_reg[5]\ : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 0 to 0 ); stg1_aurora_64b66b_0_cdc_to_reg_0 : in STD_LOGIC; stg4_reg_0 : in STD_LOGIC; \rx_state_reg[0]\ : in STD_LOGIC; \rx_state_reg[3]\ : in STD_LOGIC; time_tlock_max : in STD_LOGIC; \rx_state_reg[0]_0\ : in STD_LOGIC; \rx_state_reg[0]_1\ : in STD_LOGIC; \rx_state_reg[3]_0\ : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 2 downto 0 ); \out\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); \rx_state_reg[3]_1\ : in STD_LOGIC; \rx_state_reg[3]_2\ : in STD_LOGIC; \rx_state_reg[3]_3\ : in STD_LOGIC; \rx_state_reg[3]_4\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_23\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_23\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_23\ is signal \rx_state[0]_i_6_n_0\ : STD_LOGIC; signal \rx_state[3]_i_2_n_0\ : STD_LOGIC; signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; signal \^stg5_reg_0\ : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin stg5_reg_0 <= \^stg5_reg_0\; \reset_time_out_i_6__0\: unisim.vcomponents.LUT4 generic map( INIT => X"4F44" ) port map ( I0 => \out\(1), I1 => \out\(2), I2 => \^stg5_reg_0\, I3 => \out\(0), O => \rx_state_reg[5]\ ); \rx_state[0]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"5050510100005101" ) port map ( I0 => \rx_state_reg[0]\, I1 => \rx_state[0]_i_6_n_0\, I2 => \rx_state_reg[3]\, I3 => time_tlock_max, I4 => \rx_state_reg[0]_0\, I5 => \rx_state_reg[0]_1\, O => time_tlock_max_reg ); \rx_state[0]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"45" ) port map ( I0 => \rx_state_reg[3]_0\, I1 => \^stg5_reg_0\, I2 => Q(0), O => \rx_state[0]_i_6_n_0\ ); \rx_state[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F070F070F073F070" ) port map ( I0 => \rx_state[3]_i_2_n_0\, I1 => \rx_state_reg[3]_1\, I2 => Q(1), I3 => Q(2), I4 => \rx_state_reg[3]_2\, I5 => \rx_state_reg[3]\, O => D(0) ); \rx_state[3]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFEFFFEFFFEF0FE" ) port map ( I0 => \rx_state_reg[3]_0\, I1 => \^stg5_reg_0\, I2 => \rx_state_reg[3]_3\, I3 => \rx_state_reg[3]\, I4 => \rx_state_reg[3]_4\, I5 => time_tlock_max, O => \rx_state[3]_i_2_n_0\ ); stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => '1', D => stg1_aurora_64b66b_0_cdc_to_reg_0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => '1', D => stg4_reg_n_0, Q => \^stg5_reg_0\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_25\ is port ( stg5_reg_0 : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 0 to 0 ); \out\ : in STD_LOGIC; stg4_reg_0 : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); \rx_state_reg[6]\ : in STD_LOGIC; \rx_state_reg[6]_0\ : in STD_LOGIC; \rx_state_reg[6]_1\ : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_25\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_25\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_25\ is signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg4_reg_n_0 : STD_LOGIC; signal \^stg5_reg_0\ : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; attribute shift_extract of stg4_reg : label is "{no}"; attribute shift_extract of stg5_reg : label is "{no}"; begin stg5_reg_0 <= \^stg5_reg_0\; \rx_state[6]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"888888888B888888" ) port map ( I0 => Q(0), I1 => Q(1), I2 => \^stg5_reg_0\, I3 => \rx_state_reg[6]\, I4 => \rx_state_reg[6]_0\, I5 => \rx_state_reg[6]_1\, O => D(0) ); stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => '1', D => \out\, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => '1', D => stg2, Q => stg3, R => '0' ); stg4_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => '1', D => stg3, Q => stg4_reg_n_0, R => '0' ); stg5_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => '1', D => stg4_reg_n_0, Q => \^stg5_reg_0\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized2\ is port ( stg11_reg_0 : out STD_LOGIC; in0 : in STD_LOGIC; stg11_reg_1 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized2\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized2\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized2\ is signal stg10_reg_srl7_n_0 : STD_LOGIC; signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; attribute srl_name : string; attribute srl_name of stg10_reg_srl7 : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/common_reset_cbcc_i/u_rst_sync_fifo_reset_user_clk/stg10_reg_srl7 "; attribute shift_extract of stg11_reg : label is "{no}"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; begin stg10_reg_srl7: unisim.vcomponents.SRL16E generic map( INIT => X"007F" ) port map ( A0 => '0', A1 => '1', A2 => '1', A3 => '0', CE => '1', CLK => stg11_reg_1, D => stg3, Q => stg10_reg_srl7_n_0 ); stg11_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg11_reg_1, CE => '1', D => stg10_reg_srl7_n_0, Q => stg11_reg_0, R => '0' ); stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg11_reg_1, CE => '1', D => in0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg11_reg_1, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg11_reg_1, CE => '1', D => stg2, Q => stg3, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized3\ is port ( cbcc_fifo_reset_to_fifo_rd_clk : out STD_LOGIC; cbcc_fifo_reset_to_fifo_rd_clk_dlyd_reg : out STD_LOGIC; stg1_aurora_64b66b_0_cdc_to_reg_0 : in STD_LOGIC; \out\ : in STD_LOGIC; cbcc_fifo_reset_to_fifo_rd_clk_dlyd : in STD_LOGIC; in0 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized3\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized3\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized3\ is signal \^cbcc_fifo_reset_to_fifo_rd_clk\ : STD_LOGIC; signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg30_reg_srl27_n_0 : STD_LOGIC; signal NLW_stg30_reg_srl27_Q31_UNCONNECTED : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute srl_name : string; attribute srl_name of stg30_reg_srl27 : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/common_reset_cbcc_i/u_rst_sync_reset_to_fifo_rd_clk/stg30_reg_srl27 "; attribute shift_extract of stg31_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; begin cbcc_fifo_reset_to_fifo_rd_clk <= \^cbcc_fifo_reset_to_fifo_rd_clk\; cbc_rd_if_reset_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"FFD0" ) port map ( I0 => cbcc_fifo_reset_to_fifo_rd_clk_dlyd, I1 => \^cbcc_fifo_reset_to_fifo_rd_clk\, I2 => in0, I3 => stg1_aurora_64b66b_0_cdc_to_reg_0, O => cbcc_fifo_reset_to_fifo_rd_clk_dlyd_reg ); stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg1_aurora_64b66b_0_cdc_to_reg_0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg30_reg_srl27: unisim.vcomponents.SRLC32E generic map( INIT => X"07FFFFFF" ) port map ( A(4 downto 0) => B"11010", CE => '1', CLK => \out\, D => stg3, Q => stg30_reg_srl27_n_0, Q31 => NLW_stg30_reg_srl27_Q31_UNCONNECTED ); stg31_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg30_reg_srl27_n_0, Q => \^cbcc_fifo_reset_to_fifo_rd_clk\, R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => stg2, Q => stg3, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized3_31\ is port ( SR : out STD_LOGIC_VECTOR ( 0 to 0 ); cbcc_fifo_reset_to_fifo_wr_clk_dlyd_reg : out STD_LOGIC; stg1_aurora_64b66b_0_cdc_to_reg_0 : in STD_LOGIC; stg31_reg_0 : in STD_LOGIC; cbcc_fifo_reset_to_fifo_wr_clk_dlyd : in STD_LOGIC; in0 : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized3_31\ : entity is "aurora_64b66b_0_rst_sync"; end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized3_31\; architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized3_31\ is signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal stg1_aurora_64b66b_0_cdc_to : STD_LOGIC; attribute async_reg : string; attribute async_reg of stg1_aurora_64b66b_0_cdc_to : signal is "true"; attribute shift_extract : string; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to : signal is "{no}"; signal stg2 : STD_LOGIC; attribute async_reg of stg2 : signal is "true"; attribute shift_extract of stg2 : signal is "{no}"; signal stg3 : STD_LOGIC; attribute async_reg of stg3 : signal is "true"; attribute shift_extract of stg3 : signal is "{no}"; signal stg30_reg_srl27_n_0 : STD_LOGIC; signal NLW_stg30_reg_srl27_Q31_UNCONNECTED : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of stg1_aurora_64b66b_0_cdc_to_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of stg1_aurora_64b66b_0_cdc_to_reg : label is "yes"; attribute shift_extract of stg1_aurora_64b66b_0_cdc_to_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg2_reg : label is std.standard.true; attribute KEEP of stg2_reg : label is "yes"; attribute shift_extract of stg2_reg : label is "{no}"; attribute srl_name : string; attribute srl_name of stg30_reg_srl27 : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/common_reset_cbcc_i/u_rst_sync_reset_to_fifo_wr_clk/stg30_reg_srl27 "; attribute shift_extract of stg31_reg : label is "{no}"; attribute ASYNC_REG_boolean of stg3_reg : label is std.standard.true; attribute KEEP of stg3_reg : label is "yes"; attribute shift_extract of stg3_reg : label is "{no}"; begin SR(0) <= \^sr\(0); cbc_wr_if_reset_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"FFD0" ) port map ( I0 => cbcc_fifo_reset_to_fifo_wr_clk_dlyd, I1 => \^sr\(0), I2 => in0, I3 => stg1_aurora_64b66b_0_cdc_to_reg_0, O => cbcc_fifo_reset_to_fifo_wr_clk_dlyd_reg ); stg1_aurora_64b66b_0_cdc_to_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg31_reg_0, CE => '1', D => stg1_aurora_64b66b_0_cdc_to_reg_0, Q => stg1_aurora_64b66b_0_cdc_to, R => '0' ); stg2_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg31_reg_0, CE => '1', D => stg1_aurora_64b66b_0_cdc_to, Q => stg2, R => '0' ); stg30_reg_srl27: unisim.vcomponents.SRLC32E generic map( INIT => X"07FFFFFF" ) port map ( A(4 downto 0) => B"11010", CE => '1', CLK => stg31_reg_0, D => stg3, Q => stg30_reg_srl27_n_0, Q31 => NLW_stg30_reg_srl27_Q31_UNCONNECTED ); stg31_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg31_reg_0, CE => '1', D => stg30_reg_srl27_n_0, Q => \^sr\(0), R => '0' ); stg3_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg31_reg_0, CE => '1', D => stg2, Q => stg3, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_CLOCK_CORRECTION_CHANNEL_BONDING is port ( master_do_rd_en_out_reg : out STD_LOGIC_VECTOR ( 65 downto 0 ); do_rd_en_i : out STD_LOGIC; CC_detect_dlyd1 : out STD_LOGIC; CB_detect_dlyd0p5 : out STD_LOGIC; rx_lossofsync_i : out STD_LOGIC; final_gater_for_fifo_din_i : out STD_LOGIC; bit_err_chan_bond_i : out STD_LOGIC; START_CB_WRITES_OUT : out STD_LOGIC; ANY_VLD_BTF_FLAG : out STD_LOGIC; allow_block_sync_propagation_reg : out STD_LOGIC; p_2_in : out STD_LOGIC; cdr_reset_fsm_lnkreset_reg : out STD_LOGIC; hold_reg_reg_0 : out STD_LOGIC; ILLEGAL_BTF_reg : out STD_LOGIC; rxdatavalid_i : out STD_LOGIC; wr_err_rd_clk_sync_reg_0 : out STD_LOGIC; hard_err_usr0 : out STD_LOGIC; rxfsm_reset_i : out STD_LOGIC; LINK_RESET_OUT0 : out STD_LOGIC; in0 : in STD_LOGIC; rxdatavalid_to_fifo_i : in STD_LOGIC; \out\ : in STD_LOGIC; s_level_out_d6_reg : in STD_LOGIC; master_do_rd_en_q_reg_0 : in STD_LOGIC; cbcc_fifo_reset_to_fifo_rd_clk : in STD_LOGIC; UNSCRAMBLED_DATA_OUT : in STD_LOGIC_VECTOR ( 31 downto 0 ); Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); cbcc_fifo_reset_rd_clk : in STD_LOGIC; stg3_reg : in STD_LOGIC; cbcc_reset_cbstg2_rd_clk : in STD_LOGIC; cbcc_fifo_reset_wr_clk : in STD_LOGIC; CC_detect : in STD_LOGIC; CB_detect0 : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 1 downto 0 ); CC_RXLOSSOFSYNC_OUT_reg_0 : in STD_LOGIC; allow_block_sync_propagation_reg_0 : in STD_LOGIC; allow_block_sync_propagation : in STD_LOGIC; allow_block_sync_propagation_reg_1 : in STD_LOGIC; cdr_reset_fsm_lnkreset : in STD_LOGIC; \rx_state_reg[7]\ : in STD_LOGIC; do_wr_en_reg_0 : in STD_LOGIC; START_CB_WRITES_OUT_reg_0 : in STD_LOGIC; illegal_btf_i : in STD_LOGIC; enable_err_detect_i : in STD_LOGIC; HARD_ERR_reg : in STD_LOGIC; TXBUFSTATUS : in STD_LOGIC_VECTOR ( 0 to 0 ); hard_err_usr_reg : in STD_LOGIC; channel_up_tx_if : in STD_LOGIC; \rx_state_reg[7]_0\ : in STD_LOGIC; hard_err_rst_int : in STD_LOGIC; \count_for_reset_r_reg[0]_0\ : in STD_LOGIC; reset_initclk : in STD_LOGIC; AR : in STD_LOGIC_VECTOR ( 0 to 0 ); SR : in STD_LOGIC_VECTOR ( 0 to 0 ); \valid_btf_detect_extend_r_reg[4]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_CLOCK_CORRECTION_CHANNEL_BONDING; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_CLOCK_CORRECTION_CHANNEL_BONDING is signal \^any_vld_btf_flag\ : STD_LOGIC; signal ANY_VLD_BTF_FLAG_i_1_n_0 : STD_LOGIC; signal \^cb_detect_dlyd0p5\ : STD_LOGIC; signal CB_detect_dlyd1 : STD_LOGIC; signal CB_detect_dlyd10 : STD_LOGIC; signal CB_detect_dlyd1p0 : STD_LOGIC; signal CC_detect_pulse_r : STD_LOGIC; signal FINAL_GATER_FOR_FIFO_DIN_i_1_n_0 : STD_LOGIC; signal \FIRST_CB_BITERR_CB_RESET_OUT1__15\ : STD_LOGIC; signal FIRST_CB_BITERR_CB_RESET_OUT_i_1_n_0 : STD_LOGIC; signal FIRST_CB_BITERR_CB_RESET_OUT_i_2_n_0 : STD_LOGIC; signal FIRST_CB_BITERR_CB_RESET_OUT_i_4_n_0 : STD_LOGIC; signal FIRST_CB_BITERR_CB_RESET_OUT_i_5_n_0 : STD_LOGIC; signal FIRST_CB_BITERR_CB_RESET_OUT_i_6_n_0 : STD_LOGIC; signal FIRST_CB_BITERR_CB_RESET_OUT_i_7_n_0 : STD_LOGIC; signal \LINK_RESET[0]_i_2_n_0\ : STD_LOGIC; signal \LINK_RESET[0]_i_3_n_0\ : STD_LOGIC; signal \LINK_RESET[0]_i_4_n_0\ : STD_LOGIC; signal \LINK_RESET[0]_i_5_n_0\ : STD_LOGIC; signal \LINK_RESET[0]_i_6_n_0\ : STD_LOGIC; signal \LINK_RESET[0]_i_7_n_0\ : STD_LOGIC; signal \LINK_RESET[0]_i_8_n_0\ : STD_LOGIC; signal \LINK_RESET[0]_i_9_n_0\ : STD_LOGIC; signal SOFT_ERR_i_2_n_0 : STD_LOGIC; signal \^start_cb_writes_out\ : STD_LOGIC; signal START_CB_WRITES_OUT_i_1_n_0 : STD_LOGIC; signal any_vld_btf_fifo_din_detect : STD_LOGIC; signal any_vld_btf_fifo_din_detect_dlyd : STD_LOGIC; signal any_vld_btf_fifo_din_detect_dlyd_i_1_n_0 : STD_LOGIC; signal any_vld_btf_fifo_din_detect_dlyd_i_3_n_0 : STD_LOGIC; signal any_vld_btf_fifo_din_detect_dlyd_i_4_n_0 : STD_LOGIC; signal any_vld_btf_fifo_din_detect_dlyd_i_5_n_0 : STD_LOGIC; signal bit80_prsnt : STD_LOGIC; signal \^bit_err_chan_bond_i\ : STD_LOGIC; signal buffer_too_empty_c : STD_LOGIC; signal cb_fifo_din_detect_q : STD_LOGIC; signal \count_for_reset_r[0]_i_1_n_0\ : STD_LOGIC; signal \count_for_reset_r[0]_i_3_n_0\ : STD_LOGIC; signal count_for_reset_r_reg : STD_LOGIC_VECTOR ( 23 downto 0 ); signal \count_for_reset_r_reg[0]_i_2_n_0\ : STD_LOGIC; signal \count_for_reset_r_reg[0]_i_2_n_1\ : STD_LOGIC; signal \count_for_reset_r_reg[0]_i_2_n_2\ : STD_LOGIC; signal \count_for_reset_r_reg[0]_i_2_n_3\ : STD_LOGIC; signal \count_for_reset_r_reg[0]_i_2_n_4\ : STD_LOGIC; signal \count_for_reset_r_reg[0]_i_2_n_5\ : STD_LOGIC; signal \count_for_reset_r_reg[0]_i_2_n_6\ : STD_LOGIC; signal \count_for_reset_r_reg[0]_i_2_n_7\ : STD_LOGIC; signal \count_for_reset_r_reg[12]_i_1_n_0\ : STD_LOGIC; signal \count_for_reset_r_reg[12]_i_1_n_1\ : STD_LOGIC; signal \count_for_reset_r_reg[12]_i_1_n_2\ : STD_LOGIC; signal \count_for_reset_r_reg[12]_i_1_n_3\ : STD_LOGIC; signal \count_for_reset_r_reg[12]_i_1_n_4\ : STD_LOGIC; signal \count_for_reset_r_reg[12]_i_1_n_5\ : STD_LOGIC; signal \count_for_reset_r_reg[12]_i_1_n_6\ : STD_LOGIC; signal \count_for_reset_r_reg[12]_i_1_n_7\ : STD_LOGIC; signal \count_for_reset_r_reg[16]_i_1_n_0\ : STD_LOGIC; signal \count_for_reset_r_reg[16]_i_1_n_1\ : STD_LOGIC; signal \count_for_reset_r_reg[16]_i_1_n_2\ : STD_LOGIC; signal \count_for_reset_r_reg[16]_i_1_n_3\ : STD_LOGIC; signal \count_for_reset_r_reg[16]_i_1_n_4\ : STD_LOGIC; signal \count_for_reset_r_reg[16]_i_1_n_5\ : STD_LOGIC; signal \count_for_reset_r_reg[16]_i_1_n_6\ : STD_LOGIC; signal \count_for_reset_r_reg[16]_i_1_n_7\ : STD_LOGIC; signal \count_for_reset_r_reg[20]_i_1_n_1\ : STD_LOGIC; signal \count_for_reset_r_reg[20]_i_1_n_2\ : STD_LOGIC; signal \count_for_reset_r_reg[20]_i_1_n_3\ : STD_LOGIC; signal \count_for_reset_r_reg[20]_i_1_n_4\ : STD_LOGIC; signal \count_for_reset_r_reg[20]_i_1_n_5\ : STD_LOGIC; signal \count_for_reset_r_reg[20]_i_1_n_6\ : STD_LOGIC; signal \count_for_reset_r_reg[20]_i_1_n_7\ : STD_LOGIC; signal \count_for_reset_r_reg[4]_i_1_n_0\ : STD_LOGIC; signal \count_for_reset_r_reg[4]_i_1_n_1\ : STD_LOGIC; signal \count_for_reset_r_reg[4]_i_1_n_2\ : STD_LOGIC; signal \count_for_reset_r_reg[4]_i_1_n_3\ : STD_LOGIC; signal \count_for_reset_r_reg[4]_i_1_n_4\ : STD_LOGIC; signal \count_for_reset_r_reg[4]_i_1_n_5\ : STD_LOGIC; signal \count_for_reset_r_reg[4]_i_1_n_6\ : STD_LOGIC; signal \count_for_reset_r_reg[4]_i_1_n_7\ : STD_LOGIC; signal \count_for_reset_r_reg[8]_i_1_n_0\ : STD_LOGIC; signal \count_for_reset_r_reg[8]_i_1_n_1\ : STD_LOGIC; signal \count_for_reset_r_reg[8]_i_1_n_2\ : STD_LOGIC; signal \count_for_reset_r_reg[8]_i_1_n_3\ : STD_LOGIC; signal \count_for_reset_r_reg[8]_i_1_n_4\ : STD_LOGIC; signal \count_for_reset_r_reg[8]_i_1_n_5\ : STD_LOGIC; signal \count_for_reset_r_reg[8]_i_1_n_6\ : STD_LOGIC; signal \count_for_reset_r_reg[8]_i_1_n_7\ : STD_LOGIC; signal do_rd_en : STD_LOGIC; signal \^do_rd_en_i\ : STD_LOGIC; signal do_wr_en : STD_LOGIC; signal do_wr_en_i_1_n_0 : STD_LOGIC; signal do_wr_en_i_2_n_0 : STD_LOGIC; signal en32_fifo_din_i : STD_LOGIC_VECTOR ( 79 downto 0 ); signal fifo_dout_i : STD_LOGIC_VECTOR ( 68 to 68 ); signal \^final_gater_for_fifo_din_i\ : STD_LOGIC; signal first_cb_to_write_to_fifo : STD_LOGIC; signal first_cb_to_write_to_fifo_dlyd : STD_LOGIC; signal first_cb_to_write_to_fifo_dlyd_i_2_n_0 : STD_LOGIC; signal first_cb_to_write_to_fifo_dlyd_i_3_n_0 : STD_LOGIC; signal first_cb_to_write_to_fifo_dlyd_i_4_n_0 : STD_LOGIC; signal hold_reg : STD_LOGIC; signal hold_reg_i_1_n_0 : STD_LOGIC; signal link_reset_0 : STD_LOGIC; signal link_reset_0_c : STD_LOGIC; signal \^master_do_rd_en_out_reg\ : STD_LOGIC_VECTOR ( 65 downto 0 ); signal master_do_rd_en_q : STD_LOGIC; signal mod_do_wr_en : STD_LOGIC; signal new_do_wr_en : STD_LOGIC; signal new_do_wr_en_i_1_n_0 : STD_LOGIC; signal new_underflow_flag_c0 : STD_LOGIC; signal new_underflow_flag_c_reg_inv_n_0 : STD_LOGIC; signal overflow_flag_c : STD_LOGIC; signal p_0_in0_in : STD_LOGIC; signal \p_0_in__6\ : STD_LOGIC_VECTOR ( 4 downto 0 ); signal p_1_in : STD_LOGIC; signal \^p_2_in\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[0]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[10]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[11]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[12]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[13]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[14]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[15]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[16]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[17]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[18]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[19]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[1]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[20]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[21]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[22]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[23]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[24]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[25]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[26]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[27]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[28]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[29]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[2]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[30]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[31]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[32]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[33]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[3]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[4]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[5]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[6]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[7]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[8]\ : STD_LOGIC; signal \raw_data_r_r_reg_n_0_[9]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[0]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[10]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[11]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[12]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[13]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[14]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[15]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[16]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[17]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[18]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[19]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[1]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[20]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[21]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[22]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[23]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[24]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[25]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[26]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[27]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[28]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[29]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[2]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[30]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[31]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[32]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[33]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[3]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[4]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[5]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[6]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[7]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[8]\ : STD_LOGIC; signal \raw_data_r_reg_n_0_[9]\ : STD_LOGIC; signal raw_data_srl_out : STD_LOGIC_VECTOR ( 34 downto 0 ); signal rd_err_c : STD_LOGIC; signal rd_err_pre : STD_LOGIC; signal rxbuferr_out_i : STD_LOGIC_VECTOR ( 1 downto 0 ); signal rxdatavalid_lookahead_i : STD_LOGIC; signal u_cdc_rxlossofsync_in_n_0 : STD_LOGIC; signal u_rst_sync_btf_sync_n_0 : STD_LOGIC; signal underflow_flag_c : STD_LOGIC; signal underflow_flag_r1 : STD_LOGIC; signal underflow_flag_r10 : STD_LOGIC; signal underflow_flag_r2 : STD_LOGIC; signal underflow_flag_r3 : STD_LOGIC; signal valid_btf_detect : STD_LOGIC; signal valid_btf_detect_dlyd1 : STD_LOGIC; signal valid_btf_detect_extend_r : STD_LOGIC_VECTOR ( 4 downto 0 ); signal valid_btf_detect_extend_r2 : STD_LOGIC; signal valid_btf_detect_extend_r20_n_0 : STD_LOGIC; signal wait_for_rd_en : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \wait_for_rd_en[0]_i_1_n_0\ : STD_LOGIC; signal \wait_for_rd_en[1]_i_1_n_0\ : STD_LOGIC; signal \wait_for_rd_en[2]_i_1_n_0\ : STD_LOGIC; signal wait_for_wr_en : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \wait_for_wr_en[0]_i_1_n_0\ : STD_LOGIC; signal \wait_for_wr_en[1]_i_1_n_0\ : STD_LOGIC; signal \wait_for_wr_en_wr3_reg[0]_srl3_n_0\ : STD_LOGIC; signal \wait_for_wr_en_wr3_reg[1]_srl3_n_0\ : STD_LOGIC; signal wait_for_wr_en_wr4 : STD_LOGIC_VECTOR ( 1 downto 0 ); signal wdth_conv_1stage : STD_LOGIC_VECTOR ( 39 downto 0 ); signal wdth_conv_2stage : STD_LOGIC_VECTOR ( 39 downto 32 ); signal \wdth_conv_count[0]_i_1_n_0\ : STD_LOGIC; signal \wdth_conv_count[0]_i_2_n_0\ : STD_LOGIC; signal \wdth_conv_count[1]_i_1_n_0\ : STD_LOGIC; signal \wdth_conv_count[1]_i_2_n_0\ : STD_LOGIC; signal \wdth_conv_count_reg_n_0_[0]\ : STD_LOGIC; signal wr_err_c : STD_LOGIC; signal wr_err_rd_clk_pre : STD_LOGIC; signal wr_monitor_flag : STD_LOGIC; signal \wr_monitor_flag_reg__0\ : STD_LOGIC_VECTOR ( 4 downto 0 ); signal NLW_SRLC32E_inst_4_Q31_UNCONNECTED : STD_LOGIC; signal \NLW_count_for_reset_r_reg[20]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); signal NLW_data_fifo_ALMOSTFULL_UNCONNECTED : STD_LOGIC; signal NLW_data_fifo_DBITERR_UNCONNECTED : STD_LOGIC; signal NLW_data_fifo_SBITERR_UNCONNECTED : STD_LOGIC; signal NLW_data_fifo_DOP_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 2 ); signal NLW_data_fifo_ECCPARITY_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_data_fifo_RDCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 12 downto 0 ); signal NLW_data_fifo_WRCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 12 downto 0 ); signal \NLW_srlc32e[0].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[10].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[11].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[12].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[13].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[14].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[15].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[16].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[17].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[18].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[19].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[1].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[20].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[21].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[22].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[23].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[24].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[25].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[26].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[27].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[28].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[29].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[2].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[30].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[31].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[32].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[33].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[34].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[3].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[4].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[5].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[6].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[7].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[8].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; signal \NLW_srlc32e[9].SRLC32E_inst_1_Q31_UNCONNECTED\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of FINAL_GATER_FOR_FIFO_DIN_i_1 : label is "soft_lutpair9"; attribute SOFT_HLUTNM of FIRST_CB_BITERR_CB_RESET_OUT_i_2 : label is "soft_lutpair6"; attribute SOFT_HLUTNM of FIRST_CB_BITERR_CB_RESET_OUT_i_4 : label is "soft_lutpair6"; attribute SOFT_HLUTNM of \LINK_RESET[0]_i_7\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \LINK_RESET[0]_i_9\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of RXDATAVALID_IN_REG_i_1 : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \RX_DATA_REG[63]_i_1\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of SOFT_ERR_i_1 : label is "soft_lutpair8"; attribute SOFT_HLUTNM of SOFT_ERR_i_2 : label is "soft_lutpair15"; attribute BOX_TYPE : string; attribute BOX_TYPE of SRLC32E_inst_4 : label is "PRIMITIVE"; attribute srl_name : string; attribute srl_name of SRLC32E_inst_4 : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/SRLC32E_inst_4 "; attribute SOFT_HLUTNM of \cdr_reset_fsm_cntr_r[7]_i_1\ : label is "soft_lutpair13"; attribute BOX_TYPE of data_fifo : label is "PRIMITIVE"; attribute SOFT_HLUTNM of do_wr_en_i_2 : label is "soft_lutpair9"; attribute shift_extract : string; attribute shift_extract of master_do_rd_en_q_reg : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[0]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[10]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[11]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[12]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[13]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[14]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[15]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[16]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[17]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[18]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[19]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[1]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[20]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[21]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[22]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[23]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[24]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[25]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[26]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[27]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[28]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[29]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[2]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[30]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[31]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[32]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[33]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[34]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[3]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[4]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[5]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[6]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[7]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[8]\ : label is "{no}"; attribute shift_extract of \raw_data_r_r_reg[9]\ : label is "{no}"; attribute shift_extract of \raw_data_r_reg[0]\ : label is "{no}"; attribute shift_extract of \raw_data_r_reg[10]\ : label is "{no}"; attribute shift_extract of \raw_data_r_reg[11]\ : label is "{no}"; attribute shift_extract of \raw_data_r_reg[12]\ : label is "{no}"; attribute shift_extract of \raw_data_r_reg[13]\ : label is "{no}"; attribute shift_extract of \raw_data_r_reg[14]\ : label is "{no}"; attribute shift_extract of \raw_data_r_reg[15]\ : label is "{no}"; attribute shift_extract of \raw_data_r_reg[16]\ : label is "{no}"; attribute shift_extract of \raw_data_r_reg[17]\ : label is "{no}"; attribute shift_extract of \raw_data_r_reg[18]\ : label is "{no}"; attribute shift_extract of \raw_data_r_reg[19]\ : label is "{no}"; attribute shift_extract of \raw_data_r_reg[1]\ : label is "{no}"; attribute shift_extract of \raw_data_r_reg[20]\ : label is "{no}"; attribute shift_extract of \raw_data_r_reg[21]\ : label is "{no}"; attribute shift_extract of \raw_data_r_reg[22]\ : label is "{no}"; attribute shift_extract of \raw_data_r_reg[23]\ : label is "{no}"; attribute shift_extract of \raw_data_r_reg[24]\ : label is "{no}"; attribute shift_extract of \raw_data_r_reg[25]\ : label is "{no}"; attribute shift_extract of \raw_data_r_reg[26]\ : label is "{no}"; attribute shift_extract of \raw_data_r_reg[27]\ : label is "{no}"; attribute shift_extract of \raw_data_r_reg[28]\ : label is "{no}"; attribute shift_extract of \raw_data_r_reg[29]\ : label is "{no}"; attribute shift_extract of \raw_data_r_reg[2]\ : label is "{no}"; attribute shift_extract of \raw_data_r_reg[30]\ : label is "{no}"; attribute shift_extract of \raw_data_r_reg[31]\ : label is "{no}"; attribute shift_extract of \raw_data_r_reg[32]\ : label is "{no}"; attribute shift_extract of \raw_data_r_reg[33]\ : label is "{no}"; attribute shift_extract of \raw_data_r_reg[34]\ : label is "{no}"; attribute shift_extract of \raw_data_r_reg[3]\ : label is "{no}"; attribute shift_extract of \raw_data_r_reg[4]\ : label is "{no}"; attribute shift_extract of \raw_data_r_reg[5]\ : label is "{no}"; attribute shift_extract of \raw_data_r_reg[6]\ : label is "{no}"; attribute shift_extract of \raw_data_r_reg[7]\ : label is "{no}"; attribute shift_extract of \raw_data_r_reg[8]\ : label is "{no}"; attribute shift_extract of \raw_data_r_reg[9]\ : label is "{no}"; attribute SOFT_HLUTNM of rxfsm_reset_i_inferred_i_1 : label is "soft_lutpair13"; attribute BOX_TYPE of \srlc32e[0].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name : string; attribute srl_bus_name of \srlc32e[0].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[0].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[0].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[10].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[10].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[10].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[10].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[11].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[11].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[11].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[11].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[12].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[12].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[12].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[12].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[13].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[13].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[13].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[13].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[14].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[14].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[14].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[14].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[15].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[15].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[15].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[15].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[16].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[16].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[16].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[16].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[17].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[17].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[17].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[17].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[18].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[18].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[18].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[18].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[19].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[19].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[19].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[19].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[1].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[1].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[1].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[1].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[20].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[20].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[20].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[20].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[21].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[21].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[21].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[21].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[22].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[22].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[22].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[22].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[23].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[23].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[23].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[23].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[24].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[24].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[24].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[24].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[25].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[25].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[25].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[25].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[26].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[26].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[26].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[26].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[27].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[27].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[27].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[27].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[28].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[28].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[28].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[28].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[29].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[29].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[29].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[29].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[2].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[2].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[2].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[2].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[30].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[30].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[30].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[30].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[31].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[31].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[31].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[31].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[32].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[32].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[32].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[32].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[33].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[33].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[33].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[33].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[34].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[34].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[34].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[34].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[3].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[3].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[3].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[3].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[4].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[4].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[4].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[4].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[5].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[5].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[5].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[5].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[6].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[6].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[6].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[6].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[7].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[7].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[7].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[7].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[8].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[8].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[8].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[8].SRLC32E_inst_1 "; attribute BOX_TYPE of \srlc32e[9].SRLC32E_inst_1\ : label is "PRIMITIVE"; attribute srl_bus_name of \srlc32e[9].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e "; attribute srl_name of \srlc32e[9].SRLC32E_inst_1\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[9].SRLC32E_inst_1 "; attribute shift_extract of valid_btf_detect_reg : label is "{no}"; attribute SOFT_HLUTNM of \wait_for_rd_en[0]_i_1\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \wait_for_rd_en[2]_i_1\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \wait_for_wr_en[0]_i_1\ : label is "soft_lutpair17"; attribute SOFT_HLUTNM of \wait_for_wr_en[1]_i_1\ : label is "soft_lutpair17"; attribute srl_bus_name of \wait_for_wr_en_wr3_reg[0]_srl3\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wait_for_wr_en_wr3_reg "; attribute srl_name of \wait_for_wr_en_wr3_reg[0]_srl3\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wait_for_wr_en_wr3_reg[0]_srl3 "; attribute srl_bus_name of \wait_for_wr_en_wr3_reg[1]_srl3\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wait_for_wr_en_wr3_reg "; attribute srl_name of \wait_for_wr_en_wr3_reg[1]_srl3\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wait_for_wr_en_wr3_reg[1]_srl3 "; attribute shift_extract of \wdth_conv_1stage_reg[0]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[10]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[11]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[12]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[13]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[14]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[15]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[16]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[17]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[18]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[19]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[1]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[20]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[21]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[22]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[23]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[24]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[25]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[26]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[27]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[28]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[29]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[2]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[30]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[31]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[32]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[33]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[34]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[35]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[36]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[37]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[38]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[39]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[3]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[4]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[5]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[6]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[7]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[8]\ : label is "{no}"; attribute shift_extract of \wdth_conv_1stage_reg[9]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[0]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[10]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[11]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[12]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[13]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[14]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[15]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[16]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[17]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[18]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[19]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[1]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[20]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[21]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[22]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[23]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[24]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[25]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[26]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[27]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[28]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[29]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[2]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[30]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[31]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[32]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[33]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[34]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[35]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[36]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[37]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[38]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[39]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[3]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[4]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[5]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[6]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[7]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[8]\ : label is "{no}"; attribute shift_extract of \wdth_conv_2stage_reg[9]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[0]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[10]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[11]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[12]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[13]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[14]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[15]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[16]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[17]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[18]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[19]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[1]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[20]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[21]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[22]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[23]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[24]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[25]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[26]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[27]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[28]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[29]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[2]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[30]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[31]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[32]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[33]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[34]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[35]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[36]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[37]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[38]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[39]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[3]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[4]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[5]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[6]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[7]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[8]\ : label is "{no}"; attribute shift_extract of \wdth_conv_3stage_reg[9]\ : label is "{no}"; attribute SOFT_HLUTNM of \wdth_conv_count[0]_i_1\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \wdth_conv_count[0]_i_2\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \wdth_conv_count[1]_i_1\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \wdth_conv_count[1]_i_2\ : label is "soft_lutpair7"; attribute shift_extract of wr_err_rd_clk_sync_reg : label is "{no}"; attribute SOFT_HLUTNM of \wr_monitor_flag[1]_i_1\ : label is "soft_lutpair16"; attribute SOFT_HLUTNM of \wr_monitor_flag[2]_i_1\ : label is "soft_lutpair16"; attribute SOFT_HLUTNM of \wr_monitor_flag[3]_i_1\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \wr_monitor_flag[4]_i_2\ : label is "soft_lutpair10"; begin ANY_VLD_BTF_FLAG <= \^any_vld_btf_flag\; CB_detect_dlyd0p5 <= \^cb_detect_dlyd0p5\; START_CB_WRITES_OUT <= \^start_cb_writes_out\; bit_err_chan_bond_i <= \^bit_err_chan_bond_i\; do_rd_en_i <= \^do_rd_en_i\; final_gater_for_fifo_din_i <= \^final_gater_for_fifo_din_i\; master_do_rd_en_out_reg(65 downto 0) <= \^master_do_rd_en_out_reg\(65 downto 0); p_2_in <= \^p_2_in\; ANY_VLD_BTF_FLAG_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"F8" ) port map ( I0 => p_0_in0_in, I1 => any_vld_btf_fifo_din_detect_dlyd, I2 => \^any_vld_btf_flag\, O => ANY_VLD_BTF_FLAG_i_1_n_0 ); ANY_VLD_BTF_FLAG_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => ANY_VLD_BTF_FLAG_i_1_n_0, Q => \^any_vld_btf_flag\, R => any_vld_btf_fifo_din_detect_dlyd_i_1_n_0 ); CB_detect_dlyd0p5_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => CB_detect0, Q => \^cb_detect_dlyd0p5\, R => cbcc_fifo_reset_wr_clk ); CB_detect_dlyd1_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => CB_detect_dlyd1p0, I1 => \^cb_detect_dlyd0p5\, O => CB_detect_dlyd10 ); CB_detect_dlyd1_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => CB_detect_dlyd10, Q => CB_detect_dlyd1, R => cbcc_fifo_reset_wr_clk ); CB_detect_dlyd1p0_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \^cb_detect_dlyd0p5\, Q => CB_detect_dlyd1p0, R => cbcc_fifo_reset_wr_clk ); CC_RXLOSSOFSYNC_OUT_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg, CE => '1', D => u_cdc_rxlossofsync_in_n_0, Q => rx_lossofsync_i, R => '0' ); CC_detect_dlyd1_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => CC_detect, Q => CC_detect_dlyd1, R => cbcc_fifo_reset_wr_clk ); CC_detect_pulse_r_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => D(1), Q => CC_detect_pulse_r, R => '0' ); FINAL_GATER_FOR_FIFO_DIN_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"FF80" ) port map ( I0 => do_wr_en_reg_0, I1 => cb_fifo_din_detect_q, I2 => p_0_in0_in, I3 => \^final_gater_for_fifo_din_i\, O => FINAL_GATER_FOR_FIFO_DIN_i_1_n_0 ); FINAL_GATER_FOR_FIFO_DIN_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => FINAL_GATER_FOR_FIFO_DIN_i_1_n_0, Q => \^final_gater_for_fifo_din_i\, R => cbcc_fifo_reset_wr_clk ); FIRST_CB_BITERR_CB_RESET_OUT_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"4155410000000000" ) port map ( I0 => SR(0), I1 => FIRST_CB_BITERR_CB_RESET_OUT_i_2_n_0, I2 => \FIRST_CB_BITERR_CB_RESET_OUT1__15\, I3 => new_do_wr_en, I4 => \^bit_err_chan_bond_i\, I5 => FIRST_CB_BITERR_CB_RESET_OUT_i_4_n_0, O => FIRST_CB_BITERR_CB_RESET_OUT_i_1_n_0 ); FIRST_CB_BITERR_CB_RESET_OUT_i_2: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFDFF" ) port map ( I0 => \wr_monitor_flag_reg__0\(1), I1 => \wr_monitor_flag_reg__0\(2), I2 => \wr_monitor_flag_reg__0\(0), I3 => \wr_monitor_flag_reg__0\(3), I4 => \wr_monitor_flag_reg__0\(4), O => FIRST_CB_BITERR_CB_RESET_OUT_i_2_n_0 ); FIRST_CB_BITERR_CB_RESET_OUT_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"0100000000000000" ) port map ( I0 => en32_fifo_din_i(58), I1 => en32_fifo_din_i(57), I2 => en32_fifo_din_i(56), I3 => FIRST_CB_BITERR_CB_RESET_OUT_i_5_n_0, I4 => FIRST_CB_BITERR_CB_RESET_OUT_i_6_n_0, I5 => FIRST_CB_BITERR_CB_RESET_OUT_i_7_n_0, O => \FIRST_CB_BITERR_CB_RESET_OUT1__15\ ); FIRST_CB_BITERR_CB_RESET_OUT_i_4: unisim.vcomponents.LUT5 generic map( INIT => X"11111554" ) port map ( I0 => \wr_monitor_flag_reg__0\(4), I1 => \wr_monitor_flag_reg__0\(3), I2 => \wr_monitor_flag_reg__0\(0), I3 => \wr_monitor_flag_reg__0\(1), I4 => \wr_monitor_flag_reg__0\(2), O => FIRST_CB_BITERR_CB_RESET_OUT_i_4_n_0 ); FIRST_CB_BITERR_CB_RESET_OUT_i_5: unisim.vcomponents.LUT4 generic map( INIT => X"0004" ) port map ( I0 => en32_fifo_din_i(61), I1 => en32_fifo_din_i(62), I2 => en32_fifo_din_i(60), I3 => en32_fifo_din_i(59), O => FIRST_CB_BITERR_CB_RESET_OUT_i_5_n_0 ); FIRST_CB_BITERR_CB_RESET_OUT_i_6: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => en32_fifo_din_i(66), I1 => en32_fifo_din_i(65), I2 => en32_fifo_din_i(64), I3 => en32_fifo_din_i(63), O => FIRST_CB_BITERR_CB_RESET_OUT_i_6_n_0 ); FIRST_CB_BITERR_CB_RESET_OUT_i_7: unisim.vcomponents.LUT6 generic map( INIT => X"0000800000000000" ) port map ( I0 => en32_fifo_din_i(67), I1 => en32_fifo_din_i(68), I2 => en32_fifo_din_i(69), I3 => en32_fifo_din_i(70), I4 => en32_fifo_din_i(71), I5 => en32_fifo_din_i(76), O => FIRST_CB_BITERR_CB_RESET_OUT_i_7_n_0 ); FIRST_CB_BITERR_CB_RESET_OUT_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => FIRST_CB_BITERR_CB_RESET_OUT_i_1_n_0, Q => \^bit_err_chan_bond_i\, R => '0' ); HARD_ERR_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0000" ) port map ( I0 => rxbuferr_out_i(1), I1 => rxbuferr_out_i(0), I2 => HARD_ERR_reg, I3 => TXBUFSTATUS(0), I4 => enable_err_detect_i, O => wr_err_rd_clk_sync_reg_0 ); \LINK_RESET[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) port map ( I0 => \LINK_RESET[0]_i_2_n_0\, I1 => \LINK_RESET[0]_i_3_n_0\, I2 => \LINK_RESET[0]_i_4_n_0\, O => link_reset_0 ); \LINK_RESET[0]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFF7FFF" ) port map ( I0 => count_for_reset_r_reg(12), I1 => count_for_reset_r_reg(9), I2 => count_for_reset_r_reg(21), I3 => count_for_reset_r_reg(10), I4 => \LINK_RESET[0]_i_5_n_0\, O => \LINK_RESET[0]_i_2_n_0\ ); \LINK_RESET[0]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"00008000" ) port map ( I0 => count_for_reset_r_reg(23), I1 => count_for_reset_r_reg(11), I2 => count_for_reset_r_reg(17), I3 => count_for_reset_r_reg(14), I4 => \LINK_RESET[0]_i_6_n_0\, O => \LINK_RESET[0]_i_3_n_0\ ); \LINK_RESET[0]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"0F40004000400040" ) port map ( I0 => count_for_reset_r_reg(3), I1 => \LINK_RESET[0]_i_7_n_0\, I2 => \LINK_RESET[0]_i_8_n_0\, I3 => count_for_reset_r_reg(4), I4 => count_for_reset_r_reg(20), I5 => \LINK_RESET[0]_i_9_n_0\, O => \LINK_RESET[0]_i_4_n_0\ ); \LINK_RESET[0]_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"7FFF" ) port map ( I0 => count_for_reset_r_reg(8), I1 => count_for_reset_r_reg(16), I2 => count_for_reset_r_reg(20), I3 => count_for_reset_r_reg(22), O => \LINK_RESET[0]_i_5_n_0\ ); \LINK_RESET[0]_i_6\: unisim.vcomponents.LUT4 generic map( INIT => X"7FFF" ) port map ( I0 => count_for_reset_r_reg(15), I1 => count_for_reset_r_reg(18), I2 => count_for_reset_r_reg(13), I3 => count_for_reset_r_reg(19), O => \LINK_RESET[0]_i_6_n_0\ ); \LINK_RESET[0]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => count_for_reset_r_reg(5), I1 => count_for_reset_r_reg(0), I2 => count_for_reset_r_reg(6), I3 => count_for_reset_r_reg(7), O => \LINK_RESET[0]_i_7_n_0\ ); \LINK_RESET[0]_i_8\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => count_for_reset_r_reg(1), I1 => count_for_reset_r_reg(2), O => \LINK_RESET[0]_i_8_n_0\ ); \LINK_RESET[0]_i_9\: unisim.vcomponents.LUT4 generic map( INIT => X"8000" ) port map ( I0 => count_for_reset_r_reg(6), I1 => count_for_reset_r_reg(7), I2 => count_for_reset_r_reg(3), I3 => count_for_reset_r_reg(5), O => \LINK_RESET[0]_i_9_n_0\ ); LINK_RESET_OUT_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \rx_state_reg[7]\, I1 => link_reset_0_c, O => LINK_RESET_OUT0 ); \LINK_RESET_reg[0]\: unisim.vcomponents.FDRE port map ( C => stg3_reg, CE => '1', D => link_reset_0, Q => link_reset_0_c, R => '0' ); RXDATAVALID_IN_REG_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => master_do_rd_en_q, I1 => fifo_dout_i(68), O => rxdatavalid_i ); \RX_DATA_REG[63]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => hold_reg, O => hold_reg_reg_0 ); SOFT_ERR_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"FBBF0000" ) port map ( I0 => illegal_btf_i, I1 => hold_reg, I2 => \^master_do_rd_en_out_reg\(65), I3 => \^master_do_rd_en_out_reg\(64), I4 => SOFT_ERR_i_2_n_0, O => ILLEGAL_BTF_reg ); SOFT_ERR_i_2: unisim.vcomponents.LUT3 generic map( INIT => X"80" ) port map ( I0 => fifo_dout_i(68), I1 => master_do_rd_en_q, I2 => enable_err_detect_i, O => SOFT_ERR_i_2_n_0 ); SRLC32E_inst_4: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00010", CE => '1', CLK => \out\, D => rxdatavalid_to_fifo_i, Q => rxdatavalid_lookahead_i, Q31 => NLW_SRLC32E_inst_4_Q31_UNCONNECTED ); START_CB_WRITES_OUT_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"FF80" ) port map ( I0 => START_CB_WRITES_OUT_reg_0, I1 => cb_fifo_din_detect_q, I2 => p_0_in0_in, I3 => \^start_cb_writes_out\, O => START_CB_WRITES_OUT_i_1_n_0 ); START_CB_WRITES_OUT_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => START_CB_WRITES_OUT_i_1_n_0, Q => \^start_cb_writes_out\, R => cbcc_fifo_reset_wr_clk ); allow_block_sync_propagation_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"0000CCCE" ) port map ( I0 => allow_block_sync_propagation_reg_0, I1 => allow_block_sync_propagation, I2 => allow_block_sync_propagation_reg_1, I3 => cdr_reset_fsm_lnkreset, I4 => \^p_2_in\, O => allow_block_sync_propagation_reg ); any_vld_btf_fifo_din_detect_dlyd_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"DF" ) port map ( I0 => wait_for_wr_en_wr4(1), I1 => cbcc_fifo_reset_wr_clk, I2 => wait_for_wr_en_wr4(0), O => any_vld_btf_fifo_din_detect_dlyd_i_1_n_0 ); any_vld_btf_fifo_din_detect_dlyd_i_2: unisim.vcomponents.LUT4 generic map( INIT => X"0800" ) port map ( I0 => any_vld_btf_fifo_din_detect_dlyd_i_3_n_0, I1 => any_vld_btf_fifo_din_detect_dlyd_i_4_n_0, I2 => \raw_data_r_r_reg_n_0_[16]\, I3 => any_vld_btf_fifo_din_detect_dlyd_i_5_n_0, O => any_vld_btf_fifo_din_detect ); any_vld_btf_fifo_din_detect_dlyd_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"0001000000000000" ) port map ( I0 => \raw_data_r_r_reg_n_0_[25]\, I1 => \raw_data_r_r_reg_n_0_[26]\, I2 => \raw_data_r_r_reg_n_0_[23]\, I3 => \raw_data_r_r_reg_n_0_[24]\, I4 => \raw_data_r_r_reg_n_0_[28]\, I5 => \raw_data_r_r_reg_n_0_[27]\, O => any_vld_btf_fifo_din_detect_dlyd_i_3_n_0 ); any_vld_btf_fifo_din_detect_dlyd_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"0000000100000000" ) port map ( I0 => \raw_data_r_r_reg_n_0_[19]\, I1 => \raw_data_r_r_reg_n_0_[20]\, I2 => \raw_data_r_r_reg_n_0_[17]\, I3 => \raw_data_r_r_reg_n_0_[18]\, I4 => \raw_data_r_r_reg_n_0_[21]\, I5 => \raw_data_r_r_reg_n_0_[22]\, O => any_vld_btf_fifo_din_detect_dlyd_i_4_n_0 ); any_vld_btf_fifo_din_detect_dlyd_i_5: unisim.vcomponents.LUT6 generic map( INIT => X"1000000000000000" ) port map ( I0 => \raw_data_r_r_reg_n_0_[31]\, I1 => \raw_data_r_r_reg_n_0_[32]\, I2 => \raw_data_r_r_reg_n_0_[29]\, I3 => \raw_data_r_r_reg_n_0_[30]\, I4 => p_0_in0_in, I5 => \raw_data_r_r_reg_n_0_[33]\, O => any_vld_btf_fifo_din_detect_dlyd_i_5_n_0 ); any_vld_btf_fifo_din_detect_dlyd_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => any_vld_btf_fifo_din_detect, Q => any_vld_btf_fifo_din_detect_dlyd, R => any_vld_btf_fifo_din_detect_dlyd_i_1_n_0 ); cb_fifo_din_detect_q_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => any_vld_btf_fifo_din_detect, Q => cb_fifo_din_detect_q, R => cbcc_fifo_reset_wr_clk ); \cdr_reset_fsm_cntr_r[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"FE" ) port map ( I0 => \rx_state_reg[7]_0\, I1 => hard_err_rst_int, I2 => link_reset_0_c, O => \^p_2_in\ ); cdr_reset_fsm_lnkreset_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"0000FF02" ) port map ( I0 => \rx_state_reg[7]\, I1 => allow_block_sync_propagation, I2 => allow_block_sync_propagation_reg_1, I3 => cdr_reset_fsm_lnkreset, I4 => \^p_2_in\, O => cdr_reset_fsm_lnkreset_reg ); \count_for_reset_r[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FEFEFEFEFFFFFEFF" ) port map ( I0 => valid_btf_detect_dlyd1, I1 => \rx_state_reg[7]\, I2 => \rx_state_reg[7]_0\, I3 => \count_for_reset_r_reg[0]_0\, I4 => reset_initclk, I5 => AR(0), O => \count_for_reset_r[0]_i_1_n_0\ ); \count_for_reset_r[0]_i_3\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => count_for_reset_r_reg(0), O => \count_for_reset_r[0]_i_3_n_0\ ); \count_for_reset_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => stg3_reg, CE => '1', D => \count_for_reset_r_reg[0]_i_2_n_7\, Q => count_for_reset_r_reg(0), R => \count_for_reset_r[0]_i_1_n_0\ ); \count_for_reset_r_reg[0]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \count_for_reset_r_reg[0]_i_2_n_0\, CO(2) => \count_for_reset_r_reg[0]_i_2_n_1\, CO(1) => \count_for_reset_r_reg[0]_i_2_n_2\, CO(0) => \count_for_reset_r_reg[0]_i_2_n_3\, CYINIT => '0', DI(3 downto 0) => B"0001", O(3) => \count_for_reset_r_reg[0]_i_2_n_4\, O(2) => \count_for_reset_r_reg[0]_i_2_n_5\, O(1) => \count_for_reset_r_reg[0]_i_2_n_6\, O(0) => \count_for_reset_r_reg[0]_i_2_n_7\, S(3 downto 1) => count_for_reset_r_reg(3 downto 1), S(0) => \count_for_reset_r[0]_i_3_n_0\ ); \count_for_reset_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => stg3_reg, CE => '1', D => \count_for_reset_r_reg[8]_i_1_n_5\, Q => count_for_reset_r_reg(10), R => \count_for_reset_r[0]_i_1_n_0\ ); \count_for_reset_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => stg3_reg, CE => '1', D => \count_for_reset_r_reg[8]_i_1_n_4\, Q => count_for_reset_r_reg(11), R => \count_for_reset_r[0]_i_1_n_0\ ); \count_for_reset_r_reg[12]\: unisim.vcomponents.FDRE port map ( C => stg3_reg, CE => '1', D => \count_for_reset_r_reg[12]_i_1_n_7\, Q => count_for_reset_r_reg(12), R => \count_for_reset_r[0]_i_1_n_0\ ); \count_for_reset_r_reg[12]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \count_for_reset_r_reg[8]_i_1_n_0\, CO(3) => \count_for_reset_r_reg[12]_i_1_n_0\, CO(2) => \count_for_reset_r_reg[12]_i_1_n_1\, CO(1) => \count_for_reset_r_reg[12]_i_1_n_2\, CO(0) => \count_for_reset_r_reg[12]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \count_for_reset_r_reg[12]_i_1_n_4\, O(2) => \count_for_reset_r_reg[12]_i_1_n_5\, O(1) => \count_for_reset_r_reg[12]_i_1_n_6\, O(0) => \count_for_reset_r_reg[12]_i_1_n_7\, S(3 downto 0) => count_for_reset_r_reg(15 downto 12) ); \count_for_reset_r_reg[13]\: unisim.vcomponents.FDRE port map ( C => stg3_reg, CE => '1', D => \count_for_reset_r_reg[12]_i_1_n_6\, Q => count_for_reset_r_reg(13), R => \count_for_reset_r[0]_i_1_n_0\ ); \count_for_reset_r_reg[14]\: unisim.vcomponents.FDRE port map ( C => stg3_reg, CE => '1', D => \count_for_reset_r_reg[12]_i_1_n_5\, Q => count_for_reset_r_reg(14), R => \count_for_reset_r[0]_i_1_n_0\ ); \count_for_reset_r_reg[15]\: unisim.vcomponents.FDRE port map ( C => stg3_reg, CE => '1', D => \count_for_reset_r_reg[12]_i_1_n_4\, Q => count_for_reset_r_reg(15), R => \count_for_reset_r[0]_i_1_n_0\ ); \count_for_reset_r_reg[16]\: unisim.vcomponents.FDRE port map ( C => stg3_reg, CE => '1', D => \count_for_reset_r_reg[16]_i_1_n_7\, Q => count_for_reset_r_reg(16), R => \count_for_reset_r[0]_i_1_n_0\ ); \count_for_reset_r_reg[16]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \count_for_reset_r_reg[12]_i_1_n_0\, CO(3) => \count_for_reset_r_reg[16]_i_1_n_0\, CO(2) => \count_for_reset_r_reg[16]_i_1_n_1\, CO(1) => \count_for_reset_r_reg[16]_i_1_n_2\, CO(0) => \count_for_reset_r_reg[16]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \count_for_reset_r_reg[16]_i_1_n_4\, O(2) => \count_for_reset_r_reg[16]_i_1_n_5\, O(1) => \count_for_reset_r_reg[16]_i_1_n_6\, O(0) => \count_for_reset_r_reg[16]_i_1_n_7\, S(3 downto 0) => count_for_reset_r_reg(19 downto 16) ); \count_for_reset_r_reg[17]\: unisim.vcomponents.FDRE port map ( C => stg3_reg, CE => '1', D => \count_for_reset_r_reg[16]_i_1_n_6\, Q => count_for_reset_r_reg(17), R => \count_for_reset_r[0]_i_1_n_0\ ); \count_for_reset_r_reg[18]\: unisim.vcomponents.FDRE port map ( C => stg3_reg, CE => '1', D => \count_for_reset_r_reg[16]_i_1_n_5\, Q => count_for_reset_r_reg(18), R => \count_for_reset_r[0]_i_1_n_0\ ); \count_for_reset_r_reg[19]\: unisim.vcomponents.FDRE port map ( C => stg3_reg, CE => '1', D => \count_for_reset_r_reg[16]_i_1_n_4\, Q => count_for_reset_r_reg(19), R => \count_for_reset_r[0]_i_1_n_0\ ); \count_for_reset_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => stg3_reg, CE => '1', D => \count_for_reset_r_reg[0]_i_2_n_6\, Q => count_for_reset_r_reg(1), R => \count_for_reset_r[0]_i_1_n_0\ ); \count_for_reset_r_reg[20]\: unisim.vcomponents.FDRE port map ( C => stg3_reg, CE => '1', D => \count_for_reset_r_reg[20]_i_1_n_7\, Q => count_for_reset_r_reg(20), R => \count_for_reset_r[0]_i_1_n_0\ ); \count_for_reset_r_reg[20]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \count_for_reset_r_reg[16]_i_1_n_0\, CO(3) => \NLW_count_for_reset_r_reg[20]_i_1_CO_UNCONNECTED\(3), CO(2) => \count_for_reset_r_reg[20]_i_1_n_1\, CO(1) => \count_for_reset_r_reg[20]_i_1_n_2\, CO(0) => \count_for_reset_r_reg[20]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \count_for_reset_r_reg[20]_i_1_n_4\, O(2) => \count_for_reset_r_reg[20]_i_1_n_5\, O(1) => \count_for_reset_r_reg[20]_i_1_n_6\, O(0) => \count_for_reset_r_reg[20]_i_1_n_7\, S(3 downto 0) => count_for_reset_r_reg(23 downto 20) ); \count_for_reset_r_reg[21]\: unisim.vcomponents.FDRE port map ( C => stg3_reg, CE => '1', D => \count_for_reset_r_reg[20]_i_1_n_6\, Q => count_for_reset_r_reg(21), R => \count_for_reset_r[0]_i_1_n_0\ ); \count_for_reset_r_reg[22]\: unisim.vcomponents.FDRE port map ( C => stg3_reg, CE => '1', D => \count_for_reset_r_reg[20]_i_1_n_5\, Q => count_for_reset_r_reg(22), R => \count_for_reset_r[0]_i_1_n_0\ ); \count_for_reset_r_reg[23]\: unisim.vcomponents.FDRE port map ( C => stg3_reg, CE => '1', D => \count_for_reset_r_reg[20]_i_1_n_4\, Q => count_for_reset_r_reg(23), R => \count_for_reset_r[0]_i_1_n_0\ ); \count_for_reset_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => stg3_reg, CE => '1', D => \count_for_reset_r_reg[0]_i_2_n_5\, Q => count_for_reset_r_reg(2), R => \count_for_reset_r[0]_i_1_n_0\ ); \count_for_reset_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => stg3_reg, CE => '1', D => \count_for_reset_r_reg[0]_i_2_n_4\, Q => count_for_reset_r_reg(3), R => \count_for_reset_r[0]_i_1_n_0\ ); \count_for_reset_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => stg3_reg, CE => '1', D => \count_for_reset_r_reg[4]_i_1_n_7\, Q => count_for_reset_r_reg(4), R => \count_for_reset_r[0]_i_1_n_0\ ); \count_for_reset_r_reg[4]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \count_for_reset_r_reg[0]_i_2_n_0\, CO(3) => \count_for_reset_r_reg[4]_i_1_n_0\, CO(2) => \count_for_reset_r_reg[4]_i_1_n_1\, CO(1) => \count_for_reset_r_reg[4]_i_1_n_2\, CO(0) => \count_for_reset_r_reg[4]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \count_for_reset_r_reg[4]_i_1_n_4\, O(2) => \count_for_reset_r_reg[4]_i_1_n_5\, O(1) => \count_for_reset_r_reg[4]_i_1_n_6\, O(0) => \count_for_reset_r_reg[4]_i_1_n_7\, S(3 downto 0) => count_for_reset_r_reg(7 downto 4) ); \count_for_reset_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => stg3_reg, CE => '1', D => \count_for_reset_r_reg[4]_i_1_n_6\, Q => count_for_reset_r_reg(5), R => \count_for_reset_r[0]_i_1_n_0\ ); \count_for_reset_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => stg3_reg, CE => '1', D => \count_for_reset_r_reg[4]_i_1_n_5\, Q => count_for_reset_r_reg(6), R => \count_for_reset_r[0]_i_1_n_0\ ); \count_for_reset_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => stg3_reg, CE => '1', D => \count_for_reset_r_reg[4]_i_1_n_4\, Q => count_for_reset_r_reg(7), R => \count_for_reset_r[0]_i_1_n_0\ ); \count_for_reset_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => stg3_reg, CE => '1', D => \count_for_reset_r_reg[8]_i_1_n_7\, Q => count_for_reset_r_reg(8), R => \count_for_reset_r[0]_i_1_n_0\ ); \count_for_reset_r_reg[8]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \count_for_reset_r_reg[4]_i_1_n_0\, CO(3) => \count_for_reset_r_reg[8]_i_1_n_0\, CO(2) => \count_for_reset_r_reg[8]_i_1_n_1\, CO(1) => \count_for_reset_r_reg[8]_i_1_n_2\, CO(0) => \count_for_reset_r_reg[8]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \count_for_reset_r_reg[8]_i_1_n_4\, O(2) => \count_for_reset_r_reg[8]_i_1_n_5\, O(1) => \count_for_reset_r_reg[8]_i_1_n_6\, O(0) => \count_for_reset_r_reg[8]_i_1_n_7\, S(3 downto 0) => count_for_reset_r_reg(11 downto 8) ); \count_for_reset_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => stg3_reg, CE => '1', D => \count_for_reset_r_reg[8]_i_1_n_6\, Q => count_for_reset_r_reg(9), R => \count_for_reset_r[0]_i_1_n_0\ ); data_fifo: unisim.vcomponents.FIFO36E1 generic map( ALMOST_EMPTY_OFFSET => X"000E", ALMOST_FULL_OFFSET => X"01C2", DATA_WIDTH => 72, DO_REG => 1, EN_ECC_READ => false, EN_ECC_WRITE => false, EN_SYN => false, FIFO_MODE => "FIFO36_72", FIRST_WORD_FALL_THROUGH => false, INIT => X"000000000000000000", IS_RDCLK_INVERTED => '0', IS_RDEN_INVERTED => '0', IS_RSTREG_INVERTED => '0', IS_RST_INVERTED => '0', IS_WRCLK_INVERTED => '0', IS_WREN_INVERTED => '0', SIM_DEVICE => "7SERIES", SRVAL => X"000000000000000000" ) port map ( ALMOSTEMPTY => buffer_too_empty_c, ALMOSTFULL => NLW_data_fifo_ALMOSTFULL_UNCONNECTED, DBITERR => NLW_data_fifo_DBITERR_UNCONNECTED, DI(63 downto 32) => en32_fifo_din_i(71 downto 40), DI(31 downto 0) => en32_fifo_din_i(31 downto 0), DIP(7 downto 0) => en32_fifo_din_i(79 downto 72), DO(63 downto 0) => \^master_do_rd_en_out_reg\(63 downto 0), DOP(7 downto 5) => NLW_data_fifo_DOP_UNCONNECTED(7 downto 5), DOP(4) => fifo_dout_i(68), DOP(3 downto 2) => NLW_data_fifo_DOP_UNCONNECTED(3 downto 2), DOP(1 downto 0) => \^master_do_rd_en_out_reg\(65 downto 64), ECCPARITY(7 downto 0) => NLW_data_fifo_ECCPARITY_UNCONNECTED(7 downto 0), EMPTY => underflow_flag_c, FULL => overflow_flag_c, INJECTDBITERR => '0', INJECTSBITERR => '0', RDCLK => s_level_out_d6_reg, RDCOUNT(12 downto 0) => NLW_data_fifo_RDCOUNT_UNCONNECTED(12 downto 0), RDEN => master_do_rd_en_q_reg_0, RDERR => rd_err_c, REGCE => '1', RST => cbcc_fifo_reset_to_fifo_rd_clk, RSTREG => '0', SBITERR => NLW_data_fifo_SBITERR_UNCONNECTED, WRCLK => \out\, WRCOUNT(12 downto 0) => NLW_data_fifo_WRCOUNT_UNCONNECTED(12 downto 0), WREN => new_do_wr_en, WRERR => wr_err_c ); do_rd_en_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"BF" ) port map ( I0 => cbcc_fifo_reset_rd_clk, I1 => wait_for_rd_en(2), I2 => wait_for_rd_en(1), O => do_rd_en ); do_rd_en_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_level_out_d6_reg, CE => '1', D => new_underflow_flag_c_reg_inv_n_0, Q => \^do_rd_en_i\, R => do_rd_en ); do_wr_en_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0404040004000400" ) port map ( I0 => any_vld_btf_fifo_din_detect_dlyd_i_1_n_0, I1 => p_1_in, I2 => overflow_flag_c, I3 => \^final_gater_for_fifo_din_i\, I4 => do_wr_en_i_2_n_0, I5 => do_wr_en_reg_0, O => do_wr_en_i_1_n_0 ); do_wr_en_i_2: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => cb_fifo_din_detect_q, I1 => p_0_in0_in, O => do_wr_en_i_2_n_0 ); do_wr_en_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => do_wr_en_i_1_n_0, Q => do_wr_en, R => '0' ); first_cb_to_write_to_fifo_dlyd_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"0800" ) port map ( I0 => first_cb_to_write_to_fifo_dlyd_i_2_n_0, I1 => first_cb_to_write_to_fifo_dlyd_i_3_n_0, I2 => \raw_data_r_reg_n_0_[16]\, I3 => first_cb_to_write_to_fifo_dlyd_i_4_n_0, O => first_cb_to_write_to_fifo ); first_cb_to_write_to_fifo_dlyd_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0001000000000000" ) port map ( I0 => \raw_data_r_reg_n_0_[25]\, I1 => \raw_data_r_reg_n_0_[26]\, I2 => \raw_data_r_reg_n_0_[23]\, I3 => \raw_data_r_reg_n_0_[24]\, I4 => \raw_data_r_reg_n_0_[28]\, I5 => \raw_data_r_reg_n_0_[27]\, O => first_cb_to_write_to_fifo_dlyd_i_2_n_0 ); first_cb_to_write_to_fifo_dlyd_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"0000000100000000" ) port map ( I0 => \raw_data_r_reg_n_0_[19]\, I1 => \raw_data_r_reg_n_0_[20]\, I2 => \raw_data_r_reg_n_0_[17]\, I3 => \raw_data_r_reg_n_0_[18]\, I4 => \raw_data_r_reg_n_0_[21]\, I5 => \raw_data_r_reg_n_0_[22]\, O => first_cb_to_write_to_fifo_dlyd_i_3_n_0 ); first_cb_to_write_to_fifo_dlyd_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"1000000000000000" ) port map ( I0 => \raw_data_r_reg_n_0_[31]\, I1 => \raw_data_r_reg_n_0_[32]\, I2 => \raw_data_r_reg_n_0_[29]\, I3 => \raw_data_r_reg_n_0_[30]\, I4 => p_1_in, I5 => \raw_data_r_reg_n_0_[33]\, O => first_cb_to_write_to_fifo_dlyd_i_4_n_0 ); first_cb_to_write_to_fifo_dlyd_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => first_cb_to_write_to_fifo, Q => first_cb_to_write_to_fifo_dlyd, R => cbcc_fifo_reset_wr_clk ); hard_err_usr_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFAAA8AAA8AAA8" ) port map ( I0 => hard_err_usr_reg, I1 => rxbuferr_out_i(1), I2 => rxbuferr_out_i(0), I3 => HARD_ERR_reg, I4 => channel_up_tx_if, I5 => TXBUFSTATUS(0), O => hard_err_usr0 ); hold_reg_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"0E" ) port map ( I0 => hold_reg, I1 => \^do_rd_en_i\, I2 => CC_RXLOSSOFSYNC_OUT_reg_0, O => hold_reg_i_1_n_0 ); hold_reg_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg, CE => '1', D => hold_reg_i_1_n_0, Q => hold_reg, R => '0' ); master_do_rd_en_q_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg, CE => '1', D => master_do_rd_en_q_reg_0, Q => master_do_rd_en_q, R => cbcc_fifo_reset_rd_clk ); new_do_wr_en_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"0800" ) port map ( I0 => bit80_prsnt, I1 => wait_for_wr_en_wr4(0), I2 => cbcc_fifo_reset_wr_clk, I3 => wait_for_wr_en_wr4(1), O => new_do_wr_en_i_1_n_0 ); new_do_wr_en_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => new_do_wr_en_i_1_n_0, Q => new_do_wr_en, R => '0' ); new_underflow_flag_c_inv_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"57" ) port map ( I0 => underflow_flag_r3, I1 => buffer_too_empty_c, I2 => underflow_flag_c, O => new_underflow_flag_c0 ); new_underflow_flag_c_reg_inv: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg, CE => '1', D => new_underflow_flag_c0, Q => new_underflow_flag_c_reg_inv_n_0, R => cbcc_fifo_reset_rd_clk ); \raw_data_r_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \raw_data_r_reg_n_0_[0]\, Q => \raw_data_r_r_reg_n_0_[0]\, R => '0' ); \raw_data_r_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \raw_data_r_reg_n_0_[10]\, Q => \raw_data_r_r_reg_n_0_[10]\, R => '0' ); \raw_data_r_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \raw_data_r_reg_n_0_[11]\, Q => \raw_data_r_r_reg_n_0_[11]\, R => '0' ); \raw_data_r_r_reg[12]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \raw_data_r_reg_n_0_[12]\, Q => \raw_data_r_r_reg_n_0_[12]\, R => '0' ); \raw_data_r_r_reg[13]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \raw_data_r_reg_n_0_[13]\, Q => \raw_data_r_r_reg_n_0_[13]\, R => '0' ); \raw_data_r_r_reg[14]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \raw_data_r_reg_n_0_[14]\, Q => \raw_data_r_r_reg_n_0_[14]\, R => '0' ); \raw_data_r_r_reg[15]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \raw_data_r_reg_n_0_[15]\, Q => \raw_data_r_r_reg_n_0_[15]\, R => '0' ); \raw_data_r_r_reg[16]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \raw_data_r_reg_n_0_[16]\, Q => \raw_data_r_r_reg_n_0_[16]\, R => '0' ); \raw_data_r_r_reg[17]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \raw_data_r_reg_n_0_[17]\, Q => \raw_data_r_r_reg_n_0_[17]\, R => '0' ); \raw_data_r_r_reg[18]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \raw_data_r_reg_n_0_[18]\, Q => \raw_data_r_r_reg_n_0_[18]\, R => '0' ); \raw_data_r_r_reg[19]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \raw_data_r_reg_n_0_[19]\, Q => \raw_data_r_r_reg_n_0_[19]\, R => '0' ); \raw_data_r_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \raw_data_r_reg_n_0_[1]\, Q => \raw_data_r_r_reg_n_0_[1]\, R => '0' ); \raw_data_r_r_reg[20]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \raw_data_r_reg_n_0_[20]\, Q => \raw_data_r_r_reg_n_0_[20]\, R => '0' ); \raw_data_r_r_reg[21]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \raw_data_r_reg_n_0_[21]\, Q => \raw_data_r_r_reg_n_0_[21]\, R => '0' ); \raw_data_r_r_reg[22]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \raw_data_r_reg_n_0_[22]\, Q => \raw_data_r_r_reg_n_0_[22]\, R => '0' ); \raw_data_r_r_reg[23]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \raw_data_r_reg_n_0_[23]\, Q => \raw_data_r_r_reg_n_0_[23]\, R => '0' ); \raw_data_r_r_reg[24]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \raw_data_r_reg_n_0_[24]\, Q => \raw_data_r_r_reg_n_0_[24]\, R => '0' ); \raw_data_r_r_reg[25]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \raw_data_r_reg_n_0_[25]\, Q => \raw_data_r_r_reg_n_0_[25]\, R => '0' ); \raw_data_r_r_reg[26]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \raw_data_r_reg_n_0_[26]\, Q => \raw_data_r_r_reg_n_0_[26]\, R => '0' ); \raw_data_r_r_reg[27]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \raw_data_r_reg_n_0_[27]\, Q => \raw_data_r_r_reg_n_0_[27]\, R => '0' ); \raw_data_r_r_reg[28]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \raw_data_r_reg_n_0_[28]\, Q => \raw_data_r_r_reg_n_0_[28]\, R => '0' ); \raw_data_r_r_reg[29]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \raw_data_r_reg_n_0_[29]\, Q => \raw_data_r_r_reg_n_0_[29]\, R => '0' ); \raw_data_r_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \raw_data_r_reg_n_0_[2]\, Q => \raw_data_r_r_reg_n_0_[2]\, R => '0' ); \raw_data_r_r_reg[30]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \raw_data_r_reg_n_0_[30]\, Q => \raw_data_r_r_reg_n_0_[30]\, R => '0' ); \raw_data_r_r_reg[31]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \raw_data_r_reg_n_0_[31]\, Q => \raw_data_r_r_reg_n_0_[31]\, R => '0' ); \raw_data_r_r_reg[32]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \raw_data_r_reg_n_0_[32]\, Q => \raw_data_r_r_reg_n_0_[32]\, R => '0' ); \raw_data_r_r_reg[33]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \raw_data_r_reg_n_0_[33]\, Q => \raw_data_r_r_reg_n_0_[33]\, R => '0' ); \raw_data_r_r_reg[34]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => p_1_in, Q => p_0_in0_in, R => '0' ); \raw_data_r_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \raw_data_r_reg_n_0_[3]\, Q => \raw_data_r_r_reg_n_0_[3]\, R => '0' ); \raw_data_r_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \raw_data_r_reg_n_0_[4]\, Q => \raw_data_r_r_reg_n_0_[4]\, R => '0' ); \raw_data_r_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \raw_data_r_reg_n_0_[5]\, Q => \raw_data_r_r_reg_n_0_[5]\, R => '0' ); \raw_data_r_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \raw_data_r_reg_n_0_[6]\, Q => \raw_data_r_r_reg_n_0_[6]\, R => '0' ); \raw_data_r_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \raw_data_r_reg_n_0_[7]\, Q => \raw_data_r_r_reg_n_0_[7]\, R => '0' ); \raw_data_r_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \raw_data_r_reg_n_0_[8]\, Q => \raw_data_r_r_reg_n_0_[8]\, R => '0' ); \raw_data_r_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => \raw_data_r_reg_n_0_[9]\, Q => \raw_data_r_r_reg_n_0_[9]\, R => '0' ); \raw_data_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => raw_data_srl_out(0), Q => \raw_data_r_reg_n_0_[0]\, R => '0' ); \raw_data_r_reg[10]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => raw_data_srl_out(10), Q => \raw_data_r_reg_n_0_[10]\, R => '0' ); \raw_data_r_reg[11]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => raw_data_srl_out(11), Q => \raw_data_r_reg_n_0_[11]\, R => '0' ); \raw_data_r_reg[12]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => raw_data_srl_out(12), Q => \raw_data_r_reg_n_0_[12]\, R => '0' ); \raw_data_r_reg[13]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => raw_data_srl_out(13), Q => \raw_data_r_reg_n_0_[13]\, R => '0' ); \raw_data_r_reg[14]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => raw_data_srl_out(14), Q => \raw_data_r_reg_n_0_[14]\, R => '0' ); \raw_data_r_reg[15]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => raw_data_srl_out(15), Q => \raw_data_r_reg_n_0_[15]\, R => '0' ); \raw_data_r_reg[16]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => raw_data_srl_out(16), Q => \raw_data_r_reg_n_0_[16]\, R => '0' ); \raw_data_r_reg[17]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => raw_data_srl_out(17), Q => \raw_data_r_reg_n_0_[17]\, R => '0' ); \raw_data_r_reg[18]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => raw_data_srl_out(18), Q => \raw_data_r_reg_n_0_[18]\, R => '0' ); \raw_data_r_reg[19]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => raw_data_srl_out(19), Q => \raw_data_r_reg_n_0_[19]\, R => '0' ); \raw_data_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => raw_data_srl_out(1), Q => \raw_data_r_reg_n_0_[1]\, R => '0' ); \raw_data_r_reg[20]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => raw_data_srl_out(20), Q => \raw_data_r_reg_n_0_[20]\, R => '0' ); \raw_data_r_reg[21]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => raw_data_srl_out(21), Q => \raw_data_r_reg_n_0_[21]\, R => '0' ); \raw_data_r_reg[22]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => raw_data_srl_out(22), Q => \raw_data_r_reg_n_0_[22]\, R => '0' ); \raw_data_r_reg[23]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => raw_data_srl_out(23), Q => \raw_data_r_reg_n_0_[23]\, R => '0' ); \raw_data_r_reg[24]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => raw_data_srl_out(24), Q => \raw_data_r_reg_n_0_[24]\, R => '0' ); \raw_data_r_reg[25]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => raw_data_srl_out(25), Q => \raw_data_r_reg_n_0_[25]\, R => '0' ); \raw_data_r_reg[26]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => raw_data_srl_out(26), Q => \raw_data_r_reg_n_0_[26]\, R => '0' ); \raw_data_r_reg[27]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => raw_data_srl_out(27), Q => \raw_data_r_reg_n_0_[27]\, R => '0' ); \raw_data_r_reg[28]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => raw_data_srl_out(28), Q => \raw_data_r_reg_n_0_[28]\, R => '0' ); \raw_data_r_reg[29]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => raw_data_srl_out(29), Q => \raw_data_r_reg_n_0_[29]\, R => '0' ); \raw_data_r_reg[2]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => raw_data_srl_out(2), Q => \raw_data_r_reg_n_0_[2]\, R => '0' ); \raw_data_r_reg[30]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => raw_data_srl_out(30), Q => \raw_data_r_reg_n_0_[30]\, R => '0' ); \raw_data_r_reg[31]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => raw_data_srl_out(31), Q => \raw_data_r_reg_n_0_[31]\, R => '0' ); \raw_data_r_reg[32]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => raw_data_srl_out(32), Q => \raw_data_r_reg_n_0_[32]\, R => '0' ); \raw_data_r_reg[33]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => raw_data_srl_out(33), Q => \raw_data_r_reg_n_0_[33]\, R => '0' ); \raw_data_r_reg[34]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => raw_data_srl_out(34), Q => p_1_in, R => '0' ); \raw_data_r_reg[3]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => raw_data_srl_out(3), Q => \raw_data_r_reg_n_0_[3]\, R => '0' ); \raw_data_r_reg[4]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => raw_data_srl_out(4), Q => \raw_data_r_reg_n_0_[4]\, R => '0' ); \raw_data_r_reg[5]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => raw_data_srl_out(5), Q => \raw_data_r_reg_n_0_[5]\, R => '0' ); \raw_data_r_reg[6]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => raw_data_srl_out(6), Q => \raw_data_r_reg_n_0_[6]\, R => '0' ); \raw_data_r_reg[7]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => raw_data_srl_out(7), Q => \raw_data_r_reg_n_0_[7]\, R => '0' ); \raw_data_r_reg[8]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => raw_data_srl_out(8), Q => \raw_data_r_reg_n_0_[8]\, R => '0' ); \raw_data_r_reg[9]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => raw_data_srl_out(9), Q => \raw_data_r_reg_n_0_[9]\, R => '0' ); rd_err_pre_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg, CE => '1', D => rd_err_c, Q => rd_err_pre, R => do_rd_en ); rd_err_q_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg, CE => '1', D => rd_err_pre, Q => rxbuferr_out_i(0), R => do_rd_en ); rxfsm_reset_i_inferred_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => \rx_state_reg[7]_0\, I1 => \rx_state_reg[7]\, I2 => hard_err_rst_int, I3 => link_reset_0_c, O => rxfsm_reset_i ); \srlc32e[0].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => \out\, D => UNSCRAMBLED_DATA_OUT(0), Q => raw_data_srl_out(0), Q31 => \NLW_srlc32e[0].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[10].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => \out\, D => UNSCRAMBLED_DATA_OUT(10), Q => raw_data_srl_out(10), Q31 => \NLW_srlc32e[10].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[11].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => \out\, D => UNSCRAMBLED_DATA_OUT(11), Q => raw_data_srl_out(11), Q31 => \NLW_srlc32e[11].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[12].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => \out\, D => UNSCRAMBLED_DATA_OUT(12), Q => raw_data_srl_out(12), Q31 => \NLW_srlc32e[12].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[13].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => \out\, D => UNSCRAMBLED_DATA_OUT(13), Q => raw_data_srl_out(13), Q31 => \NLW_srlc32e[13].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[14].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => \out\, D => UNSCRAMBLED_DATA_OUT(14), Q => raw_data_srl_out(14), Q31 => \NLW_srlc32e[14].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[15].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => \out\, D => UNSCRAMBLED_DATA_OUT(15), Q => raw_data_srl_out(15), Q31 => \NLW_srlc32e[15].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[16].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => \out\, D => UNSCRAMBLED_DATA_OUT(16), Q => raw_data_srl_out(16), Q31 => \NLW_srlc32e[16].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[17].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => \out\, D => UNSCRAMBLED_DATA_OUT(17), Q => raw_data_srl_out(17), Q31 => \NLW_srlc32e[17].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[18].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => \out\, D => UNSCRAMBLED_DATA_OUT(18), Q => raw_data_srl_out(18), Q31 => \NLW_srlc32e[18].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[19].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => \out\, D => UNSCRAMBLED_DATA_OUT(19), Q => raw_data_srl_out(19), Q31 => \NLW_srlc32e[19].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[1].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => \out\, D => UNSCRAMBLED_DATA_OUT(1), Q => raw_data_srl_out(1), Q31 => \NLW_srlc32e[1].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[20].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => \out\, D => UNSCRAMBLED_DATA_OUT(20), Q => raw_data_srl_out(20), Q31 => \NLW_srlc32e[20].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[21].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => \out\, D => UNSCRAMBLED_DATA_OUT(21), Q => raw_data_srl_out(21), Q31 => \NLW_srlc32e[21].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[22].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => \out\, D => UNSCRAMBLED_DATA_OUT(22), Q => raw_data_srl_out(22), Q31 => \NLW_srlc32e[22].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[23].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => \out\, D => UNSCRAMBLED_DATA_OUT(23), Q => raw_data_srl_out(23), Q31 => \NLW_srlc32e[23].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[24].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => \out\, D => UNSCRAMBLED_DATA_OUT(24), Q => raw_data_srl_out(24), Q31 => \NLW_srlc32e[24].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[25].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => \out\, D => UNSCRAMBLED_DATA_OUT(25), Q => raw_data_srl_out(25), Q31 => \NLW_srlc32e[25].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[26].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => \out\, D => UNSCRAMBLED_DATA_OUT(26), Q => raw_data_srl_out(26), Q31 => \NLW_srlc32e[26].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[27].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => \out\, D => UNSCRAMBLED_DATA_OUT(27), Q => raw_data_srl_out(27), Q31 => \NLW_srlc32e[27].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[28].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => \out\, D => UNSCRAMBLED_DATA_OUT(28), Q => raw_data_srl_out(28), Q31 => \NLW_srlc32e[28].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[29].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => \out\, D => UNSCRAMBLED_DATA_OUT(29), Q => raw_data_srl_out(29), Q31 => \NLW_srlc32e[29].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[2].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => \out\, D => UNSCRAMBLED_DATA_OUT(2), Q => raw_data_srl_out(2), Q31 => \NLW_srlc32e[2].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[30].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => \out\, D => UNSCRAMBLED_DATA_OUT(30), Q => raw_data_srl_out(30), Q31 => \NLW_srlc32e[30].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[31].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => \out\, D => UNSCRAMBLED_DATA_OUT(31), Q => raw_data_srl_out(31), Q31 => \NLW_srlc32e[31].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[32].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => \out\, D => Q(0), Q => raw_data_srl_out(32), Q31 => \NLW_srlc32e[32].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[33].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => \out\, D => Q(1), Q => raw_data_srl_out(33), Q31 => \NLW_srlc32e[33].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[34].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => \out\, D => rxdatavalid_to_fifo_i, Q => raw_data_srl_out(34), Q31 => \NLW_srlc32e[34].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[3].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => \out\, D => UNSCRAMBLED_DATA_OUT(3), Q => raw_data_srl_out(3), Q31 => \NLW_srlc32e[3].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[4].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => \out\, D => UNSCRAMBLED_DATA_OUT(4), Q => raw_data_srl_out(4), Q31 => \NLW_srlc32e[4].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[5].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => \out\, D => UNSCRAMBLED_DATA_OUT(5), Q => raw_data_srl_out(5), Q31 => \NLW_srlc32e[5].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[6].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => \out\, D => UNSCRAMBLED_DATA_OUT(6), Q => raw_data_srl_out(6), Q31 => \NLW_srlc32e[6].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[7].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => \out\, D => UNSCRAMBLED_DATA_OUT(7), Q => raw_data_srl_out(7), Q31 => \NLW_srlc32e[7].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[8].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => \out\, D => UNSCRAMBLED_DATA_OUT(8), Q => raw_data_srl_out(8), Q31 => \NLW_srlc32e[8].SRLC32E_inst_1_Q31_UNCONNECTED\ ); \srlc32e[9].SRLC32E_inst_1\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => \out\, D => UNSCRAMBLED_DATA_OUT(9), Q => raw_data_srl_out(9), Q31 => \NLW_srlc32e[9].SRLC32E_inst_1_Q31_UNCONNECTED\ ); u_cdc_overflow_flag_c: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized3\ port map ( cbcc_reset_cbstg2_rd_clk => cbcc_reset_cbstg2_rd_clk, overflow_flag_c => overflow_flag_c, s_level_out_d6_reg_0 => s_level_out_d6_reg ); u_cdc_rxlossofsync_in: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized1_34\ port map ( CC_RXLOSSOFSYNC_OUT_reg => CC_RXLOSSOFSYNC_OUT_reg_0, in0 => in0, s_level_out_d5_reg_0 => u_cdc_rxlossofsync_in_n_0, s_level_out_d6_reg_0 => s_level_out_d6_reg ); u_cdc_wr_err_rd_clk: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized3_35\ port map ( cbcc_fifo_reset_rd_clk => cbcc_fifo_reset_rd_clk, \out\ => wr_err_rd_clk_pre, s_level_out_d6_reg_0 => s_level_out_d6_reg, wr_err_c => wr_err_c ); u_rst_sync_btf_sync: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_36\ port map ( in0 => valid_btf_detect_extend_r2, stg3_reg_0 => u_rst_sync_btf_sync_n_0, stg3_reg_1 => stg3_reg ); underflow_flag_r1_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => underflow_flag_c, I1 => buffer_too_empty_c, O => underflow_flag_r10 ); underflow_flag_r1_reg: unisim.vcomponents.FDSE port map ( C => s_level_out_d6_reg, CE => '1', D => underflow_flag_r10, Q => underflow_flag_r1, S => cbcc_fifo_reset_rd_clk ); underflow_flag_r2_reg: unisim.vcomponents.FDSE port map ( C => s_level_out_d6_reg, CE => '1', D => underflow_flag_r1, Q => underflow_flag_r2, S => cbcc_fifo_reset_rd_clk ); underflow_flag_r3_reg: unisim.vcomponents.FDSE port map ( C => s_level_out_d6_reg, CE => '1', D => underflow_flag_r2, Q => underflow_flag_r3, S => cbcc_fifo_reset_rd_clk ); valid_btf_detect_dlyd1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg3_reg, CE => '1', D => u_rst_sync_btf_sync_n_0, Q => valid_btf_detect_dlyd1, R => '0' ); valid_btf_detect_extend_r20: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFFFE" ) port map ( I0 => valid_btf_detect_extend_r(0), I1 => valid_btf_detect_extend_r(3), I2 => valid_btf_detect_extend_r(4), I3 => valid_btf_detect_extend_r(1), I4 => valid_btf_detect_extend_r(2), O => valid_btf_detect_extend_r20_n_0 ); valid_btf_detect_extend_r2_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => valid_btf_detect_extend_r20_n_0, Q => valid_btf_detect_extend_r2, R => '0' ); \valid_btf_detect_extend_r_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => valid_btf_detect_extend_r(1), Q => valid_btf_detect_extend_r(0), R => \valid_btf_detect_extend_r_reg[4]_0\(0) ); \valid_btf_detect_extend_r_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => valid_btf_detect_extend_r(2), Q => valid_btf_detect_extend_r(1), R => \valid_btf_detect_extend_r_reg[4]_0\(0) ); \valid_btf_detect_extend_r_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => valid_btf_detect_extend_r(3), Q => valid_btf_detect_extend_r(2), R => \valid_btf_detect_extend_r_reg[4]_0\(0) ); \valid_btf_detect_extend_r_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => valid_btf_detect_extend_r(4), Q => valid_btf_detect_extend_r(3), R => \valid_btf_detect_extend_r_reg[4]_0\(0) ); \valid_btf_detect_extend_r_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => valid_btf_detect, Q => valid_btf_detect_extend_r(4), R => \valid_btf_detect_extend_r_reg[4]_0\(0) ); valid_btf_detect_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => CC_detect, Q => valid_btf_detect, R => '0' ); \wait_for_rd_en[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"87" ) port map ( I0 => wait_for_rd_en(2), I1 => wait_for_rd_en(1), I2 => wait_for_rd_en(0), O => \wait_for_rd_en[0]_i_1_n_0\ ); \wait_for_rd_en[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"E6" ) port map ( I0 => wait_for_rd_en(0), I1 => wait_for_rd_en(1), I2 => wait_for_rd_en(2), O => \wait_for_rd_en[1]_i_1_n_0\ ); \wait_for_rd_en[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"F8" ) port map ( I0 => wait_for_rd_en(0), I1 => wait_for_rd_en(1), I2 => wait_for_rd_en(2), O => \wait_for_rd_en[2]_i_1_n_0\ ); \wait_for_rd_en_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_level_out_d6_reg, CE => '1', D => \wait_for_rd_en[0]_i_1_n_0\, Q => wait_for_rd_en(0), R => cbcc_fifo_reset_rd_clk ); \wait_for_rd_en_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_level_out_d6_reg, CE => '1', D => \wait_for_rd_en[1]_i_1_n_0\, Q => wait_for_rd_en(1), R => cbcc_fifo_reset_rd_clk ); \wait_for_rd_en_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_level_out_d6_reg, CE => '1', D => \wait_for_rd_en[2]_i_1_n_0\, Q => wait_for_rd_en(2), R => cbcc_fifo_reset_rd_clk ); \wait_for_wr_en[0]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => wait_for_wr_en(1), I1 => wait_for_wr_en(0), O => \wait_for_wr_en[0]_i_1_n_0\ ); \wait_for_wr_en[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => wait_for_wr_en(1), I1 => wait_for_wr_en(0), O => \wait_for_wr_en[1]_i_1_n_0\ ); \wait_for_wr_en_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => \wait_for_wr_en[0]_i_1_n_0\, Q => wait_for_wr_en(0), R => cbcc_fifo_reset_wr_clk ); \wait_for_wr_en_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => \wait_for_wr_en[1]_i_1_n_0\, Q => wait_for_wr_en(1), R => cbcc_fifo_reset_wr_clk ); \wait_for_wr_en_wr3_reg[0]_srl3\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => \out\, D => wait_for_wr_en(0), Q => \wait_for_wr_en_wr3_reg[0]_srl3_n_0\ ); \wait_for_wr_en_wr3_reg[1]_srl3\: unisim.vcomponents.SRL16E generic map( INIT => X"0000" ) port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => \out\, D => wait_for_wr_en(1), Q => \wait_for_wr_en_wr3_reg[1]_srl3_n_0\ ); \wait_for_wr_en_wr4_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => \wait_for_wr_en_wr3_reg[0]_srl3_n_0\, Q => wait_for_wr_en_wr4(0), R => '0' ); \wait_for_wr_en_wr4_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => \wait_for_wr_en_wr3_reg[1]_srl3_n_0\, Q => wait_for_wr_en_wr4(1), R => '0' ); \wdth_conv_1stage[39]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFAA808080" ) port map ( I0 => do_wr_en_reg_0, I1 => p_1_in, I2 => first_cb_to_write_to_fifo_dlyd, I3 => p_0_in0_in, I4 => cb_fifo_din_detect_q, I5 => do_wr_en, O => mod_do_wr_en ); \wdth_conv_1stage_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[0]\, Q => wdth_conv_1stage(0), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_1stage_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[10]\, Q => wdth_conv_1stage(10), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_1stage_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[11]\, Q => wdth_conv_1stage(11), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_1stage_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[12]\, Q => wdth_conv_1stage(12), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_1stage_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[13]\, Q => wdth_conv_1stage(13), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_1stage_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[14]\, Q => wdth_conv_1stage(14), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_1stage_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[15]\, Q => wdth_conv_1stage(15), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_1stage_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[16]\, Q => wdth_conv_1stage(16), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_1stage_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[17]\, Q => wdth_conv_1stage(17), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_1stage_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[18]\, Q => wdth_conv_1stage(18), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_1stage_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[19]\, Q => wdth_conv_1stage(19), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_1stage_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[1]\, Q => wdth_conv_1stage(1), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_1stage_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[20]\, Q => wdth_conv_1stage(20), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_1stage_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[21]\, Q => wdth_conv_1stage(21), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_1stage_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[22]\, Q => wdth_conv_1stage(22), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_1stage_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[23]\, Q => wdth_conv_1stage(23), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_1stage_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[24]\, Q => wdth_conv_1stage(24), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_1stage_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[25]\, Q => wdth_conv_1stage(25), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_1stage_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[26]\, Q => wdth_conv_1stage(26), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_1stage_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[27]\, Q => wdth_conv_1stage(27), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_1stage_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[28]\, Q => wdth_conv_1stage(28), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_1stage_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[29]\, Q => wdth_conv_1stage(29), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_1stage_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[2]\, Q => wdth_conv_1stage(2), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_1stage_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[30]\, Q => wdth_conv_1stage(30), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_1stage_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[31]\, Q => wdth_conv_1stage(31), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_1stage_reg[32]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[32]\, Q => wdth_conv_1stage(32), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_1stage_reg[33]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[33]\, Q => wdth_conv_1stage(33), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_1stage_reg[34]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => mod_do_wr_en, D => rxdatavalid_lookahead_i, Q => wdth_conv_1stage(34), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_1stage_reg[35]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => mod_do_wr_en, D => CC_detect_pulse_r, Q => wdth_conv_1stage(35), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_1stage_reg[36]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => mod_do_wr_en, D => p_0_in0_in, Q => wdth_conv_1stage(36), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_1stage_reg[37]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => mod_do_wr_en, D => CB_detect_dlyd1, Q => wdth_conv_1stage(37), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_1stage_reg[38]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => mod_do_wr_en, D => D(0), Q => wdth_conv_1stage(38), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_1stage_reg[39]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => mod_do_wr_en, D => D(1), Q => wdth_conv_1stage(39), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_1stage_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[3]\, Q => wdth_conv_1stage(3), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_1stage_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[4]\, Q => wdth_conv_1stage(4), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_1stage_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[5]\, Q => wdth_conv_1stage(5), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_1stage_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[6]\, Q => wdth_conv_1stage(6), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_1stage_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[7]\, Q => wdth_conv_1stage(7), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_1stage_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[8]\, Q => wdth_conv_1stage(8), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_1stage_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => mod_do_wr_en, D => \raw_data_r_r_reg_n_0_[9]\, Q => wdth_conv_1stage(9), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_2stage_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_1stage(0), Q => en32_fifo_din_i(0), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_2stage_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_1stage(10), Q => en32_fifo_din_i(10), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_2stage_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_1stage(11), Q => en32_fifo_din_i(11), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_2stage_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_1stage(12), Q => en32_fifo_din_i(12), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_2stage_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_1stage(13), Q => en32_fifo_din_i(13), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_2stage_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_1stage(14), Q => en32_fifo_din_i(14), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_2stage_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_1stage(15), Q => en32_fifo_din_i(15), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_2stage_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_1stage(16), Q => en32_fifo_din_i(16), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_2stage_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_1stage(17), Q => en32_fifo_din_i(17), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_2stage_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_1stage(18), Q => en32_fifo_din_i(18), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_2stage_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_1stage(19), Q => en32_fifo_din_i(19), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_2stage_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_1stage(1), Q => en32_fifo_din_i(1), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_2stage_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_1stage(20), Q => en32_fifo_din_i(20), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_2stage_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_1stage(21), Q => en32_fifo_din_i(21), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_2stage_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_1stage(22), Q => en32_fifo_din_i(22), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_2stage_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_1stage(23), Q => en32_fifo_din_i(23), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_2stage_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_1stage(24), Q => en32_fifo_din_i(24), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_2stage_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_1stage(25), Q => en32_fifo_din_i(25), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_2stage_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_1stage(26), Q => en32_fifo_din_i(26), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_2stage_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_1stage(27), Q => en32_fifo_din_i(27), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_2stage_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_1stage(28), Q => en32_fifo_din_i(28), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_2stage_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_1stage(29), Q => en32_fifo_din_i(29), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_2stage_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_1stage(2), Q => en32_fifo_din_i(2), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_2stage_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_1stage(30), Q => en32_fifo_din_i(30), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_2stage_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_1stage(31), Q => en32_fifo_din_i(31), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_2stage_reg[32]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_1stage(32), Q => wdth_conv_2stage(32), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_2stage_reg[33]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_1stage(33), Q => wdth_conv_2stage(33), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_2stage_reg[34]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_1stage(34), Q => wdth_conv_2stage(34), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_2stage_reg[35]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_1stage(35), Q => wdth_conv_2stage(35), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_2stage_reg[36]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_1stage(36), Q => wdth_conv_2stage(36), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_2stage_reg[37]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_1stage(37), Q => wdth_conv_2stage(37), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_2stage_reg[38]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_1stage(38), Q => wdth_conv_2stage(38), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_2stage_reg[39]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_1stage(39), Q => wdth_conv_2stage(39), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_2stage_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_1stage(3), Q => en32_fifo_din_i(3), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_2stage_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_1stage(4), Q => en32_fifo_din_i(4), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_2stage_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_1stage(5), Q => en32_fifo_din_i(5), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_2stage_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_1stage(6), Q => en32_fifo_din_i(6), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_2stage_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_1stage(7), Q => en32_fifo_din_i(7), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_2stage_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_1stage(8), Q => en32_fifo_din_i(8), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_2stage_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_1stage(9), Q => en32_fifo_din_i(9), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_3stage_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => en32_fifo_din_i(0), Q => en32_fifo_din_i(40), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_3stage_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => en32_fifo_din_i(10), Q => en32_fifo_din_i(50), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_3stage_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => en32_fifo_din_i(11), Q => en32_fifo_din_i(51), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_3stage_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => en32_fifo_din_i(12), Q => en32_fifo_din_i(52), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_3stage_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => en32_fifo_din_i(13), Q => en32_fifo_din_i(53), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_3stage_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => en32_fifo_din_i(14), Q => en32_fifo_din_i(54), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_3stage_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => en32_fifo_din_i(15), Q => en32_fifo_din_i(55), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_3stage_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => en32_fifo_din_i(16), Q => en32_fifo_din_i(56), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_3stage_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => en32_fifo_din_i(17), Q => en32_fifo_din_i(57), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_3stage_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => en32_fifo_din_i(18), Q => en32_fifo_din_i(58), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_3stage_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => en32_fifo_din_i(19), Q => en32_fifo_din_i(59), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_3stage_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => en32_fifo_din_i(1), Q => en32_fifo_din_i(41), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_3stage_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => en32_fifo_din_i(20), Q => en32_fifo_din_i(60), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_3stage_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => en32_fifo_din_i(21), Q => en32_fifo_din_i(61), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_3stage_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => en32_fifo_din_i(22), Q => en32_fifo_din_i(62), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_3stage_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => en32_fifo_din_i(23), Q => en32_fifo_din_i(63), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_3stage_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => en32_fifo_din_i(24), Q => en32_fifo_din_i(64), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_3stage_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => en32_fifo_din_i(25), Q => en32_fifo_din_i(65), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_3stage_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => en32_fifo_din_i(26), Q => en32_fifo_din_i(66), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_3stage_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => en32_fifo_din_i(27), Q => en32_fifo_din_i(67), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_3stage_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => en32_fifo_din_i(28), Q => en32_fifo_din_i(68), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_3stage_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => en32_fifo_din_i(29), Q => en32_fifo_din_i(69), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_3stage_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => en32_fifo_din_i(2), Q => en32_fifo_din_i(42), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_3stage_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => en32_fifo_din_i(30), Q => en32_fifo_din_i(70), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_3stage_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => en32_fifo_din_i(31), Q => en32_fifo_din_i(71), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_3stage_reg[32]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_2stage(32), Q => en32_fifo_din_i(72), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_3stage_reg[33]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_2stage(33), Q => en32_fifo_din_i(73), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_3stage_reg[34]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_2stage(34), Q => en32_fifo_din_i(74), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_3stage_reg[35]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_2stage(35), Q => en32_fifo_din_i(75), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_3stage_reg[36]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_2stage(36), Q => en32_fifo_din_i(76), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_3stage_reg[37]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_2stage(37), Q => en32_fifo_din_i(77), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_3stage_reg[38]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_2stage(38), Q => en32_fifo_din_i(78), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_3stage_reg[39]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => wdth_conv_2stage(39), Q => en32_fifo_din_i(79), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_3stage_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => en32_fifo_din_i(3), Q => en32_fifo_din_i(43), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_3stage_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => en32_fifo_din_i(4), Q => en32_fifo_din_i(44), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_3stage_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => en32_fifo_din_i(5), Q => en32_fifo_din_i(45), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_3stage_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => en32_fifo_din_i(6), Q => en32_fifo_din_i(46), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_3stage_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => en32_fifo_din_i(7), Q => en32_fifo_din_i(47), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_3stage_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => en32_fifo_din_i(8), Q => en32_fifo_din_i(48), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_3stage_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => en32_fifo_din_i(9), Q => en32_fifo_din_i(49), R => cbcc_fifo_reset_wr_clk ); \wdth_conv_count[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"1E" ) port map ( I0 => do_wr_en, I1 => \wdth_conv_count[0]_i_2_n_0\, I2 => \wdth_conv_count_reg_n_0_[0]\, O => \wdth_conv_count[0]_i_1_n_0\ ); \wdth_conv_count[0]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"F8880000" ) port map ( I0 => cb_fifo_din_detect_q, I1 => p_0_in0_in, I2 => first_cb_to_write_to_fifo_dlyd, I3 => p_1_in, I4 => do_wr_en_reg_0, O => \wdth_conv_count[0]_i_2_n_0\ ); \wdth_conv_count[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"A888" ) port map ( I0 => \wdth_conv_count_reg_n_0_[0]\, I1 => do_wr_en, I2 => do_wr_en_reg_0, I3 => \wdth_conv_count[1]_i_2_n_0\, O => \wdth_conv_count[1]_i_1_n_0\ ); \wdth_conv_count[1]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"F888" ) port map ( I0 => p_1_in, I1 => first_cb_to_write_to_fifo_dlyd, I2 => p_0_in0_in, I3 => cb_fifo_din_detect_q, O => \wdth_conv_count[1]_i_2_n_0\ ); \wdth_conv_count_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => \wdth_conv_count[0]_i_1_n_0\, Q => \wdth_conv_count_reg_n_0_[0]\, R => any_vld_btf_fifo_din_detect_dlyd_i_1_n_0 ); \wdth_conv_count_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => \wdth_conv_count[1]_i_1_n_0\, Q => bit80_prsnt, R => any_vld_btf_fifo_din_detect_dlyd_i_1_n_0 ); wr_err_rd_clk_sync_reg: unisim.vcomponents.FDRE port map ( C => s_level_out_d6_reg, CE => '1', D => wr_err_rd_clk_pre, Q => rxbuferr_out_i(1), R => do_rd_en ); \wr_monitor_flag[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \wr_monitor_flag_reg__0\(0), O => \p_0_in__6\(0) ); \wr_monitor_flag[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \wr_monitor_flag_reg__0\(0), I1 => \wr_monitor_flag_reg__0\(1), O => \p_0_in__6\(1) ); \wr_monitor_flag[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \wr_monitor_flag_reg__0\(0), I1 => \wr_monitor_flag_reg__0\(1), I2 => \wr_monitor_flag_reg__0\(2), O => \p_0_in__6\(2) ); \wr_monitor_flag[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \wr_monitor_flag_reg__0\(2), I1 => \wr_monitor_flag_reg__0\(1), I2 => \wr_monitor_flag_reg__0\(0), I3 => \wr_monitor_flag_reg__0\(3), O => \p_0_in__6\(3) ); \wr_monitor_flag[4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0404040404444444" ) port map ( I0 => \wr_monitor_flag_reg__0\(4), I1 => new_do_wr_en, I2 => \wr_monitor_flag_reg__0\(3), I3 => \wr_monitor_flag_reg__0\(0), I4 => \wr_monitor_flag_reg__0\(1), I5 => \wr_monitor_flag_reg__0\(2), O => wr_monitor_flag ); \wr_monitor_flag[4]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"8000" ) port map ( I0 => \wr_monitor_flag_reg__0\(2), I1 => \wr_monitor_flag_reg__0\(1), I2 => \wr_monitor_flag_reg__0\(0), I3 => \wr_monitor_flag_reg__0\(3), O => \p_0_in__6\(4) ); \wr_monitor_flag_reg[0]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => wr_monitor_flag, D => \p_0_in__6\(0), Q => \wr_monitor_flag_reg__0\(0), R => SR(0) ); \wr_monitor_flag_reg[1]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => wr_monitor_flag, D => \p_0_in__6\(1), Q => \wr_monitor_flag_reg__0\(1), R => SR(0) ); \wr_monitor_flag_reg[2]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => wr_monitor_flag, D => \p_0_in__6\(2), Q => \wr_monitor_flag_reg__0\(2), R => SR(0) ); \wr_monitor_flag_reg[3]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => wr_monitor_flag, D => \p_0_in__6\(3), Q => \wr_monitor_flag_reg__0\(3), R => SR(0) ); \wr_monitor_flag_reg[4]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => wr_monitor_flag, D => \p_0_in__6\(4), Q => \wr_monitor_flag_reg__0\(4), R => SR(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_GLOBAL_LOGIC is port ( SR : out STD_LOGIC_VECTOR ( 0 to 0 ); gen_na_idles_i : out STD_LOGIC; gen_ch_bond_i : out STD_LOGIC; CHANNEL_UP_RX_IF_reg : out STD_LOGIC; channel_up_tx_if : out STD_LOGIC; hard_err : out STD_LOGIC; gen_ch_bond_int_reg : out STD_LOGIC; CHANNEL_UP_RX_IF_reg_0 : out STD_LOGIC; gen_cc_flop_0_i : out STD_LOGIC_VECTOR ( 1 downto 0 ); E : out STD_LOGIC_VECTOR ( 0 to 0 ); CHANNEL_UP_RX_IF_reg_1 : out STD_LOGIC; R0 : out STD_LOGIC; reset_lanes_c : in STD_LOGIC; \out\ : in STD_LOGIC; wait_for_lane_up_r_reg : in STD_LOGIC; remote_ready_i : in STD_LOGIC; RX_IDLE : in STD_LOGIC; CHANNEL_UP_RX_IF_reg_2 : in STD_LOGIC_VECTOR ( 0 to 0 ); TXDATAVALID_IN : in STD_LOGIC; hard_err_i : in STD_LOGIC; \TX_DATA_reg[63]\ : in STD_LOGIC; gen_cc_i : in STD_LOGIC; tx_pe_data_v_i : in STD_LOGIC; ready_r_reg : in STD_LOGIC; rx_pe_data_v_i : in STD_LOGIC; rst_pma_init_usrclk : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 1 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_GLOBAL_LOGIC; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_GLOBAL_LOGIC is signal \^channel_up_tx_if\ : STD_LOGIC; signal \^gen_ch_bond_i\ : STD_LOGIC; begin channel_up_tx_if <= \^channel_up_tx_if\; gen_ch_bond_i <= \^gen_ch_bond_i\; channel_bond_gen_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_CHANNEL_BOND_GEN port map ( TXDATAVALID_IN => TXDATAVALID_IN, \free_count_r_reg[4]_0\(0) => CHANNEL_UP_RX_IF_reg_2(0), gen_ch_bond_int_reg_0 => \^gen_ch_bond_i\, gen_ch_bond_int_reg_1 => \^channel_up_tx_if\, \out\ => \out\ ); channel_err_detect_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_CHANNEL_ERR_DETECT port map ( hard_err => hard_err, hard_err_i => hard_err_i, \out\ => \out\ ); channel_init_sm_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_CHANNEL_INIT_SM port map ( CHANNEL_UP_RX_IF_reg_0 => CHANNEL_UP_RX_IF_reg, CHANNEL_UP_RX_IF_reg_1 => CHANNEL_UP_RX_IF_reg_0, CHANNEL_UP_RX_IF_reg_2 => CHANNEL_UP_RX_IF_reg_1, CHANNEL_UP_RX_IF_reg_3(0) => CHANNEL_UP_RX_IF_reg_2(0), CHANNEL_UP_TX_IF_reg_0 => \^channel_up_tx_if\, E(0) => E(0), Q(1 downto 0) => Q(1 downto 0), R0 => R0, RX_IDLE => RX_IDLE, SR(0) => SR(0), \TX_DATA_reg[63]\ => \TX_DATA_reg[63]\, \TX_DATA_reg[63]_0\ => \^gen_ch_bond_i\, gen_cc_flop_0_i(1 downto 0) => gen_cc_flop_0_i(1 downto 0), gen_cc_i => gen_cc_i, gen_ch_bond_int_reg => gen_ch_bond_int_reg, \out\ => \out\, ready_r_reg_0 => ready_r_reg, remote_ready_i => remote_ready_i, reset_lanes_c => reset_lanes_c, rst_pma_init_usrclk => rst_pma_init_usrclk, rx_pe_data_v_i => rx_pe_data_v_i, tx_pe_data_v_i => tx_pe_data_v_i, wait_for_lane_up_r_reg_0(0) => gen_na_idles_i, wait_for_lane_up_r_reg_1 => wait_for_lane_up_r_reg ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_LANE_INIT_SM is port ( lane_up_flop_i_0 : out STD_LOGIC; rst_r_reg_0 : out STD_LOGIC; enable_err_detect_i : out STD_LOGIC; rx_polarity_r_reg_0 : out STD_LOGIC; check_polarity_r_reg_0 : out STD_LOGIC; reset_lanes_c : out STD_LOGIC; s_level_out_d1_aurora_64b66b_0_cdc_to_reg : in STD_LOGIC; \out\ : in STD_LOGIC; SR : in STD_LOGIC_VECTOR ( 0 to 0 ); reset_count_r0 : in STD_LOGIC; ready_r_reg0 : in STD_LOGIC; rx_lossofsync_i : in STD_LOGIC; reset_lanes_i : in STD_LOGIC; gen_na_idles_i : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_LANE_INIT_SM; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_LANE_INIT_SM is signal align_r : STD_LOGIC; signal align_r_i_2_n_0 : STD_LOGIC; signal begin_r : STD_LOGIC; signal check_polarity_r_i_1_n_0 : STD_LOGIC; signal \^check_polarity_r_reg_0\ : STD_LOGIC; signal count_8d_done_r : STD_LOGIC; signal \counter1_r_reg_n_0_[1]\ : STD_LOGIC; signal \counter1_r_reg_n_0_[2]\ : STD_LOGIC; signal \counter1_r_reg_n_0_[3]\ : STD_LOGIC; signal \^lane_up_flop_i_0\ : STD_LOGIC; signal next_align_c : STD_LOGIC; signal next_begin_c : STD_LOGIC; signal \next_begin_c_inferred__1/i__n_0\ : STD_LOGIC; signal next_polarity_c : STD_LOGIC; signal next_ready_c : STD_LOGIC; signal next_rst_c : STD_LOGIC; signal p_0_in : STD_LOGIC_VECTOR ( 3 downto 0 ); signal polarity_r : STD_LOGIC; signal prev_rx_polarity_r : STD_LOGIC; signal prev_rx_polarity_r_i_1_n_0 : STD_LOGIC; signal ready_r : STD_LOGIC; signal ready_r_i_4_n_0 : STD_LOGIC; signal reset_count_r : STD_LOGIC; signal rst_r_i_2_n_0 : STD_LOGIC; signal \^rst_r_reg_0\ : STD_LOGIC; signal rx_polarity_dlyd_i : STD_LOGIC; signal \^rx_polarity_r_reg_0\ : STD_LOGIC; signal u_cdc_rxlossofsync_in_n_2 : STD_LOGIC; signal NLW_SRLC32E_inst_0_Q31_UNCONNECTED : STD_LOGIC; attribute BOX_TYPE : string; attribute BOX_TYPE of SRLC32E_inst_0 : label is "PRIMITIVE"; attribute srl_name : string; attribute srl_name of SRLC32E_inst_0 : label is "inst/\aurora_64b66b_0_core_i/aurora_lane_0_i/lane_init_sm_i/SRLC32E_inst_0 "; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of align_r_i_2 : label is "soft_lutpair84"; attribute SOFT_HLUTNM of \counter1_r[0]_i_1\ : label is "soft_lutpair86"; attribute SOFT_HLUTNM of \counter1_r[1]_i_1\ : label is "soft_lutpair86"; attribute BOX_TYPE of lane_up_flop_i : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of lane_up_flop_i : label is "FDR"; attribute SOFT_HLUTNM of \next_begin_c_inferred__1/i_\ : label is "soft_lutpair85"; attribute SOFT_HLUTNM of rst_r_i_1 : label is "soft_lutpair84"; attribute SOFT_HLUTNM of rst_r_i_2 : label is "soft_lutpair85"; begin check_polarity_r_reg_0 <= \^check_polarity_r_reg_0\; lane_up_flop_i_0 <= \^lane_up_flop_i_0\; rst_r_reg_0 <= \^rst_r_reg_0\; rx_polarity_r_reg_0 <= \^rx_polarity_r_reg_0\; ENABLE_ERR_DETECT_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => ready_r, Q => enable_err_detect_i, R => '0' ); SRLC32E_inst_0: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000", IS_CLK_INVERTED => '0' ) port map ( A(4 downto 0) => B"00100", CE => '1', CLK => \out\, D => polarity_r, Q => rx_polarity_dlyd_i, Q31 => NLW_SRLC32E_inst_0_Q31_UNCONNECTED ); align_r_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"00000C0000000A0A" ) port map ( I0 => align_r_i_2_n_0, I1 => ready_r_i_4_n_0, I2 => ready_r, I3 => rx_lossofsync_i, I4 => polarity_r, I5 => align_r, O => next_align_c ); align_r_i_2: unisim.vcomponents.LUT4 generic map( INIT => X"0040" ) port map ( I0 => begin_r, I1 => \^rst_r_reg_0\, I2 => count_8d_done_r, I3 => reset_lanes_i, O => align_r_i_2_n_0 ); align_r_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => next_align_c, Q => align_r, R => ready_r_reg0 ); begin_r_reg: unisim.vcomponents.FDSE port map ( C => \out\, CE => '1', D => next_begin_c, Q => begin_r, S => ready_r_reg0 ); check_polarity_r_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"BA" ) port map ( I0 => polarity_r, I1 => rx_polarity_dlyd_i, I2 => \^check_polarity_r_reg_0\, O => check_polarity_r_i_1_n_0 ); check_polarity_r_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => check_polarity_r_i_1_n_0, Q => \^check_polarity_r_reg_0\, R => SR(0) ); \counter1_r[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \counter1_r_reg_n_0_[1]\, I1 => \counter1_r_reg_n_0_[3]\, I2 => \counter1_r_reg_n_0_[2]\, I3 => count_8d_done_r, O => p_0_in(3) ); \counter1_r[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \counter1_r_reg_n_0_[2]\, I1 => \counter1_r_reg_n_0_[3]\, I2 => \counter1_r_reg_n_0_[1]\, O => p_0_in(2) ); \counter1_r[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \counter1_r_reg_n_0_[3]\, I1 => \counter1_r_reg_n_0_[2]\, O => p_0_in(1) ); \counter1_r[3]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \counter1_r_reg_n_0_[3]\, O => p_0_in(0) ); \counter1_r_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => p_0_in(3), Q => count_8d_done_r, R => reset_count_r ); \counter1_r_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => p_0_in(2), Q => \counter1_r_reg_n_0_[1]\, R => reset_count_r ); \counter1_r_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => p_0_in(1), Q => \counter1_r_reg_n_0_[2]\, R => reset_count_r ); \counter1_r_reg[3]\: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => p_0_in(0), Q => \counter1_r_reg_n_0_[3]\, S => reset_count_r ); lane_up_flop_i: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => ready_r, Q => \^lane_up_flop_i_0\, R => SR(0) ); \next_begin_c_inferred__1/i_\: unisim.vcomponents.LUT5 generic map( INIT => X"00010116" ) port map ( I0 => ready_r, I1 => polarity_r, I2 => align_r, I3 => \^rst_r_reg_0\, I4 => begin_r, O => \next_begin_c_inferred__1/i__n_0\ ); polarity_r_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0000000C04040000" ) port map ( I0 => rx_polarity_dlyd_i, I1 => ready_r_i_4_n_0, I2 => ready_r, I3 => rx_lossofsync_i, I4 => polarity_r, I5 => align_r, O => next_polarity_c ); polarity_r_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => next_polarity_c, Q => polarity_r, R => ready_r_reg0 ); prev_rx_polarity_r_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"FFEF0020" ) port map ( I0 => \^rx_polarity_r_reg_0\, I1 => polarity_r, I2 => \^rst_r_reg_0\, I3 => rx_polarity_dlyd_i, I4 => prev_rx_polarity_r, O => prev_rx_polarity_r_i_1_n_0 ); prev_rx_polarity_r_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => prev_rx_polarity_r_i_1_n_0, Q => prev_rx_polarity_r, R => SR(0) ); ready_r_i_4: unisim.vcomponents.LUT3 generic map( INIT => X"01" ) port map ( I0 => \^rst_r_reg_0\, I1 => reset_lanes_i, I2 => begin_r, O => ready_r_i_4_n_0 ); ready_r_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => next_ready_c, Q => ready_r, R => ready_r_reg0 ); reset_count_r_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => reset_count_r0, Q => reset_count_r, R => '0' ); reset_lanes_flop_0_i_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"F1" ) port map ( I0 => \^lane_up_flop_i_0\, I1 => gen_na_idles_i, I2 => SR(0), O => reset_lanes_c ); rst_r_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"14140414" ) port map ( I0 => rst_r_i_2_n_0, I1 => begin_r, I2 => \^rst_r_reg_0\, I3 => count_8d_done_r, I4 => reset_lanes_i, O => next_rst_c ); rst_r_i_2: unisim.vcomponents.LUT3 generic map( INIT => X"FE" ) port map ( I0 => align_r, I1 => ready_r, I2 => polarity_r, O => rst_r_i_2_n_0 ); rst_r_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => next_rst_c, Q => \^rst_r_reg_0\, R => ready_r_reg0 ); rx_polarity_r_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => u_cdc_rxlossofsync_in_n_2, Q => \^rx_polarity_r_reg_0\, R => '0' ); u_cdc_rxlossofsync_in: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync port map ( SR(0) => SR(0), SYSTEM_RESET_reg => u_cdc_rxlossofsync_in_n_2, align_r => align_r, begin_r_reg => \next_begin_c_inferred__1/i__n_0\, next_begin_c => next_begin_c, next_ready_c => next_ready_c, \out\ => \out\, polarity_r => polarity_r, prev_rx_polarity_r => prev_rx_polarity_r, ready_r => ready_r, ready_r_reg => ready_r_i_4_n_0, reset_lanes_i => reset_lanes_i, rx_lossofsync_i => rx_lossofsync_i, rx_polarity_dlyd_i => rx_polarity_dlyd_i, rx_polarity_r_reg => \^rx_polarity_r_reg_0\, s_level_out_d1_aurora_64b66b_0_cdc_to_reg_0 => s_level_out_d1_aurora_64b66b_0_cdc_to_reg ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_MULTI_GT is port ( in0 : out STD_LOGIC; drprdy_out : out STD_LOGIC; txn : out STD_LOGIC; txp : out STD_LOGIC; pre_rxdatavalid_i : out STD_LOGIC; pre_rxheadervalid_i : out STD_LOGIC; rxrecclk_from_gtx_i : out STD_LOGIC; \cpllpd_wait_reg[95]\ : out STD_LOGIC; tx_out_clk : out STD_LOGIC; \cpllpd_wait_reg[95]_0\ : out STD_LOGIC; drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); TXBUFSTATUS : out STD_LOGIC_VECTOR ( 0 to 0 ); RXBUFSTATUS : out STD_LOGIC_VECTOR ( 0 to 0 ); RXHEADER : out STD_LOGIC_VECTOR ( 1 downto 0 ); RXDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); ack_flag : out STD_LOGIC; ack_flag_reg : in STD_LOGIC; drp_clk_in : in STD_LOGIC; drpen_in : in STD_LOGIC; drpwe_in : in STD_LOGIC; refclk1_in : in STD_LOGIC; SR : in STD_LOGIC_VECTOR ( 0 to 0 ); gttxreset_t : in STD_LOGIC; rxn : in STD_LOGIC; rxp : in STD_LOGIC; gt_qpllclk_quad1_out : in STD_LOGIC; gt_qpllrefclk_quad1_out : in STD_LOGIC; gt_rxcdrovrden_in : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 0 to 0 ); \out\ : in STD_LOGIC; rxuserrdy_t : in STD_LOGIC; s_level_out_d1_aurora_64b66b_0_cdc_to_reg : in STD_LOGIC; txuserrdy_t : in STD_LOGIC; s_level_out_d1_aurora_64b66b_0_cdc_to_reg_0 : in STD_LOGIC; s_level_out_d1_aurora_64b66b_0_cdc_to_reg_1 : in STD_LOGIC; drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); loopback : in STD_LOGIC_VECTOR ( 2 downto 0 ); Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); SCRAMBLED_DATA_OUT : in STD_LOGIC_VECTOR ( 63 downto 0 ); s_level_out_d1_aurora_64b66b_0_cdc_to_reg_2 : in STD_LOGIC_VECTOR ( 6 downto 0 ); drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 ); flag2_reg : in STD_LOGIC; gt_cpllreset_i : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_MULTI_GT; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_MULTI_GT is begin aurora_64b66b_0_gtx_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_GTX port map ( D(0) => D(0), Q(1 downto 0) => Q(1 downto 0), RXBUFSTATUS(0) => RXBUFSTATUS(0), RXDATA(31 downto 0) => RXDATA(31 downto 0), RXHEADER(1 downto 0) => RXHEADER(1 downto 0), SCRAMBLED_DATA_OUT(63 downto 0) => SCRAMBLED_DATA_OUT(63 downto 0), SR(0) => SR(0), TXBUFSTATUS(0) => TXBUFSTATUS(0), ack_flag => ack_flag, ack_flag_reg_0 => ack_flag_reg, \cpllpd_wait_reg[95]_0\ => \cpllpd_wait_reg[95]\, \cpllpd_wait_reg[95]_1\ => \cpllpd_wait_reg[95]_0\, drp_clk_in => drp_clk_in, drpaddr_in(8 downto 0) => drpaddr_in(8 downto 0), drpdi_in(15 downto 0) => drpdi_in(15 downto 0), drpdo_out(15 downto 0) => drpdo_out(15 downto 0), drpen_in => drpen_in, drprdy_out => drprdy_out, drpwe_in => drpwe_in, flag2_reg_0 => flag2_reg, gt_cpllreset_i => gt_cpllreset_i, gt_qpllclk_quad1_out => gt_qpllclk_quad1_out, gt_qpllrefclk_quad1_out => gt_qpllrefclk_quad1_out, gt_rxcdrovrden_in => gt_rxcdrovrden_in, gttxreset_t => gttxreset_t, in0 => in0, loopback(2 downto 0) => loopback(2 downto 0), \out\ => \out\, pre_rxdatavalid_i => pre_rxdatavalid_i, pre_rxheadervalid_i => pre_rxheadervalid_i, refclk1_in => refclk1_in, rxn => rxn, rxp => rxp, rxrecclk_from_gtx_i => rxrecclk_from_gtx_i, rxuserrdy_t => rxuserrdy_t, s_level_out_d1_aurora_64b66b_0_cdc_to_reg => s_level_out_d1_aurora_64b66b_0_cdc_to_reg, s_level_out_d1_aurora_64b66b_0_cdc_to_reg_0 => s_level_out_d1_aurora_64b66b_0_cdc_to_reg_0, s_level_out_d1_aurora_64b66b_0_cdc_to_reg_1 => s_level_out_d1_aurora_64b66b_0_cdc_to_reg_1, s_level_out_d1_aurora_64b66b_0_cdc_to_reg_2(6 downto 0) => s_level_out_d1_aurora_64b66b_0_cdc_to_reg_2(6 downto 0), tx_out_clk => tx_out_clk, txn => txn, txp => txp, txuserrdy_t => txuserrdy_t ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_RESET_LOGIC is port ( SR : out STD_LOGIC_VECTOR ( 0 to 0 ); SYSTEM_RESET_reg_0 : out STD_LOGIC; ready_r_reg0 : out STD_LOGIC; reset_count_r0 : out STD_LOGIC; stg1_aurora_64b66b_0_cdc_to_reg : in STD_LOGIC; link_reset_out : in STD_LOGIC; power_down : in STD_LOGIC; sysreset_from_support : in STD_LOGIC; \out\ : in STD_LOGIC; wait_for_lane_up_r_reg : in STD_LOGIC; hard_err_i : in STD_LOGIC; tx_reset_i : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_RESET_LOGIC; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_RESET_LOGIC is signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal SYSTEM_RESET0_n_0 : STD_LOGIC; signal fsm_resetdone_sync : STD_LOGIC; signal link_reset_sync : STD_LOGIC; signal power_down_sync : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of ready_r_i_1 : label is "soft_lutpair95"; attribute SOFT_HLUTNM of wait_for_lane_up_r_i_1 : label is "soft_lutpair95"; begin SR(0) <= \^sr\(0); SYSTEM_RESET0: unisim.vcomponents.LUT4 generic map( INIT => X"FFEF" ) port map ( I0 => link_reset_sync, I1 => sysreset_from_support, I2 => fsm_resetdone_sync, I3 => power_down_sync, O => SYSTEM_RESET0_n_0 ); SYSTEM_RESET_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => SYSTEM_RESET0_n_0, Q => \^sr\(0), R => '0' ); ready_r_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \^sr\(0), I1 => hard_err_i, O => ready_r_reg0 ); reset_count_r_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \^sr\(0), I1 => tx_reset_i, O => reset_count_r0 ); u_link_rst_sync: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_2 port map ( link_reset_out => link_reset_out, link_reset_sync => link_reset_sync, \out\ => \out\ ); u_pd_sync: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_3 port map ( \out\ => \out\, power_down => power_down, power_down_sync => power_down_sync ); u_rst_done_sync: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_4 port map ( fsm_resetdone_sync => fsm_resetdone_sync, \out\ => \out\, stg1_aurora_64b66b_0_cdc_to_reg_0 => stg1_aurora_64b66b_0_cdc_to_reg ); wait_for_lane_up_r_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \^sr\(0), I1 => wait_for_lane_up_r_reg, O => SYSTEM_RESET_reg_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_RX_STARTUP_FSM is port ( rx_fsm_resetdone_i : out STD_LOGIC; gtrxreset_i_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 ); rx_clk_locked_i : out STD_LOGIC; rxuserrdy_t : out STD_LOGIC; new_gtx_rx_pcsreset_comb0 : out STD_LOGIC; \out\ : in STD_LOGIC; stg1_aurora_64b66b_0_cdc_to_reg : in STD_LOGIC; in0 : in STD_LOGIC; SR : in STD_LOGIC_VECTOR ( 0 to 0 ); stg4_reg : in STD_LOGIC; stg4_reg_0 : in STD_LOGIC; AR : in STD_LOGIC_VECTOR ( 0 to 0 ); fsm_resetdone_to_new_gtx_rx_comb : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_RX_STARTUP_FSM; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_RX_STARTUP_FSM is signal RXUSERRDY_i_1_n_0 : STD_LOGIC; signal RXUSERRDY_i_2_n_0 : STD_LOGIC; signal check_tlock_max_i_1_n_0 : STD_LOGIC; signal check_tlock_max_reg_n_0 : STD_LOGIC; signal gtrxreset_i_i_1_n_0 : STD_LOGIC; signal \^gtrxreset_i_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal gtx_rx_pcsreset_comb : STD_LOGIC; signal init_wait_count : STD_LOGIC; signal \init_wait_count[0]_i_1__0_n_0\ : STD_LOGIC; signal \init_wait_count[7]_i_3__0_n_0\ : STD_LOGIC; signal \init_wait_count[7]_i_4__0_n_0\ : STD_LOGIC; signal \init_wait_count[7]_i_5__0_n_0\ : STD_LOGIC; signal \init_wait_count_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal init_wait_done : STD_LOGIC; signal \init_wait_done_i_1__0_n_0\ : STD_LOGIC; signal init_wait_done_reg_n_0 : STD_LOGIC; signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \p_0_in__3\ : STD_LOGIC_VECTOR ( 7 downto 1 ); signal \reset_time_out_i_3__0_n_0\ : STD_LOGIC; signal \reset_time_out_i_4__0_n_0\ : STD_LOGIC; signal \reset_time_out_i_5__0_n_0\ : STD_LOGIC; signal reset_time_out_reg_n_0 : STD_LOGIC; signal \run_phase_alignment_int_i_1__0_n_0\ : STD_LOGIC; signal run_phase_alignment_int_i_2_n_0 : STD_LOGIC; signal run_phase_alignment_int_reg_n_0 : STD_LOGIC; signal rx_cdrlock_counter : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \rx_cdrlock_counter[0]_i_1_n_0\ : STD_LOGIC; signal \rx_cdrlock_counter[31]_i_10_n_0\ : STD_LOGIC; signal \rx_cdrlock_counter[31]_i_2_n_0\ : STD_LOGIC; signal \rx_cdrlock_counter[31]_i_3_n_0\ : STD_LOGIC; signal \rx_cdrlock_counter[31]_i_4_n_0\ : STD_LOGIC; signal \rx_cdrlock_counter[31]_i_5_n_0\ : STD_LOGIC; signal \rx_cdrlock_counter[31]_i_7_n_0\ : STD_LOGIC; signal \rx_cdrlock_counter[31]_i_8_n_0\ : STD_LOGIC; signal \rx_cdrlock_counter[31]_i_9_n_0\ : STD_LOGIC; signal rx_cdrlock_counter_0 : STD_LOGIC_VECTOR ( 31 downto 1 ); signal \rx_cdrlock_counter_reg[12]_i_2_n_0\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[12]_i_2_n_1\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[12]_i_2_n_2\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[12]_i_2_n_3\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[12]_i_2_n_4\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[12]_i_2_n_5\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[12]_i_2_n_6\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[12]_i_2_n_7\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[16]_i_2_n_0\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[16]_i_2_n_1\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[16]_i_2_n_2\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[16]_i_2_n_3\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[16]_i_2_n_4\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[16]_i_2_n_5\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[16]_i_2_n_6\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[16]_i_2_n_7\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[20]_i_2_n_0\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[20]_i_2_n_1\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[20]_i_2_n_2\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[20]_i_2_n_3\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[20]_i_2_n_4\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[20]_i_2_n_5\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[20]_i_2_n_6\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[20]_i_2_n_7\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[24]_i_2_n_0\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[24]_i_2_n_1\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[24]_i_2_n_2\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[24]_i_2_n_3\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[24]_i_2_n_4\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[24]_i_2_n_5\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[24]_i_2_n_6\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[24]_i_2_n_7\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[28]_i_2_n_0\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[28]_i_2_n_1\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[28]_i_2_n_2\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[28]_i_2_n_3\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[28]_i_2_n_4\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[28]_i_2_n_5\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[28]_i_2_n_6\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[28]_i_2_n_7\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[31]_i_6_n_2\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[31]_i_6_n_3\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[31]_i_6_n_5\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[31]_i_6_n_6\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[31]_i_6_n_7\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[4]_i_2_n_0\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[4]_i_2_n_1\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[4]_i_2_n_2\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[4]_i_2_n_3\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[4]_i_2_n_4\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[4]_i_2_n_5\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[4]_i_2_n_6\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[4]_i_2_n_7\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[8]_i_2_n_0\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[8]_i_2_n_1\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[8]_i_2_n_2\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[8]_i_2_n_3\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[8]_i_2_n_4\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[8]_i_2_n_5\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[8]_i_2_n_6\ : STD_LOGIC; signal \rx_cdrlock_counter_reg[8]_i_2_n_7\ : STD_LOGIC; signal rx_cdrlocked_i_1_n_0 : STD_LOGIC; signal \^rx_clk_locked_i\ : STD_LOGIC; signal rx_fsm_reset_done_int : STD_LOGIC; attribute RTL_KEEP : string; attribute RTL_KEEP of rx_fsm_reset_done_int : signal is "true"; signal rx_fsm_reset_done_int_i_1_n_0 : STD_LOGIC; signal rx_fsm_reset_done_int_i_2_n_0 : STD_LOGIC; signal rx_fsm_reset_done_int_i_3_n_0 : STD_LOGIC; signal rx_reset_r3 : STD_LOGIC; signal rx_state : STD_LOGIC_VECTOR ( 7 downto 0 ); attribute RTL_KEEP of rx_state : signal is "true"; signal \rx_state[0]_i_2_n_0\ : STD_LOGIC; signal \rx_state[0]_i_5_n_0\ : STD_LOGIC; signal \rx_state[1]_i_3_n_0\ : STD_LOGIC; signal \rx_state[3]_i_4_n_0\ : STD_LOGIC; signal \rx_state[7]_i_1_n_0\ : STD_LOGIC; signal \rx_state[7]_i_3_n_0\ : STD_LOGIC; signal \rx_state[7]_i_4_n_0\ : STD_LOGIC; signal \rx_state[7]_i_5_n_0\ : STD_LOGIC; signal \rx_state[7]_i_6_n_0\ : STD_LOGIC; signal \rx_state[7]_i_7_n_0\ : STD_LOGIC; signal \^rxuserrdy_t\ : STD_LOGIC; signal time_out_1us_i_1_n_0 : STD_LOGIC; signal time_out_1us_i_2_n_0 : STD_LOGIC; signal time_out_1us_i_3_n_0 : STD_LOGIC; signal time_out_1us_i_4_n_0 : STD_LOGIC; signal time_out_1us_i_5_n_0 : STD_LOGIC; signal time_out_1us_reg_n_0 : STD_LOGIC; signal \time_out_2ms_i_1__0_n_0\ : STD_LOGIC; signal time_out_2ms_i_2_n_0 : STD_LOGIC; signal time_out_2ms_reg_n_0 : STD_LOGIC; signal time_out_counter : STD_LOGIC; signal \time_out_counter[0]_i_3__0_n_0\ : STD_LOGIC; signal \time_out_counter[0]_i_4__0_n_0\ : STD_LOGIC; signal \time_out_counter[0]_i_5_n_0\ : STD_LOGIC; signal \time_out_counter[0]_i_6_n_0\ : STD_LOGIC; signal \time_out_counter[0]_i_7__0_n_0\ : STD_LOGIC; signal time_out_counter_reg : STD_LOGIC_VECTOR ( 18 downto 0 ); signal \time_out_counter_reg[0]_i_2__0_n_0\ : STD_LOGIC; signal \time_out_counter_reg[0]_i_2__0_n_1\ : STD_LOGIC; signal \time_out_counter_reg[0]_i_2__0_n_2\ : STD_LOGIC; signal \time_out_counter_reg[0]_i_2__0_n_3\ : STD_LOGIC; signal \time_out_counter_reg[0]_i_2__0_n_4\ : STD_LOGIC; signal \time_out_counter_reg[0]_i_2__0_n_5\ : STD_LOGIC; signal \time_out_counter_reg[0]_i_2__0_n_6\ : STD_LOGIC; signal \time_out_counter_reg[0]_i_2__0_n_7\ : STD_LOGIC; signal \time_out_counter_reg[12]_i_1__0_n_0\ : STD_LOGIC; signal \time_out_counter_reg[12]_i_1__0_n_1\ : STD_LOGIC; signal \time_out_counter_reg[12]_i_1__0_n_2\ : STD_LOGIC; signal \time_out_counter_reg[12]_i_1__0_n_3\ : STD_LOGIC; signal \time_out_counter_reg[12]_i_1__0_n_4\ : STD_LOGIC; signal \time_out_counter_reg[12]_i_1__0_n_5\ : STD_LOGIC; signal \time_out_counter_reg[12]_i_1__0_n_6\ : STD_LOGIC; signal \time_out_counter_reg[12]_i_1__0_n_7\ : STD_LOGIC; signal \time_out_counter_reg[16]_i_1__0_n_2\ : STD_LOGIC; signal \time_out_counter_reg[16]_i_1__0_n_3\ : STD_LOGIC; signal \time_out_counter_reg[16]_i_1__0_n_5\ : STD_LOGIC; signal \time_out_counter_reg[16]_i_1__0_n_6\ : STD_LOGIC; signal \time_out_counter_reg[16]_i_1__0_n_7\ : STD_LOGIC; signal \time_out_counter_reg[4]_i_1__0_n_0\ : STD_LOGIC; signal \time_out_counter_reg[4]_i_1__0_n_1\ : STD_LOGIC; signal \time_out_counter_reg[4]_i_1__0_n_2\ : STD_LOGIC; signal \time_out_counter_reg[4]_i_1__0_n_3\ : STD_LOGIC; signal \time_out_counter_reg[4]_i_1__0_n_4\ : STD_LOGIC; signal \time_out_counter_reg[4]_i_1__0_n_5\ : STD_LOGIC; signal \time_out_counter_reg[4]_i_1__0_n_6\ : STD_LOGIC; signal \time_out_counter_reg[4]_i_1__0_n_7\ : STD_LOGIC; signal \time_out_counter_reg[8]_i_1__0_n_0\ : STD_LOGIC; signal \time_out_counter_reg[8]_i_1__0_n_1\ : STD_LOGIC; signal \time_out_counter_reg[8]_i_1__0_n_2\ : STD_LOGIC; signal \time_out_counter_reg[8]_i_1__0_n_3\ : STD_LOGIC; signal \time_out_counter_reg[8]_i_1__0_n_4\ : STD_LOGIC; signal \time_out_counter_reg[8]_i_1__0_n_5\ : STD_LOGIC; signal \time_out_counter_reg[8]_i_1__0_n_6\ : STD_LOGIC; signal \time_out_counter_reg[8]_i_1__0_n_7\ : STD_LOGIC; signal time_out_wait_bypass : STD_LOGIC; attribute async_reg : string; attribute async_reg of time_out_wait_bypass : signal is "true"; attribute shift_extract : string; attribute shift_extract of time_out_wait_bypass : signal is "{no}"; signal time_out_wait_bypass_i_3_n_0 : STD_LOGIC; signal time_out_wait_bypass_i_4_n_0 : STD_LOGIC; signal time_out_wait_bypass_i_5_n_0 : STD_LOGIC; signal time_out_wait_bypass_i_6_n_0 : STD_LOGIC; signal time_tlock_max : STD_LOGIC; signal time_tlock_max0 : STD_LOGIC; signal time_tlock_max_i_1_n_0 : STD_LOGIC; signal time_tlock_max_i_3_n_0 : STD_LOGIC; signal time_tlock_max_i_4_n_0 : STD_LOGIC; signal u_rst_sync_mmcm_lock_n_0 : STD_LOGIC; signal u_rst_sync_mmcm_lock_n_1 : STD_LOGIC; signal u_rst_sync_plllock_n_0 : STD_LOGIC; signal u_rst_sync_plllock_n_1 : STD_LOGIC; signal u_rst_sync_run_phase_align_n_0 : STD_LOGIC; signal u_rst_sync_rx_fsm_reset_done_n_0 : STD_LOGIC; signal u_rst_sync_rx_fsm_reset_done_n_1 : STD_LOGIC; signal u_rst_sync_rxresetdone_n_0 : STD_LOGIC; signal u_rst_sync_rxresetdone_n_1 : STD_LOGIC; signal u_rst_sync_rxresetdone_n_2 : STD_LOGIC; signal u_rst_sync_system_reset_n_0 : STD_LOGIC; signal u_rst_sync_time_out_wait_bypass_n_0 : STD_LOGIC; signal \wait_bypass_count[0]_i_3_n_0\ : STD_LOGIC; signal wait_bypass_count_reg : STD_LOGIC_VECTOR ( 12 downto 0 ); signal \wait_bypass_count_reg[0]_i_2_n_0\ : STD_LOGIC; signal \wait_bypass_count_reg[0]_i_2_n_1\ : STD_LOGIC; signal \wait_bypass_count_reg[0]_i_2_n_2\ : STD_LOGIC; signal \wait_bypass_count_reg[0]_i_2_n_3\ : STD_LOGIC; signal \wait_bypass_count_reg[0]_i_2_n_4\ : STD_LOGIC; signal \wait_bypass_count_reg[0]_i_2_n_5\ : STD_LOGIC; signal \wait_bypass_count_reg[0]_i_2_n_6\ : STD_LOGIC; signal \wait_bypass_count_reg[0]_i_2_n_7\ : STD_LOGIC; signal \wait_bypass_count_reg[12]_i_1__0_n_7\ : STD_LOGIC; signal \wait_bypass_count_reg[4]_i_1__0_n_0\ : STD_LOGIC; signal \wait_bypass_count_reg[4]_i_1__0_n_1\ : STD_LOGIC; signal \wait_bypass_count_reg[4]_i_1__0_n_2\ : STD_LOGIC; signal \wait_bypass_count_reg[4]_i_1__0_n_3\ : STD_LOGIC; signal \wait_bypass_count_reg[4]_i_1__0_n_4\ : STD_LOGIC; signal \wait_bypass_count_reg[4]_i_1__0_n_5\ : STD_LOGIC; signal \wait_bypass_count_reg[4]_i_1__0_n_6\ : STD_LOGIC; signal \wait_bypass_count_reg[4]_i_1__0_n_7\ : STD_LOGIC; signal \wait_bypass_count_reg[8]_i_1__0_n_0\ : STD_LOGIC; signal \wait_bypass_count_reg[8]_i_1__0_n_1\ : STD_LOGIC; signal \wait_bypass_count_reg[8]_i_1__0_n_2\ : STD_LOGIC; signal \wait_bypass_count_reg[8]_i_1__0_n_3\ : STD_LOGIC; signal \wait_bypass_count_reg[8]_i_1__0_n_4\ : STD_LOGIC; signal \wait_bypass_count_reg[8]_i_1__0_n_5\ : STD_LOGIC; signal \wait_bypass_count_reg[8]_i_1__0_n_6\ : STD_LOGIC; signal \wait_bypass_count_reg[8]_i_1__0_n_7\ : STD_LOGIC; signal \NLW_rx_cdrlock_counter_reg[31]_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_rx_cdrlock_counter_reg[31]_i_6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); signal \NLW_time_out_counter_reg[16]_i_1__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_time_out_counter_reg[16]_i_1__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); signal \NLW_wait_bypass_count_reg[12]_i_1__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_wait_bypass_count_reg[12]_i_1__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \init_wait_count[1]_i_1__0\ : label is "soft_lutpair40"; attribute SOFT_HLUTNM of \init_wait_count[2]_i_1__0\ : label is "soft_lutpair39"; attribute SOFT_HLUTNM of \init_wait_count[3]_i_1__0\ : label is "soft_lutpair39"; attribute SOFT_HLUTNM of \init_wait_count[4]_i_1__0\ : label is "soft_lutpair36"; attribute SOFT_HLUTNM of \init_wait_count[6]_i_1__0\ : label is "soft_lutpair37"; attribute SOFT_HLUTNM of \init_wait_count[7]_i_2__0\ : label is "soft_lutpair37"; attribute SOFT_HLUTNM of \init_wait_count[7]_i_3__0\ : label is "soft_lutpair40"; attribute SOFT_HLUTNM of \init_wait_count[7]_i_5__0\ : label is "soft_lutpair36"; attribute KEEP : string; attribute KEEP of rx_fsm_reset_done_int_reg : label is "yes"; attribute SOFT_HLUTNM of \rx_state[1]_i_3\ : label is "soft_lutpair38"; attribute SOFT_HLUTNM of \rx_state[7]_i_5\ : label is "soft_lutpair38"; attribute FSM_ENCODED_STATES : string; attribute FSM_ENCODED_STATES of \rx_state_reg[0]\ : label is "INIT:00000000,ASSERT_ALL_RESETS:00000001,RELEASE_PLL_RESET:00000010,VERIFY_RECCLK_STABLE:00000100,RELEASE_MMCM_RESET:00001000,WAIT_RESET_DONE:00010000,DO_PHASE_ALIGNMENT:00100000,MONITOR_DATA_VALID:01000000,FSM_DONE:10000000"; attribute KEEP of \rx_state_reg[0]\ : label is "yes"; attribute FSM_ENCODED_STATES of \rx_state_reg[1]\ : label is "INIT:00000000,ASSERT_ALL_RESETS:00000001,RELEASE_PLL_RESET:00000010,VERIFY_RECCLK_STABLE:00000100,RELEASE_MMCM_RESET:00001000,WAIT_RESET_DONE:00010000,DO_PHASE_ALIGNMENT:00100000,MONITOR_DATA_VALID:01000000,FSM_DONE:10000000"; attribute KEEP of \rx_state_reg[1]\ : label is "yes"; attribute FSM_ENCODED_STATES of \rx_state_reg[2]\ : label is "INIT:00000000,ASSERT_ALL_RESETS:00000001,RELEASE_PLL_RESET:00000010,VERIFY_RECCLK_STABLE:00000100,RELEASE_MMCM_RESET:00001000,WAIT_RESET_DONE:00010000,DO_PHASE_ALIGNMENT:00100000,MONITOR_DATA_VALID:01000000,FSM_DONE:10000000"; attribute KEEP of \rx_state_reg[2]\ : label is "yes"; attribute FSM_ENCODED_STATES of \rx_state_reg[3]\ : label is "INIT:00000000,ASSERT_ALL_RESETS:00000001,RELEASE_PLL_RESET:00000010,VERIFY_RECCLK_STABLE:00000100,RELEASE_MMCM_RESET:00001000,WAIT_RESET_DONE:00010000,DO_PHASE_ALIGNMENT:00100000,MONITOR_DATA_VALID:01000000,FSM_DONE:10000000"; attribute KEEP of \rx_state_reg[3]\ : label is "yes"; attribute FSM_ENCODED_STATES of \rx_state_reg[4]\ : label is "INIT:00000000,ASSERT_ALL_RESETS:00000001,RELEASE_PLL_RESET:00000010,VERIFY_RECCLK_STABLE:00000100,RELEASE_MMCM_RESET:00001000,WAIT_RESET_DONE:00010000,DO_PHASE_ALIGNMENT:00100000,MONITOR_DATA_VALID:01000000,FSM_DONE:10000000"; attribute KEEP of \rx_state_reg[4]\ : label is "yes"; attribute FSM_ENCODED_STATES of \rx_state_reg[5]\ : label is "INIT:00000000,ASSERT_ALL_RESETS:00000001,RELEASE_PLL_RESET:00000010,VERIFY_RECCLK_STABLE:00000100,RELEASE_MMCM_RESET:00001000,WAIT_RESET_DONE:00010000,DO_PHASE_ALIGNMENT:00100000,MONITOR_DATA_VALID:01000000,FSM_DONE:10000000"; attribute KEEP of \rx_state_reg[5]\ : label is "yes"; attribute FSM_ENCODED_STATES of \rx_state_reg[6]\ : label is "INIT:00000000,ASSERT_ALL_RESETS:00000001,RELEASE_PLL_RESET:00000010,VERIFY_RECCLK_STABLE:00000100,RELEASE_MMCM_RESET:00001000,WAIT_RESET_DONE:00010000,DO_PHASE_ALIGNMENT:00100000,MONITOR_DATA_VALID:01000000,FSM_DONE:10000000"; attribute KEEP of \rx_state_reg[6]\ : label is "yes"; attribute FSM_ENCODED_STATES of \rx_state_reg[7]\ : label is "INIT:00000000,ASSERT_ALL_RESETS:00000001,RELEASE_PLL_RESET:00000010,VERIFY_RECCLK_STABLE:00000100,RELEASE_MMCM_RESET:00001000,WAIT_RESET_DONE:00010000,DO_PHASE_ALIGNMENT:00100000,MONITOR_DATA_VALID:01000000,FSM_DONE:10000000"; attribute KEEP of \rx_state_reg[7]\ : label is "yes"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of time_out_wait_bypass_reg : label is std.standard.true; attribute KEEP of time_out_wait_bypass_reg : label is "yes"; attribute shift_extract of time_out_wait_bypass_reg : label is "{no}"; begin gtrxreset_i_reg_0(0) <= \^gtrxreset_i_reg_0\(0); rx_clk_locked_i <= \^rx_clk_locked_i\; rx_fsm_resetdone_i <= rx_fsm_reset_done_int; rxuserrdy_t <= \^rxuserrdy_t\; FABRIC_PCS_RESET_reg: unisim.vcomponents.FDRE port map ( C => stg4_reg_0, CE => '1', D => u_rst_sync_system_reset_n_0, Q => gtx_rx_pcsreset_comb, R => '0' ); RXUSERRDY_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFAF00000008" ) port map ( I0 => rx_state(4), I1 => time_out_1us_reg_n_0, I2 => rx_state(0), I3 => rx_fsm_reset_done_int_i_3_n_0, I4 => RXUSERRDY_i_2_n_0, I5 => \^rxuserrdy_t\, O => RXUSERRDY_i_1_n_0 ); RXUSERRDY_i_2: unisim.vcomponents.LUT3 generic map( INIT => X"FE" ) port map ( I0 => rx_state(5), I1 => rx_state(6), I2 => rx_state(7), O => RXUSERRDY_i_2_n_0 ); RXUSERRDY_reg: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', CLR => AR(0), D => RXUSERRDY_i_1_n_0, Q => \^rxuserrdy_t\ ); check_tlock_max_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFB00000002" ) port map ( I0 => rx_state(3), I1 => rx_state(0), I2 => rx_state(2), I3 => rx_state(1), I4 => \rx_state[7]_i_3_n_0\, I5 => check_tlock_max_reg_n_0, O => check_tlock_max_i_1_n_0 ); check_tlock_max_reg: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', CLR => AR(0), D => check_tlock_max_i_1_n_0, Q => check_tlock_max_reg_n_0 ); gtrxreset_i_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFEF00000002" ) port map ( I0 => rx_state(0), I1 => rx_state(1), I2 => rx_state(2), I3 => \rx_state[7]_i_3_n_0\, I4 => rx_state(3), I5 => \^gtrxreset_i_reg_0\(0), O => gtrxreset_i_i_1_n_0 ); gtrxreset_i_reg: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', CLR => AR(0), D => gtrxreset_i_i_1_n_0, Q => \^gtrxreset_i_reg_0\(0) ); \init_wait_count[0]_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \init_wait_count_reg__0\(0), O => \init_wait_count[0]_i_1__0_n_0\ ); \init_wait_count[1]_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \init_wait_count_reg__0\(1), I1 => \init_wait_count_reg__0\(0), O => \p_0_in__3\(1) ); \init_wait_count[2]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \init_wait_count_reg__0\(2), I1 => \init_wait_count_reg__0\(1), I2 => \init_wait_count_reg__0\(0), O => \p_0_in__3\(2) ); \init_wait_count[3]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"6AAA" ) port map ( I0 => \init_wait_count_reg__0\(3), I1 => \init_wait_count_reg__0\(0), I2 => \init_wait_count_reg__0\(1), I3 => \init_wait_count_reg__0\(2), O => \p_0_in__3\(3) ); \init_wait_count[4]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \init_wait_count_reg__0\(2), I1 => \init_wait_count_reg__0\(1), I2 => \init_wait_count_reg__0\(0), I3 => \init_wait_count_reg__0\(3), I4 => \init_wait_count_reg__0\(4), O => \p_0_in__3\(4) ); \init_wait_count[5]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"6AAAAAAAAAAAAAAA" ) port map ( I0 => \init_wait_count_reg__0\(5), I1 => \init_wait_count_reg__0\(2), I2 => \init_wait_count_reg__0\(1), I3 => \init_wait_count_reg__0\(0), I4 => \init_wait_count_reg__0\(3), I5 => \init_wait_count_reg__0\(4), O => \p_0_in__3\(5) ); \init_wait_count[6]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"AA6A" ) port map ( I0 => \init_wait_count_reg__0\(6), I1 => \init_wait_count_reg__0\(4), I2 => \init_wait_count_reg__0\(5), I3 => \init_wait_count[7]_i_5__0_n_0\, O => \p_0_in__3\(6) ); \init_wait_count[7]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFE" ) port map ( I0 => \init_wait_count[7]_i_3__0_n_0\, I1 => \init_wait_count[7]_i_4__0_n_0\, I2 => \init_wait_count_reg__0\(7), I3 => \init_wait_count_reg__0\(6), I4 => \init_wait_count_reg__0\(3), I5 => \init_wait_count_reg__0\(2), O => init_wait_count ); \init_wait_count[7]_i_2__0\: unisim.vcomponents.LUT5 generic map( INIT => X"9AAAAAAA" ) port map ( I0 => \init_wait_count_reg__0\(7), I1 => \init_wait_count[7]_i_5__0_n_0\, I2 => \init_wait_count_reg__0\(5), I3 => \init_wait_count_reg__0\(4), I4 => \init_wait_count_reg__0\(6), O => \p_0_in__3\(7) ); \init_wait_count[7]_i_3__0\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => \init_wait_count_reg__0\(1), I1 => \init_wait_count_reg__0\(0), O => \init_wait_count[7]_i_3__0_n_0\ ); \init_wait_count[7]_i_4__0\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => \init_wait_count_reg__0\(4), I1 => \init_wait_count_reg__0\(5), O => \init_wait_count[7]_i_4__0_n_0\ ); \init_wait_count[7]_i_5__0\: unisim.vcomponents.LUT4 generic map( INIT => X"7FFF" ) port map ( I0 => \init_wait_count_reg__0\(2), I1 => \init_wait_count_reg__0\(1), I2 => \init_wait_count_reg__0\(0), I3 => \init_wait_count_reg__0\(3), O => \init_wait_count[7]_i_5__0_n_0\ ); \init_wait_count_reg[0]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => init_wait_count, CLR => AR(0), D => \init_wait_count[0]_i_1__0_n_0\, Q => \init_wait_count_reg__0\(0) ); \init_wait_count_reg[1]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => init_wait_count, CLR => AR(0), D => \p_0_in__3\(1), Q => \init_wait_count_reg__0\(1) ); \init_wait_count_reg[2]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => init_wait_count, CLR => AR(0), D => \p_0_in__3\(2), Q => \init_wait_count_reg__0\(2) ); \init_wait_count_reg[3]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => init_wait_count, CLR => AR(0), D => \p_0_in__3\(3), Q => \init_wait_count_reg__0\(3) ); \init_wait_count_reg[4]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => init_wait_count, CLR => AR(0), D => \p_0_in__3\(4), Q => \init_wait_count_reg__0\(4) ); \init_wait_count_reg[5]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => init_wait_count, CLR => AR(0), D => \p_0_in__3\(5), Q => \init_wait_count_reg__0\(5) ); \init_wait_count_reg[6]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => init_wait_count, CLR => AR(0), D => \p_0_in__3\(6), Q => \init_wait_count_reg__0\(6) ); \init_wait_count_reg[7]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => init_wait_count, CLR => AR(0), D => \p_0_in__3\(7), Q => \init_wait_count_reg__0\(7) ); \init_wait_done_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => init_wait_done, I1 => init_wait_done_reg_n_0, O => \init_wait_done_i_1__0_n_0\ ); \init_wait_done_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000001" ) port map ( I0 => \init_wait_count_reg__0\(2), I1 => \init_wait_count_reg__0\(3), I2 => \init_wait_count_reg__0\(6), I3 => \init_wait_count_reg__0\(7), I4 => \init_wait_count[7]_i_4__0_n_0\, I5 => \init_wait_count[7]_i_3__0_n_0\, O => init_wait_done ); init_wait_done_reg: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', CLR => AR(0), D => \init_wait_done_i_1__0_n_0\, Q => init_wait_done_reg_n_0 ); new_gtx_rx_pcsreset_comb_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => gtx_rx_pcsreset_comb, I1 => fsm_resetdone_to_new_gtx_rx_comb, O => new_gtx_rx_pcsreset_comb0 ); \reset_time_out_i_3__0\: unisim.vcomponents.LUT5 generic map( INIT => X"00000115" ) port map ( I0 => rx_state(2), I1 => rx_state(1), I2 => rx_state(3), I3 => rx_state(0), I4 => \rx_state[7]_i_3_n_0\, O => \reset_time_out_i_3__0_n_0\ ); \reset_time_out_i_4__0\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => rx_state(1), I1 => rx_state(0), O => \reset_time_out_i_4__0_n_0\ ); \reset_time_out_i_5__0\: unisim.vcomponents.LUT6 generic map( INIT => X"000000030003033B" ) port map ( I0 => \^rx_clk_locked_i\, I1 => rx_state(2), I2 => rx_state(4), I3 => rx_state(6), I4 => rx_state(7), I5 => rx_state(5), O => \reset_time_out_i_5__0_n_0\ ); reset_time_out_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => u_rst_sync_mmcm_lock_n_1, PRE => AR(0), Q => reset_time_out_reg_n_0 ); \run_phase_alignment_int_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFEFF00000010" ) port map ( I0 => run_phase_alignment_int_i_2_n_0, I1 => rx_state(4), I2 => rx_state(5), I3 => rx_state(0), I4 => rx_fsm_reset_done_int_i_3_n_0, I5 => run_phase_alignment_int_reg_n_0, O => \run_phase_alignment_int_i_1__0_n_0\ ); run_phase_alignment_int_i_2: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => rx_state(7), I1 => rx_state(6), O => run_phase_alignment_int_i_2_n_0 ); run_phase_alignment_int_reg: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', CLR => AR(0), D => \run_phase_alignment_int_i_1__0_n_0\, Q => run_phase_alignment_int_reg_n_0 ); \rx_cdrlock_counter[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"0001FFFF" ) port map ( I0 => \rx_cdrlock_counter[31]_i_2_n_0\, I1 => \rx_cdrlock_counter[31]_i_3_n_0\, I2 => \rx_cdrlock_counter[31]_i_4_n_0\, I3 => \rx_cdrlock_counter[31]_i_5_n_0\, I4 => rx_cdrlock_counter(0), O => \rx_cdrlock_counter[0]_i_1_n_0\ ); \rx_cdrlock_counter[10]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0000" ) port map ( I0 => \rx_cdrlock_counter[31]_i_2_n_0\, I1 => \rx_cdrlock_counter[31]_i_3_n_0\, I2 => \rx_cdrlock_counter[31]_i_4_n_0\, I3 => \rx_cdrlock_counter[31]_i_5_n_0\, I4 => \rx_cdrlock_counter_reg[12]_i_2_n_6\, O => rx_cdrlock_counter_0(10) ); \rx_cdrlock_counter[11]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAAB" ) port map ( I0 => \rx_cdrlock_counter_reg[12]_i_2_n_5\, I1 => \rx_cdrlock_counter[31]_i_2_n_0\, I2 => \rx_cdrlock_counter[31]_i_3_n_0\, I3 => \rx_cdrlock_counter[31]_i_4_n_0\, I4 => \rx_cdrlock_counter[31]_i_5_n_0\, O => rx_cdrlock_counter_0(11) ); \rx_cdrlock_counter[12]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0000" ) port map ( I0 => \rx_cdrlock_counter[31]_i_2_n_0\, I1 => \rx_cdrlock_counter[31]_i_3_n_0\, I2 => \rx_cdrlock_counter[31]_i_4_n_0\, I3 => \rx_cdrlock_counter[31]_i_5_n_0\, I4 => \rx_cdrlock_counter_reg[12]_i_2_n_4\, O => rx_cdrlock_counter_0(12) ); \rx_cdrlock_counter[13]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAAB" ) port map ( I0 => \rx_cdrlock_counter_reg[16]_i_2_n_7\, I1 => \rx_cdrlock_counter[31]_i_2_n_0\, I2 => \rx_cdrlock_counter[31]_i_3_n_0\, I3 => \rx_cdrlock_counter[31]_i_4_n_0\, I4 => \rx_cdrlock_counter[31]_i_5_n_0\, O => rx_cdrlock_counter_0(13) ); \rx_cdrlock_counter[14]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAAB" ) port map ( I0 => \rx_cdrlock_counter_reg[16]_i_2_n_6\, I1 => \rx_cdrlock_counter[31]_i_2_n_0\, I2 => \rx_cdrlock_counter[31]_i_3_n_0\, I3 => \rx_cdrlock_counter[31]_i_4_n_0\, I4 => \rx_cdrlock_counter[31]_i_5_n_0\, O => rx_cdrlock_counter_0(14) ); \rx_cdrlock_counter[15]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0000" ) port map ( I0 => \rx_cdrlock_counter[31]_i_2_n_0\, I1 => \rx_cdrlock_counter[31]_i_3_n_0\, I2 => \rx_cdrlock_counter[31]_i_4_n_0\, I3 => \rx_cdrlock_counter[31]_i_5_n_0\, I4 => \rx_cdrlock_counter_reg[16]_i_2_n_5\, O => rx_cdrlock_counter_0(15) ); \rx_cdrlock_counter[16]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAAB" ) port map ( I0 => \rx_cdrlock_counter_reg[16]_i_2_n_4\, I1 => \rx_cdrlock_counter[31]_i_2_n_0\, I2 => \rx_cdrlock_counter[31]_i_3_n_0\, I3 => \rx_cdrlock_counter[31]_i_4_n_0\, I4 => \rx_cdrlock_counter[31]_i_5_n_0\, O => rx_cdrlock_counter_0(16) ); \rx_cdrlock_counter[17]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0000" ) port map ( I0 => \rx_cdrlock_counter[31]_i_2_n_0\, I1 => \rx_cdrlock_counter[31]_i_3_n_0\, I2 => \rx_cdrlock_counter[31]_i_4_n_0\, I3 => \rx_cdrlock_counter[31]_i_5_n_0\, I4 => \rx_cdrlock_counter_reg[20]_i_2_n_7\, O => rx_cdrlock_counter_0(17) ); \rx_cdrlock_counter[18]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0000" ) port map ( I0 => \rx_cdrlock_counter[31]_i_2_n_0\, I1 => \rx_cdrlock_counter[31]_i_3_n_0\, I2 => \rx_cdrlock_counter[31]_i_4_n_0\, I3 => \rx_cdrlock_counter[31]_i_5_n_0\, I4 => \rx_cdrlock_counter_reg[20]_i_2_n_6\, O => rx_cdrlock_counter_0(18) ); \rx_cdrlock_counter[19]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAAB" ) port map ( I0 => \rx_cdrlock_counter_reg[20]_i_2_n_5\, I1 => \rx_cdrlock_counter[31]_i_2_n_0\, I2 => \rx_cdrlock_counter[31]_i_3_n_0\, I3 => \rx_cdrlock_counter[31]_i_4_n_0\, I4 => \rx_cdrlock_counter[31]_i_5_n_0\, O => rx_cdrlock_counter_0(19) ); \rx_cdrlock_counter[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAAB" ) port map ( I0 => \rx_cdrlock_counter_reg[4]_i_2_n_7\, I1 => \rx_cdrlock_counter[31]_i_2_n_0\, I2 => \rx_cdrlock_counter[31]_i_3_n_0\, I3 => \rx_cdrlock_counter[31]_i_4_n_0\, I4 => \rx_cdrlock_counter[31]_i_5_n_0\, O => rx_cdrlock_counter_0(1) ); \rx_cdrlock_counter[20]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0000" ) port map ( I0 => \rx_cdrlock_counter[31]_i_2_n_0\, I1 => \rx_cdrlock_counter[31]_i_3_n_0\, I2 => \rx_cdrlock_counter[31]_i_4_n_0\, I3 => \rx_cdrlock_counter[31]_i_5_n_0\, I4 => \rx_cdrlock_counter_reg[20]_i_2_n_4\, O => rx_cdrlock_counter_0(20) ); \rx_cdrlock_counter[21]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0000" ) port map ( I0 => \rx_cdrlock_counter[31]_i_2_n_0\, I1 => \rx_cdrlock_counter[31]_i_3_n_0\, I2 => \rx_cdrlock_counter[31]_i_4_n_0\, I3 => \rx_cdrlock_counter[31]_i_5_n_0\, I4 => \rx_cdrlock_counter_reg[24]_i_2_n_7\, O => rx_cdrlock_counter_0(21) ); \rx_cdrlock_counter[22]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0000" ) port map ( I0 => \rx_cdrlock_counter[31]_i_2_n_0\, I1 => \rx_cdrlock_counter[31]_i_3_n_0\, I2 => \rx_cdrlock_counter[31]_i_4_n_0\, I3 => \rx_cdrlock_counter[31]_i_5_n_0\, I4 => \rx_cdrlock_counter_reg[24]_i_2_n_6\, O => rx_cdrlock_counter_0(22) ); \rx_cdrlock_counter[23]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0000" ) port map ( I0 => \rx_cdrlock_counter[31]_i_2_n_0\, I1 => \rx_cdrlock_counter[31]_i_3_n_0\, I2 => \rx_cdrlock_counter[31]_i_4_n_0\, I3 => \rx_cdrlock_counter[31]_i_5_n_0\, I4 => \rx_cdrlock_counter_reg[24]_i_2_n_5\, O => rx_cdrlock_counter_0(23) ); \rx_cdrlock_counter[24]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0000" ) port map ( I0 => \rx_cdrlock_counter[31]_i_2_n_0\, I1 => \rx_cdrlock_counter[31]_i_3_n_0\, I2 => \rx_cdrlock_counter[31]_i_4_n_0\, I3 => \rx_cdrlock_counter[31]_i_5_n_0\, I4 => \rx_cdrlock_counter_reg[24]_i_2_n_4\, O => rx_cdrlock_counter_0(24) ); \rx_cdrlock_counter[25]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0000" ) port map ( I0 => \rx_cdrlock_counter[31]_i_2_n_0\, I1 => \rx_cdrlock_counter[31]_i_3_n_0\, I2 => \rx_cdrlock_counter[31]_i_4_n_0\, I3 => \rx_cdrlock_counter[31]_i_5_n_0\, I4 => \rx_cdrlock_counter_reg[28]_i_2_n_7\, O => rx_cdrlock_counter_0(25) ); \rx_cdrlock_counter[26]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0000" ) port map ( I0 => \rx_cdrlock_counter[31]_i_2_n_0\, I1 => \rx_cdrlock_counter[31]_i_3_n_0\, I2 => \rx_cdrlock_counter[31]_i_4_n_0\, I3 => \rx_cdrlock_counter[31]_i_5_n_0\, I4 => \rx_cdrlock_counter_reg[28]_i_2_n_6\, O => rx_cdrlock_counter_0(26) ); \rx_cdrlock_counter[27]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0000" ) port map ( I0 => \rx_cdrlock_counter[31]_i_2_n_0\, I1 => \rx_cdrlock_counter[31]_i_3_n_0\, I2 => \rx_cdrlock_counter[31]_i_4_n_0\, I3 => \rx_cdrlock_counter[31]_i_5_n_0\, I4 => \rx_cdrlock_counter_reg[28]_i_2_n_5\, O => rx_cdrlock_counter_0(27) ); \rx_cdrlock_counter[28]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0000" ) port map ( I0 => \rx_cdrlock_counter[31]_i_2_n_0\, I1 => \rx_cdrlock_counter[31]_i_3_n_0\, I2 => \rx_cdrlock_counter[31]_i_4_n_0\, I3 => \rx_cdrlock_counter[31]_i_5_n_0\, I4 => \rx_cdrlock_counter_reg[28]_i_2_n_4\, O => rx_cdrlock_counter_0(28) ); \rx_cdrlock_counter[29]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0000" ) port map ( I0 => \rx_cdrlock_counter[31]_i_2_n_0\, I1 => \rx_cdrlock_counter[31]_i_3_n_0\, I2 => \rx_cdrlock_counter[31]_i_4_n_0\, I3 => \rx_cdrlock_counter[31]_i_5_n_0\, I4 => \rx_cdrlock_counter_reg[31]_i_6_n_7\, O => rx_cdrlock_counter_0(29) ); \rx_cdrlock_counter[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0000" ) port map ( I0 => \rx_cdrlock_counter[31]_i_2_n_0\, I1 => \rx_cdrlock_counter[31]_i_3_n_0\, I2 => \rx_cdrlock_counter[31]_i_4_n_0\, I3 => \rx_cdrlock_counter[31]_i_5_n_0\, I4 => \rx_cdrlock_counter_reg[4]_i_2_n_6\, O => rx_cdrlock_counter_0(2) ); \rx_cdrlock_counter[30]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0000" ) port map ( I0 => \rx_cdrlock_counter[31]_i_2_n_0\, I1 => \rx_cdrlock_counter[31]_i_3_n_0\, I2 => \rx_cdrlock_counter[31]_i_4_n_0\, I3 => \rx_cdrlock_counter[31]_i_5_n_0\, I4 => \rx_cdrlock_counter_reg[31]_i_6_n_6\, O => rx_cdrlock_counter_0(30) ); \rx_cdrlock_counter[31]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0000" ) port map ( I0 => \rx_cdrlock_counter[31]_i_2_n_0\, I1 => \rx_cdrlock_counter[31]_i_3_n_0\, I2 => \rx_cdrlock_counter[31]_i_4_n_0\, I3 => \rx_cdrlock_counter[31]_i_5_n_0\, I4 => \rx_cdrlock_counter_reg[31]_i_6_n_5\, O => rx_cdrlock_counter_0(31) ); \rx_cdrlock_counter[31]_i_10\: unisim.vcomponents.LUT4 generic map( INIT => X"FFDF" ) port map ( I0 => rx_cdrlock_counter(13), I1 => rx_cdrlock_counter(12), I2 => rx_cdrlock_counter(14), I3 => rx_cdrlock_counter(15), O => \rx_cdrlock_counter[31]_i_10_n_0\ ); \rx_cdrlock_counter[31]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFBFF" ) port map ( I0 => rx_cdrlock_counter(18), I1 => rx_cdrlock_counter(19), I2 => rx_cdrlock_counter(17), I3 => rx_cdrlock_counter(16), I4 => \rx_cdrlock_counter[31]_i_7_n_0\, O => \rx_cdrlock_counter[31]_i_2_n_0\ ); \rx_cdrlock_counter[31]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFFFE" ) port map ( I0 => rx_cdrlock_counter(26), I1 => rx_cdrlock_counter(27), I2 => rx_cdrlock_counter(24), I3 => rx_cdrlock_counter(25), I4 => \rx_cdrlock_counter[31]_i_8_n_0\, O => \rx_cdrlock_counter[31]_i_3_n_0\ ); \rx_cdrlock_counter[31]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFBFFF" ) port map ( I0 => rx_cdrlock_counter(2), I1 => rx_cdrlock_counter(3), I2 => rx_cdrlock_counter(0), I3 => rx_cdrlock_counter(1), I4 => \rx_cdrlock_counter[31]_i_9_n_0\, O => \rx_cdrlock_counter[31]_i_4_n_0\ ); \rx_cdrlock_counter[31]_i_5\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFFFB" ) port map ( I0 => rx_cdrlock_counter(10), I1 => rx_cdrlock_counter(11), I2 => rx_cdrlock_counter(8), I3 => rx_cdrlock_counter(9), I4 => \rx_cdrlock_counter[31]_i_10_n_0\, O => \rx_cdrlock_counter[31]_i_5_n_0\ ); \rx_cdrlock_counter[31]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => rx_cdrlock_counter(21), I1 => rx_cdrlock_counter(20), I2 => rx_cdrlock_counter(23), I3 => rx_cdrlock_counter(22), O => \rx_cdrlock_counter[31]_i_7_n_0\ ); \rx_cdrlock_counter[31]_i_8\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => rx_cdrlock_counter(29), I1 => rx_cdrlock_counter(28), I2 => rx_cdrlock_counter(31), I3 => rx_cdrlock_counter(30), O => \rx_cdrlock_counter[31]_i_8_n_0\ ); \rx_cdrlock_counter[31]_i_9\: unisim.vcomponents.LUT4 generic map( INIT => X"DFFF" ) port map ( I0 => rx_cdrlock_counter(4), I1 => rx_cdrlock_counter(5), I2 => rx_cdrlock_counter(7), I3 => rx_cdrlock_counter(6), O => \rx_cdrlock_counter[31]_i_9_n_0\ ); \rx_cdrlock_counter[3]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAAB" ) port map ( I0 => \rx_cdrlock_counter_reg[4]_i_2_n_5\, I1 => \rx_cdrlock_counter[31]_i_2_n_0\, I2 => \rx_cdrlock_counter[31]_i_3_n_0\, I3 => \rx_cdrlock_counter[31]_i_4_n_0\, I4 => \rx_cdrlock_counter[31]_i_5_n_0\, O => rx_cdrlock_counter_0(3) ); \rx_cdrlock_counter[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAAB" ) port map ( I0 => \rx_cdrlock_counter_reg[4]_i_2_n_4\, I1 => \rx_cdrlock_counter[31]_i_2_n_0\, I2 => \rx_cdrlock_counter[31]_i_3_n_0\, I3 => \rx_cdrlock_counter[31]_i_4_n_0\, I4 => \rx_cdrlock_counter[31]_i_5_n_0\, O => rx_cdrlock_counter_0(4) ); \rx_cdrlock_counter[5]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0000" ) port map ( I0 => \rx_cdrlock_counter[31]_i_2_n_0\, I1 => \rx_cdrlock_counter[31]_i_3_n_0\, I2 => \rx_cdrlock_counter[31]_i_4_n_0\, I3 => \rx_cdrlock_counter[31]_i_5_n_0\, I4 => \rx_cdrlock_counter_reg[8]_i_2_n_7\, O => rx_cdrlock_counter_0(5) ); \rx_cdrlock_counter[6]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAAB" ) port map ( I0 => \rx_cdrlock_counter_reg[8]_i_2_n_6\, I1 => \rx_cdrlock_counter[31]_i_2_n_0\, I2 => \rx_cdrlock_counter[31]_i_3_n_0\, I3 => \rx_cdrlock_counter[31]_i_4_n_0\, I4 => \rx_cdrlock_counter[31]_i_5_n_0\, O => rx_cdrlock_counter_0(6) ); \rx_cdrlock_counter[7]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAAB" ) port map ( I0 => \rx_cdrlock_counter_reg[8]_i_2_n_5\, I1 => \rx_cdrlock_counter[31]_i_2_n_0\, I2 => \rx_cdrlock_counter[31]_i_3_n_0\, I3 => \rx_cdrlock_counter[31]_i_4_n_0\, I4 => \rx_cdrlock_counter[31]_i_5_n_0\, O => rx_cdrlock_counter_0(7) ); \rx_cdrlock_counter[8]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0000" ) port map ( I0 => \rx_cdrlock_counter[31]_i_2_n_0\, I1 => \rx_cdrlock_counter[31]_i_3_n_0\, I2 => \rx_cdrlock_counter[31]_i_4_n_0\, I3 => \rx_cdrlock_counter[31]_i_5_n_0\, I4 => \rx_cdrlock_counter_reg[8]_i_2_n_4\, O => rx_cdrlock_counter_0(8) ); \rx_cdrlock_counter[9]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0000" ) port map ( I0 => \rx_cdrlock_counter[31]_i_2_n_0\, I1 => \rx_cdrlock_counter[31]_i_3_n_0\, I2 => \rx_cdrlock_counter[31]_i_4_n_0\, I3 => \rx_cdrlock_counter[31]_i_5_n_0\, I4 => \rx_cdrlock_counter_reg[12]_i_2_n_7\, O => rx_cdrlock_counter_0(9) ); \rx_cdrlock_counter_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => \rx_cdrlock_counter[0]_i_1_n_0\, Q => rx_cdrlock_counter(0), R => \^gtrxreset_i_reg_0\(0) ); \rx_cdrlock_counter_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => rx_cdrlock_counter_0(10), Q => rx_cdrlock_counter(10), R => \^gtrxreset_i_reg_0\(0) ); \rx_cdrlock_counter_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => rx_cdrlock_counter_0(11), Q => rx_cdrlock_counter(11), R => \^gtrxreset_i_reg_0\(0) ); \rx_cdrlock_counter_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => rx_cdrlock_counter_0(12), Q => rx_cdrlock_counter(12), R => \^gtrxreset_i_reg_0\(0) ); \rx_cdrlock_counter_reg[12]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => \rx_cdrlock_counter_reg[8]_i_2_n_0\, CO(3) => \rx_cdrlock_counter_reg[12]_i_2_n_0\, CO(2) => \rx_cdrlock_counter_reg[12]_i_2_n_1\, CO(1) => \rx_cdrlock_counter_reg[12]_i_2_n_2\, CO(0) => \rx_cdrlock_counter_reg[12]_i_2_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \rx_cdrlock_counter_reg[12]_i_2_n_4\, O(2) => \rx_cdrlock_counter_reg[12]_i_2_n_5\, O(1) => \rx_cdrlock_counter_reg[12]_i_2_n_6\, O(0) => \rx_cdrlock_counter_reg[12]_i_2_n_7\, S(3 downto 0) => rx_cdrlock_counter(12 downto 9) ); \rx_cdrlock_counter_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => rx_cdrlock_counter_0(13), Q => rx_cdrlock_counter(13), R => \^gtrxreset_i_reg_0\(0) ); \rx_cdrlock_counter_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => rx_cdrlock_counter_0(14), Q => rx_cdrlock_counter(14), R => \^gtrxreset_i_reg_0\(0) ); \rx_cdrlock_counter_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => rx_cdrlock_counter_0(15), Q => rx_cdrlock_counter(15), R => \^gtrxreset_i_reg_0\(0) ); \rx_cdrlock_counter_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => rx_cdrlock_counter_0(16), Q => rx_cdrlock_counter(16), R => \^gtrxreset_i_reg_0\(0) ); \rx_cdrlock_counter_reg[16]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => \rx_cdrlock_counter_reg[12]_i_2_n_0\, CO(3) => \rx_cdrlock_counter_reg[16]_i_2_n_0\, CO(2) => \rx_cdrlock_counter_reg[16]_i_2_n_1\, CO(1) => \rx_cdrlock_counter_reg[16]_i_2_n_2\, CO(0) => \rx_cdrlock_counter_reg[16]_i_2_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \rx_cdrlock_counter_reg[16]_i_2_n_4\, O(2) => \rx_cdrlock_counter_reg[16]_i_2_n_5\, O(1) => \rx_cdrlock_counter_reg[16]_i_2_n_6\, O(0) => \rx_cdrlock_counter_reg[16]_i_2_n_7\, S(3 downto 0) => rx_cdrlock_counter(16 downto 13) ); \rx_cdrlock_counter_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => rx_cdrlock_counter_0(17), Q => rx_cdrlock_counter(17), R => \^gtrxreset_i_reg_0\(0) ); \rx_cdrlock_counter_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => rx_cdrlock_counter_0(18), Q => rx_cdrlock_counter(18), R => \^gtrxreset_i_reg_0\(0) ); \rx_cdrlock_counter_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => rx_cdrlock_counter_0(19), Q => rx_cdrlock_counter(19), R => \^gtrxreset_i_reg_0\(0) ); \rx_cdrlock_counter_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => rx_cdrlock_counter_0(1), Q => rx_cdrlock_counter(1), R => \^gtrxreset_i_reg_0\(0) ); \rx_cdrlock_counter_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => rx_cdrlock_counter_0(20), Q => rx_cdrlock_counter(20), R => \^gtrxreset_i_reg_0\(0) ); \rx_cdrlock_counter_reg[20]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => \rx_cdrlock_counter_reg[16]_i_2_n_0\, CO(3) => \rx_cdrlock_counter_reg[20]_i_2_n_0\, CO(2) => \rx_cdrlock_counter_reg[20]_i_2_n_1\, CO(1) => \rx_cdrlock_counter_reg[20]_i_2_n_2\, CO(0) => \rx_cdrlock_counter_reg[20]_i_2_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \rx_cdrlock_counter_reg[20]_i_2_n_4\, O(2) => \rx_cdrlock_counter_reg[20]_i_2_n_5\, O(1) => \rx_cdrlock_counter_reg[20]_i_2_n_6\, O(0) => \rx_cdrlock_counter_reg[20]_i_2_n_7\, S(3 downto 0) => rx_cdrlock_counter(20 downto 17) ); \rx_cdrlock_counter_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => rx_cdrlock_counter_0(21), Q => rx_cdrlock_counter(21), R => \^gtrxreset_i_reg_0\(0) ); \rx_cdrlock_counter_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => rx_cdrlock_counter_0(22), Q => rx_cdrlock_counter(22), R => \^gtrxreset_i_reg_0\(0) ); \rx_cdrlock_counter_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => rx_cdrlock_counter_0(23), Q => rx_cdrlock_counter(23), R => \^gtrxreset_i_reg_0\(0) ); \rx_cdrlock_counter_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => rx_cdrlock_counter_0(24), Q => rx_cdrlock_counter(24), R => \^gtrxreset_i_reg_0\(0) ); \rx_cdrlock_counter_reg[24]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => \rx_cdrlock_counter_reg[20]_i_2_n_0\, CO(3) => \rx_cdrlock_counter_reg[24]_i_2_n_0\, CO(2) => \rx_cdrlock_counter_reg[24]_i_2_n_1\, CO(1) => \rx_cdrlock_counter_reg[24]_i_2_n_2\, CO(0) => \rx_cdrlock_counter_reg[24]_i_2_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \rx_cdrlock_counter_reg[24]_i_2_n_4\, O(2) => \rx_cdrlock_counter_reg[24]_i_2_n_5\, O(1) => \rx_cdrlock_counter_reg[24]_i_2_n_6\, O(0) => \rx_cdrlock_counter_reg[24]_i_2_n_7\, S(3 downto 0) => rx_cdrlock_counter(24 downto 21) ); \rx_cdrlock_counter_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => rx_cdrlock_counter_0(25), Q => rx_cdrlock_counter(25), R => \^gtrxreset_i_reg_0\(0) ); \rx_cdrlock_counter_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => rx_cdrlock_counter_0(26), Q => rx_cdrlock_counter(26), R => \^gtrxreset_i_reg_0\(0) ); \rx_cdrlock_counter_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => rx_cdrlock_counter_0(27), Q => rx_cdrlock_counter(27), R => \^gtrxreset_i_reg_0\(0) ); \rx_cdrlock_counter_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => rx_cdrlock_counter_0(28), Q => rx_cdrlock_counter(28), R => \^gtrxreset_i_reg_0\(0) ); \rx_cdrlock_counter_reg[28]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => \rx_cdrlock_counter_reg[24]_i_2_n_0\, CO(3) => \rx_cdrlock_counter_reg[28]_i_2_n_0\, CO(2) => \rx_cdrlock_counter_reg[28]_i_2_n_1\, CO(1) => \rx_cdrlock_counter_reg[28]_i_2_n_2\, CO(0) => \rx_cdrlock_counter_reg[28]_i_2_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \rx_cdrlock_counter_reg[28]_i_2_n_4\, O(2) => \rx_cdrlock_counter_reg[28]_i_2_n_5\, O(1) => \rx_cdrlock_counter_reg[28]_i_2_n_6\, O(0) => \rx_cdrlock_counter_reg[28]_i_2_n_7\, S(3 downto 0) => rx_cdrlock_counter(28 downto 25) ); \rx_cdrlock_counter_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => rx_cdrlock_counter_0(29), Q => rx_cdrlock_counter(29), R => \^gtrxreset_i_reg_0\(0) ); \rx_cdrlock_counter_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => rx_cdrlock_counter_0(2), Q => rx_cdrlock_counter(2), R => \^gtrxreset_i_reg_0\(0) ); \rx_cdrlock_counter_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => rx_cdrlock_counter_0(30), Q => rx_cdrlock_counter(30), R => \^gtrxreset_i_reg_0\(0) ); \rx_cdrlock_counter_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => rx_cdrlock_counter_0(31), Q => rx_cdrlock_counter(31), R => \^gtrxreset_i_reg_0\(0) ); \rx_cdrlock_counter_reg[31]_i_6\: unisim.vcomponents.CARRY4 port map ( CI => \rx_cdrlock_counter_reg[28]_i_2_n_0\, CO(3 downto 2) => \NLW_rx_cdrlock_counter_reg[31]_i_6_CO_UNCONNECTED\(3 downto 2), CO(1) => \rx_cdrlock_counter_reg[31]_i_6_n_2\, CO(0) => \rx_cdrlock_counter_reg[31]_i_6_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \NLW_rx_cdrlock_counter_reg[31]_i_6_O_UNCONNECTED\(3), O(2) => \rx_cdrlock_counter_reg[31]_i_6_n_5\, O(1) => \rx_cdrlock_counter_reg[31]_i_6_n_6\, O(0) => \rx_cdrlock_counter_reg[31]_i_6_n_7\, S(3) => '0', S(2 downto 0) => rx_cdrlock_counter(31 downto 29) ); \rx_cdrlock_counter_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => rx_cdrlock_counter_0(3), Q => rx_cdrlock_counter(3), R => \^gtrxreset_i_reg_0\(0) ); \rx_cdrlock_counter_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => rx_cdrlock_counter_0(4), Q => rx_cdrlock_counter(4), R => \^gtrxreset_i_reg_0\(0) ); \rx_cdrlock_counter_reg[4]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \rx_cdrlock_counter_reg[4]_i_2_n_0\, CO(2) => \rx_cdrlock_counter_reg[4]_i_2_n_1\, CO(1) => \rx_cdrlock_counter_reg[4]_i_2_n_2\, CO(0) => \rx_cdrlock_counter_reg[4]_i_2_n_3\, CYINIT => rx_cdrlock_counter(0), DI(3 downto 0) => B"0000", O(3) => \rx_cdrlock_counter_reg[4]_i_2_n_4\, O(2) => \rx_cdrlock_counter_reg[4]_i_2_n_5\, O(1) => \rx_cdrlock_counter_reg[4]_i_2_n_6\, O(0) => \rx_cdrlock_counter_reg[4]_i_2_n_7\, S(3 downto 0) => rx_cdrlock_counter(4 downto 1) ); \rx_cdrlock_counter_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => rx_cdrlock_counter_0(5), Q => rx_cdrlock_counter(5), R => \^gtrxreset_i_reg_0\(0) ); \rx_cdrlock_counter_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => rx_cdrlock_counter_0(6), Q => rx_cdrlock_counter(6), R => \^gtrxreset_i_reg_0\(0) ); \rx_cdrlock_counter_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => rx_cdrlock_counter_0(7), Q => rx_cdrlock_counter(7), R => \^gtrxreset_i_reg_0\(0) ); \rx_cdrlock_counter_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => rx_cdrlock_counter_0(8), Q => rx_cdrlock_counter(8), R => \^gtrxreset_i_reg_0\(0) ); \rx_cdrlock_counter_reg[8]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => \rx_cdrlock_counter_reg[4]_i_2_n_0\, CO(3) => \rx_cdrlock_counter_reg[8]_i_2_n_0\, CO(2) => \rx_cdrlock_counter_reg[8]_i_2_n_1\, CO(1) => \rx_cdrlock_counter_reg[8]_i_2_n_2\, CO(0) => \rx_cdrlock_counter_reg[8]_i_2_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \rx_cdrlock_counter_reg[8]_i_2_n_4\, O(2) => \rx_cdrlock_counter_reg[8]_i_2_n_5\, O(1) => \rx_cdrlock_counter_reg[8]_i_2_n_6\, O(0) => \rx_cdrlock_counter_reg[8]_i_2_n_7\, S(3 downto 0) => rx_cdrlock_counter(8 downto 5) ); \rx_cdrlock_counter_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => rx_cdrlock_counter_0(9), Q => rx_cdrlock_counter(9), R => \^gtrxreset_i_reg_0\(0) ); rx_cdrlocked_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAAB" ) port map ( I0 => \^rx_clk_locked_i\, I1 => \rx_cdrlock_counter[31]_i_2_n_0\, I2 => \rx_cdrlock_counter[31]_i_3_n_0\, I3 => \rx_cdrlock_counter[31]_i_4_n_0\, I4 => \rx_cdrlock_counter[31]_i_5_n_0\, O => rx_cdrlocked_i_1_n_0 ); rx_cdrlocked_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => rx_cdrlocked_i_1_n_0, Q => \^rx_clk_locked_i\, R => \^gtrxreset_i_reg_0\(0) ); rx_fsm_reset_done_int_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFA8FF0000A800" ) port map ( I0 => rx_state(7), I1 => time_out_1us_reg_n_0, I2 => rx_fsm_reset_done_int, I3 => rx_fsm_reset_done_int_i_2_n_0, I4 => rx_fsm_reset_done_int_i_3_n_0, I5 => rx_fsm_reset_done_int, O => rx_fsm_reset_done_int_i_1_n_0 ); rx_fsm_reset_done_int_i_2: unisim.vcomponents.LUT5 generic map( INIT => X"00010100" ) port map ( I0 => rx_state(4), I1 => rx_state(5), I2 => rx_state(0), I3 => rx_state(7), I4 => rx_state(6), O => rx_fsm_reset_done_int_i_2_n_0 ); rx_fsm_reset_done_int_i_3: unisim.vcomponents.LUT3 generic map( INIT => X"FE" ) port map ( I0 => rx_state(1), I1 => rx_state(3), I2 => rx_state(2), O => rx_fsm_reset_done_int_i_3_n_0 ); rx_fsm_reset_done_int_reg: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', CLR => AR(0), D => rx_fsm_reset_done_int_i_1_n_0, Q => rx_fsm_reset_done_int ); \rx_state[0]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"4444004000400040" ) port map ( I0 => \rx_state[7]_i_6_n_0\, I1 => \rx_state[7]_i_7_n_0\, I2 => rx_state(0), I3 => time_out_1us_reg_n_0, I4 => init_wait_done_reg_n_0, I5 => \rx_state[7]_i_5_n_0\, O => \rx_state[0]_i_2_n_0\ ); \rx_state[0]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"0001000100010000" ) port map ( I0 => rx_state(3), I1 => rx_state(4), I2 => rx_state(5), I3 => rx_state(6), I4 => rx_state(1), I5 => rx_state(2), O => \rx_state[0]_i_5_n_0\ ); \rx_state[1]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAAA8" ) port map ( I0 => time_out_1us_reg_n_0, I1 => rx_state(0), I2 => rx_state(2), I3 => rx_state(4), I4 => rx_state(6), O => \rx_state[1]_i_3_n_0\ ); \rx_state[3]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFF1" ) port map ( I0 => rx_state(3), I1 => rx_state(4), I2 => rx_state(5), I3 => rx_state(6), I4 => rx_state(1), I5 => rx_state(2), O => \rx_state[3]_i_4_n_0\ ); \rx_state[7]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"000101FF00010105" ) port map ( I0 => \rx_state[7]_i_3_n_0\, I1 => rx_state(3), I2 => rx_state(2), I3 => rx_state(1), I4 => rx_state(0), I5 => \rx_state[7]_i_4_n_0\, O => \rx_state[7]_i_1_n_0\ ); \rx_state[7]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"AABA" ) port map ( I0 => rx_state(7), I1 => \rx_state[7]_i_5_n_0\, I2 => \rx_state[7]_i_6_n_0\, I3 => \rx_state[7]_i_7_n_0\, O => \p_0_in__0\(7) ); \rx_state[7]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => rx_state(4), I1 => rx_state(7), I2 => rx_state(6), I3 => rx_state(5), O => \rx_state[7]_i_3_n_0\ ); \rx_state[7]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000010117" ) port map ( I0 => rx_state(2), I1 => rx_state(4), I2 => rx_state(7), I3 => rx_state(6), I4 => rx_state(5), I5 => rx_state(3), O => \rx_state[7]_i_4_n_0\ ); \rx_state[7]_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => rx_state(6), I1 => rx_state(4), I2 => rx_state(2), I3 => rx_state(0), O => \rx_state[7]_i_5_n_0\ ); \rx_state[7]_i_6\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => rx_state(2), I1 => rx_state(1), I2 => rx_state(6), I3 => rx_state(5), O => \rx_state[7]_i_6_n_0\ ); \rx_state[7]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => rx_state(6), I1 => rx_state(5), I2 => rx_state(4), I3 => rx_state(3), O => \rx_state[7]_i_7_n_0\ ); \rx_state_reg[0]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => \rx_state[7]_i_1_n_0\, CLR => AR(0), D => \p_0_in__0\(0), Q => rx_state(0) ); \rx_state_reg[1]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => \rx_state[7]_i_1_n_0\, CLR => AR(0), D => \p_0_in__0\(1), Q => rx_state(1) ); \rx_state_reg[2]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => \rx_state[7]_i_1_n_0\, CLR => AR(0), D => \p_0_in__0\(2), Q => rx_state(2) ); \rx_state_reg[3]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => \rx_state[7]_i_1_n_0\, CLR => AR(0), D => \p_0_in__0\(3), Q => rx_state(3) ); \rx_state_reg[4]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => \rx_state[7]_i_1_n_0\, CLR => AR(0), D => \p_0_in__0\(4), Q => rx_state(4) ); \rx_state_reg[5]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => \rx_state[7]_i_1_n_0\, CLR => AR(0), D => \p_0_in__0\(5), Q => rx_state(5) ); \rx_state_reg[6]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => \rx_state[7]_i_1_n_0\, CLR => AR(0), D => \p_0_in__0\(6), Q => rx_state(6) ); \rx_state_reg[7]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => \rx_state[7]_i_1_n_0\, CLR => AR(0), D => \p_0_in__0\(7), Q => rx_state(7) ); time_out_1us_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"00000000AAAAAABA" ) port map ( I0 => time_out_1us_reg_n_0, I1 => time_out_1us_i_2_n_0, I2 => time_out_1us_i_3_n_0, I3 => time_out_1us_i_4_n_0, I4 => time_out_1us_i_5_n_0, I5 => reset_time_out_reg_n_0, O => time_out_1us_i_1_n_0 ); time_out_1us_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFEFFF" ) port map ( I0 => time_out_counter_reg(17), I1 => time_out_counter_reg(18), I2 => time_out_counter_reg(1), I3 => time_out_counter_reg(6), I4 => time_out_counter_reg(16), I5 => time_out_counter_reg(15), O => time_out_1us_i_2_n_0 ); time_out_1us_i_3: unisim.vcomponents.LUT4 generic map( INIT => X"0040" ) port map ( I0 => time_out_counter_reg(2), I1 => time_out_counter_reg(0), I2 => time_out_counter_reg(4), I3 => time_out_counter_reg(3), O => time_out_1us_i_3_n_0 ); time_out_1us_i_4: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => time_out_counter_reg(5), I1 => time_out_counter_reg(13), I2 => time_out_counter_reg(7), I3 => time_out_counter_reg(14), O => time_out_1us_i_4_n_0 ); time_out_1us_i_5: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFFFE" ) port map ( I0 => time_out_counter_reg(10), I1 => time_out_counter_reg(12), I2 => time_out_counter_reg(9), I3 => time_out_counter_reg(8), I4 => time_out_counter_reg(11), O => time_out_1us_i_5_n_0 ); time_out_1us_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => time_out_1us_i_1_n_0, Q => time_out_1us_reg_n_0, R => '0' ); \time_out_2ms_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"00000000AAAAAABA" ) port map ( I0 => time_out_2ms_reg_n_0, I1 => \time_out_counter[0]_i_4__0_n_0\, I2 => time_out_2ms_i_2_n_0, I3 => time_out_1us_i_4_n_0, I4 => \time_out_counter[0]_i_3__0_n_0\, I5 => reset_time_out_reg_n_0, O => \time_out_2ms_i_1__0_n_0\ ); time_out_2ms_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000800" ) port map ( I0 => time_out_counter_reg(11), I1 => time_out_counter_reg(1), I2 => time_out_counter_reg(10), I3 => time_out_counter_reg(17), I4 => time_out_counter_reg(12), I5 => time_out_counter_reg(4), O => time_out_2ms_i_2_n_0 ); time_out_2ms_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => \time_out_2ms_i_1__0_n_0\, Q => time_out_2ms_reg_n_0, R => '0' ); \time_out_counter[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFE" ) port map ( I0 => \time_out_counter[0]_i_3__0_n_0\, I1 => time_out_counter_reg(13), I2 => time_out_counter_reg(7), I3 => time_out_counter_reg(14), I4 => \time_out_counter[0]_i_4__0_n_0\, I5 => \time_out_counter[0]_i_5_n_0\, O => time_out_counter ); \time_out_counter[0]_i_3__0\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFDFF" ) port map ( I0 => time_out_counter_reg(3), I1 => time_out_counter_reg(0), I2 => time_out_counter_reg(18), I3 => time_out_counter_reg(9), I4 => time_out_counter_reg(16), O => \time_out_counter[0]_i_3__0_n_0\ ); \time_out_counter[0]_i_4__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FFF7" ) port map ( I0 => time_out_counter_reg(15), I1 => time_out_counter_reg(8), I2 => time_out_counter_reg(6), I3 => time_out_counter_reg(2), O => \time_out_counter[0]_i_4__0_n_0\ ); \time_out_counter[0]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFD" ) port map ( I0 => time_out_counter_reg(17), I1 => time_out_counter_reg(12), I2 => time_out_counter_reg(10), I3 => \time_out_counter[0]_i_7__0_n_0\, I4 => time_out_counter_reg(4), I5 => time_out_counter_reg(5), O => \time_out_counter[0]_i_5_n_0\ ); \time_out_counter[0]_i_6\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => time_out_counter_reg(0), O => \time_out_counter[0]_i_6_n_0\ ); \time_out_counter[0]_i_7__0\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => time_out_counter_reg(1), I1 => time_out_counter_reg(11), O => \time_out_counter[0]_i_7__0_n_0\ ); \time_out_counter_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => time_out_counter, D => \time_out_counter_reg[0]_i_2__0_n_7\, Q => time_out_counter_reg(0), R => reset_time_out_reg_n_0 ); \time_out_counter_reg[0]_i_2__0\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \time_out_counter_reg[0]_i_2__0_n_0\, CO(2) => \time_out_counter_reg[0]_i_2__0_n_1\, CO(1) => \time_out_counter_reg[0]_i_2__0_n_2\, CO(0) => \time_out_counter_reg[0]_i_2__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0001", O(3) => \time_out_counter_reg[0]_i_2__0_n_4\, O(2) => \time_out_counter_reg[0]_i_2__0_n_5\, O(1) => \time_out_counter_reg[0]_i_2__0_n_6\, O(0) => \time_out_counter_reg[0]_i_2__0_n_7\, S(3 downto 1) => time_out_counter_reg(3 downto 1), S(0) => \time_out_counter[0]_i_6_n_0\ ); \time_out_counter_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => time_out_counter, D => \time_out_counter_reg[8]_i_1__0_n_5\, Q => time_out_counter_reg(10), R => reset_time_out_reg_n_0 ); \time_out_counter_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => time_out_counter, D => \time_out_counter_reg[8]_i_1__0_n_4\, Q => time_out_counter_reg(11), R => reset_time_out_reg_n_0 ); \time_out_counter_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => time_out_counter, D => \time_out_counter_reg[12]_i_1__0_n_7\, Q => time_out_counter_reg(12), R => reset_time_out_reg_n_0 ); \time_out_counter_reg[12]_i_1__0\: unisim.vcomponents.CARRY4 port map ( CI => \time_out_counter_reg[8]_i_1__0_n_0\, CO(3) => \time_out_counter_reg[12]_i_1__0_n_0\, CO(2) => \time_out_counter_reg[12]_i_1__0_n_1\, CO(1) => \time_out_counter_reg[12]_i_1__0_n_2\, CO(0) => \time_out_counter_reg[12]_i_1__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \time_out_counter_reg[12]_i_1__0_n_4\, O(2) => \time_out_counter_reg[12]_i_1__0_n_5\, O(1) => \time_out_counter_reg[12]_i_1__0_n_6\, O(0) => \time_out_counter_reg[12]_i_1__0_n_7\, S(3 downto 0) => time_out_counter_reg(15 downto 12) ); \time_out_counter_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => time_out_counter, D => \time_out_counter_reg[12]_i_1__0_n_6\, Q => time_out_counter_reg(13), R => reset_time_out_reg_n_0 ); \time_out_counter_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => time_out_counter, D => \time_out_counter_reg[12]_i_1__0_n_5\, Q => time_out_counter_reg(14), R => reset_time_out_reg_n_0 ); \time_out_counter_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => time_out_counter, D => \time_out_counter_reg[12]_i_1__0_n_4\, Q => time_out_counter_reg(15), R => reset_time_out_reg_n_0 ); \time_out_counter_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => time_out_counter, D => \time_out_counter_reg[16]_i_1__0_n_7\, Q => time_out_counter_reg(16), R => reset_time_out_reg_n_0 ); \time_out_counter_reg[16]_i_1__0\: unisim.vcomponents.CARRY4 port map ( CI => \time_out_counter_reg[12]_i_1__0_n_0\, CO(3 downto 2) => \NLW_time_out_counter_reg[16]_i_1__0_CO_UNCONNECTED\(3 downto 2), CO(1) => \time_out_counter_reg[16]_i_1__0_n_2\, CO(0) => \time_out_counter_reg[16]_i_1__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \NLW_time_out_counter_reg[16]_i_1__0_O_UNCONNECTED\(3), O(2) => \time_out_counter_reg[16]_i_1__0_n_5\, O(1) => \time_out_counter_reg[16]_i_1__0_n_6\, O(0) => \time_out_counter_reg[16]_i_1__0_n_7\, S(3) => '0', S(2 downto 0) => time_out_counter_reg(18 downto 16) ); \time_out_counter_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => time_out_counter, D => \time_out_counter_reg[16]_i_1__0_n_6\, Q => time_out_counter_reg(17), R => reset_time_out_reg_n_0 ); \time_out_counter_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => time_out_counter, D => \time_out_counter_reg[16]_i_1__0_n_5\, Q => time_out_counter_reg(18), R => reset_time_out_reg_n_0 ); \time_out_counter_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => time_out_counter, D => \time_out_counter_reg[0]_i_2__0_n_6\, Q => time_out_counter_reg(1), R => reset_time_out_reg_n_0 ); \time_out_counter_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => time_out_counter, D => \time_out_counter_reg[0]_i_2__0_n_5\, Q => time_out_counter_reg(2), R => reset_time_out_reg_n_0 ); \time_out_counter_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => time_out_counter, D => \time_out_counter_reg[0]_i_2__0_n_4\, Q => time_out_counter_reg(3), R => reset_time_out_reg_n_0 ); \time_out_counter_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => time_out_counter, D => \time_out_counter_reg[4]_i_1__0_n_7\, Q => time_out_counter_reg(4), R => reset_time_out_reg_n_0 ); \time_out_counter_reg[4]_i_1__0\: unisim.vcomponents.CARRY4 port map ( CI => \time_out_counter_reg[0]_i_2__0_n_0\, CO(3) => \time_out_counter_reg[4]_i_1__0_n_0\, CO(2) => \time_out_counter_reg[4]_i_1__0_n_1\, CO(1) => \time_out_counter_reg[4]_i_1__0_n_2\, CO(0) => \time_out_counter_reg[4]_i_1__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \time_out_counter_reg[4]_i_1__0_n_4\, O(2) => \time_out_counter_reg[4]_i_1__0_n_5\, O(1) => \time_out_counter_reg[4]_i_1__0_n_6\, O(0) => \time_out_counter_reg[4]_i_1__0_n_7\, S(3 downto 0) => time_out_counter_reg(7 downto 4) ); \time_out_counter_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => time_out_counter, D => \time_out_counter_reg[4]_i_1__0_n_6\, Q => time_out_counter_reg(5), R => reset_time_out_reg_n_0 ); \time_out_counter_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => time_out_counter, D => \time_out_counter_reg[4]_i_1__0_n_5\, Q => time_out_counter_reg(6), R => reset_time_out_reg_n_0 ); \time_out_counter_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => time_out_counter, D => \time_out_counter_reg[4]_i_1__0_n_4\, Q => time_out_counter_reg(7), R => reset_time_out_reg_n_0 ); \time_out_counter_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => time_out_counter, D => \time_out_counter_reg[8]_i_1__0_n_7\, Q => time_out_counter_reg(8), R => reset_time_out_reg_n_0 ); \time_out_counter_reg[8]_i_1__0\: unisim.vcomponents.CARRY4 port map ( CI => \time_out_counter_reg[4]_i_1__0_n_0\, CO(3) => \time_out_counter_reg[8]_i_1__0_n_0\, CO(2) => \time_out_counter_reg[8]_i_1__0_n_1\, CO(1) => \time_out_counter_reg[8]_i_1__0_n_2\, CO(0) => \time_out_counter_reg[8]_i_1__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \time_out_counter_reg[8]_i_1__0_n_4\, O(2) => \time_out_counter_reg[8]_i_1__0_n_5\, O(1) => \time_out_counter_reg[8]_i_1__0_n_6\, O(0) => \time_out_counter_reg[8]_i_1__0_n_7\, S(3 downto 0) => time_out_counter_reg(11 downto 8) ); \time_out_counter_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => time_out_counter, D => \time_out_counter_reg[8]_i_1__0_n_6\, Q => time_out_counter_reg(9), R => reset_time_out_reg_n_0 ); time_out_wait_bypass_i_3: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => time_out_wait_bypass, I1 => time_out_wait_bypass_i_4_n_0, O => time_out_wait_bypass_i_3_n_0 ); time_out_wait_bypass_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFBFF" ) port map ( I0 => time_out_wait_bypass_i_5_n_0, I1 => wait_bypass_count_reg(1), I2 => wait_bypass_count_reg(4), I3 => wait_bypass_count_reg(8), I4 => wait_bypass_count_reg(11), I5 => time_out_wait_bypass_i_6_n_0, O => time_out_wait_bypass_i_4_n_0 ); time_out_wait_bypass_i_5: unisim.vcomponents.LUT4 generic map( INIT => X"DFFF" ) port map ( I0 => wait_bypass_count_reg(7), I1 => wait_bypass_count_reg(10), I2 => wait_bypass_count_reg(9), I3 => wait_bypass_count_reg(0), O => time_out_wait_bypass_i_5_n_0 ); time_out_wait_bypass_i_6: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFFBF" ) port map ( I0 => wait_bypass_count_reg(6), I1 => wait_bypass_count_reg(2), I2 => wait_bypass_count_reg(12), I3 => wait_bypass_count_reg(3), I4 => wait_bypass_count_reg(5), O => time_out_wait_bypass_i_6_n_0 ); time_out_wait_bypass_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => u_rst_sync_rx_fsm_reset_done_n_0, D => time_out_wait_bypass_i_3_n_0, Q => time_out_wait_bypass, R => u_rst_sync_run_phase_align_n_0 ); time_tlock_max_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"0E" ) port map ( I0 => time_tlock_max, I1 => time_tlock_max0, I2 => reset_time_out_reg_n_0, O => time_tlock_max_i_1_n_0 ); time_tlock_max_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"A8A8A8A8A8888888" ) port map ( I0 => check_tlock_max_reg_n_0, I1 => time_tlock_max_i_3_n_0, I2 => time_out_counter_reg(13), I3 => time_out_counter_reg(7), I4 => time_tlock_max_i_4_n_0, I5 => time_out_1us_i_5_n_0, O => time_tlock_max0 ); time_tlock_max_i_3: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFFFE" ) port map ( I0 => time_out_counter_reg(15), I1 => time_out_counter_reg(16), I2 => time_out_counter_reg(18), I3 => time_out_counter_reg(17), I4 => time_out_counter_reg(14), O => time_tlock_max_i_3_n_0 ); time_tlock_max_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"FFFEFEFEFEFEFEFE" ) port map ( I0 => time_out_counter_reg(4), I1 => time_out_counter_reg(5), I2 => time_out_counter_reg(6), I3 => time_out_counter_reg(3), I4 => time_out_counter_reg(2), I5 => time_out_counter_reg(1), O => time_tlock_max_i_4_n_0 ); time_tlock_max_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => time_tlock_max_i_1_n_0, Q => time_tlock_max, R => '0' ); u_rst_sync_mmcm_lock: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_18\ port map ( D(1 downto 0) => \p_0_in__0\(5 downto 4), Q(2) => rx_state(7), Q(1 downto 0) => rx_state(5 downto 4), \out\(1 downto 0) => rx_state(3 downto 2), reset_time_out_reg => \reset_time_out_i_3__0_n_0\, reset_time_out_reg_0 => \reset_time_out_i_4__0_n_0\, reset_time_out_reg_1 => \reset_time_out_i_5__0_n_0\, reset_time_out_reg_2 => reset_time_out_reg_n_0, reset_time_out_reg_3 => \^rx_clk_locked_i\, reset_time_out_reg_4 => u_rst_sync_rxresetdone_n_2, reset_time_out_reg_5 => u_rst_sync_plllock_n_0, \rx_state_reg[3]\ => u_rst_sync_mmcm_lock_n_1, \rx_state_reg[4]\ => \rx_state[7]_i_7_n_0\, \rx_state_reg[4]_0\ => \rx_state[7]_i_6_n_0\, \rx_state_reg[4]_1\ => \rx_state[7]_i_5_n_0\, \rx_state_reg[4]_2\ => u_rst_sync_rxresetdone_n_0, \rx_state_reg[4]_3\ => time_out_2ms_reg_n_0, stg4_reg_0 => stg4_reg, stg5_reg_0 => u_rst_sync_mmcm_lock_n_0, time_tlock_max => time_tlock_max ); u_rst_sync_plllock: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_19\ port map ( D(2 downto 0) => \p_0_in__0\(2 downto 0), Q(3) => rx_state(7), Q(2 downto 0) => rx_state(2 downto 0), \out\ => \out\, \reset_time_out_i_2__0\(1 downto 0) => rx_state(1 downto 0), \reset_time_out_i_2__0_0\ => time_out_1us_reg_n_0, \rx_state_reg[0]\ => \rx_state[0]_i_2_n_0\, \rx_state_reg[0]_0\ => u_rst_sync_rxresetdone_n_1, \rx_state_reg[0]_1\ => \rx_state[0]_i_5_n_0\, \rx_state_reg[1]\ => \rx_state[7]_i_6_n_0\, \rx_state_reg[1]_0\ => \rx_state[7]_i_7_n_0\, \rx_state_reg[1]_1\ => \rx_state[1]_i_3_n_0\, \rx_state_reg[2]\ => \^rx_clk_locked_i\, \rx_state_reg[3]\ => \rx_state[7]_i_5_n_0\, \rx_state_reg[3]_0\ => time_out_2ms_reg_n_0, stg4_reg_0 => stg4_reg, stg5_reg_0 => u_rst_sync_plllock_n_0, stg5_reg_1 => u_rst_sync_plllock_n_1 ); u_rst_sync_run_phase_align: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_20\ port map ( SR => u_rst_sync_run_phase_align_n_0, in0 => run_phase_alignment_int_reg_n_0, stg5_reg_0 => stg4_reg_0 ); u_rst_sync_rx_fsm_reset_done: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_21\ port map ( stg1_aurora_64b66b_0_cdc_to_reg_0 => rx_fsm_reset_done_int, stg5_reg_0 => u_rst_sync_rx_fsm_reset_done_n_0, stg5_reg_1 => u_rst_sync_rx_fsm_reset_done_n_1, stg5_reg_2 => stg4_reg_0, \wait_bypass_count_reg[0]\ => time_out_wait_bypass_i_4_n_0 ); u_rst_sync_rx_reset: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_22 port map ( in0 => in0, rx_reset_r3 => rx_reset_r3, stg5_reg_0 => stg4_reg_0 ); u_rst_sync_rxresetdone: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_23\ port map ( D(0) => \p_0_in__0\(3), Q(2) => rx_state(7), Q(1) => rx_state(3), Q(0) => rx_state(0), \out\(2) => rx_state(7), \out\(1 downto 0) => rx_state(5 downto 4), \rx_state_reg[0]\ => \rx_state[7]_i_7_n_0\, \rx_state_reg[0]_0\ => \rx_state[7]_i_6_n_0\, \rx_state_reg[0]_1\ => u_rst_sync_time_out_wait_bypass_n_0, \rx_state_reg[3]\ => \rx_state[7]_i_5_n_0\, \rx_state_reg[3]_0\ => time_out_2ms_reg_n_0, \rx_state_reg[3]_1\ => u_rst_sync_plllock_n_1, \rx_state_reg[3]_2\ => \^rx_clk_locked_i\, \rx_state_reg[3]_3\ => \rx_state[3]_i_4_n_0\, \rx_state_reg[3]_4\ => u_rst_sync_mmcm_lock_n_0, \rx_state_reg[5]\ => u_rst_sync_rxresetdone_n_2, stg1_aurora_64b66b_0_cdc_to_reg_0 => stg1_aurora_64b66b_0_cdc_to_reg, stg4_reg_0 => stg4_reg, stg5_reg_0 => u_rst_sync_rxresetdone_n_0, time_tlock_max => time_tlock_max, time_tlock_max_reg => u_rst_sync_rxresetdone_n_1 ); u_rst_sync_system_reset: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_24 port map ( SR(0) => SR(0), rx_reset_r3 => rx_reset_r3, stg4_reg_0 => stg4_reg_0, stg5_reg_0 => u_rst_sync_system_reset_n_0 ); u_rst_sync_time_out_wait_bypass: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_25\ port map ( D(0) => \p_0_in__0\(6), Q(1 downto 0) => rx_state(7 downto 6), \out\ => time_out_wait_bypass, \rx_state_reg[6]\ => \rx_state[7]_i_5_n_0\, \rx_state_reg[6]_0\ => \rx_state[7]_i_6_n_0\, \rx_state_reg[6]_1\ => \rx_state[7]_i_7_n_0\, stg4_reg_0 => stg4_reg, stg5_reg_0 => u_rst_sync_time_out_wait_bypass_n_0 ); \wait_bypass_count[0]_i_3\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => wait_bypass_count_reg(0), O => \wait_bypass_count[0]_i_3_n_0\ ); \wait_bypass_count_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => u_rst_sync_rx_fsm_reset_done_n_1, D => \wait_bypass_count_reg[0]_i_2_n_7\, Q => wait_bypass_count_reg(0), R => u_rst_sync_run_phase_align_n_0 ); \wait_bypass_count_reg[0]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \wait_bypass_count_reg[0]_i_2_n_0\, CO(2) => \wait_bypass_count_reg[0]_i_2_n_1\, CO(1) => \wait_bypass_count_reg[0]_i_2_n_2\, CO(0) => \wait_bypass_count_reg[0]_i_2_n_3\, CYINIT => '0', DI(3 downto 0) => B"0001", O(3) => \wait_bypass_count_reg[0]_i_2_n_4\, O(2) => \wait_bypass_count_reg[0]_i_2_n_5\, O(1) => \wait_bypass_count_reg[0]_i_2_n_6\, O(0) => \wait_bypass_count_reg[0]_i_2_n_7\, S(3 downto 1) => wait_bypass_count_reg(3 downto 1), S(0) => \wait_bypass_count[0]_i_3_n_0\ ); \wait_bypass_count_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => u_rst_sync_rx_fsm_reset_done_n_1, D => \wait_bypass_count_reg[8]_i_1__0_n_5\, Q => wait_bypass_count_reg(10), R => u_rst_sync_run_phase_align_n_0 ); \wait_bypass_count_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => u_rst_sync_rx_fsm_reset_done_n_1, D => \wait_bypass_count_reg[8]_i_1__0_n_4\, Q => wait_bypass_count_reg(11), R => u_rst_sync_run_phase_align_n_0 ); \wait_bypass_count_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => u_rst_sync_rx_fsm_reset_done_n_1, D => \wait_bypass_count_reg[12]_i_1__0_n_7\, Q => wait_bypass_count_reg(12), R => u_rst_sync_run_phase_align_n_0 ); \wait_bypass_count_reg[12]_i_1__0\: unisim.vcomponents.CARRY4 port map ( CI => \wait_bypass_count_reg[8]_i_1__0_n_0\, CO(3 downto 0) => \NLW_wait_bypass_count_reg[12]_i_1__0_CO_UNCONNECTED\(3 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 1) => \NLW_wait_bypass_count_reg[12]_i_1__0_O_UNCONNECTED\(3 downto 1), O(0) => \wait_bypass_count_reg[12]_i_1__0_n_7\, S(3 downto 1) => B"000", S(0) => wait_bypass_count_reg(12) ); \wait_bypass_count_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => u_rst_sync_rx_fsm_reset_done_n_1, D => \wait_bypass_count_reg[0]_i_2_n_6\, Q => wait_bypass_count_reg(1), R => u_rst_sync_run_phase_align_n_0 ); \wait_bypass_count_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => u_rst_sync_rx_fsm_reset_done_n_1, D => \wait_bypass_count_reg[0]_i_2_n_5\, Q => wait_bypass_count_reg(2), R => u_rst_sync_run_phase_align_n_0 ); \wait_bypass_count_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => u_rst_sync_rx_fsm_reset_done_n_1, D => \wait_bypass_count_reg[0]_i_2_n_4\, Q => wait_bypass_count_reg(3), R => u_rst_sync_run_phase_align_n_0 ); \wait_bypass_count_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => u_rst_sync_rx_fsm_reset_done_n_1, D => \wait_bypass_count_reg[4]_i_1__0_n_7\, Q => wait_bypass_count_reg(4), R => u_rst_sync_run_phase_align_n_0 ); \wait_bypass_count_reg[4]_i_1__0\: unisim.vcomponents.CARRY4 port map ( CI => \wait_bypass_count_reg[0]_i_2_n_0\, CO(3) => \wait_bypass_count_reg[4]_i_1__0_n_0\, CO(2) => \wait_bypass_count_reg[4]_i_1__0_n_1\, CO(1) => \wait_bypass_count_reg[4]_i_1__0_n_2\, CO(0) => \wait_bypass_count_reg[4]_i_1__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \wait_bypass_count_reg[4]_i_1__0_n_4\, O(2) => \wait_bypass_count_reg[4]_i_1__0_n_5\, O(1) => \wait_bypass_count_reg[4]_i_1__0_n_6\, O(0) => \wait_bypass_count_reg[4]_i_1__0_n_7\, S(3 downto 0) => wait_bypass_count_reg(7 downto 4) ); \wait_bypass_count_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => u_rst_sync_rx_fsm_reset_done_n_1, D => \wait_bypass_count_reg[4]_i_1__0_n_6\, Q => wait_bypass_count_reg(5), R => u_rst_sync_run_phase_align_n_0 ); \wait_bypass_count_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => u_rst_sync_rx_fsm_reset_done_n_1, D => \wait_bypass_count_reg[4]_i_1__0_n_5\, Q => wait_bypass_count_reg(6), R => u_rst_sync_run_phase_align_n_0 ); \wait_bypass_count_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => u_rst_sync_rx_fsm_reset_done_n_1, D => \wait_bypass_count_reg[4]_i_1__0_n_4\, Q => wait_bypass_count_reg(7), R => u_rst_sync_run_phase_align_n_0 ); \wait_bypass_count_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => u_rst_sync_rx_fsm_reset_done_n_1, D => \wait_bypass_count_reg[8]_i_1__0_n_7\, Q => wait_bypass_count_reg(8), R => u_rst_sync_run_phase_align_n_0 ); \wait_bypass_count_reg[8]_i_1__0\: unisim.vcomponents.CARRY4 port map ( CI => \wait_bypass_count_reg[4]_i_1__0_n_0\, CO(3) => \wait_bypass_count_reg[8]_i_1__0_n_0\, CO(2) => \wait_bypass_count_reg[8]_i_1__0_n_1\, CO(1) => \wait_bypass_count_reg[8]_i_1__0_n_2\, CO(0) => \wait_bypass_count_reg[8]_i_1__0_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \wait_bypass_count_reg[8]_i_1__0_n_4\, O(2) => \wait_bypass_count_reg[8]_i_1__0_n_5\, O(1) => \wait_bypass_count_reg[8]_i_1__0_n_6\, O(0) => \wait_bypass_count_reg[8]_i_1__0_n_7\, S(3 downto 0) => wait_bypass_count_reg(11 downto 8) ); \wait_bypass_count_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg_0, CE => u_rst_sync_rx_fsm_reset_done_n_1, D => \wait_bypass_count_reg[8]_i_1__0_n_6\, Q => wait_bypass_count_reg(9), R => u_rst_sync_run_phase_align_n_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_RX_STREAM is port ( m_axi_rx_tvalid : out STD_LOGIC; m_axi_rx_tdata : out STD_LOGIC_VECTOR ( 0 to 63 ); RX_SRC_RDY_N_reg_inv : in STD_LOGIC; \out\ : in STD_LOGIC; SR : in STD_LOGIC_VECTOR ( 0 to 0 ); E : in STD_LOGIC_VECTOR ( 0 to 0 ); D : in STD_LOGIC_VECTOR ( 63 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_RX_STREAM; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_RX_STREAM is begin rx_stream_datapath_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_RX_STREAM_DATAPATH port map ( D(63 downto 0) => D(63 downto 0), E(0) => E(0), RX_SRC_RDY_N_reg_inv_0 => RX_SRC_RDY_N_reg_inv, SR(0) => SR(0), m_axi_rx_tdata(0 to 63) => m_axi_rx_tdata(0 to 63), m_axi_rx_tvalid => m_axi_rx_tvalid, \out\ => \out\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_SUPPORT_RESET_LOGIC is port ( sysreset_from_support : out STD_LOGIC; gt_reset_out : out STD_LOGIC; \out\ : in STD_LOGIC; \debounce_gt_rst_r_reg[0]_0\ : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 0 to 0 ); \debounce_gt_rst_r_reg[0]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_SUPPORT_RESET_LOGIC; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_SUPPORT_RESET_LOGIC is signal SYSTEM_RESET0_n_0 : STD_LOGIC; signal debounce_gt_rst_r : STD_LOGIC_VECTOR ( 0 to 3 ); attribute async_reg : string; attribute async_reg of debounce_gt_rst_r : signal is "true"; attribute shift_extract : string; attribute shift_extract of debounce_gt_rst_r : signal is "{no}"; signal \dly_gt_rst_r_reg[17]_srl18_n_0\ : STD_LOGIC; signal gt_rst_r : STD_LOGIC; signal gt_rst_r0_n_0 : STD_LOGIC; signal reset_debounce_r : STD_LOGIC_VECTOR ( 0 to 3 ); signal u_rst_sync_gt_n_0 : STD_LOGIC; signal \NLW_dly_gt_rst_r_reg[17]_srl18_Q31_UNCONNECTED\ : STD_LOGIC; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of \debounce_gt_rst_r_reg[0]\ : label is std.standard.true; attribute KEEP : string; attribute KEEP of \debounce_gt_rst_r_reg[0]\ : label is "yes"; attribute shift_extract of \debounce_gt_rst_r_reg[0]\ : label is "{no}"; attribute ASYNC_REG_boolean of \debounce_gt_rst_r_reg[1]\ : label is std.standard.true; attribute KEEP of \debounce_gt_rst_r_reg[1]\ : label is "yes"; attribute shift_extract of \debounce_gt_rst_r_reg[1]\ : label is "{no}"; attribute ASYNC_REG_boolean of \debounce_gt_rst_r_reg[2]\ : label is std.standard.true; attribute KEEP of \debounce_gt_rst_r_reg[2]\ : label is "yes"; attribute shift_extract of \debounce_gt_rst_r_reg[2]\ : label is "{no}"; attribute ASYNC_REG_boolean of \debounce_gt_rst_r_reg[3]\ : label is std.standard.true; attribute KEEP of \debounce_gt_rst_r_reg[3]\ : label is "yes"; attribute shift_extract of \debounce_gt_rst_r_reg[3]\ : label is "{no}"; attribute srl_bus_name : string; attribute srl_bus_name of \dly_gt_rst_r_reg[17]_srl18\ : label is "inst/\support_reset_logic_i/dly_gt_rst_r_reg "; attribute srl_name : string; attribute srl_name of \dly_gt_rst_r_reg[17]_srl18\ : label is "inst/\support_reset_logic_i/dly_gt_rst_r_reg[17]_srl18 "; begin SYSTEM_RESET0: unisim.vcomponents.LUT4 generic map( INIT => X"8000" ) port map ( I0 => reset_debounce_r(2), I1 => reset_debounce_r(3), I2 => reset_debounce_r(0), I3 => reset_debounce_r(1), O => SYSTEM_RESET0_n_0 ); SYSTEM_RESET_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => SYSTEM_RESET0_n_0, Q => sysreset_from_support, R => '0' ); \debounce_gt_rst_r_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \debounce_gt_rst_r_reg[0]_0\, CE => '1', D => \debounce_gt_rst_r_reg[0]_1\(0), Q => debounce_gt_rst_r(0), R => '0' ); \debounce_gt_rst_r_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \debounce_gt_rst_r_reg[0]_0\, CE => '1', D => debounce_gt_rst_r(0), Q => debounce_gt_rst_r(1), R => '0' ); \debounce_gt_rst_r_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \debounce_gt_rst_r_reg[0]_0\, CE => '1', D => debounce_gt_rst_r(1), Q => debounce_gt_rst_r(2), R => '0' ); \debounce_gt_rst_r_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \debounce_gt_rst_r_reg[0]_0\, CE => '1', D => debounce_gt_rst_r(2), Q => debounce_gt_rst_r(3), R => '0' ); \dly_gt_rst_r_reg[17]_srl18\: unisim.vcomponents.SRLC32E generic map( INIT => X"00000000" ) port map ( A(4 downto 0) => B"10001", CE => '1', CLK => \debounce_gt_rst_r_reg[0]_0\, D => gt_rst_r, Q => \dly_gt_rst_r_reg[17]_srl18_n_0\, Q31 => \NLW_dly_gt_rst_r_reg[17]_srl18_Q31_UNCONNECTED\ ); \dly_gt_rst_r_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \debounce_gt_rst_r_reg[0]_0\, CE => '1', D => \dly_gt_rst_r_reg[17]_srl18_n_0\, Q => gt_reset_out, R => '0' ); gt_rst_r0: unisim.vcomponents.LUT4 generic map( INIT => X"8000" ) port map ( I0 => debounce_gt_rst_r(2), I1 => debounce_gt_rst_r(3), I2 => debounce_gt_rst_r(0), I3 => debounce_gt_rst_r(1), O => gt_rst_r0_n_0 ); gt_rst_r_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \debounce_gt_rst_r_reg[0]_0\, CE => '1', D => gt_rst_r0_n_0, Q => gt_rst_r, R => '0' ); \reset_debounce_r_reg[0]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => D(0), Q => reset_debounce_r(0), S => u_rst_sync_gt_n_0 ); \reset_debounce_r_reg[1]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => reset_debounce_r(0), Q => reset_debounce_r(1), S => u_rst_sync_gt_n_0 ); \reset_debounce_r_reg[2]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => reset_debounce_r(1), Q => reset_debounce_r(2), S => u_rst_sync_gt_n_0 ); \reset_debounce_r_reg[3]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => reset_debounce_r(2), Q => reset_debounce_r(3), S => u_rst_sync_gt_n_0 ); u_rst_sync_gt: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_1 port map ( SS(0) => u_rst_sync_gt_n_0, in0 => gt_rst_r, \out\ => \out\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_SYM_GEN is port ( stg5_reg : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 1 downto 0 ); tempData : out STD_LOGIC_VECTOR ( 5 downto 0 ); \TX_DATA_reg[63]_0\ : out STD_LOGIC_VECTOR ( 57 downto 0 ); stg1_aurora_64b66b_0_cdc_to_reg : in STD_LOGIC; \out\ : in STD_LOGIC; txdatavalid_symgen_i : in STD_LOGIC; gen_na_idles_i : in STD_LOGIC; tx_pe_data_v_i : in STD_LOGIC; TX_HEADER_1_reg_0 : in STD_LOGIC; channel_up_tx_if : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 59 downto 0 ); scrambler : in STD_LOGIC_VECTOR ( 11 downto 0 ); \TX_DATA_reg[59]_0\ : in STD_LOGIC; \TX_DATA_reg[55]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \TX_DATA_reg[63]_1\ : in STD_LOGIC; gen_ch_bond_i : in STD_LOGIC; gen_cc_i : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_SYM_GEN; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_SYM_GEN is signal \^d\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \TX_DATA[62]_i_1_n_0\ : STD_LOGIC; signal \^tx_data_reg[63]_0\ : STD_LOGIC_VECTOR ( 57 downto 0 ); signal \^stg5_reg\ : STD_LOGIC; signal tx_data_i : STD_LOGIC_VECTOR ( 58 to 63 ); signal u_pma_init_data_sync_n_1 : STD_LOGIC; signal u_pma_init_data_sync_n_2 : STD_LOGIC; signal u_pma_init_data_sync_n_3 : STD_LOGIC; signal u_pma_init_data_sync_n_4 : STD_LOGIC; signal u_pma_init_data_sync_n_5 : STD_LOGIC; signal u_pma_init_data_sync_n_6 : STD_LOGIC; begin D(1 downto 0) <= \^d\(1 downto 0); \TX_DATA_reg[63]_0\(57 downto 0) <= \^tx_data_reg[63]_0\(57 downto 0); stg5_reg <= \^stg5_reg\; \TX_DATA[62]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"5555545500000000" ) port map ( I0 => \^stg5_reg\, I1 => gen_ch_bond_i, I2 => gen_cc_i, I3 => tx_pe_data_v_i, I4 => gen_na_idles_i, I5 => \TX_DATA_reg[59]_0\, O => \TX_DATA[62]_i_1_n_0\ ); \TX_DATA_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(52), Q => tx_data_i(63), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(46), Q => \^tx_data_reg[63]_0\(4), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(47), Q => \^tx_data_reg[63]_0\(5), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(48), Q => \^tx_data_reg[63]_0\(6), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(49), Q => \^tx_data_reg[63]_0\(7), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(50), Q => \^tx_data_reg[63]_0\(8), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(51), Q => \^tx_data_reg[63]_0\(9), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(36), Q => \^tx_data_reg[63]_0\(10), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(37), Q => \^tx_data_reg[63]_0\(11), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(38), Q => \^tx_data_reg[63]_0\(12), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(39), Q => \^tx_data_reg[63]_0\(13), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(53), Q => tx_data_i(62), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(40), Q => \^tx_data_reg[63]_0\(14), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(41), Q => \^tx_data_reg[63]_0\(15), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(42), Q => \^tx_data_reg[63]_0\(16), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(43), Q => \^tx_data_reg[63]_0\(17), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(28), Q => \^tx_data_reg[63]_0\(18), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(29), Q => \^tx_data_reg[63]_0\(19), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(30), Q => \^tx_data_reg[63]_0\(20), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(31), Q => \^tx_data_reg[63]_0\(21), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(32), Q => \^tx_data_reg[63]_0\(22), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(33), Q => \^tx_data_reg[63]_0\(23), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(54), Q => tx_data_i(61), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(34), Q => \^tx_data_reg[63]_0\(24), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(35), Q => \^tx_data_reg[63]_0\(25), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[32]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(20), Q => \^tx_data_reg[63]_0\(26), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[33]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(21), Q => \^tx_data_reg[63]_0\(27), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[34]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(22), Q => \^tx_data_reg[63]_0\(28), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[35]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(23), Q => \^tx_data_reg[63]_0\(29), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[36]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(24), Q => \^tx_data_reg[63]_0\(30), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[37]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(25), Q => \^tx_data_reg[63]_0\(31), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[38]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(26), Q => \^tx_data_reg[63]_0\(32), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[39]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(27), Q => \^tx_data_reg[63]_0\(33), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(55), Q => tx_data_i(60), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[40]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(12), Q => \^tx_data_reg[63]_0\(34), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[41]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(13), Q => \^tx_data_reg[63]_0\(35), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[42]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(14), Q => \^tx_data_reg[63]_0\(36), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[43]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(15), Q => \^tx_data_reg[63]_0\(37), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[44]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(16), Q => \^tx_data_reg[63]_0\(38), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[45]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(17), Q => \^tx_data_reg[63]_0\(39), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[46]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(18), Q => \^tx_data_reg[63]_0\(40), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[47]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(19), Q => \^tx_data_reg[63]_0\(41), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[48]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(8), Q => \^tx_data_reg[63]_0\(42), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[49]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(9), Q => \^tx_data_reg[63]_0\(43), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(56), Q => tx_data_i(59), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[50]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(10), Q => \^tx_data_reg[63]_0\(44), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[51]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(11), Q => \^tx_data_reg[63]_0\(45), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[52]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => \TX_DATA_reg[55]_0\(0), Q => \^tx_data_reg[63]_0\(46), R => '0' ); \TX_DATA_reg[53]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => \TX_DATA_reg[55]_0\(1), Q => \^tx_data_reg[63]_0\(47), R => '0' ); \TX_DATA_reg[54]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => \TX_DATA_reg[55]_0\(2), Q => \^tx_data_reg[63]_0\(48), R => '0' ); \TX_DATA_reg[55]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => \TX_DATA_reg[55]_0\(3), Q => \^tx_data_reg[63]_0\(49), R => '0' ); \TX_DATA_reg[56]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(0), Q => \^tx_data_reg[63]_0\(50), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[57]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(1), Q => \^tx_data_reg[63]_0\(51), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[58]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(2), Q => \^tx_data_reg[63]_0\(52), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[59]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => u_pma_init_data_sync_n_3, Q => \^tx_data_reg[63]_0\(53), S => \TX_DATA[62]_i_1_n_0\ ); \TX_DATA_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(57), Q => tx_data_i(58), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[60]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => u_pma_init_data_sync_n_4, Q => \^tx_data_reg[63]_0\(54), S => \TX_DATA[62]_i_1_n_0\ ); \TX_DATA_reg[61]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => u_pma_init_data_sync_n_5, Q => \^tx_data_reg[63]_0\(55), S => \TX_DATA[62]_i_1_n_0\ ); \TX_DATA_reg[62]\: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => u_pma_init_data_sync_n_6, Q => \^tx_data_reg[63]_0\(56), S => \TX_DATA[62]_i_1_n_0\ ); \TX_DATA_reg[63]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(7), Q => \^tx_data_reg[63]_0\(57), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(58), Q => \^tx_data_reg[63]_0\(0), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(59), Q => \^tx_data_reg[63]_0\(1), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(44), Q => \^tx_data_reg[63]_0\(2), R => \TX_DATA_reg[63]_1\ ); \TX_DATA_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => \TX_DATA_reg[59]_0\, D => Q(45), Q => \^tx_data_reg[63]_0\(3), R => \TX_DATA_reg[63]_1\ ); TX_HEADER_0_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => u_pma_init_data_sync_n_2, Q => \^d\(0), R => '0' ); TX_HEADER_1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => u_pma_init_data_sync_n_1, Q => \^d\(1), R => '0' ); \scrambler[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \^tx_data_reg[63]_0\(33), I1 => scrambler(0), I2 => tx_data_i(63), I3 => \^tx_data_reg[63]_0\(52), I4 => scrambler(6), O => tempData(0) ); \scrambler[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \^tx_data_reg[63]_0\(34), I1 => scrambler(1), I2 => tx_data_i(62), I3 => \^tx_data_reg[63]_0\(53), I4 => scrambler(7), O => tempData(1) ); \scrambler[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \^tx_data_reg[63]_0\(35), I1 => scrambler(2), I2 => tx_data_i(61), I3 => \^tx_data_reg[63]_0\(54), I4 => scrambler(8), O => tempData(2) ); \scrambler[3]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \^tx_data_reg[63]_0\(36), I1 => scrambler(3), I2 => tx_data_i(60), I3 => \^tx_data_reg[63]_0\(55), I4 => scrambler(9), O => tempData(3) ); \scrambler[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \^tx_data_reg[63]_0\(37), I1 => scrambler(4), I2 => tx_data_i(59), I3 => \^tx_data_reg[63]_0\(56), I4 => scrambler(10), O => tempData(4) ); \scrambler[5]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"96696996" ) port map ( I0 => \^tx_data_reg[63]_0\(38), I1 => scrambler(5), I2 => tx_data_i(58), I3 => \^tx_data_reg[63]_0\(57), I4 => scrambler(11), O => tempData(5) ); u_pma_init_data_sync: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_5 port map ( D(1 downto 0) => \^d\(1 downto 0), Q(3 downto 0) => Q(6 downto 3), TX_HEADER_1_reg => u_pma_init_data_sync_n_1, TX_HEADER_1_reg_0 => TX_HEADER_1_reg_0, channel_up_tx_if => channel_up_tx_if, gen_na_idles_i => gen_na_idles_i, \out\ => \out\, stg1_aurora_64b66b_0_cdc_to_reg_0 => stg1_aurora_64b66b_0_cdc_to_reg, stg5_reg_0 => \^stg5_reg\, stg5_reg_1 => u_pma_init_data_sync_n_2, stg5_reg_2 => u_pma_init_data_sync_n_3, stg5_reg_3 => u_pma_init_data_sync_n_4, stg5_reg_4 => u_pma_init_data_sync_n_5, stg5_reg_5 => u_pma_init_data_sync_n_6, tx_pe_data_v_i => tx_pe_data_v_i, txdatavalid_symgen_i => txdatavalid_symgen_i ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_TX_STARTUP_FSM is port ( tx_fsm_resetdone_i : out STD_LOGIC; stg5_reg : out STD_LOGIC; gttxreset_t : out STD_LOGIC; mmcm_reset_i : out STD_LOGIC; gt_cpllreset_i : out STD_LOGIC; txuserrdy_t : out STD_LOGIC; CPLL_RESET_reg_0 : out STD_LOGIC; MMCM_RESET_reg_0 : out STD_LOGIC; \out\ : in STD_LOGIC; stg1_aurora_64b66b_0_cdc_to_reg : in STD_LOGIC; in0 : in STD_LOGIC; stg5_reg_0 : in STD_LOGIC; stg4_reg : in STD_LOGIC; \init_wait_count_reg[7]_0\ : in STD_LOGIC; ack_flag : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_TX_STARTUP_FSM; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_TX_STARTUP_FSM is signal CPLL_RESET_i_1_n_0 : STD_LOGIC; signal GTTXRESET_i_1_n_0 : STD_LOGIC; signal GTTXRESET_i_3_n_0 : STD_LOGIC; signal MMCM_RESET : STD_LOGIC; signal MMCM_RESET_i_1_n_0 : STD_LOGIC; signal TXUSERRDY_i_1_n_0 : STD_LOGIC; signal TXUSERRDY_i_2_n_0 : STD_LOGIC; signal clear : STD_LOGIC; signal \^gt_cpllreset_i\ : STD_LOGIC; signal \^gttxreset_t\ : STD_LOGIC; signal init_wait_count : STD_LOGIC; signal \init_wait_count[0]_i_1_n_0\ : STD_LOGIC; signal \init_wait_count[7]_i_3_n_0\ : STD_LOGIC; signal \init_wait_count[7]_i_4_n_0\ : STD_LOGIC; signal \init_wait_count[7]_i_5_n_0\ : STD_LOGIC; signal \init_wait_count_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal init_wait_done : STD_LOGIC; signal init_wait_done_0 : STD_LOGIC; signal init_wait_done_i_1_n_0 : STD_LOGIC; signal mmcm_lock_r2 : STD_LOGIC; attribute async_reg : string; attribute async_reg of mmcm_lock_r2 : signal is "true"; attribute shift_extract : string; attribute shift_extract of mmcm_lock_r2 : signal is "{no}"; signal mmcm_lock_sync : STD_LOGIC; attribute async_reg of mmcm_lock_sync : signal is "true"; attribute shift_extract of mmcm_lock_sync : signal is "{no}"; signal mmcm_lock_sync1 : STD_LOGIC; attribute async_reg of mmcm_lock_sync1 : signal is "true"; attribute shift_extract of mmcm_lock_sync1 : signal is "{no}"; signal \^mmcm_reset_i\ : STD_LOGIC; signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \p_0_in__2\ : STD_LOGIC_VECTOR ( 7 downto 1 ); signal pll_reset_asserted : STD_LOGIC; signal pll_reset_asserted_i_1_n_0 : STD_LOGIC; signal pll_reset_asserted_i_2_n_0 : STD_LOGIC; signal pll_reset_asserted_i_3_n_0 : STD_LOGIC; signal reset_time_out : STD_LOGIC; signal reset_time_out_i_3_n_0 : STD_LOGIC; signal reset_time_out_i_6_n_0 : STD_LOGIC; signal reset_time_out_i_7_n_0 : STD_LOGIC; signal run_phase_alignment_int_i_1_n_0 : STD_LOGIC; signal run_phase_alignment_int_reg_n_0 : STD_LOGIC; signal sel : STD_LOGIC; signal time_out_2ms : STD_LOGIC; signal time_out_2ms_1 : STD_LOGIC; signal time_out_2ms_i_1_n_0 : STD_LOGIC; signal time_out_500us : STD_LOGIC; signal time_out_500us_i_1_n_0 : STD_LOGIC; signal time_out_500us_i_2_n_0 : STD_LOGIC; signal time_out_500us_i_3_n_0 : STD_LOGIC; signal time_out_500us_i_4_n_0 : STD_LOGIC; signal time_out_500us_i_5_n_0 : STD_LOGIC; signal time_out_500us_i_6_n_0 : STD_LOGIC; signal time_out_counter : STD_LOGIC; signal \time_out_counter[0]_i_4_n_0\ : STD_LOGIC; signal \time_out_counter[0]_i_5__0_n_0\ : STD_LOGIC; signal \time_out_counter[0]_i_6__0_n_0\ : STD_LOGIC; signal \time_out_counter[0]_i_7_n_0\ : STD_LOGIC; signal \time_out_counter[0]_i_8_n_0\ : STD_LOGIC; signal time_out_counter_reg : STD_LOGIC_VECTOR ( 18 downto 0 ); signal \time_out_counter_reg[0]_i_2_n_0\ : STD_LOGIC; signal \time_out_counter_reg[0]_i_2_n_1\ : STD_LOGIC; signal \time_out_counter_reg[0]_i_2_n_2\ : STD_LOGIC; signal \time_out_counter_reg[0]_i_2_n_3\ : STD_LOGIC; signal \time_out_counter_reg[0]_i_2_n_4\ : STD_LOGIC; signal \time_out_counter_reg[0]_i_2_n_5\ : STD_LOGIC; signal \time_out_counter_reg[0]_i_2_n_6\ : STD_LOGIC; signal \time_out_counter_reg[0]_i_2_n_7\ : STD_LOGIC; signal \time_out_counter_reg[12]_i_1_n_0\ : STD_LOGIC; signal \time_out_counter_reg[12]_i_1_n_1\ : STD_LOGIC; signal \time_out_counter_reg[12]_i_1_n_2\ : STD_LOGIC; signal \time_out_counter_reg[12]_i_1_n_3\ : STD_LOGIC; signal \time_out_counter_reg[12]_i_1_n_4\ : STD_LOGIC; signal \time_out_counter_reg[12]_i_1_n_5\ : STD_LOGIC; signal \time_out_counter_reg[12]_i_1_n_6\ : STD_LOGIC; signal \time_out_counter_reg[12]_i_1_n_7\ : STD_LOGIC; signal \time_out_counter_reg[16]_i_1_n_2\ : STD_LOGIC; signal \time_out_counter_reg[16]_i_1_n_3\ : STD_LOGIC; signal \time_out_counter_reg[16]_i_1_n_5\ : STD_LOGIC; signal \time_out_counter_reg[16]_i_1_n_6\ : STD_LOGIC; signal \time_out_counter_reg[16]_i_1_n_7\ : STD_LOGIC; signal \time_out_counter_reg[4]_i_1_n_0\ : STD_LOGIC; signal \time_out_counter_reg[4]_i_1_n_1\ : STD_LOGIC; signal \time_out_counter_reg[4]_i_1_n_2\ : STD_LOGIC; signal \time_out_counter_reg[4]_i_1_n_3\ : STD_LOGIC; signal \time_out_counter_reg[4]_i_1_n_4\ : STD_LOGIC; signal \time_out_counter_reg[4]_i_1_n_5\ : STD_LOGIC; signal \time_out_counter_reg[4]_i_1_n_6\ : STD_LOGIC; signal \time_out_counter_reg[4]_i_1_n_7\ : STD_LOGIC; signal \time_out_counter_reg[8]_i_1_n_0\ : STD_LOGIC; signal \time_out_counter_reg[8]_i_1_n_1\ : STD_LOGIC; signal \time_out_counter_reg[8]_i_1_n_2\ : STD_LOGIC; signal \time_out_counter_reg[8]_i_1_n_3\ : STD_LOGIC; signal \time_out_counter_reg[8]_i_1_n_4\ : STD_LOGIC; signal \time_out_counter_reg[8]_i_1_n_5\ : STD_LOGIC; signal \time_out_counter_reg[8]_i_1_n_6\ : STD_LOGIC; signal \time_out_counter_reg[8]_i_1_n_7\ : STD_LOGIC; signal time_out_wait_bypass_reg_n_0 : STD_LOGIC; signal \time_tlock_max_i_1__0_n_0\ : STD_LOGIC; signal \time_tlock_max_i_2__0_n_0\ : STD_LOGIC; signal \time_tlock_max_i_3__0_n_0\ : STD_LOGIC; signal \time_tlock_max_i_4__0_n_0\ : STD_LOGIC; signal time_tlock_max_reg_n_0 : STD_LOGIC; signal tx_fsm_reset_done_int : STD_LOGIC; attribute RTL_KEEP : string; attribute RTL_KEEP of tx_fsm_reset_done_int : signal is "true"; signal tx_fsm_reset_done_int_i_1_n_0 : STD_LOGIC; signal tx_fsm_reset_done_int_i_2_n_0 : STD_LOGIC; signal tx_seq_scramb_reset_int : STD_LOGIC; attribute RTL_KEEP of tx_seq_scramb_reset_int : signal is "true"; signal \tx_seq_scramb_reset_int__0\ : STD_LOGIC; signal tx_seq_scramb_reset_int_i_1_n_0 : STD_LOGIC; signal tx_seq_scramb_reset_int_i_3_n_0 : STD_LOGIC; signal tx_state : STD_LOGIC_VECTOR ( 7 downto 0 ); attribute RTL_KEEP of tx_state : signal is "true"; signal \tx_state[0]_i_3_n_0\ : STD_LOGIC; signal \tx_state[1]_i_5_n_0\ : STD_LOGIC; signal \tx_state[1]_i_6_n_0\ : STD_LOGIC; signal \tx_state[2]_i_2_n_0\ : STD_LOGIC; signal \tx_state[2]_i_5_n_0\ : STD_LOGIC; signal \tx_state[2]_i_6_n_0\ : STD_LOGIC; signal \tx_state[2]_i_7_n_0\ : STD_LOGIC; signal \tx_state[5]_i_2_n_0\ : STD_LOGIC; signal \tx_state[5]_i_6_n_0\ : STD_LOGIC; signal \tx_state[7]_i_1_n_0\ : STD_LOGIC; signal \tx_state[7]_i_3_n_0\ : STD_LOGIC; signal \tx_state[7]_i_4_n_0\ : STD_LOGIC; signal \tx_state[7]_i_5_n_0\ : STD_LOGIC; signal \tx_state[7]_i_6_n_0\ : STD_LOGIC; signal \tx_state[7]_i_7_n_0\ : STD_LOGIC; signal \tx_state[7]_i_8_n_0\ : STD_LOGIC; signal \tx_state[7]_i_9_n_0\ : STD_LOGIC; signal \^txuserrdy_t\ : STD_LOGIC; signal u_rst_sync_plllock_n_0 : STD_LOGIC; signal u_rst_sync_plllock_n_1 : STD_LOGIC; signal u_rst_sync_plllock_n_3 : STD_LOGIC; signal u_rst_sync_plllock_n_4 : STD_LOGIC; signal u_rst_sync_plllock_n_5 : STD_LOGIC; signal u_rst_sync_run_phase_align_n_0 : STD_LOGIC; signal u_rst_sync_time_out_wait_bypass_n_6 : STD_LOGIC; signal u_rst_sync_time_out_wait_bypass_n_7 : STD_LOGIC; signal u_rst_sync_tx_fsm_rst_done_n_0 : STD_LOGIC; signal u_rst_sync_tx_fsm_rst_done_n_1 : STD_LOGIC; signal u_rst_sync_txresetdone_n_0 : STD_LOGIC; signal u_rst_sync_txresetdone_n_1 : STD_LOGIC; signal u_rst_sync_txresetdone_n_3 : STD_LOGIC; signal u_rst_sync_txresetdone_n_4 : STD_LOGIC; signal u_rst_sync_txresetdone_n_5 : STD_LOGIC; signal u_rst_sync_txresetdone_n_6 : STD_LOGIC; signal \wait_bypass_count[0]_i_4_n_0\ : STD_LOGIC; signal \wait_bypass_count[0]_i_5_n_0\ : STD_LOGIC; signal \wait_bypass_count[0]_i_6_n_0\ : STD_LOGIC; signal \wait_bypass_count[0]_i_7_n_0\ : STD_LOGIC; signal \wait_bypass_count[0]_i_8_n_0\ : STD_LOGIC; signal \wait_bypass_count[0]_i_9_n_0\ : STD_LOGIC; signal wait_bypass_count_reg : STD_LOGIC_VECTOR ( 16 downto 0 ); signal \wait_bypass_count_reg[0]_i_3_n_0\ : STD_LOGIC; signal \wait_bypass_count_reg[0]_i_3_n_1\ : STD_LOGIC; signal \wait_bypass_count_reg[0]_i_3_n_2\ : STD_LOGIC; signal \wait_bypass_count_reg[0]_i_3_n_3\ : STD_LOGIC; signal \wait_bypass_count_reg[0]_i_3_n_4\ : STD_LOGIC; signal \wait_bypass_count_reg[0]_i_3_n_5\ : STD_LOGIC; signal \wait_bypass_count_reg[0]_i_3_n_6\ : STD_LOGIC; signal \wait_bypass_count_reg[0]_i_3_n_7\ : STD_LOGIC; signal \wait_bypass_count_reg[12]_i_1_n_0\ : STD_LOGIC; signal \wait_bypass_count_reg[12]_i_1_n_1\ : STD_LOGIC; signal \wait_bypass_count_reg[12]_i_1_n_2\ : STD_LOGIC; signal \wait_bypass_count_reg[12]_i_1_n_3\ : STD_LOGIC; signal \wait_bypass_count_reg[12]_i_1_n_4\ : STD_LOGIC; signal \wait_bypass_count_reg[12]_i_1_n_5\ : STD_LOGIC; signal \wait_bypass_count_reg[12]_i_1_n_6\ : STD_LOGIC; signal \wait_bypass_count_reg[12]_i_1_n_7\ : STD_LOGIC; signal \wait_bypass_count_reg[16]_i_1_n_7\ : STD_LOGIC; signal \wait_bypass_count_reg[4]_i_1_n_0\ : STD_LOGIC; signal \wait_bypass_count_reg[4]_i_1_n_1\ : STD_LOGIC; signal \wait_bypass_count_reg[4]_i_1_n_2\ : STD_LOGIC; signal \wait_bypass_count_reg[4]_i_1_n_3\ : STD_LOGIC; signal \wait_bypass_count_reg[4]_i_1_n_4\ : STD_LOGIC; signal \wait_bypass_count_reg[4]_i_1_n_5\ : STD_LOGIC; signal \wait_bypass_count_reg[4]_i_1_n_6\ : STD_LOGIC; signal \wait_bypass_count_reg[4]_i_1_n_7\ : STD_LOGIC; signal \wait_bypass_count_reg[8]_i_1_n_0\ : STD_LOGIC; signal \wait_bypass_count_reg[8]_i_1_n_1\ : STD_LOGIC; signal \wait_bypass_count_reg[8]_i_1_n_2\ : STD_LOGIC; signal \wait_bypass_count_reg[8]_i_1_n_3\ : STD_LOGIC; signal \wait_bypass_count_reg[8]_i_1_n_4\ : STD_LOGIC; signal \wait_bypass_count_reg[8]_i_1_n_5\ : STD_LOGIC; signal \wait_bypass_count_reg[8]_i_1_n_6\ : STD_LOGIC; signal \wait_bypass_count_reg[8]_i_1_n_7\ : STD_LOGIC; signal \wait_time_cnt[0]_i_10_n_0\ : STD_LOGIC; signal \wait_time_cnt[0]_i_11_n_0\ : STD_LOGIC; signal \wait_time_cnt[0]_i_12_n_0\ : STD_LOGIC; signal \wait_time_cnt[0]_i_1_n_0\ : STD_LOGIC; signal \wait_time_cnt[0]_i_4_n_0\ : STD_LOGIC; signal \wait_time_cnt[0]_i_5_n_0\ : STD_LOGIC; signal \wait_time_cnt[0]_i_6_n_0\ : STD_LOGIC; signal \wait_time_cnt[0]_i_7_n_0\ : STD_LOGIC; signal \wait_time_cnt[0]_i_8_n_0\ : STD_LOGIC; signal \wait_time_cnt[0]_i_9_n_0\ : STD_LOGIC; signal \wait_time_cnt[12]_i_2_n_0\ : STD_LOGIC; signal \wait_time_cnt[12]_i_3_n_0\ : STD_LOGIC; signal \wait_time_cnt[12]_i_4_n_0\ : STD_LOGIC; signal \wait_time_cnt[12]_i_5_n_0\ : STD_LOGIC; signal \wait_time_cnt[4]_i_2_n_0\ : STD_LOGIC; signal \wait_time_cnt[4]_i_3_n_0\ : STD_LOGIC; signal \wait_time_cnt[4]_i_4_n_0\ : STD_LOGIC; signal \wait_time_cnt[4]_i_5_n_0\ : STD_LOGIC; signal \wait_time_cnt[8]_i_2_n_0\ : STD_LOGIC; signal \wait_time_cnt[8]_i_3_n_0\ : STD_LOGIC; signal \wait_time_cnt[8]_i_4_n_0\ : STD_LOGIC; signal \wait_time_cnt[8]_i_5_n_0\ : STD_LOGIC; signal wait_time_cnt_reg : STD_LOGIC_VECTOR ( 15 downto 0 ); signal \wait_time_cnt_reg[0]_i_3_n_0\ : STD_LOGIC; signal \wait_time_cnt_reg[0]_i_3_n_1\ : STD_LOGIC; signal \wait_time_cnt_reg[0]_i_3_n_2\ : STD_LOGIC; signal \wait_time_cnt_reg[0]_i_3_n_3\ : STD_LOGIC; signal \wait_time_cnt_reg[0]_i_3_n_4\ : STD_LOGIC; signal \wait_time_cnt_reg[0]_i_3_n_5\ : STD_LOGIC; signal \wait_time_cnt_reg[0]_i_3_n_6\ : STD_LOGIC; signal \wait_time_cnt_reg[0]_i_3_n_7\ : STD_LOGIC; signal \wait_time_cnt_reg[12]_i_1_n_1\ : STD_LOGIC; signal \wait_time_cnt_reg[12]_i_1_n_2\ : STD_LOGIC; signal \wait_time_cnt_reg[12]_i_1_n_3\ : STD_LOGIC; signal \wait_time_cnt_reg[12]_i_1_n_4\ : STD_LOGIC; signal \wait_time_cnt_reg[12]_i_1_n_5\ : STD_LOGIC; signal \wait_time_cnt_reg[12]_i_1_n_6\ : STD_LOGIC; signal \wait_time_cnt_reg[12]_i_1_n_7\ : STD_LOGIC; signal \wait_time_cnt_reg[4]_i_1_n_0\ : STD_LOGIC; signal \wait_time_cnt_reg[4]_i_1_n_1\ : STD_LOGIC; signal \wait_time_cnt_reg[4]_i_1_n_2\ : STD_LOGIC; signal \wait_time_cnt_reg[4]_i_1_n_3\ : STD_LOGIC; signal \wait_time_cnt_reg[4]_i_1_n_4\ : STD_LOGIC; signal \wait_time_cnt_reg[4]_i_1_n_5\ : STD_LOGIC; signal \wait_time_cnt_reg[4]_i_1_n_6\ : STD_LOGIC; signal \wait_time_cnt_reg[4]_i_1_n_7\ : STD_LOGIC; signal \wait_time_cnt_reg[8]_i_1_n_0\ : STD_LOGIC; signal \wait_time_cnt_reg[8]_i_1_n_1\ : STD_LOGIC; signal \wait_time_cnt_reg[8]_i_1_n_2\ : STD_LOGIC; signal \wait_time_cnt_reg[8]_i_1_n_3\ : STD_LOGIC; signal \wait_time_cnt_reg[8]_i_1_n_4\ : STD_LOGIC; signal \wait_time_cnt_reg[8]_i_1_n_5\ : STD_LOGIC; signal \wait_time_cnt_reg[8]_i_1_n_6\ : STD_LOGIC; signal \wait_time_cnt_reg[8]_i_1_n_7\ : STD_LOGIC; signal \NLW_time_out_counter_reg[16]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_time_out_counter_reg[16]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); signal \NLW_wait_bypass_count_reg[16]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_wait_bypass_count_reg[16]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_wait_time_cnt_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \init_wait_count[1]_i_1\ : label is "soft_lutpair69"; attribute SOFT_HLUTNM of \init_wait_count[2]_i_1\ : label is "soft_lutpair68"; attribute SOFT_HLUTNM of \init_wait_count[3]_i_1\ : label is "soft_lutpair68"; attribute SOFT_HLUTNM of \init_wait_count[4]_i_1\ : label is "soft_lutpair64"; attribute SOFT_HLUTNM of \init_wait_count[6]_i_1\ : label is "soft_lutpair65"; attribute SOFT_HLUTNM of \init_wait_count[7]_i_2\ : label is "soft_lutpair65"; attribute SOFT_HLUTNM of \init_wait_count[7]_i_3\ : label is "soft_lutpair69"; attribute SOFT_HLUTNM of \init_wait_count[7]_i_5\ : label is "soft_lutpair64"; attribute ASYNC_REG_boolean : boolean; attribute ASYNC_REG_boolean of mmcm_lock_r2_reg : label is std.standard.true; attribute KEEP : string; attribute KEEP of mmcm_lock_r2_reg : label is "yes"; attribute shift_extract of mmcm_lock_r2_reg : label is "{no}"; attribute ASYNC_REG_boolean of mmcm_lock_sync1_reg : label is std.standard.true; attribute KEEP of mmcm_lock_sync1_reg : label is "yes"; attribute shift_extract of mmcm_lock_sync1_reg : label is "{no}"; attribute ASYNC_REG_boolean of mmcm_lock_sync_reg : label is std.standard.true; attribute KEEP of mmcm_lock_sync_reg : label is "yes"; attribute shift_extract of mmcm_lock_sync_reg : label is "{no}"; attribute SOFT_HLUTNM of time_out_500us_i_5 : label is "soft_lutpair67"; attribute SOFT_HLUTNM of time_out_500us_i_6 : label is "soft_lutpair66"; attribute SOFT_HLUTNM of \time_out_counter[0]_i_7\ : label is "soft_lutpair67"; attribute SOFT_HLUTNM of \time_tlock_max_i_2__0\ : label is "soft_lutpair66"; attribute KEEP of tx_fsm_reset_done_int_reg : label is "yes"; attribute KEEP of tx_seq_scramb_reset_int_reg : label is "yes"; attribute FSM_ENCODED_STATES : string; attribute FSM_ENCODED_STATES of \tx_state_reg[0]\ : label is "INIT:00000000,ASSERT_ALL_RESETS:00000001,RELEASE_PLL_RESET:00000010,DELAY4_RELEASE_MMCM_RESET:01000000,RELEASE_MMCM_RESET:00000100,DELAY4_WAIT_RESET_DONE:10000000,WAIT_RESET_DONE:00001000,DO_PHASE_ALIGNMENT:00010000,RESET_FSM_DONE:00100000"; attribute KEEP of \tx_state_reg[0]\ : label is "yes"; attribute FSM_ENCODED_STATES of \tx_state_reg[1]\ : label is "INIT:00000000,ASSERT_ALL_RESETS:00000001,RELEASE_PLL_RESET:00000010,DELAY4_RELEASE_MMCM_RESET:01000000,RELEASE_MMCM_RESET:00000100,DELAY4_WAIT_RESET_DONE:10000000,WAIT_RESET_DONE:00001000,DO_PHASE_ALIGNMENT:00010000,RESET_FSM_DONE:00100000"; attribute KEEP of \tx_state_reg[1]\ : label is "yes"; attribute FSM_ENCODED_STATES of \tx_state_reg[2]\ : label is "INIT:00000000,ASSERT_ALL_RESETS:00000001,RELEASE_PLL_RESET:00000010,DELAY4_RELEASE_MMCM_RESET:01000000,RELEASE_MMCM_RESET:00000100,DELAY4_WAIT_RESET_DONE:10000000,WAIT_RESET_DONE:00001000,DO_PHASE_ALIGNMENT:00010000,RESET_FSM_DONE:00100000"; attribute KEEP of \tx_state_reg[2]\ : label is "yes"; attribute FSM_ENCODED_STATES of \tx_state_reg[3]\ : label is "INIT:00000000,ASSERT_ALL_RESETS:00000001,RELEASE_PLL_RESET:00000010,DELAY4_RELEASE_MMCM_RESET:01000000,RELEASE_MMCM_RESET:00000100,DELAY4_WAIT_RESET_DONE:10000000,WAIT_RESET_DONE:00001000,DO_PHASE_ALIGNMENT:00010000,RESET_FSM_DONE:00100000"; attribute KEEP of \tx_state_reg[3]\ : label is "yes"; attribute FSM_ENCODED_STATES of \tx_state_reg[4]\ : label is "INIT:00000000,ASSERT_ALL_RESETS:00000001,RELEASE_PLL_RESET:00000010,DELAY4_RELEASE_MMCM_RESET:01000000,RELEASE_MMCM_RESET:00000100,DELAY4_WAIT_RESET_DONE:10000000,WAIT_RESET_DONE:00001000,DO_PHASE_ALIGNMENT:00010000,RESET_FSM_DONE:00100000"; attribute KEEP of \tx_state_reg[4]\ : label is "yes"; attribute FSM_ENCODED_STATES of \tx_state_reg[5]\ : label is "INIT:00000000,ASSERT_ALL_RESETS:00000001,RELEASE_PLL_RESET:00000010,DELAY4_RELEASE_MMCM_RESET:01000000,RELEASE_MMCM_RESET:00000100,DELAY4_WAIT_RESET_DONE:10000000,WAIT_RESET_DONE:00001000,DO_PHASE_ALIGNMENT:00010000,RESET_FSM_DONE:00100000"; attribute KEEP of \tx_state_reg[5]\ : label is "yes"; attribute FSM_ENCODED_STATES of \tx_state_reg[6]\ : label is "INIT:00000000,ASSERT_ALL_RESETS:00000001,RELEASE_PLL_RESET:00000010,DELAY4_RELEASE_MMCM_RESET:01000000,RELEASE_MMCM_RESET:00000100,DELAY4_WAIT_RESET_DONE:10000000,WAIT_RESET_DONE:00001000,DO_PHASE_ALIGNMENT:00010000,RESET_FSM_DONE:00100000"; attribute KEEP of \tx_state_reg[6]\ : label is "yes"; attribute FSM_ENCODED_STATES of \tx_state_reg[7]\ : label is "INIT:00000000,ASSERT_ALL_RESETS:00000001,RELEASE_PLL_RESET:00000010,DELAY4_RELEASE_MMCM_RESET:01000000,RELEASE_MMCM_RESET:00000100,DELAY4_WAIT_RESET_DONE:10000000,WAIT_RESET_DONE:00001000,DO_PHASE_ALIGNMENT:00010000,RESET_FSM_DONE:00100000"; attribute KEEP of \tx_state_reg[7]\ : label is "yes"; begin gt_cpllreset_i <= \^gt_cpllreset_i\; gttxreset_t <= \^gttxreset_t\; mmcm_reset_i <= \^mmcm_reset_i\; tx_fsm_resetdone_i <= tx_fsm_reset_done_int; txuserrdy_t <= \^txuserrdy_t\; CPLL_RESET_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFF7F00000070" ) port map ( I0 => pll_reset_asserted, I1 => tx_state(0), I2 => \tx_state[7]_i_4_n_0\, I3 => \tx_state[7]_i_3_n_0\, I4 => tx_state(4), I5 => \^gt_cpllreset_i\, O => CPLL_RESET_i_1_n_0 ); CPLL_RESET_reg: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => '1', CLR => \init_wait_count_reg[7]_0\, D => CPLL_RESET_i_1_n_0, Q => \^gt_cpllreset_i\ ); GTTXRESET_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"555F0008" ) port map ( I0 => MMCM_RESET, I1 => tx_state(0), I2 => tx_state(6), I3 => tx_state(2), I4 => \^gttxreset_t\, O => GTTXRESET_i_1_n_0 ); GTTXRESET_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000000200020202" ) port map ( I0 => GTTXRESET_i_3_n_0, I1 => tx_state(1), I2 => tx_state(3), I3 => tx_state(6), I4 => tx_state(2), I5 => tx_state(0), O => MMCM_RESET ); GTTXRESET_i_3: unisim.vcomponents.LUT3 generic map( INIT => X"01" ) port map ( I0 => tx_state(4), I1 => tx_state(5), I2 => tx_state(7), O => GTTXRESET_i_3_n_0 ); GTTXRESET_reg: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => '1', CLR => \init_wait_count_reg[7]_0\, D => GTTXRESET_i_1_n_0, Q => \^gttxreset_t\ ); MMCM_RESET_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"BFB0" ) port map ( I0 => tx_state(6), I1 => tx_state(2), I2 => MMCM_RESET, I3 => \^mmcm_reset_i\, O => MMCM_RESET_i_1_n_0 ); MMCM_RESET_reg: unisim.vcomponents.FDCE generic map( INIT => '1' ) port map ( C => stg5_reg_0, CE => '1', CLR => \init_wait_count_reg[7]_0\, D => MMCM_RESET_i_1_n_0, Q => \^mmcm_reset_i\ ); TXUSERRDY_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFA00000002" ) port map ( I0 => tx_state(3), I1 => tx_state(0), I2 => tx_state(7), I3 => tx_state(6), I4 => TXUSERRDY_i_2_n_0, I5 => \^txuserrdy_t\, O => TXUSERRDY_i_1_n_0 ); TXUSERRDY_i_2: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => tx_state(2), I1 => tx_state(1), I2 => tx_state(5), I3 => tx_state(4), O => TXUSERRDY_i_2_n_0 ); TXUSERRDY_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => '1', D => TXUSERRDY_i_1_n_0, PRE => \init_wait_count_reg[7]_0\, Q => \^txuserrdy_t\ ); clk_not_locked_i_inferred_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \^mmcm_reset_i\, I1 => \out\, O => MMCM_RESET_reg_0 ); flag2_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^gt_cpllreset_i\, I1 => ack_flag, O => CPLL_RESET_reg_0 ); \init_wait_count[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \init_wait_count_reg__0\(0), O => \init_wait_count[0]_i_1_n_0\ ); \init_wait_count[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \init_wait_count_reg__0\(1), I1 => \init_wait_count_reg__0\(0), O => \p_0_in__2\(1) ); \init_wait_count[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \init_wait_count_reg__0\(2), I1 => \init_wait_count_reg__0\(1), I2 => \init_wait_count_reg__0\(0), O => \p_0_in__2\(2) ); \init_wait_count[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"6AAA" ) port map ( I0 => \init_wait_count_reg__0\(3), I1 => \init_wait_count_reg__0\(0), I2 => \init_wait_count_reg__0\(1), I3 => \init_wait_count_reg__0\(2), O => \p_0_in__2\(3) ); \init_wait_count[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \init_wait_count_reg__0\(2), I1 => \init_wait_count_reg__0\(1), I2 => \init_wait_count_reg__0\(0), I3 => \init_wait_count_reg__0\(3), I4 => \init_wait_count_reg__0\(4), O => \p_0_in__2\(4) ); \init_wait_count[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"6AAAAAAAAAAAAAAA" ) port map ( I0 => \init_wait_count_reg__0\(5), I1 => \init_wait_count_reg__0\(2), I2 => \init_wait_count_reg__0\(1), I3 => \init_wait_count_reg__0\(0), I4 => \init_wait_count_reg__0\(3), I5 => \init_wait_count_reg__0\(4), O => \p_0_in__2\(5) ); \init_wait_count[6]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"AA6A" ) port map ( I0 => \init_wait_count_reg__0\(6), I1 => \init_wait_count_reg__0\(4), I2 => \init_wait_count_reg__0\(5), I3 => \init_wait_count[7]_i_5_n_0\, O => \p_0_in__2\(6) ); \init_wait_count[7]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFE" ) port map ( I0 => \init_wait_count[7]_i_3_n_0\, I1 => \init_wait_count[7]_i_4_n_0\, I2 => \init_wait_count_reg__0\(7), I3 => \init_wait_count_reg__0\(6), I4 => \init_wait_count_reg__0\(3), I5 => \init_wait_count_reg__0\(2), O => init_wait_count ); \init_wait_count[7]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"9AAAAAAA" ) port map ( I0 => \init_wait_count_reg__0\(7), I1 => \init_wait_count[7]_i_5_n_0\, I2 => \init_wait_count_reg__0\(5), I3 => \init_wait_count_reg__0\(4), I4 => \init_wait_count_reg__0\(6), O => \p_0_in__2\(7) ); \init_wait_count[7]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => \init_wait_count_reg__0\(1), I1 => \init_wait_count_reg__0\(0), O => \init_wait_count[7]_i_3_n_0\ ); \init_wait_count[7]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => \init_wait_count_reg__0\(4), I1 => \init_wait_count_reg__0\(5), O => \init_wait_count[7]_i_4_n_0\ ); \init_wait_count[7]_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"7FFF" ) port map ( I0 => \init_wait_count_reg__0\(2), I1 => \init_wait_count_reg__0\(1), I2 => \init_wait_count_reg__0\(0), I3 => \init_wait_count_reg__0\(3), O => \init_wait_count[7]_i_5_n_0\ ); \init_wait_count_reg[0]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => init_wait_count, CLR => \init_wait_count_reg[7]_0\, D => \init_wait_count[0]_i_1_n_0\, Q => \init_wait_count_reg__0\(0) ); \init_wait_count_reg[1]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => init_wait_count, CLR => \init_wait_count_reg[7]_0\, D => \p_0_in__2\(1), Q => \init_wait_count_reg__0\(1) ); \init_wait_count_reg[2]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => init_wait_count, CLR => \init_wait_count_reg[7]_0\, D => \p_0_in__2\(2), Q => \init_wait_count_reg__0\(2) ); \init_wait_count_reg[3]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => init_wait_count, CLR => \init_wait_count_reg[7]_0\, D => \p_0_in__2\(3), Q => \init_wait_count_reg__0\(3) ); \init_wait_count_reg[4]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => init_wait_count, CLR => \init_wait_count_reg[7]_0\, D => \p_0_in__2\(4), Q => \init_wait_count_reg__0\(4) ); \init_wait_count_reg[5]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => init_wait_count, CLR => \init_wait_count_reg[7]_0\, D => \p_0_in__2\(5), Q => \init_wait_count_reg__0\(5) ); \init_wait_count_reg[6]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => init_wait_count, CLR => \init_wait_count_reg[7]_0\, D => \p_0_in__2\(6), Q => \init_wait_count_reg__0\(6) ); \init_wait_count_reg[7]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => init_wait_count, CLR => \init_wait_count_reg[7]_0\, D => \p_0_in__2\(7), Q => \init_wait_count_reg__0\(7) ); init_wait_done_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => init_wait_done_0, I1 => init_wait_done, O => init_wait_done_i_1_n_0 ); init_wait_done_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000001" ) port map ( I0 => \init_wait_count_reg__0\(2), I1 => \init_wait_count_reg__0\(3), I2 => \init_wait_count_reg__0\(6), I3 => \init_wait_count_reg__0\(7), I4 => \init_wait_count[7]_i_4_n_0\, I5 => \init_wait_count[7]_i_3_n_0\, O => init_wait_done_0 ); init_wait_done_reg: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => '1', CLR => \init_wait_count_reg[7]_0\, D => init_wait_done_i_1_n_0, Q => init_wait_done ); mmcm_lock_r2_reg: unisim.vcomponents.FDRE port map ( C => stg5_reg_0, CE => '1', D => mmcm_lock_sync1, Q => mmcm_lock_r2, R => '0' ); mmcm_lock_sync1_reg: unisim.vcomponents.FDRE port map ( C => stg5_reg_0, CE => '1', D => mmcm_lock_sync, Q => mmcm_lock_sync1, R => '0' ); mmcm_lock_sync_reg: unisim.vcomponents.FDRE port map ( C => stg5_reg_0, CE => '1', D => in0, Q => mmcm_lock_sync, R => '0' ); pll_reset_asserted_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF00001400" ) port map ( I0 => pll_reset_asserted_i_2_n_0, I1 => tx_state(0), I2 => tx_state(1), I3 => pll_reset_asserted_i_3_n_0, I4 => tx_state(5), I5 => pll_reset_asserted, O => pll_reset_asserted_i_1_n_0 ); pll_reset_asserted_i_2: unisim.vcomponents.LUT3 generic map( INIT => X"FE" ) port map ( I0 => tx_state(4), I1 => tx_state(6), I2 => tx_state(7), O => pll_reset_asserted_i_2_n_0 ); pll_reset_asserted_i_3: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => tx_state(3), I1 => tx_state(2), O => pll_reset_asserted_i_3_n_0 ); pll_reset_asserted_reg: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => '1', CLR => \init_wait_count_reg[7]_0\, D => pll_reset_asserted_i_1_n_0, Q => pll_reset_asserted ); reset_time_out_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000117" ) port map ( I0 => tx_state(2), I1 => tx_state(4), I2 => tx_state(5), I3 => tx_state(3), I4 => tx_state(1), I5 => tx_state(0), O => reset_time_out_i_3_n_0 ); reset_time_out_i_6: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => tx_state(4), I1 => tx_state(0), O => reset_time_out_i_6_n_0 ); reset_time_out_i_7: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => tx_state(3), I1 => tx_state(5), O => reset_time_out_i_7_n_0 ); reset_time_out_reg: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => '1', CLR => \init_wait_count_reg[7]_0\, D => u_rst_sync_plllock_n_0, Q => reset_time_out ); run_phase_alignment_int_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFDF00000008" ) port map ( I0 => \tx_state[7]_i_4_n_0\, I1 => tx_state(4), I2 => tx_state(0), I3 => tx_state(7), I4 => tx_state(6), I5 => run_phase_alignment_int_reg_n_0, O => run_phase_alignment_int_i_1_n_0 ); run_phase_alignment_int_reg: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => '1', CLR => \init_wait_count_reg[7]_0\, D => run_phase_alignment_int_i_1_n_0, Q => run_phase_alignment_int_reg_n_0 ); time_out_2ms_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"0E" ) port map ( I0 => time_out_2ms, I1 => time_out_2ms_1, I2 => reset_time_out, O => time_out_2ms_i_1_n_0 ); time_out_2ms_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => '1', D => time_out_2ms_i_1_n_0, Q => time_out_2ms, R => '0' ); time_out_500us_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"00000000AAAAAAAE" ) port map ( I0 => time_out_500us, I1 => time_out_500us_i_2_n_0, I2 => time_out_500us_i_3_n_0, I3 => time_out_500us_i_4_n_0, I4 => time_out_500us_i_5_n_0, I5 => reset_time_out, O => time_out_500us_i_1_n_0 ); time_out_500us_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000000010000000" ) port map ( I0 => time_out_counter_reg(3), I1 => time_out_counter_reg(5), I2 => time_out_counter_reg(15), I3 => time_out_counter_reg(7), I4 => time_out_counter_reg(6), I5 => time_out_500us_i_6_n_0, O => time_out_500us_i_2_n_0 ); time_out_500us_i_3: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => time_out_counter_reg(16), I1 => time_out_counter_reg(0), I2 => time_out_counter_reg(10), I3 => time_out_counter_reg(2), O => time_out_500us_i_3_n_0 ); time_out_500us_i_4: unisim.vcomponents.LUT4 generic map( INIT => X"FFEF" ) port map ( I0 => time_out_counter_reg(4), I1 => time_out_counter_reg(14), I2 => time_out_counter_reg(13), I3 => time_out_counter_reg(8), O => time_out_500us_i_4_n_0 ); time_out_500us_i_5: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => time_out_counter_reg(12), I1 => time_out_counter_reg(11), I2 => time_out_counter_reg(17), I3 => time_out_counter_reg(18), O => time_out_500us_i_5_n_0 ); time_out_500us_i_6: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => time_out_counter_reg(1), I1 => time_out_counter_reg(9), O => time_out_500us_i_6_n_0 ); time_out_500us_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => '1', D => time_out_500us_i_1_n_0, Q => time_out_500us, R => '0' ); \time_out_counter[0]_i_1__0\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => time_out_2ms_1, O => time_out_counter ); \time_out_counter[0]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"00000004" ) port map ( I0 => \time_out_counter[0]_i_5__0_n_0\, I1 => \time_out_counter[0]_i_6__0_n_0\, I2 => \time_out_counter[0]_i_7_n_0\, I3 => \time_out_counter[0]_i_8_n_0\, I4 => time_out_500us_i_3_n_0, O => time_out_2ms_1 ); \time_out_counter[0]_i_4\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => time_out_counter_reg(0), O => \time_out_counter[0]_i_4_n_0\ ); \time_out_counter[0]_i_5__0\: unisim.vcomponents.LUT4 generic map( INIT => X"FFF7" ) port map ( I0 => time_out_counter_reg(9), I1 => time_out_counter_reg(1), I2 => time_out_counter_reg(6), I3 => time_out_counter_reg(5), O => \time_out_counter[0]_i_5__0_n_0\ ); \time_out_counter[0]_i_6__0\: unisim.vcomponents.LUT4 generic map( INIT => X"1000" ) port map ( I0 => time_out_counter_reg(4), I1 => time_out_counter_reg(14), I2 => time_out_counter_reg(17), I3 => time_out_counter_reg(3), O => \time_out_counter[0]_i_6__0_n_0\ ); \time_out_counter[0]_i_7\: unisim.vcomponents.LUT3 generic map( INIT => X"FB" ) port map ( I0 => time_out_counter_reg(7), I1 => time_out_counter_reg(11), I2 => time_out_counter_reg(18), O => \time_out_counter[0]_i_7_n_0\ ); \time_out_counter[0]_i_8\: unisim.vcomponents.LUT4 generic map( INIT => X"EFFF" ) port map ( I0 => time_out_counter_reg(13), I1 => time_out_counter_reg(12), I2 => time_out_counter_reg(15), I3 => time_out_counter_reg(8), O => \time_out_counter[0]_i_8_n_0\ ); \time_out_counter_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => time_out_counter, D => \time_out_counter_reg[0]_i_2_n_7\, Q => time_out_counter_reg(0), R => reset_time_out ); \time_out_counter_reg[0]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \time_out_counter_reg[0]_i_2_n_0\, CO(2) => \time_out_counter_reg[0]_i_2_n_1\, CO(1) => \time_out_counter_reg[0]_i_2_n_2\, CO(0) => \time_out_counter_reg[0]_i_2_n_3\, CYINIT => '0', DI(3 downto 0) => B"0001", O(3) => \time_out_counter_reg[0]_i_2_n_4\, O(2) => \time_out_counter_reg[0]_i_2_n_5\, O(1) => \time_out_counter_reg[0]_i_2_n_6\, O(0) => \time_out_counter_reg[0]_i_2_n_7\, S(3 downto 1) => time_out_counter_reg(3 downto 1), S(0) => \time_out_counter[0]_i_4_n_0\ ); \time_out_counter_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => time_out_counter, D => \time_out_counter_reg[8]_i_1_n_5\, Q => time_out_counter_reg(10), R => reset_time_out ); \time_out_counter_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => time_out_counter, D => \time_out_counter_reg[8]_i_1_n_4\, Q => time_out_counter_reg(11), R => reset_time_out ); \time_out_counter_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => time_out_counter, D => \time_out_counter_reg[12]_i_1_n_7\, Q => time_out_counter_reg(12), R => reset_time_out ); \time_out_counter_reg[12]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \time_out_counter_reg[8]_i_1_n_0\, CO(3) => \time_out_counter_reg[12]_i_1_n_0\, CO(2) => \time_out_counter_reg[12]_i_1_n_1\, CO(1) => \time_out_counter_reg[12]_i_1_n_2\, CO(0) => \time_out_counter_reg[12]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \time_out_counter_reg[12]_i_1_n_4\, O(2) => \time_out_counter_reg[12]_i_1_n_5\, O(1) => \time_out_counter_reg[12]_i_1_n_6\, O(0) => \time_out_counter_reg[12]_i_1_n_7\, S(3 downto 0) => time_out_counter_reg(15 downto 12) ); \time_out_counter_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => time_out_counter, D => \time_out_counter_reg[12]_i_1_n_6\, Q => time_out_counter_reg(13), R => reset_time_out ); \time_out_counter_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => time_out_counter, D => \time_out_counter_reg[12]_i_1_n_5\, Q => time_out_counter_reg(14), R => reset_time_out ); \time_out_counter_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => time_out_counter, D => \time_out_counter_reg[12]_i_1_n_4\, Q => time_out_counter_reg(15), R => reset_time_out ); \time_out_counter_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => time_out_counter, D => \time_out_counter_reg[16]_i_1_n_7\, Q => time_out_counter_reg(16), R => reset_time_out ); \time_out_counter_reg[16]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \time_out_counter_reg[12]_i_1_n_0\, CO(3 downto 2) => \NLW_time_out_counter_reg[16]_i_1_CO_UNCONNECTED\(3 downto 2), CO(1) => \time_out_counter_reg[16]_i_1_n_2\, CO(0) => \time_out_counter_reg[16]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \NLW_time_out_counter_reg[16]_i_1_O_UNCONNECTED\(3), O(2) => \time_out_counter_reg[16]_i_1_n_5\, O(1) => \time_out_counter_reg[16]_i_1_n_6\, O(0) => \time_out_counter_reg[16]_i_1_n_7\, S(3) => '0', S(2 downto 0) => time_out_counter_reg(18 downto 16) ); \time_out_counter_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => time_out_counter, D => \time_out_counter_reg[16]_i_1_n_6\, Q => time_out_counter_reg(17), R => reset_time_out ); \time_out_counter_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => time_out_counter, D => \time_out_counter_reg[16]_i_1_n_5\, Q => time_out_counter_reg(18), R => reset_time_out ); \time_out_counter_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => time_out_counter, D => \time_out_counter_reg[0]_i_2_n_6\, Q => time_out_counter_reg(1), R => reset_time_out ); \time_out_counter_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => time_out_counter, D => \time_out_counter_reg[0]_i_2_n_5\, Q => time_out_counter_reg(2), R => reset_time_out ); \time_out_counter_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => time_out_counter, D => \time_out_counter_reg[0]_i_2_n_4\, Q => time_out_counter_reg(3), R => reset_time_out ); \time_out_counter_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => time_out_counter, D => \time_out_counter_reg[4]_i_1_n_7\, Q => time_out_counter_reg(4), R => reset_time_out ); \time_out_counter_reg[4]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \time_out_counter_reg[0]_i_2_n_0\, CO(3) => \time_out_counter_reg[4]_i_1_n_0\, CO(2) => \time_out_counter_reg[4]_i_1_n_1\, CO(1) => \time_out_counter_reg[4]_i_1_n_2\, CO(0) => \time_out_counter_reg[4]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \time_out_counter_reg[4]_i_1_n_4\, O(2) => \time_out_counter_reg[4]_i_1_n_5\, O(1) => \time_out_counter_reg[4]_i_1_n_6\, O(0) => \time_out_counter_reg[4]_i_1_n_7\, S(3 downto 0) => time_out_counter_reg(7 downto 4) ); \time_out_counter_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => time_out_counter, D => \time_out_counter_reg[4]_i_1_n_6\, Q => time_out_counter_reg(5), R => reset_time_out ); \time_out_counter_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => time_out_counter, D => \time_out_counter_reg[4]_i_1_n_5\, Q => time_out_counter_reg(6), R => reset_time_out ); \time_out_counter_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => time_out_counter, D => \time_out_counter_reg[4]_i_1_n_4\, Q => time_out_counter_reg(7), R => reset_time_out ); \time_out_counter_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => time_out_counter, D => \time_out_counter_reg[8]_i_1_n_7\, Q => time_out_counter_reg(8), R => reset_time_out ); \time_out_counter_reg[8]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \time_out_counter_reg[4]_i_1_n_0\, CO(3) => \time_out_counter_reg[8]_i_1_n_0\, CO(2) => \time_out_counter_reg[8]_i_1_n_1\, CO(1) => \time_out_counter_reg[8]_i_1_n_2\, CO(0) => \time_out_counter_reg[8]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \time_out_counter_reg[8]_i_1_n_4\, O(2) => \time_out_counter_reg[8]_i_1_n_5\, O(1) => \time_out_counter_reg[8]_i_1_n_6\, O(0) => \time_out_counter_reg[8]_i_1_n_7\, S(3 downto 0) => time_out_counter_reg(11 downto 8) ); \time_out_counter_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => time_out_counter, D => \time_out_counter_reg[8]_i_1_n_6\, Q => time_out_counter_reg(9), R => reset_time_out ); time_out_wait_bypass_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => u_rst_sync_tx_fsm_rst_done_n_0, Q => time_out_wait_bypass_reg_n_0, R => '0' ); \time_tlock_max_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"00AE" ) port map ( I0 => time_tlock_max_reg_n_0, I1 => \time_tlock_max_i_2__0_n_0\, I2 => \time_tlock_max_i_3__0_n_0\, I3 => reset_time_out, O => \time_tlock_max_i_1__0_n_0\ ); \time_tlock_max_i_2__0\: unisim.vcomponents.LUT5 generic map( INIT => X"00000010" ) port map ( I0 => time_out_counter_reg(1), I1 => time_out_counter_reg(9), I2 => time_out_counter_reg(3), I3 => time_out_counter_reg(10), I4 => \time_tlock_max_i_4__0_n_0\, O => \time_tlock_max_i_2__0_n_0\ ); \time_tlock_max_i_3__0\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFFFB" ) port map ( I0 => time_out_500us_i_5_n_0, I1 => time_out_counter_reg(7), I2 => time_out_counter_reg(15), I3 => time_out_counter_reg(16), I4 => time_out_500us_i_4_n_0, O => \time_tlock_max_i_3__0_n_0\ ); \time_tlock_max_i_4__0\: unisim.vcomponents.LUT4 generic map( INIT => X"EFFF" ) port map ( I0 => time_out_counter_reg(6), I1 => time_out_counter_reg(5), I2 => time_out_counter_reg(2), I3 => time_out_counter_reg(0), O => \time_tlock_max_i_4__0_n_0\ ); time_tlock_max_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => '1', D => \time_tlock_max_i_1__0_n_0\, Q => time_tlock_max_reg_n_0, R => '0' ); tx_fsm_reset_done_int_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"FFFF1000" ) port map ( I0 => tx_state(0), I1 => tx_state(4), I2 => tx_state(5), I3 => tx_fsm_reset_done_int_i_2_n_0, I4 => tx_fsm_reset_done_int, O => tx_fsm_reset_done_int_i_1_n_0 ); tx_fsm_reset_done_int_i_2: unisim.vcomponents.LUT5 generic map( INIT => X"00000001" ) port map ( I0 => tx_state(6), I1 => tx_state(7), I2 => tx_state(1), I3 => tx_state(2), I4 => tx_state(3), O => tx_fsm_reset_done_int_i_2_n_0 ); tx_fsm_reset_done_int_reg: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => '1', CLR => \init_wait_count_reg[7]_0\, D => tx_fsm_reset_done_int_i_1_n_0, Q => tx_fsm_reset_done_int ); tx_seq_scramb_reset_int_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"01FF0100" ) port map ( I0 => tx_state(3), I1 => tx_state(5), I2 => tx_state(4), I3 => \tx_seq_scramb_reset_int__0\, I4 => tx_seq_scramb_reset_int, O => tx_seq_scramb_reset_int_i_1_n_0 ); tx_seq_scramb_reset_int_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000000100010154" ) port map ( I0 => tx_seq_scramb_reset_int_i_3_n_0, I1 => tx_state(2), I2 => tx_state(3), I3 => tx_state(7), I4 => tx_state(5), I5 => tx_state(4), O => \tx_seq_scramb_reset_int__0\ ); tx_seq_scramb_reset_int_i_3: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFFF8" ) port map ( I0 => tx_state(2), I1 => tx_state(3), I2 => tx_state(1), I3 => tx_state(0), I4 => tx_state(6), O => tx_seq_scramb_reset_int_i_3_n_0 ); tx_seq_scramb_reset_int_reg: unisim.vcomponents.FDPE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => '1', D => tx_seq_scramb_reset_int_i_1_n_0, PRE => \init_wait_count_reg[7]_0\, Q => tx_seq_scramb_reset_int ); \tx_state[0]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"0EFF" ) port map ( I0 => time_tlock_max_reg_n_0, I1 => tx_state(0), I2 => mmcm_lock_r2, I3 => \tx_state[7]_i_6_n_0\, O => \tx_state[0]_i_3_n_0\ ); \tx_state[1]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"77777777777777F7" ) port map ( I0 => \tx_state[7]_i_8_n_0\, I1 => tx_state(1), I2 => \wait_time_cnt[0]_i_8_n_0\, I3 => \wait_time_cnt[0]_i_7_n_0\, I4 => \wait_time_cnt[0]_i_6_n_0\, I5 => \wait_time_cnt[0]_i_5_n_0\, O => \tx_state[1]_i_5_n_0\ ); \tx_state[1]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFDFFFF00000000" ) port map ( I0 => \tx_state[7]_i_8_n_0\, I1 => \wait_time_cnt[0]_i_5_n_0\, I2 => \wait_time_cnt[0]_i_6_n_0\, I3 => \wait_time_cnt[0]_i_7_n_0\, I4 => \wait_time_cnt[0]_i_8_n_0\, I5 => \tx_state[7]_i_6_n_0\, O => \tx_state[1]_i_6_n_0\ ); \tx_state[2]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FEFF0000FFFFFFFF" ) port map ( I0 => \wait_time_cnt[0]_i_5_n_0\, I1 => \wait_time_cnt[0]_i_6_n_0\, I2 => \wait_time_cnt[0]_i_7_n_0\, I3 => \wait_time_cnt[0]_i_8_n_0\, I4 => tx_state(2), I5 => \tx_state[7]_i_6_n_0\, O => \tx_state[2]_i_2_n_0\ ); \tx_state[2]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFBFFFFFFFF" ) port map ( I0 => \tx_state[7]_i_7_n_0\, I1 => \tx_state[7]_i_8_n_0\, I2 => \wait_time_cnt[0]_i_5_n_0\, I3 => \wait_time_cnt[0]_i_6_n_0\, I4 => \wait_time_cnt[0]_i_7_n_0\, I5 => \wait_time_cnt[0]_i_8_n_0\, O => \tx_state[2]_i_5_n_0\ ); \tx_state[2]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAAAAAAAAAB" ) port map ( I0 => tx_state(2), I1 => tx_state(7), I2 => tx_state(3), I3 => tx_state(4), I4 => tx_state(1), I5 => tx_state(6), O => \tx_state[2]_i_6_n_0\ ); \tx_state[2]_i_7\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFF1" ) port map ( I0 => time_tlock_max_reg_n_0, I1 => mmcm_lock_r2, I2 => tx_state(6), I3 => tx_state(1), I4 => tx_state(4), I5 => tx_state(3), O => \tx_state[2]_i_7_n_0\ ); \tx_state[5]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFEEE0" ) port map ( I0 => tx_state(7), I1 => tx_state(2), I2 => tx_state(6), I3 => tx_state(1), I4 => tx_state(4), I5 => tx_state(3), O => \tx_state[5]_i_2_n_0\ ); \tx_state[5]_i_6\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFDFFFF" ) port map ( I0 => \wait_time_cnt[0]_i_8_n_0\, I1 => \wait_time_cnt[0]_i_7_n_0\, I2 => \wait_time_cnt[0]_i_6_n_0\, I3 => \wait_time_cnt[0]_i_5_n_0\, I4 => \tx_state[7]_i_8_n_0\, O => \tx_state[5]_i_6_n_0\ ); \tx_state[7]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"101010FF10101010" ) port map ( I0 => tx_state(4), I1 => \tx_state[7]_i_3_n_0\, I2 => \tx_state[7]_i_4_n_0\, I3 => tx_state(5), I4 => tx_state(0), I5 => \tx_state[7]_i_5_n_0\, O => \tx_state[7]_i_1_n_0\ ); \tx_state[7]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => tx_state(7), I1 => tx_state(6), O => \tx_state[7]_i_3_n_0\ ); \tx_state[7]_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => tx_state(2), I1 => tx_state(1), I2 => tx_state(5), I3 => tx_state(3), O => \tx_state[7]_i_4_n_0\ ); \tx_state[7]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000100010117" ) port map ( I0 => tx_state(4), I1 => tx_state(6), I2 => tx_state(7), I3 => tx_state(3), I4 => tx_state(2), I5 => tx_state(1), O => \tx_state[7]_i_5_n_0\ ); \tx_state[7]_i_6\: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => tx_state(3), I1 => tx_state(4), I2 => tx_state(1), I3 => tx_state(6), O => \tx_state[7]_i_6_n_0\ ); \tx_state[7]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => tx_state(3), I1 => tx_state(4), I2 => tx_state(2), I3 => tx_state(7), O => \tx_state[7]_i_7_n_0\ ); \tx_state[7]_i_8\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => tx_state(0), I1 => tx_state(6), I2 => tx_state(4), I3 => tx_state(7), O => \tx_state[7]_i_8_n_0\ ); \tx_state[7]_i_9\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF00000008" ) port map ( I0 => mmcm_lock_r2, I1 => \tx_state[7]_i_6_n_0\, I2 => tx_state(0), I3 => tx_state(6), I4 => tx_state(4), I5 => tx_state(7), O => \tx_state[7]_i_9_n_0\ ); \tx_state_reg[0]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \tx_state[7]_i_1_n_0\, CLR => \init_wait_count_reg[7]_0\, D => \p_0_in__0\(0), Q => tx_state(0) ); \tx_state_reg[1]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \tx_state[7]_i_1_n_0\, CLR => \init_wait_count_reg[7]_0\, D => \p_0_in__0\(1), Q => tx_state(1) ); \tx_state_reg[2]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \tx_state[7]_i_1_n_0\, CLR => \init_wait_count_reg[7]_0\, D => \p_0_in__0\(2), Q => tx_state(2) ); \tx_state_reg[3]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \tx_state[7]_i_1_n_0\, CLR => \init_wait_count_reg[7]_0\, D => \p_0_in__0\(3), Q => tx_state(3) ); \tx_state_reg[4]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \tx_state[7]_i_1_n_0\, CLR => \init_wait_count_reg[7]_0\, D => \p_0_in__0\(4), Q => tx_state(4) ); \tx_state_reg[5]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \tx_state[7]_i_1_n_0\, CLR => \init_wait_count_reg[7]_0\, D => \p_0_in__0\(5), Q => tx_state(5) ); \tx_state_reg[6]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \tx_state[7]_i_1_n_0\, CLR => \init_wait_count_reg[7]_0\, D => \p_0_in__0\(6), Q => tx_state(6) ); \tx_state_reg[7]\: unisim.vcomponents.FDCE generic map( INIT => '0' ) port map ( C => stg5_reg_0, CE => \tx_state[7]_i_1_n_0\, CLR => \init_wait_count_reg[7]_0\, D => \p_0_in__0\(7), Q => tx_state(7) ); u_rst_sync_plllock: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1\ port map ( D(0) => \p_0_in__0\(0), Q(4 downto 3) => tx_state(7 downto 6), Q(2) => tx_state(4), Q(1 downto 0) => tx_state(1 downto 0), init_wait_done => init_wait_done, init_wait_done_reg => u_rst_sync_plllock_n_3, \out\ => \out\, reset_time_out => reset_time_out, reset_time_out_reg(6 downto 5) => tx_state(7 downto 6), reset_time_out_reg(4 downto 0) => tx_state(4 downto 0), reset_time_out_reg_0 => reset_time_out_i_3_n_0, reset_time_out_reg_1 => u_rst_sync_txresetdone_n_0, reset_time_out_reg_2 => mmcm_lock_r2, reset_time_out_reg_3 => reset_time_out_i_6_n_0, reset_time_out_reg_4 => reset_time_out_i_7_n_0, sel => sel, stg5_reg_0 => u_rst_sync_plllock_n_1, stg5_reg_1 => stg5_reg_0, time_out_2ms => time_out_2ms, \tx_state_reg[0]\ => \tx_state[0]_i_3_n_0\, \tx_state_reg[0]_0\ => u_rst_sync_txresetdone_n_4, \tx_state_reg[0]_1\ => u_rst_sync_time_out_wait_bypass_n_6, \tx_state_reg[1]\ => u_rst_sync_plllock_n_4, \tx_state_reg[3]\ => \tx_state[7]_i_6_n_0\, \tx_state_reg[3]_0\ => \tx_state[7]_i_8_n_0\, \tx_state_reg[3]_1\ => \tx_state[7]_i_7_n_0\, \tx_state_reg[6]\ => u_rst_sync_plllock_n_0, \tx_state_reg[7]\ => u_rst_sync_plllock_n_5 ); u_rst_sync_run_phase_align: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_13\ port map ( clear => clear, in0 => run_phase_alignment_int_reg_n_0, stg4_reg_0 => stg4_reg, stg5_reg_0 => u_rst_sync_run_phase_align_n_0 ); u_rst_sync_time_out_wait_bypass: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_14\ port map ( D(5 downto 2) => \p_0_in__0\(7 downto 4), D(1 downto 0) => \p_0_in__0\(2 downto 1), Q(6 downto 2) => tx_state(7 downto 3), Q(1 downto 0) => tx_state(1 downto 0), in0 => time_out_wait_bypass_reg_n_0, sel => sel, stg4_reg_0 => stg5_reg_0, stg5_reg_0 => u_rst_sync_time_out_wait_bypass_n_6, \tx_state_reg[1]\ => u_rst_sync_txresetdone_n_6, \tx_state_reg[1]_0\ => \tx_state[7]_i_7_n_0\, \tx_state_reg[1]_1\ => u_rst_sync_plllock_n_1, \tx_state_reg[1]_2\ => \tx_state[1]_i_5_n_0\, \tx_state_reg[1]_3\ => \tx_state[1]_i_6_n_0\, \tx_state_reg[2]\ => \tx_state[7]_i_8_n_0\, \tx_state_reg[2]_0\ => \tx_state[2]_i_2_n_0\, \tx_state_reg[2]_1\ => u_rst_sync_txresetdone_n_3, \tx_state_reg[2]_2\ => \tx_state[2]_i_5_n_0\, \tx_state_reg[2]_3\ => \tx_state[2]_i_6_n_0\, \tx_state_reg[2]_4\ => \wait_time_cnt[0]_i_5_n_0\, \tx_state_reg[2]_5\ => \wait_time_cnt[0]_i_6_n_0\, \tx_state_reg[2]_6\ => \wait_time_cnt[0]_i_7_n_0\, \tx_state_reg[2]_7\ => \wait_time_cnt[0]_i_8_n_0\, \tx_state_reg[4]\ => u_rst_sync_txresetdone_n_5, \tx_state_reg[5]\ => \tx_state[5]_i_2_n_0\, \tx_state_reg[5]_0\ => u_rst_sync_plllock_n_3, \tx_state_reg[5]_1\ => u_rst_sync_txresetdone_n_1, \tx_state_reg[5]_2\ => \tx_state[5]_i_6_n_0\, \tx_state_reg[6]\ => \tx_state[7]_i_6_n_0\, \tx_state_reg[6]_0\ => u_rst_sync_plllock_n_5, \tx_state_reg[7]\ => u_rst_sync_time_out_wait_bypass_n_7, \tx_state_reg[7]_0\ => \tx_state[7]_i_9_n_0\ ); u_rst_sync_tx_fsm_rst_done: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_15\ port map ( in0 => time_out_wait_bypass_reg_n_0, stg1_aurora_64b66b_0_cdc_to_reg_0 => tx_fsm_reset_done_int, stg4_reg_0 => stg4_reg, stg5_reg_0 => u_rst_sync_tx_fsm_rst_done_n_1, time_out_wait_bypass_reg => u_rst_sync_tx_fsm_rst_done_n_0, time_out_wait_bypass_reg_0 => \wait_bypass_count[0]_i_4_n_0\, time_out_wait_bypass_reg_1 => u_rst_sync_run_phase_align_n_0 ); u_rst_sync_tx_seq_scram_rst: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_16\ port map ( \out\ => tx_seq_scramb_reset_int, stg4_reg_0 => stg4_reg, stg5_reg_0 => stg5_reg ); u_rst_sync_txresetdone: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized1_17\ port map ( D(0) => \p_0_in__0\(3), Q(3 downto 2) => tx_state(4 downto 3), Q(1 downto 0) => tx_state(1 downto 0), mmcm_lock_r2_reg => u_rst_sync_txresetdone_n_1, \out\ => mmcm_lock_r2, stg1_aurora_64b66b_0_cdc_to_reg_0 => stg1_aurora_64b66b_0_cdc_to_reg, stg5_reg_0 => u_rst_sync_txresetdone_n_0, stg5_reg_1 => u_rst_sync_txresetdone_n_6, stg5_reg_2 => stg5_reg_0, time_out_500us => time_out_500us, time_out_500us_reg => u_rst_sync_txresetdone_n_4, \tx_state_reg[2]\ => \tx_state[7]_i_8_n_0\, \tx_state_reg[2]_0\ => \tx_state[7]_i_6_n_0\, \tx_state_reg[2]_1\ => \tx_state[2]_i_7_n_0\, \tx_state_reg[2]_2\ => u_rst_sync_plllock_n_4, \tx_state_reg[3]\ => u_rst_sync_txresetdone_n_3, \tx_state_reg[3]_0\ => \tx_state[7]_i_7_n_0\, \tx_state_reg[3]_1\ => u_rst_sync_time_out_wait_bypass_n_7, \tx_state_reg[3]_2\ => u_rst_sync_plllock_n_3, \tx_state_reg[3]_3\ => \tx_state[5]_i_6_n_0\, \tx_state_reg[4]\ => u_rst_sync_txresetdone_n_5, \tx_state_reg[5]\ => time_tlock_max_reg_n_0 ); \wait_bypass_count[0]_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => \wait_bypass_count[0]_i_6_n_0\, I1 => \wait_bypass_count[0]_i_7_n_0\, I2 => \wait_bypass_count[0]_i_8_n_0\, I3 => \wait_bypass_count[0]_i_9_n_0\, O => \wait_bypass_count[0]_i_4_n_0\ ); \wait_bypass_count[0]_i_5\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => wait_bypass_count_reg(0), O => \wait_bypass_count[0]_i_5_n_0\ ); \wait_bypass_count[0]_i_6\: unisim.vcomponents.LUT4 generic map( INIT => X"FFDF" ) port map ( I0 => wait_bypass_count_reg(3), I1 => wait_bypass_count_reg(4), I2 => wait_bypass_count_reg(5), I3 => wait_bypass_count_reg(6), O => \wait_bypass_count[0]_i_6_n_0\ ); \wait_bypass_count[0]_i_7\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFFFFFF" ) port map ( I0 => wait_bypass_count_reg(0), I1 => wait_bypass_count_reg(15), I2 => wait_bypass_count_reg(16), I3 => wait_bypass_count_reg(2), I4 => wait_bypass_count_reg(1), O => \wait_bypass_count[0]_i_7_n_0\ ); \wait_bypass_count[0]_i_8\: unisim.vcomponents.LUT4 generic map( INIT => X"FFDF" ) port map ( I0 => wait_bypass_count_reg(11), I1 => wait_bypass_count_reg(12), I2 => wait_bypass_count_reg(13), I3 => wait_bypass_count_reg(14), O => \wait_bypass_count[0]_i_8_n_0\ ); \wait_bypass_count[0]_i_9\: unisim.vcomponents.LUT4 generic map( INIT => X"FF7F" ) port map ( I0 => wait_bypass_count_reg(8), I1 => wait_bypass_count_reg(7), I2 => wait_bypass_count_reg(10), I3 => wait_bypass_count_reg(9), O => \wait_bypass_count[0]_i_9_n_0\ ); \wait_bypass_count_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => u_rst_sync_tx_fsm_rst_done_n_1, D => \wait_bypass_count_reg[0]_i_3_n_7\, Q => wait_bypass_count_reg(0), R => clear ); \wait_bypass_count_reg[0]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \wait_bypass_count_reg[0]_i_3_n_0\, CO(2) => \wait_bypass_count_reg[0]_i_3_n_1\, CO(1) => \wait_bypass_count_reg[0]_i_3_n_2\, CO(0) => \wait_bypass_count_reg[0]_i_3_n_3\, CYINIT => '0', DI(3 downto 0) => B"0001", O(3) => \wait_bypass_count_reg[0]_i_3_n_4\, O(2) => \wait_bypass_count_reg[0]_i_3_n_5\, O(1) => \wait_bypass_count_reg[0]_i_3_n_6\, O(0) => \wait_bypass_count_reg[0]_i_3_n_7\, S(3 downto 1) => wait_bypass_count_reg(3 downto 1), S(0) => \wait_bypass_count[0]_i_5_n_0\ ); \wait_bypass_count_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => u_rst_sync_tx_fsm_rst_done_n_1, D => \wait_bypass_count_reg[8]_i_1_n_5\, Q => wait_bypass_count_reg(10), R => clear ); \wait_bypass_count_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => u_rst_sync_tx_fsm_rst_done_n_1, D => \wait_bypass_count_reg[8]_i_1_n_4\, Q => wait_bypass_count_reg(11), R => clear ); \wait_bypass_count_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => u_rst_sync_tx_fsm_rst_done_n_1, D => \wait_bypass_count_reg[12]_i_1_n_7\, Q => wait_bypass_count_reg(12), R => clear ); \wait_bypass_count_reg[12]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \wait_bypass_count_reg[8]_i_1_n_0\, CO(3) => \wait_bypass_count_reg[12]_i_1_n_0\, CO(2) => \wait_bypass_count_reg[12]_i_1_n_1\, CO(1) => \wait_bypass_count_reg[12]_i_1_n_2\, CO(0) => \wait_bypass_count_reg[12]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \wait_bypass_count_reg[12]_i_1_n_4\, O(2) => \wait_bypass_count_reg[12]_i_1_n_5\, O(1) => \wait_bypass_count_reg[12]_i_1_n_6\, O(0) => \wait_bypass_count_reg[12]_i_1_n_7\, S(3 downto 0) => wait_bypass_count_reg(15 downto 12) ); \wait_bypass_count_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => u_rst_sync_tx_fsm_rst_done_n_1, D => \wait_bypass_count_reg[12]_i_1_n_6\, Q => wait_bypass_count_reg(13), R => clear ); \wait_bypass_count_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => u_rst_sync_tx_fsm_rst_done_n_1, D => \wait_bypass_count_reg[12]_i_1_n_5\, Q => wait_bypass_count_reg(14), R => clear ); \wait_bypass_count_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => u_rst_sync_tx_fsm_rst_done_n_1, D => \wait_bypass_count_reg[12]_i_1_n_4\, Q => wait_bypass_count_reg(15), R => clear ); \wait_bypass_count_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => u_rst_sync_tx_fsm_rst_done_n_1, D => \wait_bypass_count_reg[16]_i_1_n_7\, Q => wait_bypass_count_reg(16), R => clear ); \wait_bypass_count_reg[16]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \wait_bypass_count_reg[12]_i_1_n_0\, CO(3 downto 0) => \NLW_wait_bypass_count_reg[16]_i_1_CO_UNCONNECTED\(3 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 1) => \NLW_wait_bypass_count_reg[16]_i_1_O_UNCONNECTED\(3 downto 1), O(0) => \wait_bypass_count_reg[16]_i_1_n_7\, S(3 downto 1) => B"000", S(0) => wait_bypass_count_reg(16) ); \wait_bypass_count_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => u_rst_sync_tx_fsm_rst_done_n_1, D => \wait_bypass_count_reg[0]_i_3_n_6\, Q => wait_bypass_count_reg(1), R => clear ); \wait_bypass_count_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => u_rst_sync_tx_fsm_rst_done_n_1, D => \wait_bypass_count_reg[0]_i_3_n_5\, Q => wait_bypass_count_reg(2), R => clear ); \wait_bypass_count_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => u_rst_sync_tx_fsm_rst_done_n_1, D => \wait_bypass_count_reg[0]_i_3_n_4\, Q => wait_bypass_count_reg(3), R => clear ); \wait_bypass_count_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => u_rst_sync_tx_fsm_rst_done_n_1, D => \wait_bypass_count_reg[4]_i_1_n_7\, Q => wait_bypass_count_reg(4), R => clear ); \wait_bypass_count_reg[4]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \wait_bypass_count_reg[0]_i_3_n_0\, CO(3) => \wait_bypass_count_reg[4]_i_1_n_0\, CO(2) => \wait_bypass_count_reg[4]_i_1_n_1\, CO(1) => \wait_bypass_count_reg[4]_i_1_n_2\, CO(0) => \wait_bypass_count_reg[4]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \wait_bypass_count_reg[4]_i_1_n_4\, O(2) => \wait_bypass_count_reg[4]_i_1_n_5\, O(1) => \wait_bypass_count_reg[4]_i_1_n_6\, O(0) => \wait_bypass_count_reg[4]_i_1_n_7\, S(3 downto 0) => wait_bypass_count_reg(7 downto 4) ); \wait_bypass_count_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => u_rst_sync_tx_fsm_rst_done_n_1, D => \wait_bypass_count_reg[4]_i_1_n_6\, Q => wait_bypass_count_reg(5), R => clear ); \wait_bypass_count_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => u_rst_sync_tx_fsm_rst_done_n_1, D => \wait_bypass_count_reg[4]_i_1_n_5\, Q => wait_bypass_count_reg(6), R => clear ); \wait_bypass_count_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => u_rst_sync_tx_fsm_rst_done_n_1, D => \wait_bypass_count_reg[4]_i_1_n_4\, Q => wait_bypass_count_reg(7), R => clear ); \wait_bypass_count_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => u_rst_sync_tx_fsm_rst_done_n_1, D => \wait_bypass_count_reg[8]_i_1_n_7\, Q => wait_bypass_count_reg(8), R => clear ); \wait_bypass_count_reg[8]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \wait_bypass_count_reg[4]_i_1_n_0\, CO(3) => \wait_bypass_count_reg[8]_i_1_n_0\, CO(2) => \wait_bypass_count_reg[8]_i_1_n_1\, CO(1) => \wait_bypass_count_reg[8]_i_1_n_2\, CO(0) => \wait_bypass_count_reg[8]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \wait_bypass_count_reg[8]_i_1_n_4\, O(2) => \wait_bypass_count_reg[8]_i_1_n_5\, O(1) => \wait_bypass_count_reg[8]_i_1_n_6\, O(0) => \wait_bypass_count_reg[8]_i_1_n_7\, S(3 downto 0) => wait_bypass_count_reg(11 downto 8) ); \wait_bypass_count_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => u_rst_sync_tx_fsm_rst_done_n_1, D => \wait_bypass_count_reg[8]_i_1_n_6\, Q => wait_bypass_count_reg(9), R => clear ); \wait_time_cnt[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000002" ) port map ( I0 => \wait_time_cnt[0]_i_4_n_0\, I1 => tx_state(6), I2 => tx_state(0), I3 => tx_state(4), I4 => tx_state(7), I5 => tx_state(5), O => \wait_time_cnt[0]_i_1_n_0\ ); \wait_time_cnt[0]_i_10\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => wait_time_cnt_reg(2), O => \wait_time_cnt[0]_i_10_n_0\ ); \wait_time_cnt[0]_i_11\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => wait_time_cnt_reg(1), O => \wait_time_cnt[0]_i_11_n_0\ ); \wait_time_cnt[0]_i_12\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => wait_time_cnt_reg(0), O => \wait_time_cnt[0]_i_12_n_0\ ); \wait_time_cnt[0]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"FEFF" ) port map ( I0 => \wait_time_cnt[0]_i_5_n_0\, I1 => \wait_time_cnt[0]_i_6_n_0\, I2 => \wait_time_cnt[0]_i_7_n_0\, I3 => \wait_time_cnt[0]_i_8_n_0\, O => sel ); \wait_time_cnt[0]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"17" ) port map ( I0 => tx_state(3), I1 => tx_state(2), I2 => tx_state(1), O => \wait_time_cnt[0]_i_4_n_0\ ); \wait_time_cnt[0]_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => wait_time_cnt_reg(6), I1 => wait_time_cnt_reg(5), I2 => wait_time_cnt_reg(7), I3 => wait_time_cnt_reg(4), O => \wait_time_cnt[0]_i_5_n_0\ ); \wait_time_cnt[0]_i_6\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => wait_time_cnt_reg(0), I1 => wait_time_cnt_reg(3), I2 => wait_time_cnt_reg(1), I3 => wait_time_cnt_reg(2), O => \wait_time_cnt[0]_i_6_n_0\ ); \wait_time_cnt[0]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => wait_time_cnt_reg(8), I1 => wait_time_cnt_reg(11), I2 => wait_time_cnt_reg(9), I3 => wait_time_cnt_reg(10), O => \wait_time_cnt[0]_i_7_n_0\ ); \wait_time_cnt[0]_i_8\: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => wait_time_cnt_reg(15), I1 => wait_time_cnt_reg(13), I2 => wait_time_cnt_reg(14), I3 => wait_time_cnt_reg(12), O => \wait_time_cnt[0]_i_8_n_0\ ); \wait_time_cnt[0]_i_9\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => wait_time_cnt_reg(3), O => \wait_time_cnt[0]_i_9_n_0\ ); \wait_time_cnt[12]_i_2\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => wait_time_cnt_reg(15), O => \wait_time_cnt[12]_i_2_n_0\ ); \wait_time_cnt[12]_i_3\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => wait_time_cnt_reg(14), O => \wait_time_cnt[12]_i_3_n_0\ ); \wait_time_cnt[12]_i_4\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => wait_time_cnt_reg(13), O => \wait_time_cnt[12]_i_4_n_0\ ); \wait_time_cnt[12]_i_5\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => wait_time_cnt_reg(12), O => \wait_time_cnt[12]_i_5_n_0\ ); \wait_time_cnt[4]_i_2\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => wait_time_cnt_reg(7), O => \wait_time_cnt[4]_i_2_n_0\ ); \wait_time_cnt[4]_i_3\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => wait_time_cnt_reg(6), O => \wait_time_cnt[4]_i_3_n_0\ ); \wait_time_cnt[4]_i_4\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => wait_time_cnt_reg(5), O => \wait_time_cnt[4]_i_4_n_0\ ); \wait_time_cnt[4]_i_5\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => wait_time_cnt_reg(4), O => \wait_time_cnt[4]_i_5_n_0\ ); \wait_time_cnt[8]_i_2\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => wait_time_cnt_reg(11), O => \wait_time_cnt[8]_i_2_n_0\ ); \wait_time_cnt[8]_i_3\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => wait_time_cnt_reg(10), O => \wait_time_cnt[8]_i_3_n_0\ ); \wait_time_cnt[8]_i_4\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => wait_time_cnt_reg(9), O => \wait_time_cnt[8]_i_4_n_0\ ); \wait_time_cnt[8]_i_5\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => wait_time_cnt_reg(8), O => \wait_time_cnt[8]_i_5_n_0\ ); \wait_time_cnt_reg[0]\: unisim.vcomponents.FDSE port map ( C => stg5_reg_0, CE => sel, D => \wait_time_cnt_reg[0]_i_3_n_7\, Q => wait_time_cnt_reg(0), S => \wait_time_cnt[0]_i_1_n_0\ ); \wait_time_cnt_reg[0]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \wait_time_cnt_reg[0]_i_3_n_0\, CO(2) => \wait_time_cnt_reg[0]_i_3_n_1\, CO(1) => \wait_time_cnt_reg[0]_i_3_n_2\, CO(0) => \wait_time_cnt_reg[0]_i_3_n_3\, CYINIT => '0', DI(3 downto 0) => B"1111", O(3) => \wait_time_cnt_reg[0]_i_3_n_4\, O(2) => \wait_time_cnt_reg[0]_i_3_n_5\, O(1) => \wait_time_cnt_reg[0]_i_3_n_6\, O(0) => \wait_time_cnt_reg[0]_i_3_n_7\, S(3) => \wait_time_cnt[0]_i_9_n_0\, S(2) => \wait_time_cnt[0]_i_10_n_0\, S(1) => \wait_time_cnt[0]_i_11_n_0\, S(0) => \wait_time_cnt[0]_i_12_n_0\ ); \wait_time_cnt_reg[10]\: unisim.vcomponents.FDRE port map ( C => stg5_reg_0, CE => sel, D => \wait_time_cnt_reg[8]_i_1_n_5\, Q => wait_time_cnt_reg(10), R => \wait_time_cnt[0]_i_1_n_0\ ); \wait_time_cnt_reg[11]\: unisim.vcomponents.FDRE port map ( C => stg5_reg_0, CE => sel, D => \wait_time_cnt_reg[8]_i_1_n_4\, Q => wait_time_cnt_reg(11), R => \wait_time_cnt[0]_i_1_n_0\ ); \wait_time_cnt_reg[12]\: unisim.vcomponents.FDRE port map ( C => stg5_reg_0, CE => sel, D => \wait_time_cnt_reg[12]_i_1_n_7\, Q => wait_time_cnt_reg(12), R => \wait_time_cnt[0]_i_1_n_0\ ); \wait_time_cnt_reg[12]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \wait_time_cnt_reg[8]_i_1_n_0\, CO(3) => \NLW_wait_time_cnt_reg[12]_i_1_CO_UNCONNECTED\(3), CO(2) => \wait_time_cnt_reg[12]_i_1_n_1\, CO(1) => \wait_time_cnt_reg[12]_i_1_n_2\, CO(0) => \wait_time_cnt_reg[12]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => B"0111", O(3) => \wait_time_cnt_reg[12]_i_1_n_4\, O(2) => \wait_time_cnt_reg[12]_i_1_n_5\, O(1) => \wait_time_cnt_reg[12]_i_1_n_6\, O(0) => \wait_time_cnt_reg[12]_i_1_n_7\, S(3) => \wait_time_cnt[12]_i_2_n_0\, S(2) => \wait_time_cnt[12]_i_3_n_0\, S(1) => \wait_time_cnt[12]_i_4_n_0\, S(0) => \wait_time_cnt[12]_i_5_n_0\ ); \wait_time_cnt_reg[13]\: unisim.vcomponents.FDRE port map ( C => stg5_reg_0, CE => sel, D => \wait_time_cnt_reg[12]_i_1_n_6\, Q => wait_time_cnt_reg(13), R => \wait_time_cnt[0]_i_1_n_0\ ); \wait_time_cnt_reg[14]\: unisim.vcomponents.FDRE port map ( C => stg5_reg_0, CE => sel, D => \wait_time_cnt_reg[12]_i_1_n_5\, Q => wait_time_cnt_reg(14), R => \wait_time_cnt[0]_i_1_n_0\ ); \wait_time_cnt_reg[15]\: unisim.vcomponents.FDRE port map ( C => stg5_reg_0, CE => sel, D => \wait_time_cnt_reg[12]_i_1_n_4\, Q => wait_time_cnt_reg(15), R => \wait_time_cnt[0]_i_1_n_0\ ); \wait_time_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => stg5_reg_0, CE => sel, D => \wait_time_cnt_reg[0]_i_3_n_6\, Q => wait_time_cnt_reg(1), R => \wait_time_cnt[0]_i_1_n_0\ ); \wait_time_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => stg5_reg_0, CE => sel, D => \wait_time_cnt_reg[0]_i_3_n_5\, Q => wait_time_cnt_reg(2), R => \wait_time_cnt[0]_i_1_n_0\ ); \wait_time_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => stg5_reg_0, CE => sel, D => \wait_time_cnt_reg[0]_i_3_n_4\, Q => wait_time_cnt_reg(3), R => \wait_time_cnt[0]_i_1_n_0\ ); \wait_time_cnt_reg[4]\: unisim.vcomponents.FDRE port map ( C => stg5_reg_0, CE => sel, D => \wait_time_cnt_reg[4]_i_1_n_7\, Q => wait_time_cnt_reg(4), R => \wait_time_cnt[0]_i_1_n_0\ ); \wait_time_cnt_reg[4]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \wait_time_cnt_reg[0]_i_3_n_0\, CO(3) => \wait_time_cnt_reg[4]_i_1_n_0\, CO(2) => \wait_time_cnt_reg[4]_i_1_n_1\, CO(1) => \wait_time_cnt_reg[4]_i_1_n_2\, CO(0) => \wait_time_cnt_reg[4]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => B"1111", O(3) => \wait_time_cnt_reg[4]_i_1_n_4\, O(2) => \wait_time_cnt_reg[4]_i_1_n_5\, O(1) => \wait_time_cnt_reg[4]_i_1_n_6\, O(0) => \wait_time_cnt_reg[4]_i_1_n_7\, S(3) => \wait_time_cnt[4]_i_2_n_0\, S(2) => \wait_time_cnt[4]_i_3_n_0\, S(1) => \wait_time_cnt[4]_i_4_n_0\, S(0) => \wait_time_cnt[4]_i_5_n_0\ ); \wait_time_cnt_reg[5]\: unisim.vcomponents.FDRE port map ( C => stg5_reg_0, CE => sel, D => \wait_time_cnt_reg[4]_i_1_n_6\, Q => wait_time_cnt_reg(5), R => \wait_time_cnt[0]_i_1_n_0\ ); \wait_time_cnt_reg[6]\: unisim.vcomponents.FDSE port map ( C => stg5_reg_0, CE => sel, D => \wait_time_cnt_reg[4]_i_1_n_5\, Q => wait_time_cnt_reg(6), S => \wait_time_cnt[0]_i_1_n_0\ ); \wait_time_cnt_reg[7]\: unisim.vcomponents.FDRE port map ( C => stg5_reg_0, CE => sel, D => \wait_time_cnt_reg[4]_i_1_n_4\, Q => wait_time_cnt_reg(7), R => \wait_time_cnt[0]_i_1_n_0\ ); \wait_time_cnt_reg[8]\: unisim.vcomponents.FDSE port map ( C => stg5_reg_0, CE => sel, D => \wait_time_cnt_reg[8]_i_1_n_7\, Q => wait_time_cnt_reg(8), S => \wait_time_cnt[0]_i_1_n_0\ ); \wait_time_cnt_reg[8]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \wait_time_cnt_reg[4]_i_1_n_0\, CO(3) => \wait_time_cnt_reg[8]_i_1_n_0\, CO(2) => \wait_time_cnt_reg[8]_i_1_n_1\, CO(1) => \wait_time_cnt_reg[8]_i_1_n_2\, CO(0) => \wait_time_cnt_reg[8]_i_1_n_3\, CYINIT => '0', DI(3 downto 0) => B"1111", O(3) => \wait_time_cnt_reg[8]_i_1_n_4\, O(2) => \wait_time_cnt_reg[8]_i_1_n_5\, O(1) => \wait_time_cnt_reg[8]_i_1_n_6\, O(0) => \wait_time_cnt_reg[8]_i_1_n_7\, S(3) => \wait_time_cnt[8]_i_2_n_0\, S(2) => \wait_time_cnt[8]_i_3_n_0\, S(1) => \wait_time_cnt[8]_i_4_n_0\, S(0) => \wait_time_cnt[8]_i_5_n_0\ ); \wait_time_cnt_reg[9]\: unisim.vcomponents.FDSE port map ( C => stg5_reg_0, CE => sel, D => \wait_time_cnt_reg[8]_i_1_n_6\, Q => wait_time_cnt_reg(9), S => \wait_time_cnt[0]_i_1_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_TX_STREAM is port ( gen_cc_i : out STD_LOGIC; do_cc_r : out STD_LOGIC; tx_pe_data_v_i : out STD_LOGIC; extend_cc_r : out STD_LOGIC; s_axi_tx_tready : out STD_LOGIC; wait_for_lane_up_r_reg : out STD_LOGIC_VECTOR ( 1 downto 0 ); gen_cc_flop_0_i : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 61 downto 0 ); R0 : in STD_LOGIC; \out\ : in STD_LOGIC; do_cc_r_reg0 : in STD_LOGIC; tx_dst_rdy_n_r_reg : in STD_LOGIC; extend_cc_r_reg : in STD_LOGIC; s_axi_tx_tvalid : in STD_LOGIC; gen_na_idles_i : in STD_LOGIC; rst_pma_init_usrclk : in STD_LOGIC; channel_up_tx_if : in STD_LOGIC; gen_ch_bond_i : in STD_LOGIC; s_axi_tx_tdata : in STD_LOGIC_VECTOR ( 0 to 63 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_TX_STREAM; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_TX_STREAM is signal \^gen_cc_flop_0_i\ : STD_LOGIC; signal tx_stream_control_sm_i_n_4 : STD_LOGIC; begin gen_cc_flop_0_i <= \^gen_cc_flop_0_i\; tx_stream_control_sm_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_TX_STREAM_CONTROL_SM port map ( R0 => R0, do_cc_r => do_cc_r, do_cc_r_reg0 => do_cc_r_reg0, extend_cc_r => extend_cc_r, extend_cc_r_reg_0 => extend_cc_r_reg, gen_cc_flop_0_i_0 => \^gen_cc_flop_0_i\, gen_cc_i => gen_cc_i, gen_ch_bond_i => gen_ch_bond_i, \out\ => \out\, s_axi_tx_tready => s_axi_tx_tready, s_axi_tx_tvalid => s_axi_tx_tvalid, s_axi_tx_tvalid_0 => tx_stream_control_sm_i_n_4, tx_dst_rdy_n_r_reg_0 => tx_dst_rdy_n_r_reg ); tx_stream_datapath_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_TX_STREAM_DATAPATH port map ( Q(61 downto 0) => Q(61 downto 0), \TX_DATA_reg[53]\ => \^gen_cc_flop_0_i\, TX_PE_DATA_V_reg_0 => tx_stream_control_sm_i_n_4, channel_up_tx_if => channel_up_tx_if, gen_na_idles_i => gen_na_idles_i, \out\ => \out\, rst_pma_init_usrclk => rst_pma_init_usrclk, s_axi_tx_tdata(0 to 63) => s_axi_tx_tdata(0 to 63), tx_pe_data_v_i => tx_pe_data_v_i, wait_for_lane_up_r_reg(1 downto 0) => wait_for_lane_up_r_reg(1 downto 0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_common_reset_cbcc is port ( stg5_reg : out STD_LOGIC; SR : out STD_LOGIC_VECTOR ( 0 to 0 ); cbcc_fifo_reset_to_fifo_rd_clk : out STD_LOGIC; cbcc_reset_cbstg2_rd_clk : out STD_LOGIC; cbcc_fifo_reset_rd_clk : out STD_LOGIC; cbcc_fifo_reset_wr_clk : out STD_LOGIC; stg1_aurora_64b66b_0_cdc_to_reg : in STD_LOGIC_VECTOR ( 0 to 0 ); \out\ : in STD_LOGIC; stg2_reg : in STD_LOGIC; cb_bit_err_out : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_common_reset_cbcc; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_common_reset_cbcc is signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal cb_bit_err_ext_cnt : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \cb_bit_err_ext_cnt[0]_i_1_n_0\ : STD_LOGIC; signal \cb_bit_err_ext_cnt[1]_i_1_n_0\ : STD_LOGIC; signal \cb_bit_err_ext_cnt[2]_i_1_n_0\ : STD_LOGIC; signal \cb_bit_err_ext_cnt[3]_i_1_n_0\ : STD_LOGIC; signal cbc_rd_if_reset : STD_LOGIC; signal cbc_wr_if_reset : STD_LOGIC; signal \^cbcc_fifo_reset_to_fifo_rd_clk\ : STD_LOGIC; signal cbcc_fifo_reset_to_fifo_rd_clk_dlyd : STD_LOGIC; signal cbcc_fifo_reset_to_fifo_wr_clk_dlyd : STD_LOGIC; signal \^cbcc_reset_cbstg2_rd_clk\ : STD_LOGIC; signal fifo_reset_comb : STD_LOGIC; signal fifo_reset_comb_read_clk : STD_LOGIC; signal fifo_reset_comb_user_clk : STD_LOGIC; signal fifo_reset_rd : STD_LOGIC; signal rd_stg1 : STD_LOGIC; signal reset_cbcc_comb : STD_LOGIC; signal u_cdc_chan_bond_reset_n_0 : STD_LOGIC; signal u_rst_sync_reset_rd_clk_n_0 : STD_LOGIC; signal u_rst_sync_reset_to_fifo_rd_clk_n_1 : STD_LOGIC; signal u_rst_sync_reset_to_fifo_wr_clk_n_1 : STD_LOGIC; signal u_rst_sync_reset_wr_clk_n_0 : STD_LOGIC; signal u_rst_sync_rst_cbcc_rd_clk_n_0 : STD_LOGIC; signal u_rst_sync_rst_cbcc_rd_clk_n_1 : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \cb_bit_err_ext_cnt[0]_i_1\ : label is "soft_lutpair19"; attribute SOFT_HLUTNM of \cb_bit_err_ext_cnt[1]_i_1\ : label is "soft_lutpair19"; attribute SOFT_HLUTNM of \cb_bit_err_ext_cnt[2]_i_1\ : label is "soft_lutpair18"; attribute SOFT_HLUTNM of \cb_bit_err_ext_cnt[3]_i_1\ : label is "soft_lutpair18"; attribute shift_extract : string; attribute shift_extract of cbc_rd_if_reset_reg : label is "{no}"; attribute shift_extract of cbc_wr_if_reset_reg : label is "{no}"; attribute shift_extract of cbcc_fifo_reset_to_fifo_rd_clk_dlyd_reg : label is "{no}"; attribute shift_extract of cbcc_fifo_reset_to_fifo_wr_clk_dlyd_reg : label is "{no}"; attribute shift_extract of cbcc_reset_cbstg2_rd_clk_reg : label is "{no}"; attribute shift_extract of rd_stg1_reg : label is "{no}"; attribute shift_extract of reset_cbcc_comb_reg : label is "{no}"; begin SR(0) <= \^sr\(0); cbcc_fifo_reset_to_fifo_rd_clk <= \^cbcc_fifo_reset_to_fifo_rd_clk\; cbcc_reset_cbstg2_rd_clk <= \^cbcc_reset_cbstg2_rd_clk\; \cb_bit_err_ext_cnt[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFF5554" ) port map ( I0 => cb_bit_err_ext_cnt(0), I1 => cb_bit_err_ext_cnt(2), I2 => cb_bit_err_ext_cnt(3), I3 => cb_bit_err_ext_cnt(1), I4 => cb_bit_err_out, O => \cb_bit_err_ext_cnt[0]_i_1_n_0\ ); \cb_bit_err_ext_cnt[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFF9998" ) port map ( I0 => cb_bit_err_ext_cnt(0), I1 => cb_bit_err_ext_cnt(1), I2 => cb_bit_err_ext_cnt(2), I3 => cb_bit_err_ext_cnt(3), I4 => cb_bit_err_out, O => \cb_bit_err_ext_cnt[1]_i_1_n_0\ ); \cb_bit_err_ext_cnt[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFE1E0" ) port map ( I0 => cb_bit_err_ext_cnt(1), I1 => cb_bit_err_ext_cnt(0), I2 => cb_bit_err_ext_cnt(2), I3 => cb_bit_err_ext_cnt(3), I4 => cb_bit_err_out, O => \cb_bit_err_ext_cnt[2]_i_1_n_0\ ); \cb_bit_err_ext_cnt[3]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFE00" ) port map ( I0 => cb_bit_err_ext_cnt(0), I1 => cb_bit_err_ext_cnt(1), I2 => cb_bit_err_ext_cnt(2), I3 => cb_bit_err_ext_cnt(3), I4 => cb_bit_err_out, O => \cb_bit_err_ext_cnt[3]_i_1_n_0\ ); \cb_bit_err_ext_cnt_reg[0]\: unisim.vcomponents.FDRE port map ( C => stg2_reg, CE => '1', D => \cb_bit_err_ext_cnt[0]_i_1_n_0\, Q => cb_bit_err_ext_cnt(0), R => stg1_aurora_64b66b_0_cdc_to_reg(0) ); \cb_bit_err_ext_cnt_reg[1]\: unisim.vcomponents.FDRE port map ( C => stg2_reg, CE => '1', D => \cb_bit_err_ext_cnt[1]_i_1_n_0\, Q => cb_bit_err_ext_cnt(1), R => stg1_aurora_64b66b_0_cdc_to_reg(0) ); \cb_bit_err_ext_cnt_reg[2]\: unisim.vcomponents.FDRE port map ( C => stg2_reg, CE => '1', D => \cb_bit_err_ext_cnt[2]_i_1_n_0\, Q => cb_bit_err_ext_cnt(2), R => stg1_aurora_64b66b_0_cdc_to_reg(0) ); \cb_bit_err_ext_cnt_reg[3]\: unisim.vcomponents.FDRE port map ( C => stg2_reg, CE => '1', D => \cb_bit_err_ext_cnt[3]_i_1_n_0\, Q => cb_bit_err_ext_cnt(3), R => stg1_aurora_64b66b_0_cdc_to_reg(0) ); cbc_rd_if_reset_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => u_rst_sync_reset_to_fifo_rd_clk_n_1, Q => cbc_rd_if_reset, R => '0' ); cbc_wr_if_reset_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg2_reg, CE => '1', D => u_rst_sync_reset_to_fifo_wr_clk_n_1, Q => cbc_wr_if_reset, R => '0' ); cbcc_fifo_reset_rd_clk_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => u_rst_sync_reset_rd_clk_n_0, Q => cbcc_fifo_reset_rd_clk, R => '0' ); cbcc_fifo_reset_to_fifo_rd_clk_dlyd_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => \^cbcc_fifo_reset_to_fifo_rd_clk\, Q => cbcc_fifo_reset_to_fifo_rd_clk_dlyd, R => '0' ); cbcc_fifo_reset_to_fifo_wr_clk_dlyd_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg2_reg, CE => '1', D => \^sr\(0), Q => cbcc_fifo_reset_to_fifo_wr_clk_dlyd, R => '0' ); cbcc_fifo_reset_wr_clk_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg2_reg, CE => '1', D => u_rst_sync_reset_wr_clk_n_0, Q => cbcc_fifo_reset_wr_clk, R => '0' ); cbcc_reset_cbstg2_rd_clk_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => u_rst_sync_rst_cbcc_rd_clk_n_1, Q => \^cbcc_reset_cbstg2_rd_clk\, R => '0' ); fifo_reset_rd_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => '0', Q => fifo_reset_rd, S => \^cbcc_reset_cbstg2_rd_clk\ ); rd_stg1_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => \out\, CE => '1', D => u_rst_sync_rst_cbcc_rd_clk_n_0, Q => rd_stg1, R => '0' ); reset_cbcc_comb_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg2_reg, CE => '1', D => u_cdc_chan_bond_reset_n_0, Q => reset_cbcc_comb, R => '0' ); u_cdc_chan_bond_reset: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized1_26\ port map ( Q(3 downto 0) => cb_bit_err_ext_cnt(3 downto 0), \cb_bit_err_ext_cnt_reg[3]\ => u_cdc_chan_bond_reset_n_0, reset_cbcc_comb_reg(0) => stg1_aurora_64b66b_0_cdc_to_reg(0), s_level_out_d5_reg_0 => stg2_reg ); u_rst_sync_cbcc_fifo_reset_rd_clk: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_27\ port map ( in0 => fifo_reset_comb_user_clk, \out\ => \out\, stg5_reg_0 => fifo_reset_comb_read_clk ); u_rst_sync_cbcc_only_reset_rd_clk: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_28\ port map ( \out\ => \out\, stg1_aurora_64b66b_0_cdc_to_reg_0(0) => stg1_aurora_64b66b_0_cdc_to_reg(0), stg5_reg_0 => stg5_reg ); u_rst_sync_fifo_reset_user_clk: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized2\ port map ( in0 => fifo_reset_comb, stg11_reg_0 => fifo_reset_comb_user_clk, stg11_reg_1 => stg2_reg ); u_rst_sync_r_sync3: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_29\ port map ( in0 => fifo_reset_rd, stg1_aurora_64b66b_0_cdc_to_reg_0 => reset_cbcc_comb, stg5_reg_0 => fifo_reset_comb, stg5_reg_1 => stg2_reg ); u_rst_sync_reset_rd_clk: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_30\ port map ( in0 => cbc_rd_if_reset, \out\ => \out\, stg3_reg_0 => u_rst_sync_reset_rd_clk_n_0 ); u_rst_sync_reset_to_fifo_rd_clk: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized3\ port map ( cbcc_fifo_reset_to_fifo_rd_clk => \^cbcc_fifo_reset_to_fifo_rd_clk\, cbcc_fifo_reset_to_fifo_rd_clk_dlyd => cbcc_fifo_reset_to_fifo_rd_clk_dlyd, cbcc_fifo_reset_to_fifo_rd_clk_dlyd_reg => u_rst_sync_reset_to_fifo_rd_clk_n_1, in0 => cbc_rd_if_reset, \out\ => \out\, stg1_aurora_64b66b_0_cdc_to_reg_0 => fifo_reset_comb_read_clk ); u_rst_sync_reset_to_fifo_wr_clk: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized3_31\ port map ( SR(0) => \^sr\(0), cbcc_fifo_reset_to_fifo_wr_clk_dlyd => cbcc_fifo_reset_to_fifo_wr_clk_dlyd, cbcc_fifo_reset_to_fifo_wr_clk_dlyd_reg => u_rst_sync_reset_to_fifo_wr_clk_n_1, in0 => cbc_wr_if_reset, stg1_aurora_64b66b_0_cdc_to_reg_0 => fifo_reset_comb_user_clk, stg31_reg_0 => stg2_reg ); u_rst_sync_reset_wr_clk: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_32\ port map ( in0 => cbc_wr_if_reset, stg2_reg_0 => stg2_reg, stg3_reg_0 => u_rst_sync_reset_wr_clk_n_0 ); u_rst_sync_rst_cbcc_rd_clk: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_33\ port map ( \out\ => \out\, rd_stg1 => rd_stg1, rd_stg1_reg => u_rst_sync_rst_cbcc_rd_clk_n_1, stg1_aurora_64b66b_0_cdc_to_reg_0 => reset_cbcc_comb, stg5_reg_0 => u_rst_sync_rst_cbcc_rd_clk_n_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_AURORA_LANE is port ( lane_up_flop_i : out STD_LOGIC; tx_reset_i : out STD_LOGIC; enable_err_detect_i : out STD_LOGIC; rst_pma_init_usrclk : out STD_LOGIC; rx_pe_data_v_i : out STD_LOGIC; illegal_btf_i : out STD_LOGIC; RX_IDLE : out STD_LOGIC; rx_polarity_r_reg : out STD_LOGIC; check_polarity_r_reg : out STD_LOGIC; hard_err_i : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 1 downto 0 ); remote_ready_i : out STD_LOGIC; SOFT_ERR_reg : out STD_LOGIC; reset_lanes_c : out STD_LOGIC; tempData : out STD_LOGIC_VECTOR ( 5 downto 0 ); \TX_DATA_reg[63]\ : out STD_LOGIC_VECTOR ( 57 downto 0 ); \RX_PE_DATA_reg[0]\ : out STD_LOGIC_VECTOR ( 63 downto 0 ); s_level_out_d1_aurora_64b66b_0_cdc_to_reg : in STD_LOGIC; \out\ : in STD_LOGIC; SR : in STD_LOGIC_VECTOR ( 0 to 0 ); stg1_aurora_64b66b_0_cdc_to_reg : in STD_LOGIC; reset_count_r0 : in STD_LOGIC; ready_r_reg0 : in STD_LOGIC; rxdatavalid_i : in STD_LOGIC; SOFT_ERR_reg_0 : in STD_LOGIC; \RX_DATA_REG_reg[0]\ : in STD_LOGIC; RX_HEADER_1_REG_reg : in STD_LOGIC_VECTOR ( 65 downto 0 ); HARD_ERR_reg : in STD_LOGIC; txdatavalid_symgen_i : in STD_LOGIC; gen_na_idles_i : in STD_LOGIC; tx_pe_data_v_i : in STD_LOGIC; TX_HEADER_1_reg : in STD_LOGIC; channel_up_tx_if : in STD_LOGIC; rx_lossofsync_i : in STD_LOGIC; reset_lanes_i : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 59 downto 0 ); scrambler : in STD_LOGIC_VECTOR ( 11 downto 0 ); \TX_DATA_reg[59]\ : in STD_LOGIC; \TX_DATA_reg[55]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); \TX_DATA_reg[63]_0\ : in STD_LOGIC; gen_ch_bond_i : in STD_LOGIC; gen_cc_i : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_AURORA_LANE; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_AURORA_LANE is signal \^lane_up_flop_i\ : STD_LOGIC; begin lane_up_flop_i <= \^lane_up_flop_i\; err_detect_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_ERR_DETECT port map ( HARD_ERR_reg_0 => HARD_ERR_reg, SOFT_ERR_reg_0 => SOFT_ERR_reg, SOFT_ERR_reg_1 => SOFT_ERR_reg_0, channel_up_tx_if => channel_up_tx_if, hard_err_i => hard_err_i, \out\ => \out\ ); lane_init_sm_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_LANE_INIT_SM port map ( SR(0) => SR(0), check_polarity_r_reg_0 => check_polarity_r_reg, enable_err_detect_i => enable_err_detect_i, gen_na_idles_i => gen_na_idles_i, lane_up_flop_i_0 => \^lane_up_flop_i\, \out\ => \out\, ready_r_reg0 => ready_r_reg0, reset_count_r0 => reset_count_r0, reset_lanes_c => reset_lanes_c, reset_lanes_i => reset_lanes_i, rst_r_reg_0 => tx_reset_i, rx_lossofsync_i => rx_lossofsync_i, rx_polarity_r_reg_0 => rx_polarity_r_reg, s_level_out_d1_aurora_64b66b_0_cdc_to_reg => s_level_out_d1_aurora_64b66b_0_cdc_to_reg ); sym_dec_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_SYM_DEC port map ( \RX_DATA_REG_reg[0]_0\ => \RX_DATA_REG_reg[0]\, RX_HEADER_1_REG_reg_0(65 downto 0) => RX_HEADER_1_REG_reg(65 downto 0), RX_IDLE => RX_IDLE, \RX_PE_DATA_reg[0]_0\(63 downto 0) => \RX_PE_DATA_reg[0]\(63 downto 0), SR(0) => SR(0), illegal_btf_i => illegal_btf_i, \out\ => \out\, remote_ready_i => remote_ready_i, \rx_na_idles_cntr_reg[0]_0\ => \^lane_up_flop_i\, rx_pe_data_v_i => rx_pe_data_v_i, rxdatavalid_i => rxdatavalid_i ); sym_gen_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_SYM_GEN port map ( D(1 downto 0) => D(1 downto 0), Q(59 downto 0) => Q(59 downto 0), \TX_DATA_reg[55]_0\(3 downto 0) => \TX_DATA_reg[55]\(3 downto 0), \TX_DATA_reg[59]_0\ => \TX_DATA_reg[59]\, \TX_DATA_reg[63]_0\(57 downto 0) => \TX_DATA_reg[63]\(57 downto 0), \TX_DATA_reg[63]_1\ => \TX_DATA_reg[63]_0\, TX_HEADER_1_reg_0 => TX_HEADER_1_reg, channel_up_tx_if => channel_up_tx_if, gen_cc_i => gen_cc_i, gen_ch_bond_i => gen_ch_bond_i, gen_na_idles_i => gen_na_idles_i, \out\ => \out\, scrambler(11 downto 0) => scrambler(11 downto 0), stg1_aurora_64b66b_0_cdc_to_reg => stg1_aurora_64b66b_0_cdc_to_reg, stg5_reg => rst_pma_init_usrclk, tempData(5 downto 0) => tempData(5 downto 0), tx_pe_data_v_i => tx_pe_data_v_i, txdatavalid_symgen_i => txdatavalid_symgen_i ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_WRAPPER is port ( FSM_RESETDONE_reg_0 : out STD_LOGIC; drprdy_out : out STD_LOGIC; txn : out STD_LOGIC; txp : out STD_LOGIC; tx_out_clk : out STD_LOGIC; drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); master_do_rd_en_out_reg : out STD_LOGIC_VECTOR ( 65 downto 0 ); link_reset_out : out STD_LOGIC; rx_lossofsync_i : out STD_LOGIC; RX_NEG_OUT_reg_0 : out STD_LOGIC; hold_reg_reg : out STD_LOGIC; \txseq_counter_i_reg[0]_0\ : out STD_LOGIC; TXDATAVALID_IN : out STD_LOGIC; \txseq_counter_i_reg[1]_0\ : out STD_LOGIC; txdatavalid_symgen_i : out STD_LOGIC; ILLEGAL_BTF_reg : out STD_LOGIC; rxdatavalid_i : out STD_LOGIC; wr_err_rd_clk_sync_reg : out STD_LOGIC; scrambler : out STD_LOGIC_VECTOR ( 11 downto 0 ); MMCM_RESET_reg : out STD_LOGIC; gt_pll_lock : out STD_LOGIC; in0 : in STD_LOGIC; SR : in STD_LOGIC_VECTOR ( 0 to 0 ); stg4_reg : in STD_LOGIC; drp_clk_in : in STD_LOGIC; drpen_in : in STD_LOGIC; drpwe_in : in STD_LOGIC; refclk1_in : in STD_LOGIC; rxn : in STD_LOGIC; rxp : in STD_LOGIC; gt_qpllclk_quad1_out : in STD_LOGIC; gt_qpllrefclk_quad1_out : in STD_LOGIC; gt_rxcdrovrden_in : in STD_LOGIC; stg4_reg_0 : in STD_LOGIC; \out\ : in STD_LOGIC; drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); loopback : in STD_LOGIC_VECTOR ( 2 downto 0 ); drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 ); s_level_out_d1_aurora_64b66b_0_cdc_to_reg : in STD_LOGIC; s_level_out_d1_aurora_64b66b_0_cdc_to_reg_0 : in STD_LOGIC; tx_reset_i : in STD_LOGIC; \init_wait_count_reg[7]\ : in STD_LOGIC; extend_cc_r : in STD_LOGIC; Q : in STD_LOGIC; rst_pma_init_usrclk : in STD_LOGIC; illegal_btf_i : in STD_LOGIC; enable_err_detect_i : in STD_LOGIC; hard_err_usr_reg_0 : in STD_LOGIC; channel_up_tx_if : in STD_LOGIC; tx_data_i : in STD_LOGIC_VECTOR ( 57 downto 0 ); D : in STD_LOGIC_VECTOR ( 1 downto 0 ); tempData : in STD_LOGIC_VECTOR ( 5 downto 0 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_WRAPPER; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_WRAPPER is signal ANY_VLD_BTF_FLAG : STD_LOGIC; signal CB_detect : STD_LOGIC; signal CB_detect0 : STD_LOGIC; signal CB_detect_dlyd0p5 : STD_LOGIC; signal CC_detect : STD_LOGIC; signal CC_detect_dlyd1 : STD_LOGIC; signal CC_detect_pulse_i : STD_LOGIC; signal FSM_RESETDONE0 : STD_LOGIC; signal \^fsm_resetdone_reg_0\ : STD_LOGIC; signal \FSM_onehot_cdr_reset_fsm_r[2]_i_2_n_0\ : STD_LOGIC; signal \FSM_onehot_cdr_reset_fsm_r_reg_n_0_[0]\ : STD_LOGIC; signal HPCNT_RESET_IN : STD_LOGIC; signal LINK_RESET_OUT0 : STD_LOGIC; signal \^rx_neg_out_reg_0\ : STD_LOGIC; signal START_CB_WRITES_OUT : STD_LOGIC; signal \TX_DATA[55]_i_3_n_0\ : STD_LOGIC; signal all_start_cb_writes_i : STD_LOGIC; attribute RTL_KEEP : string; attribute RTL_KEEP of all_start_cb_writes_i : signal is "true"; signal all_vld_btf_flag_i : STD_LOGIC; attribute RTL_KEEP of all_vld_btf_flag_i : signal is "true"; signal allow_block_sync_propagation : STD_LOGIC; signal allow_block_sync_propagation_reg_n_0 : STD_LOGIC; signal \aurora_64b66b_0_gtx_inst/ack_flag\ : STD_LOGIC; signal bit_err_chan_bond_i : STD_LOGIC; attribute RTL_KEEP of bit_err_chan_bond_i : signal is "true"; signal blocksync_all_lanes_inrxclk_q : STD_LOGIC; signal blocksync_out_i : STD_LOGIC; signal cb_bit_err_out : STD_LOGIC; signal cbcc_fifo_reset_rd_clk : STD_LOGIC; signal cbcc_fifo_reset_to_fifo_rd_clk : STD_LOGIC; signal cbcc_fifo_reset_to_fifo_wr_clk : STD_LOGIC; signal cbcc_fifo_reset_wr_clk : STD_LOGIC; signal cbcc_gtx0_i_n_74 : STD_LOGIC; signal cbcc_gtx0_i_n_76 : STD_LOGIC; signal cbcc_reset_cbstg2_rd_clk : STD_LOGIC; signal cdr_reset_fsm_cntr_r : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \cdr_reset_fsm_cntr_r[0]_i_1_n_0\ : STD_LOGIC; signal \cdr_reset_fsm_cntr_r[1]_i_1_n_0\ : STD_LOGIC; signal \cdr_reset_fsm_cntr_r[2]_i_1_n_0\ : STD_LOGIC; signal \cdr_reset_fsm_cntr_r[3]_i_1_n_0\ : STD_LOGIC; signal \cdr_reset_fsm_cntr_r[4]_i_1_n_0\ : STD_LOGIC; signal \cdr_reset_fsm_cntr_r[5]_i_1_n_0\ : STD_LOGIC; signal \cdr_reset_fsm_cntr_r[6]_i_1_n_0\ : STD_LOGIC; signal \cdr_reset_fsm_cntr_r[7]_i_2_n_0\ : STD_LOGIC; signal \cdr_reset_fsm_cntr_r[7]_i_3_n_0\ : STD_LOGIC; signal \cdr_reset_fsm_cntr_r[7]_i_4_n_0\ : STD_LOGIC; signal \cdr_reset_fsm_cntr_r[7]_i_5_n_0\ : STD_LOGIC; signal cdr_reset_fsm_lnkreset : STD_LOGIC; signal cdr_reset_fsm_lnkreset_reg_n_0 : STD_LOGIC; signal common_reset_cbcc_i_n_0 : STD_LOGIC; signal descrambler_64b66b_gtx0_i_n_36 : STD_LOGIC; signal do_rd_en_i : STD_LOGIC; attribute RTL_KEEP of do_rd_en_i : signal is "true"; signal final_gater_for_fifo_din_i : STD_LOGIC; attribute RTL_KEEP of final_gater_for_fifo_din_i : signal is "true"; signal fsm_resetdone_to_new_gtx_rx_comb : STD_LOGIC; signal gt_cplllock_ii : STD_LOGIC; signal gt_cpllreset_i : STD_LOGIC; signal gtpll_locked_out_i : STD_LOGIC; signal gtrxreset_t : STD_LOGIC; signal gttxreset_t : STD_LOGIC; signal gtx_reset_comb : STD_LOGIC; signal hard_err_cntr_r : STD_LOGIC; signal \hard_err_cntr_r[7]_i_5_n_0\ : STD_LOGIC; signal \hard_err_cntr_r[7]_i_6_n_0\ : STD_LOGIC; signal \hard_err_cntr_r_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal hard_err_rst_int : STD_LOGIC; signal hard_err_rst_int_i_2_n_0 : STD_LOGIC; signal hard_err_rst_int_i_3_n_0 : STD_LOGIC; signal hard_err_rst_int_i_4_n_0 : STD_LOGIC; signal hard_err_usr : STD_LOGIC; signal hard_err_usr0 : STD_LOGIC; signal int_rxbufstatus_i : STD_LOGIC_VECTOR ( 2 to 2 ); signal master_do_rd_en_i : STD_LOGIC; attribute RTL_KEEP of master_do_rd_en_i : signal is "true"; signal mmcm_reset_i : STD_LOGIC; signal new_gtx_rx_pcsreset_comb : STD_LOGIC; signal new_gtx_rx_pcsreset_comb0 : STD_LOGIC; signal \p_0_in__4\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal p_2_in : STD_LOGIC; signal poly : STD_LOGIC_VECTOR ( 52 to 52 ); signal pos_rxdata_from_gtx_i : STD_LOGIC_VECTOR ( 31 downto 0 ); signal pos_rxdatavalid_i : STD_LOGIC; signal pos_rxheader_from_gtx_i : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \pos_rxheader_from_gtx_i[0]_i_1_n_0\ : STD_LOGIC; signal \pos_rxheader_from_gtx_i[1]_i_1_n_0\ : STD_LOGIC; signal pos_rxheadervalid_i : STD_LOGIC; signal pre_r3_rxdatavalid_i_reg_srl3_n_0 : STD_LOGIC; signal \pre_r3_rxheader_from_gtx_i_reg[0]_srl3_n_0\ : STD_LOGIC; signal \pre_r3_rxheader_from_gtx_i_reg[1]_srl3_n_0\ : STD_LOGIC; signal pre_r3_rxheadervalid_i_reg_srl3_n_0 : STD_LOGIC; signal pre_r4_rxdata_from_gtx_i : STD_LOGIC_VECTOR ( 31 downto 0 ); signal pre_r4_rxdatavalid_i : STD_LOGIC; signal pre_r4_rxheader_from_gtx_i : STD_LOGIC_VECTOR ( 1 downto 0 ); signal pre_r4_rxheadervalid_i : STD_LOGIC; signal pre_rxdata_from_gtx_i : STD_LOGIC_VECTOR ( 31 downto 0 ); signal pre_rxdatavalid_i : STD_LOGIC; signal pre_rxheader_from_gtx_i : STD_LOGIC_VECTOR ( 1 downto 0 ); signal pre_rxheadervalid_i : STD_LOGIC; signal reset_initclk : STD_LOGIC; signal rx_clk_locked_i : STD_LOGIC; attribute RTL_KEEP of rx_clk_locked_i : signal is "true"; signal rx_elastic_buf_err : STD_LOGIC; signal rx_fsm_resetdone_i : STD_LOGIC; attribute RTL_KEEP of rx_fsm_resetdone_i : signal is "true"; signal rx_resetdone_i : STD_LOGIC; signal rxdata_from_gtx_i : STD_LOGIC_VECTOR ( 31 downto 0 ); signal rxdata_to_fifo_i : STD_LOGIC_VECTOR ( 31 downto 0 ); signal rxdatavalid_i_0 : STD_LOGIC; signal rxdatavalid_to_fifo_i : STD_LOGIC; signal rxfsm_reset_i : STD_LOGIC; attribute RTL_KEEP of rxfsm_reset_i : signal is "true"; signal rxgearboxslip_i : STD_LOGIC; signal rxheader_from_gtx_i : STD_LOGIC_VECTOR ( 1 downto 0 ); signal rxheader_to_fifo_i : STD_LOGIC_VECTOR ( 1 downto 0 ); signal rxheadervalid_i : STD_LOGIC; signal rxlossofsync_out_i : STD_LOGIC; signal rxlossofsync_out_q : STD_LOGIC; signal rxrecclk_from_gtx_i : STD_LOGIC; signal rxrecclk_to_fabric_i : STD_LOGIC; attribute RTL_KEEP of rxrecclk_to_fabric_i : signal is "true"; signal rxreset_for_lanes_q : STD_LOGIC; signal rxuserrdy_t : STD_LOGIC; signal scrambled_data_i : STD_LOGIC_VECTOR ( 63 downto 0 ); signal scrambler_64b66b_gtx0_i_n_0 : STD_LOGIC; signal stableclk_gtx_reset_comb : STD_LOGIC; signal sync_rx_polarity_r : STD_LOGIC; signal tx_buf_err_i : STD_LOGIC; signal tx_fsm_resetdone_i : STD_LOGIC; attribute RTL_KEEP of tx_fsm_resetdone_i : signal is "true"; signal tx_hdr_r : STD_LOGIC_VECTOR ( 1 downto 0 ); signal tx_resetdone_i : STD_LOGIC; signal txresetfsm_i_n_6 : STD_LOGIC; signal txseq_counter_i : STD_LOGIC_VECTOR ( 6 downto 0 ); signal \txseq_counter_i[0]_i_2_n_0\ : STD_LOGIC; signal \txseq_counter_i[5]_i_2_n_0\ : STD_LOGIC; signal \txseq_counter_i[5]_i_3_n_0\ : STD_LOGIC; signal \txseq_counter_i_reg_n_0_[0]\ : STD_LOGIC; signal \txseq_counter_i_reg_n_0_[1]\ : STD_LOGIC; signal \txseq_counter_i_reg_n_0_[2]\ : STD_LOGIC; signal \txseq_counter_i_reg_n_0_[3]\ : STD_LOGIC; signal \txseq_counter_i_reg_n_0_[4]\ : STD_LOGIC; signal \txseq_counter_i_reg_n_0_[5]\ : STD_LOGIC; signal \txseq_counter_i_reg_n_0_[6]\ : STD_LOGIC; signal txuserrdy_t : STD_LOGIC; signal txusrclk_gtx_reset_comb : STD_LOGIC; signal \u_cdc__check_polarity_n_0\ : STD_LOGIC; signal u_cdc_hard_err_init_n_0 : STD_LOGIC; signal u_rst_sync_blocksyncall_initclk_sync_n_0 : STD_LOGIC; signal u_rst_sync_blocksyncall_initclk_sync_n_1 : STD_LOGIC; signal u_rst_sync_blocksyncall_initclk_sync_n_2 : STD_LOGIC; signal unscrambled_data_i052_out : STD_LOGIC; attribute FSM_ENCODED_STATES : string; attribute FSM_ENCODED_STATES of \FSM_onehot_cdr_reset_fsm_r_reg[0]\ : label is "IDLE:001,ASSERT_RXRESET:010,DONE:100,"; attribute FSM_ENCODED_STATES of \FSM_onehot_cdr_reset_fsm_r_reg[1]\ : label is "IDLE:001,ASSERT_RXRESET:010,DONE:100,"; attribute FSM_ENCODED_STATES of \FSM_onehot_cdr_reset_fsm_r_reg[2]\ : label is "IDLE:001,ASSERT_RXRESET:010,DONE:100,"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \TX_DATA[55]_i_1\ : label is "soft_lutpair70"; attribute SOFT_HLUTNM of \TX_DATA[55]_i_3\ : label is "soft_lutpair76"; attribute SOFT_HLUTNM of TX_HEADER_0_i_2 : label is "soft_lutpair79"; attribute SOFT_HLUTNM of \cdr_reset_fsm_cntr_r[1]_i_1\ : label is "soft_lutpair75"; attribute SOFT_HLUTNM of \cdr_reset_fsm_cntr_r[2]_i_1\ : label is "soft_lutpair74"; attribute SOFT_HLUTNM of \cdr_reset_fsm_cntr_r[3]_i_1\ : label is "soft_lutpair74"; attribute SOFT_HLUTNM of \cdr_reset_fsm_cntr_r[5]_i_1\ : label is "soft_lutpair71"; attribute SOFT_HLUTNM of \cdr_reset_fsm_cntr_r[6]_i_1\ : label is "soft_lutpair71"; attribute SOFT_HLUTNM of \cdr_reset_fsm_cntr_r[7]_i_5\ : label is "soft_lutpair75"; attribute SOFT_HLUTNM of data_v_r_i_1 : label is "soft_lutpair70"; attribute SOFT_HLUTNM of \hard_err_cntr_r[0]_i_1\ : label is "soft_lutpair83"; attribute SOFT_HLUTNM of \hard_err_cntr_r[1]_i_1\ : label is "soft_lutpair83"; attribute SOFT_HLUTNM of \hard_err_cntr_r[2]_i_1\ : label is "soft_lutpair81"; attribute SOFT_HLUTNM of \hard_err_cntr_r[3]_i_1\ : label is "soft_lutpair78"; attribute SOFT_HLUTNM of \hard_err_cntr_r[4]_i_1\ : label is "soft_lutpair73"; attribute SOFT_HLUTNM of \hard_err_cntr_r[6]_i_1\ : label is "soft_lutpair77"; attribute SOFT_HLUTNM of \hard_err_cntr_r[7]_i_3\ : label is "soft_lutpair77"; attribute SOFT_HLUTNM of \hard_err_cntr_r[7]_i_5\ : label is "soft_lutpair78"; attribute SOFT_HLUTNM of \hard_err_cntr_r[7]_i_6\ : label is "soft_lutpair73"; attribute SOFT_HLUTNM of hard_err_rst_int_i_2 : label is "soft_lutpair81"; attribute shift_extract : string; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[0]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[10]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[11]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[12]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[13]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[14]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[15]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[16]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[17]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[18]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[19]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[1]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[20]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[21]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[22]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[23]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[24]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[25]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[26]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[27]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[28]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[29]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[2]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[30]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[31]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[3]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[4]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[5]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[6]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[7]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[8]\ : label is "{no}"; attribute shift_extract of \pos_rxdata_from_gtx_i_reg[9]\ : label is "{no}"; attribute shift_extract of pos_rxdatavalid_i_reg : label is "{no}"; attribute SOFT_HLUTNM of \pos_rxheader_from_gtx_i[0]_i_1\ : label is "soft_lutpair80"; attribute SOFT_HLUTNM of \pos_rxheader_from_gtx_i[1]_i_1\ : label is "soft_lutpair80"; attribute shift_extract of \pos_rxheader_from_gtx_i_reg[0]\ : label is "{no}"; attribute shift_extract of \pos_rxheader_from_gtx_i_reg[1]\ : label is "{no}"; attribute shift_extract of pos_rxheadervalid_i_reg : label is "{no}"; attribute srl_name : string; attribute srl_name of pre_r3_rxdatavalid_i_reg_srl3 : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r3_rxdatavalid_i_reg_srl3 "; attribute srl_bus_name : string; attribute srl_bus_name of \pre_r3_rxheader_from_gtx_i_reg[0]_srl3\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r3_rxheader_from_gtx_i_reg "; attribute srl_name of \pre_r3_rxheader_from_gtx_i_reg[0]_srl3\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r3_rxheader_from_gtx_i_reg[0]_srl3 "; attribute srl_bus_name of \pre_r3_rxheader_from_gtx_i_reg[1]_srl3\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r3_rxheader_from_gtx_i_reg "; attribute srl_name of \pre_r3_rxheader_from_gtx_i_reg[1]_srl3\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r3_rxheader_from_gtx_i_reg[1]_srl3 "; attribute srl_name of pre_r3_rxheadervalid_i_reg_srl3 : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r3_rxheadervalid_i_reg_srl3 "; attribute srl_bus_name of \pre_r4_rxdata_from_gtx_i_reg[0]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg "; attribute srl_name of \pre_r4_rxdata_from_gtx_i_reg[0]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg[0]_srl4 "; attribute srl_bus_name of \pre_r4_rxdata_from_gtx_i_reg[10]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg "; attribute srl_name of \pre_r4_rxdata_from_gtx_i_reg[10]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg[10]_srl4 "; attribute srl_bus_name of \pre_r4_rxdata_from_gtx_i_reg[11]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg "; attribute srl_name of \pre_r4_rxdata_from_gtx_i_reg[11]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg[11]_srl4 "; attribute srl_bus_name of \pre_r4_rxdata_from_gtx_i_reg[12]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg "; attribute srl_name of \pre_r4_rxdata_from_gtx_i_reg[12]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg[12]_srl4 "; attribute srl_bus_name of \pre_r4_rxdata_from_gtx_i_reg[13]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg "; attribute srl_name of \pre_r4_rxdata_from_gtx_i_reg[13]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg[13]_srl4 "; attribute srl_bus_name of \pre_r4_rxdata_from_gtx_i_reg[14]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg "; attribute srl_name of \pre_r4_rxdata_from_gtx_i_reg[14]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg[14]_srl4 "; attribute srl_bus_name of \pre_r4_rxdata_from_gtx_i_reg[15]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg "; attribute srl_name of \pre_r4_rxdata_from_gtx_i_reg[15]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg[15]_srl4 "; attribute srl_bus_name of \pre_r4_rxdata_from_gtx_i_reg[16]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg "; attribute srl_name of \pre_r4_rxdata_from_gtx_i_reg[16]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg[16]_srl4 "; attribute srl_bus_name of \pre_r4_rxdata_from_gtx_i_reg[17]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg "; attribute srl_name of \pre_r4_rxdata_from_gtx_i_reg[17]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg[17]_srl4 "; attribute srl_bus_name of \pre_r4_rxdata_from_gtx_i_reg[18]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg "; attribute srl_name of \pre_r4_rxdata_from_gtx_i_reg[18]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg[18]_srl4 "; attribute srl_bus_name of \pre_r4_rxdata_from_gtx_i_reg[19]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg "; attribute srl_name of \pre_r4_rxdata_from_gtx_i_reg[19]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg[19]_srl4 "; attribute srl_bus_name of \pre_r4_rxdata_from_gtx_i_reg[1]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg "; attribute srl_name of \pre_r4_rxdata_from_gtx_i_reg[1]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg[1]_srl4 "; attribute srl_bus_name of \pre_r4_rxdata_from_gtx_i_reg[20]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg "; attribute srl_name of \pre_r4_rxdata_from_gtx_i_reg[20]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg[20]_srl4 "; attribute srl_bus_name of \pre_r4_rxdata_from_gtx_i_reg[21]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg "; attribute srl_name of \pre_r4_rxdata_from_gtx_i_reg[21]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg[21]_srl4 "; attribute srl_bus_name of \pre_r4_rxdata_from_gtx_i_reg[22]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg "; attribute srl_name of \pre_r4_rxdata_from_gtx_i_reg[22]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg[22]_srl4 "; attribute srl_bus_name of \pre_r4_rxdata_from_gtx_i_reg[23]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg "; attribute srl_name of \pre_r4_rxdata_from_gtx_i_reg[23]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg[23]_srl4 "; attribute srl_bus_name of \pre_r4_rxdata_from_gtx_i_reg[24]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg "; attribute srl_name of \pre_r4_rxdata_from_gtx_i_reg[24]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg[24]_srl4 "; attribute srl_bus_name of \pre_r4_rxdata_from_gtx_i_reg[25]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg "; attribute srl_name of \pre_r4_rxdata_from_gtx_i_reg[25]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg[25]_srl4 "; attribute srl_bus_name of \pre_r4_rxdata_from_gtx_i_reg[26]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg "; attribute srl_name of \pre_r4_rxdata_from_gtx_i_reg[26]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg[26]_srl4 "; attribute srl_bus_name of \pre_r4_rxdata_from_gtx_i_reg[27]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg "; attribute srl_name of \pre_r4_rxdata_from_gtx_i_reg[27]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg[27]_srl4 "; attribute srl_bus_name of \pre_r4_rxdata_from_gtx_i_reg[28]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg "; attribute srl_name of \pre_r4_rxdata_from_gtx_i_reg[28]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg[28]_srl4 "; attribute srl_bus_name of \pre_r4_rxdata_from_gtx_i_reg[29]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg "; attribute srl_name of \pre_r4_rxdata_from_gtx_i_reg[29]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg[29]_srl4 "; attribute srl_bus_name of \pre_r4_rxdata_from_gtx_i_reg[2]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg "; attribute srl_name of \pre_r4_rxdata_from_gtx_i_reg[2]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg[2]_srl4 "; attribute srl_bus_name of \pre_r4_rxdata_from_gtx_i_reg[30]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg "; attribute srl_name of \pre_r4_rxdata_from_gtx_i_reg[30]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg[30]_srl4 "; attribute srl_bus_name of \pre_r4_rxdata_from_gtx_i_reg[31]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg "; attribute srl_name of \pre_r4_rxdata_from_gtx_i_reg[31]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg[31]_srl4 "; attribute srl_bus_name of \pre_r4_rxdata_from_gtx_i_reg[3]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg "; attribute srl_name of \pre_r4_rxdata_from_gtx_i_reg[3]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg[3]_srl4 "; attribute srl_bus_name of \pre_r4_rxdata_from_gtx_i_reg[4]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg "; attribute srl_name of \pre_r4_rxdata_from_gtx_i_reg[4]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg[4]_srl4 "; attribute srl_bus_name of \pre_r4_rxdata_from_gtx_i_reg[5]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg "; attribute srl_name of \pre_r4_rxdata_from_gtx_i_reg[5]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg[5]_srl4 "; attribute srl_bus_name of \pre_r4_rxdata_from_gtx_i_reg[6]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg "; attribute srl_name of \pre_r4_rxdata_from_gtx_i_reg[6]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg[6]_srl4 "; attribute srl_bus_name of \pre_r4_rxdata_from_gtx_i_reg[7]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg "; attribute srl_name of \pre_r4_rxdata_from_gtx_i_reg[7]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg[7]_srl4 "; attribute srl_bus_name of \pre_r4_rxdata_from_gtx_i_reg[8]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg "; attribute srl_name of \pre_r4_rxdata_from_gtx_i_reg[8]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg[8]_srl4 "; attribute srl_bus_name of \pre_r4_rxdata_from_gtx_i_reg[9]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg "; attribute srl_name of \pre_r4_rxdata_from_gtx_i_reg[9]_srl4\ : label is "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/pre_r4_rxdata_from_gtx_i_reg[9]_srl4 "; attribute shift_extract of pre_r4_rxdatavalid_i_reg : label is "{no}"; attribute shift_extract of \pre_r4_rxheader_from_gtx_i_reg[0]\ : label is "{no}"; attribute shift_extract of \pre_r4_rxheader_from_gtx_i_reg[1]\ : label is "{no}"; attribute shift_extract of pre_r4_rxheadervalid_i_reg : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[0]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[10]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[11]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[12]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[13]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[14]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[15]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[16]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[17]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[18]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[19]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[1]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[20]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[21]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[22]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[23]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[24]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[25]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[26]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[27]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[28]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[29]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[2]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[30]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[31]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[3]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[4]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[5]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[6]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[7]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[8]\ : label is "{no}"; attribute shift_extract of \rxdata_from_gtx_i_reg[9]\ : label is "{no}"; attribute shift_extract of rxdatavalid_i_reg : label is "{no}"; attribute shift_extract of \rxheader_from_gtx_i_reg[0]\ : label is "{no}"; attribute shift_extract of \rxheader_from_gtx_i_reg[1]\ : label is "{no}"; attribute shift_extract of rxheadervalid_i_reg : label is "{no}"; attribute BOX_TYPE : string; attribute BOX_TYPE of rxrecclk_bufg_i : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of rxrecclk_bufg_i : label is "BUFGCE"; attribute XILINX_TRANSFORM_PINMAP : string; attribute XILINX_TRANSFORM_PINMAP of rxrecclk_bufg_i : label is "CE:CE0 I:I0"; attribute SOFT_HLUTNM of \txseq_counter_i[0]_i_2\ : label is "soft_lutpair82"; attribute SOFT_HLUTNM of \txseq_counter_i[1]_i_1\ : label is "soft_lutpair82"; attribute SOFT_HLUTNM of \txseq_counter_i[2]_i_1\ : label is "soft_lutpair79"; attribute SOFT_HLUTNM of \txseq_counter_i[3]_i_1\ : label is "soft_lutpair72"; attribute SOFT_HLUTNM of \txseq_counter_i[4]_i_1\ : label is "soft_lutpair72"; attribute SOFT_HLUTNM of \txseq_counter_i[5]_i_3\ : label is "soft_lutpair76"; begin FSM_RESETDONE_reg_0 <= \^fsm_resetdone_reg_0\; RX_NEG_OUT_reg_0 <= \^rx_neg_out_reg_0\; FSM_RESETDONE_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => tx_fsm_resetdone_i, I1 => rx_fsm_resetdone_i, O => FSM_RESETDONE0 ); FSM_RESETDONE_reg: unisim.vcomponents.FDRE port map ( C => stg4_reg, CE => '1', D => FSM_RESETDONE0, Q => \^fsm_resetdone_reg_0\, R => '0' ); \FSM_onehot_cdr_reset_fsm_r[2]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"80000000" ) port map ( I0 => \cdr_reset_fsm_cntr_r[7]_i_5_n_0\, I1 => cdr_reset_fsm_cntr_r(7), I2 => cdr_reset_fsm_cntr_r(6), I3 => cdr_reset_fsm_cntr_r(4), I4 => cdr_reset_fsm_cntr_r(5), O => \FSM_onehot_cdr_reset_fsm_r[2]_i_2_n_0\ ); \FSM_onehot_cdr_reset_fsm_r_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => stg4_reg, CE => '1', D => u_rst_sync_blocksyncall_initclk_sync_n_2, Q => \FSM_onehot_cdr_reset_fsm_r_reg_n_0_[0]\, R => '0' ); \FSM_onehot_cdr_reset_fsm_r_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => u_rst_sync_blocksyncall_initclk_sync_n_1, Q => cdr_reset_fsm_lnkreset, R => '0' ); \FSM_onehot_cdr_reset_fsm_r_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => u_rst_sync_blocksyncall_initclk_sync_n_0, Q => allow_block_sync_propagation, R => '0' ); LINK_RESET_OUT_reg: unisim.vcomponents.FDRE port map ( C => stg4_reg, CE => '1', D => LINK_RESET_OUT0, Q => link_reset_out, R => '0' ); RX_NEG_OUT_reg: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => \u_cdc__check_polarity_n_0\, Q => \^rx_neg_out_reg_0\, R => '0' ); \TX_DATA[55]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFFFD" ) port map ( I0 => \txseq_counter_i_reg_n_0_[1]\, I1 => \TX_DATA[55]_i_3_n_0\, I2 => \txseq_counter_i_reg_n_0_[6]\, I3 => \txseq_counter_i_reg_n_0_[0]\, I4 => rst_pma_init_usrclk, O => \txseq_counter_i_reg[1]_0\ ); \TX_DATA[55]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"FF7F" ) port map ( I0 => \txseq_counter_i_reg_n_0_[4]\, I1 => \txseq_counter_i_reg_n_0_[2]\, I2 => \txseq_counter_i_reg_n_0_[3]\, I3 => \txseq_counter_i_reg_n_0_[5]\, O => \TX_DATA[55]_i_3_n_0\ ); TX_HEADER_0_i_2: unisim.vcomponents.LUT4 generic map( INIT => X"FEFF" ) port map ( I0 => \txseq_counter_i_reg_n_0_[0]\, I1 => \txseq_counter_i_reg_n_0_[6]\, I2 => \TX_DATA[55]_i_3_n_0\, I3 => \txseq_counter_i_reg_n_0_[1]\, O => txdatavalid_symgen_i ); allow_block_sync_propagation_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => cbcc_gtx0_i_n_74, Q => allow_block_sync_propagation_reg_n_0, R => '0' ); aurora_64b66b_0_multi_gt_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_MULTI_GT port map ( D(0) => rxgearboxslip_i, Q(1 downto 0) => tx_hdr_r(1 downto 0), RXBUFSTATUS(0) => int_rxbufstatus_i(2), RXDATA(31 downto 0) => pre_rxdata_from_gtx_i(31 downto 0), RXHEADER(1 downto 0) => pre_rxheader_from_gtx_i(1 downto 0), SCRAMBLED_DATA_OUT(63 downto 0) => scrambled_data_i(63 downto 0), SR(0) => gtrxreset_t, TXBUFSTATUS(0) => tx_buf_err_i, ack_flag => \aurora_64b66b_0_gtx_inst/ack_flag\, ack_flag_reg => stg4_reg, \cpllpd_wait_reg[95]\ => rx_resetdone_i, \cpllpd_wait_reg[95]_0\ => tx_resetdone_i, drp_clk_in => drp_clk_in, drpaddr_in(8 downto 0) => drpaddr_in(8 downto 0), drpdi_in(15 downto 0) => drpdi_in(15 downto 0), drpdo_out(15 downto 0) => drpdo_out(15 downto 0), drpen_in => drpen_in, drprdy_out => drprdy_out, drpwe_in => drpwe_in, flag2_reg => txresetfsm_i_n_6, gt_cpllreset_i => gt_cpllreset_i, gt_qpllclk_quad1_out => gt_qpllclk_quad1_out, gt_qpllrefclk_quad1_out => gt_qpllrefclk_quad1_out, gt_rxcdrovrden_in => gt_rxcdrovrden_in, gttxreset_t => gttxreset_t, in0 => gt_cplllock_ii, loopback(2 downto 0) => loopback(2 downto 0), \out\ => sync_rx_polarity_r, pre_rxdatavalid_i => pre_rxdatavalid_i, pre_rxheadervalid_i => pre_rxheadervalid_i, refclk1_in => refclk1_in, rxn => rxn, rxp => rxp, rxrecclk_from_gtx_i => rxrecclk_from_gtx_i, rxuserrdy_t => rxuserrdy_t, s_level_out_d1_aurora_64b66b_0_cdc_to_reg => rxrecclk_to_fabric_i, s_level_out_d1_aurora_64b66b_0_cdc_to_reg_0 => stg4_reg_0, s_level_out_d1_aurora_64b66b_0_cdc_to_reg_1 => \out\, s_level_out_d1_aurora_64b66b_0_cdc_to_reg_2(6) => \txseq_counter_i_reg_n_0_[6]\, s_level_out_d1_aurora_64b66b_0_cdc_to_reg_2(5) => \txseq_counter_i_reg_n_0_[5]\, s_level_out_d1_aurora_64b66b_0_cdc_to_reg_2(4) => \txseq_counter_i_reg_n_0_[4]\, s_level_out_d1_aurora_64b66b_0_cdc_to_reg_2(3) => \txseq_counter_i_reg_n_0_[3]\, s_level_out_d1_aurora_64b66b_0_cdc_to_reg_2(2) => \txseq_counter_i_reg_n_0_[2]\, s_level_out_d1_aurora_64b66b_0_cdc_to_reg_2(1) => \txseq_counter_i_reg_n_0_[1]\, s_level_out_d1_aurora_64b66b_0_cdc_to_reg_2(0) => \txseq_counter_i_reg_n_0_[0]\, tx_out_clk => tx_out_clk, txn => txn, txp => txp, txuserrdy_t => txuserrdy_t ); block_sync_sm_gtx0_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_BLOCK_SYNC_SM port map ( D(0) => rxgearboxslip_i, Q(1 downto 0) => rxheader_from_gtx_i(1 downto 0), SR(0) => new_gtx_rx_pcsreset_comb, blocksync_out_i => blocksync_out_i, \out\ => rxrecclk_to_fabric_i, rxheadervalid_i => rxheadervalid_i ); blocksync_all_lanes_inrxclk_q_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => rxrecclk_to_fabric_i, CE => '1', D => blocksync_out_i, Q => blocksync_all_lanes_inrxclk_q, R => '0' ); cbcc_gtx0_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_CLOCK_CORRECTION_CHANNEL_BONDING port map ( ANY_VLD_BTF_FLAG => ANY_VLD_BTF_FLAG, AR(0) => rxfsm_reset_i, CB_detect0 => CB_detect0, CB_detect_dlyd0p5 => CB_detect_dlyd0p5, CC_RXLOSSOFSYNC_OUT_reg_0 => common_reset_cbcc_i_n_0, CC_detect => CC_detect, CC_detect_dlyd1 => CC_detect_dlyd1, D(1) => CC_detect_pulse_i, D(0) => CB_detect, HARD_ERR_reg => rx_elastic_buf_err, ILLEGAL_BTF_reg => ILLEGAL_BTF_reg, LINK_RESET_OUT0 => LINK_RESET_OUT0, Q(1 downto 0) => rxheader_to_fifo_i(1 downto 0), SR(0) => cbcc_fifo_reset_to_fifo_wr_clk, START_CB_WRITES_OUT => START_CB_WRITES_OUT, START_CB_WRITES_OUT_reg_0 => all_vld_btf_flag_i, TXBUFSTATUS(0) => tx_buf_err_i, UNSCRAMBLED_DATA_OUT(31 downto 0) => rxdata_to_fifo_i(31 downto 0), allow_block_sync_propagation => allow_block_sync_propagation, allow_block_sync_propagation_reg => cbcc_gtx0_i_n_74, allow_block_sync_propagation_reg_0 => allow_block_sync_propagation_reg_n_0, allow_block_sync_propagation_reg_1 => \FSM_onehot_cdr_reset_fsm_r_reg_n_0_[0]\, bit_err_chan_bond_i => bit_err_chan_bond_i, cbcc_fifo_reset_rd_clk => cbcc_fifo_reset_rd_clk, cbcc_fifo_reset_to_fifo_rd_clk => cbcc_fifo_reset_to_fifo_rd_clk, cbcc_fifo_reset_wr_clk => cbcc_fifo_reset_wr_clk, cbcc_reset_cbstg2_rd_clk => cbcc_reset_cbstg2_rd_clk, cdr_reset_fsm_lnkreset => cdr_reset_fsm_lnkreset, cdr_reset_fsm_lnkreset_reg => cbcc_gtx0_i_n_76, channel_up_tx_if => channel_up_tx_if, \count_for_reset_r_reg[0]_0\ => \^fsm_resetdone_reg_0\, do_rd_en_i => do_rd_en_i, do_wr_en_reg_0 => all_start_cb_writes_i, enable_err_detect_i => enable_err_detect_i, final_gater_for_fifo_din_i => final_gater_for_fifo_din_i, hard_err_rst_int => hard_err_rst_int, hard_err_usr0 => hard_err_usr0, hard_err_usr_reg => hard_err_usr_reg_0, hold_reg_reg_0 => hold_reg_reg, illegal_btf_i => illegal_btf_i, in0 => rxlossofsync_out_q, master_do_rd_en_out_reg(65 downto 0) => master_do_rd_en_out_reg(65 downto 0), master_do_rd_en_q_reg_0 => master_do_rd_en_i, \out\ => rxrecclk_to_fabric_i, p_2_in => p_2_in, reset_initclk => reset_initclk, rx_lossofsync_i => rx_lossofsync_i, \rx_state_reg[7]\ => cdr_reset_fsm_lnkreset_reg_n_0, \rx_state_reg[7]_0\ => \init_wait_count_reg[7]\, rxdatavalid_i => rxdatavalid_i, rxdatavalid_to_fifo_i => rxdatavalid_to_fifo_i, rxfsm_reset_i => rxfsm_reset_i, s_level_out_d6_reg => \out\, stg3_reg => stg4_reg, \valid_btf_detect_extend_r_reg[4]_0\(0) => new_gtx_rx_pcsreset_comb, wr_err_rd_clk_sync_reg_0 => wr_err_rd_clk_sync_reg ); \cdr_reset_fsm_cntr_r[0]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => cdr_reset_fsm_lnkreset, I1 => cdr_reset_fsm_cntr_r(0), O => \cdr_reset_fsm_cntr_r[0]_i_1_n_0\ ); \cdr_reset_fsm_cntr_r[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"60" ) port map ( I0 => cdr_reset_fsm_cntr_r(1), I1 => cdr_reset_fsm_cntr_r(0), I2 => cdr_reset_fsm_lnkreset, O => \cdr_reset_fsm_cntr_r[1]_i_1_n_0\ ); \cdr_reset_fsm_cntr_r[2]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7800" ) port map ( I0 => cdr_reset_fsm_cntr_r(0), I1 => cdr_reset_fsm_cntr_r(1), I2 => cdr_reset_fsm_cntr_r(2), I3 => cdr_reset_fsm_lnkreset, O => \cdr_reset_fsm_cntr_r[2]_i_1_n_0\ ); \cdr_reset_fsm_cntr_r[3]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"2AAA8000" ) port map ( I0 => cdr_reset_fsm_lnkreset, I1 => cdr_reset_fsm_cntr_r(2), I2 => cdr_reset_fsm_cntr_r(1), I3 => cdr_reset_fsm_cntr_r(0), I4 => cdr_reset_fsm_cntr_r(3), O => \cdr_reset_fsm_cntr_r[3]_i_1_n_0\ ); \cdr_reset_fsm_cntr_r[4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFF800000000000" ) port map ( I0 => cdr_reset_fsm_cntr_r(1), I1 => cdr_reset_fsm_cntr_r(0), I2 => cdr_reset_fsm_cntr_r(3), I3 => cdr_reset_fsm_cntr_r(2), I4 => cdr_reset_fsm_cntr_r(4), I5 => cdr_reset_fsm_lnkreset, O => \cdr_reset_fsm_cntr_r[4]_i_1_n_0\ ); \cdr_reset_fsm_cntr_r[5]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"2A80" ) port map ( I0 => cdr_reset_fsm_lnkreset, I1 => cdr_reset_fsm_cntr_r(4), I2 => \cdr_reset_fsm_cntr_r[7]_i_5_n_0\, I3 => cdr_reset_fsm_cntr_r(5), O => \cdr_reset_fsm_cntr_r[5]_i_1_n_0\ ); \cdr_reset_fsm_cntr_r[6]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"2AAA8000" ) port map ( I0 => cdr_reset_fsm_lnkreset, I1 => cdr_reset_fsm_cntr_r(5), I2 => \cdr_reset_fsm_cntr_r[7]_i_5_n_0\, I3 => cdr_reset_fsm_cntr_r(4), I4 => cdr_reset_fsm_cntr_r(6), O => \cdr_reset_fsm_cntr_r[6]_i_1_n_0\ ); \cdr_reset_fsm_cntr_r[7]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"FE" ) port map ( I0 => \FSM_onehot_cdr_reset_fsm_r_reg_n_0_[0]\, I1 => allow_block_sync_propagation, I2 => \cdr_reset_fsm_cntr_r[7]_i_4_n_0\, O => \cdr_reset_fsm_cntr_r[7]_i_2_n_0\ ); \cdr_reset_fsm_cntr_r[7]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"2AAAAAAA80000000" ) port map ( I0 => cdr_reset_fsm_lnkreset, I1 => cdr_reset_fsm_cntr_r(4), I2 => \cdr_reset_fsm_cntr_r[7]_i_5_n_0\, I3 => cdr_reset_fsm_cntr_r(5), I4 => cdr_reset_fsm_cntr_r(6), I5 => cdr_reset_fsm_cntr_r(7), O => \cdr_reset_fsm_cntr_r[7]_i_3_n_0\ ); \cdr_reset_fsm_cntr_r[7]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"2AAAAAAAAAAAAAAA" ) port map ( I0 => cdr_reset_fsm_lnkreset, I1 => cdr_reset_fsm_cntr_r(5), I2 => cdr_reset_fsm_cntr_r(4), I3 => cdr_reset_fsm_cntr_r(6), I4 => cdr_reset_fsm_cntr_r(7), I5 => \cdr_reset_fsm_cntr_r[7]_i_5_n_0\, O => \cdr_reset_fsm_cntr_r[7]_i_4_n_0\ ); \cdr_reset_fsm_cntr_r[7]_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"8000" ) port map ( I0 => cdr_reset_fsm_cntr_r(1), I1 => cdr_reset_fsm_cntr_r(0), I2 => cdr_reset_fsm_cntr_r(3), I3 => cdr_reset_fsm_cntr_r(2), O => \cdr_reset_fsm_cntr_r[7]_i_5_n_0\ ); \cdr_reset_fsm_cntr_r_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => \cdr_reset_fsm_cntr_r[7]_i_2_n_0\, D => \cdr_reset_fsm_cntr_r[0]_i_1_n_0\, Q => cdr_reset_fsm_cntr_r(0), R => p_2_in ); \cdr_reset_fsm_cntr_r_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => \cdr_reset_fsm_cntr_r[7]_i_2_n_0\, D => \cdr_reset_fsm_cntr_r[1]_i_1_n_0\, Q => cdr_reset_fsm_cntr_r(1), R => p_2_in ); \cdr_reset_fsm_cntr_r_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => \cdr_reset_fsm_cntr_r[7]_i_2_n_0\, D => \cdr_reset_fsm_cntr_r[2]_i_1_n_0\, Q => cdr_reset_fsm_cntr_r(2), R => p_2_in ); \cdr_reset_fsm_cntr_r_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => \cdr_reset_fsm_cntr_r[7]_i_2_n_0\, D => \cdr_reset_fsm_cntr_r[3]_i_1_n_0\, Q => cdr_reset_fsm_cntr_r(3), R => p_2_in ); \cdr_reset_fsm_cntr_r_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => \cdr_reset_fsm_cntr_r[7]_i_2_n_0\, D => \cdr_reset_fsm_cntr_r[4]_i_1_n_0\, Q => cdr_reset_fsm_cntr_r(4), R => p_2_in ); \cdr_reset_fsm_cntr_r_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => \cdr_reset_fsm_cntr_r[7]_i_2_n_0\, D => \cdr_reset_fsm_cntr_r[5]_i_1_n_0\, Q => cdr_reset_fsm_cntr_r(5), R => p_2_in ); \cdr_reset_fsm_cntr_r_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => \cdr_reset_fsm_cntr_r[7]_i_2_n_0\, D => \cdr_reset_fsm_cntr_r[6]_i_1_n_0\, Q => cdr_reset_fsm_cntr_r(6), R => p_2_in ); \cdr_reset_fsm_cntr_r_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => \cdr_reset_fsm_cntr_r[7]_i_2_n_0\, D => \cdr_reset_fsm_cntr_r[7]_i_3_n_0\, Q => cdr_reset_fsm_cntr_r(7), R => p_2_in ); cdr_reset_fsm_lnkreset_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => '1', D => cbcc_gtx0_i_n_76, Q => cdr_reset_fsm_lnkreset_reg_n_0, R => '0' ); common_logic_cbcc_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_common_logic_cbcc port map ( ANY_VLD_BTF_FLAG => ANY_VLD_BTF_FLAG, START_CB_WRITES_OUT => START_CB_WRITES_OUT, all_vld_btf_flag_i => all_vld_btf_flag_i, all_vld_btf_out_reg_0 => rxrecclk_to_fabric_i, cb_bit_err_out => cb_bit_err_out, cbcc_fifo_reset_rd_clk => cbcc_fifo_reset_rd_clk, cbcc_fifo_reset_wr_clk => cbcc_fifo_reset_wr_clk, in0 => all_start_cb_writes_i, master_do_rd_en_i => master_do_rd_en_i, master_do_rd_en_out_reg_0 => do_rd_en_i, master_do_rd_en_out_reg_1 => \out\, \out\ => bit_err_chan_bond_i ); common_reset_cbcc_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_common_reset_cbcc port map ( SR(0) => cbcc_fifo_reset_to_fifo_wr_clk, cb_bit_err_out => cb_bit_err_out, cbcc_fifo_reset_rd_clk => cbcc_fifo_reset_rd_clk, cbcc_fifo_reset_to_fifo_rd_clk => cbcc_fifo_reset_to_fifo_rd_clk, cbcc_fifo_reset_wr_clk => cbcc_fifo_reset_wr_clk, cbcc_reset_cbstg2_rd_clk => cbcc_reset_cbstg2_rd_clk, \out\ => \out\, stg1_aurora_64b66b_0_cdc_to_reg(0) => new_gtx_rx_pcsreset_comb, stg2_reg => rxrecclk_to_fabric_i, stg5_reg => common_reset_cbcc_i_n_0 ); data_v_r_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => \txseq_counter_i_reg_n_0_[0]\, I1 => \txseq_counter_i_reg_n_0_[6]\, I2 => \TX_DATA[55]_i_3_n_0\, I3 => \txseq_counter_i_reg_n_0_[1]\, O => TXDATAVALID_IN ); descrambler_64b66b_gtx0_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_DESCRAMBLER_64B66B port map ( CB_detect0 => CB_detect0, CB_detect_dlyd0p5 => CB_detect_dlyd0p5, CB_detect_dlyd0p5_reg(1 downto 0) => rxheader_to_fifo_i(1 downto 0), CC_detect => CC_detect, CC_detect_dlyd1 => CC_detect_dlyd1, D(1) => CC_detect_pulse_i, D(0) => CB_detect, E(0) => rxdatavalid_i_0, Q(31 downto 0) => rxdata_to_fifo_i(31 downto 0), \descrambler_reg[31]_0\(31 downto 0) => rxdata_from_gtx_i(31 downto 0), \descrambler_reg[39]_0\(1) => descrambler_64b66b_gtx0_i_n_36, \descrambler_reg[39]_0\(0) => poly(52), in0 => rxlossofsync_out_q, \out\ => rxrecclk_to_fabric_i, rxdatavalid_to_fifo_i => rxdatavalid_to_fifo_i, \unscrambled_data_i_reg[13]_0\(0) => unscrambled_data_i052_out ); extend_cc_r_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFF000100000000" ) port map ( I0 => \txseq_counter_i_reg_n_0_[0]\, I1 => \txseq_counter_i_reg_n_0_[6]\, I2 => \TX_DATA[55]_i_3_n_0\, I3 => \txseq_counter_i_reg_n_0_[1]\, I4 => extend_cc_r, I5 => Q, O => \txseq_counter_i_reg[0]_0\ ); \hard_err_cntr_r[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \hard_err_cntr_r_reg__0\(0), O => \p_0_in__4\(0) ); \hard_err_cntr_r[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \hard_err_cntr_r_reg__0\(0), I1 => \hard_err_cntr_r_reg__0\(1), O => \p_0_in__4\(1) ); \hard_err_cntr_r[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => \hard_err_cntr_r_reg__0\(2), I1 => \hard_err_cntr_r_reg__0\(0), I2 => \hard_err_cntr_r_reg__0\(1), O => \p_0_in__4\(2) ); \hard_err_cntr_r[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"6AAA" ) port map ( I0 => \hard_err_cntr_r_reg__0\(3), I1 => \hard_err_cntr_r_reg__0\(1), I2 => \hard_err_cntr_r_reg__0\(0), I3 => \hard_err_cntr_r_reg__0\(2), O => \p_0_in__4\(3) ); \hard_err_cntr_r[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"6AAAAAAA" ) port map ( I0 => \hard_err_cntr_r_reg__0\(4), I1 => \hard_err_cntr_r_reg__0\(1), I2 => \hard_err_cntr_r_reg__0\(0), I3 => \hard_err_cntr_r_reg__0\(3), I4 => \hard_err_cntr_r_reg__0\(2), O => \p_0_in__4\(4) ); \hard_err_cntr_r[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \hard_err_cntr_r_reg__0\(2), I1 => \hard_err_cntr_r_reg__0\(3), I2 => \hard_err_cntr_r_reg__0\(0), I3 => \hard_err_cntr_r_reg__0\(1), I4 => \hard_err_cntr_r_reg__0\(4), I5 => \hard_err_cntr_r_reg__0\(5), O => \p_0_in__4\(5) ); \hard_err_cntr_r[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"9A" ) port map ( I0 => \hard_err_cntr_r_reg__0\(6), I1 => \hard_err_cntr_r[7]_i_6_n_0\, I2 => \hard_err_cntr_r_reg__0\(5), O => \p_0_in__4\(6) ); \hard_err_cntr_r[7]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"AA6A" ) port map ( I0 => \hard_err_cntr_r_reg__0\(7), I1 => \hard_err_cntr_r_reg__0\(5), I2 => \hard_err_cntr_r_reg__0\(6), I3 => \hard_err_cntr_r[7]_i_6_n_0\, O => \p_0_in__4\(7) ); \hard_err_cntr_r[7]_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"7FFF" ) port map ( I0 => \hard_err_cntr_r_reg__0\(1), I1 => \hard_err_cntr_r_reg__0\(0), I2 => \hard_err_cntr_r_reg__0\(3), I3 => \hard_err_cntr_r_reg__0\(2), O => \hard_err_cntr_r[7]_i_5_n_0\ ); \hard_err_cntr_r[7]_i_6\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFFFFFF" ) port map ( I0 => \hard_err_cntr_r_reg__0\(2), I1 => \hard_err_cntr_r_reg__0\(3), I2 => \hard_err_cntr_r_reg__0\(0), I3 => \hard_err_cntr_r_reg__0\(1), I4 => \hard_err_cntr_r_reg__0\(4), O => \hard_err_cntr_r[7]_i_6_n_0\ ); \hard_err_cntr_r_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => hard_err_cntr_r, D => \p_0_in__4\(0), Q => \hard_err_cntr_r_reg__0\(0), R => HPCNT_RESET_IN ); \hard_err_cntr_r_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => hard_err_cntr_r, D => \p_0_in__4\(1), Q => \hard_err_cntr_r_reg__0\(1), R => HPCNT_RESET_IN ); \hard_err_cntr_r_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => hard_err_cntr_r, D => \p_0_in__4\(2), Q => \hard_err_cntr_r_reg__0\(2), R => HPCNT_RESET_IN ); \hard_err_cntr_r_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => hard_err_cntr_r, D => \p_0_in__4\(3), Q => \hard_err_cntr_r_reg__0\(3), R => HPCNT_RESET_IN ); \hard_err_cntr_r_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => hard_err_cntr_r, D => \p_0_in__4\(4), Q => \hard_err_cntr_r_reg__0\(4), R => HPCNT_RESET_IN ); \hard_err_cntr_r_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => hard_err_cntr_r, D => \p_0_in__4\(5), Q => \hard_err_cntr_r_reg__0\(5), R => HPCNT_RESET_IN ); \hard_err_cntr_r_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => hard_err_cntr_r, D => \p_0_in__4\(6), Q => \hard_err_cntr_r_reg__0\(6), R => HPCNT_RESET_IN ); \hard_err_cntr_r_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => stg4_reg, CE => hard_err_cntr_r, D => \p_0_in__4\(7), Q => \hard_err_cntr_r_reg__0\(7), R => HPCNT_RESET_IN ); hard_err_rst_int_i_2: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \hard_err_cntr_r_reg__0\(0), I1 => \hard_err_cntr_r_reg__0\(1), O => hard_err_rst_int_i_2_n_0 ); hard_err_rst_int_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFE" ) port map ( I0 => \hard_err_cntr_r_reg__0\(4), I1 => \hard_err_cntr_r_reg__0\(5), I2 => \hard_err_cntr_r_reg__0\(6), I3 => \hard_err_cntr_r_reg__0\(7), I4 => \hard_err_cntr_r_reg__0\(3), I5 => \hard_err_cntr_r_reg__0\(2), O => hard_err_rst_int_i_3_n_0 ); hard_err_rst_int_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFFFFFFFFFF" ) port map ( I0 => \hard_err_cntr_r_reg__0\(3), I1 => \hard_err_cntr_r_reg__0\(2), I2 => \hard_err_cntr_r_reg__0\(4), I3 => \hard_err_cntr_r_reg__0\(7), I4 => \hard_err_cntr_r_reg__0\(5), I5 => \hard_err_cntr_r_reg__0\(6), O => hard_err_rst_int_i_4_n_0 ); hard_err_rst_int_reg: unisim.vcomponents.FDRE port map ( C => stg4_reg, CE => '1', D => u_cdc_hard_err_init_n_0, Q => hard_err_rst_int, R => '0' ); hard_err_usr_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => \out\, CE => '1', D => hard_err_usr0, Q => hard_err_usr, R => '0' ); new_gtx_rx_pcsreset_comb_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => rxrecclk_to_fabric_i, CE => '1', D => new_gtx_rx_pcsreset_comb0, Q => new_gtx_rx_pcsreset_comb, R => '0' ); \pos_rxdata_from_gtx_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => pre_r4_rxdatavalid_i, D => pre_r4_rxdata_from_gtx_i(0), Q => pos_rxdata_from_gtx_i(0), R => '0' ); \pos_rxdata_from_gtx_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => pre_r4_rxdatavalid_i, D => pre_r4_rxdata_from_gtx_i(10), Q => pos_rxdata_from_gtx_i(10), R => '0' ); \pos_rxdata_from_gtx_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => pre_r4_rxdatavalid_i, D => pre_r4_rxdata_from_gtx_i(11), Q => pos_rxdata_from_gtx_i(11), R => '0' ); \pos_rxdata_from_gtx_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => pre_r4_rxdatavalid_i, D => pre_r4_rxdata_from_gtx_i(12), Q => pos_rxdata_from_gtx_i(12), R => '0' ); \pos_rxdata_from_gtx_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => pre_r4_rxdatavalid_i, D => pre_r4_rxdata_from_gtx_i(13), Q => pos_rxdata_from_gtx_i(13), R => '0' ); \pos_rxdata_from_gtx_i_reg[14]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => pre_r4_rxdatavalid_i, D => pre_r4_rxdata_from_gtx_i(14), Q => pos_rxdata_from_gtx_i(14), R => '0' ); \pos_rxdata_from_gtx_i_reg[15]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => pre_r4_rxdatavalid_i, D => pre_r4_rxdata_from_gtx_i(15), Q => pos_rxdata_from_gtx_i(15), R => '0' ); \pos_rxdata_from_gtx_i_reg[16]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => pre_r4_rxdatavalid_i, D => pre_r4_rxdata_from_gtx_i(16), Q => pos_rxdata_from_gtx_i(16), R => '0' ); \pos_rxdata_from_gtx_i_reg[17]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => pre_r4_rxdatavalid_i, D => pre_r4_rxdata_from_gtx_i(17), Q => pos_rxdata_from_gtx_i(17), R => '0' ); \pos_rxdata_from_gtx_i_reg[18]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => pre_r4_rxdatavalid_i, D => pre_r4_rxdata_from_gtx_i(18), Q => pos_rxdata_from_gtx_i(18), R => '0' ); \pos_rxdata_from_gtx_i_reg[19]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => pre_r4_rxdatavalid_i, D => pre_r4_rxdata_from_gtx_i(19), Q => pos_rxdata_from_gtx_i(19), R => '0' ); \pos_rxdata_from_gtx_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => pre_r4_rxdatavalid_i, D => pre_r4_rxdata_from_gtx_i(1), Q => pos_rxdata_from_gtx_i(1), R => '0' ); \pos_rxdata_from_gtx_i_reg[20]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => pre_r4_rxdatavalid_i, D => pre_r4_rxdata_from_gtx_i(20), Q => pos_rxdata_from_gtx_i(20), R => '0' ); \pos_rxdata_from_gtx_i_reg[21]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => pre_r4_rxdatavalid_i, D => pre_r4_rxdata_from_gtx_i(21), Q => pos_rxdata_from_gtx_i(21), R => '0' ); \pos_rxdata_from_gtx_i_reg[22]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => pre_r4_rxdatavalid_i, D => pre_r4_rxdata_from_gtx_i(22), Q => pos_rxdata_from_gtx_i(22), R => '0' ); \pos_rxdata_from_gtx_i_reg[23]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => pre_r4_rxdatavalid_i, D => pre_r4_rxdata_from_gtx_i(23), Q => pos_rxdata_from_gtx_i(23), R => '0' ); \pos_rxdata_from_gtx_i_reg[24]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => pre_r4_rxdatavalid_i, D => pre_r4_rxdata_from_gtx_i(24), Q => pos_rxdata_from_gtx_i(24), R => '0' ); \pos_rxdata_from_gtx_i_reg[25]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => pre_r4_rxdatavalid_i, D => pre_r4_rxdata_from_gtx_i(25), Q => pos_rxdata_from_gtx_i(25), R => '0' ); \pos_rxdata_from_gtx_i_reg[26]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => pre_r4_rxdatavalid_i, D => pre_r4_rxdata_from_gtx_i(26), Q => pos_rxdata_from_gtx_i(26), R => '0' ); \pos_rxdata_from_gtx_i_reg[27]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => pre_r4_rxdatavalid_i, D => pre_r4_rxdata_from_gtx_i(27), Q => pos_rxdata_from_gtx_i(27), R => '0' ); \pos_rxdata_from_gtx_i_reg[28]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => pre_r4_rxdatavalid_i, D => pre_r4_rxdata_from_gtx_i(28), Q => pos_rxdata_from_gtx_i(28), R => '0' ); \pos_rxdata_from_gtx_i_reg[29]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => pre_r4_rxdatavalid_i, D => pre_r4_rxdata_from_gtx_i(29), Q => pos_rxdata_from_gtx_i(29), R => '0' ); \pos_rxdata_from_gtx_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => pre_r4_rxdatavalid_i, D => pre_r4_rxdata_from_gtx_i(2), Q => pos_rxdata_from_gtx_i(2), R => '0' ); \pos_rxdata_from_gtx_i_reg[30]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => pre_r4_rxdatavalid_i, D => pre_r4_rxdata_from_gtx_i(30), Q => pos_rxdata_from_gtx_i(30), R => '0' ); \pos_rxdata_from_gtx_i_reg[31]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => pre_r4_rxdatavalid_i, D => pre_r4_rxdata_from_gtx_i(31), Q => pos_rxdata_from_gtx_i(31), R => '0' ); \pos_rxdata_from_gtx_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => pre_r4_rxdatavalid_i, D => pre_r4_rxdata_from_gtx_i(3), Q => pos_rxdata_from_gtx_i(3), R => '0' ); \pos_rxdata_from_gtx_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => pre_r4_rxdatavalid_i, D => pre_r4_rxdata_from_gtx_i(4), Q => pos_rxdata_from_gtx_i(4), R => '0' ); \pos_rxdata_from_gtx_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => pre_r4_rxdatavalid_i, D => pre_r4_rxdata_from_gtx_i(5), Q => pos_rxdata_from_gtx_i(5), R => '0' ); \pos_rxdata_from_gtx_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => pre_r4_rxdatavalid_i, D => pre_r4_rxdata_from_gtx_i(6), Q => pos_rxdata_from_gtx_i(6), R => '0' ); \pos_rxdata_from_gtx_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => pre_r4_rxdatavalid_i, D => pre_r4_rxdata_from_gtx_i(7), Q => pos_rxdata_from_gtx_i(7), R => '0' ); \pos_rxdata_from_gtx_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => pre_r4_rxdatavalid_i, D => pre_r4_rxdata_from_gtx_i(8), Q => pos_rxdata_from_gtx_i(8), R => '0' ); \pos_rxdata_from_gtx_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => pre_r4_rxdatavalid_i, D => pre_r4_rxdata_from_gtx_i(9), Q => pos_rxdata_from_gtx_i(9), R => '0' ); pos_rxdatavalid_i_reg: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => pre_r4_rxdatavalid_i, Q => pos_rxdatavalid_i, R => '0' ); \pos_rxheader_from_gtx_i[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => pre_r4_rxheader_from_gtx_i(0), I1 => pre_r4_rxheadervalid_i, I2 => pos_rxheader_from_gtx_i(0), O => \pos_rxheader_from_gtx_i[0]_i_1_n_0\ ); \pos_rxheader_from_gtx_i[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => pre_r4_rxheader_from_gtx_i(1), I1 => pre_r4_rxheadervalid_i, I2 => pos_rxheader_from_gtx_i(1), O => \pos_rxheader_from_gtx_i[1]_i_1_n_0\ ); \pos_rxheader_from_gtx_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => \pos_rxheader_from_gtx_i[0]_i_1_n_0\, Q => pos_rxheader_from_gtx_i(0), R => '0' ); \pos_rxheader_from_gtx_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => \pos_rxheader_from_gtx_i[1]_i_1_n_0\, Q => pos_rxheader_from_gtx_i(1), R => '0' ); pos_rxheadervalid_i_reg: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => pre_r4_rxheadervalid_i, Q => pos_rxheadervalid_i, R => '0' ); pre_r3_rxdatavalid_i_reg_srl3: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => rxrecclk_to_fabric_i, D => pre_rxdatavalid_i, Q => pre_r3_rxdatavalid_i_reg_srl3_n_0 ); \pre_r3_rxheader_from_gtx_i_reg[0]_srl3\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => rxrecclk_to_fabric_i, D => pre_rxheader_from_gtx_i(0), Q => \pre_r3_rxheader_from_gtx_i_reg[0]_srl3_n_0\ ); \pre_r3_rxheader_from_gtx_i_reg[1]_srl3\: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => rxrecclk_to_fabric_i, D => pre_rxheader_from_gtx_i(1), Q => \pre_r3_rxheader_from_gtx_i_reg[1]_srl3_n_0\ ); pre_r3_rxheadervalid_i_reg_srl3: unisim.vcomponents.SRL16E port map ( A0 => '0', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => rxrecclk_to_fabric_i, D => pre_rxheadervalid_i, Q => pre_r3_rxheadervalid_i_reg_srl3_n_0 ); \pre_r4_rxdata_from_gtx_i_reg[0]_srl4\: unisim.vcomponents.SRL16E port map ( A0 => '1', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => rxrecclk_to_fabric_i, D => pre_rxdata_from_gtx_i(0), Q => pre_r4_rxdata_from_gtx_i(0) ); \pre_r4_rxdata_from_gtx_i_reg[10]_srl4\: unisim.vcomponents.SRL16E port map ( A0 => '1', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => rxrecclk_to_fabric_i, D => pre_rxdata_from_gtx_i(10), Q => pre_r4_rxdata_from_gtx_i(10) ); \pre_r4_rxdata_from_gtx_i_reg[11]_srl4\: unisim.vcomponents.SRL16E port map ( A0 => '1', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => rxrecclk_to_fabric_i, D => pre_rxdata_from_gtx_i(11), Q => pre_r4_rxdata_from_gtx_i(11) ); \pre_r4_rxdata_from_gtx_i_reg[12]_srl4\: unisim.vcomponents.SRL16E port map ( A0 => '1', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => rxrecclk_to_fabric_i, D => pre_rxdata_from_gtx_i(12), Q => pre_r4_rxdata_from_gtx_i(12) ); \pre_r4_rxdata_from_gtx_i_reg[13]_srl4\: unisim.vcomponents.SRL16E port map ( A0 => '1', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => rxrecclk_to_fabric_i, D => pre_rxdata_from_gtx_i(13), Q => pre_r4_rxdata_from_gtx_i(13) ); \pre_r4_rxdata_from_gtx_i_reg[14]_srl4\: unisim.vcomponents.SRL16E port map ( A0 => '1', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => rxrecclk_to_fabric_i, D => pre_rxdata_from_gtx_i(14), Q => pre_r4_rxdata_from_gtx_i(14) ); \pre_r4_rxdata_from_gtx_i_reg[15]_srl4\: unisim.vcomponents.SRL16E port map ( A0 => '1', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => rxrecclk_to_fabric_i, D => pre_rxdata_from_gtx_i(15), Q => pre_r4_rxdata_from_gtx_i(15) ); \pre_r4_rxdata_from_gtx_i_reg[16]_srl4\: unisim.vcomponents.SRL16E port map ( A0 => '1', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => rxrecclk_to_fabric_i, D => pre_rxdata_from_gtx_i(16), Q => pre_r4_rxdata_from_gtx_i(16) ); \pre_r4_rxdata_from_gtx_i_reg[17]_srl4\: unisim.vcomponents.SRL16E port map ( A0 => '1', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => rxrecclk_to_fabric_i, D => pre_rxdata_from_gtx_i(17), Q => pre_r4_rxdata_from_gtx_i(17) ); \pre_r4_rxdata_from_gtx_i_reg[18]_srl4\: unisim.vcomponents.SRL16E port map ( A0 => '1', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => rxrecclk_to_fabric_i, D => pre_rxdata_from_gtx_i(18), Q => pre_r4_rxdata_from_gtx_i(18) ); \pre_r4_rxdata_from_gtx_i_reg[19]_srl4\: unisim.vcomponents.SRL16E port map ( A0 => '1', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => rxrecclk_to_fabric_i, D => pre_rxdata_from_gtx_i(19), Q => pre_r4_rxdata_from_gtx_i(19) ); \pre_r4_rxdata_from_gtx_i_reg[1]_srl4\: unisim.vcomponents.SRL16E port map ( A0 => '1', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => rxrecclk_to_fabric_i, D => pre_rxdata_from_gtx_i(1), Q => pre_r4_rxdata_from_gtx_i(1) ); \pre_r4_rxdata_from_gtx_i_reg[20]_srl4\: unisim.vcomponents.SRL16E port map ( A0 => '1', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => rxrecclk_to_fabric_i, D => pre_rxdata_from_gtx_i(20), Q => pre_r4_rxdata_from_gtx_i(20) ); \pre_r4_rxdata_from_gtx_i_reg[21]_srl4\: unisim.vcomponents.SRL16E port map ( A0 => '1', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => rxrecclk_to_fabric_i, D => pre_rxdata_from_gtx_i(21), Q => pre_r4_rxdata_from_gtx_i(21) ); \pre_r4_rxdata_from_gtx_i_reg[22]_srl4\: unisim.vcomponents.SRL16E port map ( A0 => '1', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => rxrecclk_to_fabric_i, D => pre_rxdata_from_gtx_i(22), Q => pre_r4_rxdata_from_gtx_i(22) ); \pre_r4_rxdata_from_gtx_i_reg[23]_srl4\: unisim.vcomponents.SRL16E port map ( A0 => '1', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => rxrecclk_to_fabric_i, D => pre_rxdata_from_gtx_i(23), Q => pre_r4_rxdata_from_gtx_i(23) ); \pre_r4_rxdata_from_gtx_i_reg[24]_srl4\: unisim.vcomponents.SRL16E port map ( A0 => '1', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => rxrecclk_to_fabric_i, D => pre_rxdata_from_gtx_i(24), Q => pre_r4_rxdata_from_gtx_i(24) ); \pre_r4_rxdata_from_gtx_i_reg[25]_srl4\: unisim.vcomponents.SRL16E port map ( A0 => '1', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => rxrecclk_to_fabric_i, D => pre_rxdata_from_gtx_i(25), Q => pre_r4_rxdata_from_gtx_i(25) ); \pre_r4_rxdata_from_gtx_i_reg[26]_srl4\: unisim.vcomponents.SRL16E port map ( A0 => '1', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => rxrecclk_to_fabric_i, D => pre_rxdata_from_gtx_i(26), Q => pre_r4_rxdata_from_gtx_i(26) ); \pre_r4_rxdata_from_gtx_i_reg[27]_srl4\: unisim.vcomponents.SRL16E port map ( A0 => '1', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => rxrecclk_to_fabric_i, D => pre_rxdata_from_gtx_i(27), Q => pre_r4_rxdata_from_gtx_i(27) ); \pre_r4_rxdata_from_gtx_i_reg[28]_srl4\: unisim.vcomponents.SRL16E port map ( A0 => '1', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => rxrecclk_to_fabric_i, D => pre_rxdata_from_gtx_i(28), Q => pre_r4_rxdata_from_gtx_i(28) ); \pre_r4_rxdata_from_gtx_i_reg[29]_srl4\: unisim.vcomponents.SRL16E port map ( A0 => '1', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => rxrecclk_to_fabric_i, D => pre_rxdata_from_gtx_i(29), Q => pre_r4_rxdata_from_gtx_i(29) ); \pre_r4_rxdata_from_gtx_i_reg[2]_srl4\: unisim.vcomponents.SRL16E port map ( A0 => '1', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => rxrecclk_to_fabric_i, D => pre_rxdata_from_gtx_i(2), Q => pre_r4_rxdata_from_gtx_i(2) ); \pre_r4_rxdata_from_gtx_i_reg[30]_srl4\: unisim.vcomponents.SRL16E port map ( A0 => '1', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => rxrecclk_to_fabric_i, D => pre_rxdata_from_gtx_i(30), Q => pre_r4_rxdata_from_gtx_i(30) ); \pre_r4_rxdata_from_gtx_i_reg[31]_srl4\: unisim.vcomponents.SRL16E port map ( A0 => '1', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => rxrecclk_to_fabric_i, D => pre_rxdata_from_gtx_i(31), Q => pre_r4_rxdata_from_gtx_i(31) ); \pre_r4_rxdata_from_gtx_i_reg[3]_srl4\: unisim.vcomponents.SRL16E port map ( A0 => '1', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => rxrecclk_to_fabric_i, D => pre_rxdata_from_gtx_i(3), Q => pre_r4_rxdata_from_gtx_i(3) ); \pre_r4_rxdata_from_gtx_i_reg[4]_srl4\: unisim.vcomponents.SRL16E port map ( A0 => '1', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => rxrecclk_to_fabric_i, D => pre_rxdata_from_gtx_i(4), Q => pre_r4_rxdata_from_gtx_i(4) ); \pre_r4_rxdata_from_gtx_i_reg[5]_srl4\: unisim.vcomponents.SRL16E port map ( A0 => '1', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => rxrecclk_to_fabric_i, D => pre_rxdata_from_gtx_i(5), Q => pre_r4_rxdata_from_gtx_i(5) ); \pre_r4_rxdata_from_gtx_i_reg[6]_srl4\: unisim.vcomponents.SRL16E port map ( A0 => '1', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => rxrecclk_to_fabric_i, D => pre_rxdata_from_gtx_i(6), Q => pre_r4_rxdata_from_gtx_i(6) ); \pre_r4_rxdata_from_gtx_i_reg[7]_srl4\: unisim.vcomponents.SRL16E port map ( A0 => '1', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => rxrecclk_to_fabric_i, D => pre_rxdata_from_gtx_i(7), Q => pre_r4_rxdata_from_gtx_i(7) ); \pre_r4_rxdata_from_gtx_i_reg[8]_srl4\: unisim.vcomponents.SRL16E port map ( A0 => '1', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => rxrecclk_to_fabric_i, D => pre_rxdata_from_gtx_i(8), Q => pre_r4_rxdata_from_gtx_i(8) ); \pre_r4_rxdata_from_gtx_i_reg[9]_srl4\: unisim.vcomponents.SRL16E port map ( A0 => '1', A1 => '1', A2 => '0', A3 => '0', CE => '1', CLK => rxrecclk_to_fabric_i, D => pre_rxdata_from_gtx_i(9), Q => pre_r4_rxdata_from_gtx_i(9) ); pre_r4_rxdatavalid_i_reg: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => pre_r3_rxdatavalid_i_reg_srl3_n_0, Q => pre_r4_rxdatavalid_i, R => '0' ); \pre_r4_rxheader_from_gtx_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => \pre_r3_rxheader_from_gtx_i_reg[0]_srl3_n_0\, Q => pre_r4_rxheader_from_gtx_i(0), R => '0' ); \pre_r4_rxheader_from_gtx_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => \pre_r3_rxheader_from_gtx_i_reg[1]_srl3_n_0\, Q => pre_r4_rxheader_from_gtx_i(1), R => '0' ); pre_r4_rxheadervalid_i_reg: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => pre_r3_rxheadervalid_i_reg_srl3_n_0, Q => pre_r4_rxheadervalid_i, R => '0' ); \rxdata_from_gtx_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => pos_rxdata_from_gtx_i(0), Q => rxdata_from_gtx_i(0), R => '0' ); \rxdata_from_gtx_i_reg[10]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => pos_rxdata_from_gtx_i(10), Q => rxdata_from_gtx_i(10), R => '0' ); \rxdata_from_gtx_i_reg[11]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => pos_rxdata_from_gtx_i(11), Q => rxdata_from_gtx_i(11), R => '0' ); \rxdata_from_gtx_i_reg[12]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => pos_rxdata_from_gtx_i(12), Q => rxdata_from_gtx_i(12), R => '0' ); \rxdata_from_gtx_i_reg[13]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => pos_rxdata_from_gtx_i(13), Q => rxdata_from_gtx_i(13), R => '0' ); \rxdata_from_gtx_i_reg[14]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => pos_rxdata_from_gtx_i(14), Q => rxdata_from_gtx_i(14), R => '0' ); \rxdata_from_gtx_i_reg[15]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => pos_rxdata_from_gtx_i(15), Q => rxdata_from_gtx_i(15), R => '0' ); \rxdata_from_gtx_i_reg[16]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => pos_rxdata_from_gtx_i(16), Q => rxdata_from_gtx_i(16), R => '0' ); \rxdata_from_gtx_i_reg[17]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => pos_rxdata_from_gtx_i(17), Q => rxdata_from_gtx_i(17), R => '0' ); \rxdata_from_gtx_i_reg[18]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => pos_rxdata_from_gtx_i(18), Q => rxdata_from_gtx_i(18), R => '0' ); \rxdata_from_gtx_i_reg[19]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => pos_rxdata_from_gtx_i(19), Q => rxdata_from_gtx_i(19), R => '0' ); \rxdata_from_gtx_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => pos_rxdata_from_gtx_i(1), Q => rxdata_from_gtx_i(1), R => '0' ); \rxdata_from_gtx_i_reg[20]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => pos_rxdata_from_gtx_i(20), Q => rxdata_from_gtx_i(20), R => '0' ); \rxdata_from_gtx_i_reg[21]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => pos_rxdata_from_gtx_i(21), Q => rxdata_from_gtx_i(21), R => '0' ); \rxdata_from_gtx_i_reg[22]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => pos_rxdata_from_gtx_i(22), Q => rxdata_from_gtx_i(22), R => '0' ); \rxdata_from_gtx_i_reg[23]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => pos_rxdata_from_gtx_i(23), Q => rxdata_from_gtx_i(23), R => '0' ); \rxdata_from_gtx_i_reg[24]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => pos_rxdata_from_gtx_i(24), Q => rxdata_from_gtx_i(24), R => '0' ); \rxdata_from_gtx_i_reg[25]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => pos_rxdata_from_gtx_i(25), Q => rxdata_from_gtx_i(25), R => '0' ); \rxdata_from_gtx_i_reg[26]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => pos_rxdata_from_gtx_i(26), Q => rxdata_from_gtx_i(26), R => '0' ); \rxdata_from_gtx_i_reg[27]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => pos_rxdata_from_gtx_i(27), Q => rxdata_from_gtx_i(27), R => '0' ); \rxdata_from_gtx_i_reg[28]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => pos_rxdata_from_gtx_i(28), Q => rxdata_from_gtx_i(28), R => '0' ); \rxdata_from_gtx_i_reg[29]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => pos_rxdata_from_gtx_i(29), Q => rxdata_from_gtx_i(29), R => '0' ); \rxdata_from_gtx_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => pos_rxdata_from_gtx_i(2), Q => rxdata_from_gtx_i(2), R => '0' ); \rxdata_from_gtx_i_reg[30]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => pos_rxdata_from_gtx_i(30), Q => rxdata_from_gtx_i(30), R => '0' ); \rxdata_from_gtx_i_reg[31]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => pos_rxdata_from_gtx_i(31), Q => rxdata_from_gtx_i(31), R => '0' ); \rxdata_from_gtx_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => pos_rxdata_from_gtx_i(3), Q => rxdata_from_gtx_i(3), R => '0' ); \rxdata_from_gtx_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => pos_rxdata_from_gtx_i(4), Q => rxdata_from_gtx_i(4), R => '0' ); \rxdata_from_gtx_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => pos_rxdata_from_gtx_i(5), Q => rxdata_from_gtx_i(5), R => '0' ); \rxdata_from_gtx_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => pos_rxdata_from_gtx_i(6), Q => rxdata_from_gtx_i(6), R => '0' ); \rxdata_from_gtx_i_reg[7]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => pos_rxdata_from_gtx_i(7), Q => rxdata_from_gtx_i(7), R => '0' ); \rxdata_from_gtx_i_reg[8]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => pos_rxdata_from_gtx_i(8), Q => rxdata_from_gtx_i(8), R => '0' ); \rxdata_from_gtx_i_reg[9]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => pos_rxdata_from_gtx_i(9), Q => rxdata_from_gtx_i(9), R => '0' ); rxdatavalid_i_reg: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => pos_rxdatavalid_i, Q => rxdatavalid_i_0, R => '0' ); rxdatavalid_to_fifo_i_reg: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => rxdatavalid_i_0, Q => rxdatavalid_to_fifo_i, R => '0' ); \rxheader_from_gtx_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => pos_rxheader_from_gtx_i(0), Q => rxheader_from_gtx_i(0), R => '0' ); \rxheader_from_gtx_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => pos_rxheader_from_gtx_i(1), Q => rxheader_from_gtx_i(1), R => '0' ); \rxheader_to_fifo_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => rxheader_from_gtx_i(0), Q => rxheader_to_fifo_i(0), R => '0' ); \rxheader_to_fifo_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => rxheader_from_gtx_i(1), Q => rxheader_to_fifo_i(1), R => '0' ); rxheadervalid_i_reg: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => pos_rxheadervalid_i, Q => rxheadervalid_i, R => '0' ); rxlossofsync_out_q_reg: unisim.vcomponents.FDRE port map ( C => rxrecclk_to_fabric_i, CE => '1', D => rxlossofsync_out_i, Q => rxlossofsync_out_q, R => '0' ); rxrecclk_bufg_i: unisim.vcomponents.BUFGCTRL generic map( INIT_OUT => 0, PRESELECT_I0 => true, PRESELECT_I1 => false ) port map ( CE0 => rx_clk_locked_i, CE1 => '0', I0 => rxrecclk_from_gtx_i, I1 => '1', IGNORE0 => '0', IGNORE1 => '1', O => rxrecclk_to_fabric_i, S0 => '1', S1 => '0' ); rxreset_for_lanes_q_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => tx_reset_i, Q => rxreset_for_lanes_q, R => '0' ); rxresetfsm_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_RX_STARTUP_FSM port map ( AR(0) => rxfsm_reset_i, SR(0) => SR(0), fsm_resetdone_to_new_gtx_rx_comb => fsm_resetdone_to_new_gtx_rx_comb, gtrxreset_i_reg_0(0) => gtrxreset_t, in0 => rxreset_for_lanes_q, new_gtx_rx_pcsreset_comb0 => new_gtx_rx_pcsreset_comb0, \out\ => gtpll_locked_out_i, rx_clk_locked_i => rx_clk_locked_i, rx_fsm_resetdone_i => rx_fsm_resetdone_i, rxuserrdy_t => rxuserrdy_t, stg1_aurora_64b66b_0_cdc_to_reg => rx_resetdone_i, stg4_reg => stg4_reg, stg4_reg_0 => rxrecclk_to_fabric_i ); scrambler_64b66b_gtx0_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_SCRAMBLER_64B66B port map ( Q(6) => \txseq_counter_i_reg_n_0_[6]\, Q(5) => \txseq_counter_i_reg_n_0_[5]\, Q(4) => \txseq_counter_i_reg_n_0_[4]\, Q(3) => \txseq_counter_i_reg_n_0_[3]\, Q(2) => \txseq_counter_i_reg_n_0_[2]\, Q(1) => \txseq_counter_i_reg_n_0_[1]\, Q(0) => \txseq_counter_i_reg_n_0_[0]\, \SCRAMBLED_DATA_OUT_reg[63]_0\(63 downto 0) => scrambled_data_i(63 downto 0), \out\ => \out\, scrambler(11 downto 0) => scrambler(11 downto 0), tempData(5 downto 0) => tempData(5 downto 0), tx_data_i(57 downto 0) => tx_data_i(57 downto 0), \txseq_counter_i_reg[0]\ => scrambler_64b66b_gtx0_i_n_0 ); \tx_hdr_r_reg[0]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => D(0), Q => tx_hdr_r(0), R => '0' ); \tx_hdr_r_reg[1]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => D(1), Q => tx_hdr_r(1), R => '0' ); txresetfsm_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_TX_STARTUP_FSM port map ( CPLL_RESET_reg_0 => txresetfsm_i_n_6, MMCM_RESET_reg_0 => MMCM_RESET_reg, ack_flag => \aurora_64b66b_0_gtx_inst/ack_flag\, gt_cpllreset_i => gt_cpllreset_i, gttxreset_t => gttxreset_t, in0 => in0, \init_wait_count_reg[7]_0\ => \init_wait_count_reg[7]\, mmcm_reset_i => mmcm_reset_i, \out\ => gtpll_locked_out_i, stg1_aurora_64b66b_0_cdc_to_reg => tx_resetdone_i, stg4_reg => stg4_reg_0, stg5_reg => txusrclk_gtx_reset_comb, stg5_reg_0 => stg4_reg, tx_fsm_resetdone_i => tx_fsm_resetdone_i, txuserrdy_t => txuserrdy_t ); \txseq_counter_i[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0F0F0F0F0F0F0F0E" ) port map ( I0 => \txseq_counter_i_reg_n_0_[6]\, I1 => \txseq_counter_i[0]_i_2_n_0\, I2 => \txseq_counter_i_reg_n_0_[0]\, I3 => \txseq_counter_i_reg_n_0_[4]\, I4 => \txseq_counter_i_reg_n_0_[3]\, I5 => \txseq_counter_i_reg_n_0_[2]\, O => txseq_counter_i(0) ); \txseq_counter_i[0]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => \txseq_counter_i_reg_n_0_[1]\, I1 => \txseq_counter_i_reg_n_0_[5]\, O => \txseq_counter_i[0]_i_2_n_0\ ); \txseq_counter_i[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \txseq_counter_i_reg_n_0_[0]\, I1 => \txseq_counter_i_reg_n_0_[1]\, O => txseq_counter_i(1) ); \txseq_counter_i[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \txseq_counter_i_reg_n_0_[1]\, I1 => \txseq_counter_i_reg_n_0_[0]\, I2 => \txseq_counter_i_reg_n_0_[2]\, O => txseq_counter_i(2) ); \txseq_counter_i[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \txseq_counter_i_reg_n_0_[2]\, I1 => \txseq_counter_i_reg_n_0_[0]\, I2 => \txseq_counter_i_reg_n_0_[1]\, I3 => \txseq_counter_i_reg_n_0_[3]\, O => txseq_counter_i(3) ); \txseq_counter_i[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \txseq_counter_i_reg_n_0_[2]\, I1 => \txseq_counter_i_reg_n_0_[3]\, I2 => \txseq_counter_i_reg_n_0_[0]\, I3 => \txseq_counter_i_reg_n_0_[1]\, I4 => \txseq_counter_i_reg_n_0_[4]\, O => txseq_counter_i(4) ); \txseq_counter_i[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"CCCC3C3CCCC8CCC8" ) port map ( I0 => \txseq_counter_i[5]_i_2_n_0\, I1 => \txseq_counter_i_reg_n_0_[5]\, I2 => \txseq_counter_i_reg_n_0_[1]\, I3 => \txseq_counter_i_reg_n_0_[6]\, I4 => \txseq_counter_i[5]_i_3_n_0\, I5 => \txseq_counter_i_reg_n_0_[0]\, O => txseq_counter_i(5) ); \txseq_counter_i[5]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"FE" ) port map ( I0 => \txseq_counter_i_reg_n_0_[4]\, I1 => \txseq_counter_i_reg_n_0_[3]\, I2 => \txseq_counter_i_reg_n_0_[2]\, O => \txseq_counter_i[5]_i_2_n_0\ ); \txseq_counter_i[5]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => \txseq_counter_i_reg_n_0_[3]\, I1 => \txseq_counter_i_reg_n_0_[2]\, I2 => \txseq_counter_i_reg_n_0_[4]\, O => \txseq_counter_i[5]_i_3_n_0\ ); \txseq_counter_i[6]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FF7FFFFF00800000" ) port map ( I0 => \txseq_counter_i_reg_n_0_[3]\, I1 => \txseq_counter_i_reg_n_0_[2]\, I2 => \txseq_counter_i_reg_n_0_[4]\, I3 => scrambler_64b66b_gtx0_i_n_0, I4 => \txseq_counter_i_reg_n_0_[5]\, I5 => \txseq_counter_i_reg_n_0_[6]\, O => txseq_counter_i(6) ); \txseq_counter_i_reg[0]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => txseq_counter_i(0), Q => \txseq_counter_i_reg_n_0_[0]\, R => gtx_reset_comb ); \txseq_counter_i_reg[1]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => txseq_counter_i(1), Q => \txseq_counter_i_reg_n_0_[1]\, R => gtx_reset_comb ); \txseq_counter_i_reg[2]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => txseq_counter_i(2), Q => \txseq_counter_i_reg_n_0_[2]\, R => gtx_reset_comb ); \txseq_counter_i_reg[3]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => txseq_counter_i(3), Q => \txseq_counter_i_reg_n_0_[3]\, R => gtx_reset_comb ); \txseq_counter_i_reg[4]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => txseq_counter_i(4), Q => \txseq_counter_i_reg_n_0_[4]\, R => gtx_reset_comb ); \txseq_counter_i_reg[5]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => txseq_counter_i(5), Q => \txseq_counter_i_reg_n_0_[5]\, R => gtx_reset_comb ); \txseq_counter_i_reg[6]\: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => txseq_counter_i(6), Q => \txseq_counter_i_reg_n_0_[6]\, R => gtx_reset_comb ); \u_cdc__check_polarity\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync_6 port map ( Q(1 downto 0) => rxheader_from_gtx_i(1 downto 0), RX_NEG_OUT_reg => \^rx_neg_out_reg_0\, \out\ => rxrecclk_to_fabric_i, rxheadervalid_i => rxheadervalid_i, rxheadervalid_i_reg => \u_cdc__check_polarity_n_0\, s_level_out_d1_aurora_64b66b_0_cdc_to_reg_0 => s_level_out_d1_aurora_64b66b_0_cdc_to_reg ); u_cdc_gt_cplllock_i: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized1\ port map ( gt_pll_lock => gt_pll_lock, in0 => gt_cplllock_ii, mmcm_reset_i => mmcm_reset_i, \out\ => gtpll_locked_out_i, s_level_out_d5_reg_0 => stg4_reg ); u_cdc_hard_err_init: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized1_7\ port map ( E(0) => hard_err_cntr_r, Q(5 downto 2) => \hard_err_cntr_r_reg__0\(7 downto 4), Q(1 downto 0) => \hard_err_cntr_r_reg__0\(1 downto 0), SR(0) => HPCNT_RESET_IN, \hard_err_cntr_r_reg[0]\ => \hard_err_cntr_r[7]_i_5_n_0\, hard_err_rst_int => hard_err_rst_int, hard_err_rst_int_reg => u_cdc_hard_err_init_n_0, hard_err_rst_int_reg_0 => hard_err_rst_int_i_2_n_0, hard_err_rst_int_reg_1 => hard_err_rst_int_i_3_n_0, hard_err_rst_int_reg_2 => hard_err_rst_int_i_4_n_0, in0 => hard_err_usr, s_level_out_d6_reg_0 => stg4_reg ); u_cdc_rx_elastic_buferr: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized0\ port map ( RXBUFSTATUS(0) => int_rxbufstatus_i(2), \out\ => rx_elastic_buf_err, p_level_in_d1_cdc_from_reg_0 => rxrecclk_to_fabric_i, s_level_out_d6_reg_0 => \out\ ); \u_cdc_rxpolarity_\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_cdc_sync__parameterized2\ port map ( \out\ => sync_rx_polarity_r, s_level_out_d1_aurora_64b66b_0_cdc_to_reg_0 => s_level_out_d1_aurora_64b66b_0_cdc_to_reg_0, s_level_out_d6_reg_0 => rxrecclk_to_fabric_i ); u_rst_sync_blocksyncall_initclk_sync: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0\ port map ( \FSM_onehot_cdr_reset_fsm_r_reg[0]\ => u_rst_sync_blocksyncall_initclk_sync_n_2, \FSM_onehot_cdr_reset_fsm_r_reg[2]\ => u_rst_sync_blocksyncall_initclk_sync_n_0, \FSM_onehot_cdr_reset_fsm_r_reg[2]_0\ => u_rst_sync_blocksyncall_initclk_sync_n_1, \FSM_onehot_cdr_reset_fsm_r_reg[2]_1\ => \FSM_onehot_cdr_reset_fsm_r_reg_n_0_[0]\, \FSM_onehot_cdr_reset_fsm_r_reg[2]_2\ => \FSM_onehot_cdr_reset_fsm_r[2]_i_2_n_0\, allow_block_sync_propagation => allow_block_sync_propagation, cdr_reset_fsm_lnkreset => cdr_reset_fsm_lnkreset, in0 => blocksync_all_lanes_inrxclk_q, p_2_in => p_2_in, stg4_reg_0 => stg4_reg ); u_rst_sync_blocksyncprop_inrxclk_sync: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_8\ port map ( blocksync_out_i => blocksync_out_i, \out\ => rxrecclk_to_fabric_i, rxlossofsync_out_i => rxlossofsync_out_i, stg1_aurora_64b66b_0_cdc_to_reg_0 => allow_block_sync_propagation_reg_n_0 ); u_rst_sync_fsm_resetdone: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_9\ port map ( fsm_resetdone_to_new_gtx_rx_comb => fsm_resetdone_to_new_gtx_rx_comb, \out\ => rxrecclk_to_fabric_i, stg1_aurora_64b66b_0_cdc_to_reg_0 => \^fsm_resetdone_reg_0\ ); u_rst_sync_gtx_reset_comb: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_10\ port map ( SR(0) => gtx_reset_comb, in0 => stableclk_gtx_reset_comb, \out\ => \out\ ); u_rst_sync_reset_initclk: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_11\ port map ( SR(0) => SR(0), \hard_err_cntr_r_reg[7]\ => \^fsm_resetdone_reg_0\, \hard_err_cntr_r_reg[7]_0\ => \init_wait_count_reg[7]\, \hard_err_cntr_r_reg[7]_1\ => cdr_reset_fsm_lnkreset_reg_n_0, \out\ => rxfsm_reset_i, reset_initclk => reset_initclk, stg5_reg_0(0) => HPCNT_RESET_IN, stg5_reg_1 => stg4_reg ); u_rst_sync_txusrclk_gtx_reset_comb: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync__parameterized0_12\ port map ( in0 => stableclk_gtx_reset_comb, stg1_aurora_64b66b_0_cdc_to_reg_0 => txusrclk_gtx_reset_comb, stg4_reg_0 => stg4_reg ); \unscrambled_data_i[13]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"96" ) port map ( I0 => poly(52), I1 => rxdata_from_gtx_i(13), I2 => descrambler_64b66b_gtx0_i_n_36, O => unscrambled_data_i052_out ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_core is port ( link_reset_out : out STD_LOGIC; lane_up_flop_i : out STD_LOGIC; SYSTEM_RESET_reg : out STD_LOGIC; drprdy_out : out STD_LOGIC; txn : out STD_LOGIC; txp : out STD_LOGIC; tx_out_clk : out STD_LOGIC; drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); CHANNEL_UP_RX_IF_reg : out STD_LOGIC; hard_err : out STD_LOGIC; soft_err : out STD_LOGIC; m_axi_rx_tvalid : out STD_LOGIC; s_axi_tx_tready : out STD_LOGIC; m_axi_rx_tdata : out STD_LOGIC_VECTOR ( 0 to 63 ); MMCM_RESET_reg : out STD_LOGIC; gt_pll_lock : out STD_LOGIC; power_down : in STD_LOGIC; sysreset_from_support : in STD_LOGIC; \out\ : in STD_LOGIC; stg1_aurora_64b66b_0_cdc_to_reg : in STD_LOGIC; in0 : in STD_LOGIC; stg4_reg : in STD_LOGIC; drp_clk_in : in STD_LOGIC; drpen_in : in STD_LOGIC; drpwe_in : in STD_LOGIC; refclk1_in : in STD_LOGIC; rxn : in STD_LOGIC; rxp : in STD_LOGIC; gt_qpllclk_quad1_out : in STD_LOGIC; gt_qpllrefclk_quad1_out : in STD_LOGIC; gt_rxcdrovrden_in : in STD_LOGIC; stg4_reg_0 : in STD_LOGIC; drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); loopback : in STD_LOGIC_VECTOR ( 2 downto 0 ); drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 ); s_axi_tx_tvalid : in STD_LOGIC; s_axi_tx_tdata : in STD_LOGIC_VECTOR ( 0 to 63 ) ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_core; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_core is signal \^channel_up_rx_if_reg\ : STD_LOGIC; signal RX_IDLE : STD_LOGIC; signal RX_PE_DATA : STD_LOGIC_VECTOR ( 0 to 63 ); signal \^system_reset_reg\ : STD_LOGIC; signal TXDATAVALID_IN : STD_LOGIC; signal TXHEADER_IN : STD_LOGIC_VECTOR ( 1 downto 0 ); signal TX_PE_DATA : STD_LOGIC_VECTOR ( 0 to 63 ); signal aurora_64b66b_0_wrapper_i_n_100 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_101 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_102 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_103 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_90 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_91 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_93 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_95 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_97 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_98 : STD_LOGIC; signal aurora_64b66b_0_wrapper_i_n_99 : STD_LOGIC; signal aurora_lane_0_i_n_13 : STD_LOGIC; signal \cbcc_gtx0_i/fifo_dout_i\ : STD_LOGIC_VECTOR ( 65 downto 0 ); signal \channel_init_sm_i/reset_lanes_c\ : STD_LOGIC; signal channel_up_tx_if : STD_LOGIC; signal check_polarity_i : STD_LOGIC; signal core_reset_logic_i_n_1 : STD_LOGIC; signal do_cc_i : STD_LOGIC; signal enable_err_detect_i : STD_LOGIC; signal fsm_resetdone : STD_LOGIC; signal gen_cc_i : STD_LOGIC; signal gen_ch_bond_i : STD_LOGIC; signal gen_na_idles_i : STD_LOGIC; signal global_logic_i_n_11 : STD_LOGIC; signal global_logic_i_n_6 : STD_LOGIC; signal global_logic_i_n_7 : STD_LOGIC; signal global_logic_i_n_8 : STD_LOGIC; signal global_logic_i_n_9 : STD_LOGIC; signal hard_err_i : STD_LOGIC; signal illegal_btf_i : STD_LOGIC; signal \lane_init_sm_i/ready_r_reg0\ : STD_LOGIC; signal \lane_init_sm_i/reset_count_r0\ : STD_LOGIC; signal \^lane_up_flop_i\ : STD_LOGIC; signal \^link_reset_out\ : STD_LOGIC; signal remote_ready_i : STD_LOGIC; signal reset_lanes_i : STD_LOGIC; signal rx_lossofsync_i : STD_LOGIC; signal rx_neg_i : STD_LOGIC; signal rx_pe_data_v_i : STD_LOGIC; signal rx_polarity_i : STD_LOGIC; signal \rx_stream_datapath_i/RX_D0\ : STD_LOGIC; signal rxdatavalid_i : STD_LOGIC; signal \scrambler_64b66b_gtx0_i/p_153_in\ : STD_LOGIC; signal \scrambler_64b66b_gtx0_i/p_157_in\ : STD_LOGIC; signal \scrambler_64b66b_gtx0_i/p_161_in\ : STD_LOGIC; signal \scrambler_64b66b_gtx0_i/p_165_in\ : STD_LOGIC; signal \scrambler_64b66b_gtx0_i/p_169_in\ : STD_LOGIC; signal \scrambler_64b66b_gtx0_i/p_173_in\ : STD_LOGIC; signal \scrambler_64b66b_gtx0_i/tempData0\ : STD_LOGIC; signal \scrambler_64b66b_gtx0_i/tempData012_out\ : STD_LOGIC; signal \scrambler_64b66b_gtx0_i/tempData016_out\ : STD_LOGIC; signal \scrambler_64b66b_gtx0_i/tempData020_out\ : STD_LOGIC; signal \scrambler_64b66b_gtx0_i/tempData04_out\ : STD_LOGIC; signal \scrambler_64b66b_gtx0_i/tempData08_out\ : STD_LOGIC; signal standard_cc_module_i_n_0 : STD_LOGIC; signal \sym_gen_i/rst_pma_init_usrclk\ : STD_LOGIC; signal tx_data_i : STD_LOGIC_VECTOR ( 0 to 57 ); signal tx_pe_data_v_i : STD_LOGIC; signal tx_reset_i : STD_LOGIC; signal \tx_stream_control_sm_i/R0\ : STD_LOGIC; signal \tx_stream_control_sm_i/do_cc_r\ : STD_LOGIC; signal \tx_stream_control_sm_i/do_cc_r_reg0\ : STD_LOGIC; signal \tx_stream_control_sm_i/extend_cc_r\ : STD_LOGIC; signal tx_stream_i_n_5 : STD_LOGIC; signal tx_stream_i_n_6 : STD_LOGIC; signal tx_stream_i_n_7 : STD_LOGIC; signal txdatavalid_symgen_i : STD_LOGIC; begin CHANNEL_UP_RX_IF_reg <= \^channel_up_rx_if_reg\; SYSTEM_RESET_reg <= \^system_reset_reg\; lane_up_flop_i <= \^lane_up_flop_i\; link_reset_out <= \^link_reset_out\; aurora_64b66b_0_wrapper_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_WRAPPER port map ( D(1 downto 0) => TXHEADER_IN(1 downto 0), FSM_RESETDONE_reg_0 => fsm_resetdone, ILLEGAL_BTF_reg => aurora_64b66b_0_wrapper_i_n_95, MMCM_RESET_reg => MMCM_RESET_reg, Q => do_cc_i, RX_NEG_OUT_reg_0 => rx_neg_i, SR(0) => \^system_reset_reg\, TXDATAVALID_IN => TXDATAVALID_IN, channel_up_tx_if => channel_up_tx_if, drp_clk_in => drp_clk_in, drpaddr_in(8 downto 0) => drpaddr_in(8 downto 0), drpdi_in(15 downto 0) => drpdi_in(15 downto 0), drpdo_out(15 downto 0) => drpdo_out(15 downto 0), drpen_in => drpen_in, drprdy_out => drprdy_out, drpwe_in => drpwe_in, enable_err_detect_i => enable_err_detect_i, extend_cc_r => \tx_stream_control_sm_i/extend_cc_r\, gt_pll_lock => gt_pll_lock, gt_qpllclk_quad1_out => gt_qpllclk_quad1_out, gt_qpllrefclk_quad1_out => gt_qpllrefclk_quad1_out, gt_rxcdrovrden_in => gt_rxcdrovrden_in, hard_err_usr_reg_0 => \^channel_up_rx_if_reg\, hold_reg_reg => aurora_64b66b_0_wrapper_i_n_90, illegal_btf_i => illegal_btf_i, in0 => in0, \init_wait_count_reg[7]\ => stg1_aurora_64b66b_0_cdc_to_reg, link_reset_out => \^link_reset_out\, loopback(2 downto 0) => loopback(2 downto 0), master_do_rd_en_out_reg(65 downto 0) => \cbcc_gtx0_i/fifo_dout_i\(65 downto 0), \out\ => \out\, refclk1_in => refclk1_in, rst_pma_init_usrclk => \sym_gen_i/rst_pma_init_usrclk\, rx_lossofsync_i => rx_lossofsync_i, rxdatavalid_i => rxdatavalid_i, rxn => rxn, rxp => rxp, s_level_out_d1_aurora_64b66b_0_cdc_to_reg => check_polarity_i, s_level_out_d1_aurora_64b66b_0_cdc_to_reg_0 => rx_polarity_i, scrambler(11) => aurora_64b66b_0_wrapper_i_n_98, scrambler(10) => aurora_64b66b_0_wrapper_i_n_99, scrambler(9) => aurora_64b66b_0_wrapper_i_n_100, scrambler(8) => aurora_64b66b_0_wrapper_i_n_101, scrambler(7) => aurora_64b66b_0_wrapper_i_n_102, scrambler(6) => aurora_64b66b_0_wrapper_i_n_103, scrambler(5) => \scrambler_64b66b_gtx0_i/p_173_in\, scrambler(4) => \scrambler_64b66b_gtx0_i/p_169_in\, scrambler(3) => \scrambler_64b66b_gtx0_i/p_165_in\, scrambler(2) => \scrambler_64b66b_gtx0_i/p_161_in\, scrambler(1) => \scrambler_64b66b_gtx0_i/p_157_in\, scrambler(0) => \scrambler_64b66b_gtx0_i/p_153_in\, stg4_reg => stg4_reg, stg4_reg_0 => stg4_reg_0, tempData(5) => \scrambler_64b66b_gtx0_i/tempData020_out\, tempData(4) => \scrambler_64b66b_gtx0_i/tempData016_out\, tempData(3) => \scrambler_64b66b_gtx0_i/tempData012_out\, tempData(2) => \scrambler_64b66b_gtx0_i/tempData08_out\, tempData(1) => \scrambler_64b66b_gtx0_i/tempData04_out\, tempData(0) => \scrambler_64b66b_gtx0_i/tempData0\, tx_data_i(57) => tx_data_i(0), tx_data_i(56) => tx_data_i(1), tx_data_i(55) => tx_data_i(2), tx_data_i(54) => tx_data_i(3), tx_data_i(53) => tx_data_i(4), tx_data_i(52) => tx_data_i(5), tx_data_i(51) => tx_data_i(6), tx_data_i(50) => tx_data_i(7), tx_data_i(49) => tx_data_i(8), tx_data_i(48) => tx_data_i(9), tx_data_i(47) => tx_data_i(10), tx_data_i(46) => tx_data_i(11), tx_data_i(45) => tx_data_i(12), tx_data_i(44) => tx_data_i(13), tx_data_i(43) => tx_data_i(14), tx_data_i(42) => tx_data_i(15), tx_data_i(41) => tx_data_i(16), tx_data_i(40) => tx_data_i(17), tx_data_i(39) => tx_data_i(18), tx_data_i(38) => tx_data_i(19), tx_data_i(37) => tx_data_i(20), tx_data_i(36) => tx_data_i(21), tx_data_i(35) => tx_data_i(22), tx_data_i(34) => tx_data_i(23), tx_data_i(33) => tx_data_i(24), tx_data_i(32) => tx_data_i(25), tx_data_i(31) => tx_data_i(26), tx_data_i(30) => tx_data_i(27), tx_data_i(29) => tx_data_i(28), tx_data_i(28) => tx_data_i(29), tx_data_i(27) => tx_data_i(30), tx_data_i(26) => tx_data_i(31), tx_data_i(25) => tx_data_i(32), tx_data_i(24) => tx_data_i(33), tx_data_i(23) => tx_data_i(34), tx_data_i(22) => tx_data_i(35), tx_data_i(21) => tx_data_i(36), tx_data_i(20) => tx_data_i(37), tx_data_i(19) => tx_data_i(38), tx_data_i(18) => tx_data_i(39), tx_data_i(17) => tx_data_i(40), tx_data_i(16) => tx_data_i(41), tx_data_i(15) => tx_data_i(42), tx_data_i(14) => tx_data_i(43), tx_data_i(13) => tx_data_i(44), tx_data_i(12) => tx_data_i(45), tx_data_i(11) => tx_data_i(46), tx_data_i(10) => tx_data_i(47), tx_data_i(9) => tx_data_i(48), tx_data_i(8) => tx_data_i(49), tx_data_i(7) => tx_data_i(50), tx_data_i(6) => tx_data_i(51), tx_data_i(5) => tx_data_i(52), tx_data_i(4) => tx_data_i(53), tx_data_i(3) => tx_data_i(54), tx_data_i(2) => tx_data_i(55), tx_data_i(1) => tx_data_i(56), tx_data_i(0) => tx_data_i(57), tx_out_clk => tx_out_clk, tx_reset_i => tx_reset_i, txdatavalid_symgen_i => txdatavalid_symgen_i, txn => txn, txp => txp, \txseq_counter_i_reg[0]_0\ => aurora_64b66b_0_wrapper_i_n_91, \txseq_counter_i_reg[1]_0\ => aurora_64b66b_0_wrapper_i_n_93, wr_err_rd_clk_sync_reg => aurora_64b66b_0_wrapper_i_n_97 ); aurora_lane_0_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_AURORA_LANE port map ( D(1 downto 0) => TXHEADER_IN(1 downto 0), HARD_ERR_reg => aurora_64b66b_0_wrapper_i_n_97, Q(59) => TX_PE_DATA(0), Q(58) => TX_PE_DATA(1), Q(57) => TX_PE_DATA(2), Q(56) => TX_PE_DATA(3), Q(55) => TX_PE_DATA(4), Q(54) => TX_PE_DATA(5), Q(53) => TX_PE_DATA(6), Q(52) => TX_PE_DATA(7), Q(51) => TX_PE_DATA(8), Q(50) => TX_PE_DATA(9), Q(49) => TX_PE_DATA(10), Q(48) => TX_PE_DATA(11), Q(47) => TX_PE_DATA(12), Q(46) => TX_PE_DATA(13), Q(45) => TX_PE_DATA(14), Q(44) => TX_PE_DATA(15), Q(43) => TX_PE_DATA(16), Q(42) => TX_PE_DATA(17), Q(41) => TX_PE_DATA(18), Q(40) => TX_PE_DATA(19), Q(39) => TX_PE_DATA(20), Q(38) => TX_PE_DATA(21), Q(37) => TX_PE_DATA(22), Q(36) => TX_PE_DATA(23), Q(35) => TX_PE_DATA(24), Q(34) => TX_PE_DATA(25), Q(33) => TX_PE_DATA(26), Q(32) => TX_PE_DATA(27), Q(31) => TX_PE_DATA(28), Q(30) => TX_PE_DATA(29), Q(29) => TX_PE_DATA(30), Q(28) => TX_PE_DATA(31), Q(27) => TX_PE_DATA(32), Q(26) => TX_PE_DATA(33), Q(25) => TX_PE_DATA(34), Q(24) => TX_PE_DATA(35), Q(23) => TX_PE_DATA(36), Q(22) => TX_PE_DATA(37), Q(21) => TX_PE_DATA(38), Q(20) => TX_PE_DATA(39), Q(19) => TX_PE_DATA(40), Q(18) => TX_PE_DATA(41), Q(17) => TX_PE_DATA(42), Q(16) => TX_PE_DATA(43), Q(15) => TX_PE_DATA(44), Q(14) => TX_PE_DATA(45), Q(13) => TX_PE_DATA(46), Q(12) => TX_PE_DATA(47), Q(11) => TX_PE_DATA(52), Q(10) => TX_PE_DATA(53), Q(9) => TX_PE_DATA(54), Q(8) => TX_PE_DATA(55), Q(7) => TX_PE_DATA(56), Q(6) => TX_PE_DATA(57), Q(5) => TX_PE_DATA(58), Q(4) => TX_PE_DATA(59), Q(3) => TX_PE_DATA(60), Q(2) => TX_PE_DATA(61), Q(1) => TX_PE_DATA(62), Q(0) => TX_PE_DATA(63), \RX_DATA_REG_reg[0]\ => aurora_64b66b_0_wrapper_i_n_90, RX_HEADER_1_REG_reg(65 downto 0) => \cbcc_gtx0_i/fifo_dout_i\(65 downto 0), RX_IDLE => RX_IDLE, \RX_PE_DATA_reg[0]\(63) => RX_PE_DATA(0), \RX_PE_DATA_reg[0]\(62) => RX_PE_DATA(1), \RX_PE_DATA_reg[0]\(61) => RX_PE_DATA(2), \RX_PE_DATA_reg[0]\(60) => RX_PE_DATA(3), \RX_PE_DATA_reg[0]\(59) => RX_PE_DATA(4), \RX_PE_DATA_reg[0]\(58) => RX_PE_DATA(5), \RX_PE_DATA_reg[0]\(57) => RX_PE_DATA(6), \RX_PE_DATA_reg[0]\(56) => RX_PE_DATA(7), \RX_PE_DATA_reg[0]\(55) => RX_PE_DATA(8), \RX_PE_DATA_reg[0]\(54) => RX_PE_DATA(9), \RX_PE_DATA_reg[0]\(53) => RX_PE_DATA(10), \RX_PE_DATA_reg[0]\(52) => RX_PE_DATA(11), \RX_PE_DATA_reg[0]\(51) => RX_PE_DATA(12), \RX_PE_DATA_reg[0]\(50) => RX_PE_DATA(13), \RX_PE_DATA_reg[0]\(49) => RX_PE_DATA(14), \RX_PE_DATA_reg[0]\(48) => RX_PE_DATA(15), \RX_PE_DATA_reg[0]\(47) => RX_PE_DATA(16), \RX_PE_DATA_reg[0]\(46) => RX_PE_DATA(17), \RX_PE_DATA_reg[0]\(45) => RX_PE_DATA(18), \RX_PE_DATA_reg[0]\(44) => RX_PE_DATA(19), \RX_PE_DATA_reg[0]\(43) => RX_PE_DATA(20), \RX_PE_DATA_reg[0]\(42) => RX_PE_DATA(21), \RX_PE_DATA_reg[0]\(41) => RX_PE_DATA(22), \RX_PE_DATA_reg[0]\(40) => RX_PE_DATA(23), \RX_PE_DATA_reg[0]\(39) => RX_PE_DATA(24), \RX_PE_DATA_reg[0]\(38) => RX_PE_DATA(25), \RX_PE_DATA_reg[0]\(37) => RX_PE_DATA(26), \RX_PE_DATA_reg[0]\(36) => RX_PE_DATA(27), \RX_PE_DATA_reg[0]\(35) => RX_PE_DATA(28), \RX_PE_DATA_reg[0]\(34) => RX_PE_DATA(29), \RX_PE_DATA_reg[0]\(33) => RX_PE_DATA(30), \RX_PE_DATA_reg[0]\(32) => RX_PE_DATA(31), \RX_PE_DATA_reg[0]\(31) => RX_PE_DATA(32), \RX_PE_DATA_reg[0]\(30) => RX_PE_DATA(33), \RX_PE_DATA_reg[0]\(29) => RX_PE_DATA(34), \RX_PE_DATA_reg[0]\(28) => RX_PE_DATA(35), \RX_PE_DATA_reg[0]\(27) => RX_PE_DATA(36), \RX_PE_DATA_reg[0]\(26) => RX_PE_DATA(37), \RX_PE_DATA_reg[0]\(25) => RX_PE_DATA(38), \RX_PE_DATA_reg[0]\(24) => RX_PE_DATA(39), \RX_PE_DATA_reg[0]\(23) => RX_PE_DATA(40), \RX_PE_DATA_reg[0]\(22) => RX_PE_DATA(41), \RX_PE_DATA_reg[0]\(21) => RX_PE_DATA(42), \RX_PE_DATA_reg[0]\(20) => RX_PE_DATA(43), \RX_PE_DATA_reg[0]\(19) => RX_PE_DATA(44), \RX_PE_DATA_reg[0]\(18) => RX_PE_DATA(45), \RX_PE_DATA_reg[0]\(17) => RX_PE_DATA(46), \RX_PE_DATA_reg[0]\(16) => RX_PE_DATA(47), \RX_PE_DATA_reg[0]\(15) => RX_PE_DATA(48), \RX_PE_DATA_reg[0]\(14) => RX_PE_DATA(49), \RX_PE_DATA_reg[0]\(13) => RX_PE_DATA(50), \RX_PE_DATA_reg[0]\(12) => RX_PE_DATA(51), \RX_PE_DATA_reg[0]\(11) => RX_PE_DATA(52), \RX_PE_DATA_reg[0]\(10) => RX_PE_DATA(53), \RX_PE_DATA_reg[0]\(9) => RX_PE_DATA(54), \RX_PE_DATA_reg[0]\(8) => RX_PE_DATA(55), \RX_PE_DATA_reg[0]\(7) => RX_PE_DATA(56), \RX_PE_DATA_reg[0]\(6) => RX_PE_DATA(57), \RX_PE_DATA_reg[0]\(5) => RX_PE_DATA(58), \RX_PE_DATA_reg[0]\(4) => RX_PE_DATA(59), \RX_PE_DATA_reg[0]\(3) => RX_PE_DATA(60), \RX_PE_DATA_reg[0]\(2) => RX_PE_DATA(61), \RX_PE_DATA_reg[0]\(1) => RX_PE_DATA(62), \RX_PE_DATA_reg[0]\(0) => RX_PE_DATA(63), SOFT_ERR_reg => aurora_lane_0_i_n_13, SOFT_ERR_reg_0 => aurora_64b66b_0_wrapper_i_n_95, SR(0) => \^system_reset_reg\, \TX_DATA_reg[55]\(3) => global_logic_i_n_8, \TX_DATA_reg[55]\(2) => global_logic_i_n_9, \TX_DATA_reg[55]\(1) => tx_stream_i_n_5, \TX_DATA_reg[55]\(0) => tx_stream_i_n_6, \TX_DATA_reg[59]\ => aurora_64b66b_0_wrapper_i_n_93, \TX_DATA_reg[63]\(57) => tx_data_i(0), \TX_DATA_reg[63]\(56) => tx_data_i(1), \TX_DATA_reg[63]\(55) => tx_data_i(2), \TX_DATA_reg[63]\(54) => tx_data_i(3), \TX_DATA_reg[63]\(53) => tx_data_i(4), \TX_DATA_reg[63]\(52) => tx_data_i(5), \TX_DATA_reg[63]\(51) => tx_data_i(6), \TX_DATA_reg[63]\(50) => tx_data_i(7), \TX_DATA_reg[63]\(49) => tx_data_i(8), \TX_DATA_reg[63]\(48) => tx_data_i(9), \TX_DATA_reg[63]\(47) => tx_data_i(10), \TX_DATA_reg[63]\(46) => tx_data_i(11), \TX_DATA_reg[63]\(45) => tx_data_i(12), \TX_DATA_reg[63]\(44) => tx_data_i(13), \TX_DATA_reg[63]\(43) => tx_data_i(14), \TX_DATA_reg[63]\(42) => tx_data_i(15), \TX_DATA_reg[63]\(41) => tx_data_i(16), \TX_DATA_reg[63]\(40) => tx_data_i(17), \TX_DATA_reg[63]\(39) => tx_data_i(18), \TX_DATA_reg[63]\(38) => tx_data_i(19), \TX_DATA_reg[63]\(37) => tx_data_i(20), \TX_DATA_reg[63]\(36) => tx_data_i(21), \TX_DATA_reg[63]\(35) => tx_data_i(22), \TX_DATA_reg[63]\(34) => tx_data_i(23), \TX_DATA_reg[63]\(33) => tx_data_i(24), \TX_DATA_reg[63]\(32) => tx_data_i(25), \TX_DATA_reg[63]\(31) => tx_data_i(26), \TX_DATA_reg[63]\(30) => tx_data_i(27), \TX_DATA_reg[63]\(29) => tx_data_i(28), \TX_DATA_reg[63]\(28) => tx_data_i(29), \TX_DATA_reg[63]\(27) => tx_data_i(30), \TX_DATA_reg[63]\(26) => tx_data_i(31), \TX_DATA_reg[63]\(25) => tx_data_i(32), \TX_DATA_reg[63]\(24) => tx_data_i(33), \TX_DATA_reg[63]\(23) => tx_data_i(34), \TX_DATA_reg[63]\(22) => tx_data_i(35), \TX_DATA_reg[63]\(21) => tx_data_i(36), \TX_DATA_reg[63]\(20) => tx_data_i(37), \TX_DATA_reg[63]\(19) => tx_data_i(38), \TX_DATA_reg[63]\(18) => tx_data_i(39), \TX_DATA_reg[63]\(17) => tx_data_i(40), \TX_DATA_reg[63]\(16) => tx_data_i(41), \TX_DATA_reg[63]\(15) => tx_data_i(42), \TX_DATA_reg[63]\(14) => tx_data_i(43), \TX_DATA_reg[63]\(13) => tx_data_i(44), \TX_DATA_reg[63]\(12) => tx_data_i(45), \TX_DATA_reg[63]\(11) => tx_data_i(46), \TX_DATA_reg[63]\(10) => tx_data_i(47), \TX_DATA_reg[63]\(9) => tx_data_i(48), \TX_DATA_reg[63]\(8) => tx_data_i(49), \TX_DATA_reg[63]\(7) => tx_data_i(50), \TX_DATA_reg[63]\(6) => tx_data_i(51), \TX_DATA_reg[63]\(5) => tx_data_i(52), \TX_DATA_reg[63]\(4) => tx_data_i(53), \TX_DATA_reg[63]\(3) => tx_data_i(54), \TX_DATA_reg[63]\(2) => tx_data_i(55), \TX_DATA_reg[63]\(1) => tx_data_i(56), \TX_DATA_reg[63]\(0) => tx_data_i(57), \TX_DATA_reg[63]_0\ => global_logic_i_n_6, TX_HEADER_1_reg => tx_stream_i_n_7, channel_up_tx_if => channel_up_tx_if, check_polarity_r_reg => check_polarity_i, enable_err_detect_i => enable_err_detect_i, gen_cc_i => gen_cc_i, gen_ch_bond_i => gen_ch_bond_i, gen_na_idles_i => gen_na_idles_i, hard_err_i => hard_err_i, illegal_btf_i => illegal_btf_i, lane_up_flop_i => \^lane_up_flop_i\, \out\ => \out\, ready_r_reg0 => \lane_init_sm_i/ready_r_reg0\, remote_ready_i => remote_ready_i, reset_count_r0 => \lane_init_sm_i/reset_count_r0\, reset_lanes_c => \channel_init_sm_i/reset_lanes_c\, reset_lanes_i => reset_lanes_i, rst_pma_init_usrclk => \sym_gen_i/rst_pma_init_usrclk\, rx_lossofsync_i => rx_lossofsync_i, rx_pe_data_v_i => rx_pe_data_v_i, rx_polarity_r_reg => rx_polarity_i, rxdatavalid_i => rxdatavalid_i, s_level_out_d1_aurora_64b66b_0_cdc_to_reg => rx_neg_i, scrambler(11) => aurora_64b66b_0_wrapper_i_n_98, scrambler(10) => aurora_64b66b_0_wrapper_i_n_99, scrambler(9) => aurora_64b66b_0_wrapper_i_n_100, scrambler(8) => aurora_64b66b_0_wrapper_i_n_101, scrambler(7) => aurora_64b66b_0_wrapper_i_n_102, scrambler(6) => aurora_64b66b_0_wrapper_i_n_103, scrambler(5) => \scrambler_64b66b_gtx0_i/p_173_in\, scrambler(4) => \scrambler_64b66b_gtx0_i/p_169_in\, scrambler(3) => \scrambler_64b66b_gtx0_i/p_165_in\, scrambler(2) => \scrambler_64b66b_gtx0_i/p_161_in\, scrambler(1) => \scrambler_64b66b_gtx0_i/p_157_in\, scrambler(0) => \scrambler_64b66b_gtx0_i/p_153_in\, stg1_aurora_64b66b_0_cdc_to_reg => stg1_aurora_64b66b_0_cdc_to_reg, tempData(5) => \scrambler_64b66b_gtx0_i/tempData020_out\, tempData(4) => \scrambler_64b66b_gtx0_i/tempData016_out\, tempData(3) => \scrambler_64b66b_gtx0_i/tempData012_out\, tempData(2) => \scrambler_64b66b_gtx0_i/tempData08_out\, tempData(1) => \scrambler_64b66b_gtx0_i/tempData04_out\, tempData(0) => \scrambler_64b66b_gtx0_i/tempData0\, tx_pe_data_v_i => tx_pe_data_v_i, tx_reset_i => tx_reset_i, txdatavalid_symgen_i => txdatavalid_symgen_i ); core_reset_logic_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_RESET_LOGIC port map ( SR(0) => \^system_reset_reg\, SYSTEM_RESET_reg_0 => core_reset_logic_i_n_1, hard_err_i => hard_err_i, link_reset_out => \^link_reset_out\, \out\ => \out\, power_down => power_down, ready_r_reg0 => \lane_init_sm_i/ready_r_reg0\, reset_count_r0 => \lane_init_sm_i/reset_count_r0\, stg1_aurora_64b66b_0_cdc_to_reg => fsm_resetdone, sysreset_from_support => sysreset_from_support, tx_reset_i => tx_reset_i, wait_for_lane_up_r_reg => \^lane_up_flop_i\ ); global_logic_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_GLOBAL_LOGIC port map ( CHANNEL_UP_RX_IF_reg => \^channel_up_rx_if_reg\, CHANNEL_UP_RX_IF_reg_0 => global_logic_i_n_7, CHANNEL_UP_RX_IF_reg_1 => global_logic_i_n_11, CHANNEL_UP_RX_IF_reg_2(0) => \^system_reset_reg\, E(0) => \rx_stream_datapath_i/RX_D0\, Q(1) => TX_PE_DATA(48), Q(0) => TX_PE_DATA(49), R0 => \tx_stream_control_sm_i/R0\, RX_IDLE => RX_IDLE, SR(0) => reset_lanes_i, TXDATAVALID_IN => TXDATAVALID_IN, \TX_DATA_reg[63]\ => aurora_64b66b_0_wrapper_i_n_93, channel_up_tx_if => channel_up_tx_if, gen_cc_flop_0_i(1) => global_logic_i_n_8, gen_cc_flop_0_i(0) => global_logic_i_n_9, gen_cc_i => gen_cc_i, gen_ch_bond_i => gen_ch_bond_i, gen_ch_bond_int_reg => global_logic_i_n_6, gen_na_idles_i => gen_na_idles_i, hard_err => hard_err, hard_err_i => hard_err_i, \out\ => \out\, ready_r_reg => \^lane_up_flop_i\, remote_ready_i => remote_ready_i, reset_lanes_c => \channel_init_sm_i/reset_lanes_c\, rst_pma_init_usrclk => \sym_gen_i/rst_pma_init_usrclk\, rx_pe_data_v_i => rx_pe_data_v_i, tx_pe_data_v_i => tx_pe_data_v_i, wait_for_lane_up_r_reg => core_reset_logic_i_n_1 ); rx_stream_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_RX_STREAM port map ( D(63) => RX_PE_DATA(0), D(62) => RX_PE_DATA(1), D(61) => RX_PE_DATA(2), D(60) => RX_PE_DATA(3), D(59) => RX_PE_DATA(4), D(58) => RX_PE_DATA(5), D(57) => RX_PE_DATA(6), D(56) => RX_PE_DATA(7), D(55) => RX_PE_DATA(8), D(54) => RX_PE_DATA(9), D(53) => RX_PE_DATA(10), D(52) => RX_PE_DATA(11), D(51) => RX_PE_DATA(12), D(50) => RX_PE_DATA(13), D(49) => RX_PE_DATA(14), D(48) => RX_PE_DATA(15), D(47) => RX_PE_DATA(16), D(46) => RX_PE_DATA(17), D(45) => RX_PE_DATA(18), D(44) => RX_PE_DATA(19), D(43) => RX_PE_DATA(20), D(42) => RX_PE_DATA(21), D(41) => RX_PE_DATA(22), D(40) => RX_PE_DATA(23), D(39) => RX_PE_DATA(24), D(38) => RX_PE_DATA(25), D(37) => RX_PE_DATA(26), D(36) => RX_PE_DATA(27), D(35) => RX_PE_DATA(28), D(34) => RX_PE_DATA(29), D(33) => RX_PE_DATA(30), D(32) => RX_PE_DATA(31), D(31) => RX_PE_DATA(32), D(30) => RX_PE_DATA(33), D(29) => RX_PE_DATA(34), D(28) => RX_PE_DATA(35), D(27) => RX_PE_DATA(36), D(26) => RX_PE_DATA(37), D(25) => RX_PE_DATA(38), D(24) => RX_PE_DATA(39), D(23) => RX_PE_DATA(40), D(22) => RX_PE_DATA(41), D(21) => RX_PE_DATA(42), D(20) => RX_PE_DATA(43), D(19) => RX_PE_DATA(44), D(18) => RX_PE_DATA(45), D(17) => RX_PE_DATA(46), D(16) => RX_PE_DATA(47), D(15) => RX_PE_DATA(48), D(14) => RX_PE_DATA(49), D(13) => RX_PE_DATA(50), D(12) => RX_PE_DATA(51), D(11) => RX_PE_DATA(52), D(10) => RX_PE_DATA(53), D(9) => RX_PE_DATA(54), D(8) => RX_PE_DATA(55), D(7) => RX_PE_DATA(56), D(6) => RX_PE_DATA(57), D(5) => RX_PE_DATA(58), D(4) => RX_PE_DATA(59), D(3) => RX_PE_DATA(60), D(2) => RX_PE_DATA(61), D(1) => RX_PE_DATA(62), D(0) => RX_PE_DATA(63), E(0) => \rx_stream_datapath_i/RX_D0\, RX_SRC_RDY_N_reg_inv => global_logic_i_n_7, SR(0) => reset_lanes_i, m_axi_rx_tdata(0 to 63) => m_axi_rx_tdata(0 to 63), m_axi_rx_tvalid => m_axi_rx_tvalid, \out\ => \out\ ); soft_err_reg: unisim.vcomponents.FDRE port map ( C => \out\, CE => '1', D => aurora_lane_0_i_n_13, Q => soft_err, R => \^system_reset_reg\ ); standard_cc_module_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_STANDARD_CC_MODULE port map ( DO_CC_reg_0 => standard_cc_module_i_n_0, Q => do_cc_i, SR => global_logic_i_n_11, TXDATAVALID_IN => TXDATAVALID_IN, channel_up_tx_if => channel_up_tx_if, \count_16d_srl_r_reg[0]_0\ => \^channel_up_rx_if_reg\, do_cc_r => \tx_stream_control_sm_i/do_cc_r\, do_cc_r_reg0 => \tx_stream_control_sm_i/do_cc_r_reg0\, extend_cc_r => \tx_stream_control_sm_i/extend_cc_r\, \out\ => \out\ ); tx_stream_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_TX_STREAM port map ( Q(61) => TX_PE_DATA(0), Q(60) => TX_PE_DATA(1), Q(59) => TX_PE_DATA(2), Q(58) => TX_PE_DATA(3), Q(57) => TX_PE_DATA(4), Q(56) => TX_PE_DATA(5), Q(55) => TX_PE_DATA(6), Q(54) => TX_PE_DATA(7), Q(53) => TX_PE_DATA(8), Q(52) => TX_PE_DATA(9), Q(51) => TX_PE_DATA(10), Q(50) => TX_PE_DATA(11), Q(49) => TX_PE_DATA(12), Q(48) => TX_PE_DATA(13), Q(47) => TX_PE_DATA(14), Q(46) => TX_PE_DATA(15), Q(45) => TX_PE_DATA(16), Q(44) => TX_PE_DATA(17), Q(43) => TX_PE_DATA(18), Q(42) => TX_PE_DATA(19), Q(41) => TX_PE_DATA(20), Q(40) => TX_PE_DATA(21), Q(39) => TX_PE_DATA(22), Q(38) => TX_PE_DATA(23), Q(37) => TX_PE_DATA(24), Q(36) => TX_PE_DATA(25), Q(35) => TX_PE_DATA(26), Q(34) => TX_PE_DATA(27), Q(33) => TX_PE_DATA(28), Q(32) => TX_PE_DATA(29), Q(31) => TX_PE_DATA(30), Q(30) => TX_PE_DATA(31), Q(29) => TX_PE_DATA(32), Q(28) => TX_PE_DATA(33), Q(27) => TX_PE_DATA(34), Q(26) => TX_PE_DATA(35), Q(25) => TX_PE_DATA(36), Q(24) => TX_PE_DATA(37), Q(23) => TX_PE_DATA(38), Q(22) => TX_PE_DATA(39), Q(21) => TX_PE_DATA(40), Q(20) => TX_PE_DATA(41), Q(19) => TX_PE_DATA(42), Q(18) => TX_PE_DATA(43), Q(17) => TX_PE_DATA(44), Q(16) => TX_PE_DATA(45), Q(15) => TX_PE_DATA(46), Q(14) => TX_PE_DATA(47), Q(13) => TX_PE_DATA(48), Q(12) => TX_PE_DATA(49), Q(11) => TX_PE_DATA(52), Q(10) => TX_PE_DATA(53), Q(9) => TX_PE_DATA(54), Q(8) => TX_PE_DATA(55), Q(7) => TX_PE_DATA(56), Q(6) => TX_PE_DATA(57), Q(5) => TX_PE_DATA(58), Q(4) => TX_PE_DATA(59), Q(3) => TX_PE_DATA(60), Q(2) => TX_PE_DATA(61), Q(1) => TX_PE_DATA(62), Q(0) => TX_PE_DATA(63), R0 => \tx_stream_control_sm_i/R0\, channel_up_tx_if => channel_up_tx_if, do_cc_r => \tx_stream_control_sm_i/do_cc_r\, do_cc_r_reg0 => \tx_stream_control_sm_i/do_cc_r_reg0\, extend_cc_r => \tx_stream_control_sm_i/extend_cc_r\, extend_cc_r_reg => aurora_64b66b_0_wrapper_i_n_91, gen_cc_flop_0_i => tx_stream_i_n_7, gen_cc_i => gen_cc_i, gen_ch_bond_i => gen_ch_bond_i, gen_na_idles_i => gen_na_idles_i, \out\ => \out\, rst_pma_init_usrclk => \sym_gen_i/rst_pma_init_usrclk\, s_axi_tx_tdata(0 to 63) => s_axi_tx_tdata(0 to 63), s_axi_tx_tready => s_axi_tx_tready, s_axi_tx_tvalid => s_axi_tx_tvalid, tx_dst_rdy_n_r_reg => standard_cc_module_i_n_0, tx_pe_data_v_i => tx_pe_data_v_i, wait_for_lane_up_r_reg(1) => tx_stream_i_n_5, wait_for_lane_up_r_reg(0) => tx_stream_i_n_6 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_support is port ( s_axi_tx_tdata : in STD_LOGIC_VECTOR ( 0 to 63 ); s_axi_tx_tvalid : in STD_LOGIC; s_axi_tx_tready : out STD_LOGIC; m_axi_rx_tdata : out STD_LOGIC_VECTOR ( 0 to 63 ); m_axi_rx_tvalid : out STD_LOGIC; rxp : in STD_LOGIC; rxn : in STD_LOGIC; txp : out STD_LOGIC; txn : out STD_LOGIC; hard_err : out STD_LOGIC; soft_err : out STD_LOGIC; channel_up : out STD_LOGIC; lane_up : out STD_LOGIC; user_clk_out : out STD_LOGIC; sync_clk_out : out STD_LOGIC; reset_pb : in STD_LOGIC; gt_rxcdrovrden_in : in STD_LOGIC; power_down : in STD_LOGIC; loopback : in STD_LOGIC_VECTOR ( 2 downto 0 ); pma_init : in STD_LOGIC; drp_clk_in : in STD_LOGIC; drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); drprdy_out : out STD_LOGIC; drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 ); drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); drpen_in : in STD_LOGIC; drpwe_in : in STD_LOGIC; init_clk : in STD_LOGIC; link_reset_out : out STD_LOGIC; gt_pll_lock : out STD_LOGIC; sys_reset_out : out STD_LOGIC; gt_reset_out : out STD_LOGIC; refclk1_in : in STD_LOGIC; gt_refclk1_out : out STD_LOGIC; gt_qpllclk_quad1_out : out STD_LOGIC; gt_qpllrefclk_quad1_out : out STD_LOGIC; mmcm_not_locked_out : out STD_LOGIC; tx_out_clk : out STD_LOGIC ); attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_support : entity is "yes"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_support; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_support is signal GTXQ0_left_i : STD_LOGIC; attribute RTL_KEEP : string; attribute RTL_KEEP of GTXQ0_left_i : signal is "true"; signal INIT_CLK_i : STD_LOGIC; attribute RTL_KEEP of INIT_CLK_i : signal is "true"; attribute syn_keep : string; attribute syn_keep of INIT_CLK_i : signal is "true"; signal aurora_64b66b_0_core_i_n_92 : STD_LOGIC; signal \^gt_qpllclk_quad1_out\ : STD_LOGIC; signal \^gt_qpllrefclk_quad1_out\ : STD_LOGIC; signal \^gt_reset_out\ : STD_LOGIC; signal gt_reset_sync_n_0 : STD_LOGIC; signal locked_i : STD_LOGIC; signal \^refclk1_in\ : STD_LOGIC; signal stg5 : STD_LOGIC; signal sync_clk_i : STD_LOGIC; attribute RTL_KEEP of sync_clk_i : signal is "true"; signal sysreset_from_support : STD_LOGIC; signal \^tx_out_clk\ : STD_LOGIC; signal user_clk_i : STD_LOGIC; attribute RTL_KEEP of user_clk_i : signal is "true"; begin \^refclk1_in\ <= refclk1_in; gt_qpllclk_quad1_out <= \^gt_qpllclk_quad1_out\; gt_qpllrefclk_quad1_out <= \^gt_qpllrefclk_quad1_out\; gt_refclk1_out <= \^refclk1_in\; gt_reset_out <= \^gt_reset_out\; sync_clk_out <= sync_clk_i; tx_out_clk <= \^tx_out_clk\; user_clk_out <= user_clk_i; aurora_64b66b_0_core_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_core port map ( CHANNEL_UP_RX_IF_reg => channel_up, MMCM_RESET_reg => aurora_64b66b_0_core_i_n_92, SYSTEM_RESET_reg => sys_reset_out, drp_clk_in => drp_clk_in, drpaddr_in(8 downto 0) => drpaddr_in(8 downto 0), drpdi_in(15 downto 0) => drpdi_in(15 downto 0), drpdo_out(15 downto 0) => drpdo_out(15 downto 0), drpen_in => drpen_in, drprdy_out => drprdy_out, drpwe_in => drpwe_in, gt_pll_lock => gt_pll_lock, gt_qpllclk_quad1_out => \^gt_qpllclk_quad1_out\, gt_qpllrefclk_quad1_out => \^gt_qpllrefclk_quad1_out\, gt_rxcdrovrden_in => gt_rxcdrovrden_in, hard_err => hard_err, in0 => locked_i, lane_up_flop_i => lane_up, link_reset_out => link_reset_out, loopback(2 downto 0) => loopback(2 downto 0), m_axi_rx_tdata(0 to 63) => m_axi_rx_tdata(0 to 63), m_axi_rx_tvalid => m_axi_rx_tvalid, \out\ => user_clk_i, power_down => power_down, refclk1_in => \^refclk1_in\, rxn => rxn, rxp => rxp, s_axi_tx_tdata(0 to 63) => s_axi_tx_tdata(0 to 63), s_axi_tx_tready => s_axi_tx_tready, s_axi_tx_tvalid => s_axi_tx_tvalid, soft_err => soft_err, stg1_aurora_64b66b_0_cdc_to_reg => \^gt_reset_out\, stg4_reg => INIT_CLK_i, stg4_reg_0 => sync_clk_i, sysreset_from_support => sysreset_from_support, tx_out_clk => \^tx_out_clk\, txn => txn, txp => txp ); clock_module_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_CLOCK_MODULE port map ( INIT_CLK_i => INIT_CLK_i, in0 => locked_i, init_clk => init_clk, mmcm_lock_sync_reg => aurora_64b66b_0_core_i_n_92, mmcm_not_locked_out => mmcm_not_locked_out, sync_clk_i_0 => sync_clk_i, tx_out_clk => \^tx_out_clk\, user_clk_i_0 => user_clk_i ); gt_common_support: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_gt_common_wrapper port map ( drp_clk_in => drp_clk_in, gt_qpllclk_quad1_out => \^gt_qpllclk_quad1_out\, gt_qpllrefclk_quad1_out => \^gt_qpllrefclk_quad1_out\, \out\ => INIT_CLK_i, refclk1_in => \^refclk1_in\ ); gt_reset_sync: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync port map ( D(0) => gt_reset_sync_n_0, \out\ => INIT_CLK_i, pma_init => pma_init ); i_0: unisim.vcomponents.LUT1 generic map( INIT => X"2" ) port map ( I0 => '0', O => GTXQ0_left_i ); reset_pb_sync: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_rst_sync_0 port map ( D(0) => stg5, \out\ => user_clk_i, reset_pb => reset_pb ); support_reset_logic_i: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_SUPPORT_RESET_LOGIC port map ( D(0) => stg5, \debounce_gt_rst_r_reg[0]_0\ => INIT_CLK_i, \debounce_gt_rst_r_reg[0]_1\(0) => gt_reset_sync_n_0, gt_reset_out => \^gt_reset_out\, \out\ => user_clk_i, sysreset_from_support => sysreset_from_support ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is port ( s_axi_tx_tdata : in STD_LOGIC_VECTOR ( 0 to 63 ); s_axi_tx_tvalid : in STD_LOGIC; s_axi_tx_tready : out STD_LOGIC; m_axi_rx_tdata : out STD_LOGIC_VECTOR ( 0 to 63 ); m_axi_rx_tvalid : out STD_LOGIC; rxp : in STD_LOGIC_VECTOR ( 0 to 0 ); rxn : in STD_LOGIC_VECTOR ( 0 to 0 ); txp : out STD_LOGIC_VECTOR ( 0 to 0 ); txn : out STD_LOGIC_VECTOR ( 0 to 0 ); refclk1_in : in STD_LOGIC; hard_err : out STD_LOGIC; soft_err : out STD_LOGIC; channel_up : out STD_LOGIC; lane_up : out STD_LOGIC_VECTOR ( 0 to 0 ); user_clk_out : out STD_LOGIC; mmcm_not_locked_out : out STD_LOGIC; sync_clk_out : out STD_LOGIC; reset_pb : in STD_LOGIC; gt_rxcdrovrden_in : in STD_LOGIC; power_down : in STD_LOGIC; loopback : in STD_LOGIC_VECTOR ( 2 downto 0 ); pma_init : in STD_LOGIC; gt_pll_lock : out STD_LOGIC; drp_clk_in : in STD_LOGIC; drpaddr_in : in STD_LOGIC_VECTOR ( 8 downto 0 ); drpdi_in : in STD_LOGIC_VECTOR ( 15 downto 0 ); drpdo_out : out STD_LOGIC_VECTOR ( 15 downto 0 ); drprdy_out : out STD_LOGIC; drpen_in : in STD_LOGIC; drpwe_in : in STD_LOGIC; init_clk : in STD_LOGIC; link_reset_out : out STD_LOGIC; gt_qpllclk_quad1_out : out STD_LOGIC; gt_qpllrefclk_quad1_out : out STD_LOGIC; sys_reset_out : out STD_LOGIC; gt_reset_out : out STD_LOGIC; tx_out_clk : out STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; attribute DowngradeIPIdentifiedWarnings : string; attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "aurora_64b66b_v11_2_6, Coregen v14.3_ip3, Number of lanes = 1, Line rate is double5.0Gbps, Reference Clock is double156.25MHz, Interface is Streaming, Flow Control is None and is operating in DUPLEX configuration"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is signal NLW_inst_gt_refclk1_out_UNCONNECTED : STD_LOGIC; attribute DowngradeIPIdentifiedWarnings of inst : label is "yes"; begin inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_aurora_64b66b_0_support port map ( channel_up => channel_up, drp_clk_in => drp_clk_in, drpaddr_in(8 downto 0) => drpaddr_in(8 downto 0), drpdi_in(15 downto 0) => drpdi_in(15 downto 0), drpdo_out(15 downto 0) => drpdo_out(15 downto 0), drpen_in => drpen_in, drprdy_out => drprdy_out, drpwe_in => drpwe_in, gt_pll_lock => gt_pll_lock, gt_qpllclk_quad1_out => gt_qpllclk_quad1_out, gt_qpllrefclk_quad1_out => gt_qpllrefclk_quad1_out, gt_refclk1_out => NLW_inst_gt_refclk1_out_UNCONNECTED, gt_reset_out => gt_reset_out, gt_rxcdrovrden_in => gt_rxcdrovrden_in, hard_err => hard_err, init_clk => init_clk, lane_up => lane_up(0), link_reset_out => link_reset_out, loopback(2 downto 0) => loopback(2 downto 0), m_axi_rx_tdata(0 to 63) => m_axi_rx_tdata(0 to 63), m_axi_rx_tvalid => m_axi_rx_tvalid, mmcm_not_locked_out => mmcm_not_locked_out, pma_init => pma_init, power_down => power_down, refclk1_in => refclk1_in, reset_pb => reset_pb, rxn => rxn(0), rxp => rxp(0), s_axi_tx_tdata(0 to 63) => s_axi_tx_tdata(0 to 63), s_axi_tx_tready => s_axi_tx_tready, s_axi_tx_tvalid => s_axi_tx_tvalid, soft_err => soft_err, sync_clk_out => sync_clk_out, sys_reset_out => sys_reset_out, tx_out_clk => tx_out_clk, txn => txn(0), txp => txp(0), user_clk_out => user_clk_out ); end STRUCTURE;