// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 // Date : Sat Apr 18 12:30:23 2020 // Host : baby running 64-bit major release (build 9200) // Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix // decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ngFEC_mgt_sim_netlist.v // Design : ngFEC_mgt // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. // Device : xc7k420tffg1156-2 // -------------------------------------------------------------------------------- `timescale 1 ps / 1 ps (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "ngFEC_mgt,gtwizard_v3_6_10,{protocol_file=Start_from_scratch}" *) (* NotValidForBitStream *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix (SYSCLK_IN, SOFT_RESET_TX_IN, SOFT_RESET_RX_IN, DONT_RESET_ON_DATA_ERROR_IN, GT0_TX_FSM_RESET_DONE_OUT, GT0_RX_FSM_RESET_DONE_OUT, GT0_DATA_VALID_IN, gt0_cpllfbclklost_out, gt0_cplllock_out, gt0_cplllockdetclk_in, gt0_cpllpd_in, gt0_cpllreset_in, gt0_gtrefclk0_in, gt0_gtrefclk1_in, gt0_drpaddr_in, gt0_drpclk_in, gt0_drpdi_in, gt0_drpdo_out, gt0_drpen_in, gt0_drprdy_out, gt0_drpwe_in, gt0_dmonitorout_out, gt0_loopback_in, gt0_rxpd_in, gt0_txpd_in, gt0_eyescanreset_in, gt0_rxuserrdy_in, gt0_eyescandataerror_out, gt0_eyescantrigger_in, gt0_rxusrclk_in, gt0_rxusrclk2_in, gt0_rxdata_out, gt0_gtxrxp_in, gt0_gtxrxn_in, gt0_rxphmonitor_out, gt0_rxphslipmonitor_out, gt0_rxdfelpmreset_in, gt0_rxmonitorout_out, gt0_rxmonitorsel_in, gt0_rxoutclk_out, gt0_rxoutclkfabric_out, gt0_gtrxreset_in, gt0_rxpmareset_in, gt0_rxpolarity_in, gt0_rxslide_in, gt0_rxresetdone_out, gt0_txpostcursor_in, gt0_txprecursor_in, gt0_gttxreset_in, gt0_txuserrdy_in, gt0_txusrclk_in, gt0_txusrclk2_in, gt0_txelecidle_in, gt0_txdiffctrl_in, gt0_txdata_in, gt0_gtxtxn_out, gt0_gtxtxp_out, gt0_txoutclk_out, gt0_txoutclkfabric_out, gt0_txoutclkpcs_out, gt0_txresetdone_out, gt0_txpolarity_in, GT0_QPLLOUTCLK_IN, GT0_QPLLOUTREFCLK_IN); input SYSCLK_IN; input SOFT_RESET_TX_IN; input SOFT_RESET_RX_IN; input DONT_RESET_ON_DATA_ERROR_IN; output GT0_TX_FSM_RESET_DONE_OUT; output GT0_RX_FSM_RESET_DONE_OUT; input GT0_DATA_VALID_IN; output gt0_cpllfbclklost_out; output gt0_cplllock_out; input gt0_cplllockdetclk_in; input gt0_cpllpd_in; input gt0_cpllreset_in; input gt0_gtrefclk0_in; input gt0_gtrefclk1_in; input [8:0]gt0_drpaddr_in; input gt0_drpclk_in; input [15:0]gt0_drpdi_in; output [15:0]gt0_drpdo_out; input gt0_drpen_in; output gt0_drprdy_out; input gt0_drpwe_in; output [7:0]gt0_dmonitorout_out; input [2:0]gt0_loopback_in; input [1:0]gt0_rxpd_in; input [1:0]gt0_txpd_in; input gt0_eyescanreset_in; input gt0_rxuserrdy_in; output gt0_eyescandataerror_out; input gt0_eyescantrigger_in; input gt0_rxusrclk_in; input gt0_rxusrclk2_in; output [19:0]gt0_rxdata_out; input gt0_gtxrxp_in; input gt0_gtxrxn_in; output [4:0]gt0_rxphmonitor_out; output [4:0]gt0_rxphslipmonitor_out; input gt0_rxdfelpmreset_in; output [6:0]gt0_rxmonitorout_out; input [1:0]gt0_rxmonitorsel_in; output gt0_rxoutclk_out; output gt0_rxoutclkfabric_out; input gt0_gtrxreset_in; input gt0_rxpmareset_in; input gt0_rxpolarity_in; input gt0_rxslide_in; output gt0_rxresetdone_out; input [4:0]gt0_txpostcursor_in; input [4:0]gt0_txprecursor_in; input gt0_gttxreset_in; input gt0_txuserrdy_in; input gt0_txusrclk_in; input gt0_txusrclk2_in; input gt0_txelecidle_in; input [3:0]gt0_txdiffctrl_in; input [19:0]gt0_txdata_in; output gt0_gtxtxn_out; output gt0_gtxtxp_out; output gt0_txoutclk_out; output gt0_txoutclkfabric_out; output gt0_txoutclkpcs_out; output gt0_txresetdone_out; input gt0_txpolarity_in; input GT0_QPLLOUTCLK_IN; input GT0_QPLLOUTREFCLK_IN; wire DONT_RESET_ON_DATA_ERROR_IN; wire GT0_DATA_VALID_IN; wire GT0_QPLLOUTCLK_IN; wire GT0_QPLLOUTREFCLK_IN; wire GT0_RX_FSM_RESET_DONE_OUT; wire GT0_TX_FSM_RESET_DONE_OUT; wire SOFT_RESET_RX_IN; wire SOFT_RESET_TX_IN; wire SYSCLK_IN; wire gt0_cpllfbclklost_out; wire gt0_cplllock_out; wire gt0_cplllockdetclk_in; wire gt0_cpllpd_in; wire gt0_cpllreset_in; wire [7:0]gt0_dmonitorout_out; wire [8:0]gt0_drpaddr_in; wire gt0_drpclk_in; wire [15:0]gt0_drpdi_in; wire [15:0]gt0_drpdo_out; wire gt0_drpen_in; wire gt0_drprdy_out; wire gt0_drpwe_in; wire gt0_eyescandataerror_out; wire gt0_eyescanreset_in; wire gt0_eyescantrigger_in; wire gt0_gtrefclk0_in; wire gt0_gtrefclk1_in; wire gt0_gtrxreset_in; wire gt0_gttxreset_in; wire gt0_gtxrxn_in; wire gt0_gtxrxp_in; wire gt0_gtxtxn_out; wire gt0_gtxtxp_out; wire [2:0]gt0_loopback_in; wire [19:0]gt0_rxdata_out; wire gt0_rxdfelpmreset_in; wire [6:0]gt0_rxmonitorout_out; wire [1:0]gt0_rxmonitorsel_in; wire gt0_rxoutclk_out; wire gt0_rxoutclkfabric_out; wire [1:0]gt0_rxpd_in; wire [4:0]gt0_rxphmonitor_out; wire [4:0]gt0_rxphslipmonitor_out; wire gt0_rxpmareset_in; wire gt0_rxpolarity_in; wire gt0_rxresetdone_out; wire gt0_rxslide_in; wire gt0_rxuserrdy_in; wire gt0_rxusrclk2_in; wire gt0_rxusrclk_in; wire [19:0]gt0_txdata_in; wire [3:0]gt0_txdiffctrl_in; wire gt0_txelecidle_in; wire gt0_txoutclk_out; wire gt0_txoutclkfabric_out; wire gt0_txoutclkpcs_out; wire [1:0]gt0_txpd_in; wire gt0_txpolarity_in; wire [4:0]gt0_txpostcursor_in; wire [4:0]gt0_txprecursor_in; wire gt0_txresetdone_out; wire gt0_txuserrdy_in; wire gt0_txusrclk2_in; wire gt0_txusrclk_in; (* EXAMPLE_SIMULATION = "0" *) (* EXAMPLE_SIM_GTRESET_SPEEDUP = "TRUE" *) (* EXAMPLE_USE_CHIPSCOPE = "0" *) (* STABLE_CLOCK_PERIOD = "25" *) (* USE_BUFG = "0" *) (* downgradeipidentifiedwarnings = "yes" *) decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_init U0 (.DONT_RESET_ON_DATA_ERROR_IN(DONT_RESET_ON_DATA_ERROR_IN), .GT0_DATA_VALID_IN(GT0_DATA_VALID_IN), .GT0_QPLLOUTCLK_IN(GT0_QPLLOUTCLK_IN), .GT0_QPLLOUTREFCLK_IN(GT0_QPLLOUTREFCLK_IN), .GT0_RX_FSM_RESET_DONE_OUT(GT0_RX_FSM_RESET_DONE_OUT), .GT0_TX_FSM_RESET_DONE_OUT(GT0_TX_FSM_RESET_DONE_OUT), .SOFT_RESET_RX_IN(SOFT_RESET_RX_IN), .SOFT_RESET_TX_IN(SOFT_RESET_TX_IN), .SYSCLK_IN(SYSCLK_IN), .gt0_cpllfbclklost_out(gt0_cpllfbclklost_out), .gt0_cplllock_out(gt0_cplllock_out), .gt0_cplllockdetclk_in(gt0_cplllockdetclk_in), .gt0_cpllpd_in(gt0_cpllpd_in), .gt0_cpllreset_in(gt0_cpllreset_in), .gt0_dmonitorout_out(gt0_dmonitorout_out), .gt0_drpaddr_in(gt0_drpaddr_in), .gt0_drpclk_in(gt0_drpclk_in), .gt0_drpdi_in(gt0_drpdi_in), .gt0_drpdo_out(gt0_drpdo_out), .gt0_drpen_in(gt0_drpen_in), .gt0_drprdy_out(gt0_drprdy_out), .gt0_drpwe_in(gt0_drpwe_in), .gt0_eyescandataerror_out(gt0_eyescandataerror_out), .gt0_eyescanreset_in(gt0_eyescanreset_in), .gt0_eyescantrigger_in(gt0_eyescantrigger_in), .gt0_gtrefclk0_in(gt0_gtrefclk0_in), .gt0_gtrefclk1_in(gt0_gtrefclk1_in), .gt0_gtrxreset_in(gt0_gtrxreset_in), .gt0_gttxreset_in(gt0_gttxreset_in), .gt0_gtxrxn_in(gt0_gtxrxn_in), .gt0_gtxrxp_in(gt0_gtxrxp_in), .gt0_gtxtxn_out(gt0_gtxtxn_out), .gt0_gtxtxp_out(gt0_gtxtxp_out), .gt0_loopback_in(gt0_loopback_in), .gt0_rxdata_out(gt0_rxdata_out), .gt0_rxdfelpmreset_in(gt0_rxdfelpmreset_in), .gt0_rxmonitorout_out(gt0_rxmonitorout_out), .gt0_rxmonitorsel_in(gt0_rxmonitorsel_in), .gt0_rxoutclk_out(gt0_rxoutclk_out), .gt0_rxoutclkfabric_out(gt0_rxoutclkfabric_out), .gt0_rxpd_in(gt0_rxpd_in), .gt0_rxphmonitor_out(gt0_rxphmonitor_out), .gt0_rxphslipmonitor_out(gt0_rxphslipmonitor_out), .gt0_rxpmareset_in(gt0_rxpmareset_in), .gt0_rxpolarity_in(gt0_rxpolarity_in), .gt0_rxresetdone_out(gt0_rxresetdone_out), .gt0_rxslide_in(gt0_rxslide_in), .gt0_rxuserrdy_in(gt0_rxuserrdy_in), .gt0_rxusrclk2_in(gt0_rxusrclk2_in), .gt0_rxusrclk_in(gt0_rxusrclk_in), .gt0_txdata_in(gt0_txdata_in), .gt0_txdiffctrl_in(gt0_txdiffctrl_in), .gt0_txelecidle_in(gt0_txelecidle_in), .gt0_txoutclk_out(gt0_txoutclk_out), .gt0_txoutclkfabric_out(gt0_txoutclkfabric_out), .gt0_txoutclkpcs_out(gt0_txoutclkpcs_out), .gt0_txpd_in(gt0_txpd_in), .gt0_txpolarity_in(gt0_txpolarity_in), .gt0_txpostcursor_in(gt0_txpostcursor_in), .gt0_txprecursor_in(gt0_txprecursor_in), .gt0_txresetdone_out(gt0_txresetdone_out), .gt0_txuserrdy_in(gt0_txuserrdy_in), .gt0_txusrclk2_in(gt0_txusrclk2_in), .gt0_txusrclk_in(gt0_txusrclk_in)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_AUTO_PHASE_ALIGN (PHASE_ALIGNMENT_DONE_reg_0, gt0_rxdlysreset_i, SYSCLK_IN, \count_phalign_edges_reg[1]_0 , gt0_run_rx_phalignment_i, data_in, data_sync_reg1, SR); output PHASE_ALIGNMENT_DONE_reg_0; output gt0_rxdlysreset_i; input SYSCLK_IN; input \count_phalign_edges_reg[1]_0 ; input gt0_run_rx_phalignment_i; input data_in; input data_sync_reg1; input [0:0]SR; wire DLYSRESET_i_1_n_0; wire \FSM_onehot_phalign_state_reg_n_0_[0] ; wire \FSM_onehot_phalign_state_reg_n_0_[1] ; wire \FSM_onehot_phalign_state_reg_n_0_[2] ; wire \FSM_onehot_phalign_state_reg_n_0_[3] ; wire PHASE_ALIGNMENT_DONE_i_1_n_0; wire PHASE_ALIGNMENT_DONE_reg_0; wire [0:0]SR; wire SYSCLK_IN; wire \count_phalign_edges[0]_i_1_n_0 ; wire \count_phalign_edges[1]_i_1_n_0 ; wire \count_phalign_edges_reg[1]_0 ; wire \count_phalign_edges_reg_n_0_[0] ; wire \count_phalign_edges_reg_n_0_[1] ; wire data_in; wire data_out; wire data_sync_reg1; wire dlysresetdone_sync; wire gt0_run_rx_phalignment_i; wire gt0_rxdlysreset_i; wire \phalign_state_inferred__0/i__n_0 ; wire phaligndone_prev; (* SOFT_HLUTNM = "soft_lutpair0" *) LUT3 #( .INIT(8'h80)) DLYSRESET_i_1 (.I0(\FSM_onehot_phalign_state_reg_n_0_[0] ), .I1(\count_phalign_edges_reg[1]_0 ), .I2(gt0_run_rx_phalignment_i), .O(DLYSRESET_i_1_n_0)); FDRE DLYSRESET_reg (.C(SYSCLK_IN), .CE(1'b1), .D(DLYSRESET_i_1_n_0), .Q(gt0_rxdlysreset_i), .R(1'b0)); (* FSM_ENCODED_STATES = "init:0001,wait_phrst_done:0010,count_phalign_done:0100,phalign_done:1000" *) FDSE #( .INIT(1'b1)) \FSM_onehot_phalign_state_reg[0] (.C(SYSCLK_IN), .CE(\phalign_state_inferred__0/i__n_0 ), .D(1'b0), .Q(\FSM_onehot_phalign_state_reg_n_0_[0] ), .S(SR)); (* FSM_ENCODED_STATES = "init:0001,wait_phrst_done:0010,count_phalign_done:0100,phalign_done:1000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_phalign_state_reg[1] (.C(SYSCLK_IN), .CE(\phalign_state_inferred__0/i__n_0 ), .D(\FSM_onehot_phalign_state_reg_n_0_[0] ), .Q(\FSM_onehot_phalign_state_reg_n_0_[1] ), .R(SR)); (* FSM_ENCODED_STATES = "init:0001,wait_phrst_done:0010,count_phalign_done:0100,phalign_done:1000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_phalign_state_reg[2] (.C(SYSCLK_IN), .CE(\phalign_state_inferred__0/i__n_0 ), .D(\FSM_onehot_phalign_state_reg_n_0_[1] ), .Q(\FSM_onehot_phalign_state_reg_n_0_[2] ), .R(SR)); (* FSM_ENCODED_STATES = "init:0001,wait_phrst_done:0010,count_phalign_done:0100,phalign_done:1000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_phalign_state_reg[3] (.C(SYSCLK_IN), .CE(\phalign_state_inferred__0/i__n_0 ), .D(\FSM_onehot_phalign_state_reg_n_0_[2] ), .Q(\FSM_onehot_phalign_state_reg_n_0_[3] ), .R(SR)); (* SOFT_HLUTNM = "soft_lutpair0" *) LUT5 #( .INIT(32'hCE000000)) PHASE_ALIGNMENT_DONE_i_1 (.I0(PHASE_ALIGNMENT_DONE_reg_0), .I1(\FSM_onehot_phalign_state_reg_n_0_[3] ), .I2(\FSM_onehot_phalign_state_reg_n_0_[0] ), .I3(\count_phalign_edges_reg[1]_0 ), .I4(gt0_run_rx_phalignment_i), .O(PHASE_ALIGNMENT_DONE_i_1_n_0)); FDRE #( .INIT(1'b0)) PHASE_ALIGNMENT_DONE_reg (.C(SYSCLK_IN), .CE(1'b1), .D(PHASE_ALIGNMENT_DONE_i_1_n_0), .Q(PHASE_ALIGNMENT_DONE_reg_0), .R(1'b0)); LUT6 #( .INIT(64'hAAE6000000000000)) \count_phalign_edges[0]_i_1 (.I0(\count_phalign_edges_reg_n_0_[0] ), .I1(data_out), .I2(\count_phalign_edges_reg_n_0_[1] ), .I3(phaligndone_prev), .I4(\count_phalign_edges_reg[1]_0 ), .I5(gt0_run_rx_phalignment_i), .O(\count_phalign_edges[0]_i_1_n_0 )); LUT6 #( .INIT(64'hF4F0000000000000)) \count_phalign_edges[1]_i_1 (.I0(phaligndone_prev), .I1(\count_phalign_edges_reg_n_0_[0] ), .I2(\count_phalign_edges_reg_n_0_[1] ), .I3(data_out), .I4(\count_phalign_edges_reg[1]_0 ), .I5(gt0_run_rx_phalignment_i), .O(\count_phalign_edges[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \count_phalign_edges_reg[0] (.C(SYSCLK_IN), .CE(1'b1), .D(\count_phalign_edges[0]_i_1_n_0 ), .Q(\count_phalign_edges_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \count_phalign_edges_reg[1] (.C(SYSCLK_IN), .CE(1'b1), .D(\count_phalign_edges[1]_i_1_n_0 ), .Q(\count_phalign_edges_reg_n_0_[1] ), .R(1'b0)); LUT6 #( .INIT(64'hFFFFAEAAAEAAAEAA)) \phalign_state_inferred__0/i_ (.I0(\FSM_onehot_phalign_state_reg_n_0_[0] ), .I1(\FSM_onehot_phalign_state_reg_n_0_[2] ), .I2(\count_phalign_edges_reg_n_0_[0] ), .I3(\count_phalign_edges_reg_n_0_[1] ), .I4(\FSM_onehot_phalign_state_reg_n_0_[1] ), .I5(dlysresetdone_sync), .O(\phalign_state_inferred__0/i__n_0 )); FDRE #( .INIT(1'b0)) phaligndone_prev_reg (.C(SYSCLK_IN), .CE(1'b1), .D(data_out), .Q(phaligndone_prev), .R(1'b0)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_sync_block_15 sync_DLYSRESETDONE (.SYSCLK_IN(SYSCLK_IN), .data_out(dlysresetdone_sync), .data_sync_reg1_0(data_sync_reg1)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_sync_block_16 sync_PHALIGNDONE (.SYSCLK_IN(SYSCLK_IN), .data_in(data_in), .data_out(data_out)); endmodule (* ORIG_REF_NAME = "ngFEC_mgt_AUTO_PHASE_ALIGN" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_AUTO_PHASE_ALIGN_0 (gt0_txdlysreset_i, gt0_tx_phalignment_done_i, SYSCLK_IN, PHASE_ALIGNMENT_DONE_reg_0, data_in, data_sync_reg1); output gt0_txdlysreset_i; output gt0_tx_phalignment_done_i; input SYSCLK_IN; input PHASE_ALIGNMENT_DONE_reg_0; input data_in; input data_sync_reg1; wire \FSM_onehot_phalign_state_reg_n_0_[0] ; wire \FSM_onehot_phalign_state_reg_n_0_[1] ; wire \FSM_onehot_phalign_state_reg_n_0_[2] ; wire \FSM_onehot_phalign_state_reg_n_0_[3] ; wire PHASE_ALIGNMENT_DONE_i_1__0_n_0; wire PHASE_ALIGNMENT_DONE_reg_0; wire SYSCLK_IN; wire \count_phalign_edges[0]_i_1_n_0 ; wire \count_phalign_edges[1]_i_1_n_0 ; wire \count_phalign_edges_reg_n_0_[0] ; wire \count_phalign_edges_reg_n_0_[1] ; wire data_in; wire data_out; wire data_sync_reg1; wire dlysresetdone_sync; wire gt0_tx_phalignment_done_i; wire gt0_txdlysreset_i; wire \phalign_state_inferred__0/i__n_0 ; wire phaligndone_prev; FDRE DLYSRESET_reg (.C(SYSCLK_IN), .CE(1'b1), .D(\FSM_onehot_phalign_state_reg_n_0_[0] ), .Q(gt0_txdlysreset_i), .R(PHASE_ALIGNMENT_DONE_reg_0)); (* FSM_ENCODED_STATES = "init:0001,wait_phrst_done:0010,count_phalign_done:0100,phalign_done:1000" *) FDSE #( .INIT(1'b1)) \FSM_onehot_phalign_state_reg[0] (.C(SYSCLK_IN), .CE(\phalign_state_inferred__0/i__n_0 ), .D(1'b0), .Q(\FSM_onehot_phalign_state_reg_n_0_[0] ), .S(PHASE_ALIGNMENT_DONE_reg_0)); (* FSM_ENCODED_STATES = "init:0001,wait_phrst_done:0010,count_phalign_done:0100,phalign_done:1000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_phalign_state_reg[1] (.C(SYSCLK_IN), .CE(\phalign_state_inferred__0/i__n_0 ), .D(\FSM_onehot_phalign_state_reg_n_0_[0] ), .Q(\FSM_onehot_phalign_state_reg_n_0_[1] ), .R(PHASE_ALIGNMENT_DONE_reg_0)); (* FSM_ENCODED_STATES = "init:0001,wait_phrst_done:0010,count_phalign_done:0100,phalign_done:1000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_phalign_state_reg[2] (.C(SYSCLK_IN), .CE(\phalign_state_inferred__0/i__n_0 ), .D(\FSM_onehot_phalign_state_reg_n_0_[1] ), .Q(\FSM_onehot_phalign_state_reg_n_0_[2] ), .R(PHASE_ALIGNMENT_DONE_reg_0)); (* FSM_ENCODED_STATES = "init:0001,wait_phrst_done:0010,count_phalign_done:0100,phalign_done:1000" *) FDRE #( .INIT(1'b0)) \FSM_onehot_phalign_state_reg[3] (.C(SYSCLK_IN), .CE(\phalign_state_inferred__0/i__n_0 ), .D(\FSM_onehot_phalign_state_reg_n_0_[2] ), .Q(\FSM_onehot_phalign_state_reg_n_0_[3] ), .R(PHASE_ALIGNMENT_DONE_reg_0)); LUT3 #( .INIT(8'hDC)) PHASE_ALIGNMENT_DONE_i_1__0 (.I0(\FSM_onehot_phalign_state_reg_n_0_[0] ), .I1(\FSM_onehot_phalign_state_reg_n_0_[3] ), .I2(gt0_tx_phalignment_done_i), .O(PHASE_ALIGNMENT_DONE_i_1__0_n_0)); FDRE #( .INIT(1'b0)) PHASE_ALIGNMENT_DONE_reg (.C(SYSCLK_IN), .CE(1'b1), .D(PHASE_ALIGNMENT_DONE_i_1__0_n_0), .Q(gt0_tx_phalignment_done_i), .R(PHASE_ALIGNMENT_DONE_reg_0)); (* SOFT_HLUTNM = "soft_lutpair16" *) LUT4 #( .INIT(16'hEF50)) \count_phalign_edges[0]_i_1 (.I0(phaligndone_prev), .I1(\count_phalign_edges_reg_n_0_[1] ), .I2(data_out), .I3(\count_phalign_edges_reg_n_0_[0] ), .O(\count_phalign_edges[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair16" *) LUT4 #( .INIT(16'hCCEC)) \count_phalign_edges[1]_i_1 (.I0(data_out), .I1(\count_phalign_edges_reg_n_0_[1] ), .I2(\count_phalign_edges_reg_n_0_[0] ), .I3(phaligndone_prev), .O(\count_phalign_edges[1]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \count_phalign_edges_reg[0] (.C(SYSCLK_IN), .CE(1'b1), .D(\count_phalign_edges[0]_i_1_n_0 ), .Q(\count_phalign_edges_reg_n_0_[0] ), .R(PHASE_ALIGNMENT_DONE_reg_0)); FDRE #( .INIT(1'b0)) \count_phalign_edges_reg[1] (.C(SYSCLK_IN), .CE(1'b1), .D(\count_phalign_edges[1]_i_1_n_0 ), .Q(\count_phalign_edges_reg_n_0_[1] ), .R(PHASE_ALIGNMENT_DONE_reg_0)); LUT6 #( .INIT(64'hFFFFAEAAAEAAAEAA)) \phalign_state_inferred__0/i_ (.I0(\FSM_onehot_phalign_state_reg_n_0_[0] ), .I1(\FSM_onehot_phalign_state_reg_n_0_[2] ), .I2(\count_phalign_edges_reg_n_0_[0] ), .I3(\count_phalign_edges_reg_n_0_[1] ), .I4(\FSM_onehot_phalign_state_reg_n_0_[1] ), .I5(dlysresetdone_sync), .O(\phalign_state_inferred__0/i__n_0 )); FDRE #( .INIT(1'b0)) phaligndone_prev_reg (.C(SYSCLK_IN), .CE(1'b1), .D(data_out), .Q(phaligndone_prev), .R(1'b0)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_sync_block_6 sync_DLYSRESETDONE (.SYSCLK_IN(SYSCLK_IN), .data_out(dlysresetdone_sync), .data_sync_reg1_0(data_sync_reg1)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_sync_block_7 sync_PHALIGNDONE (.SYSCLK_IN(SYSCLK_IN), .data_in(data_in), .data_out(data_out)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_GT (gt0_cpllfbclklost_out, gt0_cplllock_out, gt0_cpllrefclklost_i, gt0_drprdy_out, gt0_eyescandataerror_out, gt0_gtxtxn_out, gt0_gtxtxp_out, gt0_cplllockdetclk_in_0, gt0_rxoutclk_out, gt0_rxoutclkfabric_out, data_in, gt0_rxresetdone_out, gt0_cplllockdetclk_in_1, gt0_txoutclk_out, gt0_txoutclkfabric_out, gt0_txoutclkpcs_out, gt0_cplllockdetclk_in_2, gt0_txresetdone_out, gt0_drpdo_out, gt0_rxphmonitor_out, gt0_rxphslipmonitor_out, gt0_rxdata_out, gt0_rxmonitorout_out, gt0_dmonitorout_out, gt0_cplllockdetclk_in, cpllpd_in, cpllreset_in, gt0_drpclk_in, gt0_drpen_in, gt0_drpwe_in, gt0_eyescanreset_in, gt0_eyescantrigger_in, gt0_gtrefclk0_in, gt0_gtrefclk1_in, SR, gt0_gttxreset_t, gt0_gtxrxn_in, gt0_gtxrxp_in, GT0_QPLLOUTCLK_IN, GT0_QPLLOUTREFCLK_IN, gt0_rxdfelfhold_i, gt0_rxdfelpmreset_in, gt0_rxdlysreset_i, gt0_rxpmareset_in, gt0_rxpolarity_in, gt0_rxslide_in, gt0_rxuserrdy_t, gt0_rxusrclk_in, gt0_rxusrclk2_in, gt0_txdlysreset_i, gt0_txelecidle_in, gt0_txpolarity_in, gt0_txuserrdy_t, gt0_txusrclk_in, gt0_txusrclk2_in, gt0_drpdi_in, gt0_rxmonitorsel_in, gt0_rxpd_in, gt0_txpd_in, gt0_loopback_in, gt0_txdiffctrl_in, gt0_txpostcursor_in, gt0_txprecursor_in, gt0_txdata_in, gt0_drpaddr_in); output gt0_cpllfbclklost_out; output gt0_cplllock_out; output gt0_cpllrefclklost_i; output gt0_drprdy_out; output gt0_eyescandataerror_out; output gt0_gtxtxn_out; output gt0_gtxtxp_out; output gt0_cplllockdetclk_in_0; output gt0_rxoutclk_out; output gt0_rxoutclkfabric_out; output data_in; output gt0_rxresetdone_out; output gt0_cplllockdetclk_in_1; output gt0_txoutclk_out; output gt0_txoutclkfabric_out; output gt0_txoutclkpcs_out; output gt0_cplllockdetclk_in_2; output gt0_txresetdone_out; output [15:0]gt0_drpdo_out; output [4:0]gt0_rxphmonitor_out; output [4:0]gt0_rxphslipmonitor_out; output [19:0]gt0_rxdata_out; output [6:0]gt0_rxmonitorout_out; output [7:0]gt0_dmonitorout_out; input gt0_cplllockdetclk_in; input cpllpd_in; input cpllreset_in; input gt0_drpclk_in; input gt0_drpen_in; input gt0_drpwe_in; input gt0_eyescanreset_in; input gt0_eyescantrigger_in; input gt0_gtrefclk0_in; input gt0_gtrefclk1_in; input [0:0]SR; input gt0_gttxreset_t; input gt0_gtxrxn_in; input gt0_gtxrxp_in; input GT0_QPLLOUTCLK_IN; input GT0_QPLLOUTREFCLK_IN; input gt0_rxdfelfhold_i; input gt0_rxdfelpmreset_in; input gt0_rxdlysreset_i; input gt0_rxpmareset_in; input gt0_rxpolarity_in; input gt0_rxslide_in; input gt0_rxuserrdy_t; input gt0_rxusrclk_in; input gt0_rxusrclk2_in; input gt0_txdlysreset_i; input gt0_txelecidle_in; input gt0_txpolarity_in; input gt0_txuserrdy_t; input gt0_txusrclk_in; input gt0_txusrclk2_in; input [15:0]gt0_drpdi_in; input [1:0]gt0_rxmonitorsel_in; input [1:0]gt0_rxpd_in; input [1:0]gt0_txpd_in; input [2:0]gt0_loopback_in; input [3:0]gt0_txdiffctrl_in; input [4:0]gt0_txpostcursor_in; input [4:0]gt0_txprecursor_in; input [19:0]gt0_txdata_in; input [8:0]gt0_drpaddr_in; wire GT0_QPLLOUTCLK_IN; wire GT0_QPLLOUTREFCLK_IN; wire [0:0]SR; wire cpllpd_in; wire cpllreset_in; wire data_in; wire gt0_cpllfbclklost_out; wire gt0_cplllock_out; wire gt0_cplllockdetclk_in; wire gt0_cplllockdetclk_in_0; wire gt0_cplllockdetclk_in_1; wire gt0_cplllockdetclk_in_2; wire gt0_cpllrefclklost_i; wire [7:0]gt0_dmonitorout_out; wire [8:0]gt0_drpaddr_in; wire gt0_drpclk_in; wire [15:0]gt0_drpdi_in; wire [15:0]gt0_drpdo_out; wire gt0_drpen_in; wire gt0_drprdy_out; wire gt0_drpwe_in; wire gt0_eyescandataerror_out; wire gt0_eyescanreset_in; wire gt0_eyescantrigger_in; wire gt0_gtrefclk0_in; wire gt0_gtrefclk1_in; wire gt0_gttxreset_t; wire gt0_gtxrxn_in; wire gt0_gtxrxp_in; wire gt0_gtxtxn_out; wire gt0_gtxtxp_out; wire [2:0]gt0_loopback_in; wire [19:0]gt0_rxdata_out; wire gt0_rxdfelfhold_i; wire gt0_rxdfelpmreset_in; wire gt0_rxdlysreset_i; wire [6:0]gt0_rxmonitorout_out; wire [1:0]gt0_rxmonitorsel_in; wire gt0_rxoutclk_out; wire gt0_rxoutclkfabric_out; wire [1:0]gt0_rxpd_in; wire [4:0]gt0_rxphmonitor_out; wire [4:0]gt0_rxphslipmonitor_out; wire gt0_rxpmareset_in; wire gt0_rxpolarity_in; wire gt0_rxresetdone_out; wire gt0_rxslide_in; wire gt0_rxuserrdy_t; wire gt0_rxusrclk2_in; wire gt0_rxusrclk_in; wire [19:0]gt0_txdata_in; wire [3:0]gt0_txdiffctrl_in; wire gt0_txdlysreset_i; wire gt0_txelecidle_in; wire gt0_txoutclk_out; wire gt0_txoutclkfabric_out; wire gt0_txoutclkpcs_out; wire [1:0]gt0_txpd_in; wire gt0_txpolarity_in; wire [4:0]gt0_txpostcursor_in; wire [4:0]gt0_txprecursor_in; wire gt0_txresetdone_out; wire gt0_txuserrdy_t; wire gt0_txusrclk2_in; wire gt0_txusrclk_in; wire gtxe2_i_n_41; wire NLW_gtxe2_i_GTREFCLKMONITOR_UNCONNECTED; wire NLW_gtxe2_i_PHYSTATUS_UNCONNECTED; wire NLW_gtxe2_i_RXBYTEISALIGNED_UNCONNECTED; wire NLW_gtxe2_i_RXBYTEREALIGN_UNCONNECTED; wire NLW_gtxe2_i_RXCDRLOCK_UNCONNECTED; wire NLW_gtxe2_i_RXCHANBONDSEQ_UNCONNECTED; wire NLW_gtxe2_i_RXCHANISALIGNED_UNCONNECTED; wire NLW_gtxe2_i_RXCHANREALIGN_UNCONNECTED; wire NLW_gtxe2_i_RXCOMINITDET_UNCONNECTED; wire NLW_gtxe2_i_RXCOMMADET_UNCONNECTED; wire NLW_gtxe2_i_RXCOMSASDET_UNCONNECTED; wire NLW_gtxe2_i_RXCOMWAKEDET_UNCONNECTED; wire NLW_gtxe2_i_RXDATAVALID_UNCONNECTED; wire NLW_gtxe2_i_RXELECIDLE_UNCONNECTED; wire NLW_gtxe2_i_RXHEADERVALID_UNCONNECTED; wire NLW_gtxe2_i_RXOUTCLKPCS_UNCONNECTED; wire NLW_gtxe2_i_RXPRBSERR_UNCONNECTED; wire NLW_gtxe2_i_RXQPISENN_UNCONNECTED; wire NLW_gtxe2_i_RXQPISENP_UNCONNECTED; wire NLW_gtxe2_i_RXRATEDONE_UNCONNECTED; wire NLW_gtxe2_i_RXSTARTOFSEQ_UNCONNECTED; wire NLW_gtxe2_i_RXVALID_UNCONNECTED; wire NLW_gtxe2_i_TXCOMFINISH_UNCONNECTED; wire NLW_gtxe2_i_TXGEARBOXREADY_UNCONNECTED; wire NLW_gtxe2_i_TXQPISENN_UNCONNECTED; wire NLW_gtxe2_i_TXQPISENP_UNCONNECTED; wire NLW_gtxe2_i_TXRATEDONE_UNCONNECTED; wire [15:0]NLW_gtxe2_i_PCSRSVDOUT_UNCONNECTED; wire [2:0]NLW_gtxe2_i_RXBUFSTATUS_UNCONNECTED; wire [7:0]NLW_gtxe2_i_RXCHARISCOMMA_UNCONNECTED; wire [7:2]NLW_gtxe2_i_RXCHARISK_UNCONNECTED; wire [4:0]NLW_gtxe2_i_RXCHBONDO_UNCONNECTED; wire [1:0]NLW_gtxe2_i_RXCLKCORCNT_UNCONNECTED; wire [63:16]NLW_gtxe2_i_RXDATA_UNCONNECTED; wire [7:2]NLW_gtxe2_i_RXDISPERR_UNCONNECTED; wire [2:0]NLW_gtxe2_i_RXHEADER_UNCONNECTED; wire [7:0]NLW_gtxe2_i_RXNOTINTABLE_UNCONNECTED; wire [2:0]NLW_gtxe2_i_RXSTATUS_UNCONNECTED; wire [9:0]NLW_gtxe2_i_TSTOUT_UNCONNECTED; wire [1:0]NLW_gtxe2_i_TXBUFSTATUS_UNCONNECTED; (* box_type = "PRIMITIVE" *) GTXE2_CHANNEL #( .ALIGN_COMMA_DOUBLE("FALSE"), .ALIGN_COMMA_ENABLE(10'b1111111111), .ALIGN_COMMA_WORD(2), .ALIGN_MCOMMA_DET("TRUE"), .ALIGN_MCOMMA_VALUE(10'b1010000011), .ALIGN_PCOMMA_DET("TRUE"), .ALIGN_PCOMMA_VALUE(10'b0101111100), .CBCC_DATA_SOURCE_SEL("ENCODED"), .CHAN_BOND_KEEP_ALIGN("FALSE"), .CHAN_BOND_MAX_SKEW(1), .CHAN_BOND_SEQ_1_1(10'b0000000000), .CHAN_BOND_SEQ_1_2(10'b0000000000), .CHAN_BOND_SEQ_1_3(10'b0000000000), .CHAN_BOND_SEQ_1_4(10'b0000000000), .CHAN_BOND_SEQ_1_ENABLE(4'b1111), .CHAN_BOND_SEQ_2_1(10'b0000000000), .CHAN_BOND_SEQ_2_2(10'b0000000000), .CHAN_BOND_SEQ_2_3(10'b0000000000), .CHAN_BOND_SEQ_2_4(10'b0000000000), .CHAN_BOND_SEQ_2_ENABLE(4'b1111), .CHAN_BOND_SEQ_2_USE("FALSE"), .CHAN_BOND_SEQ_LEN(1), .CLK_CORRECT_USE("FALSE"), .CLK_COR_KEEP_IDLE("FALSE"), .CLK_COR_MAX_LAT(10), .CLK_COR_MIN_LAT(8), .CLK_COR_PRECEDENCE("TRUE"), .CLK_COR_REPEAT_WAIT(0), .CLK_COR_SEQ_1_1(10'b0100000000), .CLK_COR_SEQ_1_2(10'b0000000000), .CLK_COR_SEQ_1_3(10'b0000000000), .CLK_COR_SEQ_1_4(10'b0000000000), .CLK_COR_SEQ_1_ENABLE(4'b1111), .CLK_COR_SEQ_2_1(10'b0100000000), .CLK_COR_SEQ_2_2(10'b0000000000), .CLK_COR_SEQ_2_3(10'b0000000000), .CLK_COR_SEQ_2_4(10'b0000000000), .CLK_COR_SEQ_2_ENABLE(4'b1111), .CLK_COR_SEQ_2_USE("FALSE"), .CLK_COR_SEQ_LEN(1), .CPLL_CFG(24'hBC07DC), .CPLL_FBDIV(4), .CPLL_FBDIV_45(5), .CPLL_INIT_CFG(24'h00001E), .CPLL_LOCK_CFG(16'h01E8), .CPLL_REFCLK_DIV(1), .DEC_MCOMMA_DETECT("TRUE"), .DEC_PCOMMA_DETECT("TRUE"), .DEC_VALID_COMMA_ONLY("FALSE"), .DMONITOR_CFG(24'h000A00), .ES_CONTROL(6'b000000), .ES_ERRDET_EN("FALSE"), .ES_EYE_SCAN_EN("TRUE"), .ES_HORZ_OFFSET(12'h000), .ES_PMA_CFG(10'b0000000000), .ES_PRESCALE(5'b00000), .ES_QUALIFIER(80'h00000000000000000000), .ES_QUAL_MASK(80'h00000000000000000000), .ES_SDATA_MASK(80'h00000000000000000000), .ES_VERT_OFFSET(9'b000000000), .FTS_DESKEW_SEQ_ENABLE(4'b1111), .FTS_LANE_DESKEW_CFG(4'b1111), .FTS_LANE_DESKEW_EN("FALSE"), .GEARBOX_MODE(3'b000), .IS_CPLLLOCKDETCLK_INVERTED(1'b0), .IS_DRPCLK_INVERTED(1'b0), .IS_GTGREFCLK_INVERTED(1'b0), .IS_RXUSRCLK2_INVERTED(1'b0), .IS_RXUSRCLK_INVERTED(1'b0), .IS_TXPHDLYTSTCLK_INVERTED(1'b0), .IS_TXUSRCLK2_INVERTED(1'b0), .IS_TXUSRCLK_INVERTED(1'b0), .OUTREFCLK_SEL_INV(2'b11), .PCS_PCIE_EN("FALSE"), .PCS_RSVD_ATTR(48'h000000000000), .PD_TRANS_TIME_FROM_P2(12'h03C), .PD_TRANS_TIME_NONE_P2(8'h3C), .PD_TRANS_TIME_TO_P2(8'h64), .PMA_RSV(32'h00018480), .PMA_RSV2(16'h2050), .PMA_RSV3(2'b00), .PMA_RSV4(32'h00000000), .RXBUFRESET_TIME(5'b00001), .RXBUF_ADDR_MODE("FAST"), .RXBUF_EIDLE_HI_CNT(4'b1000), .RXBUF_EIDLE_LO_CNT(4'b0000), .RXBUF_EN("FALSE"), .RXBUF_RESET_ON_CB_CHANGE("TRUE"), .RXBUF_RESET_ON_COMMAALIGN("FALSE"), .RXBUF_RESET_ON_EIDLE("FALSE"), .RXBUF_RESET_ON_RATE_CHANGE("TRUE"), .RXBUF_THRESH_OVFLW(61), .RXBUF_THRESH_OVRD("FALSE"), .RXBUF_THRESH_UNDFLW(4), .RXCDRFREQRESET_TIME(5'b00001), .RXCDRPHRESET_TIME(5'b00001), .RXCDR_CFG(72'h03000023FF40200020), .RXCDR_FR_RESET_ON_EIDLE(1'b0), .RXCDR_HOLD_DURING_EIDLE(1'b0), .RXCDR_LOCK_CFG(6'b010101), .RXCDR_PH_RESET_ON_EIDLE(1'b0), .RXDFELPMRESET_TIME(7'b0001111), .RXDLY_CFG(16'h001F), .RXDLY_LCFG(9'h030), .RXDLY_TAP_CFG(16'h0000), .RXGEARBOX_EN("FALSE"), .RXISCANRESET_TIME(5'b00001), .RXLPM_HF_CFG(14'b00000011110000), .RXLPM_LF_CFG(14'b00000011110000), .RXOOB_CFG(7'b0000110), .RXOUT_DIV(2), .RXPCSRESET_TIME(5'b00001), .RXPHDLY_CFG(24'h084020), .RXPH_CFG(24'h000000), .RXPH_MONITOR_SEL(5'b00000), .RXPMARESET_TIME(5'b00011), .RXPRBS_ERR_LOOPBACK(1'b0), .RXSLIDE_AUTO_WAIT(7), .RXSLIDE_MODE("PCS"), .RX_BIAS_CFG(12'b000000000100), .RX_BUFFER_CFG(6'b000000), .RX_CLK25_DIV(5), .RX_CLKMUX_PD(1'b1), .RX_CM_SEL(2'b11), .RX_CM_TRIM(3'b010), .RX_DATA_WIDTH(20), .RX_DDI_SEL(6'b000000), .RX_DEBUG_CFG(12'b000000000000), .RX_DEFER_RESET_BUF_EN("TRUE"), .RX_DFE_GAIN_CFG(23'h020FEA), .RX_DFE_H2_CFG(12'b000000000000), .RX_DFE_H3_CFG(12'b000001000000), .RX_DFE_H4_CFG(11'b00011110000), .RX_DFE_H5_CFG(11'b00011100000), .RX_DFE_KL_CFG(13'b0000011111110), .RX_DFE_KL_CFG2(32'h301148AC), .RX_DFE_LPM_CFG(16'h0954), .RX_DFE_LPM_HOLD_DURING_EIDLE(1'b0), .RX_DFE_UT_CFG(17'b10001111000000000), .RX_DFE_VP_CFG(17'b00011111100000011), .RX_DFE_XYD_CFG(13'b0000000000000), .RX_DISPERR_SEQ_MATCH("FALSE"), .RX_INT_DATAWIDTH(0), .RX_OS_CFG(13'b0000010000000), .RX_SIG_VALID_DLY(10), .RX_XCLK_SEL("RXUSR"), .SAS_MAX_COM(64), .SAS_MIN_COM(36), .SATA_BURST_SEQ_LEN(4'b0101), .SATA_BURST_VAL(3'b100), .SATA_CPLL_CFG("VCO_3000MHZ"), .SATA_EIDLE_VAL(3'b100), .SATA_MAX_BURST(8), .SATA_MAX_INIT(21), .SATA_MAX_WAKE(7), .SATA_MIN_BURST(4), .SATA_MIN_INIT(12), .SATA_MIN_WAKE(4), .SHOW_REALIGN_COMMA("FALSE"), .SIM_CPLLREFCLK_SEL(3'b010), .SIM_RECEIVER_DETECT_PASS("TRUE"), .SIM_RESET_SPEEDUP("TRUE"), .SIM_TX_EIDLE_DRIVE_LEVEL("X"), .SIM_VERSION("4.0"), .TERM_RCAL_CFG(5'b10000), .TERM_RCAL_OVRD(1'b0), .TRANS_TIME_RATE(8'h0E), .TST_RSV(32'h00000000), .TXBUF_EN("FALSE"), .TXBUF_RESET_ON_RATE_CHANGE("TRUE"), .TXDLY_CFG(16'h001F), .TXDLY_LCFG(9'h030), .TXDLY_TAP_CFG(16'h0000), .TXGEARBOX_EN("FALSE"), .TXOUT_DIV(2), .TXPCSRESET_TIME(5'b00001), .TXPHDLY_CFG(24'h084020), .TXPH_CFG(16'h0780), .TXPH_MONITOR_SEL(5'b00000), .TXPMARESET_TIME(5'b00001), .TX_CLK25_DIV(5), .TX_CLKMUX_PD(1'b1), .TX_DATA_WIDTH(20), .TX_DEEMPH0(5'b00000), .TX_DEEMPH1(5'b00000), .TX_DRIVE_MODE("DIRECT"), .TX_EIDLE_ASSERT_DELAY(3'b110), .TX_EIDLE_DEASSERT_DELAY(3'b100), .TX_INT_DATAWIDTH(0), .TX_LOOPBACK_DRIVE_HIZ("FALSE"), .TX_MAINCURSOR_SEL(1'b0), .TX_MARGIN_FULL_0(7'b1001110), .TX_MARGIN_FULL_1(7'b1001001), .TX_MARGIN_FULL_2(7'b1000101), .TX_MARGIN_FULL_3(7'b1000010), .TX_MARGIN_FULL_4(7'b1000000), .TX_MARGIN_LOW_0(7'b1000110), .TX_MARGIN_LOW_1(7'b1000100), .TX_MARGIN_LOW_2(7'b1000010), .TX_MARGIN_LOW_3(7'b1000000), .TX_MARGIN_LOW_4(7'b1000000), .TX_PREDRIVER_MODE(1'b0), .TX_QPI_STATUS_EN(1'b0), .TX_RXDETECT_CFG(14'h1832), .TX_RXDETECT_REF(3'b100), .TX_XCLK_SEL("TXUSR"), .UCODEER_CLR(1'b0)) gtxe2_i (.CFGRESET(1'b0), .CLKRSVD({1'b0,1'b0,1'b0,1'b0}), .CPLLFBCLKLOST(gt0_cpllfbclklost_out), .CPLLLOCK(gt0_cplllock_out), .CPLLLOCKDETCLK(gt0_cplllockdetclk_in), .CPLLLOCKEN(1'b1), .CPLLPD(cpllpd_in), .CPLLREFCLKLOST(gt0_cpllrefclklost_i), .CPLLREFCLKSEL({1'b0,1'b1,1'b0}), .CPLLRESET(cpllreset_in), .DMONITOROUT(gt0_dmonitorout_out), .DRPADDR(gt0_drpaddr_in), .DRPCLK(gt0_drpclk_in), .DRPDI(gt0_drpdi_in), .DRPDO(gt0_drpdo_out), .DRPEN(gt0_drpen_in), .DRPRDY(gt0_drprdy_out), .DRPWE(gt0_drpwe_in), .EYESCANDATAERROR(gt0_eyescandataerror_out), .EYESCANMODE(1'b0), .EYESCANRESET(gt0_eyescanreset_in), .EYESCANTRIGGER(gt0_eyescantrigger_in), .GTGREFCLK(1'b0), .GTNORTHREFCLK0(1'b0), .GTNORTHREFCLK1(1'b0), .GTREFCLK0(gt0_gtrefclk0_in), .GTREFCLK1(gt0_gtrefclk1_in), .GTREFCLKMONITOR(NLW_gtxe2_i_GTREFCLKMONITOR_UNCONNECTED), .GTRESETSEL(1'b0), .GTRSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .GTRXRESET(SR), .GTSOUTHREFCLK0(1'b0), .GTSOUTHREFCLK1(1'b0), .GTTXRESET(gt0_gttxreset_t), .GTXRXN(gt0_gtxrxn_in), .GTXRXP(gt0_gtxrxp_in), .GTXTXN(gt0_gtxtxn_out), .GTXTXP(gt0_gtxtxp_out), .LOOPBACK(gt0_loopback_in), .PCSRSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .PCSRSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}), .PCSRSVDOUT(NLW_gtxe2_i_PCSRSVDOUT_UNCONNECTED[15:0]), .PHYSTATUS(NLW_gtxe2_i_PHYSTATUS_UNCONNECTED), .PMARSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .PMARSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}), .QPLLCLK(GT0_QPLLOUTCLK_IN), .QPLLREFCLK(GT0_QPLLOUTREFCLK_IN), .RESETOVRD(1'b0), .RX8B10BEN(1'b0), .RXBUFRESET(1'b0), .RXBUFSTATUS(NLW_gtxe2_i_RXBUFSTATUS_UNCONNECTED[2:0]), .RXBYTEISALIGNED(NLW_gtxe2_i_RXBYTEISALIGNED_UNCONNECTED), .RXBYTEREALIGN(NLW_gtxe2_i_RXBYTEREALIGN_UNCONNECTED), .RXCDRFREQRESET(1'b0), .RXCDRHOLD(1'b0), .RXCDRLOCK(NLW_gtxe2_i_RXCDRLOCK_UNCONNECTED), .RXCDROVRDEN(1'b0), .RXCDRRESET(1'b0), .RXCDRRESETRSV(1'b0), .RXCHANBONDSEQ(NLW_gtxe2_i_RXCHANBONDSEQ_UNCONNECTED), .RXCHANISALIGNED(NLW_gtxe2_i_RXCHANISALIGNED_UNCONNECTED), .RXCHANREALIGN(NLW_gtxe2_i_RXCHANREALIGN_UNCONNECTED), .RXCHARISCOMMA(NLW_gtxe2_i_RXCHARISCOMMA_UNCONNECTED[7:0]), .RXCHARISK({NLW_gtxe2_i_RXCHARISK_UNCONNECTED[7:2],gt0_rxdata_out[18],gt0_rxdata_out[8]}), .RXCHBONDEN(1'b0), .RXCHBONDI({1'b0,1'b0,1'b0,1'b0,1'b0}), .RXCHBONDLEVEL({1'b0,1'b0,1'b0}), .RXCHBONDMASTER(1'b0), .RXCHBONDO(NLW_gtxe2_i_RXCHBONDO_UNCONNECTED[4:0]), .RXCHBONDSLAVE(1'b0), .RXCLKCORCNT(NLW_gtxe2_i_RXCLKCORCNT_UNCONNECTED[1:0]), .RXCOMINITDET(NLW_gtxe2_i_RXCOMINITDET_UNCONNECTED), .RXCOMMADET(NLW_gtxe2_i_RXCOMMADET_UNCONNECTED), .RXCOMMADETEN(1'b1), .RXCOMSASDET(NLW_gtxe2_i_RXCOMSASDET_UNCONNECTED), .RXCOMWAKEDET(NLW_gtxe2_i_RXCOMWAKEDET_UNCONNECTED), .RXDATA({NLW_gtxe2_i_RXDATA_UNCONNECTED[63:16],gt0_rxdata_out[17:10],gt0_rxdata_out[7:0]}), .RXDATAVALID(NLW_gtxe2_i_RXDATAVALID_UNCONNECTED), .RXDDIEN(1'b1), .RXDFEAGCHOLD(gt0_rxdfelfhold_i), .RXDFEAGCOVRDEN(1'b0), .RXDFECM1EN(1'b0), .RXDFELFHOLD(gt0_rxdfelfhold_i), .RXDFELFOVRDEN(1'b1), .RXDFELPMRESET(gt0_rxdfelpmreset_in), .RXDFETAP2HOLD(1'b0), .RXDFETAP2OVRDEN(1'b0), .RXDFETAP3HOLD(1'b0), .RXDFETAP3OVRDEN(1'b0), .RXDFETAP4HOLD(1'b0), .RXDFETAP4OVRDEN(1'b0), .RXDFETAP5HOLD(1'b0), .RXDFETAP5OVRDEN(1'b0), .RXDFEUTHOLD(1'b0), .RXDFEUTOVRDEN(1'b0), .RXDFEVPHOLD(1'b0), .RXDFEVPOVRDEN(1'b0), .RXDFEVSEN(1'b0), .RXDFEXYDEN(1'b1), .RXDFEXYDHOLD(1'b0), .RXDFEXYDOVRDEN(1'b0), .RXDISPERR({NLW_gtxe2_i_RXDISPERR_UNCONNECTED[7:2],gt0_rxdata_out[19],gt0_rxdata_out[9]}), .RXDLYBYPASS(1'b0), .RXDLYEN(1'b0), .RXDLYOVRDEN(1'b0), .RXDLYSRESET(gt0_rxdlysreset_i), .RXDLYSRESETDONE(gt0_cplllockdetclk_in_0), .RXELECIDLE(NLW_gtxe2_i_RXELECIDLE_UNCONNECTED), .RXELECIDLEMODE({1'b1,1'b1}), .RXGEARBOXSLIP(1'b0), .RXHEADER(NLW_gtxe2_i_RXHEADER_UNCONNECTED[2:0]), .RXHEADERVALID(NLW_gtxe2_i_RXHEADERVALID_UNCONNECTED), .RXLPMEN(1'b0), .RXLPMHFHOLD(1'b0), .RXLPMHFOVRDEN(1'b0), .RXLPMLFHOLD(1'b0), .RXLPMLFKLOVRDEN(1'b0), .RXMCOMMAALIGNEN(1'b0), .RXMONITOROUT(gt0_rxmonitorout_out), .RXMONITORSEL(gt0_rxmonitorsel_in), .RXNOTINTABLE(NLW_gtxe2_i_RXNOTINTABLE_UNCONNECTED[7:0]), .RXOOBRESET(1'b0), .RXOSHOLD(1'b0), .RXOSOVRDEN(1'b0), .RXOUTCLK(gt0_rxoutclk_out), .RXOUTCLKFABRIC(gt0_rxoutclkfabric_out), .RXOUTCLKPCS(NLW_gtxe2_i_RXOUTCLKPCS_UNCONNECTED), .RXOUTCLKSEL({1'b0,1'b1,1'b0}), .RXPCOMMAALIGNEN(1'b0), .RXPCSRESET(1'b0), .RXPD(gt0_rxpd_in), .RXPHALIGN(1'b0), .RXPHALIGNDONE(data_in), .RXPHALIGNEN(1'b0), .RXPHDLYPD(1'b0), .RXPHDLYRESET(1'b0), .RXPHMONITOR(gt0_rxphmonitor_out), .RXPHOVRDEN(1'b0), .RXPHSLIPMONITOR(gt0_rxphslipmonitor_out), .RXPMARESET(gt0_rxpmareset_in), .RXPOLARITY(gt0_rxpolarity_in), .RXPRBSCNTRESET(1'b0), .RXPRBSERR(NLW_gtxe2_i_RXPRBSERR_UNCONNECTED), .RXPRBSSEL({1'b0,1'b0,1'b0}), .RXQPIEN(1'b0), .RXQPISENN(NLW_gtxe2_i_RXQPISENN_UNCONNECTED), .RXQPISENP(NLW_gtxe2_i_RXQPISENP_UNCONNECTED), .RXRATE({1'b0,1'b0,1'b0}), .RXRATEDONE(NLW_gtxe2_i_RXRATEDONE_UNCONNECTED), .RXRESETDONE(gt0_rxresetdone_out), .RXSLIDE(gt0_rxslide_in), .RXSTARTOFSEQ(NLW_gtxe2_i_RXSTARTOFSEQ_UNCONNECTED), .RXSTATUS(NLW_gtxe2_i_RXSTATUS_UNCONNECTED[2:0]), .RXSYSCLKSEL({1'b0,1'b0}), .RXUSERRDY(gt0_rxuserrdy_t), .RXUSRCLK(gt0_rxusrclk_in), .RXUSRCLK2(gt0_rxusrclk2_in), .RXVALID(NLW_gtxe2_i_RXVALID_UNCONNECTED), .SETERRSTATUS(1'b0), .TSTIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), .TSTOUT(NLW_gtxe2_i_TSTOUT_UNCONNECTED[9:0]), .TX8B10BBYPASS({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .TX8B10BEN(1'b0), .TXBUFDIFFCTRL({1'b1,1'b0,1'b0}), .TXBUFSTATUS(NLW_gtxe2_i_TXBUFSTATUS_UNCONNECTED[1:0]), .TXCHARDISPMODE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,gt0_txdata_in[19],gt0_txdata_in[9]}), .TXCHARDISPVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,gt0_txdata_in[18],gt0_txdata_in[8]}), .TXCHARISK({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .TXCOMFINISH(NLW_gtxe2_i_TXCOMFINISH_UNCONNECTED), .TXCOMINIT(1'b0), .TXCOMSAS(1'b0), .TXCOMWAKE(1'b0), .TXDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,gt0_txdata_in[17:10],gt0_txdata_in[7:0]}), .TXDEEMPH(1'b0), .TXDETECTRX(1'b0), .TXDIFFCTRL(gt0_txdiffctrl_in), .TXDIFFPD(1'b0), .TXDLYBYPASS(1'b0), .TXDLYEN(1'b0), .TXDLYHOLD(1'b0), .TXDLYOVRDEN(1'b0), .TXDLYSRESET(gt0_txdlysreset_i), .TXDLYSRESETDONE(gt0_cplllockdetclk_in_1), .TXDLYUPDOWN(1'b0), .TXELECIDLE(gt0_txelecidle_in), .TXGEARBOXREADY(NLW_gtxe2_i_TXGEARBOXREADY_UNCONNECTED), .TXHEADER({1'b0,1'b0,1'b0}), .TXINHIBIT(1'b0), .TXMAINCURSOR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .TXMARGIN({1'b0,1'b0,1'b0}), .TXOUTCLK(gt0_txoutclk_out), .TXOUTCLKFABRIC(gt0_txoutclkfabric_out), .TXOUTCLKPCS(gt0_txoutclkpcs_out), .TXOUTCLKSEL({1'b0,1'b1,1'b1}), .TXPCSRESET(1'b0), .TXPD(gt0_txpd_in), .TXPDELECIDLEMODE(1'b0), .TXPHALIGN(1'b0), .TXPHALIGNDONE(gt0_cplllockdetclk_in_2), .TXPHALIGNEN(1'b0), .TXPHDLYPD(1'b0), .TXPHDLYRESET(1'b0), .TXPHDLYTSTCLK(1'b0), .TXPHINIT(1'b0), .TXPHINITDONE(gtxe2_i_n_41), .TXPHOVRDEN(1'b0), .TXPISOPD(1'b0), .TXPMARESET(1'b0), .TXPOLARITY(gt0_txpolarity_in), .TXPOSTCURSOR(gt0_txpostcursor_in), .TXPOSTCURSORINV(1'b0), .TXPRBSFORCEERR(1'b0), .TXPRBSSEL({1'b0,1'b0,1'b0}), .TXPRECURSOR(gt0_txprecursor_in), .TXPRECURSORINV(1'b0), .TXQPIBIASEN(1'b0), .TXQPISENN(NLW_gtxe2_i_TXQPISENN_UNCONNECTED), .TXQPISENP(NLW_gtxe2_i_TXQPISENP_UNCONNECTED), .TXQPISTRONGPDOWN(1'b0), .TXQPIWEAKPUP(1'b0), .TXRATE({1'b0,1'b0,1'b0}), .TXRATEDONE(NLW_gtxe2_i_TXRATEDONE_UNCONNECTED), .TXRESETDONE(gt0_txresetdone_out), .TXSEQUENCE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .TXSTARTSEQ(1'b0), .TXSWING(1'b0), .TXSYSCLKSEL({1'b0,1'b0}), .TXUSERRDY(gt0_txuserrdy_t), .TXUSRCLK(gt0_txusrclk_in), .TXUSRCLK2(gt0_txusrclk2_in)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_RX_STARTUP_FSM (SR, gt0_rxuserrdy_t, gt0_run_rx_phalignment_i, gt0_rxdfelfhold_i, run_phase_alignment_int_reg_0, gt0_rx_cdrlocked_reg, SYSCLK_IN, gt0_rxusrclk_in, GT0_RX_FSM_RESET_DONE_OUT, SOFT_RESET_RX_IN, \FSM_onehot_phalign_state_reg[0] , DONT_RESET_ON_DATA_ERROR_IN, gt0_rx_cdrlocked_reg_0, gt0_rx_cdrlocked_reg_1, gt0_rxresetdone_out, GT0_DATA_VALID_IN, gt0_cplllock_out); output [0:0]SR; output gt0_rxuserrdy_t; output gt0_run_rx_phalignment_i; output gt0_rxdfelfhold_i; output [0:0]run_phase_alignment_int_reg_0; output gt0_rx_cdrlocked_reg; input SYSCLK_IN; input gt0_rxusrclk_in; input GT0_RX_FSM_RESET_DONE_OUT; input SOFT_RESET_RX_IN; input \FSM_onehot_phalign_state_reg[0] ; input DONT_RESET_ON_DATA_ERROR_IN; input gt0_rx_cdrlocked_reg_0; input gt0_rx_cdrlocked_reg_1; input gt0_rxresetdone_out; input GT0_DATA_VALID_IN; input gt0_cplllock_out; wire DONT_RESET_ON_DATA_ERROR_IN; wire \FSM_onehot_phalign_state_reg[0] ; wire \FSM_sequential_rx_state[0]_i_2_n_0 ; wire \FSM_sequential_rx_state[1]_i_2_n_0 ; wire \FSM_sequential_rx_state[2]_i_1_n_0 ; wire \FSM_sequential_rx_state[2]_i_2_n_0 ; wire \FSM_sequential_rx_state[3]_i_11_n_0 ; wire \FSM_sequential_rx_state[3]_i_12_n_0 ; wire \FSM_sequential_rx_state[3]_i_3_n_0 ; wire \FSM_sequential_rx_state[3]_i_4_n_0 ; wire \FSM_sequential_rx_state[3]_i_5_n_0 ; wire \FSM_sequential_rx_state[3]_i_9_n_0 ; wire GT0_DATA_VALID_IN; wire GT0_RX_FSM_RESET_DONE_OUT; (* RTL_KEEP = "true" *) wire PHALIGNMENT_DONE_i; wire RXDFEAGCHOLD_i_1_n_0; wire RXUSERRDY_i_1_n_0; wire SOFT_RESET_RX_IN; wire [0:0]SR; wire SYSCLK_IN; wire adapt_count; wire \adapt_wait_hw.adapt_count[0]_i_3_n_0 ; wire \adapt_wait_hw.adapt_count[0]_i_4_n_0 ; wire \adapt_wait_hw.adapt_count[0]_i_5_n_0 ; wire \adapt_wait_hw.adapt_count[0]_i_6_n_0 ; wire [19:0]\adapt_wait_hw.adapt_count_reg ; wire \adapt_wait_hw.adapt_count_reg[0]_i_2_n_0 ; wire \adapt_wait_hw.adapt_count_reg[0]_i_2_n_1 ; wire \adapt_wait_hw.adapt_count_reg[0]_i_2_n_2 ; wire \adapt_wait_hw.adapt_count_reg[0]_i_2_n_3 ; wire \adapt_wait_hw.adapt_count_reg[0]_i_2_n_4 ; wire \adapt_wait_hw.adapt_count_reg[0]_i_2_n_5 ; wire \adapt_wait_hw.adapt_count_reg[0]_i_2_n_6 ; wire \adapt_wait_hw.adapt_count_reg[0]_i_2_n_7 ; wire \adapt_wait_hw.adapt_count_reg[12]_i_1_n_0 ; wire \adapt_wait_hw.adapt_count_reg[12]_i_1_n_1 ; wire \adapt_wait_hw.adapt_count_reg[12]_i_1_n_2 ; wire \adapt_wait_hw.adapt_count_reg[12]_i_1_n_3 ; wire \adapt_wait_hw.adapt_count_reg[12]_i_1_n_4 ; wire \adapt_wait_hw.adapt_count_reg[12]_i_1_n_5 ; wire \adapt_wait_hw.adapt_count_reg[12]_i_1_n_6 ; wire \adapt_wait_hw.adapt_count_reg[12]_i_1_n_7 ; wire \adapt_wait_hw.adapt_count_reg[16]_i_1_n_1 ; wire \adapt_wait_hw.adapt_count_reg[16]_i_1_n_2 ; wire \adapt_wait_hw.adapt_count_reg[16]_i_1_n_3 ; wire \adapt_wait_hw.adapt_count_reg[16]_i_1_n_4 ; wire \adapt_wait_hw.adapt_count_reg[16]_i_1_n_5 ; wire \adapt_wait_hw.adapt_count_reg[16]_i_1_n_6 ; wire \adapt_wait_hw.adapt_count_reg[16]_i_1_n_7 ; wire \adapt_wait_hw.adapt_count_reg[4]_i_1_n_0 ; wire \adapt_wait_hw.adapt_count_reg[4]_i_1_n_1 ; wire \adapt_wait_hw.adapt_count_reg[4]_i_1_n_2 ; wire \adapt_wait_hw.adapt_count_reg[4]_i_1_n_3 ; wire \adapt_wait_hw.adapt_count_reg[4]_i_1_n_4 ; wire \adapt_wait_hw.adapt_count_reg[4]_i_1_n_5 ; wire \adapt_wait_hw.adapt_count_reg[4]_i_1_n_6 ; wire \adapt_wait_hw.adapt_count_reg[4]_i_1_n_7 ; wire \adapt_wait_hw.adapt_count_reg[8]_i_1_n_0 ; wire \adapt_wait_hw.adapt_count_reg[8]_i_1_n_1 ; wire \adapt_wait_hw.adapt_count_reg[8]_i_1_n_2 ; wire \adapt_wait_hw.adapt_count_reg[8]_i_1_n_3 ; wire \adapt_wait_hw.adapt_count_reg[8]_i_1_n_4 ; wire \adapt_wait_hw.adapt_count_reg[8]_i_1_n_5 ; wire \adapt_wait_hw.adapt_count_reg[8]_i_1_n_6 ; wire \adapt_wait_hw.adapt_count_reg[8]_i_1_n_7 ; wire \adapt_wait_hw.time_out_adapt_i_1_n_0 ; wire \adapt_wait_hw.time_out_adapt_i_2_n_0 ; wire \adapt_wait_hw.time_out_adapt_i_3_n_0 ; wire \adapt_wait_hw.time_out_adapt_i_4_n_0 ; wire \adapt_wait_hw.time_out_adapt_i_5_n_0 ; wire \adapt_wait_hw.time_out_adapt_reg_n_0 ; wire check_tlock_max_i_1_n_0; wire check_tlock_max_reg_n_0; wire data_out; wire gt0_cplllock_out; wire gt0_run_rx_phalignment_i; wire gt0_rx_cdrlocked_reg; wire gt0_rx_cdrlocked_reg_0; wire gt0_rx_cdrlocked_reg_1; wire gt0_rxdfelfhold_i; wire gt0_rxresetdone_out; wire gt0_rxuserrdy_t; wire gt0_rxusrclk_in; wire gtrxreset_i_i_1_n_0; wire \init_wait_count[4]_i_1__0_n_0 ; wire [4:0]init_wait_count_reg__0; wire init_wait_done; wire init_wait_done_i_1__0_n_0; wire \mmcm_lock_count[7]_i_2__0_n_0 ; wire \mmcm_lock_count[7]_i_4__0_n_0 ; wire [7:0]mmcm_lock_count_reg__0; wire mmcm_lock_reclocked; wire [4:0]p_0_in; wire [7:0]p_0_in__0; wire recclk_mon_count_reset; wire reset_time_out_i_3_n_0; wire reset_time_out_i_4_n_0; wire reset_time_out_reg_n_0; wire run_phase_alignment_int_i_1__0_n_0; wire [0:0]run_phase_alignment_int_reg_0; wire run_phase_alignment_int_s3_reg_n_0; wire rx_fsm_reset_done_int_s2; wire rx_fsm_reset_done_int_s3; wire [3:0]rx_state; wire rxresetdone_s2; wire rxresetdone_s3; wire sync_CPLLLOCK_n_0; wire sync_CPLLLOCK_n_1; wire sync_CPLLLOCK_n_2; wire sync_data_valid_n_0; wire sync_data_valid_n_1; wire sync_data_valid_n_2; wire sync_data_valid_n_3; wire sync_data_valid_n_4; wire sync_data_valid_n_5; wire sync_mmcm_lock_reclocked_n_0; wire sync_mmcm_lock_reclocked_n_1; wire time_out_100us_i_1_n_0; wire time_out_100us_i_2_n_0; wire time_out_100us_i_3_n_0; wire time_out_100us_reg_n_0; wire time_out_2ms_i_1_n_0; wire time_out_2ms_i_2__0_n_0; wire time_out_2ms_reg_n_0; wire time_out_counter; wire \time_out_counter[0]_i_3__0_n_0 ; wire \time_out_counter[0]_i_4_n_0 ; wire \time_out_counter[0]_i_5__0_n_0 ; wire \time_out_counter[0]_i_6_n_0 ; wire [16:0]time_out_counter_reg; wire \time_out_counter_reg[0]_i_2__0_n_0 ; wire \time_out_counter_reg[0]_i_2__0_n_1 ; wire \time_out_counter_reg[0]_i_2__0_n_2 ; wire \time_out_counter_reg[0]_i_2__0_n_3 ; wire \time_out_counter_reg[0]_i_2__0_n_4 ; wire \time_out_counter_reg[0]_i_2__0_n_5 ; wire \time_out_counter_reg[0]_i_2__0_n_6 ; wire \time_out_counter_reg[0]_i_2__0_n_7 ; wire \time_out_counter_reg[12]_i_1__0_n_0 ; wire \time_out_counter_reg[12]_i_1__0_n_1 ; wire \time_out_counter_reg[12]_i_1__0_n_2 ; wire \time_out_counter_reg[12]_i_1__0_n_3 ; wire \time_out_counter_reg[12]_i_1__0_n_4 ; wire \time_out_counter_reg[12]_i_1__0_n_5 ; wire \time_out_counter_reg[12]_i_1__0_n_6 ; wire \time_out_counter_reg[12]_i_1__0_n_7 ; wire \time_out_counter_reg[16]_i_1__0_n_7 ; wire \time_out_counter_reg[4]_i_1__0_n_0 ; wire \time_out_counter_reg[4]_i_1__0_n_1 ; wire \time_out_counter_reg[4]_i_1__0_n_2 ; wire \time_out_counter_reg[4]_i_1__0_n_3 ; wire \time_out_counter_reg[4]_i_1__0_n_4 ; wire \time_out_counter_reg[4]_i_1__0_n_5 ; wire \time_out_counter_reg[4]_i_1__0_n_6 ; wire \time_out_counter_reg[4]_i_1__0_n_7 ; wire \time_out_counter_reg[8]_i_1__0_n_0 ; wire \time_out_counter_reg[8]_i_1__0_n_1 ; wire \time_out_counter_reg[8]_i_1__0_n_2 ; wire \time_out_counter_reg[8]_i_1__0_n_3 ; wire \time_out_counter_reg[8]_i_1__0_n_4 ; wire \time_out_counter_reg[8]_i_1__0_n_5 ; wire \time_out_counter_reg[8]_i_1__0_n_6 ; wire \time_out_counter_reg[8]_i_1__0_n_7 ; wire time_out_wait_bypass_i_1__0_n_0; wire time_out_wait_bypass_reg_n_0; wire time_out_wait_bypass_s2; wire time_out_wait_bypass_s3; wire time_tlock_max; wire time_tlock_max1; wire time_tlock_max1_carry__0_i_1_n_0; wire time_tlock_max1_carry__0_i_2_n_0; wire time_tlock_max1_carry__0_i_3_n_0; wire time_tlock_max1_carry__0_i_4_n_0; wire time_tlock_max1_carry__0_i_5_n_0; wire time_tlock_max1_carry__0_i_6_n_0; wire time_tlock_max1_carry__0_n_0; wire time_tlock_max1_carry__0_n_1; wire time_tlock_max1_carry__0_n_2; wire time_tlock_max1_carry__0_n_3; wire time_tlock_max1_carry__1_i_1_n_0; wire time_tlock_max1_carry_i_1_n_0; wire time_tlock_max1_carry_i_2_n_0; wire time_tlock_max1_carry_i_3_n_0; wire time_tlock_max1_carry_i_4_n_0; wire time_tlock_max1_carry_i_5_n_0; wire time_tlock_max1_carry_i_6_n_0; wire time_tlock_max1_carry_i_7_n_0; wire time_tlock_max1_carry_i_8_n_0; wire time_tlock_max1_carry_n_0; wire time_tlock_max1_carry_n_1; wire time_tlock_max1_carry_n_2; wire time_tlock_max1_carry_n_3; wire time_tlock_max_i_1_n_0; wire \wait_bypass_count[0]_i_1__0_n_0 ; wire \wait_bypass_count[0]_i_2__0_n_0 ; wire \wait_bypass_count[0]_i_4__0_n_0 ; wire \wait_bypass_count[0]_i_5__0_n_0 ; wire \wait_bypass_count[0]_i_6__0_n_0 ; wire \wait_bypass_count[0]_i_7__0_n_0 ; wire [12:0]wait_bypass_count_reg; wire \wait_bypass_count_reg[0]_i_3__0_n_0 ; wire \wait_bypass_count_reg[0]_i_3__0_n_1 ; wire \wait_bypass_count_reg[0]_i_3__0_n_2 ; wire \wait_bypass_count_reg[0]_i_3__0_n_3 ; wire \wait_bypass_count_reg[0]_i_3__0_n_4 ; wire \wait_bypass_count_reg[0]_i_3__0_n_5 ; wire \wait_bypass_count_reg[0]_i_3__0_n_6 ; wire \wait_bypass_count_reg[0]_i_3__0_n_7 ; wire \wait_bypass_count_reg[12]_i_1__0_n_7 ; wire \wait_bypass_count_reg[4]_i_1__0_n_0 ; wire \wait_bypass_count_reg[4]_i_1__0_n_1 ; wire \wait_bypass_count_reg[4]_i_1__0_n_2 ; wire \wait_bypass_count_reg[4]_i_1__0_n_3 ; wire \wait_bypass_count_reg[4]_i_1__0_n_4 ; wire \wait_bypass_count_reg[4]_i_1__0_n_5 ; wire \wait_bypass_count_reg[4]_i_1__0_n_6 ; wire \wait_bypass_count_reg[4]_i_1__0_n_7 ; wire \wait_bypass_count_reg[8]_i_1__0_n_0 ; wire \wait_bypass_count_reg[8]_i_1__0_n_1 ; wire \wait_bypass_count_reg[8]_i_1__0_n_2 ; wire \wait_bypass_count_reg[8]_i_1__0_n_3 ; wire \wait_bypass_count_reg[8]_i_1__0_n_4 ; wire \wait_bypass_count_reg[8]_i_1__0_n_5 ; wire \wait_bypass_count_reg[8]_i_1__0_n_6 ; wire \wait_bypass_count_reg[8]_i_1__0_n_7 ; wire [6:0]wait_time_cnt0; wire \wait_time_cnt[6]_i_1_n_0 ; wire \wait_time_cnt[6]_i_2__0_n_0 ; wire \wait_time_cnt[6]_i_4__0_n_0 ; wire [6:0]wait_time_cnt_reg__0; wire [3:3]\NLW_adapt_wait_hw.adapt_count_reg[16]_i_1_CO_UNCONNECTED ; wire [3:0]\NLW_time_out_counter_reg[16]_i_1__0_CO_UNCONNECTED ; wire [3:1]\NLW_time_out_counter_reg[16]_i_1__0_O_UNCONNECTED ; wire [3:0]NLW_time_tlock_max1_carry_O_UNCONNECTED; wire [3:0]NLW_time_tlock_max1_carry__0_O_UNCONNECTED; wire [3:1]NLW_time_tlock_max1_carry__1_CO_UNCONNECTED; wire [3:0]NLW_time_tlock_max1_carry__1_O_UNCONNECTED; wire [3:0]\NLW_wait_bypass_count_reg[12]_i_1__0_CO_UNCONNECTED ; wire [3:1]\NLW_wait_bypass_count_reg[12]_i_1__0_O_UNCONNECTED ; (* SOFT_HLUTNM = "soft_lutpair11" *) LUT2 #( .INIT(4'h7)) \FSM_onehot_phalign_state[3]_i_1 (.I0(gt0_run_rx_phalignment_i), .I1(\FSM_onehot_phalign_state_reg[0] ), .O(run_phase_alignment_int_reg_0)); LUT6 #( .INIT(64'h22220030AAAA0000)) \FSM_sequential_rx_state[0]_i_2 (.I0(time_out_2ms_reg_n_0), .I1(reset_time_out_reg_n_0), .I2(time_tlock_max), .I3(rx_state[3]), .I4(rx_state[1]), .I5(rx_state[2]), .O(\FSM_sequential_rx_state[0]_i_2_n_0 )); LUT5 #( .INIT(32'h00070000)) \FSM_sequential_rx_state[1]_i_2 (.I0(time_tlock_max), .I1(rx_state[2]), .I2(rx_state[3]), .I3(rx_state[1]), .I4(rx_state[0]), .O(\FSM_sequential_rx_state[1]_i_2_n_0 )); LUT6 #( .INIT(64'h000008380000CCCC)) \FSM_sequential_rx_state[2]_i_1 (.I0(\FSM_sequential_rx_state[2]_i_2_n_0 ), .I1(rx_state[2]), .I2(rx_state[1]), .I3(time_out_2ms_reg_n_0), .I4(rx_state[3]), .I5(rx_state[0]), .O(\FSM_sequential_rx_state[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair10" *) LUT2 #( .INIT(4'hB)) \FSM_sequential_rx_state[2]_i_2 (.I0(reset_time_out_reg_n_0), .I1(time_tlock_max), .O(\FSM_sequential_rx_state[2]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair4" *) LUT2 #( .INIT(4'hB)) \FSM_sequential_rx_state[3]_i_11 (.I0(reset_time_out_reg_n_0), .I1(time_out_2ms_reg_n_0), .O(\FSM_sequential_rx_state[3]_i_11_n_0 )); (* SOFT_HLUTNM = "soft_lutpair6" *) LUT2 #( .INIT(4'h2)) \FSM_sequential_rx_state[3]_i_12 (.I0(time_out_2ms_reg_n_0), .I1(rx_state[2]), .O(\FSM_sequential_rx_state[3]_i_12_n_0 )); LUT6 #( .INIT(64'h00020002000F0000)) \FSM_sequential_rx_state[3]_i_3 (.I0(\FSM_onehot_phalign_state_reg[0] ), .I1(rx_state[0]), .I2(rx_state[1]), .I3(rx_state[3]), .I4(init_wait_done), .I5(rx_state[2]), .O(\FSM_sequential_rx_state[3]_i_3_n_0 )); LUT6 #( .INIT(64'h0055000300000000)) \FSM_sequential_rx_state[3]_i_4 (.I0(\FSM_sequential_rx_state[3]_i_11_n_0 ), .I1(\wait_time_cnt[6]_i_4__0_n_0 ), .I2(wait_time_cnt_reg__0[6]), .I3(rx_state[3]), .I4(rx_state[0]), .I5(rx_state[1]), .O(\FSM_sequential_rx_state[3]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair3" *) LUT4 #( .INIT(16'h0002)) \FSM_sequential_rx_state[3]_i_5 (.I0(rx_state[0]), .I1(rx_state[1]), .I2(rx_state[3]), .I3(rx_state[2]), .O(\FSM_sequential_rx_state[3]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair6" *) LUT5 #( .INIT(32'h80800080)) \FSM_sequential_rx_state[3]_i_9 (.I0(rx_state[0]), .I1(rx_state[1]), .I2(rx_state[2]), .I3(time_out_2ms_reg_n_0), .I4(reset_time_out_reg_n_0), .O(\FSM_sequential_rx_state[3]_i_9_n_0 )); (* FSM_ENCODED_STATES = "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *) FDRE #( .INIT(1'b0)) \FSM_sequential_rx_state_reg[0] (.C(SYSCLK_IN), .CE(sync_data_valid_n_0), .D(sync_data_valid_n_3), .Q(rx_state[0]), .R(SOFT_RESET_RX_IN)); (* FSM_ENCODED_STATES = "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *) FDRE #( .INIT(1'b0)) \FSM_sequential_rx_state_reg[1] (.C(SYSCLK_IN), .CE(sync_data_valid_n_0), .D(sync_data_valid_n_2), .Q(rx_state[1]), .R(SOFT_RESET_RX_IN)); (* FSM_ENCODED_STATES = "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *) FDRE #( .INIT(1'b0)) \FSM_sequential_rx_state_reg[2] (.C(SYSCLK_IN), .CE(sync_data_valid_n_0), .D(\FSM_sequential_rx_state[2]_i_1_n_0 ), .Q(rx_state[2]), .R(SOFT_RESET_RX_IN)); (* FSM_ENCODED_STATES = "release_pll_reset:0011,verify_recclk_stable:0100,wait_for_pll_lock:0010,fsm_done:1010,assert_all_resets:0001,init:0000,wait_reset_done:0111,monitor_data_valid:1001,wait_for_rxusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *) FDRE #( .INIT(1'b0)) \FSM_sequential_rx_state_reg[3] (.C(SYSCLK_IN), .CE(sync_data_valid_n_0), .D(sync_data_valid_n_1), .Q(rx_state[3]), .R(SOFT_RESET_RX_IN)); (* KEEP = "yes" *) (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) PHALIGNMENT_DONE_i_reg (.C(SYSCLK_IN), .CE(1'b1), .D(GT0_RX_FSM_RESET_DONE_OUT), .Q(PHALIGNMENT_DONE_i), .R(1'b0)); LUT6 #( .INIT(64'hFFFFFFFF00080000)) RXDFEAGCHOLD_i_1 (.I0(\adapt_wait_hw.time_out_adapt_reg_n_0 ), .I1(rx_state[1]), .I2(rx_state[2]), .I3(rx_state[0]), .I4(rx_state[3]), .I5(gt0_rxdfelfhold_i), .O(RXDFEAGCHOLD_i_1_n_0)); FDRE RXDFEAGCHOLD_reg (.C(SYSCLK_IN), .CE(1'b1), .D(RXDFEAGCHOLD_i_1_n_0), .Q(gt0_rxdfelfhold_i), .R(SOFT_RESET_RX_IN)); LUT5 #( .INIT(32'hFEFF2000)) RXUSERRDY_i_1 (.I0(rx_state[2]), .I1(rx_state[3]), .I2(rx_state[1]), .I3(rx_state[0]), .I4(gt0_rxuserrdy_t), .O(RXUSERRDY_i_1_n_0)); FDRE #( .INIT(1'b0)) RXUSERRDY_reg (.C(SYSCLK_IN), .CE(1'b1), .D(RXUSERRDY_i_1_n_0), .Q(gt0_rxuserrdy_t), .R(SOFT_RESET_RX_IN)); FDSE #( .INIT(1'b0)) adapt_count_reset_reg (.C(SYSCLK_IN), .CE(1'b1), .D(sync_CPLLLOCK_n_2), .Q(recclk_mon_count_reset), .S(SOFT_RESET_RX_IN)); LUT5 #( .INIT(32'hFFFFFFF7)) \adapt_wait_hw.adapt_count[0]_i_1 (.I0(\adapt_wait_hw.adapt_count_reg [0]), .I1(\adapt_wait_hw.adapt_count_reg [1]), .I2(\adapt_wait_hw.adapt_count[0]_i_3_n_0 ), .I3(\adapt_wait_hw.adapt_count[0]_i_4_n_0 ), .I4(\adapt_wait_hw.adapt_count[0]_i_5_n_0 ), .O(adapt_count)); LUT6 #( .INIT(64'hFFDFFFFFFFFFFFFF)) \adapt_wait_hw.adapt_count[0]_i_3 (.I0(\adapt_wait_hw.adapt_count_reg [7]), .I1(\adapt_wait_hw.adapt_count_reg [6]), .I2(\adapt_wait_hw.adapt_count_reg [4]), .I3(\adapt_wait_hw.adapt_count_reg [5]), .I4(\adapt_wait_hw.adapt_count_reg [3]), .I5(\adapt_wait_hw.adapt_count_reg [2]), .O(\adapt_wait_hw.adapt_count[0]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFDFFFFFFFFFFF)) \adapt_wait_hw.adapt_count[0]_i_4 (.I0(\adapt_wait_hw.adapt_count_reg [19]), .I1(\adapt_wait_hw.adapt_count_reg [18]), .I2(\adapt_wait_hw.adapt_count_reg [16]), .I3(\adapt_wait_hw.adapt_count_reg [17]), .I4(\adapt_wait_hw.adapt_count_reg [15]), .I5(\adapt_wait_hw.adapt_count_reg [14]), .O(\adapt_wait_hw.adapt_count[0]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFFEFFFFFFFFF)) \adapt_wait_hw.adapt_count[0]_i_5 (.I0(\adapt_wait_hw.adapt_count_reg [12]), .I1(\adapt_wait_hw.adapt_count_reg [13]), .I2(\adapt_wait_hw.adapt_count_reg [11]), .I3(\adapt_wait_hw.adapt_count_reg [10]), .I4(\adapt_wait_hw.adapt_count_reg [8]), .I5(\adapt_wait_hw.adapt_count_reg [9]), .O(\adapt_wait_hw.adapt_count[0]_i_5_n_0 )); LUT1 #( .INIT(2'h1)) \adapt_wait_hw.adapt_count[0]_i_6 (.I0(\adapt_wait_hw.adapt_count_reg [0]), .O(\adapt_wait_hw.adapt_count[0]_i_6_n_0 )); FDRE \adapt_wait_hw.adapt_count_reg[0] (.C(SYSCLK_IN), .CE(adapt_count), .D(\adapt_wait_hw.adapt_count_reg[0]_i_2_n_7 ), .Q(\adapt_wait_hw.adapt_count_reg [0]), .R(recclk_mon_count_reset)); CARRY4 \adapt_wait_hw.adapt_count_reg[0]_i_2 (.CI(1'b0), .CO({\adapt_wait_hw.adapt_count_reg[0]_i_2_n_0 ,\adapt_wait_hw.adapt_count_reg[0]_i_2_n_1 ,\adapt_wait_hw.adapt_count_reg[0]_i_2_n_2 ,\adapt_wait_hw.adapt_count_reg[0]_i_2_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b1}), .O({\adapt_wait_hw.adapt_count_reg[0]_i_2_n_4 ,\adapt_wait_hw.adapt_count_reg[0]_i_2_n_5 ,\adapt_wait_hw.adapt_count_reg[0]_i_2_n_6 ,\adapt_wait_hw.adapt_count_reg[0]_i_2_n_7 }), .S({\adapt_wait_hw.adapt_count_reg [3:1],\adapt_wait_hw.adapt_count[0]_i_6_n_0 })); FDRE \adapt_wait_hw.adapt_count_reg[10] (.C(SYSCLK_IN), .CE(adapt_count), .D(\adapt_wait_hw.adapt_count_reg[8]_i_1_n_5 ), .Q(\adapt_wait_hw.adapt_count_reg [10]), .R(recclk_mon_count_reset)); FDRE \adapt_wait_hw.adapt_count_reg[11] (.C(SYSCLK_IN), .CE(adapt_count), .D(\adapt_wait_hw.adapt_count_reg[8]_i_1_n_4 ), .Q(\adapt_wait_hw.adapt_count_reg [11]), .R(recclk_mon_count_reset)); FDRE \adapt_wait_hw.adapt_count_reg[12] (.C(SYSCLK_IN), .CE(adapt_count), .D(\adapt_wait_hw.adapt_count_reg[12]_i_1_n_7 ), .Q(\adapt_wait_hw.adapt_count_reg [12]), .R(recclk_mon_count_reset)); CARRY4 \adapt_wait_hw.adapt_count_reg[12]_i_1 (.CI(\adapt_wait_hw.adapt_count_reg[8]_i_1_n_0 ), .CO({\adapt_wait_hw.adapt_count_reg[12]_i_1_n_0 ,\adapt_wait_hw.adapt_count_reg[12]_i_1_n_1 ,\adapt_wait_hw.adapt_count_reg[12]_i_1_n_2 ,\adapt_wait_hw.adapt_count_reg[12]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\adapt_wait_hw.adapt_count_reg[12]_i_1_n_4 ,\adapt_wait_hw.adapt_count_reg[12]_i_1_n_5 ,\adapt_wait_hw.adapt_count_reg[12]_i_1_n_6 ,\adapt_wait_hw.adapt_count_reg[12]_i_1_n_7 }), .S(\adapt_wait_hw.adapt_count_reg [15:12])); FDRE \adapt_wait_hw.adapt_count_reg[13] (.C(SYSCLK_IN), .CE(adapt_count), .D(\adapt_wait_hw.adapt_count_reg[12]_i_1_n_6 ), .Q(\adapt_wait_hw.adapt_count_reg [13]), .R(recclk_mon_count_reset)); FDRE \adapt_wait_hw.adapt_count_reg[14] (.C(SYSCLK_IN), .CE(adapt_count), .D(\adapt_wait_hw.adapt_count_reg[12]_i_1_n_5 ), .Q(\adapt_wait_hw.adapt_count_reg [14]), .R(recclk_mon_count_reset)); FDRE \adapt_wait_hw.adapt_count_reg[15] (.C(SYSCLK_IN), .CE(adapt_count), .D(\adapt_wait_hw.adapt_count_reg[12]_i_1_n_4 ), .Q(\adapt_wait_hw.adapt_count_reg [15]), .R(recclk_mon_count_reset)); FDRE \adapt_wait_hw.adapt_count_reg[16] (.C(SYSCLK_IN), .CE(adapt_count), .D(\adapt_wait_hw.adapt_count_reg[16]_i_1_n_7 ), .Q(\adapt_wait_hw.adapt_count_reg [16]), .R(recclk_mon_count_reset)); CARRY4 \adapt_wait_hw.adapt_count_reg[16]_i_1 (.CI(\adapt_wait_hw.adapt_count_reg[12]_i_1_n_0 ), .CO({\NLW_adapt_wait_hw.adapt_count_reg[16]_i_1_CO_UNCONNECTED [3],\adapt_wait_hw.adapt_count_reg[16]_i_1_n_1 ,\adapt_wait_hw.adapt_count_reg[16]_i_1_n_2 ,\adapt_wait_hw.adapt_count_reg[16]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\adapt_wait_hw.adapt_count_reg[16]_i_1_n_4 ,\adapt_wait_hw.adapt_count_reg[16]_i_1_n_5 ,\adapt_wait_hw.adapt_count_reg[16]_i_1_n_6 ,\adapt_wait_hw.adapt_count_reg[16]_i_1_n_7 }), .S(\adapt_wait_hw.adapt_count_reg [19:16])); FDRE \adapt_wait_hw.adapt_count_reg[17] (.C(SYSCLK_IN), .CE(adapt_count), .D(\adapt_wait_hw.adapt_count_reg[16]_i_1_n_6 ), .Q(\adapt_wait_hw.adapt_count_reg [17]), .R(recclk_mon_count_reset)); FDRE \adapt_wait_hw.adapt_count_reg[18] (.C(SYSCLK_IN), .CE(adapt_count), .D(\adapt_wait_hw.adapt_count_reg[16]_i_1_n_5 ), .Q(\adapt_wait_hw.adapt_count_reg [18]), .R(recclk_mon_count_reset)); FDRE \adapt_wait_hw.adapt_count_reg[19] (.C(SYSCLK_IN), .CE(adapt_count), .D(\adapt_wait_hw.adapt_count_reg[16]_i_1_n_4 ), .Q(\adapt_wait_hw.adapt_count_reg [19]), .R(recclk_mon_count_reset)); FDRE \adapt_wait_hw.adapt_count_reg[1] (.C(SYSCLK_IN), .CE(adapt_count), .D(\adapt_wait_hw.adapt_count_reg[0]_i_2_n_6 ), .Q(\adapt_wait_hw.adapt_count_reg [1]), .R(recclk_mon_count_reset)); FDRE \adapt_wait_hw.adapt_count_reg[2] (.C(SYSCLK_IN), .CE(adapt_count), .D(\adapt_wait_hw.adapt_count_reg[0]_i_2_n_5 ), .Q(\adapt_wait_hw.adapt_count_reg [2]), .R(recclk_mon_count_reset)); FDRE \adapt_wait_hw.adapt_count_reg[3] (.C(SYSCLK_IN), .CE(adapt_count), .D(\adapt_wait_hw.adapt_count_reg[0]_i_2_n_4 ), .Q(\adapt_wait_hw.adapt_count_reg [3]), .R(recclk_mon_count_reset)); FDRE \adapt_wait_hw.adapt_count_reg[4] (.C(SYSCLK_IN), .CE(adapt_count), .D(\adapt_wait_hw.adapt_count_reg[4]_i_1_n_7 ), .Q(\adapt_wait_hw.adapt_count_reg [4]), .R(recclk_mon_count_reset)); CARRY4 \adapt_wait_hw.adapt_count_reg[4]_i_1 (.CI(\adapt_wait_hw.adapt_count_reg[0]_i_2_n_0 ), .CO({\adapt_wait_hw.adapt_count_reg[4]_i_1_n_0 ,\adapt_wait_hw.adapt_count_reg[4]_i_1_n_1 ,\adapt_wait_hw.adapt_count_reg[4]_i_1_n_2 ,\adapt_wait_hw.adapt_count_reg[4]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\adapt_wait_hw.adapt_count_reg[4]_i_1_n_4 ,\adapt_wait_hw.adapt_count_reg[4]_i_1_n_5 ,\adapt_wait_hw.adapt_count_reg[4]_i_1_n_6 ,\adapt_wait_hw.adapt_count_reg[4]_i_1_n_7 }), .S(\adapt_wait_hw.adapt_count_reg [7:4])); FDRE \adapt_wait_hw.adapt_count_reg[5] (.C(SYSCLK_IN), .CE(adapt_count), .D(\adapt_wait_hw.adapt_count_reg[4]_i_1_n_6 ), .Q(\adapt_wait_hw.adapt_count_reg [5]), .R(recclk_mon_count_reset)); FDRE \adapt_wait_hw.adapt_count_reg[6] (.C(SYSCLK_IN), .CE(adapt_count), .D(\adapt_wait_hw.adapt_count_reg[4]_i_1_n_5 ), .Q(\adapt_wait_hw.adapt_count_reg [6]), .R(recclk_mon_count_reset)); FDRE \adapt_wait_hw.adapt_count_reg[7] (.C(SYSCLK_IN), .CE(adapt_count), .D(\adapt_wait_hw.adapt_count_reg[4]_i_1_n_4 ), .Q(\adapt_wait_hw.adapt_count_reg [7]), .R(recclk_mon_count_reset)); FDRE \adapt_wait_hw.adapt_count_reg[8] (.C(SYSCLK_IN), .CE(adapt_count), .D(\adapt_wait_hw.adapt_count_reg[8]_i_1_n_7 ), .Q(\adapt_wait_hw.adapt_count_reg [8]), .R(recclk_mon_count_reset)); CARRY4 \adapt_wait_hw.adapt_count_reg[8]_i_1 (.CI(\adapt_wait_hw.adapt_count_reg[4]_i_1_n_0 ), .CO({\adapt_wait_hw.adapt_count_reg[8]_i_1_n_0 ,\adapt_wait_hw.adapt_count_reg[8]_i_1_n_1 ,\adapt_wait_hw.adapt_count_reg[8]_i_1_n_2 ,\adapt_wait_hw.adapt_count_reg[8]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\adapt_wait_hw.adapt_count_reg[8]_i_1_n_4 ,\adapt_wait_hw.adapt_count_reg[8]_i_1_n_5 ,\adapt_wait_hw.adapt_count_reg[8]_i_1_n_6 ,\adapt_wait_hw.adapt_count_reg[8]_i_1_n_7 }), .S(\adapt_wait_hw.adapt_count_reg [11:8])); FDRE \adapt_wait_hw.adapt_count_reg[9] (.C(SYSCLK_IN), .CE(adapt_count), .D(\adapt_wait_hw.adapt_count_reg[8]_i_1_n_6 ), .Q(\adapt_wait_hw.adapt_count_reg [9]), .R(recclk_mon_count_reset)); LUT6 #( .INIT(64'h00000000EAAAAAAA)) \adapt_wait_hw.time_out_adapt_i_1 (.I0(\adapt_wait_hw.time_out_adapt_reg_n_0 ), .I1(\adapt_wait_hw.time_out_adapt_i_2_n_0 ), .I2(\adapt_wait_hw.time_out_adapt_i_3_n_0 ), .I3(\adapt_wait_hw.time_out_adapt_i_4_n_0 ), .I4(\adapt_wait_hw.time_out_adapt_i_5_n_0 ), .I5(recclk_mon_count_reset), .O(\adapt_wait_hw.time_out_adapt_i_1_n_0 )); LUT6 #( .INIT(64'h0000008000000000)) \adapt_wait_hw.time_out_adapt_i_2 (.I0(\adapt_wait_hw.adapt_count_reg [16]), .I1(\adapt_wait_hw.adapt_count_reg [17]), .I2(\adapt_wait_hw.adapt_count_reg [14]), .I3(\adapt_wait_hw.adapt_count_reg [15]), .I4(\adapt_wait_hw.adapt_count_reg [18]), .I5(\adapt_wait_hw.adapt_count_reg [19]), .O(\adapt_wait_hw.time_out_adapt_i_2_n_0 )); LUT6 #( .INIT(64'h0000200000000000)) \adapt_wait_hw.time_out_adapt_i_3 (.I0(\adapt_wait_hw.adapt_count_reg [4]), .I1(\adapt_wait_hw.adapt_count_reg [5]), .I2(\adapt_wait_hw.adapt_count_reg [2]), .I3(\adapt_wait_hw.adapt_count_reg [3]), .I4(\adapt_wait_hw.adapt_count_reg [6]), .I5(\adapt_wait_hw.adapt_count_reg [7]), .O(\adapt_wait_hw.time_out_adapt_i_3_n_0 )); LUT6 #( .INIT(64'h0000000000000020)) \adapt_wait_hw.time_out_adapt_i_4 (.I0(\adapt_wait_hw.adapt_count_reg [11]), .I1(\adapt_wait_hw.adapt_count_reg [10]), .I2(\adapt_wait_hw.adapt_count_reg [9]), .I3(\adapt_wait_hw.adapt_count_reg [8]), .I4(\adapt_wait_hw.adapt_count_reg [13]), .I5(\adapt_wait_hw.adapt_count_reg [12]), .O(\adapt_wait_hw.time_out_adapt_i_4_n_0 )); LUT2 #( .INIT(4'h8)) \adapt_wait_hw.time_out_adapt_i_5 (.I0(\adapt_wait_hw.adapt_count_reg [0]), .I1(\adapt_wait_hw.adapt_count_reg [1]), .O(\adapt_wait_hw.time_out_adapt_i_5_n_0 )); FDRE #( .INIT(1'b0)) \adapt_wait_hw.time_out_adapt_reg (.C(SYSCLK_IN), .CE(1'b1), .D(\adapt_wait_hw.time_out_adapt_i_1_n_0 ), .Q(\adapt_wait_hw.time_out_adapt_reg_n_0 ), .R(1'b0)); LUT5 #( .INIT(32'hFEFF0200)) check_tlock_max_i_1 (.I0(rx_state[2]), .I1(rx_state[3]), .I2(rx_state[1]), .I3(rx_state[0]), .I4(check_tlock_max_reg_n_0), .O(check_tlock_max_i_1_n_0)); FDRE #( .INIT(1'b0)) check_tlock_max_reg (.C(SYSCLK_IN), .CE(1'b1), .D(check_tlock_max_i_1_n_0), .Q(check_tlock_max_reg_n_0), .R(SOFT_RESET_RX_IN)); (* SOFT_HLUTNM = "soft_lutpair11" *) LUT4 #( .INIT(16'h00EA)) gt0_rx_cdrlocked_i_1 (.I0(\FSM_onehot_phalign_state_reg[0] ), .I1(gt0_rx_cdrlocked_reg_0), .I2(gt0_rx_cdrlocked_reg_1), .I3(SR), .O(gt0_rx_cdrlocked_reg)); LUT5 #( .INIT(32'hFFFD0100)) gtrxreset_i_i_1 (.I0(rx_state[2]), .I1(rx_state[3]), .I2(rx_state[1]), .I3(rx_state[0]), .I4(SR), .O(gtrxreset_i_i_1_n_0)); FDRE #( .INIT(1'b0)) gtrxreset_i_reg (.C(SYSCLK_IN), .CE(1'b1), .D(gtrxreset_i_i_1_n_0), .Q(SR), .R(SOFT_RESET_RX_IN)); LUT1 #( .INIT(2'h1)) \init_wait_count[0]_i_1__0 (.I0(init_wait_count_reg__0[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair14" *) LUT2 #( .INIT(4'h6)) \init_wait_count[1]_i_1__0 (.I0(init_wait_count_reg__0[1]), .I1(init_wait_count_reg__0[0]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair14" *) LUT3 #( .INIT(8'h78)) \init_wait_count[2]_i_1__0 (.I0(init_wait_count_reg__0[1]), .I1(init_wait_count_reg__0[0]), .I2(init_wait_count_reg__0[2]), .O(p_0_in[2])); (* SOFT_HLUTNM = "soft_lutpair8" *) LUT4 #( .INIT(16'h7F80)) \init_wait_count[3]_i_1__0 (.I0(init_wait_count_reg__0[2]), .I1(init_wait_count_reg__0[0]), .I2(init_wait_count_reg__0[1]), .I3(init_wait_count_reg__0[3]), .O(p_0_in[3])); LUT5 #( .INIT(32'hDFFFFFFF)) \init_wait_count[4]_i_1__0 (.I0(init_wait_count_reg__0[2]), .I1(init_wait_count_reg__0[0]), .I2(init_wait_count_reg__0[1]), .I3(init_wait_count_reg__0[4]), .I4(init_wait_count_reg__0[3]), .O(\init_wait_count[4]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair8" *) LUT5 #( .INIT(32'h7FFF8000)) \init_wait_count[4]_i_2__0 (.I0(init_wait_count_reg__0[3]), .I1(init_wait_count_reg__0[1]), .I2(init_wait_count_reg__0[0]), .I3(init_wait_count_reg__0[2]), .I4(init_wait_count_reg__0[4]), .O(p_0_in[4])); FDCE #( .INIT(1'b0)) \init_wait_count_reg[0] (.C(SYSCLK_IN), .CE(\init_wait_count[4]_i_1__0_n_0 ), .CLR(SOFT_RESET_RX_IN), .D(p_0_in[0]), .Q(init_wait_count_reg__0[0])); FDCE #( .INIT(1'b0)) \init_wait_count_reg[1] (.C(SYSCLK_IN), .CE(\init_wait_count[4]_i_1__0_n_0 ), .CLR(SOFT_RESET_RX_IN), .D(p_0_in[1]), .Q(init_wait_count_reg__0[1])); FDCE #( .INIT(1'b0)) \init_wait_count_reg[2] (.C(SYSCLK_IN), .CE(\init_wait_count[4]_i_1__0_n_0 ), .CLR(SOFT_RESET_RX_IN), .D(p_0_in[2]), .Q(init_wait_count_reg__0[2])); FDCE #( .INIT(1'b0)) \init_wait_count_reg[3] (.C(SYSCLK_IN), .CE(\init_wait_count[4]_i_1__0_n_0 ), .CLR(SOFT_RESET_RX_IN), .D(p_0_in[3]), .Q(init_wait_count_reg__0[3])); FDCE #( .INIT(1'b0)) \init_wait_count_reg[4] (.C(SYSCLK_IN), .CE(\init_wait_count[4]_i_1__0_n_0 ), .CLR(SOFT_RESET_RX_IN), .D(p_0_in[4]), .Q(init_wait_count_reg__0[4])); LUT6 #( .INIT(64'hFFFFFFFF40000000)) init_wait_done_i_1__0 (.I0(init_wait_count_reg__0[0]), .I1(init_wait_count_reg__0[1]), .I2(init_wait_count_reg__0[4]), .I3(init_wait_count_reg__0[3]), .I4(init_wait_count_reg__0[2]), .I5(init_wait_done), .O(init_wait_done_i_1__0_n_0)); FDCE #( .INIT(1'b0)) init_wait_done_reg (.C(SYSCLK_IN), .CE(1'b1), .CLR(SOFT_RESET_RX_IN), .D(init_wait_done_i_1__0_n_0), .Q(init_wait_done)); LUT1 #( .INIT(2'h1)) \mmcm_lock_count[0]_i_1__0 (.I0(mmcm_lock_count_reg__0[0]), .O(p_0_in__0[0])); (* SOFT_HLUTNM = "soft_lutpair13" *) LUT2 #( .INIT(4'h6)) \mmcm_lock_count[1]_i_1__0 (.I0(mmcm_lock_count_reg__0[0]), .I1(mmcm_lock_count_reg__0[1]), .O(p_0_in__0[1])); (* SOFT_HLUTNM = "soft_lutpair13" *) LUT3 #( .INIT(8'h78)) \mmcm_lock_count[2]_i_1__0 (.I0(mmcm_lock_count_reg__0[1]), .I1(mmcm_lock_count_reg__0[0]), .I2(mmcm_lock_count_reg__0[2]), .O(p_0_in__0[2])); (* SOFT_HLUTNM = "soft_lutpair7" *) LUT4 #( .INIT(16'h7F80)) \mmcm_lock_count[3]_i_1__0 (.I0(mmcm_lock_count_reg__0[2]), .I1(mmcm_lock_count_reg__0[0]), .I2(mmcm_lock_count_reg__0[1]), .I3(mmcm_lock_count_reg__0[3]), .O(p_0_in__0[3])); (* SOFT_HLUTNM = "soft_lutpair7" *) LUT5 #( .INIT(32'h7FFF8000)) \mmcm_lock_count[4]_i_1__0 (.I0(mmcm_lock_count_reg__0[3]), .I1(mmcm_lock_count_reg__0[1]), .I2(mmcm_lock_count_reg__0[0]), .I3(mmcm_lock_count_reg__0[2]), .I4(mmcm_lock_count_reg__0[4]), .O(p_0_in__0[4])); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \mmcm_lock_count[5]_i_1__0 (.I0(mmcm_lock_count_reg__0[4]), .I1(mmcm_lock_count_reg__0[2]), .I2(mmcm_lock_count_reg__0[0]), .I3(mmcm_lock_count_reg__0[1]), .I4(mmcm_lock_count_reg__0[3]), .I5(mmcm_lock_count_reg__0[5]), .O(p_0_in__0[5])); (* SOFT_HLUTNM = "soft_lutpair12" *) LUT2 #( .INIT(4'h9)) \mmcm_lock_count[6]_i_1__0 (.I0(\mmcm_lock_count[7]_i_4__0_n_0 ), .I1(mmcm_lock_count_reg__0[6]), .O(p_0_in__0[6])); LUT3 #( .INIT(8'hBF)) \mmcm_lock_count[7]_i_2__0 (.I0(\mmcm_lock_count[7]_i_4__0_n_0 ), .I1(mmcm_lock_count_reg__0[6]), .I2(mmcm_lock_count_reg__0[7]), .O(\mmcm_lock_count[7]_i_2__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair12" *) LUT3 #( .INIT(8'hD2)) \mmcm_lock_count[7]_i_3__0 (.I0(mmcm_lock_count_reg__0[6]), .I1(\mmcm_lock_count[7]_i_4__0_n_0 ), .I2(mmcm_lock_count_reg__0[7]), .O(p_0_in__0[7])); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) \mmcm_lock_count[7]_i_4__0 (.I0(mmcm_lock_count_reg__0[4]), .I1(mmcm_lock_count_reg__0[2]), .I2(mmcm_lock_count_reg__0[0]), .I3(mmcm_lock_count_reg__0[1]), .I4(mmcm_lock_count_reg__0[3]), .I5(mmcm_lock_count_reg__0[5]), .O(\mmcm_lock_count[7]_i_4__0_n_0 )); FDRE #( .INIT(1'b0)) \mmcm_lock_count_reg[0] (.C(SYSCLK_IN), .CE(\mmcm_lock_count[7]_i_2__0_n_0 ), .D(p_0_in__0[0]), .Q(mmcm_lock_count_reg__0[0]), .R(sync_mmcm_lock_reclocked_n_0)); FDRE #( .INIT(1'b0)) \mmcm_lock_count_reg[1] (.C(SYSCLK_IN), .CE(\mmcm_lock_count[7]_i_2__0_n_0 ), .D(p_0_in__0[1]), .Q(mmcm_lock_count_reg__0[1]), .R(sync_mmcm_lock_reclocked_n_0)); FDRE #( .INIT(1'b0)) \mmcm_lock_count_reg[2] (.C(SYSCLK_IN), .CE(\mmcm_lock_count[7]_i_2__0_n_0 ), .D(p_0_in__0[2]), .Q(mmcm_lock_count_reg__0[2]), .R(sync_mmcm_lock_reclocked_n_0)); FDRE #( .INIT(1'b0)) \mmcm_lock_count_reg[3] (.C(SYSCLK_IN), .CE(\mmcm_lock_count[7]_i_2__0_n_0 ), .D(p_0_in__0[3]), .Q(mmcm_lock_count_reg__0[3]), .R(sync_mmcm_lock_reclocked_n_0)); FDRE #( .INIT(1'b0)) \mmcm_lock_count_reg[4] (.C(SYSCLK_IN), .CE(\mmcm_lock_count[7]_i_2__0_n_0 ), .D(p_0_in__0[4]), .Q(mmcm_lock_count_reg__0[4]), .R(sync_mmcm_lock_reclocked_n_0)); FDRE #( .INIT(1'b0)) \mmcm_lock_count_reg[5] (.C(SYSCLK_IN), .CE(\mmcm_lock_count[7]_i_2__0_n_0 ), .D(p_0_in__0[5]), .Q(mmcm_lock_count_reg__0[5]), .R(sync_mmcm_lock_reclocked_n_0)); FDRE #( .INIT(1'b0)) \mmcm_lock_count_reg[6] (.C(SYSCLK_IN), .CE(\mmcm_lock_count[7]_i_2__0_n_0 ), .D(p_0_in__0[6]), .Q(mmcm_lock_count_reg__0[6]), .R(sync_mmcm_lock_reclocked_n_0)); FDRE #( .INIT(1'b0)) \mmcm_lock_count_reg[7] (.C(SYSCLK_IN), .CE(\mmcm_lock_count[7]_i_2__0_n_0 ), .D(p_0_in__0[7]), .Q(mmcm_lock_count_reg__0[7]), .R(sync_mmcm_lock_reclocked_n_0)); FDRE #( .INIT(1'b0)) mmcm_lock_reclocked_reg (.C(SYSCLK_IN), .CE(1'b1), .D(sync_mmcm_lock_reclocked_n_1), .Q(mmcm_lock_reclocked), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair5" *) LUT5 #( .INIT(32'h01010301)) reset_time_out_i_3 (.I0(rx_state[2]), .I1(rx_state[1]), .I2(rx_state[3]), .I3(\FSM_onehot_phalign_state_reg[0] ), .I4(rx_state[0]), .O(reset_time_out_i_3_n_0)); (* SOFT_HLUTNM = "soft_lutpair5" *) LUT5 #( .INIT(32'h11FF5520)) reset_time_out_i_4 (.I0(rx_state[2]), .I1(rx_state[1]), .I2(\FSM_onehot_phalign_state_reg[0] ), .I3(rx_state[3]), .I4(rx_state[0]), .O(reset_time_out_i_4_n_0)); FDSE #( .INIT(1'b0)) reset_time_out_reg (.C(SYSCLK_IN), .CE(1'b1), .D(sync_data_valid_n_5), .Q(reset_time_out_reg_n_0), .S(SOFT_RESET_RX_IN)); (* SOFT_HLUTNM = "soft_lutpair3" *) LUT5 #( .INIT(32'hFEFF0004)) run_phase_alignment_int_i_1__0 (.I0(rx_state[2]), .I1(rx_state[3]), .I2(rx_state[1]), .I3(rx_state[0]), .I4(gt0_run_rx_phalignment_i), .O(run_phase_alignment_int_i_1__0_n_0)); FDRE #( .INIT(1'b0)) run_phase_alignment_int_reg (.C(SYSCLK_IN), .CE(1'b1), .D(run_phase_alignment_int_i_1__0_n_0), .Q(gt0_run_rx_phalignment_i), .R(SOFT_RESET_RX_IN)); FDRE #( .INIT(1'b0)) run_phase_alignment_int_s3_reg (.C(gt0_rxusrclk_in), .CE(1'b1), .D(data_out), .Q(run_phase_alignment_int_s3_reg_n_0), .R(1'b0)); FDRE #( .INIT(1'b0)) rx_fsm_reset_done_int_s3_reg (.C(gt0_rxusrclk_in), .CE(1'b1), .D(rx_fsm_reset_done_int_s2), .Q(rx_fsm_reset_done_int_s3), .R(1'b0)); FDRE #( .INIT(1'b0)) rxresetdone_s3_reg (.C(SYSCLK_IN), .CE(1'b1), .D(rxresetdone_s2), .Q(rxresetdone_s3), .R(1'b0)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_sync_block_8 sync_CPLLLOCK (.\FSM_sequential_rx_state_reg[0] (\FSM_sequential_rx_state[2]_i_2_n_0 ), .\FSM_sequential_rx_state_reg[0]_0 (sync_data_valid_n_4), .\FSM_sequential_rx_state_reg[1] (sync_CPLLLOCK_n_0), .\FSM_sequential_rx_state_reg[1]_0 (sync_CPLLLOCK_n_1), .Q(rx_state), .SYSCLK_IN(SYSCLK_IN), .data_sync_reg6_0(sync_CPLLLOCK_n_2), .gt0_cplllock_out(gt0_cplllock_out), .recclk_mon_count_reset(recclk_mon_count_reset), .rxresetdone_s3(rxresetdone_s3)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_sync_block_9 sync_RXRESETDONE (.SYSCLK_IN(SYSCLK_IN), .data_out(rxresetdone_s2), .gt0_rxresetdone_out(gt0_rxresetdone_out)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_sync_block_10 sync_data_valid (.D({sync_data_valid_n_1,sync_data_valid_n_2,sync_data_valid_n_3}), .DONT_RESET_ON_DATA_ERROR_IN(DONT_RESET_ON_DATA_ERROR_IN), .DONT_RESET_ON_DATA_ERROR_IN_0(sync_data_valid_n_4), .E(sync_data_valid_n_0), .\FSM_sequential_rx_state_reg[0] (\FSM_sequential_rx_state[3]_i_3_n_0 ), .\FSM_sequential_rx_state_reg[0]_0 (\FSM_sequential_rx_state[3]_i_4_n_0 ), .\FSM_sequential_rx_state_reg[0]_1 (\FSM_sequential_rx_state[3]_i_5_n_0 ), .\FSM_sequential_rx_state_reg[0]_2 (sync_CPLLLOCK_n_0), .\FSM_sequential_rx_state_reg[0]_3 (\FSM_sequential_rx_state[0]_i_2_n_0 ), .\FSM_sequential_rx_state_reg[0]_4 (time_out_100us_reg_n_0), .\FSM_sequential_rx_state_reg[0]_5 (\FSM_sequential_rx_state[3]_i_12_n_0 ), .\FSM_sequential_rx_state_reg[1] (\FSM_sequential_rx_state[1]_i_2_n_0 ), .\FSM_sequential_rx_state_reg[3] (sync_data_valid_n_5), .\FSM_sequential_rx_state_reg[3]_0 (\FSM_sequential_rx_state[3]_i_9_n_0 ), .GT0_DATA_VALID_IN(GT0_DATA_VALID_IN), .GT0_RX_FSM_RESET_DONE_OUT(GT0_RX_FSM_RESET_DONE_OUT), .Q({rx_state[3],rx_state[1:0]}), .SYSCLK_IN(SYSCLK_IN), .mmcm_lock_reclocked(mmcm_lock_reclocked), .reset_time_out_reg(reset_time_out_reg_n_0), .reset_time_out_reg_0(sync_CPLLLOCK_n_1), .reset_time_out_reg_1(reset_time_out_i_3_n_0), .reset_time_out_reg_2(reset_time_out_i_4_n_0), .time_out_wait_bypass_s3(time_out_wait_bypass_s3)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_sync_block_11 sync_mmcm_lock_reclocked (.Q(mmcm_lock_count_reg__0[7:6]), .SR(sync_mmcm_lock_reclocked_n_0), .SYSCLK_IN(SYSCLK_IN), .mmcm_lock_reclocked(mmcm_lock_reclocked), .mmcm_lock_reclocked_reg(sync_mmcm_lock_reclocked_n_1), .mmcm_lock_reclocked_reg_0(\mmcm_lock_count[7]_i_4__0_n_0 )); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_sync_block_12 sync_run_phase_alignment_int (.data_in(gt0_run_rx_phalignment_i), .data_out(data_out), .gt0_rxusrclk_in(gt0_rxusrclk_in)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_sync_block_13 sync_rx_fsm_reset_done_int (.data_in(PHALIGNMENT_DONE_i), .data_out(rx_fsm_reset_done_int_s2), .gt0_rxusrclk_in(gt0_rxusrclk_in)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_sync_block_14 sync_time_out_wait_bypass (.SYSCLK_IN(SYSCLK_IN), .data_in(time_out_wait_bypass_reg_n_0), .data_out(time_out_wait_bypass_s2)); (* SOFT_HLUTNM = "soft_lutpair10" *) LUT4 #( .INIT(16'h00AE)) time_out_100us_i_1 (.I0(time_out_100us_reg_n_0), .I1(time_out_100us_i_2_n_0), .I2(\time_out_counter[0]_i_4_n_0 ), .I3(reset_time_out_reg_n_0), .O(time_out_100us_i_1_n_0)); LUT6 #( .INIT(64'h0400000000000000)) time_out_100us_i_2 (.I0(time_out_100us_i_3_n_0), .I1(time_out_counter_reg[10]), .I2(time_out_counter_reg[16]), .I3(time_out_counter_reg[5]), .I4(time_out_counter_reg[8]), .I5(time_out_counter_reg[9]), .O(time_out_100us_i_2_n_0)); LUT2 #( .INIT(4'hE)) time_out_100us_i_3 (.I0(time_out_counter_reg[12]), .I1(time_out_counter_reg[13]), .O(time_out_100us_i_3_n_0)); FDRE #( .INIT(1'b0)) time_out_100us_reg (.C(SYSCLK_IN), .CE(1'b1), .D(time_out_100us_i_1_n_0), .Q(time_out_100us_reg_n_0), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair4" *) LUT5 #( .INIT(32'h0000AABA)) time_out_2ms_i_1 (.I0(time_out_2ms_reg_n_0), .I1(time_out_counter_reg[5]), .I2(time_out_2ms_i_2__0_n_0), .I3(\time_out_counter[0]_i_4_n_0 ), .I4(reset_time_out_reg_n_0), .O(time_out_2ms_i_1_n_0)); LUT6 #( .INIT(64'h0002000000000000)) time_out_2ms_i_2__0 (.I0(time_out_counter_reg[12]), .I1(time_out_counter_reg[10]), .I2(time_out_counter_reg[8]), .I3(time_out_counter_reg[9]), .I4(time_out_counter_reg[16]), .I5(time_out_counter_reg[13]), .O(time_out_2ms_i_2__0_n_0)); FDRE #( .INIT(1'b0)) time_out_2ms_reg (.C(SYSCLK_IN), .CE(1'b1), .D(time_out_2ms_i_1_n_0), .Q(time_out_2ms_reg_n_0), .R(1'b0)); LUT3 #( .INIT(8'hFE)) \time_out_counter[0]_i_1 (.I0(time_out_counter_reg[5]), .I1(\time_out_counter[0]_i_3__0_n_0 ), .I2(\time_out_counter[0]_i_4_n_0 ), .O(time_out_counter)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFF7F)) \time_out_counter[0]_i_3__0 (.I0(time_out_counter_reg[13]), .I1(time_out_counter_reg[16]), .I2(time_out_counter_reg[12]), .I3(time_out_counter_reg[10]), .I4(time_out_counter_reg[9]), .I5(time_out_counter_reg[8]), .O(\time_out_counter[0]_i_3__0_n_0 )); LUT5 #( .INIT(32'hFFFEFFFF)) \time_out_counter[0]_i_4 (.I0(\time_out_counter[0]_i_6_n_0 ), .I1(time_out_counter_reg[0]), .I2(time_out_counter_reg[1]), .I3(time_out_counter_reg[6]), .I4(time_out_counter_reg[7]), .O(\time_out_counter[0]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \time_out_counter[0]_i_5__0 (.I0(time_out_counter_reg[0]), .O(\time_out_counter[0]_i_5__0_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFEFFFF)) \time_out_counter[0]_i_6 (.I0(time_out_counter_reg[14]), .I1(time_out_counter_reg[15]), .I2(time_out_counter_reg[2]), .I3(time_out_counter_reg[3]), .I4(time_out_counter_reg[11]), .I5(time_out_counter_reg[4]), .O(\time_out_counter[0]_i_6_n_0 )); FDRE #( .INIT(1'b0)) \time_out_counter_reg[0] (.C(SYSCLK_IN), .CE(time_out_counter), .D(\time_out_counter_reg[0]_i_2__0_n_7 ), .Q(time_out_counter_reg[0]), .R(reset_time_out_reg_n_0)); CARRY4 \time_out_counter_reg[0]_i_2__0 (.CI(1'b0), .CO({\time_out_counter_reg[0]_i_2__0_n_0 ,\time_out_counter_reg[0]_i_2__0_n_1 ,\time_out_counter_reg[0]_i_2__0_n_2 ,\time_out_counter_reg[0]_i_2__0_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b1}), .O({\time_out_counter_reg[0]_i_2__0_n_4 ,\time_out_counter_reg[0]_i_2__0_n_5 ,\time_out_counter_reg[0]_i_2__0_n_6 ,\time_out_counter_reg[0]_i_2__0_n_7 }), .S({time_out_counter_reg[3:1],\time_out_counter[0]_i_5__0_n_0 })); FDRE #( .INIT(1'b0)) \time_out_counter_reg[10] (.C(SYSCLK_IN), .CE(time_out_counter), .D(\time_out_counter_reg[8]_i_1__0_n_5 ), .Q(time_out_counter_reg[10]), .R(reset_time_out_reg_n_0)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[11] (.C(SYSCLK_IN), .CE(time_out_counter), .D(\time_out_counter_reg[8]_i_1__0_n_4 ), .Q(time_out_counter_reg[11]), .R(reset_time_out_reg_n_0)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[12] (.C(SYSCLK_IN), .CE(time_out_counter), .D(\time_out_counter_reg[12]_i_1__0_n_7 ), .Q(time_out_counter_reg[12]), .R(reset_time_out_reg_n_0)); CARRY4 \time_out_counter_reg[12]_i_1__0 (.CI(\time_out_counter_reg[8]_i_1__0_n_0 ), .CO({\time_out_counter_reg[12]_i_1__0_n_0 ,\time_out_counter_reg[12]_i_1__0_n_1 ,\time_out_counter_reg[12]_i_1__0_n_2 ,\time_out_counter_reg[12]_i_1__0_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\time_out_counter_reg[12]_i_1__0_n_4 ,\time_out_counter_reg[12]_i_1__0_n_5 ,\time_out_counter_reg[12]_i_1__0_n_6 ,\time_out_counter_reg[12]_i_1__0_n_7 }), .S(time_out_counter_reg[15:12])); FDRE #( .INIT(1'b0)) \time_out_counter_reg[13] (.C(SYSCLK_IN), .CE(time_out_counter), .D(\time_out_counter_reg[12]_i_1__0_n_6 ), .Q(time_out_counter_reg[13]), .R(reset_time_out_reg_n_0)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[14] (.C(SYSCLK_IN), .CE(time_out_counter), .D(\time_out_counter_reg[12]_i_1__0_n_5 ), .Q(time_out_counter_reg[14]), .R(reset_time_out_reg_n_0)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[15] (.C(SYSCLK_IN), .CE(time_out_counter), .D(\time_out_counter_reg[12]_i_1__0_n_4 ), .Q(time_out_counter_reg[15]), .R(reset_time_out_reg_n_0)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[16] (.C(SYSCLK_IN), .CE(time_out_counter), .D(\time_out_counter_reg[16]_i_1__0_n_7 ), .Q(time_out_counter_reg[16]), .R(reset_time_out_reg_n_0)); CARRY4 \time_out_counter_reg[16]_i_1__0 (.CI(\time_out_counter_reg[12]_i_1__0_n_0 ), .CO(\NLW_time_out_counter_reg[16]_i_1__0_CO_UNCONNECTED [3:0]), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\NLW_time_out_counter_reg[16]_i_1__0_O_UNCONNECTED [3:1],\time_out_counter_reg[16]_i_1__0_n_7 }), .S({1'b0,1'b0,1'b0,time_out_counter_reg[16]})); FDRE #( .INIT(1'b0)) \time_out_counter_reg[1] (.C(SYSCLK_IN), .CE(time_out_counter), .D(\time_out_counter_reg[0]_i_2__0_n_6 ), .Q(time_out_counter_reg[1]), .R(reset_time_out_reg_n_0)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[2] (.C(SYSCLK_IN), .CE(time_out_counter), .D(\time_out_counter_reg[0]_i_2__0_n_5 ), .Q(time_out_counter_reg[2]), .R(reset_time_out_reg_n_0)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[3] (.C(SYSCLK_IN), .CE(time_out_counter), .D(\time_out_counter_reg[0]_i_2__0_n_4 ), .Q(time_out_counter_reg[3]), .R(reset_time_out_reg_n_0)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[4] (.C(SYSCLK_IN), .CE(time_out_counter), .D(\time_out_counter_reg[4]_i_1__0_n_7 ), .Q(time_out_counter_reg[4]), .R(reset_time_out_reg_n_0)); CARRY4 \time_out_counter_reg[4]_i_1__0 (.CI(\time_out_counter_reg[0]_i_2__0_n_0 ), .CO({\time_out_counter_reg[4]_i_1__0_n_0 ,\time_out_counter_reg[4]_i_1__0_n_1 ,\time_out_counter_reg[4]_i_1__0_n_2 ,\time_out_counter_reg[4]_i_1__0_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\time_out_counter_reg[4]_i_1__0_n_4 ,\time_out_counter_reg[4]_i_1__0_n_5 ,\time_out_counter_reg[4]_i_1__0_n_6 ,\time_out_counter_reg[4]_i_1__0_n_7 }), .S(time_out_counter_reg[7:4])); FDRE #( .INIT(1'b0)) \time_out_counter_reg[5] (.C(SYSCLK_IN), .CE(time_out_counter), .D(\time_out_counter_reg[4]_i_1__0_n_6 ), .Q(time_out_counter_reg[5]), .R(reset_time_out_reg_n_0)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[6] (.C(SYSCLK_IN), .CE(time_out_counter), .D(\time_out_counter_reg[4]_i_1__0_n_5 ), .Q(time_out_counter_reg[6]), .R(reset_time_out_reg_n_0)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[7] (.C(SYSCLK_IN), .CE(time_out_counter), .D(\time_out_counter_reg[4]_i_1__0_n_4 ), .Q(time_out_counter_reg[7]), .R(reset_time_out_reg_n_0)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[8] (.C(SYSCLK_IN), .CE(time_out_counter), .D(\time_out_counter_reg[8]_i_1__0_n_7 ), .Q(time_out_counter_reg[8]), .R(reset_time_out_reg_n_0)); CARRY4 \time_out_counter_reg[8]_i_1__0 (.CI(\time_out_counter_reg[4]_i_1__0_n_0 ), .CO({\time_out_counter_reg[8]_i_1__0_n_0 ,\time_out_counter_reg[8]_i_1__0_n_1 ,\time_out_counter_reg[8]_i_1__0_n_2 ,\time_out_counter_reg[8]_i_1__0_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\time_out_counter_reg[8]_i_1__0_n_4 ,\time_out_counter_reg[8]_i_1__0_n_5 ,\time_out_counter_reg[8]_i_1__0_n_6 ,\time_out_counter_reg[8]_i_1__0_n_7 }), .S(time_out_counter_reg[11:8])); FDRE #( .INIT(1'b0)) \time_out_counter_reg[9] (.C(SYSCLK_IN), .CE(time_out_counter), .D(\time_out_counter_reg[8]_i_1__0_n_6 ), .Q(time_out_counter_reg[9]), .R(reset_time_out_reg_n_0)); LUT4 #( .INIT(16'hAB00)) time_out_wait_bypass_i_1__0 (.I0(time_out_wait_bypass_reg_n_0), .I1(rx_fsm_reset_done_int_s3), .I2(\wait_bypass_count[0]_i_4__0_n_0 ), .I3(run_phase_alignment_int_s3_reg_n_0), .O(time_out_wait_bypass_i_1__0_n_0)); FDRE #( .INIT(1'b0)) time_out_wait_bypass_reg (.C(gt0_rxusrclk_in), .CE(1'b1), .D(time_out_wait_bypass_i_1__0_n_0), .Q(time_out_wait_bypass_reg_n_0), .R(1'b0)); FDRE #( .INIT(1'b0)) time_out_wait_bypass_s3_reg (.C(SYSCLK_IN), .CE(1'b1), .D(time_out_wait_bypass_s2), .Q(time_out_wait_bypass_s3), .R(1'b0)); CARRY4 time_tlock_max1_carry (.CI(1'b0), .CO({time_tlock_max1_carry_n_0,time_tlock_max1_carry_n_1,time_tlock_max1_carry_n_2,time_tlock_max1_carry_n_3}), .CYINIT(1'b0), .DI({time_tlock_max1_carry_i_1_n_0,time_tlock_max1_carry_i_2_n_0,time_tlock_max1_carry_i_3_n_0,time_tlock_max1_carry_i_4_n_0}), .O(NLW_time_tlock_max1_carry_O_UNCONNECTED[3:0]), .S({time_tlock_max1_carry_i_5_n_0,time_tlock_max1_carry_i_6_n_0,time_tlock_max1_carry_i_7_n_0,time_tlock_max1_carry_i_8_n_0})); CARRY4 time_tlock_max1_carry__0 (.CI(time_tlock_max1_carry_n_0), .CO({time_tlock_max1_carry__0_n_0,time_tlock_max1_carry__0_n_1,time_tlock_max1_carry__0_n_2,time_tlock_max1_carry__0_n_3}), .CYINIT(1'b0), .DI({time_tlock_max1_carry__0_i_1_n_0,time_tlock_max1_carry__0_i_2_n_0,1'b0,1'b0}), .O(NLW_time_tlock_max1_carry__0_O_UNCONNECTED[3:0]), .S({time_tlock_max1_carry__0_i_3_n_0,time_tlock_max1_carry__0_i_4_n_0,time_tlock_max1_carry__0_i_5_n_0,time_tlock_max1_carry__0_i_6_n_0})); LUT2 #( .INIT(4'hE)) time_tlock_max1_carry__0_i_1 (.I0(time_out_counter_reg[14]), .I1(time_out_counter_reg[15]), .O(time_tlock_max1_carry__0_i_1_n_0)); LUT2 #( .INIT(4'hE)) time_tlock_max1_carry__0_i_2 (.I0(time_out_counter_reg[12]), .I1(time_out_counter_reg[13]), .O(time_tlock_max1_carry__0_i_2_n_0)); LUT2 #( .INIT(4'h1)) time_tlock_max1_carry__0_i_3 (.I0(time_out_counter_reg[15]), .I1(time_out_counter_reg[14]), .O(time_tlock_max1_carry__0_i_3_n_0)); LUT2 #( .INIT(4'h1)) time_tlock_max1_carry__0_i_4 (.I0(time_out_counter_reg[13]), .I1(time_out_counter_reg[12]), .O(time_tlock_max1_carry__0_i_4_n_0)); LUT2 #( .INIT(4'h8)) time_tlock_max1_carry__0_i_5 (.I0(time_out_counter_reg[10]), .I1(time_out_counter_reg[11]), .O(time_tlock_max1_carry__0_i_5_n_0)); LUT2 #( .INIT(4'h8)) time_tlock_max1_carry__0_i_6 (.I0(time_out_counter_reg[8]), .I1(time_out_counter_reg[9]), .O(time_tlock_max1_carry__0_i_6_n_0)); CARRY4 time_tlock_max1_carry__1 (.CI(time_tlock_max1_carry__0_n_0), .CO({NLW_time_tlock_max1_carry__1_CO_UNCONNECTED[3:1],time_tlock_max1}), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,time_out_counter_reg[16]}), .O(NLW_time_tlock_max1_carry__1_O_UNCONNECTED[3:0]), .S({1'b0,1'b0,1'b0,time_tlock_max1_carry__1_i_1_n_0})); LUT1 #( .INIT(2'h1)) time_tlock_max1_carry__1_i_1 (.I0(time_out_counter_reg[16]), .O(time_tlock_max1_carry__1_i_1_n_0)); LUT2 #( .INIT(4'h8)) time_tlock_max1_carry_i_1 (.I0(time_out_counter_reg[6]), .I1(time_out_counter_reg[7]), .O(time_tlock_max1_carry_i_1_n_0)); LUT2 #( .INIT(4'h8)) time_tlock_max1_carry_i_2 (.I0(time_out_counter_reg[4]), .I1(time_out_counter_reg[5]), .O(time_tlock_max1_carry_i_2_n_0)); LUT2 #( .INIT(4'hE)) time_tlock_max1_carry_i_3 (.I0(time_out_counter_reg[2]), .I1(time_out_counter_reg[3]), .O(time_tlock_max1_carry_i_3_n_0)); LUT2 #( .INIT(4'hE)) time_tlock_max1_carry_i_4 (.I0(time_out_counter_reg[0]), .I1(time_out_counter_reg[1]), .O(time_tlock_max1_carry_i_4_n_0)); LUT2 #( .INIT(4'h2)) time_tlock_max1_carry_i_5 (.I0(time_out_counter_reg[7]), .I1(time_out_counter_reg[6]), .O(time_tlock_max1_carry_i_5_n_0)); LUT2 #( .INIT(4'h2)) time_tlock_max1_carry_i_6 (.I0(time_out_counter_reg[5]), .I1(time_out_counter_reg[4]), .O(time_tlock_max1_carry_i_6_n_0)); LUT2 #( .INIT(4'h1)) time_tlock_max1_carry_i_7 (.I0(time_out_counter_reg[3]), .I1(time_out_counter_reg[2]), .O(time_tlock_max1_carry_i_7_n_0)); LUT2 #( .INIT(4'h1)) time_tlock_max1_carry_i_8 (.I0(time_out_counter_reg[1]), .I1(time_out_counter_reg[0]), .O(time_tlock_max1_carry_i_8_n_0)); LUT4 #( .INIT(16'h00EA)) time_tlock_max_i_1 (.I0(time_tlock_max), .I1(time_tlock_max1), .I2(check_tlock_max_reg_n_0), .I3(reset_time_out_reg_n_0), .O(time_tlock_max_i_1_n_0)); FDRE #( .INIT(1'b0)) time_tlock_max_reg (.C(SYSCLK_IN), .CE(1'b1), .D(time_tlock_max_i_1_n_0), .Q(time_tlock_max), .R(1'b0)); LUT1 #( .INIT(2'h1)) \wait_bypass_count[0]_i_1__0 (.I0(run_phase_alignment_int_s3_reg_n_0), .O(\wait_bypass_count[0]_i_1__0_n_0 )); LUT2 #( .INIT(4'h2)) \wait_bypass_count[0]_i_2__0 (.I0(\wait_bypass_count[0]_i_4__0_n_0 ), .I1(rx_fsm_reset_done_int_s3), .O(\wait_bypass_count[0]_i_2__0_n_0 )); LUT5 #( .INIT(32'hBFFFFFFF)) \wait_bypass_count[0]_i_4__0 (.I0(\wait_bypass_count[0]_i_6__0_n_0 ), .I1(wait_bypass_count_reg[1]), .I2(wait_bypass_count_reg[8]), .I3(wait_bypass_count_reg[0]), .I4(\wait_bypass_count[0]_i_7__0_n_0 ), .O(\wait_bypass_count[0]_i_4__0_n_0 )); LUT1 #( .INIT(2'h1)) \wait_bypass_count[0]_i_5__0 (.I0(wait_bypass_count_reg[0]), .O(\wait_bypass_count[0]_i_5__0_n_0 )); LUT4 #( .INIT(16'hEFFF)) \wait_bypass_count[0]_i_6__0 (.I0(wait_bypass_count_reg[3]), .I1(wait_bypass_count_reg[5]), .I2(wait_bypass_count_reg[9]), .I3(wait_bypass_count_reg[7]), .O(\wait_bypass_count[0]_i_6__0_n_0 )); LUT6 #( .INIT(64'h0000000000000008)) \wait_bypass_count[0]_i_7__0 (.I0(wait_bypass_count_reg[2]), .I1(wait_bypass_count_reg[12]), .I2(wait_bypass_count_reg[4]), .I3(wait_bypass_count_reg[10]), .I4(wait_bypass_count_reg[6]), .I5(wait_bypass_count_reg[11]), .O(\wait_bypass_count[0]_i_7__0_n_0 )); FDRE \wait_bypass_count_reg[0] (.C(gt0_rxusrclk_in), .CE(\wait_bypass_count[0]_i_2__0_n_0 ), .D(\wait_bypass_count_reg[0]_i_3__0_n_7 ), .Q(wait_bypass_count_reg[0]), .R(\wait_bypass_count[0]_i_1__0_n_0 )); CARRY4 \wait_bypass_count_reg[0]_i_3__0 (.CI(1'b0), .CO({\wait_bypass_count_reg[0]_i_3__0_n_0 ,\wait_bypass_count_reg[0]_i_3__0_n_1 ,\wait_bypass_count_reg[0]_i_3__0_n_2 ,\wait_bypass_count_reg[0]_i_3__0_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b1}), .O({\wait_bypass_count_reg[0]_i_3__0_n_4 ,\wait_bypass_count_reg[0]_i_3__0_n_5 ,\wait_bypass_count_reg[0]_i_3__0_n_6 ,\wait_bypass_count_reg[0]_i_3__0_n_7 }), .S({wait_bypass_count_reg[3:1],\wait_bypass_count[0]_i_5__0_n_0 })); FDRE \wait_bypass_count_reg[10] (.C(gt0_rxusrclk_in), .CE(\wait_bypass_count[0]_i_2__0_n_0 ), .D(\wait_bypass_count_reg[8]_i_1__0_n_5 ), .Q(wait_bypass_count_reg[10]), .R(\wait_bypass_count[0]_i_1__0_n_0 )); FDRE \wait_bypass_count_reg[11] (.C(gt0_rxusrclk_in), .CE(\wait_bypass_count[0]_i_2__0_n_0 ), .D(\wait_bypass_count_reg[8]_i_1__0_n_4 ), .Q(wait_bypass_count_reg[11]), .R(\wait_bypass_count[0]_i_1__0_n_0 )); FDRE \wait_bypass_count_reg[12] (.C(gt0_rxusrclk_in), .CE(\wait_bypass_count[0]_i_2__0_n_0 ), .D(\wait_bypass_count_reg[12]_i_1__0_n_7 ), .Q(wait_bypass_count_reg[12]), .R(\wait_bypass_count[0]_i_1__0_n_0 )); CARRY4 \wait_bypass_count_reg[12]_i_1__0 (.CI(\wait_bypass_count_reg[8]_i_1__0_n_0 ), .CO(\NLW_wait_bypass_count_reg[12]_i_1__0_CO_UNCONNECTED [3:0]), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\NLW_wait_bypass_count_reg[12]_i_1__0_O_UNCONNECTED [3:1],\wait_bypass_count_reg[12]_i_1__0_n_7 }), .S({1'b0,1'b0,1'b0,wait_bypass_count_reg[12]})); FDRE \wait_bypass_count_reg[1] (.C(gt0_rxusrclk_in), .CE(\wait_bypass_count[0]_i_2__0_n_0 ), .D(\wait_bypass_count_reg[0]_i_3__0_n_6 ), .Q(wait_bypass_count_reg[1]), .R(\wait_bypass_count[0]_i_1__0_n_0 )); FDRE \wait_bypass_count_reg[2] (.C(gt0_rxusrclk_in), .CE(\wait_bypass_count[0]_i_2__0_n_0 ), .D(\wait_bypass_count_reg[0]_i_3__0_n_5 ), .Q(wait_bypass_count_reg[2]), .R(\wait_bypass_count[0]_i_1__0_n_0 )); FDRE \wait_bypass_count_reg[3] (.C(gt0_rxusrclk_in), .CE(\wait_bypass_count[0]_i_2__0_n_0 ), .D(\wait_bypass_count_reg[0]_i_3__0_n_4 ), .Q(wait_bypass_count_reg[3]), .R(\wait_bypass_count[0]_i_1__0_n_0 )); FDRE \wait_bypass_count_reg[4] (.C(gt0_rxusrclk_in), .CE(\wait_bypass_count[0]_i_2__0_n_0 ), .D(\wait_bypass_count_reg[4]_i_1__0_n_7 ), .Q(wait_bypass_count_reg[4]), .R(\wait_bypass_count[0]_i_1__0_n_0 )); CARRY4 \wait_bypass_count_reg[4]_i_1__0 (.CI(\wait_bypass_count_reg[0]_i_3__0_n_0 ), .CO({\wait_bypass_count_reg[4]_i_1__0_n_0 ,\wait_bypass_count_reg[4]_i_1__0_n_1 ,\wait_bypass_count_reg[4]_i_1__0_n_2 ,\wait_bypass_count_reg[4]_i_1__0_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\wait_bypass_count_reg[4]_i_1__0_n_4 ,\wait_bypass_count_reg[4]_i_1__0_n_5 ,\wait_bypass_count_reg[4]_i_1__0_n_6 ,\wait_bypass_count_reg[4]_i_1__0_n_7 }), .S(wait_bypass_count_reg[7:4])); FDRE \wait_bypass_count_reg[5] (.C(gt0_rxusrclk_in), .CE(\wait_bypass_count[0]_i_2__0_n_0 ), .D(\wait_bypass_count_reg[4]_i_1__0_n_6 ), .Q(wait_bypass_count_reg[5]), .R(\wait_bypass_count[0]_i_1__0_n_0 )); FDRE \wait_bypass_count_reg[6] (.C(gt0_rxusrclk_in), .CE(\wait_bypass_count[0]_i_2__0_n_0 ), .D(\wait_bypass_count_reg[4]_i_1__0_n_5 ), .Q(wait_bypass_count_reg[6]), .R(\wait_bypass_count[0]_i_1__0_n_0 )); FDRE \wait_bypass_count_reg[7] (.C(gt0_rxusrclk_in), .CE(\wait_bypass_count[0]_i_2__0_n_0 ), .D(\wait_bypass_count_reg[4]_i_1__0_n_4 ), .Q(wait_bypass_count_reg[7]), .R(\wait_bypass_count[0]_i_1__0_n_0 )); FDRE \wait_bypass_count_reg[8] (.C(gt0_rxusrclk_in), .CE(\wait_bypass_count[0]_i_2__0_n_0 ), .D(\wait_bypass_count_reg[8]_i_1__0_n_7 ), .Q(wait_bypass_count_reg[8]), .R(\wait_bypass_count[0]_i_1__0_n_0 )); CARRY4 \wait_bypass_count_reg[8]_i_1__0 (.CI(\wait_bypass_count_reg[4]_i_1__0_n_0 ), .CO({\wait_bypass_count_reg[8]_i_1__0_n_0 ,\wait_bypass_count_reg[8]_i_1__0_n_1 ,\wait_bypass_count_reg[8]_i_1__0_n_2 ,\wait_bypass_count_reg[8]_i_1__0_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\wait_bypass_count_reg[8]_i_1__0_n_4 ,\wait_bypass_count_reg[8]_i_1__0_n_5 ,\wait_bypass_count_reg[8]_i_1__0_n_6 ,\wait_bypass_count_reg[8]_i_1__0_n_7 }), .S(wait_bypass_count_reg[11:8])); FDRE \wait_bypass_count_reg[9] (.C(gt0_rxusrclk_in), .CE(\wait_bypass_count[0]_i_2__0_n_0 ), .D(\wait_bypass_count_reg[8]_i_1__0_n_6 ), .Q(wait_bypass_count_reg[9]), .R(\wait_bypass_count[0]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair15" *) LUT1 #( .INIT(2'h1)) \wait_time_cnt[0]_i_1__0 (.I0(wait_time_cnt_reg__0[0]), .O(wait_time_cnt0[0])); (* SOFT_HLUTNM = "soft_lutpair15" *) LUT2 #( .INIT(4'h9)) \wait_time_cnt[1]_i_1__0 (.I0(wait_time_cnt_reg__0[1]), .I1(wait_time_cnt_reg__0[0]), .O(wait_time_cnt0[1])); LUT3 #( .INIT(8'hA9)) \wait_time_cnt[2]_i_1__0 (.I0(wait_time_cnt_reg__0[2]), .I1(wait_time_cnt_reg__0[0]), .I2(wait_time_cnt_reg__0[1]), .O(wait_time_cnt0[2])); (* SOFT_HLUTNM = "soft_lutpair9" *) LUT4 #( .INIT(16'hAAA9)) \wait_time_cnt[3]_i_1__0 (.I0(wait_time_cnt_reg__0[3]), .I1(wait_time_cnt_reg__0[1]), .I2(wait_time_cnt_reg__0[0]), .I3(wait_time_cnt_reg__0[2]), .O(wait_time_cnt0[3])); (* SOFT_HLUTNM = "soft_lutpair9" *) LUT5 #( .INIT(32'hAAAAAAA9)) \wait_time_cnt[4]_i_1__0 (.I0(wait_time_cnt_reg__0[4]), .I1(wait_time_cnt_reg__0[2]), .I2(wait_time_cnt_reg__0[0]), .I3(wait_time_cnt_reg__0[1]), .I4(wait_time_cnt_reg__0[3]), .O(wait_time_cnt0[4])); LUT6 #( .INIT(64'hAAAAAAAAAAAAAAA9)) \wait_time_cnt[5]_i_1__0 (.I0(wait_time_cnt_reg__0[5]), .I1(wait_time_cnt_reg__0[3]), .I2(wait_time_cnt_reg__0[1]), .I3(wait_time_cnt_reg__0[0]), .I4(wait_time_cnt_reg__0[2]), .I5(wait_time_cnt_reg__0[4]), .O(wait_time_cnt0[5])); LUT3 #( .INIT(8'h10)) \wait_time_cnt[6]_i_1 (.I0(rx_state[3]), .I1(rx_state[1]), .I2(rx_state[0]), .O(\wait_time_cnt[6]_i_1_n_0 )); LUT2 #( .INIT(4'hE)) \wait_time_cnt[6]_i_2__0 (.I0(\wait_time_cnt[6]_i_4__0_n_0 ), .I1(wait_time_cnt_reg__0[6]), .O(\wait_time_cnt[6]_i_2__0_n_0 )); LUT2 #( .INIT(4'h9)) \wait_time_cnt[6]_i_3__0 (.I0(wait_time_cnt_reg__0[6]), .I1(\wait_time_cnt[6]_i_4__0_n_0 ), .O(wait_time_cnt0[6])); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \wait_time_cnt[6]_i_4__0 (.I0(wait_time_cnt_reg__0[4]), .I1(wait_time_cnt_reg__0[2]), .I2(wait_time_cnt_reg__0[0]), .I3(wait_time_cnt_reg__0[1]), .I4(wait_time_cnt_reg__0[3]), .I5(wait_time_cnt_reg__0[5]), .O(\wait_time_cnt[6]_i_4__0_n_0 )); FDRE \wait_time_cnt_reg[0] (.C(SYSCLK_IN), .CE(\wait_time_cnt[6]_i_2__0_n_0 ), .D(wait_time_cnt0[0]), .Q(wait_time_cnt_reg__0[0]), .R(\wait_time_cnt[6]_i_1_n_0 )); FDRE \wait_time_cnt_reg[1] (.C(SYSCLK_IN), .CE(\wait_time_cnt[6]_i_2__0_n_0 ), .D(wait_time_cnt0[1]), .Q(wait_time_cnt_reg__0[1]), .R(\wait_time_cnt[6]_i_1_n_0 )); FDSE \wait_time_cnt_reg[2] (.C(SYSCLK_IN), .CE(\wait_time_cnt[6]_i_2__0_n_0 ), .D(wait_time_cnt0[2]), .Q(wait_time_cnt_reg__0[2]), .S(\wait_time_cnt[6]_i_1_n_0 )); FDRE \wait_time_cnt_reg[3] (.C(SYSCLK_IN), .CE(\wait_time_cnt[6]_i_2__0_n_0 ), .D(wait_time_cnt0[3]), .Q(wait_time_cnt_reg__0[3]), .R(\wait_time_cnt[6]_i_1_n_0 )); FDRE \wait_time_cnt_reg[4] (.C(SYSCLK_IN), .CE(\wait_time_cnt[6]_i_2__0_n_0 ), .D(wait_time_cnt0[4]), .Q(wait_time_cnt_reg__0[4]), .R(\wait_time_cnt[6]_i_1_n_0 )); FDSE \wait_time_cnt_reg[5] (.C(SYSCLK_IN), .CE(\wait_time_cnt[6]_i_2__0_n_0 ), .D(wait_time_cnt0[5]), .Q(wait_time_cnt_reg__0[5]), .S(\wait_time_cnt[6]_i_1_n_0 )); FDSE \wait_time_cnt_reg[6] (.C(SYSCLK_IN), .CE(\wait_time_cnt[6]_i_2__0_n_0 ), .D(wait_time_cnt0[6]), .Q(wait_time_cnt_reg__0[6]), .S(\wait_time_cnt[6]_i_1_n_0 )); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_TX_STARTUP_FSM (gt0_gttxreset_t, gt0_cpllreset_t, GT0_TX_FSM_RESET_DONE_OUT, gt0_txuserrdy_t, run_phase_alignment_int_reg_0, SYSCLK_IN, gt0_txusrclk_in, SOFT_RESET_TX_IN, gt0_tx_phalignment_done_i, gt0_cpllrefclklost_i, gt0_txresetdone_out, gt0_cplllock_out); output gt0_gttxreset_t; output gt0_cpllreset_t; output GT0_TX_FSM_RESET_DONE_OUT; output gt0_txuserrdy_t; output run_phase_alignment_int_reg_0; input SYSCLK_IN; input gt0_txusrclk_in; input SOFT_RESET_TX_IN; input gt0_tx_phalignment_done_i; input gt0_cpllrefclklost_i; input gt0_txresetdone_out; input gt0_cplllock_out; wire CPLL_RESET_i_1_n_0; wire CPLL_RESET_i_2_n_0; wire \FSM_sequential_tx_state[0]_i_1_n_0 ; wire \FSM_sequential_tx_state[0]_i_2_n_0 ; wire \FSM_sequential_tx_state[1]_i_1_n_0 ; wire \FSM_sequential_tx_state[2]_i_1_n_0 ; wire \FSM_sequential_tx_state[2]_i_2_n_0 ; wire \FSM_sequential_tx_state[3]_i_10_n_0 ; wire \FSM_sequential_tx_state[3]_i_2_n_0 ; wire \FSM_sequential_tx_state[3]_i_3_n_0 ; wire \FSM_sequential_tx_state[3]_i_5_n_0 ; wire \FSM_sequential_tx_state[3]_i_6_n_0 ; wire \FSM_sequential_tx_state[3]_i_7_n_0 ; wire \FSM_sequential_tx_state[3]_i_8_n_0 ; wire \FSM_sequential_tx_state[3]_i_9_n_0 ; wire GT0_TX_FSM_RESET_DONE_OUT; wire SOFT_RESET_TX_IN; wire SYSCLK_IN; wire TXUSERRDY_i_1_n_0; wire clear; wire data_out; wire gt0_cplllock_out; wire gt0_cpllrefclklost_i; wire gt0_cpllreset_t; wire gt0_gttxreset_t; wire gt0_run_tx_phalignment_i; wire gt0_tx_phalignment_done_i; wire gt0_txresetdone_out; wire gt0_txuserrdy_t; wire gt0_txusrclk_in; wire gttxreset_i_i_1_n_0; wire \init_wait_count[4]_i_1_n_0 ; wire [4:0]init_wait_count_reg__0; wire init_wait_done; wire init_wait_done_i_1_n_0; wire \mmcm_lock_count[7]_i_2_n_0 ; wire \mmcm_lock_count[7]_i_4_n_0 ; wire [7:0]mmcm_lock_count_reg__0; wire mmcm_lock_reclocked; wire [4:0]p_0_in; wire [7:0]p_0_in__0; wire pll_reset_asserted_i_1_n_0; wire pll_reset_asserted_reg_n_0; wire reset_time_out; wire reset_time_out_i_2_n_0; wire run_phase_alignment_int_i_1_n_0; wire run_phase_alignment_int_reg_0; wire run_phase_alignment_int_s3; wire sel; wire sync_CPLLLOCK_n_0; wire sync_CPLLLOCK_n_1; wire sync_mmcm_lock_reclocked_n_0; wire sync_mmcm_lock_reclocked_n_1; wire time_out_2ms_i_1__0_n_0; wire time_out_2ms_i_2_n_0; wire time_out_2ms_reg_n_0; wire time_out_500us_i_1_n_0; wire time_out_500us_i_2_n_0; wire time_out_500us_reg_n_0; wire time_out_counter; wire \time_out_counter[0]_i_3_n_0 ; wire \time_out_counter[0]_i_4__0_n_0 ; wire \time_out_counter[0]_i_5_n_0 ; wire \time_out_counter[0]_i_6__0_n_0 ; wire [16:0]time_out_counter_reg; wire \time_out_counter_reg[0]_i_2_n_0 ; wire \time_out_counter_reg[0]_i_2_n_1 ; wire \time_out_counter_reg[0]_i_2_n_2 ; wire \time_out_counter_reg[0]_i_2_n_3 ; wire \time_out_counter_reg[0]_i_2_n_4 ; wire \time_out_counter_reg[0]_i_2_n_5 ; wire \time_out_counter_reg[0]_i_2_n_6 ; wire \time_out_counter_reg[0]_i_2_n_7 ; wire \time_out_counter_reg[12]_i_1_n_0 ; wire \time_out_counter_reg[12]_i_1_n_1 ; wire \time_out_counter_reg[12]_i_1_n_2 ; wire \time_out_counter_reg[12]_i_1_n_3 ; wire \time_out_counter_reg[12]_i_1_n_4 ; wire \time_out_counter_reg[12]_i_1_n_5 ; wire \time_out_counter_reg[12]_i_1_n_6 ; wire \time_out_counter_reg[12]_i_1_n_7 ; wire \time_out_counter_reg[16]_i_1_n_7 ; wire \time_out_counter_reg[4]_i_1_n_0 ; wire \time_out_counter_reg[4]_i_1_n_1 ; wire \time_out_counter_reg[4]_i_1_n_2 ; wire \time_out_counter_reg[4]_i_1_n_3 ; wire \time_out_counter_reg[4]_i_1_n_4 ; wire \time_out_counter_reg[4]_i_1_n_5 ; wire \time_out_counter_reg[4]_i_1_n_6 ; wire \time_out_counter_reg[4]_i_1_n_7 ; wire \time_out_counter_reg[8]_i_1_n_0 ; wire \time_out_counter_reg[8]_i_1_n_1 ; wire \time_out_counter_reg[8]_i_1_n_2 ; wire \time_out_counter_reg[8]_i_1_n_3 ; wire \time_out_counter_reg[8]_i_1_n_4 ; wire \time_out_counter_reg[8]_i_1_n_5 ; wire \time_out_counter_reg[8]_i_1_n_6 ; wire \time_out_counter_reg[8]_i_1_n_7 ; wire time_out_wait_bypass_i_1_n_0; wire time_out_wait_bypass_reg_n_0; wire time_out_wait_bypass_s2; wire time_out_wait_bypass_s3; wire time_tlock_max_i_1__0_n_0; wire time_tlock_max_i_2_n_0; wire time_tlock_max_i_3_n_0; wire time_tlock_max_i_4_n_0; wire time_tlock_max_reg_n_0; wire tx_fsm_reset_done_int_i_1_n_0; wire tx_fsm_reset_done_int_s2; wire tx_fsm_reset_done_int_s3; wire [3:0]tx_state; wire txresetdone_s2; wire txresetdone_s3; wire \wait_bypass_count[0]_i_2_n_0 ; wire \wait_bypass_count[0]_i_4_n_0 ; wire \wait_bypass_count[0]_i_5_n_0 ; wire \wait_bypass_count[0]_i_6_n_0 ; wire \wait_bypass_count[0]_i_7_n_0 ; wire \wait_bypass_count[0]_i_8_n_0 ; wire \wait_bypass_count[0]_i_9_n_0 ; wire [15:0]wait_bypass_count_reg; wire \wait_bypass_count_reg[0]_i_3_n_0 ; wire \wait_bypass_count_reg[0]_i_3_n_1 ; wire \wait_bypass_count_reg[0]_i_3_n_2 ; wire \wait_bypass_count_reg[0]_i_3_n_3 ; wire \wait_bypass_count_reg[0]_i_3_n_4 ; wire \wait_bypass_count_reg[0]_i_3_n_5 ; wire \wait_bypass_count_reg[0]_i_3_n_6 ; wire \wait_bypass_count_reg[0]_i_3_n_7 ; wire \wait_bypass_count_reg[12]_i_1_n_1 ; wire \wait_bypass_count_reg[12]_i_1_n_2 ; wire \wait_bypass_count_reg[12]_i_1_n_3 ; wire \wait_bypass_count_reg[12]_i_1_n_4 ; wire \wait_bypass_count_reg[12]_i_1_n_5 ; wire \wait_bypass_count_reg[12]_i_1_n_6 ; wire \wait_bypass_count_reg[12]_i_1_n_7 ; wire \wait_bypass_count_reg[4]_i_1_n_0 ; wire \wait_bypass_count_reg[4]_i_1_n_1 ; wire \wait_bypass_count_reg[4]_i_1_n_2 ; wire \wait_bypass_count_reg[4]_i_1_n_3 ; wire \wait_bypass_count_reg[4]_i_1_n_4 ; wire \wait_bypass_count_reg[4]_i_1_n_5 ; wire \wait_bypass_count_reg[4]_i_1_n_6 ; wire \wait_bypass_count_reg[4]_i_1_n_7 ; wire \wait_bypass_count_reg[8]_i_1_n_0 ; wire \wait_bypass_count_reg[8]_i_1_n_1 ; wire \wait_bypass_count_reg[8]_i_1_n_2 ; wire \wait_bypass_count_reg[8]_i_1_n_3 ; wire \wait_bypass_count_reg[8]_i_1_n_4 ; wire \wait_bypass_count_reg[8]_i_1_n_5 ; wire \wait_bypass_count_reg[8]_i_1_n_6 ; wire \wait_bypass_count_reg[8]_i_1_n_7 ; wire [6:0]wait_time_cnt0; wire \wait_time_cnt[6]_i_1__0_n_0 ; wire \wait_time_cnt[6]_i_4_n_0 ; wire [6:0]wait_time_cnt_reg__0; wire [3:0]\NLW_time_out_counter_reg[16]_i_1_CO_UNCONNECTED ; wire [3:1]\NLW_time_out_counter_reg[16]_i_1_O_UNCONNECTED ; wire [3:3]\NLW_wait_bypass_count_reg[12]_i_1_CO_UNCONNECTED ; LUT6 #( .INIT(64'hFFFFFFF100000001)) CPLL_RESET_i_1 (.I0(gt0_cpllrefclklost_i), .I1(pll_reset_asserted_reg_n_0), .I2(tx_state[2]), .I3(tx_state[1]), .I4(CPLL_RESET_i_2_n_0), .I5(gt0_cpllreset_t), .O(CPLL_RESET_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair22" *) LUT2 #( .INIT(4'hB)) CPLL_RESET_i_2 (.I0(tx_state[3]), .I1(tx_state[0]), .O(CPLL_RESET_i_2_n_0)); FDRE #( .INIT(1'b0)) CPLL_RESET_reg (.C(SYSCLK_IN), .CE(1'b1), .D(CPLL_RESET_i_1_n_0), .Q(gt0_cpllreset_t), .R(SOFT_RESET_TX_IN)); (* SOFT_HLUTNM = "soft_lutpair25" *) LUT1 #( .INIT(2'h1)) \FSM_onehot_phalign_state[3]_i_1__0 (.I0(gt0_run_tx_phalignment_i), .O(run_phase_alignment_int_reg_0)); LUT6 #( .INIT(64'hFFFFBBFBBBBBBBFB)) \FSM_sequential_tx_state[0]_i_1 (.I0(tx_state[3]), .I1(tx_state[0]), .I2(tx_state[2]), .I3(\FSM_sequential_tx_state[2]_i_2_n_0 ), .I4(tx_state[1]), .I5(\FSM_sequential_tx_state[0]_i_2_n_0 ), .O(\FSM_sequential_tx_state[0]_i_1_n_0 )); LUT4 #( .INIT(16'h2F20)) \FSM_sequential_tx_state[0]_i_2 (.I0(time_out_500us_reg_n_0), .I1(reset_time_out), .I2(tx_state[2]), .I3(time_out_2ms_reg_n_0), .O(\FSM_sequential_tx_state[0]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair19" *) LUT5 #( .INIT(32'h000F00D0)) \FSM_sequential_tx_state[1]_i_1 (.I0(tx_state[2]), .I1(\FSM_sequential_tx_state[2]_i_2_n_0 ), .I2(tx_state[0]), .I3(tx_state[3]), .I4(tx_state[1]), .O(\FSM_sequential_tx_state[1]_i_1_n_0 )); LUT6 #( .INIT(64'h010C0C0C010C000C)) \FSM_sequential_tx_state[2]_i_1 (.I0(time_out_2ms_reg_n_0), .I1(tx_state[2]), .I2(tx_state[3]), .I3(tx_state[0]), .I4(tx_state[1]), .I5(\FSM_sequential_tx_state[2]_i_2_n_0 ), .O(\FSM_sequential_tx_state[2]_i_1_n_0 )); LUT3 #( .INIT(8'hFD)) \FSM_sequential_tx_state[2]_i_2 (.I0(time_tlock_max_reg_n_0), .I1(reset_time_out), .I2(mmcm_lock_reclocked), .O(\FSM_sequential_tx_state[2]_i_2_n_0 )); LUT6 #( .INIT(64'h0000005400000000)) \FSM_sequential_tx_state[3]_i_10 (.I0(tx_state[0]), .I1(time_out_wait_bypass_s3), .I2(gt0_tx_phalignment_done_i), .I3(tx_state[1]), .I4(tx_state[2]), .I5(tx_state[3]), .O(\FSM_sequential_tx_state[3]_i_10_n_0 )); LUT6 #( .INIT(64'hFF5D0C0C0C0C0C0C)) \FSM_sequential_tx_state[3]_i_2 (.I0(time_out_500us_reg_n_0), .I1(tx_state[3]), .I2(time_out_wait_bypass_s3), .I3(reset_time_out), .I4(\FSM_sequential_tx_state[3]_i_8_n_0 ), .I5(tx_state[2]), .O(\FSM_sequential_tx_state[3]_i_2_n_0 )); LUT6 #( .INIT(64'hEEEEEEEEEEEEEFEE)) \FSM_sequential_tx_state[3]_i_3 (.I0(\FSM_sequential_tx_state[3]_i_9_n_0 ), .I1(\FSM_sequential_tx_state[3]_i_10_n_0 ), .I2(\FSM_sequential_tx_state[3]_i_5_n_0 ), .I3(\FSM_sequential_tx_state[3]_i_6_n_0 ), .I4(wait_time_cnt_reg__0[6]), .I5(\wait_time_cnt[6]_i_4_n_0 ), .O(\FSM_sequential_tx_state[3]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair23" *) LUT2 #( .INIT(4'hE)) \FSM_sequential_tx_state[3]_i_5 (.I0(tx_state[0]), .I1(tx_state[3]), .O(\FSM_sequential_tx_state[3]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair20" *) LUT2 #( .INIT(4'hE)) \FSM_sequential_tx_state[3]_i_6 (.I0(tx_state[1]), .I1(tx_state[2]), .O(\FSM_sequential_tx_state[3]_i_6_n_0 )); LUT6 #( .INIT(64'h0404040400040000)) \FSM_sequential_tx_state[3]_i_7 (.I0(CPLL_RESET_i_2_n_0), .I1(tx_state[2]), .I2(tx_state[1]), .I3(reset_time_out), .I4(time_tlock_max_reg_n_0), .I5(mmcm_lock_reclocked), .O(\FSM_sequential_tx_state[3]_i_7_n_0 )); (* SOFT_HLUTNM = "soft_lutpair19" *) LUT3 #( .INIT(8'h08)) \FSM_sequential_tx_state[3]_i_8 (.I0(tx_state[1]), .I1(tx_state[0]), .I2(tx_state[3]), .O(\FSM_sequential_tx_state[3]_i_8_n_0 )); (* SOFT_HLUTNM = "soft_lutpair20" *) LUT5 #( .INIT(32'h00800000)) \FSM_sequential_tx_state[3]_i_9 (.I0(tx_state[2]), .I1(tx_state[1]), .I2(tx_state[0]), .I3(tx_state[3]), .I4(txresetdone_s3), .O(\FSM_sequential_tx_state[3]_i_9_n_0 )); (* FSM_ENCODED_STATES = "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *) FDRE #( .INIT(1'b0)) \FSM_sequential_tx_state_reg[0] (.C(SYSCLK_IN), .CE(sync_CPLLLOCK_n_0), .D(\FSM_sequential_tx_state[0]_i_1_n_0 ), .Q(tx_state[0]), .R(SOFT_RESET_TX_IN)); (* FSM_ENCODED_STATES = "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *) FDRE #( .INIT(1'b0)) \FSM_sequential_tx_state_reg[1] (.C(SYSCLK_IN), .CE(sync_CPLLLOCK_n_0), .D(\FSM_sequential_tx_state[1]_i_1_n_0 ), .Q(tx_state[1]), .R(SOFT_RESET_TX_IN)); (* FSM_ENCODED_STATES = "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *) FDRE #( .INIT(1'b0)) \FSM_sequential_tx_state_reg[2] (.C(SYSCLK_IN), .CE(sync_CPLLLOCK_n_0), .D(\FSM_sequential_tx_state[2]_i_1_n_0 ), .Q(tx_state[2]), .R(SOFT_RESET_TX_IN)); (* FSM_ENCODED_STATES = "wait_for_txoutclk:0100,release_pll_reset:0011,wait_for_pll_lock:0010,assert_all_resets:0001,init:0000,wait_reset_done:0111,reset_fsm_done:1001,wait_for_txusrclk:0110,do_phase_alignment:1000,release_mmcm_reset:0101" *) FDRE #( .INIT(1'b0)) \FSM_sequential_tx_state_reg[3] (.C(SYSCLK_IN), .CE(sync_CPLLLOCK_n_0), .D(\FSM_sequential_tx_state[3]_i_2_n_0 ), .Q(tx_state[3]), .R(SOFT_RESET_TX_IN)); (* SOFT_HLUTNM = "soft_lutpair23" *) LUT5 #( .INIT(32'hFFFB4000)) TXUSERRDY_i_1 (.I0(tx_state[3]), .I1(tx_state[0]), .I2(tx_state[1]), .I3(tx_state[2]), .I4(gt0_txuserrdy_t), .O(TXUSERRDY_i_1_n_0)); FDRE #( .INIT(1'b0)) TXUSERRDY_reg (.C(SYSCLK_IN), .CE(1'b1), .D(TXUSERRDY_i_1_n_0), .Q(gt0_txuserrdy_t), .R(SOFT_RESET_TX_IN)); (* SOFT_HLUTNM = "soft_lutpair22" *) LUT5 #( .INIT(32'hFEFF0004)) gttxreset_i_i_1 (.I0(tx_state[3]), .I1(tx_state[0]), .I2(tx_state[1]), .I3(tx_state[2]), .I4(gt0_gttxreset_t), .O(gttxreset_i_i_1_n_0)); FDRE #( .INIT(1'b0)) gttxreset_i_reg (.C(SYSCLK_IN), .CE(1'b1), .D(gttxreset_i_i_1_n_0), .Q(gt0_gttxreset_t), .R(SOFT_RESET_TX_IN)); LUT1 #( .INIT(2'h1)) \init_wait_count[0]_i_1 (.I0(init_wait_count_reg__0[0]), .O(p_0_in[0])); (* SOFT_HLUTNM = "soft_lutpair28" *) LUT2 #( .INIT(4'h6)) \init_wait_count[1]_i_1 (.I0(init_wait_count_reg__0[1]), .I1(init_wait_count_reg__0[0]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair28" *) LUT3 #( .INIT(8'h78)) \init_wait_count[2]_i_1 (.I0(init_wait_count_reg__0[1]), .I1(init_wait_count_reg__0[0]), .I2(init_wait_count_reg__0[2]), .O(p_0_in[2])); (* SOFT_HLUTNM = "soft_lutpair24" *) LUT4 #( .INIT(16'h7F80)) \init_wait_count[3]_i_1 (.I0(init_wait_count_reg__0[2]), .I1(init_wait_count_reg__0[0]), .I2(init_wait_count_reg__0[1]), .I3(init_wait_count_reg__0[3]), .O(p_0_in[3])); LUT5 #( .INIT(32'hDFFFFFFF)) \init_wait_count[4]_i_1 (.I0(init_wait_count_reg__0[2]), .I1(init_wait_count_reg__0[0]), .I2(init_wait_count_reg__0[1]), .I3(init_wait_count_reg__0[4]), .I4(init_wait_count_reg__0[3]), .O(\init_wait_count[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair24" *) LUT5 #( .INIT(32'h7FFF8000)) \init_wait_count[4]_i_2 (.I0(init_wait_count_reg__0[3]), .I1(init_wait_count_reg__0[1]), .I2(init_wait_count_reg__0[0]), .I3(init_wait_count_reg__0[2]), .I4(init_wait_count_reg__0[4]), .O(p_0_in[4])); FDCE #( .INIT(1'b0)) \init_wait_count_reg[0] (.C(SYSCLK_IN), .CE(\init_wait_count[4]_i_1_n_0 ), .CLR(SOFT_RESET_TX_IN), .D(p_0_in[0]), .Q(init_wait_count_reg__0[0])); FDCE #( .INIT(1'b0)) \init_wait_count_reg[1] (.C(SYSCLK_IN), .CE(\init_wait_count[4]_i_1_n_0 ), .CLR(SOFT_RESET_TX_IN), .D(p_0_in[1]), .Q(init_wait_count_reg__0[1])); FDCE #( .INIT(1'b0)) \init_wait_count_reg[2] (.C(SYSCLK_IN), .CE(\init_wait_count[4]_i_1_n_0 ), .CLR(SOFT_RESET_TX_IN), .D(p_0_in[2]), .Q(init_wait_count_reg__0[2])); FDCE #( .INIT(1'b0)) \init_wait_count_reg[3] (.C(SYSCLK_IN), .CE(\init_wait_count[4]_i_1_n_0 ), .CLR(SOFT_RESET_TX_IN), .D(p_0_in[3]), .Q(init_wait_count_reg__0[3])); FDCE #( .INIT(1'b0)) \init_wait_count_reg[4] (.C(SYSCLK_IN), .CE(\init_wait_count[4]_i_1_n_0 ), .CLR(SOFT_RESET_TX_IN), .D(p_0_in[4]), .Q(init_wait_count_reg__0[4])); LUT6 #( .INIT(64'hFFFFFFFF40000000)) init_wait_done_i_1 (.I0(init_wait_count_reg__0[0]), .I1(init_wait_count_reg__0[1]), .I2(init_wait_count_reg__0[4]), .I3(init_wait_count_reg__0[3]), .I4(init_wait_count_reg__0[2]), .I5(init_wait_done), .O(init_wait_done_i_1_n_0)); FDCE #( .INIT(1'b0)) init_wait_done_reg (.C(SYSCLK_IN), .CE(1'b1), .CLR(SOFT_RESET_TX_IN), .D(init_wait_done_i_1_n_0), .Q(init_wait_done)); LUT1 #( .INIT(2'h1)) \mmcm_lock_count[0]_i_1 (.I0(mmcm_lock_count_reg__0[0]), .O(p_0_in__0[0])); (* SOFT_HLUTNM = "soft_lutpair26" *) LUT2 #( .INIT(4'h6)) \mmcm_lock_count[1]_i_1 (.I0(mmcm_lock_count_reg__0[0]), .I1(mmcm_lock_count_reg__0[1]), .O(p_0_in__0[1])); (* SOFT_HLUTNM = "soft_lutpair26" *) LUT3 #( .INIT(8'h78)) \mmcm_lock_count[2]_i_1 (.I0(mmcm_lock_count_reg__0[1]), .I1(mmcm_lock_count_reg__0[0]), .I2(mmcm_lock_count_reg__0[2]), .O(p_0_in__0[2])); (* SOFT_HLUTNM = "soft_lutpair18" *) LUT4 #( .INIT(16'h7F80)) \mmcm_lock_count[3]_i_1 (.I0(mmcm_lock_count_reg__0[2]), .I1(mmcm_lock_count_reg__0[0]), .I2(mmcm_lock_count_reg__0[1]), .I3(mmcm_lock_count_reg__0[3]), .O(p_0_in__0[3])); (* SOFT_HLUTNM = "soft_lutpair18" *) LUT5 #( .INIT(32'h7FFF8000)) \mmcm_lock_count[4]_i_1 (.I0(mmcm_lock_count_reg__0[3]), .I1(mmcm_lock_count_reg__0[1]), .I2(mmcm_lock_count_reg__0[0]), .I3(mmcm_lock_count_reg__0[2]), .I4(mmcm_lock_count_reg__0[4]), .O(p_0_in__0[4])); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \mmcm_lock_count[5]_i_1 (.I0(mmcm_lock_count_reg__0[4]), .I1(mmcm_lock_count_reg__0[2]), .I2(mmcm_lock_count_reg__0[0]), .I3(mmcm_lock_count_reg__0[1]), .I4(mmcm_lock_count_reg__0[3]), .I5(mmcm_lock_count_reg__0[5]), .O(p_0_in__0[5])); (* SOFT_HLUTNM = "soft_lutpair27" *) LUT2 #( .INIT(4'h9)) \mmcm_lock_count[6]_i_1 (.I0(\mmcm_lock_count[7]_i_4_n_0 ), .I1(mmcm_lock_count_reg__0[6]), .O(p_0_in__0[6])); LUT3 #( .INIT(8'hBF)) \mmcm_lock_count[7]_i_2 (.I0(\mmcm_lock_count[7]_i_4_n_0 ), .I1(mmcm_lock_count_reg__0[6]), .I2(mmcm_lock_count_reg__0[7]), .O(\mmcm_lock_count[7]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair27" *) LUT3 #( .INIT(8'hD2)) \mmcm_lock_count[7]_i_3 (.I0(mmcm_lock_count_reg__0[6]), .I1(\mmcm_lock_count[7]_i_4_n_0 ), .I2(mmcm_lock_count_reg__0[7]), .O(p_0_in__0[7])); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) \mmcm_lock_count[7]_i_4 (.I0(mmcm_lock_count_reg__0[4]), .I1(mmcm_lock_count_reg__0[2]), .I2(mmcm_lock_count_reg__0[0]), .I3(mmcm_lock_count_reg__0[1]), .I4(mmcm_lock_count_reg__0[3]), .I5(mmcm_lock_count_reg__0[5]), .O(\mmcm_lock_count[7]_i_4_n_0 )); FDRE #( .INIT(1'b0)) \mmcm_lock_count_reg[0] (.C(SYSCLK_IN), .CE(\mmcm_lock_count[7]_i_2_n_0 ), .D(p_0_in__0[0]), .Q(mmcm_lock_count_reg__0[0]), .R(sync_mmcm_lock_reclocked_n_0)); FDRE #( .INIT(1'b0)) \mmcm_lock_count_reg[1] (.C(SYSCLK_IN), .CE(\mmcm_lock_count[7]_i_2_n_0 ), .D(p_0_in__0[1]), .Q(mmcm_lock_count_reg__0[1]), .R(sync_mmcm_lock_reclocked_n_0)); FDRE #( .INIT(1'b0)) \mmcm_lock_count_reg[2] (.C(SYSCLK_IN), .CE(\mmcm_lock_count[7]_i_2_n_0 ), .D(p_0_in__0[2]), .Q(mmcm_lock_count_reg__0[2]), .R(sync_mmcm_lock_reclocked_n_0)); FDRE #( .INIT(1'b0)) \mmcm_lock_count_reg[3] (.C(SYSCLK_IN), .CE(\mmcm_lock_count[7]_i_2_n_0 ), .D(p_0_in__0[3]), .Q(mmcm_lock_count_reg__0[3]), .R(sync_mmcm_lock_reclocked_n_0)); FDRE #( .INIT(1'b0)) \mmcm_lock_count_reg[4] (.C(SYSCLK_IN), .CE(\mmcm_lock_count[7]_i_2_n_0 ), .D(p_0_in__0[4]), .Q(mmcm_lock_count_reg__0[4]), .R(sync_mmcm_lock_reclocked_n_0)); FDRE #( .INIT(1'b0)) \mmcm_lock_count_reg[5] (.C(SYSCLK_IN), .CE(\mmcm_lock_count[7]_i_2_n_0 ), .D(p_0_in__0[5]), .Q(mmcm_lock_count_reg__0[5]), .R(sync_mmcm_lock_reclocked_n_0)); FDRE #( .INIT(1'b0)) \mmcm_lock_count_reg[6] (.C(SYSCLK_IN), .CE(\mmcm_lock_count[7]_i_2_n_0 ), .D(p_0_in__0[6]), .Q(mmcm_lock_count_reg__0[6]), .R(sync_mmcm_lock_reclocked_n_0)); FDRE #( .INIT(1'b0)) \mmcm_lock_count_reg[7] (.C(SYSCLK_IN), .CE(\mmcm_lock_count[7]_i_2_n_0 ), .D(p_0_in__0[7]), .Q(mmcm_lock_count_reg__0[7]), .R(sync_mmcm_lock_reclocked_n_0)); FDRE #( .INIT(1'b0)) mmcm_lock_reclocked_reg (.C(SYSCLK_IN), .CE(1'b1), .D(sync_mmcm_lock_reclocked_n_1), .Q(mmcm_lock_reclocked), .R(1'b0)); LUT6 #( .INIT(64'hFF00FF00DF00DF10)) pll_reset_asserted_i_1 (.I0(tx_state[1]), .I1(tx_state[3]), .I2(tx_state[0]), .I3(pll_reset_asserted_reg_n_0), .I4(gt0_cpllrefclklost_i), .I5(tx_state[2]), .O(pll_reset_asserted_i_1_n_0)); FDRE #( .INIT(1'b0)) pll_reset_asserted_reg (.C(SYSCLK_IN), .CE(1'b1), .D(pll_reset_asserted_i_1_n_0), .Q(pll_reset_asserted_reg_n_0), .R(SOFT_RESET_TX_IN)); LUT6 #( .INIT(64'h440000FF50505050)) reset_time_out_i_2 (.I0(tx_state[3]), .I1(txresetdone_s3), .I2(init_wait_done), .I3(tx_state[1]), .I4(tx_state[2]), .I5(tx_state[0]), .O(reset_time_out_i_2_n_0)); FDRE #( .INIT(1'b0)) reset_time_out_reg (.C(SYSCLK_IN), .CE(1'b1), .D(sync_CPLLLOCK_n_1), .Q(reset_time_out), .R(SOFT_RESET_TX_IN)); (* SOFT_HLUTNM = "soft_lutpair25" *) LUT5 #( .INIT(32'hFFFB0002)) run_phase_alignment_int_i_1 (.I0(tx_state[3]), .I1(tx_state[0]), .I2(tx_state[1]), .I3(tx_state[2]), .I4(gt0_run_tx_phalignment_i), .O(run_phase_alignment_int_i_1_n_0)); FDRE #( .INIT(1'b0)) run_phase_alignment_int_reg (.C(SYSCLK_IN), .CE(1'b1), .D(run_phase_alignment_int_i_1_n_0), .Q(gt0_run_tx_phalignment_i), .R(SOFT_RESET_TX_IN)); FDRE #( .INIT(1'b0)) run_phase_alignment_int_s3_reg (.C(gt0_txusrclk_in), .CE(1'b1), .D(data_out), .Q(run_phase_alignment_int_s3), .R(1'b0)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_sync_block sync_CPLLLOCK (.E(sync_CPLLLOCK_n_0), .\FSM_sequential_tx_state_reg[0] (\FSM_sequential_tx_state[3]_i_3_n_0 ), .\FSM_sequential_tx_state_reg[0]_0 (\FSM_sequential_tx_state[3]_i_5_n_0 ), .\FSM_sequential_tx_state_reg[0]_1 (\FSM_sequential_tx_state[3]_i_6_n_0 ), .\FSM_sequential_tx_state_reg[0]_2 (\FSM_sequential_tx_state[3]_i_7_n_0 ), .\FSM_sequential_tx_state_reg[0]_3 (pll_reset_asserted_reg_n_0), .\FSM_sequential_tx_state_reg[0]_4 (CPLL_RESET_i_2_n_0), .\FSM_sequential_tx_state_reg[0]_5 (\FSM_sequential_tx_state[0]_i_2_n_0 ), .Q(tx_state), .SYSCLK_IN(SYSCLK_IN), .gt0_cplllock_out(gt0_cplllock_out), .init_wait_done(init_wait_done), .mmcm_lock_reclocked(mmcm_lock_reclocked), .reset_time_out(reset_time_out), .reset_time_out_reg(sync_CPLLLOCK_n_1), .reset_time_out_reg_0(reset_time_out_i_2_n_0)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_sync_block_1 sync_TXRESETDONE (.SYSCLK_IN(SYSCLK_IN), .data_out(txresetdone_s2), .gt0_txresetdone_out(gt0_txresetdone_out)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_sync_block_2 sync_mmcm_lock_reclocked (.Q(mmcm_lock_count_reg__0[7:6]), .SR(sync_mmcm_lock_reclocked_n_0), .SYSCLK_IN(SYSCLK_IN), .mmcm_lock_reclocked(mmcm_lock_reclocked), .mmcm_lock_reclocked_reg(sync_mmcm_lock_reclocked_n_1), .mmcm_lock_reclocked_reg_0(\mmcm_lock_count[7]_i_4_n_0 )); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_sync_block_3 sync_run_phase_alignment_int (.data_in(gt0_run_tx_phalignment_i), .data_out(data_out), .gt0_txusrclk_in(gt0_txusrclk_in)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_sync_block_4 sync_time_out_wait_bypass (.SYSCLK_IN(SYSCLK_IN), .data_in(time_out_wait_bypass_reg_n_0), .data_out(time_out_wait_bypass_s2)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_sync_block_5 sync_tx_fsm_reset_done_int (.GT0_TX_FSM_RESET_DONE_OUT(GT0_TX_FSM_RESET_DONE_OUT), .data_out(tx_fsm_reset_done_int_s2), .gt0_txusrclk_in(gt0_txusrclk_in)); LUT6 #( .INIT(64'h00000000AAAABAAA)) time_out_2ms_i_1__0 (.I0(time_out_2ms_reg_n_0), .I1(time_out_counter_reg[14]), .I2(time_out_counter_reg[7]), .I3(time_out_2ms_i_2_n_0), .I4(\time_out_counter[0]_i_3_n_0 ), .I5(reset_time_out), .O(time_out_2ms_i_1__0_n_0)); LUT6 #( .INIT(64'h0002000000000000)) time_out_2ms_i_2 (.I0(time_out_counter_reg[12]), .I1(time_out_counter_reg[10]), .I2(time_out_counter_reg[5]), .I3(time_out_counter_reg[9]), .I4(time_out_counter_reg[16]), .I5(time_out_counter_reg[13]), .O(time_out_2ms_i_2_n_0)); FDRE #( .INIT(1'b0)) time_out_2ms_reg (.C(SYSCLK_IN), .CE(1'b1), .D(time_out_2ms_i_1__0_n_0), .Q(time_out_2ms_reg_n_0), .R(1'b0)); LUT6 #( .INIT(64'h00000000AAAAAAEA)) time_out_500us_i_1 (.I0(time_out_500us_reg_n_0), .I1(time_out_500us_i_2_n_0), .I2(time_out_counter_reg[5]), .I3(time_out_counter_reg[7]), .I4(\time_out_counter[0]_i_3_n_0 ), .I5(reset_time_out), .O(time_out_500us_i_1_n_0)); LUT6 #( .INIT(64'h0000100000000000)) time_out_500us_i_2 (.I0(time_out_counter_reg[12]), .I1(time_out_counter_reg[13]), .I2(time_out_counter_reg[9]), .I3(time_out_counter_reg[10]), .I4(time_out_counter_reg[16]), .I5(time_out_counter_reg[14]), .O(time_out_500us_i_2_n_0)); FDRE #( .INIT(1'b0)) time_out_500us_reg (.C(SYSCLK_IN), .CE(1'b1), .D(time_out_500us_i_1_n_0), .Q(time_out_500us_reg_n_0), .R(1'b0)); LUT6 #( .INIT(64'hFFFFFFFFFFEFFFFF)) \time_out_counter[0]_i_1__0 (.I0(\time_out_counter[0]_i_3_n_0 ), .I1(time_out_counter_reg[5]), .I2(time_out_counter_reg[7]), .I3(time_out_counter_reg[14]), .I4(time_out_counter_reg[12]), .I5(\time_out_counter[0]_i_4__0_n_0 ), .O(time_out_counter)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \time_out_counter[0]_i_3 (.I0(\time_out_counter[0]_i_6__0_n_0 ), .I1(time_out_counter_reg[1]), .I2(time_out_counter_reg[0]), .I3(time_out_counter_reg[3]), .I4(time_out_counter_reg[2]), .I5(time_out_counter_reg[8]), .O(\time_out_counter[0]_i_3_n_0 )); LUT4 #( .INIT(16'hEFFF)) \time_out_counter[0]_i_4__0 (.I0(time_out_counter_reg[10]), .I1(time_out_counter_reg[9]), .I2(time_out_counter_reg[16]), .I3(time_out_counter_reg[13]), .O(\time_out_counter[0]_i_4__0_n_0 )); LUT1 #( .INIT(2'h1)) \time_out_counter[0]_i_5 (.I0(time_out_counter_reg[0]), .O(\time_out_counter[0]_i_5_n_0 )); LUT4 #( .INIT(16'hFFEF)) \time_out_counter[0]_i_6__0 (.I0(time_out_counter_reg[6]), .I1(time_out_counter_reg[4]), .I2(time_out_counter_reg[11]), .I3(time_out_counter_reg[15]), .O(\time_out_counter[0]_i_6__0_n_0 )); FDRE #( .INIT(1'b0)) \time_out_counter_reg[0] (.C(SYSCLK_IN), .CE(time_out_counter), .D(\time_out_counter_reg[0]_i_2_n_7 ), .Q(time_out_counter_reg[0]), .R(reset_time_out)); CARRY4 \time_out_counter_reg[0]_i_2 (.CI(1'b0), .CO({\time_out_counter_reg[0]_i_2_n_0 ,\time_out_counter_reg[0]_i_2_n_1 ,\time_out_counter_reg[0]_i_2_n_2 ,\time_out_counter_reg[0]_i_2_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b1}), .O({\time_out_counter_reg[0]_i_2_n_4 ,\time_out_counter_reg[0]_i_2_n_5 ,\time_out_counter_reg[0]_i_2_n_6 ,\time_out_counter_reg[0]_i_2_n_7 }), .S({time_out_counter_reg[3:1],\time_out_counter[0]_i_5_n_0 })); FDRE #( .INIT(1'b0)) \time_out_counter_reg[10] (.C(SYSCLK_IN), .CE(time_out_counter), .D(\time_out_counter_reg[8]_i_1_n_5 ), .Q(time_out_counter_reg[10]), .R(reset_time_out)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[11] (.C(SYSCLK_IN), .CE(time_out_counter), .D(\time_out_counter_reg[8]_i_1_n_4 ), .Q(time_out_counter_reg[11]), .R(reset_time_out)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[12] (.C(SYSCLK_IN), .CE(time_out_counter), .D(\time_out_counter_reg[12]_i_1_n_7 ), .Q(time_out_counter_reg[12]), .R(reset_time_out)); CARRY4 \time_out_counter_reg[12]_i_1 (.CI(\time_out_counter_reg[8]_i_1_n_0 ), .CO({\time_out_counter_reg[12]_i_1_n_0 ,\time_out_counter_reg[12]_i_1_n_1 ,\time_out_counter_reg[12]_i_1_n_2 ,\time_out_counter_reg[12]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\time_out_counter_reg[12]_i_1_n_4 ,\time_out_counter_reg[12]_i_1_n_5 ,\time_out_counter_reg[12]_i_1_n_6 ,\time_out_counter_reg[12]_i_1_n_7 }), .S(time_out_counter_reg[15:12])); FDRE #( .INIT(1'b0)) \time_out_counter_reg[13] (.C(SYSCLK_IN), .CE(time_out_counter), .D(\time_out_counter_reg[12]_i_1_n_6 ), .Q(time_out_counter_reg[13]), .R(reset_time_out)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[14] (.C(SYSCLK_IN), .CE(time_out_counter), .D(\time_out_counter_reg[12]_i_1_n_5 ), .Q(time_out_counter_reg[14]), .R(reset_time_out)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[15] (.C(SYSCLK_IN), .CE(time_out_counter), .D(\time_out_counter_reg[12]_i_1_n_4 ), .Q(time_out_counter_reg[15]), .R(reset_time_out)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[16] (.C(SYSCLK_IN), .CE(time_out_counter), .D(\time_out_counter_reg[16]_i_1_n_7 ), .Q(time_out_counter_reg[16]), .R(reset_time_out)); CARRY4 \time_out_counter_reg[16]_i_1 (.CI(\time_out_counter_reg[12]_i_1_n_0 ), .CO(\NLW_time_out_counter_reg[16]_i_1_CO_UNCONNECTED [3:0]), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\NLW_time_out_counter_reg[16]_i_1_O_UNCONNECTED [3:1],\time_out_counter_reg[16]_i_1_n_7 }), .S({1'b0,1'b0,1'b0,time_out_counter_reg[16]})); FDRE #( .INIT(1'b0)) \time_out_counter_reg[1] (.C(SYSCLK_IN), .CE(time_out_counter), .D(\time_out_counter_reg[0]_i_2_n_6 ), .Q(time_out_counter_reg[1]), .R(reset_time_out)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[2] (.C(SYSCLK_IN), .CE(time_out_counter), .D(\time_out_counter_reg[0]_i_2_n_5 ), .Q(time_out_counter_reg[2]), .R(reset_time_out)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[3] (.C(SYSCLK_IN), .CE(time_out_counter), .D(\time_out_counter_reg[0]_i_2_n_4 ), .Q(time_out_counter_reg[3]), .R(reset_time_out)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[4] (.C(SYSCLK_IN), .CE(time_out_counter), .D(\time_out_counter_reg[4]_i_1_n_7 ), .Q(time_out_counter_reg[4]), .R(reset_time_out)); CARRY4 \time_out_counter_reg[4]_i_1 (.CI(\time_out_counter_reg[0]_i_2_n_0 ), .CO({\time_out_counter_reg[4]_i_1_n_0 ,\time_out_counter_reg[4]_i_1_n_1 ,\time_out_counter_reg[4]_i_1_n_2 ,\time_out_counter_reg[4]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\time_out_counter_reg[4]_i_1_n_4 ,\time_out_counter_reg[4]_i_1_n_5 ,\time_out_counter_reg[4]_i_1_n_6 ,\time_out_counter_reg[4]_i_1_n_7 }), .S(time_out_counter_reg[7:4])); FDRE #( .INIT(1'b0)) \time_out_counter_reg[5] (.C(SYSCLK_IN), .CE(time_out_counter), .D(\time_out_counter_reg[4]_i_1_n_6 ), .Q(time_out_counter_reg[5]), .R(reset_time_out)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[6] (.C(SYSCLK_IN), .CE(time_out_counter), .D(\time_out_counter_reg[4]_i_1_n_5 ), .Q(time_out_counter_reg[6]), .R(reset_time_out)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[7] (.C(SYSCLK_IN), .CE(time_out_counter), .D(\time_out_counter_reg[4]_i_1_n_4 ), .Q(time_out_counter_reg[7]), .R(reset_time_out)); FDRE #( .INIT(1'b0)) \time_out_counter_reg[8] (.C(SYSCLK_IN), .CE(time_out_counter), .D(\time_out_counter_reg[8]_i_1_n_7 ), .Q(time_out_counter_reg[8]), .R(reset_time_out)); CARRY4 \time_out_counter_reg[8]_i_1 (.CI(\time_out_counter_reg[4]_i_1_n_0 ), .CO({\time_out_counter_reg[8]_i_1_n_0 ,\time_out_counter_reg[8]_i_1_n_1 ,\time_out_counter_reg[8]_i_1_n_2 ,\time_out_counter_reg[8]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\time_out_counter_reg[8]_i_1_n_4 ,\time_out_counter_reg[8]_i_1_n_5 ,\time_out_counter_reg[8]_i_1_n_6 ,\time_out_counter_reg[8]_i_1_n_7 }), .S(time_out_counter_reg[11:8])); FDRE #( .INIT(1'b0)) \time_out_counter_reg[9] (.C(SYSCLK_IN), .CE(time_out_counter), .D(\time_out_counter_reg[8]_i_1_n_6 ), .Q(time_out_counter_reg[9]), .R(reset_time_out)); LUT4 #( .INIT(16'hAB00)) time_out_wait_bypass_i_1 (.I0(time_out_wait_bypass_reg_n_0), .I1(\wait_bypass_count[0]_i_4_n_0 ), .I2(tx_fsm_reset_done_int_s3), .I3(run_phase_alignment_int_s3), .O(time_out_wait_bypass_i_1_n_0)); FDRE #( .INIT(1'b0)) time_out_wait_bypass_reg (.C(gt0_txusrclk_in), .CE(1'b1), .D(time_out_wait_bypass_i_1_n_0), .Q(time_out_wait_bypass_reg_n_0), .R(1'b0)); FDRE #( .INIT(1'b0)) time_out_wait_bypass_s3_reg (.C(SYSCLK_IN), .CE(1'b1), .D(time_out_wait_bypass_s2), .Q(time_out_wait_bypass_s3), .R(1'b0)); LUT6 #( .INIT(64'h00000000AABAAAAA)) time_tlock_max_i_1__0 (.I0(time_tlock_max_reg_n_0), .I1(time_tlock_max_i_2_n_0), .I2(time_out_counter_reg[5]), .I3(time_tlock_max_i_3_n_0), .I4(time_tlock_max_i_4_n_0), .I5(reset_time_out), .O(time_tlock_max_i_1__0_n_0)); LUT5 #( .INIT(32'hFFFFFFFE)) time_tlock_max_i_2 (.I0(time_out_counter_reg[2]), .I1(time_out_counter_reg[3]), .I2(time_out_counter_reg[0]), .I3(time_out_counter_reg[1]), .I4(\time_out_counter[0]_i_6__0_n_0 ), .O(time_tlock_max_i_2_n_0)); LUT2 #( .INIT(4'hB)) time_tlock_max_i_3 (.I0(time_out_counter_reg[14]), .I1(time_out_counter_reg[7]), .O(time_tlock_max_i_3_n_0)); LUT6 #( .INIT(64'h0000000000002000)) time_tlock_max_i_4 (.I0(time_out_counter_reg[10]), .I1(time_out_counter_reg[12]), .I2(time_out_counter_reg[8]), .I3(time_out_counter_reg[9]), .I4(time_out_counter_reg[16]), .I5(time_out_counter_reg[13]), .O(time_tlock_max_i_4_n_0)); FDRE #( .INIT(1'b0)) time_tlock_max_reg (.C(SYSCLK_IN), .CE(1'b1), .D(time_tlock_max_i_1__0_n_0), .Q(time_tlock_max_reg_n_0), .R(1'b0)); LUT5 #( .INIT(32'hFFFF0008)) tx_fsm_reset_done_int_i_1 (.I0(tx_state[0]), .I1(tx_state[3]), .I2(tx_state[2]), .I3(tx_state[1]), .I4(GT0_TX_FSM_RESET_DONE_OUT), .O(tx_fsm_reset_done_int_i_1_n_0)); FDRE #( .INIT(1'b0)) tx_fsm_reset_done_int_reg (.C(SYSCLK_IN), .CE(1'b1), .D(tx_fsm_reset_done_int_i_1_n_0), .Q(GT0_TX_FSM_RESET_DONE_OUT), .R(SOFT_RESET_TX_IN)); FDRE #( .INIT(1'b0)) tx_fsm_reset_done_int_s3_reg (.C(gt0_txusrclk_in), .CE(1'b1), .D(tx_fsm_reset_done_int_s2), .Q(tx_fsm_reset_done_int_s3), .R(1'b0)); FDRE #( .INIT(1'b0)) txresetdone_s3_reg (.C(SYSCLK_IN), .CE(1'b1), .D(txresetdone_s2), .Q(txresetdone_s3), .R(1'b0)); LUT1 #( .INIT(2'h1)) \wait_bypass_count[0]_i_1 (.I0(run_phase_alignment_int_s3), .O(clear)); LUT2 #( .INIT(4'h2)) \wait_bypass_count[0]_i_2 (.I0(\wait_bypass_count[0]_i_4_n_0 ), .I1(tx_fsm_reset_done_int_s3), .O(\wait_bypass_count[0]_i_2_n_0 )); LUT4 #( .INIT(16'hFFFE)) \wait_bypass_count[0]_i_4 (.I0(\wait_bypass_count[0]_i_6_n_0 ), .I1(\wait_bypass_count[0]_i_7_n_0 ), .I2(\wait_bypass_count[0]_i_8_n_0 ), .I3(\wait_bypass_count[0]_i_9_n_0 ), .O(\wait_bypass_count[0]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \wait_bypass_count[0]_i_5 (.I0(wait_bypass_count_reg[0]), .O(\wait_bypass_count[0]_i_5_n_0 )); LUT4 #( .INIT(16'h7FFF)) \wait_bypass_count[0]_i_6 (.I0(wait_bypass_count_reg[5]), .I1(wait_bypass_count_reg[4]), .I2(wait_bypass_count_reg[7]), .I3(wait_bypass_count_reg[6]), .O(\wait_bypass_count[0]_i_6_n_0 )); LUT4 #( .INIT(16'h7FFF)) \wait_bypass_count[0]_i_7 (.I0(wait_bypass_count_reg[1]), .I1(wait_bypass_count_reg[0]), .I2(wait_bypass_count_reg[3]), .I3(wait_bypass_count_reg[2]), .O(\wait_bypass_count[0]_i_7_n_0 )); LUT4 #( .INIT(16'hFF7F)) \wait_bypass_count[0]_i_8 (.I0(wait_bypass_count_reg[13]), .I1(wait_bypass_count_reg[12]), .I2(wait_bypass_count_reg[15]), .I3(wait_bypass_count_reg[14]), .O(\wait_bypass_count[0]_i_8_n_0 )); LUT4 #( .INIT(16'hFFFD)) \wait_bypass_count[0]_i_9 (.I0(wait_bypass_count_reg[9]), .I1(wait_bypass_count_reg[8]), .I2(wait_bypass_count_reg[11]), .I3(wait_bypass_count_reg[10]), .O(\wait_bypass_count[0]_i_9_n_0 )); FDRE \wait_bypass_count_reg[0] (.C(gt0_txusrclk_in), .CE(\wait_bypass_count[0]_i_2_n_0 ), .D(\wait_bypass_count_reg[0]_i_3_n_7 ), .Q(wait_bypass_count_reg[0]), .R(clear)); CARRY4 \wait_bypass_count_reg[0]_i_3 (.CI(1'b0), .CO({\wait_bypass_count_reg[0]_i_3_n_0 ,\wait_bypass_count_reg[0]_i_3_n_1 ,\wait_bypass_count_reg[0]_i_3_n_2 ,\wait_bypass_count_reg[0]_i_3_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b1}), .O({\wait_bypass_count_reg[0]_i_3_n_4 ,\wait_bypass_count_reg[0]_i_3_n_5 ,\wait_bypass_count_reg[0]_i_3_n_6 ,\wait_bypass_count_reg[0]_i_3_n_7 }), .S({wait_bypass_count_reg[3:1],\wait_bypass_count[0]_i_5_n_0 })); FDRE \wait_bypass_count_reg[10] (.C(gt0_txusrclk_in), .CE(\wait_bypass_count[0]_i_2_n_0 ), .D(\wait_bypass_count_reg[8]_i_1_n_5 ), .Q(wait_bypass_count_reg[10]), .R(clear)); FDRE \wait_bypass_count_reg[11] (.C(gt0_txusrclk_in), .CE(\wait_bypass_count[0]_i_2_n_0 ), .D(\wait_bypass_count_reg[8]_i_1_n_4 ), .Q(wait_bypass_count_reg[11]), .R(clear)); FDRE \wait_bypass_count_reg[12] (.C(gt0_txusrclk_in), .CE(\wait_bypass_count[0]_i_2_n_0 ), .D(\wait_bypass_count_reg[12]_i_1_n_7 ), .Q(wait_bypass_count_reg[12]), .R(clear)); CARRY4 \wait_bypass_count_reg[12]_i_1 (.CI(\wait_bypass_count_reg[8]_i_1_n_0 ), .CO({\NLW_wait_bypass_count_reg[12]_i_1_CO_UNCONNECTED [3],\wait_bypass_count_reg[12]_i_1_n_1 ,\wait_bypass_count_reg[12]_i_1_n_2 ,\wait_bypass_count_reg[12]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\wait_bypass_count_reg[12]_i_1_n_4 ,\wait_bypass_count_reg[12]_i_1_n_5 ,\wait_bypass_count_reg[12]_i_1_n_6 ,\wait_bypass_count_reg[12]_i_1_n_7 }), .S(wait_bypass_count_reg[15:12])); FDRE \wait_bypass_count_reg[13] (.C(gt0_txusrclk_in), .CE(\wait_bypass_count[0]_i_2_n_0 ), .D(\wait_bypass_count_reg[12]_i_1_n_6 ), .Q(wait_bypass_count_reg[13]), .R(clear)); FDRE \wait_bypass_count_reg[14] (.C(gt0_txusrclk_in), .CE(\wait_bypass_count[0]_i_2_n_0 ), .D(\wait_bypass_count_reg[12]_i_1_n_5 ), .Q(wait_bypass_count_reg[14]), .R(clear)); FDRE \wait_bypass_count_reg[15] (.C(gt0_txusrclk_in), .CE(\wait_bypass_count[0]_i_2_n_0 ), .D(\wait_bypass_count_reg[12]_i_1_n_4 ), .Q(wait_bypass_count_reg[15]), .R(clear)); FDRE \wait_bypass_count_reg[1] (.C(gt0_txusrclk_in), .CE(\wait_bypass_count[0]_i_2_n_0 ), .D(\wait_bypass_count_reg[0]_i_3_n_6 ), .Q(wait_bypass_count_reg[1]), .R(clear)); FDRE \wait_bypass_count_reg[2] (.C(gt0_txusrclk_in), .CE(\wait_bypass_count[0]_i_2_n_0 ), .D(\wait_bypass_count_reg[0]_i_3_n_5 ), .Q(wait_bypass_count_reg[2]), .R(clear)); FDRE \wait_bypass_count_reg[3] (.C(gt0_txusrclk_in), .CE(\wait_bypass_count[0]_i_2_n_0 ), .D(\wait_bypass_count_reg[0]_i_3_n_4 ), .Q(wait_bypass_count_reg[3]), .R(clear)); FDRE \wait_bypass_count_reg[4] (.C(gt0_txusrclk_in), .CE(\wait_bypass_count[0]_i_2_n_0 ), .D(\wait_bypass_count_reg[4]_i_1_n_7 ), .Q(wait_bypass_count_reg[4]), .R(clear)); CARRY4 \wait_bypass_count_reg[4]_i_1 (.CI(\wait_bypass_count_reg[0]_i_3_n_0 ), .CO({\wait_bypass_count_reg[4]_i_1_n_0 ,\wait_bypass_count_reg[4]_i_1_n_1 ,\wait_bypass_count_reg[4]_i_1_n_2 ,\wait_bypass_count_reg[4]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\wait_bypass_count_reg[4]_i_1_n_4 ,\wait_bypass_count_reg[4]_i_1_n_5 ,\wait_bypass_count_reg[4]_i_1_n_6 ,\wait_bypass_count_reg[4]_i_1_n_7 }), .S(wait_bypass_count_reg[7:4])); FDRE \wait_bypass_count_reg[5] (.C(gt0_txusrclk_in), .CE(\wait_bypass_count[0]_i_2_n_0 ), .D(\wait_bypass_count_reg[4]_i_1_n_6 ), .Q(wait_bypass_count_reg[5]), .R(clear)); FDRE \wait_bypass_count_reg[6] (.C(gt0_txusrclk_in), .CE(\wait_bypass_count[0]_i_2_n_0 ), .D(\wait_bypass_count_reg[4]_i_1_n_5 ), .Q(wait_bypass_count_reg[6]), .R(clear)); FDRE \wait_bypass_count_reg[7] (.C(gt0_txusrclk_in), .CE(\wait_bypass_count[0]_i_2_n_0 ), .D(\wait_bypass_count_reg[4]_i_1_n_4 ), .Q(wait_bypass_count_reg[7]), .R(clear)); FDRE \wait_bypass_count_reg[8] (.C(gt0_txusrclk_in), .CE(\wait_bypass_count[0]_i_2_n_0 ), .D(\wait_bypass_count_reg[8]_i_1_n_7 ), .Q(wait_bypass_count_reg[8]), .R(clear)); CARRY4 \wait_bypass_count_reg[8]_i_1 (.CI(\wait_bypass_count_reg[4]_i_1_n_0 ), .CO({\wait_bypass_count_reg[8]_i_1_n_0 ,\wait_bypass_count_reg[8]_i_1_n_1 ,\wait_bypass_count_reg[8]_i_1_n_2 ,\wait_bypass_count_reg[8]_i_1_n_3 }), .CYINIT(1'b0), .DI({1'b0,1'b0,1'b0,1'b0}), .O({\wait_bypass_count_reg[8]_i_1_n_4 ,\wait_bypass_count_reg[8]_i_1_n_5 ,\wait_bypass_count_reg[8]_i_1_n_6 ,\wait_bypass_count_reg[8]_i_1_n_7 }), .S(wait_bypass_count_reg[11:8])); FDRE \wait_bypass_count_reg[9] (.C(gt0_txusrclk_in), .CE(\wait_bypass_count[0]_i_2_n_0 ), .D(\wait_bypass_count_reg[8]_i_1_n_6 ), .Q(wait_bypass_count_reg[9]), .R(clear)); (* SOFT_HLUTNM = "soft_lutpair29" *) LUT1 #( .INIT(2'h1)) \wait_time_cnt[0]_i_1 (.I0(wait_time_cnt_reg__0[0]), .O(wait_time_cnt0[0])); (* SOFT_HLUTNM = "soft_lutpair29" *) LUT2 #( .INIT(4'h9)) \wait_time_cnt[1]_i_1 (.I0(wait_time_cnt_reg__0[1]), .I1(wait_time_cnt_reg__0[0]), .O(wait_time_cnt0[1])); LUT3 #( .INIT(8'hA9)) \wait_time_cnt[2]_i_1 (.I0(wait_time_cnt_reg__0[2]), .I1(wait_time_cnt_reg__0[0]), .I2(wait_time_cnt_reg__0[1]), .O(wait_time_cnt0[2])); (* SOFT_HLUTNM = "soft_lutpair21" *) LUT4 #( .INIT(16'hAAA9)) \wait_time_cnt[3]_i_1 (.I0(wait_time_cnt_reg__0[3]), .I1(wait_time_cnt_reg__0[1]), .I2(wait_time_cnt_reg__0[0]), .I3(wait_time_cnt_reg__0[2]), .O(wait_time_cnt0[3])); (* SOFT_HLUTNM = "soft_lutpair21" *) LUT5 #( .INIT(32'hAAAAAAA9)) \wait_time_cnt[4]_i_1 (.I0(wait_time_cnt_reg__0[4]), .I1(wait_time_cnt_reg__0[2]), .I2(wait_time_cnt_reg__0[0]), .I3(wait_time_cnt_reg__0[1]), .I4(wait_time_cnt_reg__0[3]), .O(wait_time_cnt0[4])); LUT6 #( .INIT(64'hAAAAAAAAAAAAAAA9)) \wait_time_cnt[5]_i_1 (.I0(wait_time_cnt_reg__0[5]), .I1(wait_time_cnt_reg__0[3]), .I2(wait_time_cnt_reg__0[1]), .I3(wait_time_cnt_reg__0[0]), .I4(wait_time_cnt_reg__0[2]), .I5(wait_time_cnt_reg__0[4]), .O(wait_time_cnt0[5])); LUT4 #( .INIT(16'h0700)) \wait_time_cnt[6]_i_1__0 (.I0(tx_state[1]), .I1(tx_state[2]), .I2(tx_state[3]), .I3(tx_state[0]), .O(\wait_time_cnt[6]_i_1__0_n_0 )); LUT2 #( .INIT(4'hE)) \wait_time_cnt[6]_i_2 (.I0(\wait_time_cnt[6]_i_4_n_0 ), .I1(wait_time_cnt_reg__0[6]), .O(sel)); LUT2 #( .INIT(4'h9)) \wait_time_cnt[6]_i_3 (.I0(wait_time_cnt_reg__0[6]), .I1(\wait_time_cnt[6]_i_4_n_0 ), .O(wait_time_cnt0[6])); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \wait_time_cnt[6]_i_4 (.I0(wait_time_cnt_reg__0[4]), .I1(wait_time_cnt_reg__0[2]), .I2(wait_time_cnt_reg__0[0]), .I3(wait_time_cnt_reg__0[1]), .I4(wait_time_cnt_reg__0[3]), .I5(wait_time_cnt_reg__0[5]), .O(\wait_time_cnt[6]_i_4_n_0 )); FDRE \wait_time_cnt_reg[0] (.C(SYSCLK_IN), .CE(sel), .D(wait_time_cnt0[0]), .Q(wait_time_cnt_reg__0[0]), .R(\wait_time_cnt[6]_i_1__0_n_0 )); FDRE \wait_time_cnt_reg[1] (.C(SYSCLK_IN), .CE(sel), .D(wait_time_cnt0[1]), .Q(wait_time_cnt_reg__0[1]), .R(\wait_time_cnt[6]_i_1__0_n_0 )); FDSE \wait_time_cnt_reg[2] (.C(SYSCLK_IN), .CE(sel), .D(wait_time_cnt0[2]), .Q(wait_time_cnt_reg__0[2]), .S(\wait_time_cnt[6]_i_1__0_n_0 )); FDRE \wait_time_cnt_reg[3] (.C(SYSCLK_IN), .CE(sel), .D(wait_time_cnt0[3]), .Q(wait_time_cnt_reg__0[3]), .R(\wait_time_cnt[6]_i_1__0_n_0 )); FDRE \wait_time_cnt_reg[4] (.C(SYSCLK_IN), .CE(sel), .D(wait_time_cnt0[4]), .Q(wait_time_cnt_reg__0[4]), .R(\wait_time_cnt[6]_i_1__0_n_0 )); FDSE \wait_time_cnt_reg[5] (.C(SYSCLK_IN), .CE(sel), .D(wait_time_cnt0[5]), .Q(wait_time_cnt_reg__0[5]), .S(\wait_time_cnt[6]_i_1__0_n_0 )); FDSE \wait_time_cnt_reg[6] (.C(SYSCLK_IN), .CE(sel), .D(wait_time_cnt0[6]), .Q(wait_time_cnt_reg__0[6]), .S(\wait_time_cnt[6]_i_1__0_n_0 )); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_cpll_railing (cpllpd_in, cpllreset_in, gt0_gtrefclk1_in, gt0_cpllpd_in, gt0_cpllreset_t); output cpllpd_in; output cpllreset_in; input gt0_gtrefclk1_in; input gt0_cpllpd_in; input gt0_cpllreset_t; wire cpll_pd_out; wire cpll_reset_out; wire cpllpd_in; wire \cpllpd_wait_reg[31]_srl32_n_1 ; wire \cpllpd_wait_reg[63]_srl32_n_1 ; wire \cpllpd_wait_reg[94]_srl31_n_0 ; wire cpllreset_in; wire \cpllreset_wait_reg[126]_srl31_n_0 ; wire \cpllreset_wait_reg[31]_srl32_n_1 ; wire \cpllreset_wait_reg[63]_srl32_n_1 ; wire \cpllreset_wait_reg[95]_srl32_n_1 ; wire gt0_cpllpd_in; wire gt0_cpllreset_t; wire gt0_gtrefclk1_in; wire \use_bufh_cpll.refclk_buf_n_0 ; wire \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ; wire \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ; wire \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED ; wire \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED ; wire \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ; wire \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ; wire \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ; (* srl_bus_name = "U0/\ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg " *) (* srl_name = "U0/\ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[31]_srl32 " *) SRLC32E #( .INIT(32'hFFFFFFFF)) \cpllpd_wait_reg[31]_srl32 (.A({1'b1,1'b1,1'b1,1'b1,1'b1}), .CE(1'b1), .CLK(\use_bufh_cpll.refclk_buf_n_0 ), .D(1'b0), .Q(\NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED ), .Q31(\cpllpd_wait_reg[31]_srl32_n_1 )); (* srl_bus_name = "U0/\ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg " *) (* srl_name = "U0/\ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[63]_srl32 " *) SRLC32E #( .INIT(32'hFFFFFFFF)) \cpllpd_wait_reg[63]_srl32 (.A({1'b1,1'b1,1'b1,1'b1,1'b1}), .CE(1'b1), .CLK(\use_bufh_cpll.refclk_buf_n_0 ), .D(\cpllpd_wait_reg[31]_srl32_n_1 ), .Q(\NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED ), .Q31(\cpllpd_wait_reg[63]_srl32_n_1 )); (* srl_bus_name = "U0/\ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg " *) (* srl_name = "U0/\ngFEC_mgt_i/cpll_railing0_i/cpllpd_wait_reg[94]_srl31 " *) SRLC32E #( .INIT(32'h7FFFFFFF)) \cpllpd_wait_reg[94]_srl31 (.A({1'b1,1'b1,1'b1,1'b1,1'b0}), .CE(1'b1), .CLK(\use_bufh_cpll.refclk_buf_n_0 ), .D(\cpllpd_wait_reg[63]_srl32_n_1 ), .Q(\cpllpd_wait_reg[94]_srl31_n_0 ), .Q31(\NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED )); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b1)) \cpllpd_wait_reg[95] (.C(\use_bufh_cpll.refclk_buf_n_0 ), .CE(1'b1), .D(\cpllpd_wait_reg[94]_srl31_n_0 ), .Q(cpll_pd_out), .R(1'b0)); (* srl_bus_name = "U0/\ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg " *) (* srl_name = "U0/\ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[126]_srl31 " *) SRLC32E #( .INIT(32'h00000000)) \cpllreset_wait_reg[126]_srl31 (.A({1'b1,1'b1,1'b1,1'b1,1'b0}), .CE(1'b1), .CLK(\use_bufh_cpll.refclk_buf_n_0 ), .D(\cpllreset_wait_reg[95]_srl32_n_1 ), .Q(\cpllreset_wait_reg[126]_srl31_n_0 ), .Q31(\NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED )); (* equivalent_register_removal = "no" *) FDRE #( .INIT(1'b0)) \cpllreset_wait_reg[127] (.C(\use_bufh_cpll.refclk_buf_n_0 ), .CE(1'b1), .D(\cpllreset_wait_reg[126]_srl31_n_0 ), .Q(cpll_reset_out), .R(1'b0)); (* srl_bus_name = "U0/\ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg " *) (* srl_name = "U0/\ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[31]_srl32 " *) SRLC32E #( .INIT(32'h000000FF)) \cpllreset_wait_reg[31]_srl32 (.A({1'b1,1'b1,1'b1,1'b1,1'b1}), .CE(1'b1), .CLK(\use_bufh_cpll.refclk_buf_n_0 ), .D(1'b0), .Q(\NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED ), .Q31(\cpllreset_wait_reg[31]_srl32_n_1 )); (* srl_bus_name = "U0/\ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg " *) (* srl_name = "U0/\ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[63]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \cpllreset_wait_reg[63]_srl32 (.A({1'b1,1'b1,1'b1,1'b1,1'b1}), .CE(1'b1), .CLK(\use_bufh_cpll.refclk_buf_n_0 ), .D(\cpllreset_wait_reg[31]_srl32_n_1 ), .Q(\NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED ), .Q31(\cpllreset_wait_reg[63]_srl32_n_1 )); (* srl_bus_name = "U0/\ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg " *) (* srl_name = "U0/\ngFEC_mgt_i/cpll_railing0_i/cpllreset_wait_reg[95]_srl32 " *) SRLC32E #( .INIT(32'h00000000)) \cpllreset_wait_reg[95]_srl32 (.A({1'b1,1'b1,1'b1,1'b1,1'b1}), .CE(1'b1), .CLK(\use_bufh_cpll.refclk_buf_n_0 ), .D(\cpllreset_wait_reg[63]_srl32_n_1 ), .Q(\NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED ), .Q31(\cpllreset_wait_reg[95]_srl32_n_1 )); LUT2 #( .INIT(4'hE)) gtxe2_i_i_1 (.I0(cpll_pd_out), .I1(gt0_cpllpd_in), .O(cpllpd_in)); LUT2 #( .INIT(4'hE)) gtxe2_i_i_2 (.I0(cpll_reset_out), .I1(gt0_cpllreset_t), .O(cpllreset_in)); (* box_type = "PRIMITIVE" *) BUFH \use_bufh_cpll.refclk_buf (.I(gt0_gtrefclk1_in), .O(\use_bufh_cpll.refclk_buf_n_0 )); endmodule (* EXAMPLE_SIMULATION = "0" *) (* EXAMPLE_SIM_GTRESET_SPEEDUP = "TRUE" *) (* EXAMPLE_USE_CHIPSCOPE = "0" *) (* STABLE_CLOCK_PERIOD = "25" *) (* USE_BUFG = "0" *) (* downgradeipidentifiedwarnings = "yes" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_init (SYSCLK_IN, SOFT_RESET_TX_IN, SOFT_RESET_RX_IN, DONT_RESET_ON_DATA_ERROR_IN, GT0_TX_FSM_RESET_DONE_OUT, GT0_RX_FSM_RESET_DONE_OUT, GT0_DATA_VALID_IN, gt0_cpllfbclklost_out, gt0_cplllock_out, gt0_cplllockdetclk_in, gt0_cpllpd_in, gt0_cpllreset_in, gt0_gtrefclk0_in, gt0_gtrefclk1_in, gt0_drpaddr_in, gt0_drpclk_in, gt0_drpdi_in, gt0_drpdo_out, gt0_drpen_in, gt0_drprdy_out, gt0_drpwe_in, gt0_dmonitorout_out, gt0_loopback_in, gt0_rxpd_in, gt0_txpd_in, gt0_eyescanreset_in, gt0_rxuserrdy_in, gt0_eyescandataerror_out, gt0_eyescantrigger_in, gt0_rxusrclk_in, gt0_rxusrclk2_in, gt0_rxdata_out, gt0_gtxrxp_in, gt0_gtxrxn_in, gt0_rxphmonitor_out, gt0_rxphslipmonitor_out, gt0_rxdfelpmreset_in, gt0_rxmonitorout_out, gt0_rxmonitorsel_in, gt0_rxoutclk_out, gt0_rxoutclkfabric_out, gt0_gtrxreset_in, gt0_rxpmareset_in, gt0_rxpolarity_in, gt0_rxslide_in, gt0_rxresetdone_out, gt0_txpostcursor_in, gt0_txprecursor_in, gt0_gttxreset_in, gt0_txuserrdy_in, gt0_txusrclk_in, gt0_txusrclk2_in, gt0_txelecidle_in, gt0_txdiffctrl_in, gt0_txdata_in, gt0_gtxtxn_out, gt0_gtxtxp_out, gt0_txoutclk_out, gt0_txoutclkfabric_out, gt0_txoutclkpcs_out, gt0_txresetdone_out, gt0_txpolarity_in, GT0_QPLLOUTCLK_IN, GT0_QPLLOUTREFCLK_IN); input SYSCLK_IN; input SOFT_RESET_TX_IN; input SOFT_RESET_RX_IN; input DONT_RESET_ON_DATA_ERROR_IN; output GT0_TX_FSM_RESET_DONE_OUT; output GT0_RX_FSM_RESET_DONE_OUT; input GT0_DATA_VALID_IN; output gt0_cpllfbclklost_out; output gt0_cplllock_out; input gt0_cplllockdetclk_in; input gt0_cpllpd_in; input gt0_cpllreset_in; input gt0_gtrefclk0_in; input gt0_gtrefclk1_in; input [8:0]gt0_drpaddr_in; input gt0_drpclk_in; input [15:0]gt0_drpdi_in; output [15:0]gt0_drpdo_out; input gt0_drpen_in; output gt0_drprdy_out; input gt0_drpwe_in; output [7:0]gt0_dmonitorout_out; input [2:0]gt0_loopback_in; input [1:0]gt0_rxpd_in; input [1:0]gt0_txpd_in; input gt0_eyescanreset_in; input gt0_rxuserrdy_in; output gt0_eyescandataerror_out; input gt0_eyescantrigger_in; input gt0_rxusrclk_in; input gt0_rxusrclk2_in; output [19:0]gt0_rxdata_out; input gt0_gtxrxp_in; input gt0_gtxrxn_in; output [4:0]gt0_rxphmonitor_out; output [4:0]gt0_rxphslipmonitor_out; input gt0_rxdfelpmreset_in; output [6:0]gt0_rxmonitorout_out; input [1:0]gt0_rxmonitorsel_in; output gt0_rxoutclk_out; output gt0_rxoutclkfabric_out; input gt0_gtrxreset_in; input gt0_rxpmareset_in; input gt0_rxpolarity_in; input gt0_rxslide_in; output gt0_rxresetdone_out; input [4:0]gt0_txpostcursor_in; input [4:0]gt0_txprecursor_in; input gt0_gttxreset_in; input gt0_txuserrdy_in; input gt0_txusrclk_in; input gt0_txusrclk2_in; input gt0_txelecidle_in; input [3:0]gt0_txdiffctrl_in; input [19:0]gt0_txdata_in; output gt0_gtxtxn_out; output gt0_gtxtxp_out; output gt0_txoutclk_out; output gt0_txoutclkfabric_out; output gt0_txoutclkpcs_out; output gt0_txresetdone_out; input gt0_txpolarity_in; input GT0_QPLLOUTCLK_IN; input GT0_QPLLOUTREFCLK_IN; wire DONT_RESET_ON_DATA_ERROR_IN; wire GT0_DATA_VALID_IN; wire GT0_QPLLOUTCLK_IN; wire GT0_QPLLOUTREFCLK_IN; wire GT0_RX_FSM_RESET_DONE_OUT; wire GT0_TX_FSM_RESET_DONE_OUT; wire SOFT_RESET_RX_IN; wire SOFT_RESET_TX_IN; wire SYSCLK_IN; wire gt0_cpllfbclklost_out; wire gt0_cplllock_out; wire gt0_cplllockdetclk_in; wire gt0_cpllpd_in; wire gt0_cpllrefclklost_i; wire gt0_cpllreset_t; wire [7:0]gt0_dmonitorout_out; wire [8:0]gt0_drpaddr_in; wire gt0_drpclk_in; wire [15:0]gt0_drpdi_in; wire [15:0]gt0_drpdo_out; wire gt0_drpen_in; wire gt0_drprdy_out; wire gt0_drpwe_in; wire gt0_eyescandataerror_out; wire gt0_eyescanreset_in; wire gt0_eyescantrigger_in; wire gt0_gtrefclk0_in; wire gt0_gtrefclk1_in; wire gt0_gtrxreset_t; wire gt0_gttxreset_t; wire gt0_gtxrxn_in; wire gt0_gtxrxp_in; wire gt0_gtxtxn_out; wire gt0_gtxtxp_out; wire [2:0]gt0_loopback_in; wire gt0_run_rx_phalignment_i; wire gt0_rx_cdrlock_counter; wire \gt0_rx_cdrlock_counter[0]_i_1_n_0 ; wire \gt0_rx_cdrlock_counter[10]_i_3_n_0 ; wire \gt0_rx_cdrlock_counter[10]_i_4_n_0 ; wire [10:0]gt0_rx_cdrlock_counter_reg__0; wire gt0_rx_cdrlocked_i_2_n_0; wire gt0_rx_cdrlocked_i_3_n_0; wire gt0_rx_cdrlocked_reg_n_0; wire [19:0]gt0_rxdata_out; wire gt0_rxdfelfhold_i; wire gt0_rxdfelpmreset_in; wire gt0_rxdlysreset_i; wire gt0_rxdlysresetdone_i; wire [6:0]gt0_rxmonitorout_out; wire [1:0]gt0_rxmonitorsel_in; wire gt0_rxoutclk_out; wire gt0_rxoutclkfabric_out; wire [1:0]gt0_rxpd_in; wire gt0_rxphaligndone_i; wire [4:0]gt0_rxphmonitor_out; wire [4:0]gt0_rxphslipmonitor_out; wire gt0_rxpmareset_in; wire gt0_rxpolarity_in; wire gt0_rxresetdone_out; wire gt0_rxresetfsm_i_n_4; wire gt0_rxresetfsm_i_n_5; wire gt0_rxslide_in; wire gt0_rxuserrdy_t; wire gt0_rxusrclk2_in; wire gt0_rxusrclk_in; wire gt0_tx_phalignment_done_i; wire [19:0]gt0_txdata_in; wire [3:0]gt0_txdiffctrl_in; wire gt0_txdlysreset_i; wire gt0_txdlysresetdone_i; wire gt0_txelecidle_in; wire gt0_txoutclk_out; wire gt0_txoutclkfabric_out; wire gt0_txoutclkpcs_out; wire [1:0]gt0_txpd_in; wire gt0_txphaligndone_i; wire gt0_txpolarity_in; wire [4:0]gt0_txpostcursor_in; wire [4:0]gt0_txprecursor_in; wire gt0_txresetdone_out; wire gt0_txresetfsm_i_n_4; wire gt0_txuserrdy_t; wire gt0_txusrclk2_in; wire gt0_txusrclk_in; wire [10:1]p_0_in; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_AUTO_PHASE_ALIGN gt0_rx_auto_phase_align_i (.PHASE_ALIGNMENT_DONE_reg_0(GT0_RX_FSM_RESET_DONE_OUT), .SR(gt0_rxresetfsm_i_n_4), .SYSCLK_IN(SYSCLK_IN), .\count_phalign_edges_reg[1]_0 (gt0_rx_cdrlocked_reg_n_0), .data_in(gt0_rxphaligndone_i), .data_sync_reg1(gt0_rxdlysresetdone_i), .gt0_run_rx_phalignment_i(gt0_run_rx_phalignment_i), .gt0_rxdlysreset_i(gt0_rxdlysreset_i)); (* SOFT_HLUTNM = "soft_lutpair34" *) LUT1 #( .INIT(2'h1)) \gt0_rx_cdrlock_counter[0]_i_1 (.I0(gt0_rx_cdrlock_counter_reg__0[0]), .O(\gt0_rx_cdrlock_counter[0]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFEFF)) \gt0_rx_cdrlock_counter[10]_i_1 (.I0(gt0_rx_cdrlock_counter_reg__0[1]), .I1(gt0_rx_cdrlock_counter_reg__0[2]), .I2(\gt0_rx_cdrlock_counter[10]_i_3_n_0 ), .I3(gt0_rx_cdrlock_counter_reg__0[4]), .I4(gt0_rx_cdrlock_counter_reg__0[3]), .I5(gt0_rx_cdrlock_counter_reg__0[0]), .O(gt0_rx_cdrlock_counter)); LUT6 #( .INIT(64'hF7FFFFFF08000000)) \gt0_rx_cdrlock_counter[10]_i_2 (.I0(gt0_rx_cdrlock_counter_reg__0[9]), .I1(gt0_rx_cdrlock_counter_reg__0[7]), .I2(\gt0_rx_cdrlock_counter[10]_i_4_n_0 ), .I3(gt0_rx_cdrlock_counter_reg__0[6]), .I4(gt0_rx_cdrlock_counter_reg__0[8]), .I5(gt0_rx_cdrlock_counter_reg__0[10]), .O(p_0_in[10])); LUT6 #( .INIT(64'hFFFF7FFFFFFFFFFF)) \gt0_rx_cdrlock_counter[10]_i_3 (.I0(gt0_rx_cdrlock_counter_reg__0[9]), .I1(gt0_rx_cdrlock_counter_reg__0[10]), .I2(gt0_rx_cdrlock_counter_reg__0[7]), .I3(gt0_rx_cdrlock_counter_reg__0[8]), .I4(gt0_rx_cdrlock_counter_reg__0[5]), .I5(gt0_rx_cdrlock_counter_reg__0[6]), .O(\gt0_rx_cdrlock_counter[10]_i_3_n_0 )); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) \gt0_rx_cdrlock_counter[10]_i_4 (.I0(gt0_rx_cdrlock_counter_reg__0[4]), .I1(gt0_rx_cdrlock_counter_reg__0[2]), .I2(gt0_rx_cdrlock_counter_reg__0[0]), .I3(gt0_rx_cdrlock_counter_reg__0[1]), .I4(gt0_rx_cdrlock_counter_reg__0[3]), .I5(gt0_rx_cdrlock_counter_reg__0[5]), .O(\gt0_rx_cdrlock_counter[10]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair34" *) LUT2 #( .INIT(4'h6)) \gt0_rx_cdrlock_counter[1]_i_1 (.I0(gt0_rx_cdrlock_counter_reg__0[0]), .I1(gt0_rx_cdrlock_counter_reg__0[1]), .O(p_0_in[1])); (* SOFT_HLUTNM = "soft_lutpair32" *) LUT3 #( .INIT(8'h78)) \gt0_rx_cdrlock_counter[2]_i_1 (.I0(gt0_rx_cdrlock_counter_reg__0[1]), .I1(gt0_rx_cdrlock_counter_reg__0[0]), .I2(gt0_rx_cdrlock_counter_reg__0[2]), .O(p_0_in[2])); (* SOFT_HLUTNM = "soft_lutpair32" *) LUT4 #( .INIT(16'h7F80)) \gt0_rx_cdrlock_counter[3]_i_1 (.I0(gt0_rx_cdrlock_counter_reg__0[2]), .I1(gt0_rx_cdrlock_counter_reg__0[0]), .I2(gt0_rx_cdrlock_counter_reg__0[1]), .I3(gt0_rx_cdrlock_counter_reg__0[3]), .O(p_0_in[3])); (* SOFT_HLUTNM = "soft_lutpair31" *) LUT5 #( .INIT(32'h7FFF8000)) \gt0_rx_cdrlock_counter[4]_i_1 (.I0(gt0_rx_cdrlock_counter_reg__0[3]), .I1(gt0_rx_cdrlock_counter_reg__0[1]), .I2(gt0_rx_cdrlock_counter_reg__0[0]), .I3(gt0_rx_cdrlock_counter_reg__0[2]), .I4(gt0_rx_cdrlock_counter_reg__0[4]), .O(p_0_in[4])); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \gt0_rx_cdrlock_counter[5]_i_1 (.I0(gt0_rx_cdrlock_counter_reg__0[4]), .I1(gt0_rx_cdrlock_counter_reg__0[2]), .I2(gt0_rx_cdrlock_counter_reg__0[0]), .I3(gt0_rx_cdrlock_counter_reg__0[1]), .I4(gt0_rx_cdrlock_counter_reg__0[3]), .I5(gt0_rx_cdrlock_counter_reg__0[5]), .O(p_0_in[5])); (* SOFT_HLUTNM = "soft_lutpair33" *) LUT2 #( .INIT(4'h9)) \gt0_rx_cdrlock_counter[6]_i_1 (.I0(\gt0_rx_cdrlock_counter[10]_i_4_n_0 ), .I1(gt0_rx_cdrlock_counter_reg__0[6]), .O(p_0_in[6])); (* SOFT_HLUTNM = "soft_lutpair33" *) LUT3 #( .INIT(8'hD2)) \gt0_rx_cdrlock_counter[7]_i_1 (.I0(gt0_rx_cdrlock_counter_reg__0[6]), .I1(\gt0_rx_cdrlock_counter[10]_i_4_n_0 ), .I2(gt0_rx_cdrlock_counter_reg__0[7]), .O(p_0_in[7])); (* SOFT_HLUTNM = "soft_lutpair30" *) LUT4 #( .INIT(16'hDF20)) \gt0_rx_cdrlock_counter[8]_i_1 (.I0(gt0_rx_cdrlock_counter_reg__0[7]), .I1(\gt0_rx_cdrlock_counter[10]_i_4_n_0 ), .I2(gt0_rx_cdrlock_counter_reg__0[6]), .I3(gt0_rx_cdrlock_counter_reg__0[8]), .O(p_0_in[8])); (* SOFT_HLUTNM = "soft_lutpair30" *) LUT5 #( .INIT(32'hF7FF0800)) \gt0_rx_cdrlock_counter[9]_i_1 (.I0(gt0_rx_cdrlock_counter_reg__0[8]), .I1(gt0_rx_cdrlock_counter_reg__0[6]), .I2(\gt0_rx_cdrlock_counter[10]_i_4_n_0 ), .I3(gt0_rx_cdrlock_counter_reg__0[7]), .I4(gt0_rx_cdrlock_counter_reg__0[9]), .O(p_0_in[9])); FDRE #( .INIT(1'b0)) \gt0_rx_cdrlock_counter_reg[0] (.C(SYSCLK_IN), .CE(gt0_rx_cdrlock_counter), .D(\gt0_rx_cdrlock_counter[0]_i_1_n_0 ), .Q(gt0_rx_cdrlock_counter_reg__0[0]), .R(gt0_gtrxreset_t)); FDRE #( .INIT(1'b0)) \gt0_rx_cdrlock_counter_reg[10] (.C(SYSCLK_IN), .CE(gt0_rx_cdrlock_counter), .D(p_0_in[10]), .Q(gt0_rx_cdrlock_counter_reg__0[10]), .R(gt0_gtrxreset_t)); FDRE #( .INIT(1'b0)) \gt0_rx_cdrlock_counter_reg[1] (.C(SYSCLK_IN), .CE(gt0_rx_cdrlock_counter), .D(p_0_in[1]), .Q(gt0_rx_cdrlock_counter_reg__0[1]), .R(gt0_gtrxreset_t)); FDRE #( .INIT(1'b0)) \gt0_rx_cdrlock_counter_reg[2] (.C(SYSCLK_IN), .CE(gt0_rx_cdrlock_counter), .D(p_0_in[2]), .Q(gt0_rx_cdrlock_counter_reg__0[2]), .R(gt0_gtrxreset_t)); FDRE #( .INIT(1'b0)) \gt0_rx_cdrlock_counter_reg[3] (.C(SYSCLK_IN), .CE(gt0_rx_cdrlock_counter), .D(p_0_in[3]), .Q(gt0_rx_cdrlock_counter_reg__0[3]), .R(gt0_gtrxreset_t)); FDRE #( .INIT(1'b0)) \gt0_rx_cdrlock_counter_reg[4] (.C(SYSCLK_IN), .CE(gt0_rx_cdrlock_counter), .D(p_0_in[4]), .Q(gt0_rx_cdrlock_counter_reg__0[4]), .R(gt0_gtrxreset_t)); FDRE #( .INIT(1'b0)) \gt0_rx_cdrlock_counter_reg[5] (.C(SYSCLK_IN), .CE(gt0_rx_cdrlock_counter), .D(p_0_in[5]), .Q(gt0_rx_cdrlock_counter_reg__0[5]), .R(gt0_gtrxreset_t)); FDRE #( .INIT(1'b0)) \gt0_rx_cdrlock_counter_reg[6] (.C(SYSCLK_IN), .CE(gt0_rx_cdrlock_counter), .D(p_0_in[6]), .Q(gt0_rx_cdrlock_counter_reg__0[6]), .R(gt0_gtrxreset_t)); FDRE #( .INIT(1'b0)) \gt0_rx_cdrlock_counter_reg[7] (.C(SYSCLK_IN), .CE(gt0_rx_cdrlock_counter), .D(p_0_in[7]), .Q(gt0_rx_cdrlock_counter_reg__0[7]), .R(gt0_gtrxreset_t)); FDRE #( .INIT(1'b0)) \gt0_rx_cdrlock_counter_reg[8] (.C(SYSCLK_IN), .CE(gt0_rx_cdrlock_counter), .D(p_0_in[8]), .Q(gt0_rx_cdrlock_counter_reg__0[8]), .R(gt0_gtrxreset_t)); FDRE #( .INIT(1'b0)) \gt0_rx_cdrlock_counter_reg[9] (.C(SYSCLK_IN), .CE(gt0_rx_cdrlock_counter), .D(p_0_in[9]), .Q(gt0_rx_cdrlock_counter_reg__0[9]), .R(gt0_gtrxreset_t)); (* SOFT_HLUTNM = "soft_lutpair31" *) LUT5 #( .INIT(32'h00010000)) gt0_rx_cdrlocked_i_2 (.I0(gt0_rx_cdrlock_counter_reg__0[0]), .I1(gt0_rx_cdrlock_counter_reg__0[1]), .I2(gt0_rx_cdrlock_counter_reg__0[2]), .I3(gt0_rx_cdrlock_counter_reg__0[3]), .I4(gt0_rx_cdrlock_counter_reg__0[4]), .O(gt0_rx_cdrlocked_i_2_n_0)); LUT6 #( .INIT(64'h0080000000000000)) gt0_rx_cdrlocked_i_3 (.I0(gt0_rx_cdrlock_counter_reg__0[7]), .I1(gt0_rx_cdrlock_counter_reg__0[8]), .I2(gt0_rx_cdrlock_counter_reg__0[6]), .I3(gt0_rx_cdrlock_counter_reg__0[5]), .I4(gt0_rx_cdrlock_counter_reg__0[10]), .I5(gt0_rx_cdrlock_counter_reg__0[9]), .O(gt0_rx_cdrlocked_i_3_n_0)); FDRE gt0_rx_cdrlocked_reg (.C(SYSCLK_IN), .CE(1'b1), .D(gt0_rxresetfsm_i_n_5), .Q(gt0_rx_cdrlocked_reg_n_0), .R(1'b0)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_RX_STARTUP_FSM gt0_rxresetfsm_i (.DONT_RESET_ON_DATA_ERROR_IN(DONT_RESET_ON_DATA_ERROR_IN), .\FSM_onehot_phalign_state_reg[0] (gt0_rx_cdrlocked_reg_n_0), .GT0_DATA_VALID_IN(GT0_DATA_VALID_IN), .GT0_RX_FSM_RESET_DONE_OUT(GT0_RX_FSM_RESET_DONE_OUT), .SOFT_RESET_RX_IN(SOFT_RESET_RX_IN), .SR(gt0_gtrxreset_t), .SYSCLK_IN(SYSCLK_IN), .gt0_cplllock_out(gt0_cplllock_out), .gt0_run_rx_phalignment_i(gt0_run_rx_phalignment_i), .gt0_rx_cdrlocked_reg(gt0_rxresetfsm_i_n_5), .gt0_rx_cdrlocked_reg_0(gt0_rx_cdrlocked_i_2_n_0), .gt0_rx_cdrlocked_reg_1(gt0_rx_cdrlocked_i_3_n_0), .gt0_rxdfelfhold_i(gt0_rxdfelfhold_i), .gt0_rxresetdone_out(gt0_rxresetdone_out), .gt0_rxuserrdy_t(gt0_rxuserrdy_t), .gt0_rxusrclk_in(gt0_rxusrclk_in), .run_phase_alignment_int_reg_0(gt0_rxresetfsm_i_n_4)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_AUTO_PHASE_ALIGN_0 gt0_tx_auto_phase_align_i (.PHASE_ALIGNMENT_DONE_reg_0(gt0_txresetfsm_i_n_4), .SYSCLK_IN(SYSCLK_IN), .data_in(gt0_txphaligndone_i), .data_sync_reg1(gt0_txdlysresetdone_i), .gt0_tx_phalignment_done_i(gt0_tx_phalignment_done_i), .gt0_txdlysreset_i(gt0_txdlysreset_i)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_TX_STARTUP_FSM gt0_txresetfsm_i (.GT0_TX_FSM_RESET_DONE_OUT(GT0_TX_FSM_RESET_DONE_OUT), .SOFT_RESET_TX_IN(SOFT_RESET_TX_IN), .SYSCLK_IN(SYSCLK_IN), .gt0_cplllock_out(gt0_cplllock_out), .gt0_cpllrefclklost_i(gt0_cpllrefclklost_i), .gt0_cpllreset_t(gt0_cpllreset_t), .gt0_gttxreset_t(gt0_gttxreset_t), .gt0_tx_phalignment_done_i(gt0_tx_phalignment_done_i), .gt0_txresetdone_out(gt0_txresetdone_out), .gt0_txuserrdy_t(gt0_txuserrdy_t), .gt0_txusrclk_in(gt0_txusrclk_in), .run_phase_alignment_int_reg_0(gt0_txresetfsm_i_n_4)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_multi_gt ngFEC_mgt_i (.GT0_QPLLOUTCLK_IN(GT0_QPLLOUTCLK_IN), .GT0_QPLLOUTREFCLK_IN(GT0_QPLLOUTREFCLK_IN), .SR(gt0_gtrxreset_t), .data_in(gt0_rxphaligndone_i), .gt0_cpllfbclklost_out(gt0_cpllfbclklost_out), .gt0_cplllock_out(gt0_cplllock_out), .gt0_cplllockdetclk_in(gt0_cplllockdetclk_in), .gt0_cplllockdetclk_in_0(gt0_rxdlysresetdone_i), .gt0_cplllockdetclk_in_1(gt0_txdlysresetdone_i), .gt0_cplllockdetclk_in_2(gt0_txphaligndone_i), .gt0_cpllpd_in(gt0_cpllpd_in), .gt0_cpllrefclklost_i(gt0_cpllrefclklost_i), .gt0_cpllreset_t(gt0_cpllreset_t), .gt0_dmonitorout_out(gt0_dmonitorout_out), .gt0_drpaddr_in(gt0_drpaddr_in), .gt0_drpclk_in(gt0_drpclk_in), .gt0_drpdi_in(gt0_drpdi_in), .gt0_drpdo_out(gt0_drpdo_out), .gt0_drpen_in(gt0_drpen_in), .gt0_drprdy_out(gt0_drprdy_out), .gt0_drpwe_in(gt0_drpwe_in), .gt0_eyescandataerror_out(gt0_eyescandataerror_out), .gt0_eyescanreset_in(gt0_eyescanreset_in), .gt0_eyescantrigger_in(gt0_eyescantrigger_in), .gt0_gtrefclk0_in(gt0_gtrefclk0_in), .gt0_gtrefclk1_in(gt0_gtrefclk1_in), .gt0_gttxreset_t(gt0_gttxreset_t), .gt0_gtxrxn_in(gt0_gtxrxn_in), .gt0_gtxrxp_in(gt0_gtxrxp_in), .gt0_gtxtxn_out(gt0_gtxtxn_out), .gt0_gtxtxp_out(gt0_gtxtxp_out), .gt0_loopback_in(gt0_loopback_in), .gt0_rxdata_out(gt0_rxdata_out), .gt0_rxdfelfhold_i(gt0_rxdfelfhold_i), .gt0_rxdfelpmreset_in(gt0_rxdfelpmreset_in), .gt0_rxdlysreset_i(gt0_rxdlysreset_i), .gt0_rxmonitorout_out(gt0_rxmonitorout_out), .gt0_rxmonitorsel_in(gt0_rxmonitorsel_in), .gt0_rxoutclk_out(gt0_rxoutclk_out), .gt0_rxoutclkfabric_out(gt0_rxoutclkfabric_out), .gt0_rxpd_in(gt0_rxpd_in), .gt0_rxphmonitor_out(gt0_rxphmonitor_out), .gt0_rxphslipmonitor_out(gt0_rxphslipmonitor_out), .gt0_rxpmareset_in(gt0_rxpmareset_in), .gt0_rxpolarity_in(gt0_rxpolarity_in), .gt0_rxresetdone_out(gt0_rxresetdone_out), .gt0_rxslide_in(gt0_rxslide_in), .gt0_rxuserrdy_t(gt0_rxuserrdy_t), .gt0_rxusrclk2_in(gt0_rxusrclk2_in), .gt0_rxusrclk_in(gt0_rxusrclk_in), .gt0_txdata_in(gt0_txdata_in), .gt0_txdiffctrl_in(gt0_txdiffctrl_in), .gt0_txdlysreset_i(gt0_txdlysreset_i), .gt0_txelecidle_in(gt0_txelecidle_in), .gt0_txoutclk_out(gt0_txoutclk_out), .gt0_txoutclkfabric_out(gt0_txoutclkfabric_out), .gt0_txoutclkpcs_out(gt0_txoutclkpcs_out), .gt0_txpd_in(gt0_txpd_in), .gt0_txpolarity_in(gt0_txpolarity_in), .gt0_txpostcursor_in(gt0_txpostcursor_in), .gt0_txprecursor_in(gt0_txprecursor_in), .gt0_txresetdone_out(gt0_txresetdone_out), .gt0_txuserrdy_t(gt0_txuserrdy_t), .gt0_txusrclk2_in(gt0_txusrclk2_in), .gt0_txusrclk_in(gt0_txusrclk_in)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_multi_gt (gt0_cpllfbclklost_out, gt0_cplllock_out, gt0_cpllrefclklost_i, gt0_drprdy_out, gt0_eyescandataerror_out, gt0_gtxtxn_out, gt0_gtxtxp_out, gt0_cplllockdetclk_in_0, gt0_rxoutclk_out, gt0_rxoutclkfabric_out, data_in, gt0_rxresetdone_out, gt0_cplllockdetclk_in_1, gt0_txoutclk_out, gt0_txoutclkfabric_out, gt0_txoutclkpcs_out, gt0_cplllockdetclk_in_2, gt0_txresetdone_out, gt0_drpdo_out, gt0_rxphmonitor_out, gt0_rxphslipmonitor_out, gt0_rxdata_out, gt0_rxmonitorout_out, gt0_dmonitorout_out, gt0_cplllockdetclk_in, gt0_drpclk_in, gt0_drpen_in, gt0_drpwe_in, gt0_eyescanreset_in, gt0_eyescantrigger_in, gt0_gtrefclk0_in, gt0_gtrefclk1_in, SR, gt0_gttxreset_t, gt0_gtxrxn_in, gt0_gtxrxp_in, GT0_QPLLOUTCLK_IN, GT0_QPLLOUTREFCLK_IN, gt0_rxdfelfhold_i, gt0_rxdfelpmreset_in, gt0_rxdlysreset_i, gt0_rxpmareset_in, gt0_rxpolarity_in, gt0_rxslide_in, gt0_rxuserrdy_t, gt0_rxusrclk_in, gt0_rxusrclk2_in, gt0_txdlysreset_i, gt0_txelecidle_in, gt0_txpolarity_in, gt0_txuserrdy_t, gt0_txusrclk_in, gt0_txusrclk2_in, gt0_drpdi_in, gt0_rxmonitorsel_in, gt0_rxpd_in, gt0_txpd_in, gt0_loopback_in, gt0_txdiffctrl_in, gt0_txpostcursor_in, gt0_txprecursor_in, gt0_txdata_in, gt0_drpaddr_in, gt0_cpllpd_in, gt0_cpllreset_t); output gt0_cpllfbclklost_out; output gt0_cplllock_out; output gt0_cpllrefclklost_i; output gt0_drprdy_out; output gt0_eyescandataerror_out; output gt0_gtxtxn_out; output gt0_gtxtxp_out; output gt0_cplllockdetclk_in_0; output gt0_rxoutclk_out; output gt0_rxoutclkfabric_out; output data_in; output gt0_rxresetdone_out; output gt0_cplllockdetclk_in_1; output gt0_txoutclk_out; output gt0_txoutclkfabric_out; output gt0_txoutclkpcs_out; output gt0_cplllockdetclk_in_2; output gt0_txresetdone_out; output [15:0]gt0_drpdo_out; output [4:0]gt0_rxphmonitor_out; output [4:0]gt0_rxphslipmonitor_out; output [19:0]gt0_rxdata_out; output [6:0]gt0_rxmonitorout_out; output [7:0]gt0_dmonitorout_out; input gt0_cplllockdetclk_in; input gt0_drpclk_in; input gt0_drpen_in; input gt0_drpwe_in; input gt0_eyescanreset_in; input gt0_eyescantrigger_in; input gt0_gtrefclk0_in; input gt0_gtrefclk1_in; input [0:0]SR; input gt0_gttxreset_t; input gt0_gtxrxn_in; input gt0_gtxrxp_in; input GT0_QPLLOUTCLK_IN; input GT0_QPLLOUTREFCLK_IN; input gt0_rxdfelfhold_i; input gt0_rxdfelpmreset_in; input gt0_rxdlysreset_i; input gt0_rxpmareset_in; input gt0_rxpolarity_in; input gt0_rxslide_in; input gt0_rxuserrdy_t; input gt0_rxusrclk_in; input gt0_rxusrclk2_in; input gt0_txdlysreset_i; input gt0_txelecidle_in; input gt0_txpolarity_in; input gt0_txuserrdy_t; input gt0_txusrclk_in; input gt0_txusrclk2_in; input [15:0]gt0_drpdi_in; input [1:0]gt0_rxmonitorsel_in; input [1:0]gt0_rxpd_in; input [1:0]gt0_txpd_in; input [2:0]gt0_loopback_in; input [3:0]gt0_txdiffctrl_in; input [4:0]gt0_txpostcursor_in; input [4:0]gt0_txprecursor_in; input [19:0]gt0_txdata_in; input [8:0]gt0_drpaddr_in; input gt0_cpllpd_in; input gt0_cpllreset_t; wire GT0_QPLLOUTCLK_IN; wire GT0_QPLLOUTREFCLK_IN; wire [0:0]SR; wire cpllpd_in; wire cpllreset_in; wire data_in; wire gt0_cpllfbclklost_out; wire gt0_cplllock_out; wire gt0_cplllockdetclk_in; wire gt0_cplllockdetclk_in_0; wire gt0_cplllockdetclk_in_1; wire gt0_cplllockdetclk_in_2; wire gt0_cpllpd_in; wire gt0_cpllrefclklost_i; wire gt0_cpllreset_t; wire [7:0]gt0_dmonitorout_out; wire [8:0]gt0_drpaddr_in; wire gt0_drpclk_in; wire [15:0]gt0_drpdi_in; wire [15:0]gt0_drpdo_out; wire gt0_drpen_in; wire gt0_drprdy_out; wire gt0_drpwe_in; wire gt0_eyescandataerror_out; wire gt0_eyescanreset_in; wire gt0_eyescantrigger_in; wire gt0_gtrefclk0_in; wire gt0_gtrefclk1_in; wire gt0_gttxreset_t; wire gt0_gtxrxn_in; wire gt0_gtxrxp_in; wire gt0_gtxtxn_out; wire gt0_gtxtxp_out; wire [2:0]gt0_loopback_in; wire [19:0]gt0_rxdata_out; wire gt0_rxdfelfhold_i; wire gt0_rxdfelpmreset_in; wire gt0_rxdlysreset_i; wire [6:0]gt0_rxmonitorout_out; wire [1:0]gt0_rxmonitorsel_in; wire gt0_rxoutclk_out; wire gt0_rxoutclkfabric_out; wire [1:0]gt0_rxpd_in; wire [4:0]gt0_rxphmonitor_out; wire [4:0]gt0_rxphslipmonitor_out; wire gt0_rxpmareset_in; wire gt0_rxpolarity_in; wire gt0_rxresetdone_out; wire gt0_rxslide_in; wire gt0_rxuserrdy_t; wire gt0_rxusrclk2_in; wire gt0_rxusrclk_in; wire [19:0]gt0_txdata_in; wire [3:0]gt0_txdiffctrl_in; wire gt0_txdlysreset_i; wire gt0_txelecidle_in; wire gt0_txoutclk_out; wire gt0_txoutclkfabric_out; wire gt0_txoutclkpcs_out; wire [1:0]gt0_txpd_in; wire gt0_txpolarity_in; wire [4:0]gt0_txpostcursor_in; wire [4:0]gt0_txprecursor_in; wire gt0_txresetdone_out; wire gt0_txuserrdy_t; wire gt0_txusrclk2_in; wire gt0_txusrclk_in; decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_cpll_railing cpll_railing0_i (.cpllpd_in(cpllpd_in), .cpllreset_in(cpllreset_in), .gt0_cpllpd_in(gt0_cpllpd_in), .gt0_cpllreset_t(gt0_cpllreset_t), .gt0_gtrefclk1_in(gt0_gtrefclk1_in)); decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_GT gt0_ngFEC_mgt_i (.GT0_QPLLOUTCLK_IN(GT0_QPLLOUTCLK_IN), .GT0_QPLLOUTREFCLK_IN(GT0_QPLLOUTREFCLK_IN), .SR(SR), .cpllpd_in(cpllpd_in), .cpllreset_in(cpllreset_in), .data_in(data_in), .gt0_cpllfbclklost_out(gt0_cpllfbclklost_out), .gt0_cplllock_out(gt0_cplllock_out), .gt0_cplllockdetclk_in(gt0_cplllockdetclk_in), .gt0_cplllockdetclk_in_0(gt0_cplllockdetclk_in_0), .gt0_cplllockdetclk_in_1(gt0_cplllockdetclk_in_1), .gt0_cplllockdetclk_in_2(gt0_cplllockdetclk_in_2), .gt0_cpllrefclklost_i(gt0_cpllrefclklost_i), .gt0_dmonitorout_out(gt0_dmonitorout_out), .gt0_drpaddr_in(gt0_drpaddr_in), .gt0_drpclk_in(gt0_drpclk_in), .gt0_drpdi_in(gt0_drpdi_in), .gt0_drpdo_out(gt0_drpdo_out), .gt0_drpen_in(gt0_drpen_in), .gt0_drprdy_out(gt0_drprdy_out), .gt0_drpwe_in(gt0_drpwe_in), .gt0_eyescandataerror_out(gt0_eyescandataerror_out), .gt0_eyescanreset_in(gt0_eyescanreset_in), .gt0_eyescantrigger_in(gt0_eyescantrigger_in), .gt0_gtrefclk0_in(gt0_gtrefclk0_in), .gt0_gtrefclk1_in(gt0_gtrefclk1_in), .gt0_gttxreset_t(gt0_gttxreset_t), .gt0_gtxrxn_in(gt0_gtxrxn_in), .gt0_gtxrxp_in(gt0_gtxrxp_in), .gt0_gtxtxn_out(gt0_gtxtxn_out), .gt0_gtxtxp_out(gt0_gtxtxp_out), .gt0_loopback_in(gt0_loopback_in), .gt0_rxdata_out(gt0_rxdata_out), .gt0_rxdfelfhold_i(gt0_rxdfelfhold_i), .gt0_rxdfelpmreset_in(gt0_rxdfelpmreset_in), .gt0_rxdlysreset_i(gt0_rxdlysreset_i), .gt0_rxmonitorout_out(gt0_rxmonitorout_out), .gt0_rxmonitorsel_in(gt0_rxmonitorsel_in), .gt0_rxoutclk_out(gt0_rxoutclk_out), .gt0_rxoutclkfabric_out(gt0_rxoutclkfabric_out), .gt0_rxpd_in(gt0_rxpd_in), .gt0_rxphmonitor_out(gt0_rxphmonitor_out), .gt0_rxphslipmonitor_out(gt0_rxphslipmonitor_out), .gt0_rxpmareset_in(gt0_rxpmareset_in), .gt0_rxpolarity_in(gt0_rxpolarity_in), .gt0_rxresetdone_out(gt0_rxresetdone_out), .gt0_rxslide_in(gt0_rxslide_in), .gt0_rxuserrdy_t(gt0_rxuserrdy_t), .gt0_rxusrclk2_in(gt0_rxusrclk2_in), .gt0_rxusrclk_in(gt0_rxusrclk_in), .gt0_txdata_in(gt0_txdata_in), .gt0_txdiffctrl_in(gt0_txdiffctrl_in), .gt0_txdlysreset_i(gt0_txdlysreset_i), .gt0_txelecidle_in(gt0_txelecidle_in), .gt0_txoutclk_out(gt0_txoutclk_out), .gt0_txoutclkfabric_out(gt0_txoutclkfabric_out), .gt0_txoutclkpcs_out(gt0_txoutclkpcs_out), .gt0_txpd_in(gt0_txpd_in), .gt0_txpolarity_in(gt0_txpolarity_in), .gt0_txpostcursor_in(gt0_txpostcursor_in), .gt0_txprecursor_in(gt0_txprecursor_in), .gt0_txresetdone_out(gt0_txresetdone_out), .gt0_txuserrdy_t(gt0_txuserrdy_t), .gt0_txusrclk2_in(gt0_txusrclk2_in), .gt0_txusrclk_in(gt0_txusrclk_in)); endmodule module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_sync_block (E, reset_time_out_reg, \FSM_sequential_tx_state_reg[0] , \FSM_sequential_tx_state_reg[0]_0 , init_wait_done, \FSM_sequential_tx_state_reg[0]_1 , \FSM_sequential_tx_state_reg[0]_2 , Q, mmcm_lock_reclocked, \FSM_sequential_tx_state_reg[0]_3 , \FSM_sequential_tx_state_reg[0]_4 , \FSM_sequential_tx_state_reg[0]_5 , reset_time_out_reg_0, reset_time_out, gt0_cplllock_out, SYSCLK_IN); output [0:0]E; output reset_time_out_reg; input \FSM_sequential_tx_state_reg[0] ; input \FSM_sequential_tx_state_reg[0]_0 ; input init_wait_done; input \FSM_sequential_tx_state_reg[0]_1 ; input \FSM_sequential_tx_state_reg[0]_2 ; input [3:0]Q; input mmcm_lock_reclocked; input \FSM_sequential_tx_state_reg[0]_3 ; input \FSM_sequential_tx_state_reg[0]_4 ; input \FSM_sequential_tx_state_reg[0]_5 ; input reset_time_out_reg_0; input reset_time_out; input gt0_cplllock_out; input SYSCLK_IN; wire [0:0]E; wire \FSM_sequential_tx_state[3]_i_4_n_0 ; wire \FSM_sequential_tx_state_reg[0] ; wire \FSM_sequential_tx_state_reg[0]_0 ; wire \FSM_sequential_tx_state_reg[0]_1 ; wire \FSM_sequential_tx_state_reg[0]_2 ; wire \FSM_sequential_tx_state_reg[0]_3 ; wire \FSM_sequential_tx_state_reg[0]_4 ; wire \FSM_sequential_tx_state_reg[0]_5 ; wire [3:0]Q; wire SYSCLK_IN; wire cplllock_sync; wire data_sync1; wire data_sync2; wire data_sync3; wire data_sync4; wire data_sync5; wire gt0_cplllock_out; wire init_wait_done; wire mmcm_lock_reclocked; wire reset_time_out; wire reset_time_out_i_3__0_n_0; wire reset_time_out_i_4__0_n_0; wire reset_time_out_reg; wire reset_time_out_reg_0; LUT6 #( .INIT(64'hFFFFFFFFEEEEEFEE)) \FSM_sequential_tx_state[3]_i_1 (.I0(\FSM_sequential_tx_state_reg[0] ), .I1(\FSM_sequential_tx_state[3]_i_4_n_0 ), .I2(\FSM_sequential_tx_state_reg[0]_0 ), .I3(init_wait_done), .I4(\FSM_sequential_tx_state_reg[0]_1 ), .I5(\FSM_sequential_tx_state_reg[0]_2 ), .O(E)); LUT6 #( .INIT(64'h0000FF0400000A04)) \FSM_sequential_tx_state[3]_i_4 (.I0(cplllock_sync), .I1(\FSM_sequential_tx_state_reg[0]_3 ), .I2(Q[2]), .I3(Q[1]), .I4(\FSM_sequential_tx_state_reg[0]_4 ), .I5(\FSM_sequential_tx_state_reg[0]_5 ), .O(\FSM_sequential_tx_state[3]_i_4_n_0 )); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg1 (.C(SYSCLK_IN), .CE(1'b1), .D(gt0_cplllock_out), .Q(data_sync1), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg2 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync1), .Q(data_sync2), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg3 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync2), .Q(data_sync3), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg4 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync3), .Q(data_sync4), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg5 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync4), .Q(data_sync5), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg6 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync5), .Q(cplllock_sync), .R(1'b0)); LUT4 #( .INIT(16'hEFE0)) reset_time_out_i_1 (.I0(reset_time_out_reg_0), .I1(reset_time_out_i_3__0_n_0), .I2(reset_time_out_i_4__0_n_0), .I3(reset_time_out), .O(reset_time_out_reg)); LUT6 #( .INIT(64'h020002000F000200)) reset_time_out_i_3__0 (.I0(mmcm_lock_reclocked), .I1(Q[1]), .I2(Q[3]), .I3(Q[0]), .I4(cplllock_sync), .I5(Q[2]), .O(reset_time_out_i_3__0_n_0)); LUT6 #( .INIT(64'h0000FF005555F544)) reset_time_out_i_4__0 (.I0(Q[1]), .I1(init_wait_done), .I2(cplllock_sync), .I3(Q[0]), .I4(Q[3]), .I5(Q[2]), .O(reset_time_out_i_4__0_n_0)); endmodule (* ORIG_REF_NAME = "ngFEC_mgt_sync_block" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_sync_block_1 (data_out, gt0_txresetdone_out, SYSCLK_IN); output data_out; input gt0_txresetdone_out; input SYSCLK_IN; wire SYSCLK_IN; wire data_out; wire data_sync1; wire data_sync2; wire data_sync3; wire data_sync4; wire data_sync5; wire gt0_txresetdone_out; (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg1 (.C(SYSCLK_IN), .CE(1'b1), .D(gt0_txresetdone_out), .Q(data_sync1), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg2 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync1), .Q(data_sync2), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg3 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync2), .Q(data_sync3), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg4 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync3), .Q(data_sync4), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg5 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync4), .Q(data_sync5), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg6 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync5), .Q(data_out), .R(1'b0)); endmodule (* ORIG_REF_NAME = "ngFEC_mgt_sync_block" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_sync_block_10 (E, D, DONT_RESET_ON_DATA_ERROR_IN_0, \FSM_sequential_rx_state_reg[3] , \FSM_sequential_rx_state_reg[0] , \FSM_sequential_rx_state_reg[0]_0 , \FSM_sequential_rx_state_reg[0]_1 , \FSM_sequential_rx_state_reg[0]_2 , Q, mmcm_lock_reclocked, GT0_RX_FSM_RESET_DONE_OUT, \FSM_sequential_rx_state_reg[1] , reset_time_out_reg, \FSM_sequential_rx_state_reg[0]_3 , time_out_wait_bypass_s3, \FSM_sequential_rx_state_reg[3]_0 , DONT_RESET_ON_DATA_ERROR_IN, \FSM_sequential_rx_state_reg[0]_4 , \FSM_sequential_rx_state_reg[0]_5 , reset_time_out_reg_0, reset_time_out_reg_1, reset_time_out_reg_2, GT0_DATA_VALID_IN, SYSCLK_IN); output [0:0]E; output [2:0]D; output DONT_RESET_ON_DATA_ERROR_IN_0; output \FSM_sequential_rx_state_reg[3] ; input \FSM_sequential_rx_state_reg[0] ; input \FSM_sequential_rx_state_reg[0]_0 ; input \FSM_sequential_rx_state_reg[0]_1 ; input \FSM_sequential_rx_state_reg[0]_2 ; input [2:0]Q; input mmcm_lock_reclocked; input GT0_RX_FSM_RESET_DONE_OUT; input \FSM_sequential_rx_state_reg[1] ; input reset_time_out_reg; input \FSM_sequential_rx_state_reg[0]_3 ; input time_out_wait_bypass_s3; input \FSM_sequential_rx_state_reg[3]_0 ; input DONT_RESET_ON_DATA_ERROR_IN; input \FSM_sequential_rx_state_reg[0]_4 ; input \FSM_sequential_rx_state_reg[0]_5 ; input reset_time_out_reg_0; input reset_time_out_reg_1; input reset_time_out_reg_2; input GT0_DATA_VALID_IN; input SYSCLK_IN; wire [2:0]D; wire DONT_RESET_ON_DATA_ERROR_IN; wire DONT_RESET_ON_DATA_ERROR_IN_0; wire [0:0]E; wire \FSM_sequential_rx_state[1]_i_3_n_0 ; wire \FSM_sequential_rx_state[3]_i_6_n_0 ; wire \FSM_sequential_rx_state[3]_i_7_n_0 ; wire \FSM_sequential_rx_state_reg[0] ; wire \FSM_sequential_rx_state_reg[0]_0 ; wire \FSM_sequential_rx_state_reg[0]_1 ; wire \FSM_sequential_rx_state_reg[0]_2 ; wire \FSM_sequential_rx_state_reg[0]_3 ; wire \FSM_sequential_rx_state_reg[0]_4 ; wire \FSM_sequential_rx_state_reg[0]_5 ; wire \FSM_sequential_rx_state_reg[1] ; wire \FSM_sequential_rx_state_reg[3] ; wire \FSM_sequential_rx_state_reg[3]_0 ; wire GT0_DATA_VALID_IN; wire GT0_RX_FSM_RESET_DONE_OUT; wire [2:0]Q; wire SYSCLK_IN; wire data_sync1; wire data_sync2; wire data_sync3; wire data_sync4; wire data_sync5; wire data_valid_sync; wire mmcm_lock_reclocked; wire reset_time_out_reg; wire reset_time_out_reg_0; wire reset_time_out_reg_1; wire reset_time_out_reg_2; wire time_out_wait_bypass_s3; LUT5 #( .INIT(32'hFFBFAFAF)) \FSM_sequential_rx_state[0]_i_1 (.I0(\FSM_sequential_rx_state_reg[0]_3 ), .I1(DONT_RESET_ON_DATA_ERROR_IN_0), .I2(Q[0]), .I3(Q[1]), .I4(Q[2]), .O(D[0])); LUT6 #( .INIT(64'hBABEBABEBAAEAAAE)) \FSM_sequential_rx_state[1]_i_1 (.I0(\FSM_sequential_rx_state_reg[1] ), .I1(Q[1]), .I2(Q[0]), .I3(Q[2]), .I4(\FSM_sequential_rx_state[1]_i_3_n_0 ), .I5(reset_time_out_reg), .O(D[1])); (* SOFT_HLUTNM = "soft_lutpair1" *) LUT3 #( .INIT(8'hFD)) \FSM_sequential_rx_state[1]_i_3 (.I0(\FSM_sequential_rx_state_reg[0]_4 ), .I1(data_valid_sync), .I2(DONT_RESET_ON_DATA_ERROR_IN), .O(\FSM_sequential_rx_state[1]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \FSM_sequential_rx_state[3]_i_1 (.I0(\FSM_sequential_rx_state_reg[0] ), .I1(\FSM_sequential_rx_state_reg[0]_0 ), .I2(\FSM_sequential_rx_state_reg[0]_1 ), .I3(\FSM_sequential_rx_state[3]_i_6_n_0 ), .I4(\FSM_sequential_rx_state[3]_i_7_n_0 ), .I5(\FSM_sequential_rx_state_reg[0]_2 ), .O(E)); (* SOFT_HLUTNM = "soft_lutpair1" *) LUT4 #( .INIT(16'hFFEF)) \FSM_sequential_rx_state[3]_i_10 (.I0(DONT_RESET_ON_DATA_ERROR_IN), .I1(data_valid_sync), .I2(\FSM_sequential_rx_state_reg[0]_4 ), .I3(reset_time_out_reg), .O(DONT_RESET_ON_DATA_ERROR_IN_0)); LUT6 #( .INIT(64'hFFFDCCCCFCFDCCCC)) \FSM_sequential_rx_state[3]_i_2 (.I0(time_out_wait_bypass_s3), .I1(\FSM_sequential_rx_state_reg[3]_0 ), .I2(Q[1]), .I3(Q[0]), .I4(Q[2]), .I5(DONT_RESET_ON_DATA_ERROR_IN_0), .O(D[2])); LUT6 #( .INIT(64'h4070FF0040700000)) \FSM_sequential_rx_state[3]_i_6 (.I0(Q[1]), .I1(data_valid_sync), .I2(time_out_wait_bypass_s3), .I3(Q[0]), .I4(Q[2]), .I5(\FSM_sequential_rx_state_reg[0]_5 ), .O(\FSM_sequential_rx_state[3]_i_6_n_0 )); LUT6 #( .INIT(64'h32302220D2D0C2C0)) \FSM_sequential_rx_state[3]_i_7 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .I3(mmcm_lock_reclocked), .I4(GT0_RX_FSM_RESET_DONE_OUT), .I5(data_valid_sync), .O(\FSM_sequential_rx_state[3]_i_7_n_0 )); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg1 (.C(SYSCLK_IN), .CE(1'b1), .D(GT0_DATA_VALID_IN), .Q(data_sync1), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg2 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync1), .Q(data_sync2), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg3 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync2), .Q(data_sync3), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg4 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync3), .Q(data_sync4), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg5 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync4), .Q(data_sync5), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg6 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync5), .Q(data_valid_sync), .R(1'b0)); LUT6 #( .INIT(64'hFFAEFFFFFFAE0000)) reset_time_out_i_1__0 (.I0(\FSM_sequential_rx_state[3]_i_7_n_0 ), .I1(reset_time_out_reg_0), .I2(Q[2]), .I3(reset_time_out_reg_1), .I4(reset_time_out_reg_2), .I5(reset_time_out_reg), .O(\FSM_sequential_rx_state_reg[3] )); endmodule (* ORIG_REF_NAME = "ngFEC_mgt_sync_block" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_sync_block_11 (SR, mmcm_lock_reclocked_reg, mmcm_lock_reclocked, Q, mmcm_lock_reclocked_reg_0, SYSCLK_IN); output [0:0]SR; output mmcm_lock_reclocked_reg; input mmcm_lock_reclocked; input [1:0]Q; input mmcm_lock_reclocked_reg_0; input SYSCLK_IN; wire [1:0]Q; wire [0:0]SR; wire SYSCLK_IN; wire data_sync1; wire data_sync2; wire data_sync3; wire data_sync4; wire data_sync5; wire mmcm_lock_i; wire mmcm_lock_reclocked; wire mmcm_lock_reclocked_reg; wire mmcm_lock_reclocked_reg_0; (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg1 (.C(SYSCLK_IN), .CE(1'b1), .D(1'b1), .Q(data_sync1), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg2 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync1), .Q(data_sync2), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg3 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync2), .Q(data_sync3), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg4 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync3), .Q(data_sync4), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg5 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync4), .Q(data_sync5), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg6 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync5), .Q(mmcm_lock_i), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair2" *) LUT1 #( .INIT(2'h1)) \mmcm_lock_count[7]_i_1__0 (.I0(mmcm_lock_i), .O(SR)); (* SOFT_HLUTNM = "soft_lutpair2" *) LUT5 #( .INIT(32'hAAEA0000)) mmcm_lock_reclocked_i_1__0 (.I0(mmcm_lock_reclocked), .I1(Q[1]), .I2(Q[0]), .I3(mmcm_lock_reclocked_reg_0), .I4(mmcm_lock_i), .O(mmcm_lock_reclocked_reg)); endmodule (* ORIG_REF_NAME = "ngFEC_mgt_sync_block" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_sync_block_12 (data_out, data_in, gt0_rxusrclk_in); output data_out; input data_in; input gt0_rxusrclk_in; wire data_in; wire data_out; wire data_sync1; wire data_sync2; wire data_sync3; wire data_sync4; wire data_sync5; wire gt0_rxusrclk_in; (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg1 (.C(gt0_rxusrclk_in), .CE(1'b1), .D(data_in), .Q(data_sync1), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg2 (.C(gt0_rxusrclk_in), .CE(1'b1), .D(data_sync1), .Q(data_sync2), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg3 (.C(gt0_rxusrclk_in), .CE(1'b1), .D(data_sync2), .Q(data_sync3), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg4 (.C(gt0_rxusrclk_in), .CE(1'b1), .D(data_sync3), .Q(data_sync4), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg5 (.C(gt0_rxusrclk_in), .CE(1'b1), .D(data_sync4), .Q(data_sync5), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg6 (.C(gt0_rxusrclk_in), .CE(1'b1), .D(data_sync5), .Q(data_out), .R(1'b0)); endmodule (* ORIG_REF_NAME = "ngFEC_mgt_sync_block" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_sync_block_13 (data_out, data_in, gt0_rxusrclk_in); output data_out; input data_in; input gt0_rxusrclk_in; wire data_in; wire data_out; wire data_sync1; wire data_sync2; wire data_sync3; wire data_sync4; wire data_sync5; wire gt0_rxusrclk_in; (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg1 (.C(gt0_rxusrclk_in), .CE(1'b1), .D(data_in), .Q(data_sync1), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg2 (.C(gt0_rxusrclk_in), .CE(1'b1), .D(data_sync1), .Q(data_sync2), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg3 (.C(gt0_rxusrclk_in), .CE(1'b1), .D(data_sync2), .Q(data_sync3), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg4 (.C(gt0_rxusrclk_in), .CE(1'b1), .D(data_sync3), .Q(data_sync4), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg5 (.C(gt0_rxusrclk_in), .CE(1'b1), .D(data_sync4), .Q(data_sync5), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg6 (.C(gt0_rxusrclk_in), .CE(1'b1), .D(data_sync5), .Q(data_out), .R(1'b0)); endmodule (* ORIG_REF_NAME = "ngFEC_mgt_sync_block" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_sync_block_14 (data_out, data_in, SYSCLK_IN); output data_out; input data_in; input SYSCLK_IN; wire SYSCLK_IN; wire data_in; wire data_out; wire data_sync1; wire data_sync2; wire data_sync3; wire data_sync4; wire data_sync5; (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg1 (.C(SYSCLK_IN), .CE(1'b1), .D(data_in), .Q(data_sync1), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg2 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync1), .Q(data_sync2), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg3 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync2), .Q(data_sync3), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg4 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync3), .Q(data_sync4), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg5 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync4), .Q(data_sync5), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg6 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync5), .Q(data_out), .R(1'b0)); endmodule (* ORIG_REF_NAME = "ngFEC_mgt_sync_block" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_sync_block_15 (data_out, data_sync_reg1_0, SYSCLK_IN); output data_out; input data_sync_reg1_0; input SYSCLK_IN; wire SYSCLK_IN; wire data_out; wire data_sync1; wire data_sync2; wire data_sync3; wire data_sync4; wire data_sync5; wire data_sync_reg1_0; (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg1 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync_reg1_0), .Q(data_sync1), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg2 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync1), .Q(data_sync2), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg3 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync2), .Q(data_sync3), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg4 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync3), .Q(data_sync4), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg5 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync4), .Q(data_sync5), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg6 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync5), .Q(data_out), .R(1'b0)); endmodule (* ORIG_REF_NAME = "ngFEC_mgt_sync_block" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_sync_block_16 (data_out, data_in, SYSCLK_IN); output data_out; input data_in; input SYSCLK_IN; wire SYSCLK_IN; wire data_in; wire data_out; wire data_sync1; wire data_sync2; wire data_sync3; wire data_sync4; wire data_sync5; (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg1 (.C(SYSCLK_IN), .CE(1'b1), .D(data_in), .Q(data_sync1), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg2 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync1), .Q(data_sync2), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg3 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync2), .Q(data_sync3), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg4 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync3), .Q(data_sync4), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg5 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync4), .Q(data_sync5), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg6 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync5), .Q(data_out), .R(1'b0)); endmodule (* ORIG_REF_NAME = "ngFEC_mgt_sync_block" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_sync_block_2 (SR, mmcm_lock_reclocked_reg, mmcm_lock_reclocked, Q, mmcm_lock_reclocked_reg_0, SYSCLK_IN); output [0:0]SR; output mmcm_lock_reclocked_reg; input mmcm_lock_reclocked; input [1:0]Q; input mmcm_lock_reclocked_reg_0; input SYSCLK_IN; wire [1:0]Q; wire [0:0]SR; wire SYSCLK_IN; wire data_sync1; wire data_sync2; wire data_sync3; wire data_sync4; wire data_sync5; wire mmcm_lock_i; wire mmcm_lock_reclocked; wire mmcm_lock_reclocked_reg; wire mmcm_lock_reclocked_reg_0; (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg1 (.C(SYSCLK_IN), .CE(1'b1), .D(1'b1), .Q(data_sync1), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg2 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync1), .Q(data_sync2), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg3 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync2), .Q(data_sync3), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg4 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync3), .Q(data_sync4), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg5 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync4), .Q(data_sync5), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg6 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync5), .Q(mmcm_lock_i), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair17" *) LUT1 #( .INIT(2'h1)) \mmcm_lock_count[7]_i_1 (.I0(mmcm_lock_i), .O(SR)); (* SOFT_HLUTNM = "soft_lutpair17" *) LUT5 #( .INIT(32'hAAEA0000)) mmcm_lock_reclocked_i_1 (.I0(mmcm_lock_reclocked), .I1(Q[1]), .I2(Q[0]), .I3(mmcm_lock_reclocked_reg_0), .I4(mmcm_lock_i), .O(mmcm_lock_reclocked_reg)); endmodule (* ORIG_REF_NAME = "ngFEC_mgt_sync_block" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_sync_block_3 (data_out, data_in, gt0_txusrclk_in); output data_out; input data_in; input gt0_txusrclk_in; wire data_in; wire data_out; wire data_sync1; wire data_sync2; wire data_sync3; wire data_sync4; wire data_sync5; wire gt0_txusrclk_in; (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg1 (.C(gt0_txusrclk_in), .CE(1'b1), .D(data_in), .Q(data_sync1), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg2 (.C(gt0_txusrclk_in), .CE(1'b1), .D(data_sync1), .Q(data_sync2), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg3 (.C(gt0_txusrclk_in), .CE(1'b1), .D(data_sync2), .Q(data_sync3), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg4 (.C(gt0_txusrclk_in), .CE(1'b1), .D(data_sync3), .Q(data_sync4), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg5 (.C(gt0_txusrclk_in), .CE(1'b1), .D(data_sync4), .Q(data_sync5), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg6 (.C(gt0_txusrclk_in), .CE(1'b1), .D(data_sync5), .Q(data_out), .R(1'b0)); endmodule (* ORIG_REF_NAME = "ngFEC_mgt_sync_block" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_sync_block_4 (data_out, data_in, SYSCLK_IN); output data_out; input data_in; input SYSCLK_IN; wire SYSCLK_IN; wire data_in; wire data_out; wire data_sync1; wire data_sync2; wire data_sync3; wire data_sync4; wire data_sync5; (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg1 (.C(SYSCLK_IN), .CE(1'b1), .D(data_in), .Q(data_sync1), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg2 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync1), .Q(data_sync2), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg3 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync2), .Q(data_sync3), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg4 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync3), .Q(data_sync4), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg5 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync4), .Q(data_sync5), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg6 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync5), .Q(data_out), .R(1'b0)); endmodule (* ORIG_REF_NAME = "ngFEC_mgt_sync_block" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_sync_block_5 (data_out, GT0_TX_FSM_RESET_DONE_OUT, gt0_txusrclk_in); output data_out; input GT0_TX_FSM_RESET_DONE_OUT; input gt0_txusrclk_in; wire GT0_TX_FSM_RESET_DONE_OUT; wire data_out; wire data_sync1; wire data_sync2; wire data_sync3; wire data_sync4; wire data_sync5; wire gt0_txusrclk_in; (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg1 (.C(gt0_txusrclk_in), .CE(1'b1), .D(GT0_TX_FSM_RESET_DONE_OUT), .Q(data_sync1), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg2 (.C(gt0_txusrclk_in), .CE(1'b1), .D(data_sync1), .Q(data_sync2), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg3 (.C(gt0_txusrclk_in), .CE(1'b1), .D(data_sync2), .Q(data_sync3), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg4 (.C(gt0_txusrclk_in), .CE(1'b1), .D(data_sync3), .Q(data_sync4), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg5 (.C(gt0_txusrclk_in), .CE(1'b1), .D(data_sync4), .Q(data_sync5), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg6 (.C(gt0_txusrclk_in), .CE(1'b1), .D(data_sync5), .Q(data_out), .R(1'b0)); endmodule (* ORIG_REF_NAME = "ngFEC_mgt_sync_block" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_sync_block_6 (data_out, data_sync_reg1_0, SYSCLK_IN); output data_out; input data_sync_reg1_0; input SYSCLK_IN; wire SYSCLK_IN; wire data_out; wire data_sync1; wire data_sync2; wire data_sync3; wire data_sync4; wire data_sync5; wire data_sync_reg1_0; (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg1 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync_reg1_0), .Q(data_sync1), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg2 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync1), .Q(data_sync2), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg3 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync2), .Q(data_sync3), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg4 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync3), .Q(data_sync4), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg5 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync4), .Q(data_sync5), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg6 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync5), .Q(data_out), .R(1'b0)); endmodule (* ORIG_REF_NAME = "ngFEC_mgt_sync_block" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_sync_block_7 (data_out, data_in, SYSCLK_IN); output data_out; input data_in; input SYSCLK_IN; wire SYSCLK_IN; wire data_in; wire data_out; wire data_sync1; wire data_sync2; wire data_sync3; wire data_sync4; wire data_sync5; (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg1 (.C(SYSCLK_IN), .CE(1'b1), .D(data_in), .Q(data_sync1), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg2 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync1), .Q(data_sync2), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg3 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync2), .Q(data_sync3), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg4 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync3), .Q(data_sync4), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg5 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync4), .Q(data_sync5), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg6 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync5), .Q(data_out), .R(1'b0)); endmodule (* ORIG_REF_NAME = "ngFEC_mgt_sync_block" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_sync_block_8 (\FSM_sequential_rx_state_reg[1] , \FSM_sequential_rx_state_reg[1]_0 , data_sync_reg6_0, Q, \FSM_sequential_rx_state_reg[0] , \FSM_sequential_rx_state_reg[0]_0 , rxresetdone_s3, recclk_mon_count_reset, gt0_cplllock_out, SYSCLK_IN); output \FSM_sequential_rx_state_reg[1] ; output \FSM_sequential_rx_state_reg[1]_0 ; output data_sync_reg6_0; input [3:0]Q; input \FSM_sequential_rx_state_reg[0] ; input \FSM_sequential_rx_state_reg[0]_0 ; input rxresetdone_s3; input recclk_mon_count_reset; input gt0_cplllock_out; input SYSCLK_IN; wire \FSM_sequential_rx_state_reg[0] ; wire \FSM_sequential_rx_state_reg[0]_0 ; wire \FSM_sequential_rx_state_reg[1] ; wire \FSM_sequential_rx_state_reg[1]_0 ; wire [3:0]Q; wire SYSCLK_IN; wire cplllock_sync; wire data_sync1; wire data_sync2; wire data_sync3; wire data_sync4; wire data_sync5; wire data_sync_reg6_0; wire gt0_cplllock_out; wire recclk_mon_count_reset; wire rxresetdone_s3; LUT6 #( .INIT(64'h00FF0000ABAB0000)) \FSM_sequential_rx_state[3]_i_8 (.I0(\FSM_sequential_rx_state_reg[1]_0 ), .I1(Q[1]), .I2(\FSM_sequential_rx_state_reg[0] ), .I3(\FSM_sequential_rx_state_reg[0]_0 ), .I4(Q[0]), .I5(Q[3]), .O(\FSM_sequential_rx_state_reg[1] )); LUT6 #( .INIT(64'hFDFFFFFF00030000)) adapt_count_reset_i_1 (.I0(cplllock_sync), .I1(Q[2]), .I2(Q[3]), .I3(Q[1]), .I4(Q[0]), .I5(recclk_mon_count_reset), .O(data_sync_reg6_0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg1 (.C(SYSCLK_IN), .CE(1'b1), .D(gt0_cplllock_out), .Q(data_sync1), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg2 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync1), .Q(data_sync2), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg3 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync2), .Q(data_sync3), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg4 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync3), .Q(data_sync4), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg5 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync4), .Q(data_sync5), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg6 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync5), .Q(cplllock_sync), .R(1'b0)); LUT4 #( .INIT(16'h8F80)) reset_time_out_i_2__0 (.I0(Q[1]), .I1(rxresetdone_s3), .I2(Q[2]), .I3(cplllock_sync), .O(\FSM_sequential_rx_state_reg[1]_0 )); endmodule (* ORIG_REF_NAME = "ngFEC_mgt_sync_block" *) module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ngFEC_mgt_sync_block_9 (data_out, gt0_rxresetdone_out, SYSCLK_IN); output data_out; input gt0_rxresetdone_out; input SYSCLK_IN; wire SYSCLK_IN; wire data_out; wire data_sync1; wire data_sync2; wire data_sync3; wire data_sync4; wire data_sync5; wire gt0_rxresetdone_out; (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg1 (.C(SYSCLK_IN), .CE(1'b1), .D(gt0_rxresetdone_out), .Q(data_sync1), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg2 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync1), .Q(data_sync2), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg3 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync2), .Q(data_sync3), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg4 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync3), .Q(data_sync4), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg5 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync4), .Q(data_sync5), .R(1'b0)); (* ASYNC_REG *) (* SHREG_EXTRACT = "no" *) (* XILINX_LEGACY_PRIM = "FD" *) (* box_type = "PRIMITIVE" *) FDRE #( .INIT(1'b0)) data_sync_reg6 (.C(SYSCLK_IN), .CE(1'b1), .D(data_sync5), .Q(data_out), .R(1'b0)); endmodule `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (strong1, weak0) GSR = GSR_int; assign (strong1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule `endif