Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------ | Tool Version : Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 | Date : Mon Mar 23 14:56:39 2020 | Host : baby running 64-bit major release (build 9200) | Command : upgrade_ip | Device : xc7k420tffg1156-2 ------------------------------------------------------------------------------------ Upgrade Log for IP 'aurora_64b66b_0' 1. Summary ---------- CAUTION (success, with warnings) in the conversion of aurora_64b66b_0 (xilinx.com:ip:aurora_64b66b:11.2 (Rev. 6)) to Vivado generation flows. After upgrade, an IP may have parameter and port differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality. Also, please review the updated IP instantiation template to ensure proper connectivity, and update your design if required. 2. Interface Information ------------------------ Detected external interface differences while upgrading 'aurora_64b66b_0'. -Upgrade has removed interface 'GT0_DRP' -Upgrade has added interface 'CHANNEL_DRP_IF0' (xilinx.com:interface:drp:1.0) -Upgrade has added interface 'gt_qpllclk_quad1_out' (xilinx.com:signal:clock:1.0) -Upgrade has added interface 'gt_qpllrefclk_quad1_out' (xilinx.com:signal:clock:1.0) 3. Connection Warnings ---------------------- Detected external port differences while upgrading 'aurora_64b66b_0'. These changes may impact your design. -Upgrade has removed port 'gt0_drpaddr' -Upgrade has removed port 'gt0_drpdi' -Upgrade has removed port 'gt0_drpdo' -Upgrade has removed port 'gt0_drpen' -Upgrade has removed port 'gt0_drprdy' -Upgrade has removed port 'gt0_drpwe' -Upgrade has removed port 'gt_powergood' -Upgrade has added port 'drp_clk_in' -Upgrade has added port 'drpaddr_in' -Upgrade has added port 'drpdi_in' -Upgrade has added port 'drpdo_out' -Upgrade has added port 'drpen_in' -Upgrade has added port 'drprdy_out' -Upgrade has added port 'drpwe_in' -Upgrade has added port 'gt_qpllclk_quad1_out' -Upgrade has added port 'gt_qpllrefclk_quad1_out' 4. Customization warnings ------------------------- The normal upgrade process failed due to validation failures in the given configuration. Attempting partial upgrade to set as many user parameters as possible. Please check the parameters whose values were not applied. Unable to set the value 'GTH' on parameter 'C GT TYPE' due to the following failure - Value 'GTH' is out of the range for parameter 'C GT TYPE(C_GT_TYPE)' for IP 'aurora_64b66b_0' . Valid values are - gtx . Restoring to an old valid value of 'gtx' Unable to set the value 'Quad_X0Y2' on parameter 'Starting GT Quad' due to the following failure - Value 'Quad_X0Y2' is out of the range for parameter 'Starting GT Quad(C_START_QUAD)' for IP 'aurora_64b66b_0' . Valid values are - X0Y0 . Restoring to an old valid value of 'X0Y0' Unable to set the value 'X0Y8' on parameter 'Starting GT Lane' due to the following failure - Value 'X0Y8' is out of the range for parameter 'Starting GT Lane(C_START_LANE)' for IP 'aurora_64b66b_0' . Valid values are - X0Y0 . Restoring to an old valid value of 'X0Y0' Unable to set the value 'MGTREFCLK0_of_Quad_X0Y2' on parameter 'GT Refclk Selection' due to the following failure - Value 'MGTREFCLK0_of_Quad_X0Y2' is out of the range for parameter 'GT Refclk Selection(C_REFCLK_SOURCE)' for IP 'aurora_64b66b_0' . Valid values are - none . Restoring to an old valid value of 'none' Unable to set the value 'GTHQ0' on parameter 'C GT CLOCK 1' due to the following failure - Value 'GTHQ0' is out of the range for parameter 'C GT CLOCK 1(C_GT_CLOCK_1)' for IP 'aurora_64b66b_0' . Valid values are - GTXQ0 . Restoring to an old valid value of 'GTXQ0' An attempt to modify the value of disabled parameter 'CHANNEL_ENABLE' from 'X0Y0' to 'X0Y8' has been ignored for IP 'aurora_64b66b_0' Unable to set the value '200' on parameter 'C REFCLK FREQUENCY' due to the following failure - Value '200' is out of the range for parameter 'C REFCLK FREQUENCY(C_REFCLK_FREQUENCY)' for IP 'aurora_64b66b_0' . Valid values are - 625.000, 500.000, 416.666, 333.333, 312.500, 250.000, 208.333, 200.000, 166.666, 156.250, 125.000, 100.000 . Restoring to an old valid value of '156.250' 5. Debug Commands ----------------- The following debug information can be passed to Vivado as Tcl commands, in order to validate or debug the output of the upgrade flow. You may consult any warnings from within this upgrade, and alter or remove the configuration parameter(s) which caused the warning; then execute the Tcl commands, and use the IP Customization GUI to verify the IP configuration. create_ip -vlnv xilinx.com:ip:aurora_64b66b:11.2 -user_name aurora_64b66b_0 set_property -dict "\ CONFIG.CHANNEL_ENABLE {X0Y8} \ CONFIG.C_AURORA_LANES {1} \ CONFIG.C_COLUMN_USED {left} \ CONFIG.C_DOCCPORT_ENABLE {false} \ CONFIG.C_EXAMPLE_SIMULATION {false} \ CONFIG.C_GTWIZ_OUT {false} \ CONFIG.C_GT_CLOCK_1 {GTHQ0} \ CONFIG.C_GT_CLOCK_2 {None} \ CONFIG.C_GT_CLOCK_3 {None} \ CONFIG.C_GT_CLOCK_4 {None} \ CONFIG.C_GT_CLOCK_5 {None} \ CONFIG.C_GT_LOC_1 {1} \ CONFIG.C_GT_LOC_10 {X} \ CONFIG.C_GT_LOC_11 {X} \ CONFIG.C_GT_LOC_12 {X} \ CONFIG.C_GT_LOC_13 {X} \ CONFIG.C_GT_LOC_14 {X} \ CONFIG.C_GT_LOC_15 {X} \ CONFIG.C_GT_LOC_16 {X} \ CONFIG.C_GT_LOC_17 {X} \ CONFIG.C_GT_LOC_18 {X} \ CONFIG.C_GT_LOC_19 {X} \ CONFIG.C_GT_LOC_2 {X} \ CONFIG.C_GT_LOC_20 {X} \ CONFIG.C_GT_LOC_21 {X} \ CONFIG.C_GT_LOC_22 {X} \ CONFIG.C_GT_LOC_23 {X} \ CONFIG.C_GT_LOC_24 {X} \ CONFIG.C_GT_LOC_25 {X} \ CONFIG.C_GT_LOC_26 {X} \ CONFIG.C_GT_LOC_27 {X} \ CONFIG.C_GT_LOC_28 {X} \ CONFIG.C_GT_LOC_29 {X} \ CONFIG.C_GT_LOC_3 {X} \ CONFIG.C_GT_LOC_30 {X} \ CONFIG.C_GT_LOC_31 {X} \ CONFIG.C_GT_LOC_32 {X} \ CONFIG.C_GT_LOC_33 {X} \ CONFIG.C_GT_LOC_34 {X} \ CONFIG.C_GT_LOC_35 {X} \ CONFIG.C_GT_LOC_36 {X} \ CONFIG.C_GT_LOC_37 {X} \ CONFIG.C_GT_LOC_38 {X} \ CONFIG.C_GT_LOC_39 {X} \ CONFIG.C_GT_LOC_4 {X} \ CONFIG.C_GT_LOC_40 {X} \ CONFIG.C_GT_LOC_41 {X} \ CONFIG.C_GT_LOC_42 {X} \ CONFIG.C_GT_LOC_43 {X} \ CONFIG.C_GT_LOC_44 {X} \ CONFIG.C_GT_LOC_45 {X} \ CONFIG.C_GT_LOC_46 {X} \ CONFIG.C_GT_LOC_47 {X} \ CONFIG.C_GT_LOC_48 {X} \ CONFIG.C_GT_LOC_5 {X} \ CONFIG.C_GT_LOC_6 {X} \ CONFIG.C_GT_LOC_7 {X} \ CONFIG.C_GT_LOC_8 {X} \ CONFIG.C_GT_LOC_9 {X} \ CONFIG.C_GT_TYPE {GTH} \ CONFIG.C_INIT_CLK {78.125} \ CONFIG.C_LINE_RATE {5} \ CONFIG.C_REFCLK2_SOURCE {None} \ CONFIG.C_REFCLK3_SOURCE {None} \ CONFIG.C_REFCLK4_SOURCE {None} \ CONFIG.C_REFCLK5_SOURCE {None} \ CONFIG.C_REFCLK_FREQUENCY {200} \ CONFIG.C_REFCLK_SOURCE {MGTREFCLK0_of_Quad_X0Y2} \ CONFIG.C_START_LANE {X0Y8} \ CONFIG.C_START_QUAD {Quad_X0Y2} \ CONFIG.C_UCOLUMN_USED {left} \ CONFIG.C_USER_K {false} \ CONFIG.C_USE_BYTESWAP {false} \ CONFIG.C_USE_CHIPSCOPE {false} \ CONFIG.C_active_transceiverquads {1} \ CONFIG.Component_Name {aurora_64b66b_0} \ CONFIG.DRP_FREQ {100.0000} \ CONFIG.INS_LOSS_NYQ {20} \ CONFIG.RX_COUPLING {AC} \ CONFIG.RX_EQ_MODE {AUTO} \ CONFIG.RX_PPM_OFFSET {0} \ CONFIG.RX_TERMINATION {PROGRAMMABLE} \ CONFIG.RX_TERMINATION_PROG_VALUE {800} \ CONFIG.SINGLEEND_GTREFCLK {true} \ CONFIG.SINGLEEND_INITCLK {true} \ CONFIG.SupportLevel {1} \ CONFIG.TransceiverControl {false} \ CONFIG.USER_DATA_M_AXIS_RX.CLK_DOMAIN {} \ CONFIG.USER_DATA_M_AXIS_RX.FREQ_HZ {100000000} \ CONFIG.USER_DATA_M_AXIS_RX.HAS_TKEEP {0} \ CONFIG.USER_DATA_M_AXIS_RX.HAS_TLAST {0} \ CONFIG.USER_DATA_M_AXIS_RX.HAS_TREADY {0} \ CONFIG.USER_DATA_M_AXIS_RX.HAS_TSTRB {0} \ CONFIG.USER_DATA_M_AXIS_RX.INSERT_VIP {0} \ CONFIG.USER_DATA_M_AXIS_RX.LAYERED_METADATA {undef} \ CONFIG.USER_DATA_M_AXIS_RX.PHASE {0.000} \ CONFIG.USER_DATA_M_AXIS_RX.TDATA_NUM_BYTES {8} \ CONFIG.USER_DATA_M_AXIS_RX.TDEST_WIDTH {0} \ CONFIG.USER_DATA_M_AXIS_RX.TID_WIDTH {0} \ CONFIG.USER_DATA_M_AXIS_RX.TUSER_WIDTH {0} \ CONFIG.USER_DATA_S_AXIS_TX.CLK_DOMAIN {} \ CONFIG.USER_DATA_S_AXIS_TX.FREQ_HZ {100000000} \ CONFIG.USER_DATA_S_AXIS_TX.HAS_TKEEP {0} \ CONFIG.USER_DATA_S_AXIS_TX.HAS_TLAST {0} \ CONFIG.USER_DATA_S_AXIS_TX.HAS_TREADY {1} \ CONFIG.USER_DATA_S_AXIS_TX.HAS_TSTRB {0} \ CONFIG.USER_DATA_S_AXIS_TX.INSERT_VIP {0} \ CONFIG.USER_DATA_S_AXIS_TX.LAYERED_METADATA {undef} \ CONFIG.USER_DATA_S_AXIS_TX.PHASE {0.000} \ CONFIG.USER_DATA_S_AXIS_TX.TDATA_NUM_BYTES {8} \ CONFIG.USER_DATA_S_AXIS_TX.TDEST_WIDTH {0} \ CONFIG.USER_DATA_S_AXIS_TX.TID_WIDTH {0} \ CONFIG.USER_DATA_S_AXIS_TX.TUSER_WIDTH {0} \ CONFIG.crc_mode {false} \ CONFIG.dataflow_config {Duplex} \ CONFIG.drp_mode {Native} \ CONFIG.flow_mode {None} \ CONFIG.gt_drp_clk_in.ASSOCIATED_BUSIF {CHANNEL_DRP_IF0:CHANNEL_DRP_IF1:CHANNEL_DRP_IF2:CHANNEL_DRP_IF3:CHANNEL_DRP_IF4:CHANNEL_DRP_IF5:CHANNEL_DRP_IF6:CHANNEL_DRP_IF7:CHANNEL_DRP_IF8:CHANNEL_DRP_IF9:CHANNEL_DRP_IF10:CHANNEL_DRP_IF11:CHANNEL_DRP_IF12:CHANNEL_DRP_IF13:CHANNEL_DRP_IF14:CHANNEL_DRP_IF15:GTCOMMON_DRP_IF0:GTCOMMON_DRP_IF1:GTCOMMON_DRP_IF2:GTCOMMON_DRP_IF3:GTCOMMON_DRP_IF4:GTCOMMON_DRP_IF5:GTCOMMON_DRP_IF6:GTCOMMON_DRP_IF7:GTCOMMON_DRP_IF8:AXILITE_DRP_IF_0:AXILITE_DRP_IF_1:AXILITE_DRP_IF_2:AXILITE_DRP_IF_3:AXILITE_DRP_IF_4:AXILITE_DRP_IF_5:AXILITE_DRP_IF_6:AXILITE_DRP_IF_7:AXILITE_DRP_IF_8:AXILITE_DRP_IF_9:AXILITE_DRP_IF_10:AXILITE_DRP_IF_11:AXILITE_DRP_IF_12:AXILITE_DRP_IF_13:AXILITE_DRP_IF_14:AXILITE_DRP_IF_15} \ CONFIG.gt_drp_clk_in.ASSOCIATED_RESET {gt_reset_out} \ CONFIG.gt_drp_clk_in.CLK_DOMAIN {} \ CONFIG.gt_drp_clk_in.FREQ_HZ {100000000} \ CONFIG.gt_drp_clk_in.INSERT_VIP {0} \ CONFIG.gt_drp_clk_in.PHASE {0.000} \ CONFIG.gt_reset.INSERT_VIP {0} \ CONFIG.gt_reset.POLARITY {ACTIVE_HIGH} \ CONFIG.gt_reset_out.INSERT_VIP {0} \ CONFIG.gt_reset_out.POLARITY {ACTIVE_HIGH} \ CONFIG.init_clk_in.ASSOCIATED_BUSIF {GT0_DRP:GT1_DRP:GT2_DRP:GT3_DRP:GT4_DRP:GT5_DRP:GT6_DRP:GT7_DRP:GT8_DRP:GT9_DRP:GT10_DRP:GT11_DRP:GT12_DRP:GT13_DRP:GT14_DRP:GT15_DRP:AXILITE_DRP_IF_0:AXILITE_DRP_IF_1:AXILITE_DRP_IF_2:AXILITE_DRP_IF_3:AXILITE_DRP_IF_4:AXILITE_DRP_IF_5:AXILITE_DRP_IF_6:AXILITE_DRP_IF_7:AXILITE_DRP_IF_8:AXILITE_DRP_IF_9:AXILITE_DRP_IF_10:AXILITE_DRP_IF_11:AXILITE_DRP_IF_12:AXILITE_DRP_IF_13:AXILITE_DRP_IF_14:AXILITE_DRP_IF_15} \ CONFIG.init_clk_in.ASSOCIATED_RESET {gt_reset_out} \ CONFIG.init_clk_in.CLK_DOMAIN {} \ CONFIG.init_clk_in.FREQ_HZ {100000000} \ CONFIG.init_clk_in.INSERT_VIP {0} \ CONFIG.init_clk_in.PHASE {0.000} \ CONFIG.interface_mode {Streaming} \ CONFIG.link_reset_out.INSERT_VIP {0} \ CONFIG.link_reset_out.POLARITY {ACTIVE_HIGH} \ CONFIG.refclk1_in.ASSOCIATED_BUSIF {} \ CONFIG.refclk1_in.ASSOCIATED_RESET {} \ CONFIG.refclk1_in.CLK_DOMAIN {} \ CONFIG.refclk1_in.FREQ_HZ {100000000} \ CONFIG.refclk1_in.INSERT_VIP {0} \ CONFIG.refclk1_in.PHASE {0.000} \ CONFIG.reset_pb.INSERT_VIP {0} \ CONFIG.reset_pb.POLARITY {ACTIVE_HIGH} \ CONFIG.sync_clk_out.ASSOCIATED_BUSIF {} \ CONFIG.sync_clk_out.ASSOCIATED_RESET {} \ CONFIG.sync_clk_out.CLK_DOMAIN {} \ CONFIG.sync_clk_out.FREQ_HZ {100000000} \ CONFIG.sync_clk_out.INSERT_VIP {0} \ CONFIG.sync_clk_out.PHASE {0.000} \ CONFIG.sys_reset_out.INSERT_VIP {0} \ CONFIG.sys_reset_out.POLARITY {ACTIVE_HIGH} \ CONFIG.tx_out_clk.ASSOCIATED_BUSIF {} \ CONFIG.tx_out_clk.ASSOCIATED_RESET {} \ CONFIG.tx_out_clk.CLK_DOMAIN {} \ CONFIG.tx_out_clk.FREQ_HZ {100000000} \ CONFIG.tx_out_clk.INSERT_VIP {0} \ CONFIG.tx_out_clk.PHASE {0.000} \ CONFIG.user_clk_out.ASSOCIATED_BUSIF {USER_DATA_S_AXIS_TX:USER_DATA_M_AXIS_RX:UFC_S_AXIS_TX:UFC_M_AXIS_RX:NFC_S_AXIS_TX:USER_K_S_AXIS_TX:USER_K_M_AXIS_RX} \ CONFIG.user_clk_out.ASSOCIATED_RESET {sys_reset_out:tx_sys_reset_out:rx_sys_reset_out:reset2fc:reset2fg} \ CONFIG.user_clk_out.CLK_DOMAIN {} \ CONFIG.user_clk_out.FREQ_HZ {156250000} \ CONFIG.user_clk_out.INSERT_VIP {0} \ CONFIG.user_clk_out.PHASE {0.000} " [get_ips aurora_64b66b_0]