--=================================================================================================-- --################################## Module Information #######################################-- --=================================================================================================-- -- -- Company: CERN (PH-ESE-BE) -- Engineer: Manoel Barros Marin (manoel.barros.marin@cern.ch) (m.barros.marin@ieee.org) -- -- Project Name: GBT-FPGA -- Module Name: Xilinx Kintex 7 & Virtex 7 - GBT Bank example design -- -- Language: VHDL'93 -- -- Target Device: Xilinx Kintex 7 & Virtex 7 -- Tool version: ISE 14.5 -- -- Version: 3.2 -- -- Description: -- -- Versions history: DATE VERSION AUTHOR DESCRIPTION -- -- 28/10/2013 3.0 M. Barros Marin First .vhd module definition -- -- 14/08/2014 3.2 M. Barros Marin Minor modifications -- -- Additional Comments: Note!! Only ONE GBT Bank with ONE link can be used in this example design. -- -- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! -- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! IMPORTANT !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! -- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! -- !! !! -- !! * The different parameters of the GBT Bank are set through: !! -- !! (Note!! These parameters are vendor specific) !! -- !! !! -- !! - The MGT control ports of the GBT Bank module (these ports are listed in the records !! -- !! of the file "__gbt_bank_package.vhd"). !! -- !! (e.g. xlx_v6_gbt_bank_package.vhd) !! -- !! !! -- !! - By modifying the content of the file "__gbt_bank_user_setup.vhd". !! -- !! (e.g. xlx_v6_gbt_bank_user_setup.vhd) !! -- !! !! -- !! * The "__gbt_bank_user_setup.vhd" is the only file of the GBT Bank that !! -- !! may be modified by the user. The rest of the files MUST be used as is. !! -- !! !! -- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! -- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! -- --=================================================================================================-- --#################################################################################################-- --=================================================================================================-- -- IEEE VHDL standard library: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use IEEE.std_logic_misc.ALL; -- Xilinx devices library: library unisim; use unisim.vcomponents.all; -- Custom libraries and packages: use work.gbt_bank_package.all; use work.vendor_specific_gbt_bank_package.all; --=================================================================================================-- --####################################### Entity ##############################################-- --=================================================================================================-- entity xlx_ku_gbt_ngFEC_design is generic ( BLK_No : integer := 0; TX_OPTIMIZATION : integer range 0 to 1 := STANDARD; RX_OPTIMIZATION : integer range 0 to 1 := STANDARD; TX_ENCODING : integer range 0 to 2 := GBT_FRAME; RX_ENCODING : integer range 0 to 2 := GBT_FRAME; INITIAL_DELAY : natural := 1 * 40e6 ); port ( --==============-- -- Clocks -- --==============-- gtrefclk : in STD_LOGIC; DRPclk : in STD_LOGIC; TX_WORDCLK_I : in STD_LOGIC; mgt_en : in STD_LOGIC_VECTOR (11 downto 0); cpll_locked : out STD_LOGIC_VECTOR (11 downto 0); -- buffbypass_tx_error : out std_logic; -- TX_WORDCLKX2 : out std_logic; -- TX_WORDCLK_START : in std_logic; TX_CLKEN_I : in std_logic; RX_CLKEN_O : out std_logic_vector(11 downto 0); RX_WORDCLK_O : out std_logic_vector(11 downto 0); -- TX_WORDCLK_O : out std_logic; RX_WORDCLK_RDY_O : out std_logic_vector(11 downto 0); RX_FRAMECLK_RDY_O : out std_logic_vector(11 downto 0); --==============-- -- Reset -- --==============-- GBTBANK_GENERAL_RESET_I : in std_logic; GBTBANK_MANUAL_RESET_TX_I : in std_logic; GBTBANK_MANUAL_RESET_RX_I : in std_logic; GBT_CHANNEL_RESET_RX_I : in std_logic_vector(11 downto 0); HPTD_RESET_I : in std_logic_vector(11 downto 0); --==============-- -- Serial lanes -- --==============-- GBTBANK_MGT_RX_P : in std_logic_vector(11 downto 0); GBTBANK_MGT_RX_N : in std_logic_vector(11 downto 0); GBTBANK_MGT_TX_P : out std_logic_vector(11 downto 0); GBTBANK_MGT_TX_N : out std_logic_vector(11 downto 0); --==============-- -- Data -- --==============-- GBTBANK_GBT_DATA_I : in gbt_reg84_A(11 downto 0); GBTBANK_WB_DATA_I : in gbt_reg116_A(11 downto 0); TX_DATA_O : out gbt_reg84_A(11 downto 0); WB_DATA_O : out gbt_reg116_A(11 downto 0); GBTBANK_GBT_DATA_O : out gbt_reg84_A(11 downto 0); GBTBANK_WB_DATA_O : out gbt_reg116_A(11 downto 0); --==============-- -- TX ctrl -- --==============-- TX_ENCODING_SEL_i : in std_logic_vector(11 downto 0); --! Select the Tx encoding in dynamic mode ('1': GBT / '0': WideBus) GBTBANK_TX_ISDATA_SEL_I : in std_logic_vector(11 downto 0); --==============-- -- RX ctrl -- --==============-- RX_ENCODING_SEL_i : in std_logic_vector(11 downto 0); --! Select the Rx encoding in dynamic mode ('1': GBT / '0': WideBus) --==============-- -- TX Status -- --==============-- GBTBANK_GBTTX_READY_O : out std_logic_vector(11 downto 0); GBTBANK_LINK_READY_O : out std_logic_vector(11 downto 0); GBTBANK_TX_ALIGNED_O : out std_logic_vector(11 downto 0); GBTBANK_TX_ALIGNCOMPUTED_O : out std_logic_vector(11 downto 0); GBTBANK_RESET_TX_DONE_O : out std_logic_vector(11 downto 0); --==============-- -- RX Status -- --==============-- GBTBANK_GBTRX_READY_O : out std_logic_vector(11 downto 0); GBTBANK_RX_ISDATA_SEL_O : out std_logic_vector(11 downto 0); GBTBANK_RX_ERRORDETECTED_O : out std_logic_vector(11 downto 0); GBTBANK_RX_BITMODIFIED_FLAG_O : out gbt_reg84_A(11 downto 0); --==============-- -- XCVR ctrl -- --==============-- LOOPBACK : in std_logic_vector(2 downto 0) ); end xlx_ku_gbt_ngFEC_design; --=================================================================================================-- --#################################### Architecture ###########################################-- --=================================================================================================-- architecture structural of xlx_ku_gbt_ngFEC_design is --================================ Signal Declarations ================================-- --==========-- -- GBT Tx -- --==========-- --signal TX_WORDCLKX2_s : std_logic; signal gbt_txreset_s : std_logic_vector(11 downto 0); signal gbt_txdata_s : gbt_reg84_A(11 downto 0); signal wb_txdata_s : gbt_reg32_A(11 downto 0); --==========-- -- NGT -- --==========-- --signal mgt_txwordclk_s : std_logic; signal mgt_rxwordclk_s : std_logic_vector(11 downto 0); signal mgt_txreset_s : std_logic_vector(11 downto 0); --signal mgt_rxreset_i : std_logic_vector(11 downto 0); signal mgt_rxreset_s : std_logic_vector(11 downto 0); signal mgt_txready_s : std_logic_vector(11 downto 0); signal mgt_rxready_s : std_logic_vector(11 downto 0); signal mgt_headerflag_s : std_logic_vector(11 downto 0); --==========-- -- GBT Rx -- --==========-- signal rx_reset_i : std_logic_vector(11 downto 0); signal gbt_rxreset_s : std_logic_vector(11 downto 0); signal gbt_rxready_s : std_logic_vector(11 downto 0); signal gbt_rxdata_s : gbt_reg84_A(11 downto 0); signal wb_rxdata_s : gbt_reg32_A(11 downto 0); type clken_sr_A is array (11 downto 0) of std_logic_vector(GBT_WORD_RATIO-1 downto 0); signal rx_clken_sr : clken_sr_A; signal gbt_rxclken_s : std_logic_vector(11 downto 0); signal RX_FRAMECLK_RDY_i : std_logic_vector(11 downto 0); type array12X8 is array(0 to 11) of unsigned(7 downto 0); signal cnt : array12X8; --================================-- -- Data pattern generator/checker -- --================================-- signal gbtBank_txEncodingSel : std_logic_vector(1 downto 0); signal gbtBank_rxEncodingSel : std_logic_vector(1 downto 0); signal txData_from_gbtBank_pattGen : gbt_reg84_A(11 downto 0); signal txwBData_from_gbtBank_pattGen : gbt_reg32_A(11 downto 0); --=====================================================================================-- --=================================================================================================-- begin --========#### Architecture Body ####========-- --=================================================================================================-- --==================================== User Logic =====================================-- --TX_WORDCLKX2 <= TX_WORDCLKX2_s; --============-- -- Clocks -- --============-- --TX_WORDCLK_O <= mgt_txwordclk_s; RX_CLKEN_O <= gbt_rxclken_s; RX_WORDCLK_O <= mgt_rxwordclk_s; gbtBank_Clk_gen: for i in 0 to 11 generate process(mgt_rxready_s, mgt_txready_s, mgt_rxwordclk_s) begin if(mgt_rxready_s(i) = '0' or mgt_txready_s(i) = '0')then rx_clken_sr(i) <= (others => '0'); RX_FRAMECLK_RDY_i(i) <= '0'; cnt(i) <= (others => '0'); elsif(mgt_rxwordclk_s(i)'event and mgt_rxwordclk_s(i) = '1')then if(mgt_headerflag_s(i) = '1')then rx_clken_sr(i)(GBT_WORD_RATIO-1 downto 1) <= (others => '0'); rx_clken_sr(i)(0) <= '1'; else rx_clken_sr(i)(GBT_WORD_RATIO-1 downto 0) <= rx_clken_sr(i)(GBT_WORD_RATIO-2 downto 0) & rx_clken_sr(i)(GBT_WORD_RATIO-1); end if; if(RX_FRAMECLK_RDY_i(i) = '0')then if(mgt_headerflag_s(i) /= rx_clken_sr(i)(GBT_WORD_RATIO-1))then cnt(i) <= (others => '0'); else cnt(i) <= cnt(i) + 1; if(cnt(i) = x"ff")then RX_FRAMECLK_RDY_i(i) <= '1'; end if; end if; elsif(RX_FRAMECLK_RDY_i(i) = '1')then if(mgt_headerflag_s(i) /= rx_clken_sr(i)(GBT_WORD_RATIO-1))then cnt(i) <= cnt(i) + 1; if(cnt(i) = x"0f")then RX_FRAMECLK_RDY_i(i) <= '0'; cnt(i) <= (others => '0'); end if; elsif(cnt(i) /= x"00")then cnt(i) <= cnt(i) - 1; end if; end if; end if; end process; gbt_rxclken_s(i) <= rx_clken_sr(i)(GBT_WORD_RATIO-3); end generate; --============-- -- Resets -- --============-- gbtBank_rst_gen: for i in 0 to 11 generate rx_reset_i(i) <= GBTBANK_MANUAL_RESET_RX_I or GBT_CHANNEL_RESET_RX_I(i); gbtBank_gbtBankRst: entity work.gbt_bank_reset generic map (INITIAL_DELAY => INITIAL_DELAY) -- * 1s port map ( GBT_CLK_I => DRPclk, TX_WORDCLK_I => tx_wordclk_i, TX_CLKEN_I => TX_CLKEN_I, RX_FRAMECLK_I => mgt_rxwordclk_s(i), RX_CLKEN_I => gbt_rxclken_s(i), MGTCLK_I => tx_wordclk_i, --===============-- -- Resets scheme -- --===============-- GENERAL_RESET_I => GBTBANK_GENERAL_RESET_I, TX_RESET_I => GBTBANK_MANUAL_RESET_TX_I, RX_RESET_I => rx_reset_i(i), MGT_TX_RESET_O => mgt_txreset_s(i), MGT_RX_RESET_O => mgt_rxreset_s(i), GBT_TX_RESET_O => gbt_txreset_s(i), GBT_RX_RESET_O => gbt_rxreset_s(i), MGT_TX_RSTDONE_I => mgt_txready_s(i), MGT_RX_RSTDONE_I => mgt_rxready_s(i) ); GBTBANK_GBTRX_READY_O(i) <= mgt_rxready_s(i) and gbt_rxready_s(i); GBTBANK_LINK_READY_O(i) <= mgt_txready_s(i) and mgt_rxready_s(i); GBTBANK_GBTTX_READY_O(i) <= not(gbt_txreset_s(i)); gbt_txdata_s(i) <= GBTBANK_GBT_DATA_I(i) when (TX_ENCODING = GBT_FRAME or (TX_ENCODING = GBT_DYNAMIC and TX_ENCODING_SEL_i(i) = '1')) else GBTBANK_WB_DATA_I(i)(115 downto 32); wb_txdata_s(i) <= GBTBANK_WB_DATA_I(i)(31 downto 0); TX_DATA_O(i) <= gbt_txdata_s(i); WB_DATA_O(i) <= gbt_txdata_s(i) & wb_txdata_s(i); end generate; gbtBank_rxdatamap_gen: for i in 0 to 11 generate GBTBANK_GBT_DATA_O(i) <= gbt_rxdata_s(i) when RX_ENCODING = GBT_FRAME else gbt_rxdata_s(i) when (RX_ENCODING = GBT_DYNAMIC and RX_ENCODING_SEL_i(i) = '1') else (others => '0'); GBTBANK_WB_DATA_O(i) <= gbt_rxdata_s(i) & wb_rxdata_s(i) when RX_ENCODING = WIDE_BUS else gbt_rxdata_s(i) & wb_rxdata_s(i) when (RX_ENCODING = GBT_DYNAMIC and RX_ENCODING_SEL_i(i) = '0') else (others => '0'); end generate; --=============-- -- Transceiver -- --=============-- RX_FRAMECLK_RDY_O <= RX_FRAMECLK_RDY_i; RX_WORDCLK_RDY_O <= mgt_rxready_s; --============-- -- GBT Bank -- --============-- i_gbt_bank : entity work.gbt_bankx12 generic map( BLK_No => BLK_No, TX_OPTIMIZATION => TX_OPTIMIZATION, RX_OPTIMIZATION => RX_OPTIMIZATION, TX_ENCODING => TX_ENCODING, RX_ENCODING => RX_ENCODING ) port map( --========-- -- Resets -- --========-- MGT_RESET_i => mgt_txreset_s(5), MGT_RXRESET_i => mgt_rxreset_s, GBT_TXRESET_i => gbt_txreset_s, GBT_RXRESET_i => gbt_rxreset_s, HPTD_RESET_i => HPTD_RESET_i, --========-- -- Clocks -- --========-- gtrefclk => gtrefclk, DRPclk => DRPclk, tx_wordclk => tx_wordclk_i, mgt_en => mgt_en, loopback => loopback, cpll_locked => cpll_locked, rxn => GBTBANK_MGT_RX_N, rxp => GBTBANK_MGT_RX_P, txn => GBTBANK_MGT_TX_N, txp => GBTBANK_MGT_TX_P, GBT_TXCLKEn_i => TX_CLKEN_I, GBT_RXCLKEn_i => gbt_rxclken_s, MGT_RXWORDCLK_o => mgt_rxwordclk_s, --================-- -- GBT TX Control -- --================-- TX_ENCODING_SEL_i => TX_ENCODING_SEL_i, GBT_ISDATAFLAG_i => GBTBANK_TX_ISDATA_SEL_I, --=================-- -- GBT TX Status -- --=================-- TX_PHCOMPUTED_o => GBTBANK_TX_ALIGNCOMPUTED_O, TX_PHALIGNED_o => GBTBANK_TX_ALIGNED_O, --================-- -- GBT RX Control -- --================-- RX_ENCODING_SEL_i => RX_ENCODING_SEL_i, --=================-- -- GBT RX Status -- --=================-- GBT_RXREADY_o => gbt_rxready_s, GBT_ISDATAFLAG_o => GBTBANK_RX_ISDATA_SEL_O, GBT_ERRORDETECTED_o => GBTBANK_RX_ERRORDETECTED_O, GBT_ERRORFLAG_o => GBTBANK_RX_BITMODIFIED_FLAG_O, --=================-- -- MGT Status -- --=================-- MGT_TXREADY_o => mgt_txready_s, --GBTBANK_LINK_TX_READY_O, MGT_RXREADY_o => mgt_rxready_s, --GBTBANK_LINK_RX_READY_O, MGT_HEADERFLAG_o => mgt_headerflag_s, MGT_RESET_TX_DONE_o => GBTBANK_RESET_TX_DONE_o, --========-- -- Data -- --========-- GBT_TXDATA_i => gbt_txdata_s, GBT_RXDATA_o => gbt_rxdata_s, WB_TXDATA_i => wb_txdata_s, WB_RXDATA_o => wb_rxdata_s ); end structural; --=================================================================================================-- --#################################################################################################-- --=================================================================================================--