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-- LUT FIFO REGISTERED:
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-- this is a N bit fifo constructed from LUT shift registers
-- it can hold up to 2^(cntr_length)-1 words
-- it takes two clocks to drop through the fifo when fifo is empty
-- when "write" is high, "din" is written to fifo.
-- when "empty" is low, dout has valid data.
-- when "read" is high, the next valid data appears one clock later at dout if
-- there are still any in the fifo. Otherwise, the last valid data stays until
-- two clocks after the next write.
-- "read" has no effect when "empty" is high
-- when cntr_lenght is set to 2, full goes one when there words are stored in the fifo
-- when cntr_lenght is set to 3, full goes one when five words are stored in the fifo
-- when cntr_lenght is set to 4, full goes one when nine words are stored in the fifo
library IEEE,synopsys;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VComponents.all;

entity srl_fiforeg is 
generic (N: integer := 16);
    port (
        rst: 	in STD_LOGIC;
        clk: 	in STD_LOGIC;
        write: in STD_LOGIC;
        read: 	in STD_LOGIC;
        din: 	in STD_LOGIC_VECTOR (N-1 downto 0);
        dout: 	out STD_LOGIC_VECTOR (N-1 downto 0);
        empty: out STD_LOGIC
    );
end srl_fiforeg;

architecture srl_fiforeg_arch of srl_fiforeg is
signal dout_i:			std_logic_vector(N-1 downto 0);
signal a:				unsigned(3 downto 0);
signal srl_re:			std_logic; 
signal empty_i:		std_logic; 
begin
g_FIFO: for i in 0 to N-1 generate
   SRL16E_inst : SRL16E
   port map (
      Q => dout_i(i),     -- 1-bit output: SRL Data
      CE => write,   -- 1-bit input: Clock enable
      CLK => clk, -- 1-bit input: Clock
      D => din(i),     -- 1-bit input: SRL Data
      -- Depth Selection inputs: A0-A3 select SRL depth
      A0 => a(0),
      A1 => a(1),
      A2 => a(2),
      A3 => a(3) 
   );
end generate g_FIFO;
srl_re <= '1' when a /= x"f" and (empty_i = '1' or read = '1') else '0';
empty <= empty_i;
process(clk)
begin
	if(clk'event and clk = '1')then
		if(rst = '1')then
			a <= (others => '1');
		elsif(write = '1' and srl_re = '0')then
			a <= a + 1;
		elsif(write = '0' and srl_re = '1')then
			a <= a - 1;
		end if;
		if(rst= '1')then
			empty_i <= '1';
		elsif(a /= x"f")then
			empty_i <= '0';
		elsif(read = '1')then
			empty_i <= '1';
		end if;
		if(empty_i = '1' or read = '1')then
			dout <= dout_i;
		end if;
	end if;
end process; 
end srl_fiforeg_arch;