---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 03/28/2019 11:41:06 AM -- Design Name: -- Module Name: ngFEC_top - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.ALL; library work; use work.ngFEC_pack.all; use work.version_package.all; use work.gbt_bank_package.all; use work.vendor_specific_gbt_bank_package.all; --use work.tcds2_interface_pkg.all; Library xpm; use xpm.vcomponents.all; library UNISIM; use UNISIM.VComponents.all; entity ngFEC_top is generic ( INITIAL_DELAY : natural := 1 * 50e6); -- generic ( INITIAL_DELAY : natural := 1 * 40); Port ( -- Si5345 control ports Si_SDA : inout std_logic; Si_SCL : inout std_logic; Si_LOLb : in std_logic; Si_IN_SEL : out std_logic_vector(1 downto 0); -- FireFly control and status ports FF_TX_SDA : inout std_logic_vector(3 downto 0); FF_TX_SCL : inout std_logic_vector(3 downto 0); FF_RX_SDA : inout std_logic_vector(3 downto 0); FF_RX_SCL : inout std_logic_vector(3 downto 0); FF_TX_RESETn : out std_logic_vector(3 downto 0); FF_RX_RESETn : out std_logic_vector(3 downto 0); FF_TX_PRESENTn : in std_logic_vector(3 downto 0); FF_RX_PRESENTn : in std_logic_vector(3 downto 0); -- board ID board_id : in std_logic_vector(6 downto 0); -- ngccm GBT ports GBT_rxn : in std_logic_vector(47 downto 0); GBT_rxp : in std_logic_vector(47 downto 0); GBT_txn : out std_logic_vector(47 downto 0); GBT_txp : out std_logic_vector(47 downto 0); GBT_refclk1_p : in std_logic_vector(3 downto 0); GBT_refclk1_n : in std_logic_vector(3 downto 0); c2c_rxn : in std_logic; c2c_rxp : in std_logic; c2c_txn : out std_logic; c2c_txp : out std_logic; refclk125_p : in std_logic; refclk125_n : in std_logic; -- TTC GBT ports TTC_rx_refclk_p : in std_logic; TTC_rx_refclk_n : in std_logic; TTC_rxn : in std_logic; TTC_rxp : in std_logic; TTC_txn : out std_logic; TTC_txp : out std_logic; TTC_rx_rcvclk_p : out std_logic; TTC_rx_rcvclk_n : out std_logic ); end ngFEC_top; architecture Behavioral of ngFEC_top is component TCDS2_if generic (SIM : boolean := true); Port ( reset : in STD_LOGIC; test : in STD_LOGIC; prbs_reset : in STD_LOGIC; loopback : in STD_LOGIC; Si_IN_SEL1 : in STD_LOGIC; ngFEC_rdy : in STD_LOGIC; clk125 : in STD_LOGIC; txrefclk_in : in STD_LOGIC; txrefclk_lock : in STD_LOGIC; rxrefclk_in : in STD_LOGIC; fabric_clk : in std_logic; fabric_clk_RST : out STD_LOGIC; fabric_clk_out : out std_logic; rx_p : in STD_LOGIC; rx_n : in STD_LOGIC; tx_p : out STD_LOGIC; tx_n : out STD_LOGIC; refclkp_out : out STD_LOGIC; refclkn_out : out STD_LOGIC; ttc2_stat : out std_logic_vector(15 downto 0); -- ttc_rx_err : out std_logic; BCntRes : out std_logic; BC0_missing : out std_logic; WTE : out std_logic; TTC_counter : out std_logic_vector(8 downto 0)); end component; component xlx_ku_gbt_ngFEC_design generic ( BLK_No : integer := 0; TX_OPTIMIZATION : integer range 0 to 1 := LATENCY_OPTIMIZED; RX_OPTIMIZATION : integer range 0 to 1 := LATENCY_OPTIMIZED; TX_ENCODING : integer range 0 to 2 := GBT_FRAME; RX_ENCODING : integer range 0 to 2 := GBT_FRAME; INITIAL_DELAY : natural := 1 * 40e6 ); port ( --==============-- -- Clocks -- --==============-- gtrefclk : in STD_LOGIC; DRPclk : in STD_LOGIC; mgt_en : in STD_LOGIC_VECTOR (11 downto 0); cpll_locked : out STD_LOGIC_VECTOR (11 downto 0); TX_CLKEN_I : in std_logic; RX_CLKEN_O : out std_logic_vector(11 downto 0); RX_WORDCLK_O : out std_logic_vector(11 downto 0); TX_WORDCLK_I : in std_logic; RX_WORDCLK_RDY_O : out std_logic_vector(11 downto 0); RX_FRAMECLK_RDY_O : out std_logic_vector(11 downto 0); --==============-- -- Reset -- --==============-- GBTBANK_GENERAL_RESET_I : in std_logic; GBTBANK_MANUAL_RESET_TX_I : in std_logic; GBTBANK_MANUAL_RESET_RX_I : in std_logic; GBT_CHANNEL_RESET_RX_I : in std_logic_vector(11 downto 0); HPTD_RESET_I : in std_logic_vector(11 downto 0); --==============-- -- Serial lanes -- --==============-- GBTBANK_MGT_RX_P : in std_logic_vector(11 downto 0); GBTBANK_MGT_RX_N : in std_logic_vector(11 downto 0); GBTBANK_MGT_TX_P : out std_logic_vector(11 downto 0); GBTBANK_MGT_TX_N : out std_logic_vector(11 downto 0); --==============-- -- Data -- --==============-- GBTBANK_GBT_DATA_I : in gbt_reg84_A(11 downto 0); GBTBANK_WB_DATA_I : in gbt_reg116_A(11 downto 0); TX_DATA_O : out gbt_reg84_A(11 downto 0); WB_DATA_O : out gbt_reg116_A(11 downto 0); GBTBANK_GBT_DATA_O : out gbt_reg84_A(11 downto 0); GBTBANK_WB_DATA_O : out gbt_reg116_A(11 downto 0); --==============-- -- TX ctrl -- --==============-- TX_ENCODING_SEL_i : in std_logic_vector(11 downto 0); --! Select the Tx encoding in dynamic mode ('1': GBT / '0': WideBus) GBTBANK_TX_ISDATA_SEL_I : in std_logic_vector(11 downto 0); --==============-- -- RX ctrl -- --==============-- RX_ENCODING_SEL_i : in std_logic_vector(11 downto 0); --! Select the Rx encoding in dynamic mode ('1': GBT / '0': WideBus) --==============-- -- TX Status -- --==============-- GBTBANK_GBTTX_READY_O : out std_logic_vector(11 downto 0); GBTBANK_LINK_READY_O : out std_logic_vector(11 downto 0); GBTBANK_TX_ALIGNED_O : out std_logic_vector(11 downto 0); GBTBANK_TX_ALIGNCOMPUTED_O : out std_logic_vector(11 downto 0); GBTBANK_RESET_TX_DONE_O : out std_logic_vector(11 downto 0); --==============-- -- RX Status -- --==============-- GBTBANK_GBTRX_READY_O : out std_logic_vector(11 downto 0); GBTBANK_RX_ISDATA_SEL_O : out std_logic_vector(11 downto 0); GBTBANK_RX_ERRORDETECTED_O : out std_logic_vector(11 downto 0); GBTBANK_RX_BITMODIFIED_FLAG_O : out gbt_reg84_A(11 downto 0); --==============-- -- XCVR ctrl -- --==============-- LOOPBACK : in std_logic_vector(2 downto 0) ); end component; component DSP_dividerX2 generic (use_sync : std_logic_vector(1 downto 0) := "11"; pattern : std_logic_vector(23 downto 0) := x"000000"; mask : std_logic_vector(23 downto 0) := x"ff8000"); Port ( clk : in STD_LOGIC; ipb_clk : in STD_LOGIC; q : out STD_LOGIC; din : in STD_LOGIC_VECTOR(1 downto 0); rate : out STD_LOGIC_VECTOR(23 downto 0)); end component; component DSP_dividerX3 generic (use_sync : std_logic_vector(2 downto 0) := "111"; pattern : std_logic_vector(15 downto 0) := x"0000"; mask : std_logic_vector(15 downto 0) := x"8000"); Port ( clk : in STD_LOGIC; ipb_clk : in STD_LOGIC; q : out STD_LOGIC; din : in STD_LOGIC_VECTOR(2 downto 0); rate : out STD_LOGIC_VECTOR(31 downto 0)); end component; component DSP_rate_counterX3 generic (use_sync : std_logic_vector(2 downto 0) := "111"); Port ( clk : in STD_LOGIC; ipb_clk : in STD_LOGIC; load : in STD_LOGIC; din : in STD_LOGIC_VECTOR(2 downto 0); rate : out STD_LOGIC_VECTOR(47 downto 0)); end component; component axi_chip2chip_slave Port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; axi_in : IN axi_rbus; axi_out : OUT axi_wbus; axi_c2c_s2m_intr_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0); axi_c2c_m2s_intr_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); slave_status : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); refclk1_in : IN STD_LOGIC; DRP_clk : IN STD_LOGIC; c2c_calib_done : OUT STD_LOGIC; txp : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); txn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); rxp : IN STD_LOGIC_VECTOR(0 DOWNTO 0); rxn : IN STD_LOGIC_VECTOR(0 DOWNTO 0) ); end component; component AXI4_to_ipbus Generic (aclk_period : integer := 8); -- unit in ns Port ( c2c_link_up : in std_logic; aclk : in STD_LOGIC; aresetn : in STD_LOGIC; axi_in : in axi_wbus; axi_out : out axi_rbus; ipb_clk : in std_logic; ipb_in : in ipb_rbus; ipb_out : out ipb_wbus; axi_status : out std_logic_vector(31 DOWNTO 0) ); end component; component I2C_if GENERIC ( WAIT_STATES : INTEGER := 10); Port ( ipb_clk : in STD_LOGIC; ipb_reset : in STD_LOGIC; local_reset : in std_logic_vector(8 downto 0); -- i2c_clk_en : in std_logic_vector(8 downto 0); prescale : in std_logic_vector(31 downto 0); Si_SDA : inout std_logic; Si_SCL : inout std_logic; FF_TX_SDA : inout std_logic_vector(3 downto 0); FF_TX_SCL : inout std_logic_vector(3 downto 0); FF_RX_SDA : inout std_logic_vector(3 downto 0); FF_RX_SCL : inout std_logic_vector(3 downto 0); ipb_mosi : in ipb_wbus; ipb_miso : out ipb_rbus); end component; COMPONENT delay_counter GENERIC( orbit : INTEGER range 0 to 4095 ); PORT( din : IN std_logic; shift_i : IN std_logic_vector(11 downto 0); clk_i : IN std_logic; reset_i : IN std_logic; dout : OUT std_logic); END COMPONENT; COMPONENT ipb_user_status_regs generic (sim : boolean := false); Port ( clk : in STD_LOGIC; ipb_clk : in STD_LOGIC; ipb_rst : in STD_LOGIC; reset_ctrl : in STD_LOGIC_VECTOR (31 downto 0); cntr_din : in STD_LOGIC_VECTOR (511 downto 0); rate_din : in STD_LOGIC_VECTOR (255 downto 0); stat_reg : in array_1024x32bit; ipb_mosi_i : in ipb_wbus; ipb_miso_o : out ipb_rbus); END COMPONENT; signal Si_IN_SEL_i : std_logic_vector(1 downto 0); signal TTC_rx_refclk : std_logic; signal TTC_clk_oddr : std_logic; signal refclk125 : std_logic; signal refclk125_o : std_logic; signal refclk125_buf : std_logic; signal GBT_refclk : std_logic_vector(3 downto 0); signal clk125_dcm : std_logic; signal clk125 : std_logic; signal clk125_MMCM_locked : std_logic; signal aresetn : std_logic; signal axi_in : axi_rbus; signal axi_out : axi_wbus; signal ipb_in : ipb_rbus; signal ipb_out : ipb_wbus; signal c2c_calib_done : std_logic; signal WTE : std_logic; signal BCntRes : std_logic; signal BC0_missing : std_logic; signal ipb_rst : std_logic; signal cntr_din : std_logic_vector(511 downto 0) := (others => '0'); signal rate_din : std_logic_vector(255 downto 0) := (others => '0'); signal reset_gbtbank_tx : std_logic_vector(3 downto 0); signal reset_gbtbank_rx : std_logic_vector(3 downto 0); signal reset_gbtbank : std_logic_vector(3 downto 0); signal QIE_RESET : std_logic_vector(47 downto 0); signal channel_mgt_rxreset : std_logic_vector(47 downto 0); signal channel_err_reset : std_logic_vector(47 downto 0); signal HPTD_reset : std_logic_vector(47 downto 0); signal GBTBANK_RESET_TX_DONE : std_logic_vector(47 downto 0); signal shift : array_KNUM_SFPSx12; signal reset_ttc : std_logic; signal ipb_clk_dcm : std_logic; signal ipb_clk : std_logic; signal CLKFBIN : std_logic; signal CLKFBOUT : std_logic; signal fabric_clk : std_logic; signal fabric_clk_div2 : std_logic := '0'; signal fabric_clk_div2_q : std_logic_vector(4 downto 0) := (others => '0'); signal TX_CLKEN : std_logic; signal fabric_clk_in_stopped : std_logic; signal fabric_clk_fb_stopped : std_logic; signal fabric_clk_in : std_logic; signal fabric_clk_dcm : std_logic; signal fabric_clk_LOCKED : std_logic; signal fabric_clk_LOCK_lost : std_logic_vector(1 downto 0); signal fabric_clk_LOCK_lost_cnt : std_logic; signal fabric_clk_RST : std_logic := '0'; signal update_toggle : std_logic := '0'; signal update_status : std_logic := '0'; signal update_toggle_Sync_Regs : std_logic_vector(3 downto 0) := (others => '0'); signal DRPclk_dcm : std_logic; signal DRPclk : std_logic; signal axi_status : std_logic_vector(31 downto 0); signal c2c_status : std_logic_vector(31 downto 0); signal ipb_mosi : ipb_wbus_array(0 to nbr_usr_slaves-1); signal ipb_miso : ipb_rbus_array(0 to nbr_usr_slaves-1); signal ngccm_mosi : ipb_sfp_in; signal ngccm_miso : ipb_sfp_out; signal ctrl_reg : array_128x32bit := (others => (others => '0')); signal stat_reg : array_1024x32bit := (others => (others => '0')); signal I2C_prescale : std_logic_vector(31 downto 0) := (others => '0'); signal prescale_cnt : unsigned(15 downto 0); signal i2c_clk_en : std_logic; signal mgt_en : std_logic_vector(47 downto 0) := (others => '0'); signal cpll_locked : std_logic_vector(47 downto 0); signal rx_frameclk_locked_Sync : std_logic_vector(47 downto 0); signal RxFrame_locked : std_logic_vector(47 downto 0); signal rx_frameclk_lock_lost_cnt : std_logic_vector(47 downto 0) := (others => '0'); signal rx_wordclk_locked : std_logic_vector(47 downto 0); signal rx_wordclk : std_logic_vector(47 downto 0); signal rx_wordclk_div2 : std_logic_vector(47 downto 0) := (others => '0'); signal rx_frameclk_div2 : std_logic_vector(47 downto 0) := (others => '0'); signal tx_wordclk : std_logic; signal tx_wordclk_dcm : std_logic; signal tx_wordclk_div2 : std_logic := '0'; signal RxFrame_ce : std_logic_vector(47 downto 0); signal rx_ready : std_logic_vector(47 downto 0); signal tx_ready : std_logic_vector(47 downto 0); signal tx_ready_sync : std_logic_vector(47 downto 0); signal tx_not_ready_cnt : std_logic_vector(47 downto 0) := (others => '0'); signal rx_data_valid : std_logic_vector(47 downto 0); signal rx_data_valid_r : std_logic_vector(47 downto 0); signal rx_rs_err_o : std_logic_vector(47 downto 0); signal rx_rs_err : std_logic_vector(47 downto 0); signal rx_rs_err_cnt : std_logic_vector(47 downto 0) := (others => '0'); signal PRBS_err_cnt : std_logic_vector(47 downto 0) := (others => '0'); signal prbs_o : STD_LOGIC_VECTOR(set_prbs_tabs(HBHE,20)'high downto 0); signal ngccm_rx_down_cnt : std_logic_vector(47 downto 0) := (others => '0'); signal TimeoutErrorCnt : std_logic_vector(47 downto 0) := (others => '0'); signal TCK_inCnt : std_logic_vector(47 downto 0) := (others => '0'); signal TCK_outCnt : std_logic_vector(47 downto 0) := (others => '0'); signal pwr_good_cnt : std_logic_vector(47 downto 0) := (others => '0'); signal mgt_ready : std_logic_vector(47 downto 0); signal rx_data : gbt_reg84_A(47 downto 0); signal rx_data_ngccm : gbt_reg84_A(47 downto 0); signal tx_data : gbt_reg84_A(47 downto 0); signal sfp_rx_locked_and_ready : std_logic_vector(47 downto 0); signal rx_test_comm_cnt : std_logic_vector(47 downto 0) := (others => '0'); signal clk200_dcm : std_logic; signal clk200 : std_logic; signal clk250_dcm : std_logic; signal clk250 : std_logic; signal err_reset : std_logic; signal ngccm_status_reset : std_logic; type array8X16 is array(0 to 7) of std_logic_vector(15 downto 0); type arraykNUM_SFPSX8 is array(47 downto 0) of std_logic_vector(7 downto 0); type arraykNUM_SFPSX16 is array(47 downto 0) of std_logic_vector(15 downto 0); type arraykNUM_SFPSX24 is array(47 downto 0) of std_logic_vector(23 downto 0); type arraykNUM_SFPSX32 is array(47 downto 0) of std_logic_vector(31 downto 0); type arraykNUM_SFPSX8X16 is array(47 downto 0) of array8X16; signal ngccm_status_cnt : arrayKNUM_SFPSX8 := (others => (others => '0')); signal ngCCM_status : arraykNUM_SFPSX16 := (others => (others => '0')); signal rate_test_comm : arraykNUM_SFPSX24 := (others => (others => '0')); signal rate_ngccm_status : arraykNUM_SFPSX8X16; signal ngccm_status_reg : arraykNUM_SFPSX32 := (others => (others => '0')); signal ngccm_bkp_reg : arraykNUM_SFPSX32 := (others => (others => '0')); signal ngccm_status_load : std_logic_vector(47 downto 0); signal i2c_reset : std_logic_vector(8 downto 0) := (others => '0'); --signal board_i2c_clk_en : std_logic_vector(8 downto 0) := (others => '0'); signal loopback : std_logic_vector(2 downto 0) := (others => '0'); begin Si_IN_SEL <= Si_IN_SEL_i; Si_IN_SEL_i <= "00" when ctrl_reg(1)(1) = '1' else "01" when ctrl_reg(1)(0) = '1' else "10"; FF_TX_RESETn <= not ctrl_reg(8)(7 downto 4); FF_RX_RESETn <= not ctrl_reg(8)(3 downto 0); I2C_reset <= ctrl_reg(8)(24 downto 16); I2C_prescale <= ctrl_reg(2); -- the same I2C clk prescale loopback <= ctrl_reg(1)(18 downto 16); --===========================================-- -- status register mapping --===========================================-- process(ipb_clk) begin if(ipb_clk'event and ipb_clk = '1')then stat_reg(3)(0) <= fabric_clk_LOCKED; stat_reg(3)(1) <= fabric_clk_in_stopped; stat_reg(3)(2) <= fabric_clk_fb_stopped; stat_reg(3)(3) <= BC0_missing; stat_reg(3)(4) <= Si_LOLb; stat_reg(3)(19 downto 16) <= FF_RX_PRESENTn; stat_reg(3)(23 downto 20) <= FF_TX_PRESENTn; stat_reg(3)(30 downto 24) <= board_id; for i in 0 to 47 loop stat_reg(KNUM_SFPS+i)(0) <= rx_data_valid(i); stat_reg(KNUM_SFPS+i)(1) <= RxFrame_locked(i); stat_reg(KNUM_SFPS+i)(2) <= rx_wordclk_locked(i); stat_reg(KNUM_SFPS+i)(3) <= rx_ready(i); stat_reg(KNUM_SFPS+i)(4) <= mgt_ready(i); stat_reg(KNUM_SFPS+i)(5) <= tx_ready(i); stat_reg(KNUM_SFPS+i)(6) <= cpll_locked(i); stat_reg(KNUM_SFPS+i)(7) <= GBTBANK_RESET_TX_DONE(i); stat_reg(2*KNUM_SFPS+i) <= ngccm_bkp_reg(i); stat_reg(3*KNUM_SFPS+i) <= ngccm_status_reg(i); end loop; end if; end process; stat_reg(0) <= firmware_ver; --x"fec1_0429"; stat_reg(1) <= creation_date; --x"0510_2018"; stat_reg(2)(0) <= ctrl_reg(1)(0); g_stat_reg : for i in 0 to 47 generate g_rate_ngccm_status : for j in 0 to 7 generate stat_reg(j*KNUM_SFPS+i+512) <= x"0000" & rate_ngccm_status(i)(j); end generate g_rate_ngccm_status; stat_reg(8*KNUM_SFPS+i+521) <= x"0000" & rate_test_comm(i)(15 downto 0); end generate g_stat_reg; i_GBT_refclk0_ibuf : IBUFDS_GTE3 port map (i => GBT_refclk1_p(0), ib => GBT_refclk1_n(0), ceb => '0', o => GBT_refclk(0), odiv2 => open); i_GBT_refclk1_ibuf : IBUFDS_GTE3 port map (i => GBT_refclk1_p(1), ib => GBT_refclk1_n(1), ceb => '0', o => GBT_refclk(1), odiv2 => open); i_GBT_refclk2_ibuf : IBUFDS_GTE3 port map (i => GBT_refclk1_p(2), ib => GBT_refclk1_n(2), ceb => '0', o => GBT_refclk(2), odiv2 => open); i_GBT_refclk3_ibuf : IBUFDS_GTE3 port map (i => GBT_refclk1_p(3), ib => GBT_refclk1_n(3), ceb => '0', o => GBT_refclk(3), odiv2 => open); i_refclk125_ibuf : IBUFDS_GTE3 port map (i => refclk125_p, ib => refclk125_n, ceb => '0', o => refclk125, odiv2 => refclk125_o); i_TTC_rx_refclk_ibuf : IBUFDS_GTE3 port map (i => TTC_rx_refclk_p, ib => TTC_rx_refclk_n, ceb => '0', o => TTC_rx_refclk); i_clk125_MMCM : MMCME3_BASE generic map ( BANDWIDTH => "OPTIMIZED", -- Jitter programming CLKFBOUT_MULT_F => 8.0, -- Multiply value for all CLKOUT CLKIN1_PERIOD => 8.0, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz). CLKOUT0_DIVIDE_F => 20.0, -- Divide amount for CLKOUT0 CLKOUT1_DIVIDE => 5, -- Divide amount for CLKOUT (1-128) CLKOUT2_DIVIDE => 32, -- Divide amount for CLKOUT (1-128) CLKOUT3_DIVIDE => 4 -- Divide amount for CLKOUT (1-128) ) port map ( CLKFBOUT => clk125_dcm, -- 1-bit output: Feedback clock CLKOUT0 => DRPclk_dcm, -- 1-bit output: General Clock output CLKOUT1 => clk200_dcm, -- 1-bit output: General Clock output CLKOUT2 => ipb_clk_dcm, -- 1-bit output: General Clock output CLKOUT3 => clk250_dcm, -- 1-bit output: General Clock output LOCKED => clk125_MMCM_locked, -- 1-bit output: LOCK CLKFBIN => clk125, -- 1-bit input: Feedback clock CLKIN1 => refclk125_buf, -- 1-bit input: Input clock PWRDWN => '0', -- 1-bit input: Power-down RST => '0' -- 1-bit input: Reset ); i_refclk125_bufg : bufg_gt port map(i => refclk125_o, o => refclk125_buf, ce => '1', div => "000", clr => '0', clrmask => '0', cemask => '0'); i_clk125_bufg : bufg port map(i => clk125_dcm, o => clk125); i_clk200_bufg : bufg port map(i => clk200_dcm, o => clk200); i_clk250_bufg : bufg port map(i => clk250_dcm, o => clk250); i_DRPclk_bufg : bufg port map(i => DRPclk_dcm, o => DRPclk); i_ipb_clk_bufg : bufg port map(i => ipb_clk_dcm, o => ipb_clk); aresetn <= clk125_MMCM_LOCKED; i_axi_slave : axi_chip2chip_slave Port map( aclk => clk125, aresetn => aresetn, axi_in => axi_in, axi_out => axi_out, axi_c2c_s2m_intr_in => (others => '0'), axi_c2c_m2s_intr_out => open, slave_status => c2c_status, refclk1_in => refclk125, DRP_clk => DRPclk, c2c_calib_done => c2c_calib_done, rxp(0) => c2c_rxp, rxn(0) => c2c_rxn, txp(0) => c2c_txp, txn(0) => c2c_txn ); i_AXI4_to_ipbus : AXI4_to_ipbus Port map( aclk => clk125, aresetn => aresetn, c2c_link_up => c2c_calib_done, axi_in => axi_out, axi_out => axi_in, ipb_clk => ipb_clk, ipb_in => ipb_in, ipb_out => ipb_out, axi_status => axi_status ); ipb_rst <= not c2c_calib_done; ipb_fabric: entity work.ipbus_fabric --===================================-- generic map ( n_usr_slv => nbr_usr_slaves ) port map ( ipb_clk => ipb_clk, rst => ipb_rst, ------------------ ipb_in => ipb_out, ipb_out => ipb_in, ------------------ ipb_to_slaves => ipb_mosi, ipb_from_slaves => ipb_miso ); stat_regs_inst : ipb_user_status_regs --===========================================-- port map ( clk => clk250, ipb_clk => ipb_clk, ipb_rst => ipb_rst, reset_ctrl => ctrl_reg(7), cntr_din => cntr_din, rate_din => rate_din, stat_reg => stat_reg, ipb_mosi_i => ipb_mosi(user_ipb_stat_regs), ipb_miso_o => ipb_miso(user_ipb_stat_regs) ); --===========================================-- --===========================================-- ctrl_regs_inst: entity work.ipb_user_control_regs --===========================================-- port map ( clk => ipb_clk, reset => ipb_rst, ipb_mosi_i => ipb_mosi(user_ipb_ctrl_regs), ipb_miso_o => ipb_miso(user_ipb_ctrl_regs), regs_o => ctrl_reg ); fabric_clk_MMCM : MMCME3_ADV generic map ( BANDWIDTH => "OPTIMIZED", -- Jitter programming (OPTIMIZED, HIGH, LOW) CLKFBOUT_MULT_F => 18.0, -- Multiply value for all CLKOUT (2.000-64.000). CLKFBOUT_PHASE => 90.0, -- Phase offset in degrees of CLKFB (-360.000-360.000) CLKIN1_PERIOD => 24.95, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz). CLKOUT0_DIVIDE_F => 18.0, -- Divide amount for CLKOUT0 (1.000-128.000). CLKOUT1_DIVIDE => 6 -- Divide amount for CLKOUT (1-128) ) port map ( -- Clock Outputs: 1-bit (each) output: User configurable clock outputs CLKFBSTOPPED => fabric_clk_fb_stopped, -- 1-bit output: Feedback clock stopped CLKINSTOPPED => fabric_clk_in_stopped, -- 1-bit output: Input clock stopped CLKFBOUT => CLKFBOUT, -- 1-bit output: Feedback clock CLKOUT0 => fabric_clk_dcm, -- 1-bit output: CLKOUT0 CLKOUT1 => tx_wordclk_dcm, -- 1-bit output: CLKOUT1 -- DRP Ports: 16-bit (each) output: Dynamic reconfiguration ports -- Dynamic Phase Shift Ports: 1-bit (each) output: Ports used for dynamic phase shifting of the outputs PSDONE => open, -- 1-bit output: Phase shift done -- Feedback Clocks: 1-bit (each) output: Clock feedback ports -- Status Ports: 1-bit (each) output: MMCM status ports LOCKED => fabric_clk_LOCKED, -- 1-bit output: LOCK CDDCREQ => '0', -- 1-bit input: Request to dynamic divide clock -- Clock Inputs: 1-bit (each) input: Clock inputs CLKIN1 => fabric_clk_in, -- 1-bit input: Primary clock CLKIN2 => '0', -- 1-bit input: Secondary clock -- Control Ports: 1-bit (each) input: MMCM control ports CLKINSEL => '1', -- 1-bit input: Clock select, High=CLKIN1 Low=CLKIN2 PWRDWN => '0', -- 1-bit input: Power-down RST => fabric_clk_RST, -- 1-bit input: Reset -- DRP Ports: 7-bit (each) input: Dynamic reconfiguration ports DADDR => (others => '0'), -- 7-bit input: DRP address DCLK => '0', -- 1-bit input: DRP clock DEN => '0', -- 1-bit input: DRP enable DI => (others => '0'), -- 16-bit input: DRP data DWE => '0', -- 1-bit input: DRP write enable -- Dynamic Phase Shift Ports: 1-bit (each) input: Ports used for dynamic phase shifting of the outputs PSCLK => '0', -- 1-bit input: Phase shift clock PSEN => '0', -- 1-bit input: Phase shift enable PSINCDEC => '0', -- 1-bit input: Phase shift increment/decrement -- Feedback Clocks: 1-bit (each) input: Clock feedback ports CLKFBIN => CLKFBIN -- 1-bit input: Feedback clock ); CLKFBOUT_bufg: bufg port map (i => CLKFBOUT, o => CLKFBIN); fabric_clk_bufg: bufg port map (i => fabric_clk_dcm, o => fabric_clk); tx_wordclk_bufg: bufg port map (i => tx_wordclk_dcm, o => tx_wordclk); g_clock_rate_din : for i in 0 to 47 generate process(rx_wordclk(i)) begin if(rx_wordclk(i)'event and rx_wordclk(i) = '1')then rx_wordclk_div2(i) <= not rx_wordclk_div2(i); if(RxFrame_ce(i) = '1')then rx_frameclk_div2(i) <= not rx_frameclk_div2(i); if(ngccm_status(i)(15) = '1')then rx_test_comm_cnt(i) <= not rx_test_comm_cnt(i); for j in 0 to 8 loop if(j < 5 and ngccm_status(i)(j) = '0')then ngccm_status_cnt(i)(j) <= not ngccm_status_cnt(i)(j); end if; if(j > 5 and ngccm_status(i)(j) = '0')then ngccm_status_cnt(i)(j-1) <= not ngccm_status_cnt(i)(j-1); end if; end loop; end if; end if; end if; end process; i_rate_ngccm_status0: DSP_dividerX3 PORT MAP ( clk => clk250, ipb_clk => ipb_clk, din(0) => rx_test_comm_cnt(i), din(1) => ngccm_status_cnt(i)(0), din(2) => ngccm_status_cnt(i)(1), q => ngccm_status_load(i), rate(15 downto 0) => rate_ngccm_status(i)(0), rate(31 downto 16) => rate_ngccm_status(i)(1) ); i_rate_ngccm_status1: DSP_rate_counterX3 PORT MAP ( clk => clk250, ipb_clk => ipb_clk, load => ngccm_status_load(i), din(0) => ngccm_status_cnt(i)(2), din(1) => ngccm_status_cnt(i)(3), din(2) => ngccm_status_cnt(i)(4), rate(15 downto 0) => rate_ngccm_status(i)(2), rate(31 downto 16) => rate_ngccm_status(i)(3), rate(47 downto 32) => rate_ngccm_status(i)(4)); i_rate_ngccm_status2: DSP_rate_counterX3 PORT MAP ( clk => clk250, ipb_clk => ipb_clk, load => ngccm_status_load(i), din(0) => ngccm_status_cnt(i)(5), din(1) => ngccm_status_cnt(i)(6), din(2) => ngccm_status_cnt(i)(7), rate(15 downto 0) => rate_ngccm_status(i)(5), rate(31 downto 16) => rate_ngccm_status(i)(6), rate(47 downto 32) => rate_ngccm_status(i)(7)); i_rate_test_comm: DSP_dividerX2 PORT MAP ( clk => clk250, ipb_clk => ipb_clk, din(0) => rx_frameclk_div2(i), din(1) => rx_test_comm_cnt(i), q => open, rate => rate_test_comm(i)); end generate g_clock_rate_din; process(tx_wordclk) begin if(tx_wordclk'event and tx_wordclk = '1')then tx_wordclk_div2 <= not tx_wordclk_div2; end if; end process; i_tx_wordclk_rate : rate_din(2*KNUM_SFPS) <= tx_wordclk_div2; g_rate_din : for i in 0 to 47 generate i_rx_wordclk_rate : rate_din(i) <= rx_wordclk_div2(i); i_rx_frameclk_rate : rate_din(KNUM_SFPS+i) <= rx_frameclk_div2(i); end generate g_rate_din; rate_din(144) <= fabric_clk_div2; process(fabric_clk) begin if(fabric_clk'event and fabric_clk = '1')then fabric_clk_div2 <= not fabric_clk_div2; end if; end process; g_rx_rs_err: for i in 0 to 47 generate process(rx_wordclk,ipb_rst, err_reset) begin if(ipb_rst = '1' or err_reset = '1')then rx_rs_err(i) <= '0'; elsif(rx_wordclk(i)'event and rx_wordclk(i) = '1')then if(RxFrame_ce(i) = '1' and rx_rs_err_o(i) = '1')then rx_rs_err(i) <= '1'; end if; end if; end process; process(rx_wordclk) begin if(rx_wordclk(i)'event and rx_wordclk(i) = '1')then if(RxFrame_ce(i) = '1' and rx_rs_err_o(i) = '1')then rx_rs_err_cnt(i) <= not rx_rs_err_cnt(i); end if; end if; end process; end generate g_rx_rs_err; process(fabric_clk) begin if(fabric_clk'event and fabric_clk = '1')then if (prescale_cnt = 0) then prescale_cnt <= unsigned(i2c_prescale(15 downto 0)); i2c_clk_en <= '1'; else prescale_cnt <= prescale_cnt - 1; i2c_clk_en <= '0'; end if; end if; end process; reset_ttc <= ctrl_reg(0)(14) or ipb_rst; i_tcds2_if : TCDS2_if generic map(SIM => false) port map( reset => reset_ttc, test => ctrl_reg(1)(2), prbs_reset => ctrl_reg(0)(13), loopback => ctrl_reg(1)(0), Si_IN_SEL1 => Si_IN_SEL_i(1), clk125 => clk125, txrefclk_in => GBT_refclk(0), txrefclk_lock => Si_LOLb, rxrefclk_in => TTC_rx_refclk, fabric_clk => fabric_clk, fabric_clk_RST => fabric_clk_RST, fabric_clk_out => fabric_clk_in, ngFEC_rdy => ctrl_reg(1)(3), rx_p => TTC_rxp, rx_n => TTC_rxn, tx_p => TTC_txp, tx_n => TTC_txn, refclkp_out => TTC_rx_rcvclk_p, refclkn_out => TTC_rx_rcvclk_n, ttc2_stat => open, -- ttc_rx_err => open, BCntRes => BCntRes, BC0_missing => open, WTE => open, TTC_counter => cntr_din(440 downto 432) ); cntr_din(441) <= fabric_clk_LOCK_lost_cnt; g_cntr_din : for i in 0 to 47 generate i_rx_rs_err_cntr : cntr_din(i) <= rx_rs_err_cnt(i); i_PRBS_err_cntr : cntr_din(KNUM_SFPS+i) <= PRBS_err_cnt(i); i_ngccm_rx_down_cntr : cntr_din(2*KNUM_SFPS+i) <= ngccm_rx_down_cnt(i); i_TimeoutErrorCntr : cntr_din(3*KNUM_SFPS+i) <= TimeoutErrorCnt(i); i_TCK_inCntr : cntr_din(4*KNUM_SFPS+i) <= TCK_inCnt(i); i_TCK_outCntr : cntr_din(5*KNUM_SFPS+i) <= TCK_outCnt(i); i_pwr_good_cntr : cntr_din(6*KNUM_SFPS+i) <= pwr_good_cnt(i); i_rx_frameclk_lock_lost_cntr : cntr_din(7*KNUM_SFPS+i) <= rx_frameclk_lock_lost_cnt(i); i_tx_not_ready_cntr : cntr_din(8*KNUM_SFPS+i) <= tx_not_ready_cnt(i); end generate g_cntr_din; g_shift : for i in 0 to 47 generate shift(i) <= ctrl_reg(44+i/2)((i mod 2)*16+11 downto (i mod 2)*16); end generate g_shift; process(tx_wordclk) begin if(tx_wordclk'event and tx_wordclk = '1')then fabric_clk_div2_q <= fabric_clk_div2_q(3 downto 0) & fabric_clk_div2; TX_CLKEN <= fabric_clk_div2_q(4) xor fabric_clk_div2_q(3); end if; end process; g_gbt_bank : for i in 0 to 3 generate gbtbank: xlx_ku_gbt_ngFEC_design generic map(BLK_No => i, RX_OPTIMIZATION => STANDARD, INITIAL_DELAY => INITIAL_DELAY) port map ( --==============-- -- Clocks -- --==============-- gtrefclk => GBT_refclk(i), DRPclk => DRPclk, TX_WORDCLK_I => tx_wordclk, mgt_en => mgt_en(i*12+11 downto i*12), cpll_locked => cpll_locked(i*12+11 downto i*12), TX_CLKEN_I => TX_CLKEN, RX_CLKEN_O => RxFrame_ce(i*12+11 downto i*12), RX_WORDCLK_O => rx_wordclk(i*12+11 downto i*12), RX_WORDCLK_RDY_O => rx_wordclk_locked(i*12+11 downto i*12), RX_FRAMECLK_RDY_O => RxFrame_locked(i*12+11 downto i*12), --==============-- -- Reset -- --==============-- GBTBANK_GENERAL_RESET_I => reset_gbtbank(i), GBTBANK_MANUAL_RESET_TX_I => reset_gbtbank_tx(i), GBTBANK_MANUAL_RESET_RX_I => reset_gbtbank_rx(i), GBT_CHANNEL_RESET_RX_I => channel_mgt_rxreset(i*12+11 downto i*12), HPTD_RESET_I => HPTD_reset(i*12+11 downto i*12), --==============-- -- Serial lanes -- --==============-- GBTBANK_MGT_RX_P => GBT_rxp(i*12+11 downto i*12), GBTBANK_MGT_RX_N => GBT_rxn(i*12+11 downto i*12), GBTBANK_MGT_TX_P => GBT_txp(i*12+11 downto i*12), GBTBANK_MGT_TX_N => GBT_txn(i*12+11 downto i*12), --==============-- -- Data -- --==============-- GBTBANK_GBT_DATA_I => tx_data(i*12+11 downto i*12), GBTBANK_WB_DATA_I => (others => (others => '0')), TX_DATA_O => open, WB_DATA_O => open, GBTBANK_GBT_DATA_O => rx_data(i*12+11 downto i*12), GBTBANK_WB_DATA_O => open, --==============-- -- TX ctrl -- --==============-- TX_ENCODING_SEL_i => (others=> '1'), GBTBANK_TX_ISDATA_SEL_I => (others=> '1'), --==============-- -- RX ctrl -- --==============-- RX_ENCODING_SEL_i => (others=> '1'), --==============-- -- TX Status -- --==============-- GBTBANK_GBTTX_READY_O => tx_ready(i*12+11 downto i*12), GBTBANK_LINK_READY_O => mgt_ready(i*12+11 downto i*12), GBTBANK_TX_ALIGNED_O => open, GBTBANK_TX_ALIGNCOMPUTED_O => open, GBTBANK_RESET_TX_DONE_O => GBTBANK_RESET_TX_DONE(i*12+11 downto i*12), --==============-- -- RX Status -- --==============-- GBTBANK_GBTRX_READY_O => rx_ready(i*12+11 downto i*12), GBTBANK_RX_ISDATA_SEL_O => rx_data_valid(i*12+11 downto i*12), GBTBANK_RX_ERRORDETECTED_O => rx_rs_err_o(i*12+11 downto i*12), GBTBANK_RX_BITMODIFIED_FLAG_O => open, --==============-- -- XCVR ctrl -- --==============-- LOOPBACK => loopback ); end generate g_gbt_bank; g_bank_reset : for i in 0 to 3 generate reset_gbtbank(i) <= ctrl_reg(0)(i) or ipb_rst or not fabric_clk_LOCKED; reset_gbtbank_tx(i) <= ctrl_reg(0)(i+4); reset_gbtbank_rx(i) <= ctrl_reg(0)(i+8); end generate g_bank_reset; err_reset <= ctrl_reg(0)(12); ngccm_status_reset <= ctrl_reg(0)(15); i_prbs: entity work.prbs generic map(seed => set_initialValue(HBHE,20,inv_prbs_seed(HBHE,20)),inverter=>inv_prbs_seed(HBHE,20),hbhehf=>HBHE) port map ( prbs_o => prbs_o, clk => fabric_clk, clk_en => fabric_clk_div2, reset => ipb_rst ); SFP_GEN : FOR sfp IN 0 to 47 GENERATE mgt_en(sfp) <= not ctrl_reg(3)(sfp) when sfp < 32 else not ctrl_reg(4)(sfp-32); channel_mgt_rxreset(sfp) <= ctrl_reg(5)(sfp) when sfp < 32 else ctrl_reg(6)(sfp-32); HPTD_reset(sfp) <= ctrl_reg(9)(sfp) when sfp < 32 else ctrl_reg(10)(sfp-32); sfp_rx_locked_and_ready(sfp) <= RxFrame_locked(sfp) and rx_ready(sfp); RX_Word_inst : PROCESS (rx_wordclk(sfp), channel_mgt_rxreset) BEGIN IF (channel_mgt_rxreset(sfp) = '1') THEN rx_data_valid_r(sfp) <= '0'; rx_data_ngccm(sfp) <= (OTHERS => '0'); ELSIF rising_edge(rx_wordclk(sfp)) THEN -- rising clock edge IF(RxFrame_ce(sfp) = '1') THEN -- rising clock edge rx_data_valid_r(sfp) <= rx_data_valid(sfp); IF (rx_data_valid(sfp) = '1' and sfp_rx_locked_and_ready(sfp) = '1' ) THEN rx_data_ngccm(sfp) <= rx_data(sfp); END IF; END IF; END IF; END PROCESS RX_Word_inst; RX_cntr_inst : PROCESS (rx_wordclk) BEGIN IF rising_edge(rx_wordclk(sfp)) THEN -- rising clock edge IF(RxFrame_ce(sfp) = '1' and rx_data_valid(sfp) = '0' and rx_data_valid_r(sfp) = '1')THEN ngccm_rx_down_cnt(sfp) <= not ngccm_rx_down_cnt(sfp); END IF; END IF; END PROCESS RX_cntr_inst; ------------------------------------------------------------------------------ ngFEC_module: ENTITY work.ngFEC_module ------------------------------------------------------------------------------ PORT MAP ( ipb_clk_i => ipb_clk, ipb_reset_i => ipb_rst, local_reset_i => ctrl_reg(20+sfp/2)((sfp mod 2)*16 + no_partition-1 downto (sfp mod 2)*16), ipb_miso => ipb_miso(sfp+1), ipb_mosi => ipb_mosi(sfp+1), ngccm_miso => ngCCM_miso(sfp), ngccm_mosi => ngCCM_mosi(sfp) ); QIE_RESET_DELAY: delay_counter ------------------------------------------------------------------------------ GENERIC MAP ( ORBIT => 3564 ) PORT MAP ( din => BCntRes, shift_i => shift(sfp), clk_i => fabric_clk, reset_i => ipb_rst, dout => QIE_RESET(sfp) ); ------------------------------------------------------------------------------ ngCCM_gbt : ENTITY work.ngCCM ------------------------------------------------------------------------------ PORT MAP ( reset_IN => ipb_rst, reset_OUT => OPEN, reset_partition => ctrl_reg(20+sfp)((sfp mod 2)*16 + no_partition-1 downto (sfp mod 2)*16), error_counter_reset_i => '0', ngccm_bkp_regs => ngccm_bkp_reg(sfp), TX_Clock_20MHz => fabric_clk_div2, RX_Clock_20MHz => RxFrame_ce(sfp), RX_wordCLK => rx_wordclk(sfp), fabric_clk => fabric_clk, TX_Word_o => tx_data(sfp), RX_Word_i => rx_data_ngccm(sfp), RX_Word_DV_i => rx_data_valid_r(sfp), i2c_clk_en => i2c_clk_en, sfp_rx_lost => '0', sfp_tx_fault => '0', QIE_RESET => QIE_RESET(sfp), WTE => WTE, ipb_clk_i => ipb_clk, ipb_miso => ngccm_miso(sfp), ipb_mosi => ngccm_mosi(sfp), prescale => I2C_prescale, TimeoutErrorCnt => TimeoutErrorCnt(sfp), TCK_inCnt => TCK_inCnt(sfp), TCK_outCnt => TCK_outCnt(sfp), prbs_o => prbs_o, PRBS_rx_pattern_error_cnt_o => PRBS_err_cnt(sfp), PRBS_rx_pattern_bitwise_error_cnt_o => open, pwr_good_cnt_o => pwr_good_cnt(sfp), ngCCM_status_o => ngccm_status(sfp) ); process(RX_wordclk, ngCCM_status_reset) begin if(ngCCM_status_reset = '1')then ngccm_status_reg(sfp) <= x"01ff0000"; elsif(RX_wordclk(sfp)'event and RX_wordclk(sfp) = '1')then IF(ngccm_status(SFP)(15) = '1' and RxFrame_ce(sfp) = '1')THEN ngccm_status_reg(sfp)(24 downto 16) <= ngccm_status_reg(sfp)(24 downto 16) and ngccm_status(sfp)(8 downto 0); ngccm_status_reg(sfp)(8 downto 0) <= ngccm_status(sfp)(8 downto 0); END IF; end if; end process; -------------------------------------------------------------------------- END GENERATE SFP_GEN; process(ipb_clk,fabric_clk_LOCKED) begin if(fabric_clk_LOCKED = '0')then fabric_clk_LOCK_lost <= "11"; elsif(ipb_clk'event and ipb_clk = '1')then fabric_clk_LOCK_lost <= fabric_clk_LOCK_lost(0) & '0'; end if; end process; process(ipb_clk) begin if(ipb_clk'event and ipb_clk = '1')then if(fabric_clk_LOCK_lost = "10")then fabric_clk_LOCK_lost_cnt <= not fabric_clk_LOCK_lost_cnt; end if; end if; end process; g_rx_frameclk_lock_cnt: for i in 0 to 47 generate rx_frameclk_lock_Sync_inst: xpm_cdc_single generic map ( DEST_SYNC_FF => 4, -- integer; range: 2-10 INIT_SYNC_FF => 0, -- integer; 0=disable simulation init values, 1=enable simulation init values SIM_ASSERT_CHK => 0, -- integer; 0=disable simulation messages, 1=enable simulation messages SRC_INPUT_REG => 0 -- integer; 0=do not register input, 1=register input ) port map ( src_clk => '0', -- optional; required when SRC_INPUT_REG = 1 src_in => RxFrame_locked(i), dest_clk => ipb_clk, dest_out => rx_frameclk_locked_Sync(i) ); process(ipb_clk) begin if(ipb_clk'event and ipb_clk = '1')then if(rx_frameclk_locked_Sync(i) = '0')then rx_frameclk_lock_lost_cnt(i) <= not rx_frameclk_lock_lost_cnt(i); end if; end if; end process; end generate; g_tx_ready_cnt: for i in 0 to 47 generate tx_ready_Sync_inst: xpm_cdc_single generic map ( DEST_SYNC_FF => 4, -- integer; range: 2-10 INIT_SYNC_FF => 0, -- integer; 0=disable simulation init values, 1=enable simulation init values SIM_ASSERT_CHK => 0, -- integer; 0=disable simulation messages, 1=enable simulation messages SRC_INPUT_REG => 0 -- integer; 0=do not register input, 1=register input ) port map ( src_clk => '0', -- optional; required when SRC_INPUT_REG = 1 src_in => tx_ready(i), dest_clk => ipb_clk, dest_out => tx_ready_Sync(i) ); process(ipb_clk) begin if(ipb_clk'event and ipb_clk = '1')then if(tx_ready_Sync(i) = '0')then tx_not_ready_cnt(i) <= not tx_not_ready_cnt(i); end if; end if; end process; end generate; i_I2C_if : I2C_if Port map( ipb_clk => ipb_clk, ipb_reset => ipb_rst, local_reset => I2C_reset, -- i2c_clk_en => board_I2C_clk_en, prescale => I2C_prescale, Si_SDA => Si_SDA, Si_SCL => Si_SCL, FF_TX_SDA => FF_TX_SDA, FF_TX_SCL => FF_TX_SCL, FF_RX_SDA => FF_RX_SDA, FF_RX_SCL => FF_RX_SCL, ipb_mosi => ipb_mosi(user_board_I2C), ipb_miso => ipb_miso(user_board_I2C)); end Behavioral;