----------------------------------------------------------------------------------
-- Institute: DESY
-- Engineer: Ozgur Sahin
-- 
-- Create Date:    15:13:33 01/20/2014 
-- Design Name: 
-- Module Name:    buffer_server_com - Behavioral 
-- Project Name: 
-- Target Devices: Server <-> ngFEC
-- Tool versions: 
-- Description: The commands that will be transferred to f/e is stored here, and the communication btw server and GLIB is establish with this module
-- See Specification of ngCCM - CCMServer Communication
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created and migrated from ngFEC_module
-- Revision 0.50 - Protocol btw Server and ngFEC(described in Specification of ngCCM - CCMServer Communication) is implemented.
-- Additional Comments: 
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.ngFEC_pack.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity buffer_server_com is
    generic( partition  :	std_logic_vector := "10101");
	port(
		ipb_clk_i		:	in 	std_logic;
		ipb_reset_i		:	in 	std_logic;
		local_reset_i		:	in 	std_logic;
		ram_mosi			:	in	ipb_wbus;
		ram_miso			:	out	 ipb_rbus;
		server_addr_o	:	out	 STD_LOGIC_VECTOR (BRAM_WORD_SIZE downto 0);
		server_din_o	:	out	 STD_LOGIC_VECTOR (31 downto 0);
		server_wr_o		:	out STD_LOGIC_VECTOR (0 downto 0);
		server_dout		:	in	STD_LOGIC_VECTOR (31 downto 0);
		input_size		:	out 	STD_LOGIC_VECTOR (31 downto 0);
		output_size		:	in	STD_LOGIC_VECTOR (31 downto 0);
		control_reg		:	out STD_LOGIC_VECTOR (31 downto 0);
		status_reg		: in	STD_LOGIC_VECTOR (31 downto 0);
		ngccm_state_o	:	out	 state	
	);
end buffer_server_com;
architecture Behavioral of buffer_server_com is
constant sr_address	: std_logic_vector (15 downto 0) := x"1194";
constant cr_address	: std_logic_vector (15 downto 0) := x"1195"; --registers are described in Specification of ngCCM - CCMServer Communication
constant is_address	: std_logic_vector (15 downto 0) := x"1196";
constant os_address	: std_logic_vector (15 downto 0) := x"1197";
signal reg_flag		: STD_LOGIC					:= '0';
signal ipb_ack		: STD_LOGIC					:= '0';
signal ipb_ack_en		: STD_LOGIC					:= '1';
signal	control_reg_i, input_size_i, reg_data	:	std_logic_vector (31 downto 0);
begin
control_reg <= control_reg_i;
input_size  <= input_size_i;
ram_miso.ipb_ack <= ipb_ack;
ram_miso.ipb_err 	<= '0';
ram_miso.ipb_rdata <= reg_data when reg_flag = '1' else server_dout;
server_addr_o <= ram_mosi.ipb_addr(BRAM_WORD_SIZE downto 0);
server_din_o <= ram_mosi.ipb_wdata;
server_wr_o <= "1" when ram_mosi.ipb_write = '1' and ram_mosi.ipb_strobe = '1' and ram_mosi.ipb_addr(12) = '0' and
	std_match(ram_mosi.ipb_addr(26)& ram_mosi.ipb_addr(19 downto 16), partition) and
	control_reg_i(0) = word0(0) and unsigned(ram_mosi.ipb_addr(BRAM_WORD_SIZE downto 0)) < 1250 else "0";
ipb_ack_en <= '1' when pipeline else not ipb_ack;
ipbusreadandwrite:process (ipb_clk_i,ipb_reset_i)  
begin
	if(ipb_reset_i = '1') then
		control_reg_i <= x"00000000"; 
		input_size_i  <= x"00000000";
		ngccm_state_o  		<= refresh_s;	
		reg_flag <= '0';
		ipb_ack <= '0';
	elsif rising_edge(ipb_clk_i) then
		if local_reset_i = '1' then
			control_reg_i <= x"00000000"; 
			input_size_i  <= x"00000000";
		elsif std_match(ram_mosi.ipb_addr(26)& ram_mosi.ipb_addr(19 downto 0), partition & cr_address) and ram_mosi.ipb_write = '1' and ram_mosi.ipb_strobe = '1' then
			control_reg_i(0)	<=	ram_mosi.ipb_wdata(0);
		elsif std_match(ram_mosi.ipb_addr(26)& ram_mosi.ipb_addr(19 downto 0), partition & is_address) and ram_mosi.ipb_write = '1' and ram_mosi.ipb_strobe = '1' then
			input_size_i(12 downto 2)	<=	ram_mosi.ipb_wdata(12 downto 2);
		end if;
		reg_flag <= ram_mosi.ipb_addr(12);
		reg_data <= x"00000000"; 
		--set the ngCCM state according to the control register 
		if control_reg_i(0)  = word0(0) then 
			ngccm_state_o  <= refresh_s; --start 
		elsif control_reg_i(0)  = word1(0) then
			if(status_reg(1 downto 0) = word2(1 downto 0))then
				ngccm_state_o <= wait_s;
			else
				ngccm_state_o  <= process_s; 
			end if;
		end if;
		--write buffer: ipbus -> ram
		if ram_mosi.ipb_strobe = '1' and std_match(ram_mosi.ipb_addr(26)& ram_mosi.ipb_addr(19 downto 16), partition) then
			if ram_mosi.ipb_write = '1' then
				if (ram_mosi.ipb_addr(15 downto 0) = cr_address or ram_mosi.ipb_addr(15 downto 0) = is_address) then --drive the ack signal for control registers
					ipb_ack	 <= ipb_ack_en ;	
				elsif control_reg_i = word0 and unsigned(ram_mosi.ipb_addr(BRAM_WORD_SIZE downto 0)) < 1250 then --write the commands to the buffer here
					ipb_ack	 <= ipb_ack_en ;
				else	
					ipb_ack	 <= '0' ;	
				end if;
			elsif ram_mosi.ipb_addr(1 downto 0) = cr_address(1 downto 0) then
				reg_data(0) <= control_reg_i(0) ;	
				ipb_ack	 <= ipb_ack_en ;	
			elsif ram_mosi.ipb_addr(1 downto 0) = is_address(1 downto 0) then
				reg_data(12 downto 2) <= input_size_i(12 downto 2);	
				ipb_ack 	 <= ipb_ack_en ;	
			elsif ram_mosi.ipb_addr(1 downto 0) = os_address(1 downto 0) then
				reg_data(12 downto 2) <= output_size(12 downto 2);	
				ipb_ack 	 <= ipb_ack_en ;	
			elsif ram_mosi.ipb_addr(1 downto 0) = sr_address(1 downto 0) then
				reg_data(1 downto 0) <= status_reg(1 downto 0);	
				ipb_ack 	 <= ipb_ack_en ;	
			else		
				ipb_ack <= ipb_ack_en;	
			end if;
		else
			ipb_ack <= '0';
		end if;
	end if;
end process;

end Behavioral;