---------------------------------------------------------------------------------- -- Company: -- Engineer: SAHIN -- -- Create Date: 16:12:28 08/07/2012 -- Design Name: -- Module Name: RAM_module - Behavioral -- Project Name: -- Target Devices: FC7 -- Tool versions: -- Description: -- block ram inst for partitions -- Dependencies: -- -- Revision: -- Revision 1.00 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.ngFEC_pack.all; Library UNISIM; use UNISIM.vcomponents.all; Library xpm; use xpm.vcomponents.all; entity Module_RAM is port ( -- Port A clk : in std_logic; a_wr : in std_logic_VECTOR(0 DOWNTO 0); a_addr : in std_logic_vector(BRAM_WORD_SIZE downto 0); a_din : in std_logic_vector(31 downto 0); a_dout : out std_logic_vector(31 downto 0); -- Port B b_wr : in std_logic_VECTOR(0 DOWNTO 0); b_addr : in std_logic_vector(BRAM_WORD_SIZE downto 0); b_din : in std_logic_vector(31 downto 0); b_dout : out std_logic_vector(31 downto 0)); -- b_aout : out std_logic_vector(BRAM_WORD_SIZE downto 0)); end Module_RAM; architecture Behavioral of Module_RAM is signal DOA_l : std_logic_vector(31 downto 0) := (others=>'0'); signal DOA_h : std_logic_vector(31 downto 0) := (others=>'0'); signal ENA_l : std_logic := '0'; signal ENB_l : std_logic := '0'; signal rst_l : std_logic := '0'; signal rst_h : std_logic := '0'; begin ENA_l <= not a_addr(BRAM_WORD_SIZE); ENB_l <= not b_addr(BRAM_WORD_SIZE); rst_l <= a_addr(BRAM_WORD_SIZE); rst_h <= not a_addr(BRAM_WORD_SIZE); a_dout <= DOA_l or DOA_h; BRAM_l : xpm_memory_tdpram generic map ( ADDR_WIDTH_A => 11, -- DECIMAL ADDR_WIDTH_B => 11, -- DECIMAL AUTO_SLEEP_TIME => 0, -- DECIMAL BYTE_WRITE_WIDTH_A => 32, -- DECIMAL BYTE_WRITE_WIDTH_B => 32, -- DECIMAL CLOCKING_MODE => "common_clock", -- String MEMORY_PRIMITIVE => "block", -- String MEMORY_SIZE => 65536, -- DECIMAL READ_DATA_WIDTH_A => 32, -- DECIMAL READ_DATA_WIDTH_B => 32, -- DECIMAL READ_LATENCY_A => 1, -- DECIMAL READ_LATENCY_B => 1, -- DECIMAL READ_RESET_VALUE_A => "0", -- String WAKEUP_TIME => "disable_sleep", -- String WRITE_DATA_WIDTH_A => 32, -- DECIMAL WRITE_DATA_WIDTH_B => 32, -- DECIMAL WRITE_MODE_B => "no_change" -- String default is "no_change" ) port map ( douta => DOA_l, -- READ_DATA_WIDTH_A-bit output: Data output for port A read operations. doutb => b_dout, -- READ_DATA_WIDTH_B-bit output: Data output for port B read operations. addra => a_addr(10 downto 0), -- ADDR_WIDTH_A-bit input: Address for port A write and read operations. addrb => b_addr(10 downto 0), -- ADDR_WIDTH_B-bit input: Address for port B write and read operations. clka => clk, -- 1-bit input: Clock signal for port A. Also clocks port B when -- parameter CLOCKING_MODE is "common_clock". clkb => '0', -- 1-bit input: Clock signal for port B when parameter CLOCKING_MODE is -- "independent_clock". Unused when parameter CLOCKING_MODE is -- "common_clock". dina => a_din, -- WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations. dinb => b_din, -- WRITE_DATA_WIDTH_B-bit input: Data input for port B write operations. ena => ENA_l, -- 1-bit input: Memory enable signal for port A. Must be high on clock -- cycles when read or write operations are initiated. Pipelined -- internally. enb => ENB_l, -- 1-bit input: Memory enable signal for port B. Must be high on clock -- cycles when read or write operations are initiated. Pipelined -- internally. injectdbiterra => '0', -- 1-bit input: Controls double bit error injection on input data when -- ECC enabled (Error injection capability is not available in -- "decode_only" mode). injectdbiterrb => '0', -- 1-bit input: Controls double bit error injection on input data when -- ECC enabled (Error injection capability is not available in -- "decode_only" mode). injectsbiterra => '0', -- 1-bit input: Controls single bit error injection on input data when -- ECC enabled (Error injection capability is not available in -- "decode_only" mode). injectsbiterrb => '0', -- 1-bit input: Controls single bit error injection on input data when -- ECC enabled (Error injection capability is not available in -- "decode_only" mode). regcea => '1', -- 1-bit input: Clock Enable for the last register stage on the output -- data path. regceb => '1', -- 1-bit input: Clock Enable for the last register stage on the output -- data path. rsta => rst_l, -- 1-bit input: Reset signal for the final port A output register -- stage. Synchronously resets output port douta to the value specified -- by parameter READ_RESET_VALUE_A. rstb => '0', -- 1-bit input: Reset signal for the final port B output register -- stage. Synchronously resets output port doutb to the value specified -- by parameter READ_RESET_VALUE_B. sleep => '0', -- 1-bit input: sleep signal to enable the dynamic power saving feature. wea => a_wr, -- WRITE_DATA_WIDTH_A-bit input: Write enable vector for port A input -- data port dina. 1 bit wide when word-wide writes are used. In -- byte-wide write configurations, each bit controls the writing one -- byte of dina to address addra. For example, to synchronously write -- only bits [15-8] of dina when WRITE_DATA_WIDTH_A is 32, wea would be -- 4'b0010. web => b_wr -- WRITE_DATA_WIDTH_B-bit input: Write enable vector for port B input -- data port dinb. 1 bit wide when word-wide writes are used. In -- byte-wide write configurations, each bit controls the writing one -- byte of dinb to address addrb. For example, to synchronously write -- only bits [15-8] of dinb when WRITE_DATA_WIDTH_B is 32, web would be -- 4'b0010. ); BRAM_h : xpm_memory_sdpram generic map ( ADDR_WIDTH_A => 9, -- DECIMAL ADDR_WIDTH_B => 9, -- DECIMAL BYTE_WRITE_WIDTH_A => 32, -- DECIMAL CLOCKING_MODE => "common_clock", -- String MEMORY_PRIMITIVE => "block", -- String MEMORY_SIZE => 16384, -- DECIMAL READ_DATA_WIDTH_B => 32, -- DECIMAL READ_LATENCY_B => 1, -- DECIMAL READ_RESET_VALUE_B => "0", -- String WRITE_DATA_WIDTH_A => 32, -- DECIMAL WRITE_MODE_B => "no_change" -- String default is "no_change" ) port map ( doutb => DOA_h, -- READ_DATA_WIDTH_B-bit output: Data output for port B read operations. addra => b_addr(8 downto 0), -- ADDR_WIDTH_A-bit input: Address for port A write operations. addrb => a_addr(8 downto 0), -- ADDR_WIDTH_B-bit input: Address for port B read operations. clka => clk, -- 1-bit input: Clock signal for port A. Also clocks port B when -- parameter CLOCKING_MODE is "common_clock". clkb => '0', -- 1-bit input: Clock signal for port B when parameter CLOCKING_MODE is -- "independent_clock". Unused when parameter CLOCKING_MODE is -- "common_clock". dina => b_din, -- WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations. ena => '1', -- 1-bit input: Memory enable signal for port A. Must be high on clock -- cycles when write operations are initiated. Pipelined internally. enb => '1', -- 1-bit input: Memory enable signal for port B. Must be high on clock -- cycles when read operations are initiated. Pipelined internally. injectdbiterra => '0', -- 1-bit input: Controls double bit error injection on input data when -- ECC enabled (Error injection capability is not available in -- "decode_only" mode). injectsbiterra => '0', -- 1-bit input: Controls single bit error injection on input data when -- ECC enabled (Error injection capability is not available in -- "decode_only" mode). regceb => '1', -- 1-bit input: Clock Enable for the last register stage on the output -- data path. rstb => rst_h, -- 1-bit input: Reset signal for the final port B output register -- stage. Synchronously resets output port doutb to the value specified -- by parameter READ_RESET_VALUE_B. sleep => '0', -- 1-bit input: sleep signal to enable the dynamic power saving feature. wea => b_wr -- WRITE_DATA_WIDTH_A-bit input: Write enable vector for port A input -- data port dina. 1 bit wide when word-wide writes are used. In -- byte-wide write configurations, each bit controls the writing one -- byte of dina to address addra. For example, to synchronously write -- only bits [15-8] of dina when WRITE_DATA_WIDTH_A is 32, wea would be -- 4'b0010. ); end Behavioral;