-------------------------------------------------------------------------------
-- Title      : Sync
-- Project    : 
-------------------------------------------------------------------------------
-- File       : Sync.vhd
-- Author     : Stephen Goadhouse  <sgoadhouse@virginia.edu>
-- Company    : 
-- Created    : 2012-01-30
-- Last update: 2012-06-22
-- Platform   : 
-- Standard   : VHDL'93
-------------------------------------------------------------------------------
-- Description: Sync input signal to the clk
-------------------------------------------------------------------------------
-- Copyright (c) 2012 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2012-01-30  1.0      SDG     Created
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY SyncRst IS
  PORT(
    clk    : IN  STD_LOGIC;
    ce : IN  STD_LOGIC;
    Rst_i : IN  STD_LOGIC;
    Rst_o : OUT STD_LOGIC
    );
END SyncRst;

ARCHITECTURE rtl OF SyncRst IS

SIGNAL sync_m : STD_LOGIC_VECTOR(3 downto 0);
attribute ASYNC_REG : string;
attribute ASYNC_REG of sync_m : signal is "true";
BEGIN

  -- purpose: uses two flip/flops to synchronize the input to clk
  -- shielding any potential metastability from sync_o (sync_m gets it).
  sync_proc : PROCESS (clk,Rst_i) IS
  BEGIN  -- PROCESS sync_proc
  	IF Rst_i = '1' THEN
  		sync_m <= "1111";
    ELSIF rising_edge(clk) THEN            -- rising clock edge
			if(ce = '1')then
				sync_m <= sync_m(2 downto 0) & Rst_i;
			end if;
    END IF;
  END PROCESS sync_proc;
Rst_o <= sync_m(3);
END rtl;