----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 05/27/2020 07:51:38 PM
-- Design Name: 
-- Module Name: mgt_HPTD - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
Library xpm;
use xpm.vcomponents.all;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mgt_HPTD is
  Port ( 
    gtwiz_userclk_tx_active_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtwiz_userclk_rx_reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtwiz_userclk_rx_srcclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtwiz_userclk_rx_usrclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtwiz_userclk_rx_usrclk2_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtwiz_userclk_rx_active_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtwiz_reset_clk_freerun_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtwiz_reset_all_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtwiz_reset_tx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtwiz_reset_tx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtwiz_reset_rx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtwiz_reset_rx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtwiz_reset_rx_cdr_stable_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtwiz_reset_tx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtwiz_reset_rx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtwiz_userdata_tx_in : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
    gtwiz_userdata_rx_out : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
    gthrxn_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    gthrxp_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtrefclk0_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    loopback_in : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
    rxpd_in : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
    rxpolarity_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    rxslide_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    txpd_in : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
    txpdelecidlemode_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    txpolarity_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    txusrclk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    txusrclk2_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    cplllock_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    gthtxn_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    gthtxp_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    HPTD_reset : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    mgt_reset_tx_done : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtpowergood_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    rxpmaresetdone_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    txpmaresetdone_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
  );

end mgt_HPTD;

architecture Behavioral of mgt_HPTD is
COMPONENT mgt_ip
  PORT (
    gtwiz_userclk_tx_active_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtwiz_userclk_rx_reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtwiz_userclk_rx_srcclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtwiz_userclk_rx_usrclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtwiz_userclk_rx_usrclk2_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtwiz_userclk_rx_active_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtwiz_reset_clk_freerun_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtwiz_reset_all_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtwiz_reset_tx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtwiz_reset_tx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtwiz_reset_rx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtwiz_reset_rx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtwiz_reset_rx_cdr_stable_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtwiz_reset_tx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtwiz_reset_rx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtwiz_userdata_tx_in : IN STD_LOGIC_VECTOR(19 DOWNTO 0);
    gtwiz_userdata_rx_out : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
    drpaddr_in : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
    drpclk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    drpdi_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
    drpen_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    drpwe_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    gthrxn_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    gthrxp_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtrefclk0_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    loopback_in : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
    rxpd_in : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
    rxpolarity_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    rxslide_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    txpd_in : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
    txpdelecidlemode_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    txpippmen_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    txpippmovrden_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    txpippmpd_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    txpippmsel_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    txpippmstepsize_in : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
    txpolarity_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    txusrclk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    txusrclk2_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    cplllock_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    drpdo_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
    drprdy_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    gthtxn_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    gthtxp_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    gtpowergood_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    rxpmaresetdone_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    txbufstatus_out : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
    txoutclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    txpmaresetdone_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
  );
END COMPONENT;
COMPONENT tx_phase_aligner
  port (
    clk_sys_i : in std_logic;           --! system clock input
    reset_i   : in std_logic;  --! active high sync. reset (recommended to keep reset_i=1 while transceiver reset initialization is being performed)
    tx_aligned_o : out std_logic;  --! Use it as a reset for the user transmitter logic
    tx_pi_phase_calib_i   : in std_logic_vector(6 downto 0);  --! previous calibrated tx pi phase (tx_pi_phase_o after first reset calibration)
    tx_ui_align_calib_i   : in std_logic;  --! align with previous calibrated tx pi phase
    tx_fifo_fill_pd_max_i : in std_logic_vector(31 downto 0);  --! phase detector accumulated max output, sets precision of phase detector
    tx_fine_realign_i     : in std_logic;  --! A rising edge will cause the Tx to perform a fine realignment to the half-response
    ps_strobe_i     : in  std_logic;  --! pulse synchronous to clk_sys_i to activate a shift in the phase (only captured rising edge, so a signal larger than a pulse is also fine)
    ps_inc_ndec_i   : in  std_logic;  --! 1 increments phase by phase_step_i units, 0 decrements phase by phase_step_i units
    ps_phase_step_i : in  std_logic_vector(3 downto 0);  --! number of units to shift the phase of the receiver clock (see Xilinx transceiver User Guide to convert units in time)       
    ps_done_o       : out std_logic;  --! pulse synchronous to clk_sys_i to indicate a phase shift was performed
    tx_pi_phase_o : out std_logic_vector(6 downto 0);  --! phase shift accumulated
    tx_fifo_fill_pd_o : out std_logic_vector(31 downto 0);  --! phase detector output, when aligned this value should be close to (0x2_0000)
    clk_txusr_i          : in std_logic;  --! txusr2clk                
    tx_fifo_fill_level_i : in std_logic;  --! connect to txbufstatus[0]
    txpippmen_o       : out std_logic;  --! enable tx phase interpolator controller
    txpippmovrden_o   : out std_logic;  --! enable DRP control of tx phase interpolator
    txpippmsel_o      : out std_logic;  --! set to 1 when using tx pi ppm controler
    txpippmpd_o       : out std_logic;  --! power down transmitter phase interpolator 
    txpippmstepsize_o : out std_logic_vector(4 downto 0);  --! sets step size and direction of phase shift with port control PI code stepping mode
    drpaddr_o : out std_logic_vector(8 downto 0);  --! For devices with a 10-bit DRP address interface, connect MSB to '0'
    drpen_o   : out std_logic;          --! DRP enable transaction
    drpdi_o   : out std_logic_vector(15 downto 0);  --! DRP data write
    drprdy_i  : in  std_logic;          --! DRP finished transaction
    drpdo_i   : in  std_logic_vector(15 downto 0);  --! DRP data read; not used nowadays, write only interface
    drpwe_o   : out std_logic           --! DRP write enable
    );
END COMPONENT;
signal reset_tx_phase_aligner_sync : std_logic := '0';
signal reset_tx_phase_aligner : std_logic := '0';
signal tx_aligned : std_logic := '0';
signal reset_tx_done : std_logic := '0';
signal drpaddr : STD_LOGIC_VECTOR(8 DOWNTO 0);
signal drpdi : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal drpen : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal drpwe : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal drprdy : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal drpdo : std_logic_vector(15 downto 0);
signal txpippmen : std_logic;
signal txpippmovrden : std_logic;
signal txpippmsel : std_logic;
signal txpippmpd : std_logic;
signal txpippmstepsize : std_logic_vector(4 downto 0);
signal txbufstatus : STD_LOGIC_VECTOR(1 DOWNTO 0);
begin
gtwiz_reset_tx_done_out(0) <= tx_aligned;
mgt_reset_tx_done(0) <= reset_tx_done;
i_mgt_ip : mgt_ip
		PORT MAP (
			gtwiz_userclk_tx_active_in => gtwiz_userclk_tx_active_in,
			gtwiz_userclk_rx_reset_in => gtwiz_userclk_rx_reset_in,
			gtwiz_userclk_rx_srcclk_out => gtwiz_userclk_rx_srcclk_out,
			gtwiz_userclk_rx_usrclk_out => gtwiz_userclk_rx_usrclk_out,
			gtwiz_userclk_rx_usrclk2_out => gtwiz_userclk_rx_usrclk2_out,
			gtwiz_userclk_rx_active_out =>gtwiz_userclk_rx_active_out,
			gtwiz_reset_clk_freerun_in => gtwiz_reset_clk_freerun_in,
			gtwiz_reset_all_in => gtwiz_reset_all_in,
			gtwiz_reset_tx_pll_and_datapath_in => gtwiz_reset_tx_pll_and_datapath_in,
			gtwiz_reset_tx_datapath_in => gtwiz_reset_tx_datapath_in,
			gtwiz_reset_rx_pll_and_datapath_in => gtwiz_reset_rx_pll_and_datapath_in,
			gtwiz_reset_rx_datapath_in => gtwiz_reset_rx_datapath_in,
			gtwiz_reset_rx_cdr_stable_out => gtwiz_reset_rx_cdr_stable_out,
			gtwiz_reset_tx_done_out(0) => reset_tx_done,
			gtwiz_reset_rx_done_out => gtwiz_reset_rx_done_out,
			gtwiz_userdata_tx_in => gtwiz_userdata_tx_in,
			gtwiz_userdata_rx_out => gtwiz_userdata_rx_out,
			drpaddr_in => drpaddr,
			drpclk_in => gtwiz_reset_clk_freerun_in,
			drpdi_in => drpdi,
			drpen_in => drpen,
			drpwe_in => drpwe,
			gthrxn_in => gthrxn_in,
			gthrxp_in => gthrxp_in,
			gtrefclk0_in => gtrefclk0_in,
			loopback_in => loopback_in,
			rxpd_in => rxpd_in,
			rxpolarity_in => rxpolarity_in,
			rxslide_in => rxslide_in,
			txpd_in => txpd_in,
			txpdelecidlemode_in => txpdelecidlemode_in,
			txpippmen_in(0) => txpippmen,
			txpippmovrden_in(0) => txpippmovrden,
			txpippmpd_in(0) => txpippmpd,
			txpippmsel_in(0) => txpippmsel,
			txpippmstepsize_in => txpippmstepsize,
			txpolarity_in => txpolarity_in,
			txusrclk_in => txusrclk_in,
			txusrclk2_in => txusrclk2_in,
			cplllock_out => cplllock_out,
			drpdo_out => drpdo,
			drprdy_out => drprdy,
			gthtxn_out => gthtxn_out,
			gthtxp_out => gthtxp_out,
			gtpowergood_out => gtpowergood_out,
			rxpmaresetdone_out => rxpmaresetdone_out,
			txbufstatus_out => txbufstatus,
			txoutclk_out => open,
			txpmaresetdone_out => txpmaresetdone_out
  );
i_reset_tx_done_sync : xpm_cdc_single
   generic map (
      DEST_SYNC_FF => 4,   -- DECIMAL; range: 2-10
      INIT_SYNC_FF => 0,   -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values
      SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages
      SRC_INPUT_REG => 0   -- DECIMAL; 0=do not register input, 1=register input
   )
   port map (
      dest_out => reset_tx_phase_aligner_sync, -- 1-bit output: src_in synchronized to the destination clock domain. This output
                            -- is registered.

      dest_clk => gtwiz_reset_clk_freerun_in(0), -- 1-bit input: Clock signal for the destination clock domain.
      src_clk => '0',   -- 1-bit input: optional; required when SRC_INPUT_REG = 1
      src_in => reset_tx_phase_aligner      -- 1-bit input: Input signal to be synchronized to dest_clk domain.
   );
reset_tx_phase_aligner <= not reset_tx_done or HPTD_reset(0);
i_tx_phase_aligner : tx_phase_aligner port map(
	clk_sys_i => gtwiz_reset_clk_freerun_in(0),
  reset_i => reset_tx_phase_aligner_sync,
  tx_aligned_o => tx_aligned,
  tx_pi_phase_calib_i => (others => '0'),
  tx_ui_align_calib_i => '0',
  tx_fifo_fill_pd_max_i => x"00100000",
  tx_fine_realign_i => '0',    
  ps_strobe_i => '0',
  ps_inc_ndec_i => '0',
  ps_phase_step_i => x"0",
  ps_done_o => open,
  tx_pi_phase_o => open,
  tx_fifo_fill_pd_o => open,
  clk_txusr_i => txusrclk2_in(0),	
  tx_fifo_fill_level_i => txbufstatus(0),
  txpippmen_o => txpippmen,
  txpippmovrden_o => txpippmovrden,
  txpippmsel_o => txpippmsel,
  txpippmpd_o => txpippmpd,
  txpippmstepsize_o => txpippmstepsize,
  drpaddr_o => drpaddr,
  drpen_o => drpen(0),
  drpdi_o => drpdi,
  drprdy_i => drprdy(0),
  drpdo_i => drpdo,
  drpwe_o => drpwe(0)
	);


end Behavioral;