----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 05/28/2019 10:57:06 AM
-- Design Name: 
-- Module Name: BRAM_counters - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use IEEE.std_logic_misc.all;
use work.ngFEC_pack.all;
--use work.user_package.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
Library xpm;
use xpm.vcomponents.all;
library UNISIM;
use UNISIM.VComponents.all;

entity ipb_user_status_regs is
		generic (sim : boolean := false);
    Port ( clk : in STD_LOGIC;
           ipb_clk : in STD_LOGIC;
           ipb_rst : in STD_LOGIC;
           reset_ctrl : in STD_LOGIC_VECTOR (31 downto 0);
           cntr_din : in STD_LOGIC_VECTOR (511 downto 0);
           rate_din : in STD_LOGIC_VECTOR (255 downto 0);
           stat_reg : in array_1024x32bit;
           ipb_mosi_i : in	ipb_wbus;
           ipb_miso_o : out ipb_rbus);
end ipb_user_status_regs;
architecture Behavioral of ipb_user_status_regs is
component DSP_counterX4
		generic (use_sync : std_logic_vector(3 downto 0) := "1111"); 
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           din : in  STD_LOGIC_VECTOR(3 downto 0);
           q : out  STD_LOGIC_VECTOR(47 downto 0));
end component;
component DSP_counterX4b
		generic (use_sync : std_logic_vector(3 downto 0) := "1111"); 
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC_VECTOR(3 downto 0);
           din : in  STD_LOGIC_VECTOR(3 downto 0);
           q : out  STD_LOGIC_VECTOR(47 downto 0));
end component;
component DSP_MUX
    Port ( DinA : in STD_LOGIC_VECTOR (47 downto 0);
           DinB : in STD_LOGIC_VECTOR (47 downto 0);
           PCIN : in STD_LOGIC_VECTOR (47 downto 0);
           S : in STD_LOGIC_VECTOR (1 downto 0);
           PCOUT : out STD_LOGIC_VECTOR (47 downto 0);
           Dout : out STD_LOGIC_VECTOR (47 downto 0));
end component;
component DSP_MUX_b
    Port ( DinA : in STD_LOGIC_VECTOR (47 downto 0);
           DinB : in STD_LOGIC_VECTOR (47 downto 0);
           S : in STD_LOGIC_VECTOR (1 downto 0);
           PCOUT : out STD_LOGIC_VECTOR (47 downto 0);
           Dout : out STD_LOGIC_VECTOR (47 downto 0));
end component;
component DSP_MUX_C
    Port ( clk : in STD_LOGIC;
           ce : in  STD_LOGIC;
           DinA : in STD_LOGIC_VECTOR (47 downto 0);
           DinB : in STD_LOGIC_VECTOR (47 downto 0);
           PCIN : in STD_LOGIC_VECTOR (47 downto 0);
           S : in STD_LOGIC_VECTOR (1 downto 0);
           PCOUT : out STD_LOGIC_VECTOR (47 downto 0);
           Dout : out STD_LOGIC_VECTOR (47 downto 0));
end component;
component DSP_MUX_C_b
    Port ( clk : in STD_LOGIC;
           ce : in  STD_LOGIC;
           DinA : in STD_LOGIC_VECTOR (47 downto 0);
           DinB : in STD_LOGIC_VECTOR (47 downto 0);
            S : in STD_LOGIC_VECTOR (1 downto 0);
           PCOUT : out STD_LOGIC_VECTOR (47 downto 0);
           Dout : out STD_LOGIC_VECTOR (47 downto 0));
end component;
component cntr_rst_ctrl
    Port ( clk : in STD_LOGIC;
           ipb_rst : in std_logic;
           clk_phase : in STD_LOGIC_VECTOR (7 downto 0);
           addr : in unsigned(8 downto 0);
           reset_ctrl : in STD_LOGIC_VECTOR (31 downto 0);
           ram_rsta_cntr : out STD_LOGIC;
           rst_cntr : out STD_LOGIC_VECTOR (511 downto 0));
end component;
type array2X48 is array(0 to 1) of std_logic_vector(47 downto 0);
type array3X48 is array(0 to 2) of std_logic_vector(47 downto 0);
type array4X48 is array(0 to 3) of std_logic_vector(47 downto 0);
type array5X48 is array(0 to 4) of std_logic_vector(47 downto 0);
type array6X48 is array(0 to 5) of std_logic_vector(47 downto 0);
type array8X48 is array(0 to 7) of std_logic_vector(47 downto 0);
type array12X48 is array(0 to 11) of std_logic_vector(47 downto 0);
type array16X48 is array(0 to 15) of std_logic_vector(47 downto 0);
type array24X48 is array(0 to 23) of std_logic_vector(47 downto 0);
type array28X48 is array(0 to 27) of std_logic_vector(47 downto 0);
type array32X48 is array(0 to 31) of std_logic_vector(47 downto 0);
type array48X48 is array(0 to 47) of std_logic_vector(47 downto 0);
type array64X48 is array(0 to 95) of std_logic_vector(47 downto 0);
type array96X48 is array(0 to 95) of std_logic_vector(47 downto 0);
type array128X48 is array(0 to 127) of std_logic_vector(47 downto 0);
type array192X48 is array(0 to 191) of std_logic_vector(47 downto 0);
type array256X48 is array(0 to 255) of std_logic_vector(47 downto 0);
type array512X48 is array(0 to 511) of std_logic_vector(47 downto 0);
signal rst_cntr : std_logic_vector(511 downto 0) := (others => '0');
signal Din_stat : array512x48 := (others => (others => '0'));
signal PCIN_stat : array256x48 := (others => (others => '0'));
signal PCOUT_stat : array256x48;
signal Dout_stat : array256x48 := (others => (others => '0'));
signal PCIN_stat2 : array32x48 := (others => (others => '0'));
signal PCOUT_stat2 : array32x48;
signal Dout_stat2 : array32x48 := (others => (others => '0'));
signal PCIN_stat3 : array4x48 := (others => (others => '0'));
signal PCOUT_stat3 : array4x48;
signal Dout_stat3 : array4x48;
signal S1_stat : std_logic_vector(7 downto 0) := (others => '0');
signal S2_stat : std_logic_vector(7 downto 0) := (others => '0');
signal S3_stat : std_logic_vector(7 downto 0) := (others => '0');
signal count : array192X48 := (others => (others => '0'));
signal PCIN_cntr : array64x48 := (others => (others => '0'));
signal PCOUT_cntr : array64x48;
signal PCIN2_cntr : array8x48 := (others => (others => '0'));
signal PCOUT2_cntr : array8x48;
signal PCIN3_cntr : array4x48 := (others => (others => '0'));
signal PCOUT3_cntr : array4X48;
signal S1_cntr : std_logic_vector(7 downto 0) := (others => '0');
signal S2_cntr : std_logic_vector(7 downto 0) := (others => '0');
signal S3_cntr : std_logic_vector(7 downto 0) := (others => '0');
signal Dout_cntr : array64X48 := (others => (others => '0'));
signal Dout2_cntr : array8X48 := (others => (others => '0'));
signal Dout3_cntr : array4X48;
signal Din_cntr : array8X48 := (others => (others => '0'));
signal addr_cntr : unsigned(8 downto 0) := (others => '0');
signal ram_rsta_cntr : std_logic := '0';
signal load_count_cntr : std_logic := '0';
signal reset_cycle_cntr : std_logic := '0';
signal ipb_addr9_r : std_logic;
signal ram_addra_cntr : std_logic_vector(8 downto 0) := (others => '0');
signal dina_cntr : std_logic_vector(31 downto 0);
signal douta_cntr : std_logic_vector(31 downto 0);
signal doutb_cntr : std_logic_vector(31 downto 0);
signal P_cntr : std_logic_vector(47 downto 0) := (others => '0');
signal C_cntr : std_logic_vector(47 downto 0) := (others => '0');
signal B_cntr : std_logic_vector(17 downto 0) := (others => '0');
signal A_cntr : std_logic_vector(29 downto 0) := (others => '0');
signal wea : std_logic_vector(0 downto 0);
signal load_count_rate : std_logic := '0';
signal reset_count_rate : std_logic := '0';
signal save_rate : std_logic := '0';
signal cycle_cntr : unsigned(16 downto 0) := (others => '0');
constant write_rate : unsigned(16 downto 0) := "11101110011010100";
signal PCIN_rate : array32x48 := (others => (others => '0'));
signal PCOUT_rate : array32x48;
signal PCIN2_rate : array8x48 := (others => (others => '0'));
signal PCOUT2_rate : array8x48;
signal PCIN3_rate : array4x48 := (others => (others => '0'));
signal PCOUT3_rate : array4X48;
signal S1_rate : std_logic_vector(7 downto 0) := (others => '0');
signal S2_rate : std_logic_vector(7 downto 0) := (others => '0');
signal S3_rate : std_logic_vector(3 downto 0) := (others => '0');
signal Dout_rate : array32X48 := (others => (others => '0'));
signal Dout2_rate : array4X48 := (others => (others => '0'));
signal Dout3_rate : array2X48;
signal Din_rate : array4X48 := (others => (others => '0'));
signal ram_addra_rate : std_logic_vector(8 downto 0) := (others => '0');
signal ram_addrb_rate : std_logic_vector(8 downto 0) := (others => '0');
signal dina_rate : std_logic_vector(31 downto 0);
signal addr_rate : unsigned(7 downto 0) := (others => '0');
signal ram_rsta_rate : std_logic := '0';
signal douta_rate : std_logic_vector(31 downto 0);
signal doutb_rate : std_logic_vector(31 downto 0);
signal P_rate : std_logic_vector(47 downto 0) := (others => '0');
signal C_rate : std_logic_vector(47 downto 0) := (others => '0');
signal B_rate : std_logic_vector(17 downto 0) := (others => '0');
signal A_rate : std_logic_vector(29 downto 0) := (others => '0');
signal ipb_strobe_r : std_logic := '0';
signal ipb_clk_div2 : std_logic := '0';
signal ipb_clk_div2_r : std_logic := '0';
signal clk_phase : std_logic_vector(7 downto 0) := (others => '0');	
attribute keep : string;
attribute keep of S1_cntr : signal is "true";
attribute keep of S2_cntr : signal is "true";
attribute keep of S3_cntr : signal is "true";
attribute keep of S1_rate : signal is "true";
attribute keep of S2_rate : signal is "true";
attribute keep of S3_rate : signal is "true";
begin
process(ipb_clk)
begin
	if(ipb_clk'event and ipb_clk = '1')then
		if(pipeline or ipb_strobe_r = '0')then
			ipb_strobe_r <= ipb_mosi_i.ipb_strobe;
		else
			ipb_strobe_r <= '0';
		end if;
		ipb_addr9_r <= ipb_mosi_i.ipb_addr(9);
	end if;
end process;
ipb_miso_o.ipb_err <= '0' when ipb_mosi_i.ipb_write = '0' else ipb_mosi_i.ipb_strobe when ipb_mosi_i.ipb_addr(10) = '0' else ipb_strobe_r;
ipb_miso_o.ipb_ack <= ipb_mosi_i.ipb_strobe when ipb_mosi_i.ipb_addr(10) = '0' else ipb_strobe_r;
process(Dout_stat3, ipb_mosi_i.ipb_addr, doutb_cntr, doutb_rate)
begin
	if(ipb_mosi_i.ipb_addr(10) = '0')then
		if(ipb_mosi_i.ipb_addr(9) = '0')then
			ipb_miso_o.ipb_rdata <= Dout_stat3(3)(31 downto 0);
		else
			ipb_miso_o.ipb_rdata <= x"0000" & Dout_stat3(3)(47 downto 32);
		end if;
	else
		if(ipb_addr9_r = '0')then
			ipb_miso_o.ipb_rdata <= doutb_cntr;
		else
			ipb_miso_o.ipb_rdata <= doutb_rate;
		end if;
	end if;
end process;
process(ipb_mosi_i,S1_stat,S2_stat,S3_stat)
begin
	case ipb_mosi_i.ipb_addr(2 downto 0) is
		when "000" => S1_stat <= x"02";
		when "001" => S1_stat <= x"03";
		when "010" => S1_stat <= x"08";
		when "011" => S1_stat <= x"0c";
		when "100" => S1_stat <= x"20";
		when "101" => S1_stat <= x"30";
		when "110" => S1_stat <= x"80";
		when others => S1_stat <= x"c0";
	end case;
	case ipb_mosi_i.ipb_addr(5 downto 3) is
		when "000" => S2_stat <= x"02";
		when "001" => S2_stat <= x"03";
		when "010" => S2_stat <= x"08";
		when "011" => S2_stat <= x"0c";
		when "100" => S2_stat <= x"20";
		when "101" => S2_stat <= x"30";
		when "110" => S2_stat <= x"80";
		when others => S2_stat <= x"c0";
	end case;
	case ipb_mosi_i.ipb_addr(8 downto 6) is
		when "000" => S3_stat <= x"02";
		when "001" => S3_stat <= x"03";
		when "010" => S3_stat <= x"08";
		when "011" => S3_stat <= x"0c";
		when "100" => S3_stat <= x"20";
		when "101" => S3_stat <= x"30";
		when "110" => S3_stat <= x"80";
		when others => S3_stat <= x"c0";
	end case;
end process;
i_cntr_rst_ctrl : cntr_rst_ctrl
	port map(
		clk => clk,
		ipb_rst => ipb_rst,
		clk_phase => clk_phase,
		addr => addr_cntr,
		reset_ctrl => reset_ctrl,
		ram_rsta_cntr => ram_rsta_cntr,
		rst_cntr => rst_cntr
	);
g_Din_stat : for i in 0 to 511 generate
	Din_stat(i)(47 downto 32) <= stat_reg(512+i)(15 downto 0);
	Din_stat(i)(31 downto 0) <= stat_reg(i);
end generate g_Din_stat;
g_stat_MUX_k : for k in 0 to 7 generate
	g_stat_MUX_j : for j in 0 to 7 generate
			i_DSP_MUX_b : DSP_MUX_b
				port map(
				DinA => Din_stat(k*64+j*8),
				DinB => Din_stat(k*64+j*8+1),
				S => S1_stat(1 downto 0),
				PCOUT => PCOUT_stat(k*32+j*4),
				Dout => Dout_stat(k*32+j*4));
		g_stat_MUX_i : for i in 1 to 3 generate
			i_DSP_MUX : DSP_MUX
				port map(
				DinA => Din_stat(k*64+j*8+i*2),
				DinB => Din_stat(k*64+j*8+i*2+1),
				PCIN => PCIN_stat(k*32+j*4+i),
				S => S1_stat(i*2+1 downto i*2),
				PCOUT => PCOUT_stat(k*32+j*4+i),
				Dout => Dout_stat(k*32+j*4+i));
		end generate g_stat_MUX_i;
		g_PCIN : for i in 1 to 3 generate
			PCIN_stat(k*32+j*4+i) <= PCOUT_stat(k*32+j*4+i-1);
		end generate g_PCIN;
	end generate g_stat_MUX_j;
end generate g_stat_MUX_k;
g_stat_MUX_j : for j in 0 to 7 generate
		i_DSP_MUX_b : DSP_MUX_b
			port map(
			DinA => Dout_stat(j*32+3),
			DinB => Dout_stat(j*32+7),
			S => S2_stat(1 downto 0),
			PCOUT => PCOUT_stat2(j*4),
			Dout => Dout_stat2(j*4));
	g_stat_MUX_i : for i in 1 to 3 generate
		i_DSP_MUX : DSP_MUX
			port map(
			DinA => Dout_stat(j*32+i*8+3),
			DinB => Dout_stat(j*32+i*8+7),
			PCIN => PCIN_stat2(j*4+i),
			S => S2_stat(i*2+1 downto i*2),
			PCOUT => PCOUT_stat2(j*4+i),
			Dout => Dout_stat2(j*4+i));
	end generate g_stat_MUX_i;
	g_PCIN : for i in 1 to 3 generate
		PCIN_stat2(j*4+i) <= PCOUT_stat2(j*4+i-1);
	end generate g_PCIN;
end generate g_stat_MUX_j;
	i_stat_MUX_b : DSP_MUX_b
		port map(
		DinA => Dout_stat2(3),
		DinB => Dout_stat2(7),
		S => S3_stat(1 downto 0),
		PCOUT => PCOUT_stat3(0),
		Dout => Dout_stat3(0));
g_stat_MUX_i : for i in 1 to 3 generate
	i_DSP_MUX : DSP_MUX
		port map(
		DinA => Dout_stat2(i*8+3),
		DinB => Dout_stat2(i*8+7),
		PCIN => PCIN_stat3(i),
		S => S3_stat(i*2+1 downto i*2),
		PCOUT => PCOUT_stat3(i),
		Dout => Dout_stat3(i));
end generate g_stat_MUX_i;
g_PCIN : for i in 1 to 3 generate
	PCIN_stat3(i) <= PCOUT_stat3(i-1);
end generate g_PCIN;
process(ipb_clk)
begin
	if(ipb_clk'event and ipb_clk = '1')then
		ipb_clk_div2 <= not ipb_clk_div2;
	end if;
end process;
process(clk)
begin
	if(clk'event and clk = '1')then
		ipb_clk_div2_r <= ipb_clk_div2;
		clk_phase(0) <= ipb_clk_div2_r xor ipb_clk_div2;
		clk_phase(7 downto 1) <= clk_phase(6 downto 0);
		load_count_cntr <= clk_phase(6);
		wea(0) <= clk_phase(6);
		if(clk_phase(7) = '1')then
			addr_cntr <= addr_cntr + 1;
			ram_addra_cntr <= std_logic_vector(addr_cntr);
		end if;
	end if;
end process;
g_DSP_cntr : for i in 0 to 127 generate
	 i_DSP_counterX4 : DSP_counterX4b generic map(use_sync => "1111")
		 PORT MAP (
			clk => clk,
			reset => rst_cntr(i*4+3 downto i*4),
			din => cntr_din(i*4+3 downto i*4),
			q => count(i)
		);
end generate g_DSP_cntr;
process(clk)
begin
	if(clk'event and clk = '1')then
		if(clk_phase(7) = '1')then
			case addr_cntr(4 downto 2) is
				when "000" => S1_cntr <= x"02";
				when "001" => S1_cntr <= x"03";
				when "010" => S1_cntr <= x"08";
				when "011" => S1_cntr <= x"0c";
				when "100" => S1_cntr <= x"20";
				when "101" => S1_cntr <= x"30";
				when "110" => S1_cntr <= x"80";
				when others => S1_cntr <= x"c0";
			end case;
			case addr_cntr(7 downto 5) is
				when "000" => S2_cntr <= x"02";
				when "001" => S2_cntr <= x"03";
				when "010" => S2_cntr <= x"08";
				when "011" => S2_cntr <= x"0c";
				when "100" => S2_cntr <= x"20";
				when "101" => S2_cntr <= x"30";
				when "110" => S2_cntr <= x"80";
				when others => S2_cntr <= x"c0";
			end case;
			case addr_cntr(8) & addr_cntr(1 downto 0) is
				when "000" => S3_cntr <= x"02";
				when "001" => S3_cntr <= x"03";
				when "010" => S3_cntr <= x"08";
				when "011" => S3_cntr <= x"0c";
				when "100" => S3_cntr <= x"20";
				when "101" => S3_cntr <= x"30";
				when "110" => S3_cntr <= x"80";
				when others => S3_cntr <= x"c0";
			end case;
		end if;
	end if;
end process;
g_DSP_MUX_cntr_k : for k in 0 to 1     generate
	g_DSP_MUX_j : for j in 0 to 7 generate
		i_DSP_MUX_C_b : DSP_MUX_C_b
				port map(
				clk => clk,
				ce => load_count_cntr,
				DinA => count(k*64+j*8),
				DinB => count(k*64+j*8+1),
				S => S1_cntr(1 downto 0),
				PCOUT => PCOUT_cntr(k*32+j*4),
				Dout => Dout_cntr(k*32+j*4));
		g_DSP_MUX_i : for i in 1 to 3 generate
		i_DSP_MUX_C : DSP_MUX_C
				port map(
				clk => clk,
				ce => load_count_cntr,
				DinA => count(k*64+j*8+i*2),
				DinB => count(k*64+j*8+i*2+1),
				PCIN => PCIN_cntr(k*32+j*4+i),
				S => S1_cntr(i*2+1 downto i*2),
				PCOUT => PCOUT_cntr(k*32+j*4+i),
				Dout => Dout_cntr(k*32+j*4+i));
		end generate g_DSP_MUX_i;
		g_PCIN : for i in 1 to 3 generate
			PCIN_cntr(k*32+j*4+i) <= PCOUT_cntr(k*32+j*4+i-1);
		end generate g_PCIN;
	end generate g_DSP_MUX_j;
end generate g_DSP_MUX_cntr_k;
g_DSP_MUX_cntr_j : for j in 0 to 1 generate
		i_DSP_MUX_b : DSP_MUX_b
			port map(
				DinA => Dout_cntr(j*32+3),
				DinB => Dout_cntr(j*32+7),
				S => S2_cntr(1 downto 0),
				PCOUT => PCOUT2_cntr(j*4),
				Dout => Dout2_cntr(j*4));
	g_DSP_MUX_i : for i in 1 to 3 generate
		i_DSP_MUX : DSP_MUX
			port map(
				DinA => Dout_cntr(j*32+i*8+3),
				DinB => Dout_cntr(j*32+i*8+7),
				PCIN => PCIN2_cntr(j*4+i),
				S => S2_cntr(i*2+1 downto i*2),
				PCOUT => PCOUT2_cntr(j*4+i),
				Dout => Dout2_cntr(j*4+i));
	end generate g_DSP_MUX_i;
	g_PCIN2 : for i in 1 to 3 generate
		PCIN2_cntr(j*4+i) <= PCOUT2_cntr(j*4+i-1);
	end generate g_PCIN2;
end generate g_DSP_MUX_cntr_j;
g_Din_cntr_i : for i in 0 to 1 generate
	g_Din_j : for j in 0 to 3 generate
		Din_cntr(i*4+j)(11 downto 0) <= Dout2_cntr(3+4*i)(j*12+11 downto j*12);
	end generate g_Din_j;
end generate g_Din_cntr_i;
i_DSP_MUX_b_cntr : DSP_MUX_b
		port map(
		DinA => Din_cntr(0),
		DinB => Din_cntr(1),
		S => S3_cntr(1 downto 0),
		PCOUT => PCOUT3_cntr(0),
		Dout => Dout3_cntr(0));
g_DSP_MUX_cntr : for i in 1 to 3 generate
	i_DSP_MUX : DSP_MUX
		port map(
		DinA => Din_cntr(i*2),
		DinB => Din_cntr(i*2+1),
		PCIN => PCIN3_cntr(i),
		S => S3_cntr(i*2+1 downto i*2),
		PCOUT => PCOUT3_cntr(i),
		Dout => Dout3_cntr(i));
end generate g_DSP_MUX_cntr;
g_PCIN3_cntr : for i in 1 to 3 generate
	PCIN3_cntr(i) <= PCOUT3_cntr(i-1);
end generate g_PCIN3_cntr;
i_ram_cntr : xpm_memory_tdpram
   generic map (
      ADDR_WIDTH_A => 9,               -- DECIMAL
      ADDR_WIDTH_B => 9,               -- DECIMAL
      AUTO_SLEEP_TIME => 0,            -- DECIMAL
      CLOCKING_MODE => "independent_clock", -- String
      MEMORY_PRIMITIVE => "block",      -- String
      MEMORY_SIZE => 16384,             -- DECIMAL
      READ_LATENCY_A => 1,             -- DECIMAL
      READ_LATENCY_B => 1,             -- DECIMAL
      READ_RESET_VALUE_A => "00000000"       -- String
   )
   port map (
      douta => douta_cntr,                   -- READ_DATA_WIDTH_A-bit output: Data output for port A read operations.
      doutb => doutb_cntr,                   -- READ_DATA_WIDTH_B-bit output: Data output for port B read operations.
      addra => ram_addra_cntr,                   -- ADDR_WIDTH_A-bit input: Address for port A write and read operations.
      addrb => ipb_mosi_i.ipb_addr(8 downto 0),                   -- ADDR_WIDTH_B-bit input: Address for port B write and read operations.
      clka => clk,                     -- 1-bit input: Clock signal for port A. Also clocks port B when
                                        -- parameter CLOCKING_MODE is "common_clock".

      clkb => ipb_clk,                     -- 1-bit input: Clock signal for port B when parameter CLOCKING_MODE is
                                        -- "independent_clock". Unused when parameter CLOCKING_MODE is
                                        -- "common_clock".

      dina => dina_cntr,                     -- WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations.
      dinb => x"00000000",                     -- WRITE_DATA_WIDTH_B-bit input: Data input for port B write operations.
      ena => '1',                       -- 1-bit input: Memory enable signal for port A. Must be high on clock
                                        -- cycles when read or write operations are initiated. Pipelined
                                        -- internally.

      enb => '1',                       -- 1-bit input: Memory enable signal for port B. Must be high on clock
                                        -- cycles when read or write operations are initiated. Pipelined
                                        -- internally.

      injectdbiterra => '0', -- 1-bit input: Controls double bit error injection on input data when
      injectdbiterrb => '0', -- 1-bit input: Controls double bit error injection on input data when
      injectsbiterra => '0', -- 1-bit input: Controls single bit error injection on input data when
      injectsbiterrb => '0', -- 1-bit input: Controls single bit error injection on input data when
      regcea => '1',                 -- 1-bit input: Clock Enable for the last register stage on the output
      regceb => '1',                 -- 1-bit input: Clock Enable for the last register stage on the output
      rsta => ram_rsta_cntr,                     -- 1-bit input: Reset signal for the final port A output register
      rstb => '0',                     -- 1-bit input: Reset signal for the final port B output register
      sleep => '0',                   -- 1-bit input: sleep signal to enable the dynamic power saving feature.
      wea => wea,                       -- WRITE_DATA_WIDTH_A-bit input: Write enable vector for port A input
      web => "0"                       -- WRITE_DATA_WIDTH_B-bit input: Write enable vector for port B input
   );
dina_cntr <= P_cntr(31 downto 12) & Dout3_cntr(3)(11 downto 0);
i_DSP_cntr : DSP48E2
   generic map (
      USE_MULT => "NONE",            -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE)
      -- Register Control Attributes: Pipeline Register Configuration
      ACASCREG => 0,                     -- Number of pipeline stages between A/ACIN and ACOUT (0-2)
      ALUMODEREG => 0,                   -- Pipeline stages for ALUMODE (0-1)
      AREG => 0,                         -- Pipeline stages for A (0-2)
      BCASCREG => 0,                     -- Number of pipeline stages between B/BCIN and BCOUT (0-2)
      BREG => 0,                         -- Pipeline stages for B (0-2)
      CARRYINREG => 0,                   -- Pipeline stages for CARRYIN (0-1)
      CARRYINSELREG => 0,                -- Pipeline stages for CARRYINSEL (0-1)
      CREG => 0,                         -- Pipeline stages for C (0-1)
      INMODEREG => 0,                    -- Pipeline stages for INMODE (0-1)
      MREG => 0,                         -- Multiplier pipeline stages (0-1)
      OPMODEREG => 0,                    -- Pipeline stages for OPMODE (0-1)
      PREG => 0                          -- Number of pipeline stages for P (0-1)
   )
   port map (
      P => P_cntr,                           -- 48-bit output: Primary data
      -- Cascade inputs: Cascade Ports
      ACIN => (others => '0'),                     -- 30-bit input: A cascade data
      BCIN => (others => '0'),                     -- 18-bit input: B cascade
      CARRYCASCIN => '0',       -- 1-bit input: Cascade carry
      MULTSIGNIN => '0',         -- 1-bit input: Multiplier sign cascade
      PCIN => (others => '0'),                     -- 48-bit input: P cascade
      -- Control inputs: Control Inputs/Status Bits
      ALUMODE => "0000",               -- 4-bit input: ALU control, W+X+Y+CIN+Z
      CARRYINSEL => "000",         -- 3-bit input: Carry select
      CLK => '0',                       -- 1-bit input: Clock
      INMODE => "00000",                 -- 5-bit input: INMODE control
      OPMODE => "000001111",                 -- 9-bit input: Operation mode W=0, Z=0, Y=C, X=A:B, CIN=0 => P=(A:B) + C
      -- Data inputs: Data Ports
      A => A_cntr,                           -- 30-bit input: A data
      B => B_cntr,                           -- 18-bit input: B data
      C => C_cntr,                           -- 48-bit input: C data
      CARRYIN => '0',               -- 1-bit input: Carry-in
      D => (others => '1'),                           -- 27-bit input: D data
      -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs
      CEA1 => '1',                     -- 1-bit input: Clock enable for 1st stage AREG
      CEA2 => '1',                     -- 1-bit input: Clock enable for 2nd stage AREG
      CEAD => '0',                     -- 1-bit input: Clock enable for ADREG
      CEALUMODE => '1',           -- 1-bit input: Clock enable for ALUMODE
      CEB1 => '1',                     -- 1-bit input: Clock enable for 1st stage BREG
      CEB2 => '1',                     -- 1-bit input: Clock enable for 2nd stage BREG
      CEC => '1',                       -- 1-bit input: Clock enable for CREG
      CECARRYIN => '1',           -- 1-bit input: Clock enable for CARRYINREG
      CECTRL => '1',                 -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG
      CED => '0',                       -- 1-bit input: Clock enable for DREG
      CEINMODE => '1',             -- 1-bit input: Clock enable for INMODEREG
      CEM => '0',                       -- 1-bit input: Clock enable for MREG
      CEP => '1',                       -- 1-bit input: Clock enable for PREG
      RSTA => '0',                     -- 1-bit input: Reset for AREG
      RSTALLCARRYIN => '0',   -- 1-bit input: Reset for CARRYINREG
      RSTALUMODE => '0',         -- 1-bit input: Reset for ALUMODEREG
      RSTB => '0',                     -- 1-bit input: Reset for BREG
      RSTC => '0',                     -- 1-bit input: Reset for CREG
      RSTCTRL => '0',               -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG
      RSTD => '0',                     -- 1-bit input: Reset for DREG and ADREG
      RSTINMODE => '0',           -- 1-bit input: Reset for INMODEREG
      RSTM => '0',                     -- 1-bit input: Reset for MREG
      RSTP => '0'                      -- 1-bit input: Reset for PREG
   );
B_cntr(11 downto 0) <= not Dout3_cntr(3)(11 downto 0);
B_cntr(17 downto 12) <= douta_cntr(17 downto 12);
A_cntr(13 downto 0) <= douta_cntr(31 downto 18);
C_cntr(11 downto 0) <= douta_cntr(11 downto 0);
process(clk)
begin
	if(clk'event and clk = '1')then
		if(clk_phase(7) = '1' and and_reduce(ram_addra_rate(7 downto 0)) = '1')then
			if(cycle_cntr = write_rate or (sim and cycle_cntr = "00000000000000100"))then
				save_rate <= '1';
			else
				save_rate <= '0';
			end if;
			if(save_rate = '1')then
				cycle_cntr <= (others => '0');
				ram_rsta_rate <= '1';
			else
				cycle_cntr <= cycle_cntr + 1;
				ram_rsta_rate <= '0';
			end if;
		end if;
		if(clk_phase(6) = '1' and and_reduce(ram_addra_rate(7 downto 0)) = '1' and (cycle_cntr = write_rate or (sim and cycle_cntr = "00000000000000100")))then
			reset_count_rate <= '1';
		else
			reset_count_rate <= '0';
		end if;
		load_count_rate <= clk_phase(6);
		if(clk_phase(7) = '1')then
			addr_rate <= addr_rate + 1;
			ram_addra_rate(7 downto 0) <= std_logic_vector(addr_rate);
		end if;
		ram_addra_rate(8) <= clk_phase(6) and save_rate;
	end if;
end process;
g_DSP_rate : for i in 0 to 63 generate
	 i_DSP_counterX4 : DSP_counterX4 generic map(use_sync => "1111")
		 PORT MAP (
			clk => clk,
			reset => reset_count_rate,
			din => rate_din(i*4+3 downto i*4),
			q => count(128+i)
		);
end generate g_DSP_rate;
process(clk)
begin
	if(clk'event and clk = '1')then
		if(clk_phase(7) = '1')then
			case addr_rate(4 downto 2) is
				when "000" => S1_rate <= x"02";
				when "001" => S1_rate <= x"03";
				when "010" => S1_rate <= x"08";
				when "011" => S1_rate <= x"0c";
				when "100" => S1_rate <= x"20";
				when "101" => S1_rate <= x"30";
				when "110" => S1_rate <= x"80";
				when others => S1_rate <= x"c0";
			end case;
			case addr_rate(7 downto 5) is
				when "000" => S2_rate <= x"02";
				when "001" => S2_rate <= x"03";
				when "010" => S2_rate <= x"08";
				when "011" => S2_rate <= x"0c";
				when "100" => S2_rate <= x"20";
				when "101" => S2_rate <= x"30";
				when "110" => S2_rate <= x"80";
				when others => S2_rate <= x"c0";
			end case;
			case addr_rate(1 downto 0) is
				when "00" => S3_rate <= x"2";
				when "01" => S3_rate <= x"3";
				when "10" => S3_rate <= x"8";
				when others => S3_rate <= x"c";
			end case;
		end if;
	end if;
end process;
g_DSP_MUX_rate_k : for j in 0 to 7 generate
		i_DSP_MUX_C_b : DSP_MUX_C_b
			port map(
				clk => clk,
				ce => load_count_rate,
				DinA => count(j*8+128),
				DinB => count(j*8+129),
				S => S1_rate(1 downto 0),
				PCOUT => PCOUT_rate(j*4),
				Dout => Dout_rate(j*4));
	g_DSP_MUX_i : for i in 1 to 3 generate
		i_DSP_MUX_C : DSP_MUX_C
			port map(
				clk => clk,
				ce => load_count_rate,
				DinA => count(j*8+i*2+128),
				DinB => count(j*8+i*2+129),
				PCIN => PCIN_rate(j*4+i),
				S => S1_rate(i*2+1 downto i*2),
				PCOUT => PCOUT_rate(j*4+i),
				Dout => Dout_rate(j*4+i));
	end generate g_DSP_MUX_i;
	g_PCIN : for i in 1 to 3 generate
		PCIN_rate(j*4+i) <= PCOUT_rate(j*4+i-1);
	end generate g_PCIN;
end generate g_DSP_MUX_rate_k;
i_DSP_MUX_b_rate : DSP_MUX_b
		port map(
			DinA => Dout_rate(3),
			DinB => Dout_rate(7),
			S => S2_rate(1 downto 0),
			PCOUT => PCOUT2_rate(0),
			Dout => Dout2_rate(0));
g_DSP_MUX_rate_i : for i in 1 to 3 generate
	i_DSP_MUX : DSP_MUX
		port map(
			DinA => Dout_rate(i*8+3),
			DinB => Dout_rate(i*8+7),
			PCIN => PCIN2_rate(i),
			S => S2_rate(i*2+1 downto i*2),
			PCOUT => PCOUT2_rate(i),
			Dout => Dout2_rate(i));
end generate g_DSP_MUX_rate_i;
g_PCIN2_rate : for i in 1 to 3 generate
	PCIN2_rate(i) <= PCOUT2_rate(i-1);
end generate g_PCIN2_rate;
g_Din_rate_i : for i in 0 to 3 generate
		Din_rate(i)(11 downto 0) <= Dout2_rate(3)(i*12+11 downto i*12);
end generate g_Din_rate_i;
i_DSP_MUX_b_rate0 : DSP_MUX_b
		port map(
		DinA => Din_rate(0),
		DinB => Din_rate(1),
		S => S3_rate(1 downto 0),
		PCOUT => PCOUT3_rate(0),
		Dout => Dout3_rate(0));
i_DSP_MUX_rate1 : DSP_MUX
		port map(
		DinA => Din_rate(2),
		DinB => Din_rate(3),
		PCIN => PCIN3_rate(1),
		S => S3_rate(3 downto 2),
		PCOUT => PCOUT3_rate(1),
		Dout => Dout3_rate(1));
PCIN3_rate(1) <= PCOUT3_rate(0);
i_ram_rate : xpm_memory_tdpram
   generic map (
      ADDR_WIDTH_A => 9,               -- DECIMAL
      ADDR_WIDTH_B => 9,               -- DECIMAL
      AUTO_SLEEP_TIME => 0,            -- DECIMAL
      CLOCKING_MODE => "independent_clock", -- String
      MEMORY_PRIMITIVE => "block",      -- String
      MEMORY_SIZE => 16384,             -- DECIMAL
      READ_LATENCY_A => 1,             -- DECIMAL
      READ_LATENCY_B => 1,             -- DECIMAL
      READ_RESET_VALUE_A => "00000000"       -- String
   )
   port map (
      douta => douta_rate,                   -- READ_DATA_WIDTH_A-bit output: Data output for port A read operations.
      doutb => doutb_rate,                   -- READ_DATA_WIDTH_B-bit output: Data output for port B read operations.
      addra => ram_addra_rate,                   -- ADDR_WIDTH_A-bit input: Address for port A write and read operations.
      addrb => ram_addrb_rate,                   -- ADDR_WIDTH_B-bit input: Address for port B write and read operations.
      clka => clk,                     -- 1-bit input: Clock signal for port A. Also clocks port B when
                                        -- parameter CLOCKING_MODE is "common_clock".

      clkb => ipb_clk,                     -- 1-bit input: Clock signal for port B when parameter CLOCKING_MODE is
                                        -- "independent_clock". Unused when parameter CLOCKING_MODE is
                                        -- "common_clock".

      dina => dina_rate,                     -- WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations.
      dinb => x"00000000",                     -- WRITE_DATA_WIDTH_B-bit input: Data input for port B write operations.
      ena => '1',                       -- 1-bit input: Memory enable signal for port A. Must be high on clock
                                        -- cycles when read or write operations are initiated. Pipelined
                                        -- internally.

      enb => '1',                       -- 1-bit input: Memory enable signal for port B. Must be high on clock
                                        -- cycles when read or write operations are initiated. Pipelined
                                        -- internally.

      injectdbiterra => '0', -- 1-bit input: Controls double bit error injection on input data when
      injectdbiterrb => '0', -- 1-bit input: Controls double bit error injection on input data when
      injectsbiterra => '0', -- 1-bit input: Controls single bit error injection on input data when
      injectsbiterrb => '0', -- 1-bit input: Controls single bit error injection on input data when
      regcea => '1',                 -- 1-bit input: Clock Enable for the last register stage on the output
      regceb => '1',                 -- 1-bit input: Clock Enable for the last register stage on the output
      rsta => ram_rsta_rate,                     -- 1-bit input: Reset signal for the final port A output register
      rstb => ipb_mosi_i.ipb_addr(8),                     -- 1-bit input: Reset signal for the final port B output register
      sleep => '0',                   -- 1-bit input: sleep signal to enable the dynamic power saving feature.
      wea => wea,                       -- WRITE_DATA_WIDTH_A-bit input: Write enable vector for port A input
      web => "0"                       -- WRITE_DATA_WIDTH_B-bit input: Write enable vector for port B input
   );
dina_rate <= P_rate(31 downto 12) & Dout3_rate(1)(11 downto 0);
ram_addrb_rate <= '1' & ipb_mosi_i.ipb_addr(7 downto 0);
i_DSP_rate : DSP48E2
   generic map (
      USE_MULT => "NONE",            -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE)
      -- Register Control Attributes: Pipeline Register Configuration
      ACASCREG => 0,                     -- Number of pipeline stages between A/ACIN and ACOUT (0-2)
      ALUMODEREG => 0,                   -- Pipeline stages for ALUMODE (0-1)
      AREG => 0,                         -- Pipeline stages for A (0-2)
      BCASCREG => 0,                     -- Number of pipeline stages between B/BCIN and BCOUT (0-2)
      BREG => 0,                         -- Pipeline stages for B (0-2)
      CARRYINREG => 0,                   -- Pipeline stages for CARRYIN (0-1)
      CARRYINSELREG => 0,                -- Pipeline stages for CARRYINSEL (0-1)
      CREG => 0,                         -- Pipeline stages for C (0-1)
      INMODEREG => 0,                    -- Pipeline stages for INMODE (0-1)
      MREG => 0,                         -- Multiplier pipeline stages (0-1)
      OPMODEREG => 0,                    -- Pipeline stages for OPMODE (0-1)
      PREG => 0                          -- Number of pipeline stages for P (0-1)
   )
   port map (
      P => P_rate,                           -- 48-bit output: Primary data
      -- Cascade inputs: Cascade Ports
      ACIN => (others => '0'),                     -- 30-bit input: A cascade data
      BCIN => (others => '0'),                     -- 18-bit input: B cascade
      CARRYCASCIN => '0',       -- 1-bit input: Cascade carry
      MULTSIGNIN => '0',         -- 1-bit input: Multiplier sign cascade
      PCIN => (others => '0'),                     -- 48-bit input: P cascade
      -- Control inputs: Control Inputs/Status Bits
      ALUMODE => "0000",               -- 4-bit input: ALU control, W+X+Y+CIN+Z
      CARRYINSEL => "000",         -- 3-bit input: Carry select
      CLK => '0',                       -- 1-bit input: Clock
      INMODE => "00000",                 -- 5-bit input: INMODE control
      OPMODE => "000001111",                 -- 9-bit input: Operation mode W=0, Z=0, Y=C, X=A:B, CIN=0 => P=(A:B) + C
      -- Data inputs: Data Ports
      A => A_rate,                           -- 30-bit input: A data
      B => B_rate,                           -- 18-bit input: B data
      C => C_rate,                           -- 48-bit input: C data
      CARRYIN => '0',               -- 1-bit input: Carry-in
      D => (others => '1'),                           -- 27-bit input: D data
      -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs
      CEA1 => '1',                     -- 1-bit input: Clock enable for 1st stage AREG
      CEA2 => '1',                     -- 1-bit input: Clock enable for 2nd stage AREG
      CEAD => '0',                     -- 1-bit input: Clock enable for ADREG
      CEALUMODE => '1',           -- 1-bit input: Clock enable for ALUMODE
      CEB1 => '1',                     -- 1-bit input: Clock enable for 1st stage BREG
      CEB2 => '1',                     -- 1-bit input: Clock enable for 2nd stage BREG
      CEC => '1',                       -- 1-bit input: Clock enable for CREG
      CECARRYIN => '1',           -- 1-bit input: Clock enable for CARRYINREG
      CECTRL => '1',                 -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG
      CED => '0',                       -- 1-bit input: Clock enable for DREG
      CEINMODE => '1',             -- 1-bit input: Clock enable for INMODEREG
      CEM => '0',                       -- 1-bit input: Clock enable for MREG
      CEP => '1',                       -- 1-bit input: Clock enable for PREG
      RSTA => '0',                     -- 1-bit input: Reset for AREG
      RSTALLCARRYIN => '0',   -- 1-bit input: Reset for CARRYINREG
      RSTALUMODE => '0',         -- 1-bit input: Reset for ALUMODEREG
      RSTB => '0',                     -- 1-bit input: Reset for BREG
      RSTC => '0',                     -- 1-bit input: Reset for CREG
      RSTCTRL => '0',               -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG
      RSTD => '0',                     -- 1-bit input: Reset for DREG and ADREG
      RSTINMODE => '0',           -- 1-bit input: Reset for INMODEREG
      RSTM => '0',                     -- 1-bit input: Reset for MREG
      RSTP => '0'                      -- 1-bit input: Reset for PREG
   );
B_rate(11 downto 0) <= not Dout3_rate(1)(11 downto 0);
B_rate(17 downto 12) <= douta_rate(17 downto 12);
A_rate(13 downto 0) <= douta_rate(31 downto 18);
C_rate(11 downto 0) <= douta_rate(11 downto 0);
end Behavioral;