2020.2:
 * Version 5.0 (Rev. 9)
 * General: Chip2Chip Versal Block Automation Updated.
 * Revision change in one or more subcores

2020.1.1:
 * Version 5.0 (Rev. 8)
 * No changes

2020.1:
 * Version 5.0 (Rev. 8)
 * General: C2C Migration to Versal.
 * Revision change in one or more subcores

2019.2.2:
 * Version 5.0 (Rev. 7)
 * No changes

2019.2.1:
 * Version 5.0 (Rev. 7)
 * No changes

2019.2:
 * Version 5.0 (Rev. 7)
 * Revision change in one or more subcores

2019.1.3:
 * Version 5.0 (Rev. 6)
 * No changes

2019.1.2:
 * Version 5.0 (Rev. 6)
 * No changes

2019.1.1:
 * Version 5.0 (Rev. 6)
 * Bug Fix: Bug fix for VIRTEXUPLUS58GES1 devices with Select IO configuration

2019.1:
 * Version 5.0 (Rev. 5)
 * General: Migrated Aurora 64B66B subcore from 11.2 to 12.0.
 * Revision change in one or more subcores

2018.3.1:
 * Version 5.0 (Rev. 4)
 * No changes

2018.3:
 * Version 5.0 (Rev. 4)
 * General: Improved open_checkpoint runtime by re-writing inefficient get_pins queries.
 * Revision change in one or more subcores

2018.2:
 * Version 5.0 (Rev. 3)
 * Bug Fix: IP updated to handle SelectIO link up issues between 7series and US/US+ architectures
 * Bug Fix: AXI4 Lite Base and High address exported to SDK
 * Other: XDCs updated for runtime improvement
 * Revision change in one or more subcores

2018.1:
 * Version 5.0 (Rev. 2)
 * Bug Fix: IP updated to handle interrupts more reliably
 * Revision change in one or more subcores

2017.4:
 * Version 5.0 (Rev. 1)
 * Revision change in one or more subcores

2017.3:
 * Version 5.0
 * Feature Enhancement: IP now comes with a AXI4 safety circuit
 * Feature Enhancement: IP version updated as there is a change in IO / Lane calculations
 * Revision change in one or more subcores

2017.2:
 * Version 4.3 (Rev. 1)
 * Bug Fix: Reset sequence update for better timing in selectio mode.
 * Revision change in one or more subcores

2017.1:
 * Version 4.3
 * Bug Fix: Reset sequence update for better timing in selectio mode.
 * Bug Fix: Improved GUI speed and responsiveness
 * Feature Enhancement: Support for ID width upto 24
 * Revision change in one or more subcores

2016.4:
 * Version 4.2 (Rev. 11)
 * Revision change in one or more subcores

2016.3:
 * Version 4.2 (Rev. 10)
 * Bug Fix: IP updated to avoid cascading of BUFGs
 * Revision change in one or more subcores

2016.2:
 * Version 4.2 (Rev. 9)
 * Revision change in one or more subcores

2016.1:
 * Version 4.2 (Rev. 8)
 * Aurora_8b10b single lane support added for 32-bit configuration
 * Helper core version fifo_generator_v13_1 update and safety circuit enablement for safe fifo reset operation. No other functional changes.
 * Revision change in one or more subcores

2015.4.2:
 * Version 4.2 (Rev. 7)
 * No changes

2015.4.1:
 * Version 4.2 (Rev. 7)
 * No changes

2015.4:
 * Version 4.2 (Rev. 7)
 * Example design update for Aurora drpaddr port width mismatch.No functional changes
 * Revision change in one or more subcores

2015.3:
 * Version 4.2 (Rev. 6)
 * Added upto 64-bit address width support for AXI4 master interface
 * Helper core version update (fifo_generator_v13_0)
 * IP core XDC updated as per helper core fifo XDC update
 * Example design updated to use Aurora_64b66b_v11_0
 * Enabled example design support for aurora configuration with ultrascale plus devices
 * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
 * Revision change in one or more subcores

2015.2.1:
 * Version 4.2 (Rev. 5)
 * No changes

2015.2:
 * Version 4.2 (Rev. 5)
 * GUI related updates
 * Example design minor updates, no functional changes

2015.1:
 * Version 4.2 (Rev. 4)
 * Enhanced support for 128 data width and 64 address width
 * Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to all clock interfaces
 * Example design updated to use Aurora64b66b_v10 and Aurora8b10b_v11
 * Supported devices and production status are now determined automatically, to simplify support for future devices

2014.4.1:
 * Version 4.2 (Rev. 3)
 * No changes

2014.4:
 * Version 4.2 (Rev. 3)
 * Enhanced support for IP Integrator

2014.3:
 * Version 4.2 (Rev. 2)
 * Added 12 bit ID Width support on AXI Interfaces
 * Added beta support for optional Aurora 8B10B interface

2014.2:
 * Version 4.2 (Rev. 1)
 * Updated example design IO constraints

2014.1:
 * Version 4.2
 * Added AURORA 64b66b 2-lane support
 * Included aurora do_cc and pma_init generation logic
 * Internal device family name change, no functional changes
 * Virtex UltraScale Pre-Production support

2013.4:
 * Version 4.1 (Rev. 1)
 * Kintex UltraScale Pre-Production support
 * Added beta support for optional Aurora 64B66B interface
 * Updated core constraints to accommodate helper core (fifo_generator_v11_0) hierarchy updates

2013.3:
 * Version 4.1
 * Added example design
 * Added demonstration testbench
 * Reduced warnings in synthesis and simulation
 * Enhanced support for IP Integrator
 * Added support for Cadence IES and Synopsys VCS simulators
 * Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability

2013.2:
 * Version 4.0 (Rev. 1)
 * Constraints processing order changed
 * Increased the range of parameter C_AXI_SIZE_WIDTH from 2 to 3

2013.1:
 * Version 4.0
 * Initial Vivado Release
 * There have been no functional or interface changes to this IP.  The version number has changed to support unique versioning in Vivado starting with 2013.1

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