// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 // Date : Fri Mar 12 21:30:37 2021 // Host : baby running 64-bit major release (build 9200) // Command : write_verilog -force -mode funcsim // d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/axi_chip2chip_64B66B/axi_chip2chip_64B66B_sim_netlist.v // Design : axi_chip2chip_64B66B // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. // Device : xcku115-flva2104-1-c // -------------------------------------------------------------------------------- `timescale 1 ps / 1 ps (* CHECK_LICENSE_TYPE = "axi_chip2chip_64B66B,axi_chip2chip_v5_0_9,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_chip2chip_v5_0_9,Vivado 2020.2" *) (* NotValidForBitStream *) module axi_chip2chip_64B66B (m_aclk, m_aresetn, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize, m_axi_awburst, m_axi_awvalid, m_axi_awready, m_axi_wuser, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid, m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_arid, m_axi_araddr, m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arvalid, m_axi_arready, m_axi_rid, m_axi_rdata, m_axi_rresp, m_axi_rlast, m_axi_rvalid, m_axi_rready, axi_c2c_s2m_intr_in, axi_c2c_m2s_intr_out, axi_c2c_phy_clk, axi_c2c_aurora_channel_up, axi_c2c_aurora_tx_tready, axi_c2c_aurora_tx_tdata, axi_c2c_aurora_tx_tvalid, axi_c2c_aurora_rx_tdata, axi_c2c_aurora_rx_tvalid, aurora_do_cc, aurora_pma_init_in, aurora_init_clk, aurora_pma_init_out, aurora_mmcm_not_locked, aurora_reset_pb, axi_c2c_config_error_out, axi_c2c_link_status_out, axi_c2c_multi_bit_error_out); (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m_aclk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_aclk, ASSOCIATED_BUSIF m_axi, ASSOCIATED_RESET m_aresetn, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0" *) input m_aclk; (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 m_aresetn RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_aresetn, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input m_aresetn; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi AWID" *) output [5:0]m_axi_awid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi AWADDR" *) output [31:0]m_axi_awaddr; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi AWLEN" *) output [7:0]m_axi_awlen; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi AWSIZE" *) output [2:0]m_axi_awsize; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi AWBURST" *) output [1:0]m_axi_awburst; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi AWVALID" *) output m_axi_awvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi AWREADY" *) input m_axi_awready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi WUSER" *) output [3:0]m_axi_wuser; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi WDATA" *) output [31:0]m_axi_wdata; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi WSTRB" *) output [3:0]m_axi_wstrb; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi WLAST" *) output m_axi_wlast; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi WVALID" *) output m_axi_wvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi WREADY" *) input m_axi_wready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi BID" *) input [5:0]m_axi_bid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi BRESP" *) input [1:0]m_axi_bresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi BVALID" *) input m_axi_bvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi BREADY" *) output m_axi_bready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi ARID" *) output [5:0]m_axi_arid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi ARADDR" *) output [31:0]m_axi_araddr; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi ARLEN" *) output [7:0]m_axi_arlen; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi ARSIZE" *) output [2:0]m_axi_arsize; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi ARBURST" *) output [1:0]m_axi_arburst; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi ARVALID" *) output m_axi_arvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi ARREADY" *) input m_axi_arready; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi RID" *) input [5:0]m_axi_rid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi RDATA" *) input [31:0]m_axi_rdata; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi RRESP" *) input [1:0]m_axi_rresp; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi RLAST" *) input m_axi_rlast; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi RVALID" *) input m_axi_rvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m_axi RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_axi, NUM_READ_OUTSTANDING 16, NUM_WRITE_OUTSTANDING 16, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 6, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 4, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, MAX_BURST_LENGTH 256, PHASE 0.000, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *) output m_axi_rready; input [3:0]axi_c2c_s2m_intr_in; output [3:0]axi_c2c_m2s_intr_out; (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 axi_c2c_phy_clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME axi_c2c_phy_clk, ASSOCIATED_BUSIF AXIS_TX:AXIS_RX, ASSOCIATED_RESET aurora_reset_pb, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0" *) input axi_c2c_phy_clk; input axi_c2c_aurora_channel_up; (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 AXIS_TX TREADY" *) input axi_c2c_aurora_tx_tready; (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 AXIS_TX TDATA" *) output [63:0]axi_c2c_aurora_tx_tdata; (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 AXIS_TX TVALID" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME AXIS_TX, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0" *) output axi_c2c_aurora_tx_tvalid; (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 AXIS_RX TDATA" *) input [63:0]axi_c2c_aurora_rx_tdata; (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 AXIS_RX TVALID" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME AXIS_RX, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.000, LAYERED_METADATA undef, INSERT_VIP 0" *) input axi_c2c_aurora_rx_tvalid; output aurora_do_cc; (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 AURORA_PMA_INIT_IN RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME AURORA_PMA_INIT_IN, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) input aurora_pma_init_in; (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 INIT_CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME INIT_CLK, ASSOCIATED_RESET aurora_pma_init_out, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0" *) input aurora_init_clk; (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 AURORA_PMA_INIT_OUT RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME AURORA_PMA_INIT_OUT, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) output aurora_pma_init_out; (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 AURORA_MMCM_NOT_LOCKED RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME AURORA_MMCM_NOT_LOCKED, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) input aurora_mmcm_not_locked; (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 AURORA_RST_OUT RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME AURORA_RST_OUT, POLARITY ACTIVE_HIGH, INSERT_VIP 0" *) output aurora_reset_pb; output axi_c2c_config_error_out; output axi_c2c_link_status_out; output axi_c2c_multi_bit_error_out; wire \ ; wire aurora_do_cc; wire aurora_init_clk; wire aurora_mmcm_not_locked; wire aurora_pma_init_in; wire aurora_pma_init_out; wire aurora_reset_pb; wire axi_c2c_aurora_channel_up; wire [63:0]axi_c2c_aurora_rx_tdata; wire axi_c2c_aurora_rx_tvalid; wire [63:0]\^axi_c2c_aurora_tx_tdata ; wire axi_c2c_aurora_tx_tready; wire axi_c2c_aurora_tx_tvalid; wire axi_c2c_link_status_out; wire [3:0]axi_c2c_m2s_intr_out; wire axi_c2c_multi_bit_error_out; wire axi_c2c_phy_clk; wire [3:0]axi_c2c_s2m_intr_in; wire m_aclk; wire m_aresetn; wire [31:0]m_axi_araddr; wire [1:0]m_axi_arburst; wire [5:0]m_axi_arid; wire [7:0]m_axi_arlen; wire m_axi_arready; wire [1:0]\^m_axi_arsize ; wire m_axi_arvalid; wire [31:0]m_axi_awaddr; wire [1:0]m_axi_awburst; wire [5:0]m_axi_awid; wire [7:0]m_axi_awlen; wire m_axi_awready; wire [1:0]\^m_axi_awsize ; wire m_axi_awvalid; wire [5:0]m_axi_bid; wire m_axi_bready; wire [1:0]m_axi_bresp; wire m_axi_bvalid; wire [31:0]m_axi_rdata; wire [5:0]m_axi_rid; wire m_axi_rlast; wire m_axi_rready; wire [1:0]m_axi_rresp; wire m_axi_rvalid; wire [31:0]m_axi_wdata; wire m_axi_wlast; wire m_axi_wready; wire [3:0]m_axi_wstrb; wire [3:0]m_axi_wuser; wire m_axi_wvalid; wire NLW_inst_axi_c2c_config_error_out_UNCONNECTED; wire NLW_inst_axi_c2c_link_error_out_UNCONNECTED; wire NLW_inst_axi_c2c_lnk_hndlr_in_progress_UNCONNECTED; wire NLW_inst_axi_c2c_selio_tx_clk_out_UNCONNECTED; wire NLW_inst_axi_c2c_selio_tx_diff_clk_out_n_UNCONNECTED; wire NLW_inst_axi_c2c_selio_tx_diff_clk_out_p_UNCONNECTED; wire NLW_inst_m_aclk_out_UNCONNECTED; wire NLW_inst_m_axi_lite_arvalid_UNCONNECTED; wire NLW_inst_m_axi_lite_awvalid_UNCONNECTED; wire NLW_inst_m_axi_lite_bready_UNCONNECTED; wire NLW_inst_m_axi_lite_rready_UNCONNECTED; wire NLW_inst_m_axi_lite_wvalid_UNCONNECTED; wire NLW_inst_s_axi_arready_UNCONNECTED; wire NLW_inst_s_axi_awready_UNCONNECTED; wire NLW_inst_s_axi_bvalid_UNCONNECTED; wire NLW_inst_s_axi_lite_arready_UNCONNECTED; wire NLW_inst_s_axi_lite_awready_UNCONNECTED; wire NLW_inst_s_axi_lite_bvalid_UNCONNECTED; wire NLW_inst_s_axi_lite_rvalid_UNCONNECTED; wire NLW_inst_s_axi_lite_wready_UNCONNECTED; wire NLW_inst_s_axi_rlast_UNCONNECTED; wire NLW_inst_s_axi_rvalid_UNCONNECTED; wire NLW_inst_s_axi_wready_UNCONNECTED; wire [62:62]NLW_inst_axi_c2c_aurora_tx_tdata_UNCONNECTED; wire [3:0]NLW_inst_axi_c2c_s2m_intr_out_UNCONNECTED; wire [8:0]NLW_inst_axi_c2c_selio_tx_data_out_UNCONNECTED; wire [8:0]NLW_inst_axi_c2c_selio_tx_diff_data_out_n_UNCONNECTED; wire [8:0]NLW_inst_axi_c2c_selio_tx_diff_data_out_p_UNCONNECTED; wire [2:2]NLW_inst_m_axi_arsize_UNCONNECTED; wire [2:2]NLW_inst_m_axi_awsize_UNCONNECTED; wire [31:0]NLW_inst_m_axi_lite_araddr_UNCONNECTED; wire [1:0]NLW_inst_m_axi_lite_arprot_UNCONNECTED; wire [31:0]NLW_inst_m_axi_lite_awaddr_UNCONNECTED; wire [1:0]NLW_inst_m_axi_lite_awprot_UNCONNECTED; wire [31:0]NLW_inst_m_axi_lite_wdata_UNCONNECTED; wire [3:0]NLW_inst_m_axi_lite_wstrb_UNCONNECTED; wire [5:0]NLW_inst_s_axi_bid_UNCONNECTED; wire [1:0]NLW_inst_s_axi_bresp_UNCONNECTED; wire [1:0]NLW_inst_s_axi_lite_bresp_UNCONNECTED; wire [31:0]NLW_inst_s_axi_lite_rdata_UNCONNECTED; wire [1:0]NLW_inst_s_axi_lite_rresp_UNCONNECTED; wire [31:0]NLW_inst_s_axi_rdata_UNCONNECTED; wire [5:0]NLW_inst_s_axi_rid_UNCONNECTED; wire [1:0]NLW_inst_s_axi_rresp_UNCONNECTED; assign axi_c2c_aurora_tx_tdata[63] = \^axi_c2c_aurora_tx_tdata [63]; assign axi_c2c_aurora_tx_tdata[62] = \ ; assign axi_c2c_aurora_tx_tdata[61:0] = \^axi_c2c_aurora_tx_tdata [61:0]; assign axi_c2c_config_error_out = \ ; assign m_axi_arsize[2] = \ ; assign m_axi_arsize[1:0] = \^m_axi_arsize [1:0]; assign m_axi_awsize[2] = \ ; assign m_axi_awsize[1:0] = \^m_axi_awsize [1:0]; GND GND (.G(\ )); (* ADDR_MUX_RATIO = "1" *) (* ADDR_MUX_RATIO_ID_WID_0_TO_12 = "1" *) (* AFIFO_DATA_SIZE = "50" *) (* AFIFO_DATA_SIZE_M2 = "0" *) (* AFIFO_DATA_SIZE_M3 = "2" *) (* AFIFO_DATA_SIZE_M4 = "2" *) (* AFIFO_TIE_WIDTH = "1" *) (* AFIFO_WIDTH = "50" *) (* AR_CH_FC = "128" *) (* AR_CH_FIFO_DEPTH = "256" *) (* AR_CH_PTR_WIDTH = "8" *) (* AWB_FC_WIDTH = "2" *) (* AW_CH_FC = "128" *) (* AW_CH_FIFO_DEPTH = "256" *) (* AW_CH_PTR_WIDTH = "8" *) (* AXILITE_WIDTH = "20" *) (* BFIFO_DATA_SIZE = "8" *) (* BFIFO_WIDTH = "8" *) (* BR_CH_FC = "128" *) (* BR_CH_FIFO_DEPTH = "256" *) (* BR_CH_PTR_WIDTH = "8" *) (* C_AURORA_WIDTH = "64" *) (* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_BRST_WIDTH = "2" *) (* C_AXI_BUS_TYPE = "0" *) (* C_AXI_DATA_WIDTH = "32" *) (* C_AXI_ID_WIDTH = "6" *) (* C_AXI_LEN_WIDTH = "8" *) (* C_AXI_LITE_ADDR_WIDTH = "32" *) (* C_AXI_LITE_DATA_WIDTH = "32" *) (* C_AXI_LITE_PROT_WIDTH = "2" *) (* C_AXI_LITE_RESP_WIDTH = "2" *) (* C_AXI_LITE_STB_WIDTH = "4" *) (* C_AXI_RESP_WIDTH = "2" *) (* C_AXI_SIZE_WIDTH = "3" *) (* C_AXI_SIZE_WIDTH_INTERNAL = "2" *) (* C_AXI_STB_WIDTH = "4" *) (* C_AXI_WUSER_WIDTH = "4" *) (* C_COMMON_CLK = "0" *) (* C_DISABLE_CLK_SHIFT = "0" *) (* C_DISABLE_DESKEW = "0" *) (* C_ECC_ENABLE = "1" *) (* C_EN_AXI_LINK_HNDLR = "0" *) (* C_EN_LEGACY_MODE = "0" *) (* C_FAMILY = "kintexu" *) (* C_FIFO_DEPTH_LH = "256" *) (* C_INCLUDE_AXILITE = "0" *) (* C_INSTANCE = "axi_c2c" *) (* C_INTERFACE_MODE = "0" *) (* C_INTERFACE_TYPE = "2" *) (* C_INTERRUPT_WIDTH = "4" *) (* C_MASTER_FPGA = "0" *) (* C_NUM_OF_IO = "20" *) (* C_PHY_SELECT = "1" *) (* C_RD_CNTR_WIDTH = "8" *) (* C_SELECTIO_DDR = "0" *) (* C_SELECTIO_PHY_CLK = "100" *) (* C_SELECTIO_WIDTH = "9" *) (* C_SIMULATION = "0" *) (* C_SYNC_STAGE = "3" *) (* C_USE_DIFF_CLK = "0" *) (* C_USE_DIFF_IO = "0" *) (* C_WIDTH_CONVERSION = "1" *) (* C_WR_CNTR_WIDTH = "8" *) (* DATA_MUX_RATIO = "1" *) (* DATA_MUX_RATIO_ID_WID_0_TO_12 = "1" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* EN_ECC = "1" *) (* PHY_CTRL_WIDTH = "3" *) (* PHY_DATA_WIDTH = "64" *) (* RB_FC_WIDTH = "3" *) (* RFIFO_DATA_SIZE = "41" *) (* RFIFO_DATA_SIZE_M2 = "1" *) (* RFIFO_DATA_SIZE_M3 = "2" *) (* RFIFO_DATA_SIZE_M4 = "1" *) (* RFIFO_TIE_WIDTH = "1" *) (* RFIFO_WIDTH = "41" *) (* TDM_ID_WIDTH = "2" *) (* TDM_VAL_BITS = "1" *) (* WFIFO_DATA_SIZE = "41" *) (* WFIFO_DATA_SIZE_M2 = "1" *) (* WFIFO_DATA_SIZE_M3 = "2" *) (* WFIFO_DATA_SIZE_M4 = "1" *) (* WFIFO_TIE_WIDTH = "1" *) (* WFIFO_WIDTH = "41" *) (* is_du_within_envelope = "true" *) axi_chip2chip_64B66B_axi_chip2chip_v5_0_9 inst (.aurora_do_cc(aurora_do_cc), .aurora_init_clk(aurora_init_clk), .aurora_mmcm_not_locked(aurora_mmcm_not_locked), .aurora_pma_init_in(aurora_pma_init_in), .aurora_pma_init_out(aurora_pma_init_out), .aurora_reset_pb(aurora_reset_pb), .axi_c2c_aurora_channel_up(axi_c2c_aurora_channel_up), .axi_c2c_aurora_rx_tdata(axi_c2c_aurora_rx_tdata), .axi_c2c_aurora_rx_tvalid(axi_c2c_aurora_rx_tvalid), .axi_c2c_aurora_tx_tdata(\^axi_c2c_aurora_tx_tdata ), .axi_c2c_aurora_tx_tready(axi_c2c_aurora_tx_tready), .axi_c2c_aurora_tx_tvalid(axi_c2c_aurora_tx_tvalid), .axi_c2c_config_error_out(NLW_inst_axi_c2c_config_error_out_UNCONNECTED), .axi_c2c_link_error_out(NLW_inst_axi_c2c_link_error_out_UNCONNECTED), .axi_c2c_link_status_out(axi_c2c_link_status_out), .axi_c2c_lnk_hndlr_in_progress(NLW_inst_axi_c2c_lnk_hndlr_in_progress_UNCONNECTED), .axi_c2c_m2s_intr_in({1'b0,1'b0,1'b0,1'b0}), .axi_c2c_m2s_intr_out(axi_c2c_m2s_intr_out), .axi_c2c_multi_bit_error_out(axi_c2c_multi_bit_error_out), .axi_c2c_phy_clk(axi_c2c_phy_clk), .axi_c2c_s2m_intr_in(axi_c2c_s2m_intr_in), .axi_c2c_s2m_intr_out(NLW_inst_axi_c2c_s2m_intr_out_UNCONNECTED[3:0]), .axi_c2c_selio_rx_clk_in(1'b0), .axi_c2c_selio_rx_data_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axi_c2c_selio_rx_diff_clk_in_n(1'b0), .axi_c2c_selio_rx_diff_clk_in_p(1'b0), .axi_c2c_selio_rx_diff_data_in_n({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axi_c2c_selio_rx_diff_data_in_p({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axi_c2c_selio_tx_clk_out(NLW_inst_axi_c2c_selio_tx_clk_out_UNCONNECTED), .axi_c2c_selio_tx_data_out(NLW_inst_axi_c2c_selio_tx_data_out_UNCONNECTED[8:0]), .axi_c2c_selio_tx_diff_clk_out_n(NLW_inst_axi_c2c_selio_tx_diff_clk_out_n_UNCONNECTED), .axi_c2c_selio_tx_diff_clk_out_p(NLW_inst_axi_c2c_selio_tx_diff_clk_out_p_UNCONNECTED), .axi_c2c_selio_tx_diff_data_out_n(NLW_inst_axi_c2c_selio_tx_diff_data_out_n_UNCONNECTED[8:0]), .axi_c2c_selio_tx_diff_data_out_p(NLW_inst_axi_c2c_selio_tx_diff_data_out_p_UNCONNECTED[8:0]), .idelay_ref_clk(1'b0), .m_aclk(m_aclk), .m_aclk_out(NLW_inst_m_aclk_out_UNCONNECTED), .m_aresetn(m_aresetn), .m_axi_araddr(m_axi_araddr), .m_axi_arburst(m_axi_arburst), .m_axi_arid(m_axi_arid), .m_axi_arlen(m_axi_arlen), .m_axi_arready(m_axi_arready), .m_axi_arsize({NLW_inst_m_axi_arsize_UNCONNECTED[2],\^m_axi_arsize }), .m_axi_arvalid(m_axi_arvalid), .m_axi_awaddr(m_axi_awaddr), .m_axi_awburst(m_axi_awburst), .m_axi_awid(m_axi_awid), .m_axi_awlen(m_axi_awlen), .m_axi_awready(m_axi_awready), .m_axi_awsize({NLW_inst_m_axi_awsize_UNCONNECTED[2],\^m_axi_awsize }), .m_axi_awvalid(m_axi_awvalid), .m_axi_bid(m_axi_bid), .m_axi_bready(m_axi_bready), .m_axi_bresp(m_axi_bresp), .m_axi_bvalid(m_axi_bvalid), .m_axi_lite_aclk(1'b0), .m_axi_lite_araddr(NLW_inst_m_axi_lite_araddr_UNCONNECTED[31:0]), .m_axi_lite_arprot(NLW_inst_m_axi_lite_arprot_UNCONNECTED[1:0]), .m_axi_lite_arready(1'b0), .m_axi_lite_arvalid(NLW_inst_m_axi_lite_arvalid_UNCONNECTED), .m_axi_lite_awaddr(NLW_inst_m_axi_lite_awaddr_UNCONNECTED[31:0]), .m_axi_lite_awprot(NLW_inst_m_axi_lite_awprot_UNCONNECTED[1:0]), .m_axi_lite_awready(1'b0), .m_axi_lite_awvalid(NLW_inst_m_axi_lite_awvalid_UNCONNECTED), .m_axi_lite_bready(NLW_inst_m_axi_lite_bready_UNCONNECTED), .m_axi_lite_bresp({1'b0,1'b0}), .m_axi_lite_bvalid(1'b0), .m_axi_lite_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .m_axi_lite_rready(NLW_inst_m_axi_lite_rready_UNCONNECTED), .m_axi_lite_rresp({1'b0,1'b0}), .m_axi_lite_rvalid(1'b0), .m_axi_lite_wdata(NLW_inst_m_axi_lite_wdata_UNCONNECTED[31:0]), .m_axi_lite_wready(1'b0), .m_axi_lite_wstrb(NLW_inst_m_axi_lite_wstrb_UNCONNECTED[3:0]), .m_axi_lite_wvalid(NLW_inst_m_axi_lite_wvalid_UNCONNECTED), .m_axi_rdata(m_axi_rdata), .m_axi_rid(m_axi_rid), .m_axi_rlast(m_axi_rlast), .m_axi_rready(m_axi_rready), .m_axi_rresp(m_axi_rresp), .m_axi_rvalid(m_axi_rvalid), .m_axi_wdata(m_axi_wdata), .m_axi_wlast(m_axi_wlast), .m_axi_wready(m_axi_wready), .m_axi_wstrb(m_axi_wstrb), .m_axi_wuser(m_axi_wuser), .m_axi_wvalid(m_axi_wvalid), .s_aclk(1'b0), .s_aresetn(1'b1), .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_arburst({1'b0,1'b0}), .s_axi_arid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_arready(NLW_inst_s_axi_arready_UNCONNECTED), .s_axi_arsize({1'b0,1'b0,1'b0}), .s_axi_arvalid(1'b0), .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_awburst({1'b0,1'b0}), .s_axi_awid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_awready(NLW_inst_s_axi_awready_UNCONNECTED), .s_axi_awsize({1'b0,1'b0,1'b0}), .s_axi_awvalid(1'b0), .s_axi_bid(NLW_inst_s_axi_bid_UNCONNECTED[5:0]), .s_axi_bready(1'b0), .s_axi_bresp(NLW_inst_s_axi_bresp_UNCONNECTED[1:0]), .s_axi_bvalid(NLW_inst_s_axi_bvalid_UNCONNECTED), .s_axi_lite_aclk(1'b0), .s_axi_lite_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_lite_arprot({1'b0,1'b0}), .s_axi_lite_arready(NLW_inst_s_axi_lite_arready_UNCONNECTED), .s_axi_lite_arvalid(1'b0), .s_axi_lite_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_lite_awprot({1'b0,1'b0}), .s_axi_lite_awready(NLW_inst_s_axi_lite_awready_UNCONNECTED), .s_axi_lite_awvalid(1'b0), .s_axi_lite_bready(1'b0), .s_axi_lite_bresp(NLW_inst_s_axi_lite_bresp_UNCONNECTED[1:0]), .s_axi_lite_bvalid(NLW_inst_s_axi_lite_bvalid_UNCONNECTED), .s_axi_lite_rdata(NLW_inst_s_axi_lite_rdata_UNCONNECTED[31:0]), .s_axi_lite_rready(1'b0), .s_axi_lite_rresp(NLW_inst_s_axi_lite_rresp_UNCONNECTED[1:0]), .s_axi_lite_rvalid(NLW_inst_s_axi_lite_rvalid_UNCONNECTED), .s_axi_lite_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_lite_wready(NLW_inst_s_axi_lite_wready_UNCONNECTED), .s_axi_lite_wstrb({1'b0,1'b0,1'b0,1'b0}), .s_axi_lite_wvalid(1'b0), .s_axi_rdata(NLW_inst_s_axi_rdata_UNCONNECTED[31:0]), .s_axi_rid(NLW_inst_s_axi_rid_UNCONNECTED[5:0]), .s_axi_rlast(NLW_inst_s_axi_rlast_UNCONNECTED), .s_axi_rready(1'b0), .s_axi_rresp(NLW_inst_s_axi_rresp_UNCONNECTED[1:0]), .s_axi_rvalid(NLW_inst_s_axi_rvalid_UNCONNECTED), .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_wlast(1'b0), .s_axi_wready(NLW_inst_s_axi_wready_UNCONNECTED), .s_axi_wstrb({1'b0,1'b0,1'b0,1'b0}), .s_axi_wuser({1'b0,1'b0,1'b0,1'b0}), .s_axi_wvalid(1'b0)); endmodule (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "8" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *) module axi_chip2chip_64B66B_xpm_cdc_gray (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [7:0]src_in_bin; input dest_clk; output [7:0]dest_out_bin; wire [7:0]async_path; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[1] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[2] ; wire [6:0]\^dest_out_bin ; wire [6:0]gray_enc; wire src_clk; wire [7:0]src_in_bin; assign dest_out_bin[7] = \dest_graysync_ff[2] [7]; assign dest_out_bin[6:0] = \^dest_out_bin [6:0]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][5] (.C(dest_clk), .CE(1'b1), .D(async_path[5]), .Q(\dest_graysync_ff[0] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][6] (.C(dest_clk), .CE(1'b1), .D(async_path[6]), .Q(\dest_graysync_ff[0] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][7] (.C(dest_clk), .CE(1'b1), .D(async_path[7]), .Q(\dest_graysync_ff[0] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [5]), .Q(\dest_graysync_ff[1] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [6]), .Q(\dest_graysync_ff[1] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [7]), .Q(\dest_graysync_ff[1] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [0]), .Q(\dest_graysync_ff[2] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [1]), .Q(\dest_graysync_ff[2] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [2]), .Q(\dest_graysync_ff[2] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [3]), .Q(\dest_graysync_ff[2] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(\dest_graysync_ff[2] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [5]), .Q(\dest_graysync_ff[2] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [6]), .Q(\dest_graysync_ff[2] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [7]), .Q(\dest_graysync_ff[2] [7]), .R(1'b0)); LUT3 #( .INIT(8'h96)) \dest_out_bin[0]_INST_0 (.I0(\dest_graysync_ff[2] [0]), .I1(\^dest_out_bin [2]), .I2(\dest_graysync_ff[2] [1]), .O(\^dest_out_bin [0])); LUT2 #( .INIT(4'h6)) \dest_out_bin[1]_INST_0 (.I0(\dest_graysync_ff[2] [1]), .I1(\^dest_out_bin [2]), .O(\^dest_out_bin [1])); LUT6 #( .INIT(64'h6996966996696996)) \dest_out_bin[2]_INST_0 (.I0(\dest_graysync_ff[2] [2]), .I1(\dest_graysync_ff[2] [4]), .I2(\dest_graysync_ff[2] [6]), .I3(\dest_graysync_ff[2] [7]), .I4(\dest_graysync_ff[2] [5]), .I5(\dest_graysync_ff[2] [3]), .O(\^dest_out_bin [2])); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[3]_INST_0 (.I0(\dest_graysync_ff[2] [3]), .I1(\dest_graysync_ff[2] [5]), .I2(\dest_graysync_ff[2] [7]), .I3(\dest_graysync_ff[2] [6]), .I4(\dest_graysync_ff[2] [4]), .O(\^dest_out_bin [3])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[4]_INST_0 (.I0(\dest_graysync_ff[2] [4]), .I1(\dest_graysync_ff[2] [6]), .I2(\dest_graysync_ff[2] [7]), .I3(\dest_graysync_ff[2] [5]), .O(\^dest_out_bin [4])); LUT3 #( .INIT(8'h96)) \dest_out_bin[5]_INST_0 (.I0(\dest_graysync_ff[2] [5]), .I1(\dest_graysync_ff[2] [7]), .I2(\dest_graysync_ff[2] [6]), .O(\^dest_out_bin [5])); LUT2 #( .INIT(4'h6)) \dest_out_bin[6]_INST_0 (.I0(\dest_graysync_ff[2] [6]), .I1(\dest_graysync_ff[2] [7]), .O(\^dest_out_bin [6])); (* SOFT_HLUTNM = "soft_lutpair135" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair135" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair136" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); (* SOFT_HLUTNM = "soft_lutpair136" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[4]_i_1 (.I0(src_in_bin[5]), .I1(src_in_bin[4]), .O(gray_enc[4])); (* SOFT_HLUTNM = "soft_lutpair137" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[5]_i_1 (.I0(src_in_bin[6]), .I1(src_in_bin[5]), .O(gray_enc[5])); (* SOFT_HLUTNM = "soft_lutpair137" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[6]_i_1 (.I0(src_in_bin[7]), .I1(src_in_bin[6]), .O(gray_enc[6])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(gray_enc[4]), .Q(async_path[4]), .R(1'b0)); FDRE \src_gray_ff_reg[5] (.C(src_clk), .CE(1'b1), .D(gray_enc[5]), .Q(async_path[5]), .R(1'b0)); FDRE \src_gray_ff_reg[6] (.C(src_clk), .CE(1'b1), .D(gray_enc[6]), .Q(async_path[6]), .R(1'b0)); FDRE \src_gray_ff_reg[7] (.C(src_clk), .CE(1'b1), .D(src_in_bin[7]), .Q(async_path[7]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "8" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *) module axi_chip2chip_64B66B_xpm_cdc_gray__10 (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [7:0]src_in_bin; input dest_clk; output [7:0]dest_out_bin; wire [7:0]async_path; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[1] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[2] ; wire [6:0]\^dest_out_bin ; wire [6:0]gray_enc; wire src_clk; wire [7:0]src_in_bin; assign dest_out_bin[7] = \dest_graysync_ff[2] [7]; assign dest_out_bin[6:0] = \^dest_out_bin [6:0]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][5] (.C(dest_clk), .CE(1'b1), .D(async_path[5]), .Q(\dest_graysync_ff[0] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][6] (.C(dest_clk), .CE(1'b1), .D(async_path[6]), .Q(\dest_graysync_ff[0] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][7] (.C(dest_clk), .CE(1'b1), .D(async_path[7]), .Q(\dest_graysync_ff[0] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [5]), .Q(\dest_graysync_ff[1] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [6]), .Q(\dest_graysync_ff[1] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [7]), .Q(\dest_graysync_ff[1] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [0]), .Q(\dest_graysync_ff[2] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [1]), .Q(\dest_graysync_ff[2] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [2]), .Q(\dest_graysync_ff[2] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [3]), .Q(\dest_graysync_ff[2] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(\dest_graysync_ff[2] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [5]), .Q(\dest_graysync_ff[2] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [6]), .Q(\dest_graysync_ff[2] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [7]), .Q(\dest_graysync_ff[2] [7]), .R(1'b0)); LUT3 #( .INIT(8'h96)) \dest_out_bin[0]_INST_0 (.I0(\dest_graysync_ff[2] [0]), .I1(\^dest_out_bin [2]), .I2(\dest_graysync_ff[2] [1]), .O(\^dest_out_bin [0])); LUT2 #( .INIT(4'h6)) \dest_out_bin[1]_INST_0 (.I0(\dest_graysync_ff[2] [1]), .I1(\^dest_out_bin [2]), .O(\^dest_out_bin [1])); LUT6 #( .INIT(64'h6996966996696996)) \dest_out_bin[2]_INST_0 (.I0(\dest_graysync_ff[2] [2]), .I1(\dest_graysync_ff[2] [4]), .I2(\dest_graysync_ff[2] [6]), .I3(\dest_graysync_ff[2] [7]), .I4(\dest_graysync_ff[2] [5]), .I5(\dest_graysync_ff[2] [3]), .O(\^dest_out_bin [2])); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[3]_INST_0 (.I0(\dest_graysync_ff[2] [3]), .I1(\dest_graysync_ff[2] [5]), .I2(\dest_graysync_ff[2] [7]), .I3(\dest_graysync_ff[2] [6]), .I4(\dest_graysync_ff[2] [4]), .O(\^dest_out_bin [3])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[4]_INST_0 (.I0(\dest_graysync_ff[2] [4]), .I1(\dest_graysync_ff[2] [6]), .I2(\dest_graysync_ff[2] [7]), .I3(\dest_graysync_ff[2] [5]), .O(\^dest_out_bin [4])); LUT3 #( .INIT(8'h96)) \dest_out_bin[5]_INST_0 (.I0(\dest_graysync_ff[2] [5]), .I1(\dest_graysync_ff[2] [7]), .I2(\dest_graysync_ff[2] [6]), .O(\^dest_out_bin [5])); LUT2 #( .INIT(4'h6)) \dest_out_bin[6]_INST_0 (.I0(\dest_graysync_ff[2] [6]), .I1(\dest_graysync_ff[2] [7]), .O(\^dest_out_bin [6])); (* SOFT_HLUTNM = "soft_lutpair130" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair130" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); (* SOFT_HLUTNM = "soft_lutpair131" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair131" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); LUT2 #( .INIT(4'h6)) \src_gray_ff[4]_i_1 (.I0(src_in_bin[5]), .I1(src_in_bin[4]), .O(gray_enc[4])); (* SOFT_HLUTNM = "soft_lutpair129" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[5]_i_1 (.I0(src_in_bin[6]), .I1(src_in_bin[5]), .O(gray_enc[5])); (* SOFT_HLUTNM = "soft_lutpair129" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[6]_i_1 (.I0(src_in_bin[7]), .I1(src_in_bin[6]), .O(gray_enc[6])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(gray_enc[4]), .Q(async_path[4]), .R(1'b0)); FDRE \src_gray_ff_reg[5] (.C(src_clk), .CE(1'b1), .D(gray_enc[5]), .Q(async_path[5]), .R(1'b0)); FDRE \src_gray_ff_reg[6] (.C(src_clk), .CE(1'b1), .D(gray_enc[6]), .Q(async_path[6]), .R(1'b0)); FDRE \src_gray_ff_reg[7] (.C(src_clk), .CE(1'b1), .D(src_in_bin[7]), .Q(async_path[7]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "8" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *) module axi_chip2chip_64B66B_xpm_cdc_gray__6 (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [7:0]src_in_bin; input dest_clk; output [7:0]dest_out_bin; wire [7:0]async_path; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[1] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[2] ; wire [6:0]\^dest_out_bin ; wire [6:0]gray_enc; wire src_clk; wire [7:0]src_in_bin; assign dest_out_bin[7] = \dest_graysync_ff[2] [7]; assign dest_out_bin[6:0] = \^dest_out_bin [6:0]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][5] (.C(dest_clk), .CE(1'b1), .D(async_path[5]), .Q(\dest_graysync_ff[0] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][6] (.C(dest_clk), .CE(1'b1), .D(async_path[6]), .Q(\dest_graysync_ff[0] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][7] (.C(dest_clk), .CE(1'b1), .D(async_path[7]), .Q(\dest_graysync_ff[0] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [5]), .Q(\dest_graysync_ff[1] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [6]), .Q(\dest_graysync_ff[1] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [7]), .Q(\dest_graysync_ff[1] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [0]), .Q(\dest_graysync_ff[2] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [1]), .Q(\dest_graysync_ff[2] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [2]), .Q(\dest_graysync_ff[2] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [3]), .Q(\dest_graysync_ff[2] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(\dest_graysync_ff[2] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [5]), .Q(\dest_graysync_ff[2] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [6]), .Q(\dest_graysync_ff[2] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [7]), .Q(\dest_graysync_ff[2] [7]), .R(1'b0)); LUT3 #( .INIT(8'h96)) \dest_out_bin[0]_INST_0 (.I0(\dest_graysync_ff[2] [0]), .I1(\^dest_out_bin [2]), .I2(\dest_graysync_ff[2] [1]), .O(\^dest_out_bin [0])); LUT2 #( .INIT(4'h6)) \dest_out_bin[1]_INST_0 (.I0(\dest_graysync_ff[2] [1]), .I1(\^dest_out_bin [2]), .O(\^dest_out_bin [1])); LUT6 #( .INIT(64'h6996966996696996)) \dest_out_bin[2]_INST_0 (.I0(\dest_graysync_ff[2] [2]), .I1(\dest_graysync_ff[2] [4]), .I2(\dest_graysync_ff[2] [6]), .I3(\dest_graysync_ff[2] [7]), .I4(\dest_graysync_ff[2] [5]), .I5(\dest_graysync_ff[2] [3]), .O(\^dest_out_bin [2])); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[3]_INST_0 (.I0(\dest_graysync_ff[2] [3]), .I1(\dest_graysync_ff[2] [5]), .I2(\dest_graysync_ff[2] [7]), .I3(\dest_graysync_ff[2] [6]), .I4(\dest_graysync_ff[2] [4]), .O(\^dest_out_bin [3])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[4]_INST_0 (.I0(\dest_graysync_ff[2] [4]), .I1(\dest_graysync_ff[2] [6]), .I2(\dest_graysync_ff[2] [7]), .I3(\dest_graysync_ff[2] [5]), .O(\^dest_out_bin [4])); LUT3 #( .INIT(8'h96)) \dest_out_bin[5]_INST_0 (.I0(\dest_graysync_ff[2] [5]), .I1(\dest_graysync_ff[2] [7]), .I2(\dest_graysync_ff[2] [6]), .O(\^dest_out_bin [5])); LUT2 #( .INIT(4'h6)) \dest_out_bin[6]_INST_0 (.I0(\dest_graysync_ff[2] [6]), .I1(\dest_graysync_ff[2] [7]), .O(\^dest_out_bin [6])); (* SOFT_HLUTNM = "soft_lutpair95" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair95" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); (* SOFT_HLUTNM = "soft_lutpair96" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair96" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); (* SOFT_HLUTNM = "soft_lutpair97" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[4]_i_1 (.I0(src_in_bin[5]), .I1(src_in_bin[4]), .O(gray_enc[4])); (* SOFT_HLUTNM = "soft_lutpair97" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[5]_i_1 (.I0(src_in_bin[6]), .I1(src_in_bin[5]), .O(gray_enc[5])); LUT2 #( .INIT(4'h6)) \src_gray_ff[6]_i_1 (.I0(src_in_bin[7]), .I1(src_in_bin[6]), .O(gray_enc[6])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(gray_enc[4]), .Q(async_path[4]), .R(1'b0)); FDRE \src_gray_ff_reg[5] (.C(src_clk), .CE(1'b1), .D(gray_enc[5]), .Q(async_path[5]), .R(1'b0)); FDRE \src_gray_ff_reg[6] (.C(src_clk), .CE(1'b1), .D(gray_enc[6]), .Q(async_path[6]), .R(1'b0)); FDRE \src_gray_ff_reg[7] (.C(src_clk), .CE(1'b1), .D(src_in_bin[7]), .Q(async_path[7]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "8" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *) module axi_chip2chip_64B66B_xpm_cdc_gray__7 (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [7:0]src_in_bin; input dest_clk; output [7:0]dest_out_bin; wire [7:0]async_path; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[1] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[2] ; wire [6:0]\^dest_out_bin ; wire [6:0]gray_enc; wire src_clk; wire [7:0]src_in_bin; assign dest_out_bin[7] = \dest_graysync_ff[2] [7]; assign dest_out_bin[6:0] = \^dest_out_bin [6:0]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][5] (.C(dest_clk), .CE(1'b1), .D(async_path[5]), .Q(\dest_graysync_ff[0] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][6] (.C(dest_clk), .CE(1'b1), .D(async_path[6]), .Q(\dest_graysync_ff[0] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][7] (.C(dest_clk), .CE(1'b1), .D(async_path[7]), .Q(\dest_graysync_ff[0] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [5]), .Q(\dest_graysync_ff[1] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [6]), .Q(\dest_graysync_ff[1] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [7]), .Q(\dest_graysync_ff[1] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [0]), .Q(\dest_graysync_ff[2] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [1]), .Q(\dest_graysync_ff[2] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [2]), .Q(\dest_graysync_ff[2] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [3]), .Q(\dest_graysync_ff[2] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(\dest_graysync_ff[2] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [5]), .Q(\dest_graysync_ff[2] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [6]), .Q(\dest_graysync_ff[2] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [7]), .Q(\dest_graysync_ff[2] [7]), .R(1'b0)); LUT3 #( .INIT(8'h96)) \dest_out_bin[0]_INST_0 (.I0(\dest_graysync_ff[2] [0]), .I1(\^dest_out_bin [2]), .I2(\dest_graysync_ff[2] [1]), .O(\^dest_out_bin [0])); LUT2 #( .INIT(4'h6)) \dest_out_bin[1]_INST_0 (.I0(\dest_graysync_ff[2] [1]), .I1(\^dest_out_bin [2]), .O(\^dest_out_bin [1])); LUT6 #( .INIT(64'h6996966996696996)) \dest_out_bin[2]_INST_0 (.I0(\dest_graysync_ff[2] [2]), .I1(\dest_graysync_ff[2] [4]), .I2(\dest_graysync_ff[2] [6]), .I3(\dest_graysync_ff[2] [7]), .I4(\dest_graysync_ff[2] [5]), .I5(\dest_graysync_ff[2] [3]), .O(\^dest_out_bin [2])); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[3]_INST_0 (.I0(\dest_graysync_ff[2] [3]), .I1(\dest_graysync_ff[2] [5]), .I2(\dest_graysync_ff[2] [7]), .I3(\dest_graysync_ff[2] [6]), .I4(\dest_graysync_ff[2] [4]), .O(\^dest_out_bin [3])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[4]_INST_0 (.I0(\dest_graysync_ff[2] [4]), .I1(\dest_graysync_ff[2] [6]), .I2(\dest_graysync_ff[2] [7]), .I3(\dest_graysync_ff[2] [5]), .O(\^dest_out_bin [4])); LUT3 #( .INIT(8'h96)) \dest_out_bin[5]_INST_0 (.I0(\dest_graysync_ff[2] [5]), .I1(\dest_graysync_ff[2] [7]), .I2(\dest_graysync_ff[2] [6]), .O(\^dest_out_bin [5])); LUT2 #( .INIT(4'h6)) \dest_out_bin[6]_INST_0 (.I0(\dest_graysync_ff[2] [6]), .I1(\dest_graysync_ff[2] [7]), .O(\^dest_out_bin [6])); (* SOFT_HLUTNM = "soft_lutpair102" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair102" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair103" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); (* SOFT_HLUTNM = "soft_lutpair103" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[4]_i_1 (.I0(src_in_bin[5]), .I1(src_in_bin[4]), .O(gray_enc[4])); (* SOFT_HLUTNM = "soft_lutpair104" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[5]_i_1 (.I0(src_in_bin[6]), .I1(src_in_bin[5]), .O(gray_enc[5])); (* SOFT_HLUTNM = "soft_lutpair104" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[6]_i_1 (.I0(src_in_bin[7]), .I1(src_in_bin[6]), .O(gray_enc[6])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(gray_enc[4]), .Q(async_path[4]), .R(1'b0)); FDRE \src_gray_ff_reg[5] (.C(src_clk), .CE(1'b1), .D(gray_enc[5]), .Q(async_path[5]), .R(1'b0)); FDRE \src_gray_ff_reg[6] (.C(src_clk), .CE(1'b1), .D(gray_enc[6]), .Q(async_path[6]), .R(1'b0)); FDRE \src_gray_ff_reg[7] (.C(src_clk), .CE(1'b1), .D(src_in_bin[7]), .Q(async_path[7]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "8" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *) module axi_chip2chip_64B66B_xpm_cdc_gray__8 (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [7:0]src_in_bin; input dest_clk; output [7:0]dest_out_bin; wire [7:0]async_path; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[1] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[2] ; wire [6:0]\^dest_out_bin ; wire [6:0]gray_enc; wire src_clk; wire [7:0]src_in_bin; assign dest_out_bin[7] = \dest_graysync_ff[2] [7]; assign dest_out_bin[6:0] = \^dest_out_bin [6:0]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][5] (.C(dest_clk), .CE(1'b1), .D(async_path[5]), .Q(\dest_graysync_ff[0] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][6] (.C(dest_clk), .CE(1'b1), .D(async_path[6]), .Q(\dest_graysync_ff[0] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][7] (.C(dest_clk), .CE(1'b1), .D(async_path[7]), .Q(\dest_graysync_ff[0] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [5]), .Q(\dest_graysync_ff[1] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [6]), .Q(\dest_graysync_ff[1] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [7]), .Q(\dest_graysync_ff[1] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [0]), .Q(\dest_graysync_ff[2] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [1]), .Q(\dest_graysync_ff[2] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [2]), .Q(\dest_graysync_ff[2] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [3]), .Q(\dest_graysync_ff[2] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(\dest_graysync_ff[2] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [5]), .Q(\dest_graysync_ff[2] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [6]), .Q(\dest_graysync_ff[2] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [7]), .Q(\dest_graysync_ff[2] [7]), .R(1'b0)); LUT3 #( .INIT(8'h96)) \dest_out_bin[0]_INST_0 (.I0(\dest_graysync_ff[2] [0]), .I1(\^dest_out_bin [2]), .I2(\dest_graysync_ff[2] [1]), .O(\^dest_out_bin [0])); LUT2 #( .INIT(4'h6)) \dest_out_bin[1]_INST_0 (.I0(\dest_graysync_ff[2] [1]), .I1(\^dest_out_bin [2]), .O(\^dest_out_bin [1])); LUT6 #( .INIT(64'h6996966996696996)) \dest_out_bin[2]_INST_0 (.I0(\dest_graysync_ff[2] [2]), .I1(\dest_graysync_ff[2] [4]), .I2(\dest_graysync_ff[2] [6]), .I3(\dest_graysync_ff[2] [7]), .I4(\dest_graysync_ff[2] [5]), .I5(\dest_graysync_ff[2] [3]), .O(\^dest_out_bin [2])); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[3]_INST_0 (.I0(\dest_graysync_ff[2] [3]), .I1(\dest_graysync_ff[2] [5]), .I2(\dest_graysync_ff[2] [7]), .I3(\dest_graysync_ff[2] [6]), .I4(\dest_graysync_ff[2] [4]), .O(\^dest_out_bin [3])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[4]_INST_0 (.I0(\dest_graysync_ff[2] [4]), .I1(\dest_graysync_ff[2] [6]), .I2(\dest_graysync_ff[2] [7]), .I3(\dest_graysync_ff[2] [5]), .O(\^dest_out_bin [4])); LUT3 #( .INIT(8'h96)) \dest_out_bin[5]_INST_0 (.I0(\dest_graysync_ff[2] [5]), .I1(\dest_graysync_ff[2] [7]), .I2(\dest_graysync_ff[2] [6]), .O(\^dest_out_bin [5])); LUT2 #( .INIT(4'h6)) \dest_out_bin[6]_INST_0 (.I0(\dest_graysync_ff[2] [6]), .I1(\dest_graysync_ff[2] [7]), .O(\^dest_out_bin [6])); (* SOFT_HLUTNM = "soft_lutpair61" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair61" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); (* SOFT_HLUTNM = "soft_lutpair62" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair62" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); (* SOFT_HLUTNM = "soft_lutpair63" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[4]_i_1 (.I0(src_in_bin[5]), .I1(src_in_bin[4]), .O(gray_enc[4])); (* SOFT_HLUTNM = "soft_lutpair63" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[5]_i_1 (.I0(src_in_bin[6]), .I1(src_in_bin[5]), .O(gray_enc[5])); LUT2 #( .INIT(4'h6)) \src_gray_ff[6]_i_1 (.I0(src_in_bin[7]), .I1(src_in_bin[6]), .O(gray_enc[6])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(gray_enc[4]), .Q(async_path[4]), .R(1'b0)); FDRE \src_gray_ff_reg[5] (.C(src_clk), .CE(1'b1), .D(gray_enc[5]), .Q(async_path[5]), .R(1'b0)); FDRE \src_gray_ff_reg[6] (.C(src_clk), .CE(1'b1), .D(gray_enc[6]), .Q(async_path[6]), .R(1'b0)); FDRE \src_gray_ff_reg[7] (.C(src_clk), .CE(1'b1), .D(src_in_bin[7]), .Q(async_path[7]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "8" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *) module axi_chip2chip_64B66B_xpm_cdc_gray__9 (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [7:0]src_in_bin; input dest_clk; output [7:0]dest_out_bin; wire [7:0]async_path; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[1] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [7:0]\dest_graysync_ff[2] ; wire [6:0]\^dest_out_bin ; wire [6:0]gray_enc; wire src_clk; wire [7:0]src_in_bin; assign dest_out_bin[7] = \dest_graysync_ff[2] [7]; assign dest_out_bin[6:0] = \^dest_out_bin [6:0]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][5] (.C(dest_clk), .CE(1'b1), .D(async_path[5]), .Q(\dest_graysync_ff[0] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][6] (.C(dest_clk), .CE(1'b1), .D(async_path[6]), .Q(\dest_graysync_ff[0] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][7] (.C(dest_clk), .CE(1'b1), .D(async_path[7]), .Q(\dest_graysync_ff[0] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [5]), .Q(\dest_graysync_ff[1] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [6]), .Q(\dest_graysync_ff[1] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [7]), .Q(\dest_graysync_ff[1] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [0]), .Q(\dest_graysync_ff[2] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [1]), .Q(\dest_graysync_ff[2] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [2]), .Q(\dest_graysync_ff[2] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [3]), .Q(\dest_graysync_ff[2] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(\dest_graysync_ff[2] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [5]), .Q(\dest_graysync_ff[2] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [6]), .Q(\dest_graysync_ff[2] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [7]), .Q(\dest_graysync_ff[2] [7]), .R(1'b0)); LUT3 #( .INIT(8'h96)) \dest_out_bin[0]_INST_0 (.I0(\dest_graysync_ff[2] [0]), .I1(\^dest_out_bin [2]), .I2(\dest_graysync_ff[2] [1]), .O(\^dest_out_bin [0])); LUT2 #( .INIT(4'h6)) \dest_out_bin[1]_INST_0 (.I0(\dest_graysync_ff[2] [1]), .I1(\^dest_out_bin [2]), .O(\^dest_out_bin [1])); LUT6 #( .INIT(64'h6996966996696996)) \dest_out_bin[2]_INST_0 (.I0(\dest_graysync_ff[2] [2]), .I1(\dest_graysync_ff[2] [4]), .I2(\dest_graysync_ff[2] [6]), .I3(\dest_graysync_ff[2] [7]), .I4(\dest_graysync_ff[2] [5]), .I5(\dest_graysync_ff[2] [3]), .O(\^dest_out_bin [2])); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[3]_INST_0 (.I0(\dest_graysync_ff[2] [3]), .I1(\dest_graysync_ff[2] [5]), .I2(\dest_graysync_ff[2] [7]), .I3(\dest_graysync_ff[2] [6]), .I4(\dest_graysync_ff[2] [4]), .O(\^dest_out_bin [3])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[4]_INST_0 (.I0(\dest_graysync_ff[2] [4]), .I1(\dest_graysync_ff[2] [6]), .I2(\dest_graysync_ff[2] [7]), .I3(\dest_graysync_ff[2] [5]), .O(\^dest_out_bin [4])); LUT3 #( .INIT(8'h96)) \dest_out_bin[5]_INST_0 (.I0(\dest_graysync_ff[2] [5]), .I1(\dest_graysync_ff[2] [7]), .I2(\dest_graysync_ff[2] [6]), .O(\^dest_out_bin [5])); LUT2 #( .INIT(4'h6)) \dest_out_bin[6]_INST_0 (.I0(\dest_graysync_ff[2] [6]), .I1(\dest_graysync_ff[2] [7]), .O(\^dest_out_bin [6])); (* SOFT_HLUTNM = "soft_lutpair68" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair68" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair69" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); (* SOFT_HLUTNM = "soft_lutpair69" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[4]_i_1 (.I0(src_in_bin[5]), .I1(src_in_bin[4]), .O(gray_enc[4])); (* SOFT_HLUTNM = "soft_lutpair70" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[5]_i_1 (.I0(src_in_bin[6]), .I1(src_in_bin[5]), .O(gray_enc[5])); (* SOFT_HLUTNM = "soft_lutpair70" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[6]_i_1 (.I0(src_in_bin[7]), .I1(src_in_bin[6]), .O(gray_enc[6])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(gray_enc[4]), .Q(async_path[4]), .R(1'b0)); FDRE \src_gray_ff_reg[5] (.C(src_clk), .CE(1'b1), .D(gray_enc[5]), .Q(async_path[5]), .R(1'b0)); FDRE \src_gray_ff_reg[6] (.C(src_clk), .CE(1'b1), .D(gray_enc[6]), .Q(async_path[6]), .R(1'b0)); FDRE \src_gray_ff_reg[7] (.C(src_clk), .CE(1'b1), .D(src_in_bin[7]), .Q(async_path[7]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "5" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *) module axi_chip2chip_64B66B_xpm_cdc_gray__parameterized0 (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [8:0]src_in_bin; input dest_clk; output [8:0]dest_out_bin; wire [8:0]async_path; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[1] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[2] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[3] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[4] ; wire [7:0]\^dest_out_bin ; wire [7:0]gray_enc; wire src_clk; wire [8:0]src_in_bin; assign dest_out_bin[8] = \dest_graysync_ff[4] [8]; assign dest_out_bin[7:0] = \^dest_out_bin [7:0]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][5] (.C(dest_clk), .CE(1'b1), .D(async_path[5]), .Q(\dest_graysync_ff[0] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][6] (.C(dest_clk), .CE(1'b1), .D(async_path[6]), .Q(\dest_graysync_ff[0] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][7] (.C(dest_clk), .CE(1'b1), .D(async_path[7]), .Q(\dest_graysync_ff[0] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][8] (.C(dest_clk), .CE(1'b1), .D(async_path[8]), .Q(\dest_graysync_ff[0] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [5]), .Q(\dest_graysync_ff[1] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [6]), .Q(\dest_graysync_ff[1] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [7]), .Q(\dest_graysync_ff[1] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [8]), .Q(\dest_graysync_ff[1] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [0]), .Q(\dest_graysync_ff[2] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [1]), .Q(\dest_graysync_ff[2] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [2]), .Q(\dest_graysync_ff[2] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [3]), .Q(\dest_graysync_ff[2] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(\dest_graysync_ff[2] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [5]), .Q(\dest_graysync_ff[2] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [6]), .Q(\dest_graysync_ff[2] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [7]), .Q(\dest_graysync_ff[2] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [8]), .Q(\dest_graysync_ff[2] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [0]), .Q(\dest_graysync_ff[3] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [1]), .Q(\dest_graysync_ff[3] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [2]), .Q(\dest_graysync_ff[3] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [3]), .Q(\dest_graysync_ff[3] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [4]), .Q(\dest_graysync_ff[3] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [5]), .Q(\dest_graysync_ff[3] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [6]), .Q(\dest_graysync_ff[3] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [7]), .Q(\dest_graysync_ff[3] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [8]), .Q(\dest_graysync_ff[3] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [0]), .Q(\dest_graysync_ff[4] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [1]), .Q(\dest_graysync_ff[4] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [2]), .Q(\dest_graysync_ff[4] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [3]), .Q(\dest_graysync_ff[4] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [4]), .Q(\dest_graysync_ff[4] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [5]), .Q(\dest_graysync_ff[4] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [6]), .Q(\dest_graysync_ff[4] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [7]), .Q(\dest_graysync_ff[4] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [8]), .Q(\dest_graysync_ff[4] [8]), .R(1'b0)); LUT4 #( .INIT(16'h6996)) \dest_out_bin[0]_INST_0 (.I0(\dest_graysync_ff[4] [0]), .I1(\dest_graysync_ff[4] [2]), .I2(\^dest_out_bin [3]), .I3(\dest_graysync_ff[4] [1]), .O(\^dest_out_bin [0])); LUT3 #( .INIT(8'h96)) \dest_out_bin[1]_INST_0 (.I0(\dest_graysync_ff[4] [1]), .I1(\^dest_out_bin [3]), .I2(\dest_graysync_ff[4] [2]), .O(\^dest_out_bin [1])); LUT2 #( .INIT(4'h6)) \dest_out_bin[2]_INST_0 (.I0(\dest_graysync_ff[4] [2]), .I1(\^dest_out_bin [3]), .O(\^dest_out_bin [2])); LUT6 #( .INIT(64'h6996966996696996)) \dest_out_bin[3]_INST_0 (.I0(\dest_graysync_ff[4] [3]), .I1(\dest_graysync_ff[4] [5]), .I2(\dest_graysync_ff[4] [7]), .I3(\dest_graysync_ff[4] [8]), .I4(\dest_graysync_ff[4] [6]), .I5(\dest_graysync_ff[4] [4]), .O(\^dest_out_bin [3])); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[4]_INST_0 (.I0(\dest_graysync_ff[4] [4]), .I1(\dest_graysync_ff[4] [6]), .I2(\dest_graysync_ff[4] [8]), .I3(\dest_graysync_ff[4] [7]), .I4(\dest_graysync_ff[4] [5]), .O(\^dest_out_bin [4])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[5]_INST_0 (.I0(\dest_graysync_ff[4] [5]), .I1(\dest_graysync_ff[4] [7]), .I2(\dest_graysync_ff[4] [8]), .I3(\dest_graysync_ff[4] [6]), .O(\^dest_out_bin [5])); LUT3 #( .INIT(8'h96)) \dest_out_bin[6]_INST_0 (.I0(\dest_graysync_ff[4] [6]), .I1(\dest_graysync_ff[4] [8]), .I2(\dest_graysync_ff[4] [7]), .O(\^dest_out_bin [6])); LUT2 #( .INIT(4'h6)) \dest_out_bin[7]_INST_0 (.I0(\dest_graysync_ff[4] [7]), .I1(\dest_graysync_ff[4] [8]), .O(\^dest_out_bin [7])); (* SOFT_HLUTNM = "soft_lutpair133" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair133" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); (* SOFT_HLUTNM = "soft_lutpair134" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair134" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); LUT2 #( .INIT(4'h6)) \src_gray_ff[4]_i_1 (.I0(src_in_bin[5]), .I1(src_in_bin[4]), .O(gray_enc[4])); (* SOFT_HLUTNM = "soft_lutpair132" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[5]_i_1 (.I0(src_in_bin[6]), .I1(src_in_bin[5]), .O(gray_enc[5])); (* SOFT_HLUTNM = "soft_lutpair132" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[6]_i_1 (.I0(src_in_bin[7]), .I1(src_in_bin[6]), .O(gray_enc[6])); LUT2 #( .INIT(4'h6)) \src_gray_ff[7]_i_1 (.I0(src_in_bin[8]), .I1(src_in_bin[7]), .O(gray_enc[7])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(gray_enc[4]), .Q(async_path[4]), .R(1'b0)); FDRE \src_gray_ff_reg[5] (.C(src_clk), .CE(1'b1), .D(gray_enc[5]), .Q(async_path[5]), .R(1'b0)); FDRE \src_gray_ff_reg[6] (.C(src_clk), .CE(1'b1), .D(gray_enc[6]), .Q(async_path[6]), .R(1'b0)); FDRE \src_gray_ff_reg[7] (.C(src_clk), .CE(1'b1), .D(gray_enc[7]), .Q(async_path[7]), .R(1'b0)); FDRE \src_gray_ff_reg[8] (.C(src_clk), .CE(1'b1), .D(src_in_bin[8]), .Q(async_path[8]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "5" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *) module axi_chip2chip_64B66B_xpm_cdc_gray__parameterized0__3 (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [8:0]src_in_bin; input dest_clk; output [8:0]dest_out_bin; wire [8:0]async_path; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[1] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[2] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[3] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[4] ; wire [7:0]\^dest_out_bin ; wire [7:0]gray_enc; wire src_clk; wire [8:0]src_in_bin; assign dest_out_bin[8] = \dest_graysync_ff[4] [8]; assign dest_out_bin[7:0] = \^dest_out_bin [7:0]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][5] (.C(dest_clk), .CE(1'b1), .D(async_path[5]), .Q(\dest_graysync_ff[0] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][6] (.C(dest_clk), .CE(1'b1), .D(async_path[6]), .Q(\dest_graysync_ff[0] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][7] (.C(dest_clk), .CE(1'b1), .D(async_path[7]), .Q(\dest_graysync_ff[0] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][8] (.C(dest_clk), .CE(1'b1), .D(async_path[8]), .Q(\dest_graysync_ff[0] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [5]), .Q(\dest_graysync_ff[1] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [6]), .Q(\dest_graysync_ff[1] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [7]), .Q(\dest_graysync_ff[1] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [8]), .Q(\dest_graysync_ff[1] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [0]), .Q(\dest_graysync_ff[2] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [1]), .Q(\dest_graysync_ff[2] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [2]), .Q(\dest_graysync_ff[2] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [3]), .Q(\dest_graysync_ff[2] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(\dest_graysync_ff[2] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [5]), .Q(\dest_graysync_ff[2] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [6]), .Q(\dest_graysync_ff[2] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [7]), .Q(\dest_graysync_ff[2] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [8]), .Q(\dest_graysync_ff[2] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [0]), .Q(\dest_graysync_ff[3] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [1]), .Q(\dest_graysync_ff[3] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [2]), .Q(\dest_graysync_ff[3] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [3]), .Q(\dest_graysync_ff[3] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [4]), .Q(\dest_graysync_ff[3] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [5]), .Q(\dest_graysync_ff[3] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [6]), .Q(\dest_graysync_ff[3] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [7]), .Q(\dest_graysync_ff[3] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [8]), .Q(\dest_graysync_ff[3] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [0]), .Q(\dest_graysync_ff[4] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [1]), .Q(\dest_graysync_ff[4] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [2]), .Q(\dest_graysync_ff[4] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [3]), .Q(\dest_graysync_ff[4] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [4]), .Q(\dest_graysync_ff[4] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [5]), .Q(\dest_graysync_ff[4] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [6]), .Q(\dest_graysync_ff[4] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [7]), .Q(\dest_graysync_ff[4] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [8]), .Q(\dest_graysync_ff[4] [8]), .R(1'b0)); LUT4 #( .INIT(16'h6996)) \dest_out_bin[0]_INST_0 (.I0(\dest_graysync_ff[4] [0]), .I1(\dest_graysync_ff[4] [2]), .I2(\^dest_out_bin [3]), .I3(\dest_graysync_ff[4] [1]), .O(\^dest_out_bin [0])); LUT3 #( .INIT(8'h96)) \dest_out_bin[1]_INST_0 (.I0(\dest_graysync_ff[4] [1]), .I1(\^dest_out_bin [3]), .I2(\dest_graysync_ff[4] [2]), .O(\^dest_out_bin [1])); LUT2 #( .INIT(4'h6)) \dest_out_bin[2]_INST_0 (.I0(\dest_graysync_ff[4] [2]), .I1(\^dest_out_bin [3]), .O(\^dest_out_bin [2])); LUT6 #( .INIT(64'h6996966996696996)) \dest_out_bin[3]_INST_0 (.I0(\dest_graysync_ff[4] [3]), .I1(\dest_graysync_ff[4] [5]), .I2(\dest_graysync_ff[4] [7]), .I3(\dest_graysync_ff[4] [8]), .I4(\dest_graysync_ff[4] [6]), .I5(\dest_graysync_ff[4] [4]), .O(\^dest_out_bin [3])); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[4]_INST_0 (.I0(\dest_graysync_ff[4] [4]), .I1(\dest_graysync_ff[4] [6]), .I2(\dest_graysync_ff[4] [8]), .I3(\dest_graysync_ff[4] [7]), .I4(\dest_graysync_ff[4] [5]), .O(\^dest_out_bin [4])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[5]_INST_0 (.I0(\dest_graysync_ff[4] [5]), .I1(\dest_graysync_ff[4] [7]), .I2(\dest_graysync_ff[4] [8]), .I3(\dest_graysync_ff[4] [6]), .O(\^dest_out_bin [5])); LUT3 #( .INIT(8'h96)) \dest_out_bin[6]_INST_0 (.I0(\dest_graysync_ff[4] [6]), .I1(\dest_graysync_ff[4] [8]), .I2(\dest_graysync_ff[4] [7]), .O(\^dest_out_bin [6])); LUT2 #( .INIT(4'h6)) \dest_out_bin[7]_INST_0 (.I0(\dest_graysync_ff[4] [7]), .I1(\dest_graysync_ff[4] [8]), .O(\^dest_out_bin [7])); (* SOFT_HLUTNM = "soft_lutpair98" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair98" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); (* SOFT_HLUTNM = "soft_lutpair99" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair99" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); (* SOFT_HLUTNM = "soft_lutpair100" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[4]_i_1 (.I0(src_in_bin[5]), .I1(src_in_bin[4]), .O(gray_enc[4])); (* SOFT_HLUTNM = "soft_lutpair100" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[5]_i_1 (.I0(src_in_bin[6]), .I1(src_in_bin[5]), .O(gray_enc[5])); (* SOFT_HLUTNM = "soft_lutpair101" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[6]_i_1 (.I0(src_in_bin[7]), .I1(src_in_bin[6]), .O(gray_enc[6])); (* SOFT_HLUTNM = "soft_lutpair101" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[7]_i_1 (.I0(src_in_bin[8]), .I1(src_in_bin[7]), .O(gray_enc[7])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(gray_enc[4]), .Q(async_path[4]), .R(1'b0)); FDRE \src_gray_ff_reg[5] (.C(src_clk), .CE(1'b1), .D(gray_enc[5]), .Q(async_path[5]), .R(1'b0)); FDRE \src_gray_ff_reg[6] (.C(src_clk), .CE(1'b1), .D(gray_enc[6]), .Q(async_path[6]), .R(1'b0)); FDRE \src_gray_ff_reg[7] (.C(src_clk), .CE(1'b1), .D(gray_enc[7]), .Q(async_path[7]), .R(1'b0)); FDRE \src_gray_ff_reg[8] (.C(src_clk), .CE(1'b1), .D(src_in_bin[8]), .Q(async_path[8]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "5" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *) module axi_chip2chip_64B66B_xpm_cdc_gray__parameterized0__4 (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [8:0]src_in_bin; input dest_clk; output [8:0]dest_out_bin; wire [8:0]async_path; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[1] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[2] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[3] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[4] ; wire [7:0]\^dest_out_bin ; wire [7:0]gray_enc; wire src_clk; wire [8:0]src_in_bin; assign dest_out_bin[8] = \dest_graysync_ff[4] [8]; assign dest_out_bin[7:0] = \^dest_out_bin [7:0]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][5] (.C(dest_clk), .CE(1'b1), .D(async_path[5]), .Q(\dest_graysync_ff[0] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][6] (.C(dest_clk), .CE(1'b1), .D(async_path[6]), .Q(\dest_graysync_ff[0] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][7] (.C(dest_clk), .CE(1'b1), .D(async_path[7]), .Q(\dest_graysync_ff[0] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][8] (.C(dest_clk), .CE(1'b1), .D(async_path[8]), .Q(\dest_graysync_ff[0] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [5]), .Q(\dest_graysync_ff[1] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [6]), .Q(\dest_graysync_ff[1] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [7]), .Q(\dest_graysync_ff[1] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [8]), .Q(\dest_graysync_ff[1] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [0]), .Q(\dest_graysync_ff[2] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [1]), .Q(\dest_graysync_ff[2] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [2]), .Q(\dest_graysync_ff[2] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [3]), .Q(\dest_graysync_ff[2] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(\dest_graysync_ff[2] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [5]), .Q(\dest_graysync_ff[2] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [6]), .Q(\dest_graysync_ff[2] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [7]), .Q(\dest_graysync_ff[2] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [8]), .Q(\dest_graysync_ff[2] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [0]), .Q(\dest_graysync_ff[3] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [1]), .Q(\dest_graysync_ff[3] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [2]), .Q(\dest_graysync_ff[3] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [3]), .Q(\dest_graysync_ff[3] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [4]), .Q(\dest_graysync_ff[3] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [5]), .Q(\dest_graysync_ff[3] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [6]), .Q(\dest_graysync_ff[3] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [7]), .Q(\dest_graysync_ff[3] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [8]), .Q(\dest_graysync_ff[3] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [0]), .Q(\dest_graysync_ff[4] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [1]), .Q(\dest_graysync_ff[4] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [2]), .Q(\dest_graysync_ff[4] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [3]), .Q(\dest_graysync_ff[4] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [4]), .Q(\dest_graysync_ff[4] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [5]), .Q(\dest_graysync_ff[4] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [6]), .Q(\dest_graysync_ff[4] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [7]), .Q(\dest_graysync_ff[4] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [8]), .Q(\dest_graysync_ff[4] [8]), .R(1'b0)); LUT4 #( .INIT(16'h6996)) \dest_out_bin[0]_INST_0 (.I0(\dest_graysync_ff[4] [0]), .I1(\dest_graysync_ff[4] [2]), .I2(\^dest_out_bin [3]), .I3(\dest_graysync_ff[4] [1]), .O(\^dest_out_bin [0])); LUT3 #( .INIT(8'h96)) \dest_out_bin[1]_INST_0 (.I0(\dest_graysync_ff[4] [1]), .I1(\^dest_out_bin [3]), .I2(\dest_graysync_ff[4] [2]), .O(\^dest_out_bin [1])); LUT2 #( .INIT(4'h6)) \dest_out_bin[2]_INST_0 (.I0(\dest_graysync_ff[4] [2]), .I1(\^dest_out_bin [3]), .O(\^dest_out_bin [2])); LUT6 #( .INIT(64'h6996966996696996)) \dest_out_bin[3]_INST_0 (.I0(\dest_graysync_ff[4] [3]), .I1(\dest_graysync_ff[4] [5]), .I2(\dest_graysync_ff[4] [7]), .I3(\dest_graysync_ff[4] [8]), .I4(\dest_graysync_ff[4] [6]), .I5(\dest_graysync_ff[4] [4]), .O(\^dest_out_bin [3])); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[4]_INST_0 (.I0(\dest_graysync_ff[4] [4]), .I1(\dest_graysync_ff[4] [6]), .I2(\dest_graysync_ff[4] [8]), .I3(\dest_graysync_ff[4] [7]), .I4(\dest_graysync_ff[4] [5]), .O(\^dest_out_bin [4])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[5]_INST_0 (.I0(\dest_graysync_ff[4] [5]), .I1(\dest_graysync_ff[4] [7]), .I2(\dest_graysync_ff[4] [8]), .I3(\dest_graysync_ff[4] [6]), .O(\^dest_out_bin [5])); LUT3 #( .INIT(8'h96)) \dest_out_bin[6]_INST_0 (.I0(\dest_graysync_ff[4] [6]), .I1(\dest_graysync_ff[4] [8]), .I2(\dest_graysync_ff[4] [7]), .O(\^dest_out_bin [6])); LUT2 #( .INIT(4'h6)) \dest_out_bin[7]_INST_0 (.I0(\dest_graysync_ff[4] [7]), .I1(\dest_graysync_ff[4] [8]), .O(\^dest_out_bin [7])); (* SOFT_HLUTNM = "soft_lutpair64" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair64" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); (* SOFT_HLUTNM = "soft_lutpair65" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair65" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); (* SOFT_HLUTNM = "soft_lutpair66" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[4]_i_1 (.I0(src_in_bin[5]), .I1(src_in_bin[4]), .O(gray_enc[4])); (* SOFT_HLUTNM = "soft_lutpair66" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[5]_i_1 (.I0(src_in_bin[6]), .I1(src_in_bin[5]), .O(gray_enc[5])); (* SOFT_HLUTNM = "soft_lutpair67" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[6]_i_1 (.I0(src_in_bin[7]), .I1(src_in_bin[6]), .O(gray_enc[6])); (* SOFT_HLUTNM = "soft_lutpair67" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[7]_i_1 (.I0(src_in_bin[8]), .I1(src_in_bin[7]), .O(gray_enc[7])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(gray_enc[4]), .Q(async_path[4]), .R(1'b0)); FDRE \src_gray_ff_reg[5] (.C(src_clk), .CE(1'b1), .D(gray_enc[5]), .Q(async_path[5]), .R(1'b0)); FDRE \src_gray_ff_reg[6] (.C(src_clk), .CE(1'b1), .D(gray_enc[6]), .Q(async_path[6]), .R(1'b0)); FDRE \src_gray_ff_reg[7] (.C(src_clk), .CE(1'b1), .D(gray_enc[7]), .Q(async_path[7]), .R(1'b0)); FDRE \src_gray_ff_reg[8] (.C(src_clk), .CE(1'b1), .D(src_in_bin[8]), .Q(async_path[8]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *) module axi_chip2chip_64B66B_xpm_cdc_gray__parameterized1 (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [8:0]src_in_bin; input dest_clk; output [8:0]dest_out_bin; wire [8:0]async_path; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[1] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[2] ; wire [7:0]\^dest_out_bin ; wire [7:0]gray_enc; wire src_clk; wire [8:0]src_in_bin; assign dest_out_bin[8] = \dest_graysync_ff[2] [8]; assign dest_out_bin[7:0] = \^dest_out_bin [7:0]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][5] (.C(dest_clk), .CE(1'b1), .D(async_path[5]), .Q(\dest_graysync_ff[0] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][6] (.C(dest_clk), .CE(1'b1), .D(async_path[6]), .Q(\dest_graysync_ff[0] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][7] (.C(dest_clk), .CE(1'b1), .D(async_path[7]), .Q(\dest_graysync_ff[0] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][8] (.C(dest_clk), .CE(1'b1), .D(async_path[8]), .Q(\dest_graysync_ff[0] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [5]), .Q(\dest_graysync_ff[1] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [6]), .Q(\dest_graysync_ff[1] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [7]), .Q(\dest_graysync_ff[1] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [8]), .Q(\dest_graysync_ff[1] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [0]), .Q(\dest_graysync_ff[2] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [1]), .Q(\dest_graysync_ff[2] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [2]), .Q(\dest_graysync_ff[2] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [3]), .Q(\dest_graysync_ff[2] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(\dest_graysync_ff[2] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [5]), .Q(\dest_graysync_ff[2] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [6]), .Q(\dest_graysync_ff[2] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [7]), .Q(\dest_graysync_ff[2] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [8]), .Q(\dest_graysync_ff[2] [8]), .R(1'b0)); LUT4 #( .INIT(16'h6996)) \dest_out_bin[0]_INST_0 (.I0(\dest_graysync_ff[2] [0]), .I1(\dest_graysync_ff[2] [2]), .I2(\^dest_out_bin [3]), .I3(\dest_graysync_ff[2] [1]), .O(\^dest_out_bin [0])); LUT3 #( .INIT(8'h96)) \dest_out_bin[1]_INST_0 (.I0(\dest_graysync_ff[2] [1]), .I1(\^dest_out_bin [3]), .I2(\dest_graysync_ff[2] [2]), .O(\^dest_out_bin [1])); LUT2 #( .INIT(4'h6)) \dest_out_bin[2]_INST_0 (.I0(\dest_graysync_ff[2] [2]), .I1(\^dest_out_bin [3]), .O(\^dest_out_bin [2])); LUT6 #( .INIT(64'h6996966996696996)) \dest_out_bin[3]_INST_0 (.I0(\dest_graysync_ff[2] [3]), .I1(\dest_graysync_ff[2] [5]), .I2(\dest_graysync_ff[2] [7]), .I3(\dest_graysync_ff[2] [8]), .I4(\dest_graysync_ff[2] [6]), .I5(\dest_graysync_ff[2] [4]), .O(\^dest_out_bin [3])); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[4]_INST_0 (.I0(\dest_graysync_ff[2] [4]), .I1(\dest_graysync_ff[2] [6]), .I2(\dest_graysync_ff[2] [8]), .I3(\dest_graysync_ff[2] [7]), .I4(\dest_graysync_ff[2] [5]), .O(\^dest_out_bin [4])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[5]_INST_0 (.I0(\dest_graysync_ff[2] [5]), .I1(\dest_graysync_ff[2] [7]), .I2(\dest_graysync_ff[2] [8]), .I3(\dest_graysync_ff[2] [6]), .O(\^dest_out_bin [5])); LUT3 #( .INIT(8'h96)) \dest_out_bin[6]_INST_0 (.I0(\dest_graysync_ff[2] [6]), .I1(\dest_graysync_ff[2] [8]), .I2(\dest_graysync_ff[2] [7]), .O(\^dest_out_bin [6])); LUT2 #( .INIT(4'h6)) \dest_out_bin[7]_INST_0 (.I0(\dest_graysync_ff[2] [7]), .I1(\dest_graysync_ff[2] [8]), .O(\^dest_out_bin [7])); (* SOFT_HLUTNM = "soft_lutpair141" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair141" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); (* SOFT_HLUTNM = "soft_lutpair140" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair140" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); (* SOFT_HLUTNM = "soft_lutpair139" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[4]_i_1 (.I0(src_in_bin[5]), .I1(src_in_bin[4]), .O(gray_enc[4])); (* SOFT_HLUTNM = "soft_lutpair139" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[5]_i_1 (.I0(src_in_bin[6]), .I1(src_in_bin[5]), .O(gray_enc[5])); (* SOFT_HLUTNM = "soft_lutpair138" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[6]_i_1 (.I0(src_in_bin[7]), .I1(src_in_bin[6]), .O(gray_enc[6])); (* SOFT_HLUTNM = "soft_lutpair138" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[7]_i_1 (.I0(src_in_bin[8]), .I1(src_in_bin[7]), .O(gray_enc[7])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(gray_enc[4]), .Q(async_path[4]), .R(1'b0)); FDRE \src_gray_ff_reg[5] (.C(src_clk), .CE(1'b1), .D(gray_enc[5]), .Q(async_path[5]), .R(1'b0)); FDRE \src_gray_ff_reg[6] (.C(src_clk), .CE(1'b1), .D(gray_enc[6]), .Q(async_path[6]), .R(1'b0)); FDRE \src_gray_ff_reg[7] (.C(src_clk), .CE(1'b1), .D(gray_enc[7]), .Q(async_path[7]), .R(1'b0)); FDRE \src_gray_ff_reg[8] (.C(src_clk), .CE(1'b1), .D(src_in_bin[8]), .Q(async_path[8]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *) module axi_chip2chip_64B66B_xpm_cdc_gray__parameterized1__10 (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [8:0]src_in_bin; input dest_clk; output [8:0]dest_out_bin; wire [8:0]async_path; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[1] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[2] ; wire [7:0]\^dest_out_bin ; wire [7:0]gray_enc; wire src_clk; wire [8:0]src_in_bin; assign dest_out_bin[8] = \dest_graysync_ff[2] [8]; assign dest_out_bin[7:0] = \^dest_out_bin [7:0]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][5] (.C(dest_clk), .CE(1'b1), .D(async_path[5]), .Q(\dest_graysync_ff[0] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][6] (.C(dest_clk), .CE(1'b1), .D(async_path[6]), .Q(\dest_graysync_ff[0] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][7] (.C(dest_clk), .CE(1'b1), .D(async_path[7]), .Q(\dest_graysync_ff[0] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][8] (.C(dest_clk), .CE(1'b1), .D(async_path[8]), .Q(\dest_graysync_ff[0] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [5]), .Q(\dest_graysync_ff[1] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [6]), .Q(\dest_graysync_ff[1] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [7]), .Q(\dest_graysync_ff[1] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [8]), .Q(\dest_graysync_ff[1] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [0]), .Q(\dest_graysync_ff[2] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [1]), .Q(\dest_graysync_ff[2] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [2]), .Q(\dest_graysync_ff[2] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [3]), .Q(\dest_graysync_ff[2] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(\dest_graysync_ff[2] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [5]), .Q(\dest_graysync_ff[2] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [6]), .Q(\dest_graysync_ff[2] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [7]), .Q(\dest_graysync_ff[2] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [8]), .Q(\dest_graysync_ff[2] [8]), .R(1'b0)); LUT4 #( .INIT(16'h6996)) \dest_out_bin[0]_INST_0 (.I0(\dest_graysync_ff[2] [0]), .I1(\dest_graysync_ff[2] [2]), .I2(\^dest_out_bin [3]), .I3(\dest_graysync_ff[2] [1]), .O(\^dest_out_bin [0])); LUT3 #( .INIT(8'h96)) \dest_out_bin[1]_INST_0 (.I0(\dest_graysync_ff[2] [1]), .I1(\^dest_out_bin [3]), .I2(\dest_graysync_ff[2] [2]), .O(\^dest_out_bin [1])); LUT2 #( .INIT(4'h6)) \dest_out_bin[2]_INST_0 (.I0(\dest_graysync_ff[2] [2]), .I1(\^dest_out_bin [3]), .O(\^dest_out_bin [2])); LUT6 #( .INIT(64'h6996966996696996)) \dest_out_bin[3]_INST_0 (.I0(\dest_graysync_ff[2] [3]), .I1(\dest_graysync_ff[2] [5]), .I2(\dest_graysync_ff[2] [7]), .I3(\dest_graysync_ff[2] [8]), .I4(\dest_graysync_ff[2] [6]), .I5(\dest_graysync_ff[2] [4]), .O(\^dest_out_bin [3])); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[4]_INST_0 (.I0(\dest_graysync_ff[2] [4]), .I1(\dest_graysync_ff[2] [6]), .I2(\dest_graysync_ff[2] [8]), .I3(\dest_graysync_ff[2] [7]), .I4(\dest_graysync_ff[2] [5]), .O(\^dest_out_bin [4])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[5]_INST_0 (.I0(\dest_graysync_ff[2] [5]), .I1(\dest_graysync_ff[2] [7]), .I2(\dest_graysync_ff[2] [8]), .I3(\dest_graysync_ff[2] [6]), .O(\^dest_out_bin [5])); LUT3 #( .INIT(8'h96)) \dest_out_bin[6]_INST_0 (.I0(\dest_graysync_ff[2] [6]), .I1(\dest_graysync_ff[2] [8]), .I2(\dest_graysync_ff[2] [7]), .O(\^dest_out_bin [6])); LUT2 #( .INIT(4'h6)) \dest_out_bin[7]_INST_0 (.I0(\dest_graysync_ff[2] [7]), .I1(\dest_graysync_ff[2] [8]), .O(\^dest_out_bin [7])); (* SOFT_HLUTNM = "soft_lutpair234" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair234" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); (* SOFT_HLUTNM = "soft_lutpair233" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair233" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); (* SOFT_HLUTNM = "soft_lutpair235" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[4]_i_1 (.I0(src_in_bin[5]), .I1(src_in_bin[4]), .O(gray_enc[4])); (* SOFT_HLUTNM = "soft_lutpair235" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[5]_i_1 (.I0(src_in_bin[6]), .I1(src_in_bin[5]), .O(gray_enc[5])); (* SOFT_HLUTNM = "soft_lutpair236" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[6]_i_1 (.I0(src_in_bin[7]), .I1(src_in_bin[6]), .O(gray_enc[6])); (* SOFT_HLUTNM = "soft_lutpair236" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[7]_i_1 (.I0(src_in_bin[8]), .I1(src_in_bin[7]), .O(gray_enc[7])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(gray_enc[4]), .Q(async_path[4]), .R(1'b0)); FDRE \src_gray_ff_reg[5] (.C(src_clk), .CE(1'b1), .D(gray_enc[5]), .Q(async_path[5]), .R(1'b0)); FDRE \src_gray_ff_reg[6] (.C(src_clk), .CE(1'b1), .D(gray_enc[6]), .Q(async_path[6]), .R(1'b0)); FDRE \src_gray_ff_reg[7] (.C(src_clk), .CE(1'b1), .D(gray_enc[7]), .Q(async_path[7]), .R(1'b0)); FDRE \src_gray_ff_reg[8] (.C(src_clk), .CE(1'b1), .D(src_in_bin[8]), .Q(async_path[8]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *) module axi_chip2chip_64B66B_xpm_cdc_gray__parameterized1__11 (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [8:0]src_in_bin; input dest_clk; output [8:0]dest_out_bin; wire [8:0]async_path; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[1] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[2] ; wire [7:0]\^dest_out_bin ; wire [7:0]gray_enc; wire src_clk; wire [8:0]src_in_bin; assign dest_out_bin[8] = \dest_graysync_ff[2] [8]; assign dest_out_bin[7:0] = \^dest_out_bin [7:0]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][5] (.C(dest_clk), .CE(1'b1), .D(async_path[5]), .Q(\dest_graysync_ff[0] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][6] (.C(dest_clk), .CE(1'b1), .D(async_path[6]), .Q(\dest_graysync_ff[0] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][7] (.C(dest_clk), .CE(1'b1), .D(async_path[7]), .Q(\dest_graysync_ff[0] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][8] (.C(dest_clk), .CE(1'b1), .D(async_path[8]), .Q(\dest_graysync_ff[0] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [5]), .Q(\dest_graysync_ff[1] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [6]), .Q(\dest_graysync_ff[1] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [7]), .Q(\dest_graysync_ff[1] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [8]), .Q(\dest_graysync_ff[1] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [0]), .Q(\dest_graysync_ff[2] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [1]), .Q(\dest_graysync_ff[2] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [2]), .Q(\dest_graysync_ff[2] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [3]), .Q(\dest_graysync_ff[2] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(\dest_graysync_ff[2] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [5]), .Q(\dest_graysync_ff[2] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [6]), .Q(\dest_graysync_ff[2] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [7]), .Q(\dest_graysync_ff[2] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [8]), .Q(\dest_graysync_ff[2] [8]), .R(1'b0)); LUT4 #( .INIT(16'h6996)) \dest_out_bin[0]_INST_0 (.I0(\dest_graysync_ff[2] [0]), .I1(\dest_graysync_ff[2] [2]), .I2(\^dest_out_bin [3]), .I3(\dest_graysync_ff[2] [1]), .O(\^dest_out_bin [0])); LUT3 #( .INIT(8'h96)) \dest_out_bin[1]_INST_0 (.I0(\dest_graysync_ff[2] [1]), .I1(\^dest_out_bin [3]), .I2(\dest_graysync_ff[2] [2]), .O(\^dest_out_bin [1])); LUT2 #( .INIT(4'h6)) \dest_out_bin[2]_INST_0 (.I0(\dest_graysync_ff[2] [2]), .I1(\^dest_out_bin [3]), .O(\^dest_out_bin [2])); LUT6 #( .INIT(64'h6996966996696996)) \dest_out_bin[3]_INST_0 (.I0(\dest_graysync_ff[2] [3]), .I1(\dest_graysync_ff[2] [5]), .I2(\dest_graysync_ff[2] [7]), .I3(\dest_graysync_ff[2] [8]), .I4(\dest_graysync_ff[2] [6]), .I5(\dest_graysync_ff[2] [4]), .O(\^dest_out_bin [3])); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[4]_INST_0 (.I0(\dest_graysync_ff[2] [4]), .I1(\dest_graysync_ff[2] [6]), .I2(\dest_graysync_ff[2] [8]), .I3(\dest_graysync_ff[2] [7]), .I4(\dest_graysync_ff[2] [5]), .O(\^dest_out_bin [4])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[5]_INST_0 (.I0(\dest_graysync_ff[2] [5]), .I1(\dest_graysync_ff[2] [7]), .I2(\dest_graysync_ff[2] [8]), .I3(\dest_graysync_ff[2] [6]), .O(\^dest_out_bin [5])); LUT3 #( .INIT(8'h96)) \dest_out_bin[6]_INST_0 (.I0(\dest_graysync_ff[2] [6]), .I1(\dest_graysync_ff[2] [8]), .I2(\dest_graysync_ff[2] [7]), .O(\^dest_out_bin [6])); LUT2 #( .INIT(4'h6)) \dest_out_bin[7]_INST_0 (.I0(\dest_graysync_ff[2] [7]), .I1(\dest_graysync_ff[2] [8]), .O(\^dest_out_bin [7])); (* SOFT_HLUTNM = "soft_lutpair165" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair165" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); (* SOFT_HLUTNM = "soft_lutpair166" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair166" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); (* SOFT_HLUTNM = "soft_lutpair167" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[4]_i_1 (.I0(src_in_bin[5]), .I1(src_in_bin[4]), .O(gray_enc[4])); (* SOFT_HLUTNM = "soft_lutpair167" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[5]_i_1 (.I0(src_in_bin[6]), .I1(src_in_bin[5]), .O(gray_enc[5])); (* SOFT_HLUTNM = "soft_lutpair168" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[6]_i_1 (.I0(src_in_bin[7]), .I1(src_in_bin[6]), .O(gray_enc[6])); (* SOFT_HLUTNM = "soft_lutpair168" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[7]_i_1 (.I0(src_in_bin[8]), .I1(src_in_bin[7]), .O(gray_enc[7])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(gray_enc[4]), .Q(async_path[4]), .R(1'b0)); FDRE \src_gray_ff_reg[5] (.C(src_clk), .CE(1'b1), .D(gray_enc[5]), .Q(async_path[5]), .R(1'b0)); FDRE \src_gray_ff_reg[6] (.C(src_clk), .CE(1'b1), .D(gray_enc[6]), .Q(async_path[6]), .R(1'b0)); FDRE \src_gray_ff_reg[7] (.C(src_clk), .CE(1'b1), .D(gray_enc[7]), .Q(async_path[7]), .R(1'b0)); FDRE \src_gray_ff_reg[8] (.C(src_clk), .CE(1'b1), .D(src_in_bin[8]), .Q(async_path[8]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *) module axi_chip2chip_64B66B_xpm_cdc_gray__parameterized1__12 (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [8:0]src_in_bin; input dest_clk; output [8:0]dest_out_bin; wire [8:0]async_path; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[1] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[2] ; wire [7:0]\^dest_out_bin ; wire [7:0]gray_enc; wire src_clk; wire [8:0]src_in_bin; assign dest_out_bin[8] = \dest_graysync_ff[2] [8]; assign dest_out_bin[7:0] = \^dest_out_bin [7:0]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][5] (.C(dest_clk), .CE(1'b1), .D(async_path[5]), .Q(\dest_graysync_ff[0] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][6] (.C(dest_clk), .CE(1'b1), .D(async_path[6]), .Q(\dest_graysync_ff[0] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][7] (.C(dest_clk), .CE(1'b1), .D(async_path[7]), .Q(\dest_graysync_ff[0] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][8] (.C(dest_clk), .CE(1'b1), .D(async_path[8]), .Q(\dest_graysync_ff[0] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [5]), .Q(\dest_graysync_ff[1] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [6]), .Q(\dest_graysync_ff[1] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [7]), .Q(\dest_graysync_ff[1] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [8]), .Q(\dest_graysync_ff[1] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [0]), .Q(\dest_graysync_ff[2] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [1]), .Q(\dest_graysync_ff[2] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [2]), .Q(\dest_graysync_ff[2] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [3]), .Q(\dest_graysync_ff[2] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(\dest_graysync_ff[2] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [5]), .Q(\dest_graysync_ff[2] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [6]), .Q(\dest_graysync_ff[2] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [7]), .Q(\dest_graysync_ff[2] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [8]), .Q(\dest_graysync_ff[2] [8]), .R(1'b0)); LUT4 #( .INIT(16'h6996)) \dest_out_bin[0]_INST_0 (.I0(\dest_graysync_ff[2] [0]), .I1(\dest_graysync_ff[2] [2]), .I2(\^dest_out_bin [3]), .I3(\dest_graysync_ff[2] [1]), .O(\^dest_out_bin [0])); LUT3 #( .INIT(8'h96)) \dest_out_bin[1]_INST_0 (.I0(\dest_graysync_ff[2] [1]), .I1(\^dest_out_bin [3]), .I2(\dest_graysync_ff[2] [2]), .O(\^dest_out_bin [1])); LUT2 #( .INIT(4'h6)) \dest_out_bin[2]_INST_0 (.I0(\dest_graysync_ff[2] [2]), .I1(\^dest_out_bin [3]), .O(\^dest_out_bin [2])); LUT6 #( .INIT(64'h6996966996696996)) \dest_out_bin[3]_INST_0 (.I0(\dest_graysync_ff[2] [3]), .I1(\dest_graysync_ff[2] [5]), .I2(\dest_graysync_ff[2] [7]), .I3(\dest_graysync_ff[2] [8]), .I4(\dest_graysync_ff[2] [6]), .I5(\dest_graysync_ff[2] [4]), .O(\^dest_out_bin [3])); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[4]_INST_0 (.I0(\dest_graysync_ff[2] [4]), .I1(\dest_graysync_ff[2] [6]), .I2(\dest_graysync_ff[2] [8]), .I3(\dest_graysync_ff[2] [7]), .I4(\dest_graysync_ff[2] [5]), .O(\^dest_out_bin [4])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[5]_INST_0 (.I0(\dest_graysync_ff[2] [5]), .I1(\dest_graysync_ff[2] [7]), .I2(\dest_graysync_ff[2] [8]), .I3(\dest_graysync_ff[2] [6]), .O(\^dest_out_bin [5])); LUT3 #( .INIT(8'h96)) \dest_out_bin[6]_INST_0 (.I0(\dest_graysync_ff[2] [6]), .I1(\dest_graysync_ff[2] [8]), .I2(\dest_graysync_ff[2] [7]), .O(\^dest_out_bin [6])); LUT2 #( .INIT(4'h6)) \dest_out_bin[7]_INST_0 (.I0(\dest_graysync_ff[2] [7]), .I1(\dest_graysync_ff[2] [8]), .O(\^dest_out_bin [7])); (* SOFT_HLUTNM = "soft_lutpair174" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair174" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); (* SOFT_HLUTNM = "soft_lutpair173" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair173" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); (* SOFT_HLUTNM = "soft_lutpair175" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[4]_i_1 (.I0(src_in_bin[5]), .I1(src_in_bin[4]), .O(gray_enc[4])); (* SOFT_HLUTNM = "soft_lutpair175" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[5]_i_1 (.I0(src_in_bin[6]), .I1(src_in_bin[5]), .O(gray_enc[5])); (* SOFT_HLUTNM = "soft_lutpair176" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[6]_i_1 (.I0(src_in_bin[7]), .I1(src_in_bin[6]), .O(gray_enc[6])); (* SOFT_HLUTNM = "soft_lutpair176" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[7]_i_1 (.I0(src_in_bin[8]), .I1(src_in_bin[7]), .O(gray_enc[7])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(gray_enc[4]), .Q(async_path[4]), .R(1'b0)); FDRE \src_gray_ff_reg[5] (.C(src_clk), .CE(1'b1), .D(gray_enc[5]), .Q(async_path[5]), .R(1'b0)); FDRE \src_gray_ff_reg[6] (.C(src_clk), .CE(1'b1), .D(gray_enc[6]), .Q(async_path[6]), .R(1'b0)); FDRE \src_gray_ff_reg[7] (.C(src_clk), .CE(1'b1), .D(gray_enc[7]), .Q(async_path[7]), .R(1'b0)); FDRE \src_gray_ff_reg[8] (.C(src_clk), .CE(1'b1), .D(src_in_bin[8]), .Q(async_path[8]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *) module axi_chip2chip_64B66B_xpm_cdc_gray__parameterized1__7 (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [8:0]src_in_bin; input dest_clk; output [8:0]dest_out_bin; wire [8:0]async_path; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[1] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[2] ; wire [7:0]\^dest_out_bin ; wire [7:0]gray_enc; wire src_clk; wire [8:0]src_in_bin; assign dest_out_bin[8] = \dest_graysync_ff[2] [8]; assign dest_out_bin[7:0] = \^dest_out_bin [7:0]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][5] (.C(dest_clk), .CE(1'b1), .D(async_path[5]), .Q(\dest_graysync_ff[0] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][6] (.C(dest_clk), .CE(1'b1), .D(async_path[6]), .Q(\dest_graysync_ff[0] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][7] (.C(dest_clk), .CE(1'b1), .D(async_path[7]), .Q(\dest_graysync_ff[0] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][8] (.C(dest_clk), .CE(1'b1), .D(async_path[8]), .Q(\dest_graysync_ff[0] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [5]), .Q(\dest_graysync_ff[1] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [6]), .Q(\dest_graysync_ff[1] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [7]), .Q(\dest_graysync_ff[1] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [8]), .Q(\dest_graysync_ff[1] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [0]), .Q(\dest_graysync_ff[2] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [1]), .Q(\dest_graysync_ff[2] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [2]), .Q(\dest_graysync_ff[2] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [3]), .Q(\dest_graysync_ff[2] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(\dest_graysync_ff[2] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [5]), .Q(\dest_graysync_ff[2] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [6]), .Q(\dest_graysync_ff[2] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [7]), .Q(\dest_graysync_ff[2] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [8]), .Q(\dest_graysync_ff[2] [8]), .R(1'b0)); LUT4 #( .INIT(16'h6996)) \dest_out_bin[0]_INST_0 (.I0(\dest_graysync_ff[2] [0]), .I1(\dest_graysync_ff[2] [2]), .I2(\^dest_out_bin [3]), .I3(\dest_graysync_ff[2] [1]), .O(\^dest_out_bin [0])); LUT3 #( .INIT(8'h96)) \dest_out_bin[1]_INST_0 (.I0(\dest_graysync_ff[2] [1]), .I1(\^dest_out_bin [3]), .I2(\dest_graysync_ff[2] [2]), .O(\^dest_out_bin [1])); LUT2 #( .INIT(4'h6)) \dest_out_bin[2]_INST_0 (.I0(\dest_graysync_ff[2] [2]), .I1(\^dest_out_bin [3]), .O(\^dest_out_bin [2])); LUT6 #( .INIT(64'h6996966996696996)) \dest_out_bin[3]_INST_0 (.I0(\dest_graysync_ff[2] [3]), .I1(\dest_graysync_ff[2] [5]), .I2(\dest_graysync_ff[2] [7]), .I3(\dest_graysync_ff[2] [8]), .I4(\dest_graysync_ff[2] [6]), .I5(\dest_graysync_ff[2] [4]), .O(\^dest_out_bin [3])); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[4]_INST_0 (.I0(\dest_graysync_ff[2] [4]), .I1(\dest_graysync_ff[2] [6]), .I2(\dest_graysync_ff[2] [8]), .I3(\dest_graysync_ff[2] [7]), .I4(\dest_graysync_ff[2] [5]), .O(\^dest_out_bin [4])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[5]_INST_0 (.I0(\dest_graysync_ff[2] [5]), .I1(\dest_graysync_ff[2] [7]), .I2(\dest_graysync_ff[2] [8]), .I3(\dest_graysync_ff[2] [6]), .O(\^dest_out_bin [5])); LUT3 #( .INIT(8'h96)) \dest_out_bin[6]_INST_0 (.I0(\dest_graysync_ff[2] [6]), .I1(\dest_graysync_ff[2] [8]), .I2(\dest_graysync_ff[2] [7]), .O(\^dest_out_bin [6])); LUT2 #( .INIT(4'h6)) \dest_out_bin[7]_INST_0 (.I0(\dest_graysync_ff[2] [7]), .I1(\dest_graysync_ff[2] [8]), .O(\^dest_out_bin [7])); (* SOFT_HLUTNM = "soft_lutpair108" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair108" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); (* SOFT_HLUTNM = "soft_lutpair107" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair107" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); (* SOFT_HLUTNM = "soft_lutpair106" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[4]_i_1 (.I0(src_in_bin[5]), .I1(src_in_bin[4]), .O(gray_enc[4])); (* SOFT_HLUTNM = "soft_lutpair106" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[5]_i_1 (.I0(src_in_bin[6]), .I1(src_in_bin[5]), .O(gray_enc[5])); (* SOFT_HLUTNM = "soft_lutpair105" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[6]_i_1 (.I0(src_in_bin[7]), .I1(src_in_bin[6]), .O(gray_enc[6])); (* SOFT_HLUTNM = "soft_lutpair105" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[7]_i_1 (.I0(src_in_bin[8]), .I1(src_in_bin[7]), .O(gray_enc[7])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(gray_enc[4]), .Q(async_path[4]), .R(1'b0)); FDRE \src_gray_ff_reg[5] (.C(src_clk), .CE(1'b1), .D(gray_enc[5]), .Q(async_path[5]), .R(1'b0)); FDRE \src_gray_ff_reg[6] (.C(src_clk), .CE(1'b1), .D(gray_enc[6]), .Q(async_path[6]), .R(1'b0)); FDRE \src_gray_ff_reg[7] (.C(src_clk), .CE(1'b1), .D(gray_enc[7]), .Q(async_path[7]), .R(1'b0)); FDRE \src_gray_ff_reg[8] (.C(src_clk), .CE(1'b1), .D(src_in_bin[8]), .Q(async_path[8]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *) module axi_chip2chip_64B66B_xpm_cdc_gray__parameterized1__8 (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [8:0]src_in_bin; input dest_clk; output [8:0]dest_out_bin; wire [8:0]async_path; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[1] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[2] ; wire [7:0]\^dest_out_bin ; wire [7:0]gray_enc; wire src_clk; wire [8:0]src_in_bin; assign dest_out_bin[8] = \dest_graysync_ff[2] [8]; assign dest_out_bin[7:0] = \^dest_out_bin [7:0]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][5] (.C(dest_clk), .CE(1'b1), .D(async_path[5]), .Q(\dest_graysync_ff[0] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][6] (.C(dest_clk), .CE(1'b1), .D(async_path[6]), .Q(\dest_graysync_ff[0] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][7] (.C(dest_clk), .CE(1'b1), .D(async_path[7]), .Q(\dest_graysync_ff[0] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][8] (.C(dest_clk), .CE(1'b1), .D(async_path[8]), .Q(\dest_graysync_ff[0] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [5]), .Q(\dest_graysync_ff[1] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [6]), .Q(\dest_graysync_ff[1] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [7]), .Q(\dest_graysync_ff[1] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [8]), .Q(\dest_graysync_ff[1] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [0]), .Q(\dest_graysync_ff[2] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [1]), .Q(\dest_graysync_ff[2] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [2]), .Q(\dest_graysync_ff[2] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [3]), .Q(\dest_graysync_ff[2] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(\dest_graysync_ff[2] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [5]), .Q(\dest_graysync_ff[2] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [6]), .Q(\dest_graysync_ff[2] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [7]), .Q(\dest_graysync_ff[2] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [8]), .Q(\dest_graysync_ff[2] [8]), .R(1'b0)); LUT4 #( .INIT(16'h6996)) \dest_out_bin[0]_INST_0 (.I0(\dest_graysync_ff[2] [0]), .I1(\dest_graysync_ff[2] [2]), .I2(\^dest_out_bin [3]), .I3(\dest_graysync_ff[2] [1]), .O(\^dest_out_bin [0])); LUT3 #( .INIT(8'h96)) \dest_out_bin[1]_INST_0 (.I0(\dest_graysync_ff[2] [1]), .I1(\^dest_out_bin [3]), .I2(\dest_graysync_ff[2] [2]), .O(\^dest_out_bin [1])); LUT2 #( .INIT(4'h6)) \dest_out_bin[2]_INST_0 (.I0(\dest_graysync_ff[2] [2]), .I1(\^dest_out_bin [3]), .O(\^dest_out_bin [2])); LUT6 #( .INIT(64'h6996966996696996)) \dest_out_bin[3]_INST_0 (.I0(\dest_graysync_ff[2] [3]), .I1(\dest_graysync_ff[2] [5]), .I2(\dest_graysync_ff[2] [7]), .I3(\dest_graysync_ff[2] [8]), .I4(\dest_graysync_ff[2] [6]), .I5(\dest_graysync_ff[2] [4]), .O(\^dest_out_bin [3])); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[4]_INST_0 (.I0(\dest_graysync_ff[2] [4]), .I1(\dest_graysync_ff[2] [6]), .I2(\dest_graysync_ff[2] [8]), .I3(\dest_graysync_ff[2] [7]), .I4(\dest_graysync_ff[2] [5]), .O(\^dest_out_bin [4])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[5]_INST_0 (.I0(\dest_graysync_ff[2] [5]), .I1(\dest_graysync_ff[2] [7]), .I2(\dest_graysync_ff[2] [8]), .I3(\dest_graysync_ff[2] [6]), .O(\^dest_out_bin [5])); LUT3 #( .INIT(8'h96)) \dest_out_bin[6]_INST_0 (.I0(\dest_graysync_ff[2] [6]), .I1(\dest_graysync_ff[2] [8]), .I2(\dest_graysync_ff[2] [7]), .O(\^dest_out_bin [6])); LUT2 #( .INIT(4'h6)) \dest_out_bin[7]_INST_0 (.I0(\dest_graysync_ff[2] [7]), .I1(\dest_graysync_ff[2] [8]), .O(\^dest_out_bin [7])); (* SOFT_HLUTNM = "soft_lutpair74" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair74" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); (* SOFT_HLUTNM = "soft_lutpair73" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair73" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); (* SOFT_HLUTNM = "soft_lutpair72" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[4]_i_1 (.I0(src_in_bin[5]), .I1(src_in_bin[4]), .O(gray_enc[4])); (* SOFT_HLUTNM = "soft_lutpair72" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[5]_i_1 (.I0(src_in_bin[6]), .I1(src_in_bin[5]), .O(gray_enc[5])); (* SOFT_HLUTNM = "soft_lutpair71" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[6]_i_1 (.I0(src_in_bin[7]), .I1(src_in_bin[6]), .O(gray_enc[6])); (* SOFT_HLUTNM = "soft_lutpair71" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[7]_i_1 (.I0(src_in_bin[8]), .I1(src_in_bin[7]), .O(gray_enc[7])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(gray_enc[4]), .Q(async_path[4]), .R(1'b0)); FDRE \src_gray_ff_reg[5] (.C(src_clk), .CE(1'b1), .D(gray_enc[5]), .Q(async_path[5]), .R(1'b0)); FDRE \src_gray_ff_reg[6] (.C(src_clk), .CE(1'b1), .D(gray_enc[6]), .Q(async_path[6]), .R(1'b0)); FDRE \src_gray_ff_reg[7] (.C(src_clk), .CE(1'b1), .D(gray_enc[7]), .Q(async_path[7]), .R(1'b0)); FDRE \src_gray_ff_reg[8] (.C(src_clk), .CE(1'b1), .D(src_in_bin[8]), .Q(async_path[8]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *) module axi_chip2chip_64B66B_xpm_cdc_gray__parameterized1__9 (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [8:0]src_in_bin; input dest_clk; output [8:0]dest_out_bin; wire [8:0]async_path; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[1] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [8:0]\dest_graysync_ff[2] ; wire [7:0]\^dest_out_bin ; wire [7:0]gray_enc; wire src_clk; wire [8:0]src_in_bin; assign dest_out_bin[8] = \dest_graysync_ff[2] [8]; assign dest_out_bin[7:0] = \^dest_out_bin [7:0]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][5] (.C(dest_clk), .CE(1'b1), .D(async_path[5]), .Q(\dest_graysync_ff[0] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][6] (.C(dest_clk), .CE(1'b1), .D(async_path[6]), .Q(\dest_graysync_ff[0] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][7] (.C(dest_clk), .CE(1'b1), .D(async_path[7]), .Q(\dest_graysync_ff[0] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][8] (.C(dest_clk), .CE(1'b1), .D(async_path[8]), .Q(\dest_graysync_ff[0] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [5]), .Q(\dest_graysync_ff[1] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [6]), .Q(\dest_graysync_ff[1] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [7]), .Q(\dest_graysync_ff[1] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [8]), .Q(\dest_graysync_ff[1] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [0]), .Q(\dest_graysync_ff[2] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [1]), .Q(\dest_graysync_ff[2] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [2]), .Q(\dest_graysync_ff[2] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [3]), .Q(\dest_graysync_ff[2] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(\dest_graysync_ff[2] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [5]), .Q(\dest_graysync_ff[2] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [6]), .Q(\dest_graysync_ff[2] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [7]), .Q(\dest_graysync_ff[2] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [8]), .Q(\dest_graysync_ff[2] [8]), .R(1'b0)); LUT4 #( .INIT(16'h6996)) \dest_out_bin[0]_INST_0 (.I0(\dest_graysync_ff[2] [0]), .I1(\dest_graysync_ff[2] [2]), .I2(\^dest_out_bin [3]), .I3(\dest_graysync_ff[2] [1]), .O(\^dest_out_bin [0])); LUT3 #( .INIT(8'h96)) \dest_out_bin[1]_INST_0 (.I0(\dest_graysync_ff[2] [1]), .I1(\^dest_out_bin [3]), .I2(\dest_graysync_ff[2] [2]), .O(\^dest_out_bin [1])); LUT2 #( .INIT(4'h6)) \dest_out_bin[2]_INST_0 (.I0(\dest_graysync_ff[2] [2]), .I1(\^dest_out_bin [3]), .O(\^dest_out_bin [2])); LUT6 #( .INIT(64'h6996966996696996)) \dest_out_bin[3]_INST_0 (.I0(\dest_graysync_ff[2] [3]), .I1(\dest_graysync_ff[2] [5]), .I2(\dest_graysync_ff[2] [7]), .I3(\dest_graysync_ff[2] [8]), .I4(\dest_graysync_ff[2] [6]), .I5(\dest_graysync_ff[2] [4]), .O(\^dest_out_bin [3])); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[4]_INST_0 (.I0(\dest_graysync_ff[2] [4]), .I1(\dest_graysync_ff[2] [6]), .I2(\dest_graysync_ff[2] [8]), .I3(\dest_graysync_ff[2] [7]), .I4(\dest_graysync_ff[2] [5]), .O(\^dest_out_bin [4])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[5]_INST_0 (.I0(\dest_graysync_ff[2] [5]), .I1(\dest_graysync_ff[2] [7]), .I2(\dest_graysync_ff[2] [8]), .I3(\dest_graysync_ff[2] [6]), .O(\^dest_out_bin [5])); LUT3 #( .INIT(8'h96)) \dest_out_bin[6]_INST_0 (.I0(\dest_graysync_ff[2] [6]), .I1(\dest_graysync_ff[2] [8]), .I2(\dest_graysync_ff[2] [7]), .O(\^dest_out_bin [6])); LUT2 #( .INIT(4'h6)) \dest_out_bin[7]_INST_0 (.I0(\dest_graysync_ff[2] [7]), .I1(\dest_graysync_ff[2] [8]), .O(\^dest_out_bin [7])); (* SOFT_HLUTNM = "soft_lutpair225" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair225" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); (* SOFT_HLUTNM = "soft_lutpair226" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair226" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); (* SOFT_HLUTNM = "soft_lutpair227" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[4]_i_1 (.I0(src_in_bin[5]), .I1(src_in_bin[4]), .O(gray_enc[4])); (* SOFT_HLUTNM = "soft_lutpair227" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[5]_i_1 (.I0(src_in_bin[6]), .I1(src_in_bin[5]), .O(gray_enc[5])); (* SOFT_HLUTNM = "soft_lutpair228" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[6]_i_1 (.I0(src_in_bin[7]), .I1(src_in_bin[6]), .O(gray_enc[6])); (* SOFT_HLUTNM = "soft_lutpair228" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[7]_i_1 (.I0(src_in_bin[8]), .I1(src_in_bin[7]), .O(gray_enc[7])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(gray_enc[4]), .Q(async_path[4]), .R(1'b0)); FDRE \src_gray_ff_reg[5] (.C(src_clk), .CE(1'b1), .D(gray_enc[5]), .Q(async_path[5]), .R(1'b0)); FDRE \src_gray_ff_reg[6] (.C(src_clk), .CE(1'b1), .D(gray_enc[6]), .Q(async_path[6]), .R(1'b0)); FDRE \src_gray_ff_reg[7] (.C(src_clk), .CE(1'b1), .D(gray_enc[7]), .Q(async_path[7]), .R(1'b0)); FDRE \src_gray_ff_reg[8] (.C(src_clk), .CE(1'b1), .D(src_in_bin[8]), .Q(async_path[8]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "5" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "10" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *) module axi_chip2chip_64B66B_xpm_cdc_gray__parameterized2 (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [9:0]src_in_bin; input dest_clk; output [9:0]dest_out_bin; wire [9:0]async_path; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [9:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [9:0]\dest_graysync_ff[1] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [9:0]\dest_graysync_ff[2] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [9:0]\dest_graysync_ff[3] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [9:0]\dest_graysync_ff[4] ; wire [8:0]\^dest_out_bin ; wire [8:0]gray_enc; wire src_clk; wire [9:0]src_in_bin; assign dest_out_bin[9] = \dest_graysync_ff[4] [9]; assign dest_out_bin[8:0] = \^dest_out_bin [8:0]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][5] (.C(dest_clk), .CE(1'b1), .D(async_path[5]), .Q(\dest_graysync_ff[0] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][6] (.C(dest_clk), .CE(1'b1), .D(async_path[6]), .Q(\dest_graysync_ff[0] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][7] (.C(dest_clk), .CE(1'b1), .D(async_path[7]), .Q(\dest_graysync_ff[0] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][8] (.C(dest_clk), .CE(1'b1), .D(async_path[8]), .Q(\dest_graysync_ff[0] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][9] (.C(dest_clk), .CE(1'b1), .D(async_path[9]), .Q(\dest_graysync_ff[0] [9]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [5]), .Q(\dest_graysync_ff[1] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [6]), .Q(\dest_graysync_ff[1] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [7]), .Q(\dest_graysync_ff[1] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [8]), .Q(\dest_graysync_ff[1] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][9] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [9]), .Q(\dest_graysync_ff[1] [9]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [0]), .Q(\dest_graysync_ff[2] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [1]), .Q(\dest_graysync_ff[2] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [2]), .Q(\dest_graysync_ff[2] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [3]), .Q(\dest_graysync_ff[2] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(\dest_graysync_ff[2] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [5]), .Q(\dest_graysync_ff[2] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [6]), .Q(\dest_graysync_ff[2] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [7]), .Q(\dest_graysync_ff[2] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [8]), .Q(\dest_graysync_ff[2] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][9] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [9]), .Q(\dest_graysync_ff[2] [9]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [0]), .Q(\dest_graysync_ff[3] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [1]), .Q(\dest_graysync_ff[3] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [2]), .Q(\dest_graysync_ff[3] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [3]), .Q(\dest_graysync_ff[3] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [4]), .Q(\dest_graysync_ff[3] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [5]), .Q(\dest_graysync_ff[3] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [6]), .Q(\dest_graysync_ff[3] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [7]), .Q(\dest_graysync_ff[3] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [8]), .Q(\dest_graysync_ff[3] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][9] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [9]), .Q(\dest_graysync_ff[3] [9]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [0]), .Q(\dest_graysync_ff[4] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [1]), .Q(\dest_graysync_ff[4] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [2]), .Q(\dest_graysync_ff[4] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [3]), .Q(\dest_graysync_ff[4] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [4]), .Q(\dest_graysync_ff[4] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [5]), .Q(\dest_graysync_ff[4] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [6]), .Q(\dest_graysync_ff[4] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [7]), .Q(\dest_graysync_ff[4] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [8]), .Q(\dest_graysync_ff[4] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][9] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [9]), .Q(\dest_graysync_ff[4] [9]), .R(1'b0)); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[0]_INST_0 (.I0(\dest_graysync_ff[4] [0]), .I1(\dest_graysync_ff[4] [2]), .I2(\^dest_out_bin [4]), .I3(\dest_graysync_ff[4] [3]), .I4(\dest_graysync_ff[4] [1]), .O(\^dest_out_bin [0])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[1]_INST_0 (.I0(\dest_graysync_ff[4] [1]), .I1(\dest_graysync_ff[4] [3]), .I2(\^dest_out_bin [4]), .I3(\dest_graysync_ff[4] [2]), .O(\^dest_out_bin [1])); LUT3 #( .INIT(8'h96)) \dest_out_bin[2]_INST_0 (.I0(\dest_graysync_ff[4] [2]), .I1(\^dest_out_bin [4]), .I2(\dest_graysync_ff[4] [3]), .O(\^dest_out_bin [2])); LUT2 #( .INIT(4'h6)) \dest_out_bin[3]_INST_0 (.I0(\dest_graysync_ff[4] [3]), .I1(\^dest_out_bin [4]), .O(\^dest_out_bin [3])); LUT6 #( .INIT(64'h6996966996696996)) \dest_out_bin[4]_INST_0 (.I0(\dest_graysync_ff[4] [4]), .I1(\dest_graysync_ff[4] [6]), .I2(\dest_graysync_ff[4] [8]), .I3(\dest_graysync_ff[4] [9]), .I4(\dest_graysync_ff[4] [7]), .I5(\dest_graysync_ff[4] [5]), .O(\^dest_out_bin [4])); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[5]_INST_0 (.I0(\dest_graysync_ff[4] [5]), .I1(\dest_graysync_ff[4] [7]), .I2(\dest_graysync_ff[4] [9]), .I3(\dest_graysync_ff[4] [8]), .I4(\dest_graysync_ff[4] [6]), .O(\^dest_out_bin [5])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[6]_INST_0 (.I0(\dest_graysync_ff[4] [6]), .I1(\dest_graysync_ff[4] [8]), .I2(\dest_graysync_ff[4] [9]), .I3(\dest_graysync_ff[4] [7]), .O(\^dest_out_bin [6])); LUT3 #( .INIT(8'h96)) \dest_out_bin[7]_INST_0 (.I0(\dest_graysync_ff[4] [7]), .I1(\dest_graysync_ff[4] [9]), .I2(\dest_graysync_ff[4] [8]), .O(\^dest_out_bin [7])); LUT2 #( .INIT(4'h6)) \dest_out_bin[8]_INST_0 (.I0(\dest_graysync_ff[4] [8]), .I1(\dest_graysync_ff[4] [9]), .O(\^dest_out_bin [8])); (* SOFT_HLUTNM = "soft_lutpair169" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair169" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); (* SOFT_HLUTNM = "soft_lutpair170" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair170" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); (* SOFT_HLUTNM = "soft_lutpair171" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[4]_i_1 (.I0(src_in_bin[5]), .I1(src_in_bin[4]), .O(gray_enc[4])); (* SOFT_HLUTNM = "soft_lutpair171" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[5]_i_1 (.I0(src_in_bin[6]), .I1(src_in_bin[5]), .O(gray_enc[5])); (* SOFT_HLUTNM = "soft_lutpair172" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[6]_i_1 (.I0(src_in_bin[7]), .I1(src_in_bin[6]), .O(gray_enc[6])); (* SOFT_HLUTNM = "soft_lutpair172" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[7]_i_1 (.I0(src_in_bin[8]), .I1(src_in_bin[7]), .O(gray_enc[7])); LUT2 #( .INIT(4'h6)) \src_gray_ff[8]_i_1 (.I0(src_in_bin[9]), .I1(src_in_bin[8]), .O(gray_enc[8])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(gray_enc[4]), .Q(async_path[4]), .R(1'b0)); FDRE \src_gray_ff_reg[5] (.C(src_clk), .CE(1'b1), .D(gray_enc[5]), .Q(async_path[5]), .R(1'b0)); FDRE \src_gray_ff_reg[6] (.C(src_clk), .CE(1'b1), .D(gray_enc[6]), .Q(async_path[6]), .R(1'b0)); FDRE \src_gray_ff_reg[7] (.C(src_clk), .CE(1'b1), .D(gray_enc[7]), .Q(async_path[7]), .R(1'b0)); FDRE \src_gray_ff_reg[8] (.C(src_clk), .CE(1'b1), .D(gray_enc[8]), .Q(async_path[8]), .R(1'b0)); FDRE \src_gray_ff_reg[9] (.C(src_clk), .CE(1'b1), .D(src_in_bin[9]), .Q(async_path[9]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "5" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "10" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *) module axi_chip2chip_64B66B_xpm_cdc_gray__parameterized2__2 (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [9:0]src_in_bin; input dest_clk; output [9:0]dest_out_bin; wire [9:0]async_path; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [9:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [9:0]\dest_graysync_ff[1] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [9:0]\dest_graysync_ff[2] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [9:0]\dest_graysync_ff[3] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [9:0]\dest_graysync_ff[4] ; wire [8:0]\^dest_out_bin ; wire [8:0]gray_enc; wire src_clk; wire [9:0]src_in_bin; assign dest_out_bin[9] = \dest_graysync_ff[4] [9]; assign dest_out_bin[8:0] = \^dest_out_bin [8:0]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][5] (.C(dest_clk), .CE(1'b1), .D(async_path[5]), .Q(\dest_graysync_ff[0] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][6] (.C(dest_clk), .CE(1'b1), .D(async_path[6]), .Q(\dest_graysync_ff[0] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][7] (.C(dest_clk), .CE(1'b1), .D(async_path[7]), .Q(\dest_graysync_ff[0] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][8] (.C(dest_clk), .CE(1'b1), .D(async_path[8]), .Q(\dest_graysync_ff[0] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][9] (.C(dest_clk), .CE(1'b1), .D(async_path[9]), .Q(\dest_graysync_ff[0] [9]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [5]), .Q(\dest_graysync_ff[1] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [6]), .Q(\dest_graysync_ff[1] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [7]), .Q(\dest_graysync_ff[1] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [8]), .Q(\dest_graysync_ff[1] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][9] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [9]), .Q(\dest_graysync_ff[1] [9]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [0]), .Q(\dest_graysync_ff[2] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [1]), .Q(\dest_graysync_ff[2] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [2]), .Q(\dest_graysync_ff[2] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [3]), .Q(\dest_graysync_ff[2] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(\dest_graysync_ff[2] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [5]), .Q(\dest_graysync_ff[2] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [6]), .Q(\dest_graysync_ff[2] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [7]), .Q(\dest_graysync_ff[2] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [8]), .Q(\dest_graysync_ff[2] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][9] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [9]), .Q(\dest_graysync_ff[2] [9]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [0]), .Q(\dest_graysync_ff[3] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [1]), .Q(\dest_graysync_ff[3] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [2]), .Q(\dest_graysync_ff[3] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [3]), .Q(\dest_graysync_ff[3] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [4]), .Q(\dest_graysync_ff[3] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [5]), .Q(\dest_graysync_ff[3] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [6]), .Q(\dest_graysync_ff[3] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [7]), .Q(\dest_graysync_ff[3] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [8]), .Q(\dest_graysync_ff[3] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[3][9] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[2] [9]), .Q(\dest_graysync_ff[3] [9]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [0]), .Q(\dest_graysync_ff[4] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [1]), .Q(\dest_graysync_ff[4] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [2]), .Q(\dest_graysync_ff[4] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [3]), .Q(\dest_graysync_ff[4] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [4]), .Q(\dest_graysync_ff[4] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [5]), .Q(\dest_graysync_ff[4] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [6]), .Q(\dest_graysync_ff[4] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [7]), .Q(\dest_graysync_ff[4] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [8]), .Q(\dest_graysync_ff[4] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[4][9] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[3] [9]), .Q(\dest_graysync_ff[4] [9]), .R(1'b0)); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[0]_INST_0 (.I0(\dest_graysync_ff[4] [0]), .I1(\dest_graysync_ff[4] [2]), .I2(\^dest_out_bin [4]), .I3(\dest_graysync_ff[4] [3]), .I4(\dest_graysync_ff[4] [1]), .O(\^dest_out_bin [0])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[1]_INST_0 (.I0(\dest_graysync_ff[4] [1]), .I1(\dest_graysync_ff[4] [3]), .I2(\^dest_out_bin [4]), .I3(\dest_graysync_ff[4] [2]), .O(\^dest_out_bin [1])); LUT3 #( .INIT(8'h96)) \dest_out_bin[2]_INST_0 (.I0(\dest_graysync_ff[4] [2]), .I1(\^dest_out_bin [4]), .I2(\dest_graysync_ff[4] [3]), .O(\^dest_out_bin [2])); LUT2 #( .INIT(4'h6)) \dest_out_bin[3]_INST_0 (.I0(\dest_graysync_ff[4] [3]), .I1(\^dest_out_bin [4]), .O(\^dest_out_bin [3])); LUT6 #( .INIT(64'h6996966996696996)) \dest_out_bin[4]_INST_0 (.I0(\dest_graysync_ff[4] [4]), .I1(\dest_graysync_ff[4] [6]), .I2(\dest_graysync_ff[4] [8]), .I3(\dest_graysync_ff[4] [9]), .I4(\dest_graysync_ff[4] [7]), .I5(\dest_graysync_ff[4] [5]), .O(\^dest_out_bin [4])); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[5]_INST_0 (.I0(\dest_graysync_ff[4] [5]), .I1(\dest_graysync_ff[4] [7]), .I2(\dest_graysync_ff[4] [9]), .I3(\dest_graysync_ff[4] [8]), .I4(\dest_graysync_ff[4] [6]), .O(\^dest_out_bin [5])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[6]_INST_0 (.I0(\dest_graysync_ff[4] [6]), .I1(\dest_graysync_ff[4] [8]), .I2(\dest_graysync_ff[4] [9]), .I3(\dest_graysync_ff[4] [7]), .O(\^dest_out_bin [6])); LUT3 #( .INIT(8'h96)) \dest_out_bin[7]_INST_0 (.I0(\dest_graysync_ff[4] [7]), .I1(\dest_graysync_ff[4] [9]), .I2(\dest_graysync_ff[4] [8]), .O(\^dest_out_bin [7])); LUT2 #( .INIT(4'h6)) \dest_out_bin[8]_INST_0 (.I0(\dest_graysync_ff[4] [8]), .I1(\dest_graysync_ff[4] [9]), .O(\^dest_out_bin [8])); (* SOFT_HLUTNM = "soft_lutpair229" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair229" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); (* SOFT_HLUTNM = "soft_lutpair230" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair230" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); (* SOFT_HLUTNM = "soft_lutpair231" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[4]_i_1 (.I0(src_in_bin[5]), .I1(src_in_bin[4]), .O(gray_enc[4])); (* SOFT_HLUTNM = "soft_lutpair231" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[5]_i_1 (.I0(src_in_bin[6]), .I1(src_in_bin[5]), .O(gray_enc[5])); (* SOFT_HLUTNM = "soft_lutpair232" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[6]_i_1 (.I0(src_in_bin[7]), .I1(src_in_bin[6]), .O(gray_enc[6])); (* SOFT_HLUTNM = "soft_lutpair232" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[7]_i_1 (.I0(src_in_bin[8]), .I1(src_in_bin[7]), .O(gray_enc[7])); LUT2 #( .INIT(4'h6)) \src_gray_ff[8]_i_1 (.I0(src_in_bin[9]), .I1(src_in_bin[8]), .O(gray_enc[8])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(gray_enc[4]), .Q(async_path[4]), .R(1'b0)); FDRE \src_gray_ff_reg[5] (.C(src_clk), .CE(1'b1), .D(gray_enc[5]), .Q(async_path[5]), .R(1'b0)); FDRE \src_gray_ff_reg[6] (.C(src_clk), .CE(1'b1), .D(gray_enc[6]), .Q(async_path[6]), .R(1'b0)); FDRE \src_gray_ff_reg[7] (.C(src_clk), .CE(1'b1), .D(gray_enc[7]), .Q(async_path[7]), .R(1'b0)); FDRE \src_gray_ff_reg[8] (.C(src_clk), .CE(1'b1), .D(gray_enc[8]), .Q(async_path[8]), .R(1'b0)); FDRE \src_gray_ff_reg[9] (.C(src_clk), .CE(1'b1), .D(src_in_bin[9]), .Q(async_path[9]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "10" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *) module axi_chip2chip_64B66B_xpm_cdc_gray__parameterized3 (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [9:0]src_in_bin; input dest_clk; output [9:0]dest_out_bin; wire [9:0]async_path; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [9:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [9:0]\dest_graysync_ff[1] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [9:0]\dest_graysync_ff[2] ; wire [8:0]\^dest_out_bin ; wire [8:0]gray_enc; wire src_clk; wire [9:0]src_in_bin; assign dest_out_bin[9] = \dest_graysync_ff[2] [9]; assign dest_out_bin[8:0] = \^dest_out_bin [8:0]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][5] (.C(dest_clk), .CE(1'b1), .D(async_path[5]), .Q(\dest_graysync_ff[0] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][6] (.C(dest_clk), .CE(1'b1), .D(async_path[6]), .Q(\dest_graysync_ff[0] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][7] (.C(dest_clk), .CE(1'b1), .D(async_path[7]), .Q(\dest_graysync_ff[0] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][8] (.C(dest_clk), .CE(1'b1), .D(async_path[8]), .Q(\dest_graysync_ff[0] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][9] (.C(dest_clk), .CE(1'b1), .D(async_path[9]), .Q(\dest_graysync_ff[0] [9]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [5]), .Q(\dest_graysync_ff[1] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [6]), .Q(\dest_graysync_ff[1] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [7]), .Q(\dest_graysync_ff[1] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [8]), .Q(\dest_graysync_ff[1] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][9] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [9]), .Q(\dest_graysync_ff[1] [9]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [0]), .Q(\dest_graysync_ff[2] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [1]), .Q(\dest_graysync_ff[2] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [2]), .Q(\dest_graysync_ff[2] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [3]), .Q(\dest_graysync_ff[2] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(\dest_graysync_ff[2] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [5]), .Q(\dest_graysync_ff[2] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [6]), .Q(\dest_graysync_ff[2] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [7]), .Q(\dest_graysync_ff[2] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [8]), .Q(\dest_graysync_ff[2] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][9] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [9]), .Q(\dest_graysync_ff[2] [9]), .R(1'b0)); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[0]_INST_0 (.I0(\dest_graysync_ff[2] [0]), .I1(\dest_graysync_ff[2] [2]), .I2(\^dest_out_bin [4]), .I3(\dest_graysync_ff[2] [3]), .I4(\dest_graysync_ff[2] [1]), .O(\^dest_out_bin [0])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[1]_INST_0 (.I0(\dest_graysync_ff[2] [1]), .I1(\dest_graysync_ff[2] [3]), .I2(\^dest_out_bin [4]), .I3(\dest_graysync_ff[2] [2]), .O(\^dest_out_bin [1])); LUT3 #( .INIT(8'h96)) \dest_out_bin[2]_INST_0 (.I0(\dest_graysync_ff[2] [2]), .I1(\^dest_out_bin [4]), .I2(\dest_graysync_ff[2] [3]), .O(\^dest_out_bin [2])); LUT2 #( .INIT(4'h6)) \dest_out_bin[3]_INST_0 (.I0(\dest_graysync_ff[2] [3]), .I1(\^dest_out_bin [4]), .O(\^dest_out_bin [3])); LUT6 #( .INIT(64'h6996966996696996)) \dest_out_bin[4]_INST_0 (.I0(\dest_graysync_ff[2] [4]), .I1(\dest_graysync_ff[2] [6]), .I2(\dest_graysync_ff[2] [8]), .I3(\dest_graysync_ff[2] [9]), .I4(\dest_graysync_ff[2] [7]), .I5(\dest_graysync_ff[2] [5]), .O(\^dest_out_bin [4])); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[5]_INST_0 (.I0(\dest_graysync_ff[2] [5]), .I1(\dest_graysync_ff[2] [7]), .I2(\dest_graysync_ff[2] [9]), .I3(\dest_graysync_ff[2] [8]), .I4(\dest_graysync_ff[2] [6]), .O(\^dest_out_bin [5])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[6]_INST_0 (.I0(\dest_graysync_ff[2] [6]), .I1(\dest_graysync_ff[2] [8]), .I2(\dest_graysync_ff[2] [9]), .I3(\dest_graysync_ff[2] [7]), .O(\^dest_out_bin [6])); LUT3 #( .INIT(8'h96)) \dest_out_bin[7]_INST_0 (.I0(\dest_graysync_ff[2] [7]), .I1(\dest_graysync_ff[2] [9]), .I2(\dest_graysync_ff[2] [8]), .O(\^dest_out_bin [7])); LUT2 #( .INIT(4'h6)) \dest_out_bin[8]_INST_0 (.I0(\dest_graysync_ff[2] [8]), .I1(\dest_graysync_ff[2] [9]), .O(\^dest_out_bin [8])); LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair180" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); (* SOFT_HLUTNM = "soft_lutpair180" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair179" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); (* SOFT_HLUTNM = "soft_lutpair179" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[4]_i_1 (.I0(src_in_bin[5]), .I1(src_in_bin[4]), .O(gray_enc[4])); (* SOFT_HLUTNM = "soft_lutpair178" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[5]_i_1 (.I0(src_in_bin[6]), .I1(src_in_bin[5]), .O(gray_enc[5])); (* SOFT_HLUTNM = "soft_lutpair178" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[6]_i_1 (.I0(src_in_bin[7]), .I1(src_in_bin[6]), .O(gray_enc[6])); (* SOFT_HLUTNM = "soft_lutpair177" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[7]_i_1 (.I0(src_in_bin[8]), .I1(src_in_bin[7]), .O(gray_enc[7])); (* SOFT_HLUTNM = "soft_lutpair177" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[8]_i_1 (.I0(src_in_bin[9]), .I1(src_in_bin[8]), .O(gray_enc[8])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(gray_enc[4]), .Q(async_path[4]), .R(1'b0)); FDRE \src_gray_ff_reg[5] (.C(src_clk), .CE(1'b1), .D(gray_enc[5]), .Q(async_path[5]), .R(1'b0)); FDRE \src_gray_ff_reg[6] (.C(src_clk), .CE(1'b1), .D(gray_enc[6]), .Q(async_path[6]), .R(1'b0)); FDRE \src_gray_ff_reg[7] (.C(src_clk), .CE(1'b1), .D(gray_enc[7]), .Q(async_path[7]), .R(1'b0)); FDRE \src_gray_ff_reg[8] (.C(src_clk), .CE(1'b1), .D(gray_enc[8]), .Q(async_path[8]), .R(1'b0)); FDRE \src_gray_ff_reg[9] (.C(src_clk), .CE(1'b1), .D(src_in_bin[9]), .Q(async_path[9]), .R(1'b0)); endmodule (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_gray" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "10" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "GRAY" *) module axi_chip2chip_64B66B_xpm_cdc_gray__parameterized3__2 (src_clk, src_in_bin, dest_clk, dest_out_bin); input src_clk; input [9:0]src_in_bin; input dest_clk; output [9:0]dest_out_bin; wire [9:0]async_path; wire dest_clk; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [9:0]\dest_graysync_ff[0] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [9:0]\dest_graysync_ff[1] ; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "GRAY" *) wire [9:0]\dest_graysync_ff[2] ; wire [8:0]\^dest_out_bin ; wire [8:0]gray_enc; wire src_clk; wire [9:0]src_in_bin; assign dest_out_bin[9] = \dest_graysync_ff[2] [9]; assign dest_out_bin[8:0] = \^dest_out_bin [8:0]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][0] (.C(dest_clk), .CE(1'b1), .D(async_path[0]), .Q(\dest_graysync_ff[0] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][1] (.C(dest_clk), .CE(1'b1), .D(async_path[1]), .Q(\dest_graysync_ff[0] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][2] (.C(dest_clk), .CE(1'b1), .D(async_path[2]), .Q(\dest_graysync_ff[0] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][3] (.C(dest_clk), .CE(1'b1), .D(async_path[3]), .Q(\dest_graysync_ff[0] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][4] (.C(dest_clk), .CE(1'b1), .D(async_path[4]), .Q(\dest_graysync_ff[0] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][5] (.C(dest_clk), .CE(1'b1), .D(async_path[5]), .Q(\dest_graysync_ff[0] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][6] (.C(dest_clk), .CE(1'b1), .D(async_path[6]), .Q(\dest_graysync_ff[0] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][7] (.C(dest_clk), .CE(1'b1), .D(async_path[7]), .Q(\dest_graysync_ff[0] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][8] (.C(dest_clk), .CE(1'b1), .D(async_path[8]), .Q(\dest_graysync_ff[0] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[0][9] (.C(dest_clk), .CE(1'b1), .D(async_path[9]), .Q(\dest_graysync_ff[0] [9]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [0]), .Q(\dest_graysync_ff[1] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [1]), .Q(\dest_graysync_ff[1] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [2]), .Q(\dest_graysync_ff[1] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [3]), .Q(\dest_graysync_ff[1] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [4]), .Q(\dest_graysync_ff[1] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [5]), .Q(\dest_graysync_ff[1] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [6]), .Q(\dest_graysync_ff[1] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [7]), .Q(\dest_graysync_ff[1] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [8]), .Q(\dest_graysync_ff[1] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[1][9] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[0] [9]), .Q(\dest_graysync_ff[1] [9]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][0] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [0]), .Q(\dest_graysync_ff[2] [0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][1] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [1]), .Q(\dest_graysync_ff[2] [1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][2] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [2]), .Q(\dest_graysync_ff[2] [2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][3] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [3]), .Q(\dest_graysync_ff[2] [3]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][4] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [4]), .Q(\dest_graysync_ff[2] [4]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][5] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [5]), .Q(\dest_graysync_ff[2] [5]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][6] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [6]), .Q(\dest_graysync_ff[2] [6]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][7] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [7]), .Q(\dest_graysync_ff[2] [7]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][8] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [8]), .Q(\dest_graysync_ff[2] [8]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "GRAY" *) FDRE \dest_graysync_ff_reg[2][9] (.C(dest_clk), .CE(1'b1), .D(\dest_graysync_ff[1] [9]), .Q(\dest_graysync_ff[2] [9]), .R(1'b0)); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[0]_INST_0 (.I0(\dest_graysync_ff[2] [0]), .I1(\dest_graysync_ff[2] [2]), .I2(\^dest_out_bin [4]), .I3(\dest_graysync_ff[2] [3]), .I4(\dest_graysync_ff[2] [1]), .O(\^dest_out_bin [0])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[1]_INST_0 (.I0(\dest_graysync_ff[2] [1]), .I1(\dest_graysync_ff[2] [3]), .I2(\^dest_out_bin [4]), .I3(\dest_graysync_ff[2] [2]), .O(\^dest_out_bin [1])); LUT3 #( .INIT(8'h96)) \dest_out_bin[2]_INST_0 (.I0(\dest_graysync_ff[2] [2]), .I1(\^dest_out_bin [4]), .I2(\dest_graysync_ff[2] [3]), .O(\^dest_out_bin [2])); LUT2 #( .INIT(4'h6)) \dest_out_bin[3]_INST_0 (.I0(\dest_graysync_ff[2] [3]), .I1(\^dest_out_bin [4]), .O(\^dest_out_bin [3])); LUT6 #( .INIT(64'h6996966996696996)) \dest_out_bin[4]_INST_0 (.I0(\dest_graysync_ff[2] [4]), .I1(\dest_graysync_ff[2] [6]), .I2(\dest_graysync_ff[2] [8]), .I3(\dest_graysync_ff[2] [9]), .I4(\dest_graysync_ff[2] [7]), .I5(\dest_graysync_ff[2] [5]), .O(\^dest_out_bin [4])); LUT5 #( .INIT(32'h96696996)) \dest_out_bin[5]_INST_0 (.I0(\dest_graysync_ff[2] [5]), .I1(\dest_graysync_ff[2] [7]), .I2(\dest_graysync_ff[2] [9]), .I3(\dest_graysync_ff[2] [8]), .I4(\dest_graysync_ff[2] [6]), .O(\^dest_out_bin [5])); LUT4 #( .INIT(16'h6996)) \dest_out_bin[6]_INST_0 (.I0(\dest_graysync_ff[2] [6]), .I1(\dest_graysync_ff[2] [8]), .I2(\dest_graysync_ff[2] [9]), .I3(\dest_graysync_ff[2] [7]), .O(\^dest_out_bin [6])); LUT3 #( .INIT(8'h96)) \dest_out_bin[7]_INST_0 (.I0(\dest_graysync_ff[2] [7]), .I1(\dest_graysync_ff[2] [9]), .I2(\dest_graysync_ff[2] [8]), .O(\^dest_out_bin [7])); LUT2 #( .INIT(4'h6)) \dest_out_bin[8]_INST_0 (.I0(\dest_graysync_ff[2] [8]), .I1(\dest_graysync_ff[2] [9]), .O(\^dest_out_bin [8])); LUT2 #( .INIT(4'h6)) \src_gray_ff[0]_i_1 (.I0(src_in_bin[1]), .I1(src_in_bin[0]), .O(gray_enc[0])); (* SOFT_HLUTNM = "soft_lutpair240" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[1]_i_1 (.I0(src_in_bin[2]), .I1(src_in_bin[1]), .O(gray_enc[1])); (* SOFT_HLUTNM = "soft_lutpair240" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[2]_i_1 (.I0(src_in_bin[3]), .I1(src_in_bin[2]), .O(gray_enc[2])); (* SOFT_HLUTNM = "soft_lutpair239" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[3]_i_1 (.I0(src_in_bin[4]), .I1(src_in_bin[3]), .O(gray_enc[3])); (* SOFT_HLUTNM = "soft_lutpair239" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[4]_i_1 (.I0(src_in_bin[5]), .I1(src_in_bin[4]), .O(gray_enc[4])); (* SOFT_HLUTNM = "soft_lutpair238" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[5]_i_1 (.I0(src_in_bin[6]), .I1(src_in_bin[5]), .O(gray_enc[5])); (* SOFT_HLUTNM = "soft_lutpair238" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[6]_i_1 (.I0(src_in_bin[7]), .I1(src_in_bin[6]), .O(gray_enc[6])); (* SOFT_HLUTNM = "soft_lutpair237" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[7]_i_1 (.I0(src_in_bin[8]), .I1(src_in_bin[7]), .O(gray_enc[7])); (* SOFT_HLUTNM = "soft_lutpair237" *) LUT2 #( .INIT(4'h6)) \src_gray_ff[8]_i_1 (.I0(src_in_bin[9]), .I1(src_in_bin[8]), .O(gray_enc[8])); FDRE \src_gray_ff_reg[0] (.C(src_clk), .CE(1'b1), .D(gray_enc[0]), .Q(async_path[0]), .R(1'b0)); FDRE \src_gray_ff_reg[1] (.C(src_clk), .CE(1'b1), .D(gray_enc[1]), .Q(async_path[1]), .R(1'b0)); FDRE \src_gray_ff_reg[2] (.C(src_clk), .CE(1'b1), .D(gray_enc[2]), .Q(async_path[2]), .R(1'b0)); FDRE \src_gray_ff_reg[3] (.C(src_clk), .CE(1'b1), .D(gray_enc[3]), .Q(async_path[3]), .R(1'b0)); FDRE \src_gray_ff_reg[4] (.C(src_clk), .CE(1'b1), .D(gray_enc[4]), .Q(async_path[4]), .R(1'b0)); FDRE \src_gray_ff_reg[5] (.C(src_clk), .CE(1'b1), .D(gray_enc[5]), .Q(async_path[5]), .R(1'b0)); FDRE \src_gray_ff_reg[6] (.C(src_clk), .CE(1'b1), .D(gray_enc[6]), .Q(async_path[6]), .R(1'b0)); FDRE \src_gray_ff_reg[7] (.C(src_clk), .CE(1'b1), .D(gray_enc[7]), .Q(async_path[7]), .R(1'b0)); FDRE \src_gray_ff_reg[8] (.C(src_clk), .CE(1'b1), .D(gray_enc[8]), .Q(async_path[8]), .R(1'b0)); FDRE \src_gray_ff_reg[9] (.C(src_clk), .CE(1'b1), .D(src_in_bin[9]), .Q(async_path[9]), .R(1'b0)); endmodule (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "3" *) (* INIT = "0" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_sync_rst" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "SYNC_RST" *) module axi_chip2chip_64B66B_xpm_cdc_sync_rst (src_rst, dest_clk, dest_rst); input src_rst; input dest_clk; output dest_rst; wire dest_clk; wire src_rst; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SYNC_RST" *) wire [2:0]syncstages_ff; assign dest_rst = syncstages_ff[2]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[0] (.C(dest_clk), .CE(1'b1), .D(src_rst), .Q(syncstages_ff[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[1] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[0]), .Q(syncstages_ff[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[2] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[1]), .Q(syncstages_ff[2]), .R(1'b0)); endmodule (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "3" *) (* INIT = "0" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_sync_rst" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "SYNC_RST" *) module axi_chip2chip_64B66B_xpm_cdc_sync_rst__10 (src_rst, dest_clk, dest_rst); input src_rst; input dest_clk; output dest_rst; wire dest_clk; wire src_rst; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SYNC_RST" *) wire [2:0]syncstages_ff; assign dest_rst = syncstages_ff[2]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[0] (.C(dest_clk), .CE(1'b1), .D(src_rst), .Q(syncstages_ff[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[1] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[0]), .Q(syncstages_ff[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[2] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[1]), .Q(syncstages_ff[2]), .R(1'b0)); endmodule (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "3" *) (* INIT = "0" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_sync_rst" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "SYNC_RST" *) module axi_chip2chip_64B66B_xpm_cdc_sync_rst__11 (src_rst, dest_clk, dest_rst); input src_rst; input dest_clk; output dest_rst; wire dest_clk; wire src_rst; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SYNC_RST" *) wire [2:0]syncstages_ff; assign dest_rst = syncstages_ff[2]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[0] (.C(dest_clk), .CE(1'b1), .D(src_rst), .Q(syncstages_ff[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[1] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[0]), .Q(syncstages_ff[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[2] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[1]), .Q(syncstages_ff[2]), .R(1'b0)); endmodule (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "3" *) (* INIT = "0" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_sync_rst" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "SYNC_RST" *) module axi_chip2chip_64B66B_xpm_cdc_sync_rst__12 (src_rst, dest_clk, dest_rst); input src_rst; input dest_clk; output dest_rst; wire dest_clk; wire src_rst; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SYNC_RST" *) wire [2:0]syncstages_ff; assign dest_rst = syncstages_ff[2]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[0] (.C(dest_clk), .CE(1'b1), .D(src_rst), .Q(syncstages_ff[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[1] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[0]), .Q(syncstages_ff[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[2] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[1]), .Q(syncstages_ff[2]), .R(1'b0)); endmodule (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "3" *) (* INIT = "0" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_sync_rst" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "SYNC_RST" *) module axi_chip2chip_64B66B_xpm_cdc_sync_rst__13 (src_rst, dest_clk, dest_rst); input src_rst; input dest_clk; output dest_rst; wire dest_clk; wire src_rst; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SYNC_RST" *) wire [2:0]syncstages_ff; assign dest_rst = syncstages_ff[2]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[0] (.C(dest_clk), .CE(1'b1), .D(src_rst), .Q(syncstages_ff[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[1] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[0]), .Q(syncstages_ff[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[2] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[1]), .Q(syncstages_ff[2]), .R(1'b0)); endmodule (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "3" *) (* INIT = "0" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_sync_rst" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "SYNC_RST" *) module axi_chip2chip_64B66B_xpm_cdc_sync_rst__14 (src_rst, dest_clk, dest_rst); input src_rst; input dest_clk; output dest_rst; wire dest_clk; wire src_rst; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SYNC_RST" *) wire [2:0]syncstages_ff; assign dest_rst = syncstages_ff[2]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[0] (.C(dest_clk), .CE(1'b1), .D(src_rst), .Q(syncstages_ff[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[1] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[0]), .Q(syncstages_ff[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[2] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[1]), .Q(syncstages_ff[2]), .R(1'b0)); endmodule (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "3" *) (* INIT = "0" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_sync_rst" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "SYNC_RST" *) module axi_chip2chip_64B66B_xpm_cdc_sync_rst__15 (src_rst, dest_clk, dest_rst); input src_rst; input dest_clk; output dest_rst; wire dest_clk; wire src_rst; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SYNC_RST" *) wire [2:0]syncstages_ff; assign dest_rst = syncstages_ff[2]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[0] (.C(dest_clk), .CE(1'b1), .D(src_rst), .Q(syncstages_ff[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[1] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[0]), .Q(syncstages_ff[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[2] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[1]), .Q(syncstages_ff[2]), .R(1'b0)); endmodule (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "3" *) (* INIT = "0" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_sync_rst" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "SYNC_RST" *) module axi_chip2chip_64B66B_xpm_cdc_sync_rst__16 (src_rst, dest_clk, dest_rst); input src_rst; input dest_clk; output dest_rst; wire dest_clk; wire src_rst; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SYNC_RST" *) wire [2:0]syncstages_ff; assign dest_rst = syncstages_ff[2]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[0] (.C(dest_clk), .CE(1'b1), .D(src_rst), .Q(syncstages_ff[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[1] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[0]), .Q(syncstages_ff[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[2] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[1]), .Q(syncstages_ff[2]), .R(1'b0)); endmodule (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "3" *) (* INIT = "0" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_sync_rst" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "SYNC_RST" *) module axi_chip2chip_64B66B_xpm_cdc_sync_rst__17 (src_rst, dest_clk, dest_rst); input src_rst; input dest_clk; output dest_rst; wire dest_clk; wire src_rst; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SYNC_RST" *) wire [2:0]syncstages_ff; assign dest_rst = syncstages_ff[2]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[0] (.C(dest_clk), .CE(1'b1), .D(src_rst), .Q(syncstages_ff[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[1] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[0]), .Q(syncstages_ff[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[2] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[1]), .Q(syncstages_ff[2]), .R(1'b0)); endmodule (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "3" *) (* INIT = "0" *) (* INIT_SYNC_FF = "1" *) (* ORIG_REF_NAME = "xpm_cdc_sync_rst" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "true" *) (* xpm_cdc = "SYNC_RST" *) module axi_chip2chip_64B66B_xpm_cdc_sync_rst__18 (src_rst, dest_clk, dest_rst); input src_rst; input dest_clk; output dest_rst; wire dest_clk; wire src_rst; (* RTL_KEEP = "true" *) (* async_reg = "true" *) (* xpm_cdc = "SYNC_RST" *) wire [2:0]syncstages_ff; assign dest_rst = syncstages_ff[2]; (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[0] (.C(dest_clk), .CE(1'b1), .D(src_rst), .Q(syncstages_ff[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[1] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[0]), .Q(syncstages_ff[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "true" *) (* XPM_CDC = "SYNC_RST" *) FDRE #( .INIT(1'b0)) \syncstages_ff_reg[2] (.C(dest_clk), .CE(1'b1), .D(syncstages_ff[1]), .Q(syncstages_ff[2]), .R(1'b0)); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module axi_chip2chip_64B66B_xpm_counter_updn (Q, src_in_bin, DI, ram_empty_i, rd_en, \count_value_i_reg[0]_0 , \src_gray_ff_reg[0] , SR, rd_clk); output [1:0]Q; output [0:0]src_in_bin; output [1:0]DI; input ram_empty_i; input rd_en; input [1:0]\count_value_i_reg[0]_0 ; input [0:0]\src_gray_ff_reg[0] ; input [0:0]SR; input rd_clk; wire [1:0]DI; wire [1:0]Q; wire [0:0]SR; wire \count_value_i[0]_i_1__2_n_0 ; wire \count_value_i[1]_i_3_n_0 ; wire [1:0]\count_value_i_reg[0]_0 ; wire \gen_fwft.count_en ; wire ram_empty_i; wire rd_clk; wire rd_en; wire [0:0]\src_gray_ff_reg[0] ; wire [0:0]src_in_bin; LUT5 #( .INIT(32'h696A9999)) \count_value_i[0]_i_1__2 (.I0(Q[0]), .I1(ram_empty_i), .I2(rd_en), .I3(\count_value_i_reg[0]_0 [0]), .I4(\count_value_i_reg[0]_0 [1]), .O(\count_value_i[0]_i_1__2_n_0 )); LUT4 #( .INIT(16'h9855)) \count_value_i[1]_i_2 (.I0(ram_empty_i), .I1(rd_en), .I2(\count_value_i_reg[0]_0 [0]), .I3(\count_value_i_reg[0]_0 [1]), .O(\gen_fwft.count_en )); LUT6 #( .INIT(64'h9A9AAAAAA6A666A6)) \count_value_i[1]_i_3 (.I0(Q[1]), .I1(Q[0]), .I2(\count_value_i_reg[0]_0 [1]), .I3(\count_value_i_reg[0]_0 [0]), .I4(rd_en), .I5(ram_empty_i), .O(\count_value_i[1]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(rd_clk), .CE(\gen_fwft.count_en ), .D(\count_value_i[0]_i_1__2_n_0 ), .Q(Q[0]), .R(SR)); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(rd_clk), .CE(\gen_fwft.count_en ), .D(\count_value_i[1]_i_3_n_0 ), .Q(Q[1]), .R(SR)); LUT2 #( .INIT(4'h6)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10 (.I0(Q[0]), .I1(\src_gray_ff_reg[0] ), .O(src_in_bin)); LUT2 #( .INIT(4'hB)) \grdc.rd_data_count_i[7]_i_8 (.I0(Q[0]), .I1(\src_gray_ff_reg[0] ), .O(DI[1])); LUT2 #( .INIT(4'h6)) \grdc.rd_data_count_i[7]_i_9 (.I0(Q[0]), .I1(\src_gray_ff_reg[0] ), .O(DI[0])); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module axi_chip2chip_64B66B_xpm_counter_updn_19 (Q, src_in_bin, S, DI, ram_empty_i, \count_value_i_reg[0]_0 , rd_en, \grdc.rd_data_count_i_reg[7] , \grdc.rd_data_count_i_reg[7]_0 , SR, rd_clk); output [1:0]Q; output [0:0]src_in_bin; output [1:0]S; output [0:0]DI; input ram_empty_i; input [1:0]\count_value_i_reg[0]_0 ; input rd_en; input [1:0]\grdc.rd_data_count_i_reg[7] ; input [1:0]\grdc.rd_data_count_i_reg[7]_0 ; input [0:0]SR; input rd_clk; wire [0:0]DI; wire [1:0]Q; wire [1:0]S; wire [0:0]SR; wire \count_value_i[0]_i_1__3_n_0 ; wire \count_value_i[1]_i_3_n_0 ; wire [1:0]\count_value_i_reg[0]_0 ; wire \gen_fwft.count_en ; wire [1:0]\grdc.rd_data_count_i_reg[7] ; wire [1:0]\grdc.rd_data_count_i_reg[7]_0 ; wire ram_empty_i; wire rd_clk; wire rd_en; wire [0:0]src_in_bin; LUT5 #( .INIT(32'h5AAAA655)) \count_value_i[0]_i_1__3 (.I0(Q[0]), .I1(\count_value_i_reg[0]_0 [0]), .I2(rd_en), .I3(\count_value_i_reg[0]_0 [1]), .I4(ram_empty_i), .O(\count_value_i[0]_i_1__3_n_0 )); LUT4 #( .INIT(16'hC02F)) \count_value_i[1]_i_2 (.I0(\count_value_i_reg[0]_0 [0]), .I1(rd_en), .I2(\count_value_i_reg[0]_0 [1]), .I3(ram_empty_i), .O(\gen_fwft.count_en )); LUT6 #( .INIT(64'hA999A9A96AAA6AAA)) \count_value_i[1]_i_3 (.I0(Q[1]), .I1(ram_empty_i), .I2(\count_value_i_reg[0]_0 [1]), .I3(rd_en), .I4(\count_value_i_reg[0]_0 [0]), .I5(Q[0]), .O(\count_value_i[1]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(rd_clk), .CE(\gen_fwft.count_en ), .D(\count_value_i[0]_i_1__3_n_0 ), .Q(Q[0]), .R(SR)); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(rd_clk), .CE(\gen_fwft.count_en ), .D(\count_value_i[1]_i_3_n_0 ), .Q(Q[1]), .R(SR)); LUT4 #( .INIT(16'h2DD2)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_8 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .I2(Q[1]), .I3(\grdc.rd_data_count_i_reg[7] [1]), .O(src_in_bin)); LUT4 #( .INIT(16'h9669)) \grdc.rd_data_count_i[7]_i_15 (.I0(DI), .I1(Q[1]), .I2(\grdc.rd_data_count_i_reg[7] [1]), .I3(\grdc.rd_data_count_i_reg[7]_0 [1]), .O(S[1])); (* HLUTNM = "lutpair2" *) LUT3 #( .INIT(8'h96)) \grdc.rd_data_count_i[7]_i_16 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .I2(\grdc.rd_data_count_i_reg[7]_0 [0]), .O(S[0])); (* HLUTNM = "lutpair2" *) LUT2 #( .INIT(4'hB)) \grdc.rd_data_count_i[7]_i_8 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .O(DI)); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module axi_chip2chip_64B66B_xpm_counter_updn_27 (Q, src_in_bin, S, DI, ram_empty_i, \count_value_i_reg[0]_0 , rd_en, \grdc.rd_data_count_i_reg[7] , \grdc.rd_data_count_i_reg[7]_0 , SR, rd_clk); output [1:0]Q; output [0:0]src_in_bin; output [1:0]S; output [0:0]DI; input ram_empty_i; input [1:0]\count_value_i_reg[0]_0 ; input rd_en; input [1:0]\grdc.rd_data_count_i_reg[7] ; input [1:0]\grdc.rd_data_count_i_reg[7]_0 ; input [0:0]SR; input rd_clk; wire [0:0]DI; wire [1:0]Q; wire [1:0]S; wire [0:0]SR; wire \count_value_i[0]_i_1__3_n_0 ; wire \count_value_i[1]_i_3_n_0 ; wire [1:0]\count_value_i_reg[0]_0 ; wire \gen_fwft.count_en ; wire [1:0]\grdc.rd_data_count_i_reg[7] ; wire [1:0]\grdc.rd_data_count_i_reg[7]_0 ; wire ram_empty_i; wire rd_clk; wire rd_en; wire [0:0]src_in_bin; LUT5 #( .INIT(32'h5AAAA655)) \count_value_i[0]_i_1__3 (.I0(Q[0]), .I1(\count_value_i_reg[0]_0 [0]), .I2(rd_en), .I3(\count_value_i_reg[0]_0 [1]), .I4(ram_empty_i), .O(\count_value_i[0]_i_1__3_n_0 )); LUT4 #( .INIT(16'hC02F)) \count_value_i[1]_i_2 (.I0(\count_value_i_reg[0]_0 [0]), .I1(rd_en), .I2(\count_value_i_reg[0]_0 [1]), .I3(ram_empty_i), .O(\gen_fwft.count_en )); LUT6 #( .INIT(64'hA999A9A96AAA6AAA)) \count_value_i[1]_i_3 (.I0(Q[1]), .I1(ram_empty_i), .I2(\count_value_i_reg[0]_0 [1]), .I3(rd_en), .I4(\count_value_i_reg[0]_0 [0]), .I5(Q[0]), .O(\count_value_i[1]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(rd_clk), .CE(\gen_fwft.count_en ), .D(\count_value_i[0]_i_1__3_n_0 ), .Q(Q[0]), .R(SR)); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(rd_clk), .CE(\gen_fwft.count_en ), .D(\count_value_i[1]_i_3_n_0 ), .Q(Q[1]), .R(SR)); LUT4 #( .INIT(16'h2DD2)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_8 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .I2(Q[1]), .I3(\grdc.rd_data_count_i_reg[7] [1]), .O(src_in_bin)); LUT4 #( .INIT(16'h9669)) \grdc.rd_data_count_i[7]_i_15 (.I0(DI), .I1(Q[1]), .I2(\grdc.rd_data_count_i_reg[7] [1]), .I3(\grdc.rd_data_count_i_reg[7]_0 [1]), .O(S[1])); (* HLUTNM = "lutpair0" *) LUT3 #( .INIT(8'h96)) \grdc.rd_data_count_i[7]_i_16 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .I2(\grdc.rd_data_count_i_reg[7]_0 [0]), .O(S[0])); (* HLUTNM = "lutpair0" *) LUT2 #( .INIT(4'hB)) \grdc.rd_data_count_i[7]_i_8 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .O(DI)); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module axi_chip2chip_64B66B_xpm_counter_updn_38 (Q, src_in_bin, S, DI, ram_empty_i, \count_value_i_reg[0]_0 , rd_en, \grdc.rd_data_count_i_reg[7] , \grdc.rd_data_count_i_reg[7]_0 , SR, rd_clk); output [1:0]Q; output [0:0]src_in_bin; output [1:0]S; output [0:0]DI; input ram_empty_i; input [1:0]\count_value_i_reg[0]_0 ; input rd_en; input [1:0]\grdc.rd_data_count_i_reg[7] ; input [1:0]\grdc.rd_data_count_i_reg[7]_0 ; input [0:0]SR; input rd_clk; wire [0:0]DI; wire [1:0]Q; wire [1:0]S; wire [0:0]SR; wire \count_value_i[0]_i_1__3_n_0 ; wire \count_value_i[1]_i_3_n_0 ; wire [1:0]\count_value_i_reg[0]_0 ; wire \gen_fwft.count_en ; wire [1:0]\grdc.rd_data_count_i_reg[7] ; wire [1:0]\grdc.rd_data_count_i_reg[7]_0 ; wire ram_empty_i; wire rd_clk; wire rd_en; wire [0:0]src_in_bin; LUT5 #( .INIT(32'h5AAAA655)) \count_value_i[0]_i_1__3 (.I0(Q[0]), .I1(\count_value_i_reg[0]_0 [0]), .I2(rd_en), .I3(\count_value_i_reg[0]_0 [1]), .I4(ram_empty_i), .O(\count_value_i[0]_i_1__3_n_0 )); LUT4 #( .INIT(16'hC02F)) \count_value_i[1]_i_2 (.I0(\count_value_i_reg[0]_0 [0]), .I1(rd_en), .I2(\count_value_i_reg[0]_0 [1]), .I3(ram_empty_i), .O(\gen_fwft.count_en )); LUT6 #( .INIT(64'hA999A9A96AAA6AAA)) \count_value_i[1]_i_3 (.I0(Q[1]), .I1(ram_empty_i), .I2(\count_value_i_reg[0]_0 [1]), .I3(rd_en), .I4(\count_value_i_reg[0]_0 [0]), .I5(Q[0]), .O(\count_value_i[1]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(rd_clk), .CE(\gen_fwft.count_en ), .D(\count_value_i[0]_i_1__3_n_0 ), .Q(Q[0]), .R(SR)); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(rd_clk), .CE(\gen_fwft.count_en ), .D(\count_value_i[1]_i_3_n_0 ), .Q(Q[1]), .R(SR)); LUT4 #( .INIT(16'h2DD2)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_8 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .I2(Q[1]), .I3(\grdc.rd_data_count_i_reg[7] [1]), .O(src_in_bin)); LUT4 #( .INIT(16'h9669)) \grdc.rd_data_count_i[7]_i_15 (.I0(DI), .I1(Q[1]), .I2(\grdc.rd_data_count_i_reg[7] [1]), .I3(\grdc.rd_data_count_i_reg[7]_0 [1]), .O(S[1])); (* HLUTNM = "lutpair1" *) LUT3 #( .INIT(8'h96)) \grdc.rd_data_count_i[7]_i_16 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .I2(\grdc.rd_data_count_i_reg[7]_0 [0]), .O(S[0])); (* HLUTNM = "lutpair1" *) LUT2 #( .INIT(4'hB)) \grdc.rd_data_count_i[7]_i_8 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .O(DI)); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module axi_chip2chip_64B66B_xpm_counter_updn_8 (Q, src_in_bin, DI, ram_empty_i, rd_en, \count_value_i_reg[0]_0 , \src_gray_ff_reg[0] , SR, rd_clk); output [1:0]Q; output [0:0]src_in_bin; output [1:0]DI; input ram_empty_i; input rd_en; input [1:0]\count_value_i_reg[0]_0 ; input [0:0]\src_gray_ff_reg[0] ; input [0:0]SR; input rd_clk; wire [1:0]DI; wire [1:0]Q; wire [0:0]SR; wire \count_value_i[0]_i_1__2_n_0 ; wire \count_value_i[1]_i_3_n_0 ; wire [1:0]\count_value_i_reg[0]_0 ; wire \gen_fwft.count_en ; wire ram_empty_i; wire rd_clk; wire rd_en; wire [0:0]\src_gray_ff_reg[0] ; wire [0:0]src_in_bin; LUT5 #( .INIT(32'h696A9999)) \count_value_i[0]_i_1__2 (.I0(Q[0]), .I1(ram_empty_i), .I2(rd_en), .I3(\count_value_i_reg[0]_0 [0]), .I4(\count_value_i_reg[0]_0 [1]), .O(\count_value_i[0]_i_1__2_n_0 )); LUT4 #( .INIT(16'h9855)) \count_value_i[1]_i_2 (.I0(ram_empty_i), .I1(rd_en), .I2(\count_value_i_reg[0]_0 [0]), .I3(\count_value_i_reg[0]_0 [1]), .O(\gen_fwft.count_en )); LUT6 #( .INIT(64'h9A9AAAAAA6A666A6)) \count_value_i[1]_i_3 (.I0(Q[1]), .I1(Q[0]), .I2(\count_value_i_reg[0]_0 [1]), .I3(\count_value_i_reg[0]_0 [0]), .I4(rd_en), .I5(ram_empty_i), .O(\count_value_i[1]_i_3_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(rd_clk), .CE(\gen_fwft.count_en ), .D(\count_value_i[0]_i_1__2_n_0 ), .Q(Q[0]), .R(SR)); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(rd_clk), .CE(\gen_fwft.count_en ), .D(\count_value_i[1]_i_3_n_0 ), .Q(Q[1]), .R(SR)); LUT2 #( .INIT(4'h6)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10 (.I0(Q[0]), .I1(\src_gray_ff_reg[0] ), .O(src_in_bin)); LUT2 #( .INIT(4'hB)) \grdc.rd_data_count_i[7]_i_8 (.I0(Q[0]), .I1(\src_gray_ff_reg[0] ), .O(DI[1])); LUT2 #( .INIT(4'h6)) \grdc.rd_data_count_i[7]_i_9 (.I0(Q[0]), .I1(\src_gray_ff_reg[0] ), .O(DI[0])); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module axi_chip2chip_64B66B_xpm_counter_updn__parameterized0 (Q, enb, DI, \count_value_i_reg[7]_0 , D, S, src_in_bin, \count_value_i_reg[0]_0 , rd_en, ram_empty_i, \grdc.rd_data_count_i_reg[7] , \grdc.rd_data_count_i_reg[8] , \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] , \count_value_i_reg[8]_0 , rd_clk); output [7:0]Q; output enb; output [0:0]DI; output [0:0]\count_value_i_reg[7]_0 ; output [7:0]D; output [4:0]S; output [7:0]src_in_bin; input [1:0]\count_value_i_reg[0]_0 ; input rd_en; input ram_empty_i; input [1:0]\grdc.rd_data_count_i_reg[7] ; input [7:0]\grdc.rd_data_count_i_reg[8] ; input [7:0]\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] ; input \count_value_i_reg[8]_0 ; input rd_clk; wire [7:0]D; wire [0:0]DI; wire [7:0]Q; wire [4:0]S; wire \count_value_i[0]_i_1__4_n_0 ; wire \count_value_i[1]_i_1__3_n_0 ; wire \count_value_i[2]_i_1__3_n_0 ; wire \count_value_i[3]_i_1__3_n_0 ; wire \count_value_i[4]_i_1__3_n_0 ; wire \count_value_i[5]_i_1__2_n_0 ; wire \count_value_i[6]_i_1__2_n_0 ; wire \count_value_i[6]_i_2__2_n_0 ; wire \count_value_i[7]_i_1__2_n_0 ; wire \count_value_i[8]_i_1__0_n_0 ; wire \count_value_i[8]_i_2__0_n_0 ; wire [1:0]\count_value_i_reg[0]_0 ; wire [0:0]\count_value_i_reg[7]_0 ; wire \count_value_i_reg[8]_0 ; wire \count_value_i_reg_n_0_[8] ; wire enb; wire \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ; wire \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_11_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_12_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_13_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_14_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_15_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_16_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9_n_0 ; wire [7:0]\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_1 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_2 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_3 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_4 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_5 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_6 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_7 ; wire [1:0]\grdc.rd_data_count_i_reg[7] ; wire [7:0]\grdc.rd_data_count_i_reg[8] ; wire ram_empty_i; wire rd_clk; wire rd_en; wire [7:0]src_in_bin; wire [7:7]\NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_CO_UNCONNECTED ; LUT5 #( .INIT(32'hABAA5455)) \count_value_i[0]_i_1__4 (.I0(ram_empty_i), .I1(rd_en), .I2(\count_value_i_reg[0]_0 [0]), .I3(\count_value_i_reg[0]_0 [1]), .I4(Q[0]), .O(\count_value_i[0]_i_1__4_n_0 )); LUT5 #( .INIT(32'h02FFFD00)) \count_value_i[1]_i_1__3 (.I0(\count_value_i_reg[0]_0 [1]), .I1(\count_value_i_reg[0]_0 [0]), .I2(rd_en), .I3(Q[0]), .I4(Q[1]), .O(\count_value_i[1]_i_1__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair144" *) LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1__3 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair145" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1__3 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair145" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1__3 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1__3_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1__2 (.I0(Q[3]), .I1(\count_value_i[6]_i_2__2_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1__2_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1__2 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2__2_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1__2_n_0 )); LUT6 #( .INIT(64'h0000AAA200000000)) \count_value_i[6]_i_2__2 (.I0(Q[1]), .I1(\count_value_i_reg[0]_0 [1]), .I2(\count_value_i_reg[0]_0 [0]), .I3(rd_en), .I4(ram_empty_i), .I5(Q[0]), .O(\count_value_i[6]_i_2__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair142" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1__2 (.I0(Q[5]), .I1(\count_value_i[8]_i_2__0_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair142" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[8]_i_1__0 (.I0(Q[6]), .I1(\count_value_i[8]_i_2__0_n_0 ), .I2(Q[5]), .I3(Q[7]), .I4(\count_value_i_reg_n_0_[8] ), .O(\count_value_i[8]_i_1__0_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[8]_i_2__0 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(enb), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[8]_i_2__0_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(rd_clk), .CE(enb), .D(\count_value_i[0]_i_1__4_n_0 ), .Q(Q[0]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(rd_clk), .CE(enb), .D(\count_value_i[1]_i_1__3_n_0 ), .Q(Q[1]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(rd_clk), .CE(enb), .D(\count_value_i[2]_i_1__3_n_0 ), .Q(Q[2]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(rd_clk), .CE(enb), .D(\count_value_i[3]_i_1__3_n_0 ), .Q(Q[3]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(rd_clk), .CE(enb), .D(\count_value_i[4]_i_1__3_n_0 ), .Q(Q[4]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(rd_clk), .CE(enb), .D(\count_value_i[5]_i_1__2_n_0 ), .Q(Q[5]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(rd_clk), .CE(enb), .D(\count_value_i[6]_i_1__2_n_0 ), .Q(Q[6]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(rd_clk), .CE(enb), .D(\count_value_i[7]_i_1__2_n_0 ), .Q(Q[7]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[8] (.C(rd_clk), .CE(enb), .D(\count_value_i[8]_i_1__0_n_0 ), .Q(\count_value_i_reg_n_0_[8] ), .R(\count_value_i_reg[8]_0 )); LUT6 #( .INIT(64'hFFFFFFFE00000001)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_1 (.I0(Q[7]), .I1(Q[5]), .I2(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ), .I3(Q[4]), .I4(Q[6]), .I5(\count_value_i_reg_n_0_[8] ), .O(src_in_bin[7])); LUT6 #( .INIT(64'hFFFFFFFFFBFBBAFB)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10 (.I0(Q[2]), .I1(\grdc.rd_data_count_i_reg[7] [1]), .I2(Q[1]), .I3(\grdc.rd_data_count_i_reg[7] [0]), .I4(Q[0]), .I5(Q[3]), .O(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 )); (* SOFT_HLUTNM = "soft_lutpair146" *) LUT2 #( .INIT(4'hB)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .O(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0 )); (* SOFT_HLUTNM = "soft_lutpair143" *) LUT5 #( .INIT(32'hFFFE0001)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_2 (.I0(Q[6]), .I1(Q[4]), .I2(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ), .I3(Q[5]), .I4(Q[7]), .O(src_in_bin[6])); (* SOFT_HLUTNM = "soft_lutpair143" *) LUT4 #( .INIT(16'hFE01)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_3 (.I0(Q[5]), .I1(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ), .I2(Q[4]), .I3(Q[6]), .O(src_in_bin[5])); LUT3 #( .INIT(8'hE1)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_4 (.I0(Q[4]), .I1(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ), .I2(Q[5]), .O(src_in_bin[4])); LUT6 #( .INIT(64'hFFFFEAFE00001501)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_5 (.I0(Q[3]), .I1(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0 ), .I2(Q[1]), .I3(\grdc.rd_data_count_i_reg[7] [1]), .I4(Q[2]), .I5(Q[4]), .O(src_in_bin[3])); LUT6 #( .INIT(64'hFBFBBAFB04044504)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_6 (.I0(Q[2]), .I1(\grdc.rd_data_count_i_reg[7] [1]), .I2(Q[1]), .I3(\grdc.rd_data_count_i_reg[7] [0]), .I4(Q[0]), .I5(Q[3]), .O(src_in_bin[2])); (* SOFT_HLUTNM = "soft_lutpair144" *) LUT5 #( .INIT(32'hB0FB4F04)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_7 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .I2(Q[1]), .I3(\grdc.rd_data_count_i_reg[7] [1]), .I4(Q[2]), .O(src_in_bin[1])); (* SOFT_HLUTNM = "soft_lutpair146" *) LUT2 #( .INIT(4'h6)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_9 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .O(src_in_bin[0])); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10 (.I0(Q[6]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [6]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_11 (.I0(Q[5]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [5]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_12 (.I0(Q[4]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [4]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_12_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_13 (.I0(Q[3]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [3]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_13_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_14 (.I0(Q[2]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [2]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_14_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_15 (.I0(Q[1]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [1]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_15_n_0 )); LUT5 #( .INIT(32'hABAA5455)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_16 (.I0(ram_empty_i), .I1(rd_en), .I2(\count_value_i_reg[0]_0 [0]), .I3(\count_value_i_reg[0]_0 [1]), .I4(Q[0]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_16_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2 (.I0(Q[6]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3 (.I0(Q[5]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4 (.I0(Q[4]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5 (.I0(Q[3]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6 (.I0(Q[2]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7 (.I0(Q[1]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8 (.I0(Q[0]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9 (.I0(Q[7]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [7]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9_n_0 )); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY8 \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1 (.CI(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [0]), .CI_TOP(1'b0), .CO({\NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_CO_UNCONNECTED [7],\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_1 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_2 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_3 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_4 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_5 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_6 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_7 }), .DI({1'b0,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8_n_0 }), .O(D), .S({\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_11_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_12_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_13_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_14_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_15_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_16_n_0 })); LUT4 #( .INIT(16'h00FD)) \gen_sdpram.xpm_memory_base_inst_i_2 (.I0(\count_value_i_reg[0]_0 [1]), .I1(\count_value_i_reg[0]_0 [0]), .I2(rd_en), .I3(ram_empty_i), .O(enb)); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_10 (.I0(Q[5]), .I1(\grdc.rd_data_count_i_reg[8] [4]), .I2(Q[6]), .I3(\grdc.rd_data_count_i_reg[8] [5]), .O(S[3])); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_11 (.I0(Q[4]), .I1(\grdc.rd_data_count_i_reg[8] [3]), .I2(Q[5]), .I3(\grdc.rd_data_count_i_reg[8] [4]), .O(S[2])); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_12 (.I0(Q[3]), .I1(\grdc.rd_data_count_i_reg[8] [2]), .I2(Q[4]), .I3(\grdc.rd_data_count_i_reg[8] [3]), .O(S[1])); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_13 (.I0(Q[2]), .I1(\grdc.rd_data_count_i_reg[8] [1]), .I2(Q[3]), .I3(\grdc.rd_data_count_i_reg[8] [2]), .O(S[0])); LUT3 #( .INIT(8'hD4)) \grdc.rd_data_count_i[7]_i_7 (.I0(Q[1]), .I1(\grdc.rd_data_count_i_reg[7] [1]), .I2(\grdc.rd_data_count_i_reg[8] [0]), .O(DI)); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_9 (.I0(Q[6]), .I1(\grdc.rd_data_count_i_reg[8] [5]), .I2(Q[7]), .I3(\grdc.rd_data_count_i_reg[8] [6]), .O(S[4])); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[8]_i_3 (.I0(Q[7]), .I1(\grdc.rd_data_count_i_reg[8] [6]), .I2(\count_value_i_reg_n_0_[8] ), .I3(\grdc.rd_data_count_i_reg[8] [7]), .O(\count_value_i_reg[7]_0 )); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module axi_chip2chip_64B66B_xpm_counter_updn__parameterized0_21 (Q, D, wr_pntr_plus1_pf_carry, wr_en, \count_value_i_reg[6]_0 , wrst_busy, rst_d1, \gwdc.wr_data_count_i_reg[8] , wr_clk); output [8:0]Q; output [7:0]D; input wr_pntr_plus1_pf_carry; input wr_en; input \count_value_i_reg[6]_0 ; input wrst_busy; input rst_d1; input [8:0]\gwdc.wr_data_count_i_reg[8] ; input wr_clk; wire [7:0]D; wire [8:0]Q; wire \count_value_i[0]_i_1__1_n_0 ; wire \count_value_i[1]_i_1__1_n_0 ; wire \count_value_i[2]_i_1__1_n_0 ; wire \count_value_i[3]_i_1__1_n_0 ; wire \count_value_i[4]_i_1__1_n_0 ; wire \count_value_i[5]_i_1__1_n_0 ; wire \count_value_i[6]_i_1__1_n_0 ; wire \count_value_i[6]_i_2__1_n_0 ; wire \count_value_i[7]_i_1__1_n_0 ; wire \count_value_i[8]_i_1_n_0 ; wire \count_value_i[8]_i_2_n_0 ; wire \count_value_i_reg[6]_0 ; wire \gwdc.wr_data_count_i[7]_i_2_n_0 ; wire \gwdc.wr_data_count_i[7]_i_3_n_0 ; wire \gwdc.wr_data_count_i[7]_i_4_n_0 ; wire \gwdc.wr_data_count_i[7]_i_5_n_0 ; wire \gwdc.wr_data_count_i[7]_i_6_n_0 ; wire \gwdc.wr_data_count_i[7]_i_7_n_0 ; wire \gwdc.wr_data_count_i[7]_i_8_n_0 ; wire \gwdc.wr_data_count_i[7]_i_9_n_0 ; wire \gwdc.wr_data_count_i[8]_i_2_n_0 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_0 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_1 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_2 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_3 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_4 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_5 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_6 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_7 ; wire [8:0]\gwdc.wr_data_count_i_reg[8] ; wire rst_d1; wire wr_clk; wire wr_en; wire wr_pntr_plus1_pf_carry; wire wrst_busy; wire [0:0]\NLW_gwdc.wr_data_count_i_reg[7]_i_1_O_UNCONNECTED ; wire [7:0]\NLW_gwdc.wr_data_count_i_reg[8]_i_1_CO_UNCONNECTED ; wire [7:1]\NLW_gwdc.wr_data_count_i_reg[8]_i_1_O_UNCONNECTED ; LUT1 #( .INIT(2'h1)) \count_value_i[0]_i_1__1 (.I0(Q[0]), .O(\count_value_i[0]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair151" *) LUT2 #( .INIT(4'h6)) \count_value_i[1]_i_1__1 (.I0(Q[0]), .I1(Q[1]), .O(\count_value_i[1]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair151" *) LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1__1 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair150" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1__1 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair150" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1__1 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1__1_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1__1 (.I0(Q[3]), .I1(\count_value_i[6]_i_2__1_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1__1_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1__1 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2__1_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1__1_n_0 )); LUT6 #( .INIT(64'h0000000800000000)) \count_value_i[6]_i_2__1 (.I0(Q[1]), .I1(wr_en), .I2(\count_value_i_reg[6]_0 ), .I3(wrst_busy), .I4(rst_d1), .I5(Q[0]), .O(\count_value_i[6]_i_2__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair149" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1__1 (.I0(Q[5]), .I1(\count_value_i[8]_i_2_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair149" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[8]_i_1 (.I0(Q[6]), .I1(\count_value_i[8]_i_2_n_0 ), .I2(Q[5]), .I3(Q[7]), .I4(Q[8]), .O(\count_value_i[8]_i_1_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[8]_i_2 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(wr_pntr_plus1_pf_carry), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[8]_i_2_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[0]_i_1__1_n_0 ), .Q(Q[0]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[1]_i_1__1_n_0 ), .Q(Q[1]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[2]_i_1__1_n_0 ), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[3]_i_1__1_n_0 ), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[4]_i_1__1_n_0 ), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[5]_i_1__1_n_0 ), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[6]_i_1__1_n_0 ), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[7]_i_1__1_n_0 ), .Q(Q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[8] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[8]_i_1_n_0 ), .Q(Q[8]), .R(wrst_busy)); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_2 (.I0(Q[7]), .I1(\gwdc.wr_data_count_i_reg[8] [7]), .O(\gwdc.wr_data_count_i[7]_i_2_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_3 (.I0(Q[6]), .I1(\gwdc.wr_data_count_i_reg[8] [6]), .O(\gwdc.wr_data_count_i[7]_i_3_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_4 (.I0(Q[5]), .I1(\gwdc.wr_data_count_i_reg[8] [5]), .O(\gwdc.wr_data_count_i[7]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_5 (.I0(Q[4]), .I1(\gwdc.wr_data_count_i_reg[8] [4]), .O(\gwdc.wr_data_count_i[7]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_6 (.I0(Q[3]), .I1(\gwdc.wr_data_count_i_reg[8] [3]), .O(\gwdc.wr_data_count_i[7]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_7 (.I0(Q[2]), .I1(\gwdc.wr_data_count_i_reg[8] [2]), .O(\gwdc.wr_data_count_i[7]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_8 (.I0(Q[1]), .I1(\gwdc.wr_data_count_i_reg[8] [1]), .O(\gwdc.wr_data_count_i[7]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_9 (.I0(Q[0]), .I1(\gwdc.wr_data_count_i_reg[8] [0]), .O(\gwdc.wr_data_count_i[7]_i_9_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[8]_i_2 (.I0(Q[8]), .I1(\gwdc.wr_data_count_i_reg[8] [8]), .O(\gwdc.wr_data_count_i[8]_i_2_n_0 )); (* ADDER_THRESHOLD = "35" *) CARRY8 \gwdc.wr_data_count_i_reg[7]_i_1 (.CI(1'b1), .CI_TOP(1'b0), .CO({\gwdc.wr_data_count_i_reg[7]_i_1_n_0 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_1 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_2 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_3 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_4 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_5 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_6 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_7 }), .DI(Q[7:0]), .O({D[6:0],\NLW_gwdc.wr_data_count_i_reg[7]_i_1_O_UNCONNECTED [0]}), .S({\gwdc.wr_data_count_i[7]_i_2_n_0 ,\gwdc.wr_data_count_i[7]_i_3_n_0 ,\gwdc.wr_data_count_i[7]_i_4_n_0 ,\gwdc.wr_data_count_i[7]_i_5_n_0 ,\gwdc.wr_data_count_i[7]_i_6_n_0 ,\gwdc.wr_data_count_i[7]_i_7_n_0 ,\gwdc.wr_data_count_i[7]_i_8_n_0 ,\gwdc.wr_data_count_i[7]_i_9_n_0 })); (* ADDER_THRESHOLD = "35" *) CARRY8 \gwdc.wr_data_count_i_reg[8]_i_1 (.CI(\gwdc.wr_data_count_i_reg[7]_i_1_n_0 ), .CI_TOP(1'b0), .CO(\NLW_gwdc.wr_data_count_i_reg[8]_i_1_CO_UNCONNECTED [7:0]), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .O({\NLW_gwdc.wr_data_count_i_reg[8]_i_1_O_UNCONNECTED [7:1],D[7]}), .S({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\gwdc.wr_data_count_i[8]_i_2_n_0 })); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module axi_chip2chip_64B66B_xpm_counter_updn__parameterized0_28 (Q, enb, DI, \count_value_i_reg[7]_0 , D, S, src_in_bin, \count_value_i_reg[0]_0 , rd_en, ram_empty_i, \grdc.rd_data_count_i_reg[7] , \grdc.rd_data_count_i_reg[8] , \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] , \count_value_i_reg[8]_0 , rd_clk); output [7:0]Q; output enb; output [0:0]DI; output [0:0]\count_value_i_reg[7]_0 ; output [7:0]D; output [4:0]S; output [7:0]src_in_bin; input [1:0]\count_value_i_reg[0]_0 ; input rd_en; input ram_empty_i; input [1:0]\grdc.rd_data_count_i_reg[7] ; input [7:0]\grdc.rd_data_count_i_reg[8] ; input [7:0]\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] ; input \count_value_i_reg[8]_0 ; input rd_clk; wire [7:0]D; wire [0:0]DI; wire [7:0]Q; wire [4:0]S; wire \count_value_i[0]_i_1__4_n_0 ; wire \count_value_i[1]_i_1__3_n_0 ; wire \count_value_i[2]_i_1__3_n_0 ; wire \count_value_i[3]_i_1__3_n_0 ; wire \count_value_i[4]_i_1__3_n_0 ; wire \count_value_i[5]_i_1__2_n_0 ; wire \count_value_i[6]_i_1__2_n_0 ; wire \count_value_i[6]_i_2__2_n_0 ; wire \count_value_i[7]_i_1__2_n_0 ; wire \count_value_i[8]_i_1__0_n_0 ; wire \count_value_i[8]_i_2__0_n_0 ; wire [1:0]\count_value_i_reg[0]_0 ; wire [0:0]\count_value_i_reg[7]_0 ; wire \count_value_i_reg[8]_0 ; wire \count_value_i_reg_n_0_[8] ; wire enb; wire \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ; wire \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_11_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_12_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_13_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_14_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_15_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_16_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9_n_0 ; wire [7:0]\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_1 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_2 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_3 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_4 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_5 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_6 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_7 ; wire [1:0]\grdc.rd_data_count_i_reg[7] ; wire [7:0]\grdc.rd_data_count_i_reg[8] ; wire ram_empty_i; wire rd_clk; wire rd_en; wire [7:0]src_in_bin; wire [7:7]\NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_CO_UNCONNECTED ; LUT5 #( .INIT(32'hABAA5455)) \count_value_i[0]_i_1__4 (.I0(ram_empty_i), .I1(rd_en), .I2(\count_value_i_reg[0]_0 [0]), .I3(\count_value_i_reg[0]_0 [1]), .I4(Q[0]), .O(\count_value_i[0]_i_1__4_n_0 )); LUT5 #( .INIT(32'h02FFFD00)) \count_value_i[1]_i_1__3 (.I0(\count_value_i_reg[0]_0 [1]), .I1(\count_value_i_reg[0]_0 [0]), .I2(rd_en), .I3(Q[0]), .I4(Q[1]), .O(\count_value_i[1]_i_1__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair111" *) LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1__3 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair112" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1__3 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair112" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1__3 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1__3_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1__2 (.I0(Q[3]), .I1(\count_value_i[6]_i_2__2_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1__2_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1__2 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2__2_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1__2_n_0 )); LUT6 #( .INIT(64'h0000AAA200000000)) \count_value_i[6]_i_2__2 (.I0(Q[1]), .I1(\count_value_i_reg[0]_0 [1]), .I2(\count_value_i_reg[0]_0 [0]), .I3(rd_en), .I4(ram_empty_i), .I5(Q[0]), .O(\count_value_i[6]_i_2__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair109" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1__2 (.I0(Q[5]), .I1(\count_value_i[8]_i_2__0_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair109" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[8]_i_1__0 (.I0(Q[6]), .I1(\count_value_i[8]_i_2__0_n_0 ), .I2(Q[5]), .I3(Q[7]), .I4(\count_value_i_reg_n_0_[8] ), .O(\count_value_i[8]_i_1__0_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[8]_i_2__0 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(enb), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[8]_i_2__0_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(rd_clk), .CE(enb), .D(\count_value_i[0]_i_1__4_n_0 ), .Q(Q[0]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(rd_clk), .CE(enb), .D(\count_value_i[1]_i_1__3_n_0 ), .Q(Q[1]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(rd_clk), .CE(enb), .D(\count_value_i[2]_i_1__3_n_0 ), .Q(Q[2]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(rd_clk), .CE(enb), .D(\count_value_i[3]_i_1__3_n_0 ), .Q(Q[3]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(rd_clk), .CE(enb), .D(\count_value_i[4]_i_1__3_n_0 ), .Q(Q[4]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(rd_clk), .CE(enb), .D(\count_value_i[5]_i_1__2_n_0 ), .Q(Q[5]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(rd_clk), .CE(enb), .D(\count_value_i[6]_i_1__2_n_0 ), .Q(Q[6]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(rd_clk), .CE(enb), .D(\count_value_i[7]_i_1__2_n_0 ), .Q(Q[7]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[8] (.C(rd_clk), .CE(enb), .D(\count_value_i[8]_i_1__0_n_0 ), .Q(\count_value_i_reg_n_0_[8] ), .R(\count_value_i_reg[8]_0 )); LUT6 #( .INIT(64'hFFFFFFFE00000001)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_1 (.I0(Q[7]), .I1(Q[5]), .I2(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ), .I3(Q[4]), .I4(Q[6]), .I5(\count_value_i_reg_n_0_[8] ), .O(src_in_bin[7])); LUT6 #( .INIT(64'hFFFFFFFFFBFBBAFB)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10 (.I0(Q[2]), .I1(\grdc.rd_data_count_i_reg[7] [1]), .I2(Q[1]), .I3(\grdc.rd_data_count_i_reg[7] [0]), .I4(Q[0]), .I5(Q[3]), .O(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 )); (* SOFT_HLUTNM = "soft_lutpair113" *) LUT2 #( .INIT(4'hB)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .O(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0 )); (* SOFT_HLUTNM = "soft_lutpair110" *) LUT5 #( .INIT(32'hFFFE0001)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_2 (.I0(Q[6]), .I1(Q[4]), .I2(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ), .I3(Q[5]), .I4(Q[7]), .O(src_in_bin[6])); (* SOFT_HLUTNM = "soft_lutpair110" *) LUT4 #( .INIT(16'hFE01)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_3 (.I0(Q[5]), .I1(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ), .I2(Q[4]), .I3(Q[6]), .O(src_in_bin[5])); LUT3 #( .INIT(8'hE1)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_4 (.I0(Q[4]), .I1(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ), .I2(Q[5]), .O(src_in_bin[4])); LUT6 #( .INIT(64'hFFFFEAFE00001501)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_5 (.I0(Q[3]), .I1(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0 ), .I2(Q[1]), .I3(\grdc.rd_data_count_i_reg[7] [1]), .I4(Q[2]), .I5(Q[4]), .O(src_in_bin[3])); LUT6 #( .INIT(64'hFBFBBAFB04044504)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_6 (.I0(Q[2]), .I1(\grdc.rd_data_count_i_reg[7] [1]), .I2(Q[1]), .I3(\grdc.rd_data_count_i_reg[7] [0]), .I4(Q[0]), .I5(Q[3]), .O(src_in_bin[2])); (* SOFT_HLUTNM = "soft_lutpair111" *) LUT5 #( .INIT(32'hB0FB4F04)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_7 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .I2(Q[1]), .I3(\grdc.rd_data_count_i_reg[7] [1]), .I4(Q[2]), .O(src_in_bin[1])); (* SOFT_HLUTNM = "soft_lutpair113" *) LUT2 #( .INIT(4'h6)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_9 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .O(src_in_bin[0])); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10 (.I0(Q[6]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [6]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_11 (.I0(Q[5]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [5]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_12 (.I0(Q[4]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [4]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_12_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_13 (.I0(Q[3]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [3]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_13_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_14 (.I0(Q[2]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [2]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_14_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_15 (.I0(Q[1]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [1]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_15_n_0 )); LUT5 #( .INIT(32'hABAA5455)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_16 (.I0(ram_empty_i), .I1(rd_en), .I2(\count_value_i_reg[0]_0 [0]), .I3(\count_value_i_reg[0]_0 [1]), .I4(Q[0]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_16_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2 (.I0(Q[6]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3 (.I0(Q[5]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4 (.I0(Q[4]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5 (.I0(Q[3]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6 (.I0(Q[2]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7 (.I0(Q[1]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8 (.I0(Q[0]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9 (.I0(Q[7]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [7]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9_n_0 )); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY8 \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1 (.CI(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [0]), .CI_TOP(1'b0), .CO({\NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_CO_UNCONNECTED [7],\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_1 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_2 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_3 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_4 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_5 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_6 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_7 }), .DI({1'b0,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8_n_0 }), .O(D), .S({\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_11_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_12_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_13_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_14_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_15_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_16_n_0 })); LUT4 #( .INIT(16'h00FD)) \gen_sdpram.xpm_memory_base_inst_i_2 (.I0(\count_value_i_reg[0]_0 [1]), .I1(\count_value_i_reg[0]_0 [0]), .I2(rd_en), .I3(ram_empty_i), .O(enb)); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_10 (.I0(Q[5]), .I1(\grdc.rd_data_count_i_reg[8] [4]), .I2(Q[6]), .I3(\grdc.rd_data_count_i_reg[8] [5]), .O(S[3])); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_11 (.I0(Q[4]), .I1(\grdc.rd_data_count_i_reg[8] [3]), .I2(Q[5]), .I3(\grdc.rd_data_count_i_reg[8] [4]), .O(S[2])); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_12 (.I0(Q[3]), .I1(\grdc.rd_data_count_i_reg[8] [2]), .I2(Q[4]), .I3(\grdc.rd_data_count_i_reg[8] [3]), .O(S[1])); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_13 (.I0(Q[2]), .I1(\grdc.rd_data_count_i_reg[8] [1]), .I2(Q[3]), .I3(\grdc.rd_data_count_i_reg[8] [2]), .O(S[0])); LUT3 #( .INIT(8'hD4)) \grdc.rd_data_count_i[7]_i_7 (.I0(Q[1]), .I1(\grdc.rd_data_count_i_reg[7] [1]), .I2(\grdc.rd_data_count_i_reg[8] [0]), .O(DI)); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_9 (.I0(Q[6]), .I1(\grdc.rd_data_count_i_reg[8] [5]), .I2(Q[7]), .I3(\grdc.rd_data_count_i_reg[8] [6]), .O(S[4])); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[8]_i_3 (.I0(Q[7]), .I1(\grdc.rd_data_count_i_reg[8] [6]), .I2(\count_value_i_reg_n_0_[8] ), .I3(\grdc.rd_data_count_i_reg[8] [7]), .O(\count_value_i_reg[7]_0 )); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module axi_chip2chip_64B66B_xpm_counter_updn__parameterized0_31 (Q, D, wr_pntr_plus1_pf_carry, wr_en, \count_value_i_reg[6]_0 , wrst_busy, rst_d1, \gwdc.wr_data_count_i_reg[8] , wr_clk); output [8:0]Q; output [7:0]D; input wr_pntr_plus1_pf_carry; input wr_en; input \count_value_i_reg[6]_0 ; input wrst_busy; input rst_d1; input [8:0]\gwdc.wr_data_count_i_reg[8] ; input wr_clk; wire [7:0]D; wire [8:0]Q; wire \count_value_i[0]_i_1__1_n_0 ; wire \count_value_i[1]_i_1__1_n_0 ; wire \count_value_i[2]_i_1__1_n_0 ; wire \count_value_i[3]_i_1__1_n_0 ; wire \count_value_i[4]_i_1__1_n_0 ; wire \count_value_i[5]_i_1__1_n_0 ; wire \count_value_i[6]_i_1__1_n_0 ; wire \count_value_i[6]_i_2__1_n_0 ; wire \count_value_i[7]_i_1__1_n_0 ; wire \count_value_i[8]_i_1_n_0 ; wire \count_value_i[8]_i_2_n_0 ; wire \count_value_i_reg[6]_0 ; wire \gwdc.wr_data_count_i[7]_i_2_n_0 ; wire \gwdc.wr_data_count_i[7]_i_3_n_0 ; wire \gwdc.wr_data_count_i[7]_i_4_n_0 ; wire \gwdc.wr_data_count_i[7]_i_5_n_0 ; wire \gwdc.wr_data_count_i[7]_i_6_n_0 ; wire \gwdc.wr_data_count_i[7]_i_7_n_0 ; wire \gwdc.wr_data_count_i[7]_i_8_n_0 ; wire \gwdc.wr_data_count_i[7]_i_9_n_0 ; wire \gwdc.wr_data_count_i[8]_i_2_n_0 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_0 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_1 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_2 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_3 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_4 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_5 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_6 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_7 ; wire [8:0]\gwdc.wr_data_count_i_reg[8] ; wire rst_d1; wire wr_clk; wire wr_en; wire wr_pntr_plus1_pf_carry; wire wrst_busy; wire [0:0]\NLW_gwdc.wr_data_count_i_reg[7]_i_1_O_UNCONNECTED ; wire [7:0]\NLW_gwdc.wr_data_count_i_reg[8]_i_1_CO_UNCONNECTED ; wire [7:1]\NLW_gwdc.wr_data_count_i_reg[8]_i_1_O_UNCONNECTED ; LUT1 #( .INIT(2'h1)) \count_value_i[0]_i_1__1 (.I0(Q[0]), .O(\count_value_i[0]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair118" *) LUT2 #( .INIT(4'h6)) \count_value_i[1]_i_1__1 (.I0(Q[0]), .I1(Q[1]), .O(\count_value_i[1]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair118" *) LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1__1 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair117" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1__1 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair117" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1__1 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1__1_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1__1 (.I0(Q[3]), .I1(\count_value_i[6]_i_2__1_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1__1_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1__1 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2__1_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1__1_n_0 )); LUT6 #( .INIT(64'h0000000800000000)) \count_value_i[6]_i_2__1 (.I0(Q[1]), .I1(wr_en), .I2(\count_value_i_reg[6]_0 ), .I3(wrst_busy), .I4(rst_d1), .I5(Q[0]), .O(\count_value_i[6]_i_2__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair116" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1__1 (.I0(Q[5]), .I1(\count_value_i[8]_i_2_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair116" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[8]_i_1 (.I0(Q[6]), .I1(\count_value_i[8]_i_2_n_0 ), .I2(Q[5]), .I3(Q[7]), .I4(Q[8]), .O(\count_value_i[8]_i_1_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[8]_i_2 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(wr_pntr_plus1_pf_carry), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[8]_i_2_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[0]_i_1__1_n_0 ), .Q(Q[0]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[1]_i_1__1_n_0 ), .Q(Q[1]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[2]_i_1__1_n_0 ), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[3]_i_1__1_n_0 ), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[4]_i_1__1_n_0 ), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[5]_i_1__1_n_0 ), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[6]_i_1__1_n_0 ), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[7]_i_1__1_n_0 ), .Q(Q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[8] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[8]_i_1_n_0 ), .Q(Q[8]), .R(wrst_busy)); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_2 (.I0(Q[7]), .I1(\gwdc.wr_data_count_i_reg[8] [7]), .O(\gwdc.wr_data_count_i[7]_i_2_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_3 (.I0(Q[6]), .I1(\gwdc.wr_data_count_i_reg[8] [6]), .O(\gwdc.wr_data_count_i[7]_i_3_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_4 (.I0(Q[5]), .I1(\gwdc.wr_data_count_i_reg[8] [5]), .O(\gwdc.wr_data_count_i[7]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_5 (.I0(Q[4]), .I1(\gwdc.wr_data_count_i_reg[8] [4]), .O(\gwdc.wr_data_count_i[7]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_6 (.I0(Q[3]), .I1(\gwdc.wr_data_count_i_reg[8] [3]), .O(\gwdc.wr_data_count_i[7]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_7 (.I0(Q[2]), .I1(\gwdc.wr_data_count_i_reg[8] [2]), .O(\gwdc.wr_data_count_i[7]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_8 (.I0(Q[1]), .I1(\gwdc.wr_data_count_i_reg[8] [1]), .O(\gwdc.wr_data_count_i[7]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_9 (.I0(Q[0]), .I1(\gwdc.wr_data_count_i_reg[8] [0]), .O(\gwdc.wr_data_count_i[7]_i_9_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[8]_i_2 (.I0(Q[8]), .I1(\gwdc.wr_data_count_i_reg[8] [8]), .O(\gwdc.wr_data_count_i[8]_i_2_n_0 )); (* ADDER_THRESHOLD = "35" *) CARRY8 \gwdc.wr_data_count_i_reg[7]_i_1 (.CI(1'b1), .CI_TOP(1'b0), .CO({\gwdc.wr_data_count_i_reg[7]_i_1_n_0 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_1 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_2 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_3 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_4 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_5 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_6 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_7 }), .DI(Q[7:0]), .O({D[6:0],\NLW_gwdc.wr_data_count_i_reg[7]_i_1_O_UNCONNECTED [0]}), .S({\gwdc.wr_data_count_i[7]_i_2_n_0 ,\gwdc.wr_data_count_i[7]_i_3_n_0 ,\gwdc.wr_data_count_i[7]_i_4_n_0 ,\gwdc.wr_data_count_i[7]_i_5_n_0 ,\gwdc.wr_data_count_i[7]_i_6_n_0 ,\gwdc.wr_data_count_i[7]_i_7_n_0 ,\gwdc.wr_data_count_i[7]_i_8_n_0 ,\gwdc.wr_data_count_i[7]_i_9_n_0 })); (* ADDER_THRESHOLD = "35" *) CARRY8 \gwdc.wr_data_count_i_reg[8]_i_1 (.CI(\gwdc.wr_data_count_i_reg[7]_i_1_n_0 ), .CI_TOP(1'b0), .CO(\NLW_gwdc.wr_data_count_i_reg[8]_i_1_CO_UNCONNECTED [7:0]), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .O({\NLW_gwdc.wr_data_count_i_reg[8]_i_1_O_UNCONNECTED [7:1],D[7]}), .S({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\gwdc.wr_data_count_i[8]_i_2_n_0 })); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module axi_chip2chip_64B66B_xpm_counter_updn__parameterized0_39 (Q, enb, DI, \count_value_i_reg[7]_0 , D, S, src_in_bin, \count_value_i_reg[0]_0 , rd_en, ram_empty_i, \grdc.rd_data_count_i_reg[7] , \grdc.rd_data_count_i_reg[8] , \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] , \count_value_i_reg[8]_0 , rd_clk); output [7:0]Q; output enb; output [0:0]DI; output [0:0]\count_value_i_reg[7]_0 ; output [7:0]D; output [4:0]S; output [7:0]src_in_bin; input [1:0]\count_value_i_reg[0]_0 ; input rd_en; input ram_empty_i; input [1:0]\grdc.rd_data_count_i_reg[7] ; input [7:0]\grdc.rd_data_count_i_reg[8] ; input [7:0]\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] ; input \count_value_i_reg[8]_0 ; input rd_clk; wire [7:0]D; wire [0:0]DI; wire [7:0]Q; wire [4:0]S; wire \count_value_i[0]_i_1__4_n_0 ; wire \count_value_i[1]_i_1__3_n_0 ; wire \count_value_i[2]_i_1__3_n_0 ; wire \count_value_i[3]_i_1__3_n_0 ; wire \count_value_i[4]_i_1__3_n_0 ; wire \count_value_i[5]_i_1__2_n_0 ; wire \count_value_i[6]_i_1__2_n_0 ; wire \count_value_i[6]_i_2__2_n_0 ; wire \count_value_i[7]_i_1__2_n_0 ; wire \count_value_i[8]_i_1__0_n_0 ; wire \count_value_i[8]_i_2__0_n_0 ; wire [1:0]\count_value_i_reg[0]_0 ; wire [0:0]\count_value_i_reg[7]_0 ; wire \count_value_i_reg[8]_0 ; wire \count_value_i_reg_n_0_[8] ; wire enb; wire \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ; wire \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_11_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_12_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_13_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_14_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_15_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_16_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9_n_0 ; wire [7:0]\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_1 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_2 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_3 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_4 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_5 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_6 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_7 ; wire [1:0]\grdc.rd_data_count_i_reg[7] ; wire [7:0]\grdc.rd_data_count_i_reg[8] ; wire ram_empty_i; wire rd_clk; wire rd_en; wire [7:0]src_in_bin; wire [7:7]\NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_CO_UNCONNECTED ; LUT5 #( .INIT(32'hABAA5455)) \count_value_i[0]_i_1__4 (.I0(ram_empty_i), .I1(rd_en), .I2(\count_value_i_reg[0]_0 [0]), .I3(\count_value_i_reg[0]_0 [1]), .I4(Q[0]), .O(\count_value_i[0]_i_1__4_n_0 )); LUT5 #( .INIT(32'h02FFFD00)) \count_value_i[1]_i_1__3 (.I0(\count_value_i_reg[0]_0 [1]), .I1(\count_value_i_reg[0]_0 [0]), .I2(rd_en), .I3(Q[0]), .I4(Q[1]), .O(\count_value_i[1]_i_1__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair77" *) LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1__3 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair78" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1__3 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair78" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1__3 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1__3_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1__2 (.I0(Q[3]), .I1(\count_value_i[6]_i_2__2_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1__2_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1__2 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2__2_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1__2_n_0 )); LUT6 #( .INIT(64'h0000AAA200000000)) \count_value_i[6]_i_2__2 (.I0(Q[1]), .I1(\count_value_i_reg[0]_0 [1]), .I2(\count_value_i_reg[0]_0 [0]), .I3(rd_en), .I4(ram_empty_i), .I5(Q[0]), .O(\count_value_i[6]_i_2__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair75" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1__2 (.I0(Q[5]), .I1(\count_value_i[8]_i_2__0_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair75" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[8]_i_1__0 (.I0(Q[6]), .I1(\count_value_i[8]_i_2__0_n_0 ), .I2(Q[5]), .I3(Q[7]), .I4(\count_value_i_reg_n_0_[8] ), .O(\count_value_i[8]_i_1__0_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[8]_i_2__0 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(enb), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[8]_i_2__0_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(rd_clk), .CE(enb), .D(\count_value_i[0]_i_1__4_n_0 ), .Q(Q[0]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(rd_clk), .CE(enb), .D(\count_value_i[1]_i_1__3_n_0 ), .Q(Q[1]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(rd_clk), .CE(enb), .D(\count_value_i[2]_i_1__3_n_0 ), .Q(Q[2]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(rd_clk), .CE(enb), .D(\count_value_i[3]_i_1__3_n_0 ), .Q(Q[3]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(rd_clk), .CE(enb), .D(\count_value_i[4]_i_1__3_n_0 ), .Q(Q[4]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(rd_clk), .CE(enb), .D(\count_value_i[5]_i_1__2_n_0 ), .Q(Q[5]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(rd_clk), .CE(enb), .D(\count_value_i[6]_i_1__2_n_0 ), .Q(Q[6]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(rd_clk), .CE(enb), .D(\count_value_i[7]_i_1__2_n_0 ), .Q(Q[7]), .R(\count_value_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[8] (.C(rd_clk), .CE(enb), .D(\count_value_i[8]_i_1__0_n_0 ), .Q(\count_value_i_reg_n_0_[8] ), .R(\count_value_i_reg[8]_0 )); LUT6 #( .INIT(64'hFFFFFFFE00000001)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_1 (.I0(Q[7]), .I1(Q[5]), .I2(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ), .I3(Q[4]), .I4(Q[6]), .I5(\count_value_i_reg_n_0_[8] ), .O(src_in_bin[7])); LUT6 #( .INIT(64'hFFFFFFFFFBFBBAFB)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10 (.I0(Q[2]), .I1(\grdc.rd_data_count_i_reg[7] [1]), .I2(Q[1]), .I3(\grdc.rd_data_count_i_reg[7] [0]), .I4(Q[0]), .I5(Q[3]), .O(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 )); (* SOFT_HLUTNM = "soft_lutpair79" *) LUT2 #( .INIT(4'hB)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .O(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0 )); (* SOFT_HLUTNM = "soft_lutpair76" *) LUT5 #( .INIT(32'hFFFE0001)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_2 (.I0(Q[6]), .I1(Q[4]), .I2(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ), .I3(Q[5]), .I4(Q[7]), .O(src_in_bin[6])); (* SOFT_HLUTNM = "soft_lutpair76" *) LUT4 #( .INIT(16'hFE01)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_3 (.I0(Q[5]), .I1(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ), .I2(Q[4]), .I3(Q[6]), .O(src_in_bin[5])); LUT3 #( .INIT(8'hE1)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_4 (.I0(Q[4]), .I1(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_10_n_0 ), .I2(Q[5]), .O(src_in_bin[4])); LUT6 #( .INIT(64'hFFFFEAFE00001501)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_5 (.I0(Q[3]), .I1(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0 ), .I2(Q[1]), .I3(\grdc.rd_data_count_i_reg[7] [1]), .I4(Q[2]), .I5(Q[4]), .O(src_in_bin[3])); LUT6 #( .INIT(64'hFBFBBAFB04044504)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_6 (.I0(Q[2]), .I1(\grdc.rd_data_count_i_reg[7] [1]), .I2(Q[1]), .I3(\grdc.rd_data_count_i_reg[7] [0]), .I4(Q[0]), .I5(Q[3]), .O(src_in_bin[2])); (* SOFT_HLUTNM = "soft_lutpair77" *) LUT5 #( .INIT(32'hB0FB4F04)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_7 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .I2(Q[1]), .I3(\grdc.rd_data_count_i_reg[7] [1]), .I4(Q[2]), .O(src_in_bin[1])); (* SOFT_HLUTNM = "soft_lutpair79" *) LUT2 #( .INIT(4'h6)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_9 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .O(src_in_bin[0])); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10 (.I0(Q[6]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [6]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_11 (.I0(Q[5]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [5]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_11_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_12 (.I0(Q[4]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [4]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_12_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_13 (.I0(Q[3]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [3]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_13_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_14 (.I0(Q[2]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [2]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_14_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_15 (.I0(Q[1]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [1]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_15_n_0 )); LUT5 #( .INIT(32'hABAA5455)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_16 (.I0(ram_empty_i), .I1(rd_en), .I2(\count_value_i_reg[0]_0 [0]), .I3(\count_value_i_reg[0]_0 [1]), .I4(Q[0]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_16_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2 (.I0(Q[6]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3 (.I0(Q[5]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4 (.I0(Q[4]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5 (.I0(Q[3]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6 (.I0(Q[2]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7 (.I0(Q[1]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7_n_0 )); LUT1 #( .INIT(2'h1)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8 (.I0(Q[0]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9 (.I0(Q[7]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [7]), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9_n_0 )); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY8 \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1 (.CI(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] [0]), .CI_TOP(1'b0), .CO({\NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_CO_UNCONNECTED [7],\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_1 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_2 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_3 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_4 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_5 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_6 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_7 }), .DI({1'b0,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8_n_0 }), .O(D), .S({\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_11_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_12_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_13_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_14_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_15_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_16_n_0 })); LUT4 #( .INIT(16'h00FD)) \gen_sdpram.xpm_memory_base_inst_i_2 (.I0(\count_value_i_reg[0]_0 [1]), .I1(\count_value_i_reg[0]_0 [0]), .I2(rd_en), .I3(ram_empty_i), .O(enb)); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_10 (.I0(Q[5]), .I1(\grdc.rd_data_count_i_reg[8] [4]), .I2(Q[6]), .I3(\grdc.rd_data_count_i_reg[8] [5]), .O(S[3])); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_11 (.I0(Q[4]), .I1(\grdc.rd_data_count_i_reg[8] [3]), .I2(Q[5]), .I3(\grdc.rd_data_count_i_reg[8] [4]), .O(S[2])); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_12 (.I0(Q[3]), .I1(\grdc.rd_data_count_i_reg[8] [2]), .I2(Q[4]), .I3(\grdc.rd_data_count_i_reg[8] [3]), .O(S[1])); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_13 (.I0(Q[2]), .I1(\grdc.rd_data_count_i_reg[8] [1]), .I2(Q[3]), .I3(\grdc.rd_data_count_i_reg[8] [2]), .O(S[0])); LUT3 #( .INIT(8'hD4)) \grdc.rd_data_count_i[7]_i_7 (.I0(Q[1]), .I1(\grdc.rd_data_count_i_reg[7] [1]), .I2(\grdc.rd_data_count_i_reg[8] [0]), .O(DI)); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_9 (.I0(Q[6]), .I1(\grdc.rd_data_count_i_reg[8] [5]), .I2(Q[7]), .I3(\grdc.rd_data_count_i_reg[8] [6]), .O(S[4])); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[8]_i_3 (.I0(Q[7]), .I1(\grdc.rd_data_count_i_reg[8] [6]), .I2(\count_value_i_reg_n_0_[8] ), .I3(\grdc.rd_data_count_i_reg[8] [7]), .O(\count_value_i_reg[7]_0 )); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module axi_chip2chip_64B66B_xpm_counter_updn__parameterized0_42 (Q, D, wr_pntr_plus1_pf_carry, wr_en, \count_value_i_reg[6]_0 , wrst_busy, rst_d1, \gwdc.wr_data_count_i_reg[8] , wr_clk); output [8:0]Q; output [7:0]D; input wr_pntr_plus1_pf_carry; input wr_en; input \count_value_i_reg[6]_0 ; input wrst_busy; input rst_d1; input [8:0]\gwdc.wr_data_count_i_reg[8] ; input wr_clk; wire [7:0]D; wire [8:0]Q; wire \count_value_i[0]_i_1__1_n_0 ; wire \count_value_i[1]_i_1__1_n_0 ; wire \count_value_i[2]_i_1__1_n_0 ; wire \count_value_i[3]_i_1__1_n_0 ; wire \count_value_i[4]_i_1__1_n_0 ; wire \count_value_i[5]_i_1__1_n_0 ; wire \count_value_i[6]_i_1__1_n_0 ; wire \count_value_i[6]_i_2__1_n_0 ; wire \count_value_i[7]_i_1__1_n_0 ; wire \count_value_i[8]_i_1_n_0 ; wire \count_value_i[8]_i_2_n_0 ; wire \count_value_i_reg[6]_0 ; wire \gwdc.wr_data_count_i[7]_i_2_n_0 ; wire \gwdc.wr_data_count_i[7]_i_3_n_0 ; wire \gwdc.wr_data_count_i[7]_i_4_n_0 ; wire \gwdc.wr_data_count_i[7]_i_5_n_0 ; wire \gwdc.wr_data_count_i[7]_i_6_n_0 ; wire \gwdc.wr_data_count_i[7]_i_7_n_0 ; wire \gwdc.wr_data_count_i[7]_i_8_n_0 ; wire \gwdc.wr_data_count_i[7]_i_9_n_0 ; wire \gwdc.wr_data_count_i[8]_i_2_n_0 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_0 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_1 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_2 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_3 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_4 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_5 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_6 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_7 ; wire [8:0]\gwdc.wr_data_count_i_reg[8] ; wire rst_d1; wire wr_clk; wire wr_en; wire wr_pntr_plus1_pf_carry; wire wrst_busy; wire [0:0]\NLW_gwdc.wr_data_count_i_reg[7]_i_1_O_UNCONNECTED ; wire [7:0]\NLW_gwdc.wr_data_count_i_reg[8]_i_1_CO_UNCONNECTED ; wire [7:1]\NLW_gwdc.wr_data_count_i_reg[8]_i_1_O_UNCONNECTED ; LUT1 #( .INIT(2'h1)) \count_value_i[0]_i_1__1 (.I0(Q[0]), .O(\count_value_i[0]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair84" *) LUT2 #( .INIT(4'h6)) \count_value_i[1]_i_1__1 (.I0(Q[0]), .I1(Q[1]), .O(\count_value_i[1]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair84" *) LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1__1 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair83" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1__1 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair83" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1__1 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1__1_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1__1 (.I0(Q[3]), .I1(\count_value_i[6]_i_2__1_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1__1_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1__1 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2__1_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1__1_n_0 )); LUT6 #( .INIT(64'h0000000800000000)) \count_value_i[6]_i_2__1 (.I0(Q[1]), .I1(wr_en), .I2(\count_value_i_reg[6]_0 ), .I3(wrst_busy), .I4(rst_d1), .I5(Q[0]), .O(\count_value_i[6]_i_2__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair82" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1__1 (.I0(Q[5]), .I1(\count_value_i[8]_i_2_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair82" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[8]_i_1 (.I0(Q[6]), .I1(\count_value_i[8]_i_2_n_0 ), .I2(Q[5]), .I3(Q[7]), .I4(Q[8]), .O(\count_value_i[8]_i_1_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[8]_i_2 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(wr_pntr_plus1_pf_carry), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[8]_i_2_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[0]_i_1__1_n_0 ), .Q(Q[0]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[1]_i_1__1_n_0 ), .Q(Q[1]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[2]_i_1__1_n_0 ), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[3]_i_1__1_n_0 ), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[4]_i_1__1_n_0 ), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[5]_i_1__1_n_0 ), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[6]_i_1__1_n_0 ), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[7]_i_1__1_n_0 ), .Q(Q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[8] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[8]_i_1_n_0 ), .Q(Q[8]), .R(wrst_busy)); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_2 (.I0(Q[7]), .I1(\gwdc.wr_data_count_i_reg[8] [7]), .O(\gwdc.wr_data_count_i[7]_i_2_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_3 (.I0(Q[6]), .I1(\gwdc.wr_data_count_i_reg[8] [6]), .O(\gwdc.wr_data_count_i[7]_i_3_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_4 (.I0(Q[5]), .I1(\gwdc.wr_data_count_i_reg[8] [5]), .O(\gwdc.wr_data_count_i[7]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_5 (.I0(Q[4]), .I1(\gwdc.wr_data_count_i_reg[8] [4]), .O(\gwdc.wr_data_count_i[7]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_6 (.I0(Q[3]), .I1(\gwdc.wr_data_count_i_reg[8] [3]), .O(\gwdc.wr_data_count_i[7]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_7 (.I0(Q[2]), .I1(\gwdc.wr_data_count_i_reg[8] [2]), .O(\gwdc.wr_data_count_i[7]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_8 (.I0(Q[1]), .I1(\gwdc.wr_data_count_i_reg[8] [1]), .O(\gwdc.wr_data_count_i[7]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_9 (.I0(Q[0]), .I1(\gwdc.wr_data_count_i_reg[8] [0]), .O(\gwdc.wr_data_count_i[7]_i_9_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[8]_i_2 (.I0(Q[8]), .I1(\gwdc.wr_data_count_i_reg[8] [8]), .O(\gwdc.wr_data_count_i[8]_i_2_n_0 )); (* ADDER_THRESHOLD = "35" *) CARRY8 \gwdc.wr_data_count_i_reg[7]_i_1 (.CI(1'b1), .CI_TOP(1'b0), .CO({\gwdc.wr_data_count_i_reg[7]_i_1_n_0 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_1 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_2 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_3 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_4 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_5 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_6 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_7 }), .DI(Q[7:0]), .O({D[6:0],\NLW_gwdc.wr_data_count_i_reg[7]_i_1_O_UNCONNECTED [0]}), .S({\gwdc.wr_data_count_i[7]_i_2_n_0 ,\gwdc.wr_data_count_i[7]_i_3_n_0 ,\gwdc.wr_data_count_i[7]_i_4_n_0 ,\gwdc.wr_data_count_i[7]_i_5_n_0 ,\gwdc.wr_data_count_i[7]_i_6_n_0 ,\gwdc.wr_data_count_i[7]_i_7_n_0 ,\gwdc.wr_data_count_i[7]_i_8_n_0 ,\gwdc.wr_data_count_i[7]_i_9_n_0 })); (* ADDER_THRESHOLD = "35" *) CARRY8 \gwdc.wr_data_count_i_reg[8]_i_1 (.CI(\gwdc.wr_data_count_i_reg[7]_i_1_n_0 ), .CI_TOP(1'b0), .CO(\NLW_gwdc.wr_data_count_i_reg[8]_i_1_CO_UNCONNECTED [7:0]), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .O({\NLW_gwdc.wr_data_count_i_reg[8]_i_1_O_UNCONNECTED [7:1],D[7]}), .S({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\gwdc.wr_data_count_i[8]_i_2_n_0 })); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module axi_chip2chip_64B66B_xpm_counter_updn__parameterized1 (Q, E, \count_value_i_reg[1]_0 , rd_en, ram_empty_i, \count_value_i_reg[0]_0 , rd_clk); output [7:0]Q; input [0:0]E; input [1:0]\count_value_i_reg[1]_0 ; input rd_en; input ram_empty_i; input \count_value_i_reg[0]_0 ; input rd_clk; wire [0:0]E; wire [7:0]Q; wire \count_value_i[0]_i_1__2_n_0 ; wire \count_value_i[1]_i_1__2_n_0 ; wire \count_value_i[2]_i_1__2_n_0 ; wire \count_value_i[3]_i_1__2_n_0 ; wire \count_value_i[4]_i_1__2_n_0 ; wire \count_value_i[5]_i_1__3_n_0 ; wire \count_value_i[6]_i_1__3_n_0 ; wire \count_value_i[6]_i_2__3_n_0 ; wire \count_value_i[7]_i_1__3_n_0 ; wire \count_value_i[7]_i_2__1_n_0 ; wire \count_value_i_reg[0]_0 ; wire [1:0]\count_value_i_reg[1]_0 ; wire ram_empty_i; wire rd_clk; wire rd_en; LUT4 #( .INIT(16'h10EF)) \count_value_i[0]_i_1__2 (.I0(rd_en), .I1(\count_value_i_reg[1]_0 [0]), .I2(\count_value_i_reg[1]_0 [1]), .I3(Q[0]), .O(\count_value_i[0]_i_1__2_n_0 )); LUT5 #( .INIT(32'h02FFFD00)) \count_value_i[1]_i_1__2 (.I0(\count_value_i_reg[1]_0 [1]), .I1(\count_value_i_reg[1]_0 [0]), .I2(rd_en), .I3(Q[0]), .I4(Q[1]), .O(\count_value_i[1]_i_1__2_n_0 )); LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1__2 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair147" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1__2 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair147" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1__2 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1__2_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1__3 (.I0(Q[3]), .I1(\count_value_i[6]_i_2__3_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1__3_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1__3 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2__3_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1__3_n_0 )); LUT6 #( .INIT(64'h0000AAA200000000)) \count_value_i[6]_i_2__3 (.I0(Q[1]), .I1(\count_value_i_reg[1]_0 [1]), .I2(\count_value_i_reg[1]_0 [0]), .I3(rd_en), .I4(ram_empty_i), .I5(Q[0]), .O(\count_value_i[6]_i_2__3_n_0 )); LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1__3 (.I0(Q[5]), .I1(\count_value_i[7]_i_2__1_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1__3_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[7]_i_2__1 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(E), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[7]_i_2__1_n_0 )); FDSE #( .INIT(1'b1)) \count_value_i_reg[0] (.C(rd_clk), .CE(E), .D(\count_value_i[0]_i_1__2_n_0 ), .Q(Q[0]), .S(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(rd_clk), .CE(E), .D(\count_value_i[1]_i_1__2_n_0 ), .Q(Q[1]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(rd_clk), .CE(E), .D(\count_value_i[2]_i_1__2_n_0 ), .Q(Q[2]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(rd_clk), .CE(E), .D(\count_value_i[3]_i_1__2_n_0 ), .Q(Q[3]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(rd_clk), .CE(E), .D(\count_value_i[4]_i_1__2_n_0 ), .Q(Q[4]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(rd_clk), .CE(E), .D(\count_value_i[5]_i_1__3_n_0 ), .Q(Q[5]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(rd_clk), .CE(E), .D(\count_value_i[6]_i_1__3_n_0 ), .Q(Q[6]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(rd_clk), .CE(E), .D(\count_value_i[7]_i_1__3_n_0 ), .Q(Q[7]), .R(\count_value_i_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module axi_chip2chip_64B66B_xpm_counter_updn__parameterized1_22 (Q, D, wr_pntr_plus1_pf_carry, wr_en, \count_value_i_reg[6]_0 , wrst_busy, rst_d1, \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] , wr_clk); output [7:0]Q; output [6:0]D; input wr_pntr_plus1_pf_carry; input wr_en; input \count_value_i_reg[6]_0 ; input wrst_busy; input rst_d1; input [7:0]\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] ; input wr_clk; wire [6:0]D; wire [7:0]Q; wire \count_value_i[0]_i_1__0_n_0 ; wire \count_value_i[1]_i_1__0_n_0 ; wire \count_value_i[2]_i_1__0_n_0 ; wire \count_value_i[3]_i_1__0_n_0 ; wire \count_value_i[4]_i_1__0_n_0 ; wire \count_value_i[5]_i_1__0_n_0 ; wire \count_value_i[6]_i_1__0_n_0 ; wire \count_value_i[6]_i_2__0_n_0 ; wire \count_value_i[7]_i_1__0_n_0 ; wire \count_value_i[7]_i_2__0_n_0 ; wire \count_value_i_reg[6]_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0 ; wire [7:0]\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_1 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_2 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_3 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_4 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_5 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_6 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_7 ; wire rst_d1; wire wr_clk; wire wr_en; wire wr_pntr_plus1_pf_carry; wire wrst_busy; wire [7:7]\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_CO_UNCONNECTED ; wire [0:0]\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_O_UNCONNECTED ; LUT1 #( .INIT(2'h1)) \count_value_i[0]_i_1__0 (.I0(Q[0]), .O(\count_value_i[0]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair153" *) LUT2 #( .INIT(4'h6)) \count_value_i[1]_i_1__0 (.I0(Q[0]), .I1(Q[1]), .O(\count_value_i[1]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair153" *) LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1__0 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair152" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1__0 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair152" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1__0 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1__0_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1__0 (.I0(Q[3]), .I1(\count_value_i[6]_i_2__0_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1__0_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1__0 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2__0_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1__0_n_0 )); LUT6 #( .INIT(64'h0000000800000000)) \count_value_i[6]_i_2__0 (.I0(Q[1]), .I1(wr_en), .I2(\count_value_i_reg[6]_0 ), .I3(wrst_busy), .I4(rst_d1), .I5(Q[0]), .O(\count_value_i[6]_i_2__0_n_0 )); LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1__0 (.I0(Q[5]), .I1(\count_value_i[7]_i_2__0_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1__0_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[7]_i_2__0 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(wr_pntr_plus1_pf_carry), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[7]_i_2__0_n_0 )); FDSE #( .INIT(1'b1)) \count_value_i_reg[0] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[0]_i_1__0_n_0 ), .Q(Q[0]), .S(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[1]_i_1__0_n_0 ), .Q(Q[1]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[2]_i_1__0_n_0 ), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[3]_i_1__0_n_0 ), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[4]_i_1__0_n_0 ), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[5]_i_1__0_n_0 ), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[6]_i_1__0_n_0 ), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[7]_i_1__0_n_0 ), .Q(Q[7]), .R(wrst_busy)); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2 (.I0(Q[7]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [7]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3 (.I0(Q[6]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [6]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4 (.I0(Q[5]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [5]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5 (.I0(Q[4]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [4]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6 (.I0(Q[3]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [3]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7 (.I0(Q[2]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [2]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8 (.I0(Q[1]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [1]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9 (.I0(Q[0]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [0]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0 )); (* ADDER_THRESHOLD = "35" *) CARRY8 \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1 (.CI(wr_pntr_plus1_pf_carry), .CI_TOP(1'b0), .CO({\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_CO_UNCONNECTED [7],\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_1 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_2 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_3 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_4 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_5 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_6 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_7 }), .DI({1'b0,Q[6:0]}), .O({D,\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_O_UNCONNECTED [0]}), .S({\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0 })); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module axi_chip2chip_64B66B_xpm_counter_updn__parameterized1_29 (Q, E, \count_value_i_reg[1]_0 , rd_en, ram_empty_i, \count_value_i_reg[0]_0 , rd_clk); output [7:0]Q; input [0:0]E; input [1:0]\count_value_i_reg[1]_0 ; input rd_en; input ram_empty_i; input \count_value_i_reg[0]_0 ; input rd_clk; wire [0:0]E; wire [7:0]Q; wire \count_value_i[0]_i_1__2_n_0 ; wire \count_value_i[1]_i_1__2_n_0 ; wire \count_value_i[2]_i_1__2_n_0 ; wire \count_value_i[3]_i_1__2_n_0 ; wire \count_value_i[4]_i_1__2_n_0 ; wire \count_value_i[5]_i_1__3_n_0 ; wire \count_value_i[6]_i_1__3_n_0 ; wire \count_value_i[6]_i_2__3_n_0 ; wire \count_value_i[7]_i_1__3_n_0 ; wire \count_value_i[7]_i_2__1_n_0 ; wire \count_value_i_reg[0]_0 ; wire [1:0]\count_value_i_reg[1]_0 ; wire ram_empty_i; wire rd_clk; wire rd_en; LUT4 #( .INIT(16'h10EF)) \count_value_i[0]_i_1__2 (.I0(rd_en), .I1(\count_value_i_reg[1]_0 [0]), .I2(\count_value_i_reg[1]_0 [1]), .I3(Q[0]), .O(\count_value_i[0]_i_1__2_n_0 )); LUT5 #( .INIT(32'h02FFFD00)) \count_value_i[1]_i_1__2 (.I0(\count_value_i_reg[1]_0 [1]), .I1(\count_value_i_reg[1]_0 [0]), .I2(rd_en), .I3(Q[0]), .I4(Q[1]), .O(\count_value_i[1]_i_1__2_n_0 )); LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1__2 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair114" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1__2 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair114" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1__2 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1__2_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1__3 (.I0(Q[3]), .I1(\count_value_i[6]_i_2__3_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1__3_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1__3 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2__3_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1__3_n_0 )); LUT6 #( .INIT(64'h0000AAA200000000)) \count_value_i[6]_i_2__3 (.I0(Q[1]), .I1(\count_value_i_reg[1]_0 [1]), .I2(\count_value_i_reg[1]_0 [0]), .I3(rd_en), .I4(ram_empty_i), .I5(Q[0]), .O(\count_value_i[6]_i_2__3_n_0 )); LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1__3 (.I0(Q[5]), .I1(\count_value_i[7]_i_2__1_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1__3_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[7]_i_2__1 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(E), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[7]_i_2__1_n_0 )); FDSE #( .INIT(1'b1)) \count_value_i_reg[0] (.C(rd_clk), .CE(E), .D(\count_value_i[0]_i_1__2_n_0 ), .Q(Q[0]), .S(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(rd_clk), .CE(E), .D(\count_value_i[1]_i_1__2_n_0 ), .Q(Q[1]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(rd_clk), .CE(E), .D(\count_value_i[2]_i_1__2_n_0 ), .Q(Q[2]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(rd_clk), .CE(E), .D(\count_value_i[3]_i_1__2_n_0 ), .Q(Q[3]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(rd_clk), .CE(E), .D(\count_value_i[4]_i_1__2_n_0 ), .Q(Q[4]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(rd_clk), .CE(E), .D(\count_value_i[5]_i_1__3_n_0 ), .Q(Q[5]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(rd_clk), .CE(E), .D(\count_value_i[6]_i_1__3_n_0 ), .Q(Q[6]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(rd_clk), .CE(E), .D(\count_value_i[7]_i_1__3_n_0 ), .Q(Q[7]), .R(\count_value_i_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module axi_chip2chip_64B66B_xpm_counter_updn__parameterized1_32 (Q, D, wr_pntr_plus1_pf_carry, wr_en, \count_value_i_reg[6]_0 , wrst_busy, rst_d1, \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] , wr_clk); output [7:0]Q; output [6:0]D; input wr_pntr_plus1_pf_carry; input wr_en; input \count_value_i_reg[6]_0 ; input wrst_busy; input rst_d1; input [7:0]\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] ; input wr_clk; wire [6:0]D; wire [7:0]Q; wire \count_value_i[0]_i_1__0_n_0 ; wire \count_value_i[1]_i_1__0_n_0 ; wire \count_value_i[2]_i_1__0_n_0 ; wire \count_value_i[3]_i_1__0_n_0 ; wire \count_value_i[4]_i_1__0_n_0 ; wire \count_value_i[5]_i_1__0_n_0 ; wire \count_value_i[6]_i_1__0_n_0 ; wire \count_value_i[6]_i_2__0_n_0 ; wire \count_value_i[7]_i_1__0_n_0 ; wire \count_value_i[7]_i_2__0_n_0 ; wire \count_value_i_reg[6]_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0 ; wire [7:0]\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_1 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_2 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_3 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_4 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_5 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_6 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_7 ; wire rst_d1; wire wr_clk; wire wr_en; wire wr_pntr_plus1_pf_carry; wire wrst_busy; wire [7:7]\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_CO_UNCONNECTED ; wire [0:0]\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_O_UNCONNECTED ; LUT1 #( .INIT(2'h1)) \count_value_i[0]_i_1__0 (.I0(Q[0]), .O(\count_value_i[0]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair120" *) LUT2 #( .INIT(4'h6)) \count_value_i[1]_i_1__0 (.I0(Q[0]), .I1(Q[1]), .O(\count_value_i[1]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair120" *) LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1__0 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair119" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1__0 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair119" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1__0 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1__0_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1__0 (.I0(Q[3]), .I1(\count_value_i[6]_i_2__0_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1__0_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1__0 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2__0_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1__0_n_0 )); LUT6 #( .INIT(64'h0000000800000000)) \count_value_i[6]_i_2__0 (.I0(Q[1]), .I1(wr_en), .I2(\count_value_i_reg[6]_0 ), .I3(wrst_busy), .I4(rst_d1), .I5(Q[0]), .O(\count_value_i[6]_i_2__0_n_0 )); LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1__0 (.I0(Q[5]), .I1(\count_value_i[7]_i_2__0_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1__0_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[7]_i_2__0 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(wr_pntr_plus1_pf_carry), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[7]_i_2__0_n_0 )); FDSE #( .INIT(1'b1)) \count_value_i_reg[0] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[0]_i_1__0_n_0 ), .Q(Q[0]), .S(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[1]_i_1__0_n_0 ), .Q(Q[1]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[2]_i_1__0_n_0 ), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[3]_i_1__0_n_0 ), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[4]_i_1__0_n_0 ), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[5]_i_1__0_n_0 ), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[6]_i_1__0_n_0 ), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[7]_i_1__0_n_0 ), .Q(Q[7]), .R(wrst_busy)); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2 (.I0(Q[7]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [7]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3 (.I0(Q[6]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [6]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4 (.I0(Q[5]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [5]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5 (.I0(Q[4]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [4]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6 (.I0(Q[3]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [3]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7 (.I0(Q[2]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [2]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8 (.I0(Q[1]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [1]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9 (.I0(Q[0]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [0]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0 )); (* ADDER_THRESHOLD = "35" *) CARRY8 \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1 (.CI(wr_pntr_plus1_pf_carry), .CI_TOP(1'b0), .CO({\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_CO_UNCONNECTED [7],\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_1 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_2 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_3 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_4 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_5 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_6 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_7 }), .DI({1'b0,Q[6:0]}), .O({D,\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_O_UNCONNECTED [0]}), .S({\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0 })); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module axi_chip2chip_64B66B_xpm_counter_updn__parameterized1_40 (Q, E, \count_value_i_reg[1]_0 , rd_en, ram_empty_i, \count_value_i_reg[0]_0 , rd_clk); output [7:0]Q; input [0:0]E; input [1:0]\count_value_i_reg[1]_0 ; input rd_en; input ram_empty_i; input \count_value_i_reg[0]_0 ; input rd_clk; wire [0:0]E; wire [7:0]Q; wire \count_value_i[0]_i_1__2_n_0 ; wire \count_value_i[1]_i_1__2_n_0 ; wire \count_value_i[2]_i_1__2_n_0 ; wire \count_value_i[3]_i_1__2_n_0 ; wire \count_value_i[4]_i_1__2_n_0 ; wire \count_value_i[5]_i_1__3_n_0 ; wire \count_value_i[6]_i_1__3_n_0 ; wire \count_value_i[6]_i_2__3_n_0 ; wire \count_value_i[7]_i_1__3_n_0 ; wire \count_value_i[7]_i_2__1_n_0 ; wire \count_value_i_reg[0]_0 ; wire [1:0]\count_value_i_reg[1]_0 ; wire ram_empty_i; wire rd_clk; wire rd_en; LUT4 #( .INIT(16'h10EF)) \count_value_i[0]_i_1__2 (.I0(rd_en), .I1(\count_value_i_reg[1]_0 [0]), .I2(\count_value_i_reg[1]_0 [1]), .I3(Q[0]), .O(\count_value_i[0]_i_1__2_n_0 )); LUT5 #( .INIT(32'h02FFFD00)) \count_value_i[1]_i_1__2 (.I0(\count_value_i_reg[1]_0 [1]), .I1(\count_value_i_reg[1]_0 [0]), .I2(rd_en), .I3(Q[0]), .I4(Q[1]), .O(\count_value_i[1]_i_1__2_n_0 )); LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1__2 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair80" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1__2 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair80" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1__2 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1__2_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1__3 (.I0(Q[3]), .I1(\count_value_i[6]_i_2__3_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1__3_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1__3 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2__3_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1__3_n_0 )); LUT6 #( .INIT(64'h0000AAA200000000)) \count_value_i[6]_i_2__3 (.I0(Q[1]), .I1(\count_value_i_reg[1]_0 [1]), .I2(\count_value_i_reg[1]_0 [0]), .I3(rd_en), .I4(ram_empty_i), .I5(Q[0]), .O(\count_value_i[6]_i_2__3_n_0 )); LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1__3 (.I0(Q[5]), .I1(\count_value_i[7]_i_2__1_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1__3_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[7]_i_2__1 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(E), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[7]_i_2__1_n_0 )); FDSE #( .INIT(1'b1)) \count_value_i_reg[0] (.C(rd_clk), .CE(E), .D(\count_value_i[0]_i_1__2_n_0 ), .Q(Q[0]), .S(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(rd_clk), .CE(E), .D(\count_value_i[1]_i_1__2_n_0 ), .Q(Q[1]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(rd_clk), .CE(E), .D(\count_value_i[2]_i_1__2_n_0 ), .Q(Q[2]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(rd_clk), .CE(E), .D(\count_value_i[3]_i_1__2_n_0 ), .Q(Q[3]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(rd_clk), .CE(E), .D(\count_value_i[4]_i_1__2_n_0 ), .Q(Q[4]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(rd_clk), .CE(E), .D(\count_value_i[5]_i_1__3_n_0 ), .Q(Q[5]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(rd_clk), .CE(E), .D(\count_value_i[6]_i_1__3_n_0 ), .Q(Q[6]), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(rd_clk), .CE(E), .D(\count_value_i[7]_i_1__3_n_0 ), .Q(Q[7]), .R(\count_value_i_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module axi_chip2chip_64B66B_xpm_counter_updn__parameterized1_43 (Q, D, wr_pntr_plus1_pf_carry, wr_en, \count_value_i_reg[6]_0 , wrst_busy, rst_d1, \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] , wr_clk); output [7:0]Q; output [6:0]D; input wr_pntr_plus1_pf_carry; input wr_en; input \count_value_i_reg[6]_0 ; input wrst_busy; input rst_d1; input [7:0]\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] ; input wr_clk; wire [6:0]D; wire [7:0]Q; wire \count_value_i[0]_i_1__0_n_0 ; wire \count_value_i[1]_i_1__0_n_0 ; wire \count_value_i[2]_i_1__0_n_0 ; wire \count_value_i[3]_i_1__0_n_0 ; wire \count_value_i[4]_i_1__0_n_0 ; wire \count_value_i[5]_i_1__0_n_0 ; wire \count_value_i[6]_i_1__0_n_0 ; wire \count_value_i[6]_i_2__0_n_0 ; wire \count_value_i[7]_i_1__0_n_0 ; wire \count_value_i[7]_i_2__0_n_0 ; wire \count_value_i_reg[6]_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0 ; wire [7:0]\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_1 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_2 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_3 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_4 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_5 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_6 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_7 ; wire rst_d1; wire wr_clk; wire wr_en; wire wr_pntr_plus1_pf_carry; wire wrst_busy; wire [7:7]\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_CO_UNCONNECTED ; wire [0:0]\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_O_UNCONNECTED ; LUT1 #( .INIT(2'h1)) \count_value_i[0]_i_1__0 (.I0(Q[0]), .O(\count_value_i[0]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair86" *) LUT2 #( .INIT(4'h6)) \count_value_i[1]_i_1__0 (.I0(Q[0]), .I1(Q[1]), .O(\count_value_i[1]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair86" *) LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1__0 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair85" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1__0 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair85" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1__0 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1__0_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1__0 (.I0(Q[3]), .I1(\count_value_i[6]_i_2__0_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1__0_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1__0 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2__0_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1__0_n_0 )); LUT6 #( .INIT(64'h0000000800000000)) \count_value_i[6]_i_2__0 (.I0(Q[1]), .I1(wr_en), .I2(\count_value_i_reg[6]_0 ), .I3(wrst_busy), .I4(rst_d1), .I5(Q[0]), .O(\count_value_i[6]_i_2__0_n_0 )); LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1__0 (.I0(Q[5]), .I1(\count_value_i[7]_i_2__0_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1__0_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[7]_i_2__0 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(wr_pntr_plus1_pf_carry), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[7]_i_2__0_n_0 )); FDSE #( .INIT(1'b1)) \count_value_i_reg[0] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[0]_i_1__0_n_0 ), .Q(Q[0]), .S(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[1]_i_1__0_n_0 ), .Q(Q[1]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[2]_i_1__0_n_0 ), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[3]_i_1__0_n_0 ), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[4]_i_1__0_n_0 ), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[5]_i_1__0_n_0 ), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[6]_i_1__0_n_0 ), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[7]_i_1__0_n_0 ), .Q(Q[7]), .R(wrst_busy)); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2 (.I0(Q[7]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [7]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3 (.I0(Q[6]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [6]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4 (.I0(Q[5]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [5]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5 (.I0(Q[4]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [4]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6 (.I0(Q[3]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [3]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7 (.I0(Q[2]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [2]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8 (.I0(Q[1]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [1]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9 (.I0(Q[0]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] [0]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0 )); (* ADDER_THRESHOLD = "35" *) CARRY8 \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1 (.CI(wr_pntr_plus1_pf_carry), .CI_TOP(1'b0), .CO({\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_CO_UNCONNECTED [7],\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_1 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_2 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_3 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_4 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_5 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_6 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_7 }), .DI({1'b0,Q[6:0]}), .O({D,\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_O_UNCONNECTED [0]}), .S({\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0 })); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module axi_chip2chip_64B66B_xpm_counter_updn__parameterized2 (Q, wr_pntr_plus1_pf_carry, wr_en, \count_value_i_reg[6]_0 , wrst_busy, rst_d1, wr_clk); output [7:0]Q; input wr_pntr_plus1_pf_carry; input wr_en; input \count_value_i_reg[6]_0 ; input wrst_busy; input rst_d1; input wr_clk; wire [7:0]Q; wire \count_value_i[0]_i_1_n_0 ; wire \count_value_i[1]_i_1_n_0 ; wire \count_value_i[2]_i_1_n_0 ; wire \count_value_i[3]_i_1_n_0 ; wire \count_value_i[4]_i_1_n_0 ; wire \count_value_i[5]_i_1_n_0 ; wire \count_value_i[6]_i_1_n_0 ; wire \count_value_i[6]_i_2_n_0 ; wire \count_value_i[7]_i_1_n_0 ; wire \count_value_i[7]_i_2_n_0 ; wire \count_value_i_reg[6]_0 ; wire rst_d1; wire wr_clk; wire wr_en; wire wr_pntr_plus1_pf_carry; wire wrst_busy; (* SOFT_HLUTNM = "soft_lutpair155" *) LUT1 #( .INIT(2'h1)) \count_value_i[0]_i_1 (.I0(Q[0]), .O(\count_value_i[0]_i_1_n_0 )); LUT2 #( .INIT(4'h6)) \count_value_i[1]_i_1 (.I0(Q[0]), .I1(Q[1]), .O(\count_value_i[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair155" *) LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair154" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair154" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1 (.I0(Q[3]), .I1(\count_value_i[6]_i_2_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000800000000)) \count_value_i[6]_i_2 (.I0(Q[1]), .I1(wr_en), .I2(\count_value_i_reg[6]_0 ), .I3(wrst_busy), .I4(rst_d1), .I5(Q[0]), .O(\count_value_i[6]_i_2_n_0 )); LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1 (.I0(Q[5]), .I1(\count_value_i[7]_i_2_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[7]_i_2 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(wr_pntr_plus1_pf_carry), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[7]_i_2_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[0]_i_1_n_0 ), .Q(Q[0]), .R(wrst_busy)); FDSE #( .INIT(1'b1)) \count_value_i_reg[1] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[1]_i_1_n_0 ), .Q(Q[1]), .S(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[2]_i_1_n_0 ), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[3]_i_1_n_0 ), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[4]_i_1_n_0 ), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[5]_i_1_n_0 ), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[6]_i_1_n_0 ), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[7]_i_1_n_0 ), .Q(Q[7]), .R(wrst_busy)); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module axi_chip2chip_64B66B_xpm_counter_updn__parameterized2_33 (Q, wr_pntr_plus1_pf_carry, wr_en, \count_value_i_reg[6]_0 , wrst_busy, rst_d1, wr_clk); output [7:0]Q; input wr_pntr_plus1_pf_carry; input wr_en; input \count_value_i_reg[6]_0 ; input wrst_busy; input rst_d1; input wr_clk; wire [7:0]Q; wire \count_value_i[0]_i_1_n_0 ; wire \count_value_i[1]_i_1_n_0 ; wire \count_value_i[2]_i_1_n_0 ; wire \count_value_i[3]_i_1_n_0 ; wire \count_value_i[4]_i_1_n_0 ; wire \count_value_i[5]_i_1_n_0 ; wire \count_value_i[6]_i_1_n_0 ; wire \count_value_i[6]_i_2_n_0 ; wire \count_value_i[7]_i_1_n_0 ; wire \count_value_i[7]_i_2_n_0 ; wire \count_value_i_reg[6]_0 ; wire rst_d1; wire wr_clk; wire wr_en; wire wr_pntr_plus1_pf_carry; wire wrst_busy; (* SOFT_HLUTNM = "soft_lutpair122" *) LUT1 #( .INIT(2'h1)) \count_value_i[0]_i_1 (.I0(Q[0]), .O(\count_value_i[0]_i_1_n_0 )); LUT2 #( .INIT(4'h6)) \count_value_i[1]_i_1 (.I0(Q[0]), .I1(Q[1]), .O(\count_value_i[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair122" *) LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair121" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair121" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1 (.I0(Q[3]), .I1(\count_value_i[6]_i_2_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000800000000)) \count_value_i[6]_i_2 (.I0(Q[1]), .I1(wr_en), .I2(\count_value_i_reg[6]_0 ), .I3(wrst_busy), .I4(rst_d1), .I5(Q[0]), .O(\count_value_i[6]_i_2_n_0 )); LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1 (.I0(Q[5]), .I1(\count_value_i[7]_i_2_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[7]_i_2 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(wr_pntr_plus1_pf_carry), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[7]_i_2_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[0]_i_1_n_0 ), .Q(Q[0]), .R(wrst_busy)); FDSE #( .INIT(1'b1)) \count_value_i_reg[1] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[1]_i_1_n_0 ), .Q(Q[1]), .S(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[2]_i_1_n_0 ), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[3]_i_1_n_0 ), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[4]_i_1_n_0 ), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[5]_i_1_n_0 ), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[6]_i_1_n_0 ), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[7]_i_1_n_0 ), .Q(Q[7]), .R(wrst_busy)); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module axi_chip2chip_64B66B_xpm_counter_updn__parameterized2_44 (Q, wr_pntr_plus1_pf_carry, wr_en, \count_value_i_reg[6]_0 , wrst_busy, rst_d1, wr_clk); output [7:0]Q; input wr_pntr_plus1_pf_carry; input wr_en; input \count_value_i_reg[6]_0 ; input wrst_busy; input rst_d1; input wr_clk; wire [7:0]Q; wire \count_value_i[0]_i_1_n_0 ; wire \count_value_i[1]_i_1_n_0 ; wire \count_value_i[2]_i_1_n_0 ; wire \count_value_i[3]_i_1_n_0 ; wire \count_value_i[4]_i_1_n_0 ; wire \count_value_i[5]_i_1_n_0 ; wire \count_value_i[6]_i_1_n_0 ; wire \count_value_i[6]_i_2_n_0 ; wire \count_value_i[7]_i_1_n_0 ; wire \count_value_i[7]_i_2_n_0 ; wire \count_value_i_reg[6]_0 ; wire rst_d1; wire wr_clk; wire wr_en; wire wr_pntr_plus1_pf_carry; wire wrst_busy; (* SOFT_HLUTNM = "soft_lutpair88" *) LUT1 #( .INIT(2'h1)) \count_value_i[0]_i_1 (.I0(Q[0]), .O(\count_value_i[0]_i_1_n_0 )); LUT2 #( .INIT(4'h6)) \count_value_i[1]_i_1 (.I0(Q[0]), .I1(Q[1]), .O(\count_value_i[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair88" *) LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair87" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair87" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1 (.I0(Q[3]), .I1(\count_value_i[6]_i_2_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000800000000)) \count_value_i[6]_i_2 (.I0(Q[1]), .I1(wr_en), .I2(\count_value_i_reg[6]_0 ), .I3(wrst_busy), .I4(rst_d1), .I5(Q[0]), .O(\count_value_i[6]_i_2_n_0 )); LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1 (.I0(Q[5]), .I1(\count_value_i[7]_i_2_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[7]_i_2 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(wr_pntr_plus1_pf_carry), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[7]_i_2_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[0]_i_1_n_0 ), .Q(Q[0]), .R(wrst_busy)); FDSE #( .INIT(1'b1)) \count_value_i_reg[1] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[1]_i_1_n_0 ), .Q(Q[1]), .S(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[2]_i_1_n_0 ), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[3]_i_1_n_0 ), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[4]_i_1_n_0 ), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[5]_i_1_n_0 ), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[6]_i_1_n_0 ), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[7]_i_1_n_0 ), .Q(Q[7]), .R(wrst_busy)); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module axi_chip2chip_64B66B_xpm_counter_updn__parameterized3 (Q, ram_rd_en_i, \reg_out_i_reg[7] , src_in_bin, \count_value_i_reg[1]_0 , D, \count_value_i_reg[7]_0 , \count_value_i_reg[0]_0 , rd_en, ram_empty_i, \gen_pf_ic_rc.ram_empty_i_reg , \grdc.rd_data_count_i_reg[7] , DI, \grdc.rd_data_count_i_reg[9] , S, \grdc.rd_data_count_i_reg[9]_0 , \count_value_i_reg[9]_0 , rd_clk); output [9:0]Q; output ram_rd_en_i; output \reg_out_i_reg[7] ; output [8:0]src_in_bin; output \count_value_i_reg[1]_0 ; output [8:0]D; output [7:0]\count_value_i_reg[7]_0 ; input [1:0]\count_value_i_reg[0]_0 ; input rd_en; input ram_empty_i; input [8:0]\gen_pf_ic_rc.ram_empty_i_reg ; input [1:0]\grdc.rd_data_count_i_reg[7] ; input [7:0]DI; input [0:0]\grdc.rd_data_count_i_reg[9] ; input [0:0]S; input [8:0]\grdc.rd_data_count_i_reg[9]_0 ; input \count_value_i_reg[9]_0 ; input rd_clk; wire [8:0]D; wire [7:0]DI; wire [9:0]Q; wire [0:0]S; wire \count_value_i[0]_i_1__4_n_0 ; wire \count_value_i[1]_i_1__3_n_0 ; wire \count_value_i[2]_i_1__3_n_0 ; wire \count_value_i[3]_i_1__3_n_0 ; wire \count_value_i[4]_i_1__3_n_0 ; wire \count_value_i[5]_i_1__3_n_0 ; wire \count_value_i[6]_i_1__3_n_0 ; wire \count_value_i[6]_i_2__3_n_0 ; wire \count_value_i[7]_i_1__3_n_0 ; wire \count_value_i[8]_i_1__3_n_0 ; wire \count_value_i[9]_i_1__0_n_0 ; wire \count_value_i[9]_i_2__0_n_0 ; wire [1:0]\count_value_i_reg[0]_0 ; wire \count_value_i_reg[1]_0 ; wire [7:0]\count_value_i_reg[7]_0 ; wire \count_value_i_reg[9]_0 ; wire \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0 ; wire \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0 ; wire \gen_pf_ic_rc.ram_empty_i_i_7_n_0 ; wire \gen_pf_ic_rc.ram_empty_i_i_8_n_0 ; wire [8:0]\gen_pf_ic_rc.ram_empty_i_reg ; wire \grdc.rd_data_count_i[7]_i_10_n_0 ; wire \grdc.rd_data_count_i[7]_i_11_n_0 ; wire \grdc.rd_data_count_i[7]_i_12_n_0 ; wire \grdc.rd_data_count_i[7]_i_13_n_0 ; wire \grdc.rd_data_count_i[7]_i_14_n_0 ; wire \grdc.rd_data_count_i[7]_i_15_n_0 ; wire \grdc.rd_data_count_i[7]_i_16_n_0 ; wire \grdc.rd_data_count_i[7]_i_17_n_0 ; wire \grdc.rd_data_count_i[9]_i_5_n_0 ; wire [1:0]\grdc.rd_data_count_i_reg[7] ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_0 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_1 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_2 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_3 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_4 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_5 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_6 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_7 ; wire [0:0]\grdc.rd_data_count_i_reg[9] ; wire [8:0]\grdc.rd_data_count_i_reg[9]_0 ; wire \grdc.rd_data_count_i_reg[9]_i_2_n_7 ; wire ram_empty_i; wire ram_rd_en_i; wire rd_clk; wire rd_en; wire \reg_out_i_reg[7] ; wire [8:0]src_in_bin; wire [0:0]\NLW_grdc.rd_data_count_i_reg[7]_i_1_O_UNCONNECTED ; wire [7:1]\NLW_grdc.rd_data_count_i_reg[9]_i_2_CO_UNCONNECTED ; wire [7:2]\NLW_grdc.rd_data_count_i_reg[9]_i_2_O_UNCONNECTED ; LUT5 #( .INIT(32'hAABA5545)) \count_value_i[0]_i_1__4 (.I0(ram_empty_i), .I1(rd_en), .I2(\count_value_i_reg[0]_0 [1]), .I3(\count_value_i_reg[0]_0 [0]), .I4(Q[0]), .O(\count_value_i[0]_i_1__4_n_0 )); LUT5 #( .INIT(32'h04FFFB00)) \count_value_i[1]_i_1__3 (.I0(\count_value_i_reg[0]_0 [0]), .I1(\count_value_i_reg[0]_0 [1]), .I2(rd_en), .I3(Q[0]), .I4(Q[1]), .O(\count_value_i[1]_i_1__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair247" *) LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1__3 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair244" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1__3 (.I0(Q[2]), .I1(Q[1]), .I2(Q[0]), .I3(Q[3]), .O(\count_value_i[3]_i_1__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair244" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1__3 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1__3_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1__3 (.I0(Q[4]), .I1(Q[3]), .I2(Q[2]), .I3(\count_value_i[6]_i_2__3_n_0 ), .I4(Q[5]), .O(\count_value_i[5]_i_1__3_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1__3 (.I0(\count_value_i[6]_i_2__3_n_0 ), .I1(Q[2]), .I2(Q[3]), .I3(Q[4]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1__3_n_0 )); LUT6 #( .INIT(64'h0000AA8A00000000)) \count_value_i[6]_i_2__3 (.I0(Q[1]), .I1(\count_value_i_reg[0]_0 [0]), .I2(\count_value_i_reg[0]_0 [1]), .I3(rd_en), .I4(ram_empty_i), .I5(Q[0]), .O(\count_value_i[6]_i_2__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair241" *) LUT4 #( .INIT(16'hF708)) \count_value_i[7]_i_1__3 (.I0(Q[6]), .I1(Q[5]), .I2(\count_value_i[9]_i_2__0_n_0 ), .I3(Q[7]), .O(\count_value_i[7]_i_1__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair241" *) LUT5 #( .INIT(32'hBFFF4000)) \count_value_i[8]_i_1__3 (.I0(\count_value_i[9]_i_2__0_n_0 ), .I1(Q[5]), .I2(Q[6]), .I3(Q[7]), .I4(Q[8]), .O(\count_value_i[8]_i_1__3_n_0 )); LUT6 #( .INIT(64'hFFFF7FFF00008000)) \count_value_i[9]_i_1__0 (.I0(Q[8]), .I1(Q[7]), .I2(Q[6]), .I3(Q[5]), .I4(\count_value_i[9]_i_2__0_n_0 ), .I5(Q[9]), .O(\count_value_i[9]_i_1__0_n_0 )); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) \count_value_i[9]_i_2__0 (.I0(Q[0]), .I1(ram_rd_en_i), .I2(Q[1]), .I3(Q[2]), .I4(Q[3]), .I5(Q[4]), .O(\count_value_i[9]_i_2__0_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(rd_clk), .CE(ram_rd_en_i), .D(\count_value_i[0]_i_1__4_n_0 ), .Q(Q[0]), .R(\count_value_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(rd_clk), .CE(ram_rd_en_i), .D(\count_value_i[1]_i_1__3_n_0 ), .Q(Q[1]), .R(\count_value_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(rd_clk), .CE(ram_rd_en_i), .D(\count_value_i[2]_i_1__3_n_0 ), .Q(Q[2]), .R(\count_value_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(rd_clk), .CE(ram_rd_en_i), .D(\count_value_i[3]_i_1__3_n_0 ), .Q(Q[3]), .R(\count_value_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(rd_clk), .CE(ram_rd_en_i), .D(\count_value_i[4]_i_1__3_n_0 ), .Q(Q[4]), .R(\count_value_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(rd_clk), .CE(ram_rd_en_i), .D(\count_value_i[5]_i_1__3_n_0 ), .Q(Q[5]), .R(\count_value_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(rd_clk), .CE(ram_rd_en_i), .D(\count_value_i[6]_i_1__3_n_0 ), .Q(Q[6]), .R(\count_value_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(rd_clk), .CE(ram_rd_en_i), .D(\count_value_i[7]_i_1__3_n_0 ), .Q(Q[7]), .R(\count_value_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[8] (.C(rd_clk), .CE(ram_rd_en_i), .D(\count_value_i[8]_i_1__3_n_0 ), .Q(Q[8]), .R(\count_value_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[9] (.C(rd_clk), .CE(ram_rd_en_i), .D(\count_value_i[9]_i_1__0_n_0 ), .Q(Q[9]), .R(\count_value_i_reg[9]_0 )); (* SOFT_HLUTNM = "soft_lutpair245" *) LUT4 #( .INIT(16'hFE01)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_1 (.I0(Q[8]), .I1(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0 ), .I2(Q[7]), .I3(Q[9]), .O(src_in_bin[8])); (* SOFT_HLUTNM = "soft_lutpair242" *) LUT5 #( .INIT(32'hFFFFFFFE)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11 (.I0(Q[5]), .I1(Q[3]), .I2(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0 ), .I3(Q[4]), .I4(Q[6]), .O(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0 )); (* SOFT_HLUTNM = "soft_lutpair243" *) LUT5 #( .INIT(32'hFFFFDD4D)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12 (.I0(\grdc.rd_data_count_i_reg[7] [1]), .I1(Q[1]), .I2(\grdc.rd_data_count_i_reg[7] [0]), .I3(Q[0]), .I4(Q[2]), .O(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0 )); (* SOFT_HLUTNM = "soft_lutpair245" *) LUT3 #( .INIT(8'hA9)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_2 (.I0(Q[8]), .I1(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0 ), .I2(Q[7]), .O(src_in_bin[7])); LUT6 #( .INIT(64'hFFFFFFFE00000001)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_3 (.I0(Q[6]), .I1(Q[4]), .I2(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[7]), .O(src_in_bin[6])); (* SOFT_HLUTNM = "soft_lutpair242" *) LUT5 #( .INIT(32'hAAAAAAA9)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_4 (.I0(Q[6]), .I1(Q[4]), .I2(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0 ), .I3(Q[3]), .I4(Q[5]), .O(src_in_bin[5])); (* SOFT_HLUTNM = "soft_lutpair246" *) LUT4 #( .INIT(16'hFE01)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_5 (.I0(Q[4]), .I1(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0 ), .I2(Q[3]), .I3(Q[5]), .O(src_in_bin[4])); (* SOFT_HLUTNM = "soft_lutpair246" *) LUT3 #( .INIT(8'hA9)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_6 (.I0(Q[4]), .I1(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0 ), .I2(Q[3]), .O(src_in_bin[3])); LUT6 #( .INIT(64'hEFAAFFEF10550010)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_7 (.I0(Q[2]), .I1(Q[0]), .I2(\grdc.rd_data_count_i_reg[7] [0]), .I3(Q[1]), .I4(\grdc.rd_data_count_i_reg[7] [1]), .I5(Q[3]), .O(src_in_bin[2])); (* SOFT_HLUTNM = "soft_lutpair243" *) LUT5 #( .INIT(32'h9A55AA9A)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_8 (.I0(Q[2]), .I1(Q[0]), .I2(\grdc.rd_data_count_i_reg[7] [0]), .I3(Q[1]), .I4(\grdc.rd_data_count_i_reg[7] [1]), .O(src_in_bin[1])); (* SOFT_HLUTNM = "soft_lutpair247" *) LUT4 #( .INIT(16'h6696)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_9 (.I0(Q[1]), .I1(\grdc.rd_data_count_i_reg[7] [1]), .I2(\grdc.rd_data_count_i_reg[7] [0]), .I3(Q[0]), .O(src_in_bin[0])); LUT5 #( .INIT(32'hAABA5545)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10 (.I0(ram_empty_i), .I1(rd_en), .I2(\count_value_i_reg[0]_0 [1]), .I3(\count_value_i_reg[0]_0 [0]), .I4(Q[0]), .O(\count_value_i_reg[7]_0 [0])); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3 (.I0(Q[7]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [7]), .O(\count_value_i_reg[7]_0 [7])); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4 (.I0(Q[6]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [6]), .O(\count_value_i_reg[7]_0 [6])); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5 (.I0(Q[5]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [5]), .O(\count_value_i_reg[7]_0 [5])); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6 (.I0(Q[4]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [4]), .O(\count_value_i_reg[7]_0 [4])); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7 (.I0(Q[3]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [3]), .O(\count_value_i_reg[7]_0 [3])); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8 (.I0(Q[2]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [2]), .O(\count_value_i_reg[7]_0 [2])); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9 (.I0(Q[1]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [1]), .O(\count_value_i_reg[7]_0 [1])); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_5 (.I0(Q[1]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [1]), .I2(Q[0]), .I3(\gen_pf_ic_rc.ram_empty_i_reg [0]), .I4(Q[2]), .I5(\gen_pf_ic_rc.ram_empty_i_reg [2]), .O(\count_value_i_reg[1]_0 )); LUT6 #( .INIT(64'h8200008200000000)) \gen_pf_ic_rc.ram_empty_i_i_6 (.I0(\gen_pf_ic_rc.ram_empty_i_i_7_n_0 ), .I1(\gen_pf_ic_rc.ram_empty_i_reg [7]), .I2(Q[7]), .I3(Q[8]), .I4(\gen_pf_ic_rc.ram_empty_i_reg [8]), .I5(\gen_pf_ic_rc.ram_empty_i_i_8_n_0 ), .O(\reg_out_i_reg[7] )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.ram_empty_i_i_7 (.I0(Q[6]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [6]), .O(\gen_pf_ic_rc.ram_empty_i_i_7_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_8 (.I0(Q[4]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [4]), .I2(Q[3]), .I3(\gen_pf_ic_rc.ram_empty_i_reg [3]), .I4(Q[5]), .I5(\gen_pf_ic_rc.ram_empty_i_reg [5]), .O(\gen_pf_ic_rc.ram_empty_i_i_8_n_0 )); LUT4 #( .INIT(16'h00FB)) \gen_sdpram.xpm_memory_base_inst_i_2 (.I0(\count_value_i_reg[0]_0 [0]), .I1(\count_value_i_reg[0]_0 [1]), .I2(rd_en), .I3(ram_empty_i), .O(ram_rd_en_i)); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_10 (.I0(Q[6]), .I1(\grdc.rd_data_count_i_reg[9]_0 [6]), .I2(Q[7]), .I3(\grdc.rd_data_count_i_reg[9]_0 [7]), .O(\grdc.rd_data_count_i[7]_i_10_n_0 )); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_11 (.I0(Q[5]), .I1(\grdc.rd_data_count_i_reg[9]_0 [5]), .I2(Q[6]), .I3(\grdc.rd_data_count_i_reg[9]_0 [6]), .O(\grdc.rd_data_count_i[7]_i_11_n_0 )); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_12 (.I0(Q[4]), .I1(\grdc.rd_data_count_i_reg[9]_0 [4]), .I2(Q[5]), .I3(\grdc.rd_data_count_i_reg[9]_0 [5]), .O(\grdc.rd_data_count_i[7]_i_12_n_0 )); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_13 (.I0(Q[3]), .I1(\grdc.rd_data_count_i_reg[9]_0 [3]), .I2(Q[4]), .I3(\grdc.rd_data_count_i_reg[9]_0 [4]), .O(\grdc.rd_data_count_i[7]_i_13_n_0 )); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_14 (.I0(Q[2]), .I1(\grdc.rd_data_count_i_reg[9]_0 [2]), .I2(Q[3]), .I3(\grdc.rd_data_count_i_reg[9]_0 [3]), .O(\grdc.rd_data_count_i[7]_i_14_n_0 )); LUT5 #( .INIT(32'h2BD4D42B)) \grdc.rd_data_count_i[7]_i_15 (.I0(Q[1]), .I1(\grdc.rd_data_count_i_reg[7] [1]), .I2(\grdc.rd_data_count_i_reg[9]_0 [1]), .I3(Q[2]), .I4(\grdc.rd_data_count_i_reg[9]_0 [2]), .O(\grdc.rd_data_count_i[7]_i_15_n_0 )); LUT5 #( .INIT(32'hD22D2DD2)) \grdc.rd_data_count_i[7]_i_16 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .I2(\grdc.rd_data_count_i_reg[9]_0 [1]), .I3(\grdc.rd_data_count_i_reg[7] [1]), .I4(Q[1]), .O(\grdc.rd_data_count_i[7]_i_16_n_0 )); LUT3 #( .INIT(8'h96)) \grdc.rd_data_count_i[7]_i_17 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .I2(\grdc.rd_data_count_i_reg[9]_0 [0]), .O(\grdc.rd_data_count_i[7]_i_17_n_0 )); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[9]_i_5 (.I0(Q[7]), .I1(\grdc.rd_data_count_i_reg[9]_0 [7]), .I2(Q[8]), .I3(\grdc.rd_data_count_i_reg[9]_0 [8]), .O(\grdc.rd_data_count_i[9]_i_5_n_0 )); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY8 \grdc.rd_data_count_i_reg[7]_i_1 (.CI(1'b0), .CI_TOP(1'b0), .CO({\grdc.rd_data_count_i_reg[7]_i_1_n_0 ,\grdc.rd_data_count_i_reg[7]_i_1_n_1 ,\grdc.rd_data_count_i_reg[7]_i_1_n_2 ,\grdc.rd_data_count_i_reg[7]_i_1_n_3 ,\grdc.rd_data_count_i_reg[7]_i_1_n_4 ,\grdc.rd_data_count_i_reg[7]_i_1_n_5 ,\grdc.rd_data_count_i_reg[7]_i_1_n_6 ,\grdc.rd_data_count_i_reg[7]_i_1_n_7 }), .DI(DI), .O({D[6:0],\NLW_grdc.rd_data_count_i_reg[7]_i_1_O_UNCONNECTED [0]}), .S({\grdc.rd_data_count_i[7]_i_10_n_0 ,\grdc.rd_data_count_i[7]_i_11_n_0 ,\grdc.rd_data_count_i[7]_i_12_n_0 ,\grdc.rd_data_count_i[7]_i_13_n_0 ,\grdc.rd_data_count_i[7]_i_14_n_0 ,\grdc.rd_data_count_i[7]_i_15_n_0 ,\grdc.rd_data_count_i[7]_i_16_n_0 ,\grdc.rd_data_count_i[7]_i_17_n_0 })); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY8 \grdc.rd_data_count_i_reg[9]_i_2 (.CI(\grdc.rd_data_count_i_reg[7]_i_1_n_0 ), .CI_TOP(1'b0), .CO({\NLW_grdc.rd_data_count_i_reg[9]_i_2_CO_UNCONNECTED [7:1],\grdc.rd_data_count_i_reg[9]_i_2_n_7 }), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\grdc.rd_data_count_i_reg[9] }), .O({\NLW_grdc.rd_data_count_i_reg[9]_i_2_O_UNCONNECTED [7:2],D[8:7]}), .S({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,S,\grdc.rd_data_count_i[9]_i_5_n_0 })); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module axi_chip2chip_64B66B_xpm_counter_updn__parameterized3_12 (Q, D, wr_pntr_plus1_pf_carry, wr_en, \count_value_i_reg[5]_0 , wrst_busy, rst_d1, \gwdc.wr_data_count_i_reg[9] , wr_clk); output [9:0]Q; output [8:0]D; input wr_pntr_plus1_pf_carry; input wr_en; input \count_value_i_reg[5]_0 ; input wrst_busy; input rst_d1; input [9:0]\gwdc.wr_data_count_i_reg[9] ; input wr_clk; wire [8:0]D; wire [9:0]Q; wire \count_value_i[0]_i_1__1_n_0 ; wire \count_value_i[1]_i_1__1_n_0 ; wire \count_value_i[2]_i_1__1_n_0 ; wire \count_value_i[3]_i_1__1_n_0 ; wire \count_value_i[4]_i_1__1_n_0 ; wire \count_value_i[5]_i_1_n_0 ; wire \count_value_i[6]_i_1_n_0 ; wire \count_value_i[6]_i_2_n_0 ; wire \count_value_i[7]_i_1_n_0 ; wire \count_value_i[8]_i_1_n_0 ; wire \count_value_i[9]_i_1_n_0 ; wire \count_value_i[9]_i_2_n_0 ; wire \count_value_i_reg[5]_0 ; wire \gwdc.wr_data_count_i[7]_i_2_n_0 ; wire \gwdc.wr_data_count_i[7]_i_3_n_0 ; wire \gwdc.wr_data_count_i[7]_i_4_n_0 ; wire \gwdc.wr_data_count_i[7]_i_5_n_0 ; wire \gwdc.wr_data_count_i[7]_i_6_n_0 ; wire \gwdc.wr_data_count_i[7]_i_7_n_0 ; wire \gwdc.wr_data_count_i[7]_i_8_n_0 ; wire \gwdc.wr_data_count_i[7]_i_9_n_0 ; wire \gwdc.wr_data_count_i[9]_i_2_n_0 ; wire \gwdc.wr_data_count_i[9]_i_3_n_0 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_0 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_1 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_2 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_3 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_4 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_5 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_6 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_7 ; wire [9:0]\gwdc.wr_data_count_i_reg[9] ; wire \gwdc.wr_data_count_i_reg[9]_i_1_n_7 ; wire rst_d1; wire wr_clk; wire wr_en; wire wr_pntr_plus1_pf_carry; wire wrst_busy; wire [0:0]\NLW_gwdc.wr_data_count_i_reg[7]_i_1_O_UNCONNECTED ; wire [7:1]\NLW_gwdc.wr_data_count_i_reg[9]_i_1_CO_UNCONNECTED ; wire [7:2]\NLW_gwdc.wr_data_count_i_reg[9]_i_1_O_UNCONNECTED ; LUT1 #( .INIT(2'h1)) \count_value_i[0]_i_1__1 (.I0(Q[0]), .O(\count_value_i[0]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair193" *) LUT2 #( .INIT(4'h6)) \count_value_i[1]_i_1__1 (.I0(Q[0]), .I1(Q[1]), .O(\count_value_i[1]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair193" *) LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1__1 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair192" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1__1 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair192" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1__1 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1__1_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1 (.I0(Q[3]), .I1(\count_value_i[6]_i_2_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000800000000)) \count_value_i[6]_i_2 (.I0(Q[1]), .I1(wr_en), .I2(\count_value_i_reg[5]_0 ), .I3(wrst_busy), .I4(rst_d1), .I5(Q[0]), .O(\count_value_i[6]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair191" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1 (.I0(Q[5]), .I1(\count_value_i[9]_i_2_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair191" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[8]_i_1 (.I0(Q[6]), .I1(\count_value_i[9]_i_2_n_0 ), .I2(Q[5]), .I3(Q[7]), .I4(Q[8]), .O(\count_value_i[8]_i_1_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[9]_i_1 (.I0(Q[7]), .I1(Q[5]), .I2(\count_value_i[9]_i_2_n_0 ), .I3(Q[6]), .I4(Q[8]), .I5(Q[9]), .O(\count_value_i[9]_i_1_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[9]_i_2 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(wr_pntr_plus1_pf_carry), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[9]_i_2_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[0]_i_1__1_n_0 ), .Q(Q[0]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[1]_i_1__1_n_0 ), .Q(Q[1]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[2]_i_1__1_n_0 ), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[3]_i_1__1_n_0 ), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[4]_i_1__1_n_0 ), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[5]_i_1_n_0 ), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[6]_i_1_n_0 ), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[7]_i_1_n_0 ), .Q(Q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[8] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[8]_i_1_n_0 ), .Q(Q[8]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[9] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[9]_i_1_n_0 ), .Q(Q[9]), .R(wrst_busy)); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_2 (.I0(Q[7]), .I1(\gwdc.wr_data_count_i_reg[9] [7]), .O(\gwdc.wr_data_count_i[7]_i_2_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_3 (.I0(Q[6]), .I1(\gwdc.wr_data_count_i_reg[9] [6]), .O(\gwdc.wr_data_count_i[7]_i_3_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_4 (.I0(Q[5]), .I1(\gwdc.wr_data_count_i_reg[9] [5]), .O(\gwdc.wr_data_count_i[7]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_5 (.I0(Q[4]), .I1(\gwdc.wr_data_count_i_reg[9] [4]), .O(\gwdc.wr_data_count_i[7]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_6 (.I0(Q[3]), .I1(\gwdc.wr_data_count_i_reg[9] [3]), .O(\gwdc.wr_data_count_i[7]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_7 (.I0(Q[2]), .I1(\gwdc.wr_data_count_i_reg[9] [2]), .O(\gwdc.wr_data_count_i[7]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_8 (.I0(Q[1]), .I1(\gwdc.wr_data_count_i_reg[9] [1]), .O(\gwdc.wr_data_count_i[7]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_9 (.I0(Q[0]), .I1(\gwdc.wr_data_count_i_reg[9] [0]), .O(\gwdc.wr_data_count_i[7]_i_9_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[9]_i_2 (.I0(Q[9]), .I1(\gwdc.wr_data_count_i_reg[9] [9]), .O(\gwdc.wr_data_count_i[9]_i_2_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[9]_i_3 (.I0(Q[8]), .I1(\gwdc.wr_data_count_i_reg[9] [8]), .O(\gwdc.wr_data_count_i[9]_i_3_n_0 )); (* ADDER_THRESHOLD = "35" *) CARRY8 \gwdc.wr_data_count_i_reg[7]_i_1 (.CI(1'b1), .CI_TOP(1'b0), .CO({\gwdc.wr_data_count_i_reg[7]_i_1_n_0 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_1 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_2 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_3 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_4 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_5 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_6 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_7 }), .DI(Q[7:0]), .O({D[6:0],\NLW_gwdc.wr_data_count_i_reg[7]_i_1_O_UNCONNECTED [0]}), .S({\gwdc.wr_data_count_i[7]_i_2_n_0 ,\gwdc.wr_data_count_i[7]_i_3_n_0 ,\gwdc.wr_data_count_i[7]_i_4_n_0 ,\gwdc.wr_data_count_i[7]_i_5_n_0 ,\gwdc.wr_data_count_i[7]_i_6_n_0 ,\gwdc.wr_data_count_i[7]_i_7_n_0 ,\gwdc.wr_data_count_i[7]_i_8_n_0 ,\gwdc.wr_data_count_i[7]_i_9_n_0 })); (* ADDER_THRESHOLD = "35" *) CARRY8 \gwdc.wr_data_count_i_reg[9]_i_1 (.CI(\gwdc.wr_data_count_i_reg[7]_i_1_n_0 ), .CI_TOP(1'b0), .CO({\NLW_gwdc.wr_data_count_i_reg[9]_i_1_CO_UNCONNECTED [7:1],\gwdc.wr_data_count_i_reg[9]_i_1_n_7 }), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,Q[8]}), .O({\NLW_gwdc.wr_data_count_i_reg[9]_i_1_O_UNCONNECTED [7:2],D[8:7]}), .S({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\gwdc.wr_data_count_i[9]_i_2_n_0 ,\gwdc.wr_data_count_i[9]_i_3_n_0 })); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module axi_chip2chip_64B66B_xpm_counter_updn__parameterized3_2 (Q, D, wr_pntr_plus1_pf_carry, wr_en, \count_value_i_reg[5]_0 , wrst_busy, rst_d1, \gwdc.wr_data_count_i_reg[9] , wr_clk); output [9:0]Q; output [8:0]D; input wr_pntr_plus1_pf_carry; input wr_en; input \count_value_i_reg[5]_0 ; input wrst_busy; input rst_d1; input [9:0]\gwdc.wr_data_count_i_reg[9] ; input wr_clk; wire [8:0]D; wire [9:0]Q; wire \count_value_i[0]_i_1__1_n_0 ; wire \count_value_i[1]_i_1__1_n_0 ; wire \count_value_i[2]_i_1__1_n_0 ; wire \count_value_i[3]_i_1__1_n_0 ; wire \count_value_i[4]_i_1__1_n_0 ; wire \count_value_i[5]_i_1_n_0 ; wire \count_value_i[6]_i_1_n_0 ; wire \count_value_i[6]_i_2_n_0 ; wire \count_value_i[7]_i_1_n_0 ; wire \count_value_i[8]_i_1_n_0 ; wire \count_value_i[9]_i_1_n_0 ; wire \count_value_i[9]_i_2_n_0 ; wire \count_value_i_reg[5]_0 ; wire \gwdc.wr_data_count_i[7]_i_2_n_0 ; wire \gwdc.wr_data_count_i[7]_i_3_n_0 ; wire \gwdc.wr_data_count_i[7]_i_4_n_0 ; wire \gwdc.wr_data_count_i[7]_i_5_n_0 ; wire \gwdc.wr_data_count_i[7]_i_6_n_0 ; wire \gwdc.wr_data_count_i[7]_i_7_n_0 ; wire \gwdc.wr_data_count_i[7]_i_8_n_0 ; wire \gwdc.wr_data_count_i[7]_i_9_n_0 ; wire \gwdc.wr_data_count_i[9]_i_2_n_0 ; wire \gwdc.wr_data_count_i[9]_i_3_n_0 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_0 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_1 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_2 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_3 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_4 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_5 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_6 ; wire \gwdc.wr_data_count_i_reg[7]_i_1_n_7 ; wire [9:0]\gwdc.wr_data_count_i_reg[9] ; wire \gwdc.wr_data_count_i_reg[9]_i_1_n_7 ; wire rst_d1; wire wr_clk; wire wr_en; wire wr_pntr_plus1_pf_carry; wire wrst_busy; wire [0:0]\NLW_gwdc.wr_data_count_i_reg[7]_i_1_O_UNCONNECTED ; wire [7:1]\NLW_gwdc.wr_data_count_i_reg[9]_i_1_CO_UNCONNECTED ; wire [7:2]\NLW_gwdc.wr_data_count_i_reg[9]_i_1_O_UNCONNECTED ; LUT1 #( .INIT(2'h1)) \count_value_i[0]_i_1__1 (.I0(Q[0]), .O(\count_value_i[0]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair253" *) LUT2 #( .INIT(4'h6)) \count_value_i[1]_i_1__1 (.I0(Q[0]), .I1(Q[1]), .O(\count_value_i[1]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair253" *) LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1__1 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair252" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1__1 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair252" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1__1 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1__1_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1 (.I0(Q[3]), .I1(\count_value_i[6]_i_2_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000800000000)) \count_value_i[6]_i_2 (.I0(Q[1]), .I1(wr_en), .I2(\count_value_i_reg[5]_0 ), .I3(wrst_busy), .I4(rst_d1), .I5(Q[0]), .O(\count_value_i[6]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair251" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1 (.I0(Q[5]), .I1(\count_value_i[9]_i_2_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair251" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[8]_i_1 (.I0(Q[6]), .I1(\count_value_i[9]_i_2_n_0 ), .I2(Q[5]), .I3(Q[7]), .I4(Q[8]), .O(\count_value_i[8]_i_1_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[9]_i_1 (.I0(Q[7]), .I1(Q[5]), .I2(\count_value_i[9]_i_2_n_0 ), .I3(Q[6]), .I4(Q[8]), .I5(Q[9]), .O(\count_value_i[9]_i_1_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[9]_i_2 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(wr_pntr_plus1_pf_carry), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[9]_i_2_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[0]_i_1__1_n_0 ), .Q(Q[0]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[1]_i_1__1_n_0 ), .Q(Q[1]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[2]_i_1__1_n_0 ), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[3]_i_1__1_n_0 ), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[4]_i_1__1_n_0 ), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[5]_i_1_n_0 ), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[6]_i_1_n_0 ), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[7]_i_1_n_0 ), .Q(Q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[8] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[8]_i_1_n_0 ), .Q(Q[8]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[9] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[9]_i_1_n_0 ), .Q(Q[9]), .R(wrst_busy)); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_2 (.I0(Q[7]), .I1(\gwdc.wr_data_count_i_reg[9] [7]), .O(\gwdc.wr_data_count_i[7]_i_2_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_3 (.I0(Q[6]), .I1(\gwdc.wr_data_count_i_reg[9] [6]), .O(\gwdc.wr_data_count_i[7]_i_3_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_4 (.I0(Q[5]), .I1(\gwdc.wr_data_count_i_reg[9] [5]), .O(\gwdc.wr_data_count_i[7]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_5 (.I0(Q[4]), .I1(\gwdc.wr_data_count_i_reg[9] [4]), .O(\gwdc.wr_data_count_i[7]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_6 (.I0(Q[3]), .I1(\gwdc.wr_data_count_i_reg[9] [3]), .O(\gwdc.wr_data_count_i[7]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_7 (.I0(Q[2]), .I1(\gwdc.wr_data_count_i_reg[9] [2]), .O(\gwdc.wr_data_count_i[7]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_8 (.I0(Q[1]), .I1(\gwdc.wr_data_count_i_reg[9] [1]), .O(\gwdc.wr_data_count_i[7]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[7]_i_9 (.I0(Q[0]), .I1(\gwdc.wr_data_count_i_reg[9] [0]), .O(\gwdc.wr_data_count_i[7]_i_9_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[9]_i_2 (.I0(Q[9]), .I1(\gwdc.wr_data_count_i_reg[9] [9]), .O(\gwdc.wr_data_count_i[9]_i_2_n_0 )); LUT2 #( .INIT(4'h9)) \gwdc.wr_data_count_i[9]_i_3 (.I0(Q[8]), .I1(\gwdc.wr_data_count_i_reg[9] [8]), .O(\gwdc.wr_data_count_i[9]_i_3_n_0 )); (* ADDER_THRESHOLD = "35" *) CARRY8 \gwdc.wr_data_count_i_reg[7]_i_1 (.CI(1'b1), .CI_TOP(1'b0), .CO({\gwdc.wr_data_count_i_reg[7]_i_1_n_0 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_1 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_2 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_3 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_4 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_5 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_6 ,\gwdc.wr_data_count_i_reg[7]_i_1_n_7 }), .DI(Q[7:0]), .O({D[6:0],\NLW_gwdc.wr_data_count_i_reg[7]_i_1_O_UNCONNECTED [0]}), .S({\gwdc.wr_data_count_i[7]_i_2_n_0 ,\gwdc.wr_data_count_i[7]_i_3_n_0 ,\gwdc.wr_data_count_i[7]_i_4_n_0 ,\gwdc.wr_data_count_i[7]_i_5_n_0 ,\gwdc.wr_data_count_i[7]_i_6_n_0 ,\gwdc.wr_data_count_i[7]_i_7_n_0 ,\gwdc.wr_data_count_i[7]_i_8_n_0 ,\gwdc.wr_data_count_i[7]_i_9_n_0 })); (* ADDER_THRESHOLD = "35" *) CARRY8 \gwdc.wr_data_count_i_reg[9]_i_1 (.CI(\gwdc.wr_data_count_i_reg[7]_i_1_n_0 ), .CI_TOP(1'b0), .CO({\NLW_gwdc.wr_data_count_i_reg[9]_i_1_CO_UNCONNECTED [7:1],\gwdc.wr_data_count_i_reg[9]_i_1_n_7 }), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,Q[8]}), .O({\NLW_gwdc.wr_data_count_i_reg[9]_i_1_O_UNCONNECTED [7:2],D[8:7]}), .S({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\gwdc.wr_data_count_i[9]_i_2_n_0 ,\gwdc.wr_data_count_i[9]_i_3_n_0 })); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module axi_chip2chip_64B66B_xpm_counter_updn__parameterized3_9 (Q, ram_rd_en_i, \reg_out_i_reg[7] , src_in_bin, \count_value_i_reg[1]_0 , D, \count_value_i_reg[7]_0 , \count_value_i_reg[0]_0 , rd_en, ram_empty_i, \gen_pf_ic_rc.ram_empty_i_reg , \grdc.rd_data_count_i_reg[7] , DI, \grdc.rd_data_count_i_reg[9] , S, \grdc.rd_data_count_i_reg[9]_0 , \count_value_i_reg[9]_0 , rd_clk); output [9:0]Q; output ram_rd_en_i; output \reg_out_i_reg[7] ; output [8:0]src_in_bin; output \count_value_i_reg[1]_0 ; output [8:0]D; output [7:0]\count_value_i_reg[7]_0 ; input [1:0]\count_value_i_reg[0]_0 ; input rd_en; input ram_empty_i; input [8:0]\gen_pf_ic_rc.ram_empty_i_reg ; input [1:0]\grdc.rd_data_count_i_reg[7] ; input [7:0]DI; input [0:0]\grdc.rd_data_count_i_reg[9] ; input [0:0]S; input [8:0]\grdc.rd_data_count_i_reg[9]_0 ; input \count_value_i_reg[9]_0 ; input rd_clk; wire [8:0]D; wire [7:0]DI; wire [9:0]Q; wire [0:0]S; wire \count_value_i[0]_i_1__4_n_0 ; wire \count_value_i[1]_i_1__3_n_0 ; wire \count_value_i[2]_i_1__3_n_0 ; wire \count_value_i[3]_i_1__3_n_0 ; wire \count_value_i[4]_i_1__3_n_0 ; wire \count_value_i[5]_i_1__3_n_0 ; wire \count_value_i[6]_i_1__3_n_0 ; wire \count_value_i[6]_i_2__3_n_0 ; wire \count_value_i[7]_i_1__3_n_0 ; wire \count_value_i[8]_i_1__3_n_0 ; wire \count_value_i[9]_i_1__0_n_0 ; wire \count_value_i[9]_i_2__0_n_0 ; wire [1:0]\count_value_i_reg[0]_0 ; wire \count_value_i_reg[1]_0 ; wire [7:0]\count_value_i_reg[7]_0 ; wire \count_value_i_reg[9]_0 ; wire \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0 ; wire \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0 ; wire \gen_pf_ic_rc.ram_empty_i_i_7_n_0 ; wire \gen_pf_ic_rc.ram_empty_i_i_8_n_0 ; wire [8:0]\gen_pf_ic_rc.ram_empty_i_reg ; wire \grdc.rd_data_count_i[7]_i_10_n_0 ; wire \grdc.rd_data_count_i[7]_i_11_n_0 ; wire \grdc.rd_data_count_i[7]_i_12_n_0 ; wire \grdc.rd_data_count_i[7]_i_13_n_0 ; wire \grdc.rd_data_count_i[7]_i_14_n_0 ; wire \grdc.rd_data_count_i[7]_i_15_n_0 ; wire \grdc.rd_data_count_i[7]_i_16_n_0 ; wire \grdc.rd_data_count_i[7]_i_17_n_0 ; wire \grdc.rd_data_count_i[9]_i_5_n_0 ; wire [1:0]\grdc.rd_data_count_i_reg[7] ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_0 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_1 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_2 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_3 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_4 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_5 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_6 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_7 ; wire [0:0]\grdc.rd_data_count_i_reg[9] ; wire [8:0]\grdc.rd_data_count_i_reg[9]_0 ; wire \grdc.rd_data_count_i_reg[9]_i_2_n_7 ; wire ram_empty_i; wire ram_rd_en_i; wire rd_clk; wire rd_en; wire \reg_out_i_reg[7] ; wire [8:0]src_in_bin; wire [0:0]\NLW_grdc.rd_data_count_i_reg[7]_i_1_O_UNCONNECTED ; wire [7:1]\NLW_grdc.rd_data_count_i_reg[9]_i_2_CO_UNCONNECTED ; wire [7:2]\NLW_grdc.rd_data_count_i_reg[9]_i_2_O_UNCONNECTED ; LUT5 #( .INIT(32'hAABA5545)) \count_value_i[0]_i_1__4 (.I0(ram_empty_i), .I1(rd_en), .I2(\count_value_i_reg[0]_0 [1]), .I3(\count_value_i_reg[0]_0 [0]), .I4(Q[0]), .O(\count_value_i[0]_i_1__4_n_0 )); LUT5 #( .INIT(32'h04FFFB00)) \count_value_i[1]_i_1__3 (.I0(\count_value_i_reg[0]_0 [0]), .I1(\count_value_i_reg[0]_0 [1]), .I2(rd_en), .I3(Q[0]), .I4(Q[1]), .O(\count_value_i[1]_i_1__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair187" *) LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1__3 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair184" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1__3 (.I0(Q[2]), .I1(Q[1]), .I2(Q[0]), .I3(Q[3]), .O(\count_value_i[3]_i_1__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair184" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1__3 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1__3_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1__3 (.I0(Q[4]), .I1(Q[3]), .I2(Q[2]), .I3(\count_value_i[6]_i_2__3_n_0 ), .I4(Q[5]), .O(\count_value_i[5]_i_1__3_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1__3 (.I0(\count_value_i[6]_i_2__3_n_0 ), .I1(Q[2]), .I2(Q[3]), .I3(Q[4]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1__3_n_0 )); LUT6 #( .INIT(64'h0000AA8A00000000)) \count_value_i[6]_i_2__3 (.I0(Q[1]), .I1(\count_value_i_reg[0]_0 [0]), .I2(\count_value_i_reg[0]_0 [1]), .I3(rd_en), .I4(ram_empty_i), .I5(Q[0]), .O(\count_value_i[6]_i_2__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair181" *) LUT4 #( .INIT(16'hF708)) \count_value_i[7]_i_1__3 (.I0(Q[6]), .I1(Q[5]), .I2(\count_value_i[9]_i_2__0_n_0 ), .I3(Q[7]), .O(\count_value_i[7]_i_1__3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair181" *) LUT5 #( .INIT(32'hBFFF4000)) \count_value_i[8]_i_1__3 (.I0(\count_value_i[9]_i_2__0_n_0 ), .I1(Q[5]), .I2(Q[6]), .I3(Q[7]), .I4(Q[8]), .O(\count_value_i[8]_i_1__3_n_0 )); LUT6 #( .INIT(64'hFFFF7FFF00008000)) \count_value_i[9]_i_1__0 (.I0(Q[8]), .I1(Q[7]), .I2(Q[6]), .I3(Q[5]), .I4(\count_value_i[9]_i_2__0_n_0 ), .I5(Q[9]), .O(\count_value_i[9]_i_1__0_n_0 )); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) \count_value_i[9]_i_2__0 (.I0(Q[0]), .I1(ram_rd_en_i), .I2(Q[1]), .I3(Q[2]), .I4(Q[3]), .I5(Q[4]), .O(\count_value_i[9]_i_2__0_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(rd_clk), .CE(ram_rd_en_i), .D(\count_value_i[0]_i_1__4_n_0 ), .Q(Q[0]), .R(\count_value_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(rd_clk), .CE(ram_rd_en_i), .D(\count_value_i[1]_i_1__3_n_0 ), .Q(Q[1]), .R(\count_value_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(rd_clk), .CE(ram_rd_en_i), .D(\count_value_i[2]_i_1__3_n_0 ), .Q(Q[2]), .R(\count_value_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(rd_clk), .CE(ram_rd_en_i), .D(\count_value_i[3]_i_1__3_n_0 ), .Q(Q[3]), .R(\count_value_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(rd_clk), .CE(ram_rd_en_i), .D(\count_value_i[4]_i_1__3_n_0 ), .Q(Q[4]), .R(\count_value_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(rd_clk), .CE(ram_rd_en_i), .D(\count_value_i[5]_i_1__3_n_0 ), .Q(Q[5]), .R(\count_value_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(rd_clk), .CE(ram_rd_en_i), .D(\count_value_i[6]_i_1__3_n_0 ), .Q(Q[6]), .R(\count_value_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(rd_clk), .CE(ram_rd_en_i), .D(\count_value_i[7]_i_1__3_n_0 ), .Q(Q[7]), .R(\count_value_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[8] (.C(rd_clk), .CE(ram_rd_en_i), .D(\count_value_i[8]_i_1__3_n_0 ), .Q(Q[8]), .R(\count_value_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[9] (.C(rd_clk), .CE(ram_rd_en_i), .D(\count_value_i[9]_i_1__0_n_0 ), .Q(Q[9]), .R(\count_value_i_reg[9]_0 )); (* SOFT_HLUTNM = "soft_lutpair185" *) LUT4 #( .INIT(16'hFE01)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_1 (.I0(Q[8]), .I1(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0 ), .I2(Q[7]), .I3(Q[9]), .O(src_in_bin[8])); (* SOFT_HLUTNM = "soft_lutpair182" *) LUT5 #( .INIT(32'hFFFFFFFE)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11 (.I0(Q[5]), .I1(Q[3]), .I2(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0 ), .I3(Q[4]), .I4(Q[6]), .O(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0 )); (* SOFT_HLUTNM = "soft_lutpair183" *) LUT5 #( .INIT(32'hFFFFDD4D)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12 (.I0(\grdc.rd_data_count_i_reg[7] [1]), .I1(Q[1]), .I2(\grdc.rd_data_count_i_reg[7] [0]), .I3(Q[0]), .I4(Q[2]), .O(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0 )); (* SOFT_HLUTNM = "soft_lutpair185" *) LUT3 #( .INIT(8'hA9)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_2 (.I0(Q[8]), .I1(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_11_n_0 ), .I2(Q[7]), .O(src_in_bin[7])); LUT6 #( .INIT(64'hFFFFFFFE00000001)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_3 (.I0(Q[6]), .I1(Q[4]), .I2(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[7]), .O(src_in_bin[6])); (* SOFT_HLUTNM = "soft_lutpair182" *) LUT5 #( .INIT(32'hAAAAAAA9)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_4 (.I0(Q[6]), .I1(Q[4]), .I2(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0 ), .I3(Q[3]), .I4(Q[5]), .O(src_in_bin[5])); (* SOFT_HLUTNM = "soft_lutpair186" *) LUT4 #( .INIT(16'hFE01)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_5 (.I0(Q[4]), .I1(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0 ), .I2(Q[3]), .I3(Q[5]), .O(src_in_bin[4])); (* SOFT_HLUTNM = "soft_lutpair186" *) LUT3 #( .INIT(8'hA9)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_6 (.I0(Q[4]), .I1(\gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_12_n_0 ), .I2(Q[3]), .O(src_in_bin[3])); LUT6 #( .INIT(64'hEFAAFFEF10550010)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_7 (.I0(Q[2]), .I1(Q[0]), .I2(\grdc.rd_data_count_i_reg[7] [0]), .I3(Q[1]), .I4(\grdc.rd_data_count_i_reg[7] [1]), .I5(Q[3]), .O(src_in_bin[2])); (* SOFT_HLUTNM = "soft_lutpair183" *) LUT5 #( .INIT(32'h9A55AA9A)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_8 (.I0(Q[2]), .I1(Q[0]), .I2(\grdc.rd_data_count_i_reg[7] [0]), .I3(Q[1]), .I4(\grdc.rd_data_count_i_reg[7] [1]), .O(src_in_bin[1])); (* SOFT_HLUTNM = "soft_lutpair187" *) LUT4 #( .INIT(16'h6696)) \gen_cdc_pntr.rd_pntr_cdc_dc_inst_i_9 (.I0(Q[1]), .I1(\grdc.rd_data_count_i_reg[7] [1]), .I2(\grdc.rd_data_count_i_reg[7] [0]), .I3(Q[0]), .O(src_in_bin[0])); LUT5 #( .INIT(32'hAABA5545)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_10 (.I0(ram_empty_i), .I1(rd_en), .I2(\count_value_i_reg[0]_0 [1]), .I3(\count_value_i_reg[0]_0 [0]), .I4(Q[0]), .O(\count_value_i_reg[7]_0 [0])); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_3 (.I0(Q[7]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [7]), .O(\count_value_i_reg[7]_0 [7])); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_4 (.I0(Q[6]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [6]), .O(\count_value_i_reg[7]_0 [6])); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_5 (.I0(Q[5]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [5]), .O(\count_value_i_reg[7]_0 [5])); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_6 (.I0(Q[4]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [4]), .O(\count_value_i_reg[7]_0 [4])); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_7 (.I0(Q[3]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [3]), .O(\count_value_i_reg[7]_0 [3])); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_8 (.I0(Q[2]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [2]), .O(\count_value_i_reg[7]_0 [2])); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_9 (.I0(Q[1]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [1]), .O(\count_value_i_reg[7]_0 [1])); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_5 (.I0(Q[1]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [1]), .I2(Q[0]), .I3(\gen_pf_ic_rc.ram_empty_i_reg [0]), .I4(Q[2]), .I5(\gen_pf_ic_rc.ram_empty_i_reg [2]), .O(\count_value_i_reg[1]_0 )); LUT6 #( .INIT(64'h8200008200000000)) \gen_pf_ic_rc.ram_empty_i_i_6 (.I0(\gen_pf_ic_rc.ram_empty_i_i_7_n_0 ), .I1(\gen_pf_ic_rc.ram_empty_i_reg [7]), .I2(Q[7]), .I3(Q[8]), .I4(\gen_pf_ic_rc.ram_empty_i_reg [8]), .I5(\gen_pf_ic_rc.ram_empty_i_i_8_n_0 ), .O(\reg_out_i_reg[7] )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.ram_empty_i_i_7 (.I0(Q[6]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [6]), .O(\gen_pf_ic_rc.ram_empty_i_i_7_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_8 (.I0(Q[4]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [4]), .I2(Q[3]), .I3(\gen_pf_ic_rc.ram_empty_i_reg [3]), .I4(Q[5]), .I5(\gen_pf_ic_rc.ram_empty_i_reg [5]), .O(\gen_pf_ic_rc.ram_empty_i_i_8_n_0 )); LUT4 #( .INIT(16'h00FB)) \gen_sdpram.xpm_memory_base_inst_i_2 (.I0(\count_value_i_reg[0]_0 [0]), .I1(\count_value_i_reg[0]_0 [1]), .I2(rd_en), .I3(ram_empty_i), .O(ram_rd_en_i)); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_10 (.I0(Q[6]), .I1(\grdc.rd_data_count_i_reg[9]_0 [6]), .I2(Q[7]), .I3(\grdc.rd_data_count_i_reg[9]_0 [7]), .O(\grdc.rd_data_count_i[7]_i_10_n_0 )); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_11 (.I0(Q[5]), .I1(\grdc.rd_data_count_i_reg[9]_0 [5]), .I2(Q[6]), .I3(\grdc.rd_data_count_i_reg[9]_0 [6]), .O(\grdc.rd_data_count_i[7]_i_11_n_0 )); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_12 (.I0(Q[4]), .I1(\grdc.rd_data_count_i_reg[9]_0 [4]), .I2(Q[5]), .I3(\grdc.rd_data_count_i_reg[9]_0 [5]), .O(\grdc.rd_data_count_i[7]_i_12_n_0 )); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_13 (.I0(Q[3]), .I1(\grdc.rd_data_count_i_reg[9]_0 [3]), .I2(Q[4]), .I3(\grdc.rd_data_count_i_reg[9]_0 [4]), .O(\grdc.rd_data_count_i[7]_i_13_n_0 )); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[7]_i_14 (.I0(Q[2]), .I1(\grdc.rd_data_count_i_reg[9]_0 [2]), .I2(Q[3]), .I3(\grdc.rd_data_count_i_reg[9]_0 [3]), .O(\grdc.rd_data_count_i[7]_i_14_n_0 )); LUT5 #( .INIT(32'h2BD4D42B)) \grdc.rd_data_count_i[7]_i_15 (.I0(Q[1]), .I1(\grdc.rd_data_count_i_reg[7] [1]), .I2(\grdc.rd_data_count_i_reg[9]_0 [1]), .I3(Q[2]), .I4(\grdc.rd_data_count_i_reg[9]_0 [2]), .O(\grdc.rd_data_count_i[7]_i_15_n_0 )); LUT5 #( .INIT(32'hD22D2DD2)) \grdc.rd_data_count_i[7]_i_16 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .I2(\grdc.rd_data_count_i_reg[9]_0 [1]), .I3(\grdc.rd_data_count_i_reg[7] [1]), .I4(Q[1]), .O(\grdc.rd_data_count_i[7]_i_16_n_0 )); LUT3 #( .INIT(8'h96)) \grdc.rd_data_count_i[7]_i_17 (.I0(Q[0]), .I1(\grdc.rd_data_count_i_reg[7] [0]), .I2(\grdc.rd_data_count_i_reg[9]_0 [0]), .O(\grdc.rd_data_count_i[7]_i_17_n_0 )); LUT4 #( .INIT(16'hB44B)) \grdc.rd_data_count_i[9]_i_5 (.I0(Q[7]), .I1(\grdc.rd_data_count_i_reg[9]_0 [7]), .I2(Q[8]), .I3(\grdc.rd_data_count_i_reg[9]_0 [8]), .O(\grdc.rd_data_count_i[9]_i_5_n_0 )); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY8 \grdc.rd_data_count_i_reg[7]_i_1 (.CI(1'b0), .CI_TOP(1'b0), .CO({\grdc.rd_data_count_i_reg[7]_i_1_n_0 ,\grdc.rd_data_count_i_reg[7]_i_1_n_1 ,\grdc.rd_data_count_i_reg[7]_i_1_n_2 ,\grdc.rd_data_count_i_reg[7]_i_1_n_3 ,\grdc.rd_data_count_i_reg[7]_i_1_n_4 ,\grdc.rd_data_count_i_reg[7]_i_1_n_5 ,\grdc.rd_data_count_i_reg[7]_i_1_n_6 ,\grdc.rd_data_count_i_reg[7]_i_1_n_7 }), .DI(DI), .O({D[6:0],\NLW_grdc.rd_data_count_i_reg[7]_i_1_O_UNCONNECTED [0]}), .S({\grdc.rd_data_count_i[7]_i_10_n_0 ,\grdc.rd_data_count_i[7]_i_11_n_0 ,\grdc.rd_data_count_i[7]_i_12_n_0 ,\grdc.rd_data_count_i[7]_i_13_n_0 ,\grdc.rd_data_count_i[7]_i_14_n_0 ,\grdc.rd_data_count_i[7]_i_15_n_0 ,\grdc.rd_data_count_i[7]_i_16_n_0 ,\grdc.rd_data_count_i[7]_i_17_n_0 })); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY8 \grdc.rd_data_count_i_reg[9]_i_2 (.CI(\grdc.rd_data_count_i_reg[7]_i_1_n_0 ), .CI_TOP(1'b0), .CO({\NLW_grdc.rd_data_count_i_reg[9]_i_2_CO_UNCONNECTED [7:1],\grdc.rd_data_count_i_reg[9]_i_2_n_7 }), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\grdc.rd_data_count_i_reg[9] }), .O({\NLW_grdc.rd_data_count_i_reg[9]_i_2_O_UNCONNECTED [7:2],D[8:7]}), .S({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,S,\grdc.rd_data_count_i[9]_i_5_n_0 })); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module axi_chip2chip_64B66B_xpm_counter_updn__parameterized4 (ram_empty_i0, E, \gen_pf_ic_rc.ram_empty_i_reg , \gen_pf_ic_rc.ram_empty_i_reg_0 , Q, rd_en, ram_empty_i, \gen_pf_ic_rc.ram_empty_i_reg_1 , \count_value_i_reg[0]_0 , rd_clk); output ram_empty_i0; input [0:0]E; input \gen_pf_ic_rc.ram_empty_i_reg ; input \gen_pf_ic_rc.ram_empty_i_reg_0 ; input [1:0]Q; input rd_en; input ram_empty_i; input [8:0]\gen_pf_ic_rc.ram_empty_i_reg_1 ; input \count_value_i_reg[0]_0 ; input rd_clk; wire [0:0]E; wire [1:0]Q; wire \count_value_i[0]_i_1__3_n_0 ; wire \count_value_i[1]_i_1__2_n_0 ; wire \count_value_i[2]_i_1__2_n_0 ; wire \count_value_i[3]_i_1__2_n_0 ; wire \count_value_i[4]_i_1__2_n_0 ; wire \count_value_i[5]_i_1__2_n_0 ; wire \count_value_i[6]_i_1__2_n_0 ; wire \count_value_i[6]_i_2__2_n_0 ; wire \count_value_i[7]_i_1__2_n_0 ; wire \count_value_i[8]_i_1__2_n_0 ; wire \count_value_i[8]_i_2__1_n_0 ; wire \count_value_i_reg[0]_0 ; wire \count_value_i_reg_n_0_[0] ; wire \count_value_i_reg_n_0_[1] ; wire \count_value_i_reg_n_0_[2] ; wire \count_value_i_reg_n_0_[3] ; wire \count_value_i_reg_n_0_[4] ; wire \count_value_i_reg_n_0_[5] ; wire \count_value_i_reg_n_0_[6] ; wire \count_value_i_reg_n_0_[7] ; wire \count_value_i_reg_n_0_[8] ; wire \gen_pf_ic_rc.ram_empty_i_i_2_n_0 ; wire \gen_pf_ic_rc.ram_empty_i_i_3_n_0 ; wire \gen_pf_ic_rc.ram_empty_i_i_4_n_0 ; wire \gen_pf_ic_rc.ram_empty_i_reg ; wire \gen_pf_ic_rc.ram_empty_i_reg_0 ; wire [8:0]\gen_pf_ic_rc.ram_empty_i_reg_1 ; wire ram_empty_i; wire ram_empty_i0; wire rd_clk; wire rd_en; LUT4 #( .INIT(16'h04FB)) \count_value_i[0]_i_1__3 (.I0(rd_en), .I1(Q[1]), .I2(Q[0]), .I3(\count_value_i_reg_n_0_[0] ), .O(\count_value_i[0]_i_1__3_n_0 )); LUT5 #( .INIT(32'h04FFFB00)) \count_value_i[1]_i_1__2 (.I0(Q[0]), .I1(Q[1]), .I2(rd_en), .I3(\count_value_i_reg_n_0_[0] ), .I4(\count_value_i_reg_n_0_[1] ), .O(\count_value_i[1]_i_1__2_n_0 )); LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1__2 (.I0(\count_value_i_reg_n_0_[0] ), .I1(\count_value_i_reg_n_0_[1] ), .I2(\count_value_i_reg_n_0_[2] ), .O(\count_value_i[2]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair249" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1__2 (.I0(\count_value_i_reg_n_0_[2] ), .I1(\count_value_i_reg_n_0_[1] ), .I2(\count_value_i_reg_n_0_[0] ), .I3(\count_value_i_reg_n_0_[3] ), .O(\count_value_i[3]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair249" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1__2 (.I0(\count_value_i_reg_n_0_[0] ), .I1(\count_value_i_reg_n_0_[1] ), .I2(\count_value_i_reg_n_0_[2] ), .I3(\count_value_i_reg_n_0_[3] ), .I4(\count_value_i_reg_n_0_[4] ), .O(\count_value_i[4]_i_1__2_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1__2 (.I0(\count_value_i_reg_n_0_[4] ), .I1(\count_value_i_reg_n_0_[3] ), .I2(\count_value_i_reg_n_0_[2] ), .I3(\count_value_i[6]_i_2__2_n_0 ), .I4(\count_value_i_reg_n_0_[5] ), .O(\count_value_i[5]_i_1__2_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1__2 (.I0(\count_value_i[6]_i_2__2_n_0 ), .I1(\count_value_i_reg_n_0_[2] ), .I2(\count_value_i_reg_n_0_[3] ), .I3(\count_value_i_reg_n_0_[4] ), .I4(\count_value_i_reg_n_0_[5] ), .I5(\count_value_i_reg_n_0_[6] ), .O(\count_value_i[6]_i_1__2_n_0 )); LUT6 #( .INIT(64'h0000AA8A00000000)) \count_value_i[6]_i_2__2 (.I0(\count_value_i_reg_n_0_[1] ), .I1(Q[0]), .I2(Q[1]), .I3(rd_en), .I4(ram_empty_i), .I5(\count_value_i_reg_n_0_[0] ), .O(\count_value_i[6]_i_2__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair248" *) LUT4 #( .INIT(16'hF708)) \count_value_i[7]_i_1__2 (.I0(\count_value_i_reg_n_0_[6] ), .I1(\count_value_i_reg_n_0_[5] ), .I2(\count_value_i[8]_i_2__1_n_0 ), .I3(\count_value_i_reg_n_0_[7] ), .O(\count_value_i[7]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair248" *) LUT5 #( .INIT(32'hDFFF2000)) \count_value_i[8]_i_1__2 (.I0(\count_value_i_reg_n_0_[7] ), .I1(\count_value_i[8]_i_2__1_n_0 ), .I2(\count_value_i_reg_n_0_[5] ), .I3(\count_value_i_reg_n_0_[6] ), .I4(\count_value_i_reg_n_0_[8] ), .O(\count_value_i[8]_i_1__2_n_0 )); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) \count_value_i[8]_i_2__1 (.I0(\count_value_i_reg_n_0_[0] ), .I1(E), .I2(\count_value_i_reg_n_0_[1] ), .I3(\count_value_i_reg_n_0_[2] ), .I4(\count_value_i_reg_n_0_[3] ), .I5(\count_value_i_reg_n_0_[4] ), .O(\count_value_i[8]_i_2__1_n_0 )); FDSE #( .INIT(1'b1)) \count_value_i_reg[0] (.C(rd_clk), .CE(E), .D(\count_value_i[0]_i_1__3_n_0 ), .Q(\count_value_i_reg_n_0_[0] ), .S(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(rd_clk), .CE(E), .D(\count_value_i[1]_i_1__2_n_0 ), .Q(\count_value_i_reg_n_0_[1] ), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(rd_clk), .CE(E), .D(\count_value_i[2]_i_1__2_n_0 ), .Q(\count_value_i_reg_n_0_[2] ), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(rd_clk), .CE(E), .D(\count_value_i[3]_i_1__2_n_0 ), .Q(\count_value_i_reg_n_0_[3] ), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(rd_clk), .CE(E), .D(\count_value_i[4]_i_1__2_n_0 ), .Q(\count_value_i_reg_n_0_[4] ), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(rd_clk), .CE(E), .D(\count_value_i[5]_i_1__2_n_0 ), .Q(\count_value_i_reg_n_0_[5] ), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(rd_clk), .CE(E), .D(\count_value_i[6]_i_1__2_n_0 ), .Q(\count_value_i_reg_n_0_[6] ), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(rd_clk), .CE(E), .D(\count_value_i[7]_i_1__2_n_0 ), .Q(\count_value_i_reg_n_0_[7] ), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[8] (.C(rd_clk), .CE(E), .D(\count_value_i[8]_i_1__2_n_0 ), .Q(\count_value_i_reg_n_0_[8] ), .R(\count_value_i_reg[0]_0 )); LUT6 #( .INIT(64'hFFFF800080008000)) \gen_pf_ic_rc.ram_empty_i_i_1 (.I0(\gen_pf_ic_rc.ram_empty_i_i_2_n_0 ), .I1(E), .I2(\gen_pf_ic_rc.ram_empty_i_i_3_n_0 ), .I3(\gen_pf_ic_rc.ram_empty_i_i_4_n_0 ), .I4(\gen_pf_ic_rc.ram_empty_i_reg ), .I5(\gen_pf_ic_rc.ram_empty_i_reg_0 ), .O(ram_empty_i0)); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_2 (.I0(\count_value_i_reg_n_0_[7] ), .I1(\gen_pf_ic_rc.ram_empty_i_reg_1 [7]), .I2(\count_value_i_reg_n_0_[6] ), .I3(\gen_pf_ic_rc.ram_empty_i_reg_1 [6]), .I4(\gen_pf_ic_rc.ram_empty_i_reg_1 [8]), .I5(\count_value_i_reg_n_0_[8] ), .O(\gen_pf_ic_rc.ram_empty_i_i_2_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_3 (.I0(\count_value_i_reg_n_0_[1] ), .I1(\gen_pf_ic_rc.ram_empty_i_reg_1 [1]), .I2(\count_value_i_reg_n_0_[0] ), .I3(\gen_pf_ic_rc.ram_empty_i_reg_1 [0]), .I4(\gen_pf_ic_rc.ram_empty_i_reg_1 [2]), .I5(\count_value_i_reg_n_0_[2] ), .O(\gen_pf_ic_rc.ram_empty_i_i_3_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_4 (.I0(\count_value_i_reg_n_0_[4] ), .I1(\gen_pf_ic_rc.ram_empty_i_reg_1 [4]), .I2(\count_value_i_reg_n_0_[3] ), .I3(\gen_pf_ic_rc.ram_empty_i_reg_1 [3]), .I4(\gen_pf_ic_rc.ram_empty_i_reg_1 [5]), .I5(\count_value_i_reg_n_0_[5] ), .O(\gen_pf_ic_rc.ram_empty_i_i_4_n_0 )); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module axi_chip2chip_64B66B_xpm_counter_updn__parameterized4_10 (ram_empty_i0, E, \gen_pf_ic_rc.ram_empty_i_reg , \gen_pf_ic_rc.ram_empty_i_reg_0 , Q, rd_en, ram_empty_i, \gen_pf_ic_rc.ram_empty_i_reg_1 , \count_value_i_reg[0]_0 , rd_clk); output ram_empty_i0; input [0:0]E; input \gen_pf_ic_rc.ram_empty_i_reg ; input \gen_pf_ic_rc.ram_empty_i_reg_0 ; input [1:0]Q; input rd_en; input ram_empty_i; input [8:0]\gen_pf_ic_rc.ram_empty_i_reg_1 ; input \count_value_i_reg[0]_0 ; input rd_clk; wire [0:0]E; wire [1:0]Q; wire \count_value_i[0]_i_1__3_n_0 ; wire \count_value_i[1]_i_1__2_n_0 ; wire \count_value_i[2]_i_1__2_n_0 ; wire \count_value_i[3]_i_1__2_n_0 ; wire \count_value_i[4]_i_1__2_n_0 ; wire \count_value_i[5]_i_1__2_n_0 ; wire \count_value_i[6]_i_1__2_n_0 ; wire \count_value_i[6]_i_2__2_n_0 ; wire \count_value_i[7]_i_1__2_n_0 ; wire \count_value_i[8]_i_1__2_n_0 ; wire \count_value_i[8]_i_2__1_n_0 ; wire \count_value_i_reg[0]_0 ; wire \count_value_i_reg_n_0_[0] ; wire \count_value_i_reg_n_0_[1] ; wire \count_value_i_reg_n_0_[2] ; wire \count_value_i_reg_n_0_[3] ; wire \count_value_i_reg_n_0_[4] ; wire \count_value_i_reg_n_0_[5] ; wire \count_value_i_reg_n_0_[6] ; wire \count_value_i_reg_n_0_[7] ; wire \count_value_i_reg_n_0_[8] ; wire \gen_pf_ic_rc.ram_empty_i_i_2_n_0 ; wire \gen_pf_ic_rc.ram_empty_i_i_3_n_0 ; wire \gen_pf_ic_rc.ram_empty_i_i_4_n_0 ; wire \gen_pf_ic_rc.ram_empty_i_reg ; wire \gen_pf_ic_rc.ram_empty_i_reg_0 ; wire [8:0]\gen_pf_ic_rc.ram_empty_i_reg_1 ; wire ram_empty_i; wire ram_empty_i0; wire rd_clk; wire rd_en; LUT4 #( .INIT(16'h04FB)) \count_value_i[0]_i_1__3 (.I0(rd_en), .I1(Q[1]), .I2(Q[0]), .I3(\count_value_i_reg_n_0_[0] ), .O(\count_value_i[0]_i_1__3_n_0 )); LUT5 #( .INIT(32'h04FFFB00)) \count_value_i[1]_i_1__2 (.I0(Q[0]), .I1(Q[1]), .I2(rd_en), .I3(\count_value_i_reg_n_0_[0] ), .I4(\count_value_i_reg_n_0_[1] ), .O(\count_value_i[1]_i_1__2_n_0 )); LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1__2 (.I0(\count_value_i_reg_n_0_[0] ), .I1(\count_value_i_reg_n_0_[1] ), .I2(\count_value_i_reg_n_0_[2] ), .O(\count_value_i[2]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair189" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1__2 (.I0(\count_value_i_reg_n_0_[2] ), .I1(\count_value_i_reg_n_0_[1] ), .I2(\count_value_i_reg_n_0_[0] ), .I3(\count_value_i_reg_n_0_[3] ), .O(\count_value_i[3]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair189" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1__2 (.I0(\count_value_i_reg_n_0_[0] ), .I1(\count_value_i_reg_n_0_[1] ), .I2(\count_value_i_reg_n_0_[2] ), .I3(\count_value_i_reg_n_0_[3] ), .I4(\count_value_i_reg_n_0_[4] ), .O(\count_value_i[4]_i_1__2_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1__2 (.I0(\count_value_i_reg_n_0_[4] ), .I1(\count_value_i_reg_n_0_[3] ), .I2(\count_value_i_reg_n_0_[2] ), .I3(\count_value_i[6]_i_2__2_n_0 ), .I4(\count_value_i_reg_n_0_[5] ), .O(\count_value_i[5]_i_1__2_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1__2 (.I0(\count_value_i[6]_i_2__2_n_0 ), .I1(\count_value_i_reg_n_0_[2] ), .I2(\count_value_i_reg_n_0_[3] ), .I3(\count_value_i_reg_n_0_[4] ), .I4(\count_value_i_reg_n_0_[5] ), .I5(\count_value_i_reg_n_0_[6] ), .O(\count_value_i[6]_i_1__2_n_0 )); LUT6 #( .INIT(64'h0000AA8A00000000)) \count_value_i[6]_i_2__2 (.I0(\count_value_i_reg_n_0_[1] ), .I1(Q[0]), .I2(Q[1]), .I3(rd_en), .I4(ram_empty_i), .I5(\count_value_i_reg_n_0_[0] ), .O(\count_value_i[6]_i_2__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair188" *) LUT4 #( .INIT(16'hF708)) \count_value_i[7]_i_1__2 (.I0(\count_value_i_reg_n_0_[6] ), .I1(\count_value_i_reg_n_0_[5] ), .I2(\count_value_i[8]_i_2__1_n_0 ), .I3(\count_value_i_reg_n_0_[7] ), .O(\count_value_i[7]_i_1__2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair188" *) LUT5 #( .INIT(32'hDFFF2000)) \count_value_i[8]_i_1__2 (.I0(\count_value_i_reg_n_0_[7] ), .I1(\count_value_i[8]_i_2__1_n_0 ), .I2(\count_value_i_reg_n_0_[5] ), .I3(\count_value_i_reg_n_0_[6] ), .I4(\count_value_i_reg_n_0_[8] ), .O(\count_value_i[8]_i_1__2_n_0 )); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) \count_value_i[8]_i_2__1 (.I0(\count_value_i_reg_n_0_[0] ), .I1(E), .I2(\count_value_i_reg_n_0_[1] ), .I3(\count_value_i_reg_n_0_[2] ), .I4(\count_value_i_reg_n_0_[3] ), .I5(\count_value_i_reg_n_0_[4] ), .O(\count_value_i[8]_i_2__1_n_0 )); FDSE #( .INIT(1'b1)) \count_value_i_reg[0] (.C(rd_clk), .CE(E), .D(\count_value_i[0]_i_1__3_n_0 ), .Q(\count_value_i_reg_n_0_[0] ), .S(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(rd_clk), .CE(E), .D(\count_value_i[1]_i_1__2_n_0 ), .Q(\count_value_i_reg_n_0_[1] ), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(rd_clk), .CE(E), .D(\count_value_i[2]_i_1__2_n_0 ), .Q(\count_value_i_reg_n_0_[2] ), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(rd_clk), .CE(E), .D(\count_value_i[3]_i_1__2_n_0 ), .Q(\count_value_i_reg_n_0_[3] ), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(rd_clk), .CE(E), .D(\count_value_i[4]_i_1__2_n_0 ), .Q(\count_value_i_reg_n_0_[4] ), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(rd_clk), .CE(E), .D(\count_value_i[5]_i_1__2_n_0 ), .Q(\count_value_i_reg_n_0_[5] ), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(rd_clk), .CE(E), .D(\count_value_i[6]_i_1__2_n_0 ), .Q(\count_value_i_reg_n_0_[6] ), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(rd_clk), .CE(E), .D(\count_value_i[7]_i_1__2_n_0 ), .Q(\count_value_i_reg_n_0_[7] ), .R(\count_value_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[8] (.C(rd_clk), .CE(E), .D(\count_value_i[8]_i_1__2_n_0 ), .Q(\count_value_i_reg_n_0_[8] ), .R(\count_value_i_reg[0]_0 )); LUT6 #( .INIT(64'hFFFF800080008000)) \gen_pf_ic_rc.ram_empty_i_i_1 (.I0(\gen_pf_ic_rc.ram_empty_i_i_2_n_0 ), .I1(E), .I2(\gen_pf_ic_rc.ram_empty_i_i_3_n_0 ), .I3(\gen_pf_ic_rc.ram_empty_i_i_4_n_0 ), .I4(\gen_pf_ic_rc.ram_empty_i_reg ), .I5(\gen_pf_ic_rc.ram_empty_i_reg_0 ), .O(ram_empty_i0)); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_2 (.I0(\count_value_i_reg_n_0_[7] ), .I1(\gen_pf_ic_rc.ram_empty_i_reg_1 [7]), .I2(\count_value_i_reg_n_0_[6] ), .I3(\gen_pf_ic_rc.ram_empty_i_reg_1 [6]), .I4(\gen_pf_ic_rc.ram_empty_i_reg_1 [8]), .I5(\count_value_i_reg_n_0_[8] ), .O(\gen_pf_ic_rc.ram_empty_i_i_2_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_3 (.I0(\count_value_i_reg_n_0_[1] ), .I1(\gen_pf_ic_rc.ram_empty_i_reg_1 [1]), .I2(\count_value_i_reg_n_0_[0] ), .I3(\gen_pf_ic_rc.ram_empty_i_reg_1 [0]), .I4(\gen_pf_ic_rc.ram_empty_i_reg_1 [2]), .I5(\count_value_i_reg_n_0_[2] ), .O(\gen_pf_ic_rc.ram_empty_i_i_3_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_4 (.I0(\count_value_i_reg_n_0_[4] ), .I1(\gen_pf_ic_rc.ram_empty_i_reg_1 [4]), .I2(\count_value_i_reg_n_0_[3] ), .I3(\gen_pf_ic_rc.ram_empty_i_reg_1 [3]), .I4(\gen_pf_ic_rc.ram_empty_i_reg_1 [5]), .I5(\count_value_i_reg_n_0_[5] ), .O(\gen_pf_ic_rc.ram_empty_i_i_4_n_0 )); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module axi_chip2chip_64B66B_xpm_counter_updn__parameterized4_13 (Q, D, wr_pntr_plus1_pf_carry, wr_en, \count_value_i_reg[5]_0 , wrst_busy, rst_d1, \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] , wr_clk); output [8:0]Q; output [7:0]D; input wr_pntr_plus1_pf_carry; input wr_en; input \count_value_i_reg[5]_0 ; input wrst_busy; input rst_d1; input [8:0]\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] ; input wr_clk; wire [7:0]D; wire [8:0]Q; wire \count_value_i[0]_i_1__0_n_0 ; wire \count_value_i[1]_i_1__0_n_0 ; wire \count_value_i[2]_i_1__0_n_0 ; wire \count_value_i[3]_i_1__0_n_0 ; wire \count_value_i[4]_i_1__0_n_0 ; wire \count_value_i[5]_i_1__0_n_0 ; wire \count_value_i[6]_i_1__0_n_0 ; wire \count_value_i[6]_i_2__0_n_0 ; wire \count_value_i[7]_i_1__0_n_0 ; wire \count_value_i[8]_i_1__0_n_0 ; wire \count_value_i[8]_i_2_n_0 ; wire \count_value_i_reg[5]_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[9]_i_2_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_1 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_2 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_3 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_4 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_5 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_6 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_7 ; wire [8:0]\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] ; wire rst_d1; wire wr_clk; wire wr_en; wire wr_pntr_plus1_pf_carry; wire wrst_busy; wire [0:0]\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_O_UNCONNECTED ; wire [7:0]\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]_i_1_CO_UNCONNECTED ; wire [7:1]\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]_i_1_O_UNCONNECTED ; LUT1 #( .INIT(2'h1)) \count_value_i[0]_i_1__0 (.I0(Q[0]), .O(\count_value_i[0]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair196" *) LUT2 #( .INIT(4'h6)) \count_value_i[1]_i_1__0 (.I0(Q[0]), .I1(Q[1]), .O(\count_value_i[1]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair196" *) LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1__0 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair195" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1__0 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair195" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1__0 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1__0_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1__0 (.I0(Q[3]), .I1(\count_value_i[6]_i_2__0_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1__0_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1__0 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2__0_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1__0_n_0 )); LUT6 #( .INIT(64'h0000000800000000)) \count_value_i[6]_i_2__0 (.I0(Q[1]), .I1(wr_en), .I2(\count_value_i_reg[5]_0 ), .I3(wrst_busy), .I4(rst_d1), .I5(Q[0]), .O(\count_value_i[6]_i_2__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair194" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1__0 (.I0(Q[5]), .I1(\count_value_i[8]_i_2_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair194" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[8]_i_1__0 (.I0(Q[6]), .I1(\count_value_i[8]_i_2_n_0 ), .I2(Q[5]), .I3(Q[7]), .I4(Q[8]), .O(\count_value_i[8]_i_1__0_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[8]_i_2 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(wr_pntr_plus1_pf_carry), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[8]_i_2_n_0 )); FDSE #( .INIT(1'b1)) \count_value_i_reg[0] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[0]_i_1__0_n_0 ), .Q(Q[0]), .S(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[1]_i_1__0_n_0 ), .Q(Q[1]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[2]_i_1__0_n_0 ), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[3]_i_1__0_n_0 ), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[4]_i_1__0_n_0 ), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[5]_i_1__0_n_0 ), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[6]_i_1__0_n_0 ), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[7]_i_1__0_n_0 ), .Q(Q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[8] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[8]_i_1__0_n_0 ), .Q(Q[8]), .R(wrst_busy)); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2 (.I0(Q[7]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] [7]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3 (.I0(Q[6]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] [6]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4 (.I0(Q[5]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] [5]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5 (.I0(Q[4]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] [4]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6 (.I0(Q[3]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] [3]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7 (.I0(Q[2]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] [2]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8 (.I0(Q[1]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] [1]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9 (.I0(Q[0]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] [0]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[9]_i_2 (.I0(Q[8]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] [8]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[9]_i_2_n_0 )); (* ADDER_THRESHOLD = "35" *) CARRY8 \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1 (.CI(wr_pntr_plus1_pf_carry), .CI_TOP(1'b0), .CO({\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_1 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_2 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_3 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_4 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_5 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_6 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_7 }), .DI(Q[7:0]), .O({D[6:0],\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_O_UNCONNECTED [0]}), .S({\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0 })); (* ADDER_THRESHOLD = "35" *) CARRY8 \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]_i_1 (.CI(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_0 ), .CI_TOP(1'b0), .CO(\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]_i_1_CO_UNCONNECTED [7:0]), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .O({\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]_i_1_O_UNCONNECTED [7:1],D[7]}), .S({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[9]_i_2_n_0 })); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module axi_chip2chip_64B66B_xpm_counter_updn__parameterized4_3 (Q, D, wr_pntr_plus1_pf_carry, wr_en, \count_value_i_reg[5]_0 , wrst_busy, rst_d1, \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] , wr_clk); output [8:0]Q; output [7:0]D; input wr_pntr_plus1_pf_carry; input wr_en; input \count_value_i_reg[5]_0 ; input wrst_busy; input rst_d1; input [8:0]\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] ; input wr_clk; wire [7:0]D; wire [8:0]Q; wire \count_value_i[0]_i_1__0_n_0 ; wire \count_value_i[1]_i_1__0_n_0 ; wire \count_value_i[2]_i_1__0_n_0 ; wire \count_value_i[3]_i_1__0_n_0 ; wire \count_value_i[4]_i_1__0_n_0 ; wire \count_value_i[5]_i_1__0_n_0 ; wire \count_value_i[6]_i_1__0_n_0 ; wire \count_value_i[6]_i_2__0_n_0 ; wire \count_value_i[7]_i_1__0_n_0 ; wire \count_value_i[8]_i_1__0_n_0 ; wire \count_value_i[8]_i_2_n_0 ; wire \count_value_i_reg[5]_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[9]_i_2_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_0 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_1 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_2 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_3 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_4 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_5 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_6 ; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_7 ; wire [8:0]\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] ; wire rst_d1; wire wr_clk; wire wr_en; wire wr_pntr_plus1_pf_carry; wire wrst_busy; wire [0:0]\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_O_UNCONNECTED ; wire [7:0]\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]_i_1_CO_UNCONNECTED ; wire [7:1]\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]_i_1_O_UNCONNECTED ; LUT1 #( .INIT(2'h1)) \count_value_i[0]_i_1__0 (.I0(Q[0]), .O(\count_value_i[0]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair256" *) LUT2 #( .INIT(4'h6)) \count_value_i[1]_i_1__0 (.I0(Q[0]), .I1(Q[1]), .O(\count_value_i[1]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair256" *) LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1__0 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair255" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1__0 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair255" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1__0 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1__0_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1__0 (.I0(Q[3]), .I1(\count_value_i[6]_i_2__0_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1__0_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1__0 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2__0_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1__0_n_0 )); LUT6 #( .INIT(64'h0000000800000000)) \count_value_i[6]_i_2__0 (.I0(Q[1]), .I1(wr_en), .I2(\count_value_i_reg[5]_0 ), .I3(wrst_busy), .I4(rst_d1), .I5(Q[0]), .O(\count_value_i[6]_i_2__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair254" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1__0 (.I0(Q[5]), .I1(\count_value_i[8]_i_2_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1__0_n_0 )); (* SOFT_HLUTNM = "soft_lutpair254" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[8]_i_1__0 (.I0(Q[6]), .I1(\count_value_i[8]_i_2_n_0 ), .I2(Q[5]), .I3(Q[7]), .I4(Q[8]), .O(\count_value_i[8]_i_1__0_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[8]_i_2 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(wr_pntr_plus1_pf_carry), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[8]_i_2_n_0 )); FDSE #( .INIT(1'b1)) \count_value_i_reg[0] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[0]_i_1__0_n_0 ), .Q(Q[0]), .S(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[1] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[1]_i_1__0_n_0 ), .Q(Q[1]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[2]_i_1__0_n_0 ), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[3]_i_1__0_n_0 ), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[4]_i_1__0_n_0 ), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[5]_i_1__0_n_0 ), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[6]_i_1__0_n_0 ), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[7]_i_1__0_n_0 ), .Q(Q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[8] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[8]_i_1__0_n_0 ), .Q(Q[8]), .R(wrst_busy)); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2 (.I0(Q[7]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] [7]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3 (.I0(Q[6]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] [6]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4 (.I0(Q[5]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] [5]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5 (.I0(Q[4]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] [4]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6 (.I0(Q[3]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] [3]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7 (.I0(Q[2]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] [2]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8 (.I0(Q[1]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] [1]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9 (.I0(Q[0]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] [0]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0 )); LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[9]_i_2 (.I0(Q[8]), .I1(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] [8]), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[9]_i_2_n_0 )); (* ADDER_THRESHOLD = "35" *) CARRY8 \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1 (.CI(wr_pntr_plus1_pf_carry), .CI_TOP(1'b0), .CO({\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_1 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_2 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_3 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_4 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_5 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_6 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_7 }), .DI(Q[7:0]), .O({D[6:0],\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_O_UNCONNECTED [0]}), .S({\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_2_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_3_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_4_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_5_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_6_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_7_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_8_n_0 ,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[8]_i_9_n_0 })); (* ADDER_THRESHOLD = "35" *) CARRY8 \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]_i_1 (.CI(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8]_i_1_n_0 ), .CI_TOP(1'b0), .CO(\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]_i_1_CO_UNCONNECTED [7:0]), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .O({\NLW_gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9]_i_1_O_UNCONNECTED [7:1],D[7]}), .S({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q[9]_i_2_n_0 })); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module axi_chip2chip_64B66B_xpm_counter_updn__parameterized5 (Q, wr_pntr_plus1_pf_carry, wr_en, \count_value_i_reg[5]_0 , wrst_busy, rst_d1, wr_clk); output [8:0]Q; input wr_pntr_plus1_pf_carry; input wr_en; input \count_value_i_reg[5]_0 ; input wrst_busy; input rst_d1; input wr_clk; wire [8:0]Q; wire \count_value_i[0]_i_1_n_0 ; wire \count_value_i[1]_i_1_n_0 ; wire \count_value_i[2]_i_1_n_0 ; wire \count_value_i[3]_i_1_n_0 ; wire \count_value_i[4]_i_1_n_0 ; wire \count_value_i[5]_i_1__1_n_0 ; wire \count_value_i[6]_i_1__1_n_0 ; wire \count_value_i[6]_i_2__1_n_0 ; wire \count_value_i[7]_i_1__1_n_0 ; wire \count_value_i[8]_i_1__1_n_0 ; wire \count_value_i[8]_i_2__0_n_0 ; wire \count_value_i_reg[5]_0 ; wire rst_d1; wire wr_clk; wire wr_en; wire wr_pntr_plus1_pf_carry; wire wrst_busy; (* SOFT_HLUTNM = "soft_lutpair259" *) LUT1 #( .INIT(2'h1)) \count_value_i[0]_i_1 (.I0(Q[0]), .O(\count_value_i[0]_i_1_n_0 )); LUT2 #( .INIT(4'h6)) \count_value_i[1]_i_1 (.I0(Q[0]), .I1(Q[1]), .O(\count_value_i[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair259" *) LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair258" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair258" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1__1 (.I0(Q[3]), .I1(\count_value_i[6]_i_2__1_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1__1_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1__1 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2__1_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1__1_n_0 )); LUT6 #( .INIT(64'h0000000800000000)) \count_value_i[6]_i_2__1 (.I0(Q[1]), .I1(wr_en), .I2(\count_value_i_reg[5]_0 ), .I3(wrst_busy), .I4(rst_d1), .I5(Q[0]), .O(\count_value_i[6]_i_2__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair257" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1__1 (.I0(Q[5]), .I1(\count_value_i[8]_i_2__0_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair257" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[8]_i_1__1 (.I0(Q[6]), .I1(\count_value_i[8]_i_2__0_n_0 ), .I2(Q[5]), .I3(Q[7]), .I4(Q[8]), .O(\count_value_i[8]_i_1__1_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[8]_i_2__0 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(wr_pntr_plus1_pf_carry), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[8]_i_2__0_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[0]_i_1_n_0 ), .Q(Q[0]), .R(wrst_busy)); FDSE #( .INIT(1'b1)) \count_value_i_reg[1] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[1]_i_1_n_0 ), .Q(Q[1]), .S(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[2]_i_1_n_0 ), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[3]_i_1_n_0 ), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[4]_i_1_n_0 ), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[5]_i_1__1_n_0 ), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[6]_i_1__1_n_0 ), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[7]_i_1__1_n_0 ), .Q(Q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[8] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[8]_i_1__1_n_0 ), .Q(Q[8]), .R(wrst_busy)); endmodule (* ORIG_REF_NAME = "xpm_counter_updn" *) module axi_chip2chip_64B66B_xpm_counter_updn__parameterized5_14 (Q, wr_pntr_plus1_pf_carry, wr_en, \count_value_i_reg[5]_0 , wrst_busy, rst_d1, wr_clk); output [8:0]Q; input wr_pntr_plus1_pf_carry; input wr_en; input \count_value_i_reg[5]_0 ; input wrst_busy; input rst_d1; input wr_clk; wire [8:0]Q; wire \count_value_i[0]_i_1_n_0 ; wire \count_value_i[1]_i_1_n_0 ; wire \count_value_i[2]_i_1_n_0 ; wire \count_value_i[3]_i_1_n_0 ; wire \count_value_i[4]_i_1_n_0 ; wire \count_value_i[5]_i_1__1_n_0 ; wire \count_value_i[6]_i_1__1_n_0 ; wire \count_value_i[6]_i_2__1_n_0 ; wire \count_value_i[7]_i_1__1_n_0 ; wire \count_value_i[8]_i_1__1_n_0 ; wire \count_value_i[8]_i_2__0_n_0 ; wire \count_value_i_reg[5]_0 ; wire rst_d1; wire wr_clk; wire wr_en; wire wr_pntr_plus1_pf_carry; wire wrst_busy; (* SOFT_HLUTNM = "soft_lutpair199" *) LUT1 #( .INIT(2'h1)) \count_value_i[0]_i_1 (.I0(Q[0]), .O(\count_value_i[0]_i_1_n_0 )); LUT2 #( .INIT(4'h6)) \count_value_i[1]_i_1 (.I0(Q[0]), .I1(Q[1]), .O(\count_value_i[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair199" *) LUT3 #( .INIT(8'h78)) \count_value_i[2]_i_1 (.I0(Q[0]), .I1(Q[1]), .I2(Q[2]), .O(\count_value_i[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair198" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[3]_i_1 (.I0(Q[1]), .I1(Q[0]), .I2(Q[2]), .I3(Q[3]), .O(\count_value_i[3]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair198" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[4]_i_1 (.I0(Q[2]), .I1(Q[0]), .I2(Q[1]), .I3(Q[3]), .I4(Q[4]), .O(\count_value_i[4]_i_1_n_0 )); LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[5]_i_1__1 (.I0(Q[3]), .I1(\count_value_i[6]_i_2__1_n_0 ), .I2(Q[2]), .I3(Q[4]), .I4(Q[5]), .O(\count_value_i[5]_i_1__1_n_0 )); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \count_value_i[6]_i_1__1 (.I0(Q[4]), .I1(Q[2]), .I2(\count_value_i[6]_i_2__1_n_0 ), .I3(Q[3]), .I4(Q[5]), .I5(Q[6]), .O(\count_value_i[6]_i_1__1_n_0 )); LUT6 #( .INIT(64'h0000000800000000)) \count_value_i[6]_i_2__1 (.I0(Q[1]), .I1(wr_en), .I2(\count_value_i_reg[5]_0 ), .I3(wrst_busy), .I4(rst_d1), .I5(Q[0]), .O(\count_value_i[6]_i_2__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair197" *) LUT4 #( .INIT(16'h7F80)) \count_value_i[7]_i_1__1 (.I0(Q[5]), .I1(\count_value_i[8]_i_2__0_n_0 ), .I2(Q[6]), .I3(Q[7]), .O(\count_value_i[7]_i_1__1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair197" *) LUT5 #( .INIT(32'h7FFF8000)) \count_value_i[8]_i_1__1 (.I0(Q[6]), .I1(\count_value_i[8]_i_2__0_n_0 ), .I2(Q[5]), .I3(Q[7]), .I4(Q[8]), .O(\count_value_i[8]_i_1__1_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \count_value_i[8]_i_2__0 (.I0(Q[4]), .I1(Q[2]), .I2(Q[0]), .I3(wr_pntr_plus1_pf_carry), .I4(Q[1]), .I5(Q[3]), .O(\count_value_i[8]_i_2__0_n_0 )); FDRE #( .INIT(1'b0)) \count_value_i_reg[0] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[0]_i_1_n_0 ), .Q(Q[0]), .R(wrst_busy)); FDSE #( .INIT(1'b1)) \count_value_i_reg[1] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[1]_i_1_n_0 ), .Q(Q[1]), .S(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[2] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[2]_i_1_n_0 ), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[3] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[3]_i_1_n_0 ), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[4] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[4]_i_1_n_0 ), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[5] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[5]_i_1__1_n_0 ), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[6] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[6]_i_1__1_n_0 ), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[7] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[7]_i_1__1_n_0 ), .Q(Q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \count_value_i_reg[8] (.C(wr_clk), .CE(wr_pntr_plus1_pf_carry), .D(\count_value_i[8]_i_1__1_n_0 ), .Q(Q[8]), .R(wrst_busy)); endmodule (* CASCADE_HEIGHT = "0" *) (* CDC_SYNC_STAGES = "3" *) (* DOUT_RESET_VALUE = "0" *) (* ECC_MODE = "no_ecc" *) (* EN_ADV_FEATURE_ASYNC = "16'b0000011100000111" *) (* FIFO_MEMORY_TYPE = "block" *) (* FIFO_READ_LATENCY = "0" *) (* FIFO_WRITE_DEPTH = "256" *) (* FULL_RESET_VALUE = "1" *) (* ORIG_REF_NAME = "xpm_fifo_async" *) (* PROG_EMPTY_THRESH = "10" *) (* PROG_FULL_THRESH = "128" *) (* P_COMMON_CLOCK = "0" *) (* P_ECC_MODE = "0" *) (* P_FIFO_MEMORY_TYPE = "2" *) (* P_READ_MODE = "1" *) (* P_WAKEUP_TIME = "2" *) (* RD_DATA_COUNT_WIDTH = "8" *) (* READ_DATA_WIDTH = "50" *) (* READ_MODE = "fwft" *) (* RELATED_CLOCKS = "0" *) (* SIM_ASSERT_CHK = "0" *) (* USE_ADV_FEATURES = "0707" *) (* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH = "50" *) (* WR_DATA_COUNT_WIDTH = "8" *) (* XPM_MODULE = "TRUE" *) (* dont_touch = "true" *) (* is_du_within_envelope = "true" *) module axi_chip2chip_64B66B_xpm_fifo_async (sleep, rst, wr_clk, wr_en, din, full, prog_full, wr_data_count, overflow, wr_rst_busy, almost_full, wr_ack, rd_clk, rd_en, dout, empty, prog_empty, rd_data_count, underflow, rd_rst_busy, almost_empty, data_valid, injectsbiterr, injectdbiterr, sbiterr, dbiterr); input sleep; input rst; input wr_clk; input wr_en; input [49:0]din; output full; output prog_full; output [7:0]wr_data_count; output overflow; output wr_rst_busy; output almost_full; output wr_ack; input rd_clk; input rd_en; output [49:0]dout; output empty; output prog_empty; output [7:0]rd_data_count; output underflow; output rd_rst_busy; output almost_empty; output data_valid; input injectsbiterr; input injectdbiterr; output sbiterr; output dbiterr; wire \ ; wire [49:0]din; wire [49:0]dout; wire empty; wire full; wire overflow; wire prog_empty; wire prog_full; wire rd_clk; wire [7:0]rd_data_count; wire rd_en; wire rd_rst_busy; wire rst; wire sleep; wire underflow; wire wr_clk; wire [7:0]wr_data_count; wire wr_en; wire wr_rst_busy; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_empty_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_full_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_data_valid_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_wr_ack_UNCONNECTED ; assign almost_empty = \ ; assign almost_full = \ ; assign data_valid = \ ; assign dbiterr = \ ; assign sbiterr = \ ; assign wr_ack = \ ; GND GND (.G(\ )); (* CASCADE_HEIGHT = "0" *) (* CDC_DEST_SYNC_FF = "3" *) (* COMMON_CLOCK = "0" *) (* DOUT_RESET_VALUE = "0" *) (* ECC_MODE = "0" *) (* ENABLE_ECC = "0" *) (* EN_ADV_FEATURE = "16'b0000011100000111" *) (* EN_AE = "1'b0" *) (* EN_AF = "1'b0" *) (* EN_DVLD = "1'b0" *) (* EN_OF = "1'b1" *) (* EN_PE = "1'b1" *) (* EN_PF = "1'b1" *) (* EN_RDC = "1'b1" *) (* EN_UF = "1'b1" *) (* EN_WACK = "1'b0" *) (* EN_WDC = "1'b1" *) (* FG_EQ_ASYM_DOUT = "1'b0" *) (* FIFO_MEMORY_TYPE = "2" *) (* FIFO_MEM_TYPE = "2" *) (* FIFO_READ_DEPTH = "256" *) (* FIFO_READ_LATENCY = "0" *) (* FIFO_SIZE = "12800" *) (* FIFO_WRITE_DEPTH = "256" *) (* FULL_RESET_VALUE = "1" *) (* FULL_RST_VAL = "1'b1" *) (* KEEP_HIERARCHY = "soft" *) (* PE_THRESH_ADJ = "8" *) (* PE_THRESH_MAX = "251" *) (* PE_THRESH_MIN = "5" *) (* PF_THRESH_ADJ = "126" *) (* PF_THRESH_MAX = "251" *) (* PF_THRESH_MIN = "8" *) (* PROG_EMPTY_THRESH = "10" *) (* PROG_FULL_THRESH = "128" *) (* RD_DATA_COUNT_WIDTH = "8" *) (* RD_DC_WIDTH_EXT = "9" *) (* RD_LATENCY = "2" *) (* RD_MODE = "1" *) (* RD_PNTR_WIDTH = "8" *) (* READ_DATA_WIDTH = "50" *) (* READ_MODE = "1" *) (* READ_MODE_LL = "1" *) (* RELATED_CLOCKS = "0" *) (* REMOVE_WR_RD_PROT_LOGIC = "0" *) (* SIM_ASSERT_CHK = "0" *) (* USE_ADV_FEATURES = "0707" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WIDTH_RATIO = "1" *) (* WRITE_DATA_WIDTH = "50" *) (* WR_DATA_COUNT_WIDTH = "8" *) (* WR_DC_WIDTH_EXT = "9" *) (* WR_DEPTH_LOG = "8" *) (* WR_PNTR_WIDTH = "8" *) (* WR_RD_RATIO = "0" *) (* WR_WIDTH_LOG = "6" *) (* XPM_MODULE = "TRUE" *) (* both_stages_valid = "3" *) (* invalid = "0" *) (* stage1_valid = "2" *) (* stage2_valid = "1" *) axi_chip2chip_64B66B_xpm_fifo_base \gnuram_async_fifo.xpm_fifo_base_inst (.almost_empty(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_empty_UNCONNECTED ), .almost_full(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_full_UNCONNECTED ), .data_valid(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_data_valid_UNCONNECTED ), .dbiterr(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED ), .din(din), .dout(dout), .empty(empty), .full(full), .full_n(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED ), .injectdbiterr(1'b0), .injectsbiterr(1'b0), .overflow(overflow), .prog_empty(prog_empty), .prog_full(prog_full), .rd_clk(rd_clk), .rd_data_count(rd_data_count), .rd_en(rd_en), .rd_rst_busy(rd_rst_busy), .rst(rst), .sbiterr(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED ), .sleep(sleep), .underflow(underflow), .wr_ack(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_wr_ack_UNCONNECTED ), .wr_clk(wr_clk), .wr_data_count(wr_data_count), .wr_en(wr_en), .wr_rst_busy(wr_rst_busy)); endmodule (* CASCADE_HEIGHT = "0" *) (* CDC_SYNC_STAGES = "3" *) (* DOUT_RESET_VALUE = "0" *) (* ECC_MODE = "no_ecc" *) (* EN_ADV_FEATURE_ASYNC = "16'b0000011100000111" *) (* FIFO_MEMORY_TYPE = "block" *) (* FIFO_READ_LATENCY = "0" *) (* FIFO_WRITE_DEPTH = "512" *) (* FULL_RESET_VALUE = "1" *) (* ORIG_REF_NAME = "xpm_fifo_async" *) (* PROG_EMPTY_THRESH = "10" *) (* PROG_FULL_THRESH = "384" *) (* P_COMMON_CLOCK = "0" *) (* P_ECC_MODE = "0" *) (* P_FIFO_MEMORY_TYPE = "2" *) (* P_READ_MODE = "1" *) (* P_WAKEUP_TIME = "2" *) (* RD_DATA_COUNT_WIDTH = "9" *) (* READ_DATA_WIDTH = "41" *) (* READ_MODE = "fwft" *) (* RELATED_CLOCKS = "0" *) (* SIM_ASSERT_CHK = "0" *) (* USE_ADV_FEATURES = "0707" *) (* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH = "41" *) (* WR_DATA_COUNT_WIDTH = "9" *) (* XPM_MODULE = "TRUE" *) (* dont_touch = "true" *) (* is_du_within_envelope = "true" *) module axi_chip2chip_64B66B_xpm_fifo_async__parameterized0 (sleep, rst, wr_clk, wr_en, din, full, prog_full, wr_data_count, overflow, wr_rst_busy, almost_full, wr_ack, rd_clk, rd_en, dout, empty, prog_empty, rd_data_count, underflow, rd_rst_busy, almost_empty, data_valid, injectsbiterr, injectdbiterr, sbiterr, dbiterr); input sleep; input rst; input wr_clk; input wr_en; input [40:0]din; output full; output prog_full; output [8:0]wr_data_count; output overflow; output wr_rst_busy; output almost_full; output wr_ack; input rd_clk; input rd_en; output [40:0]dout; output empty; output prog_empty; output [8:0]rd_data_count; output underflow; output rd_rst_busy; output almost_empty; output data_valid; input injectsbiterr; input injectdbiterr; output sbiterr; output dbiterr; wire \ ; wire [40:0]din; wire [40:0]dout; wire empty; wire full; wire overflow; wire prog_empty; wire prog_full; wire rd_clk; wire [8:0]rd_data_count; wire rd_en; wire rd_rst_busy; wire rst; wire sleep; wire underflow; wire wr_clk; wire [8:0]wr_data_count; wire wr_en; wire wr_rst_busy; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_empty_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_full_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_data_valid_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_wr_ack_UNCONNECTED ; assign almost_empty = \ ; assign almost_full = \ ; assign data_valid = \ ; assign dbiterr = \ ; assign sbiterr = \ ; assign wr_ack = \ ; GND GND (.G(\ )); (* CASCADE_HEIGHT = "0" *) (* CDC_DEST_SYNC_FF = "3" *) (* COMMON_CLOCK = "0" *) (* DOUT_RESET_VALUE = "0" *) (* ECC_MODE = "0" *) (* ENABLE_ECC = "0" *) (* EN_ADV_FEATURE = "16'b0000011100000111" *) (* EN_AE = "1'b0" *) (* EN_AF = "1'b0" *) (* EN_DVLD = "1'b0" *) (* EN_OF = "1'b1" *) (* EN_PE = "1'b1" *) (* EN_PF = "1'b1" *) (* EN_RDC = "1'b1" *) (* EN_UF = "1'b1" *) (* EN_WACK = "1'b0" *) (* EN_WDC = "1'b1" *) (* FG_EQ_ASYM_DOUT = "1'b0" *) (* FIFO_MEMORY_TYPE = "2" *) (* FIFO_MEM_TYPE = "2" *) (* FIFO_READ_DEPTH = "512" *) (* FIFO_READ_LATENCY = "0" *) (* FIFO_SIZE = "20992" *) (* FIFO_WRITE_DEPTH = "512" *) (* FULL_RESET_VALUE = "1" *) (* FULL_RST_VAL = "1'b1" *) (* KEEP_HIERARCHY = "soft" *) (* PE_THRESH_ADJ = "8" *) (* PE_THRESH_MAX = "507" *) (* PE_THRESH_MIN = "5" *) (* PF_THRESH_ADJ = "382" *) (* PF_THRESH_MAX = "507" *) (* PF_THRESH_MIN = "8" *) (* PROG_EMPTY_THRESH = "10" *) (* PROG_FULL_THRESH = "384" *) (* RD_DATA_COUNT_WIDTH = "9" *) (* RD_DC_WIDTH_EXT = "10" *) (* RD_LATENCY = "2" *) (* RD_MODE = "1" *) (* RD_PNTR_WIDTH = "9" *) (* READ_DATA_WIDTH = "41" *) (* READ_MODE = "1" *) (* READ_MODE_LL = "1" *) (* RELATED_CLOCKS = "0" *) (* REMOVE_WR_RD_PROT_LOGIC = "0" *) (* SIM_ASSERT_CHK = "0" *) (* USE_ADV_FEATURES = "0707" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WIDTH_RATIO = "1" *) (* WRITE_DATA_WIDTH = "41" *) (* WR_DATA_COUNT_WIDTH = "9" *) (* WR_DC_WIDTH_EXT = "10" *) (* WR_DEPTH_LOG = "9" *) (* WR_PNTR_WIDTH = "9" *) (* WR_RD_RATIO = "0" *) (* WR_WIDTH_LOG = "6" *) (* XPM_MODULE = "TRUE" *) (* both_stages_valid = "3" *) (* invalid = "0" *) (* stage1_valid = "2" *) (* stage2_valid = "1" *) axi_chip2chip_64B66B_xpm_fifo_base__parameterized0 \gnuram_async_fifo.xpm_fifo_base_inst (.almost_empty(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_empty_UNCONNECTED ), .almost_full(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_full_UNCONNECTED ), .data_valid(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_data_valid_UNCONNECTED ), .dbiterr(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED ), .din(din), .dout(dout), .empty(empty), .full(full), .full_n(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED ), .injectdbiterr(1'b0), .injectsbiterr(1'b0), .overflow(overflow), .prog_empty(prog_empty), .prog_full(prog_full), .rd_clk(rd_clk), .rd_data_count(rd_data_count), .rd_en(rd_en), .rd_rst_busy(rd_rst_busy), .rst(rst), .sbiterr(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED ), .sleep(sleep), .underflow(underflow), .wr_ack(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_wr_ack_UNCONNECTED ), .wr_clk(wr_clk), .wr_data_count(wr_data_count), .wr_en(wr_en), .wr_rst_busy(wr_rst_busy)); endmodule (* CASCADE_HEIGHT = "0" *) (* CDC_SYNC_STAGES = "3" *) (* DOUT_RESET_VALUE = "0" *) (* ECC_MODE = "no_ecc" *) (* EN_ADV_FEATURE_ASYNC = "16'b0000011100000111" *) (* FIFO_MEMORY_TYPE = "block" *) (* FIFO_READ_LATENCY = "0" *) (* FIFO_WRITE_DEPTH = "512" *) (* FULL_RESET_VALUE = "1" *) (* ORIG_REF_NAME = "xpm_fifo_async" *) (* PROG_EMPTY_THRESH = "10" *) (* PROG_FULL_THRESH = "384" *) (* P_COMMON_CLOCK = "0" *) (* P_ECC_MODE = "0" *) (* P_FIFO_MEMORY_TYPE = "2" *) (* P_READ_MODE = "1" *) (* P_WAKEUP_TIME = "2" *) (* RD_DATA_COUNT_WIDTH = "9" *) (* READ_DATA_WIDTH = "41" *) (* READ_MODE = "fwft" *) (* RELATED_CLOCKS = "0" *) (* SIM_ASSERT_CHK = "0" *) (* USE_ADV_FEATURES = "0707" *) (* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH = "41" *) (* WR_DATA_COUNT_WIDTH = "9" *) (* XPM_MODULE = "TRUE" *) (* dont_touch = "true" *) (* is_du_within_envelope = "true" *) module axi_chip2chip_64B66B_xpm_fifo_async__parameterized0__xdcDup__1 (sleep, rst, wr_clk, wr_en, din, full, prog_full, wr_data_count, overflow, wr_rst_busy, almost_full, wr_ack, rd_clk, rd_en, dout, empty, prog_empty, rd_data_count, underflow, rd_rst_busy, almost_empty, data_valid, injectsbiterr, injectdbiterr, sbiterr, dbiterr); input sleep; input rst; input wr_clk; input wr_en; input [40:0]din; output full; output prog_full; output [8:0]wr_data_count; output overflow; output wr_rst_busy; output almost_full; output wr_ack; input rd_clk; input rd_en; output [40:0]dout; output empty; output prog_empty; output [8:0]rd_data_count; output underflow; output rd_rst_busy; output almost_empty; output data_valid; input injectsbiterr; input injectdbiterr; output sbiterr; output dbiterr; wire \ ; wire [40:0]din; wire [40:0]dout; wire empty; wire full; wire overflow; wire prog_empty; wire prog_full; wire rd_clk; wire [8:0]rd_data_count; wire rd_en; wire rd_rst_busy; wire rst; wire sleep; wire underflow; wire wr_clk; wire [8:0]wr_data_count; wire wr_en; wire wr_rst_busy; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_empty_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_full_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_data_valid_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_wr_ack_UNCONNECTED ; assign almost_empty = \ ; assign almost_full = \ ; assign data_valid = \ ; assign dbiterr = \ ; assign sbiterr = \ ; assign wr_ack = \ ; GND GND (.G(\ )); (* CASCADE_HEIGHT = "0" *) (* CDC_DEST_SYNC_FF = "3" *) (* COMMON_CLOCK = "0" *) (* DOUT_RESET_VALUE = "0" *) (* ECC_MODE = "0" *) (* ENABLE_ECC = "0" *) (* EN_ADV_FEATURE = "16'b0000011100000111" *) (* EN_AE = "1'b0" *) (* EN_AF = "1'b0" *) (* EN_DVLD = "1'b0" *) (* EN_OF = "1'b1" *) (* EN_PE = "1'b1" *) (* EN_PF = "1'b1" *) (* EN_RDC = "1'b1" *) (* EN_UF = "1'b1" *) (* EN_WACK = "1'b0" *) (* EN_WDC = "1'b1" *) (* FG_EQ_ASYM_DOUT = "1'b0" *) (* FIFO_MEMORY_TYPE = "2" *) (* FIFO_MEM_TYPE = "2" *) (* FIFO_READ_DEPTH = "512" *) (* FIFO_READ_LATENCY = "0" *) (* FIFO_SIZE = "20992" *) (* FIFO_WRITE_DEPTH = "512" *) (* FULL_RESET_VALUE = "1" *) (* FULL_RST_VAL = "1'b1" *) (* KEEP_HIERARCHY = "soft" *) (* PE_THRESH_ADJ = "8" *) (* PE_THRESH_MAX = "507" *) (* PE_THRESH_MIN = "5" *) (* PF_THRESH_ADJ = "382" *) (* PF_THRESH_MAX = "507" *) (* PF_THRESH_MIN = "8" *) (* PROG_EMPTY_THRESH = "10" *) (* PROG_FULL_THRESH = "384" *) (* RD_DATA_COUNT_WIDTH = "9" *) (* RD_DC_WIDTH_EXT = "10" *) (* RD_LATENCY = "2" *) (* RD_MODE = "1" *) (* RD_PNTR_WIDTH = "9" *) (* READ_DATA_WIDTH = "41" *) (* READ_MODE = "1" *) (* READ_MODE_LL = "1" *) (* RELATED_CLOCKS = "0" *) (* REMOVE_WR_RD_PROT_LOGIC = "0" *) (* SIM_ASSERT_CHK = "0" *) (* USE_ADV_FEATURES = "0707" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WIDTH_RATIO = "1" *) (* WRITE_DATA_WIDTH = "41" *) (* WR_DATA_COUNT_WIDTH = "9" *) (* WR_DC_WIDTH_EXT = "10" *) (* WR_DEPTH_LOG = "9" *) (* WR_PNTR_WIDTH = "9" *) (* WR_RD_RATIO = "0" *) (* WR_WIDTH_LOG = "6" *) (* XPM_MODULE = "TRUE" *) (* both_stages_valid = "3" *) (* invalid = "0" *) (* stage1_valid = "2" *) (* stage2_valid = "1" *) axi_chip2chip_64B66B_xpm_fifo_base__parameterized0__xdcDup__1 \gnuram_async_fifo.xpm_fifo_base_inst (.almost_empty(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_empty_UNCONNECTED ), .almost_full(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_full_UNCONNECTED ), .data_valid(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_data_valid_UNCONNECTED ), .dbiterr(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED ), .din(din), .dout(dout), .empty(empty), .full(full), .full_n(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED ), .injectdbiterr(1'b0), .injectsbiterr(1'b0), .overflow(overflow), .prog_empty(prog_empty), .prog_full(prog_full), .rd_clk(rd_clk), .rd_data_count(rd_data_count), .rd_en(rd_en), .rd_rst_busy(rd_rst_busy), .rst(rst), .sbiterr(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED ), .sleep(sleep), .underflow(underflow), .wr_ack(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_wr_ack_UNCONNECTED ), .wr_clk(wr_clk), .wr_data_count(wr_data_count), .wr_en(wr_en), .wr_rst_busy(wr_rst_busy)); endmodule (* CASCADE_HEIGHT = "0" *) (* CDC_SYNC_STAGES = "3" *) (* DOUT_RESET_VALUE = "0" *) (* ECC_MODE = "no_ecc" *) (* EN_ADV_FEATURE_ASYNC = "16'b0000011100000111" *) (* FIFO_MEMORY_TYPE = "distributed" *) (* FIFO_READ_LATENCY = "0" *) (* FIFO_WRITE_DEPTH = "256" *) (* FULL_RESET_VALUE = "1" *) (* ORIG_REF_NAME = "xpm_fifo_async" *) (* PROG_EMPTY_THRESH = "10" *) (* PROG_FULL_THRESH = "128" *) (* P_COMMON_CLOCK = "0" *) (* P_ECC_MODE = "0" *) (* P_FIFO_MEMORY_TYPE = "1" *) (* P_READ_MODE = "1" *) (* P_WAKEUP_TIME = "2" *) (* RD_DATA_COUNT_WIDTH = "8" *) (* READ_DATA_WIDTH = "8" *) (* READ_MODE = "fwft" *) (* RELATED_CLOCKS = "0" *) (* SIM_ASSERT_CHK = "0" *) (* USE_ADV_FEATURES = "0707" *) (* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH = "8" *) (* WR_DATA_COUNT_WIDTH = "8" *) (* XPM_MODULE = "TRUE" *) (* dont_touch = "true" *) (* is_du_within_envelope = "true" *) module axi_chip2chip_64B66B_xpm_fifo_async__parameterized1 (sleep, rst, wr_clk, wr_en, din, full, prog_full, wr_data_count, overflow, wr_rst_busy, almost_full, wr_ack, rd_clk, rd_en, dout, empty, prog_empty, rd_data_count, underflow, rd_rst_busy, almost_empty, data_valid, injectsbiterr, injectdbiterr, sbiterr, dbiterr); input sleep; input rst; input wr_clk; input wr_en; input [7:0]din; output full; output prog_full; output [7:0]wr_data_count; output overflow; output wr_rst_busy; output almost_full; output wr_ack; input rd_clk; input rd_en; output [7:0]dout; output empty; output prog_empty; output [7:0]rd_data_count; output underflow; output rd_rst_busy; output almost_empty; output data_valid; input injectsbiterr; input injectdbiterr; output sbiterr; output dbiterr; wire \ ; wire [7:0]din; wire [7:0]dout; wire empty; wire full; wire overflow; wire prog_empty; wire prog_full; wire rd_clk; wire [7:0]rd_data_count; wire rd_en; wire rd_rst_busy; wire rst; wire sleep; wire underflow; wire wr_clk; wire [7:0]wr_data_count; wire wr_en; wire wr_rst_busy; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_empty_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_full_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_data_valid_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_wr_ack_UNCONNECTED ; assign almost_empty = \ ; assign almost_full = \ ; assign data_valid = \ ; assign dbiterr = \ ; assign sbiterr = \ ; assign wr_ack = \ ; GND GND (.G(\ )); (* CASCADE_HEIGHT = "0" *) (* CDC_DEST_SYNC_FF = "3" *) (* COMMON_CLOCK = "0" *) (* DOUT_RESET_VALUE = "0" *) (* ECC_MODE = "0" *) (* ENABLE_ECC = "0" *) (* EN_ADV_FEATURE = "16'b0000011100000111" *) (* EN_AE = "1'b0" *) (* EN_AF = "1'b0" *) (* EN_DVLD = "1'b0" *) (* EN_OF = "1'b1" *) (* EN_PE = "1'b1" *) (* EN_PF = "1'b1" *) (* EN_RDC = "1'b1" *) (* EN_UF = "1'b1" *) (* EN_WACK = "1'b0" *) (* EN_WDC = "1'b1" *) (* FG_EQ_ASYM_DOUT = "1'b0" *) (* FIFO_MEMORY_TYPE = "1" *) (* FIFO_MEM_TYPE = "1" *) (* FIFO_READ_DEPTH = "256" *) (* FIFO_READ_LATENCY = "0" *) (* FIFO_SIZE = "2048" *) (* FIFO_WRITE_DEPTH = "256" *) (* FULL_RESET_VALUE = "1" *) (* FULL_RST_VAL = "1'b1" *) (* KEEP_HIERARCHY = "soft" *) (* PE_THRESH_ADJ = "8" *) (* PE_THRESH_MAX = "251" *) (* PE_THRESH_MIN = "5" *) (* PF_THRESH_ADJ = "126" *) (* PF_THRESH_MAX = "251" *) (* PF_THRESH_MIN = "8" *) (* PROG_EMPTY_THRESH = "10" *) (* PROG_FULL_THRESH = "128" *) (* RD_DATA_COUNT_WIDTH = "8" *) (* RD_DC_WIDTH_EXT = "9" *) (* RD_LATENCY = "2" *) (* RD_MODE = "1" *) (* RD_PNTR_WIDTH = "8" *) (* READ_DATA_WIDTH = "8" *) (* READ_MODE = "1" *) (* READ_MODE_LL = "1" *) (* RELATED_CLOCKS = "0" *) (* REMOVE_WR_RD_PROT_LOGIC = "0" *) (* SIM_ASSERT_CHK = "0" *) (* USE_ADV_FEATURES = "0707" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WIDTH_RATIO = "1" *) (* WRITE_DATA_WIDTH = "8" *) (* WR_DATA_COUNT_WIDTH = "8" *) (* WR_DC_WIDTH_EXT = "9" *) (* WR_DEPTH_LOG = "8" *) (* WR_PNTR_WIDTH = "8" *) (* WR_RD_RATIO = "0" *) (* WR_WIDTH_LOG = "3" *) (* XPM_MODULE = "TRUE" *) (* both_stages_valid = "3" *) (* invalid = "0" *) (* stage1_valid = "2" *) (* stage2_valid = "1" *) axi_chip2chip_64B66B_xpm_fifo_base__parameterized1 \gnuram_async_fifo.xpm_fifo_base_inst (.almost_empty(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_empty_UNCONNECTED ), .almost_full(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_full_UNCONNECTED ), .data_valid(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_data_valid_UNCONNECTED ), .dbiterr(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED ), .din(din), .dout(dout), .empty(empty), .full(full), .full_n(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED ), .injectdbiterr(1'b0), .injectsbiterr(1'b0), .overflow(overflow), .prog_empty(prog_empty), .prog_full(prog_full), .rd_clk(rd_clk), .rd_data_count(rd_data_count), .rd_en(rd_en), .rd_rst_busy(rd_rst_busy), .rst(rst), .sbiterr(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED ), .sleep(sleep), .underflow(underflow), .wr_ack(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_wr_ack_UNCONNECTED ), .wr_clk(wr_clk), .wr_data_count(wr_data_count), .wr_en(wr_en), .wr_rst_busy(wr_rst_busy)); endmodule (* CASCADE_HEIGHT = "0" *) (* CDC_SYNC_STAGES = "3" *) (* DOUT_RESET_VALUE = "0" *) (* ECC_MODE = "no_ecc" *) (* EN_ADV_FEATURE_ASYNC = "16'b0000011100000111" *) (* FIFO_MEMORY_TYPE = "block" *) (* FIFO_READ_LATENCY = "0" *) (* FIFO_WRITE_DEPTH = "256" *) (* FULL_RESET_VALUE = "1" *) (* ORIG_REF_NAME = "xpm_fifo_async" *) (* PROG_EMPTY_THRESH = "10" *) (* PROG_FULL_THRESH = "128" *) (* P_COMMON_CLOCK = "0" *) (* P_ECC_MODE = "0" *) (* P_FIFO_MEMORY_TYPE = "2" *) (* P_READ_MODE = "1" *) (* P_WAKEUP_TIME = "2" *) (* RD_DATA_COUNT_WIDTH = "8" *) (* READ_DATA_WIDTH = "50" *) (* READ_MODE = "fwft" *) (* RELATED_CLOCKS = "0" *) (* SIM_ASSERT_CHK = "0" *) (* USE_ADV_FEATURES = "0707" *) (* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH = "50" *) (* WR_DATA_COUNT_WIDTH = "8" *) (* XPM_MODULE = "TRUE" *) (* dont_touch = "true" *) (* is_du_within_envelope = "true" *) module axi_chip2chip_64B66B_xpm_fifo_async__xdcDup__1 (sleep, rst, wr_clk, wr_en, din, full, prog_full, wr_data_count, overflow, wr_rst_busy, almost_full, wr_ack, rd_clk, rd_en, dout, empty, prog_empty, rd_data_count, underflow, rd_rst_busy, almost_empty, data_valid, injectsbiterr, injectdbiterr, sbiterr, dbiterr); input sleep; input rst; input wr_clk; input wr_en; input [49:0]din; output full; output prog_full; output [7:0]wr_data_count; output overflow; output wr_rst_busy; output almost_full; output wr_ack; input rd_clk; input rd_en; output [49:0]dout; output empty; output prog_empty; output [7:0]rd_data_count; output underflow; output rd_rst_busy; output almost_empty; output data_valid; input injectsbiterr; input injectdbiterr; output sbiterr; output dbiterr; wire \ ; wire [49:0]din; wire [49:0]dout; wire empty; wire full; wire overflow; wire prog_empty; wire prog_full; wire rd_clk; wire [7:0]rd_data_count; wire rd_en; wire rd_rst_busy; wire rst; wire sleep; wire underflow; wire wr_clk; wire [7:0]wr_data_count; wire wr_en; wire wr_rst_busy; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_empty_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_full_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_data_valid_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED ; wire \NLW_gnuram_async_fifo.xpm_fifo_base_inst_wr_ack_UNCONNECTED ; assign almost_empty = \ ; assign almost_full = \ ; assign data_valid = \ ; assign dbiterr = \ ; assign sbiterr = \ ; assign wr_ack = \ ; GND GND (.G(\ )); (* CASCADE_HEIGHT = "0" *) (* CDC_DEST_SYNC_FF = "3" *) (* COMMON_CLOCK = "0" *) (* DOUT_RESET_VALUE = "0" *) (* ECC_MODE = "0" *) (* ENABLE_ECC = "0" *) (* EN_ADV_FEATURE = "16'b0000011100000111" *) (* EN_AE = "1'b0" *) (* EN_AF = "1'b0" *) (* EN_DVLD = "1'b0" *) (* EN_OF = "1'b1" *) (* EN_PE = "1'b1" *) (* EN_PF = "1'b1" *) (* EN_RDC = "1'b1" *) (* EN_UF = "1'b1" *) (* EN_WACK = "1'b0" *) (* EN_WDC = "1'b1" *) (* FG_EQ_ASYM_DOUT = "1'b0" *) (* FIFO_MEMORY_TYPE = "2" *) (* FIFO_MEM_TYPE = "2" *) (* FIFO_READ_DEPTH = "256" *) (* FIFO_READ_LATENCY = "0" *) (* FIFO_SIZE = "12800" *) (* FIFO_WRITE_DEPTH = "256" *) (* FULL_RESET_VALUE = "1" *) (* FULL_RST_VAL = "1'b1" *) (* KEEP_HIERARCHY = "soft" *) (* PE_THRESH_ADJ = "8" *) (* PE_THRESH_MAX = "251" *) (* PE_THRESH_MIN = "5" *) (* PF_THRESH_ADJ = "126" *) (* PF_THRESH_MAX = "251" *) (* PF_THRESH_MIN = "8" *) (* PROG_EMPTY_THRESH = "10" *) (* PROG_FULL_THRESH = "128" *) (* RD_DATA_COUNT_WIDTH = "8" *) (* RD_DC_WIDTH_EXT = "9" *) (* RD_LATENCY = "2" *) (* RD_MODE = "1" *) (* RD_PNTR_WIDTH = "8" *) (* READ_DATA_WIDTH = "50" *) (* READ_MODE = "1" *) (* READ_MODE_LL = "1" *) (* RELATED_CLOCKS = "0" *) (* REMOVE_WR_RD_PROT_LOGIC = "0" *) (* SIM_ASSERT_CHK = "0" *) (* USE_ADV_FEATURES = "0707" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WIDTH_RATIO = "1" *) (* WRITE_DATA_WIDTH = "50" *) (* WR_DATA_COUNT_WIDTH = "8" *) (* WR_DC_WIDTH_EXT = "9" *) (* WR_DEPTH_LOG = "8" *) (* WR_PNTR_WIDTH = "8" *) (* WR_RD_RATIO = "0" *) (* WR_WIDTH_LOG = "6" *) (* XPM_MODULE = "TRUE" *) (* both_stages_valid = "3" *) (* invalid = "0" *) (* stage1_valid = "2" *) (* stage2_valid = "1" *) axi_chip2chip_64B66B_xpm_fifo_base__xdcDup__1 \gnuram_async_fifo.xpm_fifo_base_inst (.almost_empty(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_empty_UNCONNECTED ), .almost_full(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_almost_full_UNCONNECTED ), .data_valid(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_data_valid_UNCONNECTED ), .dbiterr(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_dbiterr_UNCONNECTED ), .din(din), .dout(dout), .empty(empty), .full(full), .full_n(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_full_n_UNCONNECTED ), .injectdbiterr(1'b0), .injectsbiterr(1'b0), .overflow(overflow), .prog_empty(prog_empty), .prog_full(prog_full), .rd_clk(rd_clk), .rd_data_count(rd_data_count), .rd_en(rd_en), .rd_rst_busy(rd_rst_busy), .rst(rst), .sbiterr(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_sbiterr_UNCONNECTED ), .sleep(sleep), .underflow(underflow), .wr_ack(\NLW_gnuram_async_fifo.xpm_fifo_base_inst_wr_ack_UNCONNECTED ), .wr_clk(wr_clk), .wr_data_count(wr_data_count), .wr_en(wr_en), .wr_rst_busy(wr_rst_busy)); endmodule (* CASCADE_HEIGHT = "0" *) (* CDC_DEST_SYNC_FF = "3" *) (* COMMON_CLOCK = "0" *) (* DOUT_RESET_VALUE = "0" *) (* ECC_MODE = "0" *) (* ENABLE_ECC = "0" *) (* EN_ADV_FEATURE = "16'b0000011100000111" *) (* EN_AE = "1'b0" *) (* EN_AF = "1'b0" *) (* EN_DVLD = "1'b0" *) (* EN_OF = "1'b1" *) (* EN_PE = "1'b1" *) (* EN_PF = "1'b1" *) (* EN_RDC = "1'b1" *) (* EN_UF = "1'b1" *) (* EN_WACK = "1'b0" *) (* EN_WDC = "1'b1" *) (* FG_EQ_ASYM_DOUT = "1'b0" *) (* FIFO_MEMORY_TYPE = "2" *) (* FIFO_MEM_TYPE = "2" *) (* FIFO_READ_DEPTH = "256" *) (* FIFO_READ_LATENCY = "0" *) (* FIFO_SIZE = "12800" *) (* FIFO_WRITE_DEPTH = "256" *) (* FULL_RESET_VALUE = "1" *) (* FULL_RST_VAL = "1'b1" *) (* ORIG_REF_NAME = "xpm_fifo_base" *) (* PE_THRESH_ADJ = "8" *) (* PE_THRESH_MAX = "251" *) (* PE_THRESH_MIN = "5" *) (* PF_THRESH_ADJ = "126" *) (* PF_THRESH_MAX = "251" *) (* PF_THRESH_MIN = "8" *) (* PROG_EMPTY_THRESH = "10" *) (* PROG_FULL_THRESH = "128" *) (* RD_DATA_COUNT_WIDTH = "8" *) (* RD_DC_WIDTH_EXT = "9" *) (* RD_LATENCY = "2" *) (* RD_MODE = "1" *) (* RD_PNTR_WIDTH = "8" *) (* READ_DATA_WIDTH = "50" *) (* READ_MODE = "1" *) (* READ_MODE_LL = "1" *) (* RELATED_CLOCKS = "0" *) (* REMOVE_WR_RD_PROT_LOGIC = "0" *) (* SIM_ASSERT_CHK = "0" *) (* USE_ADV_FEATURES = "0707" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WIDTH_RATIO = "1" *) (* WRITE_DATA_WIDTH = "50" *) (* WR_DATA_COUNT_WIDTH = "8" *) (* WR_DC_WIDTH_EXT = "9" *) (* WR_DEPTH_LOG = "8" *) (* WR_PNTR_WIDTH = "8" *) (* WR_RD_RATIO = "0" *) (* WR_WIDTH_LOG = "6" *) (* XPM_MODULE = "TRUE" *) (* both_stages_valid = "3" *) (* invalid = "0" *) (* keep_hierarchy = "soft" *) (* stage1_valid = "2" *) (* stage2_valid = "1" *) module axi_chip2chip_64B66B_xpm_fifo_base (sleep, rst, wr_clk, wr_en, din, full, full_n, prog_full, wr_data_count, overflow, wr_rst_busy, almost_full, wr_ack, rd_clk, rd_en, dout, empty, prog_empty, rd_data_count, underflow, rd_rst_busy, almost_empty, data_valid, injectsbiterr, injectdbiterr, sbiterr, dbiterr); input sleep; input rst; input wr_clk; input wr_en; input [49:0]din; output full; output full_n; output prog_full; output [7:0]wr_data_count; output overflow; output wr_rst_busy; output almost_full; output wr_ack; input rd_clk; input rd_en; output [49:0]dout; output empty; output prog_empty; output [7:0]rd_data_count; output underflow; output rd_rst_busy; output almost_empty; output data_valid; input injectsbiterr; input injectdbiterr; output sbiterr; output dbiterr; wire \ ; wire [1:0]count_value_i; wire [1:0]curr_fwft_state; wire [7:0]diff_pntr_pe; wire [8:2]diff_pntr_pf_q; wire [8:2]diff_pntr_pf_q0; wire [49:0]din; wire [49:0]dout; wire empty; wire empty_fwft_i0; wire full; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_0 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_1 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_2 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_3 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_4 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_5 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_6 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_7 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_8 ; wire \gen_cdc_pntr.rpw_gray_reg_n_8 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_10 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_11 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_12 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_13 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_14 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_15 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_16 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_8 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_9 ; wire \gen_cdc_pntr.wpr_gray_reg_n_1 ; wire \gen_cdc_pntr.wpr_gray_reg_n_2 ; wire \gen_cdc_pntr.wpr_gray_reg_n_3 ; wire \gen_cdc_pntr.wpr_gray_reg_n_4 ; wire \gen_cdc_pntr.wpr_gray_reg_n_5 ; wire \gen_cdc_pntr.wpr_gray_reg_n_6 ; wire \gen_cdc_pntr.wpr_gray_reg_n_7 ; wire \gen_cdc_pntr.wpr_gray_reg_n_8 ; wire \gen_fwft.count_rst ; wire \gen_fwft.ram_regout_en ; wire \gen_fwft.rdpp1_inst_n_3 ; wire \gen_fwft.rdpp1_inst_n_4 ; wire \gen_fwft.rdpp1_inst_n_5 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7] ; wire \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0 ; wire \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0 ; wire \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0 ; wire \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0 ; wire [8:1]\grdc.diff_wr_rd_pntr_rdc ; wire \grdc.rd_data_count_i0 ; wire [8:1]\gwdc.diff_wr_rd_pntr1_out ; wire [1:0]next_fwft_state__0; wire overflow; wire overflow_i0; wire prog_empty; wire prog_full; wire ram_empty_i; wire ram_empty_i0; wire rd_clk; wire [7:0]rd_data_count; wire rd_en; wire [7:0]rd_pntr_ext; wire [7:0]rd_pntr_wr; wire [7:0]rd_pntr_wr_cdc; wire [8:0]rd_pntr_wr_cdc_dc; wire rd_rst_busy; wire rdp_inst_n_10; wire rdp_inst_n_19; wire rdp_inst_n_20; wire rdp_inst_n_21; wire rdp_inst_n_22; wire rdp_inst_n_23; wire rdp_inst_n_24; wire rdp_inst_n_25; wire rdp_inst_n_26; wire rdp_inst_n_27; wire rdp_inst_n_28; wire rdp_inst_n_29; wire rdp_inst_n_30; wire rdp_inst_n_31; wire rdp_inst_n_8; wire rdp_inst_n_9; wire rdpp1_inst_n_0; wire rdpp1_inst_n_1; wire rdpp1_inst_n_2; wire rdpp1_inst_n_3; wire rdpp1_inst_n_4; wire rdpp1_inst_n_5; wire rdpp1_inst_n_6; wire rdpp1_inst_n_7; wire rst; wire rst_d1; wire rst_d1_inst_n_1; wire sleep; wire [1:1]src_in_bin00_out; wire underflow; wire underflow_i0; wire wr_clk; wire [7:0]wr_data_count; wire wr_en; wire [8:0]wr_pntr_ext; wire [8:1]wr_pntr_plus1_pf; wire wr_pntr_plus1_pf_carry; wire [7:0]wr_pntr_rd_cdc; wire [8:0]wr_pntr_rd_cdc_dc; wire wr_rst_busy; wire wrpp2_inst_n_0; wire wrpp2_inst_n_1; wire wrpp2_inst_n_2; wire wrpp2_inst_n_3; wire wrpp2_inst_n_4; wire wrpp2_inst_n_5; wire wrpp2_inst_n_6; wire wrpp2_inst_n_7; wire wrst_busy; wire \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED ; wire \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED ; wire \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED ; wire \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED ; wire [49:0]\NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED ; assign almost_empty = \ ; assign almost_full = \ ; assign data_valid = \ ; assign dbiterr = \ ; assign full_n = \ ; assign sbiterr = \ ; assign wr_ack = \ ; (* SOFT_HLUTNM = "soft_lutpair92" *) LUT4 #( .INIT(16'h6A85)) \FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1 (.I0(curr_fwft_state[0]), .I1(rd_en), .I2(curr_fwft_state[1]), .I3(ram_empty_i), .O(next_fwft_state__0[0])); (* SOFT_HLUTNM = "soft_lutpair92" *) LUT3 #( .INIT(8'h7C)) \FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1 (.I0(rd_en), .I1(curr_fwft_state[1]), .I2(curr_fwft_state[0]), .O(next_fwft_state__0[1])); (* FSM_ENCODED_STATES = "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11" *) FDRE #( .INIT(1'b0)) \FSM_sequential_gen_fwft.curr_fwft_state_reg[0] (.C(rd_clk), .CE(1'b1), .D(next_fwft_state__0[0]), .Q(curr_fwft_state[0]), .R(rd_rst_busy)); (* FSM_ENCODED_STATES = "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11" *) FDRE #( .INIT(1'b0)) \FSM_sequential_gen_fwft.curr_fwft_state_reg[1] (.C(rd_clk), .CE(1'b1), .D(next_fwft_state__0[1]), .Q(curr_fwft_state[1]), .R(rd_rst_busy)); GND GND (.G(\ )); (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) axi_chip2chip_64B66B_xpm_cdc_gray__parameterized1__8 \gen_cdc_pntr.rd_pntr_cdc_dc_inst (.dest_clk(wr_clk), .dest_out_bin(rd_pntr_wr_cdc_dc), .src_clk(rd_clk), .src_in_bin({rdp_inst_n_24,rdp_inst_n_25,rdp_inst_n_26,rdp_inst_n_27,rdp_inst_n_28,rdp_inst_n_29,rdp_inst_n_30,src_in_bin00_out,rdp_inst_n_31})); (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "8" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) axi_chip2chip_64B66B_xpm_cdc_gray__9 \gen_cdc_pntr.rd_pntr_cdc_inst (.dest_clk(wr_clk), .dest_out_bin(rd_pntr_wr_cdc), .src_clk(rd_clk), .src_in_bin(rd_pntr_ext)); axi_chip2chip_64B66B_xpm_fifo_reg_vec_34 \gen_cdc_pntr.rpw_gray_reg (.D(rd_pntr_wr_cdc), .Q(wr_pntr_plus1_pf), .d_out_reg(\gen_cdc_pntr.rpw_gray_reg_n_8 ), .\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg ({wrpp2_inst_n_0,wrpp2_inst_n_1,wrpp2_inst_n_2,wrpp2_inst_n_3,wrpp2_inst_n_4,wrpp2_inst_n_5,wrpp2_inst_n_6,wrpp2_inst_n_7}), .\reg_out_i_reg[7]_0 (rd_pntr_wr), .rst(rst), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wrst_busy(wrst_busy)); axi_chip2chip_64B66B_xpm_fifo_reg_vec__parameterized0_35 \gen_cdc_pntr.rpw_gray_reg_dc (.D(rd_pntr_wr_cdc_dc), .Q({\gen_cdc_pntr.rpw_gray_reg_dc_n_0 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_1 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_2 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_3 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_4 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_5 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_6 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_7 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_8 }), .wr_clk(wr_clk), .wrst_busy(wrst_busy)); axi_chip2chip_64B66B_xpm_fifo_reg_vec_36 \gen_cdc_pntr.wpr_gray_reg (.D(wr_pntr_rd_cdc), .Q(curr_fwft_state), .\gen_pf_ic_rc.ram_empty_i_reg (rd_pntr_ext), .\gen_pf_ic_rc.ram_empty_i_reg_0 ({rdpp1_inst_n_0,rdpp1_inst_n_1,rdpp1_inst_n_2,rdpp1_inst_n_3,rdpp1_inst_n_4,rdpp1_inst_n_5,rdpp1_inst_n_6,rdpp1_inst_n_7}), .ram_empty_i(ram_empty_i), .ram_empty_i0(ram_empty_i0), .rd_clk(rd_clk), .rd_en(rd_en), .\reg_out_i_reg[0]_0 (rd_rst_busy), .\reg_out_i_reg[7]_0 ({\gen_cdc_pntr.wpr_gray_reg_n_1 ,\gen_cdc_pntr.wpr_gray_reg_n_2 ,\gen_cdc_pntr.wpr_gray_reg_n_3 ,\gen_cdc_pntr.wpr_gray_reg_n_4 ,\gen_cdc_pntr.wpr_gray_reg_n_5 ,\gen_cdc_pntr.wpr_gray_reg_n_6 ,\gen_cdc_pntr.wpr_gray_reg_n_7 ,\gen_cdc_pntr.wpr_gray_reg_n_8 })); axi_chip2chip_64B66B_xpm_fifo_reg_vec__parameterized0_37 \gen_cdc_pntr.wpr_gray_reg_dc (.D(\grdc.diff_wr_rd_pntr_rdc ), .DI({rdp_inst_n_9,\gen_fwft.rdpp1_inst_n_5 }), .Q({\gen_cdc_pntr.wpr_gray_reg_dc_n_8 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_9 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_10 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_11 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_12 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_13 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_14 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_15 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_16 }), .S({rdp_inst_n_19,rdp_inst_n_20,rdp_inst_n_21,rdp_inst_n_22,rdp_inst_n_23,\gen_fwft.rdpp1_inst_n_3 ,\gen_fwft.rdpp1_inst_n_4 }), .\grdc.rd_data_count_i_reg[7] (count_value_i[1]), .\grdc.rd_data_count_i_reg[7]_0 (rd_pntr_ext[6:1]), .\grdc.rd_data_count_i_reg[8] (rdp_inst_n_10), .rd_clk(rd_clk), .\reg_out_i_reg[8]_0 (rd_rst_busy), .\reg_out_i_reg[8]_1 (wr_pntr_rd_cdc_dc)); (* DEST_SYNC_FF = "5" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) axi_chip2chip_64B66B_xpm_cdc_gray__parameterized0__4 \gen_cdc_pntr.wr_pntr_cdc_dc_inst (.dest_clk(rd_clk), .dest_out_bin(wr_pntr_rd_cdc_dc), .src_clk(wr_clk), .src_in_bin(wr_pntr_ext)); (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "8" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) axi_chip2chip_64B66B_xpm_cdc_gray__8 \gen_cdc_pntr.wr_pntr_cdc_inst (.dest_clk(rd_clk), .dest_out_bin(wr_pntr_rd_cdc), .src_clk(wr_clk), .src_in_bin(wr_pntr_ext[7:0])); (* SOFT_HLUTNM = "soft_lutpair91" *) LUT4 #( .INIT(16'hF380)) \gen_fwft.empty_fwft_i_i_1 (.I0(rd_en), .I1(curr_fwft_state[0]), .I2(curr_fwft_state[1]), .I3(empty), .O(empty_fwft_i0)); FDSE #( .INIT(1'b1)) \gen_fwft.empty_fwft_i_reg (.C(rd_clk), .CE(1'b1), .D(empty_fwft_i0), .Q(empty), .S(rd_rst_busy)); axi_chip2chip_64B66B_xpm_counter_updn_38 \gen_fwft.rdpp1_inst (.DI(\gen_fwft.rdpp1_inst_n_5 ), .Q(count_value_i), .S({\gen_fwft.rdpp1_inst_n_3 ,\gen_fwft.rdpp1_inst_n_4 }), .SR(\gen_fwft.count_rst ), .\count_value_i_reg[0]_0 (curr_fwft_state), .\grdc.rd_data_count_i_reg[7] (rd_pntr_ext[1:0]), .\grdc.rd_data_count_i_reg[7]_0 ({\gen_cdc_pntr.wpr_gray_reg_dc_n_15 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_16 }), .ram_empty_i(ram_empty_i), .rd_clk(rd_clk), .rd_en(rd_en), .src_in_bin(src_in_bin00_out)); FDSE #( .INIT(1'b1)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg (.C(wr_clk), .CE(1'b1), .D(\gen_cdc_pntr.rpw_gray_reg_n_8 ), .Q(full), .S(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[0] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[0]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[1] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[1]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[2] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[2]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[3]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[4]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[5] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[5]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[6] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[6]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[7]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7] ), .R(rd_rst_busy)); LUT4 #( .INIT(16'h88B8)) \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1 (.I0(prog_empty), .I1(empty), .I2(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0 ), .I3(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0 ), .O(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0 )); LUT4 #( .INIT(16'h01FF)) \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2 (.I0(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0] ), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1] ), .I2(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2] ), .I3(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3] ), .O(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0 )); LUT4 #( .INIT(16'hFFFE)) \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3 (.I0(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5] ), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4] ), .I2(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7] ), .I3(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6] ), .O(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0 )); FDSE #( .INIT(1'b1)) \gen_pf_ic_rc.gpe_ic.prog_empty_i_reg (.C(rd_clk), .CE(1'b1), .D(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0 ), .Q(prog_empty), .S(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[2] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[2]), .Q(diff_pntr_pf_q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[3] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[3]), .Q(diff_pntr_pf_q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[4]), .Q(diff_pntr_pf_q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[5]), .Q(diff_pntr_pf_q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[6] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[6]), .Q(diff_pntr_pf_q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[7] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[7]), .Q(diff_pntr_pf_q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[8]), .Q(diff_pntr_pf_q[8]), .R(wrst_busy)); LUT6 #( .INIT(64'h8000000000000000)) \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2 (.I0(diff_pntr_pf_q[3]), .I1(diff_pntr_pf_q[2]), .I2(diff_pntr_pf_q[6]), .I3(diff_pntr_pf_q[7]), .I4(diff_pntr_pf_q[4]), .I5(diff_pntr_pf_q[5]), .O(\gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0 )); FDSE #( .INIT(1'b1)) \gen_pf_ic_rc.gpf_ic.prog_full_i_reg (.C(wr_clk), .CE(1'b1), .D(rst_d1_inst_n_1), .Q(prog_full), .S(wrst_busy)); FDSE #( .INIT(1'b1)) \gen_pf_ic_rc.ram_empty_i_reg (.C(rd_clk), .CE(1'b1), .D(ram_empty_i0), .Q(ram_empty_i), .S(rd_rst_busy)); (* ADDR_WIDTH_A = "8" *) (* ADDR_WIDTH_B = "8" *) (* AUTO_SLEEP_TIME = "0" *) (* BYTE_WRITE_WIDTH_A = "50" *) (* BYTE_WRITE_WIDTH_B = "50" *) (* CASCADE_HEIGHT = "0" *) (* CLOCKING_MODE = "1" *) (* ECC_MODE = "0" *) (* KEEP_HIERARCHY = "soft" *) (* MAX_NUM_CHAR = "0" *) (* \MEM.ADDRESS_SPACE *) (* \MEM.ADDRESS_SPACE_BEGIN = "0" *) (* \MEM.ADDRESS_SPACE_DATA_LSB = "0" *) (* \MEM.ADDRESS_SPACE_DATA_MSB = "49" *) (* \MEM.ADDRESS_SPACE_END = "511" *) (* \MEM.CORE_MEMORY_WIDTH = "50" *) (* MEMORY_INIT_FILE = "none" *) (* MEMORY_INIT_PARAM = "" *) (* MEMORY_OPTIMIZATION = "true" *) (* MEMORY_PRIMITIVE = "2" *) (* MEMORY_SIZE = "12800" *) (* MEMORY_TYPE = "1" *) (* MESSAGE_CONTROL = "0" *) (* NUM_CHAR_LOC = "0" *) (* P_ECC_MODE = "no_ecc" *) (* P_ENABLE_BYTE_WRITE_A = "0" *) (* P_ENABLE_BYTE_WRITE_B = "0" *) (* P_MAX_DEPTH_DATA = "256" *) (* P_MEMORY_OPT = "yes" *) (* P_MEMORY_PRIMITIVE = "block" *) (* P_MIN_WIDTH_DATA = "50" *) (* P_MIN_WIDTH_DATA_A = "50" *) (* P_MIN_WIDTH_DATA_B = "50" *) (* P_MIN_WIDTH_DATA_ECC = "50" *) (* P_MIN_WIDTH_DATA_LDW = "4" *) (* P_MIN_WIDTH_DATA_SHFT = "50" *) (* P_NUM_COLS_WRITE_A = "1" *) (* P_NUM_COLS_WRITE_B = "1" *) (* P_NUM_ROWS_READ_A = "1" *) (* P_NUM_ROWS_READ_B = "1" *) (* P_NUM_ROWS_WRITE_A = "1" *) (* P_NUM_ROWS_WRITE_B = "1" *) (* P_SDP_WRITE_MODE = "no" *) (* P_WIDTH_ADDR_LSB_READ_A = "0" *) (* P_WIDTH_ADDR_LSB_READ_B = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_B = "0" *) (* P_WIDTH_ADDR_READ_A = "8" *) (* P_WIDTH_ADDR_READ_B = "8" *) (* P_WIDTH_ADDR_WRITE_A = "8" *) (* P_WIDTH_ADDR_WRITE_B = "8" *) (* P_WIDTH_COL_WRITE_A = "50" *) (* P_WIDTH_COL_WRITE_B = "50" *) (* READ_DATA_WIDTH_A = "50" *) (* READ_DATA_WIDTH_B = "50" *) (* READ_LATENCY_A = "2" *) (* READ_LATENCY_B = "2" *) (* READ_RESET_VALUE_A = "0" *) (* READ_RESET_VALUE_B = "0" *) (* RST_MODE_A = "SYNC" *) (* RST_MODE_B = "SYNC" *) (* SIM_ASSERT_CHK = "0" *) (* USE_EMBEDDED_CONSTRAINT = "0" *) (* USE_MEM_INIT = "0" *) (* USE_MEM_INIT_MMI = "0" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH_A = "50" *) (* WRITE_DATA_WIDTH_B = "50" *) (* WRITE_MODE_A = "2" *) (* WRITE_MODE_B = "2" *) (* WRITE_PROTECT = "1" *) (* XPM_MODULE = "TRUE" *) (* rsta_loop_iter = "52" *) (* rstb_loop_iter = "52" *) axi_chip2chip_64B66B_xpm_memory_base \gen_sdpram.xpm_memory_base_inst (.addra(wr_pntr_ext[7:0]), .addrb(rd_pntr_ext), .clka(wr_clk), .clkb(rd_clk), .dbiterra(\NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED ), .dbiterrb(\NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED ), .dina(din), .dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .douta(\NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED [49:0]), .doutb(dout), .ena(wr_pntr_plus1_pf_carry), .enb(rdp_inst_n_8), .injectdbiterra(1'b0), .injectdbiterrb(1'b0), .injectsbiterra(1'b0), .injectsbiterrb(1'b0), .regcea(1'b0), .regceb(\gen_fwft.ram_regout_en ), .rsta(1'b0), .rstb(rd_rst_busy), .sbiterra(\NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED ), .sbiterrb(\NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED ), .sleep(sleep), .wea(1'b0), .web(1'b0)); (* SOFT_HLUTNM = "soft_lutpair91" *) LUT3 #( .INIT(8'h62)) \gen_sdpram.xpm_memory_base_inst_i_3 (.I0(curr_fwft_state[0]), .I1(curr_fwft_state[1]), .I2(rd_en), .O(\gen_fwft.ram_regout_en )); FDRE #( .INIT(1'b0)) \gof.overflow_i_reg (.C(wr_clk), .CE(1'b1), .D(overflow_i0), .Q(overflow), .R(1'b0)); FDRE \grdc.rd_data_count_i_reg[1] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [1]), .Q(rd_data_count[0]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[2] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [2]), .Q(rd_data_count[1]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[3] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [3]), .Q(rd_data_count[2]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[4] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [4]), .Q(rd_data_count[3]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[5] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [5]), .Q(rd_data_count[4]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[6] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [6]), .Q(rd_data_count[5]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[7] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [7]), .Q(rd_data_count[6]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[8] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [8]), .Q(rd_data_count[7]), .R(\grdc.rd_data_count_i0 )); FDRE #( .INIT(1'b0)) \guf.underflow_i_reg (.C(rd_clk), .CE(1'b1), .D(underflow_i0), .Q(underflow), .R(1'b0)); FDRE \gwdc.wr_data_count_i_reg[1] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [1]), .Q(wr_data_count[0]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[2] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [2]), .Q(wr_data_count[1]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[3] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [3]), .Q(wr_data_count[2]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[4] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [4]), .Q(wr_data_count[3]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[5] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [5]), .Q(wr_data_count[4]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[6] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [6]), .Q(wr_data_count[5]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[7] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [7]), .Q(wr_data_count[6]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[8] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [8]), .Q(wr_data_count[7]), .R(wrst_busy)); axi_chip2chip_64B66B_xpm_counter_updn__parameterized0_39 rdp_inst (.D(diff_pntr_pe), .DI(rdp_inst_n_9), .Q(rd_pntr_ext), .S({rdp_inst_n_19,rdp_inst_n_20,rdp_inst_n_21,rdp_inst_n_22,rdp_inst_n_23}), .\count_value_i_reg[0]_0 (curr_fwft_state), .\count_value_i_reg[7]_0 (rdp_inst_n_10), .\count_value_i_reg[8]_0 (rd_rst_busy), .enb(rdp_inst_n_8), .\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] ({\gen_cdc_pntr.wpr_gray_reg_n_1 ,\gen_cdc_pntr.wpr_gray_reg_n_2 ,\gen_cdc_pntr.wpr_gray_reg_n_3 ,\gen_cdc_pntr.wpr_gray_reg_n_4 ,\gen_cdc_pntr.wpr_gray_reg_n_5 ,\gen_cdc_pntr.wpr_gray_reg_n_6 ,\gen_cdc_pntr.wpr_gray_reg_n_7 ,\gen_cdc_pntr.wpr_gray_reg_n_8 }), .\grdc.rd_data_count_i_reg[7] (count_value_i), .\grdc.rd_data_count_i_reg[8] ({\gen_cdc_pntr.wpr_gray_reg_dc_n_8 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_9 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_10 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_11 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_12 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_13 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_14 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_15 }), .ram_empty_i(ram_empty_i), .rd_clk(rd_clk), .rd_en(rd_en), .src_in_bin({rdp_inst_n_24,rdp_inst_n_25,rdp_inst_n_26,rdp_inst_n_27,rdp_inst_n_28,rdp_inst_n_29,rdp_inst_n_30,rdp_inst_n_31})); axi_chip2chip_64B66B_xpm_counter_updn__parameterized1_40 rdpp1_inst (.E(rdp_inst_n_8), .Q({rdpp1_inst_n_0,rdpp1_inst_n_1,rdpp1_inst_n_2,rdpp1_inst_n_3,rdpp1_inst_n_4,rdpp1_inst_n_5,rdpp1_inst_n_6,rdpp1_inst_n_7}), .\count_value_i_reg[0]_0 (rd_rst_busy), .\count_value_i_reg[1]_0 (curr_fwft_state), .ram_empty_i(ram_empty_i), .rd_clk(rd_clk), .rd_en(rd_en)); axi_chip2chip_64B66B_xpm_fifo_reg_bit_41 rst_d1_inst (.Q(diff_pntr_pf_q[8]), .\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] (rst_d1_inst_n_1), .\gen_pf_ic_rc.gpf_ic.prog_full_i_reg (\gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0 ), .\gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 (full), .overflow_i0(overflow_i0), .prog_full(prog_full), .rst(rst), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), .wrst_busy(wrst_busy)); axi_chip2chip_64B66B_xpm_counter_updn__parameterized0_42 wrp_inst (.D(\gwdc.diff_wr_rd_pntr1_out ), .Q(wr_pntr_ext), .\count_value_i_reg[6]_0 (full), .\gwdc.wr_data_count_i_reg[8] ({\gen_cdc_pntr.rpw_gray_reg_dc_n_0 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_1 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_2 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_3 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_4 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_5 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_6 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_7 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_8 }), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wrst_busy(wrst_busy)); axi_chip2chip_64B66B_xpm_counter_updn__parameterized1_43 wrpp1_inst (.D(diff_pntr_pf_q0), .Q(wr_pntr_plus1_pf), .\count_value_i_reg[6]_0 (full), .\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] (rd_pntr_wr), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wrst_busy(wrst_busy)); axi_chip2chip_64B66B_xpm_counter_updn__parameterized2_44 wrpp2_inst (.Q({wrpp2_inst_n_0,wrpp2_inst_n_1,wrpp2_inst_n_2,wrpp2_inst_n_3,wrpp2_inst_n_4,wrpp2_inst_n_5,wrpp2_inst_n_6,wrpp2_inst_n_7}), .\count_value_i_reg[6]_0 (full), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wrst_busy(wrst_busy)); axi_chip2chip_64B66B_xpm_fifo_rst__xdcDup__2 xpm_fifo_rst_inst (.Q(curr_fwft_state), .SR(\grdc.rd_data_count_i0 ), .\count_value_i_reg[7] (full), .\gen_rst_ic.fifo_rd_rst_ic_reg_0 (rd_rst_busy), .\gen_rst_ic.fifo_rd_rst_ic_reg_1 (\gen_fwft.count_rst ), .\guf.underflow_i_reg (empty), .ram_empty_i(ram_empty_i), .rd_clk(rd_clk), .rd_en(rd_en), .rst(rst), .rst_d1(rst_d1), .underflow_i0(underflow_i0), .wr_clk(wr_clk), .wr_en(wr_en), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wr_rst_busy(wr_rst_busy), .wrst_busy(wrst_busy)); endmodule (* CASCADE_HEIGHT = "0" *) (* CDC_DEST_SYNC_FF = "3" *) (* COMMON_CLOCK = "0" *) (* DOUT_RESET_VALUE = "0" *) (* ECC_MODE = "0" *) (* ENABLE_ECC = "0" *) (* EN_ADV_FEATURE = "16'b0000011100000111" *) (* EN_AE = "1'b0" *) (* EN_AF = "1'b0" *) (* EN_DVLD = "1'b0" *) (* EN_OF = "1'b1" *) (* EN_PE = "1'b1" *) (* EN_PF = "1'b1" *) (* EN_RDC = "1'b1" *) (* EN_UF = "1'b1" *) (* EN_WACK = "1'b0" *) (* EN_WDC = "1'b1" *) (* FG_EQ_ASYM_DOUT = "1'b0" *) (* FIFO_MEMORY_TYPE = "2" *) (* FIFO_MEM_TYPE = "2" *) (* FIFO_READ_DEPTH = "512" *) (* FIFO_READ_LATENCY = "0" *) (* FIFO_SIZE = "20992" *) (* FIFO_WRITE_DEPTH = "512" *) (* FULL_RESET_VALUE = "1" *) (* FULL_RST_VAL = "1'b1" *) (* ORIG_REF_NAME = "xpm_fifo_base" *) (* PE_THRESH_ADJ = "8" *) (* PE_THRESH_MAX = "507" *) (* PE_THRESH_MIN = "5" *) (* PF_THRESH_ADJ = "382" *) (* PF_THRESH_MAX = "507" *) (* PF_THRESH_MIN = "8" *) (* PROG_EMPTY_THRESH = "10" *) (* PROG_FULL_THRESH = "384" *) (* RD_DATA_COUNT_WIDTH = "9" *) (* RD_DC_WIDTH_EXT = "10" *) (* RD_LATENCY = "2" *) (* RD_MODE = "1" *) (* RD_PNTR_WIDTH = "9" *) (* READ_DATA_WIDTH = "41" *) (* READ_MODE = "1" *) (* READ_MODE_LL = "1" *) (* RELATED_CLOCKS = "0" *) (* REMOVE_WR_RD_PROT_LOGIC = "0" *) (* SIM_ASSERT_CHK = "0" *) (* USE_ADV_FEATURES = "0707" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WIDTH_RATIO = "1" *) (* WRITE_DATA_WIDTH = "41" *) (* WR_DATA_COUNT_WIDTH = "9" *) (* WR_DC_WIDTH_EXT = "10" *) (* WR_DEPTH_LOG = "9" *) (* WR_PNTR_WIDTH = "9" *) (* WR_RD_RATIO = "0" *) (* WR_WIDTH_LOG = "6" *) (* XPM_MODULE = "TRUE" *) (* both_stages_valid = "3" *) (* invalid = "0" *) (* keep_hierarchy = "soft" *) (* stage1_valid = "2" *) (* stage2_valid = "1" *) module axi_chip2chip_64B66B_xpm_fifo_base__parameterized0 (sleep, rst, wr_clk, wr_en, din, full, full_n, prog_full, wr_data_count, overflow, wr_rst_busy, almost_full, wr_ack, rd_clk, rd_en, dout, empty, prog_empty, rd_data_count, underflow, rd_rst_busy, almost_empty, data_valid, injectsbiterr, injectdbiterr, sbiterr, dbiterr); input sleep; input rst; input wr_clk; input wr_en; input [40:0]din; output full; output full_n; output prog_full; output [8:0]wr_data_count; output overflow; output wr_rst_busy; output almost_full; output wr_ack; input rd_clk; input rd_en; output [40:0]dout; output empty; output prog_empty; output [8:0]rd_data_count; output underflow; output rd_rst_busy; output almost_empty; output data_valid; input injectsbiterr; input injectdbiterr; output sbiterr; output dbiterr; wire \ ; wire clr_full; wire [1:0]count_value_i; wire [1:0]curr_fwft_state; wire [8:0]diff_pntr_pe; wire [9:2]diff_pntr_pf_q; wire [9:2]diff_pntr_pf_q0; wire [40:0]din; wire [40:0]dout; wire empty; wire empty_fwft_i0; wire full; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_0 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_1 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_2 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_3 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_4 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_5 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_6 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_7 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_8 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_9 ; wire \gen_cdc_pntr.rpw_gray_reg_n_9 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_0 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_1 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_10 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_11 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_12 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_13 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_14 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_15 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_16 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_2 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_3 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_4 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_5 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_6 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_7 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_8 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_9 ; wire \gen_cdc_pntr.wpr_gray_reg_n_0 ; wire \gen_cdc_pntr.wpr_gray_reg_n_1 ; wire \gen_cdc_pntr.wpr_gray_reg_n_2 ; wire \gen_cdc_pntr.wpr_gray_reg_n_3 ; wire \gen_cdc_pntr.wpr_gray_reg_n_4 ; wire \gen_cdc_pntr.wpr_gray_reg_n_5 ; wire \gen_cdc_pntr.wpr_gray_reg_n_6 ; wire \gen_cdc_pntr.wpr_gray_reg_n_7 ; wire \gen_cdc_pntr.wpr_gray_reg_n_8 ; wire \gen_fwft.count_rst ; wire \gen_fwft.ram_regout_en ; wire \gen_fwft.rdpp1_inst_n_3 ; wire \gen_fwft.rdpp1_inst_n_4 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[8] ; wire \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0 ; wire \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0 ; wire \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0 ; wire \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0 ; wire [9:1]\grdc.diff_wr_rd_pntr_rdc ; wire \grdc.rd_data_count_i0 ; wire [9:1]\gwdc.diff_wr_rd_pntr1_out ; wire [1:0]next_fwft_state__0; wire overflow; wire overflow_i0; wire p_1_in; wire prog_empty; wire prog_full; wire ram_empty_i; wire ram_empty_i0; wire ram_rd_en_i; wire rd_clk; wire [8:0]rd_data_count; wire rd_en; wire [8:0]rd_pntr_ext; wire [8:0]rd_pntr_wr; wire [8:0]rd_pntr_wr_cdc; wire [9:0]rd_pntr_wr_cdc_dc; wire rd_rst_busy; wire rdp_inst_n_0; wire rdp_inst_n_11; wire rdp_inst_n_21; wire rdp_inst_n_31; wire rdp_inst_n_32; wire rdp_inst_n_33; wire rdp_inst_n_34; wire rdp_inst_n_35; wire rdp_inst_n_36; wire rdp_inst_n_37; wire rdp_inst_n_38; wire rst; wire rst_d1; wire rst_d1_inst_n_1; wire sleep; wire [9:0]src_in_bin00_out; wire underflow; wire underflow_i0; wire wr_clk; wire [8:0]wr_data_count; wire wr_en; wire [9:0]wr_pntr_ext; wire [9:1]wr_pntr_plus1_pf; wire wr_pntr_plus1_pf_carry; wire [8:0]wr_pntr_rd_cdc; wire [9:0]wr_pntr_rd_cdc_dc; wire wr_rst_busy; wire wrpp2_inst_n_0; wire wrpp2_inst_n_1; wire wrpp2_inst_n_2; wire wrpp2_inst_n_3; wire wrpp2_inst_n_4; wire wrpp2_inst_n_5; wire wrpp2_inst_n_6; wire wrpp2_inst_n_7; wire wrpp2_inst_n_8; wire wrst_busy; wire \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED ; wire \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED ; wire \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED ; wire \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED ; wire [40:0]\NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED ; assign almost_empty = \ ; assign almost_full = \ ; assign data_valid = \ ; assign dbiterr = \ ; assign full_n = \ ; assign sbiterr = \ ; assign wr_ack = \ ; (* SOFT_HLUTNM = "soft_lutpair203" *) LUT4 #( .INIT(16'h69A1)) \FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1 (.I0(ram_empty_i), .I1(curr_fwft_state[1]), .I2(curr_fwft_state[0]), .I3(rd_en), .O(next_fwft_state__0[0])); (* SOFT_HLUTNM = "soft_lutpair203" *) LUT3 #( .INIT(8'h7C)) \FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1 (.I0(rd_en), .I1(curr_fwft_state[0]), .I2(curr_fwft_state[1]), .O(next_fwft_state__0[1])); (* FSM_ENCODED_STATES = "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11" *) FDRE #( .INIT(1'b0)) \FSM_sequential_gen_fwft.curr_fwft_state_reg[0] (.C(rd_clk), .CE(1'b1), .D(next_fwft_state__0[0]), .Q(curr_fwft_state[0]), .R(rd_rst_busy)); (* FSM_ENCODED_STATES = "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11" *) FDRE #( .INIT(1'b0)) \FSM_sequential_gen_fwft.curr_fwft_state_reg[1] (.C(rd_clk), .CE(1'b1), .D(next_fwft_state__0[1]), .Q(curr_fwft_state[1]), .R(rd_rst_busy)); GND GND (.G(\ )); (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "10" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) axi_chip2chip_64B66B_xpm_cdc_gray__parameterized3 \gen_cdc_pntr.rd_pntr_cdc_dc_inst (.dest_clk(wr_clk), .dest_out_bin(rd_pntr_wr_cdc_dc), .src_clk(rd_clk), .src_in_bin(src_in_bin00_out)); (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) axi_chip2chip_64B66B_xpm_cdc_gray__parameterized1__12 \gen_cdc_pntr.rd_pntr_cdc_inst (.dest_clk(wr_clk), .dest_out_bin(rd_pntr_wr_cdc), .src_clk(rd_clk), .src_in_bin(rd_pntr_ext)); axi_chip2chip_64B66B_xpm_fifo_reg_vec__parameterized0_4 \gen_cdc_pntr.rpw_gray_reg (.D(rd_pntr_wr_cdc), .Q(rd_pntr_wr), .clr_full(clr_full), .\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 ({wrpp2_inst_n_0,wrpp2_inst_n_1,wrpp2_inst_n_2,wrpp2_inst_n_3,wrpp2_inst_n_4,wrpp2_inst_n_5,wrpp2_inst_n_6,wrpp2_inst_n_7,wrpp2_inst_n_8}), .\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg (wr_pntr_plus1_pf), .\reg_out_i_reg[0]_0 (\gen_cdc_pntr.rpw_gray_reg_n_9 ), .wr_clk(wr_clk), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wrst_busy(wrst_busy)); axi_chip2chip_64B66B_xpm_fifo_reg_vec__parameterized1_5 \gen_cdc_pntr.rpw_gray_reg_dc (.D(rd_pntr_wr_cdc_dc), .Q({\gen_cdc_pntr.rpw_gray_reg_dc_n_0 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_1 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_2 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_3 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_4 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_5 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_6 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_7 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_8 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_9 }), .wr_clk(wr_clk), .wrst_busy(wrst_busy)); axi_chip2chip_64B66B_xpm_fifo_reg_vec__parameterized0_6 \gen_cdc_pntr.wpr_gray_reg (.D(diff_pntr_pe), .DI(p_1_in), .Q({\gen_cdc_pntr.wpr_gray_reg_n_0 ,\gen_cdc_pntr.wpr_gray_reg_n_1 ,\gen_cdc_pntr.wpr_gray_reg_n_2 ,\gen_cdc_pntr.wpr_gray_reg_n_3 ,\gen_cdc_pntr.wpr_gray_reg_n_4 ,\gen_cdc_pntr.wpr_gray_reg_n_5 ,\gen_cdc_pntr.wpr_gray_reg_n_6 ,\gen_cdc_pntr.wpr_gray_reg_n_7 ,\gen_cdc_pntr.wpr_gray_reg_n_8 }), .S({rdp_inst_n_31,rdp_inst_n_32,rdp_inst_n_33,rdp_inst_n_34,rdp_inst_n_35,rdp_inst_n_36,rdp_inst_n_37,rdp_inst_n_38}), .\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8] (rd_pntr_ext[8]), .rd_clk(rd_clk), .\reg_out_i_reg[0]_0 (rd_rst_busy), .\reg_out_i_reg[8]_0 (wr_pntr_rd_cdc)); axi_chip2chip_64B66B_xpm_fifo_reg_vec__parameterized1_7 \gen_cdc_pntr.wpr_gray_reg_dc (.D(wr_pntr_rd_cdc_dc), .DI({\gen_cdc_pntr.wpr_gray_reg_dc_n_0 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_1 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_2 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_3 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_4 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_5 }), .Q({\gen_cdc_pntr.wpr_gray_reg_dc_n_6 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_7 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_8 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_9 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_10 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_11 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_12 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_13 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_14 }), .S(\gen_cdc_pntr.wpr_gray_reg_dc_n_16 ), .\grdc.rd_data_count_i_reg[7] (count_value_i[1]), .\grdc.rd_data_count_i_reg[9] ({rdp_inst_n_0,rd_pntr_ext[8:1]}), .rd_clk(rd_clk), .\reg_out_i_reg[7]_0 (\gen_cdc_pntr.wpr_gray_reg_dc_n_15 ), .\reg_out_i_reg[9]_0 (rd_rst_busy)); (* DEST_SYNC_FF = "5" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "10" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) axi_chip2chip_64B66B_xpm_cdc_gray__parameterized2 \gen_cdc_pntr.wr_pntr_cdc_dc_inst (.dest_clk(rd_clk), .dest_out_bin(wr_pntr_rd_cdc_dc), .src_clk(wr_clk), .src_in_bin(wr_pntr_ext)); (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) axi_chip2chip_64B66B_xpm_cdc_gray__parameterized1__11 \gen_cdc_pntr.wr_pntr_cdc_inst (.dest_clk(rd_clk), .dest_out_bin(wr_pntr_rd_cdc), .src_clk(wr_clk), .src_in_bin(wr_pntr_ext[8:0])); (* SOFT_HLUTNM = "soft_lutpair202" *) LUT4 #( .INIT(16'hE0CC)) \gen_fwft.empty_fwft_i_i_1 (.I0(rd_en), .I1(empty), .I2(curr_fwft_state[1]), .I3(curr_fwft_state[0]), .O(empty_fwft_i0)); FDSE #( .INIT(1'b1)) \gen_fwft.empty_fwft_i_reg (.C(rd_clk), .CE(1'b1), .D(empty_fwft_i0), .Q(empty), .S(rd_rst_busy)); axi_chip2chip_64B66B_xpm_counter_updn_8 \gen_fwft.rdpp1_inst (.DI({\gen_fwft.rdpp1_inst_n_3 ,\gen_fwft.rdpp1_inst_n_4 }), .Q(count_value_i), .SR(\gen_fwft.count_rst ), .\count_value_i_reg[0]_0 (curr_fwft_state), .ram_empty_i(ram_empty_i), .rd_clk(rd_clk), .rd_en(rd_en), .\src_gray_ff_reg[0] (rd_pntr_ext[0]), .src_in_bin(src_in_bin00_out[0])); FDSE #( .INIT(1'b1)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg (.C(wr_clk), .CE(1'b1), .D(\gen_cdc_pntr.rpw_gray_reg_n_9 ), .Q(full), .S(wrst_busy)); LUT4 #( .INIT(16'hAABA)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2 (.I0(ram_empty_i), .I1(rd_en), .I2(curr_fwft_state[1]), .I3(curr_fwft_state[0]), .O(p_1_in)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[0] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[0]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[1] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[1]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[2] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[2]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[3]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[4]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[5] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[5]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[6] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[6]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[7]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[8]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[8] ), .R(rd_rst_busy)); LUT4 #( .INIT(16'h88B8)) \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1 (.I0(prog_empty), .I1(empty), .I2(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0 ), .I3(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0 ), .O(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0 )); LUT4 #( .INIT(16'h01FF)) \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2 (.I0(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0] ), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1] ), .I2(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2] ), .I3(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3] ), .O(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0 )); LUT5 #( .INIT(32'hFFFFFFFE)) \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3 (.I0(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4] ), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7] ), .I2(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[8] ), .I3(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5] ), .I4(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6] ), .O(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0 )); FDSE #( .INIT(1'b1)) \gen_pf_ic_rc.gpe_ic.prog_empty_i_reg (.C(rd_clk), .CE(1'b1), .D(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0 ), .Q(prog_empty), .S(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[2] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[2]), .Q(diff_pntr_pf_q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[3] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[3]), .Q(diff_pntr_pf_q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[4]), .Q(diff_pntr_pf_q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[5]), .Q(diff_pntr_pf_q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[6] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[6]), .Q(diff_pntr_pf_q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[7] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[7]), .Q(diff_pntr_pf_q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[8]), .Q(diff_pntr_pf_q[8]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[9]), .Q(diff_pntr_pf_q[9]), .R(wrst_busy)); LUT6 #( .INIT(64'h8000000000000000)) \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2 (.I0(diff_pntr_pf_q[3]), .I1(diff_pntr_pf_q[2]), .I2(diff_pntr_pf_q[6]), .I3(diff_pntr_pf_q[7]), .I4(diff_pntr_pf_q[4]), .I5(diff_pntr_pf_q[5]), .O(\gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0 )); FDSE #( .INIT(1'b1)) \gen_pf_ic_rc.gpf_ic.prog_full_i_reg (.C(wr_clk), .CE(1'b1), .D(rst_d1_inst_n_1), .Q(prog_full), .S(wrst_busy)); FDSE #( .INIT(1'b1)) \gen_pf_ic_rc.ram_empty_i_reg (.C(rd_clk), .CE(1'b1), .D(ram_empty_i0), .Q(ram_empty_i), .S(rd_rst_busy)); (* ADDR_WIDTH_A = "9" *) (* ADDR_WIDTH_B = "9" *) (* AUTO_SLEEP_TIME = "0" *) (* BYTE_WRITE_WIDTH_A = "41" *) (* BYTE_WRITE_WIDTH_B = "41" *) (* CASCADE_HEIGHT = "0" *) (* CLOCKING_MODE = "1" *) (* ECC_MODE = "0" *) (* KEEP_HIERARCHY = "soft" *) (* MAX_NUM_CHAR = "0" *) (* \MEM.ADDRESS_SPACE *) (* \MEM.ADDRESS_SPACE_BEGIN = "0" *) (* \MEM.ADDRESS_SPACE_DATA_LSB = "0" *) (* \MEM.ADDRESS_SPACE_DATA_MSB = "40" *) (* \MEM.ADDRESS_SPACE_END = "511" *) (* \MEM.CORE_MEMORY_WIDTH = "41" *) (* MEMORY_INIT_FILE = "none" *) (* MEMORY_INIT_PARAM = "" *) (* MEMORY_OPTIMIZATION = "true" *) (* MEMORY_PRIMITIVE = "2" *) (* MEMORY_SIZE = "20992" *) (* MEMORY_TYPE = "1" *) (* MESSAGE_CONTROL = "0" *) (* NUM_CHAR_LOC = "0" *) (* P_ECC_MODE = "no_ecc" *) (* P_ENABLE_BYTE_WRITE_A = "0" *) (* P_ENABLE_BYTE_WRITE_B = "0" *) (* P_MAX_DEPTH_DATA = "512" *) (* P_MEMORY_OPT = "yes" *) (* P_MEMORY_PRIMITIVE = "block" *) (* P_MIN_WIDTH_DATA = "41" *) (* P_MIN_WIDTH_DATA_A = "41" *) (* P_MIN_WIDTH_DATA_B = "41" *) (* P_MIN_WIDTH_DATA_ECC = "41" *) (* P_MIN_WIDTH_DATA_LDW = "4" *) (* P_MIN_WIDTH_DATA_SHFT = "41" *) (* P_NUM_COLS_WRITE_A = "1" *) (* P_NUM_COLS_WRITE_B = "1" *) (* P_NUM_ROWS_READ_A = "1" *) (* P_NUM_ROWS_READ_B = "1" *) (* P_NUM_ROWS_WRITE_A = "1" *) (* P_NUM_ROWS_WRITE_B = "1" *) (* P_SDP_WRITE_MODE = "no" *) (* P_WIDTH_ADDR_LSB_READ_A = "0" *) (* P_WIDTH_ADDR_LSB_READ_B = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_B = "0" *) (* P_WIDTH_ADDR_READ_A = "9" *) (* P_WIDTH_ADDR_READ_B = "9" *) (* P_WIDTH_ADDR_WRITE_A = "9" *) (* P_WIDTH_ADDR_WRITE_B = "9" *) (* P_WIDTH_COL_WRITE_A = "41" *) (* P_WIDTH_COL_WRITE_B = "41" *) (* READ_DATA_WIDTH_A = "41" *) (* READ_DATA_WIDTH_B = "41" *) (* READ_LATENCY_A = "2" *) (* READ_LATENCY_B = "2" *) (* READ_RESET_VALUE_A = "0" *) (* READ_RESET_VALUE_B = "0" *) (* RST_MODE_A = "SYNC" *) (* RST_MODE_B = "SYNC" *) (* SIM_ASSERT_CHK = "0" *) (* USE_EMBEDDED_CONSTRAINT = "0" *) (* USE_MEM_INIT = "0" *) (* USE_MEM_INIT_MMI = "0" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH_A = "41" *) (* WRITE_DATA_WIDTH_B = "41" *) (* WRITE_MODE_A = "2" *) (* WRITE_MODE_B = "2" *) (* WRITE_PROTECT = "1" *) (* XPM_MODULE = "TRUE" *) (* rsta_loop_iter = "44" *) (* rstb_loop_iter = "44" *) axi_chip2chip_64B66B_xpm_memory_base__parameterized0 \gen_sdpram.xpm_memory_base_inst (.addra(wr_pntr_ext[8:0]), .addrb(rd_pntr_ext), .clka(wr_clk), .clkb(rd_clk), .dbiterra(\NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED ), .dbiterrb(\NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED ), .dina(din), .dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .douta(\NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED [40:0]), .doutb(dout), .ena(wr_pntr_plus1_pf_carry), .enb(ram_rd_en_i), .injectdbiterra(1'b0), .injectdbiterrb(1'b0), .injectsbiterra(1'b0), .injectsbiterrb(1'b0), .regcea(1'b0), .regceb(\gen_fwft.ram_regout_en ), .rsta(1'b0), .rstb(rd_rst_busy), .sbiterra(\NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED ), .sbiterrb(\NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED ), .sleep(sleep), .wea(1'b0), .web(1'b0)); (* SOFT_HLUTNM = "soft_lutpair202" *) LUT3 #( .INIT(8'h2C)) \gen_sdpram.xpm_memory_base_inst_i_3 (.I0(rd_en), .I1(curr_fwft_state[0]), .I2(curr_fwft_state[1]), .O(\gen_fwft.ram_regout_en )); FDRE #( .INIT(1'b0)) \gof.overflow_i_reg (.C(wr_clk), .CE(1'b1), .D(overflow_i0), .Q(overflow), .R(1'b0)); FDRE \grdc.rd_data_count_i_reg[1] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [1]), .Q(rd_data_count[0]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[2] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [2]), .Q(rd_data_count[1]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[3] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [3]), .Q(rd_data_count[2]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[4] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [4]), .Q(rd_data_count[3]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[5] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [5]), .Q(rd_data_count[4]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[6] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [6]), .Q(rd_data_count[5]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[7] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [7]), .Q(rd_data_count[6]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[8] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [8]), .Q(rd_data_count[7]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[9] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [9]), .Q(rd_data_count[8]), .R(\grdc.rd_data_count_i0 )); FDRE #( .INIT(1'b0)) \guf.underflow_i_reg (.C(rd_clk), .CE(1'b1), .D(underflow_i0), .Q(underflow), .R(1'b0)); FDRE \gwdc.wr_data_count_i_reg[1] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [1]), .Q(wr_data_count[0]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[2] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [2]), .Q(wr_data_count[1]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[3] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [3]), .Q(wr_data_count[2]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[4] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [4]), .Q(wr_data_count[3]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[5] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [5]), .Q(wr_data_count[4]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[6] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [6]), .Q(wr_data_count[5]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[7] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [7]), .Q(wr_data_count[6]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[8] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [8]), .Q(wr_data_count[7]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[9] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [9]), .Q(wr_data_count[8]), .R(wrst_busy)); axi_chip2chip_64B66B_xpm_counter_updn__parameterized3_9 rdp_inst (.D(\grdc.diff_wr_rd_pntr_rdc ), .DI({\gen_cdc_pntr.wpr_gray_reg_dc_n_0 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_1 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_2 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_3 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_4 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_5 ,\gen_fwft.rdpp1_inst_n_3 ,\gen_fwft.rdpp1_inst_n_4 }), .Q({rdp_inst_n_0,rd_pntr_ext}), .S(\gen_cdc_pntr.wpr_gray_reg_dc_n_16 ), .\count_value_i_reg[0]_0 (curr_fwft_state), .\count_value_i_reg[1]_0 (rdp_inst_n_21), .\count_value_i_reg[7]_0 ({rdp_inst_n_31,rdp_inst_n_32,rdp_inst_n_33,rdp_inst_n_34,rdp_inst_n_35,rdp_inst_n_36,rdp_inst_n_37,rdp_inst_n_38}), .\count_value_i_reg[9]_0 (rd_rst_busy), .\gen_pf_ic_rc.ram_empty_i_reg ({\gen_cdc_pntr.wpr_gray_reg_n_0 ,\gen_cdc_pntr.wpr_gray_reg_n_1 ,\gen_cdc_pntr.wpr_gray_reg_n_2 ,\gen_cdc_pntr.wpr_gray_reg_n_3 ,\gen_cdc_pntr.wpr_gray_reg_n_4 ,\gen_cdc_pntr.wpr_gray_reg_n_5 ,\gen_cdc_pntr.wpr_gray_reg_n_6 ,\gen_cdc_pntr.wpr_gray_reg_n_7 ,\gen_cdc_pntr.wpr_gray_reg_n_8 }), .\grdc.rd_data_count_i_reg[7] (count_value_i), .\grdc.rd_data_count_i_reg[9] (\gen_cdc_pntr.wpr_gray_reg_dc_n_15 ), .\grdc.rd_data_count_i_reg[9]_0 ({\gen_cdc_pntr.wpr_gray_reg_dc_n_6 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_7 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_8 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_9 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_10 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_11 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_12 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_13 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_14 }), .ram_empty_i(ram_empty_i), .ram_rd_en_i(ram_rd_en_i), .rd_clk(rd_clk), .rd_en(rd_en), .\reg_out_i_reg[7] (rdp_inst_n_11), .src_in_bin(src_in_bin00_out[9:1])); axi_chip2chip_64B66B_xpm_counter_updn__parameterized4_10 rdpp1_inst (.E(ram_rd_en_i), .Q(curr_fwft_state), .\count_value_i_reg[0]_0 (rd_rst_busy), .\gen_pf_ic_rc.ram_empty_i_reg (rdp_inst_n_21), .\gen_pf_ic_rc.ram_empty_i_reg_0 (rdp_inst_n_11), .\gen_pf_ic_rc.ram_empty_i_reg_1 ({\gen_cdc_pntr.wpr_gray_reg_n_0 ,\gen_cdc_pntr.wpr_gray_reg_n_1 ,\gen_cdc_pntr.wpr_gray_reg_n_2 ,\gen_cdc_pntr.wpr_gray_reg_n_3 ,\gen_cdc_pntr.wpr_gray_reg_n_4 ,\gen_cdc_pntr.wpr_gray_reg_n_5 ,\gen_cdc_pntr.wpr_gray_reg_n_6 ,\gen_cdc_pntr.wpr_gray_reg_n_7 ,\gen_cdc_pntr.wpr_gray_reg_n_8 }), .ram_empty_i(ram_empty_i), .ram_empty_i0(ram_empty_i0), .rd_clk(rd_clk), .rd_en(rd_en)); axi_chip2chip_64B66B_xpm_fifo_reg_bit_11 rst_d1_inst (.Q(diff_pntr_pf_q[9:8]), .clr_full(clr_full), .\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] (rst_d1_inst_n_1), .\gen_pf_ic_rc.gpf_ic.prog_full_i_reg (\gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0 ), .\gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 (full), .overflow_i0(overflow_i0), .prog_full(prog_full), .rst(rst), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), .wrst_busy(wrst_busy)); axi_chip2chip_64B66B_xpm_counter_updn__parameterized3_12 wrp_inst (.D(\gwdc.diff_wr_rd_pntr1_out ), .Q(wr_pntr_ext), .\count_value_i_reg[5]_0 (full), .\gwdc.wr_data_count_i_reg[9] ({\gen_cdc_pntr.rpw_gray_reg_dc_n_0 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_1 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_2 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_3 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_4 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_5 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_6 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_7 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_8 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_9 }), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wrst_busy(wrst_busy)); axi_chip2chip_64B66B_xpm_counter_updn__parameterized4_13 wrpp1_inst (.D(diff_pntr_pf_q0), .Q(wr_pntr_plus1_pf), .\count_value_i_reg[5]_0 (full), .\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] (rd_pntr_wr), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wrst_busy(wrst_busy)); axi_chip2chip_64B66B_xpm_counter_updn__parameterized5_14 wrpp2_inst (.Q({wrpp2_inst_n_0,wrpp2_inst_n_1,wrpp2_inst_n_2,wrpp2_inst_n_3,wrpp2_inst_n_4,wrpp2_inst_n_5,wrpp2_inst_n_6,wrpp2_inst_n_7,wrpp2_inst_n_8}), .\count_value_i_reg[5]_0 (full), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wrst_busy(wrst_busy)); axi_chip2chip_64B66B_xpm_fifo_rst__xdcDup__4 xpm_fifo_rst_inst (.Q(curr_fwft_state), .SR(\grdc.rd_data_count_i0 ), .\count_value_i_reg[8] (full), .\gen_pf_ic_rc.ram_empty_i_reg (\gen_fwft.count_rst ), .\gen_rst_ic.fifo_rd_rst_ic_reg_0 (rd_rst_busy), .\guf.underflow_i_reg (empty), .ram_empty_i(ram_empty_i), .rd_clk(rd_clk), .rd_en(rd_en), .rst(rst), .rst_d1(rst_d1), .underflow_i0(underflow_i0), .wr_clk(wr_clk), .wr_en(wr_en), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wr_rst_busy(wr_rst_busy), .wrst_busy(wrst_busy)); endmodule (* CASCADE_HEIGHT = "0" *) (* CDC_DEST_SYNC_FF = "3" *) (* COMMON_CLOCK = "0" *) (* DOUT_RESET_VALUE = "0" *) (* ECC_MODE = "0" *) (* ENABLE_ECC = "0" *) (* EN_ADV_FEATURE = "16'b0000011100000111" *) (* EN_AE = "1'b0" *) (* EN_AF = "1'b0" *) (* EN_DVLD = "1'b0" *) (* EN_OF = "1'b1" *) (* EN_PE = "1'b1" *) (* EN_PF = "1'b1" *) (* EN_RDC = "1'b1" *) (* EN_UF = "1'b1" *) (* EN_WACK = "1'b0" *) (* EN_WDC = "1'b1" *) (* FG_EQ_ASYM_DOUT = "1'b0" *) (* FIFO_MEMORY_TYPE = "2" *) (* FIFO_MEM_TYPE = "2" *) (* FIFO_READ_DEPTH = "512" *) (* FIFO_READ_LATENCY = "0" *) (* FIFO_SIZE = "20992" *) (* FIFO_WRITE_DEPTH = "512" *) (* FULL_RESET_VALUE = "1" *) (* FULL_RST_VAL = "1'b1" *) (* ORIG_REF_NAME = "xpm_fifo_base" *) (* PE_THRESH_ADJ = "8" *) (* PE_THRESH_MAX = "507" *) (* PE_THRESH_MIN = "5" *) (* PF_THRESH_ADJ = "382" *) (* PF_THRESH_MAX = "507" *) (* PF_THRESH_MIN = "8" *) (* PROG_EMPTY_THRESH = "10" *) (* PROG_FULL_THRESH = "384" *) (* RD_DATA_COUNT_WIDTH = "9" *) (* RD_DC_WIDTH_EXT = "10" *) (* RD_LATENCY = "2" *) (* RD_MODE = "1" *) (* RD_PNTR_WIDTH = "9" *) (* READ_DATA_WIDTH = "41" *) (* READ_MODE = "1" *) (* READ_MODE_LL = "1" *) (* RELATED_CLOCKS = "0" *) (* REMOVE_WR_RD_PROT_LOGIC = "0" *) (* SIM_ASSERT_CHK = "0" *) (* USE_ADV_FEATURES = "0707" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WIDTH_RATIO = "1" *) (* WRITE_DATA_WIDTH = "41" *) (* WR_DATA_COUNT_WIDTH = "9" *) (* WR_DC_WIDTH_EXT = "10" *) (* WR_DEPTH_LOG = "9" *) (* WR_PNTR_WIDTH = "9" *) (* WR_RD_RATIO = "0" *) (* WR_WIDTH_LOG = "6" *) (* XPM_MODULE = "TRUE" *) (* both_stages_valid = "3" *) (* invalid = "0" *) (* keep_hierarchy = "soft" *) (* stage1_valid = "2" *) (* stage2_valid = "1" *) module axi_chip2chip_64B66B_xpm_fifo_base__parameterized0__xdcDup__1 (sleep, rst, wr_clk, wr_en, din, full, full_n, prog_full, wr_data_count, overflow, wr_rst_busy, almost_full, wr_ack, rd_clk, rd_en, dout, empty, prog_empty, rd_data_count, underflow, rd_rst_busy, almost_empty, data_valid, injectsbiterr, injectdbiterr, sbiterr, dbiterr); input sleep; input rst; input wr_clk; input wr_en; input [40:0]din; output full; output full_n; output prog_full; output [8:0]wr_data_count; output overflow; output wr_rst_busy; output almost_full; output wr_ack; input rd_clk; input rd_en; output [40:0]dout; output empty; output prog_empty; output [8:0]rd_data_count; output underflow; output rd_rst_busy; output almost_empty; output data_valid; input injectsbiterr; input injectdbiterr; output sbiterr; output dbiterr; wire \ ; wire clr_full; wire [1:0]count_value_i; wire [1:0]curr_fwft_state; wire [8:0]diff_pntr_pe; wire [9:2]diff_pntr_pf_q; wire [9:2]diff_pntr_pf_q0; wire [40:0]din; wire [40:0]dout; wire empty; wire empty_fwft_i0; wire full; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_0 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_1 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_2 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_3 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_4 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_5 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_6 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_7 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_8 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_9 ; wire \gen_cdc_pntr.rpw_gray_reg_n_9 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_0 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_1 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_10 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_11 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_12 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_13 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_14 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_15 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_16 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_2 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_3 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_4 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_5 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_6 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_7 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_8 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_9 ; wire \gen_cdc_pntr.wpr_gray_reg_n_0 ; wire \gen_cdc_pntr.wpr_gray_reg_n_1 ; wire \gen_cdc_pntr.wpr_gray_reg_n_2 ; wire \gen_cdc_pntr.wpr_gray_reg_n_3 ; wire \gen_cdc_pntr.wpr_gray_reg_n_4 ; wire \gen_cdc_pntr.wpr_gray_reg_n_5 ; wire \gen_cdc_pntr.wpr_gray_reg_n_6 ; wire \gen_cdc_pntr.wpr_gray_reg_n_7 ; wire \gen_cdc_pntr.wpr_gray_reg_n_8 ; wire \gen_fwft.count_rst ; wire \gen_fwft.ram_regout_en ; wire \gen_fwft.rdpp1_inst_n_3 ; wire \gen_fwft.rdpp1_inst_n_4 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[8] ; wire \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0 ; wire \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0 ; wire \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0 ; wire \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0 ; wire [9:1]\grdc.diff_wr_rd_pntr_rdc ; wire \grdc.rd_data_count_i0 ; wire [9:1]\gwdc.diff_wr_rd_pntr1_out ; wire [1:0]next_fwft_state__0; wire overflow; wire overflow_i0; wire p_1_in; wire prog_empty; wire prog_full; wire ram_empty_i; wire ram_empty_i0; wire ram_rd_en_i; wire rd_clk; wire [8:0]rd_data_count; wire rd_en; wire [8:0]rd_pntr_ext; wire [8:0]rd_pntr_wr; wire [8:0]rd_pntr_wr_cdc; wire [9:0]rd_pntr_wr_cdc_dc; wire rd_rst_busy; wire rdp_inst_n_0; wire rdp_inst_n_11; wire rdp_inst_n_21; wire rdp_inst_n_31; wire rdp_inst_n_32; wire rdp_inst_n_33; wire rdp_inst_n_34; wire rdp_inst_n_35; wire rdp_inst_n_36; wire rdp_inst_n_37; wire rdp_inst_n_38; wire rst; wire rst_d1; wire rst_d1_inst_n_1; wire sleep; wire [9:0]src_in_bin00_out; wire underflow; wire underflow_i0; wire wr_clk; wire [8:0]wr_data_count; wire wr_en; wire [9:0]wr_pntr_ext; wire [9:1]wr_pntr_plus1_pf; wire wr_pntr_plus1_pf_carry; wire [8:0]wr_pntr_rd_cdc; wire [9:0]wr_pntr_rd_cdc_dc; wire wr_rst_busy; wire wrpp2_inst_n_0; wire wrpp2_inst_n_1; wire wrpp2_inst_n_2; wire wrpp2_inst_n_3; wire wrpp2_inst_n_4; wire wrpp2_inst_n_5; wire wrpp2_inst_n_6; wire wrpp2_inst_n_7; wire wrpp2_inst_n_8; wire wrst_busy; wire \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED ; wire \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED ; wire \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED ; wire \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED ; wire [40:0]\NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED ; assign almost_empty = \ ; assign almost_full = \ ; assign data_valid = \ ; assign dbiterr = \ ; assign full_n = \ ; assign sbiterr = \ ; assign wr_ack = \ ; (* SOFT_HLUTNM = "soft_lutpair263" *) LUT4 #( .INIT(16'h69A1)) \FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1 (.I0(ram_empty_i), .I1(curr_fwft_state[1]), .I2(curr_fwft_state[0]), .I3(rd_en), .O(next_fwft_state__0[0])); (* SOFT_HLUTNM = "soft_lutpair263" *) LUT3 #( .INIT(8'h7C)) \FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1 (.I0(rd_en), .I1(curr_fwft_state[0]), .I2(curr_fwft_state[1]), .O(next_fwft_state__0[1])); (* FSM_ENCODED_STATES = "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11" *) FDRE #( .INIT(1'b0)) \FSM_sequential_gen_fwft.curr_fwft_state_reg[0] (.C(rd_clk), .CE(1'b1), .D(next_fwft_state__0[0]), .Q(curr_fwft_state[0]), .R(rd_rst_busy)); (* FSM_ENCODED_STATES = "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11" *) FDRE #( .INIT(1'b0)) \FSM_sequential_gen_fwft.curr_fwft_state_reg[1] (.C(rd_clk), .CE(1'b1), .D(next_fwft_state__0[1]), .Q(curr_fwft_state[1]), .R(rd_rst_busy)); GND GND (.G(\ )); (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "10" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) axi_chip2chip_64B66B_xpm_cdc_gray__parameterized3__2 \gen_cdc_pntr.rd_pntr_cdc_dc_inst (.dest_clk(wr_clk), .dest_out_bin(rd_pntr_wr_cdc_dc), .src_clk(rd_clk), .src_in_bin(src_in_bin00_out)); (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) axi_chip2chip_64B66B_xpm_cdc_gray__parameterized1__10 \gen_cdc_pntr.rd_pntr_cdc_inst (.dest_clk(wr_clk), .dest_out_bin(rd_pntr_wr_cdc), .src_clk(rd_clk), .src_in_bin(rd_pntr_ext)); axi_chip2chip_64B66B_xpm_fifo_reg_vec__parameterized0 \gen_cdc_pntr.rpw_gray_reg (.D(rd_pntr_wr_cdc), .Q(rd_pntr_wr), .clr_full(clr_full), .\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 ({wrpp2_inst_n_0,wrpp2_inst_n_1,wrpp2_inst_n_2,wrpp2_inst_n_3,wrpp2_inst_n_4,wrpp2_inst_n_5,wrpp2_inst_n_6,wrpp2_inst_n_7,wrpp2_inst_n_8}), .\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg (wr_pntr_plus1_pf), .\reg_out_i_reg[0]_0 (\gen_cdc_pntr.rpw_gray_reg_n_9 ), .wr_clk(wr_clk), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wrst_busy(wrst_busy)); axi_chip2chip_64B66B_xpm_fifo_reg_vec__parameterized1 \gen_cdc_pntr.rpw_gray_reg_dc (.D(rd_pntr_wr_cdc_dc), .Q({\gen_cdc_pntr.rpw_gray_reg_dc_n_0 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_1 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_2 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_3 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_4 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_5 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_6 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_7 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_8 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_9 }), .wr_clk(wr_clk), .wrst_busy(wrst_busy)); axi_chip2chip_64B66B_xpm_fifo_reg_vec__parameterized0_0 \gen_cdc_pntr.wpr_gray_reg (.D(diff_pntr_pe), .DI(p_1_in), .Q({\gen_cdc_pntr.wpr_gray_reg_n_0 ,\gen_cdc_pntr.wpr_gray_reg_n_1 ,\gen_cdc_pntr.wpr_gray_reg_n_2 ,\gen_cdc_pntr.wpr_gray_reg_n_3 ,\gen_cdc_pntr.wpr_gray_reg_n_4 ,\gen_cdc_pntr.wpr_gray_reg_n_5 ,\gen_cdc_pntr.wpr_gray_reg_n_6 ,\gen_cdc_pntr.wpr_gray_reg_n_7 ,\gen_cdc_pntr.wpr_gray_reg_n_8 }), .S({rdp_inst_n_31,rdp_inst_n_32,rdp_inst_n_33,rdp_inst_n_34,rdp_inst_n_35,rdp_inst_n_36,rdp_inst_n_37,rdp_inst_n_38}), .\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8] (rd_pntr_ext[8]), .rd_clk(rd_clk), .\reg_out_i_reg[0]_0 (rd_rst_busy), .\reg_out_i_reg[8]_0 (wr_pntr_rd_cdc)); axi_chip2chip_64B66B_xpm_fifo_reg_vec__parameterized1_1 \gen_cdc_pntr.wpr_gray_reg_dc (.D(wr_pntr_rd_cdc_dc), .DI({\gen_cdc_pntr.wpr_gray_reg_dc_n_0 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_1 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_2 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_3 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_4 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_5 }), .Q({\gen_cdc_pntr.wpr_gray_reg_dc_n_6 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_7 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_8 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_9 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_10 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_11 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_12 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_13 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_14 }), .S(\gen_cdc_pntr.wpr_gray_reg_dc_n_16 ), .\grdc.rd_data_count_i_reg[7] (count_value_i[1]), .\grdc.rd_data_count_i_reg[9] ({rdp_inst_n_0,rd_pntr_ext[8:1]}), .rd_clk(rd_clk), .\reg_out_i_reg[7]_0 (\gen_cdc_pntr.wpr_gray_reg_dc_n_15 ), .\reg_out_i_reg[9]_0 (rd_rst_busy)); (* DEST_SYNC_FF = "5" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "10" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) axi_chip2chip_64B66B_xpm_cdc_gray__parameterized2__2 \gen_cdc_pntr.wr_pntr_cdc_dc_inst (.dest_clk(rd_clk), .dest_out_bin(wr_pntr_rd_cdc_dc), .src_clk(wr_clk), .src_in_bin(wr_pntr_ext)); (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) axi_chip2chip_64B66B_xpm_cdc_gray__parameterized1__9 \gen_cdc_pntr.wr_pntr_cdc_inst (.dest_clk(rd_clk), .dest_out_bin(wr_pntr_rd_cdc), .src_clk(wr_clk), .src_in_bin(wr_pntr_ext[8:0])); (* SOFT_HLUTNM = "soft_lutpair262" *) LUT4 #( .INIT(16'hE0CC)) \gen_fwft.empty_fwft_i_i_1 (.I0(rd_en), .I1(empty), .I2(curr_fwft_state[1]), .I3(curr_fwft_state[0]), .O(empty_fwft_i0)); FDSE #( .INIT(1'b1)) \gen_fwft.empty_fwft_i_reg (.C(rd_clk), .CE(1'b1), .D(empty_fwft_i0), .Q(empty), .S(rd_rst_busy)); axi_chip2chip_64B66B_xpm_counter_updn \gen_fwft.rdpp1_inst (.DI({\gen_fwft.rdpp1_inst_n_3 ,\gen_fwft.rdpp1_inst_n_4 }), .Q(count_value_i), .SR(\gen_fwft.count_rst ), .\count_value_i_reg[0]_0 (curr_fwft_state), .ram_empty_i(ram_empty_i), .rd_clk(rd_clk), .rd_en(rd_en), .\src_gray_ff_reg[0] (rd_pntr_ext[0]), .src_in_bin(src_in_bin00_out[0])); FDSE #( .INIT(1'b1)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg (.C(wr_clk), .CE(1'b1), .D(\gen_cdc_pntr.rpw_gray_reg_n_9 ), .Q(full), .S(wrst_busy)); LUT4 #( .INIT(16'hAABA)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[7]_i_2 (.I0(ram_empty_i), .I1(rd_en), .I2(curr_fwft_state[1]), .I3(curr_fwft_state[0]), .O(p_1_in)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[0] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[0]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[1] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[1]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[2] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[2]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[3]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[4]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[5] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[5]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[6] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[6]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[7]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[8]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[8] ), .R(rd_rst_busy)); LUT4 #( .INIT(16'h88B8)) \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1 (.I0(prog_empty), .I1(empty), .I2(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0 ), .I3(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0 ), .O(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0 )); LUT4 #( .INIT(16'h01FF)) \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2 (.I0(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0] ), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1] ), .I2(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2] ), .I3(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3] ), .O(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0 )); LUT5 #( .INIT(32'hFFFFFFFE)) \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3 (.I0(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4] ), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7] ), .I2(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[8] ), .I3(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5] ), .I4(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6] ), .O(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0 )); FDSE #( .INIT(1'b1)) \gen_pf_ic_rc.gpe_ic.prog_empty_i_reg (.C(rd_clk), .CE(1'b1), .D(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0 ), .Q(prog_empty), .S(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[2] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[2]), .Q(diff_pntr_pf_q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[3] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[3]), .Q(diff_pntr_pf_q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[4]), .Q(diff_pntr_pf_q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[5]), .Q(diff_pntr_pf_q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[6] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[6]), .Q(diff_pntr_pf_q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[7] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[7]), .Q(diff_pntr_pf_q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[8]), .Q(diff_pntr_pf_q[8]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[9]), .Q(diff_pntr_pf_q[9]), .R(wrst_busy)); LUT6 #( .INIT(64'h8000000000000000)) \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2 (.I0(diff_pntr_pf_q[3]), .I1(diff_pntr_pf_q[2]), .I2(diff_pntr_pf_q[6]), .I3(diff_pntr_pf_q[7]), .I4(diff_pntr_pf_q[4]), .I5(diff_pntr_pf_q[5]), .O(\gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0 )); FDSE #( .INIT(1'b1)) \gen_pf_ic_rc.gpf_ic.prog_full_i_reg (.C(wr_clk), .CE(1'b1), .D(rst_d1_inst_n_1), .Q(prog_full), .S(wrst_busy)); FDSE #( .INIT(1'b1)) \gen_pf_ic_rc.ram_empty_i_reg (.C(rd_clk), .CE(1'b1), .D(ram_empty_i0), .Q(ram_empty_i), .S(rd_rst_busy)); (* ADDR_WIDTH_A = "9" *) (* ADDR_WIDTH_B = "9" *) (* AUTO_SLEEP_TIME = "0" *) (* BYTE_WRITE_WIDTH_A = "41" *) (* BYTE_WRITE_WIDTH_B = "41" *) (* CASCADE_HEIGHT = "0" *) (* CLOCKING_MODE = "1" *) (* ECC_MODE = "0" *) (* KEEP_HIERARCHY = "soft" *) (* MAX_NUM_CHAR = "0" *) (* \MEM.ADDRESS_SPACE *) (* \MEM.ADDRESS_SPACE_BEGIN = "0" *) (* \MEM.ADDRESS_SPACE_DATA_LSB = "0" *) (* \MEM.ADDRESS_SPACE_DATA_MSB = "40" *) (* \MEM.ADDRESS_SPACE_END = "511" *) (* \MEM.CORE_MEMORY_WIDTH = "41" *) (* MEMORY_INIT_FILE = "none" *) (* MEMORY_INIT_PARAM = "" *) (* MEMORY_OPTIMIZATION = "true" *) (* MEMORY_PRIMITIVE = "2" *) (* MEMORY_SIZE = "20992" *) (* MEMORY_TYPE = "1" *) (* MESSAGE_CONTROL = "0" *) (* NUM_CHAR_LOC = "0" *) (* P_ECC_MODE = "no_ecc" *) (* P_ENABLE_BYTE_WRITE_A = "0" *) (* P_ENABLE_BYTE_WRITE_B = "0" *) (* P_MAX_DEPTH_DATA = "512" *) (* P_MEMORY_OPT = "yes" *) (* P_MEMORY_PRIMITIVE = "block" *) (* P_MIN_WIDTH_DATA = "41" *) (* P_MIN_WIDTH_DATA_A = "41" *) (* P_MIN_WIDTH_DATA_B = "41" *) (* P_MIN_WIDTH_DATA_ECC = "41" *) (* P_MIN_WIDTH_DATA_LDW = "4" *) (* P_MIN_WIDTH_DATA_SHFT = "41" *) (* P_NUM_COLS_WRITE_A = "1" *) (* P_NUM_COLS_WRITE_B = "1" *) (* P_NUM_ROWS_READ_A = "1" *) (* P_NUM_ROWS_READ_B = "1" *) (* P_NUM_ROWS_WRITE_A = "1" *) (* P_NUM_ROWS_WRITE_B = "1" *) (* P_SDP_WRITE_MODE = "no" *) (* P_WIDTH_ADDR_LSB_READ_A = "0" *) (* P_WIDTH_ADDR_LSB_READ_B = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_B = "0" *) (* P_WIDTH_ADDR_READ_A = "9" *) (* P_WIDTH_ADDR_READ_B = "9" *) (* P_WIDTH_ADDR_WRITE_A = "9" *) (* P_WIDTH_ADDR_WRITE_B = "9" *) (* P_WIDTH_COL_WRITE_A = "41" *) (* P_WIDTH_COL_WRITE_B = "41" *) (* READ_DATA_WIDTH_A = "41" *) (* READ_DATA_WIDTH_B = "41" *) (* READ_LATENCY_A = "2" *) (* READ_LATENCY_B = "2" *) (* READ_RESET_VALUE_A = "0" *) (* READ_RESET_VALUE_B = "0" *) (* RST_MODE_A = "SYNC" *) (* RST_MODE_B = "SYNC" *) (* SIM_ASSERT_CHK = "0" *) (* USE_EMBEDDED_CONSTRAINT = "0" *) (* USE_MEM_INIT = "0" *) (* USE_MEM_INIT_MMI = "0" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH_A = "41" *) (* WRITE_DATA_WIDTH_B = "41" *) (* WRITE_MODE_A = "2" *) (* WRITE_MODE_B = "2" *) (* WRITE_PROTECT = "1" *) (* XPM_MODULE = "TRUE" *) (* rsta_loop_iter = "44" *) (* rstb_loop_iter = "44" *) axi_chip2chip_64B66B_xpm_memory_base__parameterized0__2 \gen_sdpram.xpm_memory_base_inst (.addra(wr_pntr_ext[8:0]), .addrb(rd_pntr_ext), .clka(wr_clk), .clkb(rd_clk), .dbiterra(\NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED ), .dbiterrb(\NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED ), .dina(din), .dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .douta(\NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED [40:0]), .doutb(dout), .ena(wr_pntr_plus1_pf_carry), .enb(ram_rd_en_i), .injectdbiterra(1'b0), .injectdbiterrb(1'b0), .injectsbiterra(1'b0), .injectsbiterrb(1'b0), .regcea(1'b0), .regceb(\gen_fwft.ram_regout_en ), .rsta(1'b0), .rstb(rd_rst_busy), .sbiterra(\NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED ), .sbiterrb(\NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED ), .sleep(sleep), .wea(1'b0), .web(1'b0)); (* SOFT_HLUTNM = "soft_lutpair262" *) LUT3 #( .INIT(8'h2C)) \gen_sdpram.xpm_memory_base_inst_i_3 (.I0(rd_en), .I1(curr_fwft_state[0]), .I2(curr_fwft_state[1]), .O(\gen_fwft.ram_regout_en )); FDRE #( .INIT(1'b0)) \gof.overflow_i_reg (.C(wr_clk), .CE(1'b1), .D(overflow_i0), .Q(overflow), .R(1'b0)); FDRE \grdc.rd_data_count_i_reg[1] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [1]), .Q(rd_data_count[0]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[2] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [2]), .Q(rd_data_count[1]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[3] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [3]), .Q(rd_data_count[2]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[4] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [4]), .Q(rd_data_count[3]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[5] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [5]), .Q(rd_data_count[4]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[6] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [6]), .Q(rd_data_count[5]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[7] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [7]), .Q(rd_data_count[6]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[8] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [8]), .Q(rd_data_count[7]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[9] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [9]), .Q(rd_data_count[8]), .R(\grdc.rd_data_count_i0 )); FDRE #( .INIT(1'b0)) \guf.underflow_i_reg (.C(rd_clk), .CE(1'b1), .D(underflow_i0), .Q(underflow), .R(1'b0)); FDRE \gwdc.wr_data_count_i_reg[1] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [1]), .Q(wr_data_count[0]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[2] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [2]), .Q(wr_data_count[1]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[3] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [3]), .Q(wr_data_count[2]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[4] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [4]), .Q(wr_data_count[3]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[5] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [5]), .Q(wr_data_count[4]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[6] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [6]), .Q(wr_data_count[5]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[7] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [7]), .Q(wr_data_count[6]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[8] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [8]), .Q(wr_data_count[7]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[9] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [9]), .Q(wr_data_count[8]), .R(wrst_busy)); axi_chip2chip_64B66B_xpm_counter_updn__parameterized3 rdp_inst (.D(\grdc.diff_wr_rd_pntr_rdc ), .DI({\gen_cdc_pntr.wpr_gray_reg_dc_n_0 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_1 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_2 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_3 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_4 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_5 ,\gen_fwft.rdpp1_inst_n_3 ,\gen_fwft.rdpp1_inst_n_4 }), .Q({rdp_inst_n_0,rd_pntr_ext}), .S(\gen_cdc_pntr.wpr_gray_reg_dc_n_16 ), .\count_value_i_reg[0]_0 (curr_fwft_state), .\count_value_i_reg[1]_0 (rdp_inst_n_21), .\count_value_i_reg[7]_0 ({rdp_inst_n_31,rdp_inst_n_32,rdp_inst_n_33,rdp_inst_n_34,rdp_inst_n_35,rdp_inst_n_36,rdp_inst_n_37,rdp_inst_n_38}), .\count_value_i_reg[9]_0 (rd_rst_busy), .\gen_pf_ic_rc.ram_empty_i_reg ({\gen_cdc_pntr.wpr_gray_reg_n_0 ,\gen_cdc_pntr.wpr_gray_reg_n_1 ,\gen_cdc_pntr.wpr_gray_reg_n_2 ,\gen_cdc_pntr.wpr_gray_reg_n_3 ,\gen_cdc_pntr.wpr_gray_reg_n_4 ,\gen_cdc_pntr.wpr_gray_reg_n_5 ,\gen_cdc_pntr.wpr_gray_reg_n_6 ,\gen_cdc_pntr.wpr_gray_reg_n_7 ,\gen_cdc_pntr.wpr_gray_reg_n_8 }), .\grdc.rd_data_count_i_reg[7] (count_value_i), .\grdc.rd_data_count_i_reg[9] (\gen_cdc_pntr.wpr_gray_reg_dc_n_15 ), .\grdc.rd_data_count_i_reg[9]_0 ({\gen_cdc_pntr.wpr_gray_reg_dc_n_6 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_7 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_8 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_9 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_10 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_11 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_12 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_13 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_14 }), .ram_empty_i(ram_empty_i), .ram_rd_en_i(ram_rd_en_i), .rd_clk(rd_clk), .rd_en(rd_en), .\reg_out_i_reg[7] (rdp_inst_n_11), .src_in_bin(src_in_bin00_out[9:1])); axi_chip2chip_64B66B_xpm_counter_updn__parameterized4 rdpp1_inst (.E(ram_rd_en_i), .Q(curr_fwft_state), .\count_value_i_reg[0]_0 (rd_rst_busy), .\gen_pf_ic_rc.ram_empty_i_reg (rdp_inst_n_21), .\gen_pf_ic_rc.ram_empty_i_reg_0 (rdp_inst_n_11), .\gen_pf_ic_rc.ram_empty_i_reg_1 ({\gen_cdc_pntr.wpr_gray_reg_n_0 ,\gen_cdc_pntr.wpr_gray_reg_n_1 ,\gen_cdc_pntr.wpr_gray_reg_n_2 ,\gen_cdc_pntr.wpr_gray_reg_n_3 ,\gen_cdc_pntr.wpr_gray_reg_n_4 ,\gen_cdc_pntr.wpr_gray_reg_n_5 ,\gen_cdc_pntr.wpr_gray_reg_n_6 ,\gen_cdc_pntr.wpr_gray_reg_n_7 ,\gen_cdc_pntr.wpr_gray_reg_n_8 }), .ram_empty_i(ram_empty_i), .ram_empty_i0(ram_empty_i0), .rd_clk(rd_clk), .rd_en(rd_en)); axi_chip2chip_64B66B_xpm_fifo_reg_bit rst_d1_inst (.Q(diff_pntr_pf_q[9:8]), .clr_full(clr_full), .\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] (rst_d1_inst_n_1), .\gen_pf_ic_rc.gpf_ic.prog_full_i_reg (\gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0 ), .\gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 (full), .overflow_i0(overflow_i0), .prog_full(prog_full), .rst(rst), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), .wrst_busy(wrst_busy)); axi_chip2chip_64B66B_xpm_counter_updn__parameterized3_2 wrp_inst (.D(\gwdc.diff_wr_rd_pntr1_out ), .Q(wr_pntr_ext), .\count_value_i_reg[5]_0 (full), .\gwdc.wr_data_count_i_reg[9] ({\gen_cdc_pntr.rpw_gray_reg_dc_n_0 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_1 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_2 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_3 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_4 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_5 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_6 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_7 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_8 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_9 }), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wrst_busy(wrst_busy)); axi_chip2chip_64B66B_xpm_counter_updn__parameterized4_3 wrpp1_inst (.D(diff_pntr_pf_q0), .Q(wr_pntr_plus1_pf), .\count_value_i_reg[5]_0 (full), .\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[9] (rd_pntr_wr), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wrst_busy(wrst_busy)); axi_chip2chip_64B66B_xpm_counter_updn__parameterized5 wrpp2_inst (.Q({wrpp2_inst_n_0,wrpp2_inst_n_1,wrpp2_inst_n_2,wrpp2_inst_n_3,wrpp2_inst_n_4,wrpp2_inst_n_5,wrpp2_inst_n_6,wrpp2_inst_n_7,wrpp2_inst_n_8}), .\count_value_i_reg[5]_0 (full), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wrst_busy(wrst_busy)); axi_chip2chip_64B66B_xpm_fifo_rst__xdcDup__3 xpm_fifo_rst_inst (.Q(curr_fwft_state), .SR(\grdc.rd_data_count_i0 ), .\count_value_i_reg[8] (full), .\gen_pf_ic_rc.ram_empty_i_reg (\gen_fwft.count_rst ), .\gen_rst_ic.fifo_rd_rst_ic_reg_0 (rd_rst_busy), .\guf.underflow_i_reg (empty), .ram_empty_i(ram_empty_i), .rd_clk(rd_clk), .rd_en(rd_en), .rst(rst), .rst_d1(rst_d1), .underflow_i0(underflow_i0), .wr_clk(wr_clk), .wr_en(wr_en), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wr_rst_busy(wr_rst_busy), .wrst_busy(wrst_busy)); endmodule (* CASCADE_HEIGHT = "0" *) (* CDC_DEST_SYNC_FF = "3" *) (* COMMON_CLOCK = "0" *) (* DOUT_RESET_VALUE = "0" *) (* ECC_MODE = "0" *) (* ENABLE_ECC = "0" *) (* EN_ADV_FEATURE = "16'b0000011100000111" *) (* EN_AE = "1'b0" *) (* EN_AF = "1'b0" *) (* EN_DVLD = "1'b0" *) (* EN_OF = "1'b1" *) (* EN_PE = "1'b1" *) (* EN_PF = "1'b1" *) (* EN_RDC = "1'b1" *) (* EN_UF = "1'b1" *) (* EN_WACK = "1'b0" *) (* EN_WDC = "1'b1" *) (* FG_EQ_ASYM_DOUT = "1'b0" *) (* FIFO_MEMORY_TYPE = "1" *) (* FIFO_MEM_TYPE = "1" *) (* FIFO_READ_DEPTH = "256" *) (* FIFO_READ_LATENCY = "0" *) (* FIFO_SIZE = "2048" *) (* FIFO_WRITE_DEPTH = "256" *) (* FULL_RESET_VALUE = "1" *) (* FULL_RST_VAL = "1'b1" *) (* ORIG_REF_NAME = "xpm_fifo_base" *) (* PE_THRESH_ADJ = "8" *) (* PE_THRESH_MAX = "251" *) (* PE_THRESH_MIN = "5" *) (* PF_THRESH_ADJ = "126" *) (* PF_THRESH_MAX = "251" *) (* PF_THRESH_MIN = "8" *) (* PROG_EMPTY_THRESH = "10" *) (* PROG_FULL_THRESH = "128" *) (* RD_DATA_COUNT_WIDTH = "8" *) (* RD_DC_WIDTH_EXT = "9" *) (* RD_LATENCY = "2" *) (* RD_MODE = "1" *) (* RD_PNTR_WIDTH = "8" *) (* READ_DATA_WIDTH = "8" *) (* READ_MODE = "1" *) (* READ_MODE_LL = "1" *) (* RELATED_CLOCKS = "0" *) (* REMOVE_WR_RD_PROT_LOGIC = "0" *) (* SIM_ASSERT_CHK = "0" *) (* USE_ADV_FEATURES = "0707" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WIDTH_RATIO = "1" *) (* WRITE_DATA_WIDTH = "8" *) (* WR_DATA_COUNT_WIDTH = "8" *) (* WR_DC_WIDTH_EXT = "9" *) (* WR_DEPTH_LOG = "8" *) (* WR_PNTR_WIDTH = "8" *) (* WR_RD_RATIO = "0" *) (* WR_WIDTH_LOG = "3" *) (* XPM_MODULE = "TRUE" *) (* both_stages_valid = "3" *) (* invalid = "0" *) (* keep_hierarchy = "soft" *) (* stage1_valid = "2" *) (* stage2_valid = "1" *) module axi_chip2chip_64B66B_xpm_fifo_base__parameterized1 (sleep, rst, wr_clk, wr_en, din, full, full_n, prog_full, wr_data_count, overflow, wr_rst_busy, almost_full, wr_ack, rd_clk, rd_en, dout, empty, prog_empty, rd_data_count, underflow, rd_rst_busy, almost_empty, data_valid, injectsbiterr, injectdbiterr, sbiterr, dbiterr); input sleep; input rst; input wr_clk; input wr_en; input [7:0]din; output full; output full_n; output prog_full; output [7:0]wr_data_count; output overflow; output wr_rst_busy; output almost_full; output wr_ack; input rd_clk; input rd_en; output [7:0]dout; output empty; output prog_empty; output [7:0]rd_data_count; output underflow; output rd_rst_busy; output almost_empty; output data_valid; input injectsbiterr; input injectdbiterr; output sbiterr; output dbiterr; wire \ ; wire [1:0]count_value_i; wire [1:0]curr_fwft_state; wire [7:0]diff_pntr_pe; wire [8:2]diff_pntr_pf_q; wire [8:2]diff_pntr_pf_q0; wire [7:0]din; wire [7:0]dout; wire empty; wire empty_fwft_i0; wire full; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_0 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_1 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_2 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_3 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_4 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_5 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_6 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_7 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_8 ; wire \gen_cdc_pntr.rpw_gray_reg_n_8 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_10 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_11 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_12 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_13 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_14 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_15 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_16 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_8 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_9 ; wire \gen_cdc_pntr.wpr_gray_reg_n_1 ; wire \gen_cdc_pntr.wpr_gray_reg_n_2 ; wire \gen_cdc_pntr.wpr_gray_reg_n_3 ; wire \gen_cdc_pntr.wpr_gray_reg_n_4 ; wire \gen_cdc_pntr.wpr_gray_reg_n_5 ; wire \gen_cdc_pntr.wpr_gray_reg_n_6 ; wire \gen_cdc_pntr.wpr_gray_reg_n_7 ; wire \gen_cdc_pntr.wpr_gray_reg_n_8 ; wire \gen_fwft.count_rst ; wire \gen_fwft.ram_regout_en ; wire \gen_fwft.rdpp1_inst_n_3 ; wire \gen_fwft.rdpp1_inst_n_4 ; wire \gen_fwft.rdpp1_inst_n_5 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7] ; wire \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0 ; wire \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0 ; wire \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0 ; wire \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0 ; wire [8:1]\grdc.diff_wr_rd_pntr_rdc ; wire \grdc.rd_data_count_i0 ; wire [8:1]\gwdc.diff_wr_rd_pntr1_out ; wire [1:0]next_fwft_state__0; wire overflow; wire overflow_i0; wire prog_empty; wire prog_full; wire ram_empty_i; wire ram_empty_i0; wire rd_clk; wire [7:0]rd_data_count; wire rd_en; wire [7:0]rd_pntr_ext; wire [7:0]rd_pntr_wr; wire [7:0]rd_pntr_wr_cdc; wire [8:0]rd_pntr_wr_cdc_dc; wire rd_rst_busy; wire rdp_inst_n_10; wire rdp_inst_n_19; wire rdp_inst_n_20; wire rdp_inst_n_21; wire rdp_inst_n_22; wire rdp_inst_n_23; wire rdp_inst_n_24; wire rdp_inst_n_25; wire rdp_inst_n_26; wire rdp_inst_n_27; wire rdp_inst_n_28; wire rdp_inst_n_29; wire rdp_inst_n_30; wire rdp_inst_n_31; wire rdp_inst_n_8; wire rdp_inst_n_9; wire rdpp1_inst_n_0; wire rdpp1_inst_n_1; wire rdpp1_inst_n_2; wire rdpp1_inst_n_3; wire rdpp1_inst_n_4; wire rdpp1_inst_n_5; wire rdpp1_inst_n_6; wire rdpp1_inst_n_7; wire rst; wire rst_d1; wire rst_d1_inst_n_1; wire sleep; wire [1:1]src_in_bin00_out; wire underflow; wire underflow_i0; wire wr_clk; wire [7:0]wr_data_count; wire wr_en; wire [8:0]wr_pntr_ext; wire [8:1]wr_pntr_plus1_pf; wire wr_pntr_plus1_pf_carry; wire [7:0]wr_pntr_rd_cdc; wire [8:0]wr_pntr_rd_cdc_dc; wire wr_rst_busy; wire wrpp2_inst_n_0; wire wrpp2_inst_n_1; wire wrpp2_inst_n_2; wire wrpp2_inst_n_3; wire wrpp2_inst_n_4; wire wrpp2_inst_n_5; wire wrpp2_inst_n_6; wire wrpp2_inst_n_7; wire wrst_busy; wire \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED ; wire \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED ; wire \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED ; wire \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED ; wire [7:0]\NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED ; assign almost_empty = \ ; assign almost_full = \ ; assign data_valid = \ ; assign dbiterr = \ ; assign full_n = \ ; assign sbiterr = \ ; assign wr_ack = \ ; (* SOFT_HLUTNM = "soft_lutpair159" *) LUT4 #( .INIT(16'h6A85)) \FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1 (.I0(curr_fwft_state[0]), .I1(rd_en), .I2(curr_fwft_state[1]), .I3(ram_empty_i), .O(next_fwft_state__0[0])); (* SOFT_HLUTNM = "soft_lutpair159" *) LUT3 #( .INIT(8'h7C)) \FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1 (.I0(rd_en), .I1(curr_fwft_state[1]), .I2(curr_fwft_state[0]), .O(next_fwft_state__0[1])); (* FSM_ENCODED_STATES = "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11" *) FDRE #( .INIT(1'b0)) \FSM_sequential_gen_fwft.curr_fwft_state_reg[0] (.C(rd_clk), .CE(1'b1), .D(next_fwft_state__0[0]), .Q(curr_fwft_state[0]), .R(rd_rst_busy)); (* FSM_ENCODED_STATES = "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11" *) FDRE #( .INIT(1'b0)) \FSM_sequential_gen_fwft.curr_fwft_state_reg[1] (.C(rd_clk), .CE(1'b1), .D(next_fwft_state__0[1]), .Q(curr_fwft_state[1]), .R(rd_rst_busy)); GND GND (.G(\ )); (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) axi_chip2chip_64B66B_xpm_cdc_gray__parameterized1 \gen_cdc_pntr.rd_pntr_cdc_dc_inst (.dest_clk(wr_clk), .dest_out_bin(rd_pntr_wr_cdc_dc), .src_clk(rd_clk), .src_in_bin({rdp_inst_n_24,rdp_inst_n_25,rdp_inst_n_26,rdp_inst_n_27,rdp_inst_n_28,rdp_inst_n_29,rdp_inst_n_30,src_in_bin00_out,rdp_inst_n_31})); (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "8" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) axi_chip2chip_64B66B_xpm_cdc_gray \gen_cdc_pntr.rd_pntr_cdc_inst (.dest_clk(wr_clk), .dest_out_bin(rd_pntr_wr_cdc), .src_clk(rd_clk), .src_in_bin(rd_pntr_ext)); axi_chip2chip_64B66B_xpm_fifo_reg_vec \gen_cdc_pntr.rpw_gray_reg (.D(rd_pntr_wr_cdc), .Q(wr_pntr_plus1_pf), .d_out_reg(\gen_cdc_pntr.rpw_gray_reg_n_8 ), .\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg ({wrpp2_inst_n_0,wrpp2_inst_n_1,wrpp2_inst_n_2,wrpp2_inst_n_3,wrpp2_inst_n_4,wrpp2_inst_n_5,wrpp2_inst_n_6,wrpp2_inst_n_7}), .\reg_out_i_reg[7]_0 (rd_pntr_wr), .rst(rst), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wrst_busy(wrst_busy)); axi_chip2chip_64B66B_xpm_fifo_reg_vec__parameterized0_16 \gen_cdc_pntr.rpw_gray_reg_dc (.D(rd_pntr_wr_cdc_dc), .Q({\gen_cdc_pntr.rpw_gray_reg_dc_n_0 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_1 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_2 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_3 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_4 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_5 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_6 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_7 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_8 }), .wr_clk(wr_clk), .wrst_busy(wrst_busy)); axi_chip2chip_64B66B_xpm_fifo_reg_vec_17 \gen_cdc_pntr.wpr_gray_reg (.D(wr_pntr_rd_cdc), .Q(curr_fwft_state), .\gen_pf_ic_rc.ram_empty_i_reg (rd_pntr_ext), .\gen_pf_ic_rc.ram_empty_i_reg_0 ({rdpp1_inst_n_0,rdpp1_inst_n_1,rdpp1_inst_n_2,rdpp1_inst_n_3,rdpp1_inst_n_4,rdpp1_inst_n_5,rdpp1_inst_n_6,rdpp1_inst_n_7}), .ram_empty_i(ram_empty_i), .ram_empty_i0(ram_empty_i0), .rd_clk(rd_clk), .rd_en(rd_en), .\reg_out_i_reg[0]_0 (rd_rst_busy), .\reg_out_i_reg[7]_0 ({\gen_cdc_pntr.wpr_gray_reg_n_1 ,\gen_cdc_pntr.wpr_gray_reg_n_2 ,\gen_cdc_pntr.wpr_gray_reg_n_3 ,\gen_cdc_pntr.wpr_gray_reg_n_4 ,\gen_cdc_pntr.wpr_gray_reg_n_5 ,\gen_cdc_pntr.wpr_gray_reg_n_6 ,\gen_cdc_pntr.wpr_gray_reg_n_7 ,\gen_cdc_pntr.wpr_gray_reg_n_8 })); axi_chip2chip_64B66B_xpm_fifo_reg_vec__parameterized0_18 \gen_cdc_pntr.wpr_gray_reg_dc (.D(\grdc.diff_wr_rd_pntr_rdc ), .DI({rdp_inst_n_9,\gen_fwft.rdpp1_inst_n_5 }), .Q({\gen_cdc_pntr.wpr_gray_reg_dc_n_8 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_9 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_10 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_11 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_12 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_13 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_14 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_15 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_16 }), .S({rdp_inst_n_19,rdp_inst_n_20,rdp_inst_n_21,rdp_inst_n_22,rdp_inst_n_23,\gen_fwft.rdpp1_inst_n_3 ,\gen_fwft.rdpp1_inst_n_4 }), .\grdc.rd_data_count_i_reg[7] (count_value_i[1]), .\grdc.rd_data_count_i_reg[7]_0 (rd_pntr_ext[6:1]), .\grdc.rd_data_count_i_reg[8] (rdp_inst_n_10), .rd_clk(rd_clk), .\reg_out_i_reg[8]_0 (rd_rst_busy), .\reg_out_i_reg[8]_1 (wr_pntr_rd_cdc_dc)); (* DEST_SYNC_FF = "5" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) axi_chip2chip_64B66B_xpm_cdc_gray__parameterized0 \gen_cdc_pntr.wr_pntr_cdc_dc_inst (.dest_clk(rd_clk), .dest_out_bin(wr_pntr_rd_cdc_dc), .src_clk(wr_clk), .src_in_bin(wr_pntr_ext)); (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "8" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) axi_chip2chip_64B66B_xpm_cdc_gray__10 \gen_cdc_pntr.wr_pntr_cdc_inst (.dest_clk(rd_clk), .dest_out_bin(wr_pntr_rd_cdc), .src_clk(wr_clk), .src_in_bin(wr_pntr_ext[7:0])); (* SOFT_HLUTNM = "soft_lutpair158" *) LUT4 #( .INIT(16'hF380)) \gen_fwft.empty_fwft_i_i_1 (.I0(rd_en), .I1(curr_fwft_state[0]), .I2(curr_fwft_state[1]), .I3(empty), .O(empty_fwft_i0)); FDSE #( .INIT(1'b1)) \gen_fwft.empty_fwft_i_reg (.C(rd_clk), .CE(1'b1), .D(empty_fwft_i0), .Q(empty), .S(rd_rst_busy)); axi_chip2chip_64B66B_xpm_counter_updn_19 \gen_fwft.rdpp1_inst (.DI(\gen_fwft.rdpp1_inst_n_5 ), .Q(count_value_i), .S({\gen_fwft.rdpp1_inst_n_3 ,\gen_fwft.rdpp1_inst_n_4 }), .SR(\gen_fwft.count_rst ), .\count_value_i_reg[0]_0 (curr_fwft_state), .\grdc.rd_data_count_i_reg[7] (rd_pntr_ext[1:0]), .\grdc.rd_data_count_i_reg[7]_0 ({\gen_cdc_pntr.wpr_gray_reg_dc_n_15 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_16 }), .ram_empty_i(ram_empty_i), .rd_clk(rd_clk), .rd_en(rd_en), .src_in_bin(src_in_bin00_out)); FDSE #( .INIT(1'b1)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg (.C(wr_clk), .CE(1'b1), .D(\gen_cdc_pntr.rpw_gray_reg_n_8 ), .Q(full), .S(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[0] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[0]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[1] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[1]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[2] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[2]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[3]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[4]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[5] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[5]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[6] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[6]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[7]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7] ), .R(rd_rst_busy)); LUT4 #( .INIT(16'h88B8)) \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1 (.I0(prog_empty), .I1(empty), .I2(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0 ), .I3(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0 ), .O(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0 )); LUT4 #( .INIT(16'h01FF)) \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2 (.I0(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0] ), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1] ), .I2(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2] ), .I3(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3] ), .O(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0 )); LUT4 #( .INIT(16'hFFFE)) \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3 (.I0(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5] ), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4] ), .I2(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7] ), .I3(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6] ), .O(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0 )); FDSE #( .INIT(1'b1)) \gen_pf_ic_rc.gpe_ic.prog_empty_i_reg (.C(rd_clk), .CE(1'b1), .D(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0 ), .Q(prog_empty), .S(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[2] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[2]), .Q(diff_pntr_pf_q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[3] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[3]), .Q(diff_pntr_pf_q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[4]), .Q(diff_pntr_pf_q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[5]), .Q(diff_pntr_pf_q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[6] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[6]), .Q(diff_pntr_pf_q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[7] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[7]), .Q(diff_pntr_pf_q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[8]), .Q(diff_pntr_pf_q[8]), .R(wrst_busy)); LUT6 #( .INIT(64'h8000000000000000)) \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2 (.I0(diff_pntr_pf_q[3]), .I1(diff_pntr_pf_q[2]), .I2(diff_pntr_pf_q[6]), .I3(diff_pntr_pf_q[7]), .I4(diff_pntr_pf_q[4]), .I5(diff_pntr_pf_q[5]), .O(\gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0 )); FDSE #( .INIT(1'b1)) \gen_pf_ic_rc.gpf_ic.prog_full_i_reg (.C(wr_clk), .CE(1'b1), .D(rst_d1_inst_n_1), .Q(prog_full), .S(wrst_busy)); FDSE #( .INIT(1'b1)) \gen_pf_ic_rc.ram_empty_i_reg (.C(rd_clk), .CE(1'b1), .D(ram_empty_i0), .Q(ram_empty_i), .S(rd_rst_busy)); (* ADDR_WIDTH_A = "8" *) (* ADDR_WIDTH_B = "8" *) (* AUTO_SLEEP_TIME = "0" *) (* BYTE_WRITE_WIDTH_A = "8" *) (* BYTE_WRITE_WIDTH_B = "8" *) (* CASCADE_HEIGHT = "0" *) (* CLOCKING_MODE = "1" *) (* ECC_MODE = "0" *) (* KEEP_HIERARCHY = "soft" *) (* MAX_NUM_CHAR = "0" *) (* MEMORY_INIT_FILE = "none" *) (* MEMORY_INIT_PARAM = "" *) (* MEMORY_OPTIMIZATION = "true" *) (* MEMORY_PRIMITIVE = "1" *) (* MEMORY_SIZE = "2048" *) (* MEMORY_TYPE = "1" *) (* MESSAGE_CONTROL = "0" *) (* NUM_CHAR_LOC = "0" *) (* P_ECC_MODE = "no_ecc" *) (* P_ENABLE_BYTE_WRITE_A = "0" *) (* P_ENABLE_BYTE_WRITE_B = "0" *) (* P_MAX_DEPTH_DATA = "256" *) (* P_MEMORY_OPT = "yes" *) (* P_MEMORY_PRIMITIVE = "distributed" *) (* P_MIN_WIDTH_DATA = "8" *) (* P_MIN_WIDTH_DATA_A = "8" *) (* P_MIN_WIDTH_DATA_B = "8" *) (* P_MIN_WIDTH_DATA_ECC = "8" *) (* P_MIN_WIDTH_DATA_LDW = "4" *) (* P_MIN_WIDTH_DATA_SHFT = "8" *) (* P_NUM_COLS_WRITE_A = "1" *) (* P_NUM_COLS_WRITE_B = "1" *) (* P_NUM_ROWS_READ_A = "1" *) (* P_NUM_ROWS_READ_B = "1" *) (* P_NUM_ROWS_WRITE_A = "1" *) (* P_NUM_ROWS_WRITE_B = "1" *) (* P_SDP_WRITE_MODE = "yes" *) (* P_WIDTH_ADDR_LSB_READ_A = "0" *) (* P_WIDTH_ADDR_LSB_READ_B = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_B = "0" *) (* P_WIDTH_ADDR_READ_A = "8" *) (* P_WIDTH_ADDR_READ_B = "8" *) (* P_WIDTH_ADDR_WRITE_A = "8" *) (* P_WIDTH_ADDR_WRITE_B = "8" *) (* P_WIDTH_COL_WRITE_A = "8" *) (* P_WIDTH_COL_WRITE_B = "8" *) (* READ_DATA_WIDTH_A = "8" *) (* READ_DATA_WIDTH_B = "8" *) (* READ_LATENCY_A = "2" *) (* READ_LATENCY_B = "2" *) (* READ_RESET_VALUE_A = "0" *) (* READ_RESET_VALUE_B = "0" *) (* RST_MODE_A = "SYNC" *) (* RST_MODE_B = "SYNC" *) (* SIM_ASSERT_CHK = "0" *) (* USE_EMBEDDED_CONSTRAINT = "1" *) (* USE_MEM_INIT = "0" *) (* USE_MEM_INIT_MMI = "0" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH_A = "8" *) (* WRITE_DATA_WIDTH_B = "8" *) (* WRITE_MODE_A = "2" *) (* WRITE_MODE_B = "1" *) (* WRITE_PROTECT = "1" *) (* XPM_MODULE = "TRUE" *) (* rsta_loop_iter = "8" *) (* rstb_loop_iter = "8" *) axi_chip2chip_64B66B_xpm_memory_base__parameterized1 \gen_sdpram.xpm_memory_base_inst (.addra(wr_pntr_ext[7:0]), .addrb(rd_pntr_ext), .clka(wr_clk), .clkb(rd_clk), .dbiterra(\NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED ), .dbiterrb(\NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED ), .dina(din), .dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .douta(\NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED [7:0]), .doutb(dout), .ena(wr_pntr_plus1_pf_carry), .enb(rdp_inst_n_8), .injectdbiterra(1'b0), .injectdbiterrb(1'b0), .injectsbiterra(1'b0), .injectsbiterrb(1'b0), .regcea(1'b0), .regceb(\gen_fwft.ram_regout_en ), .rsta(1'b0), .rstb(rd_rst_busy), .sbiterra(\NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED ), .sbiterrb(\NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED ), .sleep(sleep), .wea(1'b0), .web(1'b0)); (* SOFT_HLUTNM = "soft_lutpair158" *) LUT3 #( .INIT(8'h62)) \gen_sdpram.xpm_memory_base_inst_i_3 (.I0(curr_fwft_state[0]), .I1(curr_fwft_state[1]), .I2(rd_en), .O(\gen_fwft.ram_regout_en )); FDRE #( .INIT(1'b0)) \gof.overflow_i_reg (.C(wr_clk), .CE(1'b1), .D(overflow_i0), .Q(overflow), .R(1'b0)); FDRE \grdc.rd_data_count_i_reg[1] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [1]), .Q(rd_data_count[0]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[2] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [2]), .Q(rd_data_count[1]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[3] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [3]), .Q(rd_data_count[2]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[4] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [4]), .Q(rd_data_count[3]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[5] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [5]), .Q(rd_data_count[4]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[6] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [6]), .Q(rd_data_count[5]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[7] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [7]), .Q(rd_data_count[6]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[8] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [8]), .Q(rd_data_count[7]), .R(\grdc.rd_data_count_i0 )); FDRE #( .INIT(1'b0)) \guf.underflow_i_reg (.C(rd_clk), .CE(1'b1), .D(underflow_i0), .Q(underflow), .R(1'b0)); FDRE \gwdc.wr_data_count_i_reg[1] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [1]), .Q(wr_data_count[0]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[2] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [2]), .Q(wr_data_count[1]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[3] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [3]), .Q(wr_data_count[2]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[4] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [4]), .Q(wr_data_count[3]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[5] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [5]), .Q(wr_data_count[4]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[6] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [6]), .Q(wr_data_count[5]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[7] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [7]), .Q(wr_data_count[6]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[8] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [8]), .Q(wr_data_count[7]), .R(wrst_busy)); axi_chip2chip_64B66B_xpm_counter_updn__parameterized0 rdp_inst (.D(diff_pntr_pe), .DI(rdp_inst_n_9), .Q(rd_pntr_ext), .S({rdp_inst_n_19,rdp_inst_n_20,rdp_inst_n_21,rdp_inst_n_22,rdp_inst_n_23}), .\count_value_i_reg[0]_0 (curr_fwft_state), .\count_value_i_reg[7]_0 (rdp_inst_n_10), .\count_value_i_reg[8]_0 (rd_rst_busy), .enb(rdp_inst_n_8), .\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] ({\gen_cdc_pntr.wpr_gray_reg_n_1 ,\gen_cdc_pntr.wpr_gray_reg_n_2 ,\gen_cdc_pntr.wpr_gray_reg_n_3 ,\gen_cdc_pntr.wpr_gray_reg_n_4 ,\gen_cdc_pntr.wpr_gray_reg_n_5 ,\gen_cdc_pntr.wpr_gray_reg_n_6 ,\gen_cdc_pntr.wpr_gray_reg_n_7 ,\gen_cdc_pntr.wpr_gray_reg_n_8 }), .\grdc.rd_data_count_i_reg[7] (count_value_i), .\grdc.rd_data_count_i_reg[8] ({\gen_cdc_pntr.wpr_gray_reg_dc_n_8 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_9 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_10 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_11 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_12 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_13 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_14 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_15 }), .ram_empty_i(ram_empty_i), .rd_clk(rd_clk), .rd_en(rd_en), .src_in_bin({rdp_inst_n_24,rdp_inst_n_25,rdp_inst_n_26,rdp_inst_n_27,rdp_inst_n_28,rdp_inst_n_29,rdp_inst_n_30,rdp_inst_n_31})); axi_chip2chip_64B66B_xpm_counter_updn__parameterized1 rdpp1_inst (.E(rdp_inst_n_8), .Q({rdpp1_inst_n_0,rdpp1_inst_n_1,rdpp1_inst_n_2,rdpp1_inst_n_3,rdpp1_inst_n_4,rdpp1_inst_n_5,rdpp1_inst_n_6,rdpp1_inst_n_7}), .\count_value_i_reg[0]_0 (rd_rst_busy), .\count_value_i_reg[1]_0 (curr_fwft_state), .ram_empty_i(ram_empty_i), .rd_clk(rd_clk), .rd_en(rd_en)); axi_chip2chip_64B66B_xpm_fifo_reg_bit_20 rst_d1_inst (.Q(diff_pntr_pf_q[8]), .\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] (rst_d1_inst_n_1), .\gen_pf_ic_rc.gpf_ic.prog_full_i_reg (\gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0 ), .\gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 (full), .overflow_i0(overflow_i0), .prog_full(prog_full), .rst(rst), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), .wrst_busy(wrst_busy)); axi_chip2chip_64B66B_xpm_counter_updn__parameterized0_21 wrp_inst (.D(\gwdc.diff_wr_rd_pntr1_out ), .Q(wr_pntr_ext), .\count_value_i_reg[6]_0 (full), .\gwdc.wr_data_count_i_reg[8] ({\gen_cdc_pntr.rpw_gray_reg_dc_n_0 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_1 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_2 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_3 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_4 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_5 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_6 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_7 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_8 }), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wrst_busy(wrst_busy)); axi_chip2chip_64B66B_xpm_counter_updn__parameterized1_22 wrpp1_inst (.D(diff_pntr_pf_q0), .Q(wr_pntr_plus1_pf), .\count_value_i_reg[6]_0 (full), .\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] (rd_pntr_wr), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wrst_busy(wrst_busy)); axi_chip2chip_64B66B_xpm_counter_updn__parameterized2 wrpp2_inst (.Q({wrpp2_inst_n_0,wrpp2_inst_n_1,wrpp2_inst_n_2,wrpp2_inst_n_3,wrpp2_inst_n_4,wrpp2_inst_n_5,wrpp2_inst_n_6,wrpp2_inst_n_7}), .\count_value_i_reg[6]_0 (full), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wrst_busy(wrst_busy)); axi_chip2chip_64B66B_xpm_fifo_rst xpm_fifo_rst_inst (.Q(curr_fwft_state), .SR(\grdc.rd_data_count_i0 ), .\count_value_i_reg[7] (full), .\gen_rst_ic.fifo_rd_rst_ic_reg_0 (rd_rst_busy), .\gen_rst_ic.fifo_rd_rst_ic_reg_1 (\gen_fwft.count_rst ), .\guf.underflow_i_reg (empty), .ram_empty_i(ram_empty_i), .rd_clk(rd_clk), .rd_en(rd_en), .rst(rst), .rst_d1(rst_d1), .underflow_i0(underflow_i0), .wr_clk(wr_clk), .wr_en(wr_en), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wr_rst_busy(wr_rst_busy), .wrst_busy(wrst_busy)); endmodule (* CASCADE_HEIGHT = "0" *) (* CDC_DEST_SYNC_FF = "3" *) (* COMMON_CLOCK = "0" *) (* DOUT_RESET_VALUE = "0" *) (* ECC_MODE = "0" *) (* ENABLE_ECC = "0" *) (* EN_ADV_FEATURE = "16'b0000011100000111" *) (* EN_AE = "1'b0" *) (* EN_AF = "1'b0" *) (* EN_DVLD = "1'b0" *) (* EN_OF = "1'b1" *) (* EN_PE = "1'b1" *) (* EN_PF = "1'b1" *) (* EN_RDC = "1'b1" *) (* EN_UF = "1'b1" *) (* EN_WACK = "1'b0" *) (* EN_WDC = "1'b1" *) (* FG_EQ_ASYM_DOUT = "1'b0" *) (* FIFO_MEMORY_TYPE = "2" *) (* FIFO_MEM_TYPE = "2" *) (* FIFO_READ_DEPTH = "256" *) (* FIFO_READ_LATENCY = "0" *) (* FIFO_SIZE = "12800" *) (* FIFO_WRITE_DEPTH = "256" *) (* FULL_RESET_VALUE = "1" *) (* FULL_RST_VAL = "1'b1" *) (* ORIG_REF_NAME = "xpm_fifo_base" *) (* PE_THRESH_ADJ = "8" *) (* PE_THRESH_MAX = "251" *) (* PE_THRESH_MIN = "5" *) (* PF_THRESH_ADJ = "126" *) (* PF_THRESH_MAX = "251" *) (* PF_THRESH_MIN = "8" *) (* PROG_EMPTY_THRESH = "10" *) (* PROG_FULL_THRESH = "128" *) (* RD_DATA_COUNT_WIDTH = "8" *) (* RD_DC_WIDTH_EXT = "9" *) (* RD_LATENCY = "2" *) (* RD_MODE = "1" *) (* RD_PNTR_WIDTH = "8" *) (* READ_DATA_WIDTH = "50" *) (* READ_MODE = "1" *) (* READ_MODE_LL = "1" *) (* RELATED_CLOCKS = "0" *) (* REMOVE_WR_RD_PROT_LOGIC = "0" *) (* SIM_ASSERT_CHK = "0" *) (* USE_ADV_FEATURES = "0707" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WIDTH_RATIO = "1" *) (* WRITE_DATA_WIDTH = "50" *) (* WR_DATA_COUNT_WIDTH = "8" *) (* WR_DC_WIDTH_EXT = "9" *) (* WR_DEPTH_LOG = "8" *) (* WR_PNTR_WIDTH = "8" *) (* WR_RD_RATIO = "0" *) (* WR_WIDTH_LOG = "6" *) (* XPM_MODULE = "TRUE" *) (* both_stages_valid = "3" *) (* invalid = "0" *) (* keep_hierarchy = "soft" *) (* stage1_valid = "2" *) (* stage2_valid = "1" *) module axi_chip2chip_64B66B_xpm_fifo_base__xdcDup__1 (sleep, rst, wr_clk, wr_en, din, full, full_n, prog_full, wr_data_count, overflow, wr_rst_busy, almost_full, wr_ack, rd_clk, rd_en, dout, empty, prog_empty, rd_data_count, underflow, rd_rst_busy, almost_empty, data_valid, injectsbiterr, injectdbiterr, sbiterr, dbiterr); input sleep; input rst; input wr_clk; input wr_en; input [49:0]din; output full; output full_n; output prog_full; output [7:0]wr_data_count; output overflow; output wr_rst_busy; output almost_full; output wr_ack; input rd_clk; input rd_en; output [49:0]dout; output empty; output prog_empty; output [7:0]rd_data_count; output underflow; output rd_rst_busy; output almost_empty; output data_valid; input injectsbiterr; input injectdbiterr; output sbiterr; output dbiterr; wire \ ; wire [1:0]count_value_i; wire [1:0]curr_fwft_state; wire [7:0]diff_pntr_pe; wire [8:2]diff_pntr_pf_q; wire [8:2]diff_pntr_pf_q0; wire [49:0]din; wire [49:0]dout; wire empty; wire empty_fwft_i0; wire full; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_0 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_1 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_2 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_3 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_4 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_5 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_6 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_7 ; wire \gen_cdc_pntr.rpw_gray_reg_dc_n_8 ; wire \gen_cdc_pntr.rpw_gray_reg_n_8 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_10 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_11 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_12 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_13 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_14 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_15 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_16 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_8 ; wire \gen_cdc_pntr.wpr_gray_reg_dc_n_9 ; wire \gen_cdc_pntr.wpr_gray_reg_n_1 ; wire \gen_cdc_pntr.wpr_gray_reg_n_2 ; wire \gen_cdc_pntr.wpr_gray_reg_n_3 ; wire \gen_cdc_pntr.wpr_gray_reg_n_4 ; wire \gen_cdc_pntr.wpr_gray_reg_n_5 ; wire \gen_cdc_pntr.wpr_gray_reg_n_6 ; wire \gen_cdc_pntr.wpr_gray_reg_n_7 ; wire \gen_cdc_pntr.wpr_gray_reg_n_8 ; wire \gen_fwft.count_rst ; wire \gen_fwft.ram_regout_en ; wire \gen_fwft.rdpp1_inst_n_3 ; wire \gen_fwft.rdpp1_inst_n_4 ; wire \gen_fwft.rdpp1_inst_n_5 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6] ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7] ; wire \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0 ; wire \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0 ; wire \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0 ; wire \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0 ; wire [8:1]\grdc.diff_wr_rd_pntr_rdc ; wire \grdc.rd_data_count_i0 ; wire [8:1]\gwdc.diff_wr_rd_pntr1_out ; wire [1:0]next_fwft_state__0; wire overflow; wire overflow_i0; wire prog_empty; wire prog_full; wire ram_empty_i; wire ram_empty_i0; wire rd_clk; wire [7:0]rd_data_count; wire rd_en; wire [7:0]rd_pntr_ext; wire [7:0]rd_pntr_wr; wire [7:0]rd_pntr_wr_cdc; wire [8:0]rd_pntr_wr_cdc_dc; wire rd_rst_busy; wire rdp_inst_n_10; wire rdp_inst_n_19; wire rdp_inst_n_20; wire rdp_inst_n_21; wire rdp_inst_n_22; wire rdp_inst_n_23; wire rdp_inst_n_24; wire rdp_inst_n_25; wire rdp_inst_n_26; wire rdp_inst_n_27; wire rdp_inst_n_28; wire rdp_inst_n_29; wire rdp_inst_n_30; wire rdp_inst_n_31; wire rdp_inst_n_8; wire rdp_inst_n_9; wire rdpp1_inst_n_0; wire rdpp1_inst_n_1; wire rdpp1_inst_n_2; wire rdpp1_inst_n_3; wire rdpp1_inst_n_4; wire rdpp1_inst_n_5; wire rdpp1_inst_n_6; wire rdpp1_inst_n_7; wire rst; wire rst_d1; wire rst_d1_inst_n_1; wire sleep; wire [1:1]src_in_bin00_out; wire underflow; wire underflow_i0; wire wr_clk; wire [7:0]wr_data_count; wire wr_en; wire [8:0]wr_pntr_ext; wire [8:1]wr_pntr_plus1_pf; wire wr_pntr_plus1_pf_carry; wire [7:0]wr_pntr_rd_cdc; wire [8:0]wr_pntr_rd_cdc_dc; wire wr_rst_busy; wire wrpp2_inst_n_0; wire wrpp2_inst_n_1; wire wrpp2_inst_n_2; wire wrpp2_inst_n_3; wire wrpp2_inst_n_4; wire wrpp2_inst_n_5; wire wrpp2_inst_n_6; wire wrpp2_inst_n_7; wire wrst_busy; wire \NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED ; wire \NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED ; wire \NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED ; wire \NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED ; wire [49:0]\NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED ; assign almost_empty = \ ; assign almost_full = \ ; assign data_valid = \ ; assign dbiterr = \ ; assign full_n = \ ; assign sbiterr = \ ; assign wr_ack = \ ; (* SOFT_HLUTNM = "soft_lutpair126" *) LUT4 #( .INIT(16'h6A85)) \FSM_sequential_gen_fwft.curr_fwft_state[0]_i_1 (.I0(curr_fwft_state[0]), .I1(rd_en), .I2(curr_fwft_state[1]), .I3(ram_empty_i), .O(next_fwft_state__0[0])); (* SOFT_HLUTNM = "soft_lutpair126" *) LUT3 #( .INIT(8'h7C)) \FSM_sequential_gen_fwft.curr_fwft_state[1]_i_1 (.I0(rd_en), .I1(curr_fwft_state[1]), .I2(curr_fwft_state[0]), .O(next_fwft_state__0[1])); (* FSM_ENCODED_STATES = "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11" *) FDRE #( .INIT(1'b0)) \FSM_sequential_gen_fwft.curr_fwft_state_reg[0] (.C(rd_clk), .CE(1'b1), .D(next_fwft_state__0[0]), .Q(curr_fwft_state[0]), .R(rd_rst_busy)); (* FSM_ENCODED_STATES = "invalid:00,stage1_valid:01,both_stages_valid:10,stage2_valid:11" *) FDRE #( .INIT(1'b0)) \FSM_sequential_gen_fwft.curr_fwft_state_reg[1] (.C(rd_clk), .CE(1'b1), .D(next_fwft_state__0[1]), .Q(curr_fwft_state[1]), .R(rd_rst_busy)); GND GND (.G(\ )); (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) axi_chip2chip_64B66B_xpm_cdc_gray__parameterized1__7 \gen_cdc_pntr.rd_pntr_cdc_dc_inst (.dest_clk(wr_clk), .dest_out_bin(rd_pntr_wr_cdc_dc), .src_clk(rd_clk), .src_in_bin({rdp_inst_n_24,rdp_inst_n_25,rdp_inst_n_26,rdp_inst_n_27,rdp_inst_n_28,rdp_inst_n_29,rdp_inst_n_30,src_in_bin00_out,rdp_inst_n_31})); (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "8" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) axi_chip2chip_64B66B_xpm_cdc_gray__7 \gen_cdc_pntr.rd_pntr_cdc_inst (.dest_clk(wr_clk), .dest_out_bin(rd_pntr_wr_cdc), .src_clk(rd_clk), .src_in_bin(rd_pntr_ext)); axi_chip2chip_64B66B_xpm_fifo_reg_vec_23 \gen_cdc_pntr.rpw_gray_reg (.D(rd_pntr_wr_cdc), .Q(wr_pntr_plus1_pf), .d_out_reg(\gen_cdc_pntr.rpw_gray_reg_n_8 ), .\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg ({wrpp2_inst_n_0,wrpp2_inst_n_1,wrpp2_inst_n_2,wrpp2_inst_n_3,wrpp2_inst_n_4,wrpp2_inst_n_5,wrpp2_inst_n_6,wrpp2_inst_n_7}), .\reg_out_i_reg[7]_0 (rd_pntr_wr), .rst(rst), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wrst_busy(wrst_busy)); axi_chip2chip_64B66B_xpm_fifo_reg_vec__parameterized0_24 \gen_cdc_pntr.rpw_gray_reg_dc (.D(rd_pntr_wr_cdc_dc), .Q({\gen_cdc_pntr.rpw_gray_reg_dc_n_0 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_1 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_2 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_3 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_4 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_5 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_6 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_7 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_8 }), .wr_clk(wr_clk), .wrst_busy(wrst_busy)); axi_chip2chip_64B66B_xpm_fifo_reg_vec_25 \gen_cdc_pntr.wpr_gray_reg (.D(wr_pntr_rd_cdc), .Q(curr_fwft_state), .\gen_pf_ic_rc.ram_empty_i_reg (rd_pntr_ext), .\gen_pf_ic_rc.ram_empty_i_reg_0 ({rdpp1_inst_n_0,rdpp1_inst_n_1,rdpp1_inst_n_2,rdpp1_inst_n_3,rdpp1_inst_n_4,rdpp1_inst_n_5,rdpp1_inst_n_6,rdpp1_inst_n_7}), .ram_empty_i(ram_empty_i), .ram_empty_i0(ram_empty_i0), .rd_clk(rd_clk), .rd_en(rd_en), .\reg_out_i_reg[0]_0 (rd_rst_busy), .\reg_out_i_reg[7]_0 ({\gen_cdc_pntr.wpr_gray_reg_n_1 ,\gen_cdc_pntr.wpr_gray_reg_n_2 ,\gen_cdc_pntr.wpr_gray_reg_n_3 ,\gen_cdc_pntr.wpr_gray_reg_n_4 ,\gen_cdc_pntr.wpr_gray_reg_n_5 ,\gen_cdc_pntr.wpr_gray_reg_n_6 ,\gen_cdc_pntr.wpr_gray_reg_n_7 ,\gen_cdc_pntr.wpr_gray_reg_n_8 })); axi_chip2chip_64B66B_xpm_fifo_reg_vec__parameterized0_26 \gen_cdc_pntr.wpr_gray_reg_dc (.D(\grdc.diff_wr_rd_pntr_rdc ), .DI({rdp_inst_n_9,\gen_fwft.rdpp1_inst_n_5 }), .Q({\gen_cdc_pntr.wpr_gray_reg_dc_n_8 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_9 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_10 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_11 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_12 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_13 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_14 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_15 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_16 }), .S({rdp_inst_n_19,rdp_inst_n_20,rdp_inst_n_21,rdp_inst_n_22,rdp_inst_n_23,\gen_fwft.rdpp1_inst_n_3 ,\gen_fwft.rdpp1_inst_n_4 }), .\grdc.rd_data_count_i_reg[7] (count_value_i[1]), .\grdc.rd_data_count_i_reg[7]_0 (rd_pntr_ext[6:1]), .\grdc.rd_data_count_i_reg[8] (rdp_inst_n_10), .rd_clk(rd_clk), .\reg_out_i_reg[8]_0 (rd_rst_busy), .\reg_out_i_reg[8]_1 (wr_pntr_rd_cdc_dc)); (* DEST_SYNC_FF = "5" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "9" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) axi_chip2chip_64B66B_xpm_cdc_gray__parameterized0__3 \gen_cdc_pntr.wr_pntr_cdc_dc_inst (.dest_clk(rd_clk), .dest_out_bin(wr_pntr_rd_cdc_dc), .src_clk(wr_clk), .src_in_bin(wr_pntr_ext)); (* DEST_SYNC_FF = "3" *) (* INIT_SYNC_FF = "1" *) (* REG_OUTPUT = "0" *) (* SIM_ASSERT_CHK = "0" *) (* SIM_LOSSLESS_GRAY_CHK = "0" *) (* VERSION = "0" *) (* WIDTH = "8" *) (* XPM_CDC = "GRAY" *) (* XPM_MODULE = "TRUE" *) axi_chip2chip_64B66B_xpm_cdc_gray__6 \gen_cdc_pntr.wr_pntr_cdc_inst (.dest_clk(rd_clk), .dest_out_bin(wr_pntr_rd_cdc), .src_clk(wr_clk), .src_in_bin(wr_pntr_ext[7:0])); (* SOFT_HLUTNM = "soft_lutpair125" *) LUT4 #( .INIT(16'hF380)) \gen_fwft.empty_fwft_i_i_1 (.I0(rd_en), .I1(curr_fwft_state[0]), .I2(curr_fwft_state[1]), .I3(empty), .O(empty_fwft_i0)); FDSE #( .INIT(1'b1)) \gen_fwft.empty_fwft_i_reg (.C(rd_clk), .CE(1'b1), .D(empty_fwft_i0), .Q(empty), .S(rd_rst_busy)); axi_chip2chip_64B66B_xpm_counter_updn_27 \gen_fwft.rdpp1_inst (.DI(\gen_fwft.rdpp1_inst_n_5 ), .Q(count_value_i), .S({\gen_fwft.rdpp1_inst_n_3 ,\gen_fwft.rdpp1_inst_n_4 }), .SR(\gen_fwft.count_rst ), .\count_value_i_reg[0]_0 (curr_fwft_state), .\grdc.rd_data_count_i_reg[7] (rd_pntr_ext[1:0]), .\grdc.rd_data_count_i_reg[7]_0 ({\gen_cdc_pntr.wpr_gray_reg_dc_n_15 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_16 }), .ram_empty_i(ram_empty_i), .rd_clk(rd_clk), .rd_en(rd_en), .src_in_bin(src_in_bin00_out)); FDSE #( .INIT(1'b1)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg (.C(wr_clk), .CE(1'b1), .D(\gen_cdc_pntr.rpw_gray_reg_n_8 ), .Q(full), .S(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[0] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[0]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[1] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[1]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[2] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[2]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[3] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[3]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[4] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[4]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[5] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[5]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[6] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[6]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6] ), .R(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] (.C(rd_clk), .CE(1'b1), .D(diff_pntr_pe[7]), .Q(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7] ), .R(rd_rst_busy)); LUT4 #( .INIT(16'h88B8)) \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1 (.I0(prog_empty), .I1(empty), .I2(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0 ), .I3(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0 ), .O(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0 )); LUT4 #( .INIT(16'h01FF)) \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2 (.I0(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[0] ), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[1] ), .I2(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[2] ), .I3(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[3] ), .O(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_2_n_0 )); LUT4 #( .INIT(16'hFFFE)) \gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3 (.I0(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[5] ), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[4] ), .I2(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[7] ), .I3(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg_n_0_[6] ), .O(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_3_n_0 )); FDSE #( .INIT(1'b1)) \gen_pf_ic_rc.gpe_ic.prog_empty_i_reg (.C(rd_clk), .CE(1'b1), .D(\gen_pf_ic_rc.gpe_ic.prog_empty_i_i_1_n_0 ), .Q(prog_empty), .S(rd_rst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[2] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[2]), .Q(diff_pntr_pf_q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[3] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[3]), .Q(diff_pntr_pf_q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[4] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[4]), .Q(diff_pntr_pf_q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[5] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[5]), .Q(diff_pntr_pf_q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[6] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[6]), .Q(diff_pntr_pf_q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[7] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[7]), .Q(diff_pntr_pf_q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] (.C(wr_clk), .CE(1'b1), .D(diff_pntr_pf_q0[8]), .Q(diff_pntr_pf_q[8]), .R(wrst_busy)); LUT6 #( .INIT(64'h8000000000000000)) \gen_pf_ic_rc.gpf_ic.prog_full_i_i_2 (.I0(diff_pntr_pf_q[3]), .I1(diff_pntr_pf_q[2]), .I2(diff_pntr_pf_q[6]), .I3(diff_pntr_pf_q[7]), .I4(diff_pntr_pf_q[4]), .I5(diff_pntr_pf_q[5]), .O(\gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0 )); FDSE #( .INIT(1'b1)) \gen_pf_ic_rc.gpf_ic.prog_full_i_reg (.C(wr_clk), .CE(1'b1), .D(rst_d1_inst_n_1), .Q(prog_full), .S(wrst_busy)); FDSE #( .INIT(1'b1)) \gen_pf_ic_rc.ram_empty_i_reg (.C(rd_clk), .CE(1'b1), .D(ram_empty_i0), .Q(ram_empty_i), .S(rd_rst_busy)); (* ADDR_WIDTH_A = "8" *) (* ADDR_WIDTH_B = "8" *) (* AUTO_SLEEP_TIME = "0" *) (* BYTE_WRITE_WIDTH_A = "50" *) (* BYTE_WRITE_WIDTH_B = "50" *) (* CASCADE_HEIGHT = "0" *) (* CLOCKING_MODE = "1" *) (* ECC_MODE = "0" *) (* KEEP_HIERARCHY = "soft" *) (* MAX_NUM_CHAR = "0" *) (* \MEM.ADDRESS_SPACE *) (* \MEM.ADDRESS_SPACE_BEGIN = "0" *) (* \MEM.ADDRESS_SPACE_DATA_LSB = "0" *) (* \MEM.ADDRESS_SPACE_DATA_MSB = "49" *) (* \MEM.ADDRESS_SPACE_END = "511" *) (* \MEM.CORE_MEMORY_WIDTH = "50" *) (* MEMORY_INIT_FILE = "none" *) (* MEMORY_INIT_PARAM = "" *) (* MEMORY_OPTIMIZATION = "true" *) (* MEMORY_PRIMITIVE = "2" *) (* MEMORY_SIZE = "12800" *) (* MEMORY_TYPE = "1" *) (* MESSAGE_CONTROL = "0" *) (* NUM_CHAR_LOC = "0" *) (* P_ECC_MODE = "no_ecc" *) (* P_ENABLE_BYTE_WRITE_A = "0" *) (* P_ENABLE_BYTE_WRITE_B = "0" *) (* P_MAX_DEPTH_DATA = "256" *) (* P_MEMORY_OPT = "yes" *) (* P_MEMORY_PRIMITIVE = "block" *) (* P_MIN_WIDTH_DATA = "50" *) (* P_MIN_WIDTH_DATA_A = "50" *) (* P_MIN_WIDTH_DATA_B = "50" *) (* P_MIN_WIDTH_DATA_ECC = "50" *) (* P_MIN_WIDTH_DATA_LDW = "4" *) (* P_MIN_WIDTH_DATA_SHFT = "50" *) (* P_NUM_COLS_WRITE_A = "1" *) (* P_NUM_COLS_WRITE_B = "1" *) (* P_NUM_ROWS_READ_A = "1" *) (* P_NUM_ROWS_READ_B = "1" *) (* P_NUM_ROWS_WRITE_A = "1" *) (* P_NUM_ROWS_WRITE_B = "1" *) (* P_SDP_WRITE_MODE = "no" *) (* P_WIDTH_ADDR_LSB_READ_A = "0" *) (* P_WIDTH_ADDR_LSB_READ_B = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_B = "0" *) (* P_WIDTH_ADDR_READ_A = "8" *) (* P_WIDTH_ADDR_READ_B = "8" *) (* P_WIDTH_ADDR_WRITE_A = "8" *) (* P_WIDTH_ADDR_WRITE_B = "8" *) (* P_WIDTH_COL_WRITE_A = "50" *) (* P_WIDTH_COL_WRITE_B = "50" *) (* READ_DATA_WIDTH_A = "50" *) (* READ_DATA_WIDTH_B = "50" *) (* READ_LATENCY_A = "2" *) (* READ_LATENCY_B = "2" *) (* READ_RESET_VALUE_A = "0" *) (* READ_RESET_VALUE_B = "0" *) (* RST_MODE_A = "SYNC" *) (* RST_MODE_B = "SYNC" *) (* SIM_ASSERT_CHK = "0" *) (* USE_EMBEDDED_CONSTRAINT = "0" *) (* USE_MEM_INIT = "0" *) (* USE_MEM_INIT_MMI = "0" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH_A = "50" *) (* WRITE_DATA_WIDTH_B = "50" *) (* WRITE_MODE_A = "2" *) (* WRITE_MODE_B = "2" *) (* WRITE_PROTECT = "1" *) (* XPM_MODULE = "TRUE" *) (* rsta_loop_iter = "52" *) (* rstb_loop_iter = "52" *) axi_chip2chip_64B66B_xpm_memory_base__2 \gen_sdpram.xpm_memory_base_inst (.addra(wr_pntr_ext[7:0]), .addrb(rd_pntr_ext), .clka(wr_clk), .clkb(rd_clk), .dbiterra(\NLW_gen_sdpram.xpm_memory_base_inst_dbiterra_UNCONNECTED ), .dbiterrb(\NLW_gen_sdpram.xpm_memory_base_inst_dbiterrb_UNCONNECTED ), .dina(din), .dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .douta(\NLW_gen_sdpram.xpm_memory_base_inst_douta_UNCONNECTED [49:0]), .doutb(dout), .ena(wr_pntr_plus1_pf_carry), .enb(rdp_inst_n_8), .injectdbiterra(1'b0), .injectdbiterrb(1'b0), .injectsbiterra(1'b0), .injectsbiterrb(1'b0), .regcea(1'b0), .regceb(\gen_fwft.ram_regout_en ), .rsta(1'b0), .rstb(rd_rst_busy), .sbiterra(\NLW_gen_sdpram.xpm_memory_base_inst_sbiterra_UNCONNECTED ), .sbiterrb(\NLW_gen_sdpram.xpm_memory_base_inst_sbiterrb_UNCONNECTED ), .sleep(sleep), .wea(1'b0), .web(1'b0)); (* SOFT_HLUTNM = "soft_lutpair125" *) LUT3 #( .INIT(8'h62)) \gen_sdpram.xpm_memory_base_inst_i_3 (.I0(curr_fwft_state[0]), .I1(curr_fwft_state[1]), .I2(rd_en), .O(\gen_fwft.ram_regout_en )); FDRE #( .INIT(1'b0)) \gof.overflow_i_reg (.C(wr_clk), .CE(1'b1), .D(overflow_i0), .Q(overflow), .R(1'b0)); FDRE \grdc.rd_data_count_i_reg[1] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [1]), .Q(rd_data_count[0]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[2] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [2]), .Q(rd_data_count[1]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[3] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [3]), .Q(rd_data_count[2]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[4] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [4]), .Q(rd_data_count[3]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[5] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [5]), .Q(rd_data_count[4]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[6] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [6]), .Q(rd_data_count[5]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[7] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [7]), .Q(rd_data_count[6]), .R(\grdc.rd_data_count_i0 )); FDRE \grdc.rd_data_count_i_reg[8] (.C(rd_clk), .CE(1'b1), .D(\grdc.diff_wr_rd_pntr_rdc [8]), .Q(rd_data_count[7]), .R(\grdc.rd_data_count_i0 )); FDRE #( .INIT(1'b0)) \guf.underflow_i_reg (.C(rd_clk), .CE(1'b1), .D(underflow_i0), .Q(underflow), .R(1'b0)); FDRE \gwdc.wr_data_count_i_reg[1] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [1]), .Q(wr_data_count[0]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[2] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [2]), .Q(wr_data_count[1]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[3] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [3]), .Q(wr_data_count[2]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[4] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [4]), .Q(wr_data_count[3]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[5] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [5]), .Q(wr_data_count[4]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[6] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [6]), .Q(wr_data_count[5]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[7] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [7]), .Q(wr_data_count[6]), .R(wrst_busy)); FDRE \gwdc.wr_data_count_i_reg[8] (.C(wr_clk), .CE(1'b1), .D(\gwdc.diff_wr_rd_pntr1_out [8]), .Q(wr_data_count[7]), .R(wrst_busy)); axi_chip2chip_64B66B_xpm_counter_updn__parameterized0_28 rdp_inst (.D(diff_pntr_pe), .DI(rdp_inst_n_9), .Q(rd_pntr_ext), .S({rdp_inst_n_19,rdp_inst_n_20,rdp_inst_n_21,rdp_inst_n_22,rdp_inst_n_23}), .\count_value_i_reg[0]_0 (curr_fwft_state), .\count_value_i_reg[7]_0 (rdp_inst_n_10), .\count_value_i_reg[8]_0 (rd_rst_busy), .enb(rdp_inst_n_8), .\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7] ({\gen_cdc_pntr.wpr_gray_reg_n_1 ,\gen_cdc_pntr.wpr_gray_reg_n_2 ,\gen_cdc_pntr.wpr_gray_reg_n_3 ,\gen_cdc_pntr.wpr_gray_reg_n_4 ,\gen_cdc_pntr.wpr_gray_reg_n_5 ,\gen_cdc_pntr.wpr_gray_reg_n_6 ,\gen_cdc_pntr.wpr_gray_reg_n_7 ,\gen_cdc_pntr.wpr_gray_reg_n_8 }), .\grdc.rd_data_count_i_reg[7] (count_value_i), .\grdc.rd_data_count_i_reg[8] ({\gen_cdc_pntr.wpr_gray_reg_dc_n_8 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_9 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_10 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_11 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_12 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_13 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_14 ,\gen_cdc_pntr.wpr_gray_reg_dc_n_15 }), .ram_empty_i(ram_empty_i), .rd_clk(rd_clk), .rd_en(rd_en), .src_in_bin({rdp_inst_n_24,rdp_inst_n_25,rdp_inst_n_26,rdp_inst_n_27,rdp_inst_n_28,rdp_inst_n_29,rdp_inst_n_30,rdp_inst_n_31})); axi_chip2chip_64B66B_xpm_counter_updn__parameterized1_29 rdpp1_inst (.E(rdp_inst_n_8), .Q({rdpp1_inst_n_0,rdpp1_inst_n_1,rdpp1_inst_n_2,rdpp1_inst_n_3,rdpp1_inst_n_4,rdpp1_inst_n_5,rdpp1_inst_n_6,rdpp1_inst_n_7}), .\count_value_i_reg[0]_0 (rd_rst_busy), .\count_value_i_reg[1]_0 (curr_fwft_state), .ram_empty_i(ram_empty_i), .rd_clk(rd_clk), .rd_en(rd_en)); axi_chip2chip_64B66B_xpm_fifo_reg_bit_30 rst_d1_inst (.Q(diff_pntr_pf_q[8]), .\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] (rst_d1_inst_n_1), .\gen_pf_ic_rc.gpf_ic.prog_full_i_reg (\gen_pf_ic_rc.gpf_ic.prog_full_i_i_2_n_0 ), .\gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 (full), .overflow_i0(overflow_i0), .prog_full(prog_full), .rst(rst), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), .wrst_busy(wrst_busy)); axi_chip2chip_64B66B_xpm_counter_updn__parameterized0_31 wrp_inst (.D(\gwdc.diff_wr_rd_pntr1_out ), .Q(wr_pntr_ext), .\count_value_i_reg[6]_0 (full), .\gwdc.wr_data_count_i_reg[8] ({\gen_cdc_pntr.rpw_gray_reg_dc_n_0 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_1 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_2 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_3 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_4 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_5 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_6 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_7 ,\gen_cdc_pntr.rpw_gray_reg_dc_n_8 }), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wrst_busy(wrst_busy)); axi_chip2chip_64B66B_xpm_counter_updn__parameterized1_32 wrpp1_inst (.D(diff_pntr_pf_q0), .Q(wr_pntr_plus1_pf), .\count_value_i_reg[6]_0 (full), .\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] (rd_pntr_wr), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wrst_busy(wrst_busy)); axi_chip2chip_64B66B_xpm_counter_updn__parameterized2_33 wrpp2_inst (.Q({wrpp2_inst_n_0,wrpp2_inst_n_1,wrpp2_inst_n_2,wrpp2_inst_n_3,wrpp2_inst_n_4,wrpp2_inst_n_5,wrpp2_inst_n_6,wrpp2_inst_n_7}), .\count_value_i_reg[6]_0 (full), .rst_d1(rst_d1), .wr_clk(wr_clk), .wr_en(wr_en), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wrst_busy(wrst_busy)); axi_chip2chip_64B66B_xpm_fifo_rst__xdcDup__1 xpm_fifo_rst_inst (.Q(curr_fwft_state), .SR(\grdc.rd_data_count_i0 ), .\count_value_i_reg[7] (full), .\gen_rst_ic.fifo_rd_rst_ic_reg_0 (rd_rst_busy), .\gen_rst_ic.fifo_rd_rst_ic_reg_1 (\gen_fwft.count_rst ), .\guf.underflow_i_reg (empty), .ram_empty_i(ram_empty_i), .rd_clk(rd_clk), .rd_en(rd_en), .rst(rst), .rst_d1(rst_d1), .underflow_i0(underflow_i0), .wr_clk(wr_clk), .wr_en(wr_en), .wr_pntr_plus1_pf_carry(wr_pntr_plus1_pf_carry), .wr_rst_busy(wr_rst_busy), .wrst_busy(wrst_busy)); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_bit" *) module axi_chip2chip_64B66B_xpm_fifo_reg_bit (rst_d1, \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] , clr_full, overflow_i0, wrst_busy, wr_clk, Q, \gen_pf_ic_rc.gpf_ic.prog_full_i_reg , \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 , prog_full, wr_en, rst); output rst_d1; output \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] ; output clr_full; output overflow_i0; input wrst_busy; input wr_clk; input [1:0]Q; input \gen_pf_ic_rc.gpf_ic.prog_full_i_reg ; input \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 ; input prog_full; input wr_en; input rst; wire [1:0]Q; wire clr_full; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] ; wire \gen_pf_ic_rc.gpf_ic.prog_full_i_reg ; wire \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 ; wire overflow_i0; wire prog_full; wire rst; wire rst_d1; wire wr_clk; wire wr_en; wire wrst_busy; FDRE #( .INIT(1'b0)) d_out_reg (.C(wr_clk), .CE(1'b1), .D(wrst_busy), .Q(rst_d1), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair250" *) LUT3 #( .INIT(8'h04)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6 (.I0(rst), .I1(rst_d1), .I2(wrst_busy), .O(clr_full)); LUT6 #( .INIT(64'h00FF00E0000000E0)) \gen_pf_ic_rc.gpf_ic.prog_full_i_i_1 (.I0(Q[0]), .I1(\gen_pf_ic_rc.gpf_ic.prog_full_i_reg ), .I2(Q[1]), .I3(clr_full), .I4(\gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 ), .I5(prog_full), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] )); (* SOFT_HLUTNM = "soft_lutpair250" *) LUT4 #( .INIT(16'hFE00)) \gof.overflow_i_i_1 (.I0(rst_d1), .I1(wrst_busy), .I2(\gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 ), .I3(wr_en), .O(overflow_i0)); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_bit" *) module axi_chip2chip_64B66B_xpm_fifo_reg_bit_11 (rst_d1, \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] , clr_full, overflow_i0, wrst_busy, wr_clk, Q, \gen_pf_ic_rc.gpf_ic.prog_full_i_reg , \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 , prog_full, wr_en, rst); output rst_d1; output \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] ; output clr_full; output overflow_i0; input wrst_busy; input wr_clk; input [1:0]Q; input \gen_pf_ic_rc.gpf_ic.prog_full_i_reg ; input \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 ; input prog_full; input wr_en; input rst; wire [1:0]Q; wire clr_full; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] ; wire \gen_pf_ic_rc.gpf_ic.prog_full_i_reg ; wire \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 ; wire overflow_i0; wire prog_full; wire rst; wire rst_d1; wire wr_clk; wire wr_en; wire wrst_busy; FDRE #( .INIT(1'b0)) d_out_reg (.C(wr_clk), .CE(1'b1), .D(wrst_busy), .Q(rst_d1), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair190" *) LUT3 #( .INIT(8'h04)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6 (.I0(rst), .I1(rst_d1), .I2(wrst_busy), .O(clr_full)); LUT6 #( .INIT(64'h00FF00E0000000E0)) \gen_pf_ic_rc.gpf_ic.prog_full_i_i_1 (.I0(Q[0]), .I1(\gen_pf_ic_rc.gpf_ic.prog_full_i_reg ), .I2(Q[1]), .I3(clr_full), .I4(\gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 ), .I5(prog_full), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] )); (* SOFT_HLUTNM = "soft_lutpair190" *) LUT4 #( .INIT(16'hFE00)) \gof.overflow_i_i_1 (.I0(rst_d1), .I1(wrst_busy), .I2(\gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 ), .I3(wr_en), .O(overflow_i0)); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_bit" *) module axi_chip2chip_64B66B_xpm_fifo_reg_bit_20 (rst_d1, \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] , overflow_i0, wrst_busy, wr_clk, \gen_pf_ic_rc.gpf_ic.prog_full_i_reg , Q, \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 , prog_full, wr_en, rst); output rst_d1; output \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] ; output overflow_i0; input wrst_busy; input wr_clk; input \gen_pf_ic_rc.gpf_ic.prog_full_i_reg ; input [0:0]Q; input \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 ; input prog_full; input wr_en; input rst; wire [0:0]Q; wire clr_full; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] ; wire \gen_pf_ic_rc.gpf_ic.prog_full_i_reg ; wire \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 ; wire overflow_i0; wire prog_full; wire rst; wire rst_d1; wire wr_clk; wire wr_en; wire wrst_busy; FDRE #( .INIT(1'b0)) d_out_reg (.C(wr_clk), .CE(1'b1), .D(wrst_busy), .Q(rst_d1), .R(1'b0)); LUT5 #( .INIT(32'h0F0E000E)) \gen_pf_ic_rc.gpf_ic.prog_full_i_i_1 (.I0(\gen_pf_ic_rc.gpf_ic.prog_full_i_reg ), .I1(Q), .I2(clr_full), .I3(\gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 ), .I4(prog_full), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] )); (* SOFT_HLUTNM = "soft_lutpair148" *) LUT3 #( .INIT(8'h04)) \gen_pf_ic_rc.gpf_ic.prog_full_i_i_3 (.I0(rst), .I1(rst_d1), .I2(wrst_busy), .O(clr_full)); (* SOFT_HLUTNM = "soft_lutpair148" *) LUT4 #( .INIT(16'hFE00)) \gof.overflow_i_i_1 (.I0(rst_d1), .I1(wrst_busy), .I2(\gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 ), .I3(wr_en), .O(overflow_i0)); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_bit" *) module axi_chip2chip_64B66B_xpm_fifo_reg_bit_30 (rst_d1, \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] , overflow_i0, wrst_busy, wr_clk, \gen_pf_ic_rc.gpf_ic.prog_full_i_reg , Q, \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 , prog_full, wr_en, rst); output rst_d1; output \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] ; output overflow_i0; input wrst_busy; input wr_clk; input \gen_pf_ic_rc.gpf_ic.prog_full_i_reg ; input [0:0]Q; input \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 ; input prog_full; input wr_en; input rst; wire [0:0]Q; wire clr_full; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] ; wire \gen_pf_ic_rc.gpf_ic.prog_full_i_reg ; wire \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 ; wire overflow_i0; wire prog_full; wire rst; wire rst_d1; wire wr_clk; wire wr_en; wire wrst_busy; FDRE #( .INIT(1'b0)) d_out_reg (.C(wr_clk), .CE(1'b1), .D(wrst_busy), .Q(rst_d1), .R(1'b0)); LUT5 #( .INIT(32'h0F0E000E)) \gen_pf_ic_rc.gpf_ic.prog_full_i_i_1 (.I0(\gen_pf_ic_rc.gpf_ic.prog_full_i_reg ), .I1(Q), .I2(clr_full), .I3(\gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 ), .I4(prog_full), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] )); (* SOFT_HLUTNM = "soft_lutpair115" *) LUT3 #( .INIT(8'h04)) \gen_pf_ic_rc.gpf_ic.prog_full_i_i_3 (.I0(rst), .I1(rst_d1), .I2(wrst_busy), .O(clr_full)); (* SOFT_HLUTNM = "soft_lutpair115" *) LUT4 #( .INIT(16'hFE00)) \gof.overflow_i_i_1 (.I0(rst_d1), .I1(wrst_busy), .I2(\gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 ), .I3(wr_en), .O(overflow_i0)); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_bit" *) module axi_chip2chip_64B66B_xpm_fifo_reg_bit_41 (rst_d1, \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] , overflow_i0, wrst_busy, wr_clk, \gen_pf_ic_rc.gpf_ic.prog_full_i_reg , Q, \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 , prog_full, wr_en, rst); output rst_d1; output \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] ; output overflow_i0; input wrst_busy; input wr_clk; input \gen_pf_ic_rc.gpf_ic.prog_full_i_reg ; input [0:0]Q; input \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 ; input prog_full; input wr_en; input rst; wire [0:0]Q; wire clr_full; wire \gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] ; wire \gen_pf_ic_rc.gpf_ic.prog_full_i_reg ; wire \gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 ; wire overflow_i0; wire prog_full; wire rst; wire rst_d1; wire wr_clk; wire wr_en; wire wrst_busy; FDRE #( .INIT(1'b0)) d_out_reg (.C(wr_clk), .CE(1'b1), .D(wrst_busy), .Q(rst_d1), .R(1'b0)); LUT5 #( .INIT(32'h0F0E000E)) \gen_pf_ic_rc.gpf_ic.prog_full_i_i_1 (.I0(\gen_pf_ic_rc.gpf_ic.prog_full_i_reg ), .I1(Q), .I2(clr_full), .I3(\gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 ), .I4(prog_full), .O(\gen_pf_ic_rc.gpf_ic.diff_pntr_pf_q_reg[8] )); (* SOFT_HLUTNM = "soft_lutpair81" *) LUT3 #( .INIT(8'h04)) \gen_pf_ic_rc.gpf_ic.prog_full_i_i_3 (.I0(rst), .I1(rst_d1), .I2(wrst_busy), .O(clr_full)); (* SOFT_HLUTNM = "soft_lutpair81" *) LUT4 #( .INIT(16'hFE00)) \gof.overflow_i_i_1 (.I0(rst_d1), .I1(wrst_busy), .I2(\gen_pf_ic_rc.gpf_ic.prog_full_i_reg_0 ), .I3(wr_en), .O(overflow_i0)); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_vec" *) module axi_chip2chip_64B66B_xpm_fifo_reg_vec (\reg_out_i_reg[7]_0 , d_out_reg, Q, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg , wr_pntr_plus1_pf_carry, rst_d1, rst, wrst_busy, D, wr_clk); output [7:0]\reg_out_i_reg[7]_0 ; output d_out_reg; input [7:0]Q; input [7:0]\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg ; input wr_pntr_plus1_pf_carry; input rst_d1; input rst; input wrst_busy; input [7:0]D; input wr_clk; wire [7:0]D; wire [7:0]Q; wire d_out_reg; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0 ; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_n_0 ; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6_n_0 ; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0 ; wire [7:0]\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg ; wire going_full0; wire leaving_full; wire [7:0]\reg_out_i_reg[7]_0 ; wire rst; wire rst_d1; wire wr_clk; wire wr_pntr_plus1_pf_carry; wire wrst_busy; LUT5 #( .INIT(32'hEAEA00EA)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_1 (.I0(leaving_full), .I1(going_full0), .I2(wr_pntr_plus1_pf_carry), .I3(rst_d1), .I4(rst), .O(d_out_reg)); LUT6 #( .INIT(64'h9009000000000000)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_2 (.I0(Q[7]), .I1(\reg_out_i_reg[7]_0 [7]), .I2(Q[6]), .I3(\reg_out_i_reg[7]_0 [6]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0 ), .I5(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_n_0 ), .O(leaving_full)); LUT6 #( .INIT(64'h9009000000000000)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_3 (.I0(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [7]), .I1(\reg_out_i_reg[7]_0 [7]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [6]), .I3(\reg_out_i_reg[7]_0 [6]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6_n_0 ), .I5(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0 ), .O(going_full0)); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4 (.I0(\reg_out_i_reg[7]_0 [3]), .I1(Q[3]), .I2(Q[5]), .I3(\reg_out_i_reg[7]_0 [5]), .I4(Q[4]), .I5(\reg_out_i_reg[7]_0 [4]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5 (.I0(\reg_out_i_reg[7]_0 [0]), .I1(Q[0]), .I2(Q[2]), .I3(\reg_out_i_reg[7]_0 [2]), .I4(Q[1]), .I5(\reg_out_i_reg[7]_0 [1]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6 (.I0(\reg_out_i_reg[7]_0 [3]), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [3]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [5]), .I3(\reg_out_i_reg[7]_0 [5]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [4]), .I5(\reg_out_i_reg[7]_0 [4]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7 (.I0(\reg_out_i_reg[7]_0 [0]), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [0]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [2]), .I3(\reg_out_i_reg[7]_0 [2]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [1]), .I5(\reg_out_i_reg[7]_0 [1]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[0] (.C(wr_clk), .CE(1'b1), .D(D[0]), .Q(\reg_out_i_reg[7]_0 [0]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[1] (.C(wr_clk), .CE(1'b1), .D(D[1]), .Q(\reg_out_i_reg[7]_0 [1]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[2] (.C(wr_clk), .CE(1'b1), .D(D[2]), .Q(\reg_out_i_reg[7]_0 [2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[3] (.C(wr_clk), .CE(1'b1), .D(D[3]), .Q(\reg_out_i_reg[7]_0 [3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[4] (.C(wr_clk), .CE(1'b1), .D(D[4]), .Q(\reg_out_i_reg[7]_0 [4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[5] (.C(wr_clk), .CE(1'b1), .D(D[5]), .Q(\reg_out_i_reg[7]_0 [5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[6] (.C(wr_clk), .CE(1'b1), .D(D[6]), .Q(\reg_out_i_reg[7]_0 [6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[7] (.C(wr_clk), .CE(1'b1), .D(D[7]), .Q(\reg_out_i_reg[7]_0 [7]), .R(wrst_busy)); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_vec" *) module axi_chip2chip_64B66B_xpm_fifo_reg_vec_17 (ram_empty_i0, \reg_out_i_reg[7]_0 , Q, rd_en, ram_empty_i, \gen_pf_ic_rc.ram_empty_i_reg , \gen_pf_ic_rc.ram_empty_i_reg_0 , \reg_out_i_reg[0]_0 , D, rd_clk); output ram_empty_i0; output [7:0]\reg_out_i_reg[7]_0 ; input [1:0]Q; input rd_en; input ram_empty_i; input [7:0]\gen_pf_ic_rc.ram_empty_i_reg ; input [7:0]\gen_pf_ic_rc.ram_empty_i_reg_0 ; input \reg_out_i_reg[0]_0 ; input [7:0]D; input rd_clk; wire [7:0]D; wire [1:0]Q; wire \gen_pf_ic_rc.ram_empty_i_i_4_n_0 ; wire \gen_pf_ic_rc.ram_empty_i_i_5_n_0 ; wire \gen_pf_ic_rc.ram_empty_i_i_6_n_0 ; wire \gen_pf_ic_rc.ram_empty_i_i_7_n_0 ; wire [7:0]\gen_pf_ic_rc.ram_empty_i_reg ; wire [7:0]\gen_pf_ic_rc.ram_empty_i_reg_0 ; wire going_empty0; wire leaving_empty; wire ram_empty_i; wire ram_empty_i0; wire rd_clk; wire rd_en; wire \reg_out_i_reg[0]_0 ; wire [7:0]\reg_out_i_reg[7]_0 ; LUT6 #( .INIT(64'hFFFFFFFF00FD0000)) \gen_pf_ic_rc.ram_empty_i_i_1 (.I0(Q[1]), .I1(Q[0]), .I2(rd_en), .I3(ram_empty_i), .I4(going_empty0), .I5(leaving_empty), .O(ram_empty_i0)); LUT6 #( .INIT(64'h9009000000000000)) \gen_pf_ic_rc.ram_empty_i_i_2 (.I0(\gen_pf_ic_rc.ram_empty_i_reg_0 [7]), .I1(\reg_out_i_reg[7]_0 [7]), .I2(\gen_pf_ic_rc.ram_empty_i_reg_0 [6]), .I3(\reg_out_i_reg[7]_0 [6]), .I4(\gen_pf_ic_rc.ram_empty_i_i_4_n_0 ), .I5(\gen_pf_ic_rc.ram_empty_i_i_5_n_0 ), .O(going_empty0)); LUT6 #( .INIT(64'h9009000000000000)) \gen_pf_ic_rc.ram_empty_i_i_3 (.I0(\gen_pf_ic_rc.ram_empty_i_reg [7]), .I1(\reg_out_i_reg[7]_0 [7]), .I2(\gen_pf_ic_rc.ram_empty_i_reg [6]), .I3(\reg_out_i_reg[7]_0 [6]), .I4(\gen_pf_ic_rc.ram_empty_i_i_6_n_0 ), .I5(\gen_pf_ic_rc.ram_empty_i_i_7_n_0 ), .O(leaving_empty)); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_4 (.I0(\reg_out_i_reg[7]_0 [3]), .I1(\gen_pf_ic_rc.ram_empty_i_reg_0 [3]), .I2(\gen_pf_ic_rc.ram_empty_i_reg_0 [5]), .I3(\reg_out_i_reg[7]_0 [5]), .I4(\gen_pf_ic_rc.ram_empty_i_reg_0 [4]), .I5(\reg_out_i_reg[7]_0 [4]), .O(\gen_pf_ic_rc.ram_empty_i_i_4_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_5 (.I0(\reg_out_i_reg[7]_0 [0]), .I1(\gen_pf_ic_rc.ram_empty_i_reg_0 [0]), .I2(\gen_pf_ic_rc.ram_empty_i_reg_0 [2]), .I3(\reg_out_i_reg[7]_0 [2]), .I4(\gen_pf_ic_rc.ram_empty_i_reg_0 [1]), .I5(\reg_out_i_reg[7]_0 [1]), .O(\gen_pf_ic_rc.ram_empty_i_i_5_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_6 (.I0(\reg_out_i_reg[7]_0 [3]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [3]), .I2(\gen_pf_ic_rc.ram_empty_i_reg [5]), .I3(\reg_out_i_reg[7]_0 [5]), .I4(\gen_pf_ic_rc.ram_empty_i_reg [4]), .I5(\reg_out_i_reg[7]_0 [4]), .O(\gen_pf_ic_rc.ram_empty_i_i_6_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_7 (.I0(\reg_out_i_reg[7]_0 [0]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [0]), .I2(\gen_pf_ic_rc.ram_empty_i_reg [2]), .I3(\reg_out_i_reg[7]_0 [2]), .I4(\gen_pf_ic_rc.ram_empty_i_reg [1]), .I5(\reg_out_i_reg[7]_0 [1]), .O(\gen_pf_ic_rc.ram_empty_i_i_7_n_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[0] (.C(rd_clk), .CE(1'b1), .D(D[0]), .Q(\reg_out_i_reg[7]_0 [0]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[1] (.C(rd_clk), .CE(1'b1), .D(D[1]), .Q(\reg_out_i_reg[7]_0 [1]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[2] (.C(rd_clk), .CE(1'b1), .D(D[2]), .Q(\reg_out_i_reg[7]_0 [2]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[3] (.C(rd_clk), .CE(1'b1), .D(D[3]), .Q(\reg_out_i_reg[7]_0 [3]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[4] (.C(rd_clk), .CE(1'b1), .D(D[4]), .Q(\reg_out_i_reg[7]_0 [4]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[5] (.C(rd_clk), .CE(1'b1), .D(D[5]), .Q(\reg_out_i_reg[7]_0 [5]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[6] (.C(rd_clk), .CE(1'b1), .D(D[6]), .Q(\reg_out_i_reg[7]_0 [6]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[7] (.C(rd_clk), .CE(1'b1), .D(D[7]), .Q(\reg_out_i_reg[7]_0 [7]), .R(\reg_out_i_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_vec" *) module axi_chip2chip_64B66B_xpm_fifo_reg_vec_23 (\reg_out_i_reg[7]_0 , d_out_reg, Q, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg , wr_pntr_plus1_pf_carry, rst_d1, rst, wrst_busy, D, wr_clk); output [7:0]\reg_out_i_reg[7]_0 ; output d_out_reg; input [7:0]Q; input [7:0]\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg ; input wr_pntr_plus1_pf_carry; input rst_d1; input rst; input wrst_busy; input [7:0]D; input wr_clk; wire [7:0]D; wire [7:0]Q; wire d_out_reg; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0 ; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_n_0 ; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6_n_0 ; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0 ; wire [7:0]\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg ; wire going_full0; wire leaving_full; wire [7:0]\reg_out_i_reg[7]_0 ; wire rst; wire rst_d1; wire wr_clk; wire wr_pntr_plus1_pf_carry; wire wrst_busy; LUT5 #( .INIT(32'hEAEA00EA)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_1 (.I0(leaving_full), .I1(going_full0), .I2(wr_pntr_plus1_pf_carry), .I3(rst_d1), .I4(rst), .O(d_out_reg)); LUT6 #( .INIT(64'h9009000000000000)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_2 (.I0(Q[7]), .I1(\reg_out_i_reg[7]_0 [7]), .I2(Q[6]), .I3(\reg_out_i_reg[7]_0 [6]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0 ), .I5(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_n_0 ), .O(leaving_full)); LUT6 #( .INIT(64'h9009000000000000)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_3 (.I0(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [7]), .I1(\reg_out_i_reg[7]_0 [7]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [6]), .I3(\reg_out_i_reg[7]_0 [6]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6_n_0 ), .I5(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0 ), .O(going_full0)); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4 (.I0(\reg_out_i_reg[7]_0 [3]), .I1(Q[3]), .I2(Q[5]), .I3(\reg_out_i_reg[7]_0 [5]), .I4(Q[4]), .I5(\reg_out_i_reg[7]_0 [4]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5 (.I0(\reg_out_i_reg[7]_0 [0]), .I1(Q[0]), .I2(Q[2]), .I3(\reg_out_i_reg[7]_0 [2]), .I4(Q[1]), .I5(\reg_out_i_reg[7]_0 [1]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6 (.I0(\reg_out_i_reg[7]_0 [3]), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [3]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [5]), .I3(\reg_out_i_reg[7]_0 [5]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [4]), .I5(\reg_out_i_reg[7]_0 [4]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7 (.I0(\reg_out_i_reg[7]_0 [0]), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [0]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [2]), .I3(\reg_out_i_reg[7]_0 [2]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [1]), .I5(\reg_out_i_reg[7]_0 [1]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[0] (.C(wr_clk), .CE(1'b1), .D(D[0]), .Q(\reg_out_i_reg[7]_0 [0]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[1] (.C(wr_clk), .CE(1'b1), .D(D[1]), .Q(\reg_out_i_reg[7]_0 [1]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[2] (.C(wr_clk), .CE(1'b1), .D(D[2]), .Q(\reg_out_i_reg[7]_0 [2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[3] (.C(wr_clk), .CE(1'b1), .D(D[3]), .Q(\reg_out_i_reg[7]_0 [3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[4] (.C(wr_clk), .CE(1'b1), .D(D[4]), .Q(\reg_out_i_reg[7]_0 [4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[5] (.C(wr_clk), .CE(1'b1), .D(D[5]), .Q(\reg_out_i_reg[7]_0 [5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[6] (.C(wr_clk), .CE(1'b1), .D(D[6]), .Q(\reg_out_i_reg[7]_0 [6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[7] (.C(wr_clk), .CE(1'b1), .D(D[7]), .Q(\reg_out_i_reg[7]_0 [7]), .R(wrst_busy)); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_vec" *) module axi_chip2chip_64B66B_xpm_fifo_reg_vec_25 (ram_empty_i0, \reg_out_i_reg[7]_0 , Q, rd_en, ram_empty_i, \gen_pf_ic_rc.ram_empty_i_reg , \gen_pf_ic_rc.ram_empty_i_reg_0 , \reg_out_i_reg[0]_0 , D, rd_clk); output ram_empty_i0; output [7:0]\reg_out_i_reg[7]_0 ; input [1:0]Q; input rd_en; input ram_empty_i; input [7:0]\gen_pf_ic_rc.ram_empty_i_reg ; input [7:0]\gen_pf_ic_rc.ram_empty_i_reg_0 ; input \reg_out_i_reg[0]_0 ; input [7:0]D; input rd_clk; wire [7:0]D; wire [1:0]Q; wire \gen_pf_ic_rc.ram_empty_i_i_4_n_0 ; wire \gen_pf_ic_rc.ram_empty_i_i_5_n_0 ; wire \gen_pf_ic_rc.ram_empty_i_i_6_n_0 ; wire \gen_pf_ic_rc.ram_empty_i_i_7_n_0 ; wire [7:0]\gen_pf_ic_rc.ram_empty_i_reg ; wire [7:0]\gen_pf_ic_rc.ram_empty_i_reg_0 ; wire going_empty0; wire leaving_empty; wire ram_empty_i; wire ram_empty_i0; wire rd_clk; wire rd_en; wire \reg_out_i_reg[0]_0 ; wire [7:0]\reg_out_i_reg[7]_0 ; LUT6 #( .INIT(64'hFFFFFFFF00FD0000)) \gen_pf_ic_rc.ram_empty_i_i_1 (.I0(Q[1]), .I1(Q[0]), .I2(rd_en), .I3(ram_empty_i), .I4(going_empty0), .I5(leaving_empty), .O(ram_empty_i0)); LUT6 #( .INIT(64'h9009000000000000)) \gen_pf_ic_rc.ram_empty_i_i_2 (.I0(\gen_pf_ic_rc.ram_empty_i_reg_0 [7]), .I1(\reg_out_i_reg[7]_0 [7]), .I2(\gen_pf_ic_rc.ram_empty_i_reg_0 [6]), .I3(\reg_out_i_reg[7]_0 [6]), .I4(\gen_pf_ic_rc.ram_empty_i_i_4_n_0 ), .I5(\gen_pf_ic_rc.ram_empty_i_i_5_n_0 ), .O(going_empty0)); LUT6 #( .INIT(64'h9009000000000000)) \gen_pf_ic_rc.ram_empty_i_i_3 (.I0(\gen_pf_ic_rc.ram_empty_i_reg [7]), .I1(\reg_out_i_reg[7]_0 [7]), .I2(\gen_pf_ic_rc.ram_empty_i_reg [6]), .I3(\reg_out_i_reg[7]_0 [6]), .I4(\gen_pf_ic_rc.ram_empty_i_i_6_n_0 ), .I5(\gen_pf_ic_rc.ram_empty_i_i_7_n_0 ), .O(leaving_empty)); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_4 (.I0(\reg_out_i_reg[7]_0 [3]), .I1(\gen_pf_ic_rc.ram_empty_i_reg_0 [3]), .I2(\gen_pf_ic_rc.ram_empty_i_reg_0 [5]), .I3(\reg_out_i_reg[7]_0 [5]), .I4(\gen_pf_ic_rc.ram_empty_i_reg_0 [4]), .I5(\reg_out_i_reg[7]_0 [4]), .O(\gen_pf_ic_rc.ram_empty_i_i_4_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_5 (.I0(\reg_out_i_reg[7]_0 [0]), .I1(\gen_pf_ic_rc.ram_empty_i_reg_0 [0]), .I2(\gen_pf_ic_rc.ram_empty_i_reg_0 [2]), .I3(\reg_out_i_reg[7]_0 [2]), .I4(\gen_pf_ic_rc.ram_empty_i_reg_0 [1]), .I5(\reg_out_i_reg[7]_0 [1]), .O(\gen_pf_ic_rc.ram_empty_i_i_5_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_6 (.I0(\reg_out_i_reg[7]_0 [3]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [3]), .I2(\gen_pf_ic_rc.ram_empty_i_reg [5]), .I3(\reg_out_i_reg[7]_0 [5]), .I4(\gen_pf_ic_rc.ram_empty_i_reg [4]), .I5(\reg_out_i_reg[7]_0 [4]), .O(\gen_pf_ic_rc.ram_empty_i_i_6_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_7 (.I0(\reg_out_i_reg[7]_0 [0]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [0]), .I2(\gen_pf_ic_rc.ram_empty_i_reg [2]), .I3(\reg_out_i_reg[7]_0 [2]), .I4(\gen_pf_ic_rc.ram_empty_i_reg [1]), .I5(\reg_out_i_reg[7]_0 [1]), .O(\gen_pf_ic_rc.ram_empty_i_i_7_n_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[0] (.C(rd_clk), .CE(1'b1), .D(D[0]), .Q(\reg_out_i_reg[7]_0 [0]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[1] (.C(rd_clk), .CE(1'b1), .D(D[1]), .Q(\reg_out_i_reg[7]_0 [1]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[2] (.C(rd_clk), .CE(1'b1), .D(D[2]), .Q(\reg_out_i_reg[7]_0 [2]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[3] (.C(rd_clk), .CE(1'b1), .D(D[3]), .Q(\reg_out_i_reg[7]_0 [3]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[4] (.C(rd_clk), .CE(1'b1), .D(D[4]), .Q(\reg_out_i_reg[7]_0 [4]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[5] (.C(rd_clk), .CE(1'b1), .D(D[5]), .Q(\reg_out_i_reg[7]_0 [5]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[6] (.C(rd_clk), .CE(1'b1), .D(D[6]), .Q(\reg_out_i_reg[7]_0 [6]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[7] (.C(rd_clk), .CE(1'b1), .D(D[7]), .Q(\reg_out_i_reg[7]_0 [7]), .R(\reg_out_i_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_vec" *) module axi_chip2chip_64B66B_xpm_fifo_reg_vec_34 (\reg_out_i_reg[7]_0 , d_out_reg, Q, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg , wr_pntr_plus1_pf_carry, rst_d1, rst, wrst_busy, D, wr_clk); output [7:0]\reg_out_i_reg[7]_0 ; output d_out_reg; input [7:0]Q; input [7:0]\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg ; input wr_pntr_plus1_pf_carry; input rst_d1; input rst; input wrst_busy; input [7:0]D; input wr_clk; wire [7:0]D; wire [7:0]Q; wire d_out_reg; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0 ; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_n_0 ; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6_n_0 ; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0 ; wire [7:0]\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg ; wire going_full0; wire leaving_full; wire [7:0]\reg_out_i_reg[7]_0 ; wire rst; wire rst_d1; wire wr_clk; wire wr_pntr_plus1_pf_carry; wire wrst_busy; LUT5 #( .INIT(32'hEAEA00EA)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_1 (.I0(leaving_full), .I1(going_full0), .I2(wr_pntr_plus1_pf_carry), .I3(rst_d1), .I4(rst), .O(d_out_reg)); LUT6 #( .INIT(64'h9009000000000000)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_2 (.I0(Q[7]), .I1(\reg_out_i_reg[7]_0 [7]), .I2(Q[6]), .I3(\reg_out_i_reg[7]_0 [6]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0 ), .I5(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_n_0 ), .O(leaving_full)); LUT6 #( .INIT(64'h9009000000000000)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_3 (.I0(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [7]), .I1(\reg_out_i_reg[7]_0 [7]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [6]), .I3(\reg_out_i_reg[7]_0 [6]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6_n_0 ), .I5(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0 ), .O(going_full0)); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4 (.I0(\reg_out_i_reg[7]_0 [3]), .I1(Q[3]), .I2(Q[5]), .I3(\reg_out_i_reg[7]_0 [5]), .I4(Q[4]), .I5(\reg_out_i_reg[7]_0 [4]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5 (.I0(\reg_out_i_reg[7]_0 [0]), .I1(Q[0]), .I2(Q[2]), .I3(\reg_out_i_reg[7]_0 [2]), .I4(Q[1]), .I5(\reg_out_i_reg[7]_0 [1]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6 (.I0(\reg_out_i_reg[7]_0 [3]), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [3]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [5]), .I3(\reg_out_i_reg[7]_0 [5]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [4]), .I5(\reg_out_i_reg[7]_0 [4]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_6_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7 (.I0(\reg_out_i_reg[7]_0 [0]), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [0]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [2]), .I3(\reg_out_i_reg[7]_0 [2]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [1]), .I5(\reg_out_i_reg[7]_0 [1]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[0] (.C(wr_clk), .CE(1'b1), .D(D[0]), .Q(\reg_out_i_reg[7]_0 [0]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[1] (.C(wr_clk), .CE(1'b1), .D(D[1]), .Q(\reg_out_i_reg[7]_0 [1]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[2] (.C(wr_clk), .CE(1'b1), .D(D[2]), .Q(\reg_out_i_reg[7]_0 [2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[3] (.C(wr_clk), .CE(1'b1), .D(D[3]), .Q(\reg_out_i_reg[7]_0 [3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[4] (.C(wr_clk), .CE(1'b1), .D(D[4]), .Q(\reg_out_i_reg[7]_0 [4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[5] (.C(wr_clk), .CE(1'b1), .D(D[5]), .Q(\reg_out_i_reg[7]_0 [5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[6] (.C(wr_clk), .CE(1'b1), .D(D[6]), .Q(\reg_out_i_reg[7]_0 [6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[7] (.C(wr_clk), .CE(1'b1), .D(D[7]), .Q(\reg_out_i_reg[7]_0 [7]), .R(wrst_busy)); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_vec" *) module axi_chip2chip_64B66B_xpm_fifo_reg_vec_36 (ram_empty_i0, \reg_out_i_reg[7]_0 , Q, rd_en, ram_empty_i, \gen_pf_ic_rc.ram_empty_i_reg , \gen_pf_ic_rc.ram_empty_i_reg_0 , \reg_out_i_reg[0]_0 , D, rd_clk); output ram_empty_i0; output [7:0]\reg_out_i_reg[7]_0 ; input [1:0]Q; input rd_en; input ram_empty_i; input [7:0]\gen_pf_ic_rc.ram_empty_i_reg ; input [7:0]\gen_pf_ic_rc.ram_empty_i_reg_0 ; input \reg_out_i_reg[0]_0 ; input [7:0]D; input rd_clk; wire [7:0]D; wire [1:0]Q; wire \gen_pf_ic_rc.ram_empty_i_i_4_n_0 ; wire \gen_pf_ic_rc.ram_empty_i_i_5_n_0 ; wire \gen_pf_ic_rc.ram_empty_i_i_6_n_0 ; wire \gen_pf_ic_rc.ram_empty_i_i_7_n_0 ; wire [7:0]\gen_pf_ic_rc.ram_empty_i_reg ; wire [7:0]\gen_pf_ic_rc.ram_empty_i_reg_0 ; wire going_empty0; wire leaving_empty; wire ram_empty_i; wire ram_empty_i0; wire rd_clk; wire rd_en; wire \reg_out_i_reg[0]_0 ; wire [7:0]\reg_out_i_reg[7]_0 ; LUT6 #( .INIT(64'hFFFFFFFF00FD0000)) \gen_pf_ic_rc.ram_empty_i_i_1 (.I0(Q[1]), .I1(Q[0]), .I2(rd_en), .I3(ram_empty_i), .I4(going_empty0), .I5(leaving_empty), .O(ram_empty_i0)); LUT6 #( .INIT(64'h9009000000000000)) \gen_pf_ic_rc.ram_empty_i_i_2 (.I0(\gen_pf_ic_rc.ram_empty_i_reg_0 [7]), .I1(\reg_out_i_reg[7]_0 [7]), .I2(\gen_pf_ic_rc.ram_empty_i_reg_0 [6]), .I3(\reg_out_i_reg[7]_0 [6]), .I4(\gen_pf_ic_rc.ram_empty_i_i_4_n_0 ), .I5(\gen_pf_ic_rc.ram_empty_i_i_5_n_0 ), .O(going_empty0)); LUT6 #( .INIT(64'h9009000000000000)) \gen_pf_ic_rc.ram_empty_i_i_3 (.I0(\gen_pf_ic_rc.ram_empty_i_reg [7]), .I1(\reg_out_i_reg[7]_0 [7]), .I2(\gen_pf_ic_rc.ram_empty_i_reg [6]), .I3(\reg_out_i_reg[7]_0 [6]), .I4(\gen_pf_ic_rc.ram_empty_i_i_6_n_0 ), .I5(\gen_pf_ic_rc.ram_empty_i_i_7_n_0 ), .O(leaving_empty)); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_4 (.I0(\reg_out_i_reg[7]_0 [3]), .I1(\gen_pf_ic_rc.ram_empty_i_reg_0 [3]), .I2(\gen_pf_ic_rc.ram_empty_i_reg_0 [5]), .I3(\reg_out_i_reg[7]_0 [5]), .I4(\gen_pf_ic_rc.ram_empty_i_reg_0 [4]), .I5(\reg_out_i_reg[7]_0 [4]), .O(\gen_pf_ic_rc.ram_empty_i_i_4_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_5 (.I0(\reg_out_i_reg[7]_0 [0]), .I1(\gen_pf_ic_rc.ram_empty_i_reg_0 [0]), .I2(\gen_pf_ic_rc.ram_empty_i_reg_0 [2]), .I3(\reg_out_i_reg[7]_0 [2]), .I4(\gen_pf_ic_rc.ram_empty_i_reg_0 [1]), .I5(\reg_out_i_reg[7]_0 [1]), .O(\gen_pf_ic_rc.ram_empty_i_i_5_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_6 (.I0(\reg_out_i_reg[7]_0 [3]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [3]), .I2(\gen_pf_ic_rc.ram_empty_i_reg [5]), .I3(\reg_out_i_reg[7]_0 [5]), .I4(\gen_pf_ic_rc.ram_empty_i_reg [4]), .I5(\reg_out_i_reg[7]_0 [4]), .O(\gen_pf_ic_rc.ram_empty_i_i_6_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.ram_empty_i_i_7 (.I0(\reg_out_i_reg[7]_0 [0]), .I1(\gen_pf_ic_rc.ram_empty_i_reg [0]), .I2(\gen_pf_ic_rc.ram_empty_i_reg [2]), .I3(\reg_out_i_reg[7]_0 [2]), .I4(\gen_pf_ic_rc.ram_empty_i_reg [1]), .I5(\reg_out_i_reg[7]_0 [1]), .O(\gen_pf_ic_rc.ram_empty_i_i_7_n_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[0] (.C(rd_clk), .CE(1'b1), .D(D[0]), .Q(\reg_out_i_reg[7]_0 [0]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[1] (.C(rd_clk), .CE(1'b1), .D(D[1]), .Q(\reg_out_i_reg[7]_0 [1]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[2] (.C(rd_clk), .CE(1'b1), .D(D[2]), .Q(\reg_out_i_reg[7]_0 [2]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[3] (.C(rd_clk), .CE(1'b1), .D(D[3]), .Q(\reg_out_i_reg[7]_0 [3]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[4] (.C(rd_clk), .CE(1'b1), .D(D[4]), .Q(\reg_out_i_reg[7]_0 [4]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[5] (.C(rd_clk), .CE(1'b1), .D(D[5]), .Q(\reg_out_i_reg[7]_0 [5]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[6] (.C(rd_clk), .CE(1'b1), .D(D[6]), .Q(\reg_out_i_reg[7]_0 [6]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[7] (.C(rd_clk), .CE(1'b1), .D(D[7]), .Q(\reg_out_i_reg[7]_0 [7]), .R(\reg_out_i_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_vec" *) module axi_chip2chip_64B66B_xpm_fifo_reg_vec__parameterized0 (Q, \reg_out_i_reg[0]_0 , wr_pntr_plus1_pf_carry, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 , \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg , clr_full, wrst_busy, D, wr_clk); output [8:0]Q; output \reg_out_i_reg[0]_0 ; input wr_pntr_plus1_pf_carry; input [8:0]\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 ; input [8:0]\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg ; input clr_full; input wrst_busy; input [8:0]D; input wr_clk; wire [8:0]D; wire [8:0]Q; wire clr_full; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_2_n_0 ; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_3_n_0 ; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0 ; wire [8:0]\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 ; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0 ; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_8_n_0 ; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_9_n_0 ; wire [8:0]\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg ; wire going_full; wire \reg_out_i_reg[0]_0 ; wire wr_clk; wire wr_pntr_plus1_pf_carry; wire wrst_busy; LUT5 #( .INIT(32'h0000FF80)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_1 (.I0(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_2_n_0 ), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_3_n_0 ), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0 ), .I3(going_full), .I4(clr_full), .O(\reg_out_i_reg[0]_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_2 (.I0(Q[0]), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [0]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [2]), .I3(Q[2]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [1]), .I5(Q[1]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_2_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_3 (.I0(Q[6]), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [6]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [8]), .I3(Q[8]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [7]), .I5(Q[7]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_3_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4 (.I0(Q[3]), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [3]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [5]), .I3(Q[5]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [4]), .I5(Q[4]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0 )); LUT4 #( .INIT(16'h8000)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5 (.I0(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0 ), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_8_n_0 ), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_9_n_0 ), .I3(wr_pntr_plus1_pf_carry), .O(going_full)); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7 (.I0(Q[3]), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 [3]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 [5]), .I3(Q[5]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 [4]), .I5(Q[4]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_8 (.I0(Q[6]), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 [6]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 [8]), .I3(Q[8]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 [7]), .I5(Q[7]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_8_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_9 (.I0(Q[0]), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 [0]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 [2]), .I3(Q[2]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 [1]), .I5(Q[1]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_9_n_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[0] (.C(wr_clk), .CE(1'b1), .D(D[0]), .Q(Q[0]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[1] (.C(wr_clk), .CE(1'b1), .D(D[1]), .Q(Q[1]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[2] (.C(wr_clk), .CE(1'b1), .D(D[2]), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[3] (.C(wr_clk), .CE(1'b1), .D(D[3]), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[4] (.C(wr_clk), .CE(1'b1), .D(D[4]), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[5] (.C(wr_clk), .CE(1'b1), .D(D[5]), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[6] (.C(wr_clk), .CE(1'b1), .D(D[6]), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[7] (.C(wr_clk), .CE(1'b1), .D(D[7]), .Q(Q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[8] (.C(wr_clk), .CE(1'b1), .D(D[8]), .Q(Q[8]), .R(wrst_busy)); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_vec" *) module axi_chip2chip_64B66B_xpm_fifo_reg_vec__parameterized0_0 (Q, D, \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8] , DI, S, \reg_out_i_reg[0]_0 , \reg_out_i_reg[8]_0 , rd_clk); output [8:0]Q; output [8:0]D; input [0:0]\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8] ; input [0:0]DI; input [7:0]S; input \reg_out_i_reg[0]_0 ; input [8:0]\reg_out_i_reg[8]_0 ; input rd_clk; wire [8:0]D; wire [0:0]DI; wire [8:0]Q; wire [7:0]S; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[8]_i_2_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_1 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_2 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_3 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_4 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_5 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_6 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_7 ; wire [0:0]\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8] ; wire rd_clk; wire \reg_out_i_reg[0]_0 ; wire [8:0]\reg_out_i_reg[8]_0 ; wire [7:0]\NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]_i_1_CO_UNCONNECTED ; wire [7:1]\NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]_i_1_O_UNCONNECTED ; LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[8]_i_2 (.I0(Q[8]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8] ), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[8]_i_2_n_0 )); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY8 \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1 (.CI(Q[0]), .CI_TOP(1'b0), .CO({\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_1 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_2 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_3 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_4 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_5 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_6 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_7 }), .DI({Q[7:1],DI}), .O(D[7:0]), .S(S)); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY8 \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]_i_1 (.CI(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_0 ), .CI_TOP(1'b0), .CO(\NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]_i_1_CO_UNCONNECTED [7:0]), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .O({\NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]_i_1_O_UNCONNECTED [7:1],D[8]}), .S({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[8]_i_2_n_0 })); FDRE #( .INIT(1'b0)) \reg_out_i_reg[0] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_0 [0]), .Q(Q[0]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[1] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_0 [1]), .Q(Q[1]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[2] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_0 [2]), .Q(Q[2]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[3] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_0 [3]), .Q(Q[3]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[4] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_0 [4]), .Q(Q[4]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[5] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_0 [5]), .Q(Q[5]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[6] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_0 [6]), .Q(Q[6]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[7] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_0 [7]), .Q(Q[7]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[8] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_0 [8]), .Q(Q[8]), .R(\reg_out_i_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_vec" *) module axi_chip2chip_64B66B_xpm_fifo_reg_vec__parameterized0_16 (Q, wrst_busy, D, wr_clk); output [8:0]Q; input wrst_busy; input [8:0]D; input wr_clk; wire [8:0]D; wire [8:0]Q; wire wr_clk; wire wrst_busy; FDRE #( .INIT(1'b0)) \reg_out_i_reg[0] (.C(wr_clk), .CE(1'b1), .D(D[0]), .Q(Q[0]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[1] (.C(wr_clk), .CE(1'b1), .D(D[1]), .Q(Q[1]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[2] (.C(wr_clk), .CE(1'b1), .D(D[2]), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[3] (.C(wr_clk), .CE(1'b1), .D(D[3]), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[4] (.C(wr_clk), .CE(1'b1), .D(D[4]), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[5] (.C(wr_clk), .CE(1'b1), .D(D[5]), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[6] (.C(wr_clk), .CE(1'b1), .D(D[6]), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[7] (.C(wr_clk), .CE(1'b1), .D(D[7]), .Q(Q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[8] (.C(wr_clk), .CE(1'b1), .D(D[8]), .Q(Q[8]), .R(wrst_busy)); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_vec" *) module axi_chip2chip_64B66B_xpm_fifo_reg_vec__parameterized0_18 (D, Q, DI, S, \grdc.rd_data_count_i_reg[8] , \grdc.rd_data_count_i_reg[7] , \grdc.rd_data_count_i_reg[7]_0 , \reg_out_i_reg[8]_0 , \reg_out_i_reg[8]_1 , rd_clk); output [7:0]D; output [8:0]Q; input [1:0]DI; input [6:0]S; input [0:0]\grdc.rd_data_count_i_reg[8] ; input [0:0]\grdc.rd_data_count_i_reg[7] ; input [5:0]\grdc.rd_data_count_i_reg[7]_0 ; input \reg_out_i_reg[8]_0 ; input [8:0]\reg_out_i_reg[8]_1 ; input rd_clk; wire [7:0]D; wire [1:0]DI; wire [8:0]Q; wire [6:0]S; wire \grdc.rd_data_count_i[7]_i_14_n_0 ; wire \grdc.rd_data_count_i[7]_i_2_n_0 ; wire \grdc.rd_data_count_i[7]_i_3_n_0 ; wire \grdc.rd_data_count_i[7]_i_4_n_0 ; wire \grdc.rd_data_count_i[7]_i_5_n_0 ; wire \grdc.rd_data_count_i[7]_i_6_n_0 ; wire [0:0]\grdc.rd_data_count_i_reg[7] ; wire [5:0]\grdc.rd_data_count_i_reg[7]_0 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_0 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_1 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_2 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_3 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_4 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_5 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_6 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_7 ; wire [0:0]\grdc.rd_data_count_i_reg[8] ; wire rd_clk; wire \reg_out_i_reg[8]_0 ; wire [8:0]\reg_out_i_reg[8]_1 ; wire [0:0]\NLW_grdc.rd_data_count_i_reg[7]_i_1_O_UNCONNECTED ; wire [7:0]\NLW_grdc.rd_data_count_i_reg[8]_i_2_CO_UNCONNECTED ; wire [7:1]\NLW_grdc.rd_data_count_i_reg[8]_i_2_O_UNCONNECTED ; LUT5 #( .INIT(32'h718E8E71)) \grdc.rd_data_count_i[7]_i_14 (.I0(Q[1]), .I1(\grdc.rd_data_count_i_reg[7] ), .I2(\grdc.rd_data_count_i_reg[7]_0 [0]), .I3(\grdc.rd_data_count_i_reg[7]_0 [1]), .I4(Q[2]), .O(\grdc.rd_data_count_i[7]_i_14_n_0 )); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_2 (.I0(Q[6]), .I1(\grdc.rd_data_count_i_reg[7]_0 [5]), .O(\grdc.rd_data_count_i[7]_i_2_n_0 )); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_3 (.I0(Q[5]), .I1(\grdc.rd_data_count_i_reg[7]_0 [4]), .O(\grdc.rd_data_count_i[7]_i_3_n_0 )); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_4 (.I0(Q[4]), .I1(\grdc.rd_data_count_i_reg[7]_0 [3]), .O(\grdc.rd_data_count_i[7]_i_4_n_0 )); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_5 (.I0(Q[3]), .I1(\grdc.rd_data_count_i_reg[7]_0 [2]), .O(\grdc.rd_data_count_i[7]_i_5_n_0 )); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_6 (.I0(Q[2]), .I1(\grdc.rd_data_count_i_reg[7]_0 [1]), .O(\grdc.rd_data_count_i[7]_i_6_n_0 )); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY8 \grdc.rd_data_count_i_reg[7]_i_1 (.CI(1'b0), .CI_TOP(1'b0), .CO({\grdc.rd_data_count_i_reg[7]_i_1_n_0 ,\grdc.rd_data_count_i_reg[7]_i_1_n_1 ,\grdc.rd_data_count_i_reg[7]_i_1_n_2 ,\grdc.rd_data_count_i_reg[7]_i_1_n_3 ,\grdc.rd_data_count_i_reg[7]_i_1_n_4 ,\grdc.rd_data_count_i_reg[7]_i_1_n_5 ,\grdc.rd_data_count_i_reg[7]_i_1_n_6 ,\grdc.rd_data_count_i_reg[7]_i_1_n_7 }), .DI({\grdc.rd_data_count_i[7]_i_2_n_0 ,\grdc.rd_data_count_i[7]_i_3_n_0 ,\grdc.rd_data_count_i[7]_i_4_n_0 ,\grdc.rd_data_count_i[7]_i_5_n_0 ,\grdc.rd_data_count_i[7]_i_6_n_0 ,DI,Q[0]}), .O({D[6:0],\NLW_grdc.rd_data_count_i_reg[7]_i_1_O_UNCONNECTED [0]}), .S({S[6:2],\grdc.rd_data_count_i[7]_i_14_n_0 ,S[1:0]})); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY8 \grdc.rd_data_count_i_reg[8]_i_2 (.CI(\grdc.rd_data_count_i_reg[7]_i_1_n_0 ), .CI_TOP(1'b0), .CO(\NLW_grdc.rd_data_count_i_reg[8]_i_2_CO_UNCONNECTED [7:0]), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .O({\NLW_grdc.rd_data_count_i_reg[8]_i_2_O_UNCONNECTED [7:1],D[7]}), .S({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\grdc.rd_data_count_i_reg[8] })); FDRE #( .INIT(1'b0)) \reg_out_i_reg[0] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [0]), .Q(Q[0]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[1] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [1]), .Q(Q[1]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[2] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [2]), .Q(Q[2]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[3] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [3]), .Q(Q[3]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[4] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [4]), .Q(Q[4]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[5] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [5]), .Q(Q[5]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[6] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [6]), .Q(Q[6]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[7] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [7]), .Q(Q[7]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[8] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [8]), .Q(Q[8]), .R(\reg_out_i_reg[8]_0 )); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_vec" *) module axi_chip2chip_64B66B_xpm_fifo_reg_vec__parameterized0_24 (Q, wrst_busy, D, wr_clk); output [8:0]Q; input wrst_busy; input [8:0]D; input wr_clk; wire [8:0]D; wire [8:0]Q; wire wr_clk; wire wrst_busy; FDRE #( .INIT(1'b0)) \reg_out_i_reg[0] (.C(wr_clk), .CE(1'b1), .D(D[0]), .Q(Q[0]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[1] (.C(wr_clk), .CE(1'b1), .D(D[1]), .Q(Q[1]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[2] (.C(wr_clk), .CE(1'b1), .D(D[2]), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[3] (.C(wr_clk), .CE(1'b1), .D(D[3]), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[4] (.C(wr_clk), .CE(1'b1), .D(D[4]), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[5] (.C(wr_clk), .CE(1'b1), .D(D[5]), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[6] (.C(wr_clk), .CE(1'b1), .D(D[6]), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[7] (.C(wr_clk), .CE(1'b1), .D(D[7]), .Q(Q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[8] (.C(wr_clk), .CE(1'b1), .D(D[8]), .Q(Q[8]), .R(wrst_busy)); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_vec" *) module axi_chip2chip_64B66B_xpm_fifo_reg_vec__parameterized0_26 (D, Q, DI, S, \grdc.rd_data_count_i_reg[8] , \grdc.rd_data_count_i_reg[7] , \grdc.rd_data_count_i_reg[7]_0 , \reg_out_i_reg[8]_0 , \reg_out_i_reg[8]_1 , rd_clk); output [7:0]D; output [8:0]Q; input [1:0]DI; input [6:0]S; input [0:0]\grdc.rd_data_count_i_reg[8] ; input [0:0]\grdc.rd_data_count_i_reg[7] ; input [5:0]\grdc.rd_data_count_i_reg[7]_0 ; input \reg_out_i_reg[8]_0 ; input [8:0]\reg_out_i_reg[8]_1 ; input rd_clk; wire [7:0]D; wire [1:0]DI; wire [8:0]Q; wire [6:0]S; wire \grdc.rd_data_count_i[7]_i_14_n_0 ; wire \grdc.rd_data_count_i[7]_i_2_n_0 ; wire \grdc.rd_data_count_i[7]_i_3_n_0 ; wire \grdc.rd_data_count_i[7]_i_4_n_0 ; wire \grdc.rd_data_count_i[7]_i_5_n_0 ; wire \grdc.rd_data_count_i[7]_i_6_n_0 ; wire [0:0]\grdc.rd_data_count_i_reg[7] ; wire [5:0]\grdc.rd_data_count_i_reg[7]_0 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_0 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_1 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_2 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_3 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_4 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_5 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_6 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_7 ; wire [0:0]\grdc.rd_data_count_i_reg[8] ; wire rd_clk; wire \reg_out_i_reg[8]_0 ; wire [8:0]\reg_out_i_reg[8]_1 ; wire [0:0]\NLW_grdc.rd_data_count_i_reg[7]_i_1_O_UNCONNECTED ; wire [7:0]\NLW_grdc.rd_data_count_i_reg[8]_i_2_CO_UNCONNECTED ; wire [7:1]\NLW_grdc.rd_data_count_i_reg[8]_i_2_O_UNCONNECTED ; LUT5 #( .INIT(32'h718E8E71)) \grdc.rd_data_count_i[7]_i_14 (.I0(Q[1]), .I1(\grdc.rd_data_count_i_reg[7] ), .I2(\grdc.rd_data_count_i_reg[7]_0 [0]), .I3(\grdc.rd_data_count_i_reg[7]_0 [1]), .I4(Q[2]), .O(\grdc.rd_data_count_i[7]_i_14_n_0 )); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_2 (.I0(Q[6]), .I1(\grdc.rd_data_count_i_reg[7]_0 [5]), .O(\grdc.rd_data_count_i[7]_i_2_n_0 )); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_3 (.I0(Q[5]), .I1(\grdc.rd_data_count_i_reg[7]_0 [4]), .O(\grdc.rd_data_count_i[7]_i_3_n_0 )); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_4 (.I0(Q[4]), .I1(\grdc.rd_data_count_i_reg[7]_0 [3]), .O(\grdc.rd_data_count_i[7]_i_4_n_0 )); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_5 (.I0(Q[3]), .I1(\grdc.rd_data_count_i_reg[7]_0 [2]), .O(\grdc.rd_data_count_i[7]_i_5_n_0 )); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_6 (.I0(Q[2]), .I1(\grdc.rd_data_count_i_reg[7]_0 [1]), .O(\grdc.rd_data_count_i[7]_i_6_n_0 )); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY8 \grdc.rd_data_count_i_reg[7]_i_1 (.CI(1'b0), .CI_TOP(1'b0), .CO({\grdc.rd_data_count_i_reg[7]_i_1_n_0 ,\grdc.rd_data_count_i_reg[7]_i_1_n_1 ,\grdc.rd_data_count_i_reg[7]_i_1_n_2 ,\grdc.rd_data_count_i_reg[7]_i_1_n_3 ,\grdc.rd_data_count_i_reg[7]_i_1_n_4 ,\grdc.rd_data_count_i_reg[7]_i_1_n_5 ,\grdc.rd_data_count_i_reg[7]_i_1_n_6 ,\grdc.rd_data_count_i_reg[7]_i_1_n_7 }), .DI({\grdc.rd_data_count_i[7]_i_2_n_0 ,\grdc.rd_data_count_i[7]_i_3_n_0 ,\grdc.rd_data_count_i[7]_i_4_n_0 ,\grdc.rd_data_count_i[7]_i_5_n_0 ,\grdc.rd_data_count_i[7]_i_6_n_0 ,DI,Q[0]}), .O({D[6:0],\NLW_grdc.rd_data_count_i_reg[7]_i_1_O_UNCONNECTED [0]}), .S({S[6:2],\grdc.rd_data_count_i[7]_i_14_n_0 ,S[1:0]})); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY8 \grdc.rd_data_count_i_reg[8]_i_2 (.CI(\grdc.rd_data_count_i_reg[7]_i_1_n_0 ), .CI_TOP(1'b0), .CO(\NLW_grdc.rd_data_count_i_reg[8]_i_2_CO_UNCONNECTED [7:0]), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .O({\NLW_grdc.rd_data_count_i_reg[8]_i_2_O_UNCONNECTED [7:1],D[7]}), .S({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\grdc.rd_data_count_i_reg[8] })); FDRE #( .INIT(1'b0)) \reg_out_i_reg[0] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [0]), .Q(Q[0]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[1] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [1]), .Q(Q[1]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[2] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [2]), .Q(Q[2]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[3] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [3]), .Q(Q[3]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[4] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [4]), .Q(Q[4]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[5] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [5]), .Q(Q[5]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[6] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [6]), .Q(Q[6]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[7] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [7]), .Q(Q[7]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[8] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [8]), .Q(Q[8]), .R(\reg_out_i_reg[8]_0 )); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_vec" *) module axi_chip2chip_64B66B_xpm_fifo_reg_vec__parameterized0_35 (Q, wrst_busy, D, wr_clk); output [8:0]Q; input wrst_busy; input [8:0]D; input wr_clk; wire [8:0]D; wire [8:0]Q; wire wr_clk; wire wrst_busy; FDRE #( .INIT(1'b0)) \reg_out_i_reg[0] (.C(wr_clk), .CE(1'b1), .D(D[0]), .Q(Q[0]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[1] (.C(wr_clk), .CE(1'b1), .D(D[1]), .Q(Q[1]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[2] (.C(wr_clk), .CE(1'b1), .D(D[2]), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[3] (.C(wr_clk), .CE(1'b1), .D(D[3]), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[4] (.C(wr_clk), .CE(1'b1), .D(D[4]), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[5] (.C(wr_clk), .CE(1'b1), .D(D[5]), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[6] (.C(wr_clk), .CE(1'b1), .D(D[6]), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[7] (.C(wr_clk), .CE(1'b1), .D(D[7]), .Q(Q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[8] (.C(wr_clk), .CE(1'b1), .D(D[8]), .Q(Q[8]), .R(wrst_busy)); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_vec" *) module axi_chip2chip_64B66B_xpm_fifo_reg_vec__parameterized0_37 (D, Q, DI, S, \grdc.rd_data_count_i_reg[8] , \grdc.rd_data_count_i_reg[7] , \grdc.rd_data_count_i_reg[7]_0 , \reg_out_i_reg[8]_0 , \reg_out_i_reg[8]_1 , rd_clk); output [7:0]D; output [8:0]Q; input [1:0]DI; input [6:0]S; input [0:0]\grdc.rd_data_count_i_reg[8] ; input [0:0]\grdc.rd_data_count_i_reg[7] ; input [5:0]\grdc.rd_data_count_i_reg[7]_0 ; input \reg_out_i_reg[8]_0 ; input [8:0]\reg_out_i_reg[8]_1 ; input rd_clk; wire [7:0]D; wire [1:0]DI; wire [8:0]Q; wire [6:0]S; wire \grdc.rd_data_count_i[7]_i_14_n_0 ; wire \grdc.rd_data_count_i[7]_i_2_n_0 ; wire \grdc.rd_data_count_i[7]_i_3_n_0 ; wire \grdc.rd_data_count_i[7]_i_4_n_0 ; wire \grdc.rd_data_count_i[7]_i_5_n_0 ; wire \grdc.rd_data_count_i[7]_i_6_n_0 ; wire [0:0]\grdc.rd_data_count_i_reg[7] ; wire [5:0]\grdc.rd_data_count_i_reg[7]_0 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_0 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_1 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_2 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_3 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_4 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_5 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_6 ; wire \grdc.rd_data_count_i_reg[7]_i_1_n_7 ; wire [0:0]\grdc.rd_data_count_i_reg[8] ; wire rd_clk; wire \reg_out_i_reg[8]_0 ; wire [8:0]\reg_out_i_reg[8]_1 ; wire [0:0]\NLW_grdc.rd_data_count_i_reg[7]_i_1_O_UNCONNECTED ; wire [7:0]\NLW_grdc.rd_data_count_i_reg[8]_i_2_CO_UNCONNECTED ; wire [7:1]\NLW_grdc.rd_data_count_i_reg[8]_i_2_O_UNCONNECTED ; LUT5 #( .INIT(32'h718E8E71)) \grdc.rd_data_count_i[7]_i_14 (.I0(Q[1]), .I1(\grdc.rd_data_count_i_reg[7] ), .I2(\grdc.rd_data_count_i_reg[7]_0 [0]), .I3(\grdc.rd_data_count_i_reg[7]_0 [1]), .I4(Q[2]), .O(\grdc.rd_data_count_i[7]_i_14_n_0 )); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_2 (.I0(Q[6]), .I1(\grdc.rd_data_count_i_reg[7]_0 [5]), .O(\grdc.rd_data_count_i[7]_i_2_n_0 )); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_3 (.I0(Q[5]), .I1(\grdc.rd_data_count_i_reg[7]_0 [4]), .O(\grdc.rd_data_count_i[7]_i_3_n_0 )); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_4 (.I0(Q[4]), .I1(\grdc.rd_data_count_i_reg[7]_0 [3]), .O(\grdc.rd_data_count_i[7]_i_4_n_0 )); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_5 (.I0(Q[3]), .I1(\grdc.rd_data_count_i_reg[7]_0 [2]), .O(\grdc.rd_data_count_i[7]_i_5_n_0 )); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_6 (.I0(Q[2]), .I1(\grdc.rd_data_count_i_reg[7]_0 [1]), .O(\grdc.rd_data_count_i[7]_i_6_n_0 )); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY8 \grdc.rd_data_count_i_reg[7]_i_1 (.CI(1'b0), .CI_TOP(1'b0), .CO({\grdc.rd_data_count_i_reg[7]_i_1_n_0 ,\grdc.rd_data_count_i_reg[7]_i_1_n_1 ,\grdc.rd_data_count_i_reg[7]_i_1_n_2 ,\grdc.rd_data_count_i_reg[7]_i_1_n_3 ,\grdc.rd_data_count_i_reg[7]_i_1_n_4 ,\grdc.rd_data_count_i_reg[7]_i_1_n_5 ,\grdc.rd_data_count_i_reg[7]_i_1_n_6 ,\grdc.rd_data_count_i_reg[7]_i_1_n_7 }), .DI({\grdc.rd_data_count_i[7]_i_2_n_0 ,\grdc.rd_data_count_i[7]_i_3_n_0 ,\grdc.rd_data_count_i[7]_i_4_n_0 ,\grdc.rd_data_count_i[7]_i_5_n_0 ,\grdc.rd_data_count_i[7]_i_6_n_0 ,DI,Q[0]}), .O({D[6:0],\NLW_grdc.rd_data_count_i_reg[7]_i_1_O_UNCONNECTED [0]}), .S({S[6:2],\grdc.rd_data_count_i[7]_i_14_n_0 ,S[1:0]})); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY8 \grdc.rd_data_count_i_reg[8]_i_2 (.CI(\grdc.rd_data_count_i_reg[7]_i_1_n_0 ), .CI_TOP(1'b0), .CO(\NLW_grdc.rd_data_count_i_reg[8]_i_2_CO_UNCONNECTED [7:0]), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .O({\NLW_grdc.rd_data_count_i_reg[8]_i_2_O_UNCONNECTED [7:1],D[7]}), .S({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\grdc.rd_data_count_i_reg[8] })); FDRE #( .INIT(1'b0)) \reg_out_i_reg[0] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [0]), .Q(Q[0]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[1] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [1]), .Q(Q[1]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[2] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [2]), .Q(Q[2]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[3] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [3]), .Q(Q[3]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[4] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [4]), .Q(Q[4]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[5] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [5]), .Q(Q[5]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[6] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [6]), .Q(Q[6]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[7] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [7]), .Q(Q[7]), .R(\reg_out_i_reg[8]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[8] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_1 [8]), .Q(Q[8]), .R(\reg_out_i_reg[8]_0 )); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_vec" *) module axi_chip2chip_64B66B_xpm_fifo_reg_vec__parameterized0_4 (Q, \reg_out_i_reg[0]_0 , wr_pntr_plus1_pf_carry, \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 , \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg , clr_full, wrst_busy, D, wr_clk); output [8:0]Q; output \reg_out_i_reg[0]_0 ; input wr_pntr_plus1_pf_carry; input [8:0]\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 ; input [8:0]\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg ; input clr_full; input wrst_busy; input [8:0]D; input wr_clk; wire [8:0]D; wire [8:0]Q; wire clr_full; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_2_n_0 ; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_3_n_0 ; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0 ; wire [8:0]\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 ; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0 ; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_8_n_0 ; wire \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_9_n_0 ; wire [8:0]\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg ; wire going_full; wire \reg_out_i_reg[0]_0 ; wire wr_clk; wire wr_pntr_plus1_pf_carry; wire wrst_busy; LUT5 #( .INIT(32'h0000FF80)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_1 (.I0(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_2_n_0 ), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_3_n_0 ), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0 ), .I3(going_full), .I4(clr_full), .O(\reg_out_i_reg[0]_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_2 (.I0(Q[0]), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [0]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [2]), .I3(Q[2]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [1]), .I5(Q[1]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_2_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_3 (.I0(Q[6]), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [6]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [8]), .I3(Q[8]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [7]), .I5(Q[7]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_3_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4 (.I0(Q[3]), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [3]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [5]), .I3(Q[5]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_reg [4]), .I5(Q[4]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_4_n_0 )); LUT4 #( .INIT(16'h8000)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5 (.I0(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0 ), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_8_n_0 ), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_9_n_0 ), .I3(wr_pntr_plus1_pf_carry), .O(going_full)); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7 (.I0(Q[3]), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 [3]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 [5]), .I3(Q[5]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 [4]), .I5(Q[4]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_7_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_8 (.I0(Q[6]), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 [6]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 [8]), .I3(Q[8]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 [7]), .I5(Q[7]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_8_n_0 )); LUT6 #( .INIT(64'h9009000000009009)) \gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_9 (.I0(Q[0]), .I1(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 [0]), .I2(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 [2]), .I3(Q[2]), .I4(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_5_0 [1]), .I5(Q[1]), .O(\gen_pf_ic_rc.gen_full_rst_val.ram_full_i_i_9_n_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[0] (.C(wr_clk), .CE(1'b1), .D(D[0]), .Q(Q[0]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[1] (.C(wr_clk), .CE(1'b1), .D(D[1]), .Q(Q[1]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[2] (.C(wr_clk), .CE(1'b1), .D(D[2]), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[3] (.C(wr_clk), .CE(1'b1), .D(D[3]), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[4] (.C(wr_clk), .CE(1'b1), .D(D[4]), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[5] (.C(wr_clk), .CE(1'b1), .D(D[5]), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[6] (.C(wr_clk), .CE(1'b1), .D(D[6]), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[7] (.C(wr_clk), .CE(1'b1), .D(D[7]), .Q(Q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[8] (.C(wr_clk), .CE(1'b1), .D(D[8]), .Q(Q[8]), .R(wrst_busy)); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_vec" *) module axi_chip2chip_64B66B_xpm_fifo_reg_vec__parameterized0_6 (Q, D, \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8] , DI, S, \reg_out_i_reg[0]_0 , \reg_out_i_reg[8]_0 , rd_clk); output [8:0]Q; output [8:0]D; input [0:0]\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8] ; input [0:0]DI; input [7:0]S; input \reg_out_i_reg[0]_0 ; input [8:0]\reg_out_i_reg[8]_0 ; input rd_clk; wire [8:0]D; wire [0:0]DI; wire [8:0]Q; wire [7:0]S; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[8]_i_2_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_0 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_1 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_2 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_3 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_4 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_5 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_6 ; wire \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_7 ; wire [0:0]\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8] ; wire rd_clk; wire \reg_out_i_reg[0]_0 ; wire [8:0]\reg_out_i_reg[8]_0 ; wire [7:0]\NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]_i_1_CO_UNCONNECTED ; wire [7:1]\NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]_i_1_O_UNCONNECTED ; LUT2 #( .INIT(4'h9)) \gen_pf_ic_rc.gpe_ic.diff_pntr_pe[8]_i_2 (.I0(Q[8]), .I1(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8] ), .O(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[8]_i_2_n_0 )); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY8 \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1 (.CI(Q[0]), .CI_TOP(1'b0), .CO({\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_0 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_1 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_2 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_3 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_4 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_5 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_6 ,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_7 }), .DI({Q[7:1],DI}), .O(D[7:0]), .S(S)); (* ADDER_THRESHOLD = "35" *) (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) CARRY8 \gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]_i_1 (.CI(\gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[7]_i_1_n_0 ), .CI_TOP(1'b0), .CO(\NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]_i_1_CO_UNCONNECTED [7:0]), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .O({\NLW_gen_pf_ic_rc.gpe_ic.diff_pntr_pe_reg[8]_i_1_O_UNCONNECTED [7:1],D[8]}), .S({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,\gen_pf_ic_rc.gpe_ic.diff_pntr_pe[8]_i_2_n_0 })); FDRE #( .INIT(1'b0)) \reg_out_i_reg[0] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_0 [0]), .Q(Q[0]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[1] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_0 [1]), .Q(Q[1]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[2] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_0 [2]), .Q(Q[2]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[3] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_0 [3]), .Q(Q[3]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[4] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_0 [4]), .Q(Q[4]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[5] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_0 [5]), .Q(Q[5]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[6] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_0 [6]), .Q(Q[6]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[7] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_0 [7]), .Q(Q[7]), .R(\reg_out_i_reg[0]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[8] (.C(rd_clk), .CE(1'b1), .D(\reg_out_i_reg[8]_0 [8]), .Q(Q[8]), .R(\reg_out_i_reg[0]_0 )); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_vec" *) module axi_chip2chip_64B66B_xpm_fifo_reg_vec__parameterized1 (Q, wrst_busy, D, wr_clk); output [9:0]Q; input wrst_busy; input [9:0]D; input wr_clk; wire [9:0]D; wire [9:0]Q; wire wr_clk; wire wrst_busy; FDRE #( .INIT(1'b0)) \reg_out_i_reg[0] (.C(wr_clk), .CE(1'b1), .D(D[0]), .Q(Q[0]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[1] (.C(wr_clk), .CE(1'b1), .D(D[1]), .Q(Q[1]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[2] (.C(wr_clk), .CE(1'b1), .D(D[2]), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[3] (.C(wr_clk), .CE(1'b1), .D(D[3]), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[4] (.C(wr_clk), .CE(1'b1), .D(D[4]), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[5] (.C(wr_clk), .CE(1'b1), .D(D[5]), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[6] (.C(wr_clk), .CE(1'b1), .D(D[6]), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[7] (.C(wr_clk), .CE(1'b1), .D(D[7]), .Q(Q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[8] (.C(wr_clk), .CE(1'b1), .D(D[8]), .Q(Q[8]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[9] (.C(wr_clk), .CE(1'b1), .D(D[9]), .Q(Q[9]), .R(wrst_busy)); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_vec" *) module axi_chip2chip_64B66B_xpm_fifo_reg_vec__parameterized1_1 (DI, Q, \reg_out_i_reg[7]_0 , S, \grdc.rd_data_count_i_reg[7] , \grdc.rd_data_count_i_reg[9] , \reg_out_i_reg[9]_0 , D, rd_clk); output [5:0]DI; output [8:0]Q; output [0:0]\reg_out_i_reg[7]_0 ; output [0:0]S; input [0:0]\grdc.rd_data_count_i_reg[7] ; input [8:0]\grdc.rd_data_count_i_reg[9] ; input \reg_out_i_reg[9]_0 ; input [9:0]D; input rd_clk; wire [9:0]D; wire [5:0]DI; wire [8:0]Q; wire [0:0]S; wire [0:0]\grdc.rd_data_count_i_reg[7] ; wire [8:0]\grdc.rd_data_count_i_reg[9] ; wire rd_clk; wire [0:0]\reg_out_i_reg[7]_0 ; wire \reg_out_i_reg[9]_0 ; wire \reg_out_i_reg_n_0_[9] ; LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_2 (.I0(Q[6]), .I1(\grdc.rd_data_count_i_reg[9] [5]), .O(DI[5])); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_3 (.I0(Q[5]), .I1(\grdc.rd_data_count_i_reg[9] [4]), .O(DI[4])); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_4 (.I0(Q[4]), .I1(\grdc.rd_data_count_i_reg[9] [3]), .O(DI[3])); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_5 (.I0(Q[3]), .I1(\grdc.rd_data_count_i_reg[9] [2]), .O(DI[2])); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_6 (.I0(Q[2]), .I1(\grdc.rd_data_count_i_reg[9] [1]), .O(DI[1])); LUT3 #( .INIT(8'h8E)) \grdc.rd_data_count_i[7]_i_7 (.I0(Q[1]), .I1(\grdc.rd_data_count_i_reg[7] ), .I2(\grdc.rd_data_count_i_reg[9] [0]), .O(DI[0])); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[9]_i_3 (.I0(Q[7]), .I1(\grdc.rd_data_count_i_reg[9] [6]), .O(\reg_out_i_reg[7]_0 )); LUT4 #( .INIT(16'hD22D)) \grdc.rd_data_count_i[9]_i_4 (.I0(Q[8]), .I1(\grdc.rd_data_count_i_reg[9] [7]), .I2(\grdc.rd_data_count_i_reg[9] [8]), .I3(\reg_out_i_reg_n_0_[9] ), .O(S)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[0] (.C(rd_clk), .CE(1'b1), .D(D[0]), .Q(Q[0]), .R(\reg_out_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[1] (.C(rd_clk), .CE(1'b1), .D(D[1]), .Q(Q[1]), .R(\reg_out_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[2] (.C(rd_clk), .CE(1'b1), .D(D[2]), .Q(Q[2]), .R(\reg_out_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[3] (.C(rd_clk), .CE(1'b1), .D(D[3]), .Q(Q[3]), .R(\reg_out_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[4] (.C(rd_clk), .CE(1'b1), .D(D[4]), .Q(Q[4]), .R(\reg_out_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[5] (.C(rd_clk), .CE(1'b1), .D(D[5]), .Q(Q[5]), .R(\reg_out_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[6] (.C(rd_clk), .CE(1'b1), .D(D[6]), .Q(Q[6]), .R(\reg_out_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[7] (.C(rd_clk), .CE(1'b1), .D(D[7]), .Q(Q[7]), .R(\reg_out_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[8] (.C(rd_clk), .CE(1'b1), .D(D[8]), .Q(Q[8]), .R(\reg_out_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[9] (.C(rd_clk), .CE(1'b1), .D(D[9]), .Q(\reg_out_i_reg_n_0_[9] ), .R(\reg_out_i_reg[9]_0 )); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_vec" *) module axi_chip2chip_64B66B_xpm_fifo_reg_vec__parameterized1_5 (Q, wrst_busy, D, wr_clk); output [9:0]Q; input wrst_busy; input [9:0]D; input wr_clk; wire [9:0]D; wire [9:0]Q; wire wr_clk; wire wrst_busy; FDRE #( .INIT(1'b0)) \reg_out_i_reg[0] (.C(wr_clk), .CE(1'b1), .D(D[0]), .Q(Q[0]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[1] (.C(wr_clk), .CE(1'b1), .D(D[1]), .Q(Q[1]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[2] (.C(wr_clk), .CE(1'b1), .D(D[2]), .Q(Q[2]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[3] (.C(wr_clk), .CE(1'b1), .D(D[3]), .Q(Q[3]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[4] (.C(wr_clk), .CE(1'b1), .D(D[4]), .Q(Q[4]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[5] (.C(wr_clk), .CE(1'b1), .D(D[5]), .Q(Q[5]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[6] (.C(wr_clk), .CE(1'b1), .D(D[6]), .Q(Q[6]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[7] (.C(wr_clk), .CE(1'b1), .D(D[7]), .Q(Q[7]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[8] (.C(wr_clk), .CE(1'b1), .D(D[8]), .Q(Q[8]), .R(wrst_busy)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[9] (.C(wr_clk), .CE(1'b1), .D(D[9]), .Q(Q[9]), .R(wrst_busy)); endmodule (* ORIG_REF_NAME = "xpm_fifo_reg_vec" *) module axi_chip2chip_64B66B_xpm_fifo_reg_vec__parameterized1_7 (DI, Q, \reg_out_i_reg[7]_0 , S, \grdc.rd_data_count_i_reg[7] , \grdc.rd_data_count_i_reg[9] , \reg_out_i_reg[9]_0 , D, rd_clk); output [5:0]DI; output [8:0]Q; output [0:0]\reg_out_i_reg[7]_0 ; output [0:0]S; input [0:0]\grdc.rd_data_count_i_reg[7] ; input [8:0]\grdc.rd_data_count_i_reg[9] ; input \reg_out_i_reg[9]_0 ; input [9:0]D; input rd_clk; wire [9:0]D; wire [5:0]DI; wire [8:0]Q; wire [0:0]S; wire [0:0]\grdc.rd_data_count_i_reg[7] ; wire [8:0]\grdc.rd_data_count_i_reg[9] ; wire rd_clk; wire [0:0]\reg_out_i_reg[7]_0 ; wire \reg_out_i_reg[9]_0 ; wire \reg_out_i_reg_n_0_[9] ; LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_2 (.I0(Q[6]), .I1(\grdc.rd_data_count_i_reg[9] [5]), .O(DI[5])); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_3 (.I0(Q[5]), .I1(\grdc.rd_data_count_i_reg[9] [4]), .O(DI[4])); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_4 (.I0(Q[4]), .I1(\grdc.rd_data_count_i_reg[9] [3]), .O(DI[3])); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_5 (.I0(Q[3]), .I1(\grdc.rd_data_count_i_reg[9] [2]), .O(DI[2])); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[7]_i_6 (.I0(Q[2]), .I1(\grdc.rd_data_count_i_reg[9] [1]), .O(DI[1])); LUT3 #( .INIT(8'h8E)) \grdc.rd_data_count_i[7]_i_7 (.I0(Q[1]), .I1(\grdc.rd_data_count_i_reg[7] ), .I2(\grdc.rd_data_count_i_reg[9] [0]), .O(DI[0])); LUT2 #( .INIT(4'h2)) \grdc.rd_data_count_i[9]_i_3 (.I0(Q[7]), .I1(\grdc.rd_data_count_i_reg[9] [6]), .O(\reg_out_i_reg[7]_0 )); LUT4 #( .INIT(16'hD22D)) \grdc.rd_data_count_i[9]_i_4 (.I0(Q[8]), .I1(\grdc.rd_data_count_i_reg[9] [7]), .I2(\grdc.rd_data_count_i_reg[9] [8]), .I3(\reg_out_i_reg_n_0_[9] ), .O(S)); FDRE #( .INIT(1'b0)) \reg_out_i_reg[0] (.C(rd_clk), .CE(1'b1), .D(D[0]), .Q(Q[0]), .R(\reg_out_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[1] (.C(rd_clk), .CE(1'b1), .D(D[1]), .Q(Q[1]), .R(\reg_out_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[2] (.C(rd_clk), .CE(1'b1), .D(D[2]), .Q(Q[2]), .R(\reg_out_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[3] (.C(rd_clk), .CE(1'b1), .D(D[3]), .Q(Q[3]), .R(\reg_out_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[4] (.C(rd_clk), .CE(1'b1), .D(D[4]), .Q(Q[4]), .R(\reg_out_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[5] (.C(rd_clk), .CE(1'b1), .D(D[5]), .Q(Q[5]), .R(\reg_out_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[6] (.C(rd_clk), .CE(1'b1), .D(D[6]), .Q(Q[6]), .R(\reg_out_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[7] (.C(rd_clk), .CE(1'b1), .D(D[7]), .Q(Q[7]), .R(\reg_out_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[8] (.C(rd_clk), .CE(1'b1), .D(D[8]), .Q(Q[8]), .R(\reg_out_i_reg[9]_0 )); FDRE #( .INIT(1'b0)) \reg_out_i_reg[9] (.C(rd_clk), .CE(1'b1), .D(D[9]), .Q(\reg_out_i_reg_n_0_[9] ), .R(\reg_out_i_reg[9]_0 )); endmodule (* ORIG_REF_NAME = "xpm_fifo_rst" *) module axi_chip2chip_64B66B_xpm_fifo_rst (\gen_rst_ic.fifo_rd_rst_ic_reg_0 , wrst_busy, wr_pntr_plus1_pf_carry, wr_rst_busy, SR, underflow_i0, \gen_rst_ic.fifo_rd_rst_ic_reg_1 , rd_clk, wr_clk, rst, wr_en, \count_value_i_reg[7] , rst_d1, Q, \guf.underflow_i_reg , rd_en, ram_empty_i); output \gen_rst_ic.fifo_rd_rst_ic_reg_0 ; output wrst_busy; output wr_pntr_plus1_pf_carry; output wr_rst_busy; output [0:0]SR; output underflow_i0; output [0:0]\gen_rst_ic.fifo_rd_rst_ic_reg_1 ; input rd_clk; input wr_clk; input rst; input wr_en; input \count_value_i_reg[7] ; input rst_d1; input [1:0]Q; input \guf.underflow_i_reg ; input rd_en; input ram_empty_i; wire \/i__n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0 ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ; wire \FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0 ; wire [1:0]Q; wire [0:0]SR; wire \__0/i__n_0 ; wire \count_value_i_reg[7] ; (* RTL_KEEP = "yes" *) wire [1:0]\gen_rst_ic.curr_rrst_state ; wire \gen_rst_ic.fifo_rd_rst_i0 ; wire \gen_rst_ic.fifo_rd_rst_ic_reg_0 ; wire [0:0]\gen_rst_ic.fifo_rd_rst_ic_reg_1 ; wire \gen_rst_ic.fifo_rd_rst_wr_i ; wire \gen_rst_ic.fifo_wr_rst_ic ; wire \gen_rst_ic.fifo_wr_rst_ic_i_1_n_0 ; wire \gen_rst_ic.fifo_wr_rst_ic_i_3_n_0 ; wire \gen_rst_ic.fifo_wr_rst_rd ; wire \gen_rst_ic.rst_seq_reentered_i_1_n_0 ; wire \gen_rst_ic.rst_seq_reentered_i_2_n_0 ; wire \gen_rst_ic.rst_seq_reentered_reg_n_0 ; wire \gen_rst_ic.wr_rst_busy_ic_i_1_n_0 ; wire \gen_rst_ic.wr_rst_busy_ic_i_2_n_0 ; wire \guf.underflow_i_reg ; wire p_0_in; wire \power_on_rst_reg_n_0_[0] ; wire ram_empty_i; wire rd_clk; wire rd_en; wire rst; wire rst_d1; wire rst_i__0; wire underflow_i0; wire wr_clk; wire wr_en; wire wr_pntr_plus1_pf_carry; wire wr_rst_busy; wire wrst_busy; LUT5 #( .INIT(32'h00010116)) \/i_ (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .O(\/i__n_0 )); LUT6 #( .INIT(64'h03030200FFFFFFFF)) \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I1(p_0_in), .I2(rst), .I3(\gen_rst_ic.rst_seq_reentered_reg_n_0 ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I5(\/i__n_0 ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFEFEFEEE)) \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0 ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I3(rst), .I4(p_0_in), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0 )); LUT6 #( .INIT(64'hFFF0EEE0FFFFEEE0)) \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I2(rst), .I3(p_0_in), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I5(\gen_rst_ic.fifo_rd_rst_wr_i ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0 )); LUT5 #( .INIT(32'h000C0008)) \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I1(\gen_rst_ic.fifo_rd_rst_wr_i ), .I2(rst), .I3(p_0_in), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0 )); LUT4 #( .INIT(16'h0004)) \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1 (.I0(\gen_rst_ic.fifo_rd_rst_wr_i ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I2(rst), .I3(p_0_in), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1 (.I0(\/i__n_0 ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); LUT4 #( .INIT(16'h0002)) \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I1(p_0_in), .I2(rst), .I3(\gen_rst_ic.rst_seq_reentered_reg_n_0 ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0 )); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b1)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[0] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .R(1'b0)); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[1] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[2] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[3] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[4] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); LUT2 #( .INIT(4'h6)) \FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1 (.I0(\gen_rst_ic.curr_rrst_state [0]), .I1(\gen_rst_ic.curr_rrst_state [1]), .O(\FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0 )); (* FSM_ENCODED_STATES = "iSTATE:00,iSTATE0:01,iSTATE1:10,iSTATE2:11" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[0] (.C(rd_clk), .CE(1'b1), .D(\__0/i__n_0 ), .Q(\gen_rst_ic.curr_rrst_state [0]), .R(1'b0)); (* FSM_ENCODED_STATES = "iSTATE:00,iSTATE0:01,iSTATE1:10,iSTATE2:11" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[1] (.C(rd_clk), .CE(1'b1), .D(\FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0 ), .Q(\gen_rst_ic.curr_rrst_state [1]), .R(1'b0)); LUT3 #( .INIT(8'h06)) \__0/i_ (.I0(\gen_rst_ic.fifo_wr_rst_rd ), .I1(\gen_rst_ic.curr_rrst_state [1]), .I2(\gen_rst_ic.curr_rrst_state [0]), .O(\__0/i__n_0 )); (* SOFT_HLUTNM = "soft_lutpair156" *) LUT4 #( .INIT(16'hAAAE)) \count_value_i[1]_i_1__4 (.I0(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ), .I1(ram_empty_i), .I2(Q[1]), .I3(Q[0]), .O(\gen_rst_ic.fifo_rd_rst_ic_reg_1 )); LUT3 #( .INIT(8'h3E)) \gen_rst_ic.fifo_rd_rst_ic_i_1 (.I0(\gen_rst_ic.fifo_wr_rst_rd ), .I1(\gen_rst_ic.curr_rrst_state [1]), .I2(\gen_rst_ic.curr_rrst_state [0]), .O(\gen_rst_ic.fifo_rd_rst_i0 )); FDRE #( .INIT(1'b0)) \gen_rst_ic.fifo_rd_rst_ic_reg (.C(rd_clk), .CE(1'b1), .D(\gen_rst_ic.fifo_rd_rst_i0 ), .Q(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ), .R(1'b0)); LUT6 #( .INIT(64'hFFEAFFFFFFEA0000)) \gen_rst_ic.fifo_wr_rst_ic_i_1 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I2(rst_i__0), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I4(\gen_rst_ic.fifo_wr_rst_ic_i_3_n_0 ), .I5(\gen_rst_ic.fifo_wr_rst_ic ), .O(\gen_rst_ic.fifo_wr_rst_ic_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair157" *) LUT2 #( .INIT(4'hE)) \gen_rst_ic.fifo_wr_rst_ic_i_2 (.I0(p_0_in), .I1(rst), .O(rst_i__0)); LUT5 #( .INIT(32'h00010116)) \gen_rst_ic.fifo_wr_rst_ic_i_3 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .O(\gen_rst_ic.fifo_wr_rst_ic_i_3_n_0 )); FDRE #( .INIT(1'b0)) \gen_rst_ic.fifo_wr_rst_ic_reg (.C(wr_clk), .CE(1'b1), .D(\gen_rst_ic.fifo_wr_rst_ic_i_1_n_0 ), .Q(\gen_rst_ic.fifo_wr_rst_ic ), .R(1'b0)); (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "3" *) (* INIT = "0" *) (* INIT_SYNC_FF = "1" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *) (* XPM_CDC = "SYNC_RST" *) (* XPM_MODULE = "TRUE" *) axi_chip2chip_64B66B_xpm_cdc_sync_rst \gen_rst_ic.rrst_wr_inst (.dest_clk(wr_clk), .dest_rst(\gen_rst_ic.fifo_rd_rst_wr_i ), .src_rst(\gen_rst_ic.fifo_rd_rst_ic_reg_0 )); (* SOFT_HLUTNM = "soft_lutpair157" *) LUT3 #( .INIT(8'h02)) \gen_rst_ic.rst_seq_reentered_i_1 (.I0(\gen_rst_ic.rst_seq_reentered_i_2_n_0 ), .I1(rst), .I2(p_0_in), .O(\gen_rst_ic.rst_seq_reentered_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF00010000)) \gen_rst_ic.rst_seq_reentered_i_2 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .I5(\gen_rst_ic.rst_seq_reentered_reg_n_0 ), .O(\gen_rst_ic.rst_seq_reentered_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_rst_ic.rst_seq_reentered_reg (.C(wr_clk), .CE(1'b1), .D(\gen_rst_ic.rst_seq_reentered_i_1_n_0 ), .Q(\gen_rst_ic.rst_seq_reentered_reg_n_0 ), .R(1'b0)); LUT5 #( .INIT(32'hEFFFEF00)) \gen_rst_ic.wr_rst_busy_ic_i_1 (.I0(rst), .I1(p_0_in), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I3(\gen_rst_ic.wr_rst_busy_ic_i_2_n_0 ), .I4(wrst_busy), .O(\gen_rst_ic.wr_rst_busy_ic_i_1_n_0 )); LUT5 #( .INIT(32'h00000116)) \gen_rst_ic.wr_rst_busy_ic_i_2 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .O(\gen_rst_ic.wr_rst_busy_ic_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_rst_ic.wr_rst_busy_ic_reg (.C(wr_clk), .CE(1'b1), .D(\gen_rst_ic.wr_rst_busy_ic_i_1_n_0 ), .Q(wrst_busy), .R(1'b0)); (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "3" *) (* INIT = "0" *) (* INIT_SYNC_FF = "1" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *) (* XPM_CDC = "SYNC_RST" *) (* XPM_MODULE = "TRUE" *) axi_chip2chip_64B66B_xpm_cdc_sync_rst__18 \gen_rst_ic.wrst_rd_inst (.dest_clk(rd_clk), .dest_rst(\gen_rst_ic.fifo_wr_rst_rd ), .src_rst(\gen_rst_ic.fifo_wr_rst_ic )); LUT4 #( .INIT(16'h0002)) \gen_sdpram.xpm_memory_base_inst_i_1 (.I0(wr_en), .I1(\count_value_i_reg[7] ), .I2(wrst_busy), .I3(rst_d1), .O(wr_pntr_plus1_pf_carry)); (* SOFT_HLUTNM = "soft_lutpair156" *) LUT3 #( .INIT(8'hAB)) \grdc.rd_data_count_i[8]_i_1 (.I0(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ), .I1(Q[0]), .I2(Q[1]), .O(SR)); LUT3 #( .INIT(8'hE0)) \guf.underflow_i_i_1 (.I0(\guf.underflow_i_reg ), .I1(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ), .I2(rd_en), .O(underflow_i0)); FDRE #( .INIT(1'b1)) \power_on_rst_reg[0] (.C(wr_clk), .CE(1'b1), .D(1'b0), .Q(\power_on_rst_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \power_on_rst_reg[1] (.C(wr_clk), .CE(1'b1), .D(\power_on_rst_reg_n_0_[0] ), .Q(p_0_in), .R(1'b0)); LUT2 #( .INIT(4'hE)) wr_rst_busy_INST_0 (.I0(wrst_busy), .I1(rst_d1), .O(wr_rst_busy)); endmodule (* ORIG_REF_NAME = "xpm_fifo_rst" *) module axi_chip2chip_64B66B_xpm_fifo_rst__xdcDup__1 (\gen_rst_ic.fifo_rd_rst_ic_reg_0 , wrst_busy, wr_pntr_plus1_pf_carry, wr_rst_busy, SR, underflow_i0, \gen_rst_ic.fifo_rd_rst_ic_reg_1 , rd_clk, wr_clk, rst, wr_en, \count_value_i_reg[7] , rst_d1, Q, \guf.underflow_i_reg , rd_en, ram_empty_i); output \gen_rst_ic.fifo_rd_rst_ic_reg_0 ; output wrst_busy; output wr_pntr_plus1_pf_carry; output wr_rst_busy; output [0:0]SR; output underflow_i0; output [0:0]\gen_rst_ic.fifo_rd_rst_ic_reg_1 ; input rd_clk; input wr_clk; input rst; input wr_en; input \count_value_i_reg[7] ; input rst_d1; input [1:0]Q; input \guf.underflow_i_reg ; input rd_en; input ram_empty_i; wire \/i__n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0 ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ; wire \FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0 ; wire [1:0]Q; wire [0:0]SR; wire \__0/i__n_0 ; wire \count_value_i_reg[7] ; (* RTL_KEEP = "yes" *) wire [1:0]\gen_rst_ic.curr_rrst_state ; wire \gen_rst_ic.fifo_rd_rst_i0 ; wire \gen_rst_ic.fifo_rd_rst_ic_reg_0 ; wire [0:0]\gen_rst_ic.fifo_rd_rst_ic_reg_1 ; wire \gen_rst_ic.fifo_rd_rst_wr_i ; wire \gen_rst_ic.fifo_wr_rst_ic ; wire \gen_rst_ic.fifo_wr_rst_ic_i_1_n_0 ; wire \gen_rst_ic.fifo_wr_rst_ic_i_3_n_0 ; wire \gen_rst_ic.fifo_wr_rst_rd ; wire \gen_rst_ic.rst_seq_reentered_i_1_n_0 ; wire \gen_rst_ic.rst_seq_reentered_i_2_n_0 ; wire \gen_rst_ic.rst_seq_reentered_reg_n_0 ; wire \gen_rst_ic.wr_rst_busy_ic_i_1_n_0 ; wire \gen_rst_ic.wr_rst_busy_ic_i_2_n_0 ; wire \guf.underflow_i_reg ; wire p_0_in; wire \power_on_rst_reg_n_0_[0] ; wire ram_empty_i; wire rd_clk; wire rd_en; wire rst; wire rst_d1; wire rst_i__0; wire underflow_i0; wire wr_clk; wire wr_en; wire wr_pntr_plus1_pf_carry; wire wr_rst_busy; wire wrst_busy; LUT5 #( .INIT(32'h00010116)) \/i_ (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .O(\/i__n_0 )); LUT6 #( .INIT(64'h03030200FFFFFFFF)) \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I1(p_0_in), .I2(rst), .I3(\gen_rst_ic.rst_seq_reentered_reg_n_0 ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I5(\/i__n_0 ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFEFEFEEE)) \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0 ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I3(rst), .I4(p_0_in), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0 )); LUT6 #( .INIT(64'hFFF0EEE0FFFFEEE0)) \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I2(rst), .I3(p_0_in), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I5(\gen_rst_ic.fifo_rd_rst_wr_i ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0 )); LUT5 #( .INIT(32'h000C0008)) \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I1(\gen_rst_ic.fifo_rd_rst_wr_i ), .I2(rst), .I3(p_0_in), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0 )); LUT4 #( .INIT(16'h0004)) \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1 (.I0(\gen_rst_ic.fifo_rd_rst_wr_i ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I2(rst), .I3(p_0_in), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1 (.I0(\/i__n_0 ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); LUT4 #( .INIT(16'h0002)) \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I1(p_0_in), .I2(rst), .I3(\gen_rst_ic.rst_seq_reentered_reg_n_0 ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0 )); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b1)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[0] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .R(1'b0)); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[1] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[2] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[3] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[4] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); LUT2 #( .INIT(4'h6)) \FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1 (.I0(\gen_rst_ic.curr_rrst_state [0]), .I1(\gen_rst_ic.curr_rrst_state [1]), .O(\FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0 )); (* FSM_ENCODED_STATES = "iSTATE:00,iSTATE0:01,iSTATE1:10,iSTATE2:11" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[0] (.C(rd_clk), .CE(1'b1), .D(\__0/i__n_0 ), .Q(\gen_rst_ic.curr_rrst_state [0]), .R(1'b0)); (* FSM_ENCODED_STATES = "iSTATE:00,iSTATE0:01,iSTATE1:10,iSTATE2:11" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[1] (.C(rd_clk), .CE(1'b1), .D(\FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0 ), .Q(\gen_rst_ic.curr_rrst_state [1]), .R(1'b0)); LUT3 #( .INIT(8'h06)) \__0/i_ (.I0(\gen_rst_ic.fifo_wr_rst_rd ), .I1(\gen_rst_ic.curr_rrst_state [1]), .I2(\gen_rst_ic.curr_rrst_state [0]), .O(\__0/i__n_0 )); (* SOFT_HLUTNM = "soft_lutpair123" *) LUT4 #( .INIT(16'hAAAE)) \count_value_i[1]_i_1__4 (.I0(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ), .I1(ram_empty_i), .I2(Q[1]), .I3(Q[0]), .O(\gen_rst_ic.fifo_rd_rst_ic_reg_1 )); LUT3 #( .INIT(8'h3E)) \gen_rst_ic.fifo_rd_rst_ic_i_1 (.I0(\gen_rst_ic.fifo_wr_rst_rd ), .I1(\gen_rst_ic.curr_rrst_state [1]), .I2(\gen_rst_ic.curr_rrst_state [0]), .O(\gen_rst_ic.fifo_rd_rst_i0 )); FDRE #( .INIT(1'b0)) \gen_rst_ic.fifo_rd_rst_ic_reg (.C(rd_clk), .CE(1'b1), .D(\gen_rst_ic.fifo_rd_rst_i0 ), .Q(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ), .R(1'b0)); LUT6 #( .INIT(64'hFFEAFFFFFFEA0000)) \gen_rst_ic.fifo_wr_rst_ic_i_1 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I2(rst_i__0), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I4(\gen_rst_ic.fifo_wr_rst_ic_i_3_n_0 ), .I5(\gen_rst_ic.fifo_wr_rst_ic ), .O(\gen_rst_ic.fifo_wr_rst_ic_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair124" *) LUT2 #( .INIT(4'hE)) \gen_rst_ic.fifo_wr_rst_ic_i_2 (.I0(p_0_in), .I1(rst), .O(rst_i__0)); LUT5 #( .INIT(32'h00010116)) \gen_rst_ic.fifo_wr_rst_ic_i_3 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .O(\gen_rst_ic.fifo_wr_rst_ic_i_3_n_0 )); FDRE #( .INIT(1'b0)) \gen_rst_ic.fifo_wr_rst_ic_reg (.C(wr_clk), .CE(1'b1), .D(\gen_rst_ic.fifo_wr_rst_ic_i_1_n_0 ), .Q(\gen_rst_ic.fifo_wr_rst_ic ), .R(1'b0)); (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "3" *) (* INIT = "0" *) (* INIT_SYNC_FF = "1" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *) (* XPM_CDC = "SYNC_RST" *) (* XPM_MODULE = "TRUE" *) axi_chip2chip_64B66B_xpm_cdc_sync_rst__11 \gen_rst_ic.rrst_wr_inst (.dest_clk(wr_clk), .dest_rst(\gen_rst_ic.fifo_rd_rst_wr_i ), .src_rst(\gen_rst_ic.fifo_rd_rst_ic_reg_0 )); (* SOFT_HLUTNM = "soft_lutpair124" *) LUT3 #( .INIT(8'h02)) \gen_rst_ic.rst_seq_reentered_i_1 (.I0(\gen_rst_ic.rst_seq_reentered_i_2_n_0 ), .I1(rst), .I2(p_0_in), .O(\gen_rst_ic.rst_seq_reentered_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF00010000)) \gen_rst_ic.rst_seq_reentered_i_2 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .I5(\gen_rst_ic.rst_seq_reentered_reg_n_0 ), .O(\gen_rst_ic.rst_seq_reentered_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_rst_ic.rst_seq_reentered_reg (.C(wr_clk), .CE(1'b1), .D(\gen_rst_ic.rst_seq_reentered_i_1_n_0 ), .Q(\gen_rst_ic.rst_seq_reentered_reg_n_0 ), .R(1'b0)); LUT5 #( .INIT(32'hEFFFEF00)) \gen_rst_ic.wr_rst_busy_ic_i_1 (.I0(rst), .I1(p_0_in), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I3(\gen_rst_ic.wr_rst_busy_ic_i_2_n_0 ), .I4(wrst_busy), .O(\gen_rst_ic.wr_rst_busy_ic_i_1_n_0 )); LUT5 #( .INIT(32'h00000116)) \gen_rst_ic.wr_rst_busy_ic_i_2 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .O(\gen_rst_ic.wr_rst_busy_ic_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_rst_ic.wr_rst_busy_ic_reg (.C(wr_clk), .CE(1'b1), .D(\gen_rst_ic.wr_rst_busy_ic_i_1_n_0 ), .Q(wrst_busy), .R(1'b0)); (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "3" *) (* INIT = "0" *) (* INIT_SYNC_FF = "1" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *) (* XPM_CDC = "SYNC_RST" *) (* XPM_MODULE = "TRUE" *) axi_chip2chip_64B66B_xpm_cdc_sync_rst__10 \gen_rst_ic.wrst_rd_inst (.dest_clk(rd_clk), .dest_rst(\gen_rst_ic.fifo_wr_rst_rd ), .src_rst(\gen_rst_ic.fifo_wr_rst_ic )); LUT4 #( .INIT(16'h0002)) \gen_sdpram.xpm_memory_base_inst_i_1 (.I0(wr_en), .I1(\count_value_i_reg[7] ), .I2(wrst_busy), .I3(rst_d1), .O(wr_pntr_plus1_pf_carry)); (* SOFT_HLUTNM = "soft_lutpair123" *) LUT3 #( .INIT(8'hAB)) \grdc.rd_data_count_i[8]_i_1 (.I0(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ), .I1(Q[0]), .I2(Q[1]), .O(SR)); LUT3 #( .INIT(8'hE0)) \guf.underflow_i_i_1 (.I0(\guf.underflow_i_reg ), .I1(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ), .I2(rd_en), .O(underflow_i0)); FDRE #( .INIT(1'b1)) \power_on_rst_reg[0] (.C(wr_clk), .CE(1'b1), .D(1'b0), .Q(\power_on_rst_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \power_on_rst_reg[1] (.C(wr_clk), .CE(1'b1), .D(\power_on_rst_reg_n_0_[0] ), .Q(p_0_in), .R(1'b0)); LUT2 #( .INIT(4'hE)) wr_rst_busy_INST_0 (.I0(wrst_busy), .I1(rst_d1), .O(wr_rst_busy)); endmodule (* ORIG_REF_NAME = "xpm_fifo_rst" *) module axi_chip2chip_64B66B_xpm_fifo_rst__xdcDup__2 (\gen_rst_ic.fifo_rd_rst_ic_reg_0 , wrst_busy, wr_pntr_plus1_pf_carry, wr_rst_busy, SR, underflow_i0, \gen_rst_ic.fifo_rd_rst_ic_reg_1 , rd_clk, wr_clk, rst, wr_en, \count_value_i_reg[7] , rst_d1, Q, \guf.underflow_i_reg , rd_en, ram_empty_i); output \gen_rst_ic.fifo_rd_rst_ic_reg_0 ; output wrst_busy; output wr_pntr_plus1_pf_carry; output wr_rst_busy; output [0:0]SR; output underflow_i0; output [0:0]\gen_rst_ic.fifo_rd_rst_ic_reg_1 ; input rd_clk; input wr_clk; input rst; input wr_en; input \count_value_i_reg[7] ; input rst_d1; input [1:0]Q; input \guf.underflow_i_reg ; input rd_en; input ram_empty_i; wire \/i__n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0 ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ; wire \FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0 ; wire [1:0]Q; wire [0:0]SR; wire \__0/i__n_0 ; wire \count_value_i_reg[7] ; (* RTL_KEEP = "yes" *) wire [1:0]\gen_rst_ic.curr_rrst_state ; wire \gen_rst_ic.fifo_rd_rst_i0 ; wire \gen_rst_ic.fifo_rd_rst_ic_reg_0 ; wire [0:0]\gen_rst_ic.fifo_rd_rst_ic_reg_1 ; wire \gen_rst_ic.fifo_rd_rst_wr_i ; wire \gen_rst_ic.fifo_wr_rst_ic ; wire \gen_rst_ic.fifo_wr_rst_ic_i_1_n_0 ; wire \gen_rst_ic.fifo_wr_rst_ic_i_3_n_0 ; wire \gen_rst_ic.fifo_wr_rst_rd ; wire \gen_rst_ic.rst_seq_reentered_i_1_n_0 ; wire \gen_rst_ic.rst_seq_reentered_i_2_n_0 ; wire \gen_rst_ic.rst_seq_reentered_reg_n_0 ; wire \gen_rst_ic.wr_rst_busy_ic_i_1_n_0 ; wire \gen_rst_ic.wr_rst_busy_ic_i_2_n_0 ; wire \guf.underflow_i_reg ; wire p_0_in; wire \power_on_rst_reg_n_0_[0] ; wire ram_empty_i; wire rd_clk; wire rd_en; wire rst; wire rst_d1; wire rst_i__0; wire underflow_i0; wire wr_clk; wire wr_en; wire wr_pntr_plus1_pf_carry; wire wr_rst_busy; wire wrst_busy; LUT5 #( .INIT(32'h00010116)) \/i_ (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .O(\/i__n_0 )); LUT6 #( .INIT(64'h03030200FFFFFFFF)) \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I1(p_0_in), .I2(rst), .I3(\gen_rst_ic.rst_seq_reentered_reg_n_0 ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I5(\/i__n_0 ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFEFEFEEE)) \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0 ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I3(rst), .I4(p_0_in), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0 )); LUT6 #( .INIT(64'hFFF0EEE0FFFFEEE0)) \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I2(rst), .I3(p_0_in), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I5(\gen_rst_ic.fifo_rd_rst_wr_i ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0 )); LUT5 #( .INIT(32'h000C0008)) \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I1(\gen_rst_ic.fifo_rd_rst_wr_i ), .I2(rst), .I3(p_0_in), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0 )); LUT4 #( .INIT(16'h0004)) \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1 (.I0(\gen_rst_ic.fifo_rd_rst_wr_i ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I2(rst), .I3(p_0_in), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1 (.I0(\/i__n_0 ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); LUT4 #( .INIT(16'h0002)) \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I1(p_0_in), .I2(rst), .I3(\gen_rst_ic.rst_seq_reentered_reg_n_0 ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0 )); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b1)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[0] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .R(1'b0)); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[1] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[2] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[3] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[4] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); LUT2 #( .INIT(4'h6)) \FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1 (.I0(\gen_rst_ic.curr_rrst_state [0]), .I1(\gen_rst_ic.curr_rrst_state [1]), .O(\FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0 )); (* FSM_ENCODED_STATES = "iSTATE:00,iSTATE0:01,iSTATE1:10,iSTATE2:11" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[0] (.C(rd_clk), .CE(1'b1), .D(\__0/i__n_0 ), .Q(\gen_rst_ic.curr_rrst_state [0]), .R(1'b0)); (* FSM_ENCODED_STATES = "iSTATE:00,iSTATE0:01,iSTATE1:10,iSTATE2:11" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[1] (.C(rd_clk), .CE(1'b1), .D(\FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0 ), .Q(\gen_rst_ic.curr_rrst_state [1]), .R(1'b0)); LUT3 #( .INIT(8'h06)) \__0/i_ (.I0(\gen_rst_ic.fifo_wr_rst_rd ), .I1(\gen_rst_ic.curr_rrst_state [1]), .I2(\gen_rst_ic.curr_rrst_state [0]), .O(\__0/i__n_0 )); (* SOFT_HLUTNM = "soft_lutpair89" *) LUT4 #( .INIT(16'hAAAE)) \count_value_i[1]_i_1__4 (.I0(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ), .I1(ram_empty_i), .I2(Q[1]), .I3(Q[0]), .O(\gen_rst_ic.fifo_rd_rst_ic_reg_1 )); LUT3 #( .INIT(8'h3E)) \gen_rst_ic.fifo_rd_rst_ic_i_1 (.I0(\gen_rst_ic.fifo_wr_rst_rd ), .I1(\gen_rst_ic.curr_rrst_state [1]), .I2(\gen_rst_ic.curr_rrst_state [0]), .O(\gen_rst_ic.fifo_rd_rst_i0 )); FDRE #( .INIT(1'b0)) \gen_rst_ic.fifo_rd_rst_ic_reg (.C(rd_clk), .CE(1'b1), .D(\gen_rst_ic.fifo_rd_rst_i0 ), .Q(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ), .R(1'b0)); LUT6 #( .INIT(64'hFFEAFFFFFFEA0000)) \gen_rst_ic.fifo_wr_rst_ic_i_1 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I2(rst_i__0), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I4(\gen_rst_ic.fifo_wr_rst_ic_i_3_n_0 ), .I5(\gen_rst_ic.fifo_wr_rst_ic ), .O(\gen_rst_ic.fifo_wr_rst_ic_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair90" *) LUT2 #( .INIT(4'hE)) \gen_rst_ic.fifo_wr_rst_ic_i_2 (.I0(p_0_in), .I1(rst), .O(rst_i__0)); LUT5 #( .INIT(32'h00010116)) \gen_rst_ic.fifo_wr_rst_ic_i_3 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .O(\gen_rst_ic.fifo_wr_rst_ic_i_3_n_0 )); FDRE #( .INIT(1'b0)) \gen_rst_ic.fifo_wr_rst_ic_reg (.C(wr_clk), .CE(1'b1), .D(\gen_rst_ic.fifo_wr_rst_ic_i_1_n_0 ), .Q(\gen_rst_ic.fifo_wr_rst_ic ), .R(1'b0)); (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "3" *) (* INIT = "0" *) (* INIT_SYNC_FF = "1" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *) (* XPM_CDC = "SYNC_RST" *) (* XPM_MODULE = "TRUE" *) axi_chip2chip_64B66B_xpm_cdc_sync_rst__13 \gen_rst_ic.rrst_wr_inst (.dest_clk(wr_clk), .dest_rst(\gen_rst_ic.fifo_rd_rst_wr_i ), .src_rst(\gen_rst_ic.fifo_rd_rst_ic_reg_0 )); (* SOFT_HLUTNM = "soft_lutpair90" *) LUT3 #( .INIT(8'h02)) \gen_rst_ic.rst_seq_reentered_i_1 (.I0(\gen_rst_ic.rst_seq_reentered_i_2_n_0 ), .I1(rst), .I2(p_0_in), .O(\gen_rst_ic.rst_seq_reentered_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF00010000)) \gen_rst_ic.rst_seq_reentered_i_2 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .I5(\gen_rst_ic.rst_seq_reentered_reg_n_0 ), .O(\gen_rst_ic.rst_seq_reentered_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_rst_ic.rst_seq_reentered_reg (.C(wr_clk), .CE(1'b1), .D(\gen_rst_ic.rst_seq_reentered_i_1_n_0 ), .Q(\gen_rst_ic.rst_seq_reentered_reg_n_0 ), .R(1'b0)); LUT5 #( .INIT(32'hEFFFEF00)) \gen_rst_ic.wr_rst_busy_ic_i_1 (.I0(rst), .I1(p_0_in), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I3(\gen_rst_ic.wr_rst_busy_ic_i_2_n_0 ), .I4(wrst_busy), .O(\gen_rst_ic.wr_rst_busy_ic_i_1_n_0 )); LUT5 #( .INIT(32'h00000116)) \gen_rst_ic.wr_rst_busy_ic_i_2 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .O(\gen_rst_ic.wr_rst_busy_ic_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_rst_ic.wr_rst_busy_ic_reg (.C(wr_clk), .CE(1'b1), .D(\gen_rst_ic.wr_rst_busy_ic_i_1_n_0 ), .Q(wrst_busy), .R(1'b0)); (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "3" *) (* INIT = "0" *) (* INIT_SYNC_FF = "1" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *) (* XPM_CDC = "SYNC_RST" *) (* XPM_MODULE = "TRUE" *) axi_chip2chip_64B66B_xpm_cdc_sync_rst__12 \gen_rst_ic.wrst_rd_inst (.dest_clk(rd_clk), .dest_rst(\gen_rst_ic.fifo_wr_rst_rd ), .src_rst(\gen_rst_ic.fifo_wr_rst_ic )); LUT4 #( .INIT(16'h0002)) \gen_sdpram.xpm_memory_base_inst_i_1 (.I0(wr_en), .I1(\count_value_i_reg[7] ), .I2(wrst_busy), .I3(rst_d1), .O(wr_pntr_plus1_pf_carry)); (* SOFT_HLUTNM = "soft_lutpair89" *) LUT3 #( .INIT(8'hAB)) \grdc.rd_data_count_i[8]_i_1 (.I0(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ), .I1(Q[0]), .I2(Q[1]), .O(SR)); LUT3 #( .INIT(8'hE0)) \guf.underflow_i_i_1 (.I0(\guf.underflow_i_reg ), .I1(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ), .I2(rd_en), .O(underflow_i0)); FDRE #( .INIT(1'b1)) \power_on_rst_reg[0] (.C(wr_clk), .CE(1'b1), .D(1'b0), .Q(\power_on_rst_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \power_on_rst_reg[1] (.C(wr_clk), .CE(1'b1), .D(\power_on_rst_reg_n_0_[0] ), .Q(p_0_in), .R(1'b0)); LUT2 #( .INIT(4'hE)) wr_rst_busy_INST_0 (.I0(wrst_busy), .I1(rst_d1), .O(wr_rst_busy)); endmodule (* ORIG_REF_NAME = "xpm_fifo_rst" *) module axi_chip2chip_64B66B_xpm_fifo_rst__xdcDup__3 (\gen_rst_ic.fifo_rd_rst_ic_reg_0 , wrst_busy, wr_pntr_plus1_pf_carry, wr_rst_busy, SR, underflow_i0, \gen_pf_ic_rc.ram_empty_i_reg , rd_clk, wr_clk, rst, wr_en, \count_value_i_reg[8] , rst_d1, Q, \guf.underflow_i_reg , rd_en, ram_empty_i); output \gen_rst_ic.fifo_rd_rst_ic_reg_0 ; output wrst_busy; output wr_pntr_plus1_pf_carry; output wr_rst_busy; output [0:0]SR; output underflow_i0; output [0:0]\gen_pf_ic_rc.ram_empty_i_reg ; input rd_clk; input wr_clk; input rst; input wr_en; input \count_value_i_reg[8] ; input rst_d1; input [1:0]Q; input \guf.underflow_i_reg ; input rd_en; input ram_empty_i; wire \/i__n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0 ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ; wire \FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0 ; wire [1:0]Q; wire [0:0]SR; wire \__0/i__n_0 ; wire \count_value_i_reg[8] ; wire [0:0]\gen_pf_ic_rc.ram_empty_i_reg ; (* RTL_KEEP = "yes" *) wire [1:0]\gen_rst_ic.curr_rrst_state ; wire \gen_rst_ic.fifo_rd_rst_i0 ; wire \gen_rst_ic.fifo_rd_rst_ic_reg_0 ; wire \gen_rst_ic.fifo_rd_rst_wr_i ; wire \gen_rst_ic.fifo_wr_rst_ic ; wire \gen_rst_ic.fifo_wr_rst_ic_i_1_n_0 ; wire \gen_rst_ic.fifo_wr_rst_ic_i_3_n_0 ; wire \gen_rst_ic.fifo_wr_rst_rd ; wire \gen_rst_ic.rst_seq_reentered_i_1_n_0 ; wire \gen_rst_ic.rst_seq_reentered_i_2_n_0 ; wire \gen_rst_ic.rst_seq_reentered_reg_n_0 ; wire \gen_rst_ic.wr_rst_busy_ic_i_1_n_0 ; wire \gen_rst_ic.wr_rst_busy_ic_i_2_n_0 ; wire \guf.underflow_i_reg ; wire p_0_in; wire \power_on_rst_reg_n_0_[0] ; wire ram_empty_i; wire rd_clk; wire rd_en; wire rst; wire rst_d1; wire rst_i__0; wire underflow_i0; wire wr_clk; wire wr_en; wire wr_pntr_plus1_pf_carry; wire wr_rst_busy; wire wrst_busy; LUT5 #( .INIT(32'h00010116)) \/i_ (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .O(\/i__n_0 )); LUT6 #( .INIT(64'h03030200FFFFFFFF)) \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I1(p_0_in), .I2(rst), .I3(\gen_rst_ic.rst_seq_reentered_reg_n_0 ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I5(\/i__n_0 ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFEFEFEEE)) \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0 ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I3(rst), .I4(p_0_in), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0 )); LUT6 #( .INIT(64'hFFF0EEE0FFFFEEE0)) \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I2(rst), .I3(p_0_in), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I5(\gen_rst_ic.fifo_rd_rst_wr_i ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0 )); LUT5 #( .INIT(32'h000C0008)) \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I1(\gen_rst_ic.fifo_rd_rst_wr_i ), .I2(rst), .I3(p_0_in), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0 )); LUT4 #( .INIT(16'h0004)) \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1 (.I0(\gen_rst_ic.fifo_rd_rst_wr_i ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I2(rst), .I3(p_0_in), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1 (.I0(\/i__n_0 ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); LUT4 #( .INIT(16'h0002)) \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I1(p_0_in), .I2(rst), .I3(\gen_rst_ic.rst_seq_reentered_reg_n_0 ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0 )); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b1)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[0] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .R(1'b0)); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[1] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[2] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[3] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[4] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); LUT2 #( .INIT(4'h6)) \FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1 (.I0(\gen_rst_ic.curr_rrst_state [0]), .I1(\gen_rst_ic.curr_rrst_state [1]), .O(\FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0 )); (* FSM_ENCODED_STATES = "iSTATE:00,iSTATE0:01,iSTATE1:10,iSTATE2:11" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[0] (.C(rd_clk), .CE(1'b1), .D(\__0/i__n_0 ), .Q(\gen_rst_ic.curr_rrst_state [0]), .R(1'b0)); (* FSM_ENCODED_STATES = "iSTATE:00,iSTATE0:01,iSTATE1:10,iSTATE2:11" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[1] (.C(rd_clk), .CE(1'b1), .D(\FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0 ), .Q(\gen_rst_ic.curr_rrst_state [1]), .R(1'b0)); LUT3 #( .INIT(8'h06)) \__0/i_ (.I0(\gen_rst_ic.fifo_wr_rst_rd ), .I1(\gen_rst_ic.curr_rrst_state [1]), .I2(\gen_rst_ic.curr_rrst_state [0]), .O(\__0/i__n_0 )); (* SOFT_HLUTNM = "soft_lutpair260" *) LUT4 #( .INIT(16'hFF02)) \count_value_i[1]_i_1__4 (.I0(ram_empty_i), .I1(Q[0]), .I2(Q[1]), .I3(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ), .O(\gen_pf_ic_rc.ram_empty_i_reg )); LUT3 #( .INIT(8'h3E)) \gen_rst_ic.fifo_rd_rst_ic_i_1 (.I0(\gen_rst_ic.fifo_wr_rst_rd ), .I1(\gen_rst_ic.curr_rrst_state [1]), .I2(\gen_rst_ic.curr_rrst_state [0]), .O(\gen_rst_ic.fifo_rd_rst_i0 )); FDRE #( .INIT(1'b0)) \gen_rst_ic.fifo_rd_rst_ic_reg (.C(rd_clk), .CE(1'b1), .D(\gen_rst_ic.fifo_rd_rst_i0 ), .Q(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ), .R(1'b0)); LUT6 #( .INIT(64'hFFEAFFFFFFEA0000)) \gen_rst_ic.fifo_wr_rst_ic_i_1 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I2(rst_i__0), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I4(\gen_rst_ic.fifo_wr_rst_ic_i_3_n_0 ), .I5(\gen_rst_ic.fifo_wr_rst_ic ), .O(\gen_rst_ic.fifo_wr_rst_ic_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair261" *) LUT2 #( .INIT(4'hE)) \gen_rst_ic.fifo_wr_rst_ic_i_2 (.I0(p_0_in), .I1(rst), .O(rst_i__0)); LUT5 #( .INIT(32'h00010116)) \gen_rst_ic.fifo_wr_rst_ic_i_3 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .O(\gen_rst_ic.fifo_wr_rst_ic_i_3_n_0 )); FDRE #( .INIT(1'b0)) \gen_rst_ic.fifo_wr_rst_ic_reg (.C(wr_clk), .CE(1'b1), .D(\gen_rst_ic.fifo_wr_rst_ic_i_1_n_0 ), .Q(\gen_rst_ic.fifo_wr_rst_ic ), .R(1'b0)); (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "3" *) (* INIT = "0" *) (* INIT_SYNC_FF = "1" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *) (* XPM_CDC = "SYNC_RST" *) (* XPM_MODULE = "TRUE" *) axi_chip2chip_64B66B_xpm_cdc_sync_rst__15 \gen_rst_ic.rrst_wr_inst (.dest_clk(wr_clk), .dest_rst(\gen_rst_ic.fifo_rd_rst_wr_i ), .src_rst(\gen_rst_ic.fifo_rd_rst_ic_reg_0 )); (* SOFT_HLUTNM = "soft_lutpair261" *) LUT3 #( .INIT(8'h02)) \gen_rst_ic.rst_seq_reentered_i_1 (.I0(\gen_rst_ic.rst_seq_reentered_i_2_n_0 ), .I1(rst), .I2(p_0_in), .O(\gen_rst_ic.rst_seq_reentered_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF00010000)) \gen_rst_ic.rst_seq_reentered_i_2 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .I5(\gen_rst_ic.rst_seq_reentered_reg_n_0 ), .O(\gen_rst_ic.rst_seq_reentered_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_rst_ic.rst_seq_reentered_reg (.C(wr_clk), .CE(1'b1), .D(\gen_rst_ic.rst_seq_reentered_i_1_n_0 ), .Q(\gen_rst_ic.rst_seq_reentered_reg_n_0 ), .R(1'b0)); LUT5 #( .INIT(32'hEFFFEF00)) \gen_rst_ic.wr_rst_busy_ic_i_1 (.I0(rst), .I1(p_0_in), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I3(\gen_rst_ic.wr_rst_busy_ic_i_2_n_0 ), .I4(wrst_busy), .O(\gen_rst_ic.wr_rst_busy_ic_i_1_n_0 )); LUT5 #( .INIT(32'h00000116)) \gen_rst_ic.wr_rst_busy_ic_i_2 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .O(\gen_rst_ic.wr_rst_busy_ic_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_rst_ic.wr_rst_busy_ic_reg (.C(wr_clk), .CE(1'b1), .D(\gen_rst_ic.wr_rst_busy_ic_i_1_n_0 ), .Q(wrst_busy), .R(1'b0)); (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "3" *) (* INIT = "0" *) (* INIT_SYNC_FF = "1" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *) (* XPM_CDC = "SYNC_RST" *) (* XPM_MODULE = "TRUE" *) axi_chip2chip_64B66B_xpm_cdc_sync_rst__14 \gen_rst_ic.wrst_rd_inst (.dest_clk(rd_clk), .dest_rst(\gen_rst_ic.fifo_wr_rst_rd ), .src_rst(\gen_rst_ic.fifo_wr_rst_ic )); LUT4 #( .INIT(16'h0002)) \gen_sdpram.xpm_memory_base_inst_i_1 (.I0(wr_en), .I1(\count_value_i_reg[8] ), .I2(wrst_busy), .I3(rst_d1), .O(wr_pntr_plus1_pf_carry)); (* SOFT_HLUTNM = "soft_lutpair260" *) LUT3 #( .INIT(8'hF1)) \grdc.rd_data_count_i[9]_i_1 (.I0(Q[1]), .I1(Q[0]), .I2(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ), .O(SR)); LUT3 #( .INIT(8'hE0)) \guf.underflow_i_i_1 (.I0(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ), .I1(\guf.underflow_i_reg ), .I2(rd_en), .O(underflow_i0)); FDRE #( .INIT(1'b1)) \power_on_rst_reg[0] (.C(wr_clk), .CE(1'b1), .D(1'b0), .Q(\power_on_rst_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \power_on_rst_reg[1] (.C(wr_clk), .CE(1'b1), .D(\power_on_rst_reg_n_0_[0] ), .Q(p_0_in), .R(1'b0)); LUT2 #( .INIT(4'hE)) wr_rst_busy_INST_0 (.I0(wrst_busy), .I1(rst_d1), .O(wr_rst_busy)); endmodule (* ORIG_REF_NAME = "xpm_fifo_rst" *) module axi_chip2chip_64B66B_xpm_fifo_rst__xdcDup__4 (\gen_rst_ic.fifo_rd_rst_ic_reg_0 , wrst_busy, wr_pntr_plus1_pf_carry, wr_rst_busy, SR, underflow_i0, \gen_pf_ic_rc.ram_empty_i_reg , rd_clk, wr_clk, rst, wr_en, \count_value_i_reg[8] , rst_d1, Q, \guf.underflow_i_reg , rd_en, ram_empty_i); output \gen_rst_ic.fifo_rd_rst_ic_reg_0 ; output wrst_busy; output wr_pntr_plus1_pf_carry; output wr_rst_busy; output [0:0]SR; output underflow_i0; output [0:0]\gen_pf_ic_rc.ram_empty_i_reg ; input rd_clk; input wr_clk; input rst; input wr_en; input \count_value_i_reg[8] ; input rst_d1; input [1:0]Q; input \guf.underflow_i_reg ; input rd_en; input ram_empty_i; wire \/i__n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 ; wire \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0 ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ; (* RTL_KEEP = "yes" *) wire \FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ; wire \FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0 ; wire [1:0]Q; wire [0:0]SR; wire \__0/i__n_0 ; wire \count_value_i_reg[8] ; wire [0:0]\gen_pf_ic_rc.ram_empty_i_reg ; (* RTL_KEEP = "yes" *) wire [1:0]\gen_rst_ic.curr_rrst_state ; wire \gen_rst_ic.fifo_rd_rst_i0 ; wire \gen_rst_ic.fifo_rd_rst_ic_reg_0 ; wire \gen_rst_ic.fifo_rd_rst_wr_i ; wire \gen_rst_ic.fifo_wr_rst_ic ; wire \gen_rst_ic.fifo_wr_rst_ic_i_1_n_0 ; wire \gen_rst_ic.fifo_wr_rst_ic_i_3_n_0 ; wire \gen_rst_ic.fifo_wr_rst_rd ; wire \gen_rst_ic.rst_seq_reentered_i_1_n_0 ; wire \gen_rst_ic.rst_seq_reentered_i_2_n_0 ; wire \gen_rst_ic.rst_seq_reentered_reg_n_0 ; wire \gen_rst_ic.wr_rst_busy_ic_i_1_n_0 ; wire \gen_rst_ic.wr_rst_busy_ic_i_2_n_0 ; wire \guf.underflow_i_reg ; wire p_0_in; wire \power_on_rst_reg_n_0_[0] ; wire ram_empty_i; wire rd_clk; wire rd_en; wire rst; wire rst_d1; wire rst_i__0; wire underflow_i0; wire wr_clk; wire wr_en; wire wr_pntr_plus1_pf_carry; wire wr_rst_busy; wire wrst_busy; LUT5 #( .INIT(32'h00010116)) \/i_ (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .O(\/i__n_0 )); LUT6 #( .INIT(64'h03030200FFFFFFFF)) \FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I1(p_0_in), .I2(rst), .I3(\gen_rst_ic.rst_seq_reentered_reg_n_0 ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I5(\/i__n_0 ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0 )); LUT5 #( .INIT(32'hFEFEFEEE)) \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0 ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I3(rst), .I4(p_0_in), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0 )); LUT6 #( .INIT(64'hFFF0EEE0FFFFEEE0)) \FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I2(rst), .I3(p_0_in), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I5(\gen_rst_ic.fifo_rd_rst_wr_i ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_2_n_0 )); LUT5 #( .INIT(32'h000C0008)) \FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I1(\gen_rst_ic.fifo_rd_rst_wr_i ), .I2(rst), .I3(p_0_in), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0 )); LUT4 #( .INIT(16'h0004)) \FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1 (.I0(\gen_rst_ic.fifo_rd_rst_wr_i ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I2(rst), .I3(p_0_in), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0 )); LUT1 #( .INIT(2'h1)) \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1 (.I0(\/i__n_0 ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); LUT4 #( .INIT(16'h0002)) \FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I1(p_0_in), .I2(rst), .I3(\gen_rst_ic.rst_seq_reentered_reg_n_0 ), .O(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0 )); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b1)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[0] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[0]_i_1_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .R(1'b0)); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[1] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[1]_i_1_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[2] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[2]_i_1_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[3] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[3]_i_1_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); (* FSM_ENCODED_STATES = "WRST_OUT:00100,WRST_IN:00010,WRST_GO2IDLE:10000,WRST_EXIT:01000,WRST_IDLE:00001" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_onehot_gen_rst_ic.curr_wrst_state_reg[4] (.C(wr_clk), .CE(1'b1), .D(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_2_n_0 ), .Q(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .R(\FSM_onehot_gen_rst_ic.curr_wrst_state[4]_i_1_n_0 )); LUT2 #( .INIT(4'h6)) \FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1 (.I0(\gen_rst_ic.curr_rrst_state [0]), .I1(\gen_rst_ic.curr_rrst_state [1]), .O(\FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0 )); (* FSM_ENCODED_STATES = "iSTATE:00,iSTATE0:01,iSTATE1:10,iSTATE2:11" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[0] (.C(rd_clk), .CE(1'b1), .D(\__0/i__n_0 ), .Q(\gen_rst_ic.curr_rrst_state [0]), .R(1'b0)); (* FSM_ENCODED_STATES = "iSTATE:00,iSTATE0:01,iSTATE1:10,iSTATE2:11" *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) \FSM_sequential_gen_rst_ic.curr_rrst_state_reg[1] (.C(rd_clk), .CE(1'b1), .D(\FSM_sequential_gen_rst_ic.curr_rrst_state[1]_i_1_n_0 ), .Q(\gen_rst_ic.curr_rrst_state [1]), .R(1'b0)); LUT3 #( .INIT(8'h06)) \__0/i_ (.I0(\gen_rst_ic.fifo_wr_rst_rd ), .I1(\gen_rst_ic.curr_rrst_state [1]), .I2(\gen_rst_ic.curr_rrst_state [0]), .O(\__0/i__n_0 )); (* SOFT_HLUTNM = "soft_lutpair200" *) LUT4 #( .INIT(16'hFF02)) \count_value_i[1]_i_1__4 (.I0(ram_empty_i), .I1(Q[0]), .I2(Q[1]), .I3(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ), .O(\gen_pf_ic_rc.ram_empty_i_reg )); LUT3 #( .INIT(8'h3E)) \gen_rst_ic.fifo_rd_rst_ic_i_1 (.I0(\gen_rst_ic.fifo_wr_rst_rd ), .I1(\gen_rst_ic.curr_rrst_state [1]), .I2(\gen_rst_ic.curr_rrst_state [0]), .O(\gen_rst_ic.fifo_rd_rst_i0 )); FDRE #( .INIT(1'b0)) \gen_rst_ic.fifo_rd_rst_ic_reg (.C(rd_clk), .CE(1'b1), .D(\gen_rst_ic.fifo_rd_rst_i0 ), .Q(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ), .R(1'b0)); LUT6 #( .INIT(64'hFFEAFFFFFFEA0000)) \gen_rst_ic.fifo_wr_rst_ic_i_1 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I2(rst_i__0), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I4(\gen_rst_ic.fifo_wr_rst_ic_i_3_n_0 ), .I5(\gen_rst_ic.fifo_wr_rst_ic ), .O(\gen_rst_ic.fifo_wr_rst_ic_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair201" *) LUT2 #( .INIT(4'hE)) \gen_rst_ic.fifo_wr_rst_ic_i_2 (.I0(p_0_in), .I1(rst), .O(rst_i__0)); LUT5 #( .INIT(32'h00010116)) \gen_rst_ic.fifo_wr_rst_ic_i_3 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .O(\gen_rst_ic.fifo_wr_rst_ic_i_3_n_0 )); FDRE #( .INIT(1'b0)) \gen_rst_ic.fifo_wr_rst_ic_reg (.C(wr_clk), .CE(1'b1), .D(\gen_rst_ic.fifo_wr_rst_ic_i_1_n_0 ), .Q(\gen_rst_ic.fifo_wr_rst_ic ), .R(1'b0)); (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "3" *) (* INIT = "0" *) (* INIT_SYNC_FF = "1" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *) (* XPM_CDC = "SYNC_RST" *) (* XPM_MODULE = "TRUE" *) axi_chip2chip_64B66B_xpm_cdc_sync_rst__17 \gen_rst_ic.rrst_wr_inst (.dest_clk(wr_clk), .dest_rst(\gen_rst_ic.fifo_rd_rst_wr_i ), .src_rst(\gen_rst_ic.fifo_rd_rst_ic_reg_0 )); (* SOFT_HLUTNM = "soft_lutpair201" *) LUT3 #( .INIT(8'h02)) \gen_rst_ic.rst_seq_reentered_i_1 (.I0(\gen_rst_ic.rst_seq_reentered_i_2_n_0 ), .I1(rst), .I2(p_0_in), .O(\gen_rst_ic.rst_seq_reentered_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFFF00010000)) \gen_rst_ic.rst_seq_reentered_i_2 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .I5(\gen_rst_ic.rst_seq_reentered_reg_n_0 ), .O(\gen_rst_ic.rst_seq_reentered_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_rst_ic.rst_seq_reentered_reg (.C(wr_clk), .CE(1'b1), .D(\gen_rst_ic.rst_seq_reentered_i_1_n_0 ), .Q(\gen_rst_ic.rst_seq_reentered_reg_n_0 ), .R(1'b0)); LUT5 #( .INIT(32'hEFFFEF00)) \gen_rst_ic.wr_rst_busy_ic_i_1 (.I0(rst), .I1(p_0_in), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I3(\gen_rst_ic.wr_rst_busy_ic_i_2_n_0 ), .I4(wrst_busy), .O(\gen_rst_ic.wr_rst_busy_ic_i_1_n_0 )); LUT5 #( .INIT(32'h00000116)) \gen_rst_ic.wr_rst_busy_ic_i_2 (.I0(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[3] ), .I1(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[2] ), .I2(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[1] ), .I3(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[0] ), .I4(\FSM_onehot_gen_rst_ic.curr_wrst_state_reg_n_0_[4] ), .O(\gen_rst_ic.wr_rst_busy_ic_i_2_n_0 )); FDRE #( .INIT(1'b0)) \gen_rst_ic.wr_rst_busy_ic_reg (.C(wr_clk), .CE(1'b1), .D(\gen_rst_ic.wr_rst_busy_ic_i_1_n_0 ), .Q(wrst_busy), .R(1'b0)); (* DEF_VAL = "1'b0" *) (* DEST_SYNC_FF = "3" *) (* INIT = "0" *) (* INIT_SYNC_FF = "1" *) (* SIM_ASSERT_CHK = "0" *) (* VERSION = "0" *) (* XPM_CDC = "SYNC_RST" *) (* XPM_MODULE = "TRUE" *) axi_chip2chip_64B66B_xpm_cdc_sync_rst__16 \gen_rst_ic.wrst_rd_inst (.dest_clk(rd_clk), .dest_rst(\gen_rst_ic.fifo_wr_rst_rd ), .src_rst(\gen_rst_ic.fifo_wr_rst_ic )); LUT4 #( .INIT(16'h0002)) \gen_sdpram.xpm_memory_base_inst_i_1 (.I0(wr_en), .I1(\count_value_i_reg[8] ), .I2(wrst_busy), .I3(rst_d1), .O(wr_pntr_plus1_pf_carry)); (* SOFT_HLUTNM = "soft_lutpair200" *) LUT3 #( .INIT(8'hF1)) \grdc.rd_data_count_i[9]_i_1 (.I0(Q[1]), .I1(Q[0]), .I2(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ), .O(SR)); LUT3 #( .INIT(8'hE0)) \guf.underflow_i_i_1 (.I0(\gen_rst_ic.fifo_rd_rst_ic_reg_0 ), .I1(\guf.underflow_i_reg ), .I2(rd_en), .O(underflow_i0)); FDRE #( .INIT(1'b1)) \power_on_rst_reg[0] (.C(wr_clk), .CE(1'b1), .D(1'b0), .Q(\power_on_rst_reg_n_0_[0] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \power_on_rst_reg[1] (.C(wr_clk), .CE(1'b1), .D(\power_on_rst_reg_n_0_[0] ), .Q(p_0_in), .R(1'b0)); LUT2 #( .INIT(4'hE)) wr_rst_busy_INST_0 (.I0(wrst_busy), .I1(rst_d1), .O(wr_rst_busy)); endmodule (* ADDR_WIDTH_A = "8" *) (* ADDR_WIDTH_B = "8" *) (* AUTO_SLEEP_TIME = "0" *) (* BYTE_WRITE_WIDTH_A = "50" *) (* BYTE_WRITE_WIDTH_B = "50" *) (* CASCADE_HEIGHT = "0" *) (* CLOCKING_MODE = "1" *) (* ECC_MODE = "0" *) (* MAX_NUM_CHAR = "0" *) (* MEMORY_INIT_FILE = "none" *) (* MEMORY_INIT_PARAM = "" *) (* MEMORY_OPTIMIZATION = "true" *) (* MEMORY_PRIMITIVE = "2" *) (* MEMORY_SIZE = "12800" *) (* MEMORY_TYPE = "1" *) (* MESSAGE_CONTROL = "0" *) (* NUM_CHAR_LOC = "0" *) (* ORIG_REF_NAME = "xpm_memory_base" *) (* P_ECC_MODE = "no_ecc" *) (* P_ENABLE_BYTE_WRITE_A = "0" *) (* P_ENABLE_BYTE_WRITE_B = "0" *) (* P_MAX_DEPTH_DATA = "256" *) (* P_MEMORY_OPT = "yes" *) (* P_MEMORY_PRIMITIVE = "block" *) (* P_MIN_WIDTH_DATA = "50" *) (* P_MIN_WIDTH_DATA_A = "50" *) (* P_MIN_WIDTH_DATA_B = "50" *) (* P_MIN_WIDTH_DATA_ECC = "50" *) (* P_MIN_WIDTH_DATA_LDW = "4" *) (* P_MIN_WIDTH_DATA_SHFT = "50" *) (* P_NUM_COLS_WRITE_A = "1" *) (* P_NUM_COLS_WRITE_B = "1" *) (* P_NUM_ROWS_READ_A = "1" *) (* P_NUM_ROWS_READ_B = "1" *) (* P_NUM_ROWS_WRITE_A = "1" *) (* P_NUM_ROWS_WRITE_B = "1" *) (* P_SDP_WRITE_MODE = "no" *) (* P_WIDTH_ADDR_LSB_READ_A = "0" *) (* P_WIDTH_ADDR_LSB_READ_B = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_B = "0" *) (* P_WIDTH_ADDR_READ_A = "8" *) (* P_WIDTH_ADDR_READ_B = "8" *) (* P_WIDTH_ADDR_WRITE_A = "8" *) (* P_WIDTH_ADDR_WRITE_B = "8" *) (* P_WIDTH_COL_WRITE_A = "50" *) (* P_WIDTH_COL_WRITE_B = "50" *) (* READ_DATA_WIDTH_A = "50" *) (* READ_DATA_WIDTH_B = "50" *) (* READ_LATENCY_A = "2" *) (* READ_LATENCY_B = "2" *) (* READ_RESET_VALUE_A = "0" *) (* READ_RESET_VALUE_B = "0" *) (* RST_MODE_A = "SYNC" *) (* RST_MODE_B = "SYNC" *) (* SIM_ASSERT_CHK = "0" *) (* USE_EMBEDDED_CONSTRAINT = "0" *) (* USE_MEM_INIT = "0" *) (* USE_MEM_INIT_MMI = "0" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH_A = "50" *) (* WRITE_DATA_WIDTH_B = "50" *) (* WRITE_MODE_A = "2" *) (* WRITE_MODE_B = "2" *) (* WRITE_PROTECT = "1" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "soft" *) (* rsta_loop_iter = "52" *) (* rstb_loop_iter = "52" *) module axi_chip2chip_64B66B_xpm_memory_base (sleep, clka, rsta, ena, regcea, wea, addra, dina, injectsbiterra, injectdbiterra, douta, sbiterra, dbiterra, clkb, rstb, enb, regceb, web, addrb, dinb, injectsbiterrb, injectdbiterrb, doutb, sbiterrb, dbiterrb); input sleep; input clka; input rsta; input ena; input regcea; input [0:0]wea; input [7:0]addra; input [49:0]dina; input injectsbiterra; input injectdbiterra; output [49:0]douta; output sbiterra; output dbiterra; input clkb; input rstb; input enb; input regceb; input [0:0]web; input [7:0]addrb; input [49:0]dinb; input injectsbiterrb; input injectdbiterrb; output [49:0]doutb; output sbiterrb; output dbiterrb; wire \ ; wire [7:0]addra; wire [7:0]addrb; wire clka; wire clkb; wire [49:0]dina; wire [49:0]doutb; wire ena; wire enb; wire regceb; wire rstb; wire sleep; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTDBITERR_UNCONNECTED ; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTSBITERR_UNCONNECTED ; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_DBITERR_UNCONNECTED ; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_SBITERR_UNCONNECTED ; wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINA_UNCONNECTED ; wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINB_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPA_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPB_UNCONNECTED ; wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTA_UNCONNECTED ; wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTB_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPA_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPB_UNCONNECTED ; wire [31:18]\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTBDOUT_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPADOUTP_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPBDOUTP_UNCONNECTED ; wire [7:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_RDADDRECC_UNCONNECTED ; assign dbiterra = \ ; assign dbiterrb = \ ; assign douta[49] = \ ; assign douta[48] = \ ; assign douta[47] = \ ; assign douta[46] = \ ; assign douta[45] = \ ; assign douta[44] = \ ; assign douta[43] = \ ; assign douta[42] = \ ; assign douta[41] = \ ; assign douta[40] = \ ; assign douta[39] = \ ; assign douta[38] = \ ; assign douta[37] = \ ; assign douta[36] = \ ; assign douta[35] = \ ; assign douta[34] = \ ; assign douta[33] = \ ; assign douta[32] = \ ; assign douta[31] = \ ; assign douta[30] = \ ; assign douta[29] = \ ; assign douta[28] = \ ; assign douta[27] = \ ; assign douta[26] = \ ; assign douta[25] = \ ; assign douta[24] = \ ; assign douta[23] = \ ; assign douta[22] = \ ; assign douta[21] = \ ; assign douta[20] = \ ; assign douta[19] = \ ; assign douta[18] = \ ; assign douta[17] = \ ; assign douta[16] = \ ; assign douta[15] = \ ; assign douta[14] = \ ; assign douta[13] = \ ; assign douta[12] = \ ; assign douta[11] = \ ; assign douta[10] = \ ; assign douta[9] = \ ; assign douta[8] = \ ; assign douta[7] = \ ; assign douta[6] = \ ; assign douta[5] = \ ; assign douta[4] = \ ; assign douta[3] = \ ; assign douta[2] = \ ; assign douta[1] = \ ; assign douta[0] = \ ; assign sbiterra = \ ; assign sbiterrb = \ ; GND GND (.G(\ )); (* \MEM.PORTA.ADDRESS_BEGIN = "0" *) (* \MEM.PORTA.ADDRESS_END = "511" *) (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d50" *) (* \MEM.PORTA.DATA_LSB = "0" *) (* \MEM.PORTA.DATA_MSB = "49" *) (* \MEM.PORTB.ADDRESS_BEGIN = "0" *) (* \MEM.PORTB.ADDRESS_END = "511" *) (* \MEM.PORTB.DATA_BIT_LAYOUT = "p0_d50" *) (* \MEM.PORTB.DATA_LSB = "0" *) (* \MEM.PORTB.DATA_MSB = "49" *) (* METHODOLOGY_DRC_VIOS = "" *) (* RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE" *) (* RTL_RAM_BITS = "12800" *) (* RTL_RAM_NAME = "gen_wr_a.gen_word_narrow.mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "511" *) (* ram_offset = "0" *) (* ram_slice_begin = "0" *) (* ram_slice_end = "49" *) RAMB36E2 #( .CASCADE_ORDER_A("NONE"), .CASCADE_ORDER_B("NONE"), .CLOCK_DOMAINS("INDEPENDENT"), .DOA_REG(1), .DOB_REG(1), .ENADDRENA("FALSE"), .ENADDRENB("FALSE"), .EN_ECC_PIPE("FALSE"), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .RDADDRCHANGEA("FALSE"), .RDADDRCHANGEB("FALSE"), .READ_WIDTH_A(72), .READ_WIDTH_B(0), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SLEEP_ASYNC("TRUE"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("NO_CHANGE"), .WRITE_MODE_B("NO_CHANGE"), .WRITE_WIDTH_A(0), .WRITE_WIDTH_B(72)) \gen_wr_a.gen_word_narrow.mem_reg (.ADDRARDADDR({1'b0,addrb,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b0,addra,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), .ADDRENA(1'b0), .ADDRENB(1'b0), .CASDIMUXA(1'b0), .CASDIMUXB(1'b0), .CASDINA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINA_UNCONNECTED [31:0]), .CASDINB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINB_UNCONNECTED [31:0]), .CASDINPA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPA_UNCONNECTED [3:0]), .CASDINPB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPB_UNCONNECTED [3:0]), .CASDOMUXA(1'b0), .CASDOMUXB(1'b0), .CASDOMUXEN_A(1'b1), .CASDOMUXEN_B(1'b1), .CASDOUTA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTA_UNCONNECTED [31:0]), .CASDOUTB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTB_UNCONNECTED [31:0]), .CASDOUTPA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPA_UNCONNECTED [3:0]), .CASDOUTPB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPB_UNCONNECTED [3:0]), .CASINDBITERR(1'b0), .CASINSBITERR(1'b0), .CASOREGIMUXA(1'b0), .CASOREGIMUXB(1'b0), .CASOREGIMUXEN_A(1'b1), .CASOREGIMUXEN_B(1'b1), .CASOUTDBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTDBITERR_UNCONNECTED ), .CASOUTSBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTSBITERR_UNCONNECTED ), .CLKARDCLK(clkb), .CLKBWRCLK(clka), .DBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_DBITERR_UNCONNECTED ), .DINADIN(dina[31:0]), .DINBDIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,dina[49:32]}), .DINPADINP({1'b1,1'b1,1'b1,1'b1}), .DINPBDINP({1'b1,1'b1,1'b1,1'b1}), .DOUTADOUT(doutb[31:0]), .DOUTBDOUT({\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTBDOUT_UNCONNECTED [31:18],doutb[49:32]}), .DOUTPADOUTP(\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPADOUTP_UNCONNECTED [3:0]), .DOUTPBDOUTP(\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPBDOUTP_UNCONNECTED [3:0]), .ECCPARITY(\NLW_gen_wr_a.gen_word_narrow.mem_reg_ECCPARITY_UNCONNECTED [7:0]), .ECCPIPECE(1'b1), .ENARDEN(enb), .ENBWREN(ena), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_gen_wr_a.gen_word_narrow.mem_reg_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(regceb), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(rstb), .RSTREGB(1'b0), .SBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_SBITERR_UNCONNECTED ), .SLEEP(1'b0), .WEA({1'b0,1'b0,1'b0,1'b0}), .WEBWE({ena,ena,ena,ena,ena,ena,ena,ena})); endmodule (* ADDR_WIDTH_A = "8" *) (* ADDR_WIDTH_B = "8" *) (* AUTO_SLEEP_TIME = "0" *) (* BYTE_WRITE_WIDTH_A = "50" *) (* BYTE_WRITE_WIDTH_B = "50" *) (* CASCADE_HEIGHT = "0" *) (* CLOCKING_MODE = "1" *) (* ECC_MODE = "0" *) (* MAX_NUM_CHAR = "0" *) (* MEMORY_INIT_FILE = "none" *) (* MEMORY_INIT_PARAM = "" *) (* MEMORY_OPTIMIZATION = "true" *) (* MEMORY_PRIMITIVE = "2" *) (* MEMORY_SIZE = "12800" *) (* MEMORY_TYPE = "1" *) (* MESSAGE_CONTROL = "0" *) (* NUM_CHAR_LOC = "0" *) (* ORIG_REF_NAME = "xpm_memory_base" *) (* P_ECC_MODE = "no_ecc" *) (* P_ENABLE_BYTE_WRITE_A = "0" *) (* P_ENABLE_BYTE_WRITE_B = "0" *) (* P_MAX_DEPTH_DATA = "256" *) (* P_MEMORY_OPT = "yes" *) (* P_MEMORY_PRIMITIVE = "block" *) (* P_MIN_WIDTH_DATA = "50" *) (* P_MIN_WIDTH_DATA_A = "50" *) (* P_MIN_WIDTH_DATA_B = "50" *) (* P_MIN_WIDTH_DATA_ECC = "50" *) (* P_MIN_WIDTH_DATA_LDW = "4" *) (* P_MIN_WIDTH_DATA_SHFT = "50" *) (* P_NUM_COLS_WRITE_A = "1" *) (* P_NUM_COLS_WRITE_B = "1" *) (* P_NUM_ROWS_READ_A = "1" *) (* P_NUM_ROWS_READ_B = "1" *) (* P_NUM_ROWS_WRITE_A = "1" *) (* P_NUM_ROWS_WRITE_B = "1" *) (* P_SDP_WRITE_MODE = "no" *) (* P_WIDTH_ADDR_LSB_READ_A = "0" *) (* P_WIDTH_ADDR_LSB_READ_B = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_B = "0" *) (* P_WIDTH_ADDR_READ_A = "8" *) (* P_WIDTH_ADDR_READ_B = "8" *) (* P_WIDTH_ADDR_WRITE_A = "8" *) (* P_WIDTH_ADDR_WRITE_B = "8" *) (* P_WIDTH_COL_WRITE_A = "50" *) (* P_WIDTH_COL_WRITE_B = "50" *) (* READ_DATA_WIDTH_A = "50" *) (* READ_DATA_WIDTH_B = "50" *) (* READ_LATENCY_A = "2" *) (* READ_LATENCY_B = "2" *) (* READ_RESET_VALUE_A = "0" *) (* READ_RESET_VALUE_B = "0" *) (* RST_MODE_A = "SYNC" *) (* RST_MODE_B = "SYNC" *) (* SIM_ASSERT_CHK = "0" *) (* USE_EMBEDDED_CONSTRAINT = "0" *) (* USE_MEM_INIT = "0" *) (* USE_MEM_INIT_MMI = "0" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH_A = "50" *) (* WRITE_DATA_WIDTH_B = "50" *) (* WRITE_MODE_A = "2" *) (* WRITE_MODE_B = "2" *) (* WRITE_PROTECT = "1" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "soft" *) (* rsta_loop_iter = "52" *) (* rstb_loop_iter = "52" *) module axi_chip2chip_64B66B_xpm_memory_base__2 (sleep, clka, rsta, ena, regcea, wea, addra, dina, injectsbiterra, injectdbiterra, douta, sbiterra, dbiterra, clkb, rstb, enb, regceb, web, addrb, dinb, injectsbiterrb, injectdbiterrb, doutb, sbiterrb, dbiterrb); input sleep; input clka; input rsta; input ena; input regcea; input [0:0]wea; input [7:0]addra; input [49:0]dina; input injectsbiterra; input injectdbiterra; output [49:0]douta; output sbiterra; output dbiterra; input clkb; input rstb; input enb; input regceb; input [0:0]web; input [7:0]addrb; input [49:0]dinb; input injectsbiterrb; input injectdbiterrb; output [49:0]doutb; output sbiterrb; output dbiterrb; wire \ ; wire [7:0]addra; wire [7:0]addrb; wire clka; wire clkb; wire [49:0]dina; wire [49:0]doutb; wire ena; wire enb; wire regceb; wire rstb; wire sleep; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTDBITERR_UNCONNECTED ; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTSBITERR_UNCONNECTED ; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_DBITERR_UNCONNECTED ; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_SBITERR_UNCONNECTED ; wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINA_UNCONNECTED ; wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINB_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPA_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPB_UNCONNECTED ; wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTA_UNCONNECTED ; wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTB_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPA_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPB_UNCONNECTED ; wire [31:18]\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTBDOUT_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPADOUTP_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPBDOUTP_UNCONNECTED ; wire [7:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_RDADDRECC_UNCONNECTED ; assign dbiterra = \ ; assign dbiterrb = \ ; assign douta[49] = \ ; assign douta[48] = \ ; assign douta[47] = \ ; assign douta[46] = \ ; assign douta[45] = \ ; assign douta[44] = \ ; assign douta[43] = \ ; assign douta[42] = \ ; assign douta[41] = \ ; assign douta[40] = \ ; assign douta[39] = \ ; assign douta[38] = \ ; assign douta[37] = \ ; assign douta[36] = \ ; assign douta[35] = \ ; assign douta[34] = \ ; assign douta[33] = \ ; assign douta[32] = \ ; assign douta[31] = \ ; assign douta[30] = \ ; assign douta[29] = \ ; assign douta[28] = \ ; assign douta[27] = \ ; assign douta[26] = \ ; assign douta[25] = \ ; assign douta[24] = \ ; assign douta[23] = \ ; assign douta[22] = \ ; assign douta[21] = \ ; assign douta[20] = \ ; assign douta[19] = \ ; assign douta[18] = \ ; assign douta[17] = \ ; assign douta[16] = \ ; assign douta[15] = \ ; assign douta[14] = \ ; assign douta[13] = \ ; assign douta[12] = \ ; assign douta[11] = \ ; assign douta[10] = \ ; assign douta[9] = \ ; assign douta[8] = \ ; assign douta[7] = \ ; assign douta[6] = \ ; assign douta[5] = \ ; assign douta[4] = \ ; assign douta[3] = \ ; assign douta[2] = \ ; assign douta[1] = \ ; assign douta[0] = \ ; assign sbiterra = \ ; assign sbiterrb = \ ; GND GND (.G(\ )); (* \MEM.PORTA.ADDRESS_BEGIN = "0" *) (* \MEM.PORTA.ADDRESS_END = "511" *) (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d50" *) (* \MEM.PORTA.DATA_LSB = "0" *) (* \MEM.PORTA.DATA_MSB = "49" *) (* \MEM.PORTB.ADDRESS_BEGIN = "0" *) (* \MEM.PORTB.ADDRESS_END = "511" *) (* \MEM.PORTB.DATA_BIT_LAYOUT = "p0_d50" *) (* \MEM.PORTB.DATA_LSB = "0" *) (* \MEM.PORTB.DATA_MSB = "49" *) (* METHODOLOGY_DRC_VIOS = "" *) (* RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE" *) (* RTL_RAM_BITS = "12800" *) (* RTL_RAM_NAME = "gen_wr_a.gen_word_narrow.mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "511" *) (* ram_offset = "0" *) (* ram_slice_begin = "0" *) (* ram_slice_end = "49" *) RAMB36E2 #( .CASCADE_ORDER_A("NONE"), .CASCADE_ORDER_B("NONE"), .CLOCK_DOMAINS("INDEPENDENT"), .DOA_REG(1), .DOB_REG(1), .ENADDRENA("FALSE"), .ENADDRENB("FALSE"), .EN_ECC_PIPE("FALSE"), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .RDADDRCHANGEA("FALSE"), .RDADDRCHANGEB("FALSE"), .READ_WIDTH_A(72), .READ_WIDTH_B(0), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SLEEP_ASYNC("TRUE"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("NO_CHANGE"), .WRITE_MODE_B("NO_CHANGE"), .WRITE_WIDTH_A(0), .WRITE_WIDTH_B(72)) \gen_wr_a.gen_word_narrow.mem_reg (.ADDRARDADDR({1'b0,addrb,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b0,addra,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), .ADDRENA(1'b0), .ADDRENB(1'b0), .CASDIMUXA(1'b0), .CASDIMUXB(1'b0), .CASDINA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINA_UNCONNECTED [31:0]), .CASDINB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINB_UNCONNECTED [31:0]), .CASDINPA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPA_UNCONNECTED [3:0]), .CASDINPB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPB_UNCONNECTED [3:0]), .CASDOMUXA(1'b0), .CASDOMUXB(1'b0), .CASDOMUXEN_A(1'b1), .CASDOMUXEN_B(1'b1), .CASDOUTA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTA_UNCONNECTED [31:0]), .CASDOUTB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTB_UNCONNECTED [31:0]), .CASDOUTPA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPA_UNCONNECTED [3:0]), .CASDOUTPB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPB_UNCONNECTED [3:0]), .CASINDBITERR(1'b0), .CASINSBITERR(1'b0), .CASOREGIMUXA(1'b0), .CASOREGIMUXB(1'b0), .CASOREGIMUXEN_A(1'b1), .CASOREGIMUXEN_B(1'b1), .CASOUTDBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTDBITERR_UNCONNECTED ), .CASOUTSBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTSBITERR_UNCONNECTED ), .CLKARDCLK(clkb), .CLKBWRCLK(clka), .DBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_DBITERR_UNCONNECTED ), .DINADIN(dina[31:0]), .DINBDIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,dina[49:32]}), .DINPADINP({1'b1,1'b1,1'b1,1'b1}), .DINPBDINP({1'b1,1'b1,1'b1,1'b1}), .DOUTADOUT(doutb[31:0]), .DOUTBDOUT({\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTBDOUT_UNCONNECTED [31:18],doutb[49:32]}), .DOUTPADOUTP(\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPADOUTP_UNCONNECTED [3:0]), .DOUTPBDOUTP(\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPBDOUTP_UNCONNECTED [3:0]), .ECCPARITY(\NLW_gen_wr_a.gen_word_narrow.mem_reg_ECCPARITY_UNCONNECTED [7:0]), .ECCPIPECE(1'b1), .ENARDEN(enb), .ENBWREN(ena), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_gen_wr_a.gen_word_narrow.mem_reg_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(regceb), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(rstb), .RSTREGB(1'b0), .SBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_SBITERR_UNCONNECTED ), .SLEEP(1'b0), .WEA({1'b0,1'b0,1'b0,1'b0}), .WEBWE({ena,ena,ena,ena,ena,ena,ena,ena})); endmodule (* ADDR_WIDTH_A = "9" *) (* ADDR_WIDTH_B = "9" *) (* AUTO_SLEEP_TIME = "0" *) (* BYTE_WRITE_WIDTH_A = "41" *) (* BYTE_WRITE_WIDTH_B = "41" *) (* CASCADE_HEIGHT = "0" *) (* CLOCKING_MODE = "1" *) (* ECC_MODE = "0" *) (* MAX_NUM_CHAR = "0" *) (* MEMORY_INIT_FILE = "none" *) (* MEMORY_INIT_PARAM = "" *) (* MEMORY_OPTIMIZATION = "true" *) (* MEMORY_PRIMITIVE = "2" *) (* MEMORY_SIZE = "20992" *) (* MEMORY_TYPE = "1" *) (* MESSAGE_CONTROL = "0" *) (* NUM_CHAR_LOC = "0" *) (* ORIG_REF_NAME = "xpm_memory_base" *) (* P_ECC_MODE = "no_ecc" *) (* P_ENABLE_BYTE_WRITE_A = "0" *) (* P_ENABLE_BYTE_WRITE_B = "0" *) (* P_MAX_DEPTH_DATA = "512" *) (* P_MEMORY_OPT = "yes" *) (* P_MEMORY_PRIMITIVE = "block" *) (* P_MIN_WIDTH_DATA = "41" *) (* P_MIN_WIDTH_DATA_A = "41" *) (* P_MIN_WIDTH_DATA_B = "41" *) (* P_MIN_WIDTH_DATA_ECC = "41" *) (* P_MIN_WIDTH_DATA_LDW = "4" *) (* P_MIN_WIDTH_DATA_SHFT = "41" *) (* P_NUM_COLS_WRITE_A = "1" *) (* P_NUM_COLS_WRITE_B = "1" *) (* P_NUM_ROWS_READ_A = "1" *) (* P_NUM_ROWS_READ_B = "1" *) (* P_NUM_ROWS_WRITE_A = "1" *) (* P_NUM_ROWS_WRITE_B = "1" *) (* P_SDP_WRITE_MODE = "no" *) (* P_WIDTH_ADDR_LSB_READ_A = "0" *) (* P_WIDTH_ADDR_LSB_READ_B = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_B = "0" *) (* P_WIDTH_ADDR_READ_A = "9" *) (* P_WIDTH_ADDR_READ_B = "9" *) (* P_WIDTH_ADDR_WRITE_A = "9" *) (* P_WIDTH_ADDR_WRITE_B = "9" *) (* P_WIDTH_COL_WRITE_A = "41" *) (* P_WIDTH_COL_WRITE_B = "41" *) (* READ_DATA_WIDTH_A = "41" *) (* READ_DATA_WIDTH_B = "41" *) (* READ_LATENCY_A = "2" *) (* READ_LATENCY_B = "2" *) (* READ_RESET_VALUE_A = "0" *) (* READ_RESET_VALUE_B = "0" *) (* RST_MODE_A = "SYNC" *) (* RST_MODE_B = "SYNC" *) (* SIM_ASSERT_CHK = "0" *) (* USE_EMBEDDED_CONSTRAINT = "0" *) (* USE_MEM_INIT = "0" *) (* USE_MEM_INIT_MMI = "0" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH_A = "41" *) (* WRITE_DATA_WIDTH_B = "41" *) (* WRITE_MODE_A = "2" *) (* WRITE_MODE_B = "2" *) (* WRITE_PROTECT = "1" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "soft" *) (* rsta_loop_iter = "44" *) (* rstb_loop_iter = "44" *) module axi_chip2chip_64B66B_xpm_memory_base__parameterized0 (sleep, clka, rsta, ena, regcea, wea, addra, dina, injectsbiterra, injectdbiterra, douta, sbiterra, dbiterra, clkb, rstb, enb, regceb, web, addrb, dinb, injectsbiterrb, injectdbiterrb, doutb, sbiterrb, dbiterrb); input sleep; input clka; input rsta; input ena; input regcea; input [0:0]wea; input [8:0]addra; input [40:0]dina; input injectsbiterra; input injectdbiterra; output [40:0]douta; output sbiterra; output dbiterra; input clkb; input rstb; input enb; input regceb; input [0:0]web; input [8:0]addrb; input [40:0]dinb; input injectsbiterrb; input injectdbiterrb; output [40:0]doutb; output sbiterrb; output dbiterrb; wire \ ; wire [8:0]addra; wire [8:0]addrb; wire clka; wire clkb; wire [40:0]dina; wire [40:0]doutb; wire ena; wire enb; wire regceb; wire rstb; wire sleep; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTDBITERR_UNCONNECTED ; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTSBITERR_UNCONNECTED ; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_DBITERR_UNCONNECTED ; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_SBITERR_UNCONNECTED ; wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINA_UNCONNECTED ; wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINB_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPA_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPB_UNCONNECTED ; wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTA_UNCONNECTED ; wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTB_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPA_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPB_UNCONNECTED ; wire [31:9]\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTBDOUT_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPADOUTP_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPBDOUTP_UNCONNECTED ; wire [7:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_RDADDRECC_UNCONNECTED ; assign dbiterra = \ ; assign dbiterrb = \ ; assign douta[40] = \ ; assign douta[39] = \ ; assign douta[38] = \ ; assign douta[37] = \ ; assign douta[36] = \ ; assign douta[35] = \ ; assign douta[34] = \ ; assign douta[33] = \ ; assign douta[32] = \ ; assign douta[31] = \ ; assign douta[30] = \ ; assign douta[29] = \ ; assign douta[28] = \ ; assign douta[27] = \ ; assign douta[26] = \ ; assign douta[25] = \ ; assign douta[24] = \ ; assign douta[23] = \ ; assign douta[22] = \ ; assign douta[21] = \ ; assign douta[20] = \ ; assign douta[19] = \ ; assign douta[18] = \ ; assign douta[17] = \ ; assign douta[16] = \ ; assign douta[15] = \ ; assign douta[14] = \ ; assign douta[13] = \ ; assign douta[12] = \ ; assign douta[11] = \ ; assign douta[10] = \ ; assign douta[9] = \ ; assign douta[8] = \ ; assign douta[7] = \ ; assign douta[6] = \ ; assign douta[5] = \ ; assign douta[4] = \ ; assign douta[3] = \ ; assign douta[2] = \ ; assign douta[1] = \ ; assign douta[0] = \ ; assign sbiterra = \ ; assign sbiterrb = \ ; GND GND (.G(\ )); (* \MEM.PORTA.ADDRESS_BEGIN = "0" *) (* \MEM.PORTA.ADDRESS_END = "511" *) (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d41" *) (* \MEM.PORTA.DATA_LSB = "0" *) (* \MEM.PORTA.DATA_MSB = "40" *) (* \MEM.PORTB.ADDRESS_BEGIN = "0" *) (* \MEM.PORTB.ADDRESS_END = "511" *) (* \MEM.PORTB.DATA_BIT_LAYOUT = "p0_d41" *) (* \MEM.PORTB.DATA_LSB = "0" *) (* \MEM.PORTB.DATA_MSB = "40" *) (* METHODOLOGY_DRC_VIOS = "" *) (* RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE" *) (* RTL_RAM_BITS = "20992" *) (* RTL_RAM_NAME = "gen_wr_a.gen_word_narrow.mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "511" *) (* ram_offset = "0" *) (* ram_slice_begin = "0" *) (* ram_slice_end = "40" *) RAMB36E2 #( .CASCADE_ORDER_A("NONE"), .CASCADE_ORDER_B("NONE"), .CLOCK_DOMAINS("INDEPENDENT"), .DOA_REG(1), .DOB_REG(1), .ENADDRENA("FALSE"), .ENADDRENB("FALSE"), .EN_ECC_PIPE("FALSE"), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .RDADDRCHANGEA("FALSE"), .RDADDRCHANGEB("FALSE"), .READ_WIDTH_A(72), .READ_WIDTH_B(0), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SLEEP_ASYNC("TRUE"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("NO_CHANGE"), .WRITE_MODE_B("NO_CHANGE"), .WRITE_WIDTH_A(0), .WRITE_WIDTH_B(72)) \gen_wr_a.gen_word_narrow.mem_reg (.ADDRARDADDR({addrb,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), .ADDRBWRADDR({addra,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), .ADDRENA(1'b0), .ADDRENB(1'b0), .CASDIMUXA(1'b0), .CASDIMUXB(1'b0), .CASDINA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINA_UNCONNECTED [31:0]), .CASDINB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINB_UNCONNECTED [31:0]), .CASDINPA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPA_UNCONNECTED [3:0]), .CASDINPB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPB_UNCONNECTED [3:0]), .CASDOMUXA(1'b0), .CASDOMUXB(1'b0), .CASDOMUXEN_A(1'b1), .CASDOMUXEN_B(1'b1), .CASDOUTA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTA_UNCONNECTED [31:0]), .CASDOUTB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTB_UNCONNECTED [31:0]), .CASDOUTPA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPA_UNCONNECTED [3:0]), .CASDOUTPB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPB_UNCONNECTED [3:0]), .CASINDBITERR(1'b0), .CASINSBITERR(1'b0), .CASOREGIMUXA(1'b0), .CASOREGIMUXB(1'b0), .CASOREGIMUXEN_A(1'b1), .CASOREGIMUXEN_B(1'b1), .CASOUTDBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTDBITERR_UNCONNECTED ), .CASOUTSBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTSBITERR_UNCONNECTED ), .CLKARDCLK(clkb), .CLKBWRCLK(clka), .DBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_DBITERR_UNCONNECTED ), .DINADIN(dina[31:0]), .DINBDIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,dina[40:32]}), .DINPADINP({1'b1,1'b1,1'b1,1'b1}), .DINPBDINP({1'b1,1'b1,1'b1,1'b1}), .DOUTADOUT(doutb[31:0]), .DOUTBDOUT({\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTBDOUT_UNCONNECTED [31:9],doutb[40:32]}), .DOUTPADOUTP(\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPADOUTP_UNCONNECTED [3:0]), .DOUTPBDOUTP(\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPBDOUTP_UNCONNECTED [3:0]), .ECCPARITY(\NLW_gen_wr_a.gen_word_narrow.mem_reg_ECCPARITY_UNCONNECTED [7:0]), .ECCPIPECE(1'b1), .ENARDEN(enb), .ENBWREN(ena), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_gen_wr_a.gen_word_narrow.mem_reg_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(regceb), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(rstb), .RSTREGB(1'b0), .SBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_SBITERR_UNCONNECTED ), .SLEEP(1'b0), .WEA({1'b0,1'b0,1'b0,1'b0}), .WEBWE({ena,ena,ena,ena,ena,ena,ena,ena})); endmodule (* ADDR_WIDTH_A = "9" *) (* ADDR_WIDTH_B = "9" *) (* AUTO_SLEEP_TIME = "0" *) (* BYTE_WRITE_WIDTH_A = "41" *) (* BYTE_WRITE_WIDTH_B = "41" *) (* CASCADE_HEIGHT = "0" *) (* CLOCKING_MODE = "1" *) (* ECC_MODE = "0" *) (* MAX_NUM_CHAR = "0" *) (* MEMORY_INIT_FILE = "none" *) (* MEMORY_INIT_PARAM = "" *) (* MEMORY_OPTIMIZATION = "true" *) (* MEMORY_PRIMITIVE = "2" *) (* MEMORY_SIZE = "20992" *) (* MEMORY_TYPE = "1" *) (* MESSAGE_CONTROL = "0" *) (* NUM_CHAR_LOC = "0" *) (* ORIG_REF_NAME = "xpm_memory_base" *) (* P_ECC_MODE = "no_ecc" *) (* P_ENABLE_BYTE_WRITE_A = "0" *) (* P_ENABLE_BYTE_WRITE_B = "0" *) (* P_MAX_DEPTH_DATA = "512" *) (* P_MEMORY_OPT = "yes" *) (* P_MEMORY_PRIMITIVE = "block" *) (* P_MIN_WIDTH_DATA = "41" *) (* P_MIN_WIDTH_DATA_A = "41" *) (* P_MIN_WIDTH_DATA_B = "41" *) (* P_MIN_WIDTH_DATA_ECC = "41" *) (* P_MIN_WIDTH_DATA_LDW = "4" *) (* P_MIN_WIDTH_DATA_SHFT = "41" *) (* P_NUM_COLS_WRITE_A = "1" *) (* P_NUM_COLS_WRITE_B = "1" *) (* P_NUM_ROWS_READ_A = "1" *) (* P_NUM_ROWS_READ_B = "1" *) (* P_NUM_ROWS_WRITE_A = "1" *) (* P_NUM_ROWS_WRITE_B = "1" *) (* P_SDP_WRITE_MODE = "no" *) (* P_WIDTH_ADDR_LSB_READ_A = "0" *) (* P_WIDTH_ADDR_LSB_READ_B = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_B = "0" *) (* P_WIDTH_ADDR_READ_A = "9" *) (* P_WIDTH_ADDR_READ_B = "9" *) (* P_WIDTH_ADDR_WRITE_A = "9" *) (* P_WIDTH_ADDR_WRITE_B = "9" *) (* P_WIDTH_COL_WRITE_A = "41" *) (* P_WIDTH_COL_WRITE_B = "41" *) (* READ_DATA_WIDTH_A = "41" *) (* READ_DATA_WIDTH_B = "41" *) (* READ_LATENCY_A = "2" *) (* READ_LATENCY_B = "2" *) (* READ_RESET_VALUE_A = "0" *) (* READ_RESET_VALUE_B = "0" *) (* RST_MODE_A = "SYNC" *) (* RST_MODE_B = "SYNC" *) (* SIM_ASSERT_CHK = "0" *) (* USE_EMBEDDED_CONSTRAINT = "0" *) (* USE_MEM_INIT = "0" *) (* USE_MEM_INIT_MMI = "0" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH_A = "41" *) (* WRITE_DATA_WIDTH_B = "41" *) (* WRITE_MODE_A = "2" *) (* WRITE_MODE_B = "2" *) (* WRITE_PROTECT = "1" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "soft" *) (* rsta_loop_iter = "44" *) (* rstb_loop_iter = "44" *) module axi_chip2chip_64B66B_xpm_memory_base__parameterized0__2 (sleep, clka, rsta, ena, regcea, wea, addra, dina, injectsbiterra, injectdbiterra, douta, sbiterra, dbiterra, clkb, rstb, enb, regceb, web, addrb, dinb, injectsbiterrb, injectdbiterrb, doutb, sbiterrb, dbiterrb); input sleep; input clka; input rsta; input ena; input regcea; input [0:0]wea; input [8:0]addra; input [40:0]dina; input injectsbiterra; input injectdbiterra; output [40:0]douta; output sbiterra; output dbiterra; input clkb; input rstb; input enb; input regceb; input [0:0]web; input [8:0]addrb; input [40:0]dinb; input injectsbiterrb; input injectdbiterrb; output [40:0]doutb; output sbiterrb; output dbiterrb; wire \ ; wire [8:0]addra; wire [8:0]addrb; wire clka; wire clkb; wire [40:0]dina; wire [40:0]doutb; wire ena; wire enb; wire regceb; wire rstb; wire sleep; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTDBITERR_UNCONNECTED ; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTSBITERR_UNCONNECTED ; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_DBITERR_UNCONNECTED ; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_SBITERR_UNCONNECTED ; wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINA_UNCONNECTED ; wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINB_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPA_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPB_UNCONNECTED ; wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTA_UNCONNECTED ; wire [31:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTB_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPA_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPB_UNCONNECTED ; wire [31:9]\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTBDOUT_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPADOUTP_UNCONNECTED ; wire [3:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPBDOUTP_UNCONNECTED ; wire [7:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_ECCPARITY_UNCONNECTED ; wire [8:0]\NLW_gen_wr_a.gen_word_narrow.mem_reg_RDADDRECC_UNCONNECTED ; assign dbiterra = \ ; assign dbiterrb = \ ; assign douta[40] = \ ; assign douta[39] = \ ; assign douta[38] = \ ; assign douta[37] = \ ; assign douta[36] = \ ; assign douta[35] = \ ; assign douta[34] = \ ; assign douta[33] = \ ; assign douta[32] = \ ; assign douta[31] = \ ; assign douta[30] = \ ; assign douta[29] = \ ; assign douta[28] = \ ; assign douta[27] = \ ; assign douta[26] = \ ; assign douta[25] = \ ; assign douta[24] = \ ; assign douta[23] = \ ; assign douta[22] = \ ; assign douta[21] = \ ; assign douta[20] = \ ; assign douta[19] = \ ; assign douta[18] = \ ; assign douta[17] = \ ; assign douta[16] = \ ; assign douta[15] = \ ; assign douta[14] = \ ; assign douta[13] = \ ; assign douta[12] = \ ; assign douta[11] = \ ; assign douta[10] = \ ; assign douta[9] = \ ; assign douta[8] = \ ; assign douta[7] = \ ; assign douta[6] = \ ; assign douta[5] = \ ; assign douta[4] = \ ; assign douta[3] = \ ; assign douta[2] = \ ; assign douta[1] = \ ; assign douta[0] = \ ; assign sbiterra = \ ; assign sbiterrb = \ ; GND GND (.G(\ )); (* \MEM.PORTA.ADDRESS_BEGIN = "0" *) (* \MEM.PORTA.ADDRESS_END = "511" *) (* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d41" *) (* \MEM.PORTA.DATA_LSB = "0" *) (* \MEM.PORTA.DATA_MSB = "40" *) (* \MEM.PORTB.ADDRESS_BEGIN = "0" *) (* \MEM.PORTB.ADDRESS_END = "511" *) (* \MEM.PORTB.DATA_BIT_LAYOUT = "p0_d41" *) (* \MEM.PORTB.DATA_LSB = "0" *) (* \MEM.PORTB.DATA_MSB = "40" *) (* METHODOLOGY_DRC_VIOS = "" *) (* RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE" *) (* RTL_RAM_BITS = "20992" *) (* RTL_RAM_NAME = "gen_wr_a.gen_word_narrow.mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "511" *) (* ram_offset = "0" *) (* ram_slice_begin = "0" *) (* ram_slice_end = "40" *) RAMB36E2 #( .CASCADE_ORDER_A("NONE"), .CASCADE_ORDER_B("NONE"), .CLOCK_DOMAINS("INDEPENDENT"), .DOA_REG(1), .DOB_REG(1), .ENADDRENA("FALSE"), .ENADDRENB("FALSE"), .EN_ECC_PIPE("FALSE"), .EN_ECC_READ("FALSE"), .EN_ECC_WRITE("FALSE"), .INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_A(36'h000000000), .INIT_B(36'h000000000), .INIT_FILE("NONE"), .RDADDRCHANGEA("FALSE"), .RDADDRCHANGEB("FALSE"), .READ_WIDTH_A(72), .READ_WIDTH_B(0), .RSTREG_PRIORITY_A("RSTREG"), .RSTREG_PRIORITY_B("RSTREG"), .SIM_COLLISION_CHECK("ALL"), .SLEEP_ASYNC("TRUE"), .SRVAL_A(36'h000000000), .SRVAL_B(36'h000000000), .WRITE_MODE_A("NO_CHANGE"), .WRITE_MODE_B("NO_CHANGE"), .WRITE_WIDTH_A(0), .WRITE_WIDTH_B(72)) \gen_wr_a.gen_word_narrow.mem_reg (.ADDRARDADDR({addrb,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), .ADDRBWRADDR({addra,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), .ADDRENA(1'b0), .ADDRENB(1'b0), .CASDIMUXA(1'b0), .CASDIMUXB(1'b0), .CASDINA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINA_UNCONNECTED [31:0]), .CASDINB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINB_UNCONNECTED [31:0]), .CASDINPA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPA_UNCONNECTED [3:0]), .CASDINPB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDINPB_UNCONNECTED [3:0]), .CASDOMUXA(1'b0), .CASDOMUXB(1'b0), .CASDOMUXEN_A(1'b1), .CASDOMUXEN_B(1'b1), .CASDOUTA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTA_UNCONNECTED [31:0]), .CASDOUTB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTB_UNCONNECTED [31:0]), .CASDOUTPA(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPA_UNCONNECTED [3:0]), .CASDOUTPB(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASDOUTPB_UNCONNECTED [3:0]), .CASINDBITERR(1'b0), .CASINSBITERR(1'b0), .CASOREGIMUXA(1'b0), .CASOREGIMUXB(1'b0), .CASOREGIMUXEN_A(1'b1), .CASOREGIMUXEN_B(1'b1), .CASOUTDBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTDBITERR_UNCONNECTED ), .CASOUTSBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_CASOUTSBITERR_UNCONNECTED ), .CLKARDCLK(clkb), .CLKBWRCLK(clka), .DBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_DBITERR_UNCONNECTED ), .DINADIN(dina[31:0]), .DINBDIN({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,dina[40:32]}), .DINPADINP({1'b1,1'b1,1'b1,1'b1}), .DINPBDINP({1'b1,1'b1,1'b1,1'b1}), .DOUTADOUT(doutb[31:0]), .DOUTBDOUT({\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTBDOUT_UNCONNECTED [31:9],doutb[40:32]}), .DOUTPADOUTP(\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPADOUTP_UNCONNECTED [3:0]), .DOUTPBDOUTP(\NLW_gen_wr_a.gen_word_narrow.mem_reg_DOUTPBDOUTP_UNCONNECTED [3:0]), .ECCPARITY(\NLW_gen_wr_a.gen_word_narrow.mem_reg_ECCPARITY_UNCONNECTED [7:0]), .ECCPIPECE(1'b1), .ENARDEN(enb), .ENBWREN(ena), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .RDADDRECC(\NLW_gen_wr_a.gen_word_narrow.mem_reg_RDADDRECC_UNCONNECTED [8:0]), .REGCEAREGCE(regceb), .REGCEB(1'b0), .RSTRAMARSTRAM(1'b0), .RSTRAMB(1'b0), .RSTREGARSTREG(rstb), .RSTREGB(1'b0), .SBITERR(\NLW_gen_wr_a.gen_word_narrow.mem_reg_SBITERR_UNCONNECTED ), .SLEEP(1'b0), .WEA({1'b0,1'b0,1'b0,1'b0}), .WEBWE({ena,ena,ena,ena,ena,ena,ena,ena})); endmodule (* ADDR_WIDTH_A = "8" *) (* ADDR_WIDTH_B = "8" *) (* AUTO_SLEEP_TIME = "0" *) (* BYTE_WRITE_WIDTH_A = "8" *) (* BYTE_WRITE_WIDTH_B = "8" *) (* CASCADE_HEIGHT = "0" *) (* CLOCKING_MODE = "1" *) (* ECC_MODE = "0" *) (* MAX_NUM_CHAR = "0" *) (* MEMORY_INIT_FILE = "none" *) (* MEMORY_INIT_PARAM = "" *) (* MEMORY_OPTIMIZATION = "true" *) (* MEMORY_PRIMITIVE = "1" *) (* MEMORY_SIZE = "2048" *) (* MEMORY_TYPE = "1" *) (* MESSAGE_CONTROL = "0" *) (* NUM_CHAR_LOC = "0" *) (* ORIG_REF_NAME = "xpm_memory_base" *) (* P_ECC_MODE = "no_ecc" *) (* P_ENABLE_BYTE_WRITE_A = "0" *) (* P_ENABLE_BYTE_WRITE_B = "0" *) (* P_MAX_DEPTH_DATA = "256" *) (* P_MEMORY_OPT = "yes" *) (* P_MEMORY_PRIMITIVE = "distributed" *) (* P_MIN_WIDTH_DATA = "8" *) (* P_MIN_WIDTH_DATA_A = "8" *) (* P_MIN_WIDTH_DATA_B = "8" *) (* P_MIN_WIDTH_DATA_ECC = "8" *) (* P_MIN_WIDTH_DATA_LDW = "4" *) (* P_MIN_WIDTH_DATA_SHFT = "8" *) (* P_NUM_COLS_WRITE_A = "1" *) (* P_NUM_COLS_WRITE_B = "1" *) (* P_NUM_ROWS_READ_A = "1" *) (* P_NUM_ROWS_READ_B = "1" *) (* P_NUM_ROWS_WRITE_A = "1" *) (* P_NUM_ROWS_WRITE_B = "1" *) (* P_SDP_WRITE_MODE = "yes" *) (* P_WIDTH_ADDR_LSB_READ_A = "0" *) (* P_WIDTH_ADDR_LSB_READ_B = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_A = "0" *) (* P_WIDTH_ADDR_LSB_WRITE_B = "0" *) (* P_WIDTH_ADDR_READ_A = "8" *) (* P_WIDTH_ADDR_READ_B = "8" *) (* P_WIDTH_ADDR_WRITE_A = "8" *) (* P_WIDTH_ADDR_WRITE_B = "8" *) (* P_WIDTH_COL_WRITE_A = "8" *) (* P_WIDTH_COL_WRITE_B = "8" *) (* READ_DATA_WIDTH_A = "8" *) (* READ_DATA_WIDTH_B = "8" *) (* READ_LATENCY_A = "2" *) (* READ_LATENCY_B = "2" *) (* READ_RESET_VALUE_A = "0" *) (* READ_RESET_VALUE_B = "0" *) (* RST_MODE_A = "SYNC" *) (* RST_MODE_B = "SYNC" *) (* SIM_ASSERT_CHK = "0" *) (* USE_EMBEDDED_CONSTRAINT = "1" *) (* USE_MEM_INIT = "0" *) (* USE_MEM_INIT_MMI = "0" *) (* VERSION = "0" *) (* WAKEUP_TIME = "0" *) (* WRITE_DATA_WIDTH_A = "8" *) (* WRITE_DATA_WIDTH_B = "8" *) (* WRITE_MODE_A = "2" *) (* WRITE_MODE_B = "1" *) (* WRITE_PROTECT = "1" *) (* XPM_MODULE = "TRUE" *) (* keep_hierarchy = "soft" *) (* rsta_loop_iter = "8" *) (* rstb_loop_iter = "8" *) module axi_chip2chip_64B66B_xpm_memory_base__parameterized1 (sleep, clka, rsta, ena, regcea, wea, addra, dina, injectsbiterra, injectdbiterra, douta, sbiterra, dbiterra, clkb, rstb, enb, regceb, web, addrb, dinb, injectsbiterrb, injectdbiterrb, doutb, sbiterrb, dbiterrb); input sleep; input clka; input rsta; input ena; input regcea; input [0:0]wea; input [7:0]addra; input [7:0]dina; input injectsbiterra; input injectdbiterra; output [7:0]douta; output sbiterra; output dbiterra; input clkb; input rstb; input enb; input regceb; input [0:0]web; input [7:0]addrb; input [7:0]dinb; input injectsbiterrb; input injectdbiterrb; output [7:0]doutb; output sbiterrb; output dbiterrb; wire \ ; wire [7:0]addra; wire [7:0]addrb; wire clka; wire clkb; wire [7:0]dina; wire [7:0]doutb; wire ena; wire enb; wire [7:0]\gen_rd_b.doutb_reg ; wire \gen_rd_b.doutb_reg_reg_pipe_10_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_11_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_12_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_13_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_14_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_15_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_16_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_17_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_18_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_19_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_1_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_20_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_21_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_22_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_23_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_24_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_25_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_26_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_27_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_28_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_29_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_2_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_30_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_31_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_32_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_33_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_34_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_3_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_4_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_7_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_8_reg_n_0 ; wire \gen_rd_b.doutb_reg_reg_pipe_9_reg_n_0 ; wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_i_1_n_0 ; wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_0 ; wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_1 ; wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_2 ; wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_3 ; wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_4 ; wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_5 ; wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_6 ; wire \gen_wr_a.gen_word_narrow.mem_reg_0_63_7_7_n_0 ; wire \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_i_1_n_0 ; wire \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_0 ; wire \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_1 ; wire \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_2 ; wire \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_3 ; wire \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_4 ; wire \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_5 ; wire \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_6 ; wire \gen_wr_a.gen_word_narrow.mem_reg_128_191_7_7_n_0 ; wire \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_i_1_n_0 ; wire \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_0 ; wire \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_1 ; wire \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_2 ; wire \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_3 ; wire \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_4 ; wire \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_5 ; wire \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_6 ; wire \gen_wr_a.gen_word_narrow.mem_reg_192_255_7_7_n_0 ; wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_i_1_n_0 ; wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_0 ; wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_1 ; wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_2 ; wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_3 ; wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_4 ; wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_5 ; wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_6 ; wire \gen_wr_a.gen_word_narrow.mem_reg_64_127_7_7_n_0 ; wire regceb; wire rstb; wire select_piped_1_reg_pipe_5_reg_n_0; wire select_piped_3_reg_pipe_6_reg_n_0; wire sleep; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_DOH_UNCONNECTED ; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_0_63_7_7_SPO_UNCONNECTED ; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_DOH_UNCONNECTED ; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_128_191_7_7_SPO_UNCONNECTED ; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_DOH_UNCONNECTED ; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_192_255_7_7_SPO_UNCONNECTED ; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_DOH_UNCONNECTED ; wire \NLW_gen_wr_a.gen_word_narrow.mem_reg_64_127_7_7_SPO_UNCONNECTED ; assign dbiterra = \ ; assign dbiterrb = \ ; assign douta[7] = \ ; assign douta[6] = \ ; assign douta[5] = \ ; assign douta[4] = \ ; assign douta[3] = \ ; assign douta[2] = \ ; assign douta[1] = \ ; assign douta[0] = \ ; assign sbiterra = \ ; assign sbiterrb = \ ; GND GND (.G(\ )); FDRE \gen_rd_b.doutb_reg_reg_pipe_10_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_6 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_10_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_11_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_5 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_11_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_12_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_5 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_12_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_13_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_5 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_13_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_14_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_5 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_14_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_15_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_4 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_15_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_16_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_4 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_16_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_17_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_4 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_17_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_18_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_4 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_18_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_19_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_3 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_19_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_1_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_0_63_7_7_n_0 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_1_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_20_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_3 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_20_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_21_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_3 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_21_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_22_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_3 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_22_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_23_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_2 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_23_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_24_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_2 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_24_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_25_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_2 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_25_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_26_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_2 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_26_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_27_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_1 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_27_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_28_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_1 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_28_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_29_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_1 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_29_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_2_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_64_127_7_7_n_0 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_2_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_30_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_1 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_30_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_31_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_0 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_31_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_32_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_0 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_32_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_33_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_0 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_33_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_34_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_0 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_34_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_3_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_128_191_7_7_n_0 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_3_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_4_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_192_255_7_7_n_0 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_4_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_7_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_6 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_7_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_8_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_6 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_8_reg_n_0 ), .R(1'b0)); FDRE \gen_rd_b.doutb_reg_reg_pipe_9_reg (.C(clkb), .CE(enb), .D(\gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_6 ), .Q(\gen_rd_b.doutb_reg_reg_pipe_9_reg_n_0 ), .R(1'b0)); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_rd_b.gen_doutb_pipe.doutb_pipe[0][0]_i_1 (.I0(\gen_rd_b.doutb_reg_reg_pipe_34_reg_n_0 ), .I1(\gen_rd_b.doutb_reg_reg_pipe_33_reg_n_0 ), .I2(select_piped_3_reg_pipe_6_reg_n_0), .I3(\gen_rd_b.doutb_reg_reg_pipe_32_reg_n_0 ), .I4(select_piped_1_reg_pipe_5_reg_n_0), .I5(\gen_rd_b.doutb_reg_reg_pipe_31_reg_n_0 ), .O(\gen_rd_b.doutb_reg [0])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_rd_b.gen_doutb_pipe.doutb_pipe[0][1]_i_1 (.I0(\gen_rd_b.doutb_reg_reg_pipe_30_reg_n_0 ), .I1(\gen_rd_b.doutb_reg_reg_pipe_29_reg_n_0 ), .I2(select_piped_3_reg_pipe_6_reg_n_0), .I3(\gen_rd_b.doutb_reg_reg_pipe_28_reg_n_0 ), .I4(select_piped_1_reg_pipe_5_reg_n_0), .I5(\gen_rd_b.doutb_reg_reg_pipe_27_reg_n_0 ), .O(\gen_rd_b.doutb_reg [1])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_rd_b.gen_doutb_pipe.doutb_pipe[0][2]_i_1 (.I0(\gen_rd_b.doutb_reg_reg_pipe_26_reg_n_0 ), .I1(\gen_rd_b.doutb_reg_reg_pipe_25_reg_n_0 ), .I2(select_piped_3_reg_pipe_6_reg_n_0), .I3(\gen_rd_b.doutb_reg_reg_pipe_24_reg_n_0 ), .I4(select_piped_1_reg_pipe_5_reg_n_0), .I5(\gen_rd_b.doutb_reg_reg_pipe_23_reg_n_0 ), .O(\gen_rd_b.doutb_reg [2])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_rd_b.gen_doutb_pipe.doutb_pipe[0][3]_i_1 (.I0(\gen_rd_b.doutb_reg_reg_pipe_22_reg_n_0 ), .I1(\gen_rd_b.doutb_reg_reg_pipe_21_reg_n_0 ), .I2(select_piped_3_reg_pipe_6_reg_n_0), .I3(\gen_rd_b.doutb_reg_reg_pipe_20_reg_n_0 ), .I4(select_piped_1_reg_pipe_5_reg_n_0), .I5(\gen_rd_b.doutb_reg_reg_pipe_19_reg_n_0 ), .O(\gen_rd_b.doutb_reg [3])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_rd_b.gen_doutb_pipe.doutb_pipe[0][4]_i_1 (.I0(\gen_rd_b.doutb_reg_reg_pipe_18_reg_n_0 ), .I1(\gen_rd_b.doutb_reg_reg_pipe_17_reg_n_0 ), .I2(select_piped_3_reg_pipe_6_reg_n_0), .I3(\gen_rd_b.doutb_reg_reg_pipe_16_reg_n_0 ), .I4(select_piped_1_reg_pipe_5_reg_n_0), .I5(\gen_rd_b.doutb_reg_reg_pipe_15_reg_n_0 ), .O(\gen_rd_b.doutb_reg [4])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_rd_b.gen_doutb_pipe.doutb_pipe[0][5]_i_1 (.I0(\gen_rd_b.doutb_reg_reg_pipe_14_reg_n_0 ), .I1(\gen_rd_b.doutb_reg_reg_pipe_13_reg_n_0 ), .I2(select_piped_3_reg_pipe_6_reg_n_0), .I3(\gen_rd_b.doutb_reg_reg_pipe_12_reg_n_0 ), .I4(select_piped_1_reg_pipe_5_reg_n_0), .I5(\gen_rd_b.doutb_reg_reg_pipe_11_reg_n_0 ), .O(\gen_rd_b.doutb_reg [5])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_rd_b.gen_doutb_pipe.doutb_pipe[0][6]_i_1 (.I0(\gen_rd_b.doutb_reg_reg_pipe_10_reg_n_0 ), .I1(\gen_rd_b.doutb_reg_reg_pipe_9_reg_n_0 ), .I2(select_piped_3_reg_pipe_6_reg_n_0), .I3(\gen_rd_b.doutb_reg_reg_pipe_8_reg_n_0 ), .I4(select_piped_1_reg_pipe_5_reg_n_0), .I5(\gen_rd_b.doutb_reg_reg_pipe_7_reg_n_0 ), .O(\gen_rd_b.doutb_reg [6])); LUT6 #( .INIT(64'hAFA0CFCFAFA0C0C0)) \gen_rd_b.gen_doutb_pipe.doutb_pipe[0][7]_i_1 (.I0(\gen_rd_b.doutb_reg_reg_pipe_4_reg_n_0 ), .I1(\gen_rd_b.doutb_reg_reg_pipe_3_reg_n_0 ), .I2(select_piped_3_reg_pipe_6_reg_n_0), .I3(\gen_rd_b.doutb_reg_reg_pipe_2_reg_n_0 ), .I4(select_piped_1_reg_pipe_5_reg_n_0), .I5(\gen_rd_b.doutb_reg_reg_pipe_1_reg_n_0 ), .O(\gen_rd_b.doutb_reg [7])); FDRE #( .INIT(1'b0)) \gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][0] (.C(clkb), .CE(regceb), .D(\gen_rd_b.doutb_reg [0]), .Q(doutb[0]), .R(rstb)); FDRE #( .INIT(1'b0)) \gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][1] (.C(clkb), .CE(regceb), .D(\gen_rd_b.doutb_reg [1]), .Q(doutb[1]), .R(rstb)); FDRE #( .INIT(1'b0)) \gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][2] (.C(clkb), .CE(regceb), .D(\gen_rd_b.doutb_reg [2]), .Q(doutb[2]), .R(rstb)); FDRE #( .INIT(1'b0)) \gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][3] (.C(clkb), .CE(regceb), .D(\gen_rd_b.doutb_reg [3]), .Q(doutb[3]), .R(rstb)); FDRE #( .INIT(1'b0)) \gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][4] (.C(clkb), .CE(regceb), .D(\gen_rd_b.doutb_reg [4]), .Q(doutb[4]), .R(rstb)); FDRE #( .INIT(1'b0)) \gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][5] (.C(clkb), .CE(regceb), .D(\gen_rd_b.doutb_reg [5]), .Q(doutb[5]), .R(rstb)); FDRE #( .INIT(1'b0)) \gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][6] (.C(clkb), .CE(regceb), .D(\gen_rd_b.doutb_reg [6]), .Q(doutb[6]), .R(rstb)); FDRE #( .INIT(1'b0)) \gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][7] (.C(clkb), .CE(regceb), .D(\gen_rd_b.doutb_reg [7]), .Q(doutb[7]), .R(rstb)); (* METHODOLOGY_DRC_VIOS = "" *) (* RTL_RAM_BITS = "2048" *) (* RTL_RAM_NAME = "gen_wr_a.gen_word_narrow.mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* dram_emb_xdc = "yes" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "63" *) (* ram_offset = "0" *) (* ram_slice_begin = "0" *) (* ram_slice_end = "6" *) RAM64M8 #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .INIT_E(64'h0000000000000000), .INIT_F(64'h0000000000000000), .INIT_G(64'h0000000000000000), .INIT_H(64'h0000000000000000)) \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6 (.ADDRA(addrb[5:0]), .ADDRB(addrb[5:0]), .ADDRC(addrb[5:0]), .ADDRD(addrb[5:0]), .ADDRE(addrb[5:0]), .ADDRF(addrb[5:0]), .ADDRG(addrb[5:0]), .ADDRH(addra[5:0]), .DIA(dina[0]), .DIB(dina[1]), .DIC(dina[2]), .DID(dina[3]), .DIE(dina[4]), .DIF(dina[5]), .DIG(dina[6]), .DIH(1'b0), .DOA(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_0 ), .DOB(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_1 ), .DOC(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_2 ), .DOD(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_3 ), .DOE(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_4 ), .DOF(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_5 ), .DOG(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_n_6 ), .DOH(\NLW_gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_DOH_UNCONNECTED ), .WCLK(clka), .WE(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_i_1_n_0 )); LUT3 #( .INIT(8'h02)) \gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_i_1 (.I0(ena), .I1(addra[6]), .I2(addra[7]), .O(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_i_1_n_0 )); (* RTL_RAM_BITS = "2048" *) (* RTL_RAM_NAME = "gen_wr_a.gen_word_narrow.mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* dram_emb_xdc = "yes" *) (* ram_addr_begin = "0" *) (* ram_addr_end = "63" *) (* ram_offset = "0" *) (* ram_slice_begin = "7" *) (* ram_slice_end = "7" *) RAM64X1D #( .INIT(64'h0000000000000000)) \gen_wr_a.gen_word_narrow.mem_reg_0_63_7_7 (.A0(addra[0]), .A1(addra[1]), .A2(addra[2]), .A3(addra[3]), .A4(addra[4]), .A5(addra[5]), .D(dina[7]), .DPO(\gen_wr_a.gen_word_narrow.mem_reg_0_63_7_7_n_0 ), .DPRA0(addrb[0]), .DPRA1(addrb[1]), .DPRA2(addrb[2]), .DPRA3(addrb[3]), .DPRA4(addrb[4]), .DPRA5(addrb[5]), .SPO(\NLW_gen_wr_a.gen_word_narrow.mem_reg_0_63_7_7_SPO_UNCONNECTED ), .WCLK(clka), .WE(\gen_wr_a.gen_word_narrow.mem_reg_0_63_0_6_i_1_n_0 )); (* METHODOLOGY_DRC_VIOS = "" *) (* RTL_RAM_BITS = "2048" *) (* RTL_RAM_NAME = "gen_wr_a.gen_word_narrow.mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* dram_emb_xdc = "yes" *) (* ram_addr_begin = "128" *) (* ram_addr_end = "191" *) (* ram_offset = "0" *) (* ram_slice_begin = "0" *) (* ram_slice_end = "6" *) RAM64M8 #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .INIT_E(64'h0000000000000000), .INIT_F(64'h0000000000000000), .INIT_G(64'h0000000000000000), .INIT_H(64'h0000000000000000)) \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6 (.ADDRA(addrb[5:0]), .ADDRB(addrb[5:0]), .ADDRC(addrb[5:0]), .ADDRD(addrb[5:0]), .ADDRE(addrb[5:0]), .ADDRF(addrb[5:0]), .ADDRG(addrb[5:0]), .ADDRH(addra[5:0]), .DIA(dina[0]), .DIB(dina[1]), .DIC(dina[2]), .DID(dina[3]), .DIE(dina[4]), .DIF(dina[5]), .DIG(dina[6]), .DIH(1'b0), .DOA(\gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_0 ), .DOB(\gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_1 ), .DOC(\gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_2 ), .DOD(\gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_3 ), .DOE(\gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_4 ), .DOF(\gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_5 ), .DOG(\gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_n_6 ), .DOH(\NLW_gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_DOH_UNCONNECTED ), .WCLK(clka), .WE(\gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_i_1_n_0 )); LUT3 #( .INIT(8'h40)) \gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_i_1 (.I0(addra[6]), .I1(addra[7]), .I2(ena), .O(\gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_i_1_n_0 )); (* RTL_RAM_BITS = "2048" *) (* RTL_RAM_NAME = "gen_wr_a.gen_word_narrow.mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* dram_emb_xdc = "yes" *) (* ram_addr_begin = "128" *) (* ram_addr_end = "191" *) (* ram_offset = "0" *) (* ram_slice_begin = "7" *) (* ram_slice_end = "7" *) RAM64X1D #( .INIT(64'h0000000000000000)) \gen_wr_a.gen_word_narrow.mem_reg_128_191_7_7 (.A0(addra[0]), .A1(addra[1]), .A2(addra[2]), .A3(addra[3]), .A4(addra[4]), .A5(addra[5]), .D(dina[7]), .DPO(\gen_wr_a.gen_word_narrow.mem_reg_128_191_7_7_n_0 ), .DPRA0(addrb[0]), .DPRA1(addrb[1]), .DPRA2(addrb[2]), .DPRA3(addrb[3]), .DPRA4(addrb[4]), .DPRA5(addrb[5]), .SPO(\NLW_gen_wr_a.gen_word_narrow.mem_reg_128_191_7_7_SPO_UNCONNECTED ), .WCLK(clka), .WE(\gen_wr_a.gen_word_narrow.mem_reg_128_191_0_6_i_1_n_0 )); (* METHODOLOGY_DRC_VIOS = "" *) (* RTL_RAM_BITS = "2048" *) (* RTL_RAM_NAME = "gen_wr_a.gen_word_narrow.mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* dram_emb_xdc = "yes" *) (* ram_addr_begin = "192" *) (* ram_addr_end = "255" *) (* ram_offset = "0" *) (* ram_slice_begin = "0" *) (* ram_slice_end = "6" *) RAM64M8 #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .INIT_E(64'h0000000000000000), .INIT_F(64'h0000000000000000), .INIT_G(64'h0000000000000000), .INIT_H(64'h0000000000000000)) \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6 (.ADDRA(addrb[5:0]), .ADDRB(addrb[5:0]), .ADDRC(addrb[5:0]), .ADDRD(addrb[5:0]), .ADDRE(addrb[5:0]), .ADDRF(addrb[5:0]), .ADDRG(addrb[5:0]), .ADDRH(addra[5:0]), .DIA(dina[0]), .DIB(dina[1]), .DIC(dina[2]), .DID(dina[3]), .DIE(dina[4]), .DIF(dina[5]), .DIG(dina[6]), .DIH(1'b0), .DOA(\gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_0 ), .DOB(\gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_1 ), .DOC(\gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_2 ), .DOD(\gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_3 ), .DOE(\gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_4 ), .DOF(\gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_5 ), .DOG(\gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_n_6 ), .DOH(\NLW_gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_DOH_UNCONNECTED ), .WCLK(clka), .WE(\gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_i_1_n_0 )); LUT3 #( .INIT(8'h80)) \gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_i_1 (.I0(ena), .I1(addra[6]), .I2(addra[7]), .O(\gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_i_1_n_0 )); (* RTL_RAM_BITS = "2048" *) (* RTL_RAM_NAME = "gen_wr_a.gen_word_narrow.mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* dram_emb_xdc = "yes" *) (* ram_addr_begin = "192" *) (* ram_addr_end = "255" *) (* ram_offset = "0" *) (* ram_slice_begin = "7" *) (* ram_slice_end = "7" *) RAM64X1D #( .INIT(64'h0000000000000000)) \gen_wr_a.gen_word_narrow.mem_reg_192_255_7_7 (.A0(addra[0]), .A1(addra[1]), .A2(addra[2]), .A3(addra[3]), .A4(addra[4]), .A5(addra[5]), .D(dina[7]), .DPO(\gen_wr_a.gen_word_narrow.mem_reg_192_255_7_7_n_0 ), .DPRA0(addrb[0]), .DPRA1(addrb[1]), .DPRA2(addrb[2]), .DPRA3(addrb[3]), .DPRA4(addrb[4]), .DPRA5(addrb[5]), .SPO(\NLW_gen_wr_a.gen_word_narrow.mem_reg_192_255_7_7_SPO_UNCONNECTED ), .WCLK(clka), .WE(\gen_wr_a.gen_word_narrow.mem_reg_192_255_0_6_i_1_n_0 )); (* METHODOLOGY_DRC_VIOS = "" *) (* RTL_RAM_BITS = "2048" *) (* RTL_RAM_NAME = "gen_wr_a.gen_word_narrow.mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* dram_emb_xdc = "yes" *) (* ram_addr_begin = "64" *) (* ram_addr_end = "127" *) (* ram_offset = "0" *) (* ram_slice_begin = "0" *) (* ram_slice_end = "6" *) RAM64M8 #( .INIT_A(64'h0000000000000000), .INIT_B(64'h0000000000000000), .INIT_C(64'h0000000000000000), .INIT_D(64'h0000000000000000), .INIT_E(64'h0000000000000000), .INIT_F(64'h0000000000000000), .INIT_G(64'h0000000000000000), .INIT_H(64'h0000000000000000)) \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6 (.ADDRA(addrb[5:0]), .ADDRB(addrb[5:0]), .ADDRC(addrb[5:0]), .ADDRD(addrb[5:0]), .ADDRE(addrb[5:0]), .ADDRF(addrb[5:0]), .ADDRG(addrb[5:0]), .ADDRH(addra[5:0]), .DIA(dina[0]), .DIB(dina[1]), .DIC(dina[2]), .DID(dina[3]), .DIE(dina[4]), .DIF(dina[5]), .DIG(dina[6]), .DIH(1'b0), .DOA(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_0 ), .DOB(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_1 ), .DOC(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_2 ), .DOD(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_3 ), .DOE(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_4 ), .DOF(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_5 ), .DOG(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_n_6 ), .DOH(\NLW_gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_DOH_UNCONNECTED ), .WCLK(clka), .WE(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_i_1_n_0 )); LUT3 #( .INIT(8'h40)) \gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_i_1 (.I0(addra[7]), .I1(addra[6]), .I2(ena), .O(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_i_1_n_0 )); (* RTL_RAM_BITS = "2048" *) (* RTL_RAM_NAME = "gen_wr_a.gen_word_narrow.mem" *) (* RTL_RAM_TYPE = "RAM_SDP" *) (* dram_emb_xdc = "yes" *) (* ram_addr_begin = "64" *) (* ram_addr_end = "127" *) (* ram_offset = "0" *) (* ram_slice_begin = "7" *) (* ram_slice_end = "7" *) RAM64X1D #( .INIT(64'h0000000000000000)) \gen_wr_a.gen_word_narrow.mem_reg_64_127_7_7 (.A0(addra[0]), .A1(addra[1]), .A2(addra[2]), .A3(addra[3]), .A4(addra[4]), .A5(addra[5]), .D(dina[7]), .DPO(\gen_wr_a.gen_word_narrow.mem_reg_64_127_7_7_n_0 ), .DPRA0(addrb[0]), .DPRA1(addrb[1]), .DPRA2(addrb[2]), .DPRA3(addrb[3]), .DPRA4(addrb[4]), .DPRA5(addrb[5]), .SPO(\NLW_gen_wr_a.gen_word_narrow.mem_reg_64_127_7_7_SPO_UNCONNECTED ), .WCLK(clka), .WE(\gen_wr_a.gen_word_narrow.mem_reg_64_127_0_6_i_1_n_0 )); FDRE select_piped_1_reg_pipe_5_reg (.C(clkb), .CE(enb), .D(addrb[6]), .Q(select_piped_1_reg_pipe_5_reg_n_0), .R(1'b0)); FDRE select_piped_3_reg_pipe_6_reg (.C(clkb), .CE(enb), .D(addrb[7]), .Q(select_piped_3_reg_pipe_6_reg_n_0), .R(1'b0)); endmodule `pragma protect begin_protected `pragma protect version = 1 `pragma protect encrypt_agent = "XILINX" `pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2020.2" `pragma protect key_keyowner="Cadence Design Systems.", key_keyname="cds_rsa_key", key_method="rsa" `pragma protect encoding = (enctype="BASE64", line_length=76, bytes=64) `pragma protect key_block Smodsvllcvd6MuPfdHlFmvR8p+Pe7f/pUBu/EPfJ2zZ5ctuddGasm68DT7c1GLZh6gDWLRVWzeFo 7fcCmPmHOg== `pragma protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa" `pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128) `pragma protect key_block s2mDZJeKjJsKFE8Xp2XRbJCl6T2FNVLRNeAmU/UqqR05MWC75Dr4jE6br+1fqFRpw3qEraDZBccO 2KWWAdJBHQOh1fufTlMCJJJEIWl4RL3bkCRsGDbIquWw0kVLdFyOEx6Lt14PvUyTuHVmV8wLyqrH yrV4YPFXV6ypwrcRjr8= `pragma protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa" `pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) `pragma protect key_block x+7/agT4n/d9u1QQInxgxce2jZanNSpIonCHAMN9TwcrlJrdb8ZfXZRtPg5W5uDzAYwFlpOMaH7J K0bU2N1bJd5SulzzWFr2xmwWwHkajiQbUTVM/qR72fbwtXA37wmHeH5Tj2maA3ysmVCEOBf+PzRU Skp4HmB39p3hznf7ivb9O+sIfUNHxZBRzkiGh0ybjA8gVC3hy9NdrtQe0RHj+KDnauKeW/7F5h28 Wru9E7eo717pSBIWiXC0+XEYHLyZH8UN1U/iAvPNkpqEn4OvzptabgKAiRn6ijsrWWhVztYbGXt2 qOtTlmttFPVT2ywiD8/sG81mWcXtkBnjurP1Bw== `pragma protect key_keyowner="ATRENTA", key_keyname="ATR-SG-2015-RSA-3", key_method="rsa" `pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) `pragma protect key_block a+uyg/DogHrar2B20X0VgKpDYxx8u5tU3WA15lXV858Y9HTfE/D5Ryjp0R5g+o4hU/5agZ7PQugj +Mvi/rKN+IHrEnVKSjN5RJGFUfDKEXQdedEiVI1lKvTljh6/DbxkqYVn8yzilcIXSBDhoq5uXOcx Mwmzc2s6rW0NV5Q8EbxCcgTrGYzpifzEoYV0jTlScpaPkDqnEcq5FfdczU1m49BoU+M4J77FaKjN pv9iayEPhHjY2K5BE74HpvcRAZiQ5f6Gm3FLXXd/9cLd2FDmDBtno+HFPjWV03VK9Wa3oqggUaWc 2+IraP0j0iYXzF9j3MybI+65W/eukw9H5L3ICg== `pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VELOCE-RSA", key_method="rsa" `pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128) `pragma protect key_block pIB9TJIKMKujbrZdwkCbRqImY/XmmtgVYJYP8sQJB8aidnWCgifLnFKwPxN8+uM6n92XDeuSl2uf spMy7uFl+uyL+JqlCjJUGfHM+H03Wu2cccoisOYpY+XRV9nieltHFTy8wDgpVV0w3KMf+UV1TZtt 4ztD5z48R4BbG/Ue0sk= `pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-2", key_method="rsa" `pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) `pragma protect key_block Vn0eykMtydiA29PmAvGfWqzU/OcR9L9ZRcvug6TYIDc7Wxv5/GyVdGrNdRktD0f9KubgBa0urkHZ OVAc1qpm7pKiLBUVlFacwXaioX9Q1FD1SAxilHWB5ltYgZegy2ez2lryio4r3lIYsEXOpFFCfoTj JjvYIAKkVicZbUdPFn9Cw7BgtAyIBox5+wMxN4Woz2ieR6XD0tXW5bIK6OUZiDKv6cMDmQ7o/QLx ki3QAGoSbICwuLgoE01RbtjZTocaCLZT+wrDC/IcJB+d70CbAiRE5s6cmmTsX/12AcCznkVRMaTv CR0SNb0Ps+0ZVYz9aKP8giXb5qLYBT0vftbPPg== `pragma protect key_keyowner="Real Intent", key_keyname="RI-RSA-KEY-1", key_method="rsa" `pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) `pragma protect key_block Yt83c3DmqkpWc1KPkPbqmHqaLoT3qlzJzC6nkvkkrCh8yH/Ym2KZkrIxp3XDJeaAtDhQXBkh650y O3wUe60ck9zvA8HWGhS5BPgIw9rnangrhcvzCScfI0OfwQ6h5ZsgVFFGvkBnBgniaJ4N2G3Zujop aYKZKOok233c5nuk6znEO/qIaPnWVPy2jruPlSPfu+7OpnFaiOVBJx+VJC4YR2E6xdvjMTM4vPrQ /etKY/AYxfvM028Lxnt9Xc+CVCVOYyV5dT4unPuM89uabGBKMCLWKBA9mKxBmXNUT2MSjOds3Dut JQa6ypo8M2SEm2GGxI67ytaHq3pYFSh7UBopoA== `pragma protect key_keyowner="Metrics Technologies Inc.", key_keyname="DSim", key_method="rsa" `pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) `pragma protect key_block rWZCM2OLTdFeNt3/3w1nV8cDE8ru50QBdnwQU2vQ/RCdITRg6R67t+HHT+nMg7iJ9FgoAWWbslZP nNrhWQS1A/eoyQsI+cbuwUT7rIPRLBRpJIXKI5TnO0alZwYyePXXbSzmnbSbbxoRhXVgbY4MQ2gT 8KcbIZfsV8RKXGHsAbt8vPQSHgOXcZFD4+w2IU/VGk/KAnGsIVvTUcijNi7Q7vBbI8ceiHiKg55T nv14J6fhUXK2vndlaXvQ7Uoqcxdpu2PDWj9CiInYu5QBGzJWoMPwzfLfxB+Am5azcUDCf8FUy4IO oArsrBt5MXGK/KRLLr4vcSvW+yOxJzfrZPG8Mw== `pragma protect key_keyowner="Xilinx", key_keyname="xilinxt_2020_08", key_method="rsa" `pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) `pragma protect key_block SP+xNpp1Ho2r2B0A7yOizrsTj3eBYEq/2auUnNB7Pjs4H7cFrz5pVVFE+c9sc68Oe7YL/0e2v/jK M9zSnmOQjteVTNuriozBDU8b7ZbRl2EIwBoHjxxr3APjuHMe7B00kUieij2E3nkqNJFL0VhqMYz8 1rSTpPERO5jBUCzhjyi1cdOHrQNzt2kVY0SgJDtNz6oN07397z0su0vaN0DNs6qAu5DF5mGIdPdP vD4c7qy0B0wcB0NQPx5Gxr+54OL3AKN3BsuWEOCrY2vztdCtXoep3lXDB3fw1rOXfb0ELNDv2CtF a8UzUmODOsTlTsU5nvL0uTLS58RWaxXYE14rnQ== `pragma protect data_method = "AES128-CBC" `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 346944) `pragma protect data_block 0Sbry/NoAZtfi2lWJXw2DTsINVKQH55vJEkpHhJCPy6umyFp/H36gheOltzimgGUeKkUYhZxqgwb ptB/B3203Kvxkf8yN4+QfIo38lq8sKEUh6ucuwJggibdfcXt1vbf4g310e26d9hJpg6cS8UJhWJo yKmNA3G1K2fcCgV/HiKBfqFp7iQEHf+3Z6fqrx5JUvOcJU3dr/ygEQtEvtpnQ82PMywObM0J0tpL jcvEoz5fEOrxoT4EOX6G9XzIX6a96ST99udr54dDixW8nLMrPDKjZolJb8/XtV1haoo3V1Lrday8 hwPUb7R8og+vSQmnDFLaP05wHYeQnjS99s/eCqON43OfhowTuRTeor/18aRkfXvbYr7GkFg08nMB +X4Tz6jBnbDPXpDUDA/8j5nAp/KZ0Ooo+fMfXZll8jV/CSEFRbLpnU6HGN8vyAb/Z4BmA75ylwoy RZXKN+oZ26oIiRsgHE/suIPxGLSFOZLJGkbB6kOtocQwh2AI6tJB/E9b/jeGPu+UfoPF30878JC2 AhIatq0LeniXfx6eEAPbcNpjH2M03JllSmlq+C3+1FaVkgWjXHCe/+JZMURBsyZszLhF2ulakhBh 3zB2YUiBX4hLnWDQki/jbSerCjNxBi8jnsjzMVbquIhBy4HTHIa+vORTTP19ZgH+aMQQnQNQi6PS vZ7OJ4p3qa68X+XRCUrBRAoGUZEol8LYfRrzMyg06YjWvIQrTIS6O2FvwMd9+EH1wByGixOUwBmO ORALFO/DGKK2LXv2tLtL4pX/pSPU2XkQ3sq9Q3T08atqdyv1+ICU8IiWYEdABPuzgcMyi69aPVLn j9rtXIRktL4jZgKnjCMz/44Hm+BD94txd9OFTqRKn2d5nF1JYaDFOvCP4uILCeT2gxE7UIoeKiRT Q4L/61kogmxY6QvMLbbclcIeOuhlosF/I8REVa6iKI0yHe8FdRhFXmHsLc/Eqzwg+H/FUyrdNazS vKpWigP6p8og70+vo9r62dJ2F2ad6wFgoQFcuLQVD9CkORc10POnwSbEPpxi6jwSCEgei3fjRp53 3QsOximBD/n1digieyfJe+c+iUEDhvSL2x2B3WrIR4vPTTJ4sVqWPAGUelgwj2EgPcGe5sVbDVxa 9lIFPuCr0y6HMkSv/BDB5embgEqKg55cjP1sN9n69bU+AHPm62Gy5m29IoigG/YO0NVDTEinzvVd K5j8oJIMcv4KrnQ4g314rA6SJM8r0u/0MLy4BaKhcDwjtV/B/b0+Hfzo2raG0SYcLUlZgcBvgih1 tCo1glmExdP8K+EX4rzC4x3av9y5XonlqI+fApzulxbz5nhb8E55c/u3o8mcHrreO+tWtz2rA9NM kmPPuai4DfPFEe1i5hnQjC/+mPiT5Ztif2030icKDikbPkWUDBbKlFWwHqBQ8JnzLblvCdW9zgBq CX1ab0/6/jfYOFD/a8CxkUpi/5ps6NWWe/PkoyGAIimO/drsN8O66SWiostg+BGO5hifHCCGfK7M lIhBg8odLpfMqr6/++pM3vTfS/yXUtjVIn5xraS8v3GcJQhe1WVSgjejnautS7qr3kBwlPN1lnMk sv5KgquoHgf2Jmd1zeUEXHOTXpZRJ/L5uFIeZYJooj1AkLuS19xsn04PZnuoUiHxg3GQW86gTzf3 UOqpAx1HAslW8CFPML8//+1lsIxnzpagAjm3feujOfxNEUoVMBZctupd38IM7/QYA/GS/tS8ON/h 6J6Epw6HjLYo4zt9epOVQin7NAkzYpfq0KW0qQSf4Rv9a29fuxL9XbXCkfCwFmyHPxpYY/z1FIlB WEvw8v6UW/VOyPhysheFlIEh8VDR+87Ap8y0wkbuzHRKD26fr4K4ZXbJws9TEA2V45Ci/9b608+E GkpXMXwQqAa7VfubM9Wb5u93NJjk/0CQHIc1LdouL14GJ6JcEluZKEJaf1IVHVGiYfMsicIpPsXu fTn+hlq+Lp1WEbQDL7V2OdJ96MbIBaR3Lmnaxsr/iGV8BN9jlaL7ngDDqffjjSJxYZyCTteIXOW9 DSoGdP9QMytZV1l+W1BakCngAMq3axBnSB8IFsW8WBRUS2zKnd4pgsRuMW9QdzIp0SaJtXH/guOZ Z/KjkfF2KsLnkl5XEL8xupUl9SmSd9+oCVWRPNd6aMrCelB2vTxjAVXLZmXLnBRiSKDTN3lYhfIx c5T3CSHZz5lWzUUGi6tqvA+/lC+PIb3G7rTzusrJE5P9yahneqlrHftNor0iu0HFkuMzBI9dyewg xjTVwxLyXYi9QIw7j62zkpk0SKK63SDqPUMTEDMHYjXnQBvgxWh/klwDxf8enVZYBWdFJ4IwHkMX 0V0qSbOhFYuP3DDHZbtURymojUWwSZhd+pmtNUuceyZyo75vL2LLqw/bXqq6LrMnmoxIC40+hMeA qtZwcikx4UghOX7gJabPcrs5hLOVFe+YmKTTKFH2uQpBAK9Z1u5JfDKUFSeOVOG8QKdmrJD2/JBX dAe2zRB2slWEBETBH9ca/FrqD6J8MbcpbPagM9ZSytphYV8Q/712+eh08+A8iNGpRSc1jrFZIgEz D94LrE/cuRrsG3QnCbuzpUzxlPxsn4pMS1UnD4QOYKUNxrEHDPgWcHc4soi/E0+FRzE2cKmasJPX J6vh3Q8GhwCOV1tR7vBadJAwj0dhDWvT6P7BkTNwzp/OkZ2S7HZ9lQYicLycSfg+GKWelOLOO7TN YtiRD4+ermQ8h1NB3eDg9TowCJtjTr32JpQhagPw9MJ5+wgkwyMC2bTKc9bRKD9MPgcFp1UZRuKl fptF2RXxUt5BpFmGFGUzzsOAY50pfJgB9INO7ha9zwszgvlQka2tzyxHWIjXQpI+Ca6pDt+ybeU4 wWNO0zpQsvO/62+2qUfMM1dD4gn4GvXf05H+M8Ac+X9MOO0NCeRrr99uwxSkhb4f0xkruOHiAGdk ozwZlwm7g6swMPvgKCX4xpuCDOjaXFip1iZ3MOyaqJcV9rxwots30etLf1Kp7gT+vtE60asWc6nw 3qTCfDJloYL4ZBRA8ZcpJNFpnVn2j1lKX1pB8nUnG7Irs6cjzJTkSOYyLmCb6ylV6QYkJwl9cENn e9PPwT7Es3cUSLX8NdEVXn/5mArj8da9RaK/Hbchjlo+WdlZY0VhSMoExLD9yRmq3qbnoy62aE4U fQfBFJ5HZ4ljSuR37HZTsXam0YfGTz1x4e8xJSv29cwAtMOsakJ9DjBvmwNry25I/EszDmm4kYqS akV6k6HKp+T4bO0WPZ0gach0HXnum7+DJOAobOQ6OdCbwYwGhAk7AQ77a+HSZHm/C+DcDmrvK7c7 Z5abZTjES2w4y5qurpwQBG6PCJKUi5VuZ+n7uWS42RCrPxHPVyWSQv7VizcWgi/ENs32OXemfefm HbDoWpTfEHy+DNWCGixtjOB/B4yW3dgKSIyl8mKuYd330nfDmCGOhsAmxhzHKWKr/4BwzCLJ7q20 Sw3YL27HfmXndA92CrrVG/2ljaXFzOFx/3IaKyQfUTB1aNY74IOZtSFdB9ySGzccDDRxLfu7Qgk8 n6dfHcH80UurPGb0n6dN3GzvTzqOyBFmypVnhwsL5ZiLaArTkKLeStoM479T8jmVA5mxBUtdQ+Od vaRRF6XYhgIEQqIBKMzKgBtUEuANVC3XN1lpNPnUEdFpirIXDjo+W4WdwRopVcdfrgXApdinZs2i JfUA2i96cqzzmCgpGHNpnRCE+EuJToO8MH1x6yzYBHJUURbEf9ZHXgpL1ac8LlnSjW/NTK8o/oEr pZwcacUPO+ASom/bf+l2jvaye4fehIKePMTDZM37nCL1+xTLMWDFhj1ZWw0GluEOzwNlsIY00cUu 0At/NDIdxzSyIDu3NoSRWa01jKCXqcTip1cbiaNihcfolP8M8fC4/lgYwx4GkwyPDRgGyhhL+ATN ceEK4gierzuASlTEP4eKVgbzDOoSu9ShMxHesPpDzXHAqbn2BupiCYEA/eUjusk83WRaDJENg/ja eMfNRyuTnErimMtJKhCr/HpmpBAKr49jfe2rzAv8t5Iyaar+y7nsQ9vv8c5HJguybHMMg0FzaXD5 3tf2+mvVkEjD2BY8XRFl+YYOs+QOdnyMHR0oH9MrKIwM7S1U2zjE+WenTJ/HNvNAqz7dDU+Gxee8 F/Yn2Fcfhdf/iIdLhGykIYk7D3ytZd17jbDinJ1IdEX+m/vFYM3mScubo7Yy2DyVsj9YJTh45TA7 1bTJfbgnabI6xeGFUm5sgqUKOH4hCUeUlpkXB6usnhHBbamD5Vz8+4f7CO5/HSKksRb+RS+rCWoH E6xBubPq8lps/RVg68ORDSQX8iVw6csQl8IVvXjx0oiLzByIPExTCBE2bIA4foKd5WzRO/RquFMs l6UiVppGY+vQ5gwnyN+Pa0ioVR20m03vcENCuf8cDPu2bO71jSSao6yBsFgDB6TsCddjxwKrbw51 CmFbNGhgOpoPRg7qNGAJZNOl3wLMvlPPMf3ujoD6tOweW61O86Ul1jHuy4WkhRkUbBi4v8xIWRVC cOJ5MD59AybrQ4+GGeSCKKbH1VJuqwl48JR+0DUU49uc8J3dIDvUQRqfabJY9F4N+5zUfyoCF285 D9mac3Lm6ZlrGsPddrREy3zTrF8hzCwzenMAI5lVodHOm+dkfi8Lavwu31kV7T0USVXjJsE+81Uq KwrWQjWop6tGgaxck9bhYSxAbDtPa90OD+fsdWvpx4tau9B/sYpOqip2rKg7L4KnPpGWYnIgn7tu DNmG/dYx7xHgcrSddytlRJyN0s87AUc7+YXa4R27M9Yv4Gf0mePTWxWn5O0uGMyC/9Vm8KBQLF5B L4i4yfQRsHNEJm9oHNP7h9M5V1x5LdLc72fS6ArKMC6Y1dqu75FEc3XDRCVQgG6qBTg9rzIyd9Th +CBEm+5BwMWkIaxyydSVg2C0HzPYjgqPz6FCcN6slOl+hAfNhF+jD5IVhuhnmU+JIap6qn0I7lOV opRuAlb353GBdGkF587ZuDG+KBW+aF5eUBJPFSsrnUTKx8WD9GOHVVQoQ3aJT9TPwuFtDU+1r23v toX7ZpeG2UttkZ8JbxCPPV0QlaEXGCS0S/4qyAQE3n6nMucWgPQQwPHxUiumpoOm3y5tO/ah3Dbg xc5upI4g7f2+FqNBQLRC8mYWpZOHESpvSjZQRvs18nkwaZIgcZ7fjYt+qyuQp+q5WmJ7/7oSnZ4X NT1GPCyiaoDk4grtzNy602P2mdF8d/yZ/LLGykptmGovdIA65fTM2a3LmyX7aErcgG99HdK3MTCT 5J8C1fVACuVmI8FAhLHB6PSfhorCah2Zgt6B+YbGfMQdA19bMdfjBza6MOC457RnjkW+Q3otcJBQ Z79dOEsjScRSorEU2y/Vk/PNzHYpl0oEF+2/Un3/PLmEH6U/NwQHuv6sA+jPutkan2z/p6dlk5+x ONsLMNgurc/Ep6UAKByVTgzknPh6wkiBKBRvCfNh38By3r3YkLo9z5sAi46Mh03rgVHOvzuElrBb gVREBcwJDvsPglGUAg6IrKHSXRPiv4GMkwtujwRipkh17zkY3f5SWCiu0N9cmLyqxlsKDPrGwLoB 9a1JtVfo3fXjW2zM3nF9fBt7cRhxjFmiJMMu79jdl3KQM7GasBqUyPJC7bmlN/p1KI1mWdjQblh/ 1rFB95X7JVlGp74qNZE+iICtjLX3BJPyB3/m9QL08UOyBLIkmbnMSx/HgHK4Bd8v7L5y2EsFU9Pc BApRchz6dnuzasmW7c1bkJaZONv9ktEUTH1S0iqvf/QQa84MZ4wn6lxw9AnQYlm/YWb3DR3wtGHs wuxq9Is2zWPL4NkQWAbT3NC8dutYmJFKtEeegp94YwvMdSKSNk39CvOSVIOqi5jh0AKMb1K2AIT3 sIUSOEPx5VUwEI144hvKCPMaFNW1OhLN3HTzUWyjcUvlbQpI9whBJhND+1nEuRhesDRKxR1H1zhK lRrzAJinTRAc+J8TVqUqZft6eRMhHUBsIpmJBqBOcAJV87QFR2y+bQlQv4o/h2a0GriA3HSVD8A3 hKMzJspXjqbp0jZeyDHrhY5ZntgzAWXmlPSuy18YeNsof/qm+iK2TlyiLYGTIFjEwRON2ktOtonI 6K56dMBOIU1wYUkBp1/tWB/C7NmzuqVzkHOEW2PfbWeRiE2sxxAudKCLCItC8J6h9n3iTXh0kHa4 ZhpPCdJCEI/oUqPyBnP5kpK+7ulzTUxU5VAUwRpTiaySVvPNMqKtwMkBO2aifRVNqU6B14Z6WYFe cxV2mKamCKktxot2HfYI8nk0meAEfPhvUyM00C0xeZKN2iHa+5+xfkxGtsun42OjshqisxlrE2Sa X22iRSLzbWRCxe04l3P4oVxlSFUIosN6Arnx8iKV7FpHElwdVIfhe6ZASxe5usnzLyKYWT9yjg1r YY8kbf7FGs8QjFeXuBmoIGv5Wc7EFaJ/LjB+lEB41gZrPd3TTwdNbzfqZarfxCjieGerFCr59Vp8 zTwzhPp03WG9NFN7E1CoTGQzcBSDhOzjIA3GVtonqEg3xHtdEbQghd4aygzjBWhN+uTouZlbzEzf 2gjLWr241vSYWpTWrLRqJLrlbz4f5zfmCBFM9oMO1O9GRYk0c2syGWQTnfalx1HyPv5IykeA9oiC PtmOjbJ0BTQ2hf9XVrYnB3RzM2dbRBtjrj21eNgNWH/YrIhhj8CmH6LRdyMW2HwyItSWeetNgLAF /RPOZZAMcRJhQIvgmHhurKIJosSh2x8PgXxAkYx1ZnD1k3JQkPOM1kTgM31x4ofTgPKhZJvToGI7 JsF3NmN1wuru6m6Zm6CcX9tM7oqOZGSDXCzosKrwOseSVwR5Gh4N9AY7a1K7q1NOUenfe4Iw/lL9 AwrjUONWgCJ8Q2Ll66Rh+mVaCOVZoAT1xoJr+Kx+M0lUSqwKlAQkXZ950yW4PrUUI5H9pHsn9MTP 5SE2oeJJ8unjwZAJTwGSlhAhjW3rA5ju9wlVK0Obf1/vn3G/4wNhY4H0SLqjlc/DgHw6d8UbwW6x 8Xa8mXt6YNAaRicfzLH/+f7RXSSyJ1IyLbKardvivoxMMMQKmWZeLCFY9kDiXTxm221oD0MtZa8f GXDOeZ9Zj3saEuwrKACyZlIVkXC5MwCXmTjdvvW01aMNOZwjDXp/L6RaJbN8By2DE9UnXcchyrVU FICKsjhpMdKrnZREHbLQvVhO9IDzyuG7J38iuMVpYhtV0XTt7OSg7MLgTMiK3LS1Zy7tfT2DzzpA I/VqaADE4oWMA9xNmqTtIEwIl8ze+t+TiKCn8DREoU3Vfe4D4t7JLVzV79ZYYAdlZRspL37F6Dx4 HHckXplqoZWDHzEd9f61mD1s0RPDj8lah4Rzh4Asrz1RFWXPdDf1DzlYj42u03ezCc/rnxcrpMzf NQwL0xKoM4rDaM8zbxMKCAJyf7RVMBjLijly29jHShcc76kJLzE3z2gQIpLMjmfgapFvum73QQ32 F1/Ww33ZLfUgnQow+E1AFxJrol+puVi3j5V6zgm+e3izE/m+CJAz5nijA8kIf3kbKfUKK0DzaMVd u7MV8ZZMyhcat+WKW/RXhrwg1rUkl0kjg26aLttDz8qAPzCzBfg34HSP8yGRstbzJwwP7bGZTQhJ JJY1piFMnLohUFTDGOZ8Fl+ZDbq2k8XEvc6YtHjF5FO5gcAeEFu8lz3djReyRtCeyxLXfmpmNc31 3yIvB7bPqd+7vUmx+v1Z4FXDtchFOdYj8WqU2ZjkfWYN816jwFEb8TOPaVyTonXMuCtpVTafR0uW QoFlfmIrAi6X7Q2drCf9gNckF1/iZPX5f7ajYAMA3y+GqdfN3q9W5uJ4tRea2smuxuZiTgMTDZlO 4+g64bWq3xxR4341HC2dCC1MocY/B7N1DmXfyRBX1OJLn1SG1UZEko6nP6NsvIP11LPFnS/ue9f5 zeNCf1MoaqHRplW6KegpGS9bcEEhj7laytxapNLv8aMOj88HpEnsKYK2/qQAgwZVnjYcHZjPN2E9 kqTSPRWrDEi0gVdTh+BlJIicNJJB0xrLDcK6M7wLbo3Klfy0JtnT+b2jhU8kMNekkOGVp4nhCwpS 3bcctvFk0RDnVuRuj8FCEum8vn01VIqQhqS6F1Q/kND5Mx5RPPvW8SqliczU4KVi824+Adfr46Er 9wkZKt98Vb0CdoJMSSQ3a6teX3pRI1mlYpAAMP5cb125qDhUdwLmLZhgsPgVUTlogE0xLa1i5k16 M9kF8oozYiyeef3aNVIURcEU0xV2vzx3tKgpp1Ega+jGi/dTuZDLb3bx4FEIkSfDseEjCpz7q6uq ffXSifG0dL1sPKw7BLKvns+Z9P1lvXBqnhkqKd3sM7CbRsyR+YVOth5gSKY3NECIRQ0zmcWIJ0zJ JHtj2LhuvmFC7lCPu6fYuNTTRMWm2FWL+IRoz718LhN2Zv+r9LnUDKgNVcxLZpbQl6Wbc8Y2uWka dQkOz0T625XDbHWJko1/gJaaaov3uE2ufuKZ2nhRTSoqXqJm0/n13FRkfHGHkF+jJGrUwzxFwQU9 l65sUWbyheLm1XpDPcbjWtA39KfTB2cowDGzzyLGmDUNzvXzPHTedKppZnz2pWhPKuwibx85CbyK FtgZmmCVTSdY4hVwHH3pKpyAEnMb9YMiVdsp09aFPQO35AL7dQ8Ah8wpnYjRekO3Ucr4W+T3l6OF wL2qBhHrvjNGMGpMYxrQfg8myOm5zno5d65tsv5Ijhrcc/ngJpJhv2ix8LEadhlThUKSz3yS5KlW 15Aj5geQlsiSBR2IZxw6dZZpz9UQOAndY+V+BcbpxoRmNH3JZwrevzl9VlWBy5GYJM2ZHwY4/3cB IcE7rcroXLZVAIrFj1k/r0Gx68VhSXWrxqFJmGyV99Bqx1YbfSzF+pB6FREY157A/+Y4ae0PikUY FWlrNX0nm6GuhBD9DMCDm7Z+c02cCfd9RpjsSNpKResFt2fDzUqpyJ61v1rsC/oti+EYksrI3om/ cF2oRi5DNK+EM8ExvT+m9wCZzVB4Vn/itHUXEXiPYtPu57GmOGzhM4fRUBv7pn35xLnqO0Ah92ax 9ywaRBk+FbrQQFgNCaBNTGgmKt4hvGI7NjhRODubid7Zlwl9Q8byJ5r460w71NnDFuARmztqNbQi MnyRy/76r3wJf9CyalEah8K2B0lyGLtFTTuCx71jT3+KAoL6IuFAsKhg6F9WxejJQYKwaQtO5kpo 412mViDsF2IRuMLUvCuWK4mDvgdUkQ8s4jL7t9OoyPr0FzoZ9hDBQyns50yvyBN5H1dx+9CD1W83 6T0by2b5y6gWaFKqgk9lutXu1qmf384aB2ySa+H717PTQLPQ8RfiovpKPzVsh2pYFFItIiCwrLbD Jc7yVqYl0ui7VjlKSIJD4oTAN4drqEeDqG9vZHLCYaSLn0dNgV7DJ5jZKWex/Gz0OxxYVm1/R4zG SZHujlndIaOl/1l+0StxtUNMROTPteZQSYIXJib0ibTxomHclZFTv0MDDQI6KDRfKYFwXrws2RTt KUdD9UyxkF6yEUVBPNkhvv6y/gW0WElSAqDf5gWCKW/a3WL5rlKdBxgiwh19/El1sHBDFrsnbaly OKgbHehXTz1Vshe+1t1tSqVYAvXIg6Ixwt96W/3KLIi1ziFcsMNCrwcUx32c6x9I4YEsQXXgTWu6 QHnIkukp/2MoaV6cZw/5yvXduBrxmVUMJSpkW6TzfFONsdV7mNWTyM0QEVzW9XTZeQxNZt4a5lK/ VT3GK7Hc9sKLZK1f4K+gjCnOkJXvSh9/N/jFZP+Qzi20Xvj/QJwn66LJoWe80TiBb2ifA2w+7wqZ x2mJxCmSayFRHoCtJpLiIDWBYfTTeRnlSDNg11Atxu+CdamecukNdbsXlvbvhq3XbZQk4qj5x9L5 GxyPNeiDKHuQ5CKteyh5HqA8vh0x+0oq0y/e/J3zAMFy+R4a2+IhHA1uk3qx/Opl9oBg+/x+4B/L EN5QLC8Fx/ZarwT8v2FtbGMdx21ld50OHQng9p2Z3fJHrwfBMtRc2pzdAavUq/Qt6rxOjZce6OZ/ vxwf1gjkxBp+dc0EaMUxk6OopAlIthcdw0FfmkodVlBgbHWCSQQaS2bOnqs0p0dJyOwG6w97i1ih CIlq8q1NXwbOep3b/wG82M9Zs+ZExtYZ+V6T71wIm+gOQ+leRaeqN6+RrgD0f3JGkl42XkiNjjET JaAGADRS4IPJy2Q0xzMxdmPBYMwk6t6qVyp/VzIyBrHKAz838UzLwtJAK7GrZcelBr7074v4sNzh ETSWYmqF9WKyJfisBkaz5IhYiZIiyN0N34Q3IdlQWO/YyGamuWOevaxv1oI0b/1HkPldi5TmoEJX DU/H2xOY7SszXdeYEYOww1y74OTCjodR+Pf95zI+hT0oTZsxdDJIGCqDxFZqjd8b+Td2oBkEDyrG cgEDp0lsaZKH6EtDKDyyz1Hnvciqr+IJINrhoJjuwWzXlDjXGtzTBqX7HKChH4JVxxyEqqlQC9Lp 9+ht8CfFGQB/2pDT2HdACe8g9nA7GOnAc9ohS970E8Zt7OZW/u/n4fM662FpBGrDi68s8tU7lbtd /uM0IlfDVNoWhyq30OMKELLOBtsBsgUBeGfIrRXK7p3sJth33KHOqf7hinoFgyuNBojIkpEpcI4R MXthQv6SzHY5ubey8JegXBlfCMaTZRPRsWgfkBeF8jA14T4utyGyMMBC/s+eJfcxrtRAVlu7cu9K 5iKlL6alN0w3gmxoXUKpOc8dtYoEL0lM/KzkA3y49aVwDrqiJNslLsbaZ2OoBNQSletW5TY9pFNv 9GwxjBXbzV0X4aADRccY+RbYWl2QBlYfIOe7mRCfkj9m+ld9mkbNy/ESU3krMAO0MU9two+KVJMQ R5UwjkiRaz5YvqD0ddmLp/1F7En+2FGTvkFxhpmfrTB+suplPwL54gsuyVUY2o4glXzkA1Cfr+2s cUxIsMJnD9hqtlp68IiPT6s9Z85+8PP9gd2O0yKmXmXJP7mCBd99+c6uaNAsG2/v9oiR/gn/jox9 pCOzYGB+8QovfA/sZRmPmCmGC8dwaBrtKFvlx8H7y6T5lGwmAVI8oullE7Y6awmOJ9H4kJ764qr+ k6E5E6mfCN9afYsUBQlweu6TDfbl4sykJ4i0GfU9E+yfZ0AEoDQw+0BndB9YEQ4XC3L+ZV80oJqE mG8eL4fifl+q1c1+3l+xHv6HVS5ACkXwYAZfkGXo/bY0PVnpdwDqqCriurDRDxCbMq6NM+lZUasA QpKCDhJNEPM7ZN1aKSfG5fN1/0/sqxl/+FWL2R8NNmP7MlU4z141gcyMKG9QqanAZNj0lgQwG50P szU0lzjAgAa+u4tQOcywvvKA4PJ5ORYXHtQLYeP/Lo8b20Sa6UFh5VcxbVWuDUEhIzft6GTn+p8y tGWsxiUVzLxAiaG+e4KpoTcFdwnDSIhSxkAMewqzcjR6DGPANCXs8rKXd/+UB55pCYRHQrU/6p7W ifB8aLc+fN7sem/zb+vzsrqHHqzpaQyuLditZ7S+AgDH11OVBmctWXycEKyiu0D4HkvaOs7bmxIP 0jPSINyKQ/Gi9pR6KSLgkVoULXja5PxwDvZxX3IYzNqH0uqvPPDzQFpAuT/Z5jsj6EhyvJGJmdWt +c9cnQR9kWwxDN/BIF9OciM2lM8KodyUDIfOSoFhNElS5yFIehtx/ZVQSnaBaASpNp+pJDB6dSsi 6YapFVzXR0PiBM9yWCU90rwsn3+acrg7+nKYyDhfwCYH2Kwz0KT5In/Na5E3tBn0453MOXSmphh0 siRJpYFFpTPvOzsDVabvs9GXwHv1dreulqpNydGcuQfqKwuDnH/+v6Q/U2hwfqilrOJ/Tnng0TYc 9a6F460g0CjREAl2mPCfbLqslL6IkNSQ8NFLCdY5O1l9rUaFvzMl2jz2TZ3b+YnylgFOff+T0OUA 2crOa14LqnoYYmNgz8SMgvcMsLgoXIyeJRRv84mjgoxaAXW5/N/22WfyolLKf4YGhHARHre05K9s s3ESYcPs6c//SWughvOEtTjUFslY9l3uZJULSfa04ABi2woENX3OO1M1H7bSl0+GYJnZIiJ3IOzN ZHNc9HfcjxBgDvA473dQsBLeGAAB7+M+ekL1UjQN29JLXv6iidJDYt3UZfP4eoGLjugGo4GvcqQ4 kabBkTFTsfEkil5tfxIgK9JtEPRphpf3asfF2wig80UszXdfYiaAOclr8G+h1XRXKomasf8mrJZB +Ww2J+4nFFeLyOX7y6IYQIdWOrR97NshK+5iDzF7Wt0fz5P7k7ET2S/+92MwsBufGvor7mVKRS+c 4QPYf5uZcnrM2wy+udYYu67oTh++jhkwDV4xaQq0hLDfwy+unks3RlIijnBtQLN3d3hGsy8rQV/T YxdUNL0cXJfLtmatEZ70C67TOMUI/SszBxwbQ2B876J4mkLYSmIrmxWL+5glwXRVgZXw+fXRX9WL afHQoMoqAioi2OQcuKuho89NbkHT/JgLn6zRTAr/e9TWt6p/qt8/5EcD0D1sJ1kpPDVuKGeaeEuy rJdRR7baXzpYkP9qcCJHc2vlhI/PmZN36yaSju1ZeGIXG+7SEqTGlMaQJ3ty0rOpTodzA4vjW9Sf NtOySAE8U19wwHxYpph1d4S1DdXRlINv500XBrz0B7AaoJ9zZa9baRUyYTjt6ALcpZEwQgL5rNsU BYXeexswDnrr8oTZA8tRHt3IJyoYCpfyiCYuSZ5u65UfaDowGidTPCKa2UHNOuslZHH5Fzg0c44h lFJJCFQJCVpHTzP1Gip6+J5wJTPc73y6RzcsBIDDYp4ZcJQcoM2zxdGSqPfREzfamFai7xKPuaPC ASs/f2s3vIDE1hHr+r8p2buQMB8z8zfjytvDUhjcdEa1BhPcVvZJlGQTR5Bh9aARjs+BUHXjBTls v6NYb2BDDBryWM4mld3gSPV3yig5z4MoHpa4Og+myMq7BG2+pUCMO8QG0p3/s7Tu5/2jlddCFjgK gR/TI+GIZefEkeTIuhk8KkuIjGaF79IJGc2B6cI8uOePSRzpf8ZAN683MsKsv0gwG5p01ef6bTGy sNn56m+8U/d2VdI0RVR+PygcpwksqZak7FFfbCC+y0fmetW+7wMsoyN6FDQ5EJt+7UwpAoJX4Tok jhPw0LxTa0qSXn41bl6uY0Pn+LZANIRm0xgvwRIByiv6PuMIphw0BGs0ARtjMjTj11oflJEU07A2 y29N3iEeLUy66FKHrjb17HHu5O7vDrmp7nWyAH5FxuJwbGA7+4fhlxcpzA0hEDh6ARvjw0uyD2XU o0/psT263OpquEu4dRmP9IL64O5BBi30Foh7w/0CguGdmP1xhqJjvqSVW3rydkpWUVnJQn4Yuitf ni5NkPZh4RC4uLjr5E59+QPsl7YqJQQEavlzyPKXp5nrIHmapjH95Z4xQFvSHXPxi0LHChEpiMWW 1JCHH810l+H0j7dGP9xrLPEDMNyu0+vY2o82LDInUqZxzXdpOnTZBlKR1LXSSa3Be70h6/uvzYQz pjiq2O8UnTnw/1KT323Xs4zv00/FXwHFdt0mB6sIGRW6M1UNHgO5Ow/l4cX+KJokhHIwQictXRxY nhO8nD1o1uVMlEycUTIA7CAUKmqMcjJMclTsDP4aXENzhbfTm51W+nHIWkEWPx6AX3b6/SAcX7wt nVEJbUzdpCIq97mcW5zAxmU75GunG9qF51EnguZbDB4jHY+9Se5e+eKyPQE1ZjB830+iiy7HdtnD iwE195n/xhnsO5udIj5aY1cV1wp9f6nZzJvMOomGTtNSfX7v1yGDFDd7LjWtyC4qvcAfIudE9MxN p+1CaCxqiJKluZb9jfuyGDJfIDJ7U7rSn8pXvSDaUX+M/+gtFR2o0d9hE6W9evLm6lRPuqsdU+D0 A3/Z57AauRh89QnDS2Mpa2b2/8e8QtNPlWfVX17rWgtpHLZGqMwRPcQN3Bt3NNHIxyEJ8jrCeigf Aei8diJtdu/MFmQiKoWtQWH8Z+Bb8x4KqG7XHxLj7rI7FNKuyBJ/XRxlNMykBQE51ZaYvS+OI/2l cjHYjHuCEFcH+KffFUDxOy5dyyXkgYTq9riosa2pLKgCjtCIVfVcS3yOlx6Z8CcMnjBsut9F75hm YZ2c0xU2mNzq4JNEVgyQICUDw9JS3+cSoKU6OvanYEBMH7AUlrbHiMGL4z2DmTiOy2Zd7iDvJr2O EMamvdqgksomZLhhwm4Q1IqgYj+WYNaCnIEKmV3WQNendM4VTzrbOuh6AkvsUzcgULRizPPhM7Ex //JZxvD95HI0GNwa0O7L0pzksvQIYtEDpmrB6GQGko+TbJpNSEqz3hKr96Vp+Jqlnq6XZzOeyXru 2UNLDCaS8k6MC3TSlWhpyKKkmV3Cookd4DbUXyqgG9ashHrvGIVnthNQAdqXZJ4aaRhPCzMXE33l FscGys8sp9/Re0nLjOIPx57rfvVkLfeBNRsv2yrviU14ak35bO4jVE59t4ZGFqRERK80bsOD479P Hh+idEkJmc/80p5SsYASowjPDXoNAQZdNz/lTVqiQdbikrTOI5D1omiE2iVlFB3FIhuFCKUaN6JH nZZiGvxEue5ZfayvgAO63Xp4TkFnyuRU62XksH8XRO0r0QNjdORBQ5sV7LU+Ya3gFdfk3Lb6/obF Qmb8A2dvXjkCamOly57GmXOmbF6GS8DBbXBuS+ct5V3SJGbj3bfJByjNwitk3qlaisdbyoHrnH1a v0dRk17wiFlqzD3A4ScC1Z2we7LoTUPFlGdWcqSznYwTHWqdaZ+4adh4yTVaHocbW9EzE9HFpFvG N97m8skHjqBPTBM3ycMz85K0hCfSwrSyCRlDa8K4jVY/Ma3698jTOwg3yFU9l/6HYBUesidjlH/8 eFKU1XbRBzXeJWIOW+fZGoVDHSC+DqB/xjXfndBVD08pWcjfS6gHsay234VRGhBF8M2V+k8d3w/d eP12X84m3i64ZhjcVjch9TOX4HIxQmYnFJ0a5+w5riZ+2GGsTs8HtJ0sZHR0GpNmE2K4T3dbeNTg Zk7dt1rW3FufjUNRQdOE0+DmhLGg5pL/essmVPX772Th9czmC2Ff3k8Y6SRPYokIZ2MTK+pcH7yw CsX33xVHC7JJeMkv9ry/rufS6cYKyXftwA8RyVIfBFJ9FesFkw4DCA/tlrI/9+1B/Clh8ploJ7aT l0BbFIZbpFGa+rgnT24IPd+kqI/RRRKU/qfCy7aGar8qc7xcORzSHn1b++6luU1gh04Bm4lgmcom F/ytSYSVD4hhVICRF8uzyuksObWJ6tY3+rr9vBhrCBujidFZJpB/nifIJ7nMRrGt4Ki+Mo3T2cCt 9v96o1jh6kZvNXEOn7OD1xjOdK9wB7tCv4fY/3rwGGNabcem3AiarEuLypkYRn3zdqRsOldu8oRw Q3afjRn8IurJvuf8I9QDZ9npFn1BPQKkzOU/iMhT3tbBzOJg/+vCu22xv6vc+mfp9KrV+aZyHA18 t0XLmCiB+ez6Jee1y7z+5qRC+oylUmSeBZIw6kXMmLKOUIfu+nKC1CrYb7aUzc4g3407Rx3bqIF3 3nBLDKD2dQtC1vUwNvYmi6aNVWKgAnk8seqYoju76ggXoX3c/jLfpWOgjJMPYRWjNeV47ivVJRlr czbP68FswZkKUvN9yfmc7KHFx5zwD9wR2aAKgB0cM3S9/riIQpHxOYXNZc5ntus1/j/AdFOH1VU4 ReUlu0FmcblXcmJFwyLS3hZy5/zbxSVHPGaCq/MCK7OmxnLSVJ0Ujr/4Cl37+14Df8hPy/ZP+7be 2kyG6VAGWBGmIy/Q1pmH2Raya1j+oqY/kJ2jExdZlCPdRKILgE7bN1MkBm/fEazb22DbsfXocV/q mRGrs0AWgf1x3lljccY9ztF5yFhxTlP0naaPSwUVK58XIJBOncRzPdW5gTa2RtNAC8/COBEVRj5C U0/RLN2qUwiSQwWk3NpLQd9I6BnyDqLqWv+srjtQOBP1A/xdDPuCKCfGBvJEb4UocUS5NJKxj6wX F2Q5EFSSpdG6A7geT2FiT0u8dNqepTX6Ad8GOgM7cyB7gh4naF0+qrfpg5eBnnr9f9hk+CmCMYB3 CWM6q/vQdxO5YDcUEvCTnTexJlfmsQlrQ36ISDN/t8QUkcBILPjzurFdpK74Vz0x6uS6d8VHmZOL 6XNOGnl+r36hFL3APjp3RASM/4fKO+Z4PIB/RLFHawi0sSbi0DQ3yCCHhRcuLhnY1EEigHqsNbFa gjza30M1CTrfppNjhrTOMSiZihqIYCJDJh3P/K0jyw3qhqIYO2atCjltqoi8IA4Lri2zq45vjpDX zo4ODyXiz740HEqVj1mOCu2cxDJ24pjB6cH5KAQa9I37gVzNxGneHCtV5s2UFA0IbZY/dJxNvJTV rA6VOKKU3xfoVxp2M7OL6XcVhY+CU+jw+mzsm4Xk6XQxp7LVpBlKIE+B3d653ZbbO9VGaHNU4LLs nbs/THWrt3hA0xC5v9w6scQVLCK0d+NJvvk20KpThfFE2bSKAWOVvLGBtpf6O90G9b4vaOUzj61K HC0jx8GNfPwdhZGutK+imXGPjEwsMdZDzi46Tk+CPNtOUPzn3Z06DfRJFK8mMs9CtOMvgUnXFs7J 2jXsR20lBDZHMukHwHty+3KakS+i8mauOr8RKSf01hBHHqRXOMArHIQIdrskwkgAra3j0mqmFqgI BuIQKwwRE5RIAlps0rb0j42VC5V7y4hieeLJK2aAnT3PMf6PS/roZ4Ou6F51AQuGxACO1hQBEeWk u91H7mbOAxwoE4rxkekhJstJeVYNVBjCLdiy0qf75Pdo41oiIjy7QB8wgol66id7X+vWatIExiJN w/3snsEH6TTkaxb+a8/GF31HSG3mgVvPHOY23v97AxCcKi8zWpVwlYvCksiRtSL+KkpHH2XTPUcU M1i+h2nDUA8XsASz1foN+YU5dmfi6nERJ5758jdDm+g5D4pR5FqLEsG63dQB+28W8ULH5jaNesy+ Ia+hYg0mwhnhasdXssm+6a7QADIe+5ghg73MvXhVqqCXkbKpUsmzlU79DFA3+NB+pqNXg/jXBG6a wCFAc9a59yAHAeg1+bIIdstV715yExaDm3g1lTQWdZvmRTVo5JRpK82S8zdoJ8ziyHRmca8HLIDF HbgolJMIQCExaJVSziKyGhyaO+MIge4ZUcvY57oP/72rQir/NHDN0goP05G9S/iEVgnjsiij6LiI 5ZsKSWda0EuaSd7hD4QqSHZ57vfx1LGUgqN4PfZTbQh8yIIbX0CY1feevlVzJb1Pya6yeJOT4R9o vLs87akQnAgl6VblkQEkV3REJ4/YwjTgN0KGyDZVhFs5AP8vgFVFGwKuI6dxtTkMPwzbaHzDOYwe YGLGBMtUeJwKLNPRTX4ow27TSrvQ/LPXS+QMs/8bLJz43gsZp6DvZF7Sxz4HcO23ZOaywW1L47bw OkJSHLUdZ7gLkqUGAI9yjus0eyVB6abkqV+LkOZJQulnHB32rNhal4WYHXYRYlPxvbSU+rLNZ3K7 vq3qHONwh/nQbSpvZQUfTIRXWNMvWxF4QlChAPTHivWY5WuZX5qNhlUUsxutQ9zlS7gU4S2g71EW lJTqlwas2FxjlkMOx7vEULG3yKYbafWVXmDjyhpRiM0qbvzxdEHakWjmyUfne9cc6idV6dXYltdQ lGHsJ40QhIbxO8EvDIQkXtbi8TX+QF8tQFo5yZrwPSqdVU8vhpeNfBieaDCoWrTiQAhZ5I780n51 0ZJy4EmpiddoBY6pQKAWxzDA/S7HEY1+eKj3BCdrD5rtEWUml0Cr+aZl24UtWfwi1RCE1mgH1re7 wS5Od1lQPOI6Pkcyjr+FUk5dNtlPkUUmB5sH08mSMXR/MDL8l9INg07ewvw9GPJnS21SsOzPoe+V KcwKYzJg2Z290HH8nqyYKy5xDWY9n+M58Z+4jSoJ44GApdz6vEssfJHaBSESBfoE2iUjZzCbosYL EBNrsH6lxLTsbQHlLnJ8nHOVJEZ0Fkc0k6NGeGhTcWDysNV1GGMX9C2w4s5Md8N0rpK4LPFJlzvn Pjf4NAYDl6eDuuz1yXtCHCKN8Hx6QOTh67NcD3wH7RvQxxR88efbtuuiwjvX3zhk45ZDtER4J2Pi dFcCJkfDjpsD6O830O/fuMINCY9crOwz3WijkLEVzY4WMNkGbe2uRzwrFCyJQrLyZ493gpk0bIie J8RslYd0YHyA+1dzCURusJ5Uow0k3DQAjljdN3uYqhTGPOSqZFRTGr4IONLKucDnRRalAympUtW6 uhywlUFWi1cgIXDOmAR0P5xKuPeaJhpAdFkhOKjTmwfwOccMMT7P4tM/HESrCc6tS7WF5YcYO2SD zPqZjIiBImNZtk4Zzh4g8sIazNrKbyNJlziYofn1wLV9qqtArHHOW5POl4lOBR9aCy+ssDspiy/r mAFpxl7HiyCl2GWZ2cGPOHRJXgnOhSGc1t04tyMCsjWNrDCYUIAAA7zDZ+fjx/XBHGWCSAgjrzMM CAlUuilfOTETPs2LXs6A3FQCxdIb2VMNgvK0OpLkTiZOeIHR+KBQxSlB7kbvjM0+yxsZ61H1xT8O 7VNqGJ2XzAq7YooXiGn55q9J3nxhdXzxkxOwUM4FA1LbkRzjn//Wc1PNQhccZCgq3fIiMujo1Ji/ CI7+hX13ukR55aZnF1blRuY2hmQwi2/v7qrKHWX48Y2vuW+477zcEv5ngZ+8hT2qAiFEKFHjF+99 UYfI/BRr9+ATP6SHeB89/W3SRcfnrnIF3KGqTQO8avfeHbLa5/l0IYHP22bQq+6ARK5Pnt2zr/5W 5DFpI+CG4eVZWvdvK28E6V5ZPZR8blLl78T1ZPHiGxJ4H/NGCqp1kPzzz8s/ggA/JVJc8WEP9MCR /3d+GK6nbd5yVdwRfoWVSmkTsxxWJN+VId1qJERAbMiMr7734j7qJfHx2STjn60ny0ezXN4DdXL1 3nvR+syqTYKS5KRf/QsOyRc7FVWEY/t4GW9cIabzXRPeNUa69n8Tf46B0Ru4bvUDjBFPooLXLutx 4NI8fvB83J5BV4mNUigUMmKa4+7GDPBvbo4YcKObQvbk2yAqmUmFgKNVXJ8HIceitrp+bL4w5n6I PbDjiBFeJ6FcRVwQU97TQxf1oujo7ThsbfBuFm+Uum0jBtkouMHmSg6472Wzd798jEwiwI5Hlycr m93VE6opTFy9w9AaPngGTas9sRuo0iFpJFweNFRJ4ziSM5RMmKtF9yveh7K3SNPHbv/MSE8wgFjP rVGbdddaxh+acfWyIih+I+uW24fDVs74L61i/u68BWGp8xm+vBHLoOqbYSJPnnmCDb9z05ZFBOvY S1vvpOw+nvPVh18jcndnlzrUL674Aogiyo+kkJyiL8BUfPa0zn8j9pMzpONGtRG7w03QQ6uAPUrH 4lwvOzNLA45hbFDnDIHLHbfE/8kRuGLIWOljFeAdmoGZYifq912mmEYoN1aV/yx/17mllGWWEsAt kLq51pMnCiXzGxV1FPECZngffJHkF3WAmU0bqV6YnokwqvJr6sBkkyfgPNXEGREPIb28ckh4tJUb GtycvPL+7awjeiFWNBvpQum1uoHP8dqtKXEmaDzCaYOHirvlf+JmdOAwDr4jG16Kaeh7hsgbt8te 3AMkkR13xKxFWVEfDsk+ygt3/r/yIflEWKFT3zGlmw2ONcUdxKydSHVe/ZesHzhUJQliwWHPdeYm unueqns8b5qc3jwuVm1VK529I4n/rnyPAIlTj6/6uTDWhb9yix566XdCLhWdhhRsv9V4QhKOGeHc T9If30ZxiuUyGbOCvcT5ttxTtRWyS418A8k0YCSy6eh5ZNng02OqnifAZKdtpIhGrSjRwv4cxlHb 4qeR0d5tLtrpLgHnu//cuCSdSQornNiMuuBNDjDRIdAV/YVfeBC7Sf5KHGFJC3aLkyPrQMKQ+J/I ybTE6dpzqglIhGRKHdWC0EjnutC85YQZGnXZWmvn2Nw6pKitHX6CGTVFnti+yNjdRsl4k05BnsE2 Rdudx4ruuAyvpFxqcNXyYaONxie0nTp4lc+wx9VDQqEXQCpYjqmSJbhFWp4kIFjlT2o2H+aTwRfK MzxPm7RUZhyZabQFWqxnwDz4CHfqtfVVGHqVkqRY64651+3yDMS3Uwozt8tZi3EwpRZvEZ6gJSn8 Er8oQ+HyFCgyDILZEL2kSE+R38aATEeiUN76yAGRvy/95ieDk7iP/4NhXL9IAs532oAX7Xeyzwxc YcJBg8VH2KWKggrmzj3+e3LLJpmvnCSfQACTTrVFDvR6WccQR6EFMlP7rsnfenvw8DvA9gm4Esh6 tV5CtYJcjPL1yBWvFBhxrwUmgdKULaOsrgQltQ/XaScE+dwnvgTGTYQugxe3pXVZNJtvFNcZy85K Gc4FcK469CJffMdbXINZefht9D0dp5Jm06a25d1+GGncmMmjxcg6hGeTcQALdyufp3HNu1Cs7NX0 Vj3kvGQDs024F0s6KkEUn5dP+7L0bnRBQttudmd/Z3DHck3OeERhtIOKb73ImbasHUS48P1Z1Yo1 xb//iZMD3mnzI9FBkRG97KlTOA/ZQUuTWF3oeQ3JHIptiHk6PLZwDqBEx8grCPvkHfn0hhtTLBKo fpWmb9/mb4zBjEC2grjgub/dWGswhf+B0378QvLYQzJXG72XBG/cCJBbbwXjh6fQWCTNoGUoU/Y0 TpeYCJqAj3PoZCprfT/GMnxwy0AEH+xU1d1HvcQnOKkiBSJlKUzo/eEAN4wl1MLiuuzjZsDqYiZG WTyGs8NyhLA0Lu2rBfYfCGFUidx13hb8h6KyXE0ryahYC+A7F04iwjH55sXFmu3hPyFqwiTlPURM OwccvWHHA7BFUogH/5gq9WEbdgAwmQKnJdBS3Zq9wk9vjVYFAXwp0Pz7FunT80i6Xc/Zc4HmkZ3w 6eG96zBrwLehl3kmspmg+38FtpxOWe//nIJVQp3DpzL6Z3gOUAeYaJ6z8nLvOxv9JtySOyw8dMdC jFLasY2WjmMbp59/6f/mEr88BGE+SNteH48DL9Isx05CvWRslmfcKTGLJuutUqq9Ny0jZsb0U+l+ HPpTs3XjNsa1AvHb1wGqSalkIbDy2VD3FQZIb185pWyiMW1bHfeyhsoemp1I38kKRSg/kXOtKqRD zxaNCNfQwH13tNa3eZUff6Ej9w6V7LRAZb7FJN5eHEM9Bt69plxK8+b4WpeG775LhDOiTeKnHSU7 ye96dSkglYD+YmVj1ZYadkzzGvOI7wFX+tD/oU5n7ayjUe5j+bOFbtrnW9LcbWpRZ3JOdaY070Mm NgOuct3G6xg+3zTV/m1Ts9W4CVyxmeW0GkQffL6jBHwdMOck1uqRArWajYZ7CUZ/5DVG3V+h5Dkf lS5E4ufbzrjryg4bfpe7utCXnv/K5ZlLPOKbb71MclXDafRyNY3GTFd3CHPwSE4iPpd/UfpqGG13 Gtjlz5IU/rGLWspfGM2YAmB666DrznLi14agEgVsqyd8NjiV1PdgXyyIfV0cJv8l0qhWcXQA9lFS c0bp3Z8dKhADLT87xZ4p15niqX+CbDd8mOcoL28r3WukmQmmG09RCEgsLMU7CHmAML6YOdd1Fm7b tEDWuk/OJEZzoCsXjETHb2BZnaBXSjsskWXCqMyLUyige3GgJwMW7pP1/9ViwTVVyHpTwadAnson zdPpc90H/91Y7RnIDJv7avIfJAgMrraiiip3tIx4ViwsmrbkP7daGIumxRMHxlxDcUPPyGnuhPwn TLY6fu0bTxNQ88iMvKO1nxk3iz1AHF1cegqzuuMU7NYwQ0b2opHCvYYAwF383ZsvsF0X0wEJHC4T ua5Qr2kmGo5LgdNYygyrtzuxoxOV4Z5/oM3LrtEDPnPsH4Rv/2jjV+/pihpva1mFlB9KkociPkSd CfvMtPsL9foz/TJH3W5/X0y/cloF6v+dWDLRSBU2EzfWSRn9rdYMNfnsoqlMvVAAiTokTyjsqCmB vOU2BK9RInCBRNIYVWv2MwL7QYe8elHvbDice/odVZ6jdPgTwKq6V2xR/cq3z2kYuTRzidX+CGVF c6Uw+vcZkZtDLg0J1o0YnZyo4u6Ytx9l52GhNaM9/txiv2tL35sJJJfI+CjC0Smbe6p6FApuCJva qBY6D7PwlVgPtTQiMQn893G7JmIr06/c0ZLnW2p93xcKTkp8d9dGk46OHDdtIJCvSl98M2T0gd2m 98I44aUajeNyQyE/KGp3lUIi5/XdGXouLAFn1JCHQb6C+YWJWxMx3nWiNXULcAcGmM8TCEUQeMMq fpbYwGBEUbZK3ndbqD1S6pdI8knxTDArfgTp9XWCDR6j1/KK0h5n9Q93orC1B0wVgQxXiYEGYj3p FE8g/txImtiAn68YEqlghnIDYBVMVQkrHsHA2CwdOZPAXllx90YqCyOYutiR+OsH4B4ZsQ4W8m/K YabGwegE11lmfgGzOZ/kngVgF/pU3TPOMKbnbzVkTmxP/X4kSqvX7BKpfDd/loQzDi5qAwlzinsL WbaPTSF7gbZ7M42BGBC3MwovUBelKQkVcvspKe2CL8wUvq/QobBRIkB7wDmEmcTTvwa6U4DsnOyO D4BNk/6H0La5g3y38Tpae+ArQ67Lv4fC6MlpHC0tsUGy8GyUjKZKGwqcNmBzZljKrsCQpNTKnb2I MZi9TKjDHOOBJ6hDk/1CS00hRsE7cm4jAYL+ZboM26ym++n7zP1OpsBtweOqwCH9o/9B+J3ah5zy 2fSRQ4YtnXyJy3mXQ0V3+OcH1hB88tWvMo5aGNqskT3Xn1NLZ6lwi3dCouDsxyzTk/dM1/ziK0r2 faoP267IBw9hKvW2SjaEEOG3b5kHIbjAPCzykJ1vEK4TkgnbR7m+q6JUk9lonHbnYboJIAsvlOiC VKogjsZXam1jSrHe98qONOFulMWC3lGO80cpz72y3pG4F/SjMNQW1YCFQ/wqOyPpY8SZkQp1NykH OB7GEsynB2nFxf3ntn7ilQdkEOr5uAt/2ViXnke+wB3mMS+TshM/RelJTN3FVlZp9zvLDtce8zS9 iO0YekfGSNks/OLEX54eZU7/y61LHKDDYT6W4qgxiKY9dCiRS98oPZXIbAaR1gWTCMNmmoDAFHYQ dOskBBcqf0rqMX7RWj0M4dFFMEOnNjqRXF7bWb2kT3iFqSiMxXPDxVYjIbMDd3M3lHo1ZXuovKBv /3Q1MjzosQlPMVH04S/SV10hTfFixZkInqBp7XO19EU+y6dde+yBSHFATVm+VMYxHfjv0yCKjXKb aP54KjhjPdqfTFg86YuOn9KC4QdKZjhRCYusBx6wQ/Bt5EoJRbEbmoyeZ/582LRFExuhdL8qwBSa LTVK8FiR3bDRH5OrynFNzwc6mxbm/SRmsoCDym+dnzK+Eah+U4KirfUNJjZzAv8RX0iXyMN0Di4z /hAnWwd1LwnOX77xr675zThXhbXDlsDYPhcQMMf+QEobbX9Eh1Z0FhpfWVVdRszR+CDZk/t38tMD lEp4XFlvT8PMVNiWk6dJ884g+TmdMBavqltGEktXz+ltSbi+KPlhZbks0o/K0owWYPpUxURX3n4A fN0iF63QV0sFweZubddhWhA5DhVDCF1+0VPUbqu59ej8ILYr0gfPD1cILJiPn5pTHerF8mqnB4ZW m7nH895DJPD+QgmBMMHGaSGcIqIoeqrvjHPYaXHgFbDFzZ9FbMxgEgt94+LQG55FsMglQjx1/9ms Qdl13mFARiCfk9CzH+AjWQrpqGNm6GlZdj8yIzs74GBwoOLj8Iy/ULOQEJDPo4asvBsP3En1UPTv utldq9ztD97iAlLAGMvwFz/Wm+29G7KYKVhlRofH3MXR4ZWGbpd3x8peA99PjaTIW+lMhtWNDVwB w1LE55DcerJhq3geoXZKU8qv5AZIIEIBSZDDilA/ApjAbsuu0MnBxzMUvTBK80GK++PciHzmRWg8 LtolDYDTtR0VGxIDdSucXJgM+0ScwbvdLpzWK8wwQrrkDO5Qb19PPff3oEpz44QB9JXY8LL9f8zu tZNjcTWOjp+fUm2iTTOMunZa//lXh50sfGsZXoJX+WT5EQuIC7bCy1n/uTPIbRzX6oUbejNOQhWk InUXpt1P9nP2IcTB6ZJDb2PwXgvf5NF1sWiU/SoHl4t4Ze4frnP5Un6dzcv+c0MzRASBnAyMZS7f hWDspH/bWXGMtv/xPIdgWkpAdcJP9USF6SWjLVz2KqGHMcofvEpVXX3CBs4WY1t4x4O6TNaLRYWg XIrNeEQQF0zntujn/9DBWEI8mc9EalIfx9rAJXJAvneGpq++iiN74X9UVjBWvdXNEHo0lOzo6OQ+ ECpTx9P1RyMlgWa0ioQ0L8jLVTDWfQPYoQVL8MPxH9xAJyNP0qC7f7Ost6hOWuILobCqgr1G1m84 1wx9+E2kETEc8GqnDnNZ2C6CQWn2mVyvpC019uryS4VA55V5IiUaXG3mJzfTma4PvVz8Cu9MC516 07EUaPDpZgvmmZw2GTHavS6zupjHUsjz5F5aNxofung7/OJ89LxqRD8fAlCVnezzzkaW20UoA1cm cWfuqeSKZPvkLfQ6ByGSBU+au+jzAnKir7NJqDvrRJkO+f8RQmq4xAuFaUwR510D4GJtkXsVgBEQ DkT1oiGjqGYoPNl2cjt7fW7Zaf2WqWt1hD82qrDntl85mxZckh2bbs/1IkqobpNRQbdnlJlf6ysG qkU2HOiSd5oIsak2aNZdwYzJD0hoyYy85j3Z/IhHAAnd3AMiUXWg4z05srw12Hk9VQWEiMRz3z3U EWsBkBreYQi+KHlJfh0eg2FnJDd9TwsbqMXUpKxM3j2bsdyvFW008nPlbLL5R3YLnOleU0EbCJsp Hsiz84dg/cPgm6Jupt11TI47v28vMghIGGvcCC6jxvzem/GulUWMam50iXnqyFw05DLxiZHQ7ZP/ BMAleET4mJo6YTbAz6Lm0MsSWUCZuY8pulc1YfZ+dW0X7u04PsdgzsCnRENnfAa9vwam9Z3mKTXF +NG/rlYxHKCpyYScP8cM5c94yksfBzY25us9OXgowLRWmuRWgqLmnsVHeHVi9t2m+P9Pg5qWoQCD GEOi+NH4+w/DkO+ChCuC2BU+6JcMljMq20l9CGy5PovzdL2yW2iKSFDaPlaZJdjWOSOhkZBrJA8q lckJP1omXE8lEUKk59gL4E/DmzqFyn7EQfoQMwjMwPuCW4b5Zt/UestWWhtLKyp819RKbrsizWhk //wE2EuFHWNAwtrQrMiWnVO0sSPKv+7STwFJxZI36C52XhOuUbxZqAB9bsk0BPy+ggh5OAwfh/7t 0PCUiiRReXIbSfqOUT/K69AYXiKgJ/6zKQpF2uUwzH3MpBoDDr/2xBsL/OH+tVBGsHxJjhOEfTk4 jvbnRnkfq/UMN4OKTu71yPjgUlZxeKlJW+dlaWttfXU7FmDyMPLAtHbXHnLVGRT606my8ZmCzjCp G/AAqcik+Jk6sZ98szfEJge6RzBbkebsIa3VHQqGizUZcHYs5hZVUQM6lvFbEjhIDITwxF3Zpkt/ VWODIIcbQ28uGZPkHfiZ6GHv13Lm4/TMAW4ieLi099cSUxiWViabqXY7mBB4D0fEcNVkZOIpKgjO XjGnLONCvvABrJ4helhDJqKkGQE6To5wjtFpgBw5IZThT7a4uiBf1+UeX4DBc5ikOCHiFx1+93Im tSdkZ977N8rK2YxeZWo6yHWshmcLrf7WBzvpirjoBNiDEvLQCE/uzHGNYNtLekmEDkwuS37VgpUh RqaVxwjqnVnn0KTmKHA4vconVEw8/Y91OjWP7evxeVxIRNOpqKHgV+NwNdRJ0+iqiHNRc29+cQ65 rfao+CCNrvbf9INsrsVCFvBjokTwUai2XfP70ZcOHZLfG1tgEvwtT2/RMBQWAhNyIW/1oHpgnMOT M/ZAopskBfgg/sXxVvv9Jvrz0RJYnO/1YV1omiGUOvGJBm5q9OTPOuXDDYdjWxR0ikYHHLtc6cui oSAGz+IeujgevvLp2HK4KINsaM4Rbk0cxQFPVuT/rHqa24ABejMLTIr/XHg7y3j6sEPxA2iwlIvl 93999Y58JFZTKnMYS3F01g/kKinyF2PSj7ZkfwHMPqShBUby8ej8U79GixC1PGQgNS9t7uY3AC95 muU6muyufOPi/Fmadl+kQ/ZNa/YJ2FYViYhOtKePTSFQqZYesoPIfSlzh5GJOA/8icnzEwIYooyT 6Eh6RVPK5zPwJ00980DbsH+C3QL3Fhr2lbHslRWwzy7Weq7XF4TcK/0CoYcAh87doCGr9k8msOiZ v4sA/X/IyBc/AClfrBpgPOW/g5Em3wKzi4uR0Q4axEZQaXVqLblXLocQBbHBHDt1M0HcCgySnpd6 LXITsFlOD2fW9a2I2WuFQ3+cetd3mItpwfETh3Hg++9Zu5y5KkixQe7ZOI5HtprTNtzjQeL83m1D vXZ6ditMpOBpR9d0onj5GbTchOsUoonhWBaWC1zFSIHumEIz0axqp/OtL6x546ebewWyiEXbNci+ mmn6/+SHsKu67QreeBnA+854vfpN6G0DrKriaEZx5bqBKoMzkzslY9SBuZt+YDA0Es0EHQws+TOy DN1EM7tckwyXDQ+tt14bYUWaOO/Tt5rjZXQSR/8mJdhvUBRM/RZ6xen4GxJ7N/j2Gx4AVrWVpyny 78MxNUkNOGgWCA0/3kk4c3jyiBO1ktXqERick3aJFZuSGjMaIKR2lnp3jGp1vYtrJffysL5Fd9xI blR12WTuI62dp5znEXtbFp8buUczRumOpS0LZy0WwhxdN1RWu6FLwTLaqVR5mIGm5bM1/fr48PAI WwOoxgRnHh0XQcA7MdY2DF/XkxysajNRipReD6B5gJSdzDHFwcSK+PDA17SX01E+UPTiHTZ4bHu4 T1RX7zM9u3DsocIELobea1LvtJMElS9G8ttWUHsww/BIZZqSbjL2jctYJMiiy0BOZgs7Zh2C8de9 iwqf4BJ8vzYcnHU1GFUuCEuD89DlQ1Qjn8rwLQcm6yfec1HeKjbWsnboC+ACTdo8eDq2n0GzkKAU LOsSicVgGhK2SSTFjgU9eiEZZwTTWhnv2NbbiSXC0Zf5WUiB7wl+ycaT13SS4wnoa3hvN62cMShC DUHPd7A5o3qd+lJ1Go3vAykt7Ee0LrPq1OJux6X8SpBCh9cvw9XeWUedKhU8GdOG3wB5URLtMrZa Vdj1DRnE+fA4DrnMEcN/1rRXRPbRxqngIsKEZUZEH/o5csh6+X+TLBt9hU38eO33cDS63j0YBRmJ ozI6bNvn8S5eUOKWhxUSa4eKhAo0ubTGnJgP68pHA74xopNZP2rxriGoxoDPLi+ypiuHZVz0LL2y bw40nGL00+GKBiOYgmfImHjgqdWO7ePoV+LrRafMzu6LzlMPD9dT84E8TVI+UGDRwDIDrGYp0PUJ 9W6BYOnM9U1V4bWguZhBlGJd5jWNBXhHluwcbbY+qOVO8fuNdp/UIG0AGfX9jOc8HUXyfmEsMkFO rzBQKQ2h3002xIq3dbHUVIyxflLAbnaeWo/CtVSblyWyDzzLNAl2XFRRqPJ6pFdf/qg8lxQ4ZbCH nS/2k4jcHTm0sMyl6bSQWUXZ3WUbKQX2XO0Az545K8keddVqGB6oZlCUQTVry3N7hvbFrJgbi47c nETG6xRcXDqNjI65Mh4LHUxh2l175f/KX01GzZchKeySBUxVD9/b8yPHfEeX6j/3PoYZJ9YSLDLo VFtx7Y+QWIpGFzkcHM2jbZp+WSQEeEroHfMDhLuWTOwxcSpjl6zxrG1Gs48b0kjgNX4D4UEF1ceo 8dHIID0TKJOnbqepFB/g4sZFWJG6m6/NoDt/d3Knz4Sa0fAdtoB3F77kre6RYgyJHf+CrDZ8bqnr vFM3KSXuRplarylFXlvgdbkQ/SNx8t9mT+KkxjGeFssouhjEZrcEWXwdDYjnhvIKW0c4IB4gN6Te 0OYP+RJl+Fq0M4y6qlxHIRxgeER2oYLHqU15ISDY2VNxQR4WeS4Yv2Hyp6m2kvO98uFhoZk39AzX f5cexyhhaNiMIpIMZPL0Jyk0uc6ZPbbvAvgWrXQxnGZVo7j7v74QP66wdM47rKSOc4kRlX6tN9+I v6AmGxyc6d+sBBh1TEKrwMPnaROZ/FpTGUB5zAZhFvrGpvAuxPPH/mn7cs5di5+aTl4B6AYN/XEW QcJvkDYrYIEGZS8h/HOiej+aIyrYfko5Xmvj+f/uRkxsJrhvqdiPv9kab8zF6dBodXHOPC0eclrs 9Pk4EpFIBXB7rDhHp8p4xnM6ZYfjN2kbH8ACQcxhscQ2GYa6NKLOjWAzX4rnY+M7IJFEMPzLHkxz kiFwMyy0x2d2tdOAgNY6fyrfSUKb6GwAROtP5DsINlg6Y0klLmnu4dzpOrY7TXw0cISBEq56mLru 7IQgkgCEM/MFCX4Hs90hTrbbziBWqO4p4smETelvIbWSyDpwA8OsV6/ISs4jKkyh9HNK54By+LUq DZ1PTB4ZnMX4vOztgt6PqW8cu69yAAnGMRxJStC7tx+t0STVaNPpccipUvrB3kUHI7aXm5VUuop6 HyLsINz8rzhwRKXFu6sir0hRG5JelwYZsgFNr2M0aJEIqB0Md2jn3w8UUvEnQEX7QUISrl1Z2/c8 wJ8FMk594NlKGIBFWBmPmBNhCNWOBWESrB5RgCAFP/H2lHmyaAct25MaHiNj7ZanHeg4Qky8MnHz 3JTawUWyt90i+xWS58c8iN7kBS8xbn3u21CH53xiT+vfi5siKoZJnTcW+QqkpUohGZNHWews5uq9 tJKx4krOfRkBCDPZzGIh9xEIs6wfZOZPqGUs1djtrVtiOdZF/4mjYZ5rcRoshTFG0Peiean9Q7dz 8IhKSCLBhMCKEMiRk0VuG7aLCZoC3Cfd7bwxiucHF93ZkUSt7rmqTUjdl2JBsBdX9j/aiQaEoAzv QPwvhLVBxjQbPd06r2DFdOdxOQT1NUnJm+j9zxzj1U1r78sdniK39KZjxe8Wvf0U9DvqEqlk7FAy As6hL9BMDclVQbB7Joau3fW2i8VHlobai0rdiN7tSF87lhqpWEu66FmkrHqWtv/U70RDnkHWx9Hb mcza61TpJssvgWXqPaKyxsgwDE6XOoTUsS3Rolg1f7+XKYAtZLPbtsxLJmSdylKYeeEiQNQ+Dkc0 kjCsYTX6PeGjQ23370Lm0rsNDDv9urxEjepCfQAPAmmNydD5uZ5IJpZv+R9fnVJ3r8hWNd23HlQa fbWFUE+ZYc/p+FvQA4rlmRMux4BkHA0mgcbKuNOc1TsL7dghu3fJRF1BpHdpJQLtPAnE+Ks8C6sN jvKzgnxRqGi19nXuytL6a/XyRi9yQ8ckEtsP9mvAM1dfOx8bs72QhRVLaBp6zKuKjkoK8VM6+ZNp 6/HICQxl8g35g1GW3vuEvm+SUxvD7ntKGARsp3kObE1B9PAUGB0mRGBinQrLYu/nVmyIJ1RMXVXN 9FEAbXCXd87bT8AH+z22uS59PmXjTb1odLy+GsznjDTAEW2iPwVJN8vR4uzxIntI0bmANXDGd/rG 8SE27TBSdKYfbERmasPElAcpe5+d7fls7G72N3Q62rPqp0Am7Gnr4U1lowfMI+f7BAd9Hp+kWPrL m5oj96esyi/yPAttFqAWXJLoqKnrIBG1a8NE0eCRtI/snEFrbjPoRdb480uXLabJXNrhJOIOMW8U NN9Y4OFIqX8i1ZsJJLF5+Cyyg+18tirRMN6Eg1xSt1sXbeYxiBsY6EsfXI8czSgHn9Z1NsosHswy XYOoFQQdOTer/uww05EgV178CbUZJErOMHFwXBgLU8s3t5ia5wvOqQYqJDxJAFMpa3OusWWwUlxx 2gF05z2dFtIgwpVXK0PQghv06rG1tjePg0L9WsTn+7p7oZFB1ngwgi9dN0qDka1KOsM/+vxkzFpY Xf7hQIbA2KwwOwRdnaHDyHJYH42Nd2bcrJma0zK+vz4r7Pt71StXH6ZXpIAjS2IyCgRW2ZFDhw/u 9ksuxyzLYL74B3j0gS7Qw6LjIE9qd2DR0ZqXhHJKo6YGNe0nlJs6B1hBt/rJm5XlDKT6JCgzl9+A uimnyb6QjmIzD81b7TOUshg8zyJrVeNPCVIfuHK6OpG1O63oVOj6+KgKMuGpv1ze0AdsrDINc5Y/ HQu3q0QL2VxWmmE2fPxbnYBQyUePWVx7FguhyOhyMbYOaQ2rSoh8FuhaaY9cY/2WEec+adfpMj3k p7xtF4rME6lq+LXd1MPYKJQ68/tBz7a7hXx6pXyUuRKQgwd77CoxqDOOxMmQZ5OBmgTz5xf1CTG9 ALcmAqZ6kwPl50lbi+AinLVGB9iqFqv/KuXuQ2wd1H58ER+gCnL4hB5u9/M4vvfk51m3fWcnJyb4 n+Xit/bC/BB7ewKHAjRWHnP/aGF69azcfI4JvcxkvJt3+1yxnEiSSvZyoO3QdUj8h+rxnIEZd1Rt +q/urJIDfF036ROFCwbXYBFYMnVyiRk6SCMm2LfrMusrFw4tctbXqcddSZDoejGLn+RW6CJIsQmB dnh3KF/gLgka+vZv1oHCJdvCndSoEMla7PwD0N9NjEHbAY+GNLPAJqoztK3bNpT9aPHNdyA9uySl pTjPaG/g7UXZCm7N8A1vuzK7MTUt5+qx+XBvnpigk1nktnyP6uugDWu7n/9Hsg5XJh0uf7+187qt jsAZhiiL1ZOLMTGkpe7U5lHOaxCS/B+7pqgrKuYqBiXFWckq1WmXK8DkaCOjCEev8SV3vXN+6lem XA6dgzBT8Waf6m4XKN9hNy7ZE+lMOsU487x+9yrojGVTiN/WvWAIQ8wPzJnRdLD8067MJTTPr2tp f7BJv9uSZLHQ3HyJ9T401xxshJ6ST06DXX4z152n7XFicbZFMSW5FdRDuKsXZswTRGs/2kOVVnwF e4UXzR405eV3FLWGC8A/cZjdvwunXBDeXt/wYpVVJrf8iHRFVA/faAt0agIhFxDphe2My6/baQ41 YSj+mQF9iNA5Wo/9oJ1QMF4vHr+jGR0xH9ZQHg2exnn9MUJmKlNw/9soCPXQSaxWz1l7XM/28M5L DXCt7pVQBeEDB0YronaTHjMRX85YXe4U1i6kMETs/9IKiPLwDMgAD5kkhg8NQNhcWLme2mDUYQ1v 6uJbB+6nvHlWCCHu/ydKy/Du8LFcgl+HTFLq3hKW7idltDloWwHRwK7KPaLpIavtcOF2ozIkTJtV HXVETx3lMT7Sx08Dvqo0SfPpWtlM+I6qPmo1d4NJrKXXL6Imx/4iA14+GytROmkRXSNwkNo4ILPf yqy/yC2Sef5eLy6nrRLuPA0bbOxO07Al1d8ciHInIO8g8K5RaUSjfc8rN3mIo8POOpDsXCiPxwmL Pm/cCPHJ6HULaPWDzcN5E7gnAQQ1HIR4oWS5nZ4/TBrhvK8riRlLSzG6PPfvMBK9S/j7JIzJ/ByN tlTP544Yd4Q1sRD6G1vm4OlbRXjL1V36ipXdT7ToSZD3LaqNcE1uHWxjV6iymkG7Cnv41FyXHPro GJHDNqf9VHrEqnQc6m5i4royBfjF1T3Trce5wDKbSdz2b5xAUsdl2Nc0zEaenHfqfAvfJjLonVIZ k+fFX3j82iP9pGOSpEuxGCT/cE5Gia9feoB3W0J0JnUrXF3kRfWIhBA3z8DT1Y6bltlk9UeiyJIK +C3s4gePHf4mvinvKJSUeYYGSNN+51gMoeL5g78ivOnviBaWM3Dxg+9Ll9BeMVjCfXCQcsq7CHeb CTVBwZUcPxKM3sIEDol0QyrDoPOj+dP5GcdFLaaFKj8zXd2RDdRoO+rSlqqchXb8q8atRHQZTa+0 jfpMTMrg4UdyI0+2p/CCZqwZtXoUMo2Szihc1lyOg4MMoWc139UgLoq3YsByzRlU0yDbIRo3tE9C 6FEj0TtlDHy6FKngpTF7Y7q5qUOb7Yb23DmQXZ8zr9OOSPKfzfuBQ9+HQ7mXxfWtzLq/futIIJ9C yTGMw5+5ot8P99VAPCOjqNmcJ/oqyaddqAoAV8Ak9CPWzPXBjLwJHWps8Snd+RNIsqcCUbHPTnr4 Uzo+5JH6PgGOsDfnknC5QSYVWd03XaVu/1eyEEnPx+TS1ZPweV5JfdEYC51Irtbso/GdImrspg/1 m9Lrp9gD7HcAKJLlQ3ZmvpRPY8Grf+5hOHN2aKkvRTwIzQTR6fVrsnXFrLDiKhfUaVN716bzrXa5 8VRMu5bXiTuIzhsCrn8hi+kW82za6ulRbcTxd0+v1NUkOUR9Q11Ur7Rh6ua3F6dfcQPPu7sSV6XQ nX0177Gi/XtQB1MY43KZb2e7vg9BKnrpinK1zdu0Pf0SvGDuzhIDEaN3H4kfFN0N6sDomioNRw28 z4HyfMWHr0DUn+sqNKYL3JQfiJmrF5wtR9OND4QWiGYEcsWsili8ZnOMM0k60nh27f9K6d/q8RNZ vpabFoVZ/cfmBSR/jvscij5ONTQ31uJOvrpGeAbcsylmp4nBSpXKh0nElswEtIv6enXHnMOgPvJc QJGaQu2v7N/vQEr0yS/YiMtBZXgRuZ/vCrmb/Lko7bvTUfj3jHOoETDoXpAYTyimJPO3V57g7USZ 8lfnkkeP7XtNdHzAWmLFNIDC6j3UnHQLdeILJwkjKBZG1jiI88xQKlAQ4fi4qH1Yqg24SwWL+y7v 83WYVs9i8r94zmMk+BdHab1EiQ4QoIigCAASmDeQ2wjlY21EXwgiISh9jaYsx+yu/V+ayeHUZb24 EsH3J8BEeYkcDsvEbwu+gyxDjQlFrPzcU8sT/xmb/6K52MO6LORzsQ5JXkX7gttOivpTxfWrZukl JKbFb5BPtB4Fvq6n/l84dRWrVVzRx/Ai+BK3UuV4z98DBOvtVjKh7gLuNcFO8dgNb5/fn041Hxjz dXYYovFV/mWjc0eohpbdqDYxv1aTDi/Q95XWmji7L+5W+ZKBv6IFBrv5M42QWc8DTJcqWWWWXijI yJF8hPNJ/+dkc4uUNqvn0xhwBK6/gFHedFUXdt5q5IJE6DgHSW6Fr/8yF51u3nYMea2PrSRi4aQq ubF2xvXsFlKvY97TxR1HeNJVyv/e04hzr8rLAtcuNd3UHvJF85i8km2ao2QnquzeV6a1xWnIrFr6 DcC/WW4mqCj8XS/T8b3SMX+sGpCK7xZyfchHHLc5I5uEodwyhpqervGR68KCW0Mk8QQqG7RquJBa rxTCe2ALi2g+oOTC+9io4QtdQsyqbWnrr7/OROW94Ucgr2jGjdwhzS7+sa9xbZNXNLudsk3DKRMq 7fLK7Qmx08sz4j6t6J5VQU0tsb1UGzkiGC7KnneSNhf0CUdC51nIb6Nnd4+cw8R4m+L8NwVir2Yv d1Hab2w0mgfTQn/z1/b7j4w0lDCHkXDHTGzwzIvWkBPZKj1T11d6RjwKTwD+f1jWmiM2Mv/T8vix Jpb2zD1EZ68Sp4Ehx09XSx+3RFr7nGRwdqb9yJ6EFRNJfchkGoOP4QlSLoEdI8jslzh+Kxb4XJ53 8XULShqoY/I3XflH0B5dvsp3Z+eZEyVjASAB+RcT/9VSwHAonU39qO79qgjWPtLanK3zNeNCuTDP yy5u2hnop3+ACD29jie9ez0b3hJyisX8afcsFHxnXhyGYRvHXs/3CJ6CAI3FkWo1ykccCsE71Yks vqAARjIwsusW6YlAaFoJ9TrCt9Cm+flKuYnY+VfCvmZkZYrGbVclroNOb12K2J14jku/g593LJu3 2qLz11DDo6Foir74z6lhiJmdobDe8/Scfm1aDNYtaHMpTrBQ1aAbgNNQQ1+3JfGXA2z3SnAom6gk T1E13u7BNcLiZyaC7GJWCLH/ETBEHkRp9LgG70vZsplCTgObqRSpb4elievvGrzSjbbqbb/myjpU 4nbTKn1FutsqQYikhYOcLyKSOTVc/kjeYRoIlL2NjdCZVFuC7b6LLkezvOd4goIvaUjxVA+ljA1j zi6kDyU2dI3d4vzquw7r/9swj3cY4TKh9olxYgEphCZ5kdkf3CQyYCq8Q1J7MS6XxUtci18aYP6d game6m6xf3Uy5aUa38pOTAlDVzJG9G4b91MTIK3ND0piRk3Sk/tTzU0Rg/cYY333AHJaSJyWxeYi QVoRkEaC3rgFxyosAERg6vA+KemTGFhsx3eNYM+E4CaA1s2JB5D3yXJAzsoQclihlycE/8J+Ih4m nBq2K5KA6PuBgmrNfxo2BaYa5kHVXQ6YjR0pCIJCd4V5qfgLqX7EAXq4Pt8lDUehKmNNiNs0T7+d aNAh+wtl7oO9uxvZhg4GMUZt2+0zgVicmd5khEetl/Id1SQ8chNMGciYG5/dOvK4Hs6caKraRd0l ieOaV36rj0KV/prD7kQ4LshWt5SZKlezhApUq9MOZiyNn/C4mwWnEIbwiXGQDt7zpqsmslVqUmDG bswwztg6euM6VMIwze105YwNH76dc80Jsf31vqIm0cDcus1qRXxuJFIy1r2yOKf/1PJOO7IlpyOa /C4Lebp2eLf8MdQ+2zztqzOAidVYEuwsHZfFV8Kso0ToPNyxf2oZywPjZ/MTFg08YtAYTvrOjBAe FxpK2zHS4l+v8dvKGjkpvj7pWGdg6jMn2odzfGDD0YU0xf9VVSgxFlcPlu5GCq+HJL/S6BW3Ou26 EPEqXU94AOZPAyfPlM/Te5vSYjKXmspxox2KkEeuzPrM+Np4OiN/QKyeGOSTRfju8yoikTvp5142 9BI8WtCScxP+RDSBnX8wVMUN+j46vrkTex1L2AjZvMAi0HhOZumc8G0oEpJ96G7jtBR9iVtDmT3S FB1wYgIuscFAmtSzGRzbKhK3GV1FlCUBHU7zweag8XfAC/mVk4ZazwOPTYmSbrfGa558jSI4ayM0 9ZnXcdXf4ipkX5ZKiTJ8sFRVVZ90vYdej01HhsGJseceVLnVqiIb2OYkByyY4ER3T8MT4Ny0DnVv 0dny5SL3/nV37p8C6u+DMrGsFhqe8M1WQlHjSoN5D3r/W1CRMDtnUdMC/1cWtUBfQFqVtyhJs4XI OGsz96rCnZyEeeq594jH36SHCeYRVnjaUjzaMmvf0U8UZUFTjJHaXbgX+6Pa+/7ttE8ii6EEq9rV xFxaRaR09g9fSdf6gHguPX0ZFluFT71gGRvZV7XB0/4qlBGuvtsfdIY1bQQ10dxoabYdpVWKAZ0T usnIzb3W4GOqLjv7GBpzUgNf6zVY/BCKdb+yrcvNB1inXaPVtVnRZOKZUvcV/tMk8x3cvoK716OP a68TVa0SToKGW/TH5i3/ySb13aUP27SQJHiLLBiI1zLTG/gqKj8nEt0yZuRQsijVsDq4NrmYP6gB b+JhWrkMGAZiMcIc/RCu8czV68iI6rG8dg8lOrcjr4C5MXXulW3h9Obvc1Qyjny5ccu7oPbRRxxL 8WkvcUy82EpUJPb23xrWLbp/7GZljRGucdhjciA86N7lBqDVv7rZS8nG12EgQ3J3vW1JwZnGb3w9 2+jxpASL0qMmKzQh/dg1gby2UhaqgWoWO++y8t6NFvsZiJ0SDb1uW2rqx74vDap9D2l1NoCxCOJd OrNzIxFwNKKgXGfq3AdXJilaqGi1+6exRI52uTAzRy1gMKER6inRdKT+otZoVhvROLA9ZZg4vqa6 fxgEOLN0UQQA3C4PEyqOs4QzAI6+NDq/e9C5+HwF0fri3rMsD6iLUE/tZm/tGMrBDlnxg+eUjXNB GNVblgQ5abIwUYkYZQnPakOBeIGSnp9sveeI9jqgpu9DPQbh6Znq/NyEeOXtC4h2LvyyaiwVYvwX cPTtJWpEpB2F5PNZMPc2vQa7PmZwBKF1th+kF2IRbhrcnSDvNx8MTHOjvE6piuTRphfyKsgOUd+r L2msCiufNveL4Qhs5hy3n/aCBsVbZ438vSgYts0muS9TZjh3jnsv/ftXVx0fS8s+JEYOz1jHakYY mJzfJ3gBDeWra5Lo2aodEW3O03MjhLb5cnj109Z0/hbZK8cLk2fPsQWYwc2H+wQx157Au2FJXRdn oYEAKQGiCJI7Qpn9KBtZqLUusIuQwkrjoXHmH6Fjsxt0om/UyBIT2Nr7dqNXfkk3Tk8yrwut9t6p eIImjs/nAlURC63QEQtOCbZr59b+fKvw6ba7WkEN3La54FDfyuHF+x4U/iemEXx98PMyIEYp8qfW NcQGv0uJ4xlsi1O5zHqx/V6VvUSRq8+ZdRhDOw+sNKO4a0xNHo7NlV8jkTT7vIAYe5uPB1xWRUaQ qr1dfnkBbPw0cY3v7yzzDnjyVkhL6DZ9gIwu1lnlhdXFqe7MOmtpQkJCrMQnvO0S+Va8TAq2K9Ha CYls8onGsm0MFPPvEcVPlQ1LnWoU6b6nx/nUivhwlJM8Ui63PDBE+uoJC+XLM5W9U3ScaWrlkXpB UBQr9qzKk1XWIDcA8m7uqulqIjHkF8vSYcAAguOsYH54BCDBQTDdSkvlCXvkCWcRUNRjWPvfPts8 K8x9sE8mORSexrg2sSQt71RIs2b2Zdeyi6Dgr0Oo+cvnvkOoAUvFoDOr+92YDquWIZuS86ftWBWo eZ/vCpP68AdxKlVAgyFDPdBKfBKNWX/x3mTWdMAJx1Bp0vdGT0ukWogmfJhXEagIldKMWqEYP8Bi ZU4kT8YC1mSXpJ6VBxkeH1hko/fpII5Et0XVDfnSxYwjavJOjvhcCiVk6MbOHlx62ZjYO9LNXp1k iBwcpqqaunCnwsw+JHLgoNRD9G3vXe3i8vclm+DNpgGvO8QBinwBVv66JnYhTP8ZifrORxJaO/6v 9O5KgvYPC40H5vsWbiUfDGcS84No16Fyp9K8+62JEQyvTKi8bQ1muYCMFPqeOX66C1jZTKg7htAV fw4kjQ+JyNFcXqNDhvY6Z9ykbuPtYBKBctTh2p3iE0+n3+sAYCHsvAqZa8WbjhOrGf7mRJyPwhLK 9HuMk/eMr8K2ugXV1wLKOnBlvwj7UayKI5injZGRCt0qSqaYvfwiBGkFItc/0bS0Fwfimw4N7CdN UXXVNpmeo+i+tsakficOr9BZr8Kiax0CUnPFJy7dKwJqozy+9aWH+eobMc7eh8nOXN1UHG0MFh+k RtTvaWiud50z0iqj2RZvbzdnidqYjfG1pR+pDmB/fnUUPjKlA2XRS3aZaAZVBG+ySgJIMm2KSm8h vkLrN2zzE0M+l9xGxu6A1iL80KO1OvozcFPOLxMxs57I15y49k34lwa0QKixvf2YpkijZeHHXJ0+ I/cxuG+6xP1WliNFqbLIkndIRXq7heSBbnhGV/IVFQerUGGoxaH8eT0oNLzL99D5++6jA3hOzpHl 09cHTY7cEjAYyYxZ8EyTHEL3GAafscU4DiEfxPCrEcFR4GUZICD7rm4Z4QKD6h0e96TbRNeRiGwI AHjz+QkUm8NXk/A9g93LGmwAKELdye4hQj4ksBApY7P9yyPHL/q0Ucy3IZkY3gbjMCyLS6eUlYgu G1yYV2Zamyii8S1QkPnyNfipX6406Rr2NPxOE69zyLblx9Ia+9orEjkZOsN6u66A9kWbwKLicyha dblLrsigHxofBiW+JcmEs7qLXp/MfC3zwBcDuoF2hH332jGAXVdF4LVZLK0BgRBGILwA0XR0epl4 5BRSLwTjJaaJ0J8Q1I8dFL4VBoQeO2Z2ym/JdHjuxcaLNA41m9rUPy91Jn3LSyZzfH54iTuUmN0U LFyXlbdwq6DGJgH9bP1uqnzTMEFEj8RMPQiVjw5dhtEIDAYLC2VpeIVo0dGjRcSWppI9EbffPfQM t/mlL2xmLkC8vfcF2FQ6qGCoh+Se0YZbLf6bTMG47WNquupX0vSozoTnNZnyt03kkO8fX4dFm4zI W8TiM7frDuasBxvpMDkDkWjq5/9s0wV7BeHas2SuyezmQt5SVCwe5omxJgfXQ/wKoMvfC1v6Z7FN Q4YO36KQXQmoTSA4InViQ3Ycg+/eOSllg25w7OApqASwIA9hx/+WxemjHOB6p0wmaacG+WuNbAAc Y85TOO47NZrs3JGgzOVJeO3qprZLyRtIMeVP0B8Ji43sPr+4PrDYSBDorwsrpKuOsZu9EBaNBqel xi4LfMgclkHqIxOguch14vKaCjlsEbmFqSxuY1/iytEgH3FOXRUPmMWujcB0Iw+QaFvgGo+2JoLv tsjUZ1RpKnaLGLiM+mqQr1ltgv05tpB1WJ+LUQfAR2/+i5mOG+XgbuvDL0MWI+cVrnoHyjoCm1Ao /KcIKyqpTb0bhEbDd4OVoN31DS2/NZPHNAHX1B59SJC2YlQJxQpl29gb7cRorGhWRmjFbr//3A6p ckA8+z3F1FVBTzDZP0pFioeNQeCS2vbMd7rfS7vlTyHlZ8e4tyn+DH60qRwwR5Y4oCr3abHKeEuu asbd3Q3baIm3bnYrCBgOQH1l32VRX08Pq16JhkEUHEBf0b/FDsoZpdEgUdZq+j6nJYHVdQFlNPKt Z9R0m8+AN0bjmSTT7POnvuWRZzstABMjUC4fbrguhoMDFq22j1KQN6Y6PvvXnlQSKtfQbHlcV1Fx Dvtp0j0GXlKW1MtcPaWaDIqTrqQL/m0GyZpBV873xH1uJoc8vIh22SYcsA3pI8gsTzIc1UOLt7VI 9TiYb/nv2qtDP4gVkKliPrym8ou+rWOLlTzGhXuJE8EUE5o6hCQhySocVRea5e/wGW8kwZhKRrAq dN1uCAKCzFrtcdvqmnytCsSC7ptI7mkQpt6T0aS7C0pt80BeBpGga95xH7i1SGXZ8NFfw5C1nNFe s01dftds2g9kirxs6T4VClcsRTb5gRtn79NIqAx3xiTVnfyREsI7XKkGV0U88IArtUTu9YiC2hXv W2Ge3mcXnP0vb0wz58Dztm2q2FkV9PWQJAkMlSOW5uv/XSsR06IpPvd8RmWlAVeToBghxePTB2ta vgIHGDVMtrQ7IGBdo9ZZRMbZIQedDOIQ7Pjs3FqbofkooSmhtB5ihgwWTb8DmAv6XPSuHPqUmfc8 4DxXGPGfjeVzuj9Zyeo8cTisIaTUNK48cCPDRE8RR/y+fLcg4xlbNa8C2E91uYlkiAjKai7FchVx Ol2q9i5FCZdWlc5jfh4OeABtGWEQCR/tbL5pQpsvimZ1EXQ6edx7Wc1cf6qD85MWz0Hyob1IYC3V +UoAfQw1E1ZzOSTFaQI/r/oQh0Wl1woONFY/GlJ1vClyRGtvAmJADSJ5r4w1KcbIJjnYP59U5OAr kx10MHfIcD+Ygwik9FJJs97X0vbypwQDLATpK8htDBlP/DDMWWh3Ew2V3zjp7MAVSMvCzYueru9j Z4OrccXXcAjokE72Rw87oOUp694pchXGziEZn1yZ6WIaq8ubdksuGql69yTZkh2cPE5hL0JZRoYj 4tVoGIIXlccsf3n/wBMnxWq+ZqAaKS3SJ/JYPVkLArtT8v+yTftuD4qKD5Upg8NaIkzqdnTwWkRj H3fX7BJidUBs3feze548bxf895kf+STSpRiwNN2J88u3ivLZuudyNIVhEI46dmj1IOfv1tyoIxMC XLNiA1dK4pZGJVg7jHLtFlqnRSTOO0yGk2K5PriuRhQEy+Ut2PugcussIsQasmNx3j/MSBj+gJgW suegeCuJNLgaWAeIIIKxYpn0kjnO79U0vV9lXjimDwqq7kg7c8cSr8yhON9yLok9N3enc3j1MqAO +GuC5vAKGlVXO2vk1xBwnW+mvU6UXK/mPr355ujgrJUEGH2urZGr/Ebv2OeksTp5almEXhCvytYF lkMFZvBaTid6feOVmfOMxthQgX4Rj3V585iGKApE7djtFQEN0kclcmKiOey5Zyvgr7mwbZW06ESM KPJ+kKykBEy+eVb0PZqT+uv0vZ13w7k9WivSWLdXIFyy8RKRupZF/XyddDx4mA031ANmhIIBxHJ2 LrYhhBxYNsD0ASM9G/ovSWmD1om+auWUlMGdZn0XuDp8a91JMEfWhRMihwkwjmlzwY+bBTIyCgfv O2gIlaIVs7aFEqpgKKbxxnHxxvgLU3NgFJGg0qkp5NIHUEeYV53IWrOxP0RvuvDVjiNJVaCQb1ZG ukmD1XDvtEKXCGIXgu/5RAJZXBBlKfdJqs3Yg+PzIFfv78PsJiWE+D4z27Ks9cuudK6V7ehvlXIr CsYwix9Yl6+iw0V0Q7lnlNKmJcVgU9nrvbLTn4qhkFdS07bj0jfkkAsOB2+X+W3MWkgE7FOFTD3N lU97D1HaxiITfTG/WH7Zsjx/aG2ruow0mBsrqwS47ghvVM3m8U/J7V1rjtOXlWj/YT4wF3s1UydC pHiuJqoRuGP0MUII9pL5Y6qniAAG+ksNZpmfZRvhYIadu572qTh6OCFuS2LobaEmBYe9vxgo6b7G fXTVd8acR8blnAjC96udWb5Qda4vPF+lTF0MqHbpyJZ4IgbX5wyQdZNCKS5YxzDt2voE9bs+aGv6 JGcv6ClCtEpcamjdqpVSZNTshFTgde/tRRVmfZoNAuSDhXhiCY2ndNRjvy7i2qsK0kmfzw2vC43W J9V6RCj3F+Aavh5Ay5QZfJcEUaOES4jTEcJUtgs3QxvDyUPrMjonpqQGHenSMMq7LLZouE+BhUtQ aMk93pTljl6rX04tZNKaXuCjKfPfwQViNmfxqqzHLnS28ClEaBJXX6aFKlJ+8IC/mZJcMUpMp6+8 0bbpvKGSqe8LMX+Ltat/doGz6j4+2zPDiABGNM+/GU1tKzvQMmnIH4xQuCzHb2hSHj4CAW4P57s7 36lvT1XeN18JEJz7tNwsnYxFDO89Z33KD2rjMcOCa9e4oNDqU5j1e2q0Y+movN7pGbIuoaWvbLGV uurLv6lqlS6n2IwStHbr2b5AD7u/2dZu598LsNSpfatG1wVi2SZzckA5VIFUa0/b+3iYiaA3jdew wjQfO04wafCH7/Qk4BTiLAOhJfiSxxuh4yqzRsux6A8G8jLkVib1CxyXD7AxaZSthBG+UVQcHRdh LRZx2bzM/YfZRz82DX1lhVyOnU8+P43tU5Fv78s/YcxPmVNb+MDKovgnuXgRQn7ThBnEX3gsjiTc 6bupFDWRokDEhWwqHWwpW+Dp/bRLNvRag7MvJxVWzAwUW2uVruC4jFmt0+4JJN5Mnozx51ZadoGi KQ8mpuGTqDzQYo24Q7OcWEbOQfxChZskG0MQ+Q7QEp5ShI0+qZHRMOdZ+RIP0oqIFUpRBNtiRBO7 L3isWiP8qT3rUj/dR4tKxCatOJ1oeYWOxO7npepJnGGX/N17UjCErIw37yyIJFdjoXDHFv+YBQ8V vFmbBsrVUk82ULXjwJeuTJp+rKbdz2UiRKTZTCqn8zUi7VBggOD4bs15S6YiHz/+5bOk60xYOP7j SB2lxP42uZqyDL+sd/mJG6wj2EedaF2OHUt4rV5NKJgNeZuM+FSVBZp5Opdq43Eso0aclqPXdcKp ni3mok2ZR/MylAhq5yQWGs7tvvpCxIMqA2spDM0tUGZQJSVhvDGm9bcvzi/ZEkIxI1Wk6fWLGl0s roh1/1/9K75JtKlA0aMzShxOxUnsgx8Pp/2EGdS0bmORplycHqaDwryrt6AEBzDYvtST0cY8+MpS YXWLxLoj/aOr3N4w6iB2MlVb+u3/dzVhGMcMI6eer4+bdr6TXcIa9K2MdP/SzD6mTX+JY3/y+zT2 O/txNvT6nX9ZHoS11wZL3JSVeKEy5wmcN/baAVMGF6TN6BqEkC/063lhzr3Dja/CPg2bFSJMIuhU qfILL6lMoSvAVH1Fzu3s0Tm3tWv4DBtBUiRW/XTg7ha+I5Ehr2LMxumYX/S/yTVS/ASZdrj0nQlg xO7tcP2pgn1QZBlv8GXYgWyyw76M9oyHBsvBtywbUCMCp9AdH1Lx0A/O6aB2ow5jwlkNHDwk67cn uPy+Tcyrvy99vIQ2L7Zf7ldjjC/32oQqdeywokEMD96l6MNYnrFWW/N0PJVKN7vkr6KqH6YNePcl +ywZPg0/2lOhQyk3FG4ZdXNSc0azFcLxIAgYJXgf/DK3ShFKnN2F+AJn3ARi3uP65p3yC81BXh7M Tjm6N5bDpa/FtlSe19sUemq+jNfjJyqFJh+KqWqcCgNg6jPyAuOZUsPNid7dfSOxswXw+rgOZStt jCAGhUHqGf5OaGRbzLm/BeFuWpyXdieWAPECm4FEo5vO98Uf0TycU2MQXX43o+LmPslY9SYN1POt tf5V++eOrfQNSUdFVMi6DOXzXDe0aCmBMm3dJ9PnUN+888oXQJU4fZm/BptuhPmKmNMXuUlOre2A Q7ZoTfZKYaeFsfni86WbgW4WORvpexaL/bI2rA5g3H+JoMwDMAVyStHkrabncY1WL2ewDzzkETNs Zr4o0AObGH6C8hVEb+N/lXoFNxDMXYojVkqa/+WwKqwNaUbMzsmvYLHuulHRuAnkGgVGzX+9IEWr 96Kd1McJJXtuOfDtqb7hAFLMgEhcnrfJj+rPQuqumOtK0aL5GdUOpQbQf8/4ZhJNclD75jyIPEZh Jn37w6CHYSfteNEbQAxVFxSUVABEHVhZkyFLIpqC31NBjalQClQaVeiOHK8miDG82q7x3WLjgb+L Fm41RZK2RLSNnwgjKaI8Rvk3PLrSP3nKXie8vd+oOJZErtO/uKZj6O7bnKazNumGIZvsoW0Nd/ub lqaOi+85MBKdoDtfUxWmsyQO40QC4/GL3q1QyCPFRiNaafeS3TCetvOvgD6ffegPWJck49ros3tC fVJZeXmREjMMsC7v0jz2mKmxUzFSLcTVwynfmJXE4TzAlsvP/1SIMGQJsyp3uGoRoI9dFOuA0i9H cAmp09ByvB0/fQvShb5W/1cCSSgDme7MFcSgBkdE99pFVqDmPQWwHbVesuqhibRcJNrF76+ATE6r VpDfl+9Fj6WQ2S86FunoYAdvKMXDKcfj+xTc72OyBTdB96FuqZEcDEPRMaJgBZw25r+MGAph0Ad8 7Ks+mWvnGLFqW+bq87yB/n1+7TJQ70D3peQ/clkIkjSk+RxkxMKR28bEnfPPXP0XOTrAEjUPcNZZ 0C7Xf5RlZDGzubX1Swj1ZrKdDBBBAkR1k/zh4Yn8ZdusTF5rZAZ7s5Pcc9XqPFKutoMBqLObbv7r /8SR+wHiPosrZJ09/kuOF+bdfIkkT3XlV9/rJFd7wTEKRYZxVVVPgQp/l/J2ilfoW+HCTenc4qCs eAw8XH7CUql9s8FbNQJ1fU3CXVBTe99SCDuZ1mwHiGYkrUKXySFK+h8FuEhXaFuxy+vXQSGF0YW7 n40HPwa5o5DhXLgGAZXhX89qMr8XYoT4XLPr4THcwjaO/jWPA66kNZ06Cvcjp9Je+E4jtjVaGsIq GXwDzfqbUE0AQuyZ+pKh7r/CW2tyvhSE2l7OEC/qcMvO7rW6OT9UmkjW4Szkaza+VYufDsU+VGL4 7NyiQlWatAgdKUSBBTTblJEVvf4ULJNOHDnbEajGeKbNB+jwiISXDoR2XaIRiGOYDJWOEazCrxK4 KB0IEb1ObdWncQpjF32PY/QwbbUR+/q7AgXtOTLoTr18EIq2DpdBqM5QT9luDZwM4JRQA5D7HsBG J27W1MvuV4hKV5+yCATSQ46YC8CeqUUu8dwQdoQNCZ9OiaApUX5E1/HihGlf7ghjrenkuHfxqR73 abnbpne4KPfi3clBCIlfvlXCUfY/cFaqI4IIXjBIH1p1zFsX1ErYR6vZs+3MPohuYShmJGq7z+PN x/0doq0nRIIDAu0XtXefNaYC+mYXkpv9bp8Drm3CDbzkjMf1aRyCB26U/Z0H1XmUpAHZQtcizoLe no3gAP+/7Y0hxY29e4fZ1z+X4ZYiKICKCcU2dZsO68Z8xe2yAv2L8iKRo+bOklro2/PXBRtFd+7N PEooRBNV4uPl8DSXvd1ISupbCxntv4tmUwQ3FpDfZxJ0rB9aOpVBVi27Kbdy7lgcTIX0zOCDo/fc mjyVRWUsZTLplYVyjRUrRLg2nnlLYbPwAhoL1i2njbzHko9OzHjxUyPbgB/pibPzGBEtRTaKVtu4 yP9kgyiMnii2evJLdBZP9mUjgZ5YhshrpPP2ixlDG/mSotVI5vo/mFLJRSQTDj1x4fUdartTTjPO IkG1uoTb1xylYNHB4O6LCzup+fSvIYsB5V3SiHgcGVqnfLGkbRyDytztjnmmQqdFh0Brap0Z0hxy UZU2HaLKCzqdjhTixnwTWYkB25/w6hR/BOrZYQFPktGV0qlIRxGLrBk0SKVJHlfyLOTg9Mo/7WBN Og/pTUkWogZIM0X4Qf1U5hikmL3AsCey+5P7DlNbCgFmRB0PVT05Luh8XsDv7BqtNydF5qkbaAks zqD7vZRoM8DzME1ORqVBmxK/WiyncM/tDuGjVYvLRqv2dc1Abt30MHvdWQLiTp6cOKTK+6GRT8w/ gWA5m8MS3didFx+XJubxWpMAwu9G7aPbU9YxsNJRK/pn4NmSG0LtiitW5SMfvixecQZqv3KsG9eH GGcGvjE4DGI7s3zwHgBodejBLQ2NQEB2k8/4bru/9Y3UxrwteTga4iF3R53Avtce3oRTkSm5gFWU LfPGvj/ETI7TWeyj/PajIMwnNIH94Kvw9SpU5di7oDC55nyoCZ0iw34962ojkENgyoftsUctpLbi D11hIkcPc6aYh/H0A7tIBPPRMO5cqZhFazFXhL54NTqa/o/REcEnRncIBb2h33vpj3wAXXNXiE3Y cMgv95X0Mg5ocOfQ7tYb4gKDKDxWB+gsbF8pCi4lEkkUW5P4wtl1SNKdVteP+CT/egd0YFoynRmu BogH2njOjLy9m2aKbJS8FtINZxwFRazt0tJxzYTiB+59Rrk+a61yMx32EkG92KM8dnP05mSXNPTb KLrA8Qy0sPkiJ0tT3nmquCat4Lmxn27/FbEddX/4KbpPn3Jmw9LFWPbRslGeK6Uu5N3ZfJxzwx1S +wKEwJBUGfyzyGkPtOW3O7vcQtNb0LgoWJmnm3IIC+APncN5HfncA4HtFdOfiv81UdPKF/qoTwTR t6a9TGzwkY+BPMJCu+mY7xXFsp6mHy3ssxJIFJ9KEw+FIM4WYLXXtebX5o7ReHoTBsPoVrZLdpgA 5iZnh5st9Rvx9eT4lUukkmtPwpnPEJUL+B7EkLsHRqWQ8ndfJpviNQSWEEawO/NlDEvdcT3fU0ua oVYnszm3tkg2tSnMZCp/GCyI/kcyiqcB9RSuG/k0C00/2BjUo15W5jPKFzjxTQgyeL5JV52QFg7v sTrksbWxETRC5idpxTZAZ+fiOB1XhB4NM/yj6kN5zLF2WkLizOHD6/RuTEJk4CVCFFVHyFLhUSeW 1cUOahqZgekLgtbACZhlSrtuc/8qbaA8bGmNSSjtSj6+iPP5ZwlIxYs59mnxZtSbkj7WGmPM5HJP dTfmUbx0PjHH4vcvUtQE45n2mZ5EabqcH7Ln6fCWjYM43gw0WQcK5ybyh3PSP1GQjG27BqiEbF4w yxIcptqw+ir+wJMM/JlXAwB7827t8tAlbG33WfJsNr1zoJ7BYTQ/ME+qCHHeLTMVZwJU1D2IYEdx 16gvZ4mTr/aDDTQQBi+KJXvIcQLQ5okaFxG3P9No6g/S//1bHcwak2PBicycHvoDabfOjPHlx5WH JOpl3jkmDidXAFFzVfke6+Pmjp+f1pYjXAtJLxWy8vGZQ8+YS14/10OJ44LI0mHhoOSq0NgtkWHG FsjHKMLdIC0Cpo2ALTo7o/zbSRqzyMitEbL5kxRZjG1KSJF0b5TzZi5kDGi9K9Qfmw4w7WMhh2s7 XMcwWAA7uVaxF/VAjKzcq5r8h22QaSlzVkIDS9Xw4o8LWONuc9QWYftTx/HqvFtPrRqtqHPfiz6O cmjMawK5YgzyqK1bHBXs+15RZqzPttA0QEq6bQ3kwLoYmdHpEAu/XkQ6agwoN9bspraV5HfK7ebE lwRhVSfL7F+vN215hGXI5j+zXLX42ihCTxuX2SSWna6PSblY/MubAjToG2PkFNMXgCkBVzq6qQ/8 3+r1NIz3DlMNhLBsGVPzE48HKF5kQyAnoZrCX9/1Wo4E3ltNq7VCcKDq/g+vc8SStMV6zTbcg8Bz PP351cdm5y9QKlFDmh6ZUYKizC74+V7LVrN/Cj4jT+jLjzCoJh+YdN6QqYuytQpgcZq2reUJD7Pr WCbKSNljXAGYMo0slK3X5lP4fpXQGWEEAt6evuRYVB8sSJhCX9nL88nxh2VJc8gLHSgNSj/LKD/W fkSl+cn16QGWzXeKCF/6lasE4ClZl9TQLEFbHruufvqFJ/j2VifgZM8GlVVd1+hE9srqRB4agnzi qoV6t2Qq0h2caSwNKm6BVPQcMWC9lsAxR9fUCiDuw+ZYCTajVEvzzg3LGyaYsEBcOZfZEufDj50p VNrgGyceP+9E1rb9agr0L+yATrIQgEgp7xQZafUwWWz+7LvRf5umyl/fBBMo3cyFLNCSGTB/LzGY ADWer1zNIqnYR6fglVQlk5SygMyouds+MALHj56F/qedvkptXtqLA4rtmpkZoIyQUpWWx0PVpvAC yrK9bc5cbmMN8jaHLX29EdxVNMFYJiyVmzVw0d/UOr+GNKEzLHildSW6GdBpq89ouRQzBWLuezFo o9u2mQkIfGdFKbLqQaTsNGLLKEXwVgujk4z98X0PplPOswl+dulQHX1PBMxOC1o7OUA4AUxAdwo+ oxt8/fFQj/vnBVkOv6kvucEZzq3SvlEJ65/7bLUlki4iEiuWN9koox7WUw5h8ACBfra8F9pLMU3P gBpI7193dR1pYMWqZxvVDZN1KFpBWIV8WqO7KmPNYMej7ApPYiFIgbkK0ZpCFFjBgVPV8u2eBa9z CcFQz6xoXvmoSdA0m5G+IjE8v/FwPLESgTQxdYdkXGtQB4fE6wuNdO+ryyp1n2uLOF/olUS9J6UE h/PtYG0nRMv4sJGavDvsUT9sgi+IZn9cp2b+SIFpamu6MgdMv1hcHOvbau/6uVgtIOvSzAJrZlnk zKIS4EFmOAiddyCloH2yvFQtZhTNNy82hOheOyhv7QvnRiGxr1AZyrBjrxcpoJ0v0KntJEL45CbO 4F+7oWOcc3WtxapbPiSxxEyQ0LLzS9ETTRKNxoQC/f2vn02GmUeiLvK6xLMT/XH4BXDRikKQjvjY C3uCeaq9/eZCoqmmBiRCBhcnlNBjhXbm/Q9/sImjeqh9qPj2m8pY+F3cylOD3aRpR2nAs6mh6fJS khC2+MSKSiP61AcHXPovBfA1aIPLA1i8detNksIlAOGp0dGghC5RF3kIn5G7e5Qa412GTwXNUDYx qMKQJatnBXmLyuri7OH4vRxerVPcFrQdN2aHu/EH7T3Wefth+BtFvKxDIMY5juNA+sIx8HtHVbyi /ez2FK+SDCqtyvTOUPfcaeqlANc9IEgQu5+Bmmn70slV2rdj9BJJosr60ZDT3lVJNcQsG9Vxiybq GYlESSGQBirH/6XPLvL0vEmnxMM7yBi3su0aQlV8EYKPLgZHNlJ/pZFCslfkAkS4ds6+3E5LeARq U3DK1tS2+Gt+48n6FwaAVdsJyQAE6pxcMOYmYwB0jdK+I14b2vtty8MEWdsoswV5vm8afxDi10EN tNac6OlMEGjgu3Xqv9/u8dfbFDBCDeLsmLkywb9HimJUvcnSKM+ccj0lpwg7wTsLItPDOxnjUNQZ Bu1NXr+cvCtvhm2xt0R6aC31gOtHvx+/oiOT+fA2qOCGLXfOz3h8IL03ePKHpUFRnoYT2QZG7Cin aYqRBmUnCLZHXpy4BEPL3Js4TUxZVmXqtsNhw+5+25bdAUmKQkFwRfSelZFnslFjdOGx5HnlNhFi LXCQ6N1mVskz6kNTIjflsEQxEXbFqfKY5+sQhzbMqxTpt7ab2YRFxv7UZO6xxqFYKBnFDmUoJhrd EKBPsli+SlnwRWn2aLKACcpkoe3w1pf1iwlMFYz46jAP3PvzcB3cWqaPLjS9C0fhp3CNdRH4GllA d/yzVW1pEdKWAhTaxaRwgyUgD7cw9wTwWoLNO+jZfKWWeA8sQ0jvIP8mi9DcuLPQDQcv0NH7xoMC CgnaqOtfIXIAdOvWKaTRwF913rsrYyA0smSXzIjzvgUkwZ6Ur6SDQycYv800Bw1wOqjzh13sYoJa SZPd1cpVk75TICzXeWpGEkisJbIS8PTl2tUVMS6XUYHK7fvlyYRbTFWIHSrjudiuxl86SqgMtbfl dxPuhJVzxrw6sz3PEPzl5tFqU9XLBRUKQGdus001c/+/gieexqCkAP8yW7J9mdLDusgeIzjHomaY datLzQIBIideMb35kcmtVKJ47LY9yN879eha5MM5bEzpjTPe2tSzq5LFpTgpkcYT1Fq9U1NCdH6O dcx0AFMPAVrdCC7fsc3tYOGHeeJLUo5kPrs10v5fp58azbt9UbgTg3LcdL8NRAxwm4nQLu+8TwRt oIK2VCold4lf75bPa5jDcqnoIBSTzBgohhK90fYb2Wj9cNPRAEzB//qn9nBSlTnpjQ8I0vnGEiK0 4w39tmDju5wNwJmI+VvLxY6VpcBW5I5bpNkeyeZuUiYgkFF/dmOIb8og/M1H2CnpyRamYKf6dcFL fKSZZUTieB9QabGJzH8hytHP1J9Ob8zoTgWvXNhnzejy6fNezl/JTdo6Xl9ANK1iVYteBTjTl6JB PlYbl2jBd1Bn9opAV9D3pg8tJQpjXSGmDGBGt87RKjShjLWCYhmYrsZZ8kmOwxsKMeThf/uBpT/G 1aoCrXYSPQlfV1PB9KH0bYIhNgJ+y5L6MubMFazS2p8YdTm0C+LJLWBEuNi6i2xp2v3GLBJlIaPu qnxhqSj72rC22BvxmxBDJR589yrnBouqn+DAespJ2qE6RZAxIUVVjk93KPzFnVxZjr0zjDV573io 58zIAoJffDh8xW2fQ5Y2p0qIvs8fkwhZtT2jlnZbuUfjkUDAiZy7CcXzLCa7bl8bVNT4LNn6BF4u /NWqhj+0E1DtMX4vyVfUKzgi6KC1VoX2LJPUfHDKgfLbwSVBbd6j+I8vdKvThOP48Yfmqz3O+oyy +iIh3kNQ9JvP9aNgbMpY3RqcPqnndxoqpR+VSGLoSlVx4RkHI7kMaKVQvMeSpW3OS3RuW3SKlLkg Uk+rnwRolPNQdu8LsnLrQx3JohBNrn2vqfCMfN/gxto5E8PSTBcFCRRcEgImj+z4mj1Sr928CuD2 XtdRB/acUduxdowcr6x2ErGB27KSUoRhJWcSHIRuwt8R6JRc9BFeC3gqeFJjWMUags9MD6KpXZDj FM3QlHS/XpiVDLWnQ3yZb1i2tHOPhX7pIC6tblXy0DU1eltqzP6yg48ZgudQfhwIvuhORQoAe2NN 5jrK89Tz91mwHhR6/KQDyvyA0uKoXJqC/Stv1SN+BsKrczr4k8o6IZpWHrFY8F1Uy3W1Jmg+JnPa 4ViOG8Qdd5j4AfLF4eCzvIyrlELJH8wj/43giJjDeh0Pbgt35aKL5MU9fvMKFUrUeidoxyyPa6zd rElSzmiRT4tp9cF9+pPFOPmA/eDey3qtRAIhrYlCyS2GbAi99beELP8GvZAFvo1lvokjlO8YUkGr oXDdR9ZUJ4Q8mAHfqD46IDLBGJACS/ZWNfTSBPKWjiSMgojSnGASfMho2bWEW4GxphBQuJZ5nQZv DSmqLRloxkiz1+lUqr+fCPkNrtQQBLD6Vcl00PqY1nWUhb/t7YB93GGQJvgxlFT4R4kBQP7lnjlZ 7VWuJpQwZ9bUzJZvps87k5nO/3vO2MBJfPTC0NXc2dobx1d3MHIEDtlwTsnD1xY3hCEvvt3BgTyi Ianm1wRvpOt1RHSw5CNLW03HgPtpckDOvIZ4Ou4XASzdUlm4iny/weiQXXfc9fIjV1HU1PNppaDJ joeAxC5TpROZr7QmxkGsiulnrXtN2hwJhex7Q0gvVZCBuKaTk3avxJsJ2jHhsxpxKw/lXb+GZvLC fsJcwhu/lqwGITdzf9uGT+VpJAwGmfo6bcitUkh7WNgVb/f918u1qa6i4bRECB+72gWzwnGR53P7 QG00FFhcyNGnQkOSootm6wY/cI0WWXhGt6NrG1WgTFaXd80+XV+zVeuJI8x4QZSQnQma4hnCm7Rm yWCZBs/o785n5wyJlWdV5qL7qMuCsVtjf7uL/7zcjzgU8443WyQK64h57mc9t8reQDWkHwC8pYXk opYonL+XRT5sSR0jr3NiRvFHZUr+QaJjfrSFws5hAsFRfyIRV+dJt49QZcWja7n06IWSHp5N4j+g tZsUFeTqmeikwHKIPLXwVkk7EPiM9JIGSmuFZrwTlUgZ7AMFNkfC5jXDYBcEiPAJLtgNXRz4wkdq kSNJpIDwqMKzKOesX6CAlNoUQTajafDO0l0OeHQD5pe8BDIxFyPoYfchV9JJ95Np/KvHtA3Noso8 v8w07b4BARvJC10GRubVwyA+Z7z1oa2I1zNAil8hW8QZP9iunf4k/QDgUiFRWiMxjcAZBUByK8hf /VYzW1ds7ur1NeZ/IEpDQ2SL9bXe5a/9ebwXC8d0ZOzFSNvzii3sn/Jx5Ne3hqmhM2yTsb6sGYPo Bea1ob4KrBN53xVqdNvu5Jk8OBEciTUG34975gX9fgq+P3gc00UzaCB6n4VTDPo3Fwi0J8VJaMoF Gwl3cZ1oDyzY6aKBG6utjx9BPsdoNtEeKoDa1gMkYZAi6kQVMfjga2DvkzMmGL2rrgEjNuIgycb2 3wOt9rbdBuCaAsEP9vNjop4nVpwA2YK/7rlziRujM1loTEjk7R+KIH5Ai1Lc4h232sOoK0G8Wpkc 6ISJ3qUzlhLgdcjQfJuf9GKdIks0fdcCNTADiSriuIp587a0SmR7m8lu6hlUcro5YCBsXvQb255t GUUlga/3FpfF2q2vGOGaALJnJYxLpHEjJqs1AxnnBMNxKB88tbBctzh2LDtPMIBNfAxKS70FFuIK bJ3yirkBduLgp2M72THp7sR8z1cUmcke7COyyV3mB/UU7W8tuWV62owPQvAdBwck15D2kb8hL98N k3Hes2fMAicVHh5rffpNp2o0U/GOwO7F5KfThwe7d8kAH0uYWx1u5Ry7s8cQlX+elMXpuKxgVXcT t1C1rWSU1XIkHD0G4JGK5AIqMcBnu6KwbiBLAgbgck0bzmILWQj77ne+P8YTfaky35V5rhyn+SBq XWXGr2tzSvxRuTsbY/Uz/7OHSFWsu7XSRhGmaCneIdkEaC3mBkTbxgpmk9ohAMfQRDx0wraljieD qF8NiSO9PiCTMDRnJweD7qvRPNVbU7HyOpW+vYUEYDedipujcQS3vuabrNIbw3HzgTDqI5dmBuXs xfGP3D2kbeTzfbKt42IOcW79S+Rl2R3CSE9mmi3DylpvQxxurW3qBWqAxRYDhpvS0y8pSIOf8TSU htgEsm59w5ETuQkc9v8cKZsWSw1E1YWTTOINA6xZYyljgmpB1dM6EtZ4Nlcttz5uJMtzwbBNjH0J SmbKEBX2W1Z/rMbA1LGzjEprYDieI0sCZ7sjmlS9hEwSNzKZkdUZSqFUO4QJIJQ4Acw49Sq+4koK zTKy+le6mFU4O20ehDgqTKppo/cVHMH+gLi/gKS2T9w9uNlNtbj4I/pkXlYQZohmu9cejJR+SeWi DySpZXvKy5v2BiiqXog5ooMcIitKr4fChDL+eGYXkptMvQwyIaCjcoVcJC1ZhYl4UUvmfCjWwnGh Y6gjruefPLL4b6bazeoM4TP0Xn40/LR66Dz7vAvvPDqwFH2INEwDTLtoeaZEI628TnSVciI0pdLa tFxO17LaR/hos5BL1VchRyk5dV4FRusy8E1TUt0M2FTh3doKmeJHXsaJB4jJAzF9YN1gEmXd7Kn1 L2K2kZOkS99ugWP1Q8YHbUnUWiOeriO92QjoVg2Tm4T1MPbIkXqQjKc+jMikWg5U9E4NXCik5fWD qVdaaF8L8uOsAfdaYlhv9gNqlx8OPX3wbcg2n6wF7Sl2utBH4m7WciVKLoLL62oM/GkmgzSpUvut TPuVn7cx+9l4rAFWVTuMnGUheZaLNuKLHpPpEdvg0wgcZ1v+7BcwXNMxdZ8h16qVqBrkL2N50af+ e/vRzuIjvr37kFWE1lTLnjfmjPs1YkX5wzqqiOjLqPfg6ka57a5lIBh1cUp3tqygu99+HLYqiizu FW8puqBKJDjEvYSkpKTGAHKYn9mOcusQKy3ofwiZzRVJFZqBAr6FJ+OnUeisjXTLnX6Qorhuvq54 kX/5qTXwFI0sgDLpBJThMqxrhHHeMt+gVbAqDktFBykO3tAvHIHQfpuHyOV3p7j4CzsjZiRs8Tde bxkVj9oyN2wpwBhMu2WqmmB/9aHahGAaoBSqMXGBHXRhHSftDL0b9+tKEP+m1q25EFjw2YZT7R5a d96/xq+7XPt7HqpbMwFvfbRPn6PklmCHrevZQIKBPtzjb3giRIIPmVt0cH3sZscyU2e9XWCeNrB5 FsNTzVZHYMdF8RDiXYWZgnNd422skc3nk0V5/6VwPYES0y+U8X6LBp8K0eVvMNWhLOaCgnAZSH/8 rjyHTJ0uB6bRPPHVtoFurp6tsMrslCMq+VAdmfj8OCulupeWXHBhEWyNHffxAPdKpaZZcxA2CxTo hDqX/PLGCoin0Sb74ADGYt4tKTgm8+kDwDAPynoRjqBnUnd0F/BBMfpf17E3JCMLoI5/JrzDmEH0 J6nYy6WmSaRW5D27TxssaYMQ4J8v8cC0zdFjR1JakWFh10VeTELsJ6syOv/RCVA10KxqLPKFMXUi XbEmR8YqV4MooAq/tJG/S9IVPK2ORDnGz87zT6RDNSNMeIoVJl5ptsWX/1cuiDu1c3USVy6kpUkj LGnvMhkVermGJjSIIq5YtPr37xIfcXOxmMWSO+HGfVe3OLCwudyQak/qsXLcWd9qNnm/ABp5y7Fy vDNWTiGx7FFacLDenCzQ7gjbAJyGS9CZpKXtckRQxonnPkP/wSXSmyQqdJiswCWFyOSUo7YWy6A8 VhFOArZwc9wmRypgFKxw86rAmxxjw67AKz/hJuenEoW2b6YVuOHTrqet07E2wti1v6nAW+Y93Wdu 7c36uCCYU5NqF3tdH8TMsOy3iDidBjHl9low9qmGAerpX0bIrBIui+oA+s1EhHrL5YDArCh8Rc+c ocZ77CqMWVjXl94qyX+eWjzAcVLvbf9qytIeGQeUxOrhHP92t5+Cf9ctc43Ra93DNiIx3Ll6ltZs a1B3acSsX/sIF/rSgxZqAW6Wi3+/x3j0fqhgM2Ygjbgvco7RlEZ9NF2RYwrTXcLRGhaeWuZAs4MH +sXm7QlubVtEvS+QTnr2LdJxi7e0P623z53SBjgF9bRISBKnlWFOUkgD/DgSLO2obit3PZh0vvgK XQQjPvlqs7sv9fz6QeUIWOlcfA1APNLh7WUscHmQCK3rEEKx7PRG1jVs2XKmD/1/BhceIgOUNTwR GPdQfcXpvI8pB6aCSNI2JJNYEhbC250O8ObjgphBGBr7/NZeCiPjPtRQVQnhWiv67GSbS7nNifT6 QpJccElgvw9nkakCDYg77z8Pq9jTlyrey/jWiH4jbkxetn0dojq/l7u0B15m3bQ+4IMpbUlfdNe/ SyGVWnvx67xT/3TxykI+Qk63TX9zFtblxgdumm7WghpkLIZwmXvBV+CoQMBpSkuAXyelmniO5cXb AD49kFo5mRrb5WDNTXKayP9sDy48a1qhr3IvgYLlGH4S70MBW9pREbsUvrUfS0iPr63NDfTx/x7J XFdt1n32kbWETWnIg0jZYZ2mxtJAvFiOq6XbnnBQYGm/gqAnfq6WuupgewpgWoMEXoLxxmU6uxJH 0r5nYI7xFvRfx/ZDDEwce/yssoncWzsgmdaeQZZMJDYZfQGE9/bRp+GgyS08cMuJnO5ctaT8JwcA BTa5BEHX3ZWhUXhAT4OwgiQYM6EcaoRkJbkfYy96O2udl2pnD/y9tk6Q+68D6zZJm6MzknMsaIn3 ZkL+PRHy2vG6V8pFNBWdmKBEIazQuIMGBwkq/eqLi2MJH446hF+GCIFyMgwQFgkEo4wyl0gsLmmD b7NvTZgdmEkzWPjTOyWl6YwKkwYeNeWW5PQAD32G1slTVUCZezQP3lgHOL6hVSgxPLNxFHgAZp2/ 2rtX9kdVYtuAwBkrpvIe2Wogx4zaXJ+qeqnsWSWBJYtEZHCCLC2ovx1S850tP6RQNtRqBfKjq5qR KzRk4tLZuKjoCWk14OhPZgQB6Xl3TjZ0Q+VX1O29SwBHmQHyIp2RcHn5v3cBoGqSubjpRw8lNYxW wg6f5dtx97rDLBA3udwQ376Ss3cJTkf7c6EelzOeSqGcJBRPucMHhklE1fXx4YXl4JmrB8PIQ6uw pE3q8IH9LlalPCpwnx5DquwyisqaXlqQouZonbf2KxXReJuN8Pd/IFvT3ttot54SpDL9BOcpP+AM ztzN4IrUSQCXBD2qclaYd9yQHgz4rbPmwVOEAstbg+Cj7XmbdpeXecIfsc+znA18Xaoi/TpQLv4J vcZ6zdsbV26EfpOkBvWKmT4r7atqmbQbz+hxRu29ppA7jzohx0u0r9HqMbVIKnhZ+OVL+QjzW2yC QGs8J37XE94Md5FNxpiURnq+s+vcc3j2b7439BG/mvM/fomHv7ZmsISohik9pCocB9gXdv2rnjAN Cp481TLXCBKfeMQn18/eeKriaOcDGj9b7O8b84aR56/ahwgyVuQaMRRCcxpQ6oEB3MWz1Rf7x++p P8QmtKEByzw8hbupNNdNIPRdgiutvFqpZpLqRgbiqKmTmzGA5shRULrycIhQwvgef1bzmh1nL/AB /YbV8F7+KwFyo7PD5GidTlUivMhwdC+QAH2hP4a9xfyRV1Dft5LPAvtaf1y58XKQOVLG5CXVcQyh db39mG07n1Kcr8nyJmGLPWQMfVkxb4iN5+S/ua8J994ZFBsxvLGqN8sOOkiQRX9T6jZUntK+vZ8R 3EStMGdG3mFezQ/jcKo8w/XNO2pkzXzA8hjLqKGTW9lyvrM1kpiTbtTTRSVqwBCSbYCcngrqNltV bBR/XSPZOvp6V9D4B28u00WqXRvxToI//vLl1Qs2ilmHn/wBfl1jROC7JOxULLEUXwUZqmRdM89T ERGN2tbsLHXYGZNEHHmbUZzkcrzr+kNkXTi9JxG50x4ZihszLXzcxlSciEfdE7dlcqVnkPmBXQMo GI+PPSbmgCRHQDZA0I//xFw7yBeCVsGWj66vgUwED/Wp+WW3MHZmO0mTQz/hzR7T+VXmIHV6ZFcZ MiNGu6UxiPTQbNNUwiOvRSoewN8jyyupHIFytBiiBElscaXHjldMkZo64JltFjnn2F+Cc/SrHqMh cjx1q9TqzTrCH6QrUOTZiOX1a3kw7mrofAr3g0wd+u6RWFQNwcUQnxvgXV501NCqd7aFZnP/KhRR +ktQTaxDeK/atq8IcA698W02KDb7UABR7F4YKuPIRhO3omG/WnY5iONzKsdytSNjcyLR61y3S9Ge obdCs2fEaw9t5keQEAmIRDttdDbvCFvacfgjXGSbF7QspqLr/NxmkiS7SG45leSzMYCyYxhiA+yx SFCQ5RKDG3kHYq4rBtxdTM8PJoDroCC0b/S+yo6d6O7hdSAoM+P5irbH3Z6AQXqvCUzWWIZxAWOy SulAdvHq/nea0Alr9u9nVU/yaS5Ljs0I8xH1DrXWWCCBq7jRDxfGppGyzJwmXrm9oRWmGvo1hbRM /ofM23Ou4IDr2/Ecfjc+qMxuXuJh/dArhQzHCvQqXGkUBUpkR7zMwZ9E/t+gf/07awAyTNW32ZVJ Ic3YiBoIzYb8flzHV4bOUcloDFC/hiZ+3Fw1splzkx9IV5kdfxx78XHgTDCg+xPyo599TRL0oWF0 Ss5EZLY6Vj0+1l+2WjPX6OCpjKBuDoplAmcRO1TS4Ph/uOCBkEFFFWyc5yBZLz4a2FUWolj2O2Uo Y1wx5w63oaJOkccNNGc4a5Bzc3gHUQiGIrWOE/UPBP11m/onPiyyvdHlbrSpLjWXvnvNQJ5ajQ1z jUDXh2o67wMd6SAmQ1wnKbQwm5+rWtEEZIikVyi6lhrg5JPxH8zVlLc1l/JowYqW/UnauXHWbDhP 5wN8LQ+bCn+Ci8QtPsxzy/1iRKw6lYDhtHt/pPL2IaNwEOYuS6k4t7rmWeI8++53C22ltNZB3NN6 nBUijcHHNtxfmlT6ot4cw9qM/PEzSXubzo5nVpKMRN522zgduCcgXGBi4kObp/bVTuN3lDDZ+4tG 9Ol40/FioY2VqB8q4LtthkiWgXeFkex3KOuj8gQST1hUvrK022PX1ISsDhSuu0yMDksX8MvWZh2b 5b/E0Pw7c6z1+yL1Jb9EDqRIqmwKyc5b0cn0AWohzySHn+Xquxn6frUCOH758Y631gj5ZtjRAbXZ iuqpvnolFZTL32FayNziUrV4FI+/o694/Wm7+aoCLNWpxTjA79c21/rpL1HJwmWk7sPTKic5V7bh nreKBlMdrBQOQnbAvzKqeMgK3IZeYAwQb1LZgXc10gaW6Qwqs1QFEdisP9J+fFizgFNYdrJYv9vL w1HE6YJNcGO9cb/A4YfMUruTg0KwOFGX1plsyfDSHWhz5iFrq8IGKs+6bXjyOF4UC37FKYKpQ7Av 5jUF4vRzA/y0lb8eMRXIgsKJA0AAiBYrQfGKLpUrHp/UNeVTdo2Y9yVRiJtsxWvMEXVaJvOm1ZYg aauxcIQoNaWcp1soZb4PsHKrAolBqDBnFYuINR6yx7lr2oeBflNOgl+93a3JrYP2IzaMqnOw77l5 G+c+hSZsCSot56ZPU9qeBCKeCJH60s8pBtThbneuyiqw3zqh7B4xC0HJe6gwknHqkLlSOYZk73ID uiRb9C70FQdnv7yT6tzMzQRZKvwY78TlnIf4FBM4gdn6XjxyKoPsz8PGCp+4ZZsBsXz41lg4rjvW tl6KHFHIn1LPK1cscn130e++cqyjHq02Xuzc421c+3jDJbDVx9VuULNnZv5CUQh2vng2Ss8h0sjj XvRUK8ybgdvRsvZkbE99GRvckHBEipbKAJIWnVu+O0hpbNDC+v6nS4LeIKYE8/0N51wuVHCTOMgw ECBMXXINMm912vQbc/MxevtRRuUsTDHLJP3N+1eiTb80VGMABnHPSPQPHwmtdkDWDMb8jwnd79ZM gO1pSAV7sOeXG1pqb321sW+x9Sg90z260eg2sE437wHi3K06HIb88eA0IcQrDMyzkKM0LdAdf/GI 3G+xr0Jd27qwfMQ0YvQKhQ/T4Uu/Xzwu3gRLzpwo9/pzC1iEiGhAy2+V0zVIaujXIFSLRAo1VRgn u/NhRAzr/PlOowqUKWnRygx86X4QxHaZTvCDVpZ2YYTTEvkNS/RTOT7TPFOODYycouhAHNuuCXWf x/ukTwpGwHssVIDtc01aRDak0MD2ZdfiAJvWEs3OElFAhVhdrRdE4gb3izAncG9q+C+f81VSpvs9 QqLoSaxK61Oy6eKTgr7G2vs8uEuuFNhqWyAAKU3kog440z+tOqL/g59xHvowrX2nIxU1u0x5/IYQ VvVR5THnTMnbWdKYInsDq63elKRsrhBxG0y55T9F6lUbdVGo2yiIxCcO6LxCc3QfFdN/ndTR2/08 rCetDEAswLzOeNUXp14Ur5IU6e2BJYM9VWtUYcQ+2r9kO2XTvZ3jkkpqK79lx8SyK77ThIoJLFw3 nzPAuOG+gRXiIVsmjG809vy4u+5QiMdsFPYM0XP3deZrAI99KfpzzZ2tatfGxGlUJmE6kTIxnxZU WTGecxCnbi4qGn5EkX1ZTVwAKij2x3uLotnYJP7lkA5wJ0WaxaOy0wNQvNKRmWyp3CAJ035vBhBF 5gGDs77bk4SASSl9n5Mn4BB6FtgRUKklMeD42BaNgpCoR84k44I3nAlOXx5aKghf0nFeMAaTVf3/ q7ZOhZt0ggUJbBAX7vOFRr37wWt3LT7h710Ka3U+DJ7ZScJGlPthppSiaJKz5QJy9HS6MjTTHOEk eUforZ935+EhX3KF7N63Ni2Aa4RafCxj7qGQRqmzPcmS1/7YeFsfNVMM1/KejVy0j69Nlm0+dq1k dTAeiKpSdEiFpVun3kIyaBn8jyqttFB3wAodYuzO5lbtMFyM5wjS3Ng/MbT+uPVj29HgPzYSPQyY e0ISzGWMmmBc9dgugPX6oYoficgd3m9ft82WrQDX18aZNjcvE142WliYWKZIyQM7zLJ+XT9GOQiW irHEJ65aEjnGnrgwWj9JZtQJlKIj07poh8rnQQRms2i4PQh3rQ8GOnglRIjhZHbifGs3LNoJf//b g9xH1mxN7PCXfVtCxZccUf5tjUOM53Y2ZpL8ENd2aYEAQ4fPZkrCgZhfzWE6zDniULI8sYO15Lwg orChQ+dfgB4g8x9DEQ3ekW0gOmEH0tp4obpuyMO5ECU8rDyqkZ3vECSbHa6bKZXqpSbMuQhwdg1l stUYvYhwxRX3a1bbOmNyFX9q/nfzGuh6u+spdh3Jg8zCQIoY/ctndrgUb8S7XD2D1IDb8bPMkQ3B oBtJUTRBmaS+1SLiK8PvgPOktRcHVDvUUBfQptZrzJFj/yiSfmqUQxRopPwYwYrdAeOLuOkbnRs6 /pJyedDOuCGEpWe3NX/1+RwqKzKdsQteh2dDks6kDfwWfGlUvxqH/5ulh/qu8ByEtiSonPARwYHc 0JWztIYzAfe1T7dT7su5XZAdBjSFk2hqJi10ETej7G5QznVIkmIwqct+zl2wFqNysI2pyhxx4J4O C3vi/O6wX4IBO6cMAnKy+M5zvYqwC/eKul07W10MHDafuv6q1+p9SlY6W+/mRHmoeRAEFTmrJANd 2XUnQBWbANZVSrkIHXUdBTXi4obmGpvH1Blk9II7LjOular9fw1MS14FY+PB/h2EOcfKypHjsqyi Ryn5MDaXXELI5TbhM1N+bSCmq/OGnFknsrJPUalu9arkntCJTcwgs3WCT4H6vNul+ihj7G8pmS30 ldleixNqB8s50VOV1UQ2CPm3vrLxlJ7dAK+IncAtx2j27iWE0iCUa7GsoAyZ5pk16CpXn1f7s2kQ qLXE8P5ihNisd2wCPqiXu2Omty2xc+32tlMPDTnKX5BjE6KlMKMTEayo8oysFImLiLaVuYbX/8uy QRrryA7HFdC1j5C1jbGCFpBd8Kt1rxCV0/FuzkqNLBmFkigOcpH5cYTOXmGFkVtsMpwp7Q1ND9ZO l9kfytRZLv7CVqR2MxKa9pt5ew1UUTy0mQwSnQ8T3vXEM6nhIHyfUwfZ2zkScp+KrUrP4wfcUzSo 8CGKEDu/ngfyaFMwZnVTGYAHevZE5KFjDYW658iqiVKZrx0Ir/vpodsFnTDxmgbqFE9hAzlJh8HU 4+I6VFiFN8AgtoTjhsnifPVbXzrK52FsnoIjAHQGIPy0njKC5iru2yQK4xaGgYjh6PYCEbhlMD62 zjiVTfXU1IQUtaB0QZWs21OtV8l/T4FRvF3LFiGb+roadEW2A8Wtrjiqm8r7r/E44KVQaTJ68Dd6 8xagTGO2OyRCtIS+qtfu+A9u6H9JBHe9EI4xK68F8BLOk4qhDaYn7kv8rOnlNLHTZEEeUVcF+y7p oV5NW/bP+xOWnwSNTTEmrZhN7x9sjO1/zen22ypzaWbsiLcehVVJTEkWW4vbMDsurnEysp02QbBh 33+PY0l3o/R0e8PzGKMmgwDeQo1Qiufy4aPuCCCqw319j4JHG+Hyd2EtgK6khQKP88XtAbot6PEi IT5Ucj2bDuMBafDIjofG3Z5pgcMZygVu6AmR5blIIldnmEEX97MV8bKfei5cYHB9yaQfUqlUDqTH MsJwcDE2dsihuady7sr2uVg4jeBkk5xmbxi6lZJDnacGap2mHqo8yYOJ0FWRbuXHttb1y1jgozHE VFUxcn2loru1BIhC5ySZyyj5w+TGYRQlws1ypfOpGCx31x2XygN2LdCj+yhNCRpS1hAJMHN8jSsK wC6HK0OnNIO5cQEJIGaeI4YAnOWsgtt+plKLKmt40Qr4ToHHv+vGE4qCPkGD/PGvtwFH0UJuQxXe P012udphL6EmL2j1AKNurMedQv+X7HAPezMtuXIFyblnxb07g0USAmEiyACGhFYKdYdJHLvbVbCm AOWxRffr/+l5jNHhQARe7vaCuT9iCCwpLShXntzEo2lowxTvnRTL1PgD8ELoTY6ilyFnA1OqF2mT RDI32byX8R7NYIHDWXn72pcgjUGDSm1SKMJNXkwo+RCWAqb2mPOMCVwff7al380PHEM85gQy/LuN 6wtu34AOuwpey5g/wvCcXLyiDGneAH7NWLPkEU56U6e3XFH6amtYqly9NhW4aHWWTdgPtRg8Siqr o+kH/UxaYGJiroXAb17Co6K9FiIbFN2eRap47/tJPRww2K/aRbmJlOz4ejZJuJkwZu8g2i9Babev 9Ry7ZKXi4MZJs6Avs5gCB/bMi/OQUP0w3pcx4lL5r5CB3GDJNB995u3BPOC9QDhDNZs+On508F+7 zIjA3cuwvbA2TpIaGhXwEYdiBw+H/c6PfBlfFpPv1tQozJpZTmLdB6361GZxY9lGNqV7RDSC22P1 dMg4iGVAcFc4FZgDXxoNqHUhixlsNn6uU5OnQjj53nY64NTHlZhHwxMT+CNkaofgDRrYw+h995qr GekIBl087BVpAK80VOyvIgK5ehRhGF2uk6YIqm6qGHQoB+fN+XspRYe0VxplYLcIZk/hYXSoF2Bk Aq50/WYJtyONKCf8iVnUmD5OcotP4HCLjoXcSwCC9JwWcat6a+dbKvG2jVdCuwurb8M0VdB56fEB Mpo7/8NsHZuZDWyR0WhTFbN7RqUvrXbtecuDd4clpY9P0Ubx2mAabEqKjJs6ummHyjCNNQzvp4IE B+vpcYsbDG4rLjBZMaxRphExUN+NAnO5rAqMp/H1enerFyxoxitR4ZbEyIxcyH1Tz6togQm4IXx0 sQFVMKPLa6PtkaHtt/UR0XI1+WbAo+VE3AaQKEtmZ5fCLY9FtfovarXuqURZzPc1zi4rnRRNjc/4 LWW/ADHM1ozAoZ0ZLgPLY4YNtz3iWhPySqEuZZJOnrrMnExnHFcnRYAfHui/Qy23ETv4QM1lWfSV AQbr/VbQBGRUb1F29J68rizVU86Aa8EQBVSV0JWmAHBH0tPlpnSukhj/FQax97CGjyEFn9mQkXYQ zQD1eg/VuCmhdCXiPi3UsEyXGR2hMcUWvSGowJ9PqY8lw6ezmGJXs3lii+17zEz5krdRHXh0HgOH zoDSswYRPZ4umOMULdSmpePktWdKlqnlMF0G3QI2UnczmLyzfq7t7zMtPBddr8w3q5U4JTwBAKPY /fhV+aryF5lnlHB45ci6n4KLRzWwAFtElU2F/wykCiOjzvYWo1iztrBBC+Hxj3Tlf4qqIfVZShHO mBSXh9VbF97xqiRIhZ7uMoXfGJouN4q3GA5qLFmqCh54CDd6EqaitZ6tWAyp/Ba7dmU2VQRTKYiN 9+bzgwZxLaH8UOkyP9JQZIPCSzbVY48tWGm3C4rvm6eWVdi5LwmOPGw71z/WBycE3wfWlUfoqios VcWx1XhgbqisoiAyGW6ktnnX8/jK+qNjYWhsqE9eL/L82NluuEAwEATcLz2Rfwb27YdA+M26xqdN 9s+hTAe9L0Jztwzr9ei/qkEhwCywYmVzab6v6LBhRwi+WSWhrlrqOxfpr2kLkHUZ9ASgezorwivr isRjP/E34TZ+kWQUjrr+fU509bmEpR8+9CM3HbdPud8499ub/054QEbVGMWUAQ2DjYNZjSnP+IRP Z7QFRCF3COhEAQQbJdSdTW1u1gKlGItsgp8FmHE7pwAkOTosBy6/X+BAjdE68yvJ7ZiIJOmyHGOE 1hfOFO06etYxyaB/HoVFQWwHwjf8YvPDzxRQ8xAD4jOvELKc+9uXsKQzAJpjiPm1s8ilnA31Rg4P M77MPngwGblOFqsSBVdJXiMowwo97YJ93oQi0xYWyqPnqiIlNBgVltENI2bjh18O0H/Mpz7CZe/+ uHZiA7iy2PEgcOeNh22wpmcSjaabdDgPcW6LGoBIVZvk1JqwoVxQLGcOljPVGGsbroGMc56NZ0uB D3ERzkZSg7mU9iyR4Ohex6U3NHdSy2+CisS3rdjnPNvbJvhsUCDOrXJawlmgfXkpufWom3ZANNRa SGjLONRylW4TGKCFQGhO70t9WQWFdwkDjkT+dtsrwHCGkC8LTZDoymRLtHmOy52IRIgDzNcFKycp k9bRbI5kzCzcc7FEM9/MJ4gGGbsPCz/AHZtZxNqKwqJsuLP6tSzrpltnlfCLcYAEiT+BG4+DB5JT NTH2H1npxIVCPU5BacT/csTFH9nTXLPoWChFSqLzuP09zwvBJZ5N9x2AK4Pz3krxmHqgEnvaGpSy hPSRRH2E6vKX+IF9s/YfD9vyVgrhjYn41B7OxxbY2+44VSrw/hFap214MxFEqxC6k4JSZVBm+2A+ cBP6JZNTAOKW7xU7mcaNihNPh6Zsiqo2qMOFs9T4TPE4MoKBUt43Fksj3RcG6rYyzmugzNZClWDY Gj+992KepXq194pJxGFR1isAWjF+8DdcGoty/AyzoRz4oVb86D5MoAyjDjISaFhm0qomB7Uxdgcu yTI5szzUHUuCu4be2oadGzxj8Nf9jUGFgsZFo2xeb+UPRd7ClL8qzC+hGv+DJeEyYbQ+Kzoa31xM YmFgHrKsMnyQdhEzP1C8paR2BRi9+gjTwSXjNkSjFMDAuB7AlunTcCoK/kNJDEHhgYU42milmWXL +XoYGvcuppGXiSmEvFxnIpVQa+UAa0cdTgVHhWOqZrGoI/nOtFwXRv0mV+pCHXF0IrkfA/huyQFS d4dc6ezTPjDvjbKl3oeOXyaa4B/zr6a9xLcMaWiAR7ZCiO7Yvt8OUtLWlxuahlu5XUpD265WMpAg z4TV+pfo9TXKQM6gklg61BLRjIEY3VNSMmZWH4h7ErAsY6tDMxIzcJ2fxuUT8QygEbvaVUhFPxdQ DuDRYrI1+l+HJUCu7KIPj0HoMRiRf2eGJLESiuIqFo8YdThQflpFX1MdA7iRxVHnYlPYUJQu/mDV DmsntfkhYbTii09JlX7bg0QA2AwtfciANE4UEgQ3/ZYBnYLmMJwjAL8imIOGVBQmFF3irpHtq4T+ 2b+Q23QrhxKFY06VWmfu33Cty2inRY9Egk9y9aKIncBx6vqHuu2BdPm3bvyLm6VD5ccJjf71IZFD pgoM8N4kXSOgsvzW3kht/Bs612vrRpXah4naHHjxS1gA86tWRS3EBjnO6BgJZu0LX79H1+TxZcWu 15PQs2eEbyL8jEWxZjKSQ3Wcm1fk+qgkECkALkwobfd4Pt7wIHXLdXAOTnf66tYL2XjEIwUvuORa PBM7ja/fjcM3EXHMGxwMsAuK3SPHxdWbN9hDz0+zIrQkRp2wIsz1vvF6lvG8zAcnGDNJIPLogpzl 9JJo4nZKNNO9kCtq7nH97ruGG4XbzAvTGmNeJkjVqBhpQ3XTwwQnUw29LA43n7ugxbdn4yr/LTmw 8WjzdwUj05B181B1DN6W6ubfeUYhRfFV/fVpj+gC67TWF47FFlu0JI+rJIcS7Zvklc1glAkYkYBP RettUR9NGkcGXuF/qeUgmTW/eG3Vfo8GUeKdZsJIfuFpqaPuAT7k/MtI21YgnV6VRM5bWADArsx6 tq7uJFo3f+0zJnt/XZTP4SXlbMo7qXH16q3ppV5wi+Ap+3TB1BQDnyQ6dbrCR+lRXbW+Lds5LoPG qSf3al1vnv/MUanWk45hgzHCNMHyd5HgahaPZ+RpjbSTZ7cWlTrkUcgnfpFGBTcci1u/zPKugnA2 EzKI3OMRcMyuYDYIptmXpkpMF/rj4yVnstxQDNPb5ED7XzSPEwzDoA8d/6izzXtzEPEYB1tFb4Lq 9CyghAWNy0d2vYBt+ZoS2VfuJ98TlFnReqODTtZ5Mm6M1lMWCE1hQFZpGdIYkKb4mi8QwOwnxd04 3na5/OmJ8XI5vQsyNA/dnGeduPt5SUIdl5ndOKtbMUnPszs0B6xfQLhccur87zagmQKADGoV+LG9 gkJnehA70bkWdvvinknPvrK5+szj83tGFwRlMESOBNitz6aOsZD4J4hGZfoNgb1rp0Sd2lCXQ5QN CLoziFaOLJN2gAJ/+a/eP9FuQQi0FipNX3b1e85zRyczfeIvZYUcZRC3MFzpstnmclaqD/AZ1XQA axIqp3/pu3NUU4gyterBnKd4rG6c4OnD3ico869cx/AZ4eaZrv7zQdPwounEdFQfM20zhxWCZb90 Fde89rmHPeCs6EFXKFAQF4TRrHcit32arXoS3QKSp3+b1CjF4E2oK0DO72HwLEDZJ2tOGFC+GbJC 5sObduJmuHmxhMo6NIrP2N4++mDw01cnnYIFdFEFZ+7QQ3cVsyEllWyT9Ii+t6ez3cNSqG67ZGKp jd/ApDDJSctnRh/zn51eidMvflfHh6CTn7JWLvOHnRmCO/aPYEdu+CrUBrDbUbHsTRRGFQcRQPkJ DPQ8ej9lrFBCP1gK2AbjNFFPHBDBqur0fwL+tsmCgRAp5qwZ/VrPCSSqvDLLN8Z5ncn9YlpXLOpE DiDLPxnzodGaV/tV87y8tnVff1YNQONSVItK3dHnMvSDj24nVmPhK99Js+HzbxtvvQpNKRhqWUMH cQ3mXRpS0qEZ7tMgEWgNGb7yHvs0btJJa5Q6CVR2ONpun1hmfwmUeXRZ54Oy1XrJVBKltzY0Afob fDn2htJyldQr+AKz90MY6WHKfkYNG11ZgRuOAQoT+/tMTrXn6xjN1pvaw0eizM0f5vGu/TiSFGAG M431ahXtfD8oN1ThUxhwvWVt8fQThO8VfQDZ5eqsEWv1F2Pm/N2q39S3TFLSyRGGT6Nh/zop+pBa LOr5WeEM+XCwds3h3vPPiYzBqz+zAEWEMkX0hfnnm3zms5n2AWxh5A4kdDfnAjdTafCWFRqeaidM XiQXZa6oskIpqQNaDXp08jW2Pqu94qdbDUQw7NwLoJQDmRBqqBe6sa1hxwjTkC4M8SdobmN13UEb FitHsG7JKz8QfwnhcwjVgBPE+kPEPwu5tJ7Hqr40j8jGazoO7mOa3hWiTTj+w4oMgI9dp4+YsvS0 gR13xYNqex7vb8rOXbISAlM+L/rWZVySU6iQfK/mT0i3GX0au7uuetzn92bcxsn9ZiMGwRCoTGo2 CgKeFQFUeDfKUH5Gbd97sQuL2H0Y/p1z5N1L459nR0IJsQ+yjsUMrF+FPhrUMsDgIYEZL+JA6a4K TskTR2lg5gGdBtAbDNV+oKumL26osyf8kanStbe8ezM3y/k+1IdMIyNMQFo7pxUf8f21Vj19fsYu xDQRL1klvM25iQkjoyrxdDnPUKQaVgop9xPfVtZAx3PfpS2lz0dVKYl4mf5pdYTNPI5r3giF+pTo i3ORt8yxoLUA471IsoGjcs/ng3U2FLV/IX2Lx4rxU7kJuFkjfaFb8rt2ch1f14luWpDysHQx2LY3 4Pc0dVum0Lb+yRmC0wBhBW55ZyBASCns3EDbFLwYr2ZDwBg1x6UczJaKq2kYQoT89+NT8HOcT//v XUHxAYQTcxdiwutMiZdC9z9r0fmAc3j6Inp7OCWT2K82sayaLRURVSDb7icBvEpqvhxvTCAveHM5 0KO/+4kWVysi69YFMfbcSogaauV/FJV8Q2t5Wn5McCg2AjhcOeoCoBXQyXMAwzB176tZPAateGTF eiqnpXiBDkheXDgCw0BT2bQ9AlQS50aq9wbanA/DymDGf1xHv6s7R5yadv/XA/b5p7m9gWT+LVU8 cEWDMc7lnFnPp2X2XQxuVy9c7pfMiwZrKRwg1gmWO4J+5pLai6YEU0tIdaBxo3TArDJemW1kBalz xFrKjsOhV4wNBEpC9a0H8yxSHBkhM9m6mNCULzi91Efe7gws7Lhwg1NZn2fdtGm3PvHFkO7EpQ4X liCtz10mdbWo0TKQ3WssOCjSAECWcwAwFOiHf5K+CHyPIb8GgPU3AxNIJUL+L7ST41cvFwu8KXQY M2LZaA2JDQW4OewFvxx6K37m/txN00QubVmwfsMxcgejiXqE8pe5pRgyX8blD1U2bobEiZ6qqylB d/vPQ7MTusEl/UygceTy0ODRvG2RT/A+ABkSpAYceOLLQKTvoGwqVy7qaiXiqcL+V0BjM1X3RYur Lve0ouIcsrqUK7eswR/5GLK0KfwjmNsa3buVUwRmzcyUof+srLPGvJ+vK29tJF5ax3lvua+F6Zme W4SCaXwWZVglK63ZBfwUtKBXz9A5aqJUgHLw19BC4bS5pZd5PQ4jHOn1tGZEbL9f1hLggzI1LpjO 4pcAlEhq5t+h0Kyi8UNPbZ/pelWpYEQ6GMGUeUFzy8WafEK77JsNRwvPGALGtCZSPedPBLJ1WxQz 3hSSqKvUk2SpFTT1QNBzAfHrv1aR+RD58m5eRL7KuMDwSlYNwKV0HM3U4K2q2g9XQCe+MEMr5ZAY OfWlsNRaoilMkc4HWP+PIsc6FbXTMXy1EDiKfei7nlm7ymFxYTmZDBObxl9FTXkwOLz0Qu0b4ZLf 7UA8ygZaVM6aO002e7lQ4R0bp53xAgtVnIriDYiXQO6HO52G41EpN2wAC1k+kOdgcvIGfuX55nqw GKbLbMgvFbL3wntM9BLFAEjhAi0nu+55GIXNIA2YyVXPi5A4R9SHqDVUt6gWFZ4LA1llveVa2s8W ioqzsQJevmLKOQ8/gI8SIKttWDHUZu6pL55oGrmR+WLTimgn/qCHT1rfWbJ6/Q/1UZlOkOsycree rPfkngrI6kdNGENSyNpKfHNKCIaFml3DuTadpSYqAzPCPEl1jz5X5JeTEXD809o66iHaehVbemI/ LsRsmEG8dEq2sfso+gL5u1JsmTolvMBRzLo1GC43tRhcRIS48/RKKnSspVDie4bRWkaWKfILTl3K Wrkw2/G6uchho6n7nvl38YSScLy8AMnm6ATk7TMORszYmMBEBzBrElrdg5B5VbWY7aVHnTnLcq49 QcHiKaqzWTi6Q/LZZIf9mVHki98/hiff5g8Tkc7TYuf3ePxX718Xi5xcTBA6X5UHg5eDcdG048xF 6YV/ri1oCwFK5thuEJAAr+d2jTBMLl8aWy+g79ku6kObbU4n0oY3arL5YIhuqRilvABoHluMHDF/ NpUFrg/gMKdqpMd16qithvYac/EoYVXsQW2bmJMrhV47c8h1vIebmmZE+2y6VcUVLNzSQmcnTuz1 aTyEPC779K8zSIObmhQ5rh6GJFxZA3P+eppWnWcrTho6d5kipr0hYyPEAMovKy5vwX46JRBj7Fvm IGvBjCb6iv+y1EjA5hSsEkNYZNW9jg18NRuHTB+OLTfh4mEB+Z/UJLuQlo5IN/9do3M1h16EoS1H ge6S71Cgg9jccyu/zw2oAKnWbD9T8O3SOWgiJlCj0TtgsZKWFkHnx7kJtwbtJtVSpNoYlgW5OuP+ z4we+4CI1sNNAW4sEWiXWpqlrfWa5KzNg/RCqcZK1dQ65cmE5faPIYljZZiOoiW9803nwhOBhGgf wcseeDOJi2tjpQU5iyQ4Xdp0rMRt9zY0sdg8mQHUYMMhn3aa93V5ZM5YCK26PV2I/PMoPohpqNoq keGFvW5J3SqHDM6CY6orA/5v9O37R6ujXcjp+U+VLWEz0V0Ks42cERwKoRFCUWdDAdpZEOo4LIgi +6eJqhlkYNX1HMOYEzOoBXclvgnfyEZu4veI8ERAbHP65gaSVVN8U9rCgBb5b69GLXfZPcClURaJ mviKLbE0a+MnfABGSdUKlY6hMT9XYjE4QXyoYoFkf5jKmnhF968KP1P+CXZrQMwBc3Y8876ZYh+5 pPAAom29sQGsWPgdjK5oFSoZGlf1iWtnX5NDPczTFlvF/rS4OvwICELZ+i63jd3T/RRpvnNnfmtu Axkm/av6g/2c+wAj4Lb/sIgBwe2x5rR3Svg0uMv3qO9Zq4T0optD0thGawGQr8/kLOWYWKKJD9YK zLOqUGV8rD+V5Bd0Q6Saq5L2tcZEspoLVZ1jaTXnN5wxUVXY9cdaQvEeWvZucSt3hiF6IQFL+FGD JyvJ8yU9lPtdY0SVXpIdEC1mIisxHbeVxWj2cNdqTBcRpMNh97jH7bncXOgGQLUJAMLaS5j2HL6d NJmTKQUdLMlkgiU5uLhOk0ie7gZfQT/B/kSmWqRL0zjj6gImdCffSHlgZHfnoYthOTAy2gw3+0Rs VcjANOt7xjDPDCsmZA0ryEErnNR8CrDyeSikdXpWXs6sa1z2S9hiRayrKNgR0TjhXmwLxqbNaa9T VsMJX/1GoYcO6MIPt6f6hnMiq8GgLrJCkyZDzCfEyr0wr8Rw+i69FFpa7D1+9v7+U9gyJP8iSVaI ZRZIVdhfHwvv+px3TP6lbqVjKCYOdix8P9n4AOwleLoVBBKj9K4nm7D6bpjHd3ewXwUgE7FHhAZo pblHTO+0muxx3DsdKicsyHrKnRNWSQWy1x5qGp+JjjUtKlk4iGPhhVCqJDIxL4PT+jvViiKaMW5T VO5fDUMO1SHI82rYin0WVqcJr2uO2/lzmDse12ooDrpo+wNoG8529z1oXOHnSDA4udITi2UerLof hKIF1/RtTXGWblWwHdmxNaXIUQDt1vTZPRFCfXbUwOhvhfQE/6UxDDf9G7YfYd453Fxv75d0yWke 8kHDSwWr4zfK3ghvWZI3NcAZX9pV/8ylAyy26cm9d1y/oz+0I2Q9nPEMYNWxAN8Yyxtoh7L5Ngo1 1N8yvtTMurUzCgMlEew1SG9aqCGUn/o5RXIoP5p9+nlsbU1wx4gIxoMHKFOEnG0z3ZtEIJ/L8nQa 1UX/CBVjnzMAVykMPwORFxtLrwzk62tOWO32ZuoZlllJSMh4zT/AptIYllPiOS3LHBwcovjVYf48 LKtyj5oof3evZ8wHzgtjMMjaAwh0qqE4udvjsoSyjMWsCRvcAS2GG6TvmYgjaYFNzSvdE3uiHSOa T/6hjZMSYq2uXH7y6TshJra8bUvv1yrEe/Eo9VPAHNDQOyB/VJk6/icReywYXS3E76GeMaFQVRDc CXcsXGtDr2fdxLYlOJ8iPWk1VspIBLtHM/90VPS4Cmoi2WpwhKmZ2fwLO/OoVKl86kVNxE/7oJL9 M8obRRUljbX8WyCAaJk+ADrnro0G2esXMI/FS5HLczo+aHtaP5vCpCXI6yEi68ylNZwIDm+WngN1 0phwwnIvyS6EIwIpjDa+XWccL8YBHbVoOcOiVwrm4QKKC0j91JESzkfYet/f6EPOsGyDWxzPuSqw wolgY7dYi2Hdg5dtnktSr5WyWk1H4q78l3pWgROhcGnhvXp50ZODEMgg3Ar3fsBrUPiglF9+4w1Q 3gaoQKAuhyY7BFAeSQxYJrdNvMtJmSbkBqg60i9VCkJBWP6IZCxEbUx0W19zA1JHue5RqvBtxCG0 v5+JhG58k6ddXvqesPdFeYU513aH+nS5yubYVgQ/B/OTKMea9CvYisvTXrNXVfVSbmkiCSqQV4fu u+jvyZZrAceZMnyQRb7Wnst3TyQsYKXWyIjbtxOXAqJ7oMWGdhTD3bOFDJC7L/5rvProQVEPotXs zQumrkts/0QfPzjo956NDJOFOR+RjyDJq4/2bt6JLCiJbvfk1cuVPE8Xq30qcxsIzclU048LN3a2 TQ/bLVhMEV+4cghQaJ+HGhyunvI6lgwD9LRi2HrYvspjdCQA8uqO4CynJNTAopetpqYZ68aYwquy JOLrZNuLh7VU3Hjgna55RrrX3hrsgtkzKhO2oQZcmeyc9uU3kFFwuZ9Nx6wYCTZl5f1xXUCxvleS aWdCWgTL6MJn4H1oebuf08PhN/VRVpu3bQ8r/8N5AakevPQ0a0HjJlDSRYA7FzwxJUoOmBw+7C8E bsxGm40rmxDzTPOsbz7IeJ2SWejEYWhhAqoDlHkhHMG0wt2VAbasE2XBG56r3i0a0ypD7qlaQqmy AuRsRIhPEzCgAYEf5ujZPLkgKV8WH0WSasmaVhVjh95IEz93k1PEXfSwzxXgINSZ+J9v2Xz2R/Wo 92+7LWBxBh4reyHEZWtF3wCBq0FKRRBIxEK+g60aQbbXdr9OiyNX+ZUUq4NnAxLuMPdtE/UgP6KH f3qwS6sDUqY2nlv1YuozT0OuORIUaVZ1neHhjEs2vBuYt8OoeHw8+JG1XoLDakErRnaskyyC8nI3 yOYOSLfvo7qnrvSjxbJgOannSGL40QoH6cPtLXNkjZ50q2r2zFbQekBjpdBtZqcHzpogSmYOm6d/ RQ2GYKt8lDKW4zMlOxbTRkMHY9Um/EGSkIEJ/0B5mH2zSWfPytnrMZD3eyMrRgUShR12hOhJSxEZ NPg5oE/lTy4TZ7Msd5YVljWP5DB0nOYJdWtPJbCLPZ5FAxZei+MEhSuUDqUj9VKnn7NzOyb3BmeS 4mFrkJa8/2JuslOCQttoLZsgW5gQa0psyNE8aS5JjsS9NRf8ttySsLtdYahhBy2vtktQuzmFmO1V xUcp0BlXqABVRiGa/PNbGRpHn5/SIvlsiYSImZd+x6M2g0uRe3VMwyK9iH5FG/efUFFvBrClMODM gEpyiN5I0spkhwmbm7OuoqLSssKHPt6D4/yzYA9uQgiA/wFNoy+I3Yaqdo8ufzzjIgcYjUG9X7D7 XnxbgFKeMb5VcY0cpZCN/gcVDH3cTtlSUg9DLv3qJwqlDg1UVP7Aj9KWZ0xIqQUHCVPoJ6Kzjeiy LssrIuAgldg9CRZSYSkKWX9rVIbxIa2LZjYNPQbilcikDda0HiFeBN1okMUysgfn365pJVYga9oT yjf74vkxNcpwYKeVZAociXxp/JGFfjRqvGhPxhDScxVTytNnR9iHCFMOwvsIaKbD07EaPlrq6u6i zykzQB0HBtHHtaLLQyWDySDV9DVxrjtCSA3dGhLZj3HavETSS1VEs4douPaD1royVGGSVwLAjThJ qUpbLDS75g+Qnq4TbDiTV/GfCen7QUm+C+6RI55WKpw6KEq1AdGsl0unLHUuFJBOO2eIrzTQdVLm ekcpTPR2hvvT1C1OW8dywzNycnLP9v5rQWvzrXKdk+DMMYFzkIWSUEQoLsRgQSzqco1nH4dVgdbD bc98F0YPnOXhbJjheGZ7BFIUGzBn2D2LdpLISXSLq6BouXzlxt9ju2byVXlCTv/+HYOTHCdOlhkE qDnw8uQ9l99r2xONfylo5UYj7s7V0GUBlcZq7V5MEN0Q7vk8HINAzm/3HBBoqxyhPeAWkpufukp5 wRmlM9wxeBpdzyJHfH9BUG/XCFl7d8OwG7Vwa1q0wn5NhBwF3RyI4VCG2qMNvmyoXbKPoCrYcU1L yb1k7JmAhhdXPI3cug43PDSAE7Try47EB0/lCE/x2Q8zpCRCwe/J93VFNzwgJ0LFCCEMQL/ucdE1 n8DXzf87oSHHxXG4cibsUFy8+o5TMAalxtsqoFpVCJ3BNUy/Jf5ykgjcmlBK4eHmeZf9Mrbc50Mr f4D6Snqt1N++fqSXDtkMQEcPJ4Z30vCV44micZ2pq3ToSLiPBRvGhwk6u+vH9T+/xlRdf1Gokrie VlhbLZ9trZSd2b7xM1oqJHWdF/txEJWZI0ggXFRSUxzE1vov0r8OVcsTUUhAwHcZsu/gEK998Ymr IdG7ycKkA28SWkiBD8HD/TBZZPXFTFpMoemiENiwJKKa3BMABiSm5VFBil4lg/TSfzlVVux38+lR MnfCyznOfyEwihS+758X//9Y+ER47wmDv4037jLnlptWq+jqN2BozGq3K8iLhjwIMYoXMTb+EK3t G89szVnUEgKzihd/6CrgCgtH9bWGyRqMnJ2G0vNV5wXcSmI4Flq2mrfGj7h+7ceKpAlKYsWsJi6u sVrXYSLZWAP8MW33e4XnpcSuZW3y+QNq5b65wK66rRa88pj6YlyS+DlFyCy4NoMqHmCx0xjK6+pY PcdHGG/Jt2g9amd4gfjVdL7t0/L5y6LxTJI37OVlhSeuZM8VYZa/YVO7xFXFpzdvdytJZwEW3Cp2 Vg70kqWKRihCdm4KRNSIYCFLepSzJZ1FW6kNvxIeeYG/X19zlTvdIowW4PeVGHsnvAdOyNs8l5/l NXpIyeJZsXPQpYuvqXtQVdsKRpEsmn9TdqRsMUCH82nlJshdT1Xkh1rT1Pnn2fpDz4aYkuI8jjoC w6jGvXxqICmG5aVOKJqp3x2YhfNIcJSyKihHGY69Za2mYzEUwxbPjDd9gZuR+yNjWCb48k5UQ3++ 8hICMWatSrmIKpZA/bQ3QalYsWII4JuSB5NdDRKlVAzq39pgBGGZblUsw4me7ZFdnQck1JxJJ0O8 hO1Dhi8RtGsuMeydaCXinQyL3kCcTd8ukAe92ERXAutQRERtDb62nnQ7TJoNVGtgmtLjWx5zpn0K iWVPRTYUNBt0NTsn4EC1ctFtzb+zWDH8pk+240YpZ2xiUzAAjnYFz5hNI5rOGZAJlcTYjEZRXEej keeSTMzL9GbMt4ply8mk6H1hrLmsb51BZfddDGlwRaXYZ8S0H/VYqaJMP9PlkKgE7SsSlWS6e+JS Ahzeg/en6am06r3iZzod9Hw5qeKUtz9KOwGuS/Wv2dgsIzbv8NGPnOvWtfCR8FBkdMV3ohke8J5+ 2xtfZDpCBywJ4KMGiJwHtG1ha8z65yl42ecVVJ3XJakzPb7C7ynXW5c266ETMmMP964V5QySHA+M DCz9/61L4mUeuZU6cQ6Ejtr7gkU3kBzHFqVDpcggz4ugu19CBW9IKLHWrzhLKcG36vq9bN0cETab 8AtoyCJ649kHimIZm2CcUdhm2HYm/kElOy2knUeunOxED3An8x7KbHY6U2O7HZtS0oZvwpwp4WhL myA0IvKrM201ta946oMC8PAAsM2XfWGZkS2MJ8wWdhCF/IlrlINzTUhYlpnBInjk9+jwHIRXnVDb fhd4zEgC7Gmi1wKh4DnCa09Ya76ZFPVqt8CKB7Fo376hS8/bOPvcKFmqpaGkkxJrxHDyIzdRiF6C +NbJXZWXeSdj9ryf9veqaeeNEyN/kyAMlBkE1jxz5iKqVJwtFUNgsCrB/zrFTZSsZ6vR86QSJH08 0ZKAlS705+Y2fiqViySxSGflQuV3UVHTOFEDPLGI/Op05yjtpJsZG/fRk8q0igYBMgoopcdXgWSR YOHN3VSFT+98kTBEE8mJC9juQ8kIfs8EzVXTgrC+ZzjAdJUZe7Ckl9mbr3QwueBISbraMgBS2GKG xRFqK+nLUuBIGWOi40OwQTQ2D7pyfV9lLLoCcvGSjyFmfHNRvOV/GNBA8a1hMR+cxDT7ewfEcTts GrIV7H4t03/gSTy363Empl/4BEyH+ZAEfvp383HOHnd5BDdEDhcE1ykfN7BkhBK21A9wy1sjttlk yLrP9KDHz30yAeTSw9h8eKCfKpzn4tx3YGHYunSvdoZrbPmtIz/+1vBdMloXFTeN4C2MEE9SoqpC uZmI6xfagbfnVD5t4eG3erZwmRMM6xV2Sqh8YwA8iDbAOS/rHcxd3+u/YesCs1puIASTlKFnqao+ Rc8hyqvJ47yHJA+rt+CnNnqkD5i5Y+AQv/mkEqz+JjSKJhIjtTg/G7s3JBWRmJ9ScPZ+qQR4X33H lW0BgfJQ7DJvLS5Qmcw8Uw1IQSzybpHzdoaYkyiFUvlJFHWrl01TnXFa6wfoMc+NCtfDMU76rI9U KSC3aEEdWGmRDVVXXs2+V3zE8rQUsQxngo/aRzpHeEoYc7YA4mRTzG/vnzQGdftbq+Vf2SnzIKp0 uuoF1V8vC2wv/lwF1mhRtkPV8Ri8W0mAI2hKX9x5r06DRG7+7WdBkJpIydt/+nv3Be2G7F5Yhk7S Ksr1bMRGig0NotT4mafnDtBraUEXLgUa77Ta03YQwJfvFYcAj5xSqLeEImj1Mg83QU9gbKLJG0YW JPFu0fCmJ/fPy9R3Mp9J9uL/d5WI13OPwsJ7h1T4R8uH728TzUtOxpu1mxEuF9Hq+mvpDMgq5I0q OoQ9tj8s2hCChaaJKqlNbqymTLjhVMII8y4FApFrzSs56m1uBbUWyJgk7jagWCMiKKeq77RGns+v jKO4U4dtKDPMmBVVR+EDwwYVTP9CM2sJxonIS0tB91gPmxWZuHlAT7ZJcEqZbuyqXiWhAU0wVJM7 J+VLWtjorvrFW786Gg+I2tHBU7I6946flVW/98oNy9W98X/lz7uhORNarWbfNAep+9S1Ets4Jht+ l9E2uo92Fq+pVCPGjYPtdlwpSZxcZ9YelMUA/dP3am/XMh2fmJaSP+UJn31CoHSXPi/wq43E6NW6 a5bSeKhAhqs6zHy0PIvZsbhapY6rZZfMM0KApWLNAFScYyC+SUrqqnNu6i1ciWbHd6kS/MCmamHa 76LUYWSOT4FzyB4k1jiTPIQgC5EJz/42Z/U3zF5ao5r3Tx9WWMa5JPPusqHqogNA1MWqnquE46j0 ocuEh2QJVtjl+wKfThODrUiTBGL/SejUQOeDcAbcv6K4elBHfW3///E8FQV0ylZwUNM7201fK7bQ jXpHGV6O2KxTgRA5RkgwXxnS/TduHtkxRv70R6RsTRwBwToxgxKWBRvtkHAG4MxQCxSou5F2KS2d 648IvI0M24xZswDf84fJ6JoVMLWzNF/QDDolP6e7cZYKLXyTYfFuIaz7yanXozf3fJCCmZYM1T0S 4oQS1c5CzdeLvKRdOmh4ziZTOa2k4xsp56j2voshLsK6mG1A8zO1g5/wDlfCfvV8vfU/xrFl7LdD fNlO2eyyBkzcwnICbneP4AcLdVIpDUci+zpHrSis+ApP77bTqxZlLC04NqWUO5bB8UYM/+5nlSTs fA7YN8WnYD5uCUkUm3OD8RL7uRBUcVFyiqz5pVI4QghsPToMdEqEOSBzTLF8DC3tqeJEZC26FW88 GkC/BOlpaVndvhAf5o3AFStt0iU9NCJUL1s9ZPyIKXavJ31blnEYPYzF8bKMRuxQluymA7VFovi+ bqPrRcgWOtQ+gsagWoiuw2x5WoQIuSNDnhjT8waozjvy8UQJQz6jUWgK+fQOkyi+REEu9/ii6JTy d3DqBAOyfxaEeAKmzSe2ujolcmnjZI3UwWjtfGAl/HDkRF7D7FHI7uylkX8Spw6nil6Y0qcr70+O fqLlT+nkcYVTOnMrvyofxfjifG642PxCad8iWIY79Vw+RQzMnoD2lUtUgVGIqCAlAWsznumZCRvP k1x5yGcEzp5BR+pBIQsE4UEUQOt7pGV/pcLrjrUSgNgyv7CLAu8/MbG/FdqjNGeG5a2gooVBn9fr 8EgQY6uegUJ8aFFdL19sFeqMrW+MC9R4Ztp3KJV7PnPLA05hvM0YRjymIwflM+O90/vTsGNNNnnT uCG42xLRdeJhjdzPb8JZJzELXWmvQvRIKpfs22O12av9Ns64IRE0y0c9RFWNNCI6vSG3MoiEsr+s ykCOCBAKl2rpN3NtzkYjUhXWMijpjvtzY9VuY110BxbeKU+uADNE5jCN3bphodFOi8MdHtArT1zX CwpucoF04oMmNqE7YKLlV/VGfU+ciR40GjqDwYizgbAKALRMu6EU07CO2QI16YwCBgSFuuvCFFOp ofevDyER7ZQ7sZof6XPq8mSghxr4WUD3bvAaH/MhYSsore1k5OPNU/8F5yjxfDpx6o29nPromXJC ftawcIGoRJzwMSkuMvXgddm76VO7k3WF+XTXNN2Z8t+wadu5Fpm5t4xLp3SV972yd/NVOQJDYAud RUA1y4zkZyAyTgxqOCARGgtcNihq/JEEJOW3YCLPW7QNJxaO2Zy0FeWqI/l4ZKG9BvOHMpIYAaaH +qmkrVRFjGk/wnkkv27HE4bnzwSQdeb6+kw9VS4KFV2VvUBVYJbo8MW8hK0D8Usa8lmHlfER8TV8 Y/LX9LrLdhFqxei+XIpqeugo65xNwki4+MM0OhddZFb3f2RT/29FC+IWBE5sTukE9sVL1iaYCY9t O7XDqEU51u5+s4secVCkGMdR3L1tHDvPqQjh18EL9eeRGYDv1n/SsgP3hPJYuSgmgWqzpf/s9sOI PTndQALqPCFKh/Xe4/vMY99DmShBPJlw0kHxiVnq3Fvm7myw/f+yPWWTQ762hs8avC/XJIT+M664 Cyex+DQ0Ky+8bxAhQvyQwn0jtovGmdJoM9lVnYetKHAg9MQD17bQzvV6MEaIv8x0QMmyEMzvwqm5 944tuQ2OZs9OY/0OtF2eM1tw0+URV2MyJvWdcPaEmR1M9bDCv9sIxro7zos1PkcujRnL3tRjZHAe 3Ckgpva2G4NafO2XBWGEJKeEKWpffVlxlVCnL40zzHQICa302VaHIBYmZ5Eoej55xOkRzlMLrxow VcZnvKrwpkcPGbSKh9mpoUuMUW1bmbq5bMdsm10sCK8Ghtbxz0aJVpiZDhLILpQYkUyfkiEbjSxZ O10VwpcZr+65+25atQS6WBd/oQhzAlMcf8jd0PT0KCxEg/H3WIO1kl+Yi/3EfAJiXTQB9vOqpWTu Uwruvg1KJqqjsA2wAVoBgAht37zQ0b5GyKMWMzuQA0AvlcJOpPna3pSJ5cGAdyoYimQW0MjuzpsV wDhZVVk95qyqursnQU7CKlVc/Q8EG9v0uRCBecbiPkagELj4ggCv6I/yrl1mbdp462inoZ/SaNME tynTjbY2TpZrWPjutwY94q9WvXKANEQ/DM5UK9K8WZAfNqA6Hl4htuuPS0nkXtJ3qyjofbJlZju9 H2DSjkyElWIfP7ngBeblVd71TVLRO2TiuPVCLOD7swpJGYQ32vb35WoopBweeeOtlsmZRuQBOQPg q3/HgpW2rWCUp3G92kf25lVPC6XkcrKXJMBRqlKEhW47hCVkscZ6/RphWjFyzR4Ocmp604/Yba+r 74RUqIKoNb/3I1EhDA5q1wuwmWSLcAxxBySJpsWzqUM423kXz/Sp3PzKgVYT8/fUHvCv73rMMgSH cKFPo7D/p1WUnMbVoMmbRapO/KrS9lAgHf+KFPb/35t+M7BBB8FKJcFU+8QQkmCvJDR3LRz+vcny 7uGUU+Z7JpQZHzJ8+i6iz+8T8iE5XlKC4GeR/MCUmBDs0h0QAlh59Dd7i+F3R5jQIG9bpPWBvS90 1x49L3wSJc7z2XK4NqgiIuMwPiCHLGZlW6RocGQiEoDOubdq5E0b8mofKL+7RKpYhEdALdBjxGlQ oQl9WYFkTWcs5sV1TjCSVbmIB8A/V+Q/fVAkQiBmo8OsnhZyxidvbKXibfCpUeKZRKL2ZiHMYpAE OUrJRawGhKxCoNc53uemLYLMz7XwIS3HZLeGvxTbxDrsM6Sx99+KExWXoJ4konErP6WdZVV4BjDZ 3Bf81OARQq8BkVv1ScxQ7MZVb1TJ5RnP1Fhl1+zgWe0nrlObH7nAIbSAQXQWt1H79mkvZETFXJGE Ip9V4mKPSjKS4c+5Tq8Y3qIjQDxF+aY25WoenkzMBQ1aIYW5PNCdlTG3BAZKo42suZFH4qmKLcLa yacdW9xgTWz+hnuVh0C7DPa1rYkvdSzomaz3OVdmLoiCF6Knc4AefMyK8AvOdGaPEP8wdNJRq+xb Xfvm1KnybPH0/NLRte1jQaVRt0O0sj6X4vjDGJVNx6+rQWeshD36YSRcAe+8Roc2ePueS6TMOVpL k4wNIU8nixcCCLXaJX/vLXvuEbsEzt0r5SlIfrH5tNu7UZ8hrZmBHob5crFznBI5wVqej5vFApEG RirsM/OmlDFFbZh084qrrkXECJ3dk6ar9/zvKGOeSBFvKQeQKMlijpGQcXYZ7YPzn2DeHaXDJENi QvYO0NxqydBfZTNp1MV1vxaiXGsX1d2/m+e0eMrgx9A5K02wQpG9QNRr7+DzkzlRhg1X2T2AaYYW kVMBy9UepSHgQTBh3/jCJ/nj1KDhfl0lzXYCNT2FUBl3USenVzs7jsq8wTBM4JbIs7TBz6oL/pwg drqUA26bALEORyjCml0R7k1Ug/GpAppSsjLSXBUz/tPsntcw0Az6gKc2iEQkawA3pGW2akGSfT9J xxyp/b+S7esjcK8gYscyrLKEi137Jn0O3PxdO7D92O1KaCyhOKi0hFT6hVmrl3Iwuxlniya8rzY/ 0+s+T+vXbJx4Tcor063xNWu70YDb4vkWscXzkYJ5qztbFvvX1wNPYyJi4zyCywUO0lRajSnQG2wy u4ObxgzChDGLqLOkQD4O9sb0g6+qPCewAvL/CzeS6Yp8mPtwa0ml0ZZEYygreWfTlBp4BSsRJ/y0 uCcl81ZV/vk8UJfChAOIDwE9szy1IMmvFlc29J/ZOPa2+or1Rxh62zeip8ro2tVvaFqYAzphAI0l 0hcumT5UMCjeqTgmLR2v+u3Rm8M19WlyfXolNcWHZdxR/1d+Ma+ne/ReHFi6wdsu0D2leIG2deWM X3ajMn1teOeqaJEgocm3hHxwQhMXRz10ASEbOHNfkhm2fsJCdYKewlkWLen/zStNUr/w6T7iUoB1 Gy7rPaXLyryXzkjRNDBE8bekDKl7EuVJKv0hnScrwKrAlpAmlkPbxCdvF0zAYS28IYuHWVjtwgdP EiNXl6Xcuk2WjWMcgozZWxuoSgu1tP7Af9ghKtkjOnSIJvCisHEg5GiAIkMgjdCkq4igtA1tw8ps U85JwaSRBUwz9OFzCxdJVLkESFXfdjhfSiIfKEhLzcTqUUm9Ap0MmEVSUv8UKayKN2wCYCcZMkjq 1EyFuV9AkPSIJYlqWypGVgTHAMubULNgryFnl6zZXSAepLFoq6PdQgmZT1sL9uWHrpWo+l0fhEcb ElWCZfg/6tR60N0cnGpS2+R3wMOJT+xVeDIix/FjkkfOgjX/C8F9y5SrXMbyHWtO+FDG7dJUTqlz tDcFwdcrKU0FWbEo/H4DqsoLU8I797D+J3sC7bgvtxTksKe9s2bolUYpo2ivFm2hXIuXV3t82ydC UVFSwWA8jVJIwhbi0vQfvTsub5kreklQro8/Wj+9pX7IsSjwUO7WGj9m1MSNPc5LTo8frV7YtKCq qUQWOnOCz65rKgxWqil0UAfssCTUc84robKHiugTdBWxpKv3Sd3TDRJabPsM1VLQ3Q/+ME+0MDYX KWzr7JSj0iaVmqhypxm4ehM60YieYoS1ZsMy5mgGVhwQs2UXTuRtO8HhaQIG43AbUqJqfyyIAdLK QGR6byGGuvKQ13DXjZwLWgOP4LeU/9dlKYZ6bAubQvzOHvbihvNNCsjHWARtRxIU+DUTNMX3SCQv YtBgNuleLhsX8RlDLi2ZHi6PLlsvVwOWMUONFr8YxnDHUzOKZPBgB6azyFmnjwOv/ClzfPjbpHUU RAESq3fhZBYq2n0w6wKQ+yoRHUMZ3crtHDHDyJAqLhNrUPM3ZvzJd409IohL6KugOpoBYUCCjqbe pyGbMwjVzXyM8qwNHsSDFRZu3O45S1cUeewMnQbCQSrJDAU8tWdM5JXFNTL8UC2tYMIynsb1y9Z5 1HP/N+xUiBZvxknIvFPecYvop9pWX55MN+KIyDkxZo+Igdqtuc67N7qAP11Eg4yVy2iaSPAhIWvY wFlxP/cWo8GqZrS9IBTZpbOTjy8Q+xHWc9mV+P8vsxglqmLkFoGmRFx4j2GKrFzERoLXNck/0aGe Ui2rt7Y5agld0WQS809MYE9/wql+ZH5FDPAp5QvQ8a5Z9an+U64vXkxC4IYJHB7ogE4bsVwABzvH 1claJm1+74fiE+HGQSc2A/wRIT34VfEq1//Pfds2pDN0y6r12CwU5vc7tIRuCZo7UJEPLeiqfsEc sn8HHzUuXfxVGheRAyf/fOlJu72hGB7hCpYiCCPVSQb5iourMO/rMVvZXg2/4fxNdTAU9PnYzv2d FLamp/CrTvPa1sQtwyZ45viNJY1CoR2fv79yFNHqzqQ0/pUegh54GWXJrLZB9c5cN8ZKGoqhmzpV QMt05F8jbId8/Tu09WZE7Xxc+DaXONMtKCmuYynvO5jkq0auQJBhx4hQZ6UGjWgo08KdO7W/GL9E VHKav56dcvE7nyKhDgJ3mj6ysc0nFhjHYWV9EvVCCRcDB+j59L5uol9MfnYSz5kYlIZTDkI8FETe 8KAdJ6UwueN6AnsYjemW6+uuxCkAuLRgnhTwIdCdy2au+08SIp4zHpx9dtPiKDX88GwKJmaef4OH T41y5gDH7vwAcY07gvS66ARn3xVmGJPiMLpcvqXoXIEHqNm5su0inz8CRmjDz4qkC1zt8qqh+9QH KJcp0jo3JQq696y9uW9sH6NgVFWI3ecSFlIPK0Dc/+9yFZXvrm3/HDNEt3pD6+poPamXQibeEEX2 hC9G65XUmw4fTDqtJMS4a5BrHtqKSCdRHCoMgobqvQdXufgrGCyyHBpohNWvVnth0kphoLHZo9az xzC1LiZkDuKbbKkhl2YJABj7A3zycyGbeNaNu80PgLTBjAYiR8MF2pHE8DToZGW8HwKIfuRf3XUH R98jE+wSU6GHYP47JIhw8ia6a3AJuXh5m28OIf3sGGl3bhqqFwzbXmju8Lt7Sf3ldCVkrT/FkfLQ bh1hCeiFI7XmLFKaDt1yA1haIhedw7d2+PIu3scQ+vnGOzwa3QpeLZEIbVT0yYAhKggBF98GvNfM TltuwIuqQQjMXMxVHtRnKqRNdSKbldaDsSsGnWfjFcYwzL8cK3h/4BXN9pMja9fz6LWjcJlcFSir It3W+IWJS7AgmUHBfU3cJ/Ke0oVFsxnqShP5QDWcwM8MeSnnFbLczwxr22Va3Cs3DyU5aq4RB6FR jywmJntB4du37oLdlORH3v+H2DmKfZFlI3yTXfUBReFoyJEwv5d5ClUAVkSyiOTQRKev8T9JoYf5 geB8wDWKPCATwVFNr/unw8bB3+YxvdZ7SaDtksFaTCPZrfC7MfNDiYNLvN0ne6MO72tqbrWH10Dc QQWjLdvy+ePJ2/sbU6T4hES21/zitofcEoL/TyESW6FHwb2+GssTqbkjj5gaU80V8Ry9AcEEkAOA Ga3lLgn3mGDWWqC1sMNNMZ0UQ3QN0keYCtlD/07ngf/3M9R4EesdD7Z+M4UyuYdE0xFk6P4CO7Q5 hcbkO4OZNinW4Zs0qTBpL8q0alsZPhJ/XhEDHAETbPJH+1JRtgU3OBRgl5WCagFjDYrCnBj2cNce HGiT26YOl6kHK87H/w/8CxDgfqjklDT9MTa9TR/QDbXGRKqmHN6RqjTSkFaZYdTZKo6YMW1X72XT t9gwLT+voAfdj9k/xPVx7/LZNvck3fRnQAc2IX6+cBWZ184IDCh1666UiPYYzcn1l4qaSvhytlC+ Exqw+mYAbVzGf8dxPnjgKzAm0ymwDqAyqPyZK66VcSw7rh9uoIBaTieP/l94cf1GPiiZR680iwlB zJQLN8Cy4sQGr8i6NCVypiLRxUxzGQbMhncC9POMK7GwZIDCHPOkHhGrxB9aRkMy5sB18eePdKeu efSSkfvGCRyM3PKQuqdSe+V0kRpQUy4I7KixUu4K5HgHgd2PjcBd8dO/tqr0f2BVGjPpaHeEHAEo FiM7tJ5xhFLLp19f212P1WeIsuRGvfMOqlimN66/wRYQSYqjVTstaZaSQqixq6jEkDiuEXksZTNs Ze5HFmynPLtT4DCazUDiRwmvfy7jBQXckI0d86u/Uc+FoGIDpxR/3lppkqu1ZguhsClynVY38xsE F1IG2KylSdArrHCM1xE5dYNpIGWK4EfMiE18jgU8zMv69YG1rWR/Z1XZEI+r7+Te2Zr0umPEeXh+ RX/aO8WvW3/osyMT/BMGL3F8iDPVIUZB5NVmajFvLSojLbKA56T1uyBf6vOyIprmYshCO8awRlYB X6GGMT0025UBG4FL4JrYsYpKg7vt1zL7wLqaAYputrNJQTpX8sH48ZgNDfcWTFaOYlY2BEn9fcQN +qLb232rYxW5Vv6ZhM2ZAQGB9PJ9zaQXgNpGvY1bhSBXYZZdW+vTTfOlsuweOSwPOs1febDDY+Ka CPaZ96nqwo98UN/4KhBUnmJ3JW+lV0UL2gY1I4x0K3RqmtN3zSAsMlVdYc4DM0QZ1MzfPaZk0ICy w0S8hgtULcoTI0WeBLOu4IjrmcAHcynNPSh3Ksrq7IwVe/cxM1G9FhTVlxp+lBfV+tS3PRNiM3I1 tWN25kNuR1eX9ip6r2fHr9Ys3v75YkLzqy0X5LvBGCPDkW99UHeXvkQBsTdUq/D9aNh9NROiTKNz c/KFuuHNM6ZTxRLfTKXr59nXtjZuJqcMh5Ez/7HPV4RMWfIM9JXmsle8Mttk0sDVmlJok7R5yXPh kcq9fKopPrWb6T/u/4skXl64Q2i0WXesAbtq8Hu2Niygl7Ky+zX0iQcdysOGFb7X/ffTkUE4m/lC sHHifJpnbyN7i49/m7UycMdXjFrzwNrIrtPfKzxiZacEpSFt3uVXpdXb6sfe3ERIJanXvVondwmi AV8lgTcCyuyQsFmyDk6iO1TSDuMmFeDwr5JzTZlK5oRZavmlS3WvkA+mRpE8+gG2hq51vaJVDqm9 HJOygCFtQzt1FBBPr2SUJvlCtrErtq8Q2vXFxTC06m1DjuCUJmmSQA5XFljjHZxoFLXkb/Vq5KFt 1mZDqurA6h9GPeAV2u4HoFWB0robafccbYSsEmD+clkXqrMWVTTgHpNu1awkOEvwmYVvolBgyWoT FY1Opgg+oCQtd9RSuRDGuG+7MDvdqL0aI4JO7Oz3749TNVTjg0Zop2aQJj8r8RBOsxzZh8hOyBbU RJOh+kWNRK6pTu1XXYINVpGtc1TYbEaWlIN2HjKA6JbQXzdyyBCSXX03aPcjTtg03MPQBISWHb01 c0QIHCsylDnnU9S6Yjand116djV09ezDvDqIvj14nvG2H2jtqRc0jKaza/npMAczs6AJwek+HVFI lbgvFBr7UkQ7QwX9CdtazGwT2HPguaEGH8gDAchLDFvTbyNCq/TaA6Wh15fjPwTvM0tXhiKp0bVu FkS5VMF5XIgchtACl7xvgGlUA1BOtasGM/S38bkGHrra8gyhcvhqdTXHQ0ZMY50OkP3bej3GMm/b 1cDs6hiAO5SFOU1D57tCMSdVoXLvKG06Nd3gyC/LLbTYqfdeD1juZJ3gMe6dTOHG3lAsSnlzB363 9f0ODHUtf5kFjYl851EkcCiaCFHRBRZV0zB2zhyKUwI7ujwIYqCGqQHII8/kt+5OIi3u6SEQ/uL9 fSgb4dBCcQXmw7qAeT/BIv4OKa0SyzckECa34ttEpkSb0xYs7YaZqOq3Di6DRSbq/jWwxi3gOLtM iCjGv+f7P+nhtuuc4/vCCtYh/94u65tc84XM6vttbskRCnRVMjXactllq1jBVSIccsvZB4lPRya4 KJhNG4xI7XM1GOzRoUUrwLI2I9Uej6OkIyZ8N6FrP2TSvw3Yz8F4arpPh023WfC8oMOVPrvIRiRi OK/TvVMoPjE7k+N8OrsofoutGVIDDtJROJ+IanZvgVta8VaxtG/oT+CqKjoEtUDhH2AY1COl4GvA lM5VEHml67pXMRjycY9xhKIrR5v/F8xZJN5ggfCrJXuVhpfW2D86FTP0bSm/DVhXbm0rZXuYYiVM QPvXxg9IKMlhn6p+4R2Bf/mzePwV/xek+Q9wyBF8ooeVvMilmyWLbx1z3cO+dXT3GzfSaBgCE/By 1FgQkIw67gdoyIQDsUG2sRLkLzenv1EMex+qUv0ave3vSzQvu7iOUjwuUt7Fea+VACz1JECq9eZ3 EdTI/YJ7G0fFII/wWJAZVDZiYFrvTBQYgJ7X7DbuOot9PhohXVA8hMMvmLJHvlS//m97DZ5bFoez EQv/fQH7VGkUM6xUTCEMy50r2dPFd3T2S33tHhEKj7TwpyQrM6DKaUfztl8oCAe9ngwMwyOoGTyF PMwENBqGmx8baPpo6fBrqw/3qWSZwKhCzuVvbLGKGP93KnngSBa8GNZjbFb9hXhVYcoA0ZJM5iWk I2IR9Ofef+txKS/w9N2XxzHQimrZRUhocOqMSeqIE4rMb0OTuh3SEnZPUVN+L7d0hI9NrNLbaoPw 5iN35Yr3MVbASyHnkQrW48fLXoHKapYo7ZG0Bao9q4HBG7Yhy074bdOYPUGisn2vWRjcCceQB0wf Hw0PR0NKalPuIVMVP8jWyD8MSaPLJMFOjxorLAAQ973f054dVpq8kJLEEl9h3xMKuVWzRePviTk1 t/ARgr1Bf283qIs73r5HeqLDYeIeKh9lbWVxRrUcRqxYFmnmLsJBAkbaGM6z3gOL1dgDFSCVMcxs kTt8oHS4rov+OSBLu7kTtipGMKC6Nrpqa1G0qA95NNAgh9GefP++M0XRqFsxYcT85Oh4lHd0/8GK 4Q8/ghSlZb/W4nMGDBMhFqyJT4D3a9o9gp930aEaHFTLxMOv5R0a7gwe8DXjbZY7G8UtvISufjwz rQgbqUzXD88JpFWANtingwZ4BxWwffRHJtqjozQZWW0LIOhQbuNSJa2mH8iQwPZZ9Vb8UW8WfKci 6d8MbpScLpL3w8YqMPgYRIqk2QEe/yrizR6mVHchsAS83DsuFHwEBxlT0vebavaPyNpY/XWabLW5 K+3DuL8aHvfMfZKyGUlZbHU6d9e40Q8R4HwdD//n7a/DI0gsUpT62kbpV0PSwjF6JR23ccllwe3V hhgkn9qGzHgPPDXVFBzVBrR0HCjiCfkMFs563L5sCtVBiCpSW0UsjLch9yfl7sWmvbaOjp1MFYPO bS0e47Ya9743eFny6m1Oo/YRZwQrP8z4tcbW+rRlYS90e/FYu1moGZZHJrzHNlN8gZlG8v+e/G2f GVhCKcp34pK9USqLJ+WkNSs/39ndoPY0Tco3+CpA6FkUwoazyKIjzGHaV/tGVTX2QJHsrgBC5NjK ClJCZS/T2Aizzkm/Zh/sDJvmJqofqeA5AQfyGGyQrC67CKhgsx6DixRp51u+DkvOMm8ug5y97KqB SOIoNkhBgdcm3JSC6ueVkJPneu5ahzmM/tHTeSjzap3LrZNgn8PUcGEQRPxJneTIPigKmxvF7Dg4 NHRftpUefNY0CMu1KSn9rD5w0pN4N2HC6WAzd+sUGBbeul0rQeAlMgnKyQxS0axa6K0MLYjCV+im 2FEgTYpjjiSi/K6khOTjgPuJxy8JiGDDtN7WQr4RbanG9WIZZBFMfAKCtMZv2roI6+ni6VdNI+4i j9q1Sjqb0eZVvhBNTzW7evu9qw/M/YcT2zGhcBJVgFzMutHpgn8FRPAvknlYMzcRAhSf7BRNf+Mz 6XWxUVPWfXv6fTr8uFZ78R0jdTNNVBWX/+JiDJf0meE2ljjebSl4ypr9LlFkekfLPmGz0JJCQzIh 2rMsVpNHLg5aq6oD6qvWct2T0leGR6HLEGiGC4u3aLwqszYd7SSR7G6W4/oW46to83VgbIP8nU5B GTOJOiuxL3oxftej42GjJl0mxSBUnSzKFefVVDko9+n7nJmDGZKvuC/3tEHeXCA9mkQ47EQUIjAd fXuBCbvvjU48gchA9PumL2VA0TIIDjgtQtl603HpMMZKFw7MOoW7/7gPf+nlbd5brkIZnoOxDqvQ s9eowYO63yN06Nl2Nr56922j/V0K/kQTrYqcGsN8aoeVGP2mZVDlWUvpL1EWVUYcSAKCjYJdx5pM 58XAxecLmtzIk5XwPCwXltWTeXC9f3dgSyUO2JA8iVBB2pEx5XH3TNlxA/kjGE8RaRHq56eRHrdq 1GnfJaTOppzgcViystQ3RsLTQhrMTwxtJidYxcWZPp7AEbijEXQoxm2CFNvABKmtZ54c82aichAs aWWOQXL1bKuZx6WyMbbE9zwfVk5K9XL8cRjFaSgS/SjUWwx4okgCcq6722INP4O0Vinzhx27wz0L oHw/jT3wkIDZ3WztY2gnmZaT+otamMamxhLMO06+6Y5UxdQrCIbDur5xYgPH7i5eBYc6yLfj2Hi3 nKMmR72AmGvMkzvPor79q9USzNpF3c9jw/4LkeUAATiF2FkE5KP15WXbVP5JJ0MDDTrHzFHUV/lD EdwHH/Gv92YyzVpRPN6zIXfeimghbvbsNvrUu5FI8iUIZBC+SuWFjQBmtsCnKBsPb7nbHtdXqsa4 r0Ce8oI8t85zGaetx/EUIo/eAQGulD+jlvBHoAioEsS9JsZXOoq9rrCUAVWEw/e/cUeuaSSPkx/U aXfpmdbUtWOUHbrbNdE1NqtNY6QHESnL7Lz9QdZTEYyk9QpcRtGTY1YqxhGitjVRwpQArVwS0vzY uLoVfj6UXdiFwOU6su0u/AvePZZcLbnj7koWF2DoGsMdo2UAD1Gm/CxFyEyaXKr4hgedra2i3sXm Tvtbt0H70mLYhl3BC3UUWZV9TGU7gClksdkazcY0sOVP1HehvWO1KFxbZi1KyfJTsS7/y9QhbGiJ eYTOE3GKAEjPAfnYCcfrY53YDTbBEkdjV8llzVOMaDmO4/o6W80ifpMiZn+jrme/5ePDRnz1ZJKh U8EzhT5UxBG9eUIJdmqPv1YZbaDIUZT/mSHDgIM+tuBKL+I2YA1udj4Ecw4LNycpqDO9tLD6sXIU kFbE0Ik+4soAUn5j0UOl26m4fij7yuqFZoXTI2Fom8Tq0CmnLoIu08D+AJWlE5x1bK8iUeyk+aet 9VC/tPPnvnoWCk29Pk7WVnGpsh1uyxWAiB7Sg2pK+/sIyQ4X+n3NH+YsmLc74gjeHgm3VHqxjhrL uST4c9aQYCNDfHke0E9Knssl324iMVbjES8ezZi+TszCnBLE+bJnBttDWALZKjPZP0L024Hx1nkr PO9IDIG3fbbC1qph/lfyjhlCjy4jA1JwDhUleY0wMGTCUj5K9c8y0iBB32pVqhQIyIwej5D/mSCq IXnRYolhpMbCR4oExpvCzoi6X5j/tx7x3bOxd2i3eTAuObsmHTNLgQXR37kcmC3qDpIFgU/XlI97 1nu4WsOZCItt3a/sfE9GyNUvMptTmZaYtOEd97fOOma805MQa3yFQwy+5yrgxuByWTfJMxKaBQCH 6SiQoTYPStn6QGOEyMa1hI4sayzdTAo1xW3+PEU5RJ8him+OyyvuGmz9+MU5fodT9fKFOiSKciy8 PNWKXh09R48YCjdRgh5qYcjA1nWoSziMHSVfqCaS8Ki5D84hKzt1Gly+lzsw4Qpmf2VQ/MhECOr7 VW9lQvG6WfAmH0TRwlr6sxjQmDzdhHf/V2iLjRWDYYnnvB+6t2RrYOvLIkM1P15fjFfRXHkqzQFK sjhXGnL1oYE2JOXLNvMl6MG4eAm4sbFq60Q6i4lTOLixPcv40cW+P3L/hMMY2XE4/xD/DG+i1DZm Uvvw2FZPxt+8dL4qAZWJBrOEYb5v5PusnuLqFeeeS2sHv9NQX7jniWGZ6A8dGsby+sykXTaCD+Na OcUJQMWXJUp6k2wzP4qOe/StNPqJ/lvbe+Yt4HFB+3cAA+EU8ygNeq1GxYE/7DBnUtKfHGSqRIrS 0iqiXex5W4h4Ur29neV+VezOSB3sfXOxbpIHRTx6IiMRkNtP8z/LNjBsN7M8AyI+jLRiwqDDL9R1 agLmMTrOKMXSqwHgU0+24jlVDgtD6onYD8crNxz7D5+3FidGa8WlCpN6WLv9aUJr5NKowVczS+4U EdLlVnrrmfYrfeSwfMHOu2Pu9rBJOm5qyCBYYGwuHRyHYyxbxTsQ0Y8iAf50rL5ee96NM+44kTkA zP7/sMMYy1VqANQMihsTZGUt+eQs63QtAmtfCflmW0y74olJYDI0p53rFU4jM99/vvfeDcyV2j+M YmQY2jbGQTh0IDWqVXSf3g6j2iQOhqPviemoFaardWOmVY1Q1EYR7mLeg3H10Rszg51x/6q/FhdJ Sb6dIIy+T4PDFTQ1DxV6sXbaBf/egH03U/sFW6XYAJdCa8upNpf8bu7zEw+0DnUCNWzknjVy/6Sq EY13pBnWMtsK8GdlOoYaZ8ik+dVGPhgVAiaJhMaI6SLTF2zivqtBgFqyNHpcpPmVu9SJ7gof3pf7 kM8sdHUe0ySM3mcfuR4OJdluATAMk7xmpdxbapr+fNzxMQ1U8Jopl3TNrFsYbxwzP1gnRMK/Sxek RtZhe36P9DdDUJOePq9iwwf0P3jLZjtThQ5j8SAc/JEbYX2bfHMBTOZRAzSceNFdGW4tETosaoy6 Ius04dciPKuYJ4KYaI/VwlyczY1A3aod/jxzjV+Xw3gQFzQXniAmNSBvI+NInwwZ5ICGivbZDRA7 qnb6pxWwRtlzhA6cCA/adXdl3gC/ZE5x+7ET5hS2w9NypV/Em8wqlcWDLDaIIJN6FSp5ZMmxliFc e4XUjB1QzV9ishnHWF1WctMzYAx6I6OGih7xBKnlboaFPedqbyX6ODgWmork5Hg52q08w8Yeg0dd 6IOBkekb2kR5nROCjNgZZxTv9Q3I6McMnanpbhw9p+4Drn1anvQiCT/0HcgfAOcsGgt558j+dzgJ KzuB8oZCSwC2wVYpV97GNmhUt8NIAmwJ1W9Y9QG48nRY9JOO3aGPDyrde0hQCoPAPafG89sPtDVO yKWU1xTR+UDQ0r4/cQtikRY3L+/85FyzwHApqEKcjRb0WrDoDuMF+CjbHAnyi5YYaNwc1an0xBu4 D3fYpml8PC15jQoLBr5JJGf9I67bZ/naQImubKLKM8fVrQ/5yzqdjoJrkrFAaDFHLCmvh5TS2oHX XXFIQ+4wEzRAwsmY2XWRIFd4AOmfoEexf8tRuE6iMdTbuE/ukrEb4FI+KOL7XDZsAx5el3dz14oP FHHbI6IgNLKqM7CpTgOS0ziThD/rGnm5MTAPB9gu/SCWSssiJ6zT8iPyClp2dRhToZw8RRbiSNLQ oXJLlA8KYf8iaSCDqBqK2uG7DpZaX2o8uYFZPxsEPqD7fR/S9asZJfWOJ5DS4y9druJXg4l6CS53 VqldEDQLAoX8hQLxoYyHbdyucRxW8CvdCBUxG4ehiRMbEMMR2YombVtXnPlZ3C4n7s20YoZewwU+ g+8PbDtr9wZStd0v5D7ONKohXLtCB98j+mu0KITOrjOkg8dpxyqkTNkFQG8xiLh1j64L5e5WkJBe T7eXHMRd4yBxGVMSPM7YLNqAP/ik2gXynh2sB7lrwFeaehdzf2KSVfyCmSREPQBU3gsmJH9L+tf0 O0nOTjMSChdRJnHEF9sL+DEEe2cqaM/1MtreuDThpnl5UigEVveUVDm3j584CXPuPtpUs4tFC+1U kH/9KqFLyrriUNsXDCPslgIgmhgwM2R4MymdbMa/5YlbbDBayZC6KiyWKnhZUHenQgQWRvAfB93W zyEd5VXi/4h4r+ti0GVkYLZKG+WQKufstDunMAbWPCsMGP4PcUxKHi/m9ljtZ8w7UFRZ2hPgKQxh 8T8rTp0z+dl5vMOOAGKutP3cC/XKH9Gv0OZdm02ajCCMOxjBpSb/hbBUSj6Uz8xYv6cPhqmhtzHg Fr8oMW5H88jyEWvFL76bw+E7c+iWaiyyHbtGapIlv3Kozd6aW+v+Xrcps7DhH/laLXKSVa9qXkMz gbz4Dfn9vnab00J3u9NdyHZp6JiddIORqxV1UYbuHazrMkyV7xnv/werQj7Xj4J6W5LOKWl4sSWg 5l1xzEWWGukAzB1rUjJTCHJcOjFckblXi0jdqd6WVMK7pmutQVAV1r/d2ZulVXw6MHN98n6fkgXk x6oOHYTOt6ah7Qg1jlA+LunrZI59zrwe7YYpyOmgZwPQKPTVjHpqaIJbMZXFlJ3XlI+JpVgHrxdN MKhL8n4QOzqSUcco6r4skxoutm3BRgUdrcLK6qyHR5Nuxfuw3TphCcIQH1x/nVvD2CvBiNQGWr3G f1C/WshmhAkO5fC5utk78u+tW1dd6IadGcaADOcl5TA2fLm27ToUMn96b7vH7yhDgqbNQ2DyeJkF NNTeYmMCA1IwhueAgV0WTB7SHuXTI1I1ySXX86f7B8uIf9U9Xl9IHHmMhuYRMZ7dMH+HOFlv8WR2 T7CXvcACjKq2rEaJrgc8VC5TW0d098QwiIM6IfR/h77y2G1HRt1NAR4DnJjqxO89E3Oc2faKgw10 cxbE/9lXsF0k7CbYXWYAMGH/5PZ3GJZLFein+aHq6rHLRSyWztQMgYIhe/lf4RcUnJH74mhyVeF0 MiF0yIEs1fB1WWE2wGKetp2sz6NUpnjK8XZYqBTrwnyhjaHPVTtiHk9vPwBfVmEruwLMSK/zzXLs k8r3iJvEM/bG+ndrOVk8iCs3mWiFbMjPTGW2i9Bfpdl3ZdVMfDTtgsJmNZBHHrtTu7xvnLaiVX8B 2jMyf40hSMFCrk2wqmQudf93fi9Q6a4APA9YTzjKfBjqzeZbPSf7tCFoMAb2EKobRXF954jt0H8z ncnAcG9VbBu3IzDwjBmY5EFAoErFwUfK12MYDoWqVHb3DJdgAblSbZATog7z0Bhg11hsHLY0DlJ/ 64EPujsn/bKA1cJ2QItQ4EmZFoxECWPfSLpZC8Zsfiuyzwbv3ROWpDACCKIMIPivtvBsxjJZ6I2K bCFIEnSEolfgDE3cSokPsvaA2jKNgR0xVjeVriXM2c4BM7BmgCzZHSGwQ8B3mBT9XClSPR84b6Gu OY9CTF9Zsnh9VZqchiRvil0dfccoSpDtR0FW7c3yUB6mVNXl/w/olG5gDKBHjvJwFLjHufB7VuaU KBmZHn4YeE0QgkMqAObzboIxNA7P0wxFSl1rfSdgHPLQ59KsmR8mZd3d9j0LPIxbjqD7/h2WxcjI 8jc55fEN7twOHaWKYL3xrmuzNvy+Myg/dkjDLdfhTlydbHUvzoEgLoYouhvsrYsAvNFCGWedtxoU m2PJ2FXyKYN2MvwXwZUbnSMQAelASgXW1E1PVgUtI3QLNQxrdcpQg1xUBzpOkmN5MPuugklYkGqQ i4XC5yQYFrPdNed6+xEOH1+X0TCUNWIrTcE5wBhMvE+Q0qdpIQUJswSBwx9mMTdBJYb93ND7kLjU yFLhys5EGWXYhvrYmsrzBO5YmQao32ZoeDyHxW+1pceSAqm++FtY1fX0Erbwy2T1/hgOJk3XsAWO q8luqbw3b1sY7Yu69eKOFcyguzEC77tZDBnyKKbO40wa7mGai5ToaEcGVFNXr7QSli8+bwmuVFru AfZohlc/OJr9kOy82552KYALzZy0mdsuPQ9ULEn+hAFMitl9a2i5wTSMwJuqCZg5EWGXE7GRdXsH N/kXR48Yx60Ykn7PJwMK2vZE0SxjRwKBF2cJ+WiGaixttRRt7S3YSiVZ1KC77C3OVpzkaggWsnD4 J5Wyp4XVZKsDAup3bwQXM6Qvz7BmVXEpCRMLVGiGnw8rfQka0RGklMSWuS28fS7vy+JUbmi0v+md syFFCydjZZTjTEU1rWbJdBaXdtLn1Jj7crgCfjVvPwpwe5me9YP4+apixxEF1uAUxVD3xwuyOa+n uXiLg1OuY7WQmpj19L1fLKtLSVC0z6eTLJD4eYF9/Nrk2b/GMsgb/Wippf4yTRDk74RVG6FjJCRt GdJAaEQpl/oquptJE4LMJMVz0Op1Hy5eNfl2ezdX2soN6ZqEYhLfGlGi48uZfPJCE5wU6KkVqwz0 p4dSVblcx2EoMYvLkVpZoBLZeNVERRF2VHRWWqyvQw9rBUVzoPKOhKdC+mLwyo3pGilAulsUaBI0 s1trjSs719Zil/GXNyoLnu6/HDRB5TKX/pPwM/1iV8x172pK3/NwgsUzQwR7KwKtLaBjEYzFE0T8 0EfBbx/ftGpZjItFXBOab+He+ASEpZlBsXPFRwj1ixkrS4wC7qrJseqciWJrVCVPA4nCnekTXt1c nBf6KtC30Ee2l96oin7Y7cxt6FDrCYAJzrApdJiqekISF89izfzKgiz0poShmHcMG3T9IdTmS5U/ W6eYSdy9OYGE250xFKuVWFlrq0ZYw65S6Y37e7v89UPMx+eRPLpns2RxD+5Wac9bMUiAcqlsXHlr rFhno7SRpq4z8wKCsDnNIHdPT4iK4upMlvHfHw15ZbK52rIo7+spHQnRkeOxvabQBINxfEqJE+5c VkuU+FPa7l6eCA1Qk2Kw5DoMA9pcjCmfAm5lzeE7Ndu40DErnMCRFPa83szzu2qeczqQF6MqUMZJ mUxhUucvbD2wupDw27yQ/iUs2GL0HXsJfHIlNgpaFxT5yWYXvb6u6u2FUsWYzRI98Lk5QpcgQqnO Rd0dX/J3RfminbfbK2kOzPFbmFTYGMjRKZWtNmrwsXieF9fRGeQNjgo6UqBCMFgeum9r9QWDEibT Ga41oUi9aBd9RgfglssDZcdMAmxNJq2WqtW9MlyHxgEK1qB9F7eBz1o18Xbab8zMkgXlXXOh2j6O CPWqQnG6LUM0CHWq9m+mxgtm5mrBaFkWrOp6cAnlKLXEplwtL4OMCAtoQgTqlcPE47H9q6H74ePs f62ra/slzTGk+kwDm4XFcD3Pelp1puDZhwJjgUN5NU6IRtEfzkzFW76QGv0y6x+kW19cm8wlSzTR cWHi2W5cpDeGf+JgmXcDRJXIf4Ak0Kahn+4ltPpXtTzeku9R/V9zu+xzmawKjFzSlA8sGfJ/E3o1 7im0LQT6Wd2SkAOF0+Qbuank2IKZjguOtLpNxgb1Kz0oPJFaDwsoSk+lYf3+Ay5TXu1Z8ZAWsk5j HCN3H17cSUTBSUp7fNDH2WvLuOfIoMF+J0PA9RVEV3EMsCg8dj++pwPYJCbsJ41r+2CEjt4oH5mv czrGtQXHP2AAy41Y9Og70nPX79Ltz1SjmDZa2mqd7HRp/8HJhwG2mYsspOQcJVcA4KIzk0ULWATO 5wntQS2+EZivu/tqBhmWbf25jWMEAFGc3BheJW4om8iAEjjmQBpp5RwDsM7qP8mBKc2yONiBRQhd cplKa4XPgW8KNmJpGbOwttoWqjNAr1tur0lmrC9JEbo+YiWaEIBZGBc0bjOOvn5UAxVMhzAFgyVI yt1Mk5jF00l0kLs0NSvFIq0zHvPFthgH9+FYP4juCiHcbTyNYpN5SMXYGw6Spn3dkPD/4KhPszsl 2MVh5+jIu/o321bJWTBzE4Sussg3RDmUEx7h5yqY1MphIbQtu7+ViGSaTtsP2pLmyff5hpDACYcI KWFbM+8TAqBvUgsKhn+g8JYQUEN4g5UBKv77g6ppV9a69oWs2sttttVAOCxqeiI/2tt9n7cSOWNB cvZCkYalbYBHNF6oMoNfB3Og3E5ceT/p0eMonM1D28byp9obSOIViw3LX6hAVbfKrSvfhiI3s3ez pn08q9GK+wqli0cCnue9P4eVwqMXTOvfjbPM6xouqGT5qxXJC2M0CtoHaqcly0TOKCRcmZiHrctP 1VaW9pRCFX9qRGqLalOkolbIdlVCuUK3eter2/rnV62+tj+T6MQm/nQITJvzsTLHgeciBY8y7cLT 1d54LhjEZSdT2hl9oeFWKz+gMUa9lsPn+hiTAV5jB2PuupVHY8nlUBq+5lgBQ/hEfd0NB/18iqoW 86WMeYQ3DjJYczGDZWDyCWATvC41CMnTwDQ9vOej/gXN7z2ejZsTC8ucKXS6cf+DwnTiCP6DuLyB PN65Dc+OJbZ5NBh7ZPTUJKSNCNJJoZ1UMUkFMhfU58/lZTEzkY5yxwnBEzekFi0Tvo3+vMNzbB3W Fe0YgFoIBZ5/tDP1dTDFKz/ZKizKMRJm9kZDoSKohqeI40GSfsZzqyMXJNnDyoVnT0k0s8zh1Skq hr2wUrplE3l+Iq6qHYl/DgPbhXoZQ37TzR6RwWR53dUocASenyaatkQLBn8Xx4cZckCo7W+g70qf RpaaKU4GOnjFD2lwKjPynLcrO3kP8oVcaDs6ANkhc1177Bd3e+BobXjZX7cUfLMhfahOXelfadtc h7boyV+pctBHxFfoAtEfnQNmLhw/RClabeX3LaUlYEoXpVsZM1iVgoIkNoPaXq57uHecsT7jk1ki dv8OZzng981nZmynOCCUKOuKNtkZWKTcRNPYwPYHNQrqpCfgS1NPZ2G8uJtOA8mIDXZrls2jHKKw 5MMXuKHKXk9o1cFZwFBLRy+izH8dcPTX81l/EwkLdUDcbgqzpNYt7lPA/HuQxhH4NQzfUYGQ7PnU J+ERFLE2rtauHkHVtOkEJYwPNtZJjbN4+SMRc96ZAEV44W2ql0xIWBXJoqcF/NVJRFcryRUD/2s4 9+M1CBsq/yKg6Wh5YlVqc50xga4q+/uT+IaTDOD2gPO/vAIv2ICnve7XxX93bEpHoJcCqUsR2+hu r40sfFhJz0cECPC9d/5ayPO4GCaodV9Ml6jURlDSLBGm8PSpsVvI1K67iTLvdVeCrYwCtWYPSo7b CJFwPXudpyTmDBMHFT3D1ySFcy5Ab+1/tfDbCoeLDLGvwmBKxB6ZyszAdAdQMUEEjo3nsfTlRoIS U2LzDYvZKDhnwC7K2bin58cLISsvsYVmG8fZghJLuAQgvLjpAL2KFOgFjRX+TZUdkkU4xZH915+5 j4fbVG0VTHWavj0KdrWGAObZCpcdUl8bv9tqRqpz3guj4zulxJgzjSeK4+xvfRChIYfNreyazLl/ q+zhnXzSHrYBwiPh866xsMU3Lo9Zud258ycC92lvyu4QUQjJZD0oeJEFslcpBHZWhpIgV5F1wCvg Olk4blR2ziELll1CBP1nuXGZVox2L/lt1aXzUa9zAxurlr5JdDITvYzD6yPmd+e82pfWtKHNAEHb aT6f7wP37yJfvgqWc3W5ECXMNqtOM7Vl73IntTBu8FNBxWEjB6iLsWWWoEMEIkzR4rnj9shpCpVq kRKPiIOQLYcSEIjhy3I5HNf/fSQ8MtGi1U7HQHLKjXeZsVN/IfseT02bYuNGwAxzAjhpSmSSK+H9 PuN551dvtD07IcG7f4OD6YxehihKi9lH4RBK5hyptoofdRerKuUcDpf/ppFYbKfg34S5sqYsmbyE R6BPx4oBWUgIXTdO5BJZ+ktSIGjZi0BNM9gSRAvH71HHk8vxfw5X83HJZOkZD5vnfJgocCKX/dUF 3zI4wCU2WyUwnp/s5UO5TXFsSQNJQT+ckygWgThverGPWC1eIWBksXycdSsZdn482o4PYBzAvJrF 5siCAry9g60aMeiwzjPUAVFGAguWkVkxW4uBO/zw+46NYv0MxZXbPZXnPoxMoehadcfoqehEMaXQ Vt8SGVcOXOFYxvoiIDfAcuIsB60/+ZluTJqwLtBZVBMRMdrwemDAnVMiHxqkiDo0j8+2PSKFHmVb 1K6WrUv5jYrzkLdbJyZVbe8tdsmgSEShl7RcclRs+68wXBfmNt64Z07fJKgTpV2Fx0Kprs8rTMyC uv0eUFv1MdmFDqsvBE2wTlKHuDFqrtSqLr3oVQ1iktjF4psXE3xaq298vtq5MU3AbLR7E4L5YIbQ xdq3sC8U6kx7rfzCFUBQMbtuZWcF/Nj8mvXdl4QUXfLq/xxcMF6/j6hy9u6JLATIdkYoBTkQYBB+ RNSRomm1Sf9XbVEfG7FvH845Kf5wScUzTTSepvHlNY+KeFeTzh7eJMmBLU6JF5T73MFYL5Vbhx+v +7GwyZF1okTFbIXm7ChAxJaaDvlSUMHWTo/ZgYfhwoSR17/fgOfW2PqPvwofBC9eFk/ie1Kc8LMX j6z9aLD0QRDReXG3wj8U4xBrI1ybXnCnu3CvmP96m3omxlySHWVttujh3yubhywt/Dk7z6VhXW9g 443OkgMOn3Y5q/RQM03VyHCREJmipiFJpkFATvuIctmQIctD1FlDvK5q0ykrnGyb+DqdOwKnluwz 8U/8Qw08O3oHRw7kOQTxWBPR6LuOMByeuTEjSnGFUZZdMc/6VTPCO9VKSYArF2MNSBcv4SwHd0s3 PDjJ/1SkAYe1W1IlkVB+qjZhc+N4ujqJoqT68Te5Y3S5mUtnYJnuzd+H4jv2AkI8DcPfDBlyZQNC VCnpuKK1ASyhcvpVGupcNssrba7R7kbgdtZTcyN8YlgkFwzMGIc10xBmg92yJiZohBRmt1WUu8Rd Z8GqINQlrkmnFqKdmyBWl3ntwGmGe30S22GDyoASZTSKKuLP7CI210RWGR8dFRozkMKWxaw/mNeT PqgNQFEifpxV2nfiX8ufHJnzytXfvlesDksGx6KYg+pg0RgSptUOpddA8AwHdS1/bWFyy4rmU9E7 7Ie8+OxRYnTf8Ua0JPPg+PCE8IDN/scfJ3Df6evE2Ji/pmK/x7as1ByKIkf4VYZdxFSoKxf/M8kg 5LZ9PQu9Ji8L6GHg8KEkX/69km2I0aEedKK7oSRbcnbkNpK0uzhrekaqjbU+1Zw3KL4H9mVnZ0iQ /YtkGrYjCG695uaa2KEhwZX19gInQetinE3iaxHu5zl24p/V4L+hMZEogk+0ZgiSEZzJM9ujfGLI xLSOWAfGQPS1LLEEuu5h2MRshIDbRuxhZ7kQ5egviuZUzKej/H7TQTuBXk+eYt2hDswBT96xedu7 t55KA5/PGmdKPiK6R1cskBTK+9o6ZfgNxFdQJ2MUOskK0hvK0n7X5oRZYj8crFgHy8Ll4iHewuqM MNpgt3Ka4UKhr8q5UTWDCpuDb45SweAYdVtv7pwwImszSrtyimbrghm61yReThqvau87UKQx1wJN M2sQEdWlF7+WLGc7rHkYxLfYWfw6ghwvgqYtlj6B1JReSv/4bw7cI8U1fZg8dil99IA5wGIHc0Db ilTaR0W2U5Ql7I0rH7kdKkpYaD2gAc8ma3maSx4fgcmmrGh3m9ksh6sVJgyiHib/Znj5mv5NEGiX Ehw1mGblrJrgNU6R/d8v70c5khagVyqg8n2znqGOrCl8Og8E0TpzPJwrdSJ1GiPfleWf1cQ70sB8 quyc6xh/E0ETM5E7pxyk1NAOnHIwhNcXtZhi1p2rPpjly5sBpKPHbgdzYEFshPE6RXS8qWNy+nVo V3ea86N4dG7RbwcMUvKeibPN1Z0VG/FGHsjlQq7Jqod3Q+3fmAw7CVCcDtjpdYM/GeNXI4Wq4lJG aK7ReUgoHwvGI7otJwc6R0CwdWkfRFxDm5/bZcbZtzTuIab00zLIqIVY/xIN0dUN4L7cLZ0XPJve g9qq4E18QTLPYIxJqUUoRRGzkfhBL1yEWcwV6emWimgGWMGirk9jRgIzG2+j3vkBSAPINsg/YPgU ytAWDi3AbYjgVtJxaPZ9fzvAQNgNZOmdEQ6lvwCOISgW7ligw9j7K2bNyG0/5854I8qoc7kQxpN+ rMfvkCZr0DIm/Ogchr/k7h2qAMUyJLeDODaUp9uvY3MINA86q1xw+wwwMPFu/DnGVk7ArBYj+aCZ POwyLw5lwOaVP85/2rKAphBFZLlQTE09DtvMwS5poCQUtJy1Iiz2Z11nVeeUATPkDLhcH5tdAZnm TT3vRaykL3RPqTMpoL8LJxCUaxNqNLq3rwtzQTzNjuBJ5kmG8sDP0COtUl37pYGCpN014ohTw55O lDQywiZiOEZlljC7XudqPuAp0iCu1cewoAHpPVMKntPHp3owX6DB/pU4x1igex7pwXS3k5muJDua y6ItVD3g5Ct0qkiytf1yXfR4p1TJYSRc5mc+E7JwDGR6w3DMPxtMJK4G5TKH7emjgzQn97HCuSEb sjh7UiMYF/qqQcSpSVw1/DhK4HZFIep4H7kj6rP+akprVi1DJjxH1SOdhRDdbhehmC5rQTSQ7dnh 7PsQc+zLggzX1L/ItxDg1bIdow6Xd7kR3Ivel3A9nVmuUpzxQukk2YTrmCJRvQrojdNp35o2BVna oaVJjGmZmmduMhV/B6cr/I/BhmBAoDLywyPSUe8uYEDkUlVEzCKWD4tjaC6nnUT/AE2lpDB1JR67 a8N0B/dkwhbL3eEPhF5lq6AZe0u9n6vWpxSKDryFccdn9tBl8sVsVB1vnKHXfPESNwpf9LvhbRLH VNEELYaZa2ssXp/l6rZdwgFyU7xUac08TxuoUF1OeMtIhDtoEnR2rYRWuXgzKtoa1RcbNNOVjCvR +7I6a2RX6GiPvVMThIblGqFFGRkCw3jPHPwWSN4n/VULVVOMK2zyk2FIOgAXQU98XtMAP9mGVjep YzfPJtPf38RgmsGPVTP+mN1P9WizApHg0s4exKcByw6eo8i8iRy2TS8nZALi7Tqsr8B816agR73f QKRZpbU2r6yfMcyjrRRheGa4BaSl0KjWwvDI+fKA4qNJmj4COOH5e+OU/qt6sxFYz90Xm1Mo4arF wKMysmZZ7Utl1Z7fV24qsJablKT6xJ3FaaS2WOkYKq6LilstXZmlDz2ho2trULRlkfPbtB2kAvL0 rC1hQkTaU0EukygHpJFOkxh4QKpddmXf5J0LOrwEtUnlwnYgvdYGUSv0dzdX6j1rHI40ptZgR/ft tURCc1XoinQeof0IsVlYUIRe4aFqDWp23g/W6HbTdD/qWjNC06GmULeiHHT+xiO6pvc/+YgPmY9w mL8h+KDZcjUZ0OE6Mt2+jr7K2FeKUXeMsoW9wwbURFF38hy9gAWoia2UPU/BOKJnFl12Ga0J1m2h Mtr1KgJUodYGtFwoFL3bB9p9DMf/VgK9SW8+BC0iWyEOuFrZ3Gx67lvtIVaNiXnsktA+tVQDrnIb EXp2Ajf5I0+ue/aItUU7lkIhuHTSlTTRF1bZGp2kX4RkOgK67fQtvtMC40qLsnNheJMOeJcSt7JW FYejrY7ffJkKhI7uTK6LdXS1ZlhThcPC7Xic0YXy86TGKp/P4sJR19Avhmhovh6ENxlBwPI/h/BJ ZRgZlxE89kk2wRLX23mR69uSOPZXE1AjJryqfXdci2qtJ/FJm2sidSOeA5BjJ+Vbq+AXyZQP56OY 8gVUcSvr64yWd9fB2aUarREHJdH2AmvR1Zf6Z/ozlCJXUp1s4eU8D5mjAF7R1CZ7mScTkdAvp4Uk yxe92H9srYF8zaY1LDOpNg6MecosiQqTdQz9yfxde9tdUVjgiIf6zQ3SjZdrEtZaWwnazqNUtpmR Fl3TlwWI6sv/Z37MIyzzFPfaVfKq3DRh/a2BR1XXvZqrDxFUABwUcVRemBvRK4lgaSb+F/zedf90 dZ9KdXfJJUpS+6enDbqH4qDldsE6xDuLq7bElueP4Uac9zeJbYDq+2CLylqXflFNQpMaQdD9TXbJ RcusAvoDTkLpMGFVIOPI94sEOAGIU3bTSCE5/crQZ5b7ao7HeksqOaaPyP6XM1ct/FKtiojbemjM nT2nrocMYGl8Wm13gofQBlcMOJyiYdr/kEff5zJFDtaeeLnQJIxg/Dbt7ia+beEwqJ7iBssV23X2 lpdeDKywMHObbTHLZoL/wLHuFlElfvH0sIkq8P88k1YwBX96I3ro4EovycnB5DrAeE7M/cStNaqJ OZxjuZwFVKGwcskTCvCD/mY2UygQEFuj6TFRGXp9OznKHY4CQWoT6yXd/754qcTaNqyciA3sQI/R TVNH/Bfya84XwGQD3lPLPwofJA1nqximZPWlDEGa2juPr4yaFm4ISWpPyFQBZnhC5hP/NOaIyGMg sktNuUCMNB04q+4nbxK4xK3QZ3IWugII2m6y5jX7fmYCXgbzeW0vV0AnvJUnR7/HxLKDrIyloSP0 ql0cm6RAIB14O/sNGInXOWS7uksbQQh/O9ppeIwlllxhcYvxuPLOxuFz6gCkwR5j3yUoStk91psF 0W4U3b53PsbQ3H2TVTYDGKS/SqOM6wdHr50KHpYMEgtVAfygUxfcgERS2HD6VOVsOg4pfqpbJOs2 +NN8NxbxqKyA6/5HHqksbtCCJKGQHhPITsNA6MdK7fdddjUOYUAkPd6JxA4gAB5CdTCIK1qHeBdO Du2YorubMXavBRTqc7nPPWOUMxeLVS5T14ouxWzKNulUmITcspOYcNn7TuqvmbVh7pGtbk5q3tKj q6dBEGPnY3ms0fLEe41/YBEvPGisWuIXitbdMMWWGzOQER0Yo6H3fG1oguTqabtUhGTIxB9muyfm dyMYyWWoat6g6kJxDgy4btlF5JP2BE4yGreT6HTJVQUGt8cIBmBTAWszUmwcvHffuzD02x5gSqsG XZwImU5RDM9nwoR5KFZ4QI0ta/NaNhXWqGjJFyXUpBB8al1ajIw1eQnuPCpZY1uS7o0EFUUjKCbx fh+PZAEC8qBjdd4qooN+KOuqZYTSwvmdLXspaWe2sn8SFFDlVG+R8zwJRWXOJgPcdhgaT3B1/oZz nTuu/w6xQiZrgxRV2IZa6GPzJ1YNab73KY4bm1i3iQEkWuE0y+N8DmElxDem/ux7N5JEHLY13sC+ e92na0ZQJmSvoFHjcuUS2B2xwV3EPSoeq/AKaY5pxj3E7XWegPCO66Dvxz54xtP9Zx3HcuX4fWER PmbfvOIjergeGFhAVHS6bFWBulucO7yS7f7vrKn99LjuHUHxJDdXrTn91tUJeYPPos7va+Mzpw7o aYyf/LpDLUySUn6YvRvrZWu6zt/JPkWQ+1L4eQsMquse42AOlCki+AZijOoy3HlIIpqCs9K/Ds0Z v6/uuSByqomYL9OYUYgom66AMSQYSwjwN8alaoVQW6KnELorKi+V8zc8GHdco209yUF3hwYSk9V4 VKO0L890ktoNbCmYZOtsStZrzX/Sgz7HEJ6ENisndiJoUyVACnZPdTuI1fLK8RdzpBFzLQEcyiS9 yjc7PoHMB2L5RzkAEUmZ7PMjjTd1vZgGfXG92uPKnxrvXBvd2+y5l6V9XhheTYEixY73mtpfCmLV hiL62U9xf3Zez7al4Gu6xkSq8QTkiBPpvhhXCobuIFgfxrU/GbB3SA0DF7KSuJULqstTpeowVbpL IWxPbHn+kkzxagEoa3m5rS/8KdKL2Z3j4ZzzwGTJ/3bomvbSBhbbq2KSJ/4nHld3/hvlnyxUEwlJ 8JCkj3zPL1DxQSl+GB/aGslMf6f8zvVr4HBRkdn9swOn5iuBZ3MAcWwy5qCIDTvw0rRTnfUjuFiN 1TJuzUUCp+mdUwcgcNr58YewWw+NLUw/3M2PQoo8FqoFxLiJyrew9ZlFDuyFfIRzuE6V1vfLcAR/ ap3itm06I3MC3xtBiUT9FWKNcvkJlzcKOXZc/PKSl6HsfRdF/iglAGluHzPNmrGtHw22+Epq3/Bf qpGZiB6Bx/MTfn0xYqsLYLHxPCDPJzkpdWMmfuuZ4X0Xhk4x7MaWh6FZJA26094fN/odtjBuOiWt lLJJaeUf3kwORKHKmMFh9kLrXDqOlUnvULsth+r6G+6ZNdal69zEf7YJuaj3LFBQZwnl+cj7eC0E YJ0l5wMMcDbkmuEQNS+wwIFZLsWbsgf8Hcj09ypFs6jz1uuPcrvjUTMW/yq03QfHFQ4J2UgfInTk LyjTQ9UJCN8/j3tX87Vdzkk6LrnvqbPzRFH0DuARR81OMKOyR5VrNi0UhsTy6tGwPk6LY33aUA14 WYNV4+948Nef7V5SYB4O2F5GHkYqbkRnKVbp6mq0RwRJ5e9qKvcXaGOyznFweootQMoRSn9vjD5F R6TQE9cTGD1CpneCRCbDrBC/Ct0OJz4Rcqql+jyLQYNrowAvyaH2AnS1F+r3xwiT+V7q37oYTd61 +V5M/bdzGqPL1fDz4l1QBRZ7Jkz5+eO9jN0ZYHsSPHhGh3UFSgwvRNY8CE1E2jB1g7PDzsdoRA6m wUpCNbQD4mg5y7wmm0zTPBz+PkFzDJM+y9WPy1hYHoVYKbXggBuJDKZ2x9wJ7CgA4ucibCbNHrIY G76H1XsfnH7qZTzrXN7TMrUHUELciB5HteAxm/FLIlH/dp7VplB0rMaCfME4F+YpXDoI/4O53UQx aruGXqXbAPyVQ3j2KaI1UqoL3Grri+yQ06tDbZH0r4YB3geQIDvhk0tm+fbvYY18Wi1isWYvB8H3 V/aMFrNKuRClQS5CIMxitnnEj57Xpw1D/MWBWTJqcAWmM8xl59lvy0xyQZa+RfJx0wKU5dRP3Mmi Rs4oB2UFyEyiCwXVj+U5gp+3EG4CC5rbFqyAgZEawozbuzrbBXJeOJShLB8lJK+SyDpI8ud5YwMt cBTMlHJ+6DCjIdG42niex8JrtEVcpvhsNQ0/wVSI3nM682Pto5zy8s8QVVaSrns9CQv3Nfdbsvj7 26z8hiZy1UhxAzPfBWRF5ybLOK5b2gKintUEAM+O2WnYRruEP4yQpxLjwUVjeiG7D1coSm/AXovs d+6CUZXeT+HsV5OXPVgwi7pX7+VOS/LnWqSL8c8jVw96PTkNGreEOkBS0vtTZ6sLlnRuFQVAPV80 DOO1GuDrDRgMaKVSOzgrK5s4RGvAkg3gMXQAlz+CHWaBoC/cnLIvSLcF0JNcAzy08dWewiwiLHji Heop3lCNNSvInINSJKhUDc0G59/A4GwTbn+w9cRnoff6HWwAfwidzAnKqwLuZj5fhNKeuaj4Ow6T fS6/h5TX3i9VMVH1Ra83yZRH5KTyD2EQIOqZwqdDatAaL1QAp7xcXCGRd/EjTgjjuvN4FP5kTpN+ E57Ogw2gN2wr4X9ymdlporBzJRSb8wzmpLmQIzZp+PfpgLCGPIsnhxF90ogJLnZwvKWyjmmzVU05 3fY9ReSBIyfYYG+z7EA13AzaaSBWEVA7ouJ9MMTIvaV8kEwnIm97GFgK7e5OYBVq0GK83K7aXoja oAM2de4WAiMQXyNMsArmb7hMMID4AKmSCZijzupIGn0hls25ETOxxPkG8DZT8OFCdZ5xBIxmEDFN Zyd6o40u5IyaQwEyXgS2w1KKbpRoRVmv0TM4Oo+hd3FUmyi712zKrnEqHgejky7SEmKpO5rUVHZe odBf41bgX6/JoRxsplrOCNuGiIX5Vk4Jx5nM0chOHfoFTeQ+QXPu7oZYOMUGY9onh4EL0tyqN0HO U1vPZ9TPr52dtEG3+DuAbB6334momkP9PYWQL8Ik9TczOzikrv4wyHCpXB4d/BoPjk+gINrSmdI5 vE2p5dihmEDcyYnX7w5sc+xDQ81PWZffQ1Sj0G1We9CXe38Hh31HO5NWz/3ndJ7TyLz9HGbOlpkm XtbjXnPKFCWMhbn11FAiaQZavcxJV/44rBvfF/P3syCdl1KI2SYBtBHPIgfCtc81LatjocIh6Zc0 v/8BciqoVErAiX5+epAjJsOCEMO+czmEN++z8y6nlNO85nGlNjJ+EOP38rSKM3aszstNQfEKYsNo xdYxjenDDrWRvWVK/Hup7eSEdVcvzVCaouT3Dx3LvVtlBWD96sbgXz+IQT7z1GV0McTSSQDyzNlf B4Uxc3PsbJrfLmej33yJmyK6cpNypU1/fgFm6v5mtFee3lCYcx2bCCNZrAfaqu5/T73cgGBivQY+ P8BQKy+v5OJtB+1YwdC0PygXi5KUAEgd1vE6JIrRwbggUYT2S8gMHo0C2jT95ghpQ1MjWoEp74w2 aKAw08x4N7mdU4ZFiVnXSJJjA85tl41jRLUILfJs4FFZ7brw6g4IWPgVMPZJuZ08S8WY+lfDKu/g pA8EjWNFtiEOkUuSsBBreICCzsMeXTEMIgzmK5uUp3Vnphd4daHf6QVrZgLYinwuR4GEm+q2hiqf 0ltiDk5SS6DdrxtltZJyMsxkCvclc+wUIb8NsciMHg14z8oy2m/OaPSh3KtDso7oytinNahz3thx pNnZvvJ3JobwFicykXPgAZ3iQv53mJXX4sJWZJULXv9BIXMBw+vo7w3QB7E+ci7scgmXyRXyF6JZ IsiZZ2ZF2eqWZ7yczz1a1tRwIoaNBRwKKyfJPw6i/M88DrXC8q2lPv55iB37QJP1peVBsCzzR6Ph 6cpDNnLtFGXrUppacMi4H0umJ6hDu2QJDpIr3Xnr1MdsZR6eXtj2kNtfvsfWPUaRfonA7hOiFCz+ Fctg4oN0+juIa4IGaqV5oB4jAL7xelxH1n4eqIipiQnNpOprpLWH2/yuRrPSFXZxUiVXl0fyjjCa WtJZfbq8EsrmMll/19RV89QX414Rc9YzSKtJppyLNfnvWPK1yuOO+RYrts201SxBfXhuPStpUK2t 8X60cOnABDbgx4W4T/H6WYOngSoX0hbGyJeWeHDw9o8gvktwxABjl7I5SZsaV9jm1kf67a9ChSRV WkDaHuHpp41Vnz3n1NSzQ5sKN46OmfgbzZW61W/yVXI8d6lzZA2XC5XjVgYbsQ/YXtAt92zJaR43 qhiOgv2PjhzXkl70RKNhVsEhAb3Lq67DyFVKM8Kf1zcovukqSo/tXHadv4EYtcrmC0RarFaYAzGB Ny2HSdVxd9GEn5eJSoV/VCQdQq/1pFGZxCBfwyIO3kq03Us/JHrO1jFcn3cqE9iT6awqGwZW2Peq +I4gKQym6e0hbUu+k8BG7QsptmsSohE25FcbDsJ1TyAFtDXoamjnWD8UfQdtDUhHfdzaUnLigzIg NXJq1tVC45hJpdet9HRSf3GkzaQ8hwdnwb4UC0u84HD6dmofZE2/YWpfLB3+XWgnRtsAheJER3cw aXr+aLjJR+XFn/nocb+pBC0z4S2dREn9kTt6/kZS71ZqhoLoB//rnVBaINNKfByAS3rCPwf78IHP gy6X8HY9GE2SJz0gibCnd/oMbHMEUcECbjivnJsJnP+6royTfYb8w9LJ83dT+iMa5L9cUunfOIAC cE/3dF8cCgBWgNcJAsWTmUIKTOB1iQFn/6PvXjkWIlDYljUwt99tT51Z9HJDagTxRvLA+MrOLewW 0QPB+ktLmD4Z6uW2psMjfpMLqIHKq2mQPA6qFdQiTShqlFkp1LQDQpV431SZ8JVdmHCticTsGLWp f2Wk953jK5SUl+h0GgBDRPfwSg0mC3DKPPTLtsSEPqpDPomKZpZOKBaGG6RROE0Yq1btXRwsdpdV 5/946oytStY5X/tWYPScgXRh1oeiPcfmQlPO5zVZqs8PaThkgQEuAo3zs1ew7sx6YdJAWXSnBn+S rsGpOxftYO41NCoAzITIOzAsndKO8kiQFCHqhfiIvqP1zg+PoSdcb/5s84HupbWMPFfqmuLkkFPf gP6mhrri1gZnw7+qDOchfNF+FB9sxy2BMGBUk/ZCG3rLjUluQRiZaXUV4NHE2WtAzSfdBa5J90MB IVBGzqyLuYgr1hsOWQM5nPbtuNEcIcFTcO/VSDsdRTqOrvDM/MB1J/vhZAF7M7/g0Vtw+sroheS9 2fNBO/WLfwd9CZ2mMeLz1jRCRgu/b7b/ftEBhuBaG5jrJUKQY72N2y/6lWLDmAu2tbhtGsDmhWWj PGEWlZKWkUqEQShNK11vf4XsLotaJLHYqSuPAwy0iYLfZ/M87xuBx1jXjOMJsOU9YE+mz+sLLnjH ymzwRkEpLGseWI73rnrX7EEAMNzx0S6Ey55rO51lzzZhcrz/FsmrHfcWE9u+0CS35uH+eqd2UGs0 WB70UQ/ZPd4xro8XB39ipavvA0ctFUykoDOxT7txgpopsyBQY63jE8iV+I32fndxpfZl3PZHk9Tr FHgRXBS87mJbG0o5JX1XIFHn6nb51UGeOl7Xsih0HNVVZbxbbAxTMmTCH+mWpS/U4cd76ewcyPD/ oDkwUblVKCbbyT9hTOEvV8nEA+rJ4pGk3/+fEMjyV2qaQxvmMcsz1+xE1xVmLyRH2A7/K5v0ULzV dRwl7eivurJa9SjPPp5dvNbg8BRaYCIxolvddQP+QxQWTzldysPfBWaWddouaNhnKnB0gsUm1+vO UX3WIxjpX+NL2vvT1W4E+RJ2nT7bMLhTY9eajU8seOkOfWNrxgFDtdpENGILpxw4S0leUhpiBnvH qxchA7PEeJ0cd3R01SO1BC4ITuPllvEMSiiuO0NzHnTjSzcDC5W/DJrYwmy5zP0sL4LP8XW/Uk/0 Zx/PskyqxLgD2iLDu4ZdCl85m3QMasFKVuyUHd7KAoqHYhxD9yakbBgIFD9nmegv74FiO1LizsY9 HLQag7PB6kB35TrBuYU2kcxhLTdYvEesTcIdn1E5QSSity2oKQzG++iCbTLfd51IZQxjtSnx9hqY frLLEORub96kBPKTe4UQnPFTzup/WkBWNVxjZhVkmOrbT3hjHD+GXnaWX05uZwaeAOxxuZRDQHYQ CidotJ6MBEWb/+JY0meZq8YQa32m5C5NMcuyyFSNdfkCk08dVWfwkPl6/PWbOvpfM0ONGOU6fW4b Mnf0N0dzc6N6yukWPXXmqkSqtO9uz0q8lsrhc3Dd9TNrld2Vw+uJw4kOrPiPQiSZ2UL7gfQWByzv 9Ed5mKE7zUf/pz5OEYsrJwcjpBdBSA5qlts9lhgfz/dKkFtJKxXV2IRnDKFmsmdve35ruXGssMeX XtwX53ueS9CtNhO1SR2FlrTX9iT7BPTAwG1Z8cefJD3dXR3P4hzTvTMNUf5di5PdtkqqqRFsGWeU D3pKqLD7pmekCXDunYFTrl+8miYbgtYaHl7sLNS7XyEhm3CT7AXd8mpDFpV7v8XeYQ45d6lgyq+u yJ/3h/kJ07SE4bZqxBrkM3++snwErzXtR51dotqtYqbaQo6EKuUdqwrGZwZ4W7rbwJD2LiyiQ54D ZxQg/GyY929FLEa0i8NdN1LOglTcHiUtt3fJOFUb9TyTjObyGG+q+Cxr71hvlfs2IugdEQa3q3JH sZTiGFiGbUk2r4ctfZlI6yc8DokV/H604i1YIi7XgHZuwfjeafVjVrZRAo+jMivRAGKXivcRaIzK r6SFTK98R9kXES1qUJ2t/vsucjwhT6NQ579Qmpd48v5L6GSPZe0UloPzUWZiCOeG1Ctv/udM9z2T zzRujO9MMTh4mKHHeOONEfePH1z/wtJ8lymfkNR3ympg74tnhdlQrjxRS4d2iGbUlEtT+6IW6tW2 Nm4bfV/rXDivpwUa2yNfWr3WChxAHCK5FwmZ+RgqFXwU37DcxCXcwl2eKHdHTBMmiktFghRZPuAS Aa5skhCbaPexIoy+vqZPSM12Slc/wGtX+w+gF5JCqGN8aXEDiDL+rozJBG3CaGWDpQLU5sR1P1Ke dT2xswX5eHuSoHPhuXU7qe0Zq0HexGGlVmsuGzTIeKQOTdeYw7lKqKWGRQLK2s9Ak0GsA9tPy284 /S1eWXWS4W9rkaY7xXsc5lYD+4aiFuHTqZ8ctp/aDPKYss/j4ScdQnHs+oXHJe8csayZiP0qoGJ4 7h3kDLfrIiO7zbxZ2rWM+rDyRjqmxMHAfRIHkKKnLiobyEzNy12U2jGbTIYz5QXdgTGyNVBmdfWt XAeo6bPpFcKkhUXWbyOYkZ4Lb49PYUop2tRcy/w9Z2qKwo7eL8JvSLODpI9Dw68JrNKmiyGJga3a pnBZmNlNNu0+8LO5tYLgMDUQ1+K01wCd5fPDDIhx4+Ol22BK6I0Tbk9gfk96PZm7bxP0ychDh0LZ adRrRLDE3ho0OophtoZWYYJt9PPWLmJ4p0ZeFwe2zPtlEz4T9Wp/VCzqW3V0IDz3nGSTicSy1dIK dPFiU0g5xMhksqs4we/ATN1p4ncLv+MPfTguDiLOw3PmacCfbjD+y3DFVgZLwnEV6NtQPkD5nNCp BjwBymlrL0kbyqzX7zLy+2AOHhAom/xUBKOG+2AdE8+5uCKw1+90JKO3Mle/knZxZEVxZK0oZ08b r6VMb62ozyTgKiy/awPEEKhhD/tR2KNh8DEYstbA0ZoSTM0be0PwIaPnSQ9+u37hvQXXEPc+NqVt LkWG8ZzSkxQ/g42g0RHqds/Vyl1DKDFqFvPxUBFnps2yyd7XVz1CqjcDuMM8UifUX7oC5M4ZzhLu 4ewuPvtSR3mU5jDG+AispqCQH3fodFAA6MC+hh0nV5u80PRw//ErWvsWMWxueLf68jtM4S1UUuqt 6q/7zPaSNnsXkbA0RIMAe0FJKVf83elqUGbAxsI/4hEI7T21ro9+qgcWV15CUH6+4icJjqVshsRb QbMbzonPN8eJRBaAwD3vZZT0JO9if/LnAu0XzV7gGKqXHmSyG3ZisZHdIlTf5Isz5tiC3eWmniOo C6fBwsu0cHTfn8TAsJfM5cqpMQ+XGYtKWzHuZ0ihALoBy1V1ANhoBFto95ztVwv7b5hOikwv5r50 qF2U+jNUY7LI+GrS/+/Bz5XKV0icVc6f3QQ84/UZSPyqLEbi7IDSzs35XrSX+D+K8GsXGZutkY77 c+1IHp3PZYb4L4ziJfMx/M3mSaEiBgSOANL8kXgt2Soh8fEKYOXJg7/igMBdHzdvMOgxM89S+VGC 3Y7hwzcFARu9CHtuY52zVy5/c8Hr8vMIcxe0U8/u+40ZdFSBwyJgczU2aDQFXjCIZwyXMgNibssZ pEYi50kNxNRklqVuj7T8ZPc9mXtQ2KdbXyrvcnYWZ15Pfh29rtWBZdIgv2WX9c+gPVTBwH/IBwn7 P/mCpCUoqXV7latFxCdGI/NDCIqlZmojTz8R5W37BYYENvRa0S0vCZPr7UdwuWqETr7By7/jrWXk rM4w/r3deBGoM1e8pIV+pvjoN0CZ1vpdxjB9Dl7O59YyK4DcSn1SNMxm8471YtH+p/a094y4vzCE GmeOz8lhYWmnTlt0wvvq+8nAQADk3QL3eBN4+MkOxxXLeH2hQV6a2nsuaxeYULxtmW9uYxiuvl3K v6oS3KQD0FNa4cHP/pfCh6qyp8doS1JNTZv03sBfEcjzV9ToEgvfmz1TV/i/rOWzIVtikiBow9am ZE86hd7MDJG2Vv1o/4eWhHU9WCEdvGLx1QpyJxBreDss/7rOD+lpKtSdtuIbDv0+RF7DsxG+5VoF 9yRgRCiZ2flsge1kYpKTdHkCd/CjySP6Nvmvi42AwjY2zEspxyKN2H//Alpo1IGcgbYVhsN4tKw+ 2+kNKEVhiuHPwNgDi+tEssxNuFWPOuGD+r5qyVxathq5p7cr2LeSfQmimyAv9a7lAt70D6GRf1tT OuICyJ9+MrX6c2iVmtFH83/ZApZqOWIoK2PV98RoOyX8rGlukGEFn+qk0MtWeWArW9h8WTIL1qwB O5JnVWG7hxiU+oAL4evQTS7/47OnPC79jnp1+a1Ab0CdCmMN+MIx6u89BNz8lwESFH59KCP3vAKq HN1RO3+kX/MYpOVmHLbsTYvNb/S6u1iIlx3prMhXwwX1Zc7xqUOQChSEDEK2+Wbhid4SlAq9YRB/ X/5WhotiqRYFBFPWRq33QiXuSd28X6fh4BQAZOtsVQNkYE1cPhajw7WBX0K3Gqt0ySI57iJY0EwY LxZSc0H3qbXFHg9sBZhlNd42zhnWrla/eNtwHF12gZrN6ikB55K42hPiD6p3AQ+r9bBbfL05cSWi OU1WcLaFopS+yKZBQVSn/4GIpfc4Q5Mdbi2W/CDjAbWPgMlyOmdBauHcx33Ky2qe9YZL+J2dk+5k H0+M67Q+Bv37vtFxcVrkLTGKgleZm7xhTIbyqevysNYE/31Ie+6R5z0TI3ourKDw6rCEpBom54JZ 1Sgtz4YzcsmYF3XJtMhYt3dmGWri/r5BHILHw77Zx6bzbpNX9qLKmcyupHysxTSpIKFVm9w1YXhn uMVlb03AQdoHHgKTvnToxvHmy7rVSEye+lytXiQUsf9BE2FpOQLVGuE2t2nh5ZlhIzo9W0iNbWcc cWzVQ64CDaGHU1ISNPst8YVkvil3xySFM+qGQHQDpm+gL1YHCyfbWwCEbUViD5o+M/LbfoR8QPRt 2fJADo6bI1d3u4DGafCIRgsiH1y6oV7l6lFUoRcg326uZ8dbGeCgEttDKiF6yLyEFsHvllTk6wwL dWFHYGLEI6YAX1P12ZPsZPtsQeRz5JqM8GTmtO9SLxUs8+WDkzrIQbL0aEqHGCajtUn57gRmyQbU EsDHmPckTtEsJ/IsWjjlB7wnCjlyvcdOFCRKZI3PZvWTuDxcd7JIh9/2+iWYdU1tIuojRsEy2qnH 7+hOcGTq+pzooikOVcSusnY2kBVeoJ72/94zD9grN6gLF66qjpdLy9McRQp+0tfnFq6xHkC4XxDw rwn6Wwox1/4OfRQqRPQGmn8QsJCrN8X7td/nQknuYMaK0hp7aRGewsIZKCUHg7gVoE4z6dl8cWVL 2eQmY1sXiTprPCCI7dfR+YkrHA3A7aWQvVPxeb1/fzTxmC91vRTuLwE+wiHEbRJCOYgP2dJ2FtOs rh0ThTtinHufnk9rIl/fDijz4+Y806EXPH9KAU6huijK5Y0xBRTl/rrXtH7s2671FhiXpixlZekL NvviK+L2ivU7T/wIT1fhBFjzMc0TyU5ksVi9Ar9fyhPAAo4lyZ0/np6rsAOVpJrp2D6Ysn8WOBfM 1Bnnf8ZTOVFF2Zh6v2up9FiE0wWhPr4DJZ/tWsBrqeuoNhzA3Og2XrEhM1blqjwpZDdFVaSXhiD/ lbCZD/XNvUvjFt8KoH5q68EZ/LFoeKUlthI8efrpBxPi4+9PWV/dpN8aBqaPpOFiV4RaXsJkB9Lm 1/RJ92pO6YKFWat2JJtrx8xo/kgQGhOGWko7DaPj9LAzs0pFeAKN+Sy6+MEhgzxLGHac9lAqBxXT HhBCGEsPoARJ5R4GrUDjHIfwYJdEgGw3TVgNKHskiS/vnfvsIgMXmsT1bR9Cyt171yPjkLPiOn3G 5ytYAI3N+ZsBYvTqqcfUlzuoEMlUAjLeOJAWhLlTv3XLDhCjACNB6jt+EMvIcP6WwNzLj8a7slEu KpibrNopHu6rYNG5PLyvGyiSOn6wiSyJg6dbMsN7jIkor+1Eb9vo0Q1okzODla8Y1EVz6CARPk0L YsG2RCozNsCfqVIGgY1qIFSdsteZ812+yuJ1jDSZfjuEeqPLY8Lv05TqEmPaPOK+WPByj9AINBQ2 D6gAY9Fgnvo12EzHu5p2Hsvw5LDhBH8HoiRCqa6KQX58dw1vFrV+uWvREjmoirL6jgFcrbDILeQz CQ6+TGj/sFAzbDF/C564QlOKkMYG178Z45B9HfXGZwmNRZFmup13TMNyRxVkl6xzKi+H55whaxfN 2gD/nomg9Tj9u6OWc6wNuz5VOTtAERwc68Y6ACzzjLeRa/22NZiowp33DixtvlQVtcws1Mb3ojH8 K3crhmclp++Y+Vws93lDravOvvNq45asSmU8A/UOzrfCCtQJYNKCbY6Vh86mr725RXGTNoFtNg/I bk7rMn3pzcgveHYsfQsHZyhUjP4/Cl1My4pLVNS398fjlC9PYp+DiL74bIgfk5z8UjEKaM6BHtXO OXUwb44px65flxVl0HmxOmZdoflG1FEEz2z8m7xwckM91y0uK2DtfOXuRxl7OAHoXWs7UWwEUtMw MdNE9iWkPUsJwPYyvg5lOeoLSKhBYcDWtBX0JXP1+lzUEOV9XvAUxaKUnq/95cEjkOvNOoH5T6NS rxOgcNJnoDCfIsbWEgnR8U2YgOJpN9X/lHV4HAZzkCDI2VXZArUFjHrQ0Amtg9e9Mg6egQD+vo1W AuuQ5ydYHhJ5dlvUg+jwTzffpU0YdsZw57ltLCMiZKXZPaUCb8RRYb2pBIHHSofdeB8g9weaxAky xORE3OsBxmuD1d22dr262BiYuxEIMegHZhdvNP9YnnA/mb5zqMPHt+Ra0hZ+PvxPHlgYSl7M2HrJ YzVa3gOtd8aFeVQheIZmJdv+tvIbB4ezJJilEN6suvoXWWEELoumORvGIif8Z8b5h2Sxvg+S14gD h/EJrpvjhn6XA9dHhhA8OC7ooanS+CPept+aCo3rKgiGelX2VHKcnFmSVIpmUUzcu9qPd7T/1DeJ I4WhzxMeWg/6GjzEQ4TK0sIkgscWzY8ipyEfapueN11ABc/Fz2CgfTjXBIqEDFqH2gwDlih6fvsv u9UTIX4oJ0MSlDdniYuPFBfx/bnoSo00DS6JrK0dQgcuV7eJFQjzr4U77ZUSfdc2b1mpnkFEoxkk H+OBbbD2C6oQj/17OWxmJ79ohahKNknQJYK/If6Oc8K2vcIY++WFV+tz0VISxlvPV2aZIU/yDIUO Q96Vw3h8gYdICDkbNi6S63DS3iKXHQbMdlNUHAt6eluSWVYNY24JQNGdIWoC/GT1DMf3Z74CpqGk a/BFTXWhpBEzj/UAyS/s3+KrcxBDNDq/s0U5wVhgggV1lQvNNQUrQ/X9XAwF9YSelH96u6ED7uKf bU/xbdAmRG3L8VB+f4e2rrLUwYgPINI7Upw0lxPHczrAf4TjyNa9/wW0CF1VeVY7MTI5idxYcs2I e7mbSo9KENdzDU/eXvEWbyOGH3aZg2PL7rEi+9/W3eoQJr/xHY2vlWfAXCh1Pj2fuitICm1eDS53 Im+ZEECQVZywEHCR2E5UM1wc06F1WkxzbrOrHjHmk7ZoKxDY7rV18v+AM1JUASzUXtoAeS1S40P5 o/L6Z2SJUFrfsaClLEE5iI0q8f9xW3qPFJY6gd2r+o6pxsewD7MtKwMITG9lChADFvbszwR7N+dT kBiwAC0H458j4iw59+4qY0QD7HeeqPamt8ih47VdarXnrz2KCNzVuhVu66aU+9urY42BNN1vSEGB iGmA5laFT6ZoIzTkxnXtEVMRmkW3DF6pLKH1wZ+5DAGJMhbMYf0vgsaL7w+5moidqDi0AqSWLW6+ s6/fV79t6loFghTUQZfpI69zlAbeBD7RJbfXwVJ8S/jGGZXOCTmKbZMFwxJJhfITLskGXEVLgnST A1v9ei8pc/usB5MLqrg4BRhjSbMaBth7igkvG+qIJLncu6ON8DmQqtgfrjpB6pr1Mwkggj527QKo /USEMEV3IL0nYGwOH6PLNuupc+VQBXL621Zfc9wC6E4d9DSZhiwFaguxVt/d8tP46PbArGUMdIMM Upo+m5TODeojsK48NPqmtQeYToSZSOEOkCvrpGFOWB1pbgWC61adl6fwxNbGxRdalUe4I34LXfme PC2/Y6/Dss+XAuRczroauW5kHcUIljStVKyCm3pCFXsMrbWDciQfCcbC6b38K826MMTn3K5ddOc6 P0OPokS/KJNo+/PbcHkcelnaC9Gv8XCU/31BS4SZ5cvgmmgjaZIF5lN5C1Z0SEvBnZfly5mddzHL 40C809wvRSNC8at6jruzMCPbXT4/4if/a83mNU8bBmgMmqEdj0RCkJyS3Makmq720Ejq6Q6NB7ri 5ePvgzEB8zwZ131OQYBRUD1VlFMZ0RCzw29fI6p2O1XRA9vLIYfYe2LC8LAg3EU6OHEJA1+JLwwu LmysBtfhFoXXA4n5Xqw9adYLXCDaBsQL87VKi6zchZDReEOGrBbNOoEiMJaIIERPJpbBM2Xab/Jq tYJsDIHymsfJOtg5O1gvj6gBa+efjRAYbZkW+f2nzdjNSacpQ8JB41whsvjyTvJ9fTAmLOHS94Qe UErzCSH3I8uxh5A16Bp2cTaBvF6gOj4cdzIFV9d1QVWVITByAajha5UFQVbByru4LpqT58HVPFT7 CXzIRzEYTODT2vy781Hw+ydEzg9lfvBqbavTZHmRwfQmxXXAuC68gzLfNHlYs5aLYiwtoeTUHd4+ 5YjjAP58Z+MDsmM2gD1Msda+YJ3FNk144y1Fb9DElRX8+cOiiVWZtVsNyuWL0ZqPZam5JsKTSUOi PEZ9SQxGMnGUzTUs7SB6TAxxT51UgTSgfHtn2bRQZQZx0/hpYcQNQMQc7oL4jokyEBhJv1L6YndW YwZDVCvbJ2OVmDvZZ9E7nDOjgGSJezPMG48OcctMr0VTaY5PgDjQHmnxHv1nDz7mrrtQrQkfjWLQ 0FH2pebXpUqXWc6BQtX5xbBDPLgmHHn7XUG9dOivoX3Ds7EwXv689QJNDbsBvtxWcbtjY8CWvBd5 rRUpZ8exum8czSHjIgLYsDj+95yG7/x2tAmHHUfASk3FoYGiEKuXOuj7HFAwbPbzaxRLrx8IMtjE 468dNlMPB8nlls+2S4RLhK1ojYUo9+es4RYQmah+IYVXi++KVGE2YzMyfp6PrCHgVAfY/JGV1K7v cmYxhAvm/6MxT4eOxUVXVij9wUf1B81IJPlfDUBVlQ2jrlCK1vgq58USwOFc3Gu0j5vMYRAL63on EK9ecOlI881p+Jsbr/KO8DiynnSfxexVfsonppnNnxQu5L/UcawYbnY/IsvvhMuqroW5ueHWGxQR G5kpuOaWQJC4GOr3LKxFJ0NSMfLcAD2A+UFCjhK9rxxK5SNiEusGiRx557qFRS1yg9Lzrrsqlge0 gUR9N2bqxF7iSjPz9+7y/ps+HW/tNct8Sqg5wY5J9jFteoDGhRvTCCRX7vhgC8wousbAs8gkf0yT OJzy61p7K0lU6vko0rNjSwUOCzqqU0CO4V/DCJ8wr075mfYMiHTm8kaBgxycBnsgf6lc96vDy/cS QMq5BFZSpQWygOT8kRg3w3dhtlPn2kDR32kbFfsqSQohIXGBwHK/Z7ChRRPIX9HnlfvKSlobE0t+ TyV8wWWxfpTkkFPjGqvx94ZB0Tsigr5EFeMJeYNb7BCUuItUMhjCHt0udXIbtjjfdt/y7e3xKk0n 6DYSQtot//zikLfR0Qegvk5tJRYmiGmb+CjI9eeG/WiGgKU3iZPRQN/aJuaUPzDi3/rPEpo3sNN8 HzSu+AG1tUZqrgquiPv1S8+MUNaMKnihYDFCmen1JSebRtUCDjC1AeZxN/aT4CNgnIc4VLo1OzSw h7rj8EMNvl1W/6ZmNVN2xseXOltHlsApKQPC1w4M1cw8KU4RSPG0zlMtQ6TdggdGzfWiBi6pe45D ye4R25U6NdvpR+mTd+rykShnYztEnQqWLm9gFFBYola8o9fNx33+DGkEjHuuAcFUt2I79WumhJwA OzK/bRaT4hyflBWIRwFQEW+yBPD4vVid1s7mkaf4E94cTdlYuBpUnQy+JitFoLjE3J+gppw0PFRz yEeVrz+5GtSvDcIoILWIK+23A54l9PI0CihHBFBVw+Zu3OoV1ZZ1rZAlI3s1abSGPl++uZ22j066 9J9lrc5IIRnHTm5TwUWr5gX/K33bLOr6sVi8UDKEdIaGIwrGO18HD6cskfBnU5DD9I5Y9D1Z/lJF kdtLPxWKmvVd+bnH8xhbkSsEm3VNF4ES2CxAzN7QUnw0LGw/ENMPgaD5Kzfh+uEDQAR90qGc1/CW 3xHiQ3HFxV1wvOFCFFZl65lCgc5ipuIFzlELIkEu5oJhuOU19tbBy6PXIzmZ6LL3lbKuoy8wcwtu ssJHbaWgwpf8hQMmtr6Puwx2A8c7Zj/nZMjxxS5L2/+qJRV3CgN3lACTyqamftbrRkyI+WEZpIhR 2mUrQQKlDPFmt3yWZX+23tsAGMJH0H2DHHvmehMlfMZ2ln3m206bJBpdCgxxrI76zF61Sn9R5ydl zxJt7jaxGfA+g0Hqw7EMdILsklvCaYEJ9V6bcCr440yiCSm+0Wcl1+eBmuUHpS3FysHxT5g8loYw TUb6eGOtjv2V+Hz8BGxgfF7vgGWbEUseN8fIaloZ6iTfiKo8g88f9mAxy/eP/aFqSUnryE0Kn6sK nR8KlG0da7E+Jsqpcuz+QlKW+vgMdrRNK3GM5Tuy7T+Wc3rbSKJ397vNhMaiRVyQ3tmBryTa3ohz ny/w5Lgx6/2+v5bc2Z0qYhalB7ElDqrUKNLY1WL2afMwC2qNQZg2ixEaO4xZGnZQnH/Vrs/oQNOL ftcersW8oQ6FAFKydIY3F7t5r+o861rlt0Vo6GloKu1jmqz6FhW8ItWEUYPkr0dZNTplMFaGeLym gIhqfUeidkaw3Ec8ie47QcyuxxHd7m4O1BF9R3H0FI90zlxg54i2MrA5fumi67S1JKKXHkO91MIM iykj/ifbNhmDzytOuy2LyCFf4Wn9bnBY5zukO0bOEvdGfVRRald8jW0QX0kionjDyelYRqPMRiOS cBcEcMXPDNPlt2juw37vw3wmhGKvaHn8uUxR3/dLiGmYdBrZs5/InnaAJPswMcKORhAoFgvMHofg y3bhl2vJ0DWYZCQfefpWPMx+xOaNEdt5Mim9BMPK6BU0nYh50HrTisDVKxmLVGexRlv9XiQO7eEc TTEWixibqonPdcyieDTLIENO5AFYfexX9hsb+cYwvfLNRbR1zqPHLgjXY54/OBN06KNbzxHtp62b iQjID3wRxUle835GTJ++i/hHeIzAzXWfe+Sb3ZuGpw9CyDiXTOFB1NvarXBkxoIepAxZvqLgIlb7 vl8B5M/NDoN1r3gxPv9mUnSsKWLHIxxKDdVWZ03Jbsgrs6nS6SVgJWXNpYckgOpdZ+TuRGclltTq OkS6aDqD7fkqwxI84lCi117VhHjhwY6QokKLv/HBGmKrev6+IUuYk0ycHvfAqoPDLQqDYZHEJcoM tXiGW3zOwBSWki7jkQ4c0cjUO0+YMhyfc9zulv3i/vrszPRIFaX9QAO1qfkqxmJXczrkaljlB9+/ Y2q2pjenvokaJ54JQtz4COu6yAm6cq0/9FFZaG/rlCY1f5jMTy/zqu+HXYtvSMsIkqmoAiqcOs3N lxovY7oV93mVo+XHrwtkDl92BwguItDYam+sRTCduejSuccmhEqunfM7MwFEElqmfGfhBy0A/PpF kXabsTJ+5BEbGYwfGoFrDKOzgKI9TN2udkgmX6PciuugqdiQoz7NBgQe72jCVnEzVfE4jNlFs+eL BTzLBB5FN8SVfLjHVEXfQuRZ2i91jBOhtT/SeiKYdlXH536z4iPWPD5XqpDhEX9OdHSDsMsMiKvh veoWhiikJTeYWGoe0fJqS1sR/EaSWgUR2wo1h5pBxPu/io63FyBFQJzhrETyrvAXgDtyiw3QEVTu oNdNs28v9RERuU6nP3YL1S1ykw4OPbBMWpUJEwoMygtl2/HVYW5wmZyPhtqU1F7Qkll6HTd/OeyT UGBEZJtKFp2b6DRBVhYn3WB6tICd9vTpC89Gou8r0zV6weNel97HSQ9HkdDv9UXgKi7ZPRPhaLa9 Z4mz6LKotFURAn5ab9V1qygTnIscCCP/Uad//rkzuq8JQdLX5YLe3/9AMsBG4JjuCm+BUKv76Qj9 s3tVQZyShoYHjP80l0cix3bzkIpy6u+u33LrTUBrWZ9nCkmLc/DMu+qiIf4pV27eXfKQvWO4n7Pa XpkpXEY8So840oE/sLiaOUjLvSG8NxGC89gyS6XLTG9JMoZePeA50KUkgrkHG12ARhigQsfidrVZ djsfoC++mA48oUWw8qGRSG6wc9v5RRH84hoI7o+HrD/M8g03v2rXrhN906682Qu8svviCuf6S8wr Gvu+gMxlIQufZSbCB78LJARnyiINjOV+Ldp0qdJtVTCbpmy1tLhBjgi5LILIGEQziGqN0Atzru5v jhpaq73Xfg6n5ne2aY+ROGInWP57+cxi3PDCMMher+M+mj5EBDolNf4HZ440OuHKJqNyDTUxlHra E+TDbgTSq4zr4D1FCEUWIxliJkMDw02wzcVjLv5vx184ZvKs8/pGecPZ5e4dszDVtRW9NVNpH2zP DGwdltr0KO7OvF2762v6xEA2MTVT/nQEhsBoaN3l9JCOE+4vE8qM+5B73pMWyBqktdbj6F2liucD 5ghcDvC+j5egOFb7Hie/apw5k/BdVKbzLiaTEf5KCfr7ZNjkX5F8RTw8ATfp6xAIvY8szsRLTRZR mFqj+pOsQddyBEXdURRpPySUEhhxP/Q4UvupjZTWNdReoLl8teZuitrroDSmex605LnCuJ+6Ky9e rx3RzfnnkrTOVBaf5jjtBRakX0yDbYjYrjqNCSCaVgIpifou1osBYLs7ZijkwhFFXFFfoOLlws0g nUwrMzTqZqZb5jxBIdf3jEkqXhxQ44+zabGw7g0oPVPYgnIOzDg+51SK4THjr3IK3etLAmB7Ccpw 71vxOnBK43aCKHvQ66UCZZUTdqCWbTkcZBLWjfp2pwx4KZ3qHFaqkEL5hGMg9GBM6WNv9puglnxb MwlHi78lnoL9VPXlqEgrN6DTwG+WPUKcuQ58oy4WhC0xI0xxEaDgCQIEV2WcEkjGl7L85N0kVQ4y MUnGXmjYfy3Vg9VcjuWFbHPvkxE5tL/yyTkSnJkIBHtnd9bc/lYFFQ+jJ1ZpqAk65X5gV5PAsWH3 Ois23riGYSjNIgfYaeffF4ts9pXJzJzYAVZLE57tlemEAQEyi1RAVMK/cTchxGTzP7k64X0/O2a9 XyV2G8yZ/QtIb+eYJNASzgxKniOdPnr/Zt43Xx42Ypl0ZJJWVf/NwmHKruYb4VEcjAYg+fIzIjDK sBTXXhmnPtdMqyfPw5VcgkSKlmnVZcqY3EyeV7Ak4+iNI4rMFYcJwAcXzgw6+RSB8cuBe2MlOZRl d71cw1Elx6CR9gT9DtW91dP/OrD6IF7RpV605L0GSXCbMPgBvf9VI0+plt17ie8RWoO7IFel1ksy cwTw29kVq/vfAUjLftZw9G2KbiUuJI3myS/HczMA1A4b7N76KaVA2Xv/Kf7FAgcHyjyRzcze4ksn 4p+T3qwE/rjHfRcWGO3Wws762DfTE3hd9EqwnkxHIz7W2+wlX+T6x5ZppwVuFrYkD96tRfKib8pK vYZzb/z8T/C0WmWGZQBLbTGrWCgSCxLHLL7Zxg6MkKfk4nxhwFrVZVbCNz9r+OiIEid3BIPSHcLh y2QrzebkAYjRIxQlbMpEfSWtYNebcBJPub6Ujc+d7KBqqZamb4nuX9vDQKdmNhr3L+748SDU7HSs 1j/iY+sLiQ+sH2N5SBDfSEo2MfEjEBdCkUP3RJjTFK5GL2bAKkaflG5N5QEh2NX0lylxwhXbQKB0 W3DqB5Ly6nDhneDFB9JGCt6qbS9uHopNjtjgl6PHYqJOmkKUt1j241Adsdl5AYHK08Mo+86ba+p3 T1ZXhHOFnnIV1lGncP0KgK9e43OuiwohorKVTXxvxeOxHSHGsY3RjF/OPXEWFubKChzNGKJxDbNO EG3PCv9mcktqVzpwftcD657pt5G0u8fX+NjezMkyUEoVC6gdeF/XlOWm1Yn0hOSqiQrODVOOG3nO 1/GXeR2XvHf6YLAmJYaN1ptBYXL01diMUr2Z+30QATnY5pHmWfI2UD5mXxo/5PiNO34NlLZnhC6b wAP8bDuhROZXtODNHZ83f3o93KYQ/5p9ip5+Utaylqn7/1tnxugwWSr/Ej5jywPOid+PyAJ4GA1Z 1gogqQPJ9sI6CwDXjNE7qaKvvpNzhcIaYs+ghSiMM68vF4ZIOndbrS0FBReapk3tiGdgOzjLMkPu fXoCwuuy+LIsMSMSR6N+8iCxApszZH842js/Y+DFNl5n+/LiJoZV1jif61g7Y0CgEX+lfPyp5ymn /yV8ziQrOtJ4tr0yEG83OYuQgv0z14nN9+o3f61+nnJ+d6IWbUSxHyywM2LcTQN0sWQyf+wuXRLU nWrhk5XOUi7YIeACIBKqv7SF6FK81b25swA3bqs9rSrTD8+rQuTCpQYK5I1jCGTgoW6jsRh/GsMH PkS4fmfz7XdSjDP8RNnkBAVbZswChY65msMUzYRs7bN0i8Fc97GMp7oIDb4ZrWXsfIrsZhrNJWvd Jw59W9IsBxSbNH0o+KeYKkdRdT+SgngCtDQ1R1/vfNRmphiMIsK2GJnSs+bxiw0zirvxx47RiY71 5SK7QNdwSJOHHel+J2Y1X5HOwZllg8OVF6D8zs8X3hkwr71+N8ik7mCi4rycYhFZhFENGEPIpGec tvoMMv/eJEfjBD28r1jZ5p7fdAVcpGFxnVmfZGM70u4ieMd7etwPg5IU7+BaxR8mohiySB7YiybO iLK+UwrPNGHHf1hjhEqz83PsLRYRTypKtV2ePkhogsxyMOcaczPs6dFyXAV/N+cVUeoOspfKjLqC gJzkgUDAL0w26Re2Rdz2mc9I2NQQCWN+q79N7uUQhfSCKhfyNMAN3oAgmp+DTlqj1CtHoqVCqPc4 +hjnILOHVq13FiJMHUu399I8qo7XrD4agxACGNXFJMpasEJxjCZmUK7j6ZvCDFMhVXhuVC1ybI6b sfF0ROBS45YQQmZEbnApL2+nDNofD8gHp0uVVvhbF0NnAby4WsQwb3psUaAX6zibl95UN1OAqYEH HNuIm/nZEReleQmiu2kuo9HxW5A9iz6cfCg48FGntdk5G1+81sJDR04x9CDkYHftdCAvy5fBrC+X dhuLQeLR+dJ+ojod+Ukz2dTjscsTnynVUsxeslUKirkrc95Z6fm0cKqmpkhlqMRz9pWxffsQAOKN vZ5EuB8m+0eB2QHmIVyJfpVpHF8yJRsDBp3lgGBKQMwg6diO3NQ2pQDc2dsahHgky8ieQ1+aJ6Md BM95vKrNaAG8W8piPWJYiJPPp0AcnwRStLemivaAaaEwAs1p8/GzY2OCYRXKqVrRpDw9QYu137D1 uAw10+RLoiLN2wUwUJB9B7aGW6bN1NjmuY6uWIJr6CUWd6WQ6E5QHNcaCazVigjIFqmTOem41VMI SkI96MTa8F2dCIr6c0rzLDjANObO0i2PXWztQwv2QRMJ8CvndehfXqc5nD9GcDTZiMlA46ZMKxGA FOQfBDJzzu6zhq0ToUB02LTCTqltDbHE6BGOlZQjkLPj5vTPym76cipVXOQ+9V296FJTkc+MkYVN g4BFXOE+2ySTRG62ic1Ro7IRiOOpzopZvi3GjImGyAK+SZIaseKpy28vVdQa5QWzszjkoRswBcQK ZQWnM1pAoPkQ40trB7yN0JMkzS+62BfsMUY4EyP7j41bD++rvs2nkvpsOjbIgfKw0CwMUjTiFUMw rKR2ivugTe/qOjPiBjmTUaDrUWvZT+3eBn5q0l34tr8HR/7boIK34noos8OYV07UvV/tt4lkTZra SO8PViQgi78v+neH1rnzCmapDZlGJYBPRKDAiZoHNUFQooC2GTQmhnhkePS4+74W+80RECDzukJt t4SuGIpmgPj8zARgcvQIiTi9T+u2HCQli+GZsYLSqsM5ecFsTNj6fgiOdBiWCG9nJumXHA2Ekwf6 3qDV+ZD6jNSohCod1cX9Vzi0LAP7XPkGMjyOS4nKyHqJsS9JzUTTLyb4taT1h+YkWGdcLf3lCwBq ktPTcM8/gZLT67r3Mi9ez1Thpu4r5p0j8FT65iKLkjM9wx4dn22HM5cuxSXmMyPKMiBTko6lZ4sz +5fwfSQ7rDFZIH11AccmuIxr4XE1/Jw2A5uuMHMd79593DlqMR0lzOuahNT2w9fkWJ5//KeLt1Ir X7UHmrfaRdUKQRcmBKv0CkYWFNbcf5Wyka00NyYbjEleMoQfTPp1Dfy8h1K+l+rHgoD6U+VMC+Ku YVZSfezbLwz2kdcTtdGfbD5wM0HZ+emV1b4rpPePSe//lTMxp5SZFUCPhY+kFTCHSQTcIW1tU3vp UuYmBp+nAZwZ8RTO/uh6iTuSzDTo9xvZwacAy77EELTPdz7ns22jPzUrcp4aNd6i8d7p9ZMSBE+S L8UGZIRWqebQMpU4J5myfCEE0nUbOc9CSsfppi7OvcjYY1pgZJgIogaUB1R7ZWN+DtD0oe5UZPz9 +JECTwaentRCokn6xZ9BRZHfPlMWC9OLNxRuP5dW50ezv21+wlNhqLzcVOPpWmqJ76KGSEorVznI ENZL7kozG9r0NN61BDbnX3nXb994pnLRsHXa7uaKCmaQ/aU/9KC+i5+8+Rklm1DUo6b185Ew1y7s WP/Y1RWKvTxdoLYiaqKN4u+ho+rwgBBCDGi0gEmwUkfbICAOC52PjvPkZTe19weiyRk4+pVc84xt isdLezTkow7Dje/hPUxvncGrBnWslbXuGxgSLORBUjT5CYuOAfCxDQKrtbbhQbKYGbP9LOG9Qmqs Hzs+eTAlc5Aef9iV/B0SkRMu/0zY2mVD9TQSbT0/K+5o/7lf4ol580z7pVj/c0HeXTzX8LqbIpJN mArshNPSHhNlDNkhXxbY6BMp6hrShpbYs+0LgufYAGgYjL367i3jtmyymXwD7qBhDq4DqrJV1rP7 oFWVGtqDKq1ntMq7/oOhGa2LQ56TBNb+c0xWa2rp47gvV6QeauCkgIu++IdikTywjEuI+bakvXZ5 LphHkbmIt2NnYNpdcOrTiDGHI8ncQ006Q33CkvOJT2AmrWG5WkBkwz9p4+aiSNh223L8QELIxfja 8eydnApPOxeJ0ngmi6zuhp+yYvJAFc04XRODTMkf5rQzUl28mB5H1KUrPo5C0mvc5g0323Izyw2L zabf88vB8t12wG/Il+AXWrh7Q3kZQHLwvWP9nZOS9xK8Pje338i2cWO1D05bTK09G27trgJHRd/P b35QA0cUh5Fk0fdYxpecW+D5Sa5+MGVJSLr+xEx8c88826538aqwaRhrEU65T6k4MVHIckcuO23+ 8WP53gADQVMU8fkB0ALHB2oiLzRRG/MO0ocGeIOgbxeiFxDJAz6jZ5mBOYOxBCW5zgbBt17fAsEx PQxxDKDi12p9IXeAbVHRTteLVk6zH1adIkMYzq/VC7FTdhmfQRaNeORjrHf9Z0s6BlEsN/wEhHQf 69e5e+Ku+NznH+gft3d4wVutYRs9LtV7TqwN0/ZiAerwEDRnAofEKasg9wFUTtOsrkTZrkPu29Je zWG7MXNHRBXsaT6kF+sgevwqnjsklfQzTvBmP8AM8gHyhh20D5WDX6YUPNHhMGL6d9LYY4qHyVhT N95Xt6Wocqz0yhoiTC+MO9UKmvHk1hA4njyI9XwtUjzL8S39hfsYNT2zK9Dv6P259kmKGsFPTJiZ zsDpplNGRhWnabfg/8qaO1HpTpq7mDBk3831tC/sUzQt/pqsq4h2M6RDQUpIbVGCQYyptCe34j2V EAYqaAgrN7ddi4u1j0H/VXV6Ijk3BoGSqjyCmLEoJoskIXWLen+wSEem3Wis9UBeV/exKANejoHH NUZb+lfpB8DY7DSPOB//BGrL2OeMjIJzNXPl2QXcIkkVHUuVo06kWbfQZJZgFJe2afSdoPVrcxOr xP2cJVaCQ0m7ZYRS7lhLktyy8DiCXjOISQVvq/YpPy0hwYeuGDH6vtYRiHIMXKYNRwi5Z24d6JPh 9/Lv/cQbdiOCKuZGOFU9/i3vs6NuOfKkPSmjPU/TAcYbXU/IipeLffNoq9ynA8S+PQHSoT2Ca6ji fyO5dbD4E3m2rM+cipAyBxmKc+39IXXcB3QZ5emiFCZ6Qp/M8MDbMzv5s3jUbYl2aRkwG5rlYekH V6xE1fe+boswuTtxKfKe8MqhUBJksOe1U/NoAZ5eat2+wdTQ+b3psUgrqkJGKERzn3TbN5vwqMzR NiKszJ1Su/NN6TDosXYDuM1g28IJcD/JGo2w59tf6Wr1SBztZ0fDt5Ry+jC9pCmZkSqaSjYQAqwx SqmKjNqUbDa+sydQfEDQP0RXfUsOupBCKjWL9Ndf1qqUCJazcw/wtfuwaGVIDYlMXl/uitsxPZMB ARlONaFvYLGUEbDaLokzZkw9zO7woUraEwI5cztNby49+hniqDEcaCjRxzte9yxnDlzcHfDeqqhY JYayCrgx9POuIV9KK6pH7cAKwdJPwfmqifmcboJYCISEQRTEDvjUbI3tC3Cp3jR2Gjb+X3r3i3AF GmjUQiEqfmjhFKbkV+5IEt3d6A+jmbrIaOzr7qSy0m+LPbVDeEfLTAObdI0fMgvRgJyIuRIgtTtS 4u4zvK8chpbXXa25dF3sOxcarXdI8nndY5tQjXmpkzzg0J4Irk/H7174B8SXm9FHRqfYGQIvzRxp eBk7cXwYuAU51fNt7/6+sHGUyDkfIS5eTGtbm7iSoCG8UbpIAzEbkJNpTSyoS9Biw67XE6C49qYq lXf3/WdajaRHjzt3vQ5PoAMZxItuli+P2bUw7bkBnuL9eXGnZxt3DHczKW2TMf71OZNXeJ+Zbuzk nvcOP1FEKXRB286h4n9UpZ//gUcX/O0kJqQ6ZQEjnPf8FWrtkRD0Ba4jnESbZLigopMjgDmD3WUI T49Hc5yoJqVVsOVUce68EZQPBnqUz5YOMFIVgSzbVoGSsCSYvnzkyURF986Bxco6l8KCQNoeqUzM 3jVq8CEr8K+6uDVq1sH3bmOjpUoF1a7AMPX8NGYDVDSpajsHW9CQmG955p3BOaknZFRiYuuH0/x2 5Xf6ZeATODGkCYM/FUKKhsVmZQvZ91bKJk2CCeUjuyf/tSOD1YrVFcMt2AFiIU6whZ0TR31hKTK/ Nm7yBWJfq3XKQBVPKScbphmlsKrPLmp/T53XgMDL/BvDO1N/s8GNiz0Wrb+FrQdmNUlAkbcJzC5m AH/1ExlAd6k2xfr/M5lpwwuBJEIAgZyVdzW0+sKBdbLgACjgvBR2XYvsS7IoqlUrN08MFoyQnb+r cGVnepJtxCE81kSf0eCgH7aF2vEgZZ2MIdMr0JicxxmeUPH9/IAzYhn2bovqJtwJpL0yYIKEHlQu xybs5ddJPDxW3oqd3WpglNPEpSB2TF3ukmooOoO0NbIhGMo5zok4rGo9s4uvR28qZCh97xSdgo/B j5TK+Hwh09KM56gISW3J45qT4wRqNOuIOC5VqvtJKb0hS4LLvArIdYhIetIwBbnBBrb/CxyQmYom FDIV2rjBiL/R2cAd4oMnkly0ZaCXEIdkqd4uzZndgqmEPT/3oLdoxp3N5a1nx4KCO+wTx2zY/1Ct 85vZQrwQnqX0Q1SlJXWHkFahcflZQ8vpsCY8C9U4SIKg3yzPgAUr4IuZFPxLTfP575wLlJcrnlEM 0ZzsKWL9I+4je1yq/AIVLS4wIZipvYYYK1Oij7tC5Qejx3Pc9ezqyWhxW8yczuyhqWmJy8rBoE5Y RHNOCWtMNtw3inqodICMVMkpoyjpGecsXAucrWp2p0XLJtt+dtKHS13RnXtxXH5br96domU1qXxY +1Gaqvmzq8TQKiIo89mprgkDoW+4BD/5dpPmLZJHLTO6G4eG2LwjclYGLcNJ3y375EGlD2ve27gu BL7UdVPF3Qp++MOsfE2w8WJq5fzlQGef36f800Jd7hz77CtY2gHfuYIicSpQ7q9ujRCSwzY6UNUi Fq3GHF+omqV63bk9UAWciJdPReVXQJVevQdZkVaLkr13ofpaksKdmRv+CZaTk5DfbAcNTvRZxuf9 ZpbyCCv2GQPiG6/A9AhCnJKYhK3sBSfxvra0axVmV0VQwiJLCrLLlztJwi6Xz803z7fjyysuBv2o QTQOXNekeqiLkyaNzoIkXTOXSiZhFVlCFVxK6MddxRw0Sz6Cr4DfcD0/XNvdljx8uQpwC3eeyif0 oqeNYO3aEdG9UKtjEubBHPfXwQ+TS5iI72Y4VC4G/okuzlrgPlJeaEdxjSGdcps2DBdtgv7cl/jj Qenuxx3DtK1aVPqim9WFDHA0YvyEqX0Sv1mBNsEkNcRn8/4Va1kaB2wTDpTmGrFpHRlGDFin1naY fwzz81kL1En90F3kn7ujOBgS6ueoGdgW1R+3jsMomhux/dxu0ispyfV9tFvYjUx8UVXpDVRbZ1xi sfkuoJZNA5gIJd9fzbhnCG654PGA4M8aetIuiLxExhQQl8gbHUCa8/QibUmhYQ92UqP6QReG0uot TpNcSaQnvDTh6UKp+H4ooV2K5tObKNiVlzp14XLR/n6qLn1IaLORSAq6Xrna2TxwqDx1DxHkZpUS Z1G94Ml9l9CG80YsHnhr6AcIcyzUPSkoi9cokSB2Vu+LrDoW5CVtRnqHB5KN2Bb/YCYycar4z1sq pdBToR0o8/y6BN/49q93cfYzZ0mp0wRQOGwoRgO/yPsvcBCdqJ98dF4+4bzrql6htlzGKacpvuTm 695JvWVjlW6jTkZKKQXcS1rUDaJ1g8EKUbybhqaAiN3V+QKXc4UqmnOqJ1tv+/BqcGguLBIjqHTD jzyNhGsG5SqrDLDGV5kIFij0SZ7WO8chK29b0a+WqNwQ6lgWMM3WUgbj/HhqC0kvJRDpdenlh8w9 4+WqIljWzwCwkAEYdFDuKhCcyomxRQmssAKomy02Nw8VTahsM0OqdRzmcIGLEv//GHxrPHxDoQBJ Y/BVFLYecXFObiqNRHqPSJK6lDslGDmaVeDN8MTFYFZe+j9qZl3+GxJSWggEaNtFyPAYR8we56/x Ei2nfY+kaWo+9r823eaxiscIpG21dAmsEimNNZSX+t/L06eDAmD6HInfmN3LQ3Fz0bxyzukTFk3V F4n0X412UHycxCZIbEHQC4iQ2nAzmuCIR5bKf4cxMO50ZSONmyuvoFdRa0PtNgmKR5X9zOl6zntQ H/E9dpQ6izMJZejsQjgoOUitiLaAPBK4ceu1xVtJVWN10pn6XTaaD9q7CinF/Vbkolx2TGMlvrGZ 6HbxItzwXCPu/WOSCV8W0KV/C6E1FlgrQTw+Y4q78RHrs35ETZxHvISq7mjpD3hyvzl9o3xo2xS5 mA/LGTw8m4NMsjbxEaSiXc1mtMmVJ1NDpDvKBDfsSSPNviQKMPOWLCL4t/qftgF7VVj9GFbsIPkC Gu6xqQBwvN0zU9rZpOoCwp8cqLq01T7d4yduanDLX5FE77QVZHyFPKepvXFfuuKbdbaVGc1+JIRR kSUVuBlu3Qn9F28JnvJlk1+bFd/BZKVYMR4r79hgGQvwqW8R8+ZEWMjOECQPsxx0gSkB2kAzr00p HvdEUowEzQu6gp0akHcL9P9DznXJGY6Qz+vxynC6ztgA1FOcQ3A/kMazhLU3raCkVjyWj3lRMXTa Li9J4Crzo9KR4XLDfN9Q9xtsScDp4ixYmls6BhTq9xZy06u0nX5tT4aQjN7UXSz0s2fw6or8yBXk EDoK0AsTF+oar3Iif03UQtJxxmkVbydTmYvZBkRwa8s2i2KXVt/UoDevdb6LPLCW6M6NZeY7QNdv Xe14HB4hE+sNKuwE0uDzsbCoLkYJXy1l9dB7z1WW90KI+OAWipsHh7e0s4y2sTFfxFrV4fARJxd4 9qjTo0oraxKSIRxehI2ckthcxFYQWNnGNF30LOycOgrngT/Bsz5dfy6kRUJn2ZiBSqR8p8VYPD5k xvZ/2EiI+ISK5JO+MwP6vVK4lzAW59718/FGuLkeMqM/zwgTkN32BcegBi098yTVewL6tAg3AFbS KvxS5wamAAKmEqS1V3NS3LZ8XM/QE37ThLeo38zWPupbOogCy4kYW2rbE1heeWjfQTbcEcdI/+P3 0OSeEJcQVTl5JwkMn1qapp6tU+gUqgJUKmeBhTlOsQCkqACaLl3+r92ekrCXzzqzaif83X5yZ0iM FenKCKshrdQlBj2iZ6om2/gMV3VLtqOFEsWwtnOOASC2l/h2Q1m8K/qYCvKGeGsuCnbS8J81TcPC bwGjKG7veGGGMWpvMpPmCfHJfocSU6LZfdqB+BQQMSiKIabMrYFfpULgIGKkAdr15tcGftl4m5AS 8sqsF0EaSgiGg0KuIreFV8akdGMPqsrIhuIJEXXvav9rJvcLdKxrfrkOeybpMISMNWjnVwFIi31/ 0YAu9VBCsscSb2h0Q2jjsiPnlssWYk/RGciilxpSFEdqmxLC8ojVDJiCOn+1QMnLD7A8BXiUKjZ6 9TXEyOGKnjrEHVwHCTMstl9iX5EQqiDVWkXXo8QkhFNWCuU7TdAnSb8PzLO8Nam0vc6Uc1F7kNKR Qipp7ynL6TQqEJyKszv3GEJbI8eudiqxKKIcv+aSSUTKQi68ihV6zWCHq7nUMxD6ACtD2NYBdHBF 81vViLQO7v34UzuSrqYnLGaakAHSh+aTiaVMXWYFE8cmhmFkSS72RKodivYkCt3DLq2asS6ArA2U jxUrZXthGpRbgiD878DQZyIxiEyEiC/AcO05FMhUz8LvmLkioQJIPyQL9Fh0r4zZYNc5J5rV1KwF Dh4fXPxtVe5VuM49qlYjlMvznXf+UGakIehtkwuMoruwwRxZ0gqZqSvswnnpYI+TU1uQShhWyKAQ mLXP3NReod2gnZDGo/MOuIQYLXxGECm1sMmyYLTcDZ2NFWrhnHOljOHtKFpQpSCKyZg3Lpif9DPg fh23L3s9/Tx5F73zl3vywxOzq9eRRAe0B1YpQ3t6PUOw5Z/rX5Odae8kV6puMzupXV+ao29/AyQA JdvvmiqRlCdzq2ytlXkXzKsay3qCL5xFoH+foNr3V8e565SmLgjkyS1nJEitnR0NENrZj4bApxSJ DkCKMS5iJ1P/cdgc+/s/2lbYH6HLwOiu3W/ND1HAXeNBlMwxcvKUS+oAZiscYjmvmVG+RJhNY8Pb mOb6Linfjl5/MTJteUWXsdxEmwFcm/a8MDbMj4tOXHVLq+LxAzh11z67+7QUys75lxVkrhaxmaFm rYfkTQb+0VWHkQzNuz79ZhTIhIHsGinBzIPuHMTzOaRGaCr0d5Uv2VHIAzK7oV4S6ZuzMFDQ7dAo J9kvuJPEuTDviC+BhHjkMzvkDdRPuF1iHNTdcEic3MAsJIgzMQ5dYo1sIEN/p29mHPFiUlz5tx8R 7GetfyMvJK9vG42BNIdQw1Hu8e75yV77sgvISGuW0zBV7Rl868bSr0wZVbNiaRKbvwMSP2hcMUO6 nFVjPeYgIMeCveaejNfVjA18CWUMfoLhXYD1Y6Ceyc7xsoHCDkT3XhPSkUmTBNqYzo5U4bHi/X46 jEgY9XMD+maQgOh5VpB0l1RLK7BiZvZL0ndT2ndzk2uSrHx45Lz1c34fuMu8lmGDI3YTEC2pX0aX FfA40iwg1JJvs+EDfdtHM4RuEu+BGn/CbD+RE3gqlI8AjzaOp5GqBfV85vu5qjkayi3DbgvhiJAp J5aEa4/qqNdQxSeivie4TFJWbt3wa6Us/YUbbKQgGjfSwG3DaJXxWtkeVa4cjKzjIkow1lSqE6M0 awoZ5ZiK4Pvd3PwEhWJCz7TvjGh75uY/piVoVFaRFEOfeTGO7hBdSkJ0hqNXLdd0xvv3QqpDLXXg EZlyY6D7IHI4bbs70D3nKw1jjD4l53xvtTH22WywDMahLVthj/bOxRvVVBSLPQge+W2bVFvhKz8m NRMEDk+2V7jzdmbtyfb40m8ZwC2a42NnixKSkKXExIXf5bWS/URhbtBD6IgmV1ANYbDDjUiABr/e IiWEnsJkjlyYWIijLvy8+yVJTdpGHsUG6rN8IOQfZ4/nAD58IsNnjJ6/4zg/eSE4Un5MH1wJNWGJ BliXXBIp/Y4VBaTG78pu6hg9h3827XuUTv8hrDkIX7f9bA0/sddm7p693OIstu5djyCUEnCk5wYJ JGL5ha3t3ypXN9jdfK1SdMSvYt6HPA002hsJa38JX/H66LT3GVvx4QTDJ3jQHKtsySS9xciEsxGs GZY87xiJdOnUoXjYYGEs1+W4lS+pfyLdEUsYlG/dkEbYoGnSGGcKU1Gz7dfAYIHT65jhYWjZ21pg ZpLxd83YsAbPXv7SNgnePfdKcLsnbJS14iCuXKOHlpJMwgUa4/wXa420LJtNLtthCIAvbav/h3MG pbPbTC5fXYsEobVB60cLCq7e2ZAJ+8D4m/MESrPLW2uWbhNv3m7G4Qb7IiHXwIjZTI4LCNZLJygT JgI4xw7frZHLnuMf4Se7REoRD9HuGCu+71U9NmlxYC+Nbact/93Ok2rJgFnH5jUk+tcaFGAa3opR 8s+6p9Wn8ArVktUmhyyjUMI6gA6MxbYb2U0dD1kenLfE4ei7+s6uSRHrHnYIE6rFsv1ZfZ2yUGBE a3s2/JIukv7ChmCp7EKLNZKq4dJ8mgQgcLUf6wgNNQlrc+F5uKhrunSSDwCs/+D65yj7qFlcxwYk fqxc77jKU6AJxguxQk6cTC/XF+4knXVZBOG3uLFLxjK882SRx0M09YenqjIznKik15FdKvWz8Eet cj/o4Li6qXEHoDpQ+HgkB0/BZsdgRlu3ARZwRlwGWj8f//WjYa8hR8E/MzQnfbYLTHzS8cwSMGqq 7P6qKhEqq6U/mVAiwnsrGduWb3mEK/tPKSV6QBY6bmu5qdIW9WQVZ0yD1T5A5EIDn2Ze2dw4aWyg pzP7cntP8UXpz3rVKzWG1SxwjRqiLYOq7eeHu3UYNgZdmfE3uUCIYOogw2GoCayOfHOr//W7zYF+ Du8slAUCO6amybibxhaLD+WVVxk07pXvLVlDr7eROyqRmQN6QMdzs78Nb/khkjmGDo2z1O23MNzg 1ia7shQ0S6gCGdJVO/6n+R7ASJkQ6QjFz+3EXghuYsj7LofLa2KEWPVmottOcOFBQ+HMDhFT5BJg yay7wQVo1FWdKXzIoHjL1INXU0BLxvtWXB/8+Ax4EO721GHcZ5sisSWZ11ljHCtdXSFk6wTexKPE ZNwXH0BQIJ0HApO+0DOnR0YEdAzy9whQb1En42NCmyziM5n0OIqRtJ4ZrmSe4pFeCElMEeUZLbyw eN55kL4Rj6TMcVRHe5OsYbM8po22uLYh4HtWT+AurSYUZh6oS0PaxhguV9vK9fx4CEqRDIMEe8ML nuUs0t+VWe4qwb/ldDldS6gFZJVMTwpzGLHfDsKrFdGLUNR+uVboC+a39Tu2weLlfh779jZ1LyuH XOGhEaTFhwhVxhIzcLMY8PZMq2ZHDuLnzWJ+ojB5Mp61Vtce+apXp+j5U7EUOOJl1A9xdpX9yyXz zbRb78IInwCJGns50rqSOHKR6HybvhfJAKkD+0mOz4BG9Izi5EHpYzM8Z4prI00UHls6D+8e671K /7Vk/AH5xVUy9u5Tlp74nTOXW41JlKMQOTxxhw2bBysZE3/im6wzjzqfCqY/47p1ft7Eg7pCAMJy rU3Xp6xdjCmMScKFIaeHf+Fx1paS/C3g3hrX9jxkF8Hkh3CnO3S+RX/nKc71rWHMp9/vvMhnIK36 K2uFAUEC/Gt8FMLFmpEv1Loo6fKv6JBsfGViotFuRqlijb16JkzH5U+REyjVXBMUry7M+AJyD8qz 6/gZ7zKJEzNlOM3xTFjb3/WDcB1XlRPKPup87GAqcF6FmR5iORFmqmByoQZ2xjCjVmdZlsBAjp62 YN9ysJtp5Wzp8FtQGEAmvGfhyQ6hkHk7ZO8yEFDAs9SFzDOFZ/XU2DEaPlXEQMKKAbH9zVyxljj4 gz3d4VwwBmufrn2ib/IHW3w6HtbtyXRTp/R1tnzt80TRm3hUuaC1XJFZsB/QMLgBimEWr/OgReJt NEl/6a2ecGLO6Mtu2VkppnphwwjE8UTz8XIWh4YXLZ98hJeMyvUJDigCThM/b+4hn6GL+fzjNLPy 7iQJ7kgDYNC6nX9wFfPEJSB9VTfTxiw7E4YEshG+Ra7QRXQ8bcFz/uWBl65ZY+Cf602Oxif3xO6S dWhZ1rSEEfBz3N8Bqm4rXPVg4SNzj6HnSSPfYGOmeC7bDWQhJSecexKSmzTSyf6uKV6pXwwrRwBA M7J02k0Uj7KmH+QOROEwfxFFz0ubQdw/NiS5KBatib4bGE0uHfXwEJUIilvLeqKn/VEQ/eTKXWo/ EQs40a8z9vsmgFLyr4C4lKz2ZPQHEZcsXfdV0/t65xhTLhtsrKdpoFGgLZaIlFpegTd/QyVm/Lwj 9jZIiqIjOoyQabnCQS1Ci7mqC9RzGUsa7GcOrSWorpv4oLU122Zt7RtiD9iVUklnsJXgfi1XCWob dF3+73IAr5mgUlgciQEQjM/3FYXhAFUbpVgdZtWSRTc3Y2hI/mcVVBXVywJ63VUsD/+Fda7MPnzi rjFHTxQS/iVSAccWmDui8KK7hy6o9rap60Y6VI834T2atjI7r2sA2RE+uFjzY5diNN2JRcQslary z3gCTfgE+Kd09u8QPZs5CpP6ZoluRsjztna8/iNOAFeMWZ4uCS+XJA/0SMtrv3ZgZKygLB1jTlE4 CSsOTuLfevldDvz3JXyDqfTZb1jafgd+DeIpEvYdszrE8Z0J/GQI+JAv0chjJzzKtTDV/3lCoz0g UGodf95xbqYYudc2DwzXtqZRfjh821k3M3BYDnGSrtIfIHlVToVi5EXR6QmJwOtHQqAVZ3KSU1l6 WLfhXtYGxSxsfHiBCAWYlaJJ5RFFEg6JpDbHjUShExx38NNWbXN+dRa7Emwc4BydmGIpJQ0rYN7s 9G4kDpuXO/hnDEzm8M6rxVo1oZg7RN7PgC43AEo/NJLib48+lvQlyQiOLxZ7h24tUpT6Hrw8mmDS vOO7RwGK7SVKHjmGa6xAi7uZfcM/Vkee1/NUBa4e1TssfZ4Zi+Vkrgbt6zOm9QlikuEBA5uCTtaf PBgXPcqvzZIPviOVr91GpU+Zzer9EgQ8eRvowbFRz/Am7FrO23xNhMUoUzVPDuLeTHyXOeRliLpB puq5wyazLhm80Qf3kdD8921XEvvBmpPlZlPfE87zz+3raGTq474G10S+dl7K2YRsc0kHZNeJmZnL t7T35B53nxk31wYeDZQz04P2nrQHpSKSzT5Tl3cl381Lgdbl5cEDABT9PVUvjgyMgETsOsHY86H8 gneL+YrzNZg+xlEApheVLn1mYHBMJJmqlBo3voFpLYD6ylcD1igKYrVoHQZmvEHLXFi++TNnTbRx 4Ke9gXdxzXVHa2/7gjhTlozh2Lj5M0Agj1YVS5rBfvdOplVMbBOIlyqH7+knAL9fM8n3VPQf+iBK 7o4/h5Z2E4sfsGFeGYIjygTZoNaO0Or2q3DZVeTQLblizr9nMpF6qR+XW4Byl/lgnw+TZh9sS514 W7lyaIJda9lgL4ay/8n8NNbMAvGxLW60+WaYmcXklgh0+OcJ9vltwME8rAhhLBQ23thI8G6rpIf3 sIMUTUzmdOi/fmm7Zz0il7kt2C9c82nfY9rypyDGORmZE7gvEfdhtkLx1Zle4T0A6+w6ViJXxurW sZi3GnP0sQeMpnWVNXVxMOJuDReCCkREMdJhGT9nIUeHQ0Lgyoo1HdkvYL022te+aFThjWg9SdX2 MWBPfR8V3xXWMZTzJawal5K4CnGDUDiYPHgt1PTe4lDcgm9Lh1Vp72qxdCFRG3gfGOOpRdBVNEYQ ijBIIvYZxnnnVQeX+gNfalV5QlxCnYrgST7N5GbrSysFDduUMPPXHAIuSFus8+P95YikVOnmfJyi ycRGNt6/ANovR+lPXcgOTGLQF80QBQXly9GqMqrLV5ruOfPAap5nsFtpVMsKsZcygqF3RumxFPkh gcarQqdv9+GRFh53qpMByLX6tK8qbwjyYfHy3ypED0NY919exwMm1CGbsSzlVRfrJB20bKuW1gHc Q2gn33JvVv0X/tzJfLNVAPdm2ZEQFxhL1IGe/vPEdqDnOv8A/28ggvwIsglPyT+1tZLU4Xwj9+PB Z5z97csLV7tmoG5pDVn9YYrhC4TpY4biwJVEwBbaFmM7OalW1acrSigYCezbyUsmw95WRLBNPGFi b/rXn5JivF3kKJXSCE0+ihkjwsUqnj5+sypgwrYhFVUezxJsFUU4jEwsEQAUU+LJjJp9mh6/iZvK IDmAyvPyGieZZ6j3+dKMizV2MnwjqBzM7OVb0l83RxCFb/uhGqBj6YlhkaxO4hwZZphrEty/JRBk mHTfWa6a65nISpAEBh8oiPdxJK2TKm32vPzks+QTh7Ni9XnrUUyzdu/C5rA3Oau0pd9b60aF8feh oUM8KlNvaxurf8DEAEZvj1lX/HYqOgl1YKb1P9h67p6GE+oN65iPmSGvzife/BKBasbNbHa79alL y4zuC8HZmp37K4mbPTXpLWfser0Yw/qA47BmsEW0xc4XValgzOIxiFAjj2eaSxUOoWBzSq+tZpuy gsazqr2kZHNDWxZvh4ReT+mP1ul2h0BzIuivKnoBRk9MypIdGanX+Lf+ZdLhiK5ZO2AZIeykdg0B sa/6pjRBCDaOfLIcToiYiJktUfpiCslIe7RnNkEgD9GNirGBgeySKYxqU3eBJuYrUejOMtjzUzMb ftPKEIkwyjxntezm2JalccdXIMN5YBlUIuiRYDgxc9FmwYTqsW2Ps++KVt1pa1OT4lo//PBAdndu eZOHZ1AB9xbp6ksBA4EAxFybLD5c6R5R3LPEXUcMNWXwUqUqtThiNWZ/Y+HIiSsxsaIuex6oxhlI RP2ZdE7GB7Oyn1Cerh59EIkMrjDomk39Ii1MEx8gaMag6O+n/PFzYPVS3QEfKXjSVQ+14wRP5wbt eATSqKNaU5jvnOxCJAx4NgyfFT2JIW79qZrO8v9VbWB3us7Mhecqt9pRMsfcvMkEsSPWfnQTkOA0 tBeR1HVNr7lZqqsb2NopTsUdGROax1nV/FZCoLCwUOSgf31ieiBqEFxh5iQI7QRN+/JWsVbbLi7w ObfvQz2jTkFp679IaIUxOl6dm3KrLwiCQbfwDMxKIsVYo/YEOVg8Ta31Gmpp6Sz7CM17aEGPanm0 vro4+y1SlLsbQCx1u2/WVetTiffgnw2l7T12RLkQG+Z8LRCJiU1CH0xLcU8L98WLVErkvJz9Xk9B FBITg7MzVMiuy/9fE8zG15cKsjfR+4cajdDH/msw6vIVDJ6ksIEFzzEvJpHNWie0BP5EDxmanS26 wyrot5oDrgJ9YbJ4k2JGRvOxoXsomxq94MQiYCG4KNZb2rgTjJl1slpHFrfGp64zdhNSa/npu0i0 5OBFfrn4HoAifUCsZ3/6Tjv0osWRmAiq1AovTSBDJ0MhgPE3pm5HpnXVI6SonaYwtQv5fnfbkaKB Ed0bac6uGdVmZH3OWot8hKwGbKVh8ZgtQxM8E+Kru5UGfT2WZo6e+yXstKtEZJLqOJXLlsxkbkZx MYzF4R0TE/BizU6D3XmqowD+FjhpfQkoac1OHCedA9gaP+fRzzgAXWaYe+9w7axryQs2tMeNHiVd dpWjFiEUwL+bkJ0zChdGlAlKqW3Uf2EDpJu5VoJEoR5VQh0WuhICm4VfAn/YvaF3GDuYfX7pqJac 5Asu+Kehrp2DPFah0KYn+aImFaa6wwkHf0v3uPS0hkVV47wSGU3VFsGJhlA1yXt+IeLLUumUhtPj stSVGLNnC2V9f+Wbzfzs9M8Jshg2LslUr91bqzN8LndQSJ4CFMgqNCuPtjUh5qyRMy+SLkxcSZ1b RBh2rWev3EfQqN6WhzHg6JseXcmZQwb0v847+j6tx4F9p4jXkVpjVgOdPZkz4RLoTz0+CLlJXb3E 8Yjl7F4NT3MOIEDSeQb+hvGe5NsgKeeKGfYXTZzqGcqirqR6QeaMrENqMu7rOmy1617TdA3TQ2aU 0H+Je+QmPrPRio+J5qZJRLVNaEaScUipSvPrIqM5WUttUfZcS91F/U9pftE5jOAJtEoYWSZdFsoa /6MbG3CJAO/woJAsN4dc/KHqNk/G8bjax/ER3jlFhW7QwnC5ybPG8ZpXhpYCluKsxfTiB2u1GTXn OEs9r9UvVG6pQ3rm+lbd6ZbjpjB8/mHdFEyon4Fmj3A2Ww/+qWZ9U9ndwzEZKq85OtXsoeQhasuU ojmnAB1Ulp/Al1ohc3rc2LefSO92YgamPdObWdCcYHhe3JKgGmnOFhRliY9PcLROt+0AgOQdm1/r UvSinXw6gwkisymuG8Rn/tisCQ7HK4XZo9OKd8tiT42qJZNaRq2Zq9d+vj+SzGxIq0MuLRVpAS1m tSP3wGtfs5chacxrIm/qUdZr2U0sHXMpxN+s5pwkzmLbGDCg3d5GChASDyhfu8h0D0Qke8z31tqJ lTBFSAEU4yXplQAEWjvxtj+rqgLts3mPVe7G8rexAFxngH22hnkDYo7CwSfKI9zTFNmo5mfVZ1pb dv+uiR/VWUz4GoODiKFI6+WZAo940cnPxL1SsU3w7zYPiI3n55kARoLd77HNQ2wLqQR/s1jG/7jM 0ZX392YOcer5w2lqmMcVCF1OSpJHTjykviD9aZte/smN6I7PiaUD2WVGyUjZWqH7vbVNDsMF8xsG 6HDCEzLuhuuTmODGZL9mG75vkh+y+mItYSHcJNuCTX9HiGE3rO50ryBwCNSERKsZGmgIKFvkx9+t 0wrMAjdiJbj3qchfMY4nHotPHanF6sSBL9f1yN4f99EoajGpkLx7zFTVdmgkZ0m1ql3rCVdOZQYx Zc6VfEWArZrwv+5EhRceL6u5CBE4WgRErpXo+dSZ3yzBoAlJNwEgmi/fUA+VUO3ChlJncvaJQRmf oZ7+MsTqfFJufxmisgyDT1lMfjBaiSNkTiwgt+4Cq9/x1/mGMaa/WFONBNmm4RrzCNsr6sNezu7R 4hGjPdctYMGwJTIPmyEBEShmNaPWjjW5s9yfzS855GXAlh5Lbgc4PIT0it+IArBurBzXpjoSLpJE tAclPZg8JsQRCFgnowyrrgo9735kw8tzGQEu2kr1TPiZF5g6iMgOj7qkXHnd3oNxh4G4OWuTheXz IGHOBCoUyrJr74buYkD3ZNZY5EYk1TXlfjpoaoIaDoSoxmFzgVOctwO9SgygscuklGDSeciA4N3t IGCIW6RMaEvRp519/xCcVPSBd5NgvTjgAOiAa4l8RIukzMhipdW18bhTswmEgkzGOu5E5V5MvF2U U1RycQ6E1vgaudVY1Lbnj1I4qafS2a4upjBByhvbFAl9TH84oNZxypfQJ+v7cEC98p9AjAgolk7e LEcurhN9gUWi2XAS4rciGcD9qDw0LhL0YBQFT3IKFgb+MrJ8zUZtj27ipTkjI+wG031+l6qk6qEa Pt2+FHdTsQqpaSq9tgmhOIK+7HqGIR+0zgQh6VbakwCfs83HhgKmwWQeCeIqkN8K7Uz1JDVUV9fh 6Ppe1p+0L0Iq/YEvOY092T/p5ItE6CgAxX3y2Yev8rMeZE/efGXGChgkiEI0qJodcXSbLZm3AyEX odFNUkxFqIZd8hV0R0DZTt7dkDkgTSdAzjh5bZN7JnaMxI2XMqgCSUT1zjGjcHO4JCXHIgrdo1hU OWQO6e8f6sh9fUZrK4NaXDkEB7vRGMR9uUjCb/rgxrx3ofcQuTcA8Xe14CfGXy1q6wGQs1V/vjvg VeEZcqVeKba442orlZTrAwuflEM+saW65bzK/JbKzfvpLqpFO+T3Itq4swhcPUNjiagOiPhoKjo2 m9X3V/qrpeSRftO98f1TsfxDntJt8eWYtdra2o6yI8G+zvFLkqibpgV/3+VWHGobzmXatkCdf2Hj XkL7qCvyr7ptrW0iJrFUIs6YzhmDLxC/ukdSXzzJzGf5lbcs3iq0PjwOjBHxsYn+JX99zGV7gqt7 4Ox90PcD2Ge5I8UrglPMg69lSLsGSTAS0XbYwDKHPtqYv98/qKqo9KvZbfjLmHsWNOz3E6JV9LmC FC81noAVx6FJEShcAnQw9TM8YsSwTqW+9l90D8mOb+9nfGCPeQCSElkDzn2mzlJGJh9Hho2JBwkG Hcm8e9kcOEIvmQs//tPRBwykZQTOCS8N4LROVD4OikMyzQnX6ViEW1eaZrwWyFYNTWL/4t0gQvhc tRuP+qDLuSmS6IMqkY6bMdS/5HL9yHREmXUhPdqKYJBiQjpplVad7RVZ+pn9LD7ombupOfeRm4Ga 1rl6Uq/hH+wOE9vIlLpV6pAL68jsPbTln5AhyRWnvrzxUrE2pLX+Dx0UjaxpXhLhzj+CMZ7GUWTl I3PNXjpD/xXGudgDKpEERoZsS495iAkvnYeRqOyA+YumvJpqUGnMae72drevTYuLBRwbfWxbtrL9 6Mnk6IAvQ9Ud+bBmVwJ3OqJxWRpPXwjokvrEPlfQ6hJe5MIdGE7vJMZWAOdwxRmAf2NMFc8pnjxL YS0N71El60LcJAumZw0QFM1Q8m8QQ7+Rt9NmK9BT8XQ3TN7/aye+nPT5Xrat4i5rUwKHbENNBStc TDokAtzKDT07F8nOl2D31fsLewGsZ/Qgp9R+IfF3RJcHgOEZmIp0Hw9zE0ZFLczltJKVS6QuWLQs VzG0Vm4E5ov8A1432HeM5R9FZ2vcBX2cyf9OElN2DoPyy1M6L/Fc7Yilck2S+N2tGXF8D4+vPZ07 Br5FCoNGhZzN1CiKEjun1mhClXV0jQBWhOR/xBIbPp4BmXGrUuHI2+VRGD4gQi+60JSjijUos32A rpbeImiPjtiy4NY4wDPTfhzMdsJqKWOATHjmfMwD5C4G5fXlkupbqyheCSvH4nGA2iqEvJ0dBAcj 0J9yt/UXMCmT8cYhW3xaitCPRzRR/GrTm7PuTau7EndgWfujLZzGAxy2LaQZa4VtMzcww27+Ownb MwOpGqzhIyjnLUTZcQR2QJX2ew3whesXxp/AjA4KptkjuekcEJD4eBuaJaS4P8VsgU0lRYRjf3Hj D7DmGt1G3XVAhgRUAp68fDWH8REDASbVjlryvMSCOV2itl+UE21c665gSbWUhEGrBnjUnuccWXFB CQ1enwk86nS7f7zxGRSyVvYRMP7Yu21OCgMVg0H3tOtYGAb88zXlddN++Tllx893PfyWhkeIpc27 03IseprfR26XM20FdyUqxNyFDBTIdpTAd0r22DvQCHDYaDfkQtxLmpKy5SyPzzQ4Q1VLYNkM0qJn 1VDRZTANM0AIhovm18SUh7Z+eId1naRb1iZTC1yw8lpKpn+rK+iMnu7zD4UrZtjapO693/5N/TKr kNgbEsGB6v6uYXcv4IsJRkH7vJ7Y/4YuWZt6znETkyO0hAXjTe4t1prpa2V0jh0XspQKCJMtqpQx 8UNv6Zh//lp1mx4SKt8+bWME59PS7wPEbF+4GtmWPUkFgi25ea472XCRMA6XiC5z4/hvfb7H2TSg 5vUfXgkS4g66OBZZJex18QGonrGrictz6LR36PwmUsW7HL0dGCFTPpAmBDRGmOL64+Yc3fOgHgIT 9fskSr6x+5U3xlMrHNrmLw+/hJYnfpvivxATn5WQpHhOGxM9BWsSC4EGbrohJgd0o/UkSkYXChpW YZfbvA+mAU71GfZezv2RWNy0X/5LUTXhYpM+GYEX6ffDFvqdZZ+YdRsR+Vq4ipBup5kOOHxxZjLF 231hMA6BYsRt9qR9UASQ6a6rZWki2aMr6dtJtM8Fts5IWVK38iodMLsUi0Uhqww+WZYt/z+Ja9LF hgaT2QRQOyl4x+heHdKsZ9fMNjh+zgkN4gVNo0P142WMN8wPwV5xmBm43MN2NnNJAOyjYd4rQVGj iVzBXPKqnnRpkEBRPn/1N358CfVP7JyS2/tF3MhKPGCpos8/+3qWzA0bVR/ysMFkNAc+JiDlyGnN mT2ZC+4RgZHFE6p5jTHUKkNJBktfj1dCdN3pgzx5XEj1tr9MIw24aVUwCJjbeXiYS+pTx59OP+ag YIvLu4slLDgf5M0YKMbEB9CEB4KQ3YH0GepFEtOsE4T2PA2oaeNIHgbjyoRN/yu/d1tHZD0ZzBHo f4gkS2DLCfAafLK8KWPkuk6FfI3Wx7Ns0/u7B15bR2sweRQavkAwrxDdwCSsbgG5miIwsNFjTF0q q4f7L729sWY1MK0pcP1gvoaVk6J2A/hX22aIsoZGhDojFdtoXIu+m9oudF3ROSsnqnxh5nHJ41ov VUcDwbQ4WE8Gc+jTGQc504Bg/4r+ciIST4NUW3vVMQ0sDfeT2afA1b2JXLPTxHjmv0qfnCwvcWCk lFgfMcmFapY2n86xlQUkhpVUWpMQetQpkDDbi/oLRZZNvdiN8T+63KU0C9bMAm+lwUeD0C8ZfX4K Nkhs9POnz1X1yS8wTDUqHhJbt9pBLvwY+MxW+g6pzXuwNDMG9tDUGTOnxGvoEiMZ0VceWDdIDw8y 21Xm6imvqa/umd8fLnFQQkJ+yipbo3p3XPpnQqRv0X05aRV46Gwf0SIzQirAaCawvIpSFKNQfNgG LqFVIwOqOaqKZ4vzRqff+CTLdeQtbySlZ0DvSU+cBOXY2jIBS9JdSFJBLk/GfxYonJlBgkRtJ2k5 OP4e5fxSs1fHxN6pojDAOea3IXQRmlR+p3j7nGvpreM2he8M8W6i1KBesT82HjdHGR7nLE1Ins0u MQ7bR55q67OeRzCYzt2XZ9Jdl1+twzEmG/Aal5DrE0L1Jpmt0tfhPnAp4cDP5Ea5NjUTQK2IGP1n CWLl/roDvKbzBGzOntIEZqpRDh2eg8ERTOCXoupDAADiHNIQH6bJIoHGEn+BGRtMoTLOZyIUgaD2 3Rr3NKhR+JjqWhzSbBpOEhEHHN8uvhgmqIdWkbBpKckN6WZDtddTF/pWXNy/0aTwxE60Zfn3KwNV E2NiIKm/SyNjT82MQVTDlJCkQde4oYT0Tu8GlR2mziAYr3K3RPKHBxvqd81lzwY6KO1g3tR6yqcl dtPPMX2Fx2pYwBvxLiwNZRxJ3SI2viQIOBhAIoAHbKaMgz8DXFDSejiIt22altvElPE/ZZObnHff EviV/QZs5UPseRAGfpfjPdL+99xOYiM290hxbM5Knio7vHWB6mIJZsrcPMRc4nD9WoeYIqNn2u9b X08dI61X5dpsfL5cOXegufSf9XUTcQNNwXYXNMIOQgH0Izvebp39WQFL2k0pN42NkTwe6b9DUzK1 HUoKfQmSGIxhKjyRiVAeHnt6q8SUS8vF8YEFVb3QyIeXDPBNoZY2SiEVaePox7L2fnX5VIYshDWT DGmamj5fn9hwwGLER+bIxp8fiCZtwhVSX092iCQ/TSHPVD+ySE5xUdOBjfCWSL4Oum6ToaZrBiDT z51Wa283NTUP9LR3b18DsTiU9LOWHmLr6sW2l/CEVvysSiLOxhUn7PyxL5lmurRdNMtAVNCJ19Ze GVpCTHuiQnCJOcknOcZI88egsR4awD2TvlwBkcUs/YtWS25gWpIiksWtIKYYYx+BxEW8O7E9kP4N 09ZE7uHes2YV+qahAW+7QYv+qls5I56ZhTcUrw3zCvfuOqXPKnSpDLpZCjmpRbTXyvFIb3N2Kq8L qeCj88hbxdm96XDpnEF1oJohEMrmaOxkAq6BSn9DZHu13VnoCniusV+niZduZ2zyF3Yl7EIvHk+p vjVnXsQDiXsnIkIoKN93SsZEenyVFmTkKX+CnuGEuCpYjkYqn9a1mmuZEwTxVeVYZgyLbABjDVky ha/kduS8buHdnoTvYWNCsNPZH6BBYe2I+Dqf3HPxxN7Q7Mn8X4kcaGzOhSXHKJWqnmv6SW38xyIr 1hLmRSMkYx5qLHQ/X6vTOwgI4zDsbToy+YEnjvlOM5ZE7ckwQA+jweRxVNryTpY36JmdpiGrtDB+ ffFR4iHNxNcNEY21ZlLRM4vETEoFGYpyoJRYkcDXgocAYTA/iS53lyCdnrUumpFvo/yUvdEGECH/ tg7Gkcmnx/8UTG7IJjf8oDiCiQFcUGpj9dbkkC/WIeNLTkJE+S0VHs9kQ1R0B5pBlNIWqnP0M7BY RGYI62C+JwpIHowp5LrEDtnQZ9yg684+M8A4scg5nuOwy3u59L1hS+bDUptoooYr2h0KCetwyjH0 m8/WNY6r8HcjpD9u10+BG1tNXf+SDAG4A+lXgbcGdnJ8xGqAlQ7jGwur+4lhWfnJcI1uE5uDc5+X xmpzW5WDbDKb1GhQNnB07QPFpzdeNNd8zmbZpJkX/kviik/CNQlsZKDrGQsrvQmCnKmgha4w3V6J TkXllauP4lwoSDPqR35zQnE285k6ke/5qyEorR+6pK51iHRUN/c1LNEcwQTYuUQ83eIMwroL+zES xX3BfuaflWu+gLBHIi4I8y4OTazlogRVzMrCg49F5/jbKwHwPWiH7GELBANfNli3/ZSizIoNvM7+ YsJgod/aw7DduR2l9h/1sgEiYyylhbdOFGPvI7MMgvUGXXk/9Ln0XJ9AWo6TbdVoFeju/iHg2Eln hmoK7jeT5Rg9j6UAjP3kOZtF6CoMlcbA4CY9gCxS/PdmOfEgdf1Yddu7CR55dXmqgTKt0Bw+bQPv lhkWI90e9ndy46EuirLhxn4r7NaTUqOmn45LKan/K4LZ4GlFWdrvI2M3DrbtaK3YYiyTBRoJebf3 XikdqweuSh+ZCN/wrMZfH622eTSapEjfe85DHeQigHY5GSRTXdtFC7YeA1/ggxeWnmMOvDHoJYnW WRpwHnFORqBmA+zq7cG9WVrzjBZGMwFD7rZ1J9/Set+cyKmJmEFMNSs/QsQkK2F+uMQOK2Cy2yGQ Ae191wlE2V8ikdG7wbj7W/VyabYcgFVbQwjTpJtTtGeqsjasFBolMsBjI20MGClP46/vNjE172vY 7J0DhX18B29kVZbduHnICK3Q7COpkL44b7YgygF+aM++J6c0sjowovMlQhsJVYIGvCYKfV0eFTxZ 7W723uTtSzZ8LnYK3BNN5ajbLroAhm0LdpLtYKdT0T+8ovw6D6XCTSaSr98KVWyz75DtOzewn2OC YFGwx7PeYr7j76Ehxwf122rrrgLicT2loZssCADZEyZV8KTieQ40s8SccyXgg6P8BGjPeuWR4oji F5an+eb7F8ZFqfEU34ZMcKSjZjfM+uGQWdLd/bFqM86O9wQLlesMbSK1RnZakV5dqJcHDEBQa+MT dJ5wRpbz07yEgYCq7+D4AL1kujqhnzxNlgRlTN4fNyehDrxym8Y2OR+YC0rb9rkCFNXowrJ/06/8 GpPGN5NUrBR1SESCFn9R3FcSSELeYgw7Is4wmb9AEuZNI98AQtWglKOduY8SNIczR1PMDpa4tNIF psa7YT84tQkT3zFqsxRiR+a7NZvYq53krin2F9YwaCVgMaqeKAVVqeEaqX5RP30KEJce6KJvbHeR YHWH7Llkn06GQkPEv4KJ19C9FTYPFRPA8Mzukk2qVbM6bbGQ7+IeIoSLT9Dg4B7Mf21Kxjk404pJ cgCtB2p2JrSniYsjV5a9IP07d2UYe9dYXSZeS7C8rgc5A39u/JQkxhYJPsLqOMfBZ/uaiBf9DpGr Vu0i9xqXw74hKEm/M2Ey22CIdYOiMK52hr6tUPG8GeBI0dMC1gw887NckB2ihGSiOq0L0RwbtGGA mjcsBX77bcOM1QJJgiLs44VIc5Zy6qB+nWhuwnIyXebEPp50Cmtb8qZR9s9tHG3QtqOJm0yGtRHj g8XEFbBrFTfd3gQrHnEhE8UawQ0egEXGPxUxUwMdZtkKyGNOCwmtCwU9K7NaVUEuWygLqO9g/fTr S0xw2yDwPy3rmuMMmz8kVFzoBdVt23KUr/6vfcb1YPlZnWXgfdN+OcjsVahBozbVlLliwmS4Y0WU u2uRAvu8FOUQGf0UAZi7yU7iytFwDYIqgVlh/XRur+LFZBudXRnhFJIGa4kJpz2WXniW6rP1BG7D V7rr4O+pPgOKpztHn7eASVTiUq4hckBrGSwHCWN0P4j0kkmeCQs35yevkwAk+ji9N7OlnWFlJcre D7cnusQdcsFkTBqf8thMyXm0qiglrDC4GZNWvzS8mTPyhtK4GWVIHnIVuJ6KIGEKZNNBkYCi91Ri b9mudveQ44kV/GVYVH97wXCTtRCb0loQy6Gyg/rubFdJZ1IKk6VJAyA7BCefvrKYrLef/szyhuht KskDerbkYImWLg/8UW3GIr6WOND4AB/SkxranWorEWbNeMn3dHiYFD/VdZQ452/flbEPE0eg601P PYnqS+yCw2aK6svhou+VIj9AAx9HQdlii/Y0VhIVtN8IO7eIvzOHRVillc0uVjuPWxW0X9MvvD8I TJ8tZyN63XoHT/cSRHz+dslH0scSfU8B3MBoiLma/CsuQC9UIYGsIRt1zzOcYB9Igo/vK3DkyGwV 2bzqIG03CrXHAkubhgu5yvWlZ5HDUrG1adj7PN8rJB2vCzZQDlAp4HA+nEpjQmb5rdc/glwx72Vd rXPoVbyG1ivNBlysdiTvbvjVm464sWaNmOIwWWUjFkKgdw0Z0aPp58j6jiDngq1ISJAtUyt/uIfQ LEaTM9TvUxnrP36McG98i7KNQtBxjGrjdVgITVZKM5u5hhSRUFp03O3j3k0y96hm9py/Y5GnasOb ARJY08RjhF76iZN9LpbWmIb91H+cK+cajpxULsgrFUmRdaK8EV8eSE38wPUw44gXthBG6mm51TEC h7dmvCyM+iv7e9Pq3+2OMSgqVQOw7j8rcUFoLg9hYEyaivBPhD+BONFI2eOhLzo4f/wwecf/N0cC w2sZ7Pn86L7att96stt7PAKCL8kfuJ1SzCU5JrFGFnqgMpyXKy2dE85M361ZJ9nausn+uap6n8DK xlJIP10wZd/eiEEQDfuZIVLauAuvCJ7oVgFRg9eZPX0lAVIB37h9Jkj69p5zlMya/jxMjyjcJ1/m 0MCVidg4f7DbOdkjh+H8lwnC3U5HhReqeeZNqPex0iGEhfh0Lli0aSrl0QqyULAfnel4F3eH0Zsx oeyvgN+bHC6BeScQy5KK4H/tsafKA87unwGV9n4BBCr5Gn9le0rzwwiFisilf828KLYzGhFT/poi uS8GpOSEfQc8cPh6KScB2gWgvTKQoEF9sAuIC8Qe5YVdV2htWLbwDPFWuQCp66AdvgZs/ImhVs/p E/RKwGrC8kjjVc+LvRpI6IwDc2ZPQQM/LEoIJt2/p11dhWysTZpzQ/w1P8mfgvKQzdk/fjEwz4FU yxaEx8hVzuvJji12VSUUtyyQxqSK0QN1BziMO3tJ0eNnhb8H0qPVZPsQJMm3nXGvtamDSB0Pvefz nq4HehNE4N57HNjBK5raULn8jQWA9Ka7Pe86u+bCvXF8MPKUkvSpqnhe+QEJsBh/w5VeKMnoifRs txZCawqRuMalLIUYp+wpEVnfv0m0pbC11l82yGpsUQJhYAtTikbks1xTpGIJqzq5sXcjfC3wKT7z NQMZvC76CpWszS26/AZHkFvGLE6bn53eTq4Q7bwIXG4JQMDhDJRcOaROHIjT529h5C6giDOyOQ37 7Jp322ZMLvISVxcXk9eWWAAImCV18Chv+weBedJP9Q4CNDtmJVKg6YM+3szmEj6JRT76rY0OSPtg fCDbRPenmWZSEDVpxlpreF1WBG0dxnJaJc0aOZHlFlSEb4IGwOr8TVJ9D1a0nfUDRtD/58vppBo1 2ojy3SMu7ASoChLK5+NJi30HGVYxe+0XZQlbNxsTJe3ZPLFgbwyI/+yhQ3sEkK3U0fPT8sPHsXhZ d0XlbtjU6C9BVDuf0tywDG7mbfieW/an9H33Wkg6Q28KMcInzkC77U1pek3lHR7SN2lYiYEddyuu 02jKlmgo1ier09mITjBaQg0D70/Rh915JR5F+kCOXt91dEfHtj+i7jiCRgoJyAHX3n8OqSMGI8bQ 59djaj7ev2pOsq9SEYsKkfBWicqKDugXj1l2yhCaW1ir5d5S8sTKxWU+lkxxeX3UUJGEQH/r+7Pi /5lIjU5JH8lbWIrC5ADeFezwKKm9ZhKx5X7CNmuIa2uBTFV1uJ139jhIKhll+0jgSUd4c0kfFAcC 084FeIOKaWMI0tYwHLwTfOKQ4wiZZrKgmifu4xvDD0554v2rJnrqKrRqfRB2LGeYM2Ctami7fgpm E3zZKdz7mb12K+8bcr/XA/WXIrG9kd43PefAMOh4KD7TB7wyacac4QEimmt78E85vyaxvP3AXp0F 0gPUOFpGU8e33qcArmN9UsRtw49LBPWcnAmp0rSj4DG76qgETQb0Mm9rkgRWgRXUoPnfHRUaiP8C pgvXzyORw8EVAAdYvy9mfxyXboq+VPr6eq3nXJe0YYHSX72N7UIL66Bpb+bFgnVQok0/MR8lZ7b/ wzDplkB41gQ5DK9mvtpK6GLduR6rACUfFXIYxRwcaAhDhhMqTacO3h+ZtC6hEJNaOZ2AuyAnAUpm hbqKHcu3aNI2yEvzZUwYwnLWJvF/mwQvoq9/gNInjUjmHTY3/8wCEzloFSxFNGnJV04NUvjpuyt4 kUDhzUi4elOyUiIYifuXQ32zPdvTmX17+tQPMEq9pevhoEDPA3/RMzhqf1GNySKDvZ9wjZ2ODa5+ jQwHGnjP0XT/qWtF0jpWI9xlvbFdlKW4ESeg3HfN2YQOkO3iKVroGvqevRLC+qzQssBfuaHZftVB ZQx+k55BXc7Nc63z5YvGsFW1hPAWts5mHXa5mCAvgTrUesyU4hGtQs5p6BMr0hT3PGIbpHkVcCbH XsHYNF4tYBf5FFaM2d3lJ4h07KUmYRkig7qjItedhzj6mfhuzl4kcu3C64rN1RU+rbohG0+2dTMU T3h7eOHihZ/Ey/5pAUSOqEajNuDmF/lFiXLdxdvzPalDP6wWrlZLyOplapGPdIpFY6J1DAGL05w9 D5rmVmQCaa/o0VEwDACSzFPxDJlcUgQjgV/TatsGLIl+mFUMl8Bi88T2H4jDaPz4rL1gZqMUl8r1 2oLkuwarXqIL5/qEhP1FAZkVhQb4xiwU1ukcYourFDJn/Boo8A8mD+iYByrudw9+9MozRxGzczcH 6zqa5kFkmyMVFGA6m3Lapi6h6eyR7Oiu4fidUvtLF/rxPIXE03yJV89yrTqQUs4IvFiHDA8mNHlZ ON00v6syRf1ndn6dFZaTeGX0pkhkHTVowRzhfal07ijcqO9GqiMIPrwCANVe2F61yf1gj4ePI+9g p1nopi7Ai/tsCcHqkJpKJpwEgIglTjJ9Cvy42DdW/7wMOGmC7T4wmI4Qlc2RcuFBjuYUXZ9j19p9 o6t9kJEvvfszzkXFCE9H+/vYpmwqvi3jGPf4JuXF7oOtTqTcCwRtlY+/TWUGebqX1tLJpqUYsNA8 Rd+X8doFHsm+31mg8GbqegNNry+B6yW6NJK9J6BrjIXnGk3eJhj/Mn0V7R3+iNPc6rImhhJoZ+jt 6YfI984eL/1SYJ9jDk/FV8SfnKTO1/dfz+ujMXVp2gocFwWpXa/ZX0M8ptbpYrDen3dFxT37Y90p Rt+JoRx2ccVhuCfVx5OPpahFjlomyq10Qvy3xWYNGTT6YdG4u1ehxL2/Voj3vRCeGBfx8nrW942f Fx+5vRu5+xlUtTHP+Ny2BBNifi58AgnpT9WtQh/DWU4pIuEkOuAhAPx9aRn3A2XsV4w3tBydDIjF UHr70eTXk3+ZyVK6VQTorBhXdVrIkbNuW2yzHE33i3sdsBrasbEtuhmxi7UQWjEBOEOeppCuAymf ALSEIs0E7mb0mm1ke7co95NrtvLEhiw7kmpFVg4eOFDdkqpPep0Y9ye+JMypXQyqggNeZsSmMmFm tlRsW+bM1/XHwfZQUKu5JW7lXmRLzHmujAMJPAjy5Qur6x4R926jr2lhEwLV5ot2D5PFxmWmpBZe Wnzhx8T0iD4lsHW9ek9HxJNNj7rkv7QUlX/kW5nFSMOmNlJPq7fkUnQ20V0k2ElPtOhhheeGquQa Tdyhc7Bmgn2eTztv/gqe4STcdOD/NTmsIxQuV575+cwZo9v+XCegmxKcETCsVArGYTkkS7AjcdWi JzTC+BgmoG3exnSdKqyxnGWMcncfDyLVKNW6RvrpxuLHPuKgwS4htjFmQtvRoFq/ypP0syi5ixjp 9sWSSukOk6AcMsBvrZ5DTAVm1/ANPyTotE+TXpU7AHvDN/WPi9l4J4eZVDpCp9ZGyt9osQogJD+T 7yerj4TnoER/UQaFE5L2v2dS+DQOMkepQJhTmQ5AeWjJw38BuRLpuevPivDxaqwnzyoLhZquhgCN dfzVFepFZpuzh3EdXM+vl7J47c7kprvxTWxnYjtCp0Knb0fnF0ewoINhtRTWudLGhfZTEbgPt2nI s2TKd3WHyo42aPHD1ywA0z1dbjidppB0I2ZQw3Zt/roZ5Bim42GU8OVZJcrtyzGHNkRcxzUXfhTG OK4pqTkcGjJpowfIYvSxRHxyPN9fiJJ+8U9BI+aye5eDmNA7pC/G60+/rEh8yWdRRk3JfyQxXU9V hohqM7hYBOuxJ825hWdkHF6XVFiw3OkrgbRrOlfCwHQaHbkF7lvd8iHmiZZzCjR/nLouarhbfOyz Q8EABXRU85WB3JIyXlykgpXWBTutKrzroaPldJTTslMRiENbTNNhpNYZj/ZrPoTOvqXKnkWIgYHP 6YJ6gbWl6vQB9UuEPQ/Ft0iZKUH+QCOzS2IEnZEVAi72bByNBuXFLKVC6AKhs3r+huSiYaIJOn4h 3kP2U79Q/lYO5OIo1l2lbx5BGGhJyy+vzFSF6CHNJN4h+oCjFEoZCYI+YkkIhs4SLDaP/86CeZTi WeQeAnZqgyDRp+1Z9EYKmXTTTh3DI9FU/jH6QUgZWGSvTIptvRX4XZTsmKRlTN+GFNA1aigpzhR+ QNtrqvyCpsi4LqiBU3OcHlBzIX+uhuNnehZD5mD9KHAQyuW57VJ2346WA0xmmf1oQ+akyqCAAos2 1yWK3bubmcPaLLizYOeCOJ/UctbF/4UhH9N0nNOo0c5X7qo4ghwMdpRXOIgdtfFfhJJYGqykABDD nLnPkl6+st14RCq3/5XUBb2mbFOnbrzF9Pps3QHAK1ttylBU3UuDr6/IOBzYX1dYAK3uobtoY+n7 /z2ZWOGIMoovLfbLL7Wr46BU1TTf+qNYlZqUdoUe+AMaKVS0SX493ASQd2mSj3tbco641p78aPrJ jS0aQ6IsmD4fSZEp0FhqSA9W3JyiwNNZ24124krN7YTTtTTJEz2hC0jU4xoBCw2LYUNRMlUTDzTD oU0TXUH8whIrlJ9WRyL3sPKuxS3I3g/Ce9jrFjOi14AOIUGowuu5D0f76SqTKAx4ywBu8HepsHBa ineGYLf56S6VzAJ0Nu6vSrMuJxOr1GpdOivvOj4KOvjUvzyS1QpXyeT8jjF5mrL0vZav0NLdanKM nXnF2OG5TfiqGL9Lpu9JlT2fWhiLHXqO5rod35Yum9RjDVphLpPO9jCI+q4FiVDFxHasn4seQ+cR U/N4Mtn3LPenesYURVmiEXDkO20rnGvkkWof/puV0Vf82x5LXIow88s1qVx8Qf2c+6ro3Qh8ZFaz AMSmlckmR6N15xFRGg5Y2MO3IOpiSOM5D/eRd92E9oopk0TQ/gx1Kz6lVYzD8svem3plJcmghPNz UvHzUz3UVjr8fXJ2U4Lxn35Nc9xvwoEDtX9Q3ojnlyoG+IJzDuG38oRpjyJx+gtErRecDuVKwwOO ElhZqPZ6uCW8OOs9L+Lo7fX7nZJdgiZH38YPFnsQlDn2nRAJ7cQseqYDELXwoqVtCcuNkufG1fxt 73RnwKBew32gaiNgUzn9Jba7Ikl0qNJ3Ds7HrvP6nDSdGTAW7l79mj4w8q7+iX8W1X67kOLW/WcG 3lG6XLcIsJWD1M51BP4xkOH9MysvqQDEzL0LVlDIOeB0Zr0Z9YPVo3ErbIMDcVNHg1aZZz3mCw8j 1VsQDFGDCKCUfwHIe99RWcsnLvCtjMImGq9360qiKCRN0xtmcrLoM2He2n0U6XuoRLbnEdynekDo i4JEImdNqjv2xocsvPHCcFxYHV4kWjRwhNXd/UJ5U1fbUMX2hc6T9Jy5B1u1L3bTW0Xj63xSTzew ohQOu2UnIMbF6jZPdJ78REdQbrCZGi6VFq1M+h9C68psHdV1gzNjTkNKfa26nMVTrbBek4ncqbuH 9LsW2C1tCPdV24GakbRgMGpiaITEmok54ngkRIYRQDKtSkoxSuEisz5rbhbdIa2uisKWv2R8Ot8h C0OFbpBVBBzPGsL8q70MroUCsbU5ly37yf4QhTQZyBRKYiXQBM3pdlGW5jOBg5nJnmmWdKwPqIzm 0w1bpDG7ePijh9nY/MgBDX2R+th48m7V67qNSmuW6XIq2erPnCzeJkgypQyhz0+kuoFOD0YfZxqp MHgpQ/+DgvvTN14fY7MM11wHFUNHma85iBRyl8yZCKWI7M8iWXc8Uw3CutlvhEy6j8eDYiRHGgOY ER8/8WkiCNTW+Hbk4/bMjTpmu1GEEUPPEf9qbzEz2+oeztLxhqEEhQVjXMuErbibjUnInw30N2WD EUg/alQjtfW+Bsn/R2heDNewKQp6NZTLq8+Z6W8UcLiYpp86xXlRYibNEwQRXWEKjCdymj+SlQ30 iJVdQSBa43Gu8J2OG8ZAd9ZdwPfAXGO3IDIAAfs8pg/+FaVCKyZamnZN9dvhfEiPflbGoMO1m+dA BqopfXNHZmXDnF9gCUoTwODbnU1PXZAWzQGRWOxp2Q0M/4D5yhpZL7e2gVJyZYqBY1fiWAs/WKzr eb0e7gqHCJhsUzROtoawvKkBLbkycLnYcATik366Jn8SVbJODxhGeEnPx34AMRuzZJmAG5YOfit4 YQAJk2UUwh71xl8b52suvQWbDNbMG4Lpey/tIJyR6bPdBK3GxvTiA+j1QK0DVPDh7uTklcLLCA+i lClRgM7F4iwp4qHdCH8QKTOW5mkOYEVsBXyvJ92Q7In9FwREe7wa/F2/toqtGU7omzee2N0BxQOn w9/bdMT++vDUvZrbX/iPw0rEpTONMret2o9lpeByYt8+WWxbMhEnZUDEEl2448ZgMjMG5pJ+N0B1 1HVxnzhX2sOgzov2z/mF8F7pIPW1uWDWavTonNCDMST72uNhbRIIlPvjxyXGEJqYcwYxWRpfrZXl 7DSH5+Bg/K4I8JPVXNhevkDfB4ZCNjGRlVx2YrEYgZwsRNVC8LccW1E8BYaw8CbYArF/7KF+uO+Y bNB33WUhZh3LXKXFtmnkcPH0Jcjhk0ETmF0lZEZoEaA9S/9TCwQa8UOutre5E66pWUOqtE3R7MPy hEtMfLnnAgMrs66BpZOkp8JLE8Z3hgK53vAsvYfyCzqn9WZyBH0irXOE93RCWUhfjss1JOF4i92A 1XHNkvZQnOixCLocDDLVK6u3u6fphDaveESM2xAnhXlC8amP9dWYvOgu5b5ytRh7zw9yb+7BiP// A55tXjypDcX0+ZWMG9nIgBU+7E+weCqBBox9rcKYmqUlzBAj6LOghfWxN2PBHQp3kRKUh+7sjUML 5fG8GrQZqlOAaDdSXhTQKQVEFYirHdrD4eHYsp2J/xEJJs04oru5FaWP6PD/7p/RC9PgGQ9Pq1hF RJkLlPwtoSlJKrUGFPZDQbF3jMDzDApbU+KorGlNPd/qSbX5LnvDOzpxAYEAHbo4Yeu7Z83tgpYf Zfdlp1cp3H6zjTuZhgFYPNq0juJAN2n8y3kAvM1tLQxqgypv+Xa9Oiu7/c8oo/6vS5GAElxlJhRf ocBalxsss2v/wXtMjz21agIl+UjjzPweiXQExeHjsAWA89KNpPioplm0caj83b3LtArejS6cZldh y7t5fxVEGIKsDAXUx9UU/CrRZPR1UTdzth02UOKdkNrCWxsS48daywmncvBvunkFYkvnofMlb2fV vr+3qxBTw52tW3lbP04HpL8KTaaj6Dw89SzmXw9Uq1thOQqweZjd0b66JGkokmIvQ3nBSBzae3yS 2gEaduQtsmAnHu3arm2TAvO9bnuyzlAV2vfRPjiFznVjeUVO51LhT0H9oWdDSI7Jaavuy/OSO5a6 jME3NJFSbfq3uy4mrnJJVdOSv8FT97EDf2esT82nNqqwGl+UzUajGUmYJ78NiHktQ6eHop3qjH02 vEPTe0uqQxusHbVrDttdOgNemMh0vuhalo3O/jSK4nOn//w1qA22F5AYpj+tBPJKbMPtdFJHKpYy qCUQThtI8eVF3WuVmJBs9bIxZQqKV6uqN/PFAE3CAIWXhVNp7WxQx7swom6B+8hSklbdE+RI78LM L/Uk2aBNiJLXs5MqUUQuK3aD6/XMcib/6uV0vVx3KN9j8uo+Z3n8Jk53MBBS0vUb76IYmOr5DGK4 iBlXAhtBe6yJGbBfx1OiYbAvqfZOgWdVmLq9Yv8yJ0RnILF8ewuosFLG2JgqAJ6csKRVhApOFTd7 Xb47N9M2GiNi7mXkiueLRgAIF7xr3yvnvpHHxkcyL76GXTkhK0RjM6JhsPY/GKau93X9PrDQVdW7 X+09RHlep1g4j1RW1Q21Q96pynFMcRuGY2d39bvB6boICmBeeB3LPhdFihR7xZLDp1MlThyDOhx/ tlgrvpjB5bdv7BGI5AbNJ6bfd33VkNsRiXl6ayUg2skqjcoB3Gpk66EzYrYzeRcNY9h6AyyCKIwX Rkl/82GE1nhWPuSsgbK5Ju7VVJ21Qu/KCvOtAJuepErtQQXa930lRQzR5iRqx50uD4EXithwF4YA o1whfdQ8G2mcpmTFby7xTEAwYSRfQSNWoMs+eek51kbf/MYIP9ST+uPlI1ibq0P96oIM6nBtrPY5 D3seDncLq6nTZmLQ4i2jd15wpUGSjAAJjTYqwBVtpCkuZs2gm0VqeXAhKNi+0l3AQ8TalzfEl0Sd H0zCNeVxQ/3SmEgr2O/sXGLjG+oNVQpF4TjeouFjmTAQcklTdt8/DQsQnBov9i+jpRIYi7wbS5Mi Ruyv74FB8xfIrxod/qAOMLmiMcGqpUvwKKBX5cr4Ek+0lI3P58UAzqQbSs2vmN6xccV4i53C0SrO Hk9dLvmN3CvWTyWHj510mowIJuvW5yPb+mPjxlsHh6kRgPfcTK4a4xLbWd3ZjUc+ZJ1McHt+YMvr KEu8NKXXZItUBzKZkaO6tD+fzj/E1Iq6cZeav0hNXyg92ojz8pfYiLWp/J0+go2I5Fs97ZN0TxWu LIX/XEZZaUErqXiWj7LH4n7mrzm9GUzrHdAjmvWnlAIZHMjdAIL5rQpYhdeRmJAZOrpxWl1ClFhU sDYfwUuR90qp0B/OksmaTde06JYqzT0VnPifYBNmmsk/6b+D0WLD7h/CtV/JyxflRB/WTN/cBB82 2/TDTjET6CYuVhBLRpp+BZmO/GVbsGWcIzt7YCaWdPIqzJ8BmgawKcH5N7Xa90q76x9vqZ2zyqnY ErArTBNG+spUtPnQiN4h9UCVf2/5IhM/h58TgH/h8zOArd3uSKnBShQQ/RM/N5xjHGdQCmBeMVNS NgCf1r4YQwUcDswxqStcyoXwO/qdZw8hyl7kKBZy0+jBgOXJtB4lBaitL2DV/lun5a4WSm/aNcF0 9/okWUTrgpsPkBeziXeL/058j/IXUQVG1gSM8m/rZTBR/9+IY6qazKM17PIygMc6Md+Rl/tJdR4D lWEPOrkil6Xgj/1mg5ap0nUIuDLC+Fm03rR1b8fzz9sxC/2y51OP+VBC2vyUZ1MPIVv/6AWoLD3b tC7SvC6YqSvvIRGh5bI/j2cWYu1jc86bdmsSbfXFEBLCRalNN5AMZX5keTYIuOoPI5/BCtK9ZZ1V OPmw9x4arP4uqCBwYr7iaj9IfxkTrZTHwbec+LrbwrLIJ4pE/YEhAXFzgEPKRCUz6IIOrpbMrMT1 wyH5TUgvJIefRhYViiI3U6Xjc5y3z8MWS0OZdn302jX2P8PqI9Yj3ejYk9zKqp/1PhaFXsmYm6tv f/QgnTFVv2UZ8d2+QKqkQ4pWVEHz6zzOdLRuGh6fLmAe4aXBxs2ETkYSTMzoabdPQsvG/tKxBeTZ SByXYzlDwQVUVu0lYtt5K/+8Uga2w97Tl7iczdl4nCluhmYTLcQ3iQK4ZrKMsmCEK2Zv2UhZHiVP rpxmOkhm8WbIlFCyBLvv4ZURfMBNQl4B38zWV0OWgnCPuE6kFuGLoZw6j23lkgyKFA/B0qk962Oy G0naCxwfSMqosZ/odZUIZ7v2hX09/DHsL0tRae8YMZaz9XqZwEKdO1Blub55nATRGNgxAGXhLfup 7jYPvtaQ7p3Pm0ieRW8merz36WJnBKlEkUQ+QpUtgYaxgO5o6q661gGQVm4942Aq3JY29DaSStLl 8tnLqBeCMq2cAVwoG7JyHZT857d3rrebLsAUDydft/hsB1osM42sXGLeM6ODKmEVuAEdeoWxKi4+ Hf/KXcCVhcka6VnEZJsgilYuvq+ehCDjssKSW36URM5ptS8XdD5TksBgC5xJohzF1gl/0q6fc4XT jmrYSy/cdrILpKO8NqUd5kZLOD8pGg3QFUmrKJuITWQcjH9//oDZUvJuoVSRiaVVfo1Nc6cj6Bdh D2mM01Nxpe221Hjk1RyiLFjQ1vjGLP29thPgBvY/pmgL0GuVmpI55J9ohXh8HAmve4v4jhiqFDEi rOmhTTcNq0wndXvFPdkBM0/9/Ep43LSO12pkQ5lgkqAALHqyaq/piARhICZDy/zud5t/2d6A6hwy RKwCj65v0L5+cbEzaRnORGHywnlVAo2EgDinD31m43c273/hiqkXFhpIOLXR2qQueUSFNmPLNkEY XOKDm0q0I8LiinxfdHT67a6hfgypngyV6q/Bzea+QFVpZ/2kzMs0SNsjHVnb0tYzQGxhFZaPX/cy Y95wA2hmn/r+ea8cDPMlQdNkS/OaJysMIiPn89faRFRjLn0Y5uKcapVm6j1RCdhURyb6PKLlpdAH /2O/uiF5Sk68Xmje+UO2r6zzFptG6XKzmaJ8ZIzHJkN06+keIlvDfChSXa+y2xhDEbt+ucLsYXg6 GFIx8TJX67AUBpw7qEhEcOAZBeTXHno0bwsLZzhd+2AJtnMhJ0mci7pGbFO8Zw2Q3TkPEpYoSKZZ QmGDff/buJUIpVUt79g38BF0w3aEEs7ZhaUHB/jQ6PK0tdaek1v+GI//P+Fm7KI3jv+xSUkZuNE9 uYKsMJdsnalYFZOVl0fAIXo+aQuKYkY2TPBgBtAi0ztwdpHkBgSTIj+krKhGyzszWMVX/JjQXTCH DzmflTjX9W6ZshRaRZl0/0qX4PooeV4wEwDLr9o0rtkGu+MRRu9hUaeGt+gqPPLjvplVj/vZvgaW CS1JPszLE2m9XqRaGh/3VTb6UkBCcwWgNEGlu4enVo3lZFKQbEqe6mm+ByVhALY9ik7UFs2Uav7I qKhlzzk34oBIj1heXXQbWDrh61ALDGMtvAMNPo8fMJUKpwVO53L3IUQOAgARxxnClwRwqr4iF6SJ V5VH0Ukz4l7OqucLJuSqTWG9mYPytJuXcoq0sDUCaqtvCKuS1Pax1uUwnf+hg2yo0k7BES21ghLf toHpZzQzGk875QZV1AVDX850xfkHuauIMGOmqrgwRPRRBlsHrHfwhbwPzvco4IQzAYOlTVHyTjAJ an9PQUxw7Bw+taT1rzKFbXV+/8XFg5wAFSIgEAv/N31+lgbytejP0/qHtaMudbm51WtSHn4t3XzY +gqQMi4P1tNgqc96167aU8G+jx4pSH2IwDD1EZFB8+SF2k3wcQ68lUepf2o1KF8AlpiVS9z9fOfV 9tG4+XC/xuGjGSlS3DCl7y68hV0wsT/Wd603HrbVlc1hfPhqrIQXL8Xix8VCt9L3nVq7oEXrfL/m 9P3cXljLIZB3gztr6hQ+rO76NqfdJVkV1gt8XVCg+qYpgTZgkD5JXI+oq7NHz6ziv/o+hDT4RdXD y1w+kUU9RNG4d7OoyQ7OvQo9KlsOjZ/9vs3O1T3ny+DFDv9GlqMMcDxTHNIoWy8CG0cimE/EJMTs Npg5mpKPSyJ1JcgjxElIvgmjk8qC9teB2740vdBMoT88/NSTFpFs3kt5OAPsOzpUtccqFmpZgcoh tzegXJ/n4ycnt/4TMsI8bH9hs5xTmOxtmNayLIRtJWflD7fs3M1UtBbPbyU7OrmSoR43puMRbHfx D3pGU2s19WPcvw7IYKh7f/X1YkK2k5H2Q2+6/lpguxdYP8TBkYWgk95RkEHJBzyFCSX8ZuYEx0Ws 9yX3EePkDvVJ77x1YCuFZmm5WvaEEWRLHnXl+TYUSwhZ35i0c7jagfUrzbIni1gp2uwtXL2sZ20h Y6soye9qas+hD3ztlc07INkBtl8EjnvttLZUtONSW6qp2i+JSdQpjyhK3FakWrZxCrtalNrHyR// clHIqQmNZkw7amWPNpJpJDBb7vndKZGDKbRetkvEQOP3Bojml7LHsiVkcISCNMwpUFKjGLqVcH6o z1SEE7cFG8NaWEUCqSKKad8Zn78LcGKH8yayAKST3iz80DruIpe8HoDQ6SUYOaVb6ikednqf5UU8 PXHv7KYi1rfb54Ms8rbqQBfI2w7pEM7FM9JsUDga+edreMjyUT7Pap7Bgs/DDgR4Xo3AkphKTMHu hRmDIjvggpCcf8tpxeJWBDHw8LB0a9VIDhsqy1D51DpahQh1D0RIFxBTFxt+B1YhBuJAV05hdf0q MEFLPO34VqJFjicp+tHp1lGZoaBfy7bpuAUw0PZydDAyUrysLVI7n30AYwLhmWZnNtdedMhAtsQX ZSByW32S8WNrNUV0tOIIndtKx/gPf+RMGyMnzlku+R6+AUXUve6JIn3si1D8mRVYeOlCAcSZWKyV dLX20D5Im9Lrw8qWaVsazm33YxyRpPRFIpQ4d7Oem1O+MotjcMvsjrfWG51WNRympmneTVRHzEQ8 oeiZf/v8TTFkPuzYIXpU48rl+Ra6xDQYb6UiABqvUFIDg5smqEoz0vXAOwkzosaaEYXVIdmomkiO CPCGer58s53NNpMaW/DlT5guXfdCG3LorE3BSBJBXvkkHPSU2TAiBk1lG/ykSKHBMzHV8h0KSU1M 5ZkfRqL7O5ZUotzf8gO2BYaSfqt7VKA8HQuzkXRW9VxKAnz4mxF4eekV7rs38VqpccovoXUtjQf/ OxPE9sTLAN42m2GmHJAvrOgwIc0cX31xMMVgOz9K0+D84xdQcDflRy6PCsSFX6B3mWV+7VoO/InY DO5RgCaLWv8fHrAE7+zFrMEM8GvVWh97PQcCyF92ClKLu99ZjEeqTplQyi+5SydKdoz+gExZIjN0 bcP4JACRESP03NhGMZRD0/xclrBnlt612I7A1/6SL9ovTQbd1m7KynO66E3LvSFr8sb3xLl645l4 sRDOm0DLY9ReNVxWdhF9bYn+149UqyYCPikIZJvAJvKRKGFWRhLiFbB7v8utyktMyo88urOUfMRb xPJGlcYEDv/+yQ3Rg2GgSinnW2wX8JFO0Nlqf4vWrOb4IAlo4rAMnucEObGkhM+iGAWL4vL08k0o 6TmFnhQZf35OGjYVgI3CJfMJkYw0I8oUG5UM7Bc/GQ+rksyWsVsrNvDbfhKesInvxWVeOVcVjPPV ggbqka6K3I6AOwgxbF8tk4Vokf0ZR7gayLkwLXulm5nd821OH7yQA2U47cADHUSdMh/MbWaz4DKb AyeI/j042HBpxVll72dqrR5sLiBPBl4StYsRDjf5QEGMJj8WB6yza3tyuXn+dhM+CNZcWEn/DmmT 8ADkDoVKz8PA5brIMdQVYtNaUFTzkXNgCpXFpkbmfY+Z9pUIch4wka6+iYP6JGkzpKBqCW9DyPs0 OTkhz2WEvC+pG5T6Z3oBVK0syXLEbXcn9MYbsk1q8vDMn9nHF4FNwm170WK+3HEJCWoIxeG+oIzD ODhaGfu96Mh3HvbDuMD4deENLvXJyCWkK+Xb7Fz4c6xLr3b3QweEGK10pb6UZoO+heiKEg/q1MOt NCZqCZqOmHDV5AdO2pFezd06QTqk+B3b1EZcJB54jIp9Q4VinhWn+aLtuRT+5oYkbvFlpV66f+RR AjfIc0Bv9ihFYF+28H0XSvmAJNyAdgTAjXJO+8IFyYE0CZHB8nnwTIT+vFIWQLENLiLyv/NdOfz8 FkG2Q4S8/Ivbv9juFHyDZSP6A1wq+FcBCxjTfBq+MQqPfl6jcsz5D8j8umQsx+UJA7QJj2OJfoMR +jxNb6DTKlEB3I9stYnNTzqPbRjG51l9FotRYOWZXDrWhmSt+FNYGUjiz2SiojW35ZO58xqiBeTq 5n+6OfggW196qFbT8pwxYE2/OtwSS/nKpbYqEONSwxRA92VmGp5Jdm4RHrISraaSxo9EbuK55Mnl pYG8ICobjE6Yr6hXc1oIhXf1/vLFqdFZnNwygUTDMabWWrcSZTk1aFx6gyWhCvwDnU9/8eKhONoJ GxShOwReuG1alK1H97B3K0TG1c2PPYKZX9CJHVotAG+3BPE2BqkMvkDBNDc6R9vytpZCBy/1w+Ad R6LKadzs8V8BBj2Uba1J6QqeSLZuBcwWGZ6wjz9GG/xmroYcwvJyQH9oBBmWj40RHD68lY6dpAR5 dI2dEYKgn9Ro41QpbroBcpXbzy6SU/A6LDUF6OOIlJZcWpFSRY4u8L9TNVISfeCyuRQ3sRfRHBnG d8WgYJxEpBOikTs05riawwbf3VjXU6Tg9taXbD8nHCzxgQsNzojrkvB96sVMRDyqwn3AqP+kMLX5 /Dey78ElH+yOPi55KdbcNBSPuX8RTMST6Jn41lpBMPJJ7NtG6JXsnpEqfZh2ahT3XPYhc+uTjBP9 aYu2HgYthQ8POlCw19RgPw+drP/IKTMCba1ILNYHfENOVNUuM/BBteJt744JbCLpQaGu2zl4H3FQ wlxn01O+Cx4ZFk/RL6XBBlI64cCVAomxMhbP5GwJOYtldx4eqoF0vqiO3OG0V4wnRfqJ5mvbSn/n cslmEcfGTygBltwmyNI/vTlAaNSGRF/Z8tNP50+WuVU8GP9A1aGcUr2lNsiCZyCIn5JvxPW+WUov LHz28WA59uXz2XFasQiVimepui6MbYHGmeB7RAyV41XYnnjHJwRWN4I3uXicmwA86NVcIDP2dr0b Cc1oTBCnFxZkdWvPXP/EGzc3Rxsyj8zL1jXYLN0GV+DNdNrTeI3idqyQHZnrp4j0TYFKjpHZnTnA d8Pi1gvpfkl58TAgCtzXtwwOxM+Sq0GBxuKIzMJ9vN2kIPqBFYXFgrNH8HCc0DfcsshyDenobIlW 8m1/Ucj4xv22xwsi4q7S2WtHmWKzsX41GrjxlmC3h8X/3I0BuDFMH3RMvFaix9laRoVdll1JSMph CXaoSKGpwgC3Ut9CdBXb8XIXBZpoW8rUIVVLIfxK9s5HvAjbQp6bTThjdsbxc/hNoewi/42CDtGx JTyzCM6+8+cpn6CPGeTcye0GkafSxBpy0lnK1WiiggN246nteXmmbb41VubOJi010YnGWvu2nmS9 hPpgDVQe7AWX99oEAvnHsImeFzHdmo6rrdRly517piHrCqJN0+LyjFIxZpLMgw7Yd6bJOyekYEPj tXfxe0aPfHPIHgeh9gVLgDkQqUHz7F7/OyHcH+gnJSwxA2NXCeSr6h9nnAZEPyWZpWi5fbVgsHoA xgofqixMqWhuaNTsPV013O1MHchI4Q6iN7KzKVTfanlHg2P6XFcUzPjmVBAZmho/ZyYW42DEcBhK kip+oic7N9+bu16wrsTx3Es35PmLn1Goa+ClOZL1bzWYH8drHfec+G27cxLZb+8ajU3Rudu3Wz7k SG27Q2f/VerTuMk/FuVbxtYlDCFuGrBkuuh9Vf2/LH7dnTRiwBf9ybyw6NYaiFmg3WaBwkxcjAJ7 PRk5SU3sS21AyFtZId38bHg13EROYihWx403lyiNWYZyf9K8ZwIr9oQ9i8l4/CHYI12Kmh1KyRFA QZ2D4zzQ0LC8Yx1wWgfuG5Oa9gAyB8HI7oOlJB7m5g5ItnFtApTwYU1YDCqCTRvTXHpapEVoYeXu p0J1kxQNk2fQ/Xu+SYCiBsqhbMcqNjvmb818YBPvE0LrSY2y2eMN82HZEpPXSae7pa8VDh30nq3C O53+tFgUYuRTrcfaN+YD8UfYLsUw3GdU29EpTtGdfmpmNJoAZOidRLtmQQOauhfVabWnJj3MUFBp xvIyLk8W7JTbj1a4KlpkKCx5wHFI2YgBKh2Xnj0TnJpAqwhXMGJVzggKA2IS6VxdJpjvjpUx0USy kG/LYHo7vx85qcR49rOxYKWA4zBKo+2/dOFE5blOl99JG1j4zz4pwdIuX0TGMrd30Dwk/YQRWVYI QFwLHAu50GOmtwknCn4ykYXp/YZzJffD22CQiTen0SAXBu5ALBZdTkrPVxGBdXtzqM/OGjt+hfge uzFvO0WVmp9oEoc2u9rD5YDCNHhwV3dGPQoh6odmM8T2McS2i9pIYDcx36VECFMRwK41Z+Bvd1XH w3onNYQjbV21Mxwg/i2UP7OESwopXGDUo8RZQZh3DQ8Xvj/vBcZd2QD6W1r7dBeHkiLy8mVDyDTP Mlosntn3XJVdJTaZZmh6dwXq3rfg7bC/NlM77LrSQFbUxjkFZKSFv887X+00hPv0WmZ5sKbaErZW 3gFWgQkdKP9hx+xrKZuTUFOJvM3CKH96HV2CBR4W4vxZoYGwhb8nuspEcoadTW+6gA79PuRpRGfM zKERmtNxTKbMgDwKtB41+CvsIu8kmNO2vA035UkWQDzWF7q3+LtNHHdrR0+ZUEW9qU1jypXLgi55 F+UeUuLQkMQ5zdUctDTmztmXOJFkaZSaOKYFNUgFoGxL6tDp1cyGzDSzMhd1S4MZ/i6kjr1TzlH9 JQ/d/Do2szRqMSthpQWXBGpAFT8ILapl7JqgccxMVMT3hdaFYAg/ftnYf279uqiGTBZ/hM7a7kFD rSXwoq2rliY1cjGxq4yu9BidKQkcuZvO9VOgg/z6NReWc0N8BAiZ3atW27lnzCSxDcte3eRM5T/q xpGtzyquD9MSQ2VvIA+9CLCLdv9wzEKLcSOGcLp/hyuDPkGd0DXVaS5Epbliq1Uz0XbVkRqRBWdL zhfXfDD+ID1c/KjVMElegKqpx9PhN/gBDwofhkXzxayu0dm1c8OgtNl8OTuKy97ZvHSk5ZVAfD5y nKZHyjQs8NOgHZg0h5fYm6oTX19Ojpj6/St7gTHcpSkgDxuPwJVLNcweVFoLXOPcqHpswGcFvrk4 zuvFyocALJdNa0ouVx9HNc1qbD+xAg7pywD8Ldfuv1rGb3kHHkatrf1a3HBtfe6tDXuLy2ByQIAk scV11yBFOc1K13x3tQxdHzKFMyxgKzpcVc4cJLOiKBcWhEd2S9+IrMSGYLYS5MGj5qC2FTfJWcub iv2mts8ssXT+FoID+2m5Jp4QE4sIvK98dhhdmrADfhX/X3d3ha00tvvntJl6GwoCAJfiN26oJY7X laBqRj3BBeyy5Yxnb809PhCs6HUVTunN0qRlx9HKCHSDfAqZg08TbGE/6kz5eD/oBUcEng1zHR7h lE0tHC0f3ersn/RAIKazD5SwkEPQY81olskZufGW0PnwbARr50w9vRp1dk+z09LAxzVaOAg54Wp8 5e034z3f9xK9w0MRJ3ty9ggNbBS4zvW3U61F8KvulaxxomPL1yM1Ip5J9UIjYZeGe5l8BWNfJr6q ZdTxLPQTVup146vccyiCv8/BCUtGvT8QGBgYGkWV/eBtejGoK0rk4Iq0n/nrF33z5LPOxiOPb8yH iqdxnWZ/3PKVk43dKoY1koyscj6ys9HhEHJBQeXLz306SSQxZjMpZOSENRVKJG4sqSqELMneHkkY X9aswJDOqjwWw8PxYaNSKK6Z6zzeLE/A28jynphavidaPzlYGieTwHPHa87nVGv2xVby+laSiWpS SZPEB+Kz/zao+8wedjN6X1ocRGEp95lb2binRG2AHXFkiqnb2MJlwzVItPGoIusm7ZSEXI7EBYO3 SvI9FSJdfivgE0cUPK1Ucmmtp7opP9V7k1y5TW6nPHBpHCBCz6+jJ7u+PxS6O5fERD95+QyFzLxQ WSoGORhm6DQPdalPNCkNFH80Yjo5yJGFl5cuDHELnowL80IuwV9GGhAkpZe6hGgdq/1TsN6YJ3Mx VxhvCj1Z7da6Dfzl0f/SxWRCMhJfYKi2/buaHqTDshXR4NozswxhwCMd1U2M+JtjkxcEXmw1SoAL 46YghwlVUFwUQdu9uZDDO3+tZdpMEp16flFjW/O4tkUhzUiAB9uxdN3mjoIycyZLGtxGh3K77Mq8 /55OdhI3MUfioAiENAymBx1yCZMxaXQrr5dKzEyB0LE566PshfK8eCy9Twcx9DeovK0sile/GzNk u29gqB85/4TuPh1/6iEm/p8XM4vSs/jzbWpefPi47UXqWSJ/iodG2Tw/H/ihLuDp6YCXLrYP8fJ5 bIfZGxRx8sp6+FNBS5nkzXdliymhrvYQuoWCbaEB9jHC06Bk6BNkTE05UX1Wa/tO0C5NIdbJI0A/ y0D5u4/FDB8FNUnsZPJcIcyAjt5zr01TjQsavsyerS5dRMDrlBSGnnE5g4c7Scdk6FQd0WixG9tj rGDMSnNZDXq0GFmUuNcLDA0v4BEvreYPQ0BzHMnX20IYhBQMEhfTnVpV9B7BA935dL2pVpJEcHBC M0aGqBiTX+EqrK+IOwE3ySiaRI09+LTM04Xb8qN0bHntO547xb7kSATjHJafMw+w4GP8Fne+tRhC RLni8A36qhN2h+IoGXLvBb/fquA2lxBojIxbv685oj8umcAlDsg6YV+ubqcIkEKT49bXpXNucCUO ZGupqA2xMvxFuKw5pnQRHk1o0+Wf61g/NJ5kLEE6ETdJ+AZJAyIdKsgdyOAtgirYN7UG6alBW3J0 k5RQgMYY9gJxeoTYfLoWQ54wKXqmN+82rcXslQVTVKbnoRRbTFYO5PzczS4rR9yaTDivWfQy6Diq wnxdQQZXdzXP4Hih3AeNG4AlOB+3N60Mk2oRSruTXf1Z1a01JQhNw220XVUeEdagcBhgI9ImdRsn E7sViHZiTA4tZ+DEVmQN4kCujkWsTHK9ND4tk3MyRhVfY6a6NdLAvcCFKNyULGy6LnEzo+6bjeJy X6KkxsXB5ggfjd3SXH8xSJITyQsgqTOe3+WBRPuJPlauUbj76RWAd8gtjeclzmH1Waie7d0N1WaD QikaUXWY1k7sDrOoZWebRDhwi25RbcAWW6p9PSguQdy7vLNHvHtJJ4jadyGF3s2mSVyw/4PGh0LW bSWA2/F7Qcmkn4RU3BQtgVBzpVoNkrXk6pQDCgZpEf4yaVtfw4EUeztya7HUJMAsZrhw1E/un9D/ 586IYkkUjaypS3d1+F2FZl/jYieggulDSJSYXVYYqePlXVsTuMvsPdnFlKDWl3vi1QzQOSqVBBZG /+muiibCgLTfc5JxHOr1PEO5tT9w46udmF+M1ob/D0cJuGKM939cyIIee2I1EaUr0KWtbEFO5H1/ rKgb643vGa+22A0tWbvaDqH52C386RFhrd7GuuBD7bCziKcCH11499OUZa/QAk+XxlvFJlOZdCSW mnCf60XdCyUV+/dMQRV+J6u/qvF29Xbx6LJ4yw0RTffIbxFtN7E0KRNoqpsIIvYHLdEQ4fiD8u8s 7UFy9R/xdae3MY2igUd4naNyARkj0XF6tfnT4qvFfeBFl54nWy7bydCGkGBJt/dV4/6iLKNu4gBt klUssqg2HA0ObceCyj1hGZFocBJp+wRr+gMKCazkXuv2SSnO+2Pi3N5LUqDfkHH/p7wdNA+uJrgg F3DuzFJToEtieASeqJwfXq5La6IEhVh0UNUJKlNDbjXCeHoMjy4aKISh69tIhiPiMf+mttKiiiu2 kBzQHcoYjA7KEyJWwIZ2grZii9tUbM6xFNwDbrFTtgrZMoiON5o+O1qzxR9mAzuRShfInbV76VpC ujY/YDr7gzNNM5vjCeTNVbGKkEcrmUu2DApSoWDYu2cYtraqS+OK60s2K3pbc0SEQd7B/zLf7IMs BZw1EeKNua3EKy39wdnG//OB+GYCr6jXw7dLTBivNWpsQ4Yf1UtA0kgJHg2cAv7Evj0iR2VlcON0 2d78LNBINFfmNtI/Zh0vkKuTN0Ps2+Gg+nC3MIIazHT1j/0K3kIgvTiRX8KCxB9eUPSIv81WbasC bhKI6xM6h25+1iUe3MPPyVlQSKgIGpeL9CNXFLsnfYZUWX6F3A0+Rklik2X3WUXKSRwoYlVoWdlQ 9eOEBX0spcn7d/uN3tO2hCsH6BHd7yZl8RrhRbFYPD1/ILX0TySs1MRAYrkD7SROhqq06uPom5Xk cpuFdMOXYvNhBQcouNCIx/5HbiMBuXxOh+CMso7jGlQfvRx0VO/YimN7Cs25nuIUuQ9WClvbtYyv GBXPi/9qS6E9woLgFNFn+0xd6UtxhBFWh786AqwzkFQLSXP5zE5JdjRbo4LK4Ek6bVk+AlyLkxe3 RiEglR0oZMHPOq9PJXt5fPX2wn1ULs2OKV3ihM8IAYENDN5acbSxxqJZ2tv8VO8HY+6SCMxh/B2L TlgSEThTUBRWFOYgX7uzkkxUAl194Bf4wZ+ImDE+iXMDYrkCO8NtbBc64ojGtpd/04eDFQ37IZAM mrr9AGB/0higamsEM8P3ZX56Nf4ZjkWTENRULHJYl375PRTryfuGiGa4V/AV+dDhyhP2uuyUaPRh qroggCWyCy7XzUNnUKbykvWDFUyaFTOGC3XuHjY8olSCH75YKLLH3g6PaThst+ddbuOibhU4YyVB 15an9PXzosF6wmZmhCCoo0EO5bKJoTx6zGYvWKDcn0NSlZF07SOE36qAkzn+59kn37pwxQQhMfAz t2/7ggigQ5Yj6kopzJMX4bAtD6s9Dlu2Ww/DFo3SzCfvsQb5MAYylc8KCBiSe7Z7ApkaTx4DUlGM o2nDEoUT3/ATwzAuOscxZ1UhgHym7xV3i3Njc2gyrcbW9Rq4DIz6xf/APPAresJ6dJiMHNXHJGJl 6JI6GWJtMyOC8e00Wc42X69IF4hSIXfDW+nh/Qb3lY6UJ3aGvMBsEVngamxzAiW2YEAm7gcGTFY4 vnx8qu3b939uUW7fw0ZW4ZhZnvscRod5TxY7dqvEaMDjAHMLiDYumSuG+W6cHHvE/uNg0TYB6hft YK2FThkVe9+cPI5MyMLnTIoEA6AE07MfSKMHKT4MINs0qMZ1GHg0VqTtf0qzgXUvszxFVQaDQNjq Az3+mhPOKCdgk3ozMWgF/mtEDLkQhpeG/tq1dd360cA/h4MULIr5LgqNMcu2Gyyrcmby5Gw1vTxw yUkCFVw3MmL+tm//LzzxVMJ/N2kmNVxQr5C+Tdyyz3iQ7c8GMsoF1PTYkj5OSzd4/8FSUUf6ciFZ Yf1GI2VXRcx21fGCF8zqQ9c3VZ+UXbcWMWWWzmEJPtHLrRkXFyqcpeoqZf9wlkoGhVf8sdVyVclR R9yvRHKXGmr+XjcOQJIBj7ak1TAOeD4qGEifTZAAYsQcGsRdontB2g0juVnUB51N0286rfmr7OV8 sVxngw1Repcj2jVuyzcSq98duYsh+fP4I0hOnivR3ZLTFKb1xBjnqfqf5JRkuU3H9h0+Eu6ZhgMm mmYVV4CZz5IghJY4QFxli85rLNT13bpUceXY1www+pjs0alEmb7erYXyx8CQ0WTnSMDyHjXPdyuy 6lqWCj0uq8ZLZ1GbK13MaCxZE6rRF8prc6vu8yhG0vYcDNWcT6thFMavPzHJD0KGpZd68DJwehwf CZzxN3uOO5u8+kvyqb0eka1JmtouQCU70URz6iIZAGHBwiaSRDnDSMYNSTZ/chxLPfVaR+yH4R5n 5jHi5EHl5n6lJrci6zVcWbNKMAs/K9lcBMzw8wWQqLUPlCU7/LnJLh6r70Cn6qhVIlqXJhVOPktF iEW5buMczDS1LG36Tr+iIepYYTDhOt48Vcoo5bQiouE/MPNZaHduGoC8WLKkiUq7MzUxptYIkC+m xebtesPXnYmtuav7kpHWJ3ldx4puGRXqKY7cRGcjrMw1WlgLX5s6eiXqxdg8jeGYsg9mbcT+VG7G cV7B8Xqs5Y9yzfbnufHB4brBq22ZElskiecu/qEGQA2Qe9lXAwqwZqdPsm2KahqgloNr+t9+rEbx E+dkpGu1xBPJ1ZYC35pjyA5KuF6ulJfmWjUhN6di9c9GQ/Z3k2Mtb791X20Zpn+6eterHNsUXEhH LIEYnQd94cEcknp19kMNzi0Cvlgtgz3HXU8NDzNko1GJpq+WfS2bMbXDYmnsTpRtMVE31rXNwSjN XlhShWqDS7f84yNXwnVZDuZ53Oax521k4hMaweUgchEhUlHwQsLaHKD9SfbDouE6pq/PhRH00uyR B6vySdlnQwcgI+M1zBFA7gOJaq4Ut6iX2UMnXqPs//68hceU24AA43bbeMBucPftLlIoj8D968Rb 47XQB3zDHk2dUzPoM6v1FHFl0j2lOlRDO5KNPlaVDtS1NJ/0rVouBFkPzZaxIXbxCRLLMv6iSbrb f6gAPvpGhCYHcmRNKxH3rekGSCQVkpbiol2lLkj+58fRrTKLnuWiFeIWWC4mzG+bE2iFcsnefGYX 8FvTUhDRFFpkqgLY2MBq5zSyMCP0j8pkFUKgkZkpntKPt2VWvb5nP8BNEYLcmWzSb5YC96UETjZd rqbNyNOBnJsIHW50Ktl5xxicyb3Ma1ILpex8ilBXC+h/54BslaiPUZTzzwGWqzJSopypSMUtUrbI GajKIIvn6RFnTXM6hYG5V24w0UNrFR/frutriqyWt0lYbsEua3hcrmDN9652xzHHVVs5JdOeXOwH 5JybVsil8hwf1gKEKRXiOMPUNOcmCSPjW5Bwfr4omUpZ9lQXtK5ygw6Cs8OBdn6Yrk6CiMP6Q+ty CzHMCA5dlPEG0j7jBrWJ+Ob4Ra4Ssuvi4tH1luczGJXNX8z1v6tcywgndTI/k0TORGAwS5q4eii0 UT3zXKUdXaWfVCPZXWh5uapLUzGPVNUlI/96vm0+LoLk77N54ma4sAn8xj+G64d3Ifd1/PSLhvuv WY164t5sz2A832++as0J1ql3SfgAryJApCAnirJASaJ4+LcRRmCNWNhu8yaW3YJkSUEbGpeUGgEQ HaDdcDTnVZrTNPSbi/QJ5vJkoE2vVNRVRYhj9BOalMRGsreWhpSvbhtfD8hKWidRz5DlSxOjSzHC w/LYaeBhltMauSU4I0ql8cwNNIjtiOM3Wgq6d01CXG05ueuf4pTqyfG5m0oqnORyK3GyEGkS9OD9 LsgiyJUQzcDXf8AUiiusgolWIhGY8yZnA/zK6E7yYed7axR51E7mfq60V5rVLivnEsOA8Th8lyPK MS3mAQTmcfMDYHv5iguqwrbLPJHzqeqnNId1SJPjd0E+dfcqVkI/tL44TDRotA0nttL9ZSjKKZLz bLbHinUVzlfehsAdKlWS3i07se+Ts/1uoot2APUXUpHaeUkoRLsAt9HkFZDCGrBNwCXSNNcHKlYq Zk7RgeMqFcefACNzwcy2qAESjTt0yJbOfUFArJuT71piP944NvCWCj3xRWSlkIVwC8Vr0sO9XLF3 HIZuvyNJrFPIj3BzrZDEyJn8qElMhhcEcfR2hzkxErmBJVod77U+xqLqAfTiz/J1pVjaM2TvdeF6 f7ppoNmm8fb1eRRv3WL1KXr0IYKhn8Cnte2kwYiATcy3rxZUDO59HLCeeG2MNXiBa8X5OSfTdloW w0T3a+iAQBnp7KIBZMMl174sxjUMPFERrbwdOr32FIXP1IBrYcSQiHYHjUJ4cDzHQpzBpuUpHtHI WDSvpwjYii3m2xaxv3ARMKj4dmXBnqYYjI+se6xxpOeCuFgAFaonhSO0I58QcdpyLsWqcV8FDaIK nFEr0ZHs2sPJ1fV1sH81tl8bQnDMK/7caImHAjS/MSMQVK38m9gle1jsJ4KqBtF5DLlKgH9KitKS hWsdt2DR/JpavpPo5NxgbU/1YXqJoi349tvVkgJOYX04VBP1fvJwCutEcd2q4wtSwWx0KqCwQzNS UjEJDMyqVyBUkgv4dLX9yB40BjD+vbTWgcruzax4JoLT6xtQpo0epyK8MItu3vlFICGLv83bTnXj s+SWDM1/POB3OT+2adFyq07hcWRI076BHxZ6tclTFYrZbECTQfTGJhG8lniBGib+6iupvPB0+FPV ZACqSiVtQ+hFusLOH1k12Sefq8hJWBkKhyb1qguFoy0Ca+T2u0SXusqn7HJbW86QSHDo1swKu3X0 8CXRNy4nFGXu/OpYQX0yD4p8RirAYRNZcxtJoqZhR1WoM7UAjezyvOy6NucetopPbGG7cogakCW2 5Zuev23uaoCTxOedBMrilN7TkAoMtodvQ5J1KvAyql0UxL7VPmsA+b+Q7JUSMLz9En4DCnmZMusg RftUmEM/TXC378paYiOgd6mWmoUE/9L+upz9jzY8i4osYr+aqc6JZ4jficjNXQrHL+3mLFvdLH+H +GMs5InZE76w9r6+3aVCFbXvvHFrd/Ht0bkA/ka4Ym+1e9K4mHq0tBrH8kpd/IqyOkzITBphA1DO VbnDVA64aWmUf3XpA+DVbfJkBR7XzibM1ITpGNFc6cuLpeZvPpxBpNPF3JokU/P2gilColhNh2os WWB1pupnQWQ0sSr02/IoMCzTwA3ruJqmrixhlr8wrNkcljGlhl8GEdOVYzdWJnfA9p7b+Qc0VVYk j03N937WHuD80vHSLogHw/GEgWqaHbV6pOshCNDHmM1dSueqA63cwZNq0fZVJwb6HjRSwiaG1iJ1 Y1jJm5TaNAwmGy6vWEoMKHOsQGxpVMjjTVgfnAJE0NMLGHQ2VtbWS022ylGHM91SK6a1ygbcZZxL iYrjav2M4pHOjXM51pxxU/HJlWJismeUbKqqA78LHIDKkF6BcZ5WMEFT/wpInAFnFZ6RK99/FYd3 6fW2194KlY7zjzVkxdEaFobYcg3OBcbdTfrYH1lWl4pMP7lC/LRMhX1d7hzQ0tP42h+UJ1kdv5nY Oxj5MiVMFDOBFUexcMMH81RiKuLJcuvOazuRHEVMc3pF/JICusPrjtLAoVuou0B9vgmuJZCw8R4Z 7oUb0ufSidI7THGyhTKHkcHwwl+alKYNMIxiXC93SY3ZT9BBXYVLfjmkl5nIo9OztE6BkBay4u1m PX6t2PqtgB3sYp+sMnYTOYDmDHZGbNjorqslmXZAGeXWyFa/d3Ye8tCGHi/U2EA/b8PxOT+SrBoJ qTlUuY7JtaJiI5MxVBh0oOFkCEBBAh3SlmSzOExLCD7Z+T9o78gl//odcxQjjdOhJuAHXsl4sFfv 512R1VFNB/9QAJG1gRZKJzIdM5PDfQCxCZmjpGLlvWDbUAqNtx/N/tm8eyQhihqE5VIWUezTyb/Q +dsa4o2telPfYoqXgg+xgktzeluNZsm/+Jb9yHLPF25mVoSWptn1Wukl2DPvJwgtQyDMEIz0pDtf UgJGkRXA2yuViSBxXM8YaQDhgAB8MB9xTGUqZj3FthqfhHXuS4ltkTjeJCN5oGtDKjKzBxbuWSQE usleYnzQFAjJPijcBk7kUDj6Lo5Y3VAmCLK7LnyqWm7Zhh4XO4c/xqC/QH74ZlcDefXfFFDPoaoX n6BVInyw0OQPcXl6osXWW14DfUK43A9/+BLAJD7Gjpfdby7eCDOQywAhuPISTLpXMJ9HBOghiwy1 Ys/5OxfbESuzqys+IYz7gyym41xmwHjR3IySCmnQOBp4CB+VdaehausWwzkzcnxcejZCupkxKFF5 lQInBh6YcET+18yVU04jLlc6uN5H1ifVZxiIaCjxw0xYqohI20zhIWAF7YuDQSAj9gFYrNug5qLA Jj3pPwG2639Keu6wAB8TwEAoXqZhEg9fvhvCLbDHBmgKwCvpM7po+sYPm6vh6gNs4fwTkaaYPFIE kRDISuhc3N6EZivaS08rOpCEXg80crnOCfkklIRVhMXaOGuvzTmtDFI1YWri5EOu9SrFPo6pYs+T sQlry84V5VZ/+sGIDFie/BNmYG0LgvYCKaKPRhjrD0aVXAMVyki9SA4u2GKWEN3OErJySGgZ2tPC IUyRvs5d+e4w/Byt5a5IzSNTtgKl1dMsY3MHpJTlA/mywftVT8BtDweAJbiQoOzH5Gbo0F6l2VfF OtTnC7SrT7riFlyhfeA8mjxOMJBZPcRq2dG4PFWdco4TsMmkyeZZFUtAzCUUqmGFNzioXsd9LQHy cstcbSbUUo+XTBcaNXDbQN3uD+CvVYFQM+psY5smSQt2HB6KkxE2g95GudAVW4R0xpxRTL3qDDz9 phbnvuf7BDaMYNLl6Zoat1LGxkV0lzZbiLTOrH3EBbJzpxT+SCLIU3qFS+T+lzhBB8qKaJ3uFzfV 7/KOImnamzZPVTnEYDMEsw8zY9m5WdORmE9eM6egJolD7HLm+E+GPu0BfaY7BtOgFhF4IzAN4x/I bHxoDuheUYtOl4T9G25UU5TH6zOmsVnihabvYlq7wdgGyBT8am9vZCVJndazrleI81+rH/j4QEo3 xBLinfypq3EBg4TkA4FsHIK1CfTcPzkN/lVU4rtHoWmYcI/EBI81i+YTKt0+vLYRe9P23XPPVDuQ 3Qnpxpko+d//y0frac2SZEjukC829vIBjD0OUysyldkBpAxlllMN/qZBxwhZLETjKgd2QgVAnSI8 wmq/dQuGDfDYpCdIrvrdMzs+yD2irc71dn7Y0x/+mwQjHD4L7omLtStYdByj0coGFdQn4fDcPmhS iNd/XORSWhBcOdLhjIejW91ccjRhyw6oeGlusEDLMEfZQrfN6Mq9GVNVcFbB+NxZqQpGGejwsW6/ wtirnSx3igiuMT0r6CHCJNAyLUSmXbVrXh7V/5XXgLniJKaAIO4klroOC+XzV7H8siZ3to6LX5cW ioajriYPuLgCjm6kTUr6rGMiq5KKGNYLj4ZLQ2rko3Om+ihZT803X51gef1w+xdRNiFLF+HnTSd0 vZ40DdX+dvpDHs18fOdOWIZeJMfaThShVXPRMSRWFb38GAHvWUjXcl0wBvnAhLGhINkD0ejKdzo7 ID8WLEfrbRP6nEt9JChI6J5p3zx+6LGyV8+JuueEaBFiX/ADegqOpzhI/szuu8AO22q045VjLfOh GhUCGtlkwD+8cpwSfZId2E1g/+Ut8V0/dPC3rkw4zoNb4UBf14j5Mr6LSPMVf1mGeukvCFQVmI8m xb6TipZrAIzYmRni/hYqszmZvomx1b9x5YssvfDZSs1dN8MfSuQ9IXwgoVe/iMsm5eFcc/654Yhp KziPZbtHE+KpgAzO4Vy3pvu6tqHtNw9OWRHmBU8HkiDJN7rR6q/gJ/M+1jh6cUXtLrpLVl3TrCbj +ij9E37tNgg3Yc3gaZJ03oeJGnJoq6qfupP3dr7zP9cXpXzQSbw0R3ZE4f5PCjVrleuvCVW7kVa+ Zr6R4cPEQCV7JSbMls/I2XrSRTENI91SS6O3oOiWvc1ZuGrFyQ17S4kSAqvyIA0Y36jr/9ilC2Pw SfvJpwKPN7BFJq5UR3Mst+qLHkTKBAlcMIBCd3guhPxbWqASHo4qM85xRUl3B4rQm+pDwce1fRSP a/ZhQP6AV179LdyJ4bp+jFfL9GcR8nlvEVxsl68qzDlYNcH3/plx4W5u17DBsI5pK/a2AyUnkVXG KgRCg1/+fZSFCozVAKM6EAGMNCXBLH/ERD/UqVB0rWDG/CFaxCirVzYIdBMlQc5mwv+Nqc7hEpIN 6Se+5aFhgmrPAv0ZFR0o8JF05AKVPCCgrDAZuqo5/GnQSb7893etMGU85NBTNNbaKSBu8izMeC4V Fx+MivQlf3RifPkogo1sKXrOP6H+8OOd7Tgk0wM55xv5bS3W8xYTRTz3C0/TqLmorvfqKJ016SiX heC1lf6BRUThDmljk2GgaXWwrHjX50U/TSHt00xZH1ZZAspZh8D81AHRkNB66+DD45FHjkLOOaQ6 k+w4SmKdKvl2af132RX87FhgSbvChIvbkax+WZ4Up7KZjRxFyfKbmA67IvkWQStZC15D1718wxgr bFa+VKLRvzaJWTs7EziVM8Thjn2xW8itBZa/5th+nJFf+MxMRwNc3HVFwOvFd2WxIFplnItZ32Do t22lxD/RmL6dKM8R64LVt7S8bfj3NdIAy4ejbf7G7Tj7Vvy/51wziZ7We1HOU/8MDJFBQZ5lhJeS AkjOzKyShAngBsNg64LHCh+eAWR/9k9xqNOlPJlhedHFJUtnIJEOgR8y/Ij/ZDxbFbZnhOQ93DmE MOnGvdwmQUZ4uObT1wLbiKA5rxAdQQNmaTisPrh0Y0aqM7pPE31PH5EFy5VbgoQj+jTXrzTw19y2 tYm9RcTNIzYvh4SNZMqXIng6lVDO9wx/dx3YfLWZovvYBuDPHHJLReHVYsuHQ1hlnHFpGW4PylWN qmRGXYe2r8slXIz2dXDkYOxnbbtUQKUtfCxYy490w/LTrv+fUPNPNl7LEt3UtsReMIvhte4yf10Z ksnM7L1dBaBIlspAhY/AJcbyumprteCeWSzKDtUsD/SFx63SAoPRtht47UQUKORA906Bs96Y+p42 tImkvudGS4mfSmAgROJJ/RrxjkhJDSK/uYmdcCFnKFSQe6wVoeS96HnaCysxyTofnc/s6vM7Eh5d TW0MspdkFNQOHVbgkpnp5+SRfiKzqFVwuOHcTFpo6pbtdxtZHC425pMIQs3D4lLeKmdVJrlDeNVc 6Z3VBXw8WW9L7p8p+7/W/kxnh2EEc+OCn8B7amXtTixAzwBDpo4YW6/+R154BLuqNfvhs0hldeJ2 x4saLCr4ahB2mX+g3X5t3C199IZaoSHJ6Cwrs0gO7NvNDTx5nybP3Opti4K6hFKls9yYHLzNn4r2 19VVCOpes5N3yRkZnx+NtRu8BYJgQ9lUG08oJo+5eB3gjSSDJ5EPe/eblVjRth8WCBPBOf6PcA0H vdHfnqeCjead5WAf4Djlm7KzD8ckwV894P9cWCYnm0mrtfDkpQkmBAJaAHT93HRymo4wCWRmf2FC Lum+P+7Zwn/k6sc1QzJtUF/eI2QFqEznoQucXk49OTzWv0EMpE5LA+V5DJSThRplC6O4iY61ZVge 0C+rzZoffoOUOxNkpEVux/YhjOMPBOUDPdz8HFKWhsN9Xx9jLJtLfBQBwllw8KPbMR0Nn8KovOvp uil0hZqX8XX0EitCPKie6jVKz4MdxchA+pn+EHUZAqsGK3RD1lBn0nxYt0ACTXBdu0roKN8u7cIU ixFm7bLKYHu0aihw+8v6D+DeFZGSQpAcsUj6syE/BktriYbyVGFl7NuVx2pG0qznxmCZbEuRsK9t bUb7y9OH+WvkRd3omxHiGtWrnfFbgUtZnY5nhYIE9ixkDIyPSJeBXEWBo7Mbn8G7dsPYDCaJ8BwC OZYHlru5M+LBajSgMC//lx4cX8t9ZrfL8/jsGBJ/OVeLI8N/pLlwHNFBJSA8fK3pQLOSST60UJkR uG+mMV6O36poPdJVln442HKoOXQRZMzaYwYy251uOinoSPfrL9aWBjZNgGFnBRaTy/VbE8RwQugn X4vU83hbjHkuzmMOqZB315WkNAPC7DIMa7vMPR8dABw7jAPxq/sbxOkEz5n3oLTmlXo73kw5WQyy uZrdi6p8vGOPrtwHxQyzOLUdyH5c0sQOQjl5Yc+2JihDy0Sz9HkDRa9xA32930Z5UXv8Bo11SBop Aq/rdpXRdPrbwrp9ZpQMIlynKuZjGMhX/x47n/Qd8m2uqYjNq4gONpDmhGIT/Z5ZHxNMNHPhBQvu K5RqA9kAVnCQNsxKCE+RlQA4Ckbgam4Rba3A7bZ+yMLLrVcC0BX1SuV+Aw1S1EaZtDhSmovny2p+ BpBC9FzNNTCr3QnFiAuA532jKMsj/Qe1zBYetIV0Bcqj31PLu8v1zvfh9W1LWKCI7VIOYgq/416j JacNsJyo8lqMPQ3NRRkipLhtlPsvc0czYkGw/C4gLaTsyAJjZc3we4V9eAR8KaHTkz4X63wmAieW 52Vs345+tMXhNXY9Plkoqx1JbJEysGjTjkdelhdJRrOzByPdvRp8e6Po6f3b8cjfkD/hkt+YWvlW hYS1y/kOVUSE/g+RvcgiYrPM7f6xiV2dojNpeEBIVhR58tZpCMd74/TkUNEWt43m7jQPDy742OjL sqTtQiOxNHjG7LxWAmAOvcWtR2yr10GDro3TPcRQFT3xI0zvhRSAqtDbv2XVq8rKvHqsn2mM6B2l t4dXFyQe+GVk5cCOi+ovP0nz+r3bUYNp6OQONa0wpuJut3uxjAxgy5huuVTpdKmQv1HHQ25IhlnJ MuRcnw6rJ7J42PEaFCvU9EqtqSkn8WpLDS1DuugQlbqJzPJyNjrxn/ogCIYCOfAUMpdinEkpXVm1 kE8yYQFMIw9Rg0O5ld8dbMFypk5Fp7HDCyI/RpTonR1GVbNFELksdPBe48dKWbmtltkG81s8/Win 0M8pUb/zmhDmZ0ddiHjpMOS6L5KOvnFgPtlx+CcnF6Bz/YY4JPB/rkGktMJKseliZUmOkxW75Z69 rE7JQiq8zauh1M77jHJz6PtV56ZxVc2ZneyL2eICETPVQO2Tyyy3BJT+l2tdhq1GzYNQQXBRJRSW /ZrgiKSHuzNDxwCyUdkBqK/+EHb2PahcP8z5NdbFkzEM3HwDPgHKWf+vEth4lNrraGrqhWtO/ijd s1WCkpiDZfuEdSJH7k3+iLScBT56rEbhJj0GMN6mW4eHBVF0N0OrcKUOGT4yYDbdWps+paX7Ksdc fzTMkXDBp+pggNDpmXbjH7zk/cFkVVAbYRraNrjfe3ExebkyLxgrXNwu5XDQPULlpFrkmUwD5dm2 oHEj16R9LoZKUU17EZ1w3kImzCXp+H6pMiBxfvGbbbeNT6fyeAAPnDYxTwReLKS0+T7WRTVdhp69 RfOnKqeg3jOqUOuJQQHAeH+WLMHcHAcgtE0KTsOiRafMlnGgp6aUXFbmEn6Zqp8RmsGFtirVkrcd nmQKcKpSGTSxPGhQPLZubFw72klHF00fZv8ZokeTXq03S8wO0gRWxNOjH1v0Au/TnoGAi4xCtoBx VBdcJxGJ1oipDukGWJXU5uHX0914QEcVueAs6rxyRUuxpyLg4o677UcnZo3RUgXvbLT/a4TbM9Po fu9uBcq63OhYTHTS3rZFqnFYdjNKx7clnIoV83dYORmJ85LKVg7pY1tAfMxiudhXwBBCNsYlCSOT eJYb8msoLIw6YDjD/8PFsXqcg8ttsiih6L71usJnPW0U5SeowN94G7EL+3R5waVIlf8hpLFThDyM h+TzlN/9wtgfqzCycU+quwHWvgYVy2BGnLdh/HN5Y8IHMLRIXfQK5EfHl+K9B43aM3jKH9F5VM6o t7tsX+EzCFy62n7wZ4/BlOmSkQzILLJbjF1rqnBV9n2iBlql1OqcSaKPnC/WH7GMoY3SdOjG1EDd b/hBM+qXTZb53TaN5QUbeH20QwGXUeHN0/ljJJGJD7nSBnfnmSrGVi8/n1AGoyiF0mp8qzJY+T9r lVGtC+FxhghekI5clsHpaLsr8mqNhxOaQUg7Vur56PEcMm1kdq8TvOZ/snpiShtZ0OlxnFN2p7W1 KtY/gyzoGrCEbjRn6gZ+sNA5p5XjYhAyW7uFheQ2ilvMK8arvwkg/LvkaXaTNi2YIYV4cPAkvK1X 9sM/tLtfuJXEUlQPm3FUent+UUxJoR5mP3icodL80Zhl7Zi2BdInYH9YxrHgO3NAK+9SnlDdlUn2 DyskoT2NaLV+AHEv0CxTipQSpmeiCRvvfv3G4OFz01RKKc3Bjrb/Qfd15tr/Rb1bACynTERspcZe rGBDwq+iRb1yqx1NnLwVQflLvA5L3mSek4+nasjPJgNSVX/jadvZiU+poRAUsK7wASV89i0iCO4y woCuqckyqRWMG0U/um0mMt24rQVoWd837S2dXNMu65an1FwQNb7D4Tq3e93l32fgWIEmuvaII/Jn rr+yuZJ/pHB9cR3t2ATwiT508PxsMIoBAGl66Xy4HGFA0yFbv+d0Gqc9jHnx7qjuPH41sDemJz8m sQ/nUFMeSdTn6jwkR3GKWW7I2kfvhDzgZf96+65YLCVCqSz6/E+JuBEgdACkePkXRbcMCYmW7Nnp ToODi5OttDBYTMRlcfm1ga7OIyvs5W7dyX6HQuVYWIHnGHrFrf1fVjITS7iA2sk11XkMDvQ5sRtJ ZEemeJ7EwAnokc/2TIwLFJTCom92WSAk1j5qtqIt3ZcR91ev7k18qFkxVjAe8aaJpKFIaKZiygyZ y7/zdZ60zSWQ5CPNX+y2HKmcj4ES58CQhbc/AASPfJgjYACOqgnoScrjx7qckfGpCaI0eg7Pj/Ac 6Q45hJv8BuqKiTfRK7cACmky31eGcmuEM2VciYZpoHhPyi/KgpA2dzjr9tcPJFM96Zp0HWhBy/i5 xcKneRqByV3CjvwD2MbwdM8lRRmP6rwvyb85kwyH+MbOaRI7rqs65jdFzs2aRfVrV3lRA0rtB6p3 5EHOxBXpBvciAdX5fpf3A5n1hrtwHg/6r4hwNgLlsLrnZruDTf+VCqXuOt5jLT8lYv2QXbqmBRw+ wAITduGpweNsmkukYCyg8yHR9/i22S4LD0JvxnlNC7VdrjkhrBH5CA5qogqHotdcheaepxPm8HWD 9yiIpCKrUTsmjI+hTIiNfqxKt2+P+rIkBE8nTnSY42yic2P1fStJu61mf1y372Ac41UKKiwDdhDT J8OEyfT0QkZ3cswaspoNr6ZfJyZkozxGdHC6HWgAkwzOD+0l4lZfc2fJFob7th7ctqJ+ueijXubK t4Z1PS9zBPMtH9LQfnyliSh9zyyJ95MYjPCETxwc64G9vHb1uyT6DUGGu82HOjfmEnoTIVILv14X vvZESTpCjhUBJGoxdHYKN2zOrb5fvGueEL6ZrAC9a+1YbvTwdb5tjydSEJ3YM7Z/Z5rTkKfyVg+C mk7zuILMITXIpuGdsD3WE2CNFGj5EWuzh9pEthQqh78CNEmXZNxV8j0nZ6a9Qtzf7JKecJ8Fd2Az GBpDWiadH7a80P2WWgiDZLd8sDviSTMHN7ZUuX9P7SHYYC5owEOU0nGrGqPlH+Cw9d7rIzd/jHu9 FHFsi8V+BKDvv9+8PhAiJlbpiaTwxJcOTBHeJ4zSzCB8Tdizm3sQsrpHK/3nY16wuftQZY6lZhXt cMvL1/B3Mg2tbiIo4E1AWaBgeUXwXibV4neoc+7aOAjmUKNrHNSMzFiBhcmlVHorPcY8lAfqdehi pRM/nrounG2bepJtka+zFHPQOaov9oGmG7u7NQ8RviSAezDtpI3HJ6W4AHMcfESzy9u8NIBq4WrZ qAc5rkesCeXN+IddN9bqE7EJalo+H4ygV7KnfOnX6Z1T2fouYOZCrq3rW5I0cczYER7ZZXOj18hU GTJEKjzGmPVECBESvtet3kr12Oca42za4toJpi4VU829psA2itevgfvWPQJFBpJNJTKvByJg6QvX QqtPyZnlR3HXS1JmM0jMQVg/mbftYtkjvCXNIvT6mtsLksKKDpvKnuS0fpOOVlU3M6YCUV/FSGEO HFO2hkVG30L6xXRwJY5BorpwymxoBtdw/wn1At2Gu/iDg5upOghelt7byhVf/DoFyCBUG1lmuSfU 8SvsHtMkGGacfgum5NpYGM1v/x/Ffz3Jkx5uVVAL9RGfJ64lOPRse8dg1ZSWqq9llkORGuGXmK0R 1tuDfjCsrpqDDtoGXbciE7h76QhIOQNrkJIbl2BcPIvKLluaRb4Uk9DeLKrGYWaHIpkUy8Vgp6PW uwDeh8+9tZB6tceAu3obfyDe3/cRj/qwwgeeyPe13nVY1dAu+rwBjdGRJ0RnqpyC0GB0c3YOpdGV HGd8UoTU1ICNgo9f+eNRdQF1529sCTK3eGx7/hoVkN//vxTx/AGg3C8N6DCPKEBJDlwExi8Zfu+9 49u/HMb3+dAnDc5vdkYc+GpzGW4NG5zTwPqcaov1X5C8pRguYhXFKXJF+q1mCUOV2QbhhkXaevjN +um4T72I7wW7UoEt7MJF7qZSFotdkT4jLxh1daReSSIndPl3f5kkuIwdFIzXez5+BdCHHISOOAU/ BtXxcXtjSuhH1Ct4w6bXtvJJJV3XL6Y9LRDW4ajUtwVhqNCvYFRALjU15ByTN7pNo5ZJuI8Ehotl r2gWujEV2aWWCATx9ETjnOp7SpIxYg2Uk+YIbWP8Vs5Rj6dZMJA9i7Y/heaSqKV4VOL6q1zEsqrM OxnJtf/biYRaU/qtuvAeiFVyOdrNgbj36FhIKR7bH+Rrsol/NNT9lddcKJVkTwHuCkAvVeF7+5C8 GKnBTGjhVOJKjO7XjkUAEInfCf2hFZ6+w4vMqcbaUdwB7oqo/1g+vVBrT9Z550NE938NI4KeKx9v LMry/mu8kFvHaA9shxhbKroFhw+D3azeXV3AEoYbZKEQGWbG5RtDTL5rWR5Cv8IGFjLOP0tvK6LY EgsHyxHzUQPI1wonja8xHRORMIckWdVOCKkGDDqr+1jXQae6fjeoAsP7T0HoXF7tKPmXBiYZCMmg Jsf6pN0cEPVegfHkTfr86Vga+HSYK59rekHkRMVWP1YCKFXkcCp/fAR1W1p8/BQRB5vOw0zYVJcC zdoLGBxyGoqwYfozYXHToAgnt92+juPSAiIMMGIaTtHnpHPcuDeprMZomgrVkYruyVXkmi1B88XV 7Crxzic1FywVxOudrSaoa5aoDucFlvXgeMf+1qgmowAmGxzVuryrRLrN5bAlVrearNolPVchPpXf J5NV2f95tVRi1+MOAiA/lXigO0omYqPgQCW5WUFScsfeVQRHwTgeIyMrEH+rUoo0QuLVPvCYcur+ fW/4keeEf+nmTIlBtk3BHUAs71iGEWkyZFFNa5511D7kzcElMEpEmoCXAsMeEhKf2BcHkCseGRee m3eY5ESus9lV6wV6jp+LrwKOdedG1I2/LlwaO5id4NZVQGG4mmbZSCn7/U9wlD0nzo+qwsfCWiGd P+7iFImHdwJcgnVeo22RbHYk8S1yIJucwN/sXZPI52rVwYn9/VDZsGwd0H+Ytv7cdobz1VeB96Bk OiqDI88IZl7b9/IOhuMDu7ha3j1dkaaaVpVkMxdJbhbNz9yf+cKAwSuQ3W9uvl6A9ZKcaPH65QOv zPYgxgX9VGxe+LSPE0tYZXLwjmajP4vVTVddYTY/Z5NxhA/jI19rXk2l35HU995ky3J7KPcJuZHS CnkmRXs7IZbBbvIPIwmkBpyMpR13FXfx7eDfgBEIwFRLdti9ZMYEO//VSBk6AyNzklK6H76+wNAE cR7qmbvSbJZXYnNTtCM9A8IAgLYtl/LMnp1Uh69n55RBdVhcrWJld5zUKc6TRAV+oB5/Tk6uqmpF RcxxWG0DdhTXTHD1KNWZ7W7QmqVOVDnlTaNqxGRroMzBVdzk4vGzTran8/Gu8o6lQI9AsqzFRoMc zgcS6jfYC9HUJlbZwSJNf6zj2oDAn81YsrgAlHkAAThYb1pJKCCwfSnLfhmGFqtOHtDlDh9GmeD+ 6S1dLpWjiQE0mPK316s615Ij3G7NZ0SuWxYEhjER694R/a3O+EMjHPy+TSN4vlBJ9Hg0wrA8X6Yr r0WX0ozFaAa6eSy7UVBcJPaAaJGpSojRFDjgq2U8NNMHeAMRFFMt9Nd/Juk/IoXrjEiA/yOfmRXK jRxaVALdr25BdgTkPa41uPnA3hihafZDwvEXAIU2i0xy7UtynQ5tPQJT7Fc/dtuvu/4QSwS0Ir3e 6L+DPUlO8Wn7yUxJzDW8ZsKtAWt8zdNlNzzXMzLLsy0Dmv/P5Q226HG3Zdg7npbo1fqpYKmki+JC KeFwFgzxJyHWSuoY4xbRCjc1Msp11jEdUJEgtOqGMSYiPdwFsvBj7l3a61aFHY1nhCmdBC9PlRIh 984/wVKhUV/KyKbNLmVA+4ev60Q1O2uwTN+7H/Ejfu8BryrtuO7c0WoYJbrUTPkcODaGEsHb4TGj II1kccEVR2/lRxacUlQLI52ap+CC/vaTw5UFpyDjqI8h1ax4MnyYPyrh++k0/+ub0b8eVlTm9gA9 h0gkjtvoyDn68Y7FTNHqLw0lYqryfW46ZgUV/6IG8KEgy8CBEqQJenRAlM6B8ECB9EtsvV9LOU2t hIdc/GTqiQoi47uPJwHzeGgXxNQHJ95Shd/WRYwbbRboNdDyT6BRYaRludDmY1cdV0ws2W9Jlqqk E72OiY6Kgfk28y7JYi1AdKSMQ1Lcz5y39+tvngIvN/MGdN8LJ//5tssCemoTQUj3Cr9//+EYNNg4 /hrQ1MaftiuB5Uyhd3/QDWwGXQ3Ze6qfZ6mfmF3fsts5Cmsdr6V/NrRz9zirafODc6WDGMpAN1nO An3eOL4NZANAhnR3/rqBmgoS1qTB5gkQp1Ue5gDYQkt5Hn94iSthjm7mUKeqF6nVxbj2RQ4mufcs a1ItiD23Hn7j92mMbfw+E+6OYZXihG46vBZC1uvu1NDB7gCaPwNGHZ2aJnHsFHogitfapLcW2cfK uodrWClcPXe0D/hwGfVEIR9Gb0/VD05e2E9brR0BntEdaAQsJyADe2IoO/EI7tRbbiGdPB5nQq1T 98hGBDX8s1Nmf1E4O9jRKfZWpJvyWziV8ctDNR0m84dZYWArrGgdJmBNB/paE8DxTkzRfk+d63G7 KSK1+9wWwrXxDFbBfqHL4jfZVQK6Caty+o5YAadQTs3wgoRJSMBTsIYUdKf/jZe2Jo7u2TMYDdEC WIz9m/HiPMcUAWjo7JWpjpBtvaoTVlc2o9RwiShImg9eBOea1FNCHdtjXv20TbM7pUBvZN2XQdgx IApfMZ7/DQkkMugSyaqDxI9WBvRPmm5ZgrB9ZhrGhLC3fcXfw7EMSVB2zEcnFaxoK0nF2nx7zhEk PQ+SUozs6B+b0iId3mYw2DsiKF+skcbZ0uI+th2VE5XK0X6v47YlckmUyzvLGM9ziVqmz3zLbYsu /LjKIChTCHnM76r9yPCbVdZEm3On0b67PSHAmP0scv850Mu8btJUyNmdLgLIk5L+YzV9xCgVNeOs 7lFBwNCJDzCgoIU14XFSFio8t9+GdoNtjZsmr6qNclkS1reN3C+p/lCxvkO/+54CA2Pfpfw8XRLV D/wRLys3dZPKrVVdDvsRCWak8r4kUTGdhx04OygRwqBCmA9T9OY1pOh08EXnhEbbpNxcIE+HmLAr l5cWxGMIBq9R4pmBVIyvQSCeOsSDz2+D+/C71OrZO8u1gVkb+fjai3aA//K26+g2HFMCrG2Zw5ZD nLKa1xAfiq06C4lbngibZPaTDiOd5exuJOoLLCeJ/JMmzcNUvbQljkHsudCXE83fYDmmVofnOYAX kTOAQmJN9srAu2+bz7JZo/Pd3Cx0EchILDoWjHnTAWjFmGJQHYdHDX0G/5Y7lIF3OsqGaJ/YQ1CR zXR9NqYTUr9KGw++SrznRumdvFcW96hFX1A/iFEaojutMebh0RgFWAUh/apemzGuhl7jfnFVDEWX OxX7WO1so2MN8D1KHJv/JH1pDH+pkEip9X1DRl0ZabnCS9+I45aMFoUhpYvLdUxZDbBLRaOWy61+ VGrS0fYNTDvOsgO2Cj1H3j9dkMs2ItyKct4c8VHgdMPY981kWDMeVFZ4tZIhECN0Nej9QCWfs+/0 0wINM4Zsy1fGtTfAEMFBEj/x6RGK3wVwIL3HrRPNapW8KrCZPZwfs3zVM5QLZOiOKMwosYJFEcNW e/bYAzKyhtZgVcpPi2uTEpeGYHIuVZqLmdACMpAQ7wKEeBq5hZZAqVNl6UG6hANXho2CYgF22Axn A13HfzW8euDoI6a/4Obtz/0w0Ua0MujTF0OHDqQyyPZQi9aqstazWTRZ8pIYLM1/6jSvXsyx9bDK CI5WA7c4PDw+memeOlwWrc4ahr0ZaDN2Fkjn/Xa5xgMw85F7n84cA6yS87DkesAsn+9KOUZUQmrs 6nNmLGtiBXTU94LX0wfOWz77FICWdWxAZLN5ME51YHJZfo7ioAICDjNlDhXOqLr5XfdzyMMUSoVu uvj88UhboGxbeSgZl6k8ept7lzRd746HwUgM31cdMMlz0lix6AIRPE3FJ6eN+LzhOC7Pt344DNEz FJUDZszV07y2bq+603RU7wNwxyQdOf9f0blXCHsv+TbxMuIM+/rU7eTHZ2FwKoBEYLRI8ZJ9C1F1 peiMN//Dvz3GnRSl+JeYgVCr1Bareb6KjLL23wpk/096I6vMNsCO2eXdKvmEPTXctBe2lCHzanXy SKk4qbxA6uwUDvIHDE5MTTQxj6gs5kCUfwvX/xEtiwF3fDYWLl/Oxmygqh4SMd31LW+jUGF/RTk+ eC/VQYXIH57JO2+Di2VA8K3sssAxg85mZJ0jIBtjQ+lqVNr9mNBqANNkFekNr+kcyKraycF/cZxg t1jfPLBPKuqU8pL+If726kS4HqHnsHzUSaAibidiz9tt6naVaouO91CXlbQlDOuRbezEQtad4QKV 2N7tIBmwZhuia8d4ukmqo3v8BkI+QoIKGiGb5usalqUbYsrJ4hS3vDUiIsjX6KltoIveC8mg/c/d F4ZU2RlmqUnykKJwvetHigYkIzzs+/22KF1hwcKFT/55e0OfGfrGe5RVfljwBlQqa7K/pQOd3v1N IwZiCRRAYfa25kNDg4D/70k/GEQg5zW8Qo1czmhY3EcAGsQYwV0JdfOp2ou3tHmxJw9Ka0lP3mQC gN/VqGcBrsH+t4nRV26iPCNQ8jvv/Z8TTPgpxSqQ8I0AvWczTYxZqiySdcM5QhJPtZSE7xQDRPis h6Zd4A3FQ5Rps3yPRgaY4VMJT3o6/zp4x8BI2fA1huJ6j+eN0yTYEqLwFqR5wCe/Z9zlDpLi5DsM g/6csOHoYMzlCKO9zBuecafCltmGz4wZ/RjnHv7maclqLL6cN8RAmLH/xgPEHS0rC57V4S1YfmkE fwNgjYhxBbaE/vui4q8tBfVN8g7v3o6xv9TNb0mYo5grwBEK90f9ILrp1E/r8BVETRgwnzFjAz9c 1ojGP4d5DRUd+Ci1VLSx3R7oNTlWDcbG8fh+W9D+Ja7+MzX44Ytgd8pyccSKGmIW05jXA8D+o3s0 BJmYs2X+mh72OyvWj0VbOCOz5+TNRljQDdBkGMohCo9G1V9h+9rlMRUYnYtu7A/Noi8rhcrt/jj8 dKCQdF+UBzvvje6qP8t93z0nE7lxMJg3A2JjABD2h+EYsheEuFX5nxHW4oaYR8Rm9VHTGuvh+863 RnGr810x2fHNUFXbUBv9GfKSk+4UeNWf0zAjGg1D5s+DabtIFLp+hdhktw/uzqLdrnqFZkj8ajTu uXhYWRAvDXrD5r8cHYeWo/AWmomOg9rONI9gGe+cTtTZkxVNJkN+tZ69yfMcRUkvgCbngdmhk+zw wiBgope1FwTsonCdlVzGghjHdIYMxNzxSsCb7Mf08EgsKxrqirA3W5NCO4Ii8MT1anrUPSrZF+sm f0Yn5Be0XiLXleFveuhE85Gi1X5QrFXjvUZKDFCyG5PC/RA8aYWRAoTo09hcEieX4F2WsMSM/7hw UbqCfEqmwOJPTCZTzvT1yM8naNmAueX3rnqQM3nv/X5hXmCJdWD33hwrglZaB6ZMpLLtd8WpekVr H6BihZKyeP2lEGS/YoNllvYto3TJF0LLCEEn6TRdWtt2XIFKfVqKXzjJhKa8haZBYTDPyr5RGnM8 k4ercaFsZ1zNpBK/obpV11W/YTFhqtgFwbWR+PpbjxmFNjL2bFiOli3ZAjqIhwL1YzRHvn4DsCY2 cwDjRZssU78gQTDkTmsrWZYOiAihU/JPj3FkuXLAxRPE428gF+ZhjD9YjLAjlqNUaRBjf/90EiR7 8fr1kg63Gwiw1y2txUw3DJ8ngPywhOtSkpxqH5b/xkeX3FIT306CpjlSdCxsYHRSm+du6VDy694U CaKvIuLbROz3lHB/XVzTf8aEWSU/LiJqDF6tBKQYtuiywp0xHK99xTTsftPFfoSNSAUyZ19MPMxL 2qWQvWUBZkyW9mcurJzu4F3Fwni0pMjXfpcavH8ll6u/VlNwt2dV+ZP6XOdvR9dLmnFTWZUkW5hc ZfoVaXXzRhbppL8pCe+W/ZNnmMAdVdTS9x3cQQRY79q42214/cfKba4desaKVDhlBBhpSJk/B5uS nJbUbIovrcx4dMwg63mVrD2OR0jCro7gW5p03gYMcUWhU+QxBAHkLNoqn2y9lpm1iPdLEj51ft3F lQvglWl9VlO2JsasA+uvni55MPhwsJf51ATXMQ2nzG7nt6oix4u+ZehNCXTnHZC8DqK22Le3FdIJ KLGtq5DfL8PJXoAGgoYvLg6BrfYOizhPrV37xsemIOQQlDI0DIiJ4YkTEuITfGMsCPONOKQAckpB GNO126Qr7P65vUhBLhz6imnjC9RIAP+GVViI92i73o1gugkqj/1vMbNOooU/p+HTqImkqMJHLaX3 7P7T5PT1xRimdr1cJuULNkLSxQVcBjmsBFDtkkxJo11fFCxwAfh8m8oSn1TYNtAjWHBCRlxiJBFc Z0GuMmd/JO+7iTxMtVByYUVQJjI1CMm9THK6vroFB+SCxbtRTebGLPErobqbAqW1cwelh68wJqQ7 6FuhZbYZKEoK5syBCbV3kYcM3fD0D9o/Jd+P3QtimnyBCLjMChOLpY1BW6OoyCcVHjvQtLaPH2JA zXYSW3rRtg8qxaVkoO0x1c2jkpJvREMOO0MNprLkn+KOlEbXVRCOXt7mycS6Kce8CIUwH5V44Hhq isWsVzbiKEHwkjRAHteohPRoUhwlrrTJ7yv0Z7+D1axgy8334JJbe56/7p4hoop0BDJvXgsQ96Jp YLBnUpbwloSp/WdbUUyRcmvJ8ShMnb0PfjJNTLYbmSqsDhBA23SVbeeEXS+zOKRYy42rmcEWhNbb H9hoD7tR1WSSUblHGvST12zHthyjv8gnc8q2fPHUBXSo9BJbmvQewmygAdyu3F6vHhpaYt47l2ud 73Ks829JOLqZem5UXp+UOm2oJEXF5b5ltK7ja8FP/Y6Ts40hXF7h3BoEk/srcUZiIYZyBf9mtZLg gc9dQ+eVmnnbr2fmmzWG2PEH1/qpv4JbfXPKCR4PMtgtpeuqJxICnEmerctQoLypjOQ3JK1YvWYu bbRHQeefb5MAcznqCpGQFxvPYxUSOhQMWO+R948SXcBfqS+hBW+2sfOKCl2Ek/ldTKJEgNV8fJ5u ZM0x3ozxt71cXVZMcGTPPAxjHMTaPSI/g6auysYU5yAPehZVi9iUT6pZF2kSYu8YbqYd5TL5KstG D5Ss1wn2tcQBeMEktamVkA8VrATnkDjQEyY3y9lkZgZ8+xZdE6W2vzBDeAzXolOXJJRJidKi3v6f 3/t8S0osrQcWO/sM1TDwYDyScVwcmswkvzlKb1uAsDJA/mi+w3/rqL0Rcd06Jd0M/u0vjPKPXUxQ a7P1H9eRUjq29Kq1VzxT3kO5xLOu5PCWHcBmZzClJUoCAXoW/bFUfh34Ln51p2q5PpA4OW2m61ib yF3ZV6hKe4rkBDezrL+lY7xZPfiQ29S/tTCoKjZCrvk3HW+OZfi0PuQKaVh+4OiY9Pw5HWgjPc8r 0z6oypTrfdE9Is8jtRIVBcmdJRYRh8A85/DgUyUTKEhoxW4LfmLNghToEEHWHrt4Zcc9rFMlNcTB 2pXaIBzRYlcn22UH9ztfVkwTsENfes3693VlthDtpWY27suk5erPGAHvARZqScqzLjgEIl8wNXcr smH2wD8c0zfT62O8uEnqSJ2gg/uYvhazvzlidf1ykC07cveBGNDvka7/gZyoOPDuH6+U7xQbGCAk YpNtujii4bh+uRVxgPyCppeuxVa7W1D9wSbnBM1BOHcJaQnUh6Ep37wenrfyK6hILfg7q9Z0fqXp 6VXVsICzgWDLlAiBxevukuK0ckeLNJ/LmLAGl2PDwp0p61TFrlRSiNsc6wo3XOK2QHNor5vMeum0 FJJRauQGmVG5HyJO9BOB5fSL9p+UZ4VEJZ9997lrt+PX6ce8fUrBBWMbVGm8c+UX3G2Boapb00eM 7BGPKlPASsPEC4kb+aVTYjHZeoE71Fchf/hfRRkerolpBi657jNNt2a+DAC9hY+l9PZXQrIkYyxC XafPJzqYjGTIIDFMhwBAq93yYybZrj3OItV7Bd5nTUDEzIDxKu/FoLWYdkU/sTrwh6vjuC7fky9v 2KnmjpXxOAMQUhTt2htdkPkB8nV3fbJ/8PwI8+YV2WP3NQamiqEYxEUSvc0xDRYQBVn0GGzd+Gx/ aYNtTm+eHE+8N6t48vM05J5IPhQ6QETfZR8ZZZQVTJVLusnNLRNbiboVSMaH1kbPKAHSCTCLszlE J8CgKb6fywYfVoF8MiteHUYkF1GOLmVWhVoiHTqjbRiwCuSvWR3fN1+LuG72X79U+JEk7hzmlUuc NPSO3BmD//diWH1ATNAQiyNVZW4aGtaMGO9+29oMbPfI7QWdAuLlRchF/UGdk8CCZgOeF13En2Wf AKhnI7QpZzlTj5Slq/VTrvcJX6yLPWxjtqSqn+7zV2JQtIYau3LcXPGXRfdFqTmKBSZZGcPHAsak 2/B/FnM8X2vq7dq7gIZZAuXH4oKCkV7E5IVctfT2e0GLDTgJ07Q9qXdcLI2zCCsIBkPdeMy5U8AN rUkW3rvkYNdRBYY19mvCGQJ+mzVNXDAO7Wwcg6RVwAc7gC3eAs+cgWohYc6SztKUhtX3xn5GGjHp 9k/2JdsfiM1Hi7gF67Jei93xRFFCtV9fhhsOXCUGwFe7wv4zCh55e68TqU1k5lW4L09mAiwdej1n nBKGJ2FfrncS941uZdjPLKNMq19/XkwyaJLzNZOVdYqaNOVPoo1Z9g/tvP1K5jHCRPmjVbTdGgIs DP7P0+MIJHSgACDc3donK9aAe8acU1hmLIMVEZweMoYkfMQapqH0NFBwutK9V+KIUXuHb/e52R2L KQMfuU6yzHJ1v7wls6UUc8pR3qf+dgRreq+IGNYo8vKRfakcAMmVQD+jHp7pZb3y/LH8gUCGrOhP koMPqwmiM5NMWUkahsrwVKI+7acOcBDFPKyp1FNEtyilSoOnqTAwM61Uk6Wx3ZkJdPwfw7lT6D7P uvLDHIE8xqWR8Q8HeWlcNOsMzQxE7icdAWbfSI8ckJa24LjWhH10/QI4bFz8MbNCLWOZtE8iaO+n cxaauhAMcCJTJUHkdGtp8e/UgYDgPoyttWAJbl3w6xNW/mrUNAxplrRmG5xAfidx4yE59m04sYty E6bu59idu2nQMMHMs+dGfn0f8YCb2P/VaM9ZO/vm4bHmo93+baqvqUrUG3t7wgqJDQYR5+pAOKX1 uqC1fym1VOLxw1d1HVjvJtjTs2NSK4XKfeIRuFtxOQQS8WzqjTkVytd3OHwLgLawKcIEU6CGqeKc Cy9f+3Uib77Q+FD6FSjQPbmw5kT24yUAIttdXtOqjax7e8klvwVHixpEVilVSGOkUxot3xu5qAJ6 tqePiHAXa0RvNr5N5VeW8Va1opoJcoMLm1FjOdYKskweR49szaLtFKAyfGWTat+raTMO1SAaX1w5 acvl4tfzjsy8v5HUPOOeISTe9kTesGEDlvbg+7RxEqFov+BNBzOL3tkPNdsQdmcgvitu46s+PK21 abop2rODZ6jWnQJ+FjslYiMQjv4J40i+NnCrl1sH4EHqCqcsCvo76HDaztM+RAqvugpdilLSquD2 KiBhV/3cbvuqoMdMBaCoMT+ZLmY2joXQzo0jMYqnrpg6XFIdOObMWVbKfOV5VWmxRogcYMpwwMH7 JKLrYJUXcScAM9NV9AUsxGMuVg1Lmqnwn2n/kbKvTQ2n1A3sXaqcsWfoRMgsFhn6Wc+s3IBnNPP7 o49w9Wkmz+6GnyjuLrNdI67mys5RZWP9ZGjmt7QR3CX73v/FnSg60MVeJOTzuUWHe2pKCuls3yYD Kt8mhrcGGg0ZPs1nq37RuHxP/o+ATaIVcDUi6azLIkWLoYX2EyJYiDESyyV15LpnXjcYvp+XHRTt yWQxPN/B31gebxzFS7wPcCTpnYb1SUSvVe34vZxjSPm4ajvptANTY5Z3Ow4twM7vzW2b47+gld6T VQ2ftOSfxH+98tt4lvlQMDuEmr+8VrQm0oR1nDAYoS/Fc+t4K10VXOZJ7FjIfwijpLSmVnU9d26Q IZuYAYASolxjcIKNTvhRBeUjMntaxPigQt5ycAW0YRQGDQF6cEuEw74u4g8qqV6LS+PCIL0T9NHX B0HgPwsSCfsjzScr3hbWkulrRJtNa7fzaBfBU3XXlscadBTmUA4SK+2/Da/JHeZb9SUgLwj4FBew fHmQN2rE7T2iKfGlTb+9JrmoR31znna2heZMHS55NvvX7BdM9SLkv88Y8Q8JOrCr9jb9SUzO4FDT Ka2E5mY8+UfrMhiehCgDdv/+uUvVXKSuaRRhhkHyFXzfLASF+fx8RlX7el5HrJYrobvfghh5I6QT V++RwHJhRbGKz0Xu+Izw9/XX6NnFg1focy5iNmDbKkbxUHrZCTA8ycBefZujBAo+QpEZapzqqs8e TUbe8t34XXkFs33e+y4fiJb6V8cXorCVu8ivUU0mcoqjfil4rdokIdRmmfY5pSY7oYG/E9WhcSJ1 ToCj/8nJKwujez7yzOO/tEAe2ZMPKGpf1cHkSZlC++G4rfbJu//TDspkhmqUxo9e3Zkd7TLjPS5B nxwd70uF7JKRS5t3wTsyIxHNSB+IQntCPapb8EgDghlVQYjv1KcEKujALQGMDINi9z2BRKmsH0tm GDU7lPzVnXj/1IUZSB8BYqFldsykCao7bvHCJgfbWFVruFgUs4pmuxRrPV18rDAtvQCwManBT/2C v2NhCIc0BmFfk8iI+3xW3tFdnKtmgmBQdAg4ZpT7JPhbqeY2HYICvgXeSrM+mIQ/YlMaoX0xFtUI xmtLfKq3oljtU//JjnBgPIUy3eNN1pQGCQ651hT3Y+YyZdj6UwzA1hMGQeCKgtWXRdAH2cFuQA5U q0KRw99f516dsPWO1dkGu/9o9XkjCaa2RXpShNplpp6KXxcS5IMhyZvHN+q0RD7X/TOkjlS9GJkv Rwkt8rR5OaBebiPrWNw3hxzwnHYKM5lVkTP217L9sJhNWUnz+H3zEH5nfy7VzUjJmES7p1Mn1r/p 1+VMAjmoci+4PNcd/6GQ6MXXKqIdgMVBxLzl+q+be/OKn/SKDNIKfV17h/VBJci18ElbtEScPiP8 yBLGItFXAZ9R82pp23d7S20HcTAh+T1DKRdrosQZ/Sxtf2ZgZsb4u3Poz/NFECWzgFm4fk/WgOwx DzoQ3w2YoBBxUAZ3EGCSOLfn0tzHMUET/ir1JjBn4aLiL1RuuYPdlcZBk9crVedRfwVhl2/YlcgF 3X7T3V4Bn40R/UPHEMb2KEXkKjFbMBjWLr8hhG3AHDUE8qtsEUp4T3mhkNtkehgybn5vVdqSWTOO 9bkfiWkbCE/FIMdUgOTjBq0Bj9wXYsvBu6LPNcrIXAMwTwB6EZH6gWzbNsfXUVtPEKJFiHf+OWHu Z0PdNj9ggFgdDSJlnBqy9gD0ZdrL6xU2bSYvp0dEMioxhkRB3JNCQ9b/91prV0FO0rbwzXeZ+BX8 lbQWyBqQ/tJGXN0/LATuiT2A6zA9Yx1j29lIwSwyl1Qek5s50eCZbJY8Sw6oFEkQyq32W9ehKUf7 s4/7Mhs+k/Yugrmgevy6+kgMEqPttAD9Qwwwp1NkQdVGBRfQAMZqXbYV22BvMy26aGs8UDpVc1dL i0IEhI0U4Qo+4VlL0eqvChwhPJ3cj4q7QYTYoL5hXB0x9E2j0yo81oYjlveN4zQ7EbehnSE2pD0t udZzAiyUlNTxTJ08JzVZGYOjbOnqty8hCVXBiEIBqTm7BUuAby0kVm36387cf9pwN0t2uojgVfzq GGJwEJ4woTKajLTcRth/05NUBzY/y6QMZDla2OCMrNspVSl/xuOeyKTtE52vzFuPE5o/FOIynzod I0wWi8rj9rI8v0Azsk54UzFwHvuT7W/5C2UxPkYf2kphD6k53JD8THxInJAWkVPR184LPhrzhL8s 59VVsCH0zS568CexTASbtqJzq39CpbVGyFrQ5GoIzb0LfTmWkfmCUc2wPOtZvOWNOQnohvCoIFcg Iow5GqRoZDldH3GU6fsW+evyXTIFK+2F2y8z4H1ZtClXBGxBDVHiBcNfxmzKmu9WpE8Kesnq9kZn w6IYeAt5TGByi8+x1JUeVpymMTwjzT1TW+Dj+T19+sqwd4V/pakNyjzR83jDETCtxZmalmBVwaG8 Tt5DJYp5U6swPoqucY9/sszPSxxITslw5VqnRo0lk3F8gsz2VqSrK+KC6yPrxH+EVfAKB8h0G1Br zTZFpzrgbYPBqdO1OqkClWmaZZioThQCWqz4bPOX5094urpbykOaY59xDti11Oxzk+5yAgclytkB FEecV4QzbeF39iOjcIlNVLH0hbpUgV/mo113sd9fgSMQp8K794fZ9zJZukfefbyAY71rUNI7baf9 CO9hiRU2B0olgLWuR+dhjHNoJWJKlzU9bDpGHc2nnTNqoA93JRdgQezWe7+BpC+dQ3JpFUyXJdZ2 xR2/vUlDJxB5x22vrakJcXJ1b+8Z64UgxfJ9cLKc/hzk0W4Is/+ILYpgbcUz4rF9+nWeM4PoGV8c 5/muiH1hDJzynwA9xRHErUBdItmsDE+yccUA8NlMp9AjU6m/sZS9xSAe7nzn6sGndOuuSthaOBOg TexMzcriFxmIQMJc18gEyO8dasGNYkvDyqQjLaQVMsg9lt/BAxZL/ztu+1N1JQt5G+gYMpK1RQlS lIOQ5TO3B6CPTxA1vx+9sfeWD+WCZJr3mfUuW4fEguBJb8VdZEU0Xhipf2aYnfLFXZdxOAYqAzlG OacdZ/YpPKiYU+F1P4N1zbBGvcFcjXnvvQseBSyvG1hPdcpKMKE0ZNX/90/T3OU6TgphRjZGn8TM aGZwAo32O+oyRG9umk0WqLO0/luIX6P31/+lwZcLmCvZgFK288CmwGOw7L8lsRk3GyQJAO2fIyFD 0XXWk05RWfickrpdb6klQO3n+wO5FwHcqJDg+li6FiTBAIuRg2KSrDVMpXMCta2nsFlNq5PrruH6 Hdf47t2lck1Exivh+WR3SN4vrOE9EnI0scU/2VK+Bj4SxG98sCkWL5QIjlujsIDHeDAh92QX8i2y mujEzFc9+5HwpwrIcc9QjPzJhqYtX2+Ud9szNBoctQBwar4Wp7W6beNhQz7fHudcWwzHOLsuw6A1 /7ssAPyCYHSESh/F3yNTY4t4hx58JZhRXqq1xG1jdnUyI3YCUx7Q6lxg0jDcwSKU24TEW8qQbPT4 nX3eId0vc4oor8lEQ9khtlJbHxPya/zS0X9CJvtQ/XgLxa/pRW/SPwFHuoFeMqWPzZMgQy+hfxoO 8G6cDXFT6E8+ZD4hx/KlKY3WlRAht4L/aDJwTnyVuGrdbblH2ALj2+5kENFFeI9TscnYMbmBY9Zo +BI/KV9Rt732sANc0MJzvQJst8MoA0yOByhyzYVb0zoCtGAwHdJu7a3i3VR05XDZ1B/Y08VJsv1O Vz9npbq7TMPO0lfOdxZxyF9kjmDGR7BTLsjfC4nYG988qorE3W5saQfNJIVTK+R4PCtzjfz2CrlS QfUuVNPhBTQJW7hJdfub56RXuRt+TCw3wPX7f4+1BzwCtmC8uLVNyjCpRMjZ19GPbThu9RE9bUuy W+p3xRzNYIfhScqkEBH6QSeOGRKwIhrnki88188mACg8KMM0bq0lCSEfqd1RVhrsqLY2kQbhWbAg 1KCuPqPF/XnKk6djBLd//DkZhKUfpWpIoZGf72W4qJqYI4IGG1KYfJ4w7J+VDY0mCkh0fvOQyZ1B 2R4RyxqY26f4uTg/4iTQxMupFeHj3mEf2ip4UIpeyAu1LbNqSZGQgA/0syTrDQkk5vsqDtv5JdrQ 0EnwzgOVGrs6RD15NiJrIlFNy8GNIBiuTQMdBOBPZA+7wxXSf14BdBKi9o7Wg8VikbAUArIMVh1C y8K061Hu9vngsdPJfEyLLGrlJmGJhqUetppCSt+Z5vevZVhZYN22ScapcYz7k68tYS0h09YjNgDz NwJ08Ka5d57eVQlOEurQXIhFBKTLeYMV0p0gNJQQb+aJ2vBeUx/Oc4tL+n/wThdXOvUdO1slGHKF FIpAI3XS2VCxdWuAZ7lX12jVoNchduIM0ILWYoVrebednSpVCjhYwVidA6kpOsp/5XDl4wQvaZ2r zGt9tCNDRfNO+piy8wjMYXiRNGkiBzhYMjdIZmzMlQ6acPCu4vOlK/1DkFF7YOBWQOU4K/QCm2aP rpVfc/kMwqjliTx/cKoUq9rFnwGX/M25TEzI7vj8cbycC55TRNWCIx4H/LQzJCfw69qXyqgyvVP3 cskM9LQLvqRJ5RPdSCUkzsE+VTJrDlGZ733gaAe4lGFHoZ4iYfXLB0rSA5ZQ7SyEyA10H+eeYA69 0LbOh3fRAUw2rjmgJB2PckfWw462Eb38sJsEWyG27wIhJmFNPig6+o/vY0//x8JcrwENqJPeKmH0 40A6DMY9nRdT5mGgZVwLKuq/EiIoeT55vAXibIxGG+y13TK+OLXa5weWjj80XXNQvYfjYKdM7mLY eR32v1MNiAUEED6USeukuEo8iJL9dOJOLcVhfypOZHIfpXb5PzvNA727GxR3+1IJy37rvV3Iah4M /3QbrWlboCxzZzximIC6/MzdxHekuWnEc554LYgWfD0QfgJq13Qqj8KB4KyT7hH3hqx9yftqysDg wHIu2QWtEAzte55dKQhERAXZsQmJ5rbeIOSVw/Uu11jGtbbFcwaaMSxQGoD+3ADJxrgRVZIcJWdH baO0nzJAh7Lk9wmus4485adD9lCtHFoH+Et1CR6KDUUtp4RYlUs4BKS8sedBxqf86f8hUxoSC7zS cu8hFyi2iFNWztANH0GGN4HC8y4vLXbqe+DEY/lBbHrvEr+4zU94YbXMfTPCCcJElA6ZxIspt4GS /QIPX2XNH4s2a6VNHusPOpRZgG215iKUx2QxW9WaBBZRj9QaQw2r8PR7oLcjj/ptRdLH+klRSbfi KKhJoKhvl0hzkN0Ne6rjru3UhSB9NSWzscNOtjXqZCrbnUaWHUt6D7w4HZEcMhqXiw10AChDUFcd SZWzek6T+ONXHrjTqeFTj7FLQvtkrG10w6OBL79jTfSXceZc+Z2kou/urEt7Ta3zhxu/u7hxOPhW u2dORL7Aqp7Z2uSj57gyv5+w3canwRHzt8i6nN+9SDWYqJHr/4zZQKp9WdFG/n58bI9ZDbuJDZsr 4cfuzpI1q+vUcOcsKw31lgAmzJpztL5BI6q760kjCWpQ6DcMnNt02oRFuvcoP1k2R3eGPEir4j2v 9DG+1/g2bT2Xm/cX3Q5QF0+J9sTXB+0VTA99rbs7l+vMg9G66t8uHyVdGIgvZbqBwLTWkZYelF6T 0NpFE/+x4yoTbqoCTi1S3wuw5FlRTdVVIN081SXQObHyEI2G8w+Ds9eJ4cbsQ0vAI4RCPRmiGhdS IHI1Ch5mjtao+ZAavbDUzD+f3CxmwOoUqnJuqSWuLo5i1kSW93ahNQ6gBAyGrhwaahtZ6PMa4sac XRHYIWeq/OIt6JhWROgaEAPrnFk8tJPXt2HPpxGRyWe0ExdHa/4pr6XJveWuchDYHVQNNKmp0edG 4iYRH0lxi6KBWHpinfjwyRh3CjEtnv1Aj6GpsKmwycj+dUTzgamdSWLhyxDbfyI5UF9sOX0+aP2H MDB1Y1ZwBRoMEEEBcPNMB+r/XW4k2/nnFjksWb27bmDfRZDlkEkppiFWI2zTDcDa75oBdY9l7axk PXvcB08sOkrbQZyAQ+ajHg9b9T6GiUoCkQTpGVGYIcKRSEp6TswiLGQ6I9KdBsem9AgBicq0dmsw myvYUf2e8ZUGX9DHV1T/erGk04a/9QmSvht8R7RXg3xfppuHDKXRPm9BHw3SK6GYpzuojj3QyaR0 Uo5HPdQKhIUHpjOB9XNH6+Ksy/YOd6D7XidcZPrc+MqvvP1e9adIBSW1Xag1hT2nx8FPuIoNr8oN vl4nBagVastbUXR0y+ySPKYkSdo31jI6bQ5nb7HEqMOCFCNJKvZvd9NICIsXN8FJG4QYPQW5/3qZ 5GpAq9Ll0QEsmAKyJAC1zT9X6k8vjGC81CEJLwlUqY/p3zmdp8igFSNg/mpSzFL5+XYNsLDCahCP +3nDmzBRFG9bmx4gYrxpDm0SGDQev4u6DVz3Lu+Ph9HveD17Ru6KIHjPPoM+CwhGl+KrDxj38qjD DB0N9VKfYMpbVfNFuIVh3g8GQn/eZVkmp5cPCkv6vsSbbhcTq7GaX3QALVoCK3E8nY6NY3C4bonY JLQUlG/3RfgianHRnXGYQow5C+uNPvm9MQKT3XpmjceyHn/rsdTbn4tasLysylyhkmMsLABbHOSI TWYZ9Q9tdZ/4LTmXGgtprukpmP13YXcGHYg+asjgMZKvPCTrufY6prCt7r/SzvrWJf8haVvKJLZO H8vfUXnLGBKS+ZYdq6hEeNENP7GnFzzHPrdjXGDHIua2Y0+0ts5nt4UHyVRxz9CL6XMN9EZboksS rPh+v1y+HP5Cp3GaqSNYjjD1PFW9Z8OCsvH0ircV3+Joi/IHUGDaHV7BtrXLp6crFQeuRRthz6y6 pLYoSgDiW1ivyhSF1Ei6fxxld+LlHaI2FvtHGxD6I7lAySgDgtVDyrlWDKtDP1ke26fkjBcj0SXk MBzKCrNQaB75XEUhDNs5jMwG1LZoRK6rGN1tuuaV43gs7Wh7AE03L2q4kQWq68tMdz8yl/aQJ3tE Vu/WBSFjIJySivEToCv5hvSwRt6r2RuaWnJ5k+Hmh3b7ADtwxlNrQoOvgtbLuSWnIwKBLCk54mgs LTkOIty5B3MUKymSDhfF2v0odrS3o9USeI5NAOK5f3AqqnvR4s/TFobMl+lWCMjtNrx6DglJyPoz wYod28e/GW+A9mGfEl5temKF/LjVYOo9i4qEQlYrlokMQK6IwcY3ZFJQspmRB/GCdPgDeZDZTZPj a/F+XSCtSmumbRFaL4QFq5BN2YFXaBuca6lViS33xATu+WUFW5N3YxkcUcdhhjwmNR1RxTpsYOE6 i6zTiGhh6O8VK3tyco4E+uWLM8FsT0HwO2wb7tt1favRVQp4EwQwu8T4LxjdiQDUMKWkEuK9Gw2P nLH/GaWVgCLeNMLjxK2DjOxX/CT/Ir08ZVRJKqJtxC1FgA5N5E47atxoJTZYCCvdflWM2sFPCDas st8KAYf+LKJ9GkpDV+LP/MXOlF5G/FkiXH3lcoa43OZBRcf3F9cnpV6/5k4zSq+iJV+1jyn93EUI 4DahPr5pZqzaRQn5hbj+lhLkiPDwj50cn0hL31oT26LADiC2ysLTFynNkFDW5oDrWAYg2YmyKcln mKSssfWVJmw3VcBmTu27amnmBFzwUD/KSbbFZ43ho9pqmeaqITFNDYrI2HyhdHoJFpOLpzZOMHBC qFOveza9uE47uETkXMHo4KWJCYgcqitlBltfkooMIrfS6rS3mpIKLGXSlqBywjg7wJyrMLzcM1cz dXzUlSYI/Y1qseo9TqaiRCu7DMGx01M70vddd5yX04Yslym6oTnBV9cETRPslcRVBaqpUpiTDyD8 aiYi3wTWJ2H6D5ejp7Z2wIS68l54gvmxD9jXKt80B7WX+uFFyXQMiGAKsrFI+00ohU0gEjR/+7eU LJn7TBj7d2BXlQim/68lX+sS+tRuX3sMRUqJntLq6BOxtzUQvkrtiujNL4kiLj402e6/quTNNRew 9W0EVPWnF7EoDsitYcaEjP3sgZJyeXIVmhAgxZWPhRT2IxrIn7hnWAjs0B0mQAZ0S2KBxUpJJwJp NN9KbO3ZlyjRoe8i0lpET538+KR9v1e5GcrgvUP2byR18H/prvaFmKH5eAMV92uaAqQtpi5dZjJ0 iV78ZRzYC3K18FuvR4RJuFtiyfHfb0tw148B/EQQoEpYiZOoMO2p/tqfZMpqD0AoqCQLVuwY9DMP SMu3vGN3DyHYfdj7iRVusEAVa0iqlWi9YAKvyioyqJWSm4o3ZPji2Q9oUCOyxlFYQaKYrfzySD/y kV1fBpJ5a6HCJaiwUBvxRdZ/yiAXcahkr8v8dUpgXuHYEElFGpNXnNlnHBzXnecSvW4ZxwyORF55 3ZCjPg5zkWvjGK4RoKCK6RxRStEGsBG14Y2dIL9TXuIE07cx33I+w3/YkRk0peJgWrI0ZnFfRCG1 dCJLszB0shoVTZ6m21kuLJrDI1KL0eotg+WzhNW1h5Dr98dNxF0UzDrXCsSoVA8IF5tqLJl32/aW IUioLO1H5RglhxtdhkoAiL0MN2ua08tSZbVu2X0bI+956kFnqflm1J7NaTh9yFkAmh40CcPNr9wa qkaiLmuFl95So26fRhzjyO2Rdbgh762Ou1wPa8kf7xbETGnHpd4mnGL1YaWNoKzHJYx4Gms5CH3K XqtvWIKQRBRM5suhdSvvrqGyOWfDvf1dILaRsUuwY62Eao5aM1eDwASlphaG+QEsGdSYEoB6cikh 8qW6NWv0NZH18iSGq+XBFbkKf7tmrlmGLdUbYnTt3IP3qBmqOdN3llvFK1z8tUOynZi5IZ+mu7w/ gK6e8d6UN4Bq5/x2I6eEHrIWQLQbOGuW0p65LT8YLFQ9fUvxACmQewM5v9S/qVZ+HRBUl6kfSHfM Aki94b7lV6YouT1inZ7EDvYewyCzVg8mT3h/3Woe9+JOCh+0h3uY3m8lh5MsVLszc87bMz5R3f/7 zDVSCul/cbEIou4+SRmOUEZHHyZdu6i1Oezbbyv3DYlOWvExKqgY3Xs/4OAbtX+KfCwt9sRLA6Ny MWOTMH31+AopHezvmotD6bsPkTnxgfTQzUDfkMR9Xve3Xeed9usuCIbtVSDh+42kSb3vUoinhVJ6 5b/aAnexLM4h5mq+InFlcwtdx30Wd4qoUYxrLKE4/MFT+HuB8eYLx8Y1lzHysV7jsJn12I9jLJoF gRNJOKX6gLTTM6/hqmzkmLuJdjaXXiC8hBn3kQ7y7QxGBkmon3fwwQ/vpekTQWNy8GPwyVF+Pat1 K/6CT61J62ylfvcBxME8gG7eg/bnHRFBz7T5CFr60Wsu48W41x2S2tPjMXdUnUmCHA2p4v+qrVlw 7IoaklZ0ILP0Zi8rpMTRte80yDb/p+/7UmwnG5Co69PviFnw8I1CvYiYFtxyjAvN/l/q9XdPTf4/ lLpBmV/Jc+JPNhxr8fm5wzlWuVQbLh0RQk/IhA/Yc7oUeXjnVI+wAQJB+FyFiZRnuV3EHmcurNg8 dX4y8Vn0mGYAfiqaj/HrUI1VTL2109jTMrm/3rL2fw0cXBSSjpuMDWdrVGioIheeNNEILMzpWmvA xfTcs7TZOMS1i2fDsI5/xSuDCYxcOklKIheIZ8s54a64J8KACvW4zJDPjhJBL25lXlgeFUerT2Fe KCWI9xKpUnf9w9Sll3fUHtt9RySM/1SfSLpDVl/GZaoXq1N3R+Oy1kQoVXh9eTP9n8RI1NxPdnBr aaynMu2rPsiZTIPSFXfPFjaAZxgJfou68FGoK7yzGpCid1vWu9s4AEk88SoncDGmsXZHFcY0nA5Y JkezcenJ3sqBsdkUencsBBMZwSrsI1HbWmm6b2SwUkGtEntoPOC2P9t+f1I47TOZVFtfUL9kowjM hage3PLjVdFRFSriCNiIIfwTO2Xf77rv9riu2b45p4cKdfkghU2ak7k6pwi6MRgt5Rl1fn+Ot0a0 xPLxq2j6j2UbzGVbOEaXf8RapcMmbQZ1V1caEByY6bQxZmlvXIfhpkGiwNCBkybw3SM3+O+APgDr bKLfv0mSw2GoKkajvzhgBGBz9K8muVyMqeSpIeNbBnUiWGh3XuEclCCYlaPAJc1kmEQwxJtj5VMi +x8PikgsNkjbZg7jXn7FvLFUcLLtWw44EyTtgaUVXbb2QcJ+5Od50OqjACieqo8t7eOr4uWvkSxn TR/jf0SC/lprUajdleRMtOkOcbPU9chHcGl0OCOrWc9ELGBQwJLZWV6oXtoLq2l/pjGdkWeG58CN iQOu4Ok//D/OVP9zWRyArBEGAucaLDXMjI691WlPt2vsDKG1WTeifersLVwz2coTV6VV2N79gRDw J9xhlZKOkmSP8rjGYQG6yqp8uqdOxB7dADkUv0vR3kymY+QPCsD0car/qN9qDKB163+mleSIYDn1 OSS9o15Q+y21r90q70KKin0KO6//itsvl+g+6hmmspapIBX3oYniOUUHCdm90SsROYhNe/iS3tQU P1FJD0P2jTMYLDBDcMuZ7L4pZQ83d3HhMpgRWnDKnwT85Gbf7z+fLnBUkeI4jsaDZhYYQPeU1M6A 1xsnRGVwdOuTvLY7dAQyLv4OTYNvFZNo3DIWj6cjrJovv00NV25RYZdFq1JhhjYw1ITZXit046VN ik/9v6kryQH9NtdfeQyQ0DpB8wSp5Xv5Q9DoQ6Sef7su7IMxlP6Jy0jlsnvV4J6CJkhW69+sLNBr RgSnslVSD9KHw9C65HXLUTTbcDjO6DwoC/izVfrJgRCXs8OqhO/US0O3dXKNxIj/dmpIy3Ri+3eT xG7aptMNEksd8TGg/zKZW2M6w5dG5orFIEWMsO769ho7KI6yt52Te/KhGSQKCYGvWyaEEblo376y FMDsqVZ/JYoA7jxMCXmmDWM8rqU0F9ywuSd4HRL1TmAE9okdT2Mix/n9PJbpFFdQeyyp0VbT40TW ZLPbjZ5VrRa00QiNkPAAy567z2GONEHcVk8RHKI+uL5zfX2T0JzLHcrJtukEwyogejm9NEPtkQZ+ wUUnVO3zhm+ucNZtabjxTmWBXBVIGp24CCMJcvDHUBbLCYc+3s1tohKnnGehzY3D05jcg8kku0/b 8Tnf15kgOUNsNx3gIjrWwNNzCyk85dm7RbG4gZ69krvlgJCGjrt34FqgEI+AbJ0BIdEPRYw523FA 0spR2mcus+sYUt92pMp4gb9ClDsWT1ANKqv6sibCrC5WIcY96HEBqEOugYRcNfc8GNb6xhs8TX9o fwqQHiuzZGcRDV7Lh0wgHnwXedTLFMaulGU5lCluvqyjEwCU2DKryxYn0zhl5PlLtM+iu2HwSiU1 oThhKYi0d+gn6UR6DazVusf5KmuemYSZM2EDfQ/9me4q3kFPfH9dG9sxzFXpHmooge+KYA7TkP+B O1MbSiGnTL15UmAbfcdE7oip6G+naMpUQHLdmtPMcpdNUgGwB8itJ3zDUEtXzf1aNMVsyqEMF3ju x9s9QSxijfJwtjiMDfIo4MZtZrBDiyWCeM5lFsWju/69hXwMTE6NXy1ORCZcC0G3VuSPMhS8yedt aYRm4d+wmHXSRrvz8EBDonh2ZFZYINyEEQIKCb0c6VZZec+P9dlMwd5QsDtEJnbYvYeJS0k6/BfP fzEv3lwC0plgUHbJL2G57IWNIYcdvQgBBROadu9PYZ4Stlr+MqMU/CDkudB/uI0IWR8vh/sO31Ry J5a3PmNqZRrFM6pHRZmJWe2M0Y48MnzNiDvy1mP7nH9JQjfKyQ4jheiJklH/nxqAEyrsGu7UjBCl t5SEhpQS6+G8CVDiXsGf2dNxxdhFquvMoDw1Mj2boRhLfq5hT0MmNQfg5tBDi0WydeRnvrn+tkR8 F+d7IcskOC43f7hQNQGK9kmdvzm04INzdB5eATNv6htIkYZR8J20cEcKGwl1JbNXwJka+Kcq9BbE o/rnSiBzFTzrYjkDQw3hc9t+8Q9fHzThD2uZdKe4z6QXUH+BHPeD9R711kj1SUgVTnQE0PCOSBWC jm0l2rtn/WN/RXcESBSfyxVShz90GVk0JNa+xvMQouPU3gTI1Bidsi/k3tNSSnGpsR2lr06hMLCK kDQpSujQmcPoENg3hekzGdm15pfhwYHQkSoT4j0qmxKdejtuBl3u7APm4zInrdZPEZGuG8kxykvd UsesLc8iFbC+WE8m9yoeY65iTqe5NhWznNCFDyrjcVeyuN74icJkLer0S+1haqWWhTedBSSF+6D7 EBALED8jh61bKfpBE1nOrQuLgMAIN9skY6rRcChUhBco07dtVhmqxPw2r+gJtz8koCMoCY9gVG+C nE0Ux5mUaBEtrss99iJpW18EJiITp/FDI1BGMECSFX1BYr44r9YC+XcpHKiLINcQF5MjGKumyn41 je/dzZ2U/iuf4s5l3vTQ6KdgFC0mb/qUQ8sVG2nA5Ku6GRBlFoL3XkcI9v9Ohro/MSK9gADfWG5R LAqMNMjqWJgPbcxlk0G41I2h7WheUVTOH7eK/47jkGPpy/Fr5ajmSYjxgEi6REQwxzC0Z6t1RPul LtjQMS3uEAiVGQzxrdgrPJFNjED7YLFs7NI1ipbaVduwf2wo/PoULJCTzP2t45B+4ZBujKRg3j0b 1RsmPgmojk+xMx2YiP0M3v5rwFNOJAMIYspbX34w4vJZiCtsDpnQK85SOM3Kt2vWIIm5BEAkNCYo hGKW7S96jAeG+Q8MVX6cocwR+NqAA8t2ycDm/TMkNpqIE0+AlLpXTxKwVNEiSHkv2H5APSpK+XqD NH1AbCelH+WD4Z1RYinM5MNcRO8u4r2fqxaLgG/tjNHYtF4kX4MF0BiTFoLGCKoUzmUN9zuz9bzv qgYZcU0D81W+XjvZRax9qSmQOF3gBlM2BcCUbQdwqRlTJzgKFiwDtHoiSG8Sa4thg5M+c3pPyg9u xTUoUnI3KCylSdupTzEGisYknav3oypeqalIDrH+7/aTIRkR5gFkvZxytn9H9KnTkFHYZ+u90Fjh VE+KUOjSMeyl90TRlJPhyaTjMCXh5zZYo0CIHAGkZPcBwSyABKIhIT+yqZDcXLJQXGc91Tsui4A8 6VNiEQxIs0E7iMmm2f6Ek055/TIq0E/ESOnHJ3hP3//uysjTv4i8UqbkvJtgH3zMrgybQrDHlM74 B+acPiC1EHT5FL2avepEuxpkPukCEwxf+j2JJVTtz5o1VAVO7cZSBEVAAdTSYG1JnX0k0DFCr+pH tk12sNYKGSVi+JKwXulGa28gnAtUnkbNeMYcXPb6ablCeQSJw0m76cEZFzZzxEJMyyp0gi4NdhBX wCGIDhGpIf6acDW3Rz3tzvI8F1U7bqMXgXzh0P5VpMJPn0+sQrIPRFz16xeCC3ry4+moykjnG4/3 AckLk3Nz8mucw3HujXdk4U27WED/nknCbhTcRvcRMX2LxgD9M2MGeNtoDlgRi9GNfwGVIXrdv0FK x7nSlR0o0LR08mOQVL+A4dfsXqKpuCQwa+mYHhOMthsGlney8G/nlWs9eMY2N4PPxFmFp+V+tqvO eavojZQUGf+lleUPF3MBy+w9cw2b7O5ztTlmnSOX8c+rrP9BtAkihV7v4wuyw8AYNNinB8IuRWfz oUJ2wDZMCtjp0a2LTWH5GErPwk4z6bdycIt3ZJCWhAFdM59n7qxINhi+6oMajmx1qWhhqoE1xklO UeOiEapulrXM18oxc5l/CLkBPvI+u/bR5NZ6/XXTHWMPmfV9SYQJIgWyAmkFYIEBzaW6Ra2NrhfO LAc945SohFtDDcu0senosYB0jBkB8xWRmY4USByzOiipiHJqQsJD2JJh25iucK1RsHiKAwEOr5TH vRfSQONm1Mpzojn+XjCYS3L2YJRa5wGADfE4fP4uXcfyhsQ7WTz+eRnC3Hu9m2AGYTtJvsd4ToO2 tGpv7U0E0Pirsm1B4sIA2ngBjSbKk4+ZD5763KOcSv7zojpxTVKTOTGYDiQkhp2AETwBV6F1WpmF glWdngbkAqYrXTtGTqQ3eWdVRvc1Ttm2T6YejuFITzdb7g6hYb0euupwBVrmXtTIVCwCuGZujRN5 4WHTLYX7vCoW7AJbv5mIjnfYXjYm+SpVbtNwGkpZmcvNw1hGtT0Udff9Mu8M3ozA46m6LzlCOlxw FTpP0C5La1m840OHDbJ4qhuejWhmDJ+wIbQB8S3yfG6B/KIyYxwj6ZcTeD1A4rMi6xv11C1OyMnH J3bGdneYsNObDuK/YxwSOrZUYux5XMtid7RizYz8tAbtgfGHfFKkz6zJnit/DyzJEeVibMIZ86Ym gWBZ0M3rsR3jnO+AfdnWwnomQeR4j5xLo4J2wYr5nNS8o8Goy/W/vV/kyCrwbw2UyzHMhbAyo1yd TChh97gBXFs80wNdPDhUdlXFkNo2cgBKZ5N36iJSoWpyKDCBiDvliNHsz48HZK2/oQkUQWdGG64e qrzbCDjsBxN9xf8laxdWqQycoVnmliFDDOT6poUkY/d5jBfAc9vYSBXgei92OaZZNaf1B/DCw8PE D9Z0t4uRDqCpd1ogvNfiiHbJfdkgItzUBIRnevk7cNXfXgGiCmYMkSegDfb8yMg5BL6FINdWuT7M i82MJnCw8S7v3DFJF5c1S6R3dW81wu3y+CL6A3kjg8cJ8hmJ2Hfwlm4+Js4r18cP9Fv/l9vnqpHM 6Y03aoAPfxaobAsngpRZxIQo2VjHEYStyAs97AJVjQxPPpyKxbr/4o4wo8j2v0R17HEKwOKgHxqL pahpdxAYScx1rPMmZ6o0VGayV+QTu++3ZOSSH/V3G1USdGvvvXIcJhivDVnRBv4n0p1z3a2Zi+yg L4UnOjPROjbcIdaBmrjslKVmi4Xd/g+o0J4lpg5T5gP81EMXc9e/TGp3cx+wbRU3gOF78Q7fmBeS xhShaez3LggUb4oufxNRmkMXLbKHQ2YiPcB7BtcT4z27CmLmcsETEqZ6MRYfCYrlpPIwOS+YK6iu bdH9mQorsaS+lOctGn4mLDOJM/Kz4ecwtWaSangWa23XhzmJRziB9oTHDHfu5YrH7rQQlMByAB+i +dBgQ8lEO+LGTzFnxv22FrCq5/ImH+6hcWMigzuGSsFoVOu72rzuak4jT/Q6v62e417TYt4nJV6K TA/lBWB1jg9xhJI0865LmJmkRnjrQ2FFNe5ViB0r23/mwvB54AggKnuGg62MEtDlX7VNA34HwAcr ASgwVOGEza64h2BFU8C4LqQiuOUX1l07D4BHY1qTI49Kf8W6kXcbdLTXpdR5HkjAdZy7detpsE6D pVkekaiQOv9Vx27Xi2gh3vGlDaUe4QJaKOfvLpLVtdIzSqnBVp6BbJ8ZuraNNPVk3kYiM1w7cH6j o0Vwm3gT5wU0m3TKwaEax+oS076yL1bZjo/r/rkLZ0yKj2Xftf9LIqJFe1EYSU2Uflf/2gxqCr1p tfmEG/7kqo0WzzN4A4cYDKkkrtSkPq+dqnHe2I5KZvNS7+2UhqT4HSJOK6JYvZNzcnrCQZpOKe2J 2z/T2bNbOSlyBMMIrruTRAuRAnfqACujhJqzitTHtOHwo4jc5FSeYisnaGqx20ctqfjH9QTkNK6+ VcYuWj95mfKstLQgmwMf/PI3rJEOTqSD7HUd4DWmirkfqQmZtGZuu8MxWDJFqv+XDhGB6XAY08Td KHFVduDbOodqSwlKaIOoTWtXx6U/+HTHRXqp81VByB9UFM0kcAjR9vpbD4WI2TO3QrljG9Q+/wwU vjZbRdUqcJdkOAxDFx5tVWIpGdQZmFdnaKRAXbXHtb1oVZnhpsbYgbMbIDEhPBuNFp4sU3MoSyua OLKCgv4fIt83MDwynszVJ7mac0+cjGg8V2Ah64Z+CbO0pzJvcvAUMOrDTIOAEK1Q3xSUY5Pe62K6 kfRhRJ4TJQ5rjlfk2Wrk7ywd1b7p9Q3gY4R1XVmwHlsrfATm1wwx4YstT04NlHZJQ5b5dVKpZZfq WiO05/uZtw6K8hML7L3nUfHG+DuIES4QdmnYtbuKiPtaFdTrT9aaQXyWC2wIHDuO3wYSs68/WNxC nIRH7itIOZTHRXRnG69gGPtkyyijDMb81N8DUYZ1s63fWINUSoN1vR6NODe1tL5/Jtmv37MNIuKH AttaDUx/FHTsczrkpeBVpWLgSOrMYiZ1HiFilhgiQN7HtJvgS+rHTa+fRCY8/cynjNNDwSsvbBsX BUsvOqFo2I8mXHBlIB7aGyc2q8BqodKRqxzA/yilkk9xQE0IKQ8jOTDcj7w2IfUvqly+GrUZ7ejR 4x8ifBvo/xdAmvAJu1bBJbbMevWOB4SiANHyqtoR9qIACXhJtYrUUjCNgexc1m8XKyfwfuQjxWqP mw9iqk13PCDh+ztOGgt4fpQAbbu9Hbgotd3B0ODDff2CXiBglbttmkIkwHK26IISxG7DKlU7JRaM QCs9NxA6Q8RkQPH5k0MnRzI1LVn5K8Z5SYwaTSeDu8ghedeImaAP1XwcKOH2ftH6EzL8H7Zeblok 4PB3pvDSJWer28WNA56e1a4JzEE0XDyIginDJDsQOWsccf2PtgMLRwDM9RHCFVK+YyutPpD0CoBP ZU65Ug/DNLi6pfp/t3rWBe21vmVdlPdh7yzMA1C892buqsarG9hMr/WIIn4zPjxREdLGq9JW4JTz bsOlJB08xxY9QdTtun8rlvPCBT5XWrK/aX9nmfm3GPsl5uWLsIBy+yafJ+yDHuBxvJhnghHWEykO m8Pw2QFhca6uMdsJF+ogXi20a+RRV4ZvWxVJ/JtmBqaqJuVtKVAWSmafj69vT9d2WjQ/lOHa4O8d 4iY2RKaEpx/SLiLR4uww0+WjL63PqAQgdNUAPrKXFTZSf1nBKxnVmOwsmIiBeB5uDTPJPEaTQBDy yhRgXaPr5ygudZb7m6kYEye92mIPYDycgIt35nuFfSAfXRppxWGlAImIVVGZHsmmN3q7yw1LD6k7 +EdLHSk+XiAyW36qVlQH/Ee0jXW2zci56J7ypJkMSZcDrECId5Z1zUgYKpIL2TNcfNLDyejUzqkM yBFSfM1fusA3m4A44knkl3YAq29p1iGaeEwnRxZyILfkpeqvquAoe/Tas36XnvNBEafHZWRzWHSA D26Z3DfdH/cck+hgKA/2wCH+22GaOBU23NhneaiK5t4tjHKQ5q4NM45TQYnSEfaDwkD9vlQYUvrW IvO71x5uFLgtWwgmJcGQJ/2pyPNGYd7Kf7Fr5NTVw8NdwnLTKG7wDFonQu8O1r7MTJT4nQ5aD7gq DVxt7Qy6JYYJTgW2lo3H0Y8G/771xJKMu8vAQe6XVZ2KRHRsKwWiJLc7MoB7y4MMUwGlCmiz0s+Y y/pMyJQietyR1ysgOHFiLjYhNxCqGNzzSkJzq2n4vMCvr/4MDc7PhQDXn+iCZqLYUpsdsIXumBiG Vfkl/zfkD3r6ufI+/7OH6HLWXkod9+XH+bzq3usCdJNsiIwiiPpqnXJsSbu9WxeWztEhHyNIM2b1 BmkLtMIbCQ2KSAzlji9vaHtFGmUnea6KqsQUFbApnw6T8ce0nxyOMWT00sf99mZy8qIGt81TGlWD R4WS0y22geqq7n+ehs/+hhAihGyrKAFWbfarwFQH2IltCUw+7+CTvXXNpnwgaZqlanMcQ8Y1BPVO 2zqjnJ9PoA1dzJ+V1JxIWBVA/V8zruDfnl03vilz7UbBXodctuZhBYsmKydQ2fXlalmLKc2ejgde af2JRBznZXpxS9pGyBZvU7wY4JxrjKq7zkMA9K47jOYPiBpJaQRWhiffKjDYfLnVQhbx1BtPkgqG mRPjUqZNjMRmq6Zn/Ab91t8vZormcrfhMunHQRtM5y0MlmniIQSGCS6S/EnqVFOoIDkDBAiFNzS5 0pi2B1xd82lSHKPfU6Zwnt6vXF7Vxk5Rt7joFatJbow5zvq00sRYS2Dq6PofnKZ25fL3olDLWWs/ 50yw4x79Z2dfJzC7izXG5p9LTPrSGPbigMIlxASFDyrF/NBXp+hAsGzNG1Zt8k4qb20JSvwj6MBB EKbK39rwHjANkDlAc/v/OJYogLMfK58znYOR7rIJRF0j/SXYTE+kV1cVhmtvPWXyIR1PVIP58oEr cmbEvtvcuYVZO257D+0lpzDh8RRTd51cqvN2IPCzYnK6Kbqv3OcUv1KoTGlfFtkf1CL09XVQsyDy 8H6v65VXSVJUrSHGy1xzSaHQUDL3rvIJnb3lU3G61PEeyTImXl3I4eoNasOEHW7r4aV+yvE8PIak brHYWjuVVmKk3P7EXmkczjqalk/yiUK4he1rZ4sVQdlW/ZkUyETmUJkQ6CexeEgvFjJ7ooVCCF9O /8V7VFFtajH3sWj3NlFD6QZWcOH54SNgYM2CkXckerUgZQL0PVOJPm2uKUIDT0qXynL7J56CS1DK ue/XWFuE+NCIAtNhMjLCk/eDEuxtT0YX9Jhurh13fXph7cMeWe0Pvf4zZOr3cg/rXKR6TNphgJGV qN27Qv5atIFlsVJ2lGp0uDRGvG2VpxqnnWXDu665veBzyw0fRWevJ+s9D/+jypQkkznc6xYWHKSI abAA218wNOoxrr5bdVvI7/2DhehoSDfk4zuo0kcSBNngxD50xC4jv1Lx017nxWZnWF5pU6GepKlB B7jPipAEUZ4zaWbLKgBNVdCyKtWc9JG6LOkCR8vzVzn6gkPOsEzAIseZUPOGGzXwkFonYt6m13Gn zYNy4Ak9NbM7QLrmLwdokTS2s/ERTQqZoWC5wi6m6S14ihyDBKr2ii6/yU4Dwn42F5ZTReo2daC5 lLShcJ3TTDhYLlPxdJa4eMXqQmOMkqy2bzy2Fz8NZ3QDZi9jBZXWvbFCzrtJOoyomointsgoz0VE FXHSXrCDkBlvWY1SCRHWpAlilx20dj/5JoyRujNg2xDzphogjQaqFz8APiunvHDri/7Y0sdF0PDX xtTkbQpS98mBdVwP8iTG+cQKh6VGbQn9r4CCFN6sit4od+3+78uiSFcsBDEJCGBe1T3425nlGLJV XgEnZ8ZaxwF1zRwBVJKd6LjT+iuhpT9HnLXBCsLx4u11tqLpE3xmZb04Z9UN8RlNArMJ0caK7hLg C3c5amQFIH3cSXSj8hiLtPCm+3oXf/EqLN79d4SPijfNPV5cKu2OzwP1NkUCD4yQQSvnQgasTheV PiJdFiSLPlsqW051BIKzuzKTVFvd5LN4TycV0OkVbufgVYl0VVGTMwkxFzlfbp41B7KwQhaTP9MP OGYRy1JjYScf0QWGsGZ15PnodBVcpEZtdbZchMcNmIUzhEp/ynwWWkVoXMxIkGz52FzoOUEY8y4r iUSqqfosmsdNiqtBtjvket4W2qhiO9rndyDokI2Qbmu6Vbdy3Bbc1CIEHLS5ejkPIuPzhxFie+Io L3JeS4fF7/XlJRJ/+BwYlH2j1RS09kb0vYC4j2UJ/6/HnZVrxhW9OR+c2ClDVLmdJa9dTTmbbPUC 0gKaB5UKDh0WWv3GjHwDmYq9TWca1aZ5DpGOMzfB2nfnAKQ+T5vef6N/FvNNae3w3vhTk2JEjDuZ oWz8a08b6EdOroDoP/VGEHJzd6IppXHCasDWylYAN2gIbffVwrxVWikrMW5Vths7hy1roZzImpvw MLNhc+0j0rtZdK+JkXlhVxDLtl9CnVFrrHYSa/luqUTitKV15FBD5Qz60+EHZfuk+Pq7J9hQ6Ps0 WpriKvcgcgxFKDvnuchN4YILcpvKOTghec5nh0KgfRUDdDIGZbsftuowK1lz1cyqgsk0v8MpYuSW uJ3HkpkuUCyrhcg7ANoQ/Y0Ip+IyTzll5z1T/b84Es+5m3PkHP40tcK7IS/hMh/smwKjqRnMbM+k qeEU00EL7gdbjymA23stEnSYL7j1Y4xrrrxw01mE2Ucv9hk7Rpnwn1rhmte4RVY0Lv7Cn3hRxn32 E6kzuyqi0J8lB+6qADwG7SDwqVEwLVkxJJVrSH2KGfRtGWimSC6z3vqTvUjuQ3L+Qt1XkBZtm/os uKevh6kqnMofT5/CY+IdJyvB2gqAoXqvQLniy2zxEON0HQaq6pMuY1Otp2C8aQehf2wpwl3LYtvo ipraNl7pGqauP8cmLaCe/lPSVxFrOigBaV95t6fzcGVRFidubrbkcrseYFfo+njrdDlwlDWl6PEc L8Y1kbLkTuwnLUC6IJcjEOzlbiXh4DbTX4T7tokonF4UsVcF8On/rrWXrQbhk6U5jaHoV4EG2zff FLxr5UzmF8XnlEzLMMh0Wom4XaISeSom39xzzYFDcH91pOdVU1zOXmm0fPTqfSpLvWB/+DtpgKRm Ki4pFBwEm5IdMAChgqEHytb909ltrk+oZHHcRJPOImpUetMVoKA/Ty1bMHGkrlQfuUVfIt3INpyT O4e4Kq9pvbH/62ZCec6UQj1ZKIPhyJCwz7q64ufXnuA+Hg5T9JXVR4WmwCPiDX7aj9YwaIDiS0Cy HnEdpIai/NisNXTSl1nWTi486U4AxPANVrmggjkbpGoPK0GYraCy+UCC+fkm7QTjCfG+Kij1dx51 +c/tG5pD1elzW0ddGIbDXj6D8kvP+56+IKks2/E/SMtsuEhNMFQXGzfD73gZOj1r/aKeHacrCzQb JHbxRPsARP7uB/MbBg94jinB6GCdQv9nV05dM6PbkeZdbsoRt5n1gSdNaxqL7/seB/UJjYU+aggl uDplGjF81KwBv4muczD/Luyz8RZS7SVP0O19ODWvrqVKauV3TMM+pY29c8RBXOTi3vNMh2VF3G2T 3ckYJoTjzHrrVXxp+CTsPyeJcMyCuaHNDBybxdRGFhypXZEnyHFBNMqg8h5kkv9ygHMB2ryAfJEZ eN1y18gybCJVrrgBQbJaAOxof6cYhEQNYKz8nr31exnckDdUHPFOSyKjt9tBb7JR+MJFFNqN2vUe BX5hJom3dRCnhNLVLbSSLf9u5jHN5PGun3TJBPEDTYLAsa8PTLqjxsS2oU9vSW1OQAkYWmaVz1FN E6t0YXQTpf0j/jKD3vvoAHNF91uMaJUzjjWwlydvaaGjwoLfTcYCZJ3DyQIMGqUx8ozBe2DA7cxg /8Dm/dfgZZ/efqKf6G0y7erZY70EprbttZyI+V4U7loR1VV7sDG9VmAjhTYIwaBSdlEOI0Cez8vg ayjVHTajwhpNbG/6g+ajNWCj+sgSJ+nUfF6YAbEztmc8s1oq+wLHMsLhqZ96v1bQTcNGG2sfdDEB zV9uHOZe5j3klsaC9GfIO/Ps9HF50W+Xoc2IIgeeQG4X9+D24DzCe1OIGTXw4Y9WP9kZ+1qG6e5V BSBe4RWrAMShMVPlpbx18nRsV71b6LN/SdhRFe84SC0VvvIk7Ud93yHvXkzJIGU8ekBeVjO0vCSj ZeioxXPDpg/2g5GSOOG+Bzp5fpEwiSiguAGcRQ/Ly6+WzXCuktq9aLQOOkj/yB8Dvf5EBzQcIuwu tmHoQ90MnULJCwkgKndei7K+aO+BEqopDvf2WsDSvRrtJi2nJaOz9o0vExtOp6x7UP9b3F2RsPjJ I9ykMaw/SmQXqLpi0wYXJlISwMccpMyH4U6VmjwUNCHDQNoE0scd7wCHaVn3KJ6lYclpoKTSLQK7 OfqLvwYgjGxh4ROpORS/5Ko2FkuMzsMSagggizZ9CGQYbQrvbO/ndCZwS//x5ErVYQi7Owd7/pHX YhoJxnf5S0ROTOKZzv6PhVtp4EgVWl6/81aSzs2DE3Ze7/vM7OcLrdZahWawVrzqBIzT3EKxISFg V1zlDOVo2naYt1HFdAVY1qC42i6/Kc+L1Y39WbVs5Zj9ouudoZcCZh/rdyEBQrKKPWkc3oqGvbst W9WLWWNbvakKj/jC3suzZFus7tCkCgaP9f20FRyZa4WQP8pIrimDTBzvOFCdN3AsVipEhq0SxD3o oPE1WejpqVTQoowui53M268HSzmyAdRgL2xLS9LSyIeZb1EYQsQKMCdzSdWwdu0R6sUzC8zDP6Ni Qdvv1Z5V43+HzhAjHjMVBy4C76LFcUNFTVP1W+cocT4e+V9pu2MrX5Mmc6R9x8ARf341gTsUTRFb fGy2BVlNqY+USAaGN4AwUKrdDRTLGrG3YgO/nrL0+9CBR/KAG1yZQmtor0Ez8WodvQsBqIB5XGEv fsdwXzxUI/hxtIkvG/9s5VVv/4/LfdAcESzN1qtC4sEczo69LJYsQH0HsXerk9cDnKvkObqjM1xw J0Wjw8jrLNI/oN66L+yM/p7vy9/hc+CJ9CXsF3k4fsJuHgbqSs6uLHLzsqcGFCedJ7xu0FqQ+5+o vcfHSh+TXVTpWvlWKmkwF6taydCLjEtECggT1ef0EAq10CVh8aWFlKna461/hzRGluSszoxKkBtG vHvogeNe6ir1x4NkbNi+OiQCqyLMPbzFjRL42neuwx43op74NENODTHMei/atf9z6CDIW681CTCP +W4XxcXQCrUMd2bgUwpb1dShrTb7FjTkBrZkDTBPvET/sF7Sv4mqKpVSPDb8wnrFJoZfmlcHtzDL Zw3MOrVhFsFRqhX/A5GJ+DPOvLV3Fqws9cAma0shvfLgJJqMMTIe+Fzo3+8K3bfEHMkKaPtQ6k3D w0HQFZpeO1znCX1hkxk8DgXTNz3ZWd3z+i40l/c3CjQblq11E/04lM89zhWH6aGavFeMtU6zA66Q Bcpkb79EBzSZYRkXQcQyFyhnv9ON27sW5p7LdaXUTN9T4ULcW2uYItqS8LOUCl1M4+xpOT7y9lhO HaaJ5OgDm5uYMorSPgj1+eVGOWkyexzOky72isifb4NKUJLdv+j5qk0CeRVjJJA5r2iTySXLh5wI j38dHjgaJYhXHQEWlWlRUR2QWYw6uCkhlPL0tuHH7ozjS0UA9kXjkGBbE+Fy245yBRl2oAgPAssp NxU5TyTNmWNNZmHeyCgIS6BZeDsLuPf8o2sSeUEdlix9RKtdh01H8o3yx0DZOTpr+BurhTqwZTdd Be+ECEOTcHwmf8AIuYle8ugG4gCgevM3XFPxEH1y4Dc5exHPMnCs2mOT9sipwu2ME/Vj2P/1uCTl Oe8HjZ8dWYYm1IUzxliEavDh8AY0s6VNjBE31o+kSUOQ4sHupdpRE8QrJ0vDxw8uQBG8V0d8SO1k 4h8OzbSA7+4edg0KIpfDyGC0pSgDaQgsqf/A7bcR/GNT+ZeET2t0q4bvgcgqD+QLc2Tdo2gtJYz/ V+WbmqMw3pGHq+5Ut1fweHuLks/4qTJdzxstrF7CDupR6LvhiGM5JCqd5g2E+tcBqgvwEVAueIg1 H45t3Rh5AZ05z2XUnQ5sR7oIA9/B5NHbpe5zDLUr+hhwM0iV0cYnOSVN+SS0+XSKjLX7swCdVp+l eXRywuL5ppwzhWXlcBgvySggQAFTX4sDLYKvkMPhvn4GFMm/cg7MGLB/5I9J838oKJwwINW2aq84 SSIqwphNvf3wJxIx0is7i9J6+R1n0GgAHCJrdKefuBd07Nq0Fg020dmlKTWmsNnzvEDWaK6As87Q vy1oKVZahdyd4mzn+fqIP/xbM+NIRkFTHsApMlNkH3KkFFG2t7hPYohz7OBabcPt5CYe/ncFhikk ydxJw0JEl0SS2FDd9iUL1WMqTDsDw9TLsFR3BcX+FDkq7r+ULGlWNAexSLMSkA+gtKDwMzYcfdNe LRAZY7H4z6pxtnJfYEiWzOfCFefaHfd7yMbMhBkaKns9DV7U4afK2RWdnPbuh6J5v8bzzqZtAkeA CtpesQdMrttm+ygSDfhWlQ9Z1I60tVnWLBv1zPmd63PF+4XvqUgoZeWhIThQOhOnT/9K3I1RJS4r RDrMNEZDha087gyp0PmMGOLIUUk3hJ/TF2iSnskIzIaIk65OXAeixxeyk0VbWv8qNJ9KLSalW60K 3e5pg0nddCXET670TwBrQlZsxWFL60pIKUNzcG6Ri/TK7f+Kc8lzbEQVmS//RBa5Nh9yQ/aCxCOQ itng1r/QwL2eP0YB4q4qthzl5R91IsbkNAo1U+l+jN3l3Ds6LXsc857TzFnJ5i0DFx/8eCaL81RF bfdr4OBP7CGZlHZLXiO8qphJHC07+fGO1lzrIkm4IJzSWXgBS0lTk+IJkOeS2iJrTmuX8owDHxIm Y7hYQnTr66BHmIXhYADUn0Pk3umshVAI0uCfZ9P5tnlTw9AusSb74JukaCvPV3FR8cXyG0UmPR8c PDLujXwfYv2sd/Og8SFLRYTEa7eNUQfD4qwv7pklkHRg0LeLsZ/MrWHSsA16Cea7bEO2fW/cxXBE y3a0Qj6DFTz6GRdqm0bF5O+Z4bsVupXn9JLLOEdCAcdRj4I1/ETLTNCgKnYPi/AjwaAQRLoRhTU6 e1W8wFzuZQUrC2xIZf8UcEeqQioEpSBgW6DjAMfmDi9cJVR73YqyG0yvPysc4bgSSBWwh8hiGVWU eMLS8FGG/tF5rvdA05HGxohFGoBiRuxk3Oxkqh9UDGAn7tNxHZDB3XRtaihPirKejI08u/nAnE4m bActcgOJKnDVIvPsm/tTfdwtrovYyNIG9HssLANDniKHk+XAyzyej/JzDVGgEI1bNoDn6XZvjYHO zf7XiDHp2zieLWZROLwYPm236aqLOgVIm4XtdTGnH4JnnJE3Ksc4pizNve92nAIZqVV6vGxdn1UF wenSs2h6+YbMMdax/eTX0R9l2Vpy+2BaG4im3ShdKuH605OltzLeLUlrPyG793KkCYRaLHFDW5EM tjSpPV/9voFJbp3wbDwtOQv38CZBPFLVWw4JCYZH3/0etUSgVYcWtpEDOJcztm4zG6ywgRtAiMXZ QIafKynODR34jPaRFOY3s9ZwWv6W2GqfDCxMfLkZv1oB+onrV8XqubTYzUJpTeNe4SIeq/kjOsjP n2RsY2u+IcGymxyKZLXEUlAiIjMQG9lN3SNWVXiN2tysJB0GMPqbVliuRx8JdgWIMVuCNQWW+z0R MFqPN4O/hS+lGja9XthVGWu6TYU5jV/631SI3tbgcHsmJwpzkVhn0ZEd24yu+h5x4StgvBLgWqSf uh0Uniyy8lWS9z6ydSaCMKicd5ZGTzXAPSDqMgCLwHzgNeLci9aYEFfVw/We+anCAUccmTXeIUiK a8nNjRA4sjE9VD4ruxIPqyWkaUcss4ssKqxAm/51D1RDHaAaFtBOrozmHAEVVftNvA4lVtqVFrns CWMLFRJJy9d9XXZXpVHD7P1e9MQRD38v/0yuSY5IAB93ZOywU4ie+DW/UXeD+DlYLucU2h23eBCJ m7Hj+efarvH9WxtUZih6ZmrcsTSP4Pnz+Ngg8FculAyChLSKOKVupKoZo0pnG7YgpFtL98txgywj oD1Wh9O8FTOQ9Iqf9DYs0x1ndZELcNMmZiiegutpJNQedEK2lWxxB3i9rCDSWjkEiX+bMkop2jEW RUOZiSKMJx/EeqNX3CW/ZYNXIp5hseGVDbuE+9FIDtmCM2iVx/ivz6e96r8tZ1cvPzZZpjwTSkfu f2cbkk8mvp1MBbhObXooCwbQkQaophUYdoStjvKCyAr3M0+qM5PjAju76tD6uTCpwJw4OErVC4lG XUGaR/AEdpxvgRLOhp7sQAnBJTHxqAg7AgRzFWBWXi9kBATpxlM89EYiqNigEQra6A/GRe2J2/cS I1wxqcvbRwimOPCzFF1p+EmLXDu6h6sFswoz1yJervJm/D13i94Z+Slk1YIICfukrMyJI6du4hT1 cG0fUcaBF9/w4XrWgSjKHbkFUiat6SVx9yyYwRC31A6uPbbYtOiXEI7L/y+QoJiAraI6RlefrAbS 7/tFnEkytLLh8LltUqM/mSOf3UIa5VURVpmPxzBbbdvtxXo775GMMWtw1mZxXTMqyb2Lbw4JpA26 ettQrgrFhlFIUnBT4YtR+F3PDITR3ePps6/hdckvTwgoOm6w+gQcQp52zht0oBoHbVGdIV3dg/14 KBHlwgyMRziTPGufwhYKcN/okNgl4a7p/pDGm3kb3qkzVdDhpJOD7mM9aoL/4nB5WS7sIIX4YSj2 w7rhQ4X5mY4uX/j2BfyGn4tkbcp/9pMKPh8QoT7dg9gxEO0uDZ+1m8AU7LrucfsLhKVvF4OhXzpY op4l+iMJbpbBe11bBysAYQjHNlHlHkAbO1wN4nfNRO3NdAddLa3JZKuRmMs4dAC8vckVit5TeqBe tBKiTtT5pjOEnOWXPLlbwAbT5XErKkZiJaN14EBWfLvH96DOM8oVot0yVEASFdkzz+c+SL/b1BVZ QcRM6xAoXdVPFJO9tLQTDGTQKUEAnNbC3X4Hj9fbuE9fQJZyOvtREH8O2NAZwO7g8VsyM5j8y/vU kcKhPT0w7W4epzTzek7qCCC8RXz7qYV/p2HtaQnMCrGnJdPxaks0ru6piq6YRp/z5mPVdbzihw8/ No1aO1b/S0kRGWBif1kThjxkbC8KKXWfh18y5YX7Z80knQkOPLBaxL9XRbVvBi1WZeXDiTqpU3+y eMu7/JB629qCpjUSqpMjPhcGvYI/drfByHJIDW+P7G6GFqGhAHEHguQQMEzFGUJ2PUX3StfQGJBC qlWY2j6pJghfAQGmsTYFQEL0XfO82OapNOdT4xzCI+uQdDLM78Cq8gdTtzCu5eBLeFQ1jp9qxxXX io39XowCl1XzkP+ASW8HnaAKYI29hnr7i1vrjOKy7lwWXmidqhO2Wx0AY6yBumb6lM1wPED4UC5p FxdWy6fIUhb2daNyBXbxeoMciknFSB+ED4W+ACAXgP1xlTgQWJMQOCjhXlG/T48iMOuoLy2G5H7y 0nn9jzpnnRvmcPz5Oy0RI1VyEFtAREZZrusocX2gh+mWN7NgP55czJTX+XazNY0G3aqbwzY+Vudc PX0ZU3A7Xx177DtzUEftqUuvbd03ls76YFEQBpyNJsDAa1wYEvMoyo29TDLNpRhbsuJSd0DXxBMf lYrY0mle5vnJPtBn1zOaYyeDQfBOCAYwcMIE6UBu59aOK+/N46ZuN4rE6d1ztroLC1eIKG3sOJlH MP/yYIUqakK8YWoHyiJ26jZ9+4bwhWGgQyvot95fpPvr9dTOuOi9TDREmIt2tSz/zZ9uXY8zcFZ0 cj5o95wMGD+m7HiVl/my7LOEg79cbAPfmpRuTp4V51PICiLoIul4KPshWc5axjxow+bbtaMnvM4P EnrOloZUSxtVb1ciyeKmebNN/CGQUgMsqppgzOaSasQ7ajx8e5NbxgjMbzeJggCPTJz+BS92Oty/ JeEeB1Bl9eGERc8F320RUdwnpAagYUWW9ZYNcuBUsGIqyMOcCI/paZ3PKj1FdpiEk8WUY3BMzWrY V2G2dzQK42WmpUvxb7VoPq0qvFcFv31qI6/+k7bWfXNnDcP2yDJdfWA9qYR4NQucY0ulAhMJWrPD CP91p9LV+ThIIS9wip6yU0Syj5LwMXkyEI6pD76XiqquJIW/dDtnEP7hMwqX5Fz/RdYANomqwtlI tGSVDMmqigQLpkzf5G8VPPcbq3tkUu6cgncocdjR9oI3WRJXZPHKYu1DBw6I0sGYY/XhZEEQQ/F+ 72g4xvl9EW58mr/SAO7dNxYkREE8y4LShUcHHraGL/onbYdneD4AZcqUSbozfLIORaZp/wO2NT96 fHyOhnytXEVhSPkkgP2I6HFhkY4N7D2jEzJBVHdK2B7gaSn8SuK1wjRpB+IC10Eq2ZHNlC4stqXm +lCEJ7ghn56GJ/qCpyRlr/KebpmgWhc72lnTE3VKl9J51Xd/015t/t7ittZQv4+ZWVR5R96aP7S5 5AjEwwjlVcNE1Q4RjGBdz9nIuGtCkDpqqADQX7yH4lvMexTVb/IpsVK1F71OYUlIzvhgHUzmVrCs 50ucARqoHmhsPiEnb/xquo2nijAUvrS6IjXbuyRgjt8g1m5hczNVpYmDngdhSbYIAXzY7JVl9uqA nYLxa94B7ef8GdnX6RPyGgeVs9j8OlHo3A/G3Ciligz/lGdHQaI6Yj+IQsG6u4qpywN25iiI1O1D r8OCg0sJD/Emeegn8GuPGHg/zwrRLZZIFl6TsFlCwbMVzUPdiHSifqaVnnniq26OxDwQPRvhdvSv kH1eE1dcoOQTkbDdgM4H6OsHyCI8X1SQUXe0G1ZlRRMqvE8SKlfh0PBJnkqiHdmuhTWzVEll78fx iyjAcaEh+VDP5QwhHKm7CpJiRVhmsQkxi7mpBkebHslh7IyQtht8XD6DsPj8Mx43KXWULvg/afHs plyMIJJZ3CDjvZUjqPOA+93V7tFpsWgbIGGSyqp1qsSiFEemfXoi7+w7yLApcz6fVS8T4AurnAcW c0lSEsPGnj9MZI8GcV0PYhQ2QN9ykbOZPJl+Yfs0SmyFeuhxjP1GHCIUn34aWpBpWQ/uKaBb8OYT /t2xjBvzOECyIuO3L2fqb7/9LfFb16xjUDVBPcKT5pLUBPzzmAImD4u8d31lK2GXhAHtCdDlbMFC 0Ux/Lrk5fj/5zsS/a/7gW+qUr4ZysBxtj0cRJcDUtmSp0f0cJMPpsyVGpxYqQLvpELX2Wt+k1knp CMMqLVpcrvhGvKci+atpomwQ/pXWP0MB7Q6v+jRMSAQCProQvIsezKC37lSB68HcXEwkd1taz9Uk Gwz4gAXkuo3jsxZk6fGQNtxQjixnQLu3zuq7v4L3MC0mZv42AkLaxAGn3OzAVjMZ6jH8TV0nrNVm 3iBaMSDckaRq1im/5ZD0TJrpslwm75spr7b7R/gM6eIGFLTMT/G8pzyV24bP8EIepGSxPms00M4b 1iKHXfZO/ODUsFe96obRS9fr6B47RIMSoH7abz410Tu/pRuHwPtsHx2p/cGAKv7wqzE9BNEg8UqM ayGPJJrYrg39fXa7LrBN++V3vbm8mPhxjyDDOqNwaSdikdKDXxrvAzZkpNoghFi9QBS8YztqPIcw 2HDVY5ZPH+NwaSMslcUvnaJi9ZjjSoIaz7psGhRs85iYeUvCQIwrpV58cop02jY0SWdp0D30FE0o g232eUw8M2yKAb7SXW62JPJOK/X1fzwT+VD+D3p68Z+rKj7B1f/C51nbgQNBZvVAHIJYrtyIyuP8 RtFOHqmh3TnZ7vV/VQj6QtBXzpzGNz2GSM2DCpotSROggYLsVCNS8sfSMUdm9kkeVHWxHkPe2DwW bFVUgHrn8IyXYZcINlc5jqY3hrNkNrtVtdLAeDjFUNPdRYUB4/i1LCkdT8fwT0tx7Jux5NXud7W+ SRJ4t0QKmvS5Fz0Of66euV03Za3zLf2PHUgyChDQbumnRjwAxx85prPckXoVuhT+AaFJkyzVpHH+ 7A6yfyJDqktdGymP/nt2pkIRejCEhKAC0FkhIevAA6ZfHXBhG38Oz3jggSNZCwDgPJYyHdjxqSgQ FIxVgFpIGslVSmoHb17ZKgphnAYuE2neL1JHdvigmkTX1IlO5yhcIDqyu0Ymkk8CHRrPtRZggFF2 Upxm6wo5p2KeDxYhlBPK0M+vNzxgiIZvZ7mPTMa4BHyZru0jfgyDffWvY/Y5rggNBxc3EyJaV6rb RInssQqtI1SNg4YDw98al33rW2EB/lFmB0Oq33enfwyoOyKpWgR62sJ+NKyUOk1kIUXaDl6ckE1M bTpLmsD/Uw0FnC8N5Nw/nYD88jjBEcfK7uDfgPUGbggReFzVjwLphLtmkfAyE/fQN4AfFBvbGL9Z tOtMcP/bW7xn6vZ5B4sUyKu9t8DugbiHdmsww57ouR2N4Rn06k8x6RsI3WnWAsVRM6ewTxUuuJLf WWxJ0pgt/CjQiKrO0P0eAC0KOeBZKN0ZotlwSTjGVb6eIgqGu3s8gu7r2pqWbFtonugLTz9WZlWE hjMKaWOrOeMfnn8E7SavdX8s0C3jNenGRgschZOvoe4SpKX+GnCK2heBT4HxAAdKciLWoLRp+YTU Sg8JWQ4th7dRfQ9yN2Lh23dIDJjjvH3xkXF4k5nL/UrcflwoPg2PV3n0UMLljONKsW1cqX0QblRN 3jvjXVuR2nRCpTApTw2rrCDBR3Yui57VGeeRGhLsbTvHbTHGy5LQmHiIws2fJj4CpcazDLP2MVrJ j5fJLrSZ+y6jf1+oc7WLvTyrFCNpib67J5GoVCHyiYiC6kWWbUg7itEP+ai8w2+VugiCh7k/HVGw 9TRkuI7DS4uW+wAwq3Xy+di72w68O82lI1jcloc5NP0InKgLqAOSl0lV6RGiqaPbqfpdfeJgVW88 9SalydJydIug2XQ4DkwlHVCZkbhbQm/Fc/r/lHh+uxvMsDie1oWQUT6TaTG7mpU/1O33DVQFJ1FQ +NA0xEEqKSvglfdDUw77tPeo10Y1rR2WwRseHpsSS78g6KYw+l66Npw3xl5np9k5GaAHS038gUq/ 02Vsx+0oy69ic9QdEifo4nqc8XhDSkv8a6wrzs1OFhziwSwok8WpI5f+f/LWF8TdE+h3wPrbOdPz r+vxpM9UU5SX1lwQmrSnmo3HQcLm2gA+Fmz1FLkincQnBq5yeX/nJlaheT0jbExOK14W0RdzuMW+ BJjsrODgrwFM2R7YaILzuCIgW3utBVEjbL6l0Ru3g01vlMV7q69Bwqyk0DenkcCWsimSPUrnG4yR Xadsqnq+KiwmWKU7rY1NVMOnuFZrQbfA8QLaXtPU/8aNsvxDNBOvFeoiPgkEZ4vNffNu+QX/jAXl c9CBZkyBFeCdWlleVtKRZVkVgjjpWUq1Il/IfpE7tnBNQkvz48cE2YI4KjRK4ngXV9WcAvk6xkm4 eMLQdW2Oe0imvW3dp/a3q8KZnKJMjioOU5pFDFwVSOlfa9gS4Kp6BWEFGa44qm8dR1d4NdGRnvqE hOiw1LBhRjInE/BDy6MwW0eVyhHs99INclnk03L5Sndk8fAAmBNGFwad1s2+NvZuaLM9hc7E5aET Bvah6msfPoyeW7gIWgg4KZ2SiVpApye7R1U50rLJ7zjImh4OPSDUTujS56+vyYG+SZJBhxegd42D hznNzsdY2VEmYLaZPnOA257XPCAROZxizWNFe9Sb+My0Nc/lKFZeC2QWk7xr3VupWJapjJ0275Fh V3v3534D63Klr/qlfL0jqGDOXgqZ8SjlQBdNUqcvQQh+LG04E5nF5V7swt0hzo41xArZYICpZCcj Lb3lbQXpBYlzTC/osaw5OiUqzzUWplX2pHr/mu+ttkaQCrVhzwpFFlicGMPgESBjqwPqQzq5Eyvr 5of2CUVnyZrxNANbQFeuijl8d2eDxOt6jnrEU/acNxzrnd9MBK/Yi2qqnb1HK2aoe1s4NzhvZoth sDVD3Xg8Y09laP5TXBbSD6lSAHe+4CfDlI/x1FbSMSomshLDS4XKrL+WtyDg+/YA9WsjwCtJc6cZ 5g+nZtWRMiIyB1jAMEGFEqcPvJCUWBA8noAvKqNgPx+tPCygTlJlo9AOv2W2TXUNBkkb+hFzW/yu H8YmEquFtmqfEVMlS9qLOsDSe0+tezwRW167e+J3cvLTxK0F9tUpuuDOIy61OjN3OMB4dWKDwnVT o8lK7GNyLzHH50/85FPCE44ZKflNpw5mVVeSRJIocXW72d0GMpHPo/XSi5XC3aGZFFIRLjCB2f23 GLyBmM0tcxO1UGTnTarQMULb6JL+UO05OiF6rIo5kGi1VbIX6mzgtHhd+H+5eHK+500AqTcthWaB IRXgycxgsRp4vhGm38hEsojm7FCt51eIFt55q65/48+iIYedDzIloBbCdFlUJx1kEpo6L48zzloa XoiRNjwldenbqPmZYp891GQwn5p1L6Ryn4FXTbdhrcGxNHBr3itjL8qy/BsdhDWqb8LwzGNBfvZY RQCeVdSvfoPk92CyeOAV3/OzPL/T+zAR6VcW3NdLdLTUHko4veDbdwUShdqCdG+BtnDRiSMPH0O1 v14ViTNUpbo6GX8aJb+sAL9+grAGpKm17yPSWqtH5WyfbcvNKIIi2uSxXgJmd2eCT5SbTjXbdv55 Zqa0a9RvkaGI3SbvSa0klEC2TmS79Fz2c6xKdMmE5QbTzUSA4J8xG6HW9MK5SFzOOjIMgPJ9+O7T 78F2GH10/brPTbvwSfrkaJG1aoCUfBuQttsqldlNcZ/A+vetE983LrOo9zexasxMpJsSa7JqAFgo 26jyZEfljXYmhlsWklrN0rYKrsQs3lKMKk8bmVfWKoqwTmuoDlr8eKnY90+U6iYUt9XIswim+TyS kezy4FIn9qQNAzHdng/JeZbxO8OGUqXAC4LmvzG5e9aHi3F3mI7FrqPhHrg95ASQL/lLIGEWid36 KhQdL9dcr6Ic2tMgarMhjVMzmXYbc1Ou3XZy/kogTIDFBUZhWGaFkOfgbQSEZzMDqevUpMDn+tdn 7tbLeB4IgClhTLwhmLLucRKujDL7lSOLaNf+ZZQDk6ZVWw1mLMS6wF8YVycxZ6dIxjrIQEiEUeC2 5JtuMZ5BawRPqDq+sZviDmn0SlyQhtI+tDU9kx/DlHdqoJ34FqqZZUEJ7zE2+lJb7Bjyjl0rwrNF LJ4ZKkuaNI+F1zl30t4uwyVgjV9ZBx3TLwGJsaYaigwMrIMV5cwbkoI7OMoR2r9I9ZC6MXN2hbnB fArLphlq4x1KUIihRlP457M+7MMXpDgj0UcJ4YlpTb9PJbqIiI28AtUb/QSjd0Ssaax5EI8qR2SH fQFlyr0E+0pYpas/zFTQQ/+NrWiepfyMlVTbhD572r1X8QcfNRCsJ8wcifqJMN1zQRjRluiS/Gvc /ATbBcgoMe2TNcK8dWeTWfLCxAJ7y3AILG3ucTHlaDeqw3uKfqQiULS5BhvzquTSTE/RfmcnpMxQ fOWziFeSrYZQ9MuuqtDXPJ18EJnel12vFavjgL5+M5diT+F+eoVS+7aJDN9yogjbiZ4blyH4BvPr ZIWZGwQo2MA3V3s+9XZoJx4w/ZD7zOtFoY8zl7JyNK5rrHWMxmiUPkmQZofB0IFtwkgiGFwXB1uD ekGjE2q04HD9RL3hA2D59GAjKujod4kuCkwOA8Sb6kWlcJSO5OjOs9dkbiRTN8viiSoXh6FDnfUI q5qVBOUWXRs4T1FMBFiLoTkO2huldkGyPhdNdaS7L7MHChlJzniYQ7Gwg4T3leQngBeSRNhFL1Qm XozOkllJIF96U3Ny8chJCHLpZHgP50AOShxHj0K6nBw6l7+kUa75UAni/W61n2LCwrO3iqJNWvux AjlhQa+vVBby2Utwhs/UyEQ9hAhbWepJZJCI+AarM/+Z+yRCWfZ12HGLdWMC25fW1/c6NeA9uqbN g83NmbPo+ncOLL3ZVBDJUe23Feidsdvyo50IXgAboc3FhtNYJ1ZBkP51t/pKvS+p+gSiKVzMQ/Y/ YqRTOzzYssd80x6hv+tN4o4ctgEJGEo6z/nuT/divtbXEFsqm5KPVeU3na2xT46tD5FKPEpf1Y04 oMiyvbDDHfEDcm/U+RKLQAmS7jDunv5cqnPMckRXTuMqoCUTrJjuUGfnvBopid/gYa5PMtT13uVg wEH14TN+etU7KHalrycejPGkRK5x9/jYOy/IzP8qUy2rPY71oFhPj1SjEpxiSkm1y0GXVy3ozVZp QC8Bcgf786DNL2FJm8xX3zSRqb7SORjNQ+felBJdFBj6f9AA86uPb15OK5M3VJTFJ/Nz4sxxYR7W j5Tu8is1KsFdL61cz+u/5U6AJ5b+WNhxoEgIRk/AxTmQyKsoo00gMKJd0ZKIyU4sJWe2XuAMutT4 wbP9pBX9VZSsSlhpepgEX+bghbd7IqlOx7r/3wdvm4RHhZZYGI17bHdrHu1hFt8aO0HGRvaAGRoc l90412iu3vi5Igl2LPEX5NyvpLWeo0pTXN1W9zmc8yb7acx9a0mUG7DI2JM2MAbM3WtmNcEYO4L5 igIic4PlBVTsdbe/rEksPqOneiF6EchSN6awD6NF3eoo8/qXyafrvgUiYW/a2XYE2ed9lCdoTkrV f6bnrRTNhsfO8KTcheJa9pPHMQkGNfxFyfZT8QDvQMgaJYSMJKTfL1bTSpd6TqLaBwK9UtCYyXMj o4ix6dcRigTngJZfZG0vEIhVsKUwicIDUpYu0iTjNxa1SptgHlmrp2gPeojZPDvEH+/coDMAJEzh yx/Of/h1Vw9hTaU/jqfhkFu5qNp8WBovmNwcuo1qaCxUnTszii8Y8KIdTzL090xxYal3ziIHwceS GE4MsND5JWceDaybaFqp4kVVmFCVuXWaSY92bRHxfRUVEUo6+4ThiSax+zH1ocJR2cPXONiPGnEO BGIpgUQ+HFCQmw/nVHlDDMlcqO8LySGrI9789RxImBXdnfFWbSc6YmgfSuM7n0jkl2lLyAG6iwmI 5w6dNvIq0VRUdQvk7j1VKZ8Z9jkRt6G9rpwMHXFZEJENKWJpmFTx8aCmkDXgsgIPg40wQCFZgv5n PNcn/GiSE1NMk1o+rAVQsHrI4IoW18QVxQq82K4SqCQl/g59QIiS+wTj1ZoVjYbLmeEl9bE28h17 RgwqhDYpP3eHEwxZD8WZB6jkhi8tpYDTWiAz8DJGqQgEECu76bRT7Ry3nUm/QPmhUP13j5yxsLAX 0FX1GoiWbwh405/LmWVWYrnv/5H5WgUWJvM7njlJmCYNnae6h9/1HOnfqv2dgw830h3gl+uSkvkX kATSXKkZbb6orJvnfs1lz/4k035JmkVsxNEpB0q9+DwNrlMhOTR3JaJFB4Ye/mV03iSLD5pxOzuC zI/8KNuyIbDnWJJvBPW2h8ynQBE/dB/pTwiGHPUUN7Q3MMobYVgoqCxNHY15U+zC/1hldcuTN9mc WmN3NKcYGkG6Gf+sFCEVg3x+j80enlic1w8lpUVzQyMI5K/pgeomXhZmFHV3vfs0ztLjU9uZCoyv liTzzWpMzZKPzJON7EIGZ7WSUjN4aMXZd+vh6lyD+wc89ZnPFf7UgWWQ1sIsbO4A0rC5b7t3Blzi NiY/FomjPezyhZXbFb+3FiYLgF4h6oAIEYbe5Fm6nCpRerDeW0xciZqlAkdxnG+1M5FZR7+O3Nq2 e/89HpxlaKq24Q1DrhYwbaXWeQZQQk8uPeopE2hGd0nQVWoYVxEkkyaEf1Oi3JHIbrwZQtAf6I0K cAh1t5tUieFgvYScSp3gbI8MlgBq/N0WKEm57UQfRjjogTua3VyY0cuQ8biAbNC450hSRjxUL2bk AjZ1rR8Ql/h6g9javwJMebez8/caTkEFiWvC7WUJbA8uWZMlkrzDyJg4jA/QjMKCdb59hvYM8uJN q267LpO/jSJFUZGXeh8w868jPEPahwiO6v5uJyUxvJlXhEd0o+HCfAbxvWrG8vvndZXMNXzdtzL+ dK7lMSy4nTqVAm6SUilURhhFVQpG7YrqmmyKmrQ2KT4BFGg/WqLPTJ9j1OlfZ4tmqqlQgVRY5Kkv ofSBbBfb8X3juPJX5Dr3zNvSkL6+iHVbA4ZlHJPL+JQBTXZzOBf0ZGDvMct1F4liee8k1phxVIlc pU5cL5zbf2Pne5naopdtwFAoPQ7+w3Ey0RzWlOz5895F5SyXET6SOqoVOsI+lKjoPSfOreSRxiM6 Fzm+jIOG3kwHnZ1x1RlTGBU1rmqSFxmLJVgZgiu5FE1GfUasl4fcEPN20kx7Kxn6zNyT7zsgkPwk NYRhU9ofoZOuc4ElZsENK+lLWVT53qzGJ8PpWxt6mc4/deWDPcSE85/k2oD8bbrf8MlD1WxcFS4h VlIjVGFYg2bGf61lm37burHVD+DUB8Csrkms778PJMrlhBSpvzUWgsGNAAbih+WVXwrXeTZ6qW38 XkdVwY/tFgOA/VMIMnUPR96cj/txwy0KbFMNvKsvAOmGjK4+IeqCLb3N+TxrKZPrAdf0bUmy7/ja RBjerF7uER09/wyA2eGd7g3iaafrsr+zYE/goOEcJL+RA8cG5KhJA8LwyvqLIOPgzXMV1fpsmj/Z FTpUoh9kOOB2AauYCyF70jtVTAkMP+RUDXt2gSJJCNa0FqRKsEwk/Z6MejB7bPJA+8fFrvHKIX6E I57kpElPAcp43OyyAK9e1PfFhy38fGJArqO7nFVlgCo0J8tHecSvJ9TnJGY2rTWQPS0vZYANnRlM VVOVfb3Bi/NFvEFnyU0rg8CFcGCRvag9y11nKeeWCp3ftaut1tBan6vhRsGi+xDQn8RFXRShwiL1 /rmzAv6kAWz6/DVnLQk3/LMLyXJvkfxoTcsAnDNktC4CJwNe80MlppoQnIoZAh7yUOwkzZ90qaKd 2ELs4EwaqYnqLGVhAnt5Yzc5MluyPSkDKjdhRO7zxU7YaDyRoXatobd2GHXk2hmZiDh+XMqOWeI2 SS9pPMtwgNBSkgldP3U3h7SudikZlN04OfVnUEcFrjGMmse/BzjY5aq3fsTCa0ayV5cj7T1fX0Z8 Vf10LTy3etH5lxsREir/QtvjCgGkTfJi3iJNXWr5tcaYegrD60IUazAUBGqS6EINhGM+FxkjisVm kBiKCmMR33obk/64ruPllQWUdBULK83jSXwWCIcC9AmGi7dbBtAbwRcFKqcCAFKfQ9VvVeuMHrNt BPc6FeBnH+sEt8+dLEQD42Ol0ZozRe+pZH1VOWoZwvJPrlJIm9L/G5TVE4QcnAgD9uZZeKRFckz8 wYwqCwdvJN8Np7tRkE3/a0Pw4pbnmwz4SSZzYGAtVrrlBTX8AmLhhOuRpfsyhV7H0pLiEJHK5Prd D3CM/wGsPjQAWm7uUz3q5+JyYzh6N4XaMBU9igCxMjF2w+FCMvrFAFHT8BEJMKIj+2EKN99k1vvz 1DyKjelJvRTKEQPa1HC2zUEYTzNcl7cgBNW4ZbUW7rVNc9SdOve78bY/GRB7oVztCqKNdrfFGKCb FKHjdBWiGyj4f0EdS4kfpQiTwoRwHyDJVFr8Wwa6htxGMtPDd7xoCi9B/xaKWGeLMDmL40NoHAUh NAIhNejKq6W1JSvVE3iM+7d3ehYxU51RQAWG7epAbeJaIn3KehA5tzw0ZumMIhuwVe2+dOKU99Ju MyR/mFgWC2OBFdJog5vX3X9DNBTCfDt6sEJEfKeH9WzYokcldgLFCGdx/FTu4CsZppvUzBI2yLhN rw7CcsYyHQm1PEVnPNBgJKPUw6XqxHiMRkrw408/0XxgEt+03m66BrHFjgE7UyCa47MXZBrkQS+m QDYmV+OLcGJ9gbgvjPBxCy+GfzeUncVrvlozJXo4SKOvXbTNy55raUr4l8i42ILehRrDherIDD12 3+ps6mO6of/F3dER84iI5gP6hrIexR81hRnOojrj66ind1AAIYk/sf88qWbeteenpCNLFEVw321/ k02aFmd8hd+SD8dMvfiFx2fUmFBSFIHbJ/x2d81YBWoLqFvphlGSNcYtSXnmXzbobIgA6rgldORj 8L23dLjZ/80aPxpFX8WZv447oTgdFrMTZ/4ukxGEKkkLyO832EZmpVXsvvaeCn90bBP8DeEDvsoF WbKd7hOf6FEumCjyW6CkxeGOTFlAxKzQTKHpXOx0qyOzMPQDxiorw9qnGDcUZGkusfeHBU/OLS5S MBaBQyRM7n+9GVaqV47oYr/ctXVjJfH6D7GOuR0mla9fcu3ZYI4sUNHqt1FP7iqwcgfXE9xdZ7o5 hNRXaKVaoeoRfJlm1VxTiFlCJk+Z8DAi7ACvyff4FWUCavbLm6Kcnp9G2PsnNTquUgiNnu3rpEnN b4jLStToHRbpmkefw51PUbs23vU3LAPrJL5vkFJLUD6S33+uPhRTCv7vk65ip3P7bAY9Jj8rSTCh SogrqYAupmVLuePYONOPRQQ3wUzPX/1YEKOIlzm83B4kzHOCuK73ZJhUHsf8RAfZt6HdRbKZY0wh 8xzJKEw96tQslHuo5z7YTy0t3wBVckReYJYukvL702du0r4U6C1cw2iAWzdTdYAPBx6Wh5jHtzQr y2j1bCy2D3QSjAM8kEukwRvGrDYp6J562vByZefvue9q3CKrWDxRJMyNwla6Oh4nuWrCp6ihHFZR MioKqWzsHARRkHGsIpGNBkQTsT+jOSI+yaUBh47oUYHyEB9dbQu5GnqEoRbB5z/gZ6SeWEgWNFag 4SIjzxyczt20YoAso2RkB1WHkG6YCPHQc6Jk/TgrWMaCXZFQ1O1nmIOj5dtOZQX/zdSPBovWb+lj 2qnRUHJnLeV6x/ofcSQJMOENDiO/9SMMtQoWcGtGPYWc3ED6V3WVR8e3VvFZmIb0HEVuQ6IdSjp/ 314hXGk+JgEbgn45r0lOtg+Ex4ByV9Ug+AUGRJePwePZxhuoLc/Ax1KRrUxYKMG5wxp+e5YemPJU +Mz16LZ9easc7PpQVTjBkrafkisNquPNlB4Etjrmv6jjFEaC0sVQ2u/pcMgdMDjQ8ol35Sb/uTPu cfL962MN42Nlct53zvRnojCBquOjiv5+Vov8vsYWlf4QPLHSWxvfjxIrlk/MZkZSCrEkLVfGGUhg BjbGggA1Nm1lOi4pAjwMYO6uFBjuDYmaO+qidTjDhRGq0NYSA8f0s/RnqmYVpGp2CnT2CPP/6mEo MUlZrTTBJZzVh4G+pXInq21jIwCZ5YNd0MCKBGGUgGnmMUjTogNtj30G0BH3wHl5tqQ7itJtQasP jeAwIBYq+m1uf0aga6F0Cv6bKlGKiFvZycNoLkbyPTF1AeAhPIMFqnI4wBZ7f4RH54b+SGEtPMNs wlBxRNv2xF3TxvLhRJdASuaNAyAmEHGEQ2K/4uN6viS+kdp7jR2b0J8jp7QbGcfFroP+xDzAitpB aabIemtO8QRCfDMEC8cDT/CzRmwmLy11HDzG6H6zKzIpNYjxeGD7FrVEJ41jxJVQxnB5lN+686pH D5FPeCK6M5ICVTQ3cU0pcglVVlqqQvdP6+DzYEiioZKudZc+hIuF9fOfdFGsdV3e77TV212423Kd N6RXZU3hldEoFK2nY9jLeg8Z7OACWjHBF46m3ynt3o+1DHwTFBM9xg8BPqNczNBay3uA1YtnI3Zv pglVVAX9V9yGW9wPaFyemvBYwk1h9GpM1OovoH7G/3QfYE80BGKdKIcuZsVGgs19ZBT4TA+PgTE1 wEuvUwrH9WKTOI29t1w63AqzFgaVFRVNxoFHhC7q8xDDclvc2ffG5YC7wi9Idlo+ffryGR1JPs78 Wv0SkZSXp3alAsN6c2ZN4ZCuI5dyZuPqupveV8QJn/HacPZt5qs4py3anE/RJjI9G5n3o3dfsf+y N0ANLaWDP9PUJfes6cXan5mmblPllT+GhXzIGG80AGh9P1aNk9V2bU6FOcRHYZ1h9R77sl0ztGmj gKGVdX5rFK8xM4W/5xVPhyn9jzE6cF60r36OfYMMJ/fIMPxz1VywYFGOde+cJS9OJSN4VgAN9s5A S9sPdYdNc8GL3i3LPcqS35OWCk1oX8fVhaU0pOu1seghYLNGZndE2OhAj6veHEDRUxT415XM22A4 Oo6srxtSd3D17VOZvbHrHbv0F1pxR2EJ3VYJiuxfErzoI8pqA9eaK1LsMuCY+K/JNj3wqv/YQVYy acBzUVVWImRUu6vho5aWzCd4JiYGFGljJELpyATxvtTcN/49sbBtH85aDNx8QD2wXNYnuxanT1B2 j4SuGr1Q5V/MBgPVUmR9dAm4IBsJT2QE7wNBOd0cvmqDe3bblXsCElU9BpPIga6OQzgg0plbcGj1 wc1uEqTRNjZD3ZFJlwmIhytq4i0Vd751/coLLoHvGgbvcZrEQbW26seBmYrqgPHZfHCMkL+O3Fh2 1zKDYaEV7KcLjPXRONM10QzDmWFPC0omwV2150/wbu42HrlDbcWf66PhsF1H6EXB7AF8sbkNVidj N1UrErsMpG1TFXk/Kgd1zpsPNalpFNVcvDrZuPwOugo0Ys1bCWXWyhsBBfe0Mw9+vhDiOJ2to25N 7BjS3SZoj5aUeMw5i3hpulJA+G2IWjYlqcSv/vSRu3YS1SC/oclnmeMteo1t7vwxbejZUpFw0nqu f1chWfhcQtxxm2ekQwZeYnjvoNUr7i+lV99H8NYs6PAZUUUdOASNadHWjFChAW6adRNtP+h6S3ll Y3k62JPf7LihHQ6QkAqOyVvY7mQEh7G04aNBJ/MhTzyUNqrmt0U9OOlpNvYA3rWlQBdWbcUQfXQh rvW1JouPr1Ue67RR3GSn/7AI4+VGzWUCpm9S56Mtt2bCa1KdrRNFv/3gYAs5soegETRJaCvyRePh 1pqp19U28Xy22ICwk5RTIB4X7YnIojTxpTtTyPVzqAZUDDILBmzYmOjmmQqVN1yhBPfHFoZmLt7I H6NSdvy2TQRUnfHR2B1KOCSYueYrbJSleW4wcp6rB9ABFxYXgjGFx32AZpMXGV6n5nqWlPjAa3+O YvlvdLwzXIcSRvc9/3YbdCB7BhU/tArefW40Nwx+Ftx/58bqHlBe3UZ66fL55iUb4qM7nwlSegLx cmwhlpnq2bYQLEauxKmO4lXF3s7ReGQPr48zfJwy8ip+JnsyXa0PbYJ6eSuH8wEZ5Uz+noaLTleR 6y+5Y0k/Tpsq+pPdwWtXxHZax34ksgD1kjbNVm3D2yuRmrTCNqMN5xcvzLKFiS9cfUou3eCojxMk dDzCKOkF5W8YKtyYycNwpl2avhNti6SbvtB4mAIrxLKMHYA/xhNS5E/vVRwKztHj3UVGm+xvTDNk gVWxlR6HK+Mi6og1JFGHTry7OHiinLAOh1KLTP3OcSDSmkbFme70XpAkQhl2FXL9tSXpr1r5RRmI w37+zEWF6DzluvAbgy4hqWMdf15Gt8ERChd+3fowKGrb/3dV8vU+hLN9K5SIJsvyCxDmibb8LKCZ jTHTbWoeehEaSNryoD2kl8lEYvdluAvz5hy1HdWH5t7cbXNK3g+8PjMdkFORJnpVv+A64cXg0t5n gMhNMRCKf73kxRA1kO6eGTl7XfX/0qikcSWugetvFAYM7xnvr0kjEY/GR9Om19P0NCJCPMldQvyu nxnkE0yo0B9uFTYRWdnfjCL4FfqQ2FFpVpwexn2V/o/ZcMPr6U4/8IPItD/wUWVKigYaHUqXR3JX Hd3F+EmDBcGIkE9hY0i/1w85I2PDkbvMJ7XnlHaOMjjCe23ASCIie9DLmIADSNgIsK2a7KRSAqyg GPkdizhpa2T/BB1nWpSSfZXeLC81nNK6HqnkB/iLonog18wDagkHZ4/3s8MVCAF8feH+fx6yJXas JFkcZ6E9c2tD0o1cSfmV3PoUCVBu0A7wrKj3CvCszs8qvA/3Z0OTvAR7YUp7Zc8JDQdD5KreN/qG fGv7rgceGsH8ZvfQB4n95ErdmAqkE9LUeg+JBPnLftIObjRY1FMb4jGjNGWtuBNNaDpnZ8jzK0u+ 9Tgm70wjsvjkrpxt+L4c1EUMj9dqbksBpxWB9LK3Iak9R6bpqDeFsRm9Ey1WEaemxdvxpnZJNNwC xcqtjfgj+1wMhNT5vn7dqNg/lBWXDLlKh+Z6gXKiepGNa3jGehC1cmoR73UCO5bGRzHK+BB4YTeI jomGXsUy88Qkp6XzkPRo28XL15+LbjyVwGl9VVlGyMT7GcTuUNjzEHSI+/YChXGzu/QS8Qr6F7L5 TOOaIT6x74EriX3ZcaDapirXrP5tIHT6z/pXxXeTzL2Xl+3uR1dij1/EXMLxWQJMQZepzjthDSVj K0+gXjWtmXi2qKmrkIteId0ZmelZFiK64pjoifw0Q+F6dCHCa1v//rlCRnJ+Dq49Af8KC0Y5Ocwr S0xYPnMv75uV/Q434aAe5BzD1qg08MGwveZSL2CpMxeAvCfinSeR7pVrDa+9Tg3yBXlj6keryJbP /cT6sBNOfuh/qbRbJ2W/I76XAHXj/N8mp3ShWRAxww9UmCEN+LNVJFDg1nSowY19xVV2EIFxGfr7 v2fCDtU1nQTa1DSknQnngtdx/SDKviDhFhDK6CuYgSedaimCRtnl20ipHH9MIfJEfnqJt4zjfMQ7 UjV3S5oDjGcoI27FZcgORB1OycVwZBTMF0eZ2Ct7Fi95woBIlm5x/DJegyfEgXH9UC5Z6oZgKE+O bEWUI0ezJTTzEneBhB83FlErDFFh984/u3C0qgvQofJ6zSrZNlS5QdfvnAefQiqlpE7YMq7gHPvK 2yTln2zb2XvvSIrezUMJ7M+9vABE2Cpb55werUzXuAPAk6iNx/9+c3ZjhfnvrHriTlmEsNCcvB46 nbFk/fVgrfXw3eWYfmylhetl6lWgzoE5TS6PvipUBcrto7O7KqSbBi6ZGwvOm28GB4WZ2AZVMJ/E 5v66V5rC+zgMRxmKei92SS6DxxCf34AOanC9dGi43jtCNTojrMIo2jgZGy8jZRa3Tdo16Yt3QcCf y9up5Rc41FmHLtQeSXW9sh1UhNJdeeADBGdM4nSjxCMCINnbZztsaJEDb8SuaM9quGfT5qR+i4T+ KJBAX0z2lVKT60oMlJGoMRKszouXu7b5gnshFgVFSrUBMDwJXEO9tDV21SECHKX4w0BbCZfQ7GxI YbwW6DnHwypB9T+gW6WEBgh3fyNSAjVIqm720zot3GDKrA4xKN0UI3RR/Asiwj48/aNyg+Dwf5dK Eyiqt0Ygysan6tT9SIP9+3V4aOkL6mijRO8MC1vuGBWwmfiaoDov8swyxI2QIaKhXwGXxqxdirTR 3Uv/n/QtWA6P1QK5Oin9QPykUKNWQTfG51013VWP4dsiAGTn5eqq7nWPcFc5JGFiKKpUoL+33JKa wKzyt3jnojjNe8SdpET8eHdIcHFs3aCbqUtKCWX5cQrnWrUZp7k+ZbEkHIQKbmzbsmwoWHtQcdva +Z2v52hkJges7zhOzr3GPhJ2UZkbiFoQ3CuLB/glDVSRdGBI+v3YAtRRw0CUDAvWwpmj7A64B6gi jB9fJ35AkR2uBa7Mt+GkRPxCONKFr0feeEo2uY2x4IcCCSKJ2GQoF27MlrHuQmkYQyIboJpNNbEU dKGgQVZ/SyxhMozijz1HmxokmReeLhTqa2+rmlGWdBjZeIUeYirqJfIfKfbQgVxmZ4wwUOtN9Xna 0a3VzBanxiygaKp69PaX/eKaXNMbepodFMrbZGsZLaSR+6leCD0XFmiEncUGsF+PBhBb2PPHMmd5 NWHHrGSnqEmJCimulmJT7+BGxVCTU6gHT8OUiMS/En9ZU4uDcSHI0Af6gYzeCt7BFoJFVqX0LYJJ QE9N89hXKQpKH5YJ4aSK6WP1jiniBliMg0rObZD0ak+F5v9ERGc7mWvuDryd35F+gFgKYLoPBPiq kPDH6mVM9X4zELAquzPXfCRNSm1e5yqYycAefe+1gfkp6o9RzrxNVSQb+CKiuGl/djNeW0K4zPQ8 DjvnTMWTKixR1z2s81vOOVcdlNHdeBxqYUcC1VJMbmk/Q4Ln1w/5GDV+N+cQTXIAnVcU7d99IvZk Ld4HDisr46WPeEcIQg0pbbanlpdf+z+RR7D4MKc09OzDjvL8JjqK7JIQ10q3R7afA3JuJs44FT48 Q4aqTH6oJjeBjPXFbLW7YIeBMXzMuiCjTUUtxI1CR5iXF1RESZlXfOAn6cFolKP8ODQISGM5PgGe ms9DJiFOAoBcql0rtjpEdjjXoGzPt7ce1Tkw8kap2JPIkBrjU08bCLv7iIvmiGPnseeVVzWIo0JP daT2o3xdclxd597bSwQlq+iLh8ZZHHHZHMAPd7WBiPsSk+h/r2Qg2V+l1Vy+atGIRnM53sFzOv7K SpQyM/yY+MY8gKTknCnpP1kKFOHG5OWmztZnO9IWyLuJMP/FnreJVcjEjxZsUikp6lYLTvKpaZe5 a/aDV/RjNdKoVg2MbfjZkaDi2HU/4p9ib5czOaKl4iz2paxyov7oYRU+b0kZykY9W7JekVnR7eWT h8nZ5WpBjDeh7JV5KXsS95fjUKdWP0vtm2sY46WbnbERTaGJ5Rgu82tecrz2a7zfdAWu6EBqspOc WWPmh1j3bzPhGpbDO6ke29Xfzav+lxETcwCcoURDHX7juLQtJKhjxi+cyUcU9as3GVUc3pUNrKP2 JeoenTEmKcD3BeVpjbGxV74XV5CjlLPfd/kzrQNVyIk5KoBGV23T5DnWEdaxcWCwAZEWyEBRhVpb XCTwabFTi46ZBp9/M5oUMItyV0SyVEOa88zEhbNIWIUrH+ee/UlfYUSluuL0q6vdtXufrLqrpM+s F3EsSq4/p3SJntj5SGdrTvohiHbPNKLQhQMb23mmJFIvqBqJ7Km4IivnkfJulZoMD6l09HyatSxX T6TGGk5z8O+vhq9LnOms79MsT+JvuPO7e4m9dgNZjjt+3kfkJxa3Xv8tX2J93DyUuvjVKBgW9Nqf KJovPbQd2o82FLOFtfUpqpFymDFvPtlhg7jDeOzIhmcHfNc9S0sVWRElQshBKiQH3m54QvHJQHv4 a06mf02Nisq0Tmv68/NrcereNk54REnuBKoIpJsJDM33cYsVSsteRskcjz1Y4YKgMXjnK76f8Ic2 p6f4GTL/npULqdAcHPVe3XOLWETIW5OW+F5xNGW0xRsSwtI4V/Bvu6McxwBRdFxP7KlRZTOkP4Qo EWSsDzHkHs/ZUbFIsCI+Hk7SepwODqg5c8oFNe2VDGKVRWBplH1cpTqZscpdCPc9mwouun2FPMgY DfR4zwUMWOR5k/oBUaO/KeDFvbiu2YXbuA75Eehfj7kViwhwrpTH5DzXomJnF+MAeNKw/nANXyGq 0b/dKadiOICAFwxURoAH1l1sGzEVSVUKVFSQJRq6e3Rzx57NsrldXVc+96Kh4+JB4NCCSMHGS0j4 wQGXyg/Sjqw6TKuRFRZXK6Wcw38mrjwgfHWw2LtH4zJaFkeKG3C5RUR0JEQx7Sd3r9W01SYUTDos HQnZE7R0FPk/5Y0C46bWrSl1Z4/c3sAmrcJwTvevUverVT8wXbvc4C4AoipZvk1essnhF+Pru7XZ xDRJy2nxm5rrst1PcmzwBOjyJsxDXZAZ7juolo9G3oll8T+XifD58McxeLH2xygGHzDE9qVLW74i daHYfr0Ww/pcBUEEaavWtyR8eK5j876kkC8nn3NCkGsJMzAGwc3SAgcg+VyTdYBUl2UKfBjTUSrg AIrHec2B9r4wWX6Zo1mSF23s1FYHn21esRfGt6j0xAfsaVJPV1SkQnMFX/YmljgSPYno5do9BKVJ xHuh15SWLOexa3KifXAnt2JITxMpLkB/iEkL32Yxci7/4UbKSjogdysEMBwj2mUCf/nsbjsnFBhE ePU/J4ybjHY+VsS+l7WQETuQzHzIMHMqvcT52u0mmRwAu9ygGnpEDwYKCgkEUMOs27y5VwUMra77 HussXfKIFIplqJlIpGzN+jYuvC0tqFH/Y3WVExZcr7cblDNBv1jx6Qbq3mtc/tbJ4N9rghTtvV8h 502CxBGDo1u3fiDHGUICDE7Ax+ZgJPay5EhN0aReSaoLnBbdMMBEVBQwnIPywYJfo1UFYSuP3+3v G6jMXlulAnm/AKFMFItoGEZQy189BDfFcR6RqUJevopXH8HYSNhpatB1cyjF4boHuAqS2PNH93dp y+HIHSiE3KH9qDd5SzpGo7FhD3wJwC2Efai84Ep9eyx4A1lkly7RIV7gkg6b7XSO2EHfbcUEumiW ooXGtfuz6OONn7Oazp6JagDqRwXUzzVaCWwylauw0FrkgTYUzeU2dZbUV9+2b5xrchGWey23q8hv rEqa/tvZv1k7pHp8pfh32Mde9WJGyc8dUqGVzSjpJvsTS415KtoA7+yKzXmqG5afJxX1o04jYsZo JRyMkw8UHm+ufntprodKWKIHmMaI9tN9gkJiCPQhHUodHynIE0WIQ6rx1IQWDZAqdQBkLaMXXXxP UCIy0SLjkQWqzbJ78R5OUBWRtlEzVc+SIbSepW9FBKZO0sb7ENpusXYenuSjwrx76sqW6vBS5o17 SYadh8ZFonJw6OcNrrt0sZjATp2VqB7Td83LnfSPGmqQuEVu+PpPLPdpH3UD2LzZ9h3M5gKH55vF CB410Ea6if0BQd222sCyrdtKaQqAqgOMEbC0AEM+VH7tghHQmVnmCLCQUJJkmj5txG8C+hKFn8oR VGgXb6eatnZ8CNcQfQIJlb0YQ9uJ6liqDdMD8cZLanBTJG72PFfJKJSfX/MPAaKe0NvZgNvHkUTX ULMEOImZMMuO5OzC8XFeJf7+duNAo2J7ijVA6nUNPROJFz5vOrVjWfPgP8eQmlkvA795AUVh8r7l Xu6lABd8ISE/1Mb4xdBRe5ki6mky8dBvR4WNw7/YVEyrs/hqgAuC2j5guxNAPoSTjoi2q+7cVuq6 DDE0V/0nEAs9FXCfkNfbD+n6R40QPmG4Z67moYar80x0Dm0flCuEOj3Gi4UMnS16S151jD2zF+DK Yd/OhnD0/Msp/G0lFk7DmOYZiD5f4O3rK2r+3ZovFOJcFbCF02ulAybuXGvHUKi6rFISllYDM8+C 3zS/Oe4nX5fge1JoyCoLu3KQJqbSHWpPdet0HEomM1SAeSmsrZG2Ad3t9i4y2cTYGCSvaZ8EDVRe NJBrD4QRaK6EMfzGAyroVQKHEM8YlFAN4D7N89hpjuwfvg6bo3n2AMHhDux8CpQr/sac7P9ZLEC9 g84jQ2HQt+wpJm68CShcfj7HSBoQRk/0RzdJnEjBRGI0tNaNtIWmyWdwIthDr9CPpqMl7z3axXWw Z8uqOOLmYM7OeWgezm6/dwynBYtYahya/37rz+0nXq8LU6cRabVJQu0AVgU6uVlWBvj4iWkvfI2L h8zcPwktSLFdojwUOnz6sasjIheZOHdCalkkSrrkJzuExwDsYPu4Pamssaahqerig1TnSJ+Behp+ b4t20YYHHi+EeXKl9rxflglLB2MOv98UIs4qBfjM8kuSZnsTs7QCoe9A+8l+wMOYakdeBdSlCcNn khE9obY2MVtvNcDo7RR0zHdSJB8W0+YQyKEcLKxoSGdYYGHOU1OP1tZszv5OaROPf9eTi61Ow0jN jP6Nbx4PrYsCO+rkTdQsmsIyf4+PtCR5QEw2F6hmzFd+rpHU8C/WZtlp0LfS/8KhFRNk09+zE8JI y4495/+xHUoz2iC3ORcCzb2FOIuhgP07vJj96Na1DIMZs68+fPm8w5zl4Jc4yW3fksMBUMnXrWXr ehyNeEWJBUqP5iGbEaF2O1j4jZqcTEpvieQboRNwd0oOMLiSpHvoyvFyNQZ0eeGiL5m8gONPG7NO 36Ogg2+oMes/u23txuATiipg1n753IxMfWD0vbMnIPnxEdQlReBv4XbRiL9JaWzeVQjTWsoebI/p riu2SF3URMnfK8YA/9dAQ16ac+P0PU2aXge1O9mGwHNFacrATy443Y3WXgO6KxJOYbVmMsxpC811 T8kFvmQRwCZgSutIufHVjxj8yLzT8W9WCnsj/G8YAr/bBGOIxBoOq834n005wSqv3u+RUvzlJDrG W957YLrEy8O8PxMq4Id2D9HSkETfOB1lXBjPl7e02fq3aZjpoTSbz/Vx3jI2cf8UscurDZwkzL9O 454sYdXczUcsNlYXyngOmKUh9m/X4l+iEe9RD9NPcdSLOYyLJ9iOgARo5meZyUfnBTgEflFG1Nz5 NBymg+iJjRSH/aCHhfgQ6IfWHqmSnyHUccWp7PZR6mJhYTHRnDK/hLu+UOfyKO6VW7tbm5uFilTI yvOckIfd0lOCI1I9WRTnnLfSfN4rumY+NKnq2oZhVD0BcACdHMX/7zPy+IsLebiJb9rUTu4PPxi4 A9dDhAFgXj3OXhjxP0/i3dWxQKtZFwCmIKwFgAzucw+Dfkg4aDWruLSogBIRoItvDEXtG3/ydN/o r5+T44i11W2iVs0yycbIiRelCIAdC4wsAFgcCiuGQPy0zKyBZ96TZX7Mw9pT1ahZNAYd2XBjn5kq 6u1isgoBQwbDc8dqDg6Sch2AyZWQE0DMk3uoKioxAHZuPuM8NUa3/OJiQXeeyzYkF1s7cZAJMsLA Mjzi3cUu8p9vBs+vBw/Z6DYS/EjfmnHSED6WL4ZNhJ2luI5JqClnaafCtJJLMWRpG3ILssEr4M+N SM0aKKMpnpXD+7kDt8+W4bSLxaYBZLUqgKO3w9KqlDW2ept1QnbRsQ28ez+f+5v5bL5BxgokuXnR UmZs4q6sfplZ2pNZmJ4FzKRM3e5lZjnBZ3K3UsNb7o6gR4Lfq5h9S72u0Tgl5X+g7ZZtUoQaDrJ0 ICc6cVnB61jSoDLZKm05LPEe2gBUjMWrnopr4PIIsl+GBRVZNH6ZlEfnEtRTFPveBSS3H3eX96Xx oge1nn+2K745GSfeW2/0NUm8NlQDEQOqfAvEJlevQ212sulICrHZ740RARzkLvmUKgbThwot295T CYTlvGwCHALR/mYvhRqGjKoMCsY3Iy1uKTDNpE44ieNqVk95GfMjMESbn4Ux2myEBKDnaoa4NQ3p bDSuldCZYO+FGe2JGFpxtMgtMUBoem2WBTilk0W+yebNp72cLK6Hip3AOFZUI5JZAC8OTF+2hPP9 +0CNvZlG1HNms2dsx9cLnyo/zDH5zYvivno+hGMk0tojFsVhq1wxKaarPmNSAAc+pYFCChIaNUsU rheHUCpM1id9j5v8VXtoezDUaw7LfGAqb38h8KxVQo0ZpZ3oTI8woqwcXISjUCtn/Vy+f10959/G y7wNMuxAZQ9IQSwB0Q1pI9ikUSE1YNa73UfxIsWB50SxfPWSFuz+LSHhYQWzayfs39g9b8R87nzi jF69tvucG0FWT8ysAnD+caM7r8bN1He8LKyHe4FgHnjhjkcRVfpsOO2Q8BBbZrmoU/DFgCYe6Sly 5bITJbL2RyAyChXdt7d0imVJy8x8y7X8rugR8GIlwvBMhD7/Go1kX/3ZII3VlJR4RoyyB1bL/kQe VJYh6cp1QBgO1p6mM5V//bpTEORe9Ud/wRCo/z0CHyPKj9qahBywJcGUV8jkWhN2dH8qqrQpWdQ/ jJqT/OS4DIiIHeunsw0HqueydhEyBPl4qGFtr9kWInwg+ERuiQk2pfVZPPKlcUqyjj+K5W881hzg ijQq87Bvz06/UPfKPfK0M7h2YsgssKztTqiT0qoBr7Ea9mQDvaKWxfJtWD/hxX3RJ84RwYaqSo5J StUS9J3DXGFMfsQhza3k040mA2tXNlQQUH9N/clrXyiTY8Ac7cWGz3/x13LXFFEBuPZq/LzIumUY rTGEwzPgvOvwzgSlqXZa5V9JNNQ73lcgZSjdLAG+omJPyrmCpLlqF2/GE88gOStA74LWKjSaYces BK7noerDtJszjD6KoZVK54MCbYfilG8gJJE/nAy1pU7JTiA5qRjJZl2U1QTJBVjbjDCiRjGvKKba fu5xVv//UonBlL4nTqBmIrOpj5vzQY9TcpALhiXenUHnbgtR5X8RTL9vS4qcOSJteL3dowLvgnp2 xGw7GLTi7+N+DG8csXQJXJSqeRXUCw58ABmY0/Y7udYpDJLt0++DgArk4rlzGKIEVgu4ctR4GQXn 3XrQjuYJs4lNhFvpEz3OoT1bmyt9Cfot41MB9bbZEm/55JdB2eTRQPOon4DgY2/tqTZJAmADcNIO gRS+ekh/b7pQXBbENaCSVsjiyDpndD+VOXQ6JhB/ZeBcLtAG3/98Y/CqgVBNmVOZkEo6NuINi8di 1RIyLuG5HTE1lf37bIhByXKNnuUQZ+Fh1DLai+Lzvwhw0+QpzfpnTKfIbX56nKvkG4DvV4FOEyzp h6uDusTSoN4pPZoIieLAAKAGYSDRmKjpxq1NfcXGRqjOMam04U5Y/Ydob037XPWt2P3hypZdvCy8 UQ1Qskj3zC91RcuiSQCLf9dZb9kZJj++K3CwONfiHuO6z7dzqfbC0RlCVZpATnuCJg0hC4uLF79u khaKk72/oCH8pFvoqFX0AkAIOxSeSMYA5cHx4WWkFyA8So3HN5hMyaKJylqDeioJmM8OKEJLsnun /7tfWPSj+nbEWmcy1S43aY3HXY7UdjbHa3hjDs3uh33RKReEK3772dYrZlOO9ZnxoGk5sMBeVPAW Y/8ehoqPYkUREvYFEWpEeUpgmcNAEVDuZhe1HZ8jNyClFwXvK8TehqEL8fdSf8oENyWmApw2YJLI mqKFJDUSU/pw8dWaVNFZxFPv5C20mGzIOziDcw173mgEwNpTNbHzYsXexMzrGvMtea++zbhHKZpe 3PxQQnuKtXHY/duGuoAvQEfpFn+6Zt1klFwf/TYNMPX1NtarE61hZc1U5d5jlGE079U/MAdmFF71 YLBpRncdT70H1B5lXk0uegApt1INW3hjkthpeNEIUWyJT9gw64oqimzONK/LwbHm60p8VneHO9SA JQVrnNz6v0PIydr5YdiHfxadcbB22B5N5DocwYXplSkamMzL8hA19RYAHTlsVMCF7nopMfTBUaH0 J5LB1WmCRy1m2UBrTv5DvXu+G3LYpof5N0fT+E04jXwY9dLPdWG+n/cD59/TAm2taGd0xloSkoC0 0B4uN1sxvDHqa+9X128M8uXR6x5m1wpDpeXFi1KPSLN6SA/FmwaREFNvH/uZEhH6foo45xA2MfUt htT8+4W1+jvc1j4dKdHqciU30zv0sBiFvzLx1zbCtWsrMfGoN2w8qRs9B9CMnoLvZc2uz6kFzfZo vwPCe9bN7zJr8WarTa6EEVfTjbXGRz7I38E0g592Uh+PhMQcQ+fmuC2RS5/aUf6XgrrZo4iJxk3f uEyK2+0vZbNla4KjDcxiO2iYVT/8ftsurXw3TB2XzrGjxGcMX3NzJz1ZeBYK3NCImdkxZGE1jYdJ Dj6sVTqTW7g+ynuAQEeYarHHAsRQgZZ/YPf0mWDmjsdbxiEE1o99v5Aluv7vU5ErIwLGb32yVsPx 1oPuynu2Kahltc0IebCMJUZ465dKE7j7tquNU5PDVVg9Atp/YoobiCj6zniUrHPDvb2qPQXfvUYH 2fRbhKADnxEK4tymYfppcLIgrq+/JSRIFPIIcrQPbdIJ09yu453UBXr/1VhMjzRfyJ2IC4kOuEWT bSVopFQDtQeLouUVMvEBkHYliGiWQqO60RIAU7J5NMSaqoJ/lUQlUXF8aQDkzgPahUQFc9eb9cPW 9fOAf1KMG0XAGG5mtosz3xFC3yBHS6Uk7Kf1hdfR4v5ACPwSud3V+rko4jjNLcnHh7hAh7LKqmz3 +k458eYq0CWI1MczPRHoDouidt/W9v/uaM2JKVAGRkJZXF0q6AM7mBTT9dES9DzXifRx18FFkA+H 8Uit64kzk4FGmUP2+rLNPLZcAb42ftskpODd6zpsJ7IoZY/rrNLD31VGyAtM+30CYLuOqNlNgkQN ZlLs8/mY6Vcj1eATJMbLaVEuUehjTXIBgUX5KxD0bjmxTqHr10qqoKY/A7e8tNc/qDFhzgwe57/c VwuH9WPfQCWtQzKWeGxVU/t7o3Ss6sfFvQeXXBAEpG28LvJVnGVpsL8/hw5DQvcOOrEcZichL2V3 yDiBljuOUlhvoCvoOQdxRpPgo7IWjCEOww/HEiddr5PPvqHGTzkQkrccexh/9u9abCIFa2IfDGod j2Zrwnlh6Fsv9oigvh+nq+FR49sX0TF2QCw8GV1Q6Kd/RNtCGBRzHU+T5xZP6C4j6awwfP4Qkg0+ 1Y3+rc3uM9MKD0O5V3vGMqbbGvH+xQ95THaOzYg7rWpXInJZAQ2hhFUXnAcWSls2ISfK0MDIEyCB 7Bq2ZdWAAiaKJwHsPG48pAw5kAQZSmeoRkgubVMzXdyVUq0dL5WQi25rFrxk5/9MRNJczHuc2YdR Ump6Lo5JtUZQoYyv0wyEoRyFUb5Td/zINv7FgXeEsEvvdSNfUYgurNWmHM1jwJMaLMj/HzbzW08/ gXhnTFO16aAgzT3bbFZd7kcjsdJ3nUYjC4AabmES6tWq9F42tn3OXWCgUjN2VafTkKqihGYvr84R r8RhFispWDjneaNg2ySWVV8mAwWRBWYafcrgJVf9cOl0ve0fL3CxsrwnporAmLvwRaqej4UjLisd hS2dYgw8GyGxKNDah97ST21NFJUocedY91GSH2opxxHppQMUhH2FVoRE0fLn7wl50wEAlVYu881c SjOsa4uirONZMwu3LioS/PMyK3o+PQAhWH9FTftUUWDIgfXEptdNtVo2Mhzpc2hrgvC5lGaKVAfJ aRKa5/4Q4IGLKIjBySrQPlpTBHIlTtAM1FcWngsa9QUbokdvsyUWShqi6yQR1w0yCOiF1N0csfb5 2w4wmlmLBrpiVtj5YK9muOAa+dfRz/kaj6ZrY2cjj6xLOXn2sxfuydSjqb0Oo3HwvG7Erv8P0eHo tU1cXw626CFoN4Dv3tJZP8Di3FwXfOWJ21oIfpAB8TT5GjBnKenxYPaRGvk+QzgFXrgmit3CKzQ9 Nor1hu/YgW+LOnN6bUcRJHcxgUYe6pr1EUYXhQMcHhDrOyIGDjlA9ftmrg3YlyNkAbYEpmP66WSb ILh/KqLMI+e9Cg0mH2/3h4ClA9YrGEEbXVr5ldS2GxQn0aQFSD2Xug2e04SK/jWAY1v1tX6/vNyK xKZjP24K+LV6vQ5GgJkJTdyuu+E1VGR1eLsq1vC0046qk/y3YWKI812oQZclPSNc5Y/q4BB8+Pgg XPm0BYh/0wup7yqmqEmX/o6s02yAQtDPblnAGQAX8ZjWHOXiEt5ZY5NF5uJuBsB+/Fl+Vp9Dfo8M ObkTyEbl2om6+CmkxsFQc/zwakXQwKisRZIUmNWvi5GNooDQerjxyLuW+Y8PO1LyFA68tgClBpsU Z2ViPYJ/tfoliCdPGbvhINuD4kYfaIVEmVGlOJ66HAtvRbP3C/ZLfitbm+hhGnIQtgNUo9PqgL4n pyeI4tXqpV4NWmzmzMgDc8155nSc1id/0z8tPGCfU9R9WOkkcYsfQlCBAbs33qYwbQU2ybWWMf4O wwmV+IorY2gRj226ftT3Z4Q+UZneDEkY1pnSg1uO4xewqPKHTDy7NRho+y1OEEN9A1BxDZ4CMQay 9Hs6i1wZdnpr6LcOvStbyr1f1bN8oNZkd/6+IFOn4Dth09t9EOMW8pNlU2AkbA1DNRVI4faZ1MvF 5fwiv1udrmQSJo8DvdQjcS68Nh1mzXOPKUZeG2zYj12dloNAsnAw8bgkH7yh6PG/CSoabOQCrCmh 7h/L0TfC+gvYIdE7H7/AjEFIMa0DA0UJQVuB8zcXOgV1XNIJc75nsOEpUpkhbTRN+FlOBf0urVya 2d1YWvYOAERHbkFWu78bHMp3e7qbJTI6Ks4UPDvciJdflpXVIr8lRdFmAiJj0toPoxkPh9apCccA lBRQogpDFXbEUCu1OwV49YJPC5u4AM3tV5jQvJBSPGXXh+rGLNRa5BcC7hVG9XQ4P0UMIikfIrlv KrF67OfCu+8ZVHz3loijz65q13tQaaNJlaExDYMDEKglJ2ThWU9KjzYCMH7NUwp7IBuAz1F6QIDj mdf8gVpnLriLgxuHMZfCM/7BHtW40MTHEJKwCSQ0gGcNAxibpNAXH9AgUiO/n6RIUEkK1mjvXEwM sWFhcfWBlE4XushgAaTTe2Cc9gpgv+caBmU+q0sWF1wjUA8wOvfyAJJqMUDTsfSmHmsQCApVJ3pL m0ad/A67ZeoZzlZPvpeZLM2YR/kCsvoxq3mn5bGqSUHxUsvlxvotG0yGlYjmfFCoW1d9X0T5NKZc h4PLluFcyykDZb11GqM3kaE07LbW/ppDIR8BmVHwWUjUSGNvYxOozvFc/71lb7fOpPx4ASkCx3kS /f3j0lMTO3igQHgMAgxeqBt6YzVtnpZX7tGJjPZ61FFX3ba/CmtdeZ4FU8BWUPJhqSlQ0GuaNcNC RXoOFntZaNiI4H912ONg8IF+/DnEubSf7W9cODhllt/PWmxDSCNE6tF9LXA9bGBG6gXTHtoirKKo kfTaujqJxJRUr324pOeC2sZFzSe1WAgWL6LE6so+n1IIKy0dwoEx5DglB9quhrmAhuY73aKh57zr MZhjOyyQSNcshY1oquMBlCXXQf+Nw6MeXVL7sJ/pKuQ5KVX8WxafmjP8PEMKZkBzsj/xSf5DsAld yzooH6nqhlCSZebq8RrE4eJ3J6rBACbs4/mmNH9KFHKaxkQAd0K4mtwKAi+du2INK2CXPJCASc4d BroZma2/zDbkKnmaDa92HqMAA+wQCdc6UrAebuEmff9Z3SP5vClRscnLRKEmFFKe0d0DPbffEmwl V3TuvPonUbnPdUqac8h+c97MmSePBAwfP7/Au/QuBFwg5Dq0gy3LbuJjzweqAGlssdObpq0INzV/ dXnDZhTDZdYewYfaVg0azVL3NszZsLJf1l/GgADAV1UnCcAXI6a+SRgOX8N0dsfv5SfAM8So6Vmc wXwVLjZOY8UjW8q/gjztwnmRSXSV3iLP1cmLe9T3guT8f5M5px/rFfOy+tXtDetOP18sBUthwsD6 GTEL0R9fTIDGuEwUBJ1XUfe9mj3O/V8a890O40HGqEJDr2M1AAkKHEySUw5nz6RVxYIUrbp8beLX 8tr40dKPFIXfEkpNk5wPalibs2y8ZyqR1x4FWRtjaReyQzvQmEM/SxTRLfh9Tr7wPgcuJOjQMgoS BkXvN195DVear0Xx39gjRZ9sB2vykFxaph6Ys33jR0w3vAY2m80J/TK6L1ZMk8Y5e9DP7ySbkCpS tuOvLaugUMsnY7f/FyaVgxzSHwwvv7Kw0Ah+GXUY5GX0AESuwXPQi3J2/5mzIlz54ZTpzN2SvuuM b/ZtBhUEqaWJL5hbsn6I1eRJsAiiaSm2u3ntvyLtcQBW1ecQPH5+2A3Bg+fJz9lQIJvsdruf/IT4 257JES8sbX1tAlUcZix4fWb6PGZT8dfY0HpiRaj/gcwrKl8uB27vipQkfqkiUZlp34iIOHm1VH/4 xwt9zxDsl9KwpXQIBrep1eGXhXBIl9j6RYQunfLVTvcGrhhfp6MPTSDc+RDUM81gOGfNWgEhWUng HHkZNoVwIwGmiydPaaKq9LvQdQF8hrxKcujIDwkhcUQY2kM7fRsQshcXJtAAwGbBMGQKLl1Vd7/K +kIwyREZ0asXG7ZAv2xoxiAEbMValYzZ0LA99sdxhNKVc82wTpnm90WD/RKlCPRv3Ei6xqpKDSu2 WKCXxcJGoZaXg0HiQo6c7QRaz7iwEhNpgCR4uFqWXSbyxHMrbJFNAnH5XU32++qKngHFusRGh8tF 0oV+LvROWULiHYEDBkdY1ZAPnTj/Mr3EyAm/DPfiPeS4QMs7p4ZCfaFD+oSAjdgf6mBttLmdrDbs qSWHE6u9lqD42102xQ2NSoqJOY6plMQRt9TUm/nfIRGhPOLr6ct1bsSZUMid6DAnWorgQJJTd27Z IyqbmWq/FlMmEQWu7UeM8JHzi3JHNsiVMZO0inx04iyrohJHz1nf7nIqfRAPEN1XSiWm8WdaeCuX Cq7FHkEx9IaC/Uqv2MLYLGveY5wLGrqvvJCpwYVTECRF3KkcOIDYymEagmVdMW6RspYs8NclsPDE IO/1Q/mKxsfQ59XuuYNlbhIjYdoeGmP9/gCqjJRqtZvvQ1VbZ5gKa2qJES1hCwahJ/qSyMeub73U uJDdpeTGwdPquReTNVr0g54Z4kCfo4xf3aJhj92PiVjZOUM3M8AlSDt9HrKj432YnToAD80hOnT/ Mg9wQpaseD+hHWkvlPOnb+GoeRrZ4u0GgAb2m8//hQrPMSzawnWfJJMU26WHiivoDlJPV/BX6Yps wzQVLtX+PRZ2+e4R+GsmoMvL0vqApkGOO0WgMAs22rgQaKS+go+1Z2sIzU4qR3x+1mFIpzGnTYge Ar4oMLkVZsCDiZe5rIkgQS/WjzU04W3+S0P4mUT8+0bKiv7FyvF+meQGszdcpwNHFwdaZN17hEG0 6MWDaNCqKdsVHOLrqHGKyWw8jduVhaVCFy7eCehTLj4YMLB2h4GZDa54gMiF7IKOCgRIR9ystu6o unQ5Df7C2hih5RxGEPYg+zb/UApmHLHNBgtJjok7c878/x3YK/rVGG74mWKGF6NmdQQ1p7nYz5lV iWywsnOAFqg/pGyDSdyUEE52G2vzRF5bOCqepRZBObTp6FfJIzOhvriFSEbz8fTsdfKUgZXV+IHV h1DyLUfgjLvqf1CwxARdzj3Qux+vfoH5te1rM0CHGkDpDFEdP+LBv3fV08h/FAABJbu/lVHf3AcB 2IPlCbaLszZo7F51PBw+XeMuYUIjfwVSDEOJ+1Sa8cPOGa1bx4iuWqKGnPe+JOK6fL+RFa5VVkKv KqKRKb9XnibmxZUed0+04Rr1soXWgJ8A/xSJFySYqTMCZ4MKcdNcbTNARRjSktPCelLlPv5i6Lbu 6f0vFnyTHPlqVjouYzJSwRez+efzmsJxr5DsdQlHXaKmI+rNVeOqMkJd6AbER6X5j+qXC6YJ17nM P/vvk0E9gQ6oN76aldmPgtx2divqAIC3sW+2imTNModytQo8ZwXTJ3MMH1WPnIXrZB5PfG0zBZ0Q PvSVoJqhbPeEpEsHLmAYvoveVTxndx/8kthnJsj3mZOWAyjw88J1bM2EVX9lPoifPKOvQu8t7fMB /Z5UAKTpMXlqnR++gHETtS9+Rv0PpjlkshX5VfXv51c2dSrs4nfnoUNM7dU2EUTbxoHutdw58NPT KrKD5Nrsaa5f27q97SLgQciGM/oQZqlJg05UslfTz/0dSEWod6O8JfSbel9PMa3Hw7GBUegdtIWG zd1ExMTRpLB3QVNwaVQxi/vp6LbbB0Tn63DEVgzf0pOXUkmEh54QHiigHRyp4qnWgQlrTM0qz8Kn 00idX4UIV9lwk8oHWGCPoGs+YtUdOBe+ZXhH/IM+BPQrTC4lgv7LWMNSP39C+Dq5vVtGqSppA495 M2akQU1w6iCZq+/5jqm+fIyE0R9V5ET7vILzRvQczZ4m/czezGyWHlyQ9jojQb5ZeMSfURV9Zp+A yVFoakMRnSiJcVnfKSw3drbafpFLgzJNVzAfWXakzGXZxw2lroidEv5+goLssCbhS0KbyhClQQ6A 8BnMWC4fgzMqh6AsafbyKJNy2NL9fDiJ8MzR7s0rsyKSS3s7iu0tEMb9ODm1xwLhhsWOh7sz80SQ Kv1MIg1XB3IKgOGxkmjNeaAuPr+XYxbQ0XyGas12xqDlfQsIZhoCAk/92+66vZyyOoHTAVQoQ/Gw SJ/CD7y5/qRxCJwsftgH9wpY4w90hJdl6w0ymBrhBNdgio9/WN/BGazZaotZfQ5ISPLGTG/HQXrG +j6PtWb3xI71S6UMhrECd4eTM0KeEGSj5YO0j5mbNd4EinusLr7duMeFNzg14hypCMZECZ1pKARy phNLhDjvHUdY8ly668RF0NV6hOXAcCZ9tgW52V5Gr+VzKu7yof0uMjBiNe5JDOnrkBN6vPCgI8SK FOjjqXt5mG/Y9egBCrd7b1nLxAkZez7Sp/xrsKW+l7eT8lHgIBwe8WlGrVzvx3JS4KQLtOtpYK1A vQz2f+qjiMV2HRUgC5fXuy9YOKKleHMJkAyZ8dlL60SdltvpLMWBMJJP0C330x+yhUTVTX3XWIIN KIC1t9oKOggoekMbMLLe3JXUX3BCxmcA32dH1u1Rvqr6Zn/BBCjQ82C2YkoC/a3m/EpQAcj+6lZO 6YlcLLOqsYvbfmJlG2J7edgQ66q4AztKPXwTRpJTgvOII4+a5j6v+OAk3dyTUBdTLh5B3XnZGo5Y ww4BMlXxBwn2CyLdzJ2mkqoPScO6KHdGq4cpbb3WNKNI556oA+x+g4mjNsdIqJN9pUqQkAt1SUQo D6wfjnEFgoeBXS6uRlQylYJqkc44DtH1DvkHk89Wj3cs8SqTBwFY+lgQrQI65U9caRP9SxQ118JI JsVL10NhlDqEuwoyG0zMeBMcRKDGS9GhTwl2zS8OS5ORmi+pDE+t6P9lAb+ZcXgryggwruL4jyzZ SpQ79bkEWPR9Fz5eTjWb55SoIxRx1iwt8fZ0nYFsuEgs3bnAQv19toadBh8mbvG48v+Cnnpm/hX8 CJg1Co5BrsdEANnsruLsAnEnLpDpKhVNHbuMU9cRXuxbKceRk/m8qGrzXEaPW2a4SSpbjhGjG04H qae/T+f2r88Ze18MyOL6Q37cscczWda0Wbp3X+4NaiUpz45hgcXJGpDgUN6aYxnIuccWsw7HLs4O PGF8ohqmj5WRiqb1BNJNlyaCdyXm8i7j8kzK8+GjDXFhmrhKb/vjWpvpJIBZTQ7jaqSsi3Uvt6WS hjzmKOvFJ/Gk/X3u1V9oxtzHy/b9qGqVp//oXKL+fh/RWvumrxTg4UYp0Q8mb/qDBqnfiUYlN4r4 mxHEcfkbnrArjOwM585I9QOjbkfHKF07zh7gtiRFov694rMoBHQzJKsEMxT4WNclGgZt2W/q5/9X Knn1gQxM1KAZIDI0SItmp+fRXKEX+IoZPIaHudmE7Gvzp62ArsKO6nsPNvq/ommHkIJtnNWrWfaL sRvgdTZSS2sLNjcxDmTYRzCB6wbFS9I2QEiuVWJOBViVPvqg9VNxCkmmKD/DyKOpuDYerMJudusq H7HBmNkIS4IDMeb02b0oHGeO5dPz08G5JU2xDdL4C28Nzu8bghbenxAfGVL+Bj8ZQq4nzmIsBjlJ 9lA3gQTiJfA7l85pdYoSv/iSAG9Wv2JpUc+q1F2PDSx0+8Seu+MoQ2FOq+iMJvYGagintuGF3xkB kx38+KaMmKIwJie+5BnrKVqCvQUOYe4B4s91wSsjnciOa9alXWPg93NTpbVpVZdjtCbY5z6e3T4Q oRW8HYu0QQPKoKJVFcoJlWLKYm/CClNBnXb7FnGnMSb/tEX9dtOhpu/isJRsDB6l5C3U0HKm+cci NKYyRH6KqhfUIzzzgHMkKh63TxuRLInkj1MbEAcx56dxRGkGQsdw4PdOoTK1gLKl44557HBcaO1g HpIKMWREFv1n1UgTod3tffdBzrsAnxzNpH2Mu+6dAWKkteYWNlsBx7ZIDuCMhVOxI4h14P7cjyMU 152kBNyFGTcyo1bZg2uHP86V5+NHqgLCt7KZilaW7WvqX8Cw4+15+/m9DO0i3kYsQvQ9NpA2fBvZ vkLyEoIAGinetgoR+e20V760LT2kIIMFvUSBr+0O8Ai/vAXu6A4vCr5yQD0B23njgmjWFYEp9/QH 4AoGvsjv1SQXtjIJnIrigRolituaLTAr0IAVcr6lsJM/FH+OL+bF1g+gnxV5pK2e52gjhBmJNchR 6p5JTt0Rz8YoRpJsyT8jcfNwOgu9kkjFMfMOuy4srN1VZ+CMXV+Mn2OKtgU9vw+Tea+A1SRr4ua9 OZVT3XBTYsOrb2O4/ZUc4mQv12LJjxowKdEGqAd29r9++NXwOP0MoxMJQVz1d89mN3w7bTBgB0lJ u3ddHfjl+mT7+1pJhOPf9R4pqQiTjOVXnIXQNv4Wg7hzi9ZdW1a0GIYH8A6BNkEP2NDJXc6KOdPY vYe5EgaDw2xq5i/MfSQaWYtPvhBUWRpdCWxv55RhGm/2XZEkL9pM6GbE6OZ9I21bfBWy9Mqom0tE gR42674SzuAYU9DOpAKZjjMTQG1aI8xbL6ZSPy11kz1lAEzjKE1YjWgGwkIbqr1+KRZBV+DkrU8B RRE0x+Lb0nDfoDBte6ClijBF6mTbKpZU9x/0CFi2tbeAkfM7OtO3mgb6rfCctuPAM1IDLeAPy3oa oK//bRfeGX0aNEc0VA4GY/sXo5Nyf/4MGxdwcqWxRG7E/nM2plEX0D5gp92mq9KDyWpeY7hFQkoD Gx2CcVGvNOkeyJDIgwslvll54HVR+EK+S0cZcPjZ/cRbFqd/zuy2L1QhEzs7WMg33YHLUI9EaKPt duF3WuhPpntrEPuZ8wzyxpni6dlkJgOWi8K4QtCXjih9Wdrg7EGa75Fc1Or70psN0NQiKebcQs3W r82bg+r3KUGlihet/PqL/B/pLTo7zDnUNomX+hqx0IZzwQxv38McUuwXd3mAs+ieiNU4RrAEt4YB C7JHkStOhxWjxLRu6+BqbdZBeo86xU2HR22gu7ZUV1SGV2jd6Jiw5kNldvexh69b639XPCi29xss kXSYmeuyNEWkKo7xct7Vm/bjoOhIrQ/M8WTWIX5bApX7NS/iVXpDMqur+QIyjsCnAwm8y/S99D0d YAEyTR4UcrY3FwFHvJrEqNKI01EUj/nl5ivgPml8Z+7kJQmzBDKY13j4Qk2BW03o7M49TUSJzVcP sYlpUVDNYDIolke71q8rC8XuPGIR/BN7dELz3cbCrOxZ5DdMyED6X8VPWRY5k6E6T0XCkGWDJQVg cNxftCxQuTXrOvg5caBR83i3pnEOStr7nQxpgtPr9Va6mNMkbpa1XluDvk4i0GOk4tGZ9shlG54e greAfwfi+T2hnlx4iyu7FFCfWnV4lufXiVrXHHDB2+H2M6TpEr7LzgFjAATjh8R2MMAc3nZ3LhS4 ILLDjvBPLp9zqByjOYA/TJ2Gypk8wvqMGpxnwv+f6et/Spdz1M/6uJmYkwP7KxQFMiNocsvdiVuP YZsqKz4DQDI4TVfzYVUkGpM+tLWbsgCOuJNug/ypT/6cIZwx47H9BiNFrGY0k5X86631SIEcNrnj l2b63AFslu+hEkBs4Vv+yWpI/xHEct9h2LYfu6lZ2k4SDe2gEdDlRRg0V+2XXNdshHznkWYScRnU AoNbp/uMR0MISO1e6oCqYoAG/lyMKl6BgqsussiKhFDBgGB95B7uc2g+Ow0xlrubc0/n7qnR2dqk MoHj3bVgwh7ujdiP+6soUP/ejU0E3fS83Axukj9hpH87KcKlJfQEEZ2hgxz12l7q9w+OyfMuDMKL dUfIgmCp7ZgypdkTgeGTEJLiYlYG4UiGIvps035aZg5aq+CuNURiJEpyb8H2y0vs6zJiDeHRrpH9 0Ifp9EEQ/AyYwkt/nwoGMHTQozB7kM4Tl8PoERfNSYjF87eBm2mV2BAl2yWyl7y/rkoR49e0bin3 XnOa9B4xS3hS+HIY53wZ61+sX+2lQSFyV55dOjHcPKjrzx+NprLNhAGOKP6tziII17ydX5/NDlg0 oxFXoc0cExiVGTlI4e7y/BhFXAfbqWgrga+K6PxNRcVswLwc9fb9dQ9vURGXXAac+R8BQ+5b//jL vOduoHXPhE60EkO0K3GxwUstG0tneeajZOwz/PyNGkaK4ZHDIdmTMQAmPjAV9m/SN6x5zlcbthMX dKLxxBxhNC/VOEK0INNuDYthii1tTSnzMi+KO4VmjslQj2GQPQVqbKfiwTFAcFra1U6JhCGO2HBx ZVZ3iGXTgjzm/A9dY8zZMyn9qqJ6zkOAdcZamHVhZBVPF0g4SnZOOacvmWNbRHtxNsbSgHpX328s LGOYRhrcRTimmTT6h4U7IlAlbZiym936AUrzgbldh1TSlZKA+usKgtNtdfShKlL/cmRaac4sdMTN KAofjpc77dJ3jnsvRznonNLpcEpmjsrk1vaZ+jX9TWjbjWGvIwzhkKrc2EZF/vVxTdcrwGdae/Oy XzxbmZmzWeOzLiib419BD44gGkCwjC8TpNBh8XRUzmvv+vu3FxhDNWYsubiOOaF3AKw/MCosnyEB 5guJKPSTX+izf/KBWc3Uve/Kgc+WXGa4c4ka6pOfyKTu3zSzMylg7fHt3PVf5xwd2v/Kzzs1qnqL 0V/FKkFaxBc5q81Sy6GhiydOf504m29yy1Gh9IFPrH2NykRiQiWTyB1ekccUkdZWoidXNXM4JXfl ffnGy9Eb2hQRZNoA2yv6uW0cnzggZfpcVXtvymUKjfiHg7FwLpwDxSNCtrobIM2SrsidB5TO1q/K 55eEYlyAIjMQBGQa+LCZ0UAsNXY+CYB6eGNzUallp/PJtaKiYliILQpOt8GQcmpMWjEaFVZ1BW0f iSb9nVGchoRUQdnI2eyZSkrjm8dvqPcRz91Ps2x72n7AXD85bloOJVshMTPyR/8/oaaxMI1xuX+F 6XVkhYdW+/wPXc8fmXRnXnWMAbbvP41+2FOPlCQRRLXUYwIMjg3dKYGejAtWbsx/aep82Zrltwbi u4MtNufPcylx6y9UhVIw3/DOvzQtWcIF5dyL227awxYXLgrKMJtEtZaq9nunoxrBT5TsJGS8Utmq WZwUFBoKGU5rrCiO7QLTMlE3Bwy38XP+hpzWfuNhyJOLa5jOIi9j0eUq5wuyixFJllZQzEo4iBuj o9p6qTui/fVwtrEhecoFTNvfFBMvZs1GWaOiMYIeHypIs/JaZZsR4KxR5nJdP5j7ghdcPEPplgSU cpCByYaziT09ITmLZF2Pn8GbdResoi1E2dbjpn2U8+vxFFzi4dgKk285uqTRFAhM+DqjKCuvdH9E fZzj4hWDX8YGLzlkj6dPrllInQeDh2CAYChq4fUxHN7PCT7sQ1XZoMDgZEDQUJPJCwFjjdacEwt8 CCJ0sN61tyokDtWy2Nwis/Xvmd7rUlme49Nd1XblSQ4grjILQCq69OucejKC3HsQE/IToGo0vWGb UNSkjgpo6iPRCbftMyqWNlWRfQpjR5CzsJvEcpIqwrGTKurVAVu0xi2yrE7skzJ1UIn9HMI1VRUb oRL7mWSABSOorx/PUtjCV21Gf2Oi7WQtO9qiBqOVD2+Yp9PypHKJ2Z60pr91ADE0SON54ugtF78/ W+cDE/4dThY9/j5gRbfgPm8+z3ApQngTG92EkNs1iKmR1wyweR0TAjcRADr0THM3VEioIbuq3YM1 7U2xp6RUecKquVBzkJozz9hh8XmMvkhZIg/4X/c2ezMCBz9axGzgE2otW9L/sgoZ+38YmYfbIAXN 6WWXD+az8bqbWUk6BUnUSlvgtvR/iUrWbWS+hab3WgHGg7WoUSNJrcTyOBnbIxsCnymXlgFo0uZp ElBlBx/FZh1rj5DSBRUnjbcoBjMPr2D4rgN7yZp1VBlwwC6lldxrdcvzqqgp4sQgri19odPaSfQu S3e2aiIt5DMbke01v4AaGoWAouOagwfLpyWIZiYQzejw83OU3LG+EdBdXkXImNSTSuMT19b31p6J bBqjSFkvmZi+2U/KG1iVqlnJZhRKzHee1estNGHDC3d/gYuHDahU0ntTIJEXb6GehmlBbWjA9C2C mb8AdVadKvzGDeiabJa+gUTdzAQYZ5ADT5WXM35Jqy1edJVT6kmsuQASXf9dgYz5dw6DEVFt5GJS gn1RcXLM4IiV2OnR58+imiC85ge6wEfrRSxTe7bwkJ30NP9KQd3dp1dKjDwbttQ0Jw7UwD5wMTwh t74zgEInu0+bPj330exW+0JcA62KsTbt3NTmzSpVQvLhPZ/5RiOtgnM+gJEUEyEH8oIvluUEeKyZ 8AuapeDYU9CgiE9gyJYNZsul1YzGKnZbtukPnxUcIrtfkfVhN/OX1yZiL8+s30HGiAzQO4zkPoEq 5SmfdhqOIKhi8lG5ig2l5D68QgSe72La1mXslr+rHlOUtTpHJUmE71o/iaBjZmhDURcWgWou203Z Lfm8yo4B0DYaSkw4f2mjw6qHarPrd2ut6D7KDu2tSclGmXSjDcsrE1LTyAksW9esaJSXsjR8qo7x g/7DpiXn9EdSkAfwQHDd3sgqimwtMqwQlAH2Mm063glQKm09n6PwhPLK6PWmkeFrFEXpai/I8wVe 6Fwxn8kTeEierogzvXZUESm5rlV8K2ZxyUVMDB7mT+5udOFg7MGiDDDKb7UttfjMYc3JfCo7j+1z sfl13hd6jTei7B4/iJ22b4juvXWqftTxQKAaF0XLXRcn0YTmbla+pZwPx5/pUuRJd87Xb8Gp5pPv BhnYXIHI4X6opB09+Ro6nq8P/By+ZsFaCsTqNU7S7HgwRn9IG6hJQZf9h6djeuRnRecUw++X+B+a YtJCpQ44e2gQpZhiF7dQ7t4qtaoqtPN8fp9LEHjMKONHaUpYLSXig81m8vzGBtdSfZWNidXycx7V TKJ7cBvO8nW/SjnGWeOLpUpiV3JJgDl6LVuptRJmx0RWlEZeYJhftDYpdv3UimAiQX4G0vqt0jU4 IJ1vnMS4eIix2M5AoN5OZYqkh2en6ETY4ymOVXcrQD+MtJ5G4f/BAP9W3S2kAP2/xA9hq+oGBoty uobUe4xA2hRn4bt6lYoyUU4HJqZNcT7ZSrQjh6BuMu8NFgtDpc6jkTGP610mORVZYwYhq1j2GrX6 JGuC/sVlUbFtIi6UkYBJfOAce/ioipn250UBuTrqRZAJevSR2Pz17TMuuwQOWhag1KBmhKQMSUZ3 aAXihBLduRkQ1P2QXtXzRyWpENJpt2ofstkw1kFoE2wPi6HOzUM1XF43XJ43A1exMpKOVb5ENVwB DwDTMCAswoF4ORXGapUA/tQ1RXoVFYkS4dgztIA1BF/LIc6zw09EOIMX5eiVvRxAiVMrRpT55scy aCRuLD3ouqT07FG+UZi5a0ZdPYkUm2rG58XCfpqf3pGeJVHZ1Dy++cMQY5jZZWrCIxxE7TpfQBhy h0/DA1b9KnS72TkZdfTMwCAe9fU+0hdeCz3hhrnIDyyVTSM0+Zq2SF8tZsEQDaMaHNkhr/AjiNG/ WHPPaRW4ySInPeZjStdbIMQzexyl4MuEsk9LKuptF9NU8abcUA+KSsExXLRHpq35LS7hhEW/gDv+ ggLP+oGlsRlndCeHfNMCq+Qkp/ItT92EeYaBi+Na6GBfSGeNFZTzkbFwedZvThdLkFW8KK+ls1b8 pLK0vu5clqEb2RaPwJG1yoPztEQ1ZP3KD0x0Lu1k5ev2WJ+Zf04mGou3gdWE+6wu6tFisbQ5agRj jeX6eBCkMHoaqU0/xQoE1/z37twAm6EujI+MWC1FNyFY48H5tGcem6sbT+nRCjhCf+NRL0frNDUZ FhYe6A4zdRuElMbHtyfIOy1RJtFOIUpidKM0rpVuTzpgjazAhhQdePtzFSc4kgxdaksukJ1o+I+e OIMnV1d1XH10w52P9LdQN5do21wyxxCEgo/TqD/Kc+iJ4JTWLYosjDv52bIDOCh/kyGyRl54tHaA LonHCg7EMt4kuJe57u8RCBjaQwdeqBN/AE6j5BRBi7Oc0f81Ju13BaM1rcGTQqoUcCV91ekc82BS LdrBTt+a+udOcjHnFGk5nKggW6dCNlSc0P/TLKOb1iKUmf9jUNF2ICsNJ1u5WADq14XHNEh0m2GE oz0m1uJRXKVan7eOWhQ60usvmh0Lvu/yu11wwaTd4rHdpHySoRU5SOVMb8zrFGZQqIYpAu82zZrm +6PnxxMfAlCmoK22ZvjTdByIHHmOtSeujQM8oP9qHyFMHTU7p5lsEPjzTvDROF6I2Oc1vzYoTKIq UNz7XcrV+mv7V4y5ocPcc6MT/pEW8i8yxVAmb5MAAqKVKBfh52sspCYLKe+YWlFD7EPVOceD/R8w NrIlfTjlA3/rVGWNaerJciojDYiL9aH+1aWj6Iju6ByD7p6sBlAb19tcG6xb3SomsCMJfBY1CAUn Rop8qtJkGNvMItu/h2ICNRaN7zdEEgZXftMpHc7MNfAPPyL+6tWp5gd1ohjlV/urOQUnGo/rIncW OFo4CKcIb2zMSSVn5V3XHdID1H6/S12qUjVV3z/znMo0CUG849el/LAIpmSFHdZvNmQVSi2lue7H wbvoYGEReG9VwwWbfZj7Ma/urZHiK9N3mfT2c52cs+tkpDK1PTTSIMOl0Pa2sJrXG1q9oze8RiK3 RxzHaKOmSEKPmA5H3DNxgiIvt8LjiNJ3g+FF0iwU89EWvCjqdj+jQOGwXLWAhSjCSPJ7BpK/2vNe pBUAfwquHMklqNXn0uTHe4a5plZ74IDipwcZcgkJWpZ76WrzEn3NHy710ptzWuOI6GRFPoj/7CYS 5fUWVoIz9GnxEhhivuEgdialv5KhBGF3dlcgzoK477o5umK3l6ZMTE7TAklzruEbDrBxqT8FQZmA vxKfR8jiZf90uBJwuQ8IOQIRUkFtJDNaLaoGmqQT2hZCNWu1h2dJmnsZWqOyxx60jyYb8xBlTlIO 4f3gaL8myYeyX5Xpot7fzXTMZO/LMiA/5yO/NxhT141NhUVzNn/Cgxa18KqwSQKFftPIXAupUN0J uVnvj56pKsjO108ySMlywX94ZIaujwNF+5X5YgINhCLC5mFBY4WOcpGy0ZBM0Y13T30J2Lx6fv6O tHMNBRyyWHh0a4XiPPgiW3CjdWnJF7B+k24f6f1JcWsZhFY+AesdWueNEifKhHzfZHDXfWxHr/70 64+muGzLfOmVdIizX6usSe47ZwYozCwth1SWcEpTSfLJd74FFPWqwJjUCI1YqERE/4crEKaoK1nq ebN2gcc8gbxejSDzS8IdBso10+XCxSq0Kab+ESJx/2rrunrCf2OKuIGz38fRPP5fiNG9d5P+aISE 6CkHJGLqQkYt0+VRfj06p5X3PcVNDe6jmnGC+LsZS39GWk9y7F4wnCujgkCgDX8g7jLZEr0ZC3C+ 4JgZMJqigb5rMmlA9zetWa9SK4XFQ95d2Lf+KU4BoBk5dCpoS6z4wQfbSyTnRKVVUHGdzhDW/Omi xZbp3pshT508JSSQ9T7GVjk7E9u7v4Fn/KjORgBS0fujvVglKGH/Uigwd3tw4O5WY52Mu8//pMqw YW8rboWQiYJ6Dk6dgCM9FkP9mrcDZQlh6Y/KshE+3NRpnwdz/5nQV3EerUDXrEoPt1sDtV3oJ6Ct NrMmty8HUU9hiLhcNRpw7OyDDwSAbL6hm/Y0A0b23M5/cOGVRL1pgu0eIvV3DHIgTXZsoD/NaZGW JY9AQlILFSgrG/TIDZOKxTrRbkjRfQgZECChAi2GVBRHFpbjJNomnkbCEh2k5xMI+78uCiYg41Ku ICRKlELAIyx79xy/OYLbYXDo1tUOxjg6iupa3K9UarXlX1Ba4Kc24hGcvPOKfTo9kiLtqVl3710g jrthiDbtFmhqtzb1BerLypihlLzv3LurHFraRYVB3TTO8LccZtP+OA2hdIic4lF292HMVZ0SUusp dHGaHIOlonNXnHLD6xQUk0sOnDYAUJQcjPrWcBs4cBEtWScLmc1o1nQAObdij0ZuvSZyKfVEB9qR EOnR/iU4J7yAqlYZUMPCgR/W8ESdOaJc8G+x0l3ybBDF6xvDzz5TUVfMz9CeXYKI9+W8ImikST1d DZVj67Cg1ctgpNkfhS7cPn0Jlhw2vzLy/b5RG6CZMWt1jGsr1eT17QJIvVtnBRee9kd7f0VbW6AE iQx57NKyFdcBGOM3tx+5isvJoU1eKft9SVeDKLieIF5Az2uAHXWEmYw/yYFJLkJDn9pwMkPtynEo YDwUb9aOZccJKGG0a6ZgI/NUA6sGhsQLSKByxfzLHc9sfzUmcG44LsTDStzqC2bHGqF7S7eQ1oxb f94hvQTX81+OQ5dBb9aulCYqNPa90hEWqn4sJsjRhQFAAC0DuVaD7XmscnRjgVjfL9KJ7nqHwrsa f3l0MuLp+NPkFCFbj8TDw76xDS8e9yCw+VgWfCvztkWwj2bg/IC6m8bokYb0iVellg/XBRk36eDu 759klzZVFiGTV1q1nJofTOjAv/Z6g+WwKQSLSiC7ed+ThhyVB39Dam+DkXvBJB0iMszDlVkZG3zX ubR+iWtocKVcT0xfAVdCONJ0r+RSi14DFtdQvaokvRO2bV4y0b+G9OcTAbptjeCCrs4gsC7Ns+X1 Lz22ZrJaBnzryGduvrR5k/8j7zvIHJoMvh9bZcbHFKX4Sw8b0g4FcrS1sxA1QXTYWS7hgQQ5UELf OejGLfXV2mwbqY9lptGGtV/H8rhXCCAQE9cKYOjmDdZOYqF2tldLRgJqZO1dnRSCERVi6HzLw/KV IM7hu7usuRh/JDD03tbBbO1ZwWHY4dUmp6SZGCTArc7Bw7wNovS5pFN3zNPNzcKoo++s/SOpENLq Sfs/A7UDJMbmGJNFN2027z0T9Ho9yE9iszsLqrJBC56uuPwUBOmlGe9yfw4tL9dMThJi4jJOq7IS zyVyC5gh8JpFc7fJwyXl8d1HTlCcGnx4mJQ+0j+aNFiwKs5cUymT6w3UUuBS86Tt/tTS7opxaoix l5v6DjWq5brJIxE7KjlUVtOnGKKHQ9t8wakfKkrsP2OkPbJl6xc3Yizg3Sz3zp3khc/1oJkCHbKm zLcxE1dKskpISN6klPd/dLIH72eoHMPSXbj28pEQKSQ5rtTzo0YFwmHJyFuieo63xpo5UgB64HLf 1FG1A6A/A9o2MU+gMkeFbD0kBjeT82n4CemPQP92UaZ6WUm1tizaPc/ptem7dX6OfbeX1JU+ZB/X AvUGT5eTYH1Lk2YXNokG9eQyoMUbFcG00Nzkweh+DLu1/TuGdTXeBTMTYAT2VYI2jMQych0cNFBu sp3KUXJIfKS4GAEm+NXPy0u8mANB67lpSNAn9PaLuIXLY+KYi8Le2k0cO38qiouKB2I3incagwD0 gklvSFaHftcqZ2RBHvWbJL6xMje8st4/npBPq8vOcD4Vupe/ZxD9Fy3+hUiNWNfAnUIpgTzD+0HH 4PLfR2PtpcP3SF6DQUuqLDjNUbrDGvSood8FKsj7EN2EY5sPoD+vu5ftQv676VrMMXHhTIAkMnM1 6Gu46m4G7dZAk+MQBs+ZaPQyTFNa+z+ISacQkIBOlwnCudN2my9C88kmkJiR3YCgqo5Nhy3sFU4C qxhai+JbklOX8mkCOFwizKqxHN6ehMkob9e3LhZbziX58qDu4vueTgasnc5Mi2AAMKw5vAdcYrUY TiMOQST5MPGYR3M+dJ1+zg2BqDBMijdgCup/OZiHvpV06hBEQJCiLBTeuf9IOJkS53aI2BlSbVmi 5RyAmv+ZRmyLNZohzMt+3S8RmyZZ75RUA0aj99eY9TyBkpqbaEX+wBwTqIG+St78EW3aPFbHToD1 RrsN4/9MtCy2uZMdhBBEsJ4yFI4I/TV4QYQR+d/z/rSmuln/+TtA+uGH+AbT0AT3HwEo+U2TScBo 3InK1LGj4+gttZgebyOjX1pwnBTRxrM1OHxRUmUxzkdQLVnjzm74OW0AZxCLvVs9/lw4UlM2uSxB UVvoS+9S9T1olpOVmxyUe1x0rUTbRex6RKGH7NLKqpdYTIlPwkXbA7ikZ/0ymCiYw1GV8bodMx44 5PR7s2Vvf7557sxdg9wrXdk1OgN9z9tbZ9g95GBTbk8V/f9IxAlB9AjPcM+t4ZXilQQ6QJYslFCK hvYRwQk9KY/D9UWFIkx0RQjK6rF0wDyRaoR4uEtFcH5aqqeVU9w6Z6pOlU/ApvcC4oX2zPETA5ZY 3id3lkEMDreo7xFLEbvBjWlR4ZM/PA44tzpiGv94ho+zsyy5K4lMMhaXMMDzbIdBfgJHy2S2e+dI 4N3/kR+Hf6HZs+RR/8hel01Eo74Y8pqZ8e03SMz+ewo9opB6v+ILONmqrqIIQuvFSjlhe4EA5hTc Sbkpii0+Wo4kpFLenTSoPmixk+kHIUfty8hGtgn1xtlKtGvd3zTT4SmUzoLDxWrUZbf+4QeXXxuK cDEQ4PxUqW7J/EgkE+ek+OVD0VXIyUavPj/kDiEY6N0pHHBqaXNe5sOIGnG/Z3L9RnORI1mTNs1J XRSk9IplVCuGpo3f6qPye5q2jyonRoTzWgrTGGrDbZzK/tu3LGpVwMBrMVxAVow15K4HDBpXrxjw HxcB+5wrA0k2hHildSC6+6X1LtwY6WXEPhKHW9squWCPZyxehHvpcs+xG/EV7kDtnUDyLm7PLrHt hKYJcZPRbiwO+3XxXHKD61WUcWZG38wyey3BzSfbhyTFKuAEHf8/NvpSc/CRWQNFkqP8Bk1T5ME7 Jt3kFYE0pcLlZhnjsqiG6zTlyTTvyDiUndk/O4TSoU+8ovREMMgjK8PECyXquDiUEamHACNCaqTg GIUEt3gb/47Ujxd1pi7EQ62beb7qMIop0GHignDBpto8XML+IO9KLuo3287+qj8h555z+fCdXtNm 4HzV8HZxYtx7f43hzbCL4Tazu6JxOjG++ybhf5QwYphCZW5n+yRN3rqEpdHcRhHec1yWX1scMssp HmEPcszRA6ph5FJqlxArV1LgJPVRpRRGJ3tGCEtIQQrOpfbI3SrIoNsZMu7UuZH+sFdLyemUKr9T 6yHyr8cEgVMtmn7oqQiClEqBb4SPdAJnk489e0KJQ+9Af4G+e/5ekRW9L7Z9dQirAPIgKciMfv5h 9W3kNrpHfRBjJgrMTNHBm8P1Su+EL3idw5x7/D9RTlFo9mWJOczdTyZMxJcJa44eFJFvvXjCjviB EzlPhk1NYVoUwiW/HIr636T4iPpKo3JTmTUH1fIthFF6U0TVa1Nld4m6I5rk5GQnXGSpgTMVVeAU U+4M14Mzx6ZsAb7s6MJetZ1mvxdvUO21iMGSQKMhfjtnXRAxKwb6I2CmGAndZ773xRc3j+/XN831 2JTPh/pqhxTDunpGrg1IRejnGP6qMzGxBV6TpY0v0hgE0d7yNzG7wBFiSCePYpHO8hbFiMvGHg6H v2MGvGXL8Cuh5RkkRoT5gFjMJJm71t2aCCK/+xkPuAbxASbV+os2CJ7ZfqG/qe17Grn7Hju5Bybm bmqfi+c0cESsKMvpbW0vLqG0m/cCiQfNbrGSIKvwLtS/dnpbcfTodKdlIMRuLJPufVhW+HLMZT6J oC16rDaOdnNsL7L9tVedEeFz/cZSde9llA09N90da/GfjqOcl/xge4eesQ1uaWx0K/5N0N+/T6Eg riGQlr6IxhouK3GuWcoRHQAirI7VysyMAAY5zFGWi4JK7lgvrCDaAub4+AzhKzFsWwb9a85PKnP5 90+iDEWeUiSv70JVCqQFM2hEqi/fZDs8wClI6JlcVL8hXTXzjjWEO6Wf3iBbMm/H5VdTeYy4PutC +bjCP7AYdSQsl+CjBsy1S3THeYGMl7cNxv13Sh9Zoa86i43DOGHJgbpe8cjrYd4JEmoSzK6P6X1m pdSIQDZpDJCP1KpFOGXBWHmAvlHtgu6AAO8dCANNJ4N9gwMZ9+CKHLLBvwLuq87xdu/QkFS5jNlA WGB7selyDQnqVzdi2LyzE7DDiFLD8NLDfvfQA7mWiaD1ZK0j4K4kco6TNrk39KL6RsIZTe28/DuK vAe0wEVWSFDNZuSK3ZKU3/jLLWJDpQ8jJW9OxsoXKHbuIEGn81Jxb9sgAQLMZMLfG+avA4YEVmx5 9yVm8psehuw75wSACjGtDApnG9GC0jMQN1YECUlR/I9I1U+I5BKS73O8OVaJIRwSqezlen1OQvFH x5TaSDKHcToKOTXk4VHzyjeXpRedOHBq7hofzRCTiS5vqlKbPl4wjcOp/Z9cU1UuvhfLIG5ZU2b+ 9VLFTh6IoD+9iHtADeIxmy88/u61YmVgZUeOUsz/3Ky5BseyJdUbqMII+gLKsslbyq7/JADAsHE/ rD0A8SpgfQS07gyCFlqVm0tMlZ90DrOhqqSSJGJLyVCFaAAjLYhl4enZp6efNtuKfeJ4VjFCbxxn rZQccPxIKruZgmRrStBRAifBs3Luk41DWZaaAiw+mdxi8WcKYF+e6n3hyJ2REaIRsEECMHc9JCJ3 ncS95ZXXWRxfWXB4T9IuSOehWTZYfhDoWI0s3jZzlhBS1SeRClNssNuWbhlU3Jn4XFPnmgUcbS95 Q0UfGkWTD5Ik0NC+drsH5QwWUatFv9ka6v29ETGrnqfR8A7X4rjVLSfCL5BPO80h5NtG41iKk0zs ioRWNlqV9l3LRoWTRtS/lNoO4QKZkMU06weBDet37XGXQNVBLnElzqfOiSZ+kp1EQ0QO/m7wfTEL crTeylGnX2uBK+SqdVWGTHZsIH4b6klq2bgi6jIqffhTJJsMgOmuvdhis7g28kTMtRefW1jONmT8 OZ5RIT0j9d7yZRaGqBXtYXQnlJzw/98g36ANDKBKQBgqbHCLCWbc2P6UMCwMS/UqHaEm0GOThUJ1 h5s5inP5+Uu1vX4ydPTwGh14HdR1QG7kUMt6K7mv/KYcOKUhwpn3eFmuoXK5HAs/rkQV/RsY0LyE y7fKt5kRPrvAAt2RMOzI+KvxNJW/Gk3afWhblh+6AUtS/8PevM/ykSX9wkma+St7K4UG4lviDZJK 8uX9BJlOJ7wGw/jnJh/avxbhhwUDNknzQ3dk35mpRg0gr6356jP5h3OAhmi3lw9Cf4G8g+k9lGjo Podt0YKULMilWqs8Tv8c/43uLkLK832FVK4g8DKAxH76zsTZRYQwlU9o3pVq7hD8LYePOLJraDwk FMXHtGzmQCcRHg/5e6YK2ddPByVv4izwYsVc/KAP1U9OnXMMCodsbiX2RVdXMjYeYraccbLamfGL 1ZqncK2a+gxE140mL7z5gKcmOuh/mIX4gJOxHuHp849lf6XgR+3N4LzTpUk/PdNvZiqZEj1T5uSL Wm5opYd2atxcCMxwaNzO2MXJOkEaBr4Ihc33NNMdJIakit1qG7/RvJIyFXhjUhcNtrVws1DJ+BlB A4wTqogcYAzYqMqPLxHUjoEOvZOyKOs5Lb39ziHfwOkgOPSdsR9he6amUtW/Ka+soig2029b3WjI KDXVPcHlpBvuqMhC1bz6qTf+mSduHW+5vTzSZdS+Kl5lfZLnox1a54P4rKZhasqL+ikr8yYg/ZZE 8hnpDeWTA0yt7u0ljow7apBT7eVm6G+ExFWd0LJJ2eiSX4J4jfD3Jo/VuCplcPt0sYWNhT2RE6N8 /70yZfab4u/fCOsb7CG+ZgJd0siAVCkjhPcKopdTF0DJCuqjnClCsTG1rv/nQhNnkRelhULKL6SK ORhvKBsxovQ9fIldrjXssD7SJxY+FZ7aUbzlZ5/GP1Bk0cCveWO/lLB8xqdQUaUUgCCZ+4j5IkIQ oaznFRnA2/+TciOx5qTmTFxxVnSAaJ39BSTq8CVkN7G8yX38PNgMsi69v4ekvY/3xeNqrmWXqyxw nEGTOO14I0zUgUAEqzlky3dbzQvbHYgHH9QbiK3YOylBnWA++YRK4CyoFL2esWqA5AEqGX4qNISb HBJ+MaRb9/z4JlfkKcK6dbhMv1eEZgjh0xlnRArUKV+a/nJr5w0u/1/lPy2dQiHW/hruqV+uhyVt rYQ/PSlH5jL2Cq5zQXI0Gp+1xfflYel4INItlafmjGR/lXKydQ246HligpvF8lrnwL8P1mT8mCNf tHWMK5WW/WwBQRgNXqM0TFvDo07CriW8XDcz5y44SdGrV5Wvyku1lYNjB/3ZL+fYELvaGeV3QsoY pMMflLG8oz+EbTwTXU8jgxcjBJU3qQAmEEk8wulLSoQdQy/Og16Gcj75BuUgbLlqWLWAz2+yT3+V mvqysFo05MBBPpFl3IxX4czZeElDzad3FadHeoeuB/7Tob0g6i8D106YEuzLJeV11hC4C9E1r/wr BJplxC6X3S8xk6+DIsNGihyNrHOhlCfcAV0ekmRzAO8vJQqj4TgKIp8vumwAt0YLwJY3Y0LlqVq8 kkXdc+jT3LyrlpzGX7A8oweiaFwFN21UlrQxYpU7Ep0whv//dPpjNNgSkX5m7G7mA8DrfuSXWmyo r0HYGwq5+UdSe4VPKUOacnahEgfVYFbaAIq0u3KEIDTE3wt7Ymb2IRkMdtHucOTbBtH8oi6OKXu1 js8oaU5ulgOxcTLZHvor2c9l89WjSaTxmGDjxFHBLvIP+oC4UHPUQR6qvJV1R/JM5A0eEV5CsM2B rQHKOM+7KnDgVup/ErLYlVZJzs2FkRiPmjoEahZE3wkyRrdx6FLikqeETjx8CsblFOtyJnWviQoB tt2gJ9e0caeshgqJDh79R1MuUaBI42Cv3iXfzaDOqaNe67LRkJSTzGMjLx0njqr2KjT/r26U4Wdx u48kuH05nI8MnStte3Avd/Xom0rOFIppPaY+WjSu/PI1LmRDFLX8HxR2LlGLWAp1T3f971vq7wqu 3770MXacxRXO0KCE8+CzZsjBocxC+Rr6Ot4q6qPbX9cHuNNRienIMfs2saPAyyTYdLFSpHjxfqol /6oDAvihwHf75eQsAU+9zbZsxjwVQlL1mDoaj8X+75D/3p2vfpg2D/hWciqlDcdpBQcQMB8mNrFC lNV5PxMJPMoFQ0aX+dwtz1qyQMY/6xSPdjGkns/wp/mz4TB86QHxQsKXWcaK1DcvpVAdsuwG0KFD gDvvJmKDcKC5xEy+jtPeUny1f2AHXwrP9u529XtFRxIYzVNw0y5at1IE9TofYeFILlE7V+Hhc1kG XT2PozQzE/4REqxsK41YdqW1tCcspj5l2t+SQrNtz8kpwTU0JIgIR1PXQ3eslqjlOSHflEJRi0cP I60OeGFbJhX1JtptH8BfuEZwuRg/KUIy7aNKIDXGd0UveyqHsI8TCYfUYM+kAdsN3iZveT9ZsJBW JRN3bTnReHd9ZfowpwNcOtdgVD7ZfNmlY7UguKNAs9y6YLWLUc0xmWx8ShtmmCfnyURy3UFL55pi RALVvNKJsSgP6jCKIMnHTrn4MINHzMt3wuZZbJXiOiQhPmvhd+7FRB89fzgH6SKxzsxUoWguGML0 8oQT87e2VJRBXaa9190EKThor/6DNnUbBu0V63N24JFAsJBQ7/8G2PHCOxmgFhWRbKpiEmr/gy+j tZ4jjQYtJv5g0n+zCOOLth1aDIIBmXNuDnYiGm+JzvDWLegvYHZQ+/yFq82k/Dh4kI+wVmesVJqA e4IhpkVOtpfbl5FZYNlDre5gMjrRT60VO82w0vGLaCa5Ou3ZSsQRt5l3pjvAvEDFjMpzOSoVyfvp 5T/kYnKYhEo2ujk+wOPuHSWj8L9fGx5+kcpFB1Npog1mhp3wEPb5zRxZnBmjCNWdc/vbX7v0AYGy ZCoGzn9UdDgUX2iHXRIaAlGuj4Y0TJDXYUvxy4ENJfVN9tVpH7X1V9PLF6eroXKp4yz69pgIs8iP jt+ts+//vN3ryf/co9INIKKZQ6Ik955p5eCtsNS08Q9gZM9qddSMaHfnXEEpMHxHQ60HRRJ5cpXQ mFCHZuLgySCYFSVLAXvDtfH8aCXfkkh/rW2KPf1jeRHutvO8klzXZZ/Va9KHCoiy8q8URfzkVqvH KtyMXB3WVd9cqQlztLRJlq7oya9lJU4sM+gccArQCENzPGMr2gkk5wcHWa3oEpXE5aaqC7bYRarb kKYhQVXCcepIK+skJi7kHeaLerOYDrbz+tBbqBdTqNYDA1rsPbQDb5lDkUWG3+rYC/zwl5nL/7g8 EOl5TOImbmWgQZauLCWf53GD/LqSxm4XVDpntPmlbuDk08JXxNqrVQ8BXbGEeY0LrcRM6od6LeF0 ZgmhLfJ5WUQ7gaaY7wmFbSdYZsLd/OUtt5JMvkNKC2I64vxFkwvTZ9w25tfdtD8vEPqo1Bzdwm+2 iXOjLwaMsWXprLT2Ez3DxWdb778M6df5Ewm4UNfnQXK16riISuoaEEsm5a1wd4gLHEGilnBXjgfv vNvBovnzlRjsdwN32BXPS/3LO0bl8fOekRf2KuuT2zY5FvLzM2l/l3uWNTiDCf6PdW22nDzX+/BN iHtlvArVRWajTzN+nu/dHjshvIvz3tdEStA0df4ZOJiLG3zQLC4GePKpp6tq6Z2YoTP6dbuiOKmL QaAGS40JF4uj3FmgPq19Mh024AZmPaRHaKLWbmQEM/9FO686DJp9qVfopfsjZy9CxJxtKLJG9gWT 6Ph/80ifV4iT/SQnx+Cu8SO8kREbljjIGlYZVqvduIHEpuav5bMIOqtPk14vHrSHCuVxf5Q1qNeR oMyDi1odXW2u/LQsYrT0PiYtaP+OpEHiPmuCxBqFXffrW3pqV9gIecNnWhqNGYRl7MOCtGYVqrvn F2Ydv78lM++y0CWFyMjwBBDh97+YhSUHNCH3rWWyaiaTFEYJWFpoR096+N5/lOkqV4Bd9iCJ8KdD 6cY2YEaNK4wTSDDyhF28/dbp93tt3r7RS7hdW/iWoq9rNb9GOVoGvfPXOyNASDHgq307ETvLHDn/ xnAWaNJ3bW+fd+nCH1s/V/+6DgkRuzaFLm7W52uT0CfvqSQ0FBYqldp8GnqKVTHi0OZfH8Zqli5c pwl/nY50e7GT1HQTNj+JuRK7VH8hL4Qls0Ozz/HaDUywwJJBwe6hfsYjFErq6IDCfwAKnRmoDr49 naPpJGHLdCMmb2rrm7xGiNZnMQm2PF8XPFiTyawqN2rJQvc4MPrWGu6+9BLtsA+mORVYXMykhQJe yrjT8oizpoMmUm9+SzR0AlVnJRch4CmAIuWH6LjyIjjA8/9ikUpPpiZZTnfYo7EBRd+coujy4yEP T9bt0PjZBh8WLVaxPCM+9Lm+QIfGln70c5+/dhRa/qD608fcfqxDh1Q2alomgZdI3oXEIHCy671w xDJFeP82FO0SlG67QgVsIbkpFnwpE/LWeFwvDB8IlY4+K/JtxtbL0mZaKVwfLTnqssjd99mQXxiM 9aACgBoMKZE4cETAAhISFkmyk4SXRSnPlCAVR/P2zcJm1F7b0sExdxwRwzVi3btTw1f5YcXBHdP5 I/Vm+Lp6URHeZYNXrJabzFyU8jg7lvmXRxoeKgJmAVs7OSZ+MoAQksVvPWrKEmsqxgDOyvUFM9tZ XSzh8rxGyla4kXcAlw38jbpehr7OA5x+ac7sNLlwYteywGp33yTJUKRIAyW/20RQy4Qf7bRORBLD 8OEKZ4/nwbx8/ljCneMLN16m8wX4AYYli5Ax/iRYeYrwR7tGUCookxqSdXu0bn/gU/jx1k+kd7k6 1jRMAh92N/nLDy/KQszxCqGSsVULJzsz2emMEPd0y4XbzPMg23fn4QW/GTX+MW1pQ7dDctLaXOtm dD4bIJuw4xT+lttfMw4Z/tSGaG/c6LkFQEHSu2bXSWZvFFquFkel8raIVzMUv7xuSV1AsBAYKnK5 Vd5ryCFzzeT49B2i/iYxPCrU4MtpFpHQux0f/yNYR7JzTG4ibf5j9dKIr0XXFtXWtpfdIxZf5xLL MZvl/8bRDUz38qJ34H0EKiXCE8Pl7UYLc3dAVDblFhztev8Qk6cOgMFz/1H+LCh8le4ipCfr8vwX j2jP4Tw6C1ZQDUnEipzq260Q6uOkPs0mfzV8KgWIXlMyZA6mI8FGb8jgAMUbwpxXT+fDn4R6wNYD /IPwh/eMmF+dEFi/79YPEV6AaFYz6xNfdaY+FIcuF/1PorUW0aLnyJ69K5tbw+V2FuUYOmmXuoYH xw9DAg6Tvs8dCxz6vnsg+s70EGmkH5DTJnEcQDXRUxwfaaVfGS0K5buEK3DYeRflqDE1vN/8qvRI LZi8FOyApHtYSecWmWFlKAbOF+GFvnD2nREVRmH+YTU2TwAvnVSBykkKQpR3O8b4r2sphYmD5Mvr g4/MB52LFjNFd0C7PmaCxZ6u7utu3OEypeaYs0Y15VgbJDCC21rit45ZLnScAuWvZ2O9GnTTcGjQ 6krzeG94XY39u0C3hOr4IajELk7Gw7TkpBCzsQbxrgr/AL/gvZbCPbb9bMyU5EUp8ahWSK+f4Ri9 hPWvVHpK7M1qQwvfDWwqiSjaWRB/eZIkxGR+2HMfV0oEodAw8h6guZeNSITFdNR8ko82jjqzpNyG oi36RJYPZd/FVWTKGkIqols+rd4HXAv+mInK3QBhofgyeEPWHjyst2LH/iCtWDGX7NKSqT/0RfgM IFpiX+USSWzH1S9lXckwxrPD5mcCS+q3+ndE1iV1FSRoEttY7Co7o2e/o6GMpyyOqayHsQnLm0lx V+q8yRdlsS0X6jwIb/65Kra5N2pBkQy/fXT2BmhriG2xu7EBaDlkYWLoOybTgNPssPm5RhCIKa0V V+Q1vebA4k5Wp5bxWZ9JS9dsK30sfZJ7qpRo8yuZqpS8O+RoQU3w3OBZoNL3f5IFqEbSg3XUwoVV 3iUGVlih7K/9rj1HrX68bC0PjSAdC0UWAvNv7ygOb/KFZQXJAebH51+eIaousYi9rLXtNfK5bp/N E9GDmKg1KbhTqhpu5Fde+6PwiWw/MWKqFTXYrqrG64817tcaPnxM8TSHKOQdCusijfvob6MDkFXP CKyzkdE5JTWwJOO+6FuvZpylciV/QqudtrVKJLjEvgJ2bl6JPOc0Ku7f+AX5TXLb/5Arp8y/naIi 4gG1dmRvC67FZrvm+SO/j6eXCsfYSpgct600lRzmx2bouy3ldNuQ2T4oDg0wXtBIHoi8HHjM8biL dETHXjOHWWhuOTIeX6Y4qyt+ld4RXGg0Aq3/LJO9dc8VF4kE51yw4KFLesvyTW2SMTZRylPPbtSI o87Z3ctqbOzzFPMwyh92u9bMS/eCTBuwy1YX6hrph+5NMkucDKUqCdQoaWnqXzxWI5br/B1okiFg Yn+D3747bywh08u31m/OB3MYJle5ApGSY3Ot+AQ/C4zKSRTKU6TtAsHKxmyx3zZUCjPU+g1LJxCO WI2NUr9U2JcL5NMzpo49NspN72G2QIRupfhZ7kgNIqTO5SGBOMh56jOtn/9Zr9khBLjqjm0/5Ea/ smvU7sWjq7s1G6IhjUjwSIE3kxiyMjOb9XySIjRgeFenka4MyNrSBlJmcGNMmgi2cjpO7gEkyEWn XZGMydekvqSIlmZdCvkbYKKGJqtGrCgfYzH/fTAlSpGVxe+YfSUTqlYCSuxKbQfHZlnhzMAvH8xa rHsOJjvLPF/oXWc8zbvncIduZZJwVP754yxk1YDvZKGeEVdTd25vtlcYk6oAgRqCjfdmBz4ijYP/ Ta3UVV3d5atlnYu8Cm6dC4gWaIUdcQf1ZfwQOi43k4U96ud0hqY/nxcScYri9pcZ9ZXn2M8KZHBT UTpsfcKnwbDtD0Vt2zVrVPXiys+BbK38rsbKs5KbP/muKVRJFCJwXXKZKNsmpUFc93vlJ0TEYnF+ MTps4sykCU0eH+E5guEf495rqFhq9SarSJQCwINIbspe9l/hSFS9paF7gKocDNMHVLaT3xitHGXH x9CetFISvBj/+AULcJiPUL8EVo187Ia5s42+9V2rGdPjwAoDR4zHVT67dwe3Nh4RDM3v2NzJobIu /2xK076G86tuIFHX5Qd0sChcC7xki28/N6GGVnm5aQFYEk9K07GQb2fpu8hH7tvBNhkK/BkffVBG q/tbc1FiGfSnjMHH1cOOgtgknxOgbvS2nQ9rP9SPmDIFFagjSamM58kGpm3OcRnUyUCo+b8WOFqs NVGHIOQ5lkQejTHJLgm6/wACcIn/sLFxyDQK/IJTqb+/x6k8m9sWEwHhfo+SKFS+QQ0drUiV30Ta +p02SC/z8z8plsw1y7cIgSnwkalSRwfDOkNuuL6+pxG6SNahbAjxSyja6BdvO5eusZDd6w94/Wgg jkv8/yVvkvZEplUvjoSVvPRyIh6YfDEExkjyAiKgplJJASRI+jFzWOZ027Vyrz555R3dRiRHtfNI kCgPo1p+wNQFcRdbzLEAV1KAyriEPtafOkA9NmUs1dQZeHzt1o8+9vTQtJSyWfDm4OR701KMxWIB JeyG+pyUg4N/uc8Y7JvdhtBoKtm3VCYUAJh++YxyfeGhGvSCZNa4Kk+GyEUqUkzAwQbT2bk1KWGT aOP6nvuk7AqFhaAYEyngQgyn3hD8nre+K7xOpCDCK1JJ1ULr/Tn6WmKkDVabsILT7XGn77KVVP6A zEU2YA147vSKyqwrVuS7sj4iduPfCXVmiVaOhOKBLBXwZe3O0cY6O8Nq3A4BUEHSNp8hLlJZptjs NlcWFWDqB39R4vF42N0zYPqWlHyxdMkOXBq/X4kxo0y4ng1m+tlrony+1Oeb3ZT7X2Wp5Tsz12Ad cDaS9yZrAwPM5am+EzqHMX7q7P/BPsyZ52gG8TFZ+smI6hXApgzJqh5tHz7HqxjyRAHev6k5Ettw Bn3NFl68iIgUuD1J6u/T5RGu8lEjj9XhG9RlyAJHf6tyR4NfTTcmxnOVWH+btu/ZzKzsNqiyRMgh 9i/py5nptpNz9oBUmI/5czlixF8UhPJMLng6uF9RWIEAkcdh2AYJ6HOtb7I+zY0iZP06+3SFmH4N +nU7xpeO2iqPHtji96HBRRMmPq92KRV7m1ukkyMbX5Y4a40GHWs2KttLDCRVgVJkVkp7EwGBVJOs Z7ofLs5d+732wJ85Tlo4wKKRmv0zKqsgcPm/I8O2H1fVFxh3+ztu6aWfk0OeTh2Svarr+PT5JlWT j38/ZgvNcvzx7K+CQ8Ylnr6JiPCT2sNOjTrJ6Zci49TjRCfPN3JsNirMweE5+gy0qmfr1C/y2dgR GYy5KslucQvrjsidtcz9PfV1jvNy5ju+xyk681XCLAfLJtlBFewwYnJjqP0L1HtpaYXv4+dUiLbR pt9/sMaaCpVNMkgTJYham2vvSacd4rBS8uUHIZOUGIIBVvSdcJMtfPrZvWrsBt4g8ao+FDfOjEO4 Pm65Z/ZyABP9a8C/tu1Iytr5zL07IHvzgtdPUJOdXG4vd3Y/AYONPN3s/Pe5NHFvNlQTyzAFMbfk lE9SxiZm3hYXJFhowWB1uEEliBMNzvBRCFz+fVdo6sXalDIqIiZTcD7aOEa4h9BRAo0jLJPNge0s DG9Xg8chyzYa2l/i1TvGL8g/tXgYIsD08YWN8o4O0p/G/NbHdH+EuJ4xxCPRVpPyCDBJ1dXU766D je3MagkEhlcgojqwZ2TI2tPZ2HgGERI3s4fwCxFQ50BRsDM0yN1KNgbMXpT3x286M241gf+GCkZC /A4/IZN1MdtHMiDdkDUUmzhYoXJZkJa1Z06C0i/kV7CJGLBYZbm/Kvo92D7nn/yLJJ/cgU8j+wwH VsK5hqeQRGAnowxF1ARJ0YlDROIOy4I7tH8mP9ZXeYDEk1Yj/sKfjuIKevN4ahaTKDjiotfCquH2 14TXNqOBWoso/Nyu481SoOGYj3Q15Koz2LfTS+lroW2NLXGYZ232kQewnqzAK5rWc34BPbhNiIes YisU5PoSsLg1za0DirvZO3/sZZrBr1eUFW83HWl2xrbYIW2o+dZe6a5NGxDPLYvLrWEJT9FobeQV zy8ZdZutmcRbnlLPI+P3sRDE3tSuUvhNlxHGSL73grqmyOO98RriddGDcCPtlSSNFnuUbUlNaeD+ nmpGLLnAYPwKqGllKYNgkQ075RXp5D8fXskz+XCwxtsTEg3n0Rp8kl5IvzZxaSSzREspwBLIxOvi Sa7GGYerFQgSXH5xIPRpgZ7C6TTJBSD1MnvDnGIVLKJsBVAL1NY8tsiz2mH2nzhXVCwV4fcXQYNr DhqW/PIXU/aeMuB3Pwu00R/JLsH/Def07Nih+VLX7SZ+a6ZiVUoq4aqRi8kgiROLodQXzoidlXdO XgcG11vfYZySSMVhUAbEKIVi2gSkjBE2GaDArLgk3FBVaQWMCZ8yxNt1HB9w+qd7Z65rhdd46sgO /U68csv7g8JmhhX0Gad92+jta0Kh5sA6zmWTtNI0lotFvXHGlhnndaQfoFSLVagK0fwy/3CBdeNP aLRqyVSn/LqLqZgozgsdwBEe9ikQ7gB1RzI3HYnZCzIE6z9SKKn1/WT3wNVXuOkNIrHKsryatpsI 8VMTNXeQ2ryyRxDsNbL+Ws2VCLA/rAf9i0hp2IeneNyCa4YguK1pkrFT1unQgzf0BS5BauEeuUxu OTg1RQ3qqh3Q3Ea4b+8EUJcUR8uorkQ6lvohKkqpc/njGR0TTyHO3DBwcY6wmAQU7CrKSqPZ8n4N 1PvSiEfZKd1v06mtHH5xAmz5kIZ02Lx7Q6j7WK4tM/CZxOIlL0nVW4KvI3qdKCno8cUtXxQS2pFk +RPoG9dpv0VrwFbdb4G7mR+BJboHiPx6yemhD8YDBB8mnMBJKMg6M2CpVj0ktGd3gP7Wuo7TqYWA vFvWRF4B8t0PBa9maXjsvedSpHuCLc3Gd/R+0PVNhyrAEBo9ZR1bFs4hY+S+06MSVCiUsAKY/GHk jlF7tHC9DiDd3Tb6+RlvkXovBFV9lInkGOfpILliuJne+mXvELgVqtIqRXpyQASq/dIVtBx2vh0C zch967dLc7/ezhCypuMMYJVwzBFatNpns4z2ybpy38+3vY9bJHJ7NxN6YFa3mmDv/8T1dV0KE9s9 dxn25ffUgmkNiJe3XJX2brR+chp8mAXRDp+YPib7BT8hx0Lq6/lf0at5n0mtURxgjApboNOSjl6a 15eaQ0Qj8ZTPnQBl2IBlC10TlXIZjWDAXEmCBu9j8vgnonWAbEJpnyD/sWGCEgaeVLM+09nUdypc 6WrkJ8DkBqKklUb0gQxDF56wsttBg6iyVY2UTmqH5BOk1MuIt0dMuLitOw+wiZ7wXxzPOCdPcr92 kSI3ckQPry+Jz4x65n6TnZ8qI+vKjueLbtOHlTM89I+katHODXxaVibPK45YBT3KWDo0G5x6FZBh QsdvYJDKvQDOOEbNkTriNFwtc8uVxan7Fjpc9UWcssS8H3JpVkoxsr7v08lfJgasj7gNt8CSUeff +vuplV2lvmhozHBaWy0GDfaMxOztSSs8rrJGMMG/RkQzoO0pakG1irXaPcKcTwomnHU8QzhWQ4VU 1sgh04qGj6vRwJA6NE2yKUhCt8iKvr/UthTFIXM4v1dxS/i/KrQQRs6h5/Kn4IIH2CIVYN/DI1oW 8djAO5P0AwkQFoQxUXqWaujbq2tA7W0aASdhWnVL9X1DJC1VfnlUBwPQBxLDg8HZ0EPMTz/q7B+f QVdM56p3LEEonjFsQNDbZ9i3qstrhmvPMJYasWaGbBGRaCVGMPC68PKfzTR4EoSFP9Gj5+GAWNxh XY2CMCcz9ZYHU/++jOQLW34xLse39hhLtVR/3S3cJbh8tO3GaDacntAH+C7g9lNTYjXkasSbIBTP YjTjHufVOh/g6j+Wp1jqpX0hQOzQmHNCl9KeWd+UHlD/uRyClcraD74aWODvOmRV4fJsTkTftubq gVvOGBtClPzxEp4r63Q25CAr4NylaOjbmnOJYbZWR7BLlRMlPvThK1NHCqYAHusauBKNvvwzxUPN jnh5o6fofLVfEVcVcci6ODiG19a4eUO/bTZ7YwCh8iUROL2JzOj+8vvUNYTYHEJSAnMrO+33cs9G LTQLGXNPA3yESXGpOqX+x6gHRAPedmw48TqDxiwJtfZDtNolh2b3ly/73PI0JH5TsyyIlyzXC9LI jPvT2bD3v7E+OR/1VZFor4sVeuYpRY+Prma1Ja9mHXEjdK5B/rHqJnexaVQBX43ciWgBLf92cN1k O9WTpl8kKQOQ0elioBT/y7He+uhGcipAjglB5kgFowYQktotOt411dojgGFWGPaWuYi/9MVeCmkg v1r8Ooyjp3rkvjLZeTfl+FSKSUwshJ8Apj9hoZ0CCQzt6Un+PyZKZhbszuEYXKgA4JBdjVDerS8q Me5ACpPfpkskStkSNYD5fAAruaLKUbfm3cpkCwbMMkTlbU1CHeLV16cMnybLTyAXmVHQQrUXDkfX CYOkTssQVLjkF/m5Ldeu1DubqcMhDCIeDppDYBjsaEdRF21Y9nMtSSOXvhnXnMxrjFeSjTfJt0UW k1/F2WrZVzG4lxFwDhKQATcp5HJI+AraJ/q2UhVFvNUNIe786lhyfIVNP7k2f+hBAEs3J5cC0FS0 k46uiNak0hlN94ukCQJHb9nbSfbriQaalfdvAR+egigI1xY1N0ayOqmMWFYfDyGUQ/h+owx7lgpK 9RjmERE9sBfVLywcoJnu+b2AMUHhtdmgSZs1QbCSiMPuiFTuqLQew8N7vdfg77PYkfynPrq+B/to VkhKuTWgI/SE9T1UzO9afSLDfw62h1Eu9r8T0ObXc+coGGqYLpnB67YvYfHiRMsnYAyQ6pDUrgQs 4+xLmp7kNFe5TE6a7VskNEtet5G0xWXi8swE8uqTNYaKYbTx43F+HxPbyvJWYOgIdbX8nsDe2P5t Ytf83Vyne3hdgVJhOybWQHytgvXuqXJWH2oIx6DHapWvX8qrGmJTu0RvfV0QAJ7B3oRrem9cBUEf MmzyOfFY7B/JrqKIi/PEyRrAFQ0vwqvp2Uhv5SLT1q1TTJ3H/FDe0k16gDm/6giXc0dM2aAUhoQ3 oZIus/7oN/s2A/f+myLB3ecg8gXj9GbRakMz+YG6qnAXi7Tt6kr/6IH//lBAX+6v04Sfsyg9uMLy XkF+R+aVmk7MtVrvSzm0KToklE/Z8MDBVhjvAw7NfY8ClHwBbPsYuhTyMxqxPGNN3jnmfLGA2eDC HFpYBQxa6jQGoo4xKan6z7aUkzyq8QJ+QRX7wCSJuYFDLfFTb9SG6dyJMHSwXs1OuJrfrEODUavR /Wk89ENWp5+qIt//dNS+0NPmlcrhVbxBSu//5tT5WiXaNj9jlE4UZdyfuCtZ/NUAZMQAwqjetNos jDx50UqOQRJZS54H8xXh4xGgyLGO0tV2jx2dM4A/LeEoWkAVjv70YF7V4Txqz1leuoyxaabTK/vx /Wc6+sZKWIsZPWklxWUqNwdpLWWBsDIQjhsRglptAUssAEiJXSgGL8dpaDwDRZ4ALJZ2v/U4AVoM XhKTQW3GxOfA7wbfSpJ3zc+rWWDksPcVI1arFZvsixX1y9Ab0axHrMmTN8A5/QKR0sY5fBi8Qzlx WjqP9AJn6bV5CseSo03rvoVSRqlMrRCXWOEShGL6ETWdzxIzrn77f3uUiuNO3XQkd4dHgzdvPLu6 4xUJ07WMzql9ijLL+v+Ge6EhLGWacVxBiTPAqQ/UyJ9elo1DkaV2z3FJ+29KwPEC7V5TNh9hsuCS 4LUn89NQoQtV8N0Npn4X1v5rkh9WToDIeuNOp/5fiq2Jhn3aAdLlHNEXP/hjoBh5J0fYMEphIsyT guP8yDVLlNlsoc78hxF7izsojhP/l8jred3kuLgzo8sCECUVgIF/HUfsIEqixtMHCISy/9Jhtg97 gz0dJh3ZEANDLEHYCgkTOaW4XuVkngd5GLqxykJAQVvzwHYofVWABfuSFDRaoh3vQ7hcXc+qxHGj LICn2JR9kaxd1m0ouBP2OOh89SsS5Ocv7ralizKy6ynofRPFDKgGogLRNi8jkSeRnw3GQW422CT2 EejFZVhvdicE6XFkiUTfn+srLrglDYmIGKeKDKDhrQmlYAFSq7r24f0RSO+1+cbcAayuAS8GDe6p ZEnmNaAf4lKkUwKneJ7lem0FyG28yiH3OyFKdbVMyV//EY70Z04tGgKJXxLtZqC8WGsxkF4bh33+ qZyBeoCGvhQ9lObUp+iBuOd4Xi0+g9xFtpUAGsEtP75Zs/qAGSH7aAoYePrgTiTM6x1/Lz/1Ui5C ExEH835WH/k/3jdIqtgXtKnmNWjwHyb78kRk2ZvO7u1WcR1+CtrOrPyy6Vk6VmwtF6tH3jws5by/ REoIuJlaOg/BjexQr3png/FgxEPvf/dUj9KGtaXtUtZvyogV0Vf9BGYo6d+mreIgh/7yJXRnlMlc C49L0TBRSfSQXEb3uDERgega8Bdn4oXMf7Cn6Bs6b01ud2wlPVYw7zuPzo3yWa+2NcXz9OMLMEcQ B+IkAnpyuqdWFDlgtZlRCpD6RHaek/QWCxYCaQIcdfeSbqnE5aN7G9LqfN8MuaPzWvoGwNbUGNeo gFbATdmtyJdQBNofjgoAQlRt1JuIQVFBGRFzDozV/DB1s/KcyXQ3A2YpENrKoIZB8cxyVGu7fNEo rHr5CTXZHQ1pADSuWfnZbdGo0J4x3gdwVP2Za9bn53WrO92azka3Hwo8hSWujA1X730IpGo6KqNZ n3G9PEL3/9DhT9Y6W1F2tO7K4Nk0cE1rWbCc3VwTvwp+FZRCDlGZBa7gX/MQ6mHh/qhi6YuqXFRj bOl6y5qs1499N5wK3SGLu7cLCq3QhZE3a5rW3PTtnwENqcAdPZm3WBdpozVOP6EdrZNwaqU8OXsh DOBsWffrmg2yIF/KupeXzxoW4pYGZMqwuqwL0GbJoEtP4mEuh1mEKZKrk7qqXrpJHsn0B8wylEQX itSUE/jXMyaNW4o0ZR2uPhAJPdvRFF05VLcvnsPMcRRBTRBxg1zbryXSuKOV/hvfI4KdxRIium/B DRCltWveHw5lvmOVI5pyW4AM+vXt2IabzOQre3iugiB4ZzAlDClYGFjW5txCwSaj46aAXXNnxGB9 WLFNxfFxHrCXRZY8P/D+Fd7wak8opF97ncgvnMmFY12SWbxWiNJvC8J5tSiMVtM2gdw+fdLJRDSE tc0TQBmkF7txIgl2UUXnp3HHZ3h678hv0FeOJ0rzIfFY59zs2I+Q7z1p/1Qe/IBRDWKcGRNihe4Q ltdhN4LbwjJy6FZ2mcnd6e1+eOhZEeWj/Th256V6NV0+nhGWdjgKuqRI6wzarIWvIOirHMQsEyRB 3DmvRmFNciNMI7y0y2VW0WUnEpDRW2kViRTpEwbYNSEm3N2SK94aLFIeHYkdrvo6zQNXZHUCQZmZ MxPD7A1Ii02ayzYgEHvF/smNJYbu3rXdcg4suKJ0zbIQCWTZj8VoxdaqXRQKkUxcKH9RGMo7Aq+v CJJT2P100kKBVmitQInk/l4xP87hY99n+/u7FxHo7pAM+9Kjhs1q/YraoIaQKTL3Hhrx+u/GMc6j c6fi+16A6oNIY2plr4H2E0euBfM5D33YAjopogzcqtCJXH0zZsyT0UwZf9sY5ZyMTL00imLmw0+T D094gRoQuc3xWS57x8pjrvf6U8Q9VtKxy8X1Trx1FOjti7sgbWi72S9iyyUjJrLCjO9F5VD+I4BV iw7SrbNb5OZh6SR7Rz5ff4Yg9tneA65BmWTbiFI4zo4lhhA/OOKrcELKUVGu1iMajrFfl8yzkvkL jnGBJEB28msAvbYlQtlx951L8DYk/14ay4J16oMdj2OvaQcx9isaU+NSw7O20yuw29V7YYKmV+i/ 1LEl2Yx1Oq2n7kqnkRI8hPrFaOOvXhMSaOp3HIqbnORwPKHiFd/4EjnLKq4E91LoewE1cplQeXI7 YyRLYKeEqesru9tymyt10hI+UJVnNIdQMxDcpWBSMxwcSX06KALpJuOY1SZTY/tOz0kVm/LfL2xN jFvovzY43ntJslzII7UskFJp38fmRx3N//lDD5TPRwpRKHJqGUHeQY5Vj+JR11FhOWVjJQl3LWIK Hr7fSV8qGMHcCEiZ7CpnTOWqgL9CrpVjRH8/EHEEYQTo+OD9IbuXPf4gWhwtiEBnlur+q+XdqAyN y8W5G7riG5mCQAGxBXsZztV+q1iY4HOmYQRoP/T4ZqfwnrlNeHkNfa2IeKMaRDREdU4L5PUOaLkJ vA0cMEuegFSjrhH4YqmXbSU2hSigb0RjLYTBOX2W6Xz42U6FTOTHxTsLyCJ8MVoZbIBSh8cuDDaV ibpq1ppI3dyMxlOcNlNItiRGBe3hkptMo+m3LtDrrwxgmlcwZY5G7ofAIvLR5ewWk8lqSh/j6XRC J5UQsR6l7M5pDGxfRoR38Arx4IOsriVl67JbJ2gfpeBXozj/SSXFU60Oj4w85L14GDow4Opo4lLo MEcSzXLxWRGmotSmPDZJpQDD8qDwxsUj8fX+amGXHgbBeb558t4uqJdSHJrOWlLGoBCYX+1Lw0Kk xzgOz/BTK47st4vH18iYTnTEMnUWcYqAOi4q2b5L+mOm7v3QfM+qAkcnvtTGm3GawPrq1OrOwih5 r8eLLzUZceL1OUTl9TnvNCdYn6r4+dQBZ0MflFeXAt3ArEeiOxVNPhvkadjYkpO7Es1NQebATOBJ 67XheRHVKk7r5im90iOpz6p46SIFXV5jK2y2xw/8aLk+0vnwZpRS2ieCBWuiPks79JZml0bf/pIq J6XI52JouZ16RqpVXZ6gc9HGoxIlk5Ur5dMV6JHRg5tqBw/SeW/H8ANnMaU5ev7iCHnO+tKuEI0U EX7NVM73GVQRBT5HhFXcIynM6LV3D8hS2S4IpfuiPhTxFjPg/4jZ1k+OH0OkVZzqPsO7fUNHF+Fr uTAX5e2leuadZ8nRzai10Fke2L+wIQX+xSFCJfvpuhlMhWK14seGmgT/vaRse/uKAOo7DgT/ymVU VgDmM0ICbSQh6wtJfPPJ1bwp0+a7C3IthwJZ9Oe0IPBR+G3ye2loMvVX85wjeW8vsBjQxWrE7Cl1 5ee3vQsff09Nk6CacezNQ2AlFMqhgK7PdRxIPXG5HaiPt9we89vIwNzov1VZ/qIGYCHzrAEn9hTC Zqozu0I3bfpBhebDg7gIwPSFaLoxDpBOUCgFKgQZIcehEPwPaP4Z8voKK4DIqwVttk7zDmnvV6F/ uSBFyg0Mlf5xilX2zM2Plp/dJrDxtNqzxugGwrmgKELyY1C8zdw4e/KqzWFMHPLJMCFlEFEVgU7x t3qju/zZiXB7vMOninxXVTT1ofmpQWLYY7MWSSx2kuwiaDZHuKJdcaawpZFc9O7vQOrAEA5ABxJ0 n/QfjFfDZ/Zia1AzGGTxOzZiiZABC7BGwb3e5K4Fq4nYCAuhIMHhd60QtJiwMzoxfVnwk65pkiOL u1hCZ5+4U6md8xHX5WRttUvJAzLpyn9QOCxxCYj+mkwtjrANkurueMRn/m0vSfds1qyuReOVVIrl 8zuU3ztVPfatF5gVJpqy3x+lA9tAbkQMAgeUeC0RnpH6Au7LhTKhjAT3wtERKJ6b8J26wNo4rhAG GN7o0aloT+5zVpRNvWZAcAdgfrLRHU74rNU44urru75G2nMACeQeNMmKfWKwoPPPdy7LVEl7xmxp EpKCbUZx2YEQ0j5FUT2r6otJ9gnBL6t+KTC0pMHkQx0W1yUzwc2m096wIJktG2CE78DrxDEwewor 3HlSD5ec4ln+YjMFLQYP7E+PrdnjhR/YtI4BqLVfjuQTFQvERiLgtHSG4bucHEzbGcngHy4GciPY /cM8rDvOEzp9t4t5NyMB4uxTU1BQvyLgrKSlbT9MIXCR4F0M/nXgStUrR+7aiz1nmaCbCvCFp3H1 3j1iA45+XFQf5pjc8JWVmpr9Qg27tC9LLuH1riOulg0kPzuPPK5BKHrEZgPPIxb+JdfVdSFhc4/m lI12w48XR0l+Jkm2DHISdKP/UcbNmdyQSNGmip4WX4h549YvTGyjHNFBn8d6lpMoQyPTPAF74j3N Mj6ienWtXxaVGXoedFkg0rg7qyE6h+4qe3l0YiUc3gz6mOvlYqAppFiskdw98yVNHdY3+YQe0yVD HawUSEtON8vJPB5ywkKGQ/OtPTgqM1qbnxSTErwNjAxQyK/xhre76a3GHRMbOBvLMIVMxpL0aEga qqUpm8eTWR3PCgOESGuLagJvFZRD4SH+5jv+Y7/BBN/zOzJbK+UDy/hah5xMXQG91PGiyFyNFoeF IYC41yXwOC0LbRfQatL6k4MZ0k6yKpZbBa8/Yb7dZzj8k7KPh9LT2IQgasYGz2KhWq4ursae2/lC LImZUZvNG051Moq8CrUZXD8kHnhpJjY33+WG/pi2FbnQnv2KZwuyE5oCr+BdYLj2uB+TCQtsEEu/ jaxE0UVXMA73+gYpnvMu3eE7/ohf5JA89Kc7DUX6heI1SuwCWWaCMjXhsyCtoSAnVMUX3/5pYWrq 0beGo99tPlJJJFSm3p9ze3eiexttJ2cc34cAx14MO8wh0XXJW+KdxViGM5iJprp9yXZITxlyR69Y DieZQEbKymlJ38egvFundSHZjipQ4XZZczq6PwH7KG36cyG9OaPRNIkaE4ZdQWuOvREHMD/inyyo AZ1Wn/0v4cYCQ88FuvI33lH3hqOsNJnn6bzo8eTDJccLHciVwZbS3mcWRyavLrPxgcOSA59LW8Bj /7okPe4qdkiVBSRXex9ufi0iXAnE8pbBhT9XuAWoD8Qc8x3jHqaPjwhY13BckT3GRE0SzCCm+Sff xdcjHxc3ZNUzrB6VcQG5vH0QR4On6r+OZmewd7q8o8YnbOh4HFcEkYF1y90j/VzbgFoEIi3GLeVi ZKEhABxh9EiVoTWVuuoo/+MuFCpFVXUQpkInWeoZieB3n231VXK42QA3ua3Duqk5Egvapzl973m9 pqcxKPiKN97febIzoDkvs/yTxXSb8Z08CWkcFZhgL+FW9BR6FFcbbjvk329fbhuo3gtmVdERlvD7 t4wDdvcbpm/YQk5H8EtHsv+M0j3dyu+VCaLCV18EK+afzKyC2VVg82ClbNl3b5UcuvVCAG8XypRt byjNg497mZ9pT97p/UPNCb4cxdfFr7cr0UthYLGx8kdXIsygOfwbEvNb2qekQOFjCp91qtVH1DiU 9V2QusV+lVCLoTE+XpGFFwTT+6i/PPYitKgJu9G/kEfwGbBGAu4EgYFprHp33Yi7UwSFd1Bdi1D0 1jNZQ3J/Zc+x02txZ02ppuKsErgHezRjrpfCN44oRoiM/7UxZdsyMSoXkoN8nH/KnHMk26qRsPqb U/7vL+e8+NHTwLr7W5EX5eQ05qXWns0Eaixod4YoTnrEYYvbxEr5S70KR2v/CzoSnw/Do55oPlwU JweieiBM0+myyxOBF0FfUuQfOviSam/HsxT+yqHnIXHe+X+46rH/bEwVylRQU3+DzwGNZ6NFRhMC YKPbSz0fQREd/0+fLeK1wy5Lzvr/EtRsbKoeKHVIQtDUMJ+Dt6GBjaErwZSjzUzek3oUjA6kpfbN gMkAIr0jDNzPmobbLncHuZaxdw8itQNcRJL2H65qDb2L8Q3GJYMLa3n3RXQYO0FVzp3iQ0IKnM95 w6ejsDh8EInVBFl6No1sc7Ml8MOoYG6j+bfrA5pwA5SMh+TbayACB8WS9xs26ysn1ZbznydOz5Cr wxVRwukLLanswooL/RzvCFbDdz5oG927iXOpmS13/6RYj1FiOCoER5klJpSANjIPXiY2msSz0rtn 2xN6leJeh3wjQjiKRuYCO6pStXUvXvrlEgXNWOEqKvswV0BM1VtBPU8UivdqtM2DB51FJOklUeD1 9onPTWdZf96T2uLGAnkh5UdGw+KG9v9Y/GNSouNXcXsDafWdo6y47aDET3ljhVaqkmCIWAQL89bz +Of+HPu2gClp60jRSuPouNxqFa6IQ9/HFmUV2NPnJXvglqoSYJydWm5LzStOKvyuyrjbyvmH+fIH AvbR0kz47rMmmw/y58bK/FwDU5UnMjQxSaOpgVm5ylYW+PWXH/ZipCJrvsA53G2MQ5rneGPztSGj TA8js/TmlHtmDEjUU1O5lICX++y8lXOXwgNFwHKYgtshvDxPC21WJEyH63tI20w7EmmwBM/A1Wmn NNqX7UQxwULy0wfkuaTDXOTqn6ZqA7f/GbPTLiYWYSMq+GX79p3L5/P6OVCsDWGJQZxGrB6KvNGP n6fWgXpL9Fb654PfS9EDH4qxbWxdbMQmRpJ6VajIDbldiubhkJ7u734jckWqUxp5TKKtiIkcYx/+ uDaKVxQ1BrOFYepKOc58bQRiG/kaBr3WtsBpoaqmpH1r0nOYcaoa5TMQ9KpoffbvusmM1avbWLyu ZcIoEMpADZZlyV+85T2L7Js4jkXlCauqmj4mGrU5cCDE+nkZay0feFXA/vyabGB276EUgjz4adKP LXAMCsep8jEJTRH2E9kVo9I2jSJFirmwWxkTclfIwo9VAYmB4mHohpnmSUYRO9Q2BgL9qLp+PIvq 2ncXhZnWZXzqLKTInajnvMaWg92lyU+kjEfZwha1BalhMlPC0uQbZ4ng7JnnuhDO8BM8F6zrPai6 LX/Wwzom0T9Ft32yp1Zu3iFIQE8X4AgfXrcN+ptGNECBJWjsuX9N6ZUr8UPSlqgPznG9IhvGSVSa gZe/qCawPe7GdHOE5J2q0WynTIdkghvnEDIJOqblxULCY0jbmdJb8fog7n86cwhGixGYaSMABFJ9 iM1pHLIqumA6kJtBKrkVKlwvkTlyb0sjuokbnHuIOmbMRYL8yJFe+/y/iHt+KtPYe8zbIrEv8SHn iCmvXdVO1hoItLXgYNEQH1ZYP76qISsmL00m0whitg9GpgJ4AaEfQdc6T5M+92vqgz65YLWohuca b98if5S/uvoFgtUnzrXVZ9b7s1PMUsBjhKFCRkPnChTT4tZQlmwomE0ZVW3fbrUu4bx8SJ4vSI4I fe82UgDNFz8ldHCPOLh4YcvG/E93oySsnvAx/4e1zNoLmfvp5F7fOrNWEpqbmM+VajU+yFuhwHmJ IJhIuY/iL2YlNW/UxAh2X1eDx+lShZoQd21W1zp9uP19zkZ2uk5cp40QjO3hXSSV911EdGwTV17W yU+imACy5oFFYn7eTjTJ7ntQc47ZJ/Dtnd78kE1OHVwsQ+bv/pNngrsZklSWmQsqIpeubODUkXe7 8eZtCLrfYEi9SHb7Qv5py1HUetY/gvfNY2DLjd7zv6A60vYZ5mfK6Y6ihXdcDt3IuqoK8TnkGQ4T dnMH0n2tsaVRkeg747UU5zlfK6OwbuXmyJ1nIYejgvlvrW8iiUzC+qI9qieQf1mLAqAy5x1vsurX hhPzu2cUENazwG5O5m6HX5AyGoQdQoqb+V1g/t90bTG7mZi2c3b4+8KeT7vdMDiF/UnVsTaqFx3g AC6AFdQXgX+CsmMWHb82kxXTMEwYVxB9Egvzc6nT0xSPuSzJUrVLQvJYfvc9MQW0gmbOcYtZBMeS l8OHk9cWX6yQPqAWuuvtQIFr2tLFe1ATYru37DHz5Kp5tl7n8Dnnhia9iu704wZqaJEodAWkcLwF GGNpEGTGoWBULNxcRiXD/hHBHE7TXLCAK6vCFIO4Ck1TyTFt/k6Qh/QJQCZwlr19UCBlitTO25aZ REZ2Xn9YWx1xNBmuMqaE0P9J8ujoKvSoc7EH7Xz9yLWHVPsS4A4kRcbvLGUSQzNH09swAMl3Rx9j rXbtLH2CpRMKIJtFevbZeZGK4EXaIsT/FrReiH7pSR7/VvIKLQqW8EzvdDGsFc2GehyYFMeI9lsH i1WfDzuKXMGwHX5YJVZLkatwlBOD+6TKEZHLE5EpHL1s02UCO9olVRzc84seXHbY0l7zr0E6z+mL /xrUpjFRxMsjr5hv1UYOBe8lL7lSOzDM/V3uKtSuiVrRFQlbGwWcwhN+bNcCJ4MYm8DxIpWnu58S xLF9Fkynulz4UoFNhk2jkUDIHj6HO6dH4Rde/LqAg7CUvcxrgobBrwZSIekLRgaf4Zch0S8Z9CMK tZZY8ptkHCuGpjNZ9xw+lOJPpI3/8GfU0G5FhjUkxxfZ55D04ctOrTdBVm18Fx7naJ9wfrimqTWb /831MLudTnnRKPqphoDmxv79gzkAxhofb477VQsHMqopxiq/J+tF5JRsfsEJmMPkYJ9NEYP3utRR H4FeSycB2Z81V4YBz3CB2LyMAxhv13A/2SMs5jFd7pu0PvUXj1PgxrWYylwdZoULa+WxcGG2wHQl vv+r9pgwKSZfM0B6Qo0LX5dy7UtqGp4mvZd7qpBEKQlsqs2xtKy8xukYDLCUJjHf0wuxKC04TnUn LCm2xvrYg6MR8uwAya/q4gx0Fac5mjbgMUEgFfyehI9kLjvMAVR2IUvBvyFtosphkU+dK4GT89tL XQlAC7aniKG5hx/g4EdRTDg6KI/ZAvLk4m2cZ8j15s3uXtClrCFN1FlEjktaKfQXUS1BaSWpXfgM xrWbqqaDtQihfZA7/PmSgpZkvHknv7gaYKOY/QXKnaayeEGTfzzbdS/0yjldIRrncVO5tHVgtHDZ VU0OFecLetTd5ipjE6/xWa/DMtEYOI1x7TdqKg0vhEE1PALHsuIyG2ZKdpLSpSCV+xpOFRDYFBkX M2/hjnFBrGju0TjZHJCzMP+9xWOO0sx3Oz2Zr56GPzCfTk6STrqozJ6dJ8gozhiRbxGzTPNeZcjD 4l8FzNEGVt8anEplvXG03UIEFJivPjYtVHs2Ww89P+sayJQWYjD+9PABbkTIrxlZpXhuqcfb2gt8 PSx1isscf+1enu5/euhJj6hp1gRsKAvZguAaTNzJffsyWy0EIEdHTz1LWqSHMwesNmwDdxJfMuMT EaFfMOXueovaQ7VBpPLM1Bly0CbZrGggE0qIDJZdk9A0/MMkj30jxI2Ywo+kwR6AqwzqO4itAPvI cHgYOpn1fO+3wFGaIZ15qR9GVI7oFJFD9KyBQPvtLTT9S1DUeExDagVUEibnG8lG3styGcbiSYU6 reh0Gruha4LgFLvKvEibM3LAZF5kT1unA7NmsYyobRwaY+d+2sKnQGk/VNpMDooI7k+lQQ3Vo7TW uYAY3tmi9BBND0TiJwCqwN4IHc7RoHlRHRtBWN1C+Zzsi4Fp5s4ZRZ+ku/cRawTxDxdVQdWF5IqN loZT/bynu+qBfbP3FxwjM6eGx+TzkEgikMZNREo0/XXINGMtzBGgUtIk3CLh9iZMtXBLX0QkIzU0 TAFnbpZzoyYKGa8mMnY3sd/NeqEUUXXYPnjQijLQYKrNtSZFiO7bnl4e8mnd+FpigyBgxFuaIFNw H7VqZT8ZGj/GWXKwbym+4Du5g3UBPEl5l4hewFKMbFX2zy2clys6Usnce5+t1P+blVEo74XZrEE4 03Ff9DkId2rsAsFPQ6mZuqTSRYcwgiyeg2R46JbL7Pqs8kvO585YkWQxgq4oAqgEQS+gVzWXIhoz SdhmpyZ+PMGJ0x1gnYbmtLWomP2JfUgWvRs90pLeuPC9F2hb5kWzi4jwD+g91ATaXozSLrjDLA4M WtfLRaT5sE0ZkUawQrriqJGATu85QPgQs2ti1m9OJKOtEH9F6AOr+UAP46ZDEeCrJBRdkNpQDFsz RQe6dP6lSGq/YIaT5WXaod3R5gIEQTbnVIiNLdcxJNNw+w2Kd+nwZjb/MBqT+YHHwz+BMHuRNLTt CK1qXiLQN13QahYiGrDWhgE+j1iReCaYCAHdpltd9spou3O0bK793Tf8XVezLW6Ta8ebFaveMpur lkHB9FRZAsBbs4fjRqyltsER2ubCpfxd69JQBEUQelb29z9RDW0AWw5o16eRL1XWhMz5e1N0hRb+ wCLxXBGeA69aRNCoxsLwvfySo6FADlgLijcEz5IsxiC6pJg3QNKL9aeTHaA9A2AMcogDuBOmI2/A b34t9QF2pD2cZTqT/+6bmcdoezSONkLpLSR67tPJAqVBTGX+O8i2Bd7cf00oPakpX9rI3AyNuO0D UFAYpxn1nazUk6t6LmoRdL6iEdQX/G881OvWWsCQJXlviS+hu/zIMzEaBzdXVhthM/fXItjGSw0P ZpejkLvLN0C9/GjcjYkp3eLLHsmorCunA7TXv7pREi3rXy9jj0aJvxupIVsLOdsCrHobUbC0Pbo4 y9Y1sihjiOJOASfv2zr5IE4jzaBIcPdT+J5xHvEGpMUl/S1j0K05gcd+XJjpWI026bzaV+0Nxg7r DdVhgbWEDlXZuoLMHvYyiU2zbyHAAbTHFKYxdbV982UEwKb5cBu48KdrTdw+qj0wnUV2EFRYWmdB j0vj2il1skauhudde6QnNeXpH7e/mqpejGlwkzOHhs5Fw15pmbMOSkTwLHZ1dXVd+2HjtKT9u8Jj u4NsMlusSIP3p6DFadUZ3WWXbhkIBtQMAwEfBDesYCWeF01ocBoJfQQR8OzOPpUF8SnSXul+mhIK BhofdoPCH/cXg3aHrR6QBspAIdLBMq+iU/qRllorWgRSl5oobMZNnsGoS8TEtbzQ5Ap6BB5LGhUI qf9ik1NvyDXhuBUhROWROmvWCRMxTnOYY0U8u53bXOIJZ1ChuDcLvEtneBRB5dUsI9ZjHMNyg1cd /5XvOWwyukiIiNIehADBoNGAqRD5WUBsEmLiLL0nkfUqqq5lGNvH5jsRtANP9mw+N0UY1OYM5QNL xXHjGAi+L0Yd/mTAkaQK+0vuP4ZjlS1P22nV5W2Q/Gpsu8P/tTpY9L1r3cRBbgs8m0KleZNAyq3D 0iXhCjuJ/iP1v6Jvt4i97aBK/2p6sUlMGBB3zhje6tDcf5Gt5RUQaYic76fLXoNAsR2wXZwso3Ke 9hEF/zgKmQpwBR7yW6/O/lme6hec79T+dFGtTJ4fK+t42V4nRyYJOBxwJyx9+/iZ04LMM5yJzLee e5PUQt/t3teGV3b4JZ9c/GFtwpoIvmiSH1YvKs2Q9yaoa6EfsRyH75aZ84EFIrpk+ZeJ/fEiDj0r M3yxgjL18qCG39TpSa9YmmsDbyJRCNoEy8nsVuAVc74DGtUQRnPtPBva2Rss4pPDDDEFHn+csEIB s8qpfchAKhPSqgOaytjIJSRivfWl+23D8Sjwbi4mscl0scrBg0v4+yBEXFTYyKsDrnq3qmqxerSQ 0yB4miKQQRe013YcprDI8h5L71b9xfxnHsXUWiQYb7yK7LpbjHSNUz1+wtdgJuSs3mhvS1/bME0h atuRqoijnSI/KqZtDx3QpbW6AgKggTzjMCKgumnszN8lm7PDwUKlXFHfkQmEWewYWIYUle7ToaAH /HWLoqrcvJD/zJszr4ZzersfwV1HWOdngcZb6Z6K92mIhFuJItf/5EH/lMQQCvW8zguNe5wEsTgB a6jX2anHpvckC315gC60WGiThcVcGkSdd8yaK5T04XLLjCHHm4+ul/m6CZhDHFLPnZoDtUz0ReFq VbF8VJeuQU10h2/Qpaf8i8Ci791bYIbMxe+IqFMxmEuH9SXjeBzu7crLeAtUyBfZbTS3w5WsiV6V IpUlTqeVU4AoCCfk5ukJPJmGVm2ZP0qSoMI1nYq2uh6E8MFo0zidIJoaIkJtq2NZk18zEMu4/dOu Ku0T7jEPWVGk1fpjxvUoZHZfHSfW+dANCG0ne1coovb0avppnk8wKx/MH/LSzjfWZSTlU6O1FU5B aMG2pjBNOBu7SAg5x4+zmSemIZhHPWpVPXlGa/+4vHdat+LpdWxrw3OzTsZUYpA/6BcuzXbO+Cae t/pnDPXQIYx1Kj5ErDIwjgcHn6PPFUQww5JRilxYS1c4cBJ1h9j0FVvk145UchbUd5qYRaNaWjPr UqORPDBv1oI6UA3NtKTlNLkzoOpvsZWHvfZr4UVIYKTNbPbf5wpgPa+GD6HXggSc8rBZwlu7fkS2 6iFoPiTleB8xPlMYORbPqdAT/Qho9RnGT0OSnkMC1RY+hqslswZ0HKmEzQQbbutGQwQmR48txuDX 8JWE3UqdZYD9fTYWDmADwLErGO6aOpfWohdv2sRHDNErcBATfX5xZP3CQUUlUL2Au/TEDGnCjfuc rF+llYRREurPQ3dUVbIDuqPRuyik8jJK3vEuTtystkzTg10BwRNwSuwv6N4VzMdI3H8L5WwAa7ZY xcLk1xiCb9rZBN0tmbyhnLAqSZLhRXu1dERni58aoZN8uzCcr+pEAHNv2lEozgZTnlJ3kHzM1N82 awkQdTxSeMtocZbkbfq2d/WozJwPXZxjqg/QJXVN9kUkAayzppionuhJNBPfoCT/owiZ+dRPf/JE 0Zd8m05LLtj6coqJVStsEEWae4vBSVjIWogHnBq2gEhE1TZM2yAZVf5GKwPCGqD4BiG13mDpAoxU sRZS2tJjcNd1V9YjxJR8VrN6upznwdPpXnaN8xuhNAqj6pCQ0RPSvqk1MguW39E4xhxvhA4Ze8mp 67r673b88V0WsJU0iLCFp7rN/WSsoI8uZaem/ePuEY2HUO6fRarJw7eNppt+kxa/+rJE+HaCdCxz e0d1hfVrJ9qSqfBBNRhnmpqwWtQAcAi03lYpeqlbXUHJGUCKUqLO1BdehWHGNH6NGtjjkKj4YF9I 3xJKZCfu5CSDjb0vRUBjdwTZA6FMsi4Z/RZvdgz3FE6D6vLlnRm5mycS1O+jGarLvGJTUX5Ucvod kbWHrv1jSkcT5c5+TlYIdrDEaHAfg5fepS1Z/ApGqJc6vlX7xmZ3Y1Bn0KH4zYRv+0TIcujREByl E32QVxKDPnBCkbEBIanInWamSgJMKqowgNR9RMvC4nrtTQNjr3VVg6AgMCI8vCwJb8Ed3dolKmbA cos/YAaxRMDkkQrkNAHQRM7TL7jVg+vPPL2ayoEMr/YA1vs9Ko7zAIDqeVesSXK0n5T1WebHN6lg 6m5Lwewb5yZV0lXwysq8HxdCCa+C9N8+X+WPXubFSbgYU2wjRUdI+cQ3xSkiuXqW3uPp0NAwTGTE elILoX1W9wbqKA2RghufBzWsuKvZJBganh06DbRraR8B2n8rWlWgaRGcFQaWDs1VoZmIPYRioGUk cZ7WgN50Jzw7F+dmOW3rVJF1CQzRWDf8kjkTDbAnzCMzwOcXkWGfptzqQWst1RXKvYfa9yIkJgos D5M16mILOgXy1wHRUpXMbaPHV3ec1k0gLTTy5S1U8cR04Mj/7C5/WLlSDdqEN/itVIivGZLD1Rrb JydtcpQn98PqMlZqp9Ri4HpV0kt3tlolewJEfhgzS9ftTTU66IpkrN0+HEkNAhj+rxvf5483Usn0 nyT3kFUN4paZ5J62GKE1KWNmIPPk+2OdxHDt12tPEcHQ9VMHo5mVrqMTMbQAqRaGK7tXkPrrKdzh hgvZ1Eokl8XlspbC/HaTGArkqPNR2k5JtPO03QOSxYKHhhN9YEy7xrHCXGqGIBev+Cje0SsXayP4 vL6K0Brc91daHuyUqfPv9LRh6OVIrSbeafAy9S+dsRLJ7eopZ5R6E6Im/opb5E5N3ZvgvM9qncPb P9J/1ydnOF3Szp3vSGvIfzgEfU6uXVRQUQ4Yduo99dB/SuPqwKcY6/TDgT7qAYZKPDNL23E3EaoL xart3RzViF0LleGaSZIYivnSrY8o3QnqAz//OKcvXZfyEZStgeoGZdKmTik65sXSha7WCip6bY/V Uh4VOGZS2uBQ7cFZbEuEaoc4frffJvYI7dLHi1eD0WEKDNZuogyU4XS+SKfG9nA3dG72uXvw67OE MF6DA/ETi8d+APYLRWGRZ/bfD9Gv+OJ8el/92hmWCB+LccvFG+G4tOZQCeoa2ciSuTEbNSGBrsn0 EzXyGhDmTGnh9T2yy8i9F75xn2vwAMjCJQJG8vML8NgAIIoSzX7Ac/ngrj7FH4mFzXYPlsPrOyP1 Wz9+tf6LQQan+A7v7c9b417jSKoqKje1sBhIKqrnOWRbF5VtXODyu3OLLt4v5JSxUGhBITSfW4hv qR25eeK9/BK0I+goHi1aIdCx6/KnR6IsdjO8fEeh0eETV/BBU54l256eeSIp6jiWpab8GwpGVbpZ zr/XOdXdBETD2Hqmj9Uw2LkhZCgt9NS/bxCrywCa7lchgs4iKawfDVrdqJASNwZ136hh7wyAT4GJ ICUeVOSMnL4H/O9ZjFLv8l8d8NHTgN97r5nJR5AuNzPypm49FRo/6hD+ky1PKgIsb+3uR0k9rYUo X7bn62/GzLqmF2TP5UEdwKE0kJ1OLaOnqJXanuG3Cp/Y2K1JwxQwQuPk4+5RY7jOIs4PIYY5Tw3C 1aDkZzRJx4wo+8jpbtfTCh6NyWLyE7lGRVt8RxIBYvAmh1nFPQfmoYu+PjSzUeJRO5VjoFuGKOXm dwmTkvzXDvZPa+9GObPXx3wy7pUBC4SKbJylz5VKcmC6P5dU4BQaEucr10P4TDhdVpbgaXLtlrIU 790NzJuRkLnPyMDud4i/N2i7MoJw5XQNE5tpqwGJLAGX66q7qRd18oVppeDEyUKtdZbfXjZF1nrV mHBi7KCS1AhDjS2Y+lrwlXBaFMlLj8jwmmFHVrZO7P6nFVuuhrerY9wprUYibW3Zs3jhdTtRJhYF 1ei7Ec39UPdM8BxDX4s2+tHZYeq0ON4n+QShKZZOE8kZcEYyg/WIyOrnKs6KggeSekjnMIkX8wDx Lqwuq4Rnpex6TOfl7HC5CXNUHddjoJFdUu+jQ9xR/fZ4hMFClw1OoJ8wEF2nxcMCCOshL4RJzB7w TtrqT8ueZDfZrOrIPprDHQTIpBIv2xLIh87DjvwiX7cxjID4Eh/3JKeyGiPe3fUzLJlPoZKLX8m4 tTlpLyxyOhVaDwZqAXc1pYjhrMfJMinVH5yjCtxJE5ApkiV5561K/+XXe0u4A41QOMEHmQ0ePo8m CumSEbwWCqm7Go3eyvofdFvq89aSjjGYh6d6cbE5Y8PQRlu/MqxLDhbazUSFQ3j21WodmM6iUdjV 3DyPCDAxYrSBH1cCF39G6zeRiSUbjl3xz6XZ8ScJNt1wz/pNz5k46pvrgZzSeCT3u49Y8fDJkQu0 H0puhzXa7M/230s52eLFmCOeJ+RZEZxr0Y890VpB1694bGkeuySBijAz9OuvmilXLf0c7l/l4mFJ IOGlAEeN8l8s7HNw1LdZPsqlZhO5lS9RN2rT+MgIJ//vo4s1GZUyc6MIobzFAlMu4WI5DmxAUYyb ZqHN53XvOewqb4Y35i7+T1i5gaIpgk3d4WDzpihMY4DKnaNQcweRZvntacwx7MX/6H518HAqr7uu 1NLQ4G5wOhzdhLCgE6xwrp6tR1CGKz83DDAhCknAV4ESxitXJKUPqE+mITW9tKBdYKyn/cxxQ0HM T54iOtm240LH7JkT13RbfWysgf/kemBDkYcOrZdpeCYudSkoGHauJtSF16zrr+YrALJcYeMUDCUA epxxE74+Za2U8ytd5vH8oXEQYeCixxvce6tgZsKpMlQm8+oQM3unYCsVb1XrP+zHOFaGK0rgg6xR IB9eNZBKjq4GdB/3v35KKbeMGSPZJX1fXRDNc6Xio8jRZ7sGbEKAdCCHY+NtUQfBRgInSJSy9ESw cYaPsir4wfFXjojXLsWyV4r3hkXlQPXwv1/VqVq4rtHDd3dsZxP4omJYsWuAQ9WxFds+Kt9GIInS Fkj5x0KEPsetu2ZBuahy2wmVBNIVU1oxnPIH5fybgxSR9Ul8I6uPTy/41Zbom1WuNfWhynUdZ+M0 GIDRgPo3FOq1Kw8ZXPRbDSKFS36NrAMNrNMnkqtRNmrS/7Sn7f7kg6r2KKUl/kr52QdJVSMTQkYB GtFinTGLd7ZUkFdBiIcTx6CaW1iM0Oqve9ulh/mlD1ublfs9av5OUTwcT8GySkemFVmZh/T909mx 3QEoDAMJZBEfaHK7oOPRjOPT2xNJ/ZmSBMpJfBbfXtuDtzyq97P4jlnsGIsqLsblvL0ypd957Ccs fb7MDYq/zRM4ZvoA5JlqFvtzWpMiR3NWEQUjeq0kmZ3Qdh/t1NRLqRMVJKHZGO+K1ApwHsOPG0Qk Tdu8ZYsXwN9Uillngyk4NqKOfgjZKr7Qbd0qAaxk2HLe9lNLnbzVte/ifQ/UaIxSffBRGcHM+FCu p+9o/Ow2tfpbX7V4nHtyzAelTcplYxXUmPgmU7NkFx+PjYFsugWDpc1v+/thz99lVvd7Kpg8dwJw enUWJP/oui2zO8sXucREUmjlATqa3yEjLd2voVyNZbZSxxLB3uX7dBLdh8MToQen2FOthd3S1VB7 eOpC2+089TNodEwJ7Al5vxuyYo/uO4Xyd8hnvqATP1NHLe5AFTjfBgeeQX2zeeC4dJ0R13MyOr0X pVWbVjJJA0hd3h7KlS1uTqUQiK0x0vTWnzY+IzdjCpwLiW/O99Q9vlr9flFia3GYxoDE9ASl5CTF N6q7dZxVL0BdouuqEGR2NWZwmXF/NU/IyxUDKxY7XDLOhRG5bep6Qr9mq48yp5ZUQsAA979srwJr 12T5Q2QqYYBx+jBhvs3Ztto2XXqfmqCyQEk7LPhWdAW+nTX98v5ivejAVWnlfh1RMuHsHuUTZPRS /V/y2kfYjU6DrceHpASB5HqY+rl1YsW/YxYv+P3L5/tGldYQVJLK5myZoPR/uuLyNAsAb2fsNXum ZWueBWkNQgNFR9i6o0174CfwwTCZPAHSYYsgzWLjmo9MmNthWdEL6OkJF4fFPpNLELfHeXBaBJRD 2fnph9SM8W4Y0c2vlTHFArVmCVmqociy70GQ8ILkw10/bfSbR0L57xh8edYpXU8jSXrRGuiQvOli fQhV/1XyTvUJIceFgAjnGV0f+UqVCYsh5QnKMvXqjl0O41ZDM0AhsYFH+R7jjU0MTdXjxhZxBCVK lUCo0w73xFwzxn/ap1JDoPwLS9cH60OYYUXF2kqkU+Vnss3BAALeNSQ9kJMu0EMi/xwwI/O6YaLR 1rCak5UPTf4FBwr5E/aZp/vR2qv4b0HL695e8uH5+mpguKXyLg+YZN/ZofvDPPbRjNmvszjEf/cL 6aoy9a/ObX0L99KzmXOJT6EnS0yYeRbfcB7wjlAvHgcGoTuKa33P8HSLNZgujjowzESATYdcp/eU kiL2oqj2qlTmLt1H+qjYvYAKAwc7JWUmxVop3qeys7460FNjuo7+si98STHqX1ZSGhzEv8dv23mE 1QD5fEWebM0mcQgpXztYCKZCTtV9vT7uvraqm2MCWzEWx6V4opvJ6jkT7X4ATkonI8id60Xag5HC S7kecSuW4xs5DTl4f2sjKdRGqVBJan3Q9AV03mpZ2JM0pMcnTOUVzulnJ9P+O4Dl2XqtSZ5sv7kl iX40qBN+NjgX5VaRniJwczUpkbpi+o+z5UhkcL8sdQEECtszAyXKwPoxXD6ape7vkWEaDWJyGmaA jOeF5vQe+pvEzP6kAW6oWyxWCl+cBAUZX3lGp2/NVi07ywFiCmc0O3AKm/YUXdkpqgxCLyHiakdU wIkURQ16Rtf1GH7EXAQXnS0qEq2eOAWZIz2mZFmIy3FKLjUOsicwGbvBI47vPidJ4xbwMFqpLvya P5M9o80zyoLzt/iSB+SBvAUXGroDu6Ob7NLZOEp5V0ESg7OMptbo5Dz1s/N3aQKuN1MG5r+HcEKs XvFqgjoCxtSF4ndn/ZujwJx+bw+2LEwzne4I311nFezEaz+faUesz5GQHiFoAEhNBn4teFbB0slp czcYNKeTB1x82pg8MIE51lRV0mDYbghRXtznUySBpAQTWB5vBUZ9AKXpxQEacbIftijr+IvnHkJt C7mPI7dJC9sAOR5yOgmeACrB0ny8uI4E2R7FHeBmI1tQxahKNv/uFh58FRTm90/beAtcdks4xPlD a+wGq6lazCr7/f/xcTfS+XKVnp/aMKTJrjgfWNowcy5P/jXQUHvXpX7ipVvc18unkrhoMrV/bXEN Xwgw8JftMFcRAFebWDlRThBoBp6mdC8v08BAU+oQiZLFbgNdRRT1ZsWTeQ3TwvDYB3hiXliTjy3V H+yTQyz8UcsQwmwVeC7+JU9CMvIwCSeJjRhrrx/hWv8pmuiaut5erv1vjFhasLvWbV3BlUmXAI72 GEMxcKznivlhPMmX4Fsx0Clie2QcOxwLHUvmHcMwDrv4zzvBtkpvHAd3gcB4iaTVhBtHv2079UU4 56sTCnwnYaU9YdyEmgV3fmdSgiv/3c9+9ud4Ik7+RoY1ORI6nI7MRyV/4M4ECxxOfUUjagzZfV0L fEeYE2sM9VsIqBI8TZspGcogHJ6cD7G45Ed9eZprH7w/Yb0m95Spnh5VkjjOKHDJ3SYR0wxTW5+Z SBhK/AD2LbQlgHK2HkF0WpcyC5UKzVV2l+qzn38jrLzWsgNxrbVydavJIQMdNZPQMwM+Eu8JO+jG C1iR9hzbxwJFVd3TNyshTFkcALxKKbfOWKqC3SfqrWVqbGV22ZqIDZ9pA2YISYJGguxSTWscgT43 h1hf8kJTGHcenRApGxuX0jxEa+6AL53N5A7gMiwPEh/qPHUsXGO4ACRN1qiMRI7t99UzwMGgfEun HVrVK2VWa8xWRmNsYOGMW/q3Al4Uww29zH13hHHI1j2s0OVcpmTLTMaGBNfxJ0RzXYQOEoE2kWR0 Bbei8UGUzAYwEvz9dxDaKUZR6Xjq5BJAWN0Z1c/fasLja8qAtE6xzMF/4txK8oHVXJiIlvqfYuAW H2zEpqVzW6dLFAtndsGQiXqYr17DXb/BToJ54fv44PttyqzLZTmZygNfsP3FQO1ZhMMNKSg7YYS1 O/bpdZnB76d2S2LjM7/0AxIt7sOoVvX6zlov0u/RbxzbY6dQx2Sqh4wMpL/cg6+957xbLj/1mViu oivmaVYKkjitvJsh7d6yeS23LmNCYyzFR5Oukg/H9qffK3bOQHxDojz0m5G2oRP8R5ITUTi1ZDaW SHYOiw0dj2V1DEIQFAKZNqwkwPXtaqxCSDu8zt63Z/Gt/W5HMbYA56AMFVeGvM7qdNSkoUuLhJ4R U4sn5/O/IhN1sqFphbqj0O7uRZxQ4oNYSmxQybMTAgZh6JppNBi0suVpwBwZByCDF1ZU1hC2Lopa WplaNrFBwOrXQjfp6dvoFuQsD00PcBB6iFJ7vapz47G/6ab/G3DlwR07GgFHcTiXnYuOgVGwxF8k 8YYlie3s0kw8v7KEeKUb2Ltk5+HdFBsPr5QiB7wgMNARFZosAG3qW8tsof0TWNvHF3lEs4XzAlC0 OrIeDGRJvt2ZOT5eRuYh6CKYBljhMIg1JNPiTPQRw+Q5vY8Ej7JFEvyJs73gXX2glM1mEIUrBcE4 COLb9GSbSl4hHwrxYWqZX8bltI4G6j2otn2vmptPoX28+5o6m5L+gosxaYeZ1TlTE9fgIhidxwwN dFLeBwQL9QyAsPWeG2nZcWzqeRBEBLnIigb/zOJxMk7OlJH1YfejMEDheTh4PElZ5gLL91mGWhoH ui6dBNR6Xs9NwpFdnBEH9I2iaOOM8kroYm5hVhgh2w6QqzB6MATn1RpWAHB96wm2frMp/Ziw395b 4V9M+BAfRE1IwzZ7Si80+GhxlpIFz+3MVTZ9r+92HOVKkNPPQqP1VcLvk37nEVzyhhOTEWp1hTDH efFs2BnvzguJ6q//sTM4d+Yrkj3wl1GozTlzNEKTIUVomlh4vSLf1JAo1ih4VVH9Xlz9HgiqoNf+ /pCFep1w31S8o55y0nHMIrED8IaNnQuMLR10VBjN1royyMZf/3kBpw5N72CIgYSPtWGnIcVqziFp 3683oMBEPQfkLyxocdX5LU10qTodvbt4YK4ITCY01QP29fEsCzdAM9peK509UxfLbZVp1lihKfZN L1xLL/oun8bgJNgivpyxzvVGLI+ASCsdN3NQqhqCN3tm3yDwFUdHISoB1DPQo1tTv2IsAeNwQ0Hd YR2FPFyb1v1BvP9ML2CRyEtE7Q/FAFzzXI0hjCugy53l6o7I0SzJHO5GKlv6DER592GDnbXQMDAA mMFrLWW93I/3YruvIC2eihBkJzMlqeWiNg0L31nxnsx9RhxjIt5FftlH7bmcwKAqTr/FrW4O9Pfm YlnvblRzK0+37ejsigjl+goRE0l0XNgBjPdrqhp5IVQkv2P8nTDUaLznTv/kvtZackQvU+xP9QDT VjmCA8f8NQGt8D5NNKJmakv5i2nMo7WP8NqSDjU1QjV1fcOTNF2v34Ob9CrGN5X9Rb/tVzRxxvvW OM1AtDpvH5MeSrdFKt3HU4RGAn9evMkc096P0ltgdsBPeTtNBG4EO3Ovrc/+mBQIye0Stv8Rla5s jjWI0fOH/yFkxV5ZdyuC2BExMQwKCRuFCZfy4aSLJACdHpnmC2Q2ERkQWnoQdpb/Ozep868S8Hs5 dDjdVdp2ElZfPE4Me+KYO+IWo8oyL9eQ02krBtn6AAtVA/zCNzuE/HdTsIYjWw0uj7qGj5SRFl3O D4HwDgfxiCcQDZVNu6ProfBvlhmP80D9HPTuno6b1YiX0zn+i1szMAI9gceT40DgeJYVqBbjzUgo 6Ju1t+rTrIXkRUzqGbYd+xDK1ssO4PtA65KkniIBOzkkbnWSRCC+MCVvLSc4zSaE5PEcaGj+4KuW iQc/yhss5zSVhSK2eGIm3MLx1EJ865s1UCqXJ6FNUsIgBBOv+YUnUh4Lv4GcOEmODyUm7zJgTmSH CP7wuv9X1vkDJE2qKza4Iiiy/xwLqscyEW88v8phFIlTZIkmtZUgxqkJgozHxgOy/hAkQKyiGrBt u8b168oVlpRyxxmLXvPinY7EFkYnS+vX4myqjMu2OFTcIMYXqg+rBmTgYAmAe5V1rcJq16vuceuL tjjsK9gsiTVEgiPTuUoB3kjX+/mbK9FBCGwXtE35gbu0MWCvS6Cd2CUAWuLraGx2E2LEySpGFXyi BS772iqMcA7wAZwU+iTgLZ0pHmjqNgicFzmaj8iQ9/u7RN8L+EDdTb+AT78enO609PRmitYqPmS3 M0f6kDFPSWKM1IgY8PATjPbN7FWoAnBcGQ8nSa5/c7gBuMzpqnaoznMu56kGhM/QbV8V6o9G6bmi x78/xO1dsyQQZ3keuOjNJnfsugl5iD5YTdGX1/PrksgcT6GfcQUtOYC7MoGXzA6wDA3h24RIaH1/ GzNcZreuDpcPHXe7LnoABLMAhJHPI28LoNZzYpLJUFUySvnAUK6glaf1Mg7d+yKMb06IrKyMa6uX /d4+nD6uvvmG5CpWfxmTSZpUzVWIvsNcRDl1vCOrcI2uiP8GYHLUkQmJFpQbnr3RdN6jW1UBEGsq A5tzEXqVGX9Dnfin2jaOmpg+XYGs3M/XInQinQd7VwQrC/dLVAjX1kUViKqdpbmBVFWdC0tJgLyb f5uWQgjq9altYaeALLYpbC7CDpd6fJjq1yVXQ+cxP0RRaFOy6MEHnT3K/jA+DwF7qS0F6Uyn4LQN 3I4DMWjX4EtGME2gKVVGcnnOZrUApzxyugKi+gq/iQi6IlbaFAMI05vWhlQGpT8jv37tdo23bbS8 ZOPbl+yjXUzVBEkD2KuaxYhsSSQ/fJSKhHxaX3MuDqf6mgYamqmXb0+Q7+A8aTXGUGpBeqMqqlca ZmEqzTtlSIFHuA3IzzuTK6KcOZTNZ+VnInhQ86PbPKYr9r0qHSo6fguq2xbZdeX26qculRkC2sx8 KDYdwnHBkX6AkhGvTySm0t2AOhHM8E4ejzmn7QfpiLcRTpZ15C3/GQRLuq0wfD/ItCzKqmWXivrD tbxmZUdWjE0/r+hWYSZ8bgs8YahYKRQDiF2O07Lf7gdWGKpr48OlVwu5yGQbVJ60oNxsjSSzG+fn Gmij88qZOgAs55L9zMikKzNAaxmuQZiDY5LG8yswTCIYkcsoopVwvlZPj20pB9futkDnmT4G4GP5 H32PapcGq/5753SpOutYfL0k2Fe/U/YGSYjjjhjg4ZzY8k4gdV5JTJU+UFZFP7U6Yw8DBtswXEAK oKrlYMNXbUx9IAXZmA/zcyLyL6djTvRBcplX5+lLA/3eg4iC3nTsd0Kg67C4GBcnHenGzTE1vEUp qNj4yy8vDrDqfQvGKOpcR7T3ZMRSC5DpoQ/ayfhxNnRpD8+AdLJ7rhUVD4ZQXRb7rFCFfhK0gM4L swsULwaf5d3hd+KsY7+dht9vmzcLduyslLBzLSoQwckotp/drGsdw8DZcn6mujnVriLLO/7kxD4v r/s4KAJyFI31jsIp3pCKz23X6fsjSEV21ZpjxKTRPhEQpnzKoZXYVTak5aHFlp4pqCqUB1RG8lHr /01SfiCaXzAC5kJGD9HhRSfo6XHgZ0Y185FI3BMYzkXYa7V1pwroiqkFKucFE/2rhlcjwGp7KzW3 al6uA7mijp/eQqRI6PtVRg+FPiNJw0yJc6f2QvpxqlSN2NFLZUattKuvKDTZ4zUYjdMBTO+dtqlK BAZEKjkSKmWfd/D+szfbYxXuwGwPrzPR8p+ZnxygUdGFz4LVbX+jZ7tjb1pGFo5s1aQ+m/OoaEQr 86jyvjFmsvCGuLS7AbD0k77spdQMCqsNXXgkWSkh5Iq+pf8643Dl0DI8CHmlJstO+/qMoEZ3ACQT RzxUWFZ0yzINlpuElD5XnnqcRtwL9k7CoZ1RWju3gFcT9fEyy0ag6UWhLj6uF9AaxgrXY6Oittau B9qFfn7Vp3K1qbA4EJuBj7MI+gk1BuVZlSLoQH5dhWPEHAA9xW6HoDa2qcP9xDxRH1sOiFHngDrk jrcTD2QXkYJ9DOFTyXOV3phjfhOdAOILVqK1fcD49YhGw+SIm2/LvCPrZXeBRLCWqvoa/yqAB1kX H9EEfnEQi8lL4C0THwHtyoo+IMSvC+mZjpfvI2vnjup3nqy+C+zp68hrxlvyPBvgVP+cq4JZpdJk EnbramkQ9qwRxxgtfIwnru6wcWFiij7/Svw5AMqEd0+B3LQaGhHsF/szYq3uhVw8lMVKzpKp1dmn TjfW82M4IvnnMa/a02SV8WxU6n7c9w/sOzo+tm+2J32Pqul0ZNuCNZHNJOwrdxe4CJ2pCwmhWmyl BRocd1Xod2+I913oLBusAUoMz4/mR99WA9rl/UiB6TX5HdNT/ns+eF/fmtvM1a+A3SShrKdbxJfU Wp+FNg5CjF1vMElfnfirSAzrhLMMIPz3hpFoWbwnEjDqGIvig8nCdRPouhCY3saxkz/WThECc9Rf gENcU7cLUZHMhsebX43vC9tPpCTmC61pCyI+Rjt65avzOPkmMEnnmJz862WD/sHMTRlHAUK0gcPN MCIVYL4TIxKXb97RgEx3qIxVSR/VTLMSFL45V3D94i+jaf4euaToW24RGK4t98OQAm3hAmdXc9mH 7Ilh7Y6HcGUhfbjj6mdg4fcrAcwaEBIN5btGRMjQmhpM+arItgEo1PYuqgXTrHfeZfUKOQczsWJW AtBI6VlmY57JYyUTXk2OkzXRjUTUhDAtHw5Og2Xk43ZnxsMDv1uNtVQcDXSgL9YMymaAdcS/Zewk 6hndj1MUH90koGLy3I02tbAi2VHubOI1lUmtUYiz5za58fWoj/AGyX3Ldgs6g9nTWBV/u0vP+a00 qbgyvjk0O4c49Yb0B+mWUdCHqjfmZMljEHQK5YrQEBGlj0/KVYKvaL2IVbWuSZpcLwlECSwFfl+X 1MW+INtGINVL4JEqFNPB5Xy5SMBsuMCmcBZ4DUTKpFgG+PXwTdtL441kX2ihvUV3lizQJZAum0nE EMFkYQ/ZeBJD3jb/MWo0ux2S85ipmH5+ZjkOmfmjVkVUwW/qt6L93tbmb9dlxlizQwH8o97Dqwfj jbx3B4fnrPCuyfZEQCg5h/5RRzQEpgFAeNRtOyIY2JTV42ewPsVMORh383W6C6cmSPiItNs8VC9W HEZYna7tWm20spCrnEPSoupw+Dd9Umd3Xw80oKMTtKCZayenj+S247FnZ33XqQoynlnFW1vJaCKh y1HJyh8BHwr/rkOJatdHcb76s0UNSPEGmQwuvrmjZRJA7F/m3pNkU2X4Agye6Sik38QfCre+bQ1E hAclcFTIUQ2A421R5e87LAh8C2ZJJEsiA9fpqJh8Iu7i8l1U7IIv2Q28rX60/HQi+rkcvXn0vhRQ MXut9FNqe2rD9n822X1PLgI50eeUrmCAJT7s0f1pkTmw8Cry7gsy0wA0WOTP8GQmuK8n/uZ3G/Qp /dLW+cPQLRn9h1bUu4dUrmvRbz77X6Xyl9lEUkA9eMpBgY/9UzM0W/YR86fd3p5EdjuKrsG1t3jO 3SyH7po7JhGSC7UWHEAOHmVvFzl7o2868xeZx2HHQ3DiGipl3+s3nltz7xV9jF89AWxTBpSI2dm4 +AITqk8uPjLwF7QEElgsR9v9FDEkp+fZqTNhPSMlnMAwR5cWEiPJqdcUOKNK7XIwDtL45v/89Zfd x9+gKWp5fYMprPDaXh7Qe0ewFZDXfrXeqaefYhqMXIUTUNtCbKlDe7SRErdba2HJCItb6/fgQppu HsjsEl4u3JGHaxQISnaz3gIQ4EoBYHWHRGfU4Ri+8aocwMLO1OMW/iLAp+AE7/zpjmgmv2eVogMd ANg6h1PuIQfrNqcqKA13agcHUnUW1zmiRSpJuHUxSdNRXBw9hgI42nlbEweUd29ZgJrIN/YlyGCT hCGsKsnEAJmwcvFj9aC+7L32NvuSV+z0GgxVDPyG567keAO7XqhApAj2n6SheW0lwhCcTNTjWGqM fEZ/6elJcPIlmknuV7VHAraRftJzjLjE27aEU6wG3GmYwT4s4bzeMjNS6wZ8MP+qEGOiY2k2EdKj Tc95NvOcpgVwkjFHpt587O4xyMWE5WxXPB10M9rAv3RCZ6nUtQfpB//VbcQAnI3xgj6Y6Yas87Vq 7JqjLhIgWK4GJ183slrznZMXTksLhP+cXL/9eu5jq/xdB4fTJMaVmYr2+kCB2+PMzYVd2YmHZC1l p2MFcqgat52upGMw2XFYQyXpCkAfrHSjBP+Nz3qqzNff1//3vx+FYLwUpU4V25jaYUDVxMCNI1vy w+uZeYzidcz5IN6wqvIa+i1Yog6z/LDRqilAfZ2UBhPRVHN5ixUojc2er9vLsBCwh7z7yIQdCPvi hizG2R95bSKF9gFy2osG+x6UE6uV2hM418PvPueuacOftwxz2VLbn8fXoAlXDJvCNf4nzvn6WJse sprJhaCo0OjkE+OdBr3zi4xYfSvyhs0jHTbIk0yGZJtiSe39sADs5sfCR4kW00F3psoPR8Bm5zXk w+ey713+u95Bjq7nXnXBYuHlxaHWoxXvXuJK2Uq90dLUromx/7iITzOn9VgDP+Wv+8YOOf8U3892 dHvlK1TUTvj8ivuHOF/j/WVIGunqI9BBc+eAFRuYTczQfX0t4gU8v6Hs9VFnY96aehDVY7TM2xvl xDDDdIC7kTGATUWsfQOr2uf0hp6HYFYqK5p4Aq4Md84GFnKtz2NZR3BtkJZuOMRfNNinrJlWpTEV q2F5LfGRMqadDKXPOCgfvmmspTKLCCSBCZlZsU00tZYz/0d83eM0v+yhcM4Gq+NGc3Lw056Ypj1B h5sLmZzPHodRRNsga8TCi0TbB8dRJUPOlamLKTV0HLNms+K4sWzuwzBrOMWC/t53ooyznNkcEIJm 9rQNUtmUy+UdnakokBM2P+sINsQ0M7fBGGTHP6Ta1ikUab6OuAB5Kszo1NDabXPbw4//d2ep8RAS cLofNXI2ye4paHAihVwSMs1RApmQZAYxwvgzK2wbrRMmcEzSBKxPg3TUyQoawgBCuiqfkB/jaYlr BtomQXXpCGsW5w0l2/pXzgdEpJIJBsPiQ7ActXJ0f2Ro78dXFWVpSAugMZVnvDsBRsN0PHsEdT9b USuQnpE2nYl88wqKCr+2sFOyx7FQ7jZRtq8oPQQ9yeTWhcE5eJd7kogAP+ofL9X1DBwme79bCyYD rneczbo/SZ7LgMbwWsUH2xHuZ3Ysi4s59JlQCeFUl2vBAhf+Yeykv1T+MLDmZ6X2/gSGb9M4K/rq 9LMi5nNCUTYwwEY6vwE6GUhisaDVIaaXblyT17iNJfW3DFA1DxZ40B2z0ICjH6XNNCMouI8YhSYT Fx1sWSr/0YOs06Ai2lx0WDM4V2P2Qvoz94mC/b5j3yA9vJQidNG21n3kGe603v1UdwSbLd2v8RCO eVRc14v8DrYsFEmEH0cJJLTK4aY5EScbCdgqbNNi3LGynvfRKT9GPo4DSagAOkdteoNYFQwU7sV3 erZWO5QVo1Rt3s6q+FXrj8Ujzagaa1V1bbgTsKcS1LpdMcCTtyF6S989S4RGWssqUEo2Zugv6Aex 6wO7lj1B1H7T2Cz8GIzI3XPMWbfJByw4tDjGAPO70eb6Rtq80keZcSBWkGYTQB6xHqueafxXe98t ZLbNzaNaL8vObJRjzZ68aaaMQNFA8o/Zgio0OkAgS9ynBaNJGRTgFlmRyLBnhiOMMvLalES3RhuA VwO3lJw2dEyYel8zTgyDLdaLZW5PVHWQvZQJSPoi2AyoaxBgHYWbKf1AUpzVww5PEnigL7eXs7xl ZDoAdbTVSz62vDq+un9eWKuAbP2gjzstAAFucV6XBty0ZFZIanSZwJuhPW8grMIa3pEm6YtoTTBN C6ODP5qMy6ABSCI9/iMoolH5lLBAWOtjq/9BhECX2rEsysx/yZrozsimi6IDMsbgpe7X3r3XNxPa 5pK4EO6qXHLNj/K1hom1Kt/6pxNoyDsyYPramK4UmTLgDyMy2oVRamAe96bEFN9Lx0GdaeJrliE1 bT5Kn4OHE9WUdLeeMNtvq/FF6w0ZcCiXLLMQPXdmN17IvxUrrL8PyLwJJ2DHkGfK5amg3jQU4avG +/t+wHxqsLNfotUt8UDrlADtq6+z1NiSiHY11T/lO6BW9XiX97FIjX0giDITfjymzgIY77swIV9V NuWpsRSrAb09ee0Xx0hvvtS+C414Z3QyB6EgufhGHe12WruxqGDftnBnPYRFvt0J+ERNkNoYXwta pNvL0x7fB8BU8Df9TObrO1AwMW2JmbWqAVmvYNB6pOqSu3PQabIYGJwOx0hqbMOI45+urQF+dy9F IdpqOcxZquudpcOydrkd8w1wkJXtlWHWkrpeHFez5qJNmTtEgHy3j7bAgj5hB6KJl73vPmGgUreG 4myxxTpgizyxY1cees3ZKutLzf1L3kwlTY8BDncVi62NrbRcg4jqlq6Y7f5LZ5Py39HirEMQGAua j/3hky33g6LqUiXMZsjob1XHGwt5IqrTYgvlwhl0JJfAVXUh/7mDnvjrdUjxDEIE0I+N9e5OVweU lIQGQuDjenrDnhrmQ55457re41spn0SxbUxnbsF6Ddd7K39GErTYpcDvcb4THT1gZfjQj3nUy5qP s3Ky5GsY9kXAzR7s08J0n50RTXaJHI4PobT8QV4SUuoMPQ59tzfT1xmOnzfNWfcleClwpHvg3Wt+ B/T11s9I3N+BvQu4RaDIODAwpsix2ZPK+P4l4ITDNHbiaYcqfci/cY0tWHVRlCf2ba+2VVo0GT1E aDjW9I3DGUC5ssFIl3LOWC65WFsgTOdX5mvWImgNBrh3casdnU0t8zmOQtFM61Hvw98tlsqmzMoC Dgh963lpCfIs1DU2t2DqCof+eWubLNw7Negl7oH8HVIX4tZySbgpKRqZIJZ1XuRhCDMPyE6/vmiA CqNNLOkRWl/tnqS7Rkp1ILBksMqm+4qv06IzYn/3fBUt+DCBzhkSI1VM9ZNMtOGf6DTY/7nru1eU kq62UZ8St/Pf0L3KnLyrK9lsGEYZQA+ImQSr7uc0s3QE3AR93ssEKtW2TYAHlSH1gr+5wA/UOJ/Y V2Nx1zgZGqn+1JpC5BAfyDCfkRrRb5wI79MN2Qu2qxqANWivIvsVg6/3HVwMbt5+y/VKeUzCtv3x S5xjXDgZhwS84SjqPDuKl1SnQy2EIqLBDwpKg71WdNuriXDtwn/UPiH+HPva/aimxGJQLXQksVlu lYBbqgjBM9W4+dCbX3r1T8Cr21ds/ZhtrgBpdkzMqeyqAAerLCNXE6l8CaoSEHUpiU+w1mkbDGB4 3rd7Ki/xuvVjVL87mu2VFsyUj8fnm425bOFi8vQ30xAh68abPtXe4JcnFF8f/oNozcJ1kt4EZnt9 5LPJhkrIrAXq+2VyjMtv5zTYnpHEpAgL3vpFDe0TMXlkSDcs9n4WevC0r/wIfZED25pA5atd74Zk qjUdO/Y2MHCkBHOi3ui7c700GmEXfohwzXKjlK1F1xeMI/FFmB6LsC7chMAb4jYkdbBOKchMZyHU CaL0d4dl6LI0iEBNRfhPTf+Hc3L202eRWg7N/xWhEJY+1XyWKF25+OJ1JEuICITiYTM6tc48SaRy 9hsqjp9znwtraXFDcYlfbbCIXSfn06mSpRp85tyj85lLMWRB+wrJouQPgfI2vBE0pjY1nB5kwtB8 P2CxEkeo/qennBfyOHJuGH7VnqTUWULwfVE0ioHfOkZ5X1BWtnTnlePZNcl2xKxHxbOPBHyOiIIQ NygjBNku0tmWYoNhGywqy1QnVioPCwJWDz/oDB0Z+7VR5cQ4hEHe+/cHNELw7qNGfRLHNRmNK3lP rpraU/9NwaBmjoMrq8TX4kwv7iSF7B90u1fk/TcTsKG6HiTqTykaZUIsmba2p2lk/DUdjak2qVm7 65pf0qiCarJ9I94krDyWEsQUw814FRYqJCGHjhR/VwmMGHzk+o/yrieiAqPb5r6AWVsFKjJijh9F yRf2Yrm9M9kHBNWH4Oqi9CGpWzxA5bwuYN6+uSBMDqv4M8IFozV8C6NsMv5p4WwBlea4rYmFbKpp 2HEIBBaKeETRQCuCf80CQjYWk4l6AMxnVt/MdBwTFF7HO0MUWg+W+uRjBuo/VaPgwg+PvxkhMdRP KXV47qKLiXRYHg361mRuobJPQfZfvCI5KGx3e9PKXcgki0s8vtcFSpbEeqwNUr7mxbwdRgxkiYrj 71HFggYgOSvXYs8ReStfN7z97X6sGlxNckhNrwKD4BX5CU94MAP2725jbA0yV9+KgpbfOm2mKCec s395ur6nK8G7mLq/2dd92LpiMpw5RRC3CJB0JHUUhridvD8uMjdJdBMzFbBMkfRvn/SSOcCfYkmP abrGDJ2lyEnMgGc214F3AuKa91AnD1gCJ/wHMHLwQdmsfese6VLxoe46qS6PbMa95tM/Dot+Szil IB7KCV8Vc3Y2edvAJ2dozSxy+cuCCcne7UP9VLecLwx39PXDkLUGvrNgck6uqowkfpG9qDU6qFDm ELqmPwW5zx6arhAiTeHeRYyVhN8B6I6iFf/IbhgaGzw9dbDwKuCeBxUTDeAdHUAxZN637ZRDg/G4 FlpAMbEIJDQvT0EQbhPXZYjnfjhDMxn5OWgfJzYPi2SFVRVitKchsrmN16lIIB1KFbP8+URXX8Hc +KiZSwy1bmen9hlmiH45CXnGeCSpgSLRgVgfFqEI9VRMm4VSj3ehrvwKUBbjBpoWcN3j0VtrWEmK gQtOaOgkiHSg3bvdloAF1tT9W3tr99RsaCEp/PAQJT5P7E7aD2cc+ZrKT7Dr1XH1hUUTagXSPznM IJYrxRApAcZjXRK15FtghaonGaGHL/Bd0heajMcZBqbj41Zq0fxu1JNDdEszGCvUXKqHOBeByuoc Q+edpBOsZhtAnM3fK39si4Hwt01iX0czTYm7WrYn70QmZ1qTjalTbm9sTgZU4dc1wb424sIhV7+X jKSaH18qVRiPTx6phBhwKZGb5Ari+TPCM0k6qznOrkRzeVqPTzdzSEu/+aUSweO9Mk3bbtL+A9n+ FJTqJHAuyQycpHYWMtOgnz3Bmx3/ri2TsRjZDtuXHo5Tm9hcZr6vUdRzkOrZWqYSvbkCSrKrnM+f qeMEZK39AYmqrjyzkbnpqAj/6GwTP21jHbgj9IkfYqcykCOmnlkmI7ouvFIwMSAibgJVJC4Ca/5k KSHAkPSwCXdNYqsf38kiB7YTn1wPdrbGbC8uP1+Yj+9f+0n68xRqioxL3ljyi5EPDdM/GFBuJ7Pt ejTh7Ftj0trKFyGCb77sYVtSMvQVPPCHidfSxOn+gPIV9SXBQxPLIri9jPLhV6eXa9jlv5UJmYUN lIz3lPP+q5R/I4P9H0VRi22ETUvAUJP4LVYKhoPacFIfgd9dyFYDVxTGKtspVhWCkAmwxKg04heB ODisYN+XuqDzTDx4J/wPW4RdSvNvJDwC0Fs4oJiJ+nwEAkQVJFqO2HsfrjypARNDoNdzqc/VyT/4 wD42pSg+rLHJIK8p7qu4fWDmgXyHpJKrOEHmKSErauOEw/41ja0rayh+HFexEMgOekJJgS+9W8SE ObOByTRN0lAg5cHoc1fzRHMkdpoxsTp0Q0RtVvJvmRsSjJytqmt7U5jWYl5LQcAuIpGDneghI8NH vwQFU6bkTfo7bspQJilsBUnCIBDXrebhyp4KOVCUYkeH/IRK90Mf/1Kra0oIvlbB4nEu/WAzbxsK Mr5rdzSP6AzLj12FT745cM62q1AZcMfGHCDb5hX3iyNWQXck1XZaetss03r//fZn2qxc/a2ZWXwL XBjV3BYz4N/4OgLbpdiYmywMw0LsW32ebbvAwUaPsRTtFAl67uGhOXMDcQdSKMaMwq7mMFv8I2To Zkbf5KgrKs26gs2aA21d6FUbwIRvEvrmNHxGGIZarXPJw81kpjPwE8gJqzU7w9U0iVSahGGCVtRM m1DHfkfBXCstnpye+4pEjqM5FfTJSRqrEeUcw2RNLPZjnMe9wQj1eBJ5Sxp0wdfw3kcO6AmPFQPw WHbjwmnH2x/WzsfYQfvn1qlpFQ0jsQFs70MnvbiqT6Kp+9lxZ2nEXOZpArvAbzFHYt8zrY9Mm/sK qtFnKOuDM5nkqWDPKJlLaXFY7GOUQ/8wUwa3SguFbzLxU+ZH/NcXdqCOsqcuTmUV4v8mIBv/HO/e umHC8xIvZ7NnFfEtfiovv0EhRC/j/z9mWI6BwrVwy7/+rJRi7CiiQBXWY66F9q+/CAonL/d4CQ7R nhIVWpO0LagZeko0JWNvmh2ltu7u9wdqSuQ6NSLGbcazaSFY+etTWF0SHg9GHkLYlDzImvjTA/pT MC8Q1tbNDVVNnc13r5U6JlThEJNY5ZoTlamvpYZu4w/CeuZ8Rn6JwuMM50m12AQCnDk2KTEJIBoH VyC4sTPEwHwKe/evWZyUyCbZ88qWzpVvGNI2Px/zDZxaMyB76arJhPrXdRyeWw4XRHDoSQVrw+g7 4YfP1AcmGqKguVEm37mYvQ6tP3GPxSZd1Ybvc5uZ0GYYeXDrCD7S4J5h73GOJ1ywN6rqPVlTZBFL z8TWgrGlyiiea23mVfMTMSpuJ+HFlSrSMB3J4K1g5hgWLL7WB3y5Oz4qTLp2QRMnhEomiPJn+VhN mbOiOlm67nBUE7ebdEEs1HenMaYoTMJaf0JOFvcOs7RUx2jf/PnrDKbBaLphDSZxZgeyzz7MovI6 KCqoamy0VScCY8sNi1v4BphIbc/cVoIJPl/Y1easmlPtOrzeX0I1Xm2qt8TGUjUH4QrlC8ejwjfP 2Z2rCVndpXwPsaPy9nXrAbVanBLG59hY0wqRE5xVgzA9dI8EojsY2zDSmbxzLpZN10xRDJM733kQ LyRsE2NmIsNedHUyyTB9JAJMNyq4q5zQiibeovIF/V682eeE4cQhiaAMcM8E0D3dQc2DFromYbN3 kw073A6nT67hxWjebcma4imsL+C/GEBDNrt00F/Q0qUzKgkCzmVyEPSQGMHC8x1oKR9RQP7klzES lcw3NCoXF1nmrUwYNdBA/OkqBmtjCeGLbIJhYsvVIBrlI/EzG2LsK/iA8nL9wDaMd5+qRpowcbYY JLCN2FG9zweBqHn1+z3QwBLhn3kUE+BP7S6rj7IPvzVwCdTjEK7oprYOl05g6YFtgpFH+hHJASQe +fgTBOx0PTp437GJdZcty7Mx/DSp/Qg09NH6yxP4bPrssPbGGZzo82Uhd/rT/TPV13csHi6IPBp+ 1Zi0r3i2JTdaVWbVnQ8vZHUVgV1WDemGpEWWMjsdepxpI2Ac5oPzve+7i2PnckdKv1mbmC6B6P0E pBuPLA7ge0CNuRjMTKxnaU7jg+Z/gR6WFWqJsKGHPfiSZOwm+ZTnR04dH9iMWMCYLm8Wh4qm15YA Pc5pxYvHvkyqQgmDcHsdpSIKKuyjeXOvdvZpHSugXOFTS69+5Oxx/Kn44NGo+JXQXHHbfTNc2QsT cTzPXFoOLorHB3NXl4lv9g3HXwdDXdoVp6cq4PtEMSiCwNiFBkWnoeS8T8q1ICySZ+DuBYZKWrhQ SxlicYFPY1YlJFFDveDD+gTMfHC3GHApOHeJ9y3zRgWlP0eaPPfssi6hYdSPMiIf6uNgquYJFhbJ VjeVlCAycpfTisUE/habnLM0+CsqdIpub/peHVQakxpIr18QpPCBKBsIOqhjzvxLfFGmK1YUa7Z2 QlCsm4dJAGkmQ6NsV1kpXQF6QVSnXxb2dP83eNDIHqj0fNoqqjPxdnPfamJZ5rkeVyl9IufGpaoz AHS/1LcgXqvVX1DmVsrGngb4zojfJry8mXkmBGK8rvLN/IadpKe0hUAjxV/h9JlGaVt81e3Ix/XH HW2VfmPkN5ZHBe3pudD7Tu6FLAORaLUecGeNCfbozN4ejlaFrGq6AgZLPQO/upDUrZBJDM0BzY2e AbVWhHhe7Qv0Pj6Pth4ae7W33wPxTYR7QmXQ/kBsJQ32VCSRrcEIbp22kh4NdJaxqDhXctUL6NpZ QXJzkHWq6R/Hdr5HLsz2+XdGVXzYUhNM/nKVkuxCDZdnBJwtGqc1jDlkC3W3h2/DUymXq/oNFf4H TcR1Ze6whqNezBcKKFclytnr2o/HLMR4MwSgHQ7YlpJePd1vWh0UkiJh0AkDwsJw0wv1jfpFlShN lNyPx66AoLE3FJduhG+ncY3qOxUlgTfHn5bWL7larcap8zXU0/pgHU6IV/zrkfutG6IY5TIbVYpu NwvkviqCamybkpNXbQwXItHN6k89wedsZl7Eh6yweIr1FQKurTA169/YMoZ/a96Mib0a0dtpzG9x rLr7Jp8cmhYL7Rxk8FLmHpw/VpRR2JvzhS6JduAxkD2EF4G8Z60rFTfwawjL+RIGo9ogcuEBexJV iEgkgLdTjV5O4ZZ1NL3t6jkvVh5MwwBTHzemxle9xg8wyGULGq9IfiIl9cpKymnDVIg+b0/wIpNs 9uAF4ZH6lD2tXRsmDeyHAyv4CvhyQyjV0saZfu1dPmj8syYl05b7JK6pkVTbaxwk09TRmNi36Lsk tQ68/EzJie8/3RzU11Mz2jhkX5ugkIzSMnIdS4emF7aoaVu7ybqJ5g+sOr3N3sAccGaW1e5kceeQ b4tPTYmL7zRN4s1mHRt7BXEy/2pUJ4TRrnLqHtCVWlR0atWaAxK/GBysyVCrvy751aru2snD3uUt xM/KmfTt1ZoNtW0/C8bpM9BnLKdMwn55bHuSxFzOBThrYorWvTMRl+xkIMHR06FBWnMpVik0fFf0 yEyksYXangqyNomb2RsqR+E9/eaZwRiFpgSKxoEoR+QOpJLLK8gf2/MbP60B/tEnDZPkCb3mmIXR bc145S7rnb8lmmzsqgAjZbBMA2OeOwAXQ99w9bGZPxlHicsCHFvLixJwB+gR4Vw0DLnze9gTTN3e MwiTa1LfJavFF1r9FiN841R0hNDA6G77Rl1R3aA8epQ8Zjww0y7QkAtoBTBbYshCubo9uA0q/b6Z wPTyVyQZC08V/AsSTbdFioJSzP4y7VHWLCmpNUtQqz021owHLzuce9AiEreW5H3fHRV1FhgwH4UZ km8bVRXp04C7uL+8EQtTjTgm0WCTvjO8WsiC1pP9mEB7gKQpH54hHpYDUPr04HeN6k0c7cdxKJ4W P8yBYVNWv2ewPeq5U9761tluG31XMKExHEYXTKzT4/mo9RTMEwWaexbYWJNjCBzsHQLdAAav5Mn7 cTZ2ymRFZNOQydoa5zH+JgPTGCgAwSQ6nwpJp0Sgb36ar3YZtz/ieryyOAPpvDu3l+grvBqvEE6y 2g/CMGtDkcx9fZA31YaPUkW9ou1qR7aRCaOQCiUsEq9Ye1j709csza0fTX5wHVj/Mhv4u0w7VHLa 4rwgefcdAvYdUtBNNozUbq4hIK+BjzJUtPzGZySide7hnz0GyySTYetP5MTS/rX4k0RLIIROKt9c g/4WY03y2qLMtZ/EN8ZnrSakFkT89r7Xk883YZHXshCY6n8UIO+9zzMvuJd66Li1biQplRrwQ6Ae Thpt6/5qt+OZ5kraR5zzv4Juk5yWhK9ldzTrKJtBMc0/gxk2FIVcpk2xBEvh0Vsb/XSRgvVs3t3m Bmgzb1WdJfWmDHqfgR2chtw0xwuNyOyx3DI7+BL0Wa21pJLst0rwNzb7fAXMtNnUfeW4gKABk5Xg DjNj8dRPW1irbzyUjVyJoQLXwrzyFcv+DbI8UjktVfpteQOXNzK6vVRw7CjhmWg1UPzUD2NmACTt AJGzvVJuUkoZgkXVlX4kOzxw/BtgAx0GKnMMJ2v+pUZRoUpaWZJLVku4+qN5tI2RrnNSkw0ttKnr GoP3t1YPxJ30XtJBimcHQjaLWCFWvZneQ5eyMHsTDr8y1JAzOITA/WM+G5mBtZw1XNWt4XAXsDRL EH6JX2g2ObwVhbU0/TLs3EU8mTgPsqXj2iivTg+GdktDDwTHvXOBHXQl0B4f2PkdWgVomaBuJlth ioF/+8myqnBRcDbxJQYCnI5FXwmTLq+8isZTHJsD8Tau+DRBXrMU+9G4lS6K1Vvp5sRMnsYHi73j MujoDjZJ28W9oZ08j/5bFNYNnsTouNBO1UpV+OGNOnAsod55SHnSkkVwhi+ZlbFqOyb5OYihna1Q krt5bT1Nix1vfxzBR70IFkXMSWI+bFeHBIXPALEClTSSJfGWNBxLjYUOZqswED4d8qj2eQgXMGU2 er75kYdl+lRKIvF84a4Iw6r8IexrCRp3rhGpM+Zj9K3ywBmaQcMN8Ql+LtPmaKO4cWK2sTQPQa4S B2zbIuaTWoxVg/UTi2aom863RmgecTtSUqBLxpHUFJxf0PvBAzSxPh3E9T7eo6tiG8GUNRuk6fQm 4IUwhviuZH4qVuBZYxXE2wVeZc/BRjoCiX1Xm8ustyKU/pR9fzqJymRgd27OABRKTgM8o319vwDU Mz3LD5qYLneu2B3hGRfOAJ4PIVbcFZe1vz2/HPbEJ2EMnLzPk1Q46zJAQJvdClqxxmBiU2g5aelp RyD87XOmd6gnP/V4kKmdP0uGLe7MwrPPdvieKxkQ29YcBEyOCzZS2ki5Gmft+bPE5/tpzuMdqfbb MmwQ5mvN0MF98HpE1TPbZSWvdOJnxdQS33gWSqLDdc7BQzqcKtSzLCg7F3j3yLMiS+nPhqJGKhH1 gTnIWtw6LT548/QkSyiaksR1MqkMqStb1IpK7dOmbCVnf0nnFG+uwRB31l4jVsQR0cYWqNpvowxV zEnfiLOhEMFSwDEA289M+Z3KB0vK5E4WIaJ/SGSGGGOVQEKMklh2RGe0chSEz6rWEc3EEvnUIhyw YE6o7TmThuUZCHHDVkdU47DahZr5RNQ9g61/sXoWlWK4gektAHWQ0XbSpHEVD/WUsrF5KOT7qYOs AI8o1rPd2nl3Yytqb7V1OAKEve2yHmrXrCuZwviNxQ7EX6vy92q6jAKxZPJ1H2IXYt58zLhomeGW nFvwC2VPmc76r22Y+aaJrXbepacY0tSmDVwW2kZfmZyFMZUYrG3WjCYph1pU9AFjrZsId3RTsCwT eCWg9XNC/Vee/EBjrQNECGzgDVDiyS0yPFBI6WRxWQUgonvm8Aq549RS50ySuLH7TYRDxUehFF4Y LtsN53ita320XyVEXD1kYL2G+lGkqZA1nzgiAcgUyvB6wU7gzChuX/WLxBqzRS5ZQEFnHK90KXzw XhGbxni/AGwxmDew7R6OjVDcdLqCTSe3eZP+EC+b7Ua1u8Dw7o+7vfIcfB7QLqWMHDwnPeKNY5C3 SY30mc7MgYOsD4e+AilcFOTciuqRxX3qUJQMBV3a6pVkOuO+RBcszGlc4931thbCCFz1jxmCLY2N IXGhrtv7pK5E8fSP05aVxbPt+rEdmbD71ik8boAap7NchngCv8RKMhSdkRy0TkgImyJLwTka7H0g 1tnDPCuJJGX5hZogsSvK5E+TeItEZj5yky4yLpWqGet9zzO1crQU5tpAVvFFyT7MYfI7mVGEj/t0 JXk4rsQWywEE3LJatWjr27wISkBqDccadW023yDq9NIuHX22xyvNr6/tUAg0LlegmXbzV5pYxbwQ JWlpXIJ1Q1/dN2AoG868mkzg8TOCiNZUDEXVo5pW1LxHFkhm+K7cekfXs53FBOr+O9k+QTAtm90v 207Ct+dKU9eLCZQqXHR+ISlPEW0FD4XRXW6yfaFhUQJ7hSAvZ8E0FiZX99xdeecwFJeHqLkIul3U ckt0pR7IiI0a65sEfev6XSIwBKy/NSuIjCPyuQAhAJhDrgTwsWm6Hpf4yi0ZicjM6YxgOdQqJn3B ZBnrpcpD4FLRt2ljKDqT9Oni161V03tV6lhbpnF5jIlMlbUrBgRiIDlRX0FxZX81JaFng1lS3L82 y9AgSSlIWJaWHEZ9rOHlR3GNRTDkqfFAVUAPw9+Zj94F90K3zExceP/OxwBXlHvu5koe3339xPOQ kKdOz8MSdZqvwmrfbzEtnVv84YXYekbv8dXRtETg8asdZFJ/c+gmAr6lqPPXGZc4l+/c8R8R5KBm ZaAmBivpew7Bm1lw/ZxCvrrJLnv32A0Imlhqhi+XXus7sUoPyqK3qs78FZX7wvbURu+InWgxK6Hz nlbzjsnZZtiG5+hVUyc7RUcbv2ADebJg4TRDbGlHV0R2ZOa0KLWbCjidnpJTrR6XzKVwFknkA4BQ trlCEq3DX9jGj35EyEPGs+AJTprvuPoX3MgsGEqy4VcTXjswaMl9PP6vhFf6F5cvFZyh/hXQFNI/ 1i0b3qBcIJWqd+9iCfKus00UZQ+bLZJWiNJ+F8EXYf6GRhNdGXEbw0GjIoUNEzqGGyqnmqFBhCu/ EGAiqwWBX3DeU64MJ97wPVuRkxJN4scoQIJhEBO5fxTf7M67rmWFv2fJMIt2dVkwjALGfjdk8P97 5XyZgdmHV4PQSLvq0Bzps7yCnLexBqj3U0QuEVnxn/8lAeYjQhgjee0N4SZng/xmY5zUPHQtwpHz d9GbzzXsIqwyFvQe+5SfiVvN2NqXGyVTwdHscWdUchCF8Htm1k7EngotYQv6wWH8M0GtoDQ6x6hA 6E5SvR9PKsfK1pV3sGWCnhVaJkcF5wEm31jOOhxQOwqR5IRxE0CjgcUl1dShqFXR0R4xGnbaFDVz k0Jas4MRJ2AeM0LO449E/vvixQZA1cZ4iPl5pihUtaYMXJjrrV4Z0+pIC0RWCZwBQuoAohdbVT/h Uj3RE93IzOek5UXBKo9qli8zCvVCS7gH6x+00uEtF7ZBMoibyZ7sJ4D6B0crGovy1r/DIMAPqFZi MCZ5ZZbU+M74OmttUqWqAxkHS/ysg9U47QRwf6zvquVLx/i6s1INlV2i2b3LXoxYtX34Nce9PAiG zCnDhA7wikdlB3d99Cp0/qjxtXI0VZP72Er1w9fGBzRPVdQAo7Q9ZVtosqYaUXdkvYE4SNiG2UIP XRjwR3gbNuMgMbT866jbDvrPrZPOAHqM74MYVOQRc2V99wfvz/JyMtOWrpn5ANZgwi/xUY4qu6Sd mOILAUJ0fpganGmrwnqJsjvsSgztxZ3RWrCHnBQHsIKFbQHhvJqhg7CBfq/eQk7T8uvtCFcAPfaA k34z2Wl/VLkafgpBJpRPCcaTG3s8Dw91a6EoOF8/wb+HRQ1U7feqoWMhHJ2OqJQpFaaFP3vjS/yt 6LlZKU3IPFm/hMaJ/J3KTCjA03lDAkm2zGECSo7AMlsS4uZOPNoP4qbjHsulrLouJeOFgbbMWvZ0 kC9FstRNZXcTV5aM1TVRVCpeghWbIJ2PLsQ7H42L4uQ9c8CVr3yNMVMxG/E72T2uBmJhxTHkk9x2 17jB4EOKJDCO1WVkV4XX1QAIKPDFOKnJZ2ljUjlVgVB9acoXzKsUy9D9pt2brJlEBKr1jWIBREsd BejIymjAsNyAgnhYnSmVvKfayGBaGpV7BZsaghq+Wgsoq05vPfaEO3mSfRNizCAIYdJszTfTbTv2 83pFVktObS5+s7vdg/l2/3NazIZd6GSBjUvpTYWOMh2taKGgFQKwBM8ct+z2NZcuSGuiw7WwreXB SOW9LQ0CkD9d9umYnbwG/6BBs+We0SKMyD+nCNUdNovf+c0hrMegs6nHbqfFOITp126tUga28iOQ DMG0z0S5WwOt9oXd4tPiKZ1UcUBf2+h/JI18M1oAOMrzVDyEtKmtMw5yw3wXC+MqeDWz3v/R8zRj Z2FNEp6/M78/pqBjLd33H4hvPAsIAelhBtetFCGZHJ9onnzQ3fgp1L6nwYWX8MmE71X9iCb7p+kH ARnAK29B/kLtrdsuaFEUYbHsFEqyKe+d6zJUuoWf6E+eSOdgwPRalgnwWTm5g43vvXaKyx4n6qQj snTtmXNJL8he/9Yz9KWuywxHHMQh+9ZKLFQPcdDo1tvU5h7JQcSrWTmBzObXBBFLzxT5vDe793J3 7DMomUkDvKh8ubaN0NyTsn62UNcCDdIHsV7wXUhInGa1rJjkewrMb6BW6RZGKJiz5Jlhg8cxz6oy doB4SL3HcvQhK4qDSFSzCtklZRf1ygP4Ysc3JoYkXr6+w5ygr6szJz6o8LOTaXA1QBlUZqLLn6D+ 7iKzVDaUDcU7U+UdC7k7WGSyaumuFIISgm2+GEAejNbeH7Y9d72IABPdOR9rlde8t+CLf5kHuzTN Mebbg16+LdfK0iAul5V0bYdMW8EnVm3sKoap9+fVq/7lNJOwVE9ygMEfkWw//2iji5o2Snf3zuZx 81ajP4hgzT98trQsbaQnUrgZ45UMycRi4eAi4QW12xdB2oMn7Vw2Uvz58EYk8zKEDfCWpDC4bb/x I6iZQL5d6KlAxMM8IDSVBH9IqFQjSZF8/vRH7utQHfs3ZeuzxBrcQfeRzSxtgzvr7Wg0MMQ2UKqT gePPE6prwWHOscIic6VQZbiHDWOAk2rI9ji0kEQjiLDWG3NjIuSjymRThy1pR2YTPfI5Y9dtgZa0 J03/4jNn3MYleOB0hf5Znqgk0g43gEwJsp0KunOokPDxEx3i8vSz2LLIrvYgIcBviOgDLeTpjFzJ 4QR7GfWbpUTjqP2YyXxxWrbX+DXultsWSzkMSkNM8YvRKGygzBuwovLM2k0qSNIjxklu68O5UpGO cCh4OgDIhpPuH2rUMim85ySytYEHnUCiuaTN6RUAAwL0SnOEv8n006Ge6OPSepCuyihKQrqpKJtc Xf3vPXs31VEI2SzgKdVRNsUBCSrWGT0TQQ8dct888gOPNRTT4GEmqA2ECUsIYC6ubKon4NjdIa9p shZjD5CnK2MXCSVsKp4bWCSFGfoWOdzS4uOdy/alcuatpGuORRJTeBsSvfYA+zz3+zSFk+3SuLPd FJMOmmz+1mrabmkDZH5LuPsygsbt8HnAHVdqBAfgXfvbRryodPasgf2wxwbtvYD/yjvBVIrzgrBi SW8ZYWFB1BsH5MBOF6uUVAXWLg3welneBQvsA1vU94YbOIK3nXTJETwFv1kr/gKD/rRoo6JDIvDz 99gOVlfgwqYhbbTOXBDnTyq3WYpg8ZS6qnt/KKta/6g9OEFFeyUl2oVeyU9NE5bLERFTGDj551VU Hke+w0cKmTtZ0d8pqr0hov3X/yFletfF8dSDzZg73GJPrWnV0c9gzMFWXWaz8qReVUdJensQZRW5 1Bukd9OtDCjWrFTidcCYZBdIVFxLVi8vLGorQ4nO0e/5RTFAiL/n4N+95tweHEp3uTfiVsUxRakn Qtbxl6mNHfVq7ch3v6m9gRVhxxK7LsVsCG8rjCLVmX/+DhfBCmd4PoZPA2nVhQ85GPBa8nBsrFp9 ndsc3KAP14jHYJj88hucS28k1Ty7B+DOYPHWWVKo7DGceovUBBWSTega9cqFwUqzPJGUTZKqsQrR VTAqZVi1pnXgguSLfyw3UjZ2+2Wq4vAoynCg1QZ7QDMud2VDHJ+E4LM1ImWMlVFzRkx9SKGaDIno Y4GoYza358yBvwLVT2HwtlKiE5WLViBEMMc6zbsATYhaRrmlc4y8sLNQ8WxZXDkG4y5+l+PRpA3V x1clptrEIeVA8cVqir36ttjMCmwE6mnXxL1DhBbsW++YzGGHvJ2m/lKJ+IXItlTE59Rzle3FAa6T lgvrQzM3hTQQOkL9mg3K4Gh9MifHiAB/OsUpZcjJh6okegFikHEMzmJuqJNzfs+UPiNj0+nLUApK ihb7wiVitn4a2sLq9vvG0l90pL88BObPHq6Uaru7BpKDsghTZqV6tE7u8BBxS27RWVItZAikq3nW yJjhaIekUXl4HU0zaFDEjB0XVX6w9gH/ybYSRP9FAMmSrDByeiiVP9AXmrapvx0KCfD6szF8rwz8 50SnYuCYBMUD0OoH/QA7Q+js/ZMURKEW424Y03t7M09r/thL3rxUW34Q1mb6OnmXOQgpr4mJfyqP fGoTnj6LSFgc/SLufAaF9ovBL7ML/McDKhh9Sk8TqCyxuMoRnZhCSKCfJuAlhKWjOPEsnuxO73l1 NkYA40u8KybWyWooW9iKlJOtTdZmsIt1DyxN6atYso/yr3QgEaoH9DAZOwlcIX7hab7Sm6WJZbuS Ntf4wQtVazyQf7JpKgeeVeFq6CF/KbPIuDxHX5ULeuAwOJUm5tKweXZSn7fpaI/0y/BVqeVZRzih UD5ePoN7qxqW4T7P8xfXYfseneQ/zHYjLzCKGbv9quI4E9cOkvuSFNHc+YxKxwPBPRzN8n97OvlL QCEThpI6nacu2xr926IMsywvbaVGSC2zRNrJUUzIkUwLv3xMCMduP5KCoKdPtWX5bmTsxk9aklxZ ArH/969HfobYdJVS0KjIMcOQAMlOtUvlQdMLVArAB2U3bAv8+mhI/OLke07C8LIeDDHQvUZREgtD dumFn2uYlrjMlqYuQ6rbjYVJ04rzZkuqdOUi95X37gH6hxlsbagdFlOWHbnADhA0FOCM8QjApLgt fDoPdbsxgBhmYkk1Jz+Q5YJ1neBc37x9EM/XRLguvE183c8YkWYzvhX5Jsr9JHgG23yLb5svzezv 1DSyrCN9e0zzZhlwxhnmAy/+cQo8RCFz4PzJ/f968xCbHoWwuzwxrXUgLiFlTzg/Ef6ak8rtFAE3 zz/GIAIG0hzlINDgJFseayFzyUvUOHEDaB42jow2GR/gusDA27CurYcfXe3gf+zun6tbZp22x3je +3DCkVcPQjjkhTSPgHYOOE1UI8l8md7UKUrXSymUtISPOzCKzuh2UANXc/ShxhhjKIZmMWKBjZfK eK43ngLzL+rnWst3Hc3PWA+FdPVXGBb9UI1EWehr+tBsHyBHt4fXdm/aogQp/305amooIGxQnR11 qeNr/rl6YnDV8kItCm72TchDrXr3HkQ19WY2VbvtpYQz0kX/d1E+SQ/zNl6wYZiG2s1UIJWTxqvr GgrmrSqE8NN7b5h2PyfZXQ9xQQKLyxDo/eFFFJFEdV/KoqFGIauxuhUH2/cYvrOlRO73urRKSGbd FMKMJjEfWr/1hN5aS7mlK+cmT7h/YqT41cFImiXNYwa4Oyb1pUHVds5bgYDucmUoi7BD4NKzzVum f2Rw/en5halCgeTDYLk+WBaRvLUvWthLCIUbQNczFMEDIGBEgCUXXgAOGCnlg7x8jmF7GIU/gxWc VgOdl6kUDyi6r/ZosqvGPQKJvNJTw6PZLUX7nO7fIDWzltR7XnBgjasXvQcI36O8+0Q3iJ7tNM+1 CW06WVoNm1O4CQTWgJk0ch8QzPv2OUeH9AtHx95urk0F3Af70mksWasNCx1Z/DkWe8Z9hqMsL91y W3SxY2oct4E+BpyTiO2TPr/HQwGBYFwAUZdxT2i5MeGD/DF3BauTL3lkEeDChvbYjAKMg1FRbpgc ry0YsWVGLmlayYjvrtK2q5PAmvb/GggERjk9KTRzPTxcU33KQFpUBP2mPuqPnliGGv68GA811LcS VGQ6I3xdzH5+vSSyqRuZmCRjnqmT8/OjReDhD3MzktqUCN3Q5Zwmrnc5zOisVohcOFsc0AIXETiT pcsBM8z6tH46+pjNADbMj9slY1S7xkttJKby6U6Fpta5pUih0PJsPO5CsAbzm+FcrzXY27RfEpgi WaFR/8GZdlDNMXeNgh4V4KwahaaaZyRMEMoQbuWqBql0euWwpEjzZbigxyNQBSeYVJ4AeAdvX3NP reBWvyzToQDzy2EK0mKm2jcj+yb2fJcq/MhdOvWYy9m2qU3yrdOC1XDZjOaJPuJmOB3V5h7vu7fY 9TMmxeubhhNi7PFGOFiI3YZFFrFcN/0SsdCt8IjgVlpHLP0jPJkuUHsgt6OY5goYtRbMFtw1psNi nrCyi/CrvCflazMCdiFozNaqRZXCSzrEg9nrZkm+UXSwTIHEch4GmZj+8CoNCh1Zop24RVNrrxwu tdZe15IbEFuowVt/4yA54bHmHaIFLzYRNfHGFt0bEnCfBhbD/BSOZo4mpjuG621DjZfDql6Gz7r/ tMIBA3b8F/AgOdxFCXW6xW0WiAyD16LerxhgqfGSgO8P3IuspFUdVY5W3LKAZjNcQ/LC9u/V/V3K tkHrPkJkuuZqQW3aUhbYDQVyeKGMojuIpSWNWKcUOt2VeE2MZVOwjDUte3Lx119+UeyKHbgVj81+ sZ4dOo4fK2oq3eNzqoZOfYJecDsEbhuA2wM6/KurJYqXdzryodzUoyyknuVOZi90ehjaurdS2t4a Kc+AJUDFTQv8YIc0q2CmxjV18/WOKvKOB3NDQwqUNOKidHov1i64opQ8cxx6MeFWmzz3SyxYrSe7 JZXfxFk3Lt03j5J9AgegMgLpR/JphChYuXwEWBhjqs9P9pbvrY+Kw0MGJupyaYKK4FNDGhJUNLur 9ezUJD9/jtoxs7K2BS9HnYI5BcrxerTe0DsBYsS81YOSmUjlibHAE5bU07P2m3bEKZ52bqF4sgwZ xaxFnTcSAu7zrBGp462VORsSkv6Pg/n1D+XdmbKcyL0ase0K9Jr8QYqZCR/Ffxca7GjxCfrQWr4H EYfpwkCuXFC9tfLayM5tSIUP+RGN24lPw901LO8GitvqwKJaXk86YdWtm8tqyXq/3fe8fgAoxlZ6 eMenoXnzx6FPKk+HjSfD3BvRYZXj0guZOtwO866LSL12qo2pmKcQHwULy1WhTyAV2M991fG+jg9Z lYb5So1RHFiT7SDW/vjZambSOP4rBQzEA0pAZGTFfKHRm9RLvEPPA9Sq2AnjCFqTjeLx77aEfCd/ l0oLp+VB8vGToU1XPufLZS6HUYrD1hs7SmOaPO4G7KlrNXY+s7WfZ92B85lxvN1U/IebuFanBERe WrNNv5qGcu5OEn1eVVP+wh6OqXmzVe2ekvpd+XiS8mawgN1AToUkzYo+RzL2n4LmsH7TIswqKuXq BK+kCBemg92VRQ5uqopfYnxbOB8J/NjexyPd5Kis/zVC/0WYQIYTNize8Z5/y3db28XnlRREX3z8 iXSwSyMaHLWb2/IIj1eykHirMm8gSo+1iRxe63dnDDBSQizqq/NgI2JRN4YlNRyFQywVbaInHRS+ VoDbWaqeixOHryQv/bAFa/cw1OVABV9cDgqQFLaBuQzCiBFz4L0xJx+qTnTlLBf4mqZue4Sa0wqb hPIRNoAq+EgIVq0hOqrH6AtfVgZ5UI+sYqMWVMTmo+hEnqY4+YTBfDJu+nIukBKs0zT7aa/RDb98 eLV6Ix1SfQJqv+F6iFgIWyMyBcS27ZP8ZvOvShTtwy25jz7qZ1Ch4knqCdk9Tdm/XfBZ6rFjNWiz R1+VKUcFL/xQAlxlxB1xRvSPK4e9K91OeB2PIqhbYE+J+l8ShSGffhhvtsGHb2Hwlac7FtG6NgFD 6cA5ET1wQfxuDtR7I+qIL4Mu2uhop5lpfz60FSnDU88j4whOqGQvnjWBSOc9VRSsald6YCQUQo3T gvDALSaNp2+b7ijIJv84CpOjg89x783lexcgzNDQLIx8aY/SjIHlefzGO34kOr6Zi8MMbcGtORp8 SzJyvGjshrrc3cRzWwu+I5wYhvg95axAsBEsNmom1z/PpzV3uh+c4+ong/GWwuiFqqsFXp43h82j y54lSsv0LK14O/UPFg+Lg3wZq5Z4Uw6keJRJMC2taB0A+WeMzZLfPU8anbzOWXd9JxFDuugQimQG ZAuC58nHOu8YjhBE5KcCNfLeVji5nDbBdHJWqniHk5NEriXDRLv8jcWFSGwgi3XjUtIgUxXwyjSq hSrYprlxtP5IlvEXkfn+rBtyeCN22QpKF6vxOaBfgTBdG7PTM61RlbKS3wRKcAyPmZ5p3wEKwkhq AhEdASs9OL5flsQopnQ+xFjY9ur9DLIk7dL2SKvA5Zsi9cnkrk1ebTG2Ziy5fL+iIB4rX5p8GwgV o3vFGZ7WELJbPAAeRBLOqsTwoXMn1FMbALa+I6u7c0f54D1jjuwA/RX2duNvz1eEVMywEAx9EzDp 7W2RK6HBDwCTMRm+DgJUh+3yCITncLKpX2zJN8ybF8Ff0lPCK1W4spK1sfQntXJ0xsAta/EBAOOH cS4WG7Mr7NSzbZXpnh0pMOgcSQ90XYm8RS/5rBmwWV6DujFsn7hMe6Jpe4dX5QgHGKp/Gf+WR2HO OOPmFmYM8jsHMfg3cOldxOZUVkxnsIya3UedDHo/Qbs+PApB/yR9i2AmMism8GvLJWmg3BcZiXvY fFh6VbbG+Km1ta30KWDjd3+b8x2963SrqmWn4wDL1N4Focz1HE8kI4btXvnt57FN57qVxRGx8s33 TeZmO0VyRv9HBrz5xa5Uqb03OeARPGxsvxLXbf2Ojxrjx0LdRAA4xm+hsh3zyo2nxFStP0vhS8Iq s4/5BosAzD34sgmwFDHV2ylqN44mU994e3bNJUge1c4vuY/d7vDILCdn4paJvK7xvoZR5dE9mljw sLhIkNceFpKNzOq9WzN2HyW82t/fCsgr7fyI131CMZim8jAhCnEuT5bUdYBVFkXxDFwDDLGy6VsM O4IytB79IjJ/kGWfuT8H3F/4dcRqvF5lp5GnIQ8QcNZxZv8N8pVJygpZIGCqn4VhIIAkCwhyDEnp KMSFzXMWgGPEBxDplTi9OArVKecVvimF4PKgQrts3iCDR64REWNFI+/u8UPggzJ6HSEBrQk14st3 tfS+KFMeeSoqjTnyvF63D1QNeaUfE/SaIJsiUxQvZq56i1RzZLHtGos9C6GHFnHIpWdLT8gWVX7R VbHZBMwvRxDBo8a/zq492FUD6c9VIM+3i4sPRMZ4I0gK7EM+TMmUGBjrH8y6ejvpLF+u/kNxEgAG F/GFjwgHkDGFu4gUssnOyQwuf6PjdejnwWLaHMHmOQMfS1/+t8nXknZxiaYBTvCI0plLOB6UV6of GQJxDOWnrbylp/1BHn9oKIV5qHBCT2sJ/S2QvE+va7btaAwH0wVISpNHdu9qNBw/pTA8SlePvOUF efSrhnRDyDOAmnKZmBqhRrE3CMhvSkufUZ3TdLuOiJq1tK9kBv4pTC2dslpcciRELeMSuwmhtlgn a7vsH9h+R2D5E4elC8FZ+HhsZYkGht5PZzl8DZCvXyE/EqiHO38fd+49QpaLifPiX14u++iZOnKP hnfRcGzdOFXvSOQA1zPGrBgN+A9N9UqE2SJwBR1yLunBKAKVb129XG0o8DTBfEM0l9SYaZAc3f0M UV9Tj1nPObwx95/bhJb3YBSKY0KJpikzIUJnS1zBBzdA/nFm+3p3watOgSStj++8jcnVElUdWjRu oKMAVA9w/Q20lGeqMX5UMvJkZgpfB8I+RXAQc9LPjeeMMihpCChJoz93l3BXbxL+0HjGeNHL3giw /CMyBjzkxgLm/6uQwCUV6fhDhxbWbmSiyxzBfmFmrWEwhAyJudT0ShvUUUvks/XVPw5bq0xBpVgr uLPUH84smoIknwnE06UK4kEzqGgZemORKiNxeBPfMyi+wq+CMJo9ONvZqwapY2Yibfg+OmJIhA5h vTwKiM2H685w/APF+R/JsE0Cmyk5JWCEDsyOViS2DhutDQ7DfQKuNAMTQ2kabW+ZXM3WR+ixRbtf wBzlbquDyfC1Dy1owLJszFgZRLYIJ24n2UJMpgOsicTUE7OaIWjoR/pLUQF/uPta3joqySJBl3/t ngREcumJFR12G6GCt+UHVeCLBAFXlI0V7vu7uaFF6n17PvMdjW/Hb5nN/H4W6HEEclTA7kQ9bgUy iCBZaPk7PCAI6t2q0A2zj/t8R3rXvugaoM0FniNsPrZiXE/CJ+j7Xs4aMQ/QkWDhA7UBnRtR5aqL 5io+QkFUZLzLAC8gtRdg4am4urvNy/jkUkXiKdoNfMOYzhqVElf3CQHV9uX45URgob4hKk6KkRBt ZYSjuX5qgaS0R4UVH4WqlcDOLhC+DkVYgJQVXfI8D3VVzPaLzj7DKV1kTSFr3LBg3vMljouk8qmA j6mCnYZv/Gy0JjsWRe0q4my4AuIw/3bI5Pb/AMv4WYt4x1Dcb7f8aUij5T8tbo11BiS4AGFkBzJD qb1lWIiaHRg0D3R95jyDQMH7IT+tJvjgdP070C1hR2isWQojarobK+iFD4EJMNfWR80NI6alANFk tkVkw0t8qEihyyWGtSMu5AuTTQOBb6PZBYfuQUlOfXiyAi6D7Ianixn6wQplWOWtbnTm7vzSRyn6 mCGe4fK1pS8xRQyJ1CgPmPkK6uzO21tkE/l7iVln26I8Fp/+NYnv251ikhl1Ipp0yFVm1RcpvAKB B0dFJ07ptJApSDcpCnPE527cJuHJWTVbNl243sWQxyqughjBy5vdeOIXdBd4UO3fDAiAcJrUkhQR Jc5MXmorpC468P5JMz1Jf1s/X83CMlGpp6Zmkv+JMdsVXmOIkcG28HkeiBpolttJ0etxAyGulkoz 0x2J6V0pJ9Ix2yPnLm1f8AC9Cn2qg92LCmr6IPgSpEfHjpCkiDcwmdYR1ssvTf32PAzSAko3MwFt +MrlZZKKzMLNdM98RC8FUzvd0Eucy4pvsbUxzghROvSJE1zA0rhHzy/T0BO+p+zrcnc6Nu+qq6/Q eltIUlgDVyPxX91B5HW1eYXGad86kQtx7ng5782Qfhh298CgsBJuRECGP5n0jCdZO4otKgdLb1KG nAwQkkvFncoiN8i+I0lYqq3ivrOrc0edwX3CKA0OLPnFaQ15VHsWKZTIDpcDUKg3+eNGiFE1zjgC YV0quChCIR5naSAY9exV9XULQv3jSv5TKy3VPGDrtNaqvwtAGCcmmB/Jf1Mkhj+pzHtzlrQbi8Ap 929Qp8+4UM+d1VHz6iLMGglSTVhJgfMMSXfbek/wwAayungTFZkzMzh6TWGsxkICZltLTMPS83PM Tk2fW7CQMpT8aH3zUnkh5asmYZR73ugdifhcpt7tR/XOshmVy4xY69e+dkDkJDRJrnxTf+MaqwQI Dl0bSNUy+BeO91SHDNh3BO7aIZ4hFqIslDC+NAJ9S9A9Eu3/JWL/dAsumrMbRU/hGcu3iEo9Cz4L XpawveUfDKIR9jx2uJB+QPWbwvueSs3aHjJa9GOHHQ8h72i1xYt47HNBUeO+GX6hj+EMDL+Z1aAz jH8eDU3noq8Mh+6M0L5vloOGQD5IFuPurwTrUZuSOLOJrzTE2GUU5qF4z20mJWL0iLLr7WZdx4Pl 6snLv77Q1MuHE2NYwQoDExyB0Vahd3haFztEZFI5CuEst3vzx4U6If2A6ySZKUw2bxYkW0Tw6dB4 Ktt8ppPwNwH9qGEq+M8OVd2WqrfDcLaZJbJO4nC8cNgC2DUZStOuLxB6fHDZeBHdF7OWhwXOR1Xu y0T7jb71t4sCWuFvkGzbu2lQhMJCpjqHXdjQ5MHLIzrXiogxYcy1dYoQs85+BFnspBzu7PZLNDfk shXSyZ20Dpz51GXBZFHLcu1NXOVu2q80RMOCECNltUkiXbXnaBXYSkc1nlXEZecjsIYGP1amT/Ov 6riSReiEkBnthwzRdFNxzhVbecGv+wpnFAHTAVGkKn6ROW5kuP6v1yLMnvcAEv8tzk81vjrDjEg1 8C4k9AFjI9TxqBqnVCgEDRq5cznhAN7GC/tZkyeqW21rVgesqoR7dc4pdDCWfDCkdHWWdGXxvyQf Ec0ZXddBxfBVyIAguVsXGBZhyxkQBDLLx71ZN//mKXwk/9vD2L94+HNpz2zH5OT/a4iH1GUdeFo5 +1xjyVE5xPcszM7v7KnyKoEy163npya3zOc0seN766XvBfb3AD3ScqbsKYo8rlShsZ7pIc2Pk8MY OL7QA44BywrMQhJCVcL++oSVz1Yp9LDKhTeSRheLQXh6LxkU4HxyikjXVFvl47v12oQBpsVfAa1W jOXQ+BLMRN8FeAqbnQ+BzxD6dr3FPTRwH/bABOrxreVzVby6mv6pkIbGsgC8XHH5nA2+Pag0ctAs V6K8yg4ec3Kx1v1TKNNOEDuNtsnFjSDeZaPztb++KXSMyFWm8Pu0RdwPXT5oLDkI0k5E3XnJ3s4s geZd/uN/3o2Nz6CKHhcXgAhui5+1699+CVOzWub/Y6CLwX+gkRyAwXX4y7RYclDZEXKc+MA9XQ7y NYe8A+j0t8Mknmvl/7sjmre+ZBWkE76a6O8TXTV4QmYI+X46+6C0bRrpp0qOk09kD3zwv6tSZUv2 VyBe8/Y+GlT7JIq6bm/CQDudJKNG+OfW0Xh9+UgsOlTimIosPwdihByjiTe7pMPRzYe5Kn8+Dqiy TKDoBfhPV8mrR/8U2J00Sy6qZ8X4G8d6INnweDqKYu44efBW5EcHm029kRK2aGR97sou7gP1+pgk Zh7mVoOdU4h+pIq3Qb7RoBjRXKJkB69hvU6dq6l7W1rkSrqMjbz5895u4/K+EMZrG1PDnoof/leL 0ChOi2uUMLYpEe13MbKks8b9FDfrbWAPTrvmYJmFLfOeMvOzZGwWRhbiLMbT50zVcOx4qvRh1XEL 3A6abeUx1rddQutVLd8Bbnqcu9KcSKJ8HaNK9JilziWUt7Ot7rIJz+bJU0gKos5eUbanFntMqPil WZTjdOPwTR/TJo5EaILcCKJuVEJLAFENdvf2EehZH6NZgCdsFTObSRMNMXiXDOlUbaTnAkFAEpgi DNDDuCLpAFCPAhYEcT2jlUxsEVi2OQ5Pm+z28uLRyaptaZrxLYNVlighOQDwb7XMqmp8pE7YscW5 a6Sa1Sr3duRl9OmORRanH8CUY2p/ro9+tjxDh69KchuEnLUgMd1jJ7v+S3S3Qcztdi75W8Xx7NUS bbUrIMqcB670Xyh6zQqWwCpYeJ7f7PCWZEkKgpXMQ5lq6i6oS5iKvI3sbgxJmHW+UKbwhhDW3U5y hZ6J5UW5jdZOmnqTSqFQrnXtKqL8R5ghFFKPq6VwZt5ldsd3wbqfEsQSU54xsve71nZFBL17OWYx eWAdrH9UcufOy0WgWxjsKzOgXGLIch8Eqr1qGrbmh1inWW8vljnHcJT9XQhkPZhkAAEMiDj/GA4q 81KFkqpF8fo4lVBpCm8abqEdpKcbkUkukxDovlt5UwpD6g9wAwoA1+Bjhx6OQS42iOgI6TM+Zqi6 DYerHVueP++lFCeL4Z+8550XTejJsMvJl5hXu4aVcdoJ9xEmK71x91gekVuvcz1z4MQ6CIpK+V05 /p7qwhcg+hR1NV3s7/bCVVKMJsLzjR8tIp71eFll2bCL77Mpw4/Bnb4tjMKbXa8tFkW5x0xMY8sa s+Ji3MPzDN4t06ZqYm4T6qW3i6UhseRekTD0dPIbtONw0lak4t3sR9DzVpKFiPqNZxCVZ6etsuj5 ftr8ZV180FcnV0iadjcM13QI+JOvE5BTT+UD5uuijAkv19LlFE3Zyh/U76LaAB7Xq4wWuJo3lhO2 lZehUXLQ4aS0a2trzKPhoi/KfqSZfqLD/q/NoipkJfOlC1FiSSqy4mLYgl543OA9qYgdXq0baNAL OBK2KJLTn/UMnTMO8aTHTaVSqXChmLZCY+4y6/8T1jahSZNdyAd04yh5ZDpERxA7je7j2sS5gsmq e3fwK3iPUk+G5AY0Hb3cWotz0JiQSo0imh6D96QxzvrsB22g7a4ZfGHpjhpbotlmrDEYkQe/3hG9 7xaVmYEWjnr9zeO0ml+/1zrPHvhdEd3eF6s4IMkBAbV7W1Knxa11BH9/fZvAS7eXlDJ2vAvQiJev I6ZKBkioTtZ8qnrTVHqd5VVMaLEOPETG0GlfA63aCJI/Iw5QgvIN4JB2z2D5LcASW3Q1IklSRPpG nXgjOAHu4/GAWifUftZRyYT/P0WUMTJQuc08qnDrD9oj1Q/l6YPyTI+DQmNiSuNlNhQHiTY+Ar4n hmgqe4EYXpoehyjrnR+qR/JWbipAAQ+aBj3KfjWnPCAQV1tvxY7iK01wLg8vNID+x1HcixEJwB0N yyR5IMZIJaaff7ZTd6hWXlRBNB6DXM6LVL9UbfLcH9Vv4rR07jfMmOkUwyn6JOgc8FZEKSj9qL6c hAIRn1uKFw7rh2kZjnbn+hxg04jorl57c5D30la8J5DAHvtiTK1JJ/JPxXc2H3denFWvLK38v2SQ W1/hxZ+xi6usULVifL2b7i4j0dauld4FGc3QT/WnjqDILZF33DeOG+sa1VPizyfYb7csQnBbe6lU IG0yLWwouqRgd3L/JbsU+fgaDmC3UJoJLXwmoay4L/RReCqFQWNXXVfEsm8NX7nExjoVLKKynEle UxXQYU2N2A8pBqtTrOvRfYbCLP+qVZOQnSxSog2Fvd/cA21Ki/qARmbYo/MzOJYbV85kvoCfx5jz NySjxDvHlIRH6pEmvaHjaJs5a3SLGK1cs6okAZ5bheToLlYwZ24y/oVmpHhfawa0QhbBGRwPL1Jf /ioAA2HYLZv3QSITBxLGjVy0A88mFAj+Bu/fWmfSCPJPNv5cX4PJrJ4GIR3CKsqauREdLzoMdC0L tqxR9mEUJgaFOWvsBIsOU1gwqIeZLTwZhvloehKRo++uOETCDi4p6ZPgDTom9EWOURR7m7dGkk/f GoA75uiqeN0mQUAHPE74sd7bs/EaseVxBzYmYqG5YwbepmR/pzXElNbkZ18pT7c77/8FWhANMZ+s nK/73lyDYtneG+20gyEVhFdR12sTJu/ebVYfXN2/ZFH8F1XHvcjTUtRuKEn8iJaXbmpeq1PBdEMm 49NusrOC80T2MygChycXDZTPeC9d3wbK4+SRi43yG+dYjlR3UL21coM70nAG54YBsisJPsIyR3Ps MO7L2xGXhR34qzChQ5K3nljTydw5pAex4RMGQJoc/jTOcWuI0OYFQyy8O3WnWzIsn6oLyQQqBN5I spP7OAPaZD8v1CwccLizlBS7cXSTMBfxrsjQuhaDwcX3HrS4mTRvDzuK7qC7UZfIklLu6u5snvu9 eIlP+M5R38lshZoxXzp1diy9iBdNN5gr3IqOGeaIOmP8Ql7vuyFjEiGJO2G4jF5Un+dhaV+Jbi4r byeQb1+zDvXLFcXaIwj2afl3w51Mg0+vr+MMXR1pRrowLC3mwjZAb2q545B9TvQlhVpnUmkT2GRQ UZn+7pPNW+lT0CxBQhCoycB2RxjAWsmApsmAQYXqw52CaQb8WK7x+RK73x145sX6YoEa1rZOzdsj sz5DekNawvbRDUt4a1WO8KGHfwGG7LE8EJnbjPQcoh8+YbA1HtOamCmN/KmWdccONyQm8BKy8oYP lE5FSyneWNUr4JS7JkVUM2JOw9/K/IZGUKt3aBuvzC5kjq1SllWlYR3YopIKIxfCWwrEqvtM/7r5 /SK3o0pPB5+sTkzS2Upx4v1ERnxaxGlcpdTZVNE7GvfXhP4V9SUU3U4W1MgA0Gy06XG6CO163qWX jg1OhWtbWtJ5F6DmaayLHD5gHqyknJzMLTLPMyrzthF+jY9wnkOERT5T0hkvhr6YjHDY5ejvBMoI TrGQkuhSrz+wR5miVQAo7kRtjTpNGwOOsL3DaNnSEIrUtwT/IvMBW/0OMd1BxlY8lx/jxWdnVvBu E4rIswTsJvfd3TADTn6Jczv6MjDbQqzlodZc19mX9v62ahMDkZj+Zume9odLVQfhL4bDSxsJqZAX l4MG2XXETVJ/W0n59CH4y+xonGZIbH4KArM9fOX3H4DTdr7XKybuiCXjIZMabZW0s3OToBS4Y1i4 dqP4CyZ6IsnRcIq220coKSRzM1bZ9lIeyvf6f1INfJSyYChEsQQb5VeV4b5QkUY3jO5L+OSaU8/y jISlDzRAkDRcA3bOV5PjuIcfj1i7v/xwykesC/BWHjseDhAcZsodyEK3mu8YfRRMslv1JVIIL+1U NjhpmCtqmSveIbfYXpQKkLUHMxhkVMhBDJQu5vxXViIwiQrcQATL3hTby40GmgESL6YfXCcWAzi+ yLloBMOkzeAKRlUYAzpDeKLOOxuq9HSzUGC6M57yxFdT/2uE9KSpNwfCtFr47C+ihF2IP3Bl/iVr ltSjlIzWnDcmvrMs4M1D0+nKoWUF2CHoWK/nq5nywUPqG2s1M/7MUBIl2fFXAKOEUGL9kugd6yU2 dfcwq4K3F+3RnNhNdqFMfAfm9c9M0Msd70ZE+vZnvaUv0hi5RBUDfBnBI5CXKCOqzGFtXrjQa+FB u9pK8FBgnHx0PWqurQGZKRkbyLv7fJ6WU/LpRJwztP8zauYN6MDsvyK0/yzREB6E1p7a0M3jlX1G H7tCQfnXjT009oAN6y45ElPTqqklJO3m464z75n+/sUweI4qVgy42PabWLZ3T2lWxFGDl3k4xOFN +xTKv5vTErBqbBLvMiE0T/utlFYSSrMXHrdDXf2VNiNOMBbOHe1IcGk1gwuIWEjPqctFR8Kclr/u dsZNY68GXOJsy9SW4FNDbrh8pKyQV2qmfrAmbw0r+7aRe58PBWp6aLmrnqKpnvMhQUXqx0bqIAr+ ejl+/H/tgUuAespILh5PO98ETWe5DeZEj1Eny0mOMit+pw9Wf4C0C+kKdNW+TolTJc/dZ69RVI16 dFBC4S+MDwH6teJc2LcE+GAfyvxl8PstHKssgbKhVTPUNwFSk2xz59tCULC37ENcH0RrGIIAFwB6 pvpYW5OTj+WVfvqVX7u5i63czuIfxzqX/BvwUjCcu04rRluQ0W/93+sY2J3ZfYedkDEMtNrWNOLC /umWiLjlBd5AKPgXjTAlzyxDOjUIcFA0/thcu1np1ZZKSPBwOSRquD5oLFE9e8HaKqhxv/bYkRqt C6cPPYJyYJ/GZ/Eqak3Dc5bHrbm4T5KNOe7zNrnvlowWoRLoTpCvGkvoEYpUwcXUJhoTFFhaDPU1 37P43vOdUS0Rns3Oel232CLTiR09z4dn8l3yYlHRhm405lDcevTkcAJHjE+SueO6I/d9PuY46Pvf ocGMYGVBPAQUepSowpVQe/z06/MzCTY4H4nUWKLrsKunXqNWUPDk2P4BpDYIgtOSNFI53U20F5ir zoM/46BxrPfiNRCk4SIBa8o/546RKoBblSCKe4UOCTnqjldNN3rTAaH7XkV9yxvSTWCnMEtwoNl9 sjwQKUNhv2zKwSTyeupLeTu9IkNj5/Vcs8lqgVICWAH3pfFxbeBDcLVYV7glxwAod6ZxW6nIgn63 +ujszybXwJcFFFuDyLTdnXKEOKyMnnmQW9sEhYtyEZocPhegIdFKoRCQy292Y4L7xI7J0gc3Skxm ghQQuhyBEHpOd2Q7uJNRi4jc2BMXcAHvhK0A0VEe1fzGRa7aKC58JWNbHxvEd1D9rlyY4A3j8ptT i00Y4LFgJVFBh5vosi7aY1WnLrmJU+OyhkvstkdLOPqNEFJdYLAchqfcLAWueiE327QAh1wdzwEt Dyn/F0WZJnhhdubS8YUDunRgtZ7u0RCVBAwvsIcVBeau4MAZyUtG3ITno4/SRvvjBGh3hpwLs3+J n9l54k8lH6UdgtXPcZwFK5EDuGK/h0wEFqfi/WE0Nx8u6fHx6eF9eqREjAV7RjW60OBhGucGz79Y bPjCox/KZmbMotNvmCGe3tR9dD1XcR3lCumOPyzGCxwGM87WWx/qtDdcKjnFlgP3bfDSOOOnLWBi X/4QfW41A5CpE+N1hAbsygn2TL7aZadtf1c4QKv7ApZ/aQ0j6uOIUtbc7OxPHmXty/g7ok6M3o8M 0tAb4jG/5VO/iDOdGakR6/ER47islFnBa5YD5eXG11bPpAmFXhDxwjYqKjxenjDuCvJFX2Q9N4aJ PC9zB4qJ8dRD0pqithWicA5Z2LttmQffyZ0WKTLg4mizqOe6FPaFuKmH/fLXLGZ9KmP/Tp3/1hbK bSN6/AEPMGuJtuM2dHFFAPqmhtpWG5ywNG7pKyB55Bd/yzmCeJjRvRMHIchrC2dkDsvK2wWo89Zv YtJuCkEG/B7y61oW4+VEpcf7d4w/R2kQyVNPVtjuvXTqFY5LgwN7oUYjiybqiX6xSzHDfqXxgeZL NDrin93+r3gBXUq1StjVheZydMFlSkMY39griw3jM6vSxVEXvUgXGbjo2WmqkNYReaUzm/IZ1tmI zXb75B1k05sbjxpE+2YpqvKpnmJB164x5IVN6BPnpfW9sdub0rLyRUnXIMRkAQwvxb0P6s49YYZZ 7lVRLkR/GjGa7t5KuXltDl7iRRC7ekI+xOX2tcTXXEcAzHU2FxIKEleQE7uC/5JIY1fWtM92KEQn sUQUad7HNC/kBVAejHk7bCUQ5UoFPSHLBcnsQv8eEX7hquJ5yGWQeLoEBT33MqaJtsJQr5nI92lS YRIkfhF3cHx91TC2ldNAkdSdehZ/OB+/Df7s1Arp+LHNCGUVnEwlCXFMaCWoJozBQjqB7/UBnwlE rV8wkJP2Jfk0VOj5PkR+oCgDGSF3AxqCmzoyOdEXgx0f9JB8ghy3dMzmcLDB3UVwoNNIOdI7U5Il IxBnoYFTumMmZgUlyiE32Ynn9KuKVo/Y55X0bTX2Whe1NsJztjS33f0/VXMSmbHrt6/AGDPGpZOq ixnYIXoDIQbWdtvLvM5Yz3DHKVY7clC2P2WWBTfrH2+AvZ2OhCTXu0uJrsnKDeUV5Z9zSulItKdn kzGEDGjT5n2dQ6BbuFrbFQcdJbCTLWuIHgKEUo0QmNbBs3OOnPrtFlBy6TnIO29ATaGgXvT6YfY9 VXQpiADv31GXU0HJweOnDQEq+q9XxDELreGDBj3U5sy7YSOWcqYu3H7UBRJQC3BA3+yvloQfallO 5Pdw+22noWtaYviUpwiJ7MyG9Hyr1vxRnmRue/CTfac4RMtgL6pxJPbBfnduug9YcBhD+SRgQ9fj UtkuVbbwcfen0tw4DPkKgJQnaIfXGm25NliYIx2LpD5iQM/R93tZWblrTcQT6BY9NBy7TMLgHEfV tsqCaiPsK1R0QD+P5Xw3U1tr7iMnmXwjnlHHx/AKeDIL65SWV503+m6qsIKtJkAXR2F32QbOaxTz 37VTxU0OSHjqtI8mKUUWqjt93NublPnZjd27mtVu8SYR3P3pSx//IA660kkIXOOR2GQ94YuTvRnu PCYbvUkivJQm4UDoWA61iGGRVrGl8xosnmAc4K3iI6so5jr4wXRDoNjSv9YiBMB15llnl+/wbMQF TAzCJcnTafBPfF+ni1dq3eGTVG+Ayn8vF2JCkjDfI1L5qLpB1PZBYUslYgRptFyZekTRRFpbG5G4 Kr1x/BUjn6psxvPdkIfa/7UIbjXoBh9Z3bmLyY4uLecHXZ6T+pt2dHfGQMO0nyVC4HgIQiKOH2z+ 9ZB2z6GLZ8XRGYHdhwVW86nlpgo6noOXC5re9j1TYWLQbin9PjEcXjjyrvyEemfjRljsCYGpiR59 h6poFMX4mfFUVh4pKkyPGdNIU+fuSdT4nAsYmjewbxXjLMZ75nZ5cMEtIIhTcyc/9e4jJuLzfdx7 biX/h4wSJRdU5/1utzXWD+MSW4yI0yN7Nj0uwUhsBGatAOVpJHjohMn1lMG3LJ3lTCRg3qit/E+W ioFWbEgI/ZtV73yTLryVJ/PjDjWaZbymJH0Rr76va0d35BZfSWWTyOrf9Z49SluO37bBW8Y8rhIM LBRuN8j3+g2E0hqYw+Y7aSqqQf5XDAES702rmIkOL22nodDRA7X1FjIr3KUkeg143QKOXz4bhfKe iRm6OwP8t2E4bZskcfwHGekaTf5BhszgMprE9+u5Sj8NOnnoTTvRKB9uBNwUdrY8hxueyOtgxLwj 530qf7q6TF2cRtUr3LqLkDa/nROZwIKQcvUS7EUll+DZr0QXpJjy1Pis5B1ysZApaofXft5oKryM 8dC8EKMgX9mxFfjUXy9FbPM8+6bSJivWXcJ2A2T8/hJd0xim2z5PYmyPkDA1j7k6E9F8VO1+j6wh qaCq8GfY4qGdh9jEMrzPNaF98PbWimQsAqpmpWVLg03CDbEjUjBuZwmlC9rBw0i5bm+dYfaS7Zxy 6eRibeCkCST5Z9jpy7PtEtipSqRQ0K6PaTWQ6l3tqykD/Wah8UYfqSV4n7tS1yiYNA70fRICRi6L Aezz/48QdzvH1F1vlKYUEcP8zAYB0IT/i2BOgXW/JWwRA/LhemnFsVzd9EFVKZJl62uH+EXpKao3 hS6S75SJ/Tj7usSuGNxvyKj0Cz1Ub5cZtGOqF6nh4TC703o1W/2bMyO21oQMYjJ45l+EGSo9Ks/R jsPxap/WN9CAla7jOBBz1jnYt8iFduh/e/sb2apou6BZEREiD9bpdQi5CjLQDJwoWpa0LNeql2Ml fqIqZKMA9Ly2yKrdWGIDJJi2lYDuLhVY6+4hHfJheGK0U7RGQrw+QSuDz/5t6kJKyd7P7QCKKoks 6PmjF9OeNmoyUyioSMD6wQtXVCvBEGJpgR+OoKNuvPdnoKWX2bdEF4qfB3GmrmIp0uWdJf7gkhYk +rDp98AtczvST60FkDTTUGCsmDM0y3XDDqv7uE/2h5eV249MoIkB0ZqzD5310Q13v4Rk94M9luH6 7aefuj23Wga+JgQf+fv/19SmhTTfvXAbgpftYBn3EG7mIZx7AcNULmZAcLbjbHYMoHAXw0ACaTDc gkNmP8E41OgQJ6dL0xg4JttG2w9bGGeRKITwsZO7O2BFb23ngeGaCl4KJClJq8rxhI4M7WI/8JUq 4JDZWmCfNyEbP9+MBRaynPh4r6S/S19cxQfvJ78qAv51KcYtwcVTVAodZUKPH4Goq1zV+wOxHpEi UJgnIq8J+7gfol/DVUChK0PsP8f1veguk6eIwwJ0TMITUg55OqW/gc88svy7UGfXdZR9H+u/XSmB ++904MiXxr44efbdSiah0L/v5tTzIXzm/Dtj5l1YtYzRfVCYDUhpMgh3FAD1v2F3H5d410JTu6yz HNmTDq0twdckOba3BI7QAsjGxp3ghkivjEqpGVPjXXEeW+j1nVTb2hKaNAahMf5q54eWIDHbN28S VW+s3OymuGF4ERYee2Rm5mdYRtdTdJkWgkMPFdzwDRruLkJnpwQzegCWCwfnI2UReQVrHp5ACajS t2ekVS73YPdXqid+VyN6iNXtYOJsV/PmX9Ny5YKEVNl0eBNUDR2YspZ8OoCUkQjLseARKsRoWb+A bVSsk5bK0MT0K/6GbAXmekA+1jXY9b/gG3dGLtmwV83hae6REYoOqjk+7X46ZXs8bnH1X5S+T+rE 5fL+/YWWIxnB6RTM0ynK9pgdWUSr/BEPtir6+3Gl+vV472xzhV80kSs5OcQHn896+JbEz2UVH9HV O94QmT4j17TKVVg/AyUugR7Z50jfcEj/2263MAHvUpQMmCHUrGegkhvQBYwm8pTyecaG0IgQnebS itxHzqxzfl5ti7J0XafwppipiRd5V2faUWUeQEVrAY0CWWRGJRGE9t1FSM4NBxtb+DADkLz9rmlj +0vKH9L9XLsmI6Z9WNQDJfG2NyZhOHvTjsk3JCisiM9hZLD36OoubUVFy6JQgnuK4B+uHq9l4Zcs C6XrRMPgeyudxIbmBYkj0wrc92GNkwFJ1xXzv3uJ3kU0FP2W3NSuOLepS13T3j8cQpQA91Ob541H Wj9HiEck5golNHzr7sp8LS83dNpa3uPM8HILPC17Fx+sLPAfbnnBy/zZAaZ2i/rW3/iHCeNYmi5I T48hMC8HpPVNCFN8cgBhiMLsegBfuwm7I/LtVG8nUOf3IWiprys4SSGuwmyetj+kqUz/DOUjIJzz ia7Oj34ORAYLP5EZyt3mH/VPtKyfwRALatdCauQruvTIpoc6jgjfdeM12hbTfRutyopUwuDfXbVb /HWvXyGx6dUPwv+I4oNkJpyR2tVfPoQdJMJSiCx72SkNz9/Z1LYTk+bXtYo/AIVC9h9ZpZXsTvDP 6+kVin34+UW8acKXNsPMn/shnbVUjQGIY+rtBp9syToaapyOEm0lig7M2Fddo3Kpphj4YKG281AO wivoUaLfHmGK1sDo7EcvU+Ig5VyX+0yVzCqLbHpXGBmPr4T03GFEf8TVYHIhudmm5nGfA+AuCC/p CmKJYuV3VdrkU/wQpFxGeOKfSB3fEBFNSl5Vc+yLr/kJ4v99QgCpA9ptIcBvmfM7RNn6fM86s5Is Loq7TX2COV0G2UsVeadOis6FJhXOv2pYFXTk/OAOAKmUFfUFAm6gnoDAYvgB9yfLFizm0fnhm8+/ C502HwR3qfpCXw+zGOkBv1J0ry66u56EzjpE6EmCaOQrQfaUqMJvEBVcRtYyvSScA3cZYTal8+OP yZ2n4pugcNlW5F3E/LjO+I72DZ6GeK4tgtRYdcDP1nhoFp4eb6YzV4aHBGVj/hY7EJy6+G7TupsY epkjOi8h7wJG73AZPwXhsZIVjFlv4BIyemEVBmFZFpZgLiiNJoeONqg6XmON3Vomfr9XxRt7+Oh+ R1mDCaiGX3k/H7hRcXVn5/zCZriabpJXVXl73eEadojXO4uhtAt8Bq19SiuXPDgYRpG6Kwgeyxwr bPJtSBOpHOb90T8KTVWLX13NflhSrF0lhSRoFpLfTy9LfpXR05s7geNNb1+V4CCBDKe1anG1njlf dkuH91KEPCogPBcA7F+ZOrKPAtzIwKenWRigBf7Gd7pwxdk8VkrQsBpS3dxtQLTfLDUCT5kQq/3e nbKTUcrq93D5b/CQo3wqjlqafTzkLIhK7PV72sQn+QTjNQHcZa9iLcCU/W3YGYvM9mbxODj3yASf MuIWzFviJn1Yu75aduXcbJmvNwbcuIdkkbCMuToNrOakd44WMSFu7MOt8Lb66G+mfxlkVt9klbd6 Z0tl7hFwaHxoE2HxfXzwV5MD/WbI9lmrOzNMhzrOfDgTzLY4shgXrrBsbJHUvSA+xPQIteq1x8C8 2+ijOAwGbjJHj55tx8GnQoOC16cWC7Rv5lQmBgPk5dInBHseGn+1S1WmyKo5wEUFDnouE8Gubgr2 CNnuwmls3uIkcBEzijzgUmArxFK+ya/e9Eh8Nb2JcIHTHpVXETkwvkpL9TEtpGETtls2/qcf3+40 4KCSShUlNa0/bsfjxZ01vAd12PhndBzXlifR+R3nYyJ3qJUiW66stTrAMFQ184jWSKzpHV9RuYer 7XEpMcxhIXadNv82TBroISuqYy9SIpGR/tnhIewD12bdxnlFbsA9ZwwTrx6i6OClIIk1YZfybBet Bd6gVg+xNxuVwD8XYKSKQ35bqWC9ujPJec0qwWJfPe37/iKOsk03YOSHKAnQciFSG0+S08w26SK0 tHGHo6PpqwAv3LG9k65X2M7qnVMHidaJVfGTmusp1j3IMc5TrUw9diHAjXqvLGrDyEQr7PXwT3AL AZKtypnCW1e023GCfvjJmOR10QZXdqooNx1RS/2UvOzRQtz2gVbF+2AU1WxMbODR/abXryqFzIDh 2F6k1qmiTlYZ5atJjfc50QaLJVdLJZebUFmxyeiNBHezApYRJ/uyrY48+Pvk4fworvd0+sSN603X eL3Q0k+k9aK5v4K6X/0HhX5+/2SVE6zxjgmJzBOW+NzRa6z8R3BVuk8uR1tAx2WRCGm6C0nRCcrs 5HMT3kZiVCQc3yxdreY+SZuBcq/EkOkgDo8qJB4r/VDZ70m7E5Ru9+E2AtvbqA/glXenu0ALYf5O rHSLZPKRNO9p3vIqEI2GOMcMuzBvWAX4LtBemdWXKLuBv5uSL/QULatoJb2OJXybbrrAkFHftuWF WesswDiGlKKspSLShZbX1P+PAt+FxJq8Wsa88NBTXkRSdxRgMJIoGOSUB/ELNceHaFwXM1LxWn4X x7LKqs+97tNWgreo8OPUOqw5+AhH7rHQ02jR3MIL0OZMVokbS/QhUdaqdmZed5yAjXKGKabN2SH/ BanB4BxRx14Ljv+WlRM41CnrurKkW1JGDxo/MMS/0sJ3uCRPcoqY8b6Ippky2r6szJQNQnj5lSs5 CGd1N/hAhqAXXD8peQa+fLWxxcytbT9bI4bsI4CUA7N3L97NKXVLyuNwNgBG8fiC2CFzi7PLPN0h TG1WV6rhINwbHQpMNsCYG1yJYytr/ojECBqDrUsNNipxb3urP7H15hSGNaEfTZFmt/g9LvLnEQxY 2iNMunz2QCuw7BCC8RTUZl7ZFFGWPgyJ+PAFs5EXq/oqIHjKjPZciCI7RgKVOcR/ToCUK/uQYCT6 KkPkvNs3Xu9z7vxSpyT6dHp8NtG+xkfFDUoQyeGUMSJUipfZdIdPI/57SvzprOweSXfJ5IIlDtMB sSLmc71YmJI3fOzSEe0QqTMY/3fMerHgP3qfXIRat21glRa2pCG5OCdiY0Y6/XXeuRavSUXjHRau ESZKzqjjDtosAYBv555wG7QodXbGt8p46aPU5WF00pZju0fKOjwhHJmYn1yNUCmJPwFCndNuXhmx 9TJCKliD560vwh36XNSsD9JsWYlWSdfEJ0kv1gkqJx7bApN5mZaEFZcGY+Ku61GiXxpO6L2FMHG5 Lruubf1xBAOajbsK2DYFxaGxqYwTejBBmxeKDiq5glj2sehWjlqCnxysX08tg653NYc3h2ndyGAl SPguRPrjMEfqhIUwfz0jZ1O3StiL+gXA0tRbcaP3blXvnXbB+Y7S7DpX+7gjoOMpsbfWWEMb4Fzv QmAF8LI7GDZpDem/7amWKNBrrO/Q3xrhOnQEDJauxCI3R0StHpiP9JUVMGxRPzkWzRwuSJW6hHkD LaQ+QouLTo7vqlDsUW2Vv6GwPehGjxZNUOg92s5xrdtB9M5GFCTTaoAV4LX1GvMt4p+faFF4rTA0 onfCzVMo2R2xuTbBoscGH3EB9H0IZvDpMbR6sgny3XaJ+rX77BjIPEQTYaKC1zdajkQl1KWoUrdO Ec2yXyz2BUkyPiwh0lZYcQlOR2NEhzGaWMvF5qxPYTQ8lKuYOYY8yoTen4Ru12bzo1CMj0AYUIl/ ZCFjwykpCQ2wvFmhjfqtK8WadIi1ftSQpZ1fYuu+oIQTcEYyXYJ0tUCV1R9Wl4Y0RDOwKWNPhyj0 BQSYCNQ1Tzbq3flH+KuzWGEESiPhxRLB6Y24JHri/zQ+YRvq+BwOo+RNWK6Vzwgt2s45JPAsxrC7 /iWHGtXfxTUmmNF6474R7Wbbu1asFvjACR6z97p0zHgZRVpp6hwlmifE5RRY8qe7idHKVp3w8U1n AeoUvB0InhL1xkJgfmP98bO+rdbmJ51As7rKG5ufWIuwgMfvzzWjV0Rpx9hnEVCgr/IItbswLPF+ FcBOMmTRdygeBIkVSVWgR20wLDrP5R24boNbVlwIUNVZRwNKSiSQtnPTn7Egz+OYeyrgb2lKf/Lp MYg9F2zrIDf9PxE9Nd7LzlhfhAgZ9+x1H/tVTrVX3vTRrJWO/UejmsHhjW2Eg7XTbgn1Gw24fAV+ Cm6olFjqHo2dEEfWFzzsSUHMkfYXquzbbhjd5MIdGbNwK5EaSFcEqO9tX3rebMFh4A/yGejsfxg1 U5xVtzi+JC/D6Ub8wzKdL5BnIz0J7UH+PGrDu85+laYEBHrYAwTHCVq9QLSB+/1ab/U/h9Uva1mw K0y2c4MR7sVjiTV6CWV36yS4YT9NCUpJBBOyW5lWB+77xr+0ZtlLX55GJX1+XU4NsHiZKSrtY26C lrcBxIlcOxYRWxs3gcXrN2LQzVA/jArRzlvS42z+oj3LehzXY8z1rUT3BPSYKQwrQEUos/GKl9cC u1hx6AbH0RV+5iXMkfXGHKm/V3Iuw9A8H4MTB8iTY3KK5Wmm63bzdDSsuicoNiDJffweNoUzkl8F tmLJVfr1pdoWn2GOMwySo57NilcMBKOsKXI1DDgdrXvDDKGd3x1tiCtZrAIJ6pjm8RrErmzKNdHJ Jx3EUUzK7cL+GzWLaTxss0dDyb3ZIlLFfa3fObGySPdfE76FIR840JVgktO72A2FPvb+CjsJGXoi 1vETDH9TNIroAk1HLESOuXgOnAQx4RJ3qZfEO6eAtO0A1O4dz0Lli/yocvTjsXLciJgLx963F4Mw k16wFbl7G/AHRl3/Xi8wGtFL76Osf4hwnpg7Bh5Bs1NaGNrXyDU2v0EY/ByumEPk3SllAXmLsV66 LLDKNO0uj4B0ENDgTPLOuGq36zQ+b4oGvH+8oY+iz+wqw8RlI3GPsf/ttSC6H3XdsNIXqLfnxAD/ HyrHG++np693q6/rxoUfT4t6qDexXd+jcabCVJbTqlf+WxsL7Zd5TOXcBFfw/phHtNJlb7TSS5GU aw0p8O2afPSQMGviBW7OJQbef/+r1bqE/bQ/NMQL7zu5D/4VbDeOOQbNAijT1EhVzNZmJMW03+8z tsO9XlC1+0y+liNTD2MUjylZzBS/w6kPImgCg80Qdv/xDOhadMjKuqxXHfARIkzVm4Fd1dVxNkKd UR6jfM1EMjzj59RlZNr9lDJCqHJ7AJ6rz1yDLOTIASe1xMMYEa5Dka6V13fhGjia7AYcXs7M3IjG OHMiOO5JWePRVUKA97qQdSElG9NWLnovPxZes8nzaZpneBeRjX/eVmrz3nLeD0vKOqQ/7gDJgMji +83iZj+SqYGOpjOxn+Qh8HQdaZHOGbTP+qY8gLcKcdYx6M46okWOw/Fz0TvVLxLbLWqOMk2ZLgLm Bp1rU80ffnGDE8yEDDQ11zCTaJEtoWhEjK7EC+Ibs863Fkzo75egeSPTKWRLfIvD/tZ9zOJ6ZZV1 A9jhWU4/Ne4+xYhiB/b/+bb1sXNxoRO6TzlPwz5XhHJtigSiei0+CWUmBqa+proozGy1ljhXwNtr 3ot1+BLhIdErEY4PqOBVuj2IQQ56CpKC0xrzGAUDfJ4U+fRamhkyhf+EGlzwC5tqXYb3IxD5vjNo MN2fqznEDXmD5tEBDbEjz9IKlp7qU9vcfjXHd6oGvSF7mciKh0PhCyFaRqhy6BzKYdhvK+MBb2wU AZCq1ro+GhcBB0CR7Cgkje/w3N9lS6532lPp1WQZ/NOHISl1JSMbHe+6yQ7L3Xu047kNgGHZd5eJ GQFsJ5vPGj7NDE6+3TLNqpLp48lT8A7vkSiCIkduuF7UO6PYXw4Pi9aCHDDud7wQlnIIW69Je0qp G2q3UXfOhO91DZyWkdPPOthKhLe7Fu+1cqFwQg52gQGnSerr7bG5JjjyTgAGgIAtcqwrMWeX+aSN SOpyeoJI4EDIy3S/qmkHvC8ycq0F+IWJV4s0p7vPR0vSKcNnLEQVfK6FKzfEMPkA9GN4raTl9KBD poASBzHjEWKoy1Y1XmtF18Hj458AFtDpiSqhD3N+s2aZ127IVNEIMVauHUSV9eiNGEsj98kGjpAT mcU3YDwu8Q9v+xslEMbD5uZp12UiG6ujGEWnLuN/2GWPDYdV95W6IVGRCblqM4fCtuZMgeZXIgqx X6gncP+hl67axprmQODTvrF1clFQc2uIPokmra9Je054NGaSEyLjB96t0+I9kX+geG645TnmT0dI xoCKuivGQ+Y2yoZC3VT9KM7cGrelgHwDrJUQfsXm84jI0skRj3eVM4Lri2xODIf7N+KfbFLbvVyw bX0XJeVubwangB6IJ1JNCgciu7ei6o6e2vj0qzGar9tQfEkrqRhI+y6WGKpDm+eJBlLSBSUU9baG XCm83jDCTW4UkwkTq5p1f/8T6Rf29HGq5zATyPEE/AJyXP6vrsoh0Hjy6NzTzEX5ia4H62mlGzcQ TrEbwqr764+CfXolYByUGQDSHY5pkOyds6b2A4tXXQa1Yfe6hwZA20qowHBqO2p3LMG8EAGUbDW2 1JrIYrH/T0RfZtTxLbtOTEj+6DQVme2W1abP4TFdQhNpSTH+ZC58OE1CQtfDtW9T9Mtp9o/dM/sR IR7Fid6zoD2cXrXxPj/VtTJ9E+38eJzlVyowKwQbaMPJnDOayNNHll9ENHAbIcPn0rayw4bJnfXv iPpcwsvDT1PemV5NY9Ds8zYHVVm67rhetHCHk2/PJA8tTEwSHGX/LUY+7kHMmy2r/w7C9d+IH0k4 L8dyMe2ugrBUXPUbromlJ2aphzPwPOZlCMTU6a9xK3yRRRMqTFL9GVW6zvdXDBQgZVtwPEMIzJHe N0o4eAKtXdZkmAIcK8F1G1D3kLkjiL6qLz1gQDc3MQYKDhdPMSYtV80PngKrnU6uPPvRIzasjz8H jwJyArpNCqDnE8ZhlVXFQTiknrBAJ0QCl9MjXOlYHPPwknAVF1GCB7R2twDOEd1M6v1XUbzFJ6up 2luEIhLvfnBbdQuqo525cKC0kEF8nk1h4n6R/MlsNuwN0FMenYUmn3vsvh5g8nwaAa6MlsmQZez+ k5eMn668wVvthMz84p9vqAwT7vvEJhJqinIZcjAMYlw9fbUb/XyNCcQ1N/J/3JftJzB1LJ8uI1Ed 5lvKCIkJc3WRxLxLAsibFY2NVvvpyvDelmJPIEo63BLGamMtrnbXTmRjH64brSxe19L2MLTU9cG/ 6FPzlNrp4nbmqQL3CLHmz7Q+2ShKD0dNwcBOhrNtfRFWhHoJgUANXTgoKulRJRz06JrrKQ4rOUmG fPdC5LLeRUAQxZwvvFz/15wZ1d1G1wawJT22kFY9z+eCvl9Vp0Rdwkk1iFZy4QHF/xOWkwFXp+6w cQ3TTGcgLhps0kfIxBRjdnzfF6C7NhvwQ1O9To0oTK6Yg4lbjPj4vQhWi29Mpkan8hjtrQq51XrS nB1PM2cs7cbEmo0tn3XHq7Qr+gjVkzybx37ZsiVyo/IVBS6ZPckvClOCIiBoxmfasJHpPI4SCJjj qydDiV2nGoJ+7FfyfmItoqLvg1W43tqJd7qbwgEaPl/pMB/swrEOPoTzjGSsqw94t7b0svSum4yF jJZswvIABEi1JVRolOqOBSrhc4arKOFmY8oMuDtQWQqFQtL8nunvtYEjUIBDKATzMkqGY3mKOxM8 XWowXWS1Ouqd/N+PLkL9UEJ+JLKkqkbYiSyj1b86bPMweiV7IAoVR3Xa/hb24PFUwzMvXqBb3krK /dTMzTwtyoVbOREQ7+EYOcCJJQNcDCZusplwGVw8Eh8Nrh9wtOIVX0Zx4GtPQCcBW0YWPJ6mhUs6 sd8P21q571IToc5uXCU1XPfBxc00GkSS99q4zQeVGQ9eKXQ9DRWkTivnkY1DQHhDqK60G8c2mJ4h G87vTbvxCLc4EJKGhbph+DX9zqE6q6+A++EAFfm7L7etGIq4zfmIa2z4gvOpsJVHuKKXZ3ZktHbZ pZehy25KpNVsphSW2hsxlT+Q8CrTTV+hcsRMvB19Qt0n+kJ/zEmD5IF9NROJmZxfjMzElcG6qlhx y8EKxatJiEDY2hQQ3UM1MaWPhAHnPmygCtH8ZrESQwxFlL0afC8Sn0TDeE+F3RWa1k4Q46PYQTON GnDgRu7foltbPI8joxa/+3ExZbtYKi9V4L5THZomMFCE5+4mnkKh/koF/3u2fkp4mj/BQh+sDM3b RDB3cZ0PyyVpYBv9Pukpb92qcdFqsafJDIK/9Y+1nWXVTaKYYIbNGmWPFMgHkFdyZkHX2votJ2TP IJ0KUdWM0Jsm9J2ITql8C5s86MSebHnCwgOV6HrYv2OLHIbZBczHCHTWeo9c3k+7IsyMsNqqPnqu B2GiYcp9gEQdkarJn8O5UPS1M123c7d5JmHRPZYRX6LGgxahgM8gApQ2S6Dt5hkAuLAhZN3YbxzK HzH4hzeIJnmXgXZfua2TuZ6967mBGv1kRY7NBBUsIibZM43N5jeI5FLyhcp1dpv90tysy9inKh1z oyE48/PySu8+Gn5jBKXwpPijI1W+S5O48++7xarCxrXeGBVef8atiIu23sBDVlwL1m1Z4VWdhVsE vd/vRT8vgOqqXzNqFhPE3/Cq/tX81YPht65QvtECpjk0r42dm1XHlEWrmTxrmPQBzobR9W5IJjrf JkHecUu95IIE45KNStVxB0MI0Tm3J0lzWxNB+2YurLRQRdORIkojceEiu4foZGiS1tfDTXRFDsmM m/o+vpL4dpM27DrZArWftbon8tkxlQxq9f2W6JaNkKXCJoE9VF14knD2uza8F48WmRRApS9cRJw7 QA9QUY/Q0qla5o6Cwi8Mw8t369QVLW0ACaXwzuZazV1xCSVLlI3zkVfQ+poLss4zuQxgCvYRu6GT TvLfwYu1ZcGnjFNm/3xA6qWXptoKVRg7kPrTitXLunpPU3gWcLyBnvEriH2kZbwCL+DPvYMvF9Cx Ot0rtWwt25dPVKo+W3dJN2lcEK4wagPzNgnMfVAPna/s/JLIX/H7OCLfjkPnOU3DZbFOphZ53Umh kUbetmqHvildxsgzAbmzl+/CHzZP5QxL51+i7rqACkfUrhnaqTyDdAra89Vik7yQw3aZR+xuCque jSq2AEY+sC8jG3mCR7cEqkxXHHKuIyyOt8kpTAg+KOpgzWGNdZw6E1X0+RuBdehC2+vMgYcxOvbK QJBipOkwEAbO1NNuhV3LyB4gdz1WNGR/Om9RMYXYKNVMp/65aatKG3QaHxl2ije7aVzNVfEJX+BK 1z07ss/i+Yh+hAec35K3IqMFlzBeTUu1zN7gV1ONzk0AOPt5QSyIVNFhc7M/WyUf4zr5oQa9zSu7 x/154JBBdqEQRaiAmGde1R06hvZVydFB5R0iRPH0toKeDkCcvEDwA/umtpNKiGJcrlAZbGGQ/NFP 9cQuTT2XVSOIk8AJb7Zo2EPiHaTzvB4VRQAEeEQ0OGDYkWNBbdlEx5dMJwUj0T9auU2JmkQmuY8M 52htn23umc5afbY3XRGN14T5SDJ708l9Xdw/a2KK+euB681C9ACu67SnABXRwxF0pVPeSNCT5oPE sXRRyixZ2PDTQJ3SOgM5ikQbvUd6gR7okSM4l4Rj11OQxo8fASue9F4W9SbPIQun/m9OgsSYOoKK SSZZF/MDT6rSwLWurLS4YLBOn0flqYekMZYhSL50yJxIurCgK5yy2sLDPaxwt16VYaM/EZSptMyx Qdxm3bsecjm6o3w+U5F3JAz4sLvL74JpeSjp6qOt8jXUvlhBLqyr+B/XFw69DpD13ACmchKAZ8sH NiSc3orAPgyJZHIVwJUvdnkMUCFwuPjVDOd+sZDANQjDb9VcvadYjJJbcDBAlTas1NDhDPZ8uHUc 0wZS5ilT6QpZ+fcRyOHg/rkb1c9yL6ycO+D8wFYjpOzmr/6PQ59sMVgRIudS1pVrJORWPOdnBadO hiJXXVrpcK3ahCmk4l7nsc4X9BRL2GdBiRnniocbuQ5SicUXxFWf3bp7BK8SXgCRjV1uhP780y3f urGdmJ/DlrYaYqyo+w/8ACyCQM9XLhpXQC8qyUrSdkp7O4ChLNw9f4nLoicX/shWq7DhY3kaDVU7 sBJP0XkFtoAvj8kn3g006uGzpskxq0B/KZeJiyBWrgFn99tEYDBPHLSJ9uFe/i147v9LXuOl5ZNc iAcBxG2HYGNbiThEGYyCBCO1VJFxIhscV6vc3gAridrY0hQ4CLbiuo4bB7NydZxTaKgVUQt8n7TG 5AGEh09QC3sY1EYLE1sMWeDZn2TeAyDcLvEdJREKrJxyQF6ImoRh3Ofj+3E0ld+rBuj9VwbbIGAn 4ui9TpH6Za8PhfGn0608HAQPiR0LH3pxo+3amEWOUYMsd2v/5NZvy4hQ1y5kvcBw2ATG9oJSSdCR 2y/r/JTgExqOVzc2Hcud0SBlcWQ5zdmYWPPm/DvNS9vjX2vomk/4aP5DNqsI116Hl5CGr4V5T/KN tQnORm9VUh0MUhVWgkFGxhifSSFAvfLrHN0R35WzE0686V4WD6Hvg0l7x/7EgQGD8Vi7T02cGTM/ +Oc6lzXvLy5Vu3S1AkHAPJkL0T5NDkdyZcL75Jcenmx+9eN0omTLsdIhzdk3X6ibu1L3fk/WHQui dO+LyxrXd30Tkn2hoWkAgftVUpLwoA0EUvpRc2CVhQ/FkVmyRPQuj0NCDsmzhsR2PunpRXOHpoPt XeKJ5Ci/6YVqqrXsbPNifJoJpDbiEtrid7nbZj0xS9vfXbSwwIkHh8VSKhaB4eUotf/jP2C9eyjT /E96hJkOqy922Fu2U8/s7z0ZMLlccR9R5QVHMfKyoIDPIwrtAVaIyAr7ASSkEhwZ2WnFbXovONFp RdtKXfbCzILvx/pd3ArDw0Zl6gs4p7he8bq+Ayq1ZVMjHCJ9sEYSZi3BYPuGiOf+AG8xXNO6bu6e rzygVsBKl2zgmOnsZMjcrdVTnJeNE63PPtVhJvkaZSq7yg0uexWK3U17WlSGeXilmw4wGL44yT02 yWZXPBzKmYecfhlFV/UmDmRoQRujWYWhkJR7Suh5WaIxj4cU0AFBvM+vfukt0dgslQUXL7JwgALz jsEuVtLMmpWt0gOzNZUltwZx8RQI4mdlSWmSBoFJiRxfCRP7K9gPRbkjVV88jI1krpAVlznpQJN3 IFk1hTsyzmJxrM/YlYK0Vpb/bKmARyy+a5uM8FM3g28Kr95qDP0RI3o6slORd6aAliKld5vzAG+i ntyNPYSdDB7wWd/xZP04wNJibyHOvzfeMFqTo028jdBnDsCyQuqMoJyKrUJF1VNLjiSdYx1LlrnS Jk/X84y524EbA93UPhtu69Q2UTyfSS1RhKk/wNUBkNhh9rpSfS3D3obghderlRH2sKuVci1SCNmT SvEDbfYNoKC2/oYsf+vnxY9gmlC30+PuX3FCazxRYmdqjHMURaSzTjjOgPZAmCidcA0nkhoYR0jg q7M/wREUh8ap/zvkW0i01fHbs8/CaFi+jOXE9YGAJuHzR2aiYuJN2evVn7xWlECXLDszAoCy7fei +wd/xVSVuNnO/Dez9OpYJYhgCLMkCoM9t1M5/b4BGKhihwPEcEhIRNQ3ctQGsgb6W71i2KizkO0z cXsZDdsNO5d0sBaj1MVbH55T3JW62W0Chc2UuM6S/MwuzZfxQ0JQKPN9DT6/9tTGpkVovxF2hEUc 6x//MSmXuRqxgcjX7Qr3oVDX8aRVtqHhTtp9pMGGf/0nL/H6YuUf53txuU643e7dRjl8rZlswU7O L59QblQKBDIJzHFRX/TF2C4348BZsYwTdct+gGzgxMLobLq2n3TBMfThI0iHnylyF2j8q/PB1Bx3 1yBQrX5G7WeexnltruDUS+gvVdrgXbELvX/Zwg+lhySk3SPMDGyjzTTY8yDKdZBMJRVQ7AZA7Ozx 8xKZpMfKrA0J5eCYq4ElwHE738kIfoIeemBZgtd2VvvcNVssUreM4K0CgKVGtQO4COwiEL468ppg qYZk1j03P6g/LJmrYvCryHqwuSJekzL83qMPb29owrX+vD4IbVqOb9Qou+kMFI/kJTt6tqvc7JTC W5Eco7FcK3ywVLVuGJ3lDGabfPevT+TEAutZeCsD/L4WvLOVf22llYnINvSSe25s7HbgapjRmA9j 7Qa4canpXGl3uJ+SUgHQT03jiU8W958zPfUplzp4kZhWksC/TA7sdRGNfyib2MuxEsO1pRSNzV3/ kiphuxOCMS4+vLzzlhnmJHQ5Lmi3y0wsjP0NIpz4Blfwsxr3iBcWFyK1GX4cMV+LB8SxmgXBI3FT XS2oXS3/WkJOo3ArT5+5ajvd5tDMtlX6zJhJhDejyRJzKReCwnTLrmh2M4qhHV3z6adIY9Asw1hL w+9clWKVwanlQoQYxc4JA9Tor4+a3VRssz8CXKZKVtU4zZTuHlE755KyhEAimD9MwRt5ciymB1w6 vD1+hAYm9/UO8cz4siy1AR3JuOQeSNDpPkao8g+rWf6Qba9GlTNkbNOOgvbArpYkSkucNyACfLAq J3Z8D1Y2AuhmreE25alJdsJiHRtciEFrbL4oc8zqF/mancz2RfYqpVXGCzo0zqmULuS2k/6GpagN UQwcA4NFuiSObyYUsU/vjbRSgp8b2+Bo/ITyxfZDO5xUx2ijl59DvUl04EMEsas4jsyTxyJezdPZ MZOUM7UkSDY77fz7YQdlvdfjEoU7QnA3BIK6Rt992KgjKkejajuJ+bg5ou7AUqxalZb9n691BFLX si9GbeeiZaAjfGmyiMIx1HPmtOm+w/4CP2GXEZyFk2ehG/WYWjiRce4ovK4Hyf8ja8La858EBxq1 mQZ8emFwL8H0xvy2QF8kk7x2e44bL68A8hRwvXYejOlLoocT5Rxxdslr2gZ6Il1vfR7T4dAK5mUB 5UrFOqbwbteH+8IxXv8H9mNLF9JdD+PyTN7HcBbu5wIP2sRsentxPHe3X/f6GT3hyXwe/NfcaO3m sI6Ajo2rJENr/cClMOCnRnyRiPfBZAKHv5j+b6jftUnuMeoiI0C24QX69gg1lGTjpGItcyTU7IXm d/KSdAmhjJpEKkV6zXgiQuZpm3E3RB38jQctoLF0ZOaVGM/ZeITfuLocxN47o60z7RWkS+shBrhT CQb74sEX/mG17rpWPFnCXhQQ5vAhtjRN418PcJYW0vJQ3ZLPTdK4Ev05NxG0u01BXvVwWMpxd5N+ VoGBBw4GLySXcZNdc9p/LSTCkUsK1PN2PAGt6iIjNWqy06xaY/R9iY+SmCgYTio3My6RxQNOB5pz tUN7iE+flu6GxLkW+ICrKUsbuJBrTns77TMbHF7VFvif5zZRQi2jquQt0y7tYTisLOg6oE8hTTTP MWJK5tkZRch/EWD4BboigPp+nhDtvRmaYQYh1X/LimhVkzlgfKnfRBgfB8Jv/nf0HsnlxwMw4ZGJ Wa7cZEYjxG0CoFD6Ig8gr1fLCR+OiIuydLhTBoCNODpIiMR2rTUhFaD2K3N0z+iqaFKBGo3P/dyD Fzgwj112fUdGXE+bW24zsTn7kIA+mDCKpkS9JDsL8GD+FljrFqJy/KX6RBHMhVFb+MTVSvUHasoW emHQly6WCFK7rTNRKy16G9YjRYEJhCG+EyHRvdoXzkUQaME0ZmMt6TiPGWfRs+9hH1CX0h/D01lh bmDKdCbuoz81eqwD+v1+gG8mTauQa6uQHqnHr8hYhYAiURcfu5ieYs60P+Ch6cpn4mz2WY8ZkC1c 6O+Rr/L2o90RFmuyp93/FKUF/fFk4uY7eMbd+uwMvjq8BfChiiR2e3suoT6pjS1LsAVqtXogRxmI BjgsxVPfqiplbAJ1JYT5bDBlI7LpJzWEQLzbdHiLVx2zRE9Blef7MAMcsPy9DqQo72fVrNdlUFCC uHfOqIY7FDYrF9IWZazkPOVSwoyUxqz44ankgXQBl3mayGyYXttkiSUj6Gw1mfcAcc9t+vdLz1Sm yQ45IFqw1ntMgtawdV6rNQoa29Ejd3dkGV9c2liFh27E7o9lxBZ38CJ5MJBOZVOliIcqrzNw7bWN BcBwKZ98Dw+2piVwPWVsH+szmHtcF/lePpzJ1MlL0rv3/S+Qml1r3SXM8cBXuNszMbrJitVKlgTC BKjdZseJzfxj6Z6RY8GYbFPa03Rc1Mg+ckhinCAGwfTdaihzkPS37kyCtFrkuf7QZrUSUkaS5ky7 ZjTdeec6tQYZoRRD8tqbB5eXS965sONX0+6KO/r2V3VL/yanWn/7ajgKdZixxt1UnVJJTyXz7JEa UMfZany23glYC9TakvoX5ixgYznzxHJMEAVBTdq917jrf+X/W1pMnVbWC4H0nBMKfK/4y01ancX5 EPefoBbCBTp6/WPD3dXQsLP9UFh7LbCDeVMD4us5DbKpEm9UFCOMWnhbKYjp3E3870MW3siiOM0m T72CvVObRhxo3EuEVPuPzvf8zdJPlE+xB2TJibzy0+6djGcRQLlG7wjF+yYWp7p/2MJ/J+xw5ygL OltfWjoyJxywUp/2Nwv7ALGGAmlOSP0fVtawXSYaAPMtfE04R8xel5J7KGdaSTJXw4u4tQNDwWoy H1qSLXk7OCPbjxW9muixh6XLOwqQXfDY20SE2QhEgWUQgsvjLuxCUGmpZ0GKsHEEdxlMcNpCdHEi PD6GPcwOQE/UBmb02GDhKvpb3zXx97g5SygXal3T2+5tqFjZrKtqwAUym91TmVVgsFVVPxKrqnX2 l0G/tCpVD0n15XPueQhe70rPQDEaqayorfN2synggp+IDu44XeeePtcXOgcNrWzoq7wCon5p7SXm IYkAGRt6U6XKHfI4dVg4iv1Tf6TIW/bHqlIj0F+VbTsl80syPDBvD/qg6HC+J2PAPe1x2rxjj4zV K1jERtz+xEC2cWNrJufyU+4RjF1IT4jn69U2Br2RGezEh1nizBX9X1PIigBHXMiqmGo8dZsJ1iU9 YPBfgZQgxSA2tHZZooUvG/11f8uqeHgcDwQA58faGjzTnS+/UjBvQ2TNWhD62/DcQf9BLX3mr9Xe MrYWyZs4o4qKVGd6PPhHnSMkFbfec7DhFHS8OaoE8Lo4eCv4dDN0j4JEv9uGsttvmkbv7nTg29AD uRkHKsYyEUESkrOyH/n09q3tUsjJFz4HT47w5MiAEojDzBR0wZbs7V0W+6jrKqh+GLCk2e9w8wHJ LCOGvMhw1golRJ3GqI7J1Qm0P+JVMuMtt2n65CzFbMtPDADtT8qU0F4hS0JYt62PX5zB4in3A/lQ bOnFU8Uoan4RH4Dvmw8fjavN60r5vx+tbgfPAm7itlOUvr6OoKnZVFGoTiR97krmWN2aYQRjYHox YyuasbUVshqkSk4qEMAG2Cj8slFE7QCzoilaYbAP/R0sUrQQ80F1u/Pb2VoL/EF6N48gzqImCogj nPTXuR+kkdP2/J1usuVQSBhYY43PURWNrvWJbyHH1D5GefpWm6GGERkPMO3Cs2G8mRSOvlZyTwQp 9qCjsd6VAp/g66WiCM9neKF40uy6D5BwJ4LtUmbeTz42qTWQNJDIQkbxHADNn/FimH8h74yfo8q2 omH4q9wETVUWifKMKmSD+JAdkpif0ZH3lHOwnHZtbJvw8kVSJiGmEXl0+j3QVa82hfyA86QR0idh YYlqgRIWcvsEIBs9U0xfNHyM5pE/gHxPWDGD9Fypc8K6Rvg2BuX/qLfoJhBJsqQ1+EetcjxazvKo PkMeYuB99DYnA0awjGVSrDleRxHUzIGWPc59BLQWZ1BI15uKBHCTeXzMyvMcbZmYYgVvPfckmrGr p777r6bWnkr8+lD/FqQ2uyhbVI4xMw3aGUJ9bplo023MuwYxg2qDnKJ5ID4gd5RVN7h9+bymSSUe DISZXnfCtTaI2zn96z+Kml6dCFaQKveXsW61vIHOlVByXO2k4AGs9Kh7cF8UVhhFPuHT3KkrmjZp FW7V3sO7ub10yhD7VAY4Ds3uENDSvTg09LawZRIIvtdPw5qqsGdxVKPXpszOhyeXGjL0K0Lkbsxq 0J96qjLeeOo/RHRBkV8ywZtcH+++pbLZPvrD6Iqf/sQAZPWvoZH74apXY3SrXMIYYTV0PCWttv4y tfCzDvRKTmJqnRR1c1gex55Zur74UcSKCHFhyLaTNsn9ItcQicadGIgTLpnj5MV4bEHFxnvOEA+Y AO7gP1S/jtdS1/WCitBgeD6dOBEvW4WsVf3mDGCORRRZMQFrgRSW05Vwo1IfK5GFPWw7uFejmM3q MJtI82+EL3xcbsGqSc4k03j6WAQEFyomw5uz/T8YuP1WHBUggnqJ/kElY/y4TRsQezWUqhLCEaU9 iLDPnbPegf/yzXVdklPehs+D1tdLMwlMm9PPG98eDCNxmxvddW5HB1LhOohs1ckk4LAWcZ5AXAre guERZXSFqBL5t1ECkp9Oicuj2DAcmUve4SrthViLMMtpInYv6wqMQe3Gza89vi4pM//wN9tMNrB5 7x3dvx9RK6LT/rPZJ7im3vnjtTwk6+q2ijHN0o9j8BHgXv89Lw7kLeECPIwgtS4HBh/wHInxZS3r mouyBu7VDV2ZR0WdVXOgr2/Ob+zIvKjCCbZfhPJQUVa4HWVwgcAByzb1xduOpM0rX2+4pcZT/uZr oxkJYYzuGfdGOENeMo7I5AN9M7sy6jGk28SMV5Nvurx218TJzguE9U3dU5u8SLekaH0QmCOwez19 vEzmHKPnuY9zh1KcCV1BwlvyJ+yjcjURyzFJv+EMEeQaCzYfKUJzXLTh5m68vCxMiJWVh/uR2xr/ ulagkeQHc3FyrI23TQcyZRlXWVLhjVSS0Kv3a1fhck4yN6NCiYnDmejEG8o5wdrkkL5bF3JhLvPl O+/KIDR6He1IQcyYAJU2Pw0Eq/q3pT613UbKnb1llsuJBKBiHABeA7kDWmSYCo+qiRoGucqBU7X/ 3etPDFr2FFi1H/uHe1Gh+EsVKzxDb9tYgcAOmCSlq62eQ2hIox64WckVrCqyqAt7nGFETt3tnJg7 G1YpeE06hBrWohVc1QFDB1EHb+GrJ2oNs23mDjBPY0hXK1t4xQ4xTWrc5qUvpD6tcPE0B0/uuL0D mi1wTq/Kl8adW/bnijCsgF5BhibPZDVCsJdnMK4ucqKD2DkkGNR8vBWONv7zU8kJrCboKPoaTUGO dcrcKueldkJq5TtMEkBHxTUqI1AP+/uG8RN7wUsiyjifPs5U+UcoKgVEpnXE5gUhTY4ydcD0xtUk wn+0TY4uhkFr1kw1yUaiDeE98D8N5eEgZUz22UWbMUW+Oi1AAKPhj7TIsqITzKycX46fLegSyw75 NuXOf8i80JoqBC3b6p15VeCswzHWx5y+AtE2O1PLUN9RCZ/qRlTl34Um5tnOQwlBDqhS721JTFvR lAW0agEnBYTCnHOvZ/1rxbkSgOy7PSd8S6TaaCfzlXyr1dx9/+8zVqbXbGNARGlPlFYlw6+tCIH2 FpU62gOJkt+23x1+yKnMMrWJ0B6dRv3nR2mc1H9GvCTyOnUyZlSbXr02i2ezpULyF2myPuQ3n30B B+cYfViGKEO0r7H8aQy0i4gqAMGpJqtFGLaU8GFlprKLS+YR5qK2aoJpHxtYG6ctrfd1Qva4L1p7 4DfHfxVr0ePAAnJ3wdUr6ZAIvdLWciLAmZHnR6g7oc2Y09R5oHTFcq7AFdX+iEmntC+JwvonWE0Y 5tUHuyeVUaUBlvddiOJ83d7UVhyS/7Jm1gSVY6b6sUPZhLRioQ+nUQoTDr8Z2G4+muKVtY5s4GIN ERvky9UyH6MXg291mmmjdZyfTp5oWoA5jYizUQ5TG3SzG1k0uLxlPaTeEFhyHYe9u2mfWqfPcuFw Jox/13IWfB3qVwIBdXqXcQl+3Z6DnjRX1512WZGSHM9SabyF9P9K3HaQ2+lS1PA7UESC1gRqvANV 8xOB/dwF5oitikxpjVtvP9CdjctO+XPvv1ZONJS8zLVQKOpXVAAMxn0E02/KURQH5VBM0j1S9qzw yHc3Su5OxnW3jFMqoOa9G7qhjbMwXBccRddSTUUp84P1m6aRKXS9FUcRjBWhc9ztxJq+mH+/7kM+ Mbp7WlRpMprkU6TQmrg35FrumZhNf4qSa0tUo9TDMPlSEATeI0ZYOY1yo2G4o3y7IQlHOUc0oN2U aRVfJYtmWx894gGTOipg1qyvI20j8SscDkKvyrIhkc/9QnrHLxoW7exOGkHJ9st9JBNNykfXn+/Z 6L7L/raWTPMU6g8JF6Q8dH1yt+VWOhlerfsQmm+Ww8P1tzqz72E9iNTnZCWfd7stkMUWyv828okp pzjEJ6O8qRdR6vvlQLurG17FVBjYAwnZsFZFFAsVpAi9xrs1229l5KediXJjCB3HalVyFGYijTAG UfqqpN7OL7kddX2HY90OOCJ5w0tZ6OOlM9WpP3hTShod5utu44FJrV9lgqnSqcpBs20VXhZkWjY4 Fqtlp6gV/eRAylr+APWIX78C/GwocH5jFTlm/dAanbkwGj3hBcYBy36FLIkuR4jsBVHYYMUD9nGn C8vGjqPAJC7zt5eRM5no3I3vJf+WJtc8RYVs7VAdthSPYxIYWnUCKov50IJDYCGFUOXdg0ODAnyi g9FZAcJRobphffJmUHeK/psvDFTi9ndxmbkcSyY26LhJ/v5om3Qkfokg3c6haqHGCMPF10Dnelre A/X58h0ZvdV6E2zHRfX5UXoV33IaRBrVD2hcn9t00Q2x3hsf5k6DQrYEywmPJx5NauFdwaYpH13O utioA+WaTiLVcVSc8V+Nff72cTktwJTOr4TVmFIHnf781jnxnRBcIxyY9Bm/6LIpnJVs7Acue5st CKbyFRustz8qyaHHDeJo74FNoqCCwsZOANHObfbub+U0uxehirI3pFUzuwLf+ohWfrSYmxgHiEIZ NUFmo350nGu43uQCiHZ9qvlrUZrJ6H2i2B/8wxgTyVZF32fyZYznp2P14ceYd0YGanMJrWAPCylp zUy2IhubKK6xup29Q/vNyMv803Mwm+0mm/8wE5s3uk/SHQd+eAysXpAS0H4C4Fnp8+L+X9XITd2w 2r1czM3/N8TYhOYZokCVSmzifRJErLKixzKhnqO4sKxLWRxXAKfUYbEuEytvRKrzT5vzyFuj90Nc T6X/KbJjxAEoyImwzozhrakRJAosks4AimlyABFhea6BdcTk9nTTcvD7e/SDU8wee1CMjTwfAyS8 VtDj/SF02l5Yyj7jFpC15H0lwkVn8rCP9DzUWOWNIxoacvgvEeIogy0q6nSCfDDZb42Rexkj297u EQ4bT7RaBFd57mC5C7++DNMSDstCVfZXXs1qgk8w5wT3WURRepAJ13QJNOYu+BzpvxWAe6XBM0Y4 lmyNNkWzHDdBoygPUa3wjm9bGiFsM79mOxxP16HHmNPqH8WlgGRUSvC04v1S+W3TC8SzdTfc6j36 ru24t2uJXjuma5v2ptPd3tJ/wCY2aEw7aJnHeyMP08vbbV90HINA36ufdPwTv4gGtbXd2XOa0uT7 7ClQygGow6W3WcyoMUMjN8I6yY6gHyodBAmdfqUez78HUYmLx4rDmZZtLPQngE8k//mslBgwGtrZ DBXFLGfzwJwd2bB/S6KyeQbfNhNz5FSyGBtutyeRAeNkml0kxzZZSukbiXwbLEEbVUs3AHTliSrW 5cr07FltHGW1NsIZzvY+NQNq/QGvCr5HHxWa4a4qKqREq9nMobGlZjJyeWCJw90K27ZlghS2yl3U xD8ZzyEt+/J5EraLVfMsSJjcyou/VNA2to7jRka0sRovFKynKdaURi4VHqVJ33d+bN0Zat7Mg24m 6lAbeqrujlu4UWzH5pSyLUSFg4aR42gDqGC9rGmLimQXKNEMbTEz3pAhlRrqjItofDNgj+kl1K1+ 7o7wcO0V8+V8VJrjcpQ2K9psE45XDpEaN4V6wXmv3B/KhH6IwO9kzi+mS5a9YzUXwBqrrBX1m2gq Q9GSOxATxP8J1LxMMpMio18TB2JZwYQmhw7/zYugY7EDg885BVojsxPzkylN41L+xAQ/mOFEv7V2 9xx3K/+RvxTxuy4rp5uZoXotEfRyUL8bL73/wcNP0F0hT61r9c73xpBdFe/hfTvImpSlpKOBgl4G dgUryum1TqH+c74nKleNux3IANgew9u3UIIbRwlBL3Kbr1dT8rjAaRhq67yeQlZRmtCcWwCOgjXv SbHn3Rogyov0SVx4g4Gy8M/9yMMq6OCtG+Dg+WIK8AFzkr9pHXGlAFxR8fup3gX9Sv5lRwjepjYD yiv+/cmyXFESjtlALclRuJe+8R3WFcZbSNpbMi1axTHWJVadC9UY7MSnqkVKOapk7V8cvZw5plJX tcKLgH2EGpQaFP8rbMTucbYje09k1TqjfiJGlDVZ/N3FLrz+aU1TFJ91skkcqbo+B1Su5KII55Uo 5LmTQj+DHK/wtAZweaEUwE2CnmA3FcEId/3x1qye7cG9Zcv2J3tT3rxAH19yl7g2WTHYBUSiJNJg SAxGwX1y+iUEfBTWbw8c0vkRDnIRv2dp5ZEMxFCAyqwcxYQtGMIHEsrf28y5Pm6LM/ZWnk0sOtXj Mts/QLOlW+XZSsiQYX9XBdD1pcXOaUudFlViNwhY7prbbdvBELh5h51nIZzs0X+JtV/SIHiCCZJ3 bmsTGzrFcmve/42Vmp/xp7wt7QuSI61DNuS1pI/s5oL0Wxi6mo+iNh2Y5Zthpp5oQyELg3vENSI3 YHu8inZ4r3ACnNcnpFDZokonoe4562n5C3bgpHD2A7OXzATzgROatoqR53iU+ubQU6cwNPSUlsI+ RTm3TW1/3fBnt7BrPYSKEXjJzl2GWit/HsU7BjrLJhJG7RruL1RnPWsZglSRFRL5dp7hem/AR2Wn MPS8MscPlJbD7n1S5Hs+jGTaC9j8Aid0V4B2fkUQWYYQ5vgMVC20FZPZ2mSOLaV+EKc6NUWYhsPE B6cL4lItxzPY29eIaWZDAeNkXSeL0FmoDIC6mV+9BEyGQ0hfYLBY5CH3n/EhiZOCRvO8hPIzG1oF 3h3Ucs6ZC3MQ7gRMW4zDatLryZXsqNaKBjoGS12F0JPxYzEnl5Z3R3gcw8KdO3/Q6+iZZEC4IxDp ezNZNXHSMSjoa4BFPX/VID+H0/LVDo3qhVpjkHr7GZHPbSwNs3dodwXuFk5nxdLuX5csLuoGsrLv UQFQtIJJP5VIzELatUHj4MKUnmQcwqgCLk7r8RT4zIP00xLQkveveyT/HP5VtBezr5VNGLXCwrqI BcMFhza1SzKrbk14RNiGyC1W2hOIzSMv7NQkJEVKCNNA3SeIV4mLwV8ROI2mWNSzUfoesiZ3VKAg nnEmf8RIzTqeCnVNpmoUhTBUZc6DOuRPTDtX00mWtCk8yspM/3aK2yR7t1lJ2Nmy4KKW/jnkeGfv zA67zWQGzCr7TmSKD/Wm4v/ft7wYoMSA8XttMcoB5c74bEQzaD8JSfp1LXsDAx0XNp5zN7SSUWLR 3gtS9LFBTBHV+V66GtFSOcwtQWkCHIDKxy2zTDlFS+51VAWDCA4zj1RI4UonAw25OTz4zSVz7qBg ZNKZAaAWCO2e1822APoTvNtHrnY8ALsrZxlyDwD9zqwhwx2McA5fseo1JJsmZbtbCY/eNuhrEwta 6OGqDduEqPsiRNh0wHwNAPXwFI4ImdZb4esAoM1tp7PtA/Dz8fjOy0gMjuXp2S22LxeUarXiLRBp CDgSDYtCGSzYUZ0t52rXpF3PLaOMvBRaHkiCfkJAoFIUgjvj1IMfYVdrFuQqzQSVCJTc30eFn14o 8g21qWB4uQb+dKlIK0Vn2VXxkNTwq+40uOz0lcPMkcnR1oasezZ2XTjFzqb2eU+CTSQ7JQl/G3W7 mI+gRwTc7+s4yeZ6JN2AZV5W/MifGdB6wV1ujdfkW8wh0f7W2E7jWMUbAazi2rz1cx0chyZYWral R+kwstgT9e4OIW+5XCTthuyYZRoEF/vA3LVwj6d6GIpsfxv5czFbpgwldc8Ye//5pDgkM34EcJUR lOai7/PKFG1hTKO5kJ3HLk1PzRbYjpm+FmSfVRaMrkuiU55B5xrsdsVT+CDaIR9CYD2gylGetmCP ZC3GQA78qNxGAN8jYpikraFvds9p3jB13xAmKiAFydgh3S5jLVGGtPraKhNWSPn3qMSqUkMlWCtr DH02Wht6B2Ut1Ny60aZ9RmHNhAU8ZZgW1SzWA5QnbQarRNKo3NtJOPlvXHAZoBjcxxD9K6zF2S3E 3BzKLiOLvVye1kCNrY7QqQnyTLPzU3gf1he32H1rpFY2qTueNCcYOxrYvNDTA7Dfz7ROwwLr47// uyG2gFP2MbdMxdwPr04NPaOYrA+b50/hcJ1hgypzw94Wy9viOmW09ls+v4nEYGznMgAC8evqv6V3 +1qxGmAFE9+Xs10c3Q7+F1HbQUgWmAHuGOT8Ppwo2E4J/tuJUZzUhMozly3ao+/ItScRiCWeRAwp 6mY6WaUQ4X9WNy9kuuVwh0KuEz+4cQBWQwoWVXsKt+69mbXqxvfQuydha5BgcDP3+EnwwLm0RN6o fVidXBv/4XeG/K3azGNKA4tFbSDDHpVhSEuqs82Yy1Vw6NSP9XhmHWexXSMv2jkNfH0SVSCb8gV4 obtQEVHe62tm1ldgD9hT+572MKVaTX/0sFKdzPHDHuBn286eveo/D5QRLFVB/LtiHk5B0hx9hXtX MBJ7QyImAtKdbfb7KG7srfTvRJzFnXVVhnnczOijTaswYCBl4ItW/knxrqKQNxfjSqIr0Ox+mqH+ KXg2Zld9Kz0XAeuXyCma7/VwqJBbSfhG1MZ+plax+NLpaMNsPGMedtQhsyYU9cPyG+Q2KucnPb9b z2wqGzX7QuydUBuwWuMwVF73D1ycFWA5hwV1HMnLMfxCz3l/eBXjYFP3YlpT+j2jqPt2bel2wy4r hYEex5gqJkbSEucMiB/uZZ/MOc8uugbyn8XRBto3I+50lKzHOLIKd5f9O4xjLZv+4A8eHKVXC2ov nCI/9mpTPZ1y+JcVeCyVFCmXP+C57GpyvvrFJ5uVLMTvnwrjPHgEhIKAmfBlLiUY4suXfhamHsGD o2kNqcdelYqbeFeYUbMjIM4KRt3Hl4RBu1eeWFUauluz3ZTcPat8p06PPfzln8oe7j1CZEj/df7Z stFOLG24SEW2IC09b/znJaBVqSLbrMW4zPQGg+PJMBYaMQx3eJVw8KegNQDIqzJUPyYjNLASCmTY oJe9HpSZ4NYw1BsvUnhgR2rQLS9APxwhV3cMGuRJGYYJyV3I2g4dTTGf3dHiqL4H1NqaTxDSaUnh jVCTzAF4FrBpfkEwR8656Y6+zFRbNYwCX5J1YIlnWBYbQjIRHSnlsvnqgt/kiG2KnOp3DuX/Mp3B vyC5E/CDuBBLxyZdybhEJus7o2O0pQovn40W3g1VsN79T8JeavrIKkqGwHXtXLWxR4Ons+5GBZ+a So+ZOQy+1cUS46lXZJO7xBH6fvVprlX8GF9P/eX/Cpwv2RZjK5k2yRRjyMLQVtrOLoubMvMvGRg4 pItnYvjKaSjlIY2nAE9LP6dZJqnk2mD0OTmVweRYwdCsOlvg21jOfZWir0iZTf8dSfTSMIPS/UID G/pXEPPdMyhak1QDyxMxwRJcT52rAqUNMFdjfaCl9nR0VfJ5mOtdLPcFyPDwe2qcUlRVRzF0r+uQ Cp5Uz/2sjqjUC5kW9ZRtpdEBjaD3qRXrBtqiojtQBU44AcvHOZb2lk7Q/4XoAYNmratY2ksooIMB uygmizYrjXWarZdjTsdxkCqi2PSpgbbFymb4rajyuemgiZ3EfMEvO6k+Is7yRLbWnhi0JdWoXPa/ dJ/L+JRMFAKGZ9Z4ejNFezucWXh2gFjl+F9IgUFB7YwgoiteBCNc2LEKie6OgCPs0J0OTvU+HLcD JfBuU43UQcT99kr9AHqpET7SCL6TcRv8M/vPBGQxJRBO+P5A01odYVHsNmqRh/DJC1gqjRaHKkPy OXOFq9RhhRShx1xwOEn5LJk1NzR2SuKzPUNmG0qkSDQVefATLw34cCTZdjG8EZSqY+D2GNswB9hi aqR/+mVLt7m7rXDS4TohO85/wtsXzZ7mEjqAj9xeOk5030O/TCXjo468MRPWQHyJ/3WUQS2asvV0 xTatxztDF5oKFjoGY6tcW4kHAQOVb6+XN3BHAKcaHXSwDoGWPXy5pYk993qI5KUgdSv11aJIxEq/ AOL35z64nN3XA9Z+jlG1y1w6HIzXKOyEX75mDdH0MwkKlzY4meq3UNKqPANkHknJYeyOObsneSv1 0kQB+LTEk15PHvA6Psadh9pgQE9hogx2HIG50W7xONLL/j5j09Fv5Klwyq9SQWZ/pGDygj6D17fh i3MerX0IgkHNyCtO0jGQ6oxUrYaMxHZ0tIzUT2r8sLgaV1ZCevUJnxPpw0AIybRzFi5BGUxhlBGX /HGjUUQEnWRTLoVpMjZojgDysvq0hUKRRmdDotL17/9Z4pzbFCe1QmvTcN6WOe4dr13QpS+sOzgs q2imJdeX8B2Qckr9rOp8vKoeUpe8I4AKW/L8t/Z69hcK4RGry/SAu28jB4jWtzxeq9ZtCkP4ZMGL pmXkKMgcGANpVdNPoLJs5aiS8rhV4tKmGIOke3HnGmWPgosgDWkZu0oKTVukOhRkSzdo/qb5yW9a v7ENBBR+U7G8u9g8xcjQqtoBmXc7/rDUpAyTHdC2HvrXnMbskJ8ZXETHSavPl9PkxbdZLZvi6D5H ea57MijHRgT7PAph54KXHKZ66jXVveTQL3L/V6OA6vuFLZyRhcs/dZPyS7zXED9PFuwx2r8J6x3/ sK0XNeXKMs3dDYEEwW2Hc4f5hShfQBQG2QAV7fydddsxjLqBS/BBsYz11TootUnMAnyYmhct+qFF Soe4gZXJ2iSCJOp4BEcMIC0v/bsnriLq/MBNQf0C12tTO0Yqs4uQd7fHoOgidGtiurTxCtl7UgHe fgf4Ej98GZH0UF2bDCttQbz/UhP8qdoBdRRTFyCdXUbLs7BRyL8ZGyUSr1R4xDNjtCeoHA+WtUdP 5Y6FU51eDz5576kkyfqW2eueALW95S2dFGyTLUpHJz7jNDXjq875F9oWjQQz/uIigdjzgnhdWSym ioDEo18SCUCTA06IKVieLgCyvi4qs4dwSfX9crm0H4L0GfpySTbzqNDmDVaW+XkHomBmocwn/hIy 2ZhzERT2l3f3OPPD9Hr4rGMN2hwZa5aS7m1Ng45/7IZVqYc4IZmNkdShadU6fBlTe+mPVPRebRjD Kpp1YoUxaCqGVrUgkmzBDOZmflh20IEXWO2CyRGjBHA0hnj9AAtlo0xJpn1F+G+CSv7dRw8QVQV7 7MZh+Zd34PnGxvyi+31gv7lqoUX/z0aLWzujlUO79Dktwf1sVBVsH5+lp+TaG3JFGMppoEwoOLhp xAfeyleffPcX0BSTh766sxAdQYz7AwO9wEh4NNvQAzL7cosj9Wi3leZpx7k6l7Wm+tIfrDRhMJ/8 9GlMuCwD/ZBwZutHKx90XTbtCIiW0ykMOppA6S0E93o7WLEFO//PqgCBpc67Dw7NzFs/0TSATyyF WIyd0rLT9ehNPSw52DIRN3DShlwTQUcFwShbz7G96ly+eZHCgtO9Nel6CLGKsb+Eg4o07eAekDqa U3IV44TbNEYyqcn6WJwg4MJdPyLyoH8WhwoVS9VNiYMY0KBYUuQcOhB1aFE0w9xQvqxQj/0qBebi 8Ww3V+XXLWyBqyovmvEh3qX5ZxQmKp6a6A5RPX50R9e/aASBziOYhtYWYQS84hLS0Thaww5yZ9CX NXrXIcYV+02KRClrNMcWjAmtQvOxudVOGsg0TG4AQa7J7LMzrrtKk3Df8iWQS72VlOzD5XT3YWzi nsUEx3z2aXy6GziPpmbkv0w0dOt2XUsZ/ksUmXro4XbI5mUb4y2OVdqDKA7T9RE+ctHI/3Y50iQG r3HslSzaXh0ky1KeU2dyrOQwvr14cBDoo+roAadk+Z/O8preBC5C4dKZ3d2CpXMP0lvaWJAOq2k1 q64O70MzAJ+JYKzxrke3ql8/smVrWvmiTSE30EqpDMT4DPrgHCLy0Jgfu9iVOCLOHouPQvrHmwh+ CsBQtiMpHKPE7AuCLG8Q3ccc69S7+O8jFMhNhll+jbZFMoQbsjDsrV2atwhAv9773hDnUzqOdls4 /xdF72FDHustBO8/bAsyZa0Zht2YILSHT6+UO0GdpR/SIM5oN76hTSCWeCoN3A8lDfsIE/daBZjn UbDLIyqzBqjjbhh+wtDwPPbBTOaxp5iaAKF/9MO7odLAK4Kb9Nnz8i132SVEVEIMniF5QvcDkKwT e+jPjDg+DEeXx79bsboZVE6imfZ/IsOfG/44F9m79E1cWKkHfWcuxP5Cc6gkGYHXHRVhjs+gaZZn TVgXc1NJ/FF2Tv7jCQsWhDBSazeNkCshg+TCIxz620EKprGgUHYdLRyQaRan4Z2xhtdXIrjTIITt Exo9ixmYXwBZh/x2Y9oc85DNSntI+K+aVbT/qSVtIqEybyQFCKjTOcu9earys5/l0bOM50rXZAXl rcTFRPSo8j492bF1/E6N4/MMX5CvbCoHueZngBKHwWApGQ956/52O8ml/fDuBw0fX5ls9/mJNyYZ O+rhcSSyHeSl+60lRe3XdHYXCPWHPbXIdH0HAqRmEJqsgp5KcULNIBggUllY7rY03pKIORgh5lG6 G7wt2qp+TyxS0OxU4JjOeCjOyQbIh2w3ebb+xxH+oMfhhw7Bljlrji39q7mBGnKLhH17YqMrxJHz hKuziYGkQ/PDyQNi4U9/Fd1z8W+qvbkAaqFfHqULhCtwF95bL6dNQzYNVbfZ0B19vQ8HPIBlDdBx Mcb2CJA0WhwKSnlxz7Js13R8ZKbpiEHgEH2W0TudzCcrj0XnMu3K2JD37ZZK1BcrqJEv5rM7PkDq 30WVFcDC7108jMt5jfRcSwQlhW21kfFZxtBqoYEO660RFPKF1LIXsVrwWkLmO++/TpkHYShtWCLo mlsunnjJN5CaaQksfhZgqXprSAHmCpJr7ri74+VbcJpwU09VZLMVEw3dtAinlZFwhu1RfJJlmSBo Ddh9L+A5YHeYisyITJmOuQKcR3mCtsQVpkrpLUVXf2dLrcAeH0Neq11bCd0rNBzUmUosHEuCdCak OKWING5Azak5Ype+OjC+B30+YtlW52xuMeTXzqeY8n1Blhzezu8bSwmY6mXpmAzYvWMd7G2VHGHM 714Nis0YhkVEcw3BczBxxNm9dtb+tFv9cCQGKIesjWV5MbOX7r7Bb9Ns8lniqX8UyCoFyzcP08mD q1/DAstldL8l0xtQ586n9AbAW/XgjcLb1Kw5XTzDXNKC1tIotcFnAUuZM8O4P2DtjRSqjYBrfymI 0mSQFA2Lunue3ZZutbHy3qLotlBIRVLVGGN3TsVYLRchFZNnOXuHx0FRagglz2zlR4rniXpzNzgz 1Qox1gWg8b4q4mbV5wnl4H7SGCZL4PnGtJ3yI3Ax11VKfShUlZ4/o6aKO3VmTiU0ErPsJrzW2LLK lEsrHmyFBtDIsi80fNXNKADAFh8+BK5tnRZYyPtQwxXi+0MWhTTwQ6e9INtncpT7DeAdCEEco6Ru ri93x3yM88P7gzt494chjVVeds6xVRELY4sjtDDymGZtL+z8gezx7FdLYIQRsR6DKhD+K1Dt0XV3 Cs2QhEMH6pBKGD4urZlhFy7IS+p2x82tuoewbT5KDYWZeTCHzoYkwnaIHKBVA/GZ618NeIbg+I7a pepaWAJUUj3HelTnp5Ix6adfJGeCe+bsChuMU9Yl8tna0mVGEpMsfwBXuyAzi+XycWMj8oAjqHW/ 27RZEuVluao08tChqw/mAK/9NNp2FHrReCHyFBCz8u4tPKapc2zRUgOcVqVAez3imZlhH+i+zTrm wO1aISdOOUB8UGYxl3vi3q8+l9X41kopmFDwNtfF0OKyMVHvDAVR/TDHUliA8XYb+Je4LJNob3ya DRUZXdbR/JBG1NdHeU63htGgn8Dz5IaayX1ODEtT7QJ6XRFSZYKWPom/gDq50T/mBd7RP1CC5r2u xfTFXTcVCWPWpn8o7ehQEeuVfSuzmG7Pv1YIstcBtU5ImAfRq9U85eWPg3RXWKS1FSzsA09j6hSK QEy24EJWh7Un/rlRIZs7cCGTMo7J5QkjOKmwFpgGcDrFz1/P6Z/tjH8IgWloV4nsrdQzXy1ZPHWt s/bSgwK5qfqa4qI/G1lFh414tZuLFeiqq3fdSAw5eZqd1czAHYAxbtvZ4aZKIL8G8L/a2NADip0E gyoL54GSdi8YK6j+l0QT2yFoOob5d5RRFksDpjsZtZCipbhDdJmBZJdYL46lx6ltqYbD9R9gNBEl u/UyegqtRMIzP95gG7q8tUojGP+x9R/2eUnXlAtkMmxu3C8p8qLepGnNsjsDj31XwzwymSrSY5iZ 1HAPErk7uOJTGHOFpjjzV7ecxkAWFkDROCSZDNjyvuz+Aqc4CCY750WomfEJzAJMEBuL9tOsEwAA jEg12UXnTqkteBDm+6cX92U8z/trZDZ6hi0GYasgZfdtb55sSq/T7WX+ux5HE/GgJYFlmdEiGTOL ck1kwROn0HzRXxNdKhfhkXduVaCRZMUE+RjarVxYQYZU8E1/JxIsZFBA3NhVwpm2xGlVW83T/xdO RiURJbZthzzyPIpwsEaEPGjlhgO2NqmsOzxv1FXtSzNzvKOIbSt+zQZy21+W9vNzacvU3JUQ6mhf xoU+U/3f+sqS5pUYmeRIF4TTocOgwmcEVuec8C1pX/OKELIczPc+4vLusorh2Ndfqcd9UurhrJ1q a6sq3ZEl1xC7OG1IwruGaUFsSvbbGrUtwoFd/+y7jgL78C0Cr+oGnoi12WMDv6BrvR6fL/kJX0HH ZV1FHhuIk/8eTzhZOf06zgZ/McEX/YpapKbRpakCNDXeTk6F4YeuxPz5l4NYLtXM2e0UnyaPfs03 7mqrUN0G71qOpo6ZEyd/wm7loGjMyr2k4+7uKpwUbxAjhVxqd/S0K61iC1AeYyXmTrMqwcmewj1i ftNux95cto7K6G13TV3kuOVUG3cfW5Y8hKhRw02sNHX2fM4n0tt9O+sgS2bwf3MwALqZRaAJP1t1 RDccj5ttX25BrBEvBI9j5yMV3kfKGaoPpIFSQX0a5j3hKGfw7Zp6KmA7GMk7imnc+1z59Hte88jA adHe/wRjZqCU1AlJ1ByXX8CpvlwfJvN4IuOfoh9Ibq8GTfPYKHfPBsTzDFlqM8/H3FdiYRNEy2KC cuJNFSXQcnoaGgApysteh+gcm71c71k9mFoSDSZSNh4lQR5UvaI9HuUKGcUW7JeiU+y+VmsGFUG2 UgRSk/8I8/gprh/6M/jAjXO2D7X4BUpUvtp4DmAUX9e1sZc6zME4nxQRDfnzGZ4Bbrg8Mfh0Kcc2 5JgBlXxsNCaoHtGc6g9cVzm0wbz9iQxM7kw1uX9ESiMD2gxHWVMm0lRz9zlLjM8i0ZnCSQoJ5nFy Q/iu5wzHj8MpVcOwgho5KEs2Inz+kLmSPAakCsTSBoDeegMoBL02OFTojVn0C1KzrwZ/TB3gFoT8 fShf1xIptdJRpbQLRskam/Y67guR7N6PkPOAAHiHwLOwkYSd9QhzxttNJsVEgsA8BEOinDq6kKv5 Y9akJ34/42w4X/JxRtp/GoS0oGt+V2a/mau/INwVCeim5iXGbNqL3Z8cWl8SsrnAwrx5YhR01hx0 uJFohCkxcDNkF1MwpzkGEcyZ8NDLiSJv3HYsAoNqlB3PlEOdI7599+0L01EAcKl5dLqIBsUzvEuP xS6jArlZyaKXiWNrcTG5QM/bxfmPmjha6vzurTONaRg+S1y1wElXD9yvM3Kgk/7K9plP5J3cxRmS e/HFta/qLlbF46yOvc1Vppofu2g/4Ln35l/37RgprYAg+NPgXCGLTMUaq+ChFGVQJVafxMhpfADj 1xVNynAq+D7uvOch55oydZbGKjG6a0l4qSQ4mrX3gd75U8OhwZ19NwJg+vDlzfk9X2m0n0w071l5 lBwBtb1EKIuXfHZFg7MGpDJbBEjzZcNRDIorCDNmKYmf4BnXOc6R8FqGlHG7YXlvOugkeHXRhfjy yLTBm5Px1voA/Rj59kVYV7wXD6JBW2Xu3xPkfrxHBOvpwsS9LIePufxnYLhDTegHTU3fiZgn3Z9i Bo6PDKUlZlE7mUja2Y578S3+1PNipVvoAWHKTU4BIWemlztcr64ipN0UFmiW+bBng+oi+EBmL53/ Gq+c759pIpbPx3adSeC4H4tPd57W22yxBK44AvSnB30cinwAs0/UvFBs/8X08FASBO8KaS96QWRf RirbT0W5MwgAaxPSY266Qf1PSZ7wh178cYG2YsfAS4/DXEQYTrrDZ+PiBIh91uU2LwWOaKHfVHKm Hc9vfkM5selVRIgE9Xe/ykpzmfrw9wRs3HWsdK27sduBEtXNZR9Lvo8taD1YZj580fvordJ2F8IV xS7R4zyXjLyM10W16+Qlcz01AvDSliSAm7kCCllgH/kIXLFfwHYqNyim6g8x4GvOl95CKmLE7FzV 4MKDOu6zUOHXj3Pyu1XMxhD7imNwJZWgZlNi/hO+33sM0o1YDt5RzZnv2OcP25Ez6Rbzcl6ltSbu hRGS6/iQ+TE2XG5pHQic6ZMat6FuYbD3Iwy6YMXp1wk+qzKMLBuabh9lVjuxzsrK7ONT5rfVFSQu f2tJH3ARu5ab4kZw3124B58nq9p/duGT2YSxwlaE80pwOfe+9v14hRuLTEBygFvSXcyL5Cua7Tbx 8T10ZZ5Cww5bHDg2OJrJr/ewu8bmcHWuVLywNEushOLpDW+gMhdoNDvjC2djYfE4qfKAkfpig/Km WSdYckVBmfrHGN/Ra/b5sGn/+nUs2j9HzmC3W0epsOeUMGnPoWXVVpwF+IOTZPAuOKVQOIEAlQgT JiVWmLWYMFSu1tCjiF/K5jgFFCWBVB0GjAGzCXOu6R/qIGpoW28v2vPEv0TKktNFSxioUBFRDGo+ NqS41l7cak0MfYLIU7Vr58WpLGy1URQzw1Mt6wBHcrB8O/6vZwBG5lTFJH/tAkNBnY4PCidvlPda aD2MmgM8ubkzWptRhTy5lrHqlTCXojjUvij83Kft+Uryv0beJq6emAW/zO3nzie6DxGY8xpfj5by sRJorj71PKJ4WKMtzWzTrqvFbsrWYL75vE+lvV+KSGUxFsfzwN95OWqualqsVKfQLWt+j8czYWJ3 fo/lvFym2gGIv+r0h0VNiAIlJEzkNiZH4jVWDV++CrL+uHEzSa4EipvoMnUo7M3J75S7i4v8YZPU zPwF9D/hCnocpPdgrhQaZC6qXhE9Ct8JrKXg79eVXl2vIv+5qYOm3D0X/Znd3muUVCXNy9LvmsOt hZMcB09Oe9HxCi2DyDBdjIgnkhE8A1MfRNDLDlPrZHT5jDd1vZS8yPz7K/gi4HAwG3WX9//Qqvag OmzoOqlzmZmfH1qULxwG2BuPJB+kbkDQAxfp2OBxvTUXREeVem1c7OJdweTXb5uUkOTcUKGqIXnh Dvh/jKyXyIXkHDo9YDiBduxw9ZDTHEyeIxkZzNzeZfXHlQg3fuJeSwKzUD7LtKrol8LvdjdPjTFb 7w95iE0eGqHb6V1LHsrCc1h7HOV9hIPE3t6nRbKqK6kJ22g2CUNFA1JZe5KxMsWzg6jXWY/+O1GR PlRxQ5CKX2lYN4VcdQQ7JfKPL4LuGrDDfmNANpiFVFGbTE0P1ll60HSyly0VJdMVl/KS2aTQvwqV A9u0S7DN0Q6m+BCkEXT0gjSReTzF9vL5HKqjoy+c1XXFGCS4NgiTGWXsOGWTTR8ZHo9LvNluSU3Q 1RImRKGPhmQQwHYbdJtb3C4vH/cBDf9Fa7sPFCcBy4qVNfssSy0RaZmcsCwagXN3aD9J3B/414b7 wiMSxGiakB84a8jc4C0kn7gaW9UHNhhuHCh97dPSBi0RxVhjJVXh9r/4N3SaESk/z23azt6aX93E MGb/Kn4390755VbAYbLQgJXonZ4+8JDOTlsmAV3ECCq0ArPkxZW9OQWysfhnk4PemsCwEwzGkdkI 38XE/QC6mfzf52Kng4MlJpT5cKAUGQVCZI5iXG9W/Ni0OqesyjJPwUNZZOorwj0uiaYYBaRxKDlk famQHVjRK4fqWSe7SWntfib5fTRx46Tp51taHpyT34ZR9lE0sF2jK+9r7PQ0vOcjTh7055dZ4800 6xQRNkR4R5Ga2xmeYY7jhzmpSKePa54dWVBgQa0HdwXphipNQNTPhEXHs72ZBIfT+Z3u/ikIcneZ ruGcVu0xJZxXB+gx+RBMy/6zDLvNwsCrASIDTPzlWdNy9zXp9N5JCZ36INCHaDFDqLeJwoAQIkh+ shW21OlOD02VjQwWYwQWO9XB1OHtB2HlDwgs9Z4s5xtakuFaiN+aAfGlK/9VQJIVZdN1wtiK9L9/ //cqvlVfLbNgn1ASggYYpt2fzLFuHrK8bkUoPOHRA9feE7Djj4jCB8jLLUMyi03e77E2dS337esi 0RB8eY37CLV8eqjyJRotKtbX1K2reVjm8QcCtbOMEKeYHaITwkmzzYm+HQsbtVWiOmusba4a3qQX WHK6qytLMTKIFfw0vz5C+85V66tsuX+NZsUqQWl0jmbDHa44exWMQgi4nnr87z7tsxrMzT+Wk9uC mexT1nWO1W9yZ322/oYw/wgF0R+XA19NxqOWQ2q480I/ju1Zi1znawUsc7QbCG1uUU+Bm+PWWtI8 Q7QDPpEzSztDQFUaAEKhg95lKcV4XwXQQdQSmUP7mXVuP4QLqqHxOPr11/W4N1wtbHFkhKmaCd2r G1p01AWvj8mhNaQnd9/vcyYNpfJ5LELjX7NU6EH9T2K0p056kE7EBPhP88rvuO3+iEke9jtGOyCv 8dDCRe74VslWxoVRECKxOf+dKECXIaVokMuadHWNRY4dw3pwBiDDUlQHRnAaOii+mc5fNYXg3INO khZRzKi9G6x0BOkrqaZDnPGM2wgQ0mc3jSRpmJ/ii4KwjLFW9cuitxpIwf8rXXxq8GJRaL7DvEjW NnfPTETeBquk7Ep9JxjOvye/Ucd21wXhdYxO2d6dGOa2/GfFLoZkELt68g10UqTGpwy2wegbLsau +VcLSr59l0E4WKWiNef+6uXOkh2vvIzCQUiLamEvyGrPP7ddt44bnZQIBo0pjwAj03qb9K8GRkrF bHdupt2U68eT5RcwxFPtos3Q7RsUAycMd3duRJJcqnV1rLhIeLwp8Ed+2bpcThZQ4kq2VfSM4e1N mM+dqa5KKeWjXbGufFmItYmcZl8EGTwNPaAfGhFnSFHN3DM5R3dXopCvm002C/4FNJ9Ya6bvJwWH Z9s/U1IBm4d5OcWp9f0dZZIf3zcfqWw3MAFtjjExKFNYqFMl3OVmJhEQo1LJcRD93MIB/dQNrxOA 275CN8tCXRRPzOZvb6Hp9ru8POBXOnyhcsHLtGj3kdUqDNyvhJBvP7BxZSMi946i2/2tjmramBEI v6jnL0SDqPm+9ECJQDITyCGGKGkvbgVUae8kgls+xRTETq+TJk84QKA3vo1++fFX0CtUWs7qyHZN G3tApEhJaHWiqs8e6FQoQz+z77aMlpTUx1C8ia659HQMtorbeKiVUYpfGeSYy0U+EldNxpPmaSrF bo3evhrDGdx0HSBNDiZCFgYnfn0KLitbrxg2ZFLtG5G0u2RiuqQhlPZhPznx/+NmS5RnmMeXUG60 vgxEIEcVFLWLV+qrR1Z87Jd7uGEKPnFT2R2mwnHsVyzp59W4uJtfQqlHw5JO2IkzgLz3no+kdeff l3esXPa8hPRLe8VqKswhn5Qu8GuPxq898o9fNPQ7P9i2Q7WPkST/eMZyNwVF1hsDbWk44U7mZOhi qsc4z5HszdI9SkwKIw/Iy/BLYAAXehadRGB5pAnhsMEIo9a8vZi1IXeUKLuWFwKYezpBwFPYayqi QWpOsUnq8rSrmWpJhEw39gRfFjcIpWShl8TAoM3LJ4UT72jEJM5W65h6POUQsx+PV5v/gSi0jWSp 2FN0ML/SfGgMTSoTSSILTNyW9MrmACepP/Ckoseny6mUypBAZdMdUS3sIna1xA02Cyy47A+PFBI7 dFFJV4anXsrKy8Cz/dzquv5kfPc8nxbrgtqgp9gT+z24AMrSbIBoXtRcDgEJoellPotSM1aiSb4t d/Pst8mtqR9Jeqoe72GG0TiMyqa8RnpDZj1QgV9lfs+drnowkC4HiP1vByOyjg7UMjn5io5E2zLL cRI06aAlwC7puyXWWeVP7JOe9Dhk9dIAeITWol/tqP9YoZyv7vmMnSifrqQsVYAp/zxZZ25B92s+ waeLKKR69cg6GnCTmH4UnGHTpQnlhB1Yb+xuHa8wBqD95TQ57uutKT3zsKCvM0wXfLEoJU6ePhG1 sShxV3f57mSQcKhGAx50cYXXh+526qpRmoRaNbvUGmPORsT7LQgb6iHpFXRn9AMoN/GxhrJx22MY pUKfKXgkWgxr2+X3PUDJFoQ9HI8ILB0tiYOjLXF/8Dd9UAwcsqc3agYkf/ouH84DdHm51Ix5MnzW yG5iInoWFFwBAeMmR1DOgYsQuyQ0jif++umRWnIQh2PLYlBdDm7wldT+0eq2cHs1LTQp/ilCkfcY nZn26DlEtLSq0sAyVvjzYp4s65c9a4S0kgox7llHDboFt6ntVKfA8SC3ei55LhUmDsACgXWEP8zr 7yipDC2FgMnpN5QAPw9fM+J6nOR1glbA7mFMTOROdoUs8TiRbCn7x+VqZQLawzsv1abov2+DO1QP clGSctdJTtIztmNZmQ7lRsYkPGj/FsMGJr7WF80FhlOJlKOXMOvZBmjt1AvIHU+TKi/rsI9E3bGH 04P9+hiGFQtO/OOgzafWjXvsdkSTypXacZ6qhVRFygBwDHltjbnIwUpgBW35gcg2Fa8ayblkgnPo /ex3Di8HkGx5df3M3EU68JsxxSVLcIAzboVeR7wofgoJ6uS5KYk+3olTUpu47JWjHLNP0vhXCcXK 1ldIzNUr69I3QezEFP5CH2bwstvenTDDCDTXDB6juqE1thm7jG2pLO9Ed7wPvza0e2w/XiuIR4Cx uf4gzgsX273T+T7i8uOjSgpPBkw/q0KnfpYEqj63TdbouFqlO7vY9np87ZWsCJWDNy2lYH1buOlu zZuw/xhBb6zH2beNSUORccp6IGvw13WbdaxS+sdUhHaaYqDgAaswKgEcux7Tw4LwRUep1ijmSFKP z7M40NfIxMvTcHYjmedByjQa7wn/ndiNoQZr+sBLBYOT81yJq65XNCHFEKs4N/EavlSV5NGNKRoW GV3v9KGi3CtPuv3uMfX6iDmMscdvDD0/sVZGX01GU3L5miy1x/NeXQq5hWXFOOLNPtwg3wxD3c4V xjfo1qerWJXSrv6ad4xS2VYprf5rxPUQ+VuJh/nr6eqpVhl9EJDy02EvJ8WMH5XRxFqOtqyTVTxK 8ioTcaFEMFj4kRqppBd+7ZuACh5GuG4hIx3Xt/bUy0mwgllJJYwq+HBEZjXVL/yr/wZSex28vePp hACXjIOnLmRpDqEe0jZ/qyv4j5rtQjXio0iKGlxgC4bAeR6gUg2JRYzY7fzj146uo4cGOUU7mQ0a 4g/ynuUsgFXxYoPQrgHP95dRow8ZrePVo3ZoKeh/Irqqqudujc3qhvRjNGsx0kqN2P5mnfkVuZLq NruxwgLqiC+HskbGJ0ukMUCsXPMkNHd8TbGIIukv+GKR4sri9lRe5hCb2cQeHdCi7nk7qyVEBqPU ba2SPHQ4dz01x21kO+HSdBVYfh8nojv5kDHSblxsEceSzYR4BSShy8tG4WBK9DtinxNYPmK4EjFc PxM+PLGznFA/oFR2/PEquXDsAzmiozhOfpudo/Z/vNh6jk0MinguesJcEjOmigwEq/AhAMAasIrr XFXo2BF1XPEYIJFImNaAIpq3pwk8elJLHX8qNyf3KQAKkuRl+qD/d2dS9Z1IxThZXONHaZPsSJV9 68w3imlJcaM3m1cKusYqLXOBszsLN2y0TlBLylDtwpWcWzbXIaNVOeqH9Iyk2AoZiDzkivHN21t7 QYbTPAFh/oEmAStclsNFQNOOCxnaswV191WGkCvsu5aCfFcIee91tonBNcb7h3yez1+XsUkYd9BE exnfboe7GJMnrLtiUzX5t9cRSfEBcRpYNEKRPduH2xs4HHdGeuY+9wl5yI6ROex4wZe6Asp+Rm7c 5Ktdcz7KooKAlLO9XBKcgg2qLDDhtyV4aNr7fz2KTYUxs2wo9m17TB4NRJ1X0ETkjxYzB1IYcCsE rF59Kll5BgkXVrs+5AiT4XdI+5v2NNNrj21nQJXjwKEAAnQGQaLHhigFDtqquzZ50R92SemIUNZ/ fOhJfux2TF1rcBVWmp7d2qQBGR8MqvM7SoszZ8xI12Q5edVquBGlrDkPAJeg+/q3T6W9G06g00zV 49MLKdt39uJFYLe2vPqsoBe/AC8bJ5qeo4bzVSK4R9yh0CS36Q4GX/9RSrcx96eqxVDgWVxxbbWF Fj9HCphv/lhVlqJMzeCiu90ECqoTmuK/2rqY5BFL+9fOqr01p1hlCRPYWNOkAiXcznWMGrRAQaBt 7ktEonvWaYxCt4yBTTg9f0NPTPRRvwnALEQ5WBLA0X6/sVSMAlzdpBHMQbfmxW+ihJNG4H6ZMjBL vPwOU34+VmS0VyMDVXmveM+SIzjVJVlhi9zR2i31yUnUXmIzAFN+ALwmyOiIy9Wcwh7rscuiA3Y6 I0ICAXytxuUd4D94QjnBtF3r0iFjkIcc+XpuFXuikSJpXCUDMFrnL6Q+qHwmePcy9giN/dWMKw3W mmAjhdu7JW4+gxjg5MwsxGcXfOniNlnDiumpvmVvSpaJYWM1qJgpPaWtFka0R7J34WHauU1zA3Km jFv7ISAAHAayZSCDVlW+cx5exUrffgEUVzWpDNTY2icbLe9/lUbO5Z20UU9xaCXWTiSTjIsPGLnh Ky56pB6wk/kC7gT0LXrbiBVolzlONcomrBFrblMkvE6nwYqC43Sr93JNMw4Jqpst25/+RjntViaE nc4ABQ5gaFf/OBVsFawcCI+1Lgu6CVXY++uujzzIVLyFYBgM1VoDiSu2hcXcFDgxvoiPVGZCU1CO Kk178C7X+Id4LYD7sNJMsCe+AqGbu2aJfostj0Ujj7wmBQPzfbufJqVEJ6Th9HE5UXSKB5q1jott xhkK0SBHvI5kzHlr+fcJJw16Phrj03p8d5RUhPoMN7ynb1+p1cHayWpY0Fhr1s3N8rRNy7MC6WTx qUZ5GZj6v70P7+fqSTxHvEwn2fjRMoVzY1Nez5byXtVb9CRmvaAAsV2eeSAfX0prHd7BpE8/f0RJ dzVGiGL8F3PvDCSrGsr1GoltamiOMbKVRE33HMW9pb6WdqHoJryv7UGcd4XXUZseKzyxm3r+qtq/ Y/J4Xs/gVWS7iZURKPZ0WNHDfFESz7sJDxzuyZSSTSou+MmlOmgZoth4da/lVZmIr2ipRqouRM1m juej27aUCH2X5J6D9tSDcMVrGYA4pM5oeeA9iqL04cZvKJa4V7W+t7xYUFELKk6LNWp71prRI86r Al1xfhwSX1NKJzOpGp+9A4yZVSl/YnQdcWbLj4yBrv8z6QNJDNQblMMPwIUUIJ7ju6XUK5i8PSkT NLTODdiGa41JrTFrRZe7ToC2Zp8oUnNacrEWQ4yVgIjWZ7O0c0IpdXaUlEL2GmfWNlxuckOYUyXV clHelLpd9d3T0hv+SBPbim4VihnRos4eSR58IDgxXKF/PHyPDVKTprj1n35+eZqtGer6DltlvFw/ yGH1eOwX3+Ip8A+1hzAj5WJl4S8XvMNXHEUTsyamlPEo4WkFLYeaoeMlTuZDOGgUNLWJ4ec/sIz/ dx/ZM9EC4JJvVu+rBHvXE4oN4aJxoRy9HywGsbL8BNw6bXnvv+xm35nvJAwj0AE04I/GPUVsd4N0 8sU5ThGnBo7GgnoUjDhwrJM1925qMO13vmb8JKXSr1xMLTLjx4f+Cc1gjpc/TniEfGoy5jqZYynq 5RcVN/SxG0hTQEsAXgSCC9r0k3ZH10RdAhrwocEAC5uIYUHptfLK9NdHKVbdydnsYHoj3uJWWtXT LK0m5SMaBjGhZiiJ+1CpEifUb1IQhcHdxRdn4TmLpSY3Dya8fwK4h6ymfD0dNJBUDgJWDGmhOLg+ 0GFjjoJe+UVSUaIiwUupOIKmBhkrS4HD/C9KP+H26C4bLTsrU31cF/qjCgwheTDeOd05w87WjGcn mJDRRzz2Eq1c3Qz+Dk1kxWznDdXdiZkL+59RVtglich6Kvio9j3+4bSJDCunNqTFP6nPrS7YfBxs 2pQY7UN/o37IPXgqD88pohgz/s2Z62BC29b50l2PpsWddJOoAhVHG/5hqGNEkZ4/8O7o0i1qgIrq 8BpINakGZ2aGX0YPoSO2BdnwLI+cGbMzHh+Rw0OumQ7qF0TKKEZZLYeXl+LStcGehFq8s1cQBvWi gaw2nzT5/DfExCt1FoMCRKooF9acmbYHhanE+eWH3kICj7XfX8LufzFBSSsECQrACQyOjLaItbSQ vLhuethPAL/0GkBft4HNObhfvDZnx2CBKupigqf83xrhDNyv3C2bVAu947k+yDNJoylwIKp6E7Fc DAoAzADzGXqwdy3sRL9Pz0XU82G4TQIzc6SQiruSSay0zZhMQsNVXTxuofYNfsqyjj5R5KHGeaKv zRxLPR4h76JcmXBfXFVY9JcgWCHPH0kEs+lvtlrlahLPd0AIkda1q0qCANrRay+WGUTKMwJvLP5u 3jcKbelBP4ygI7dTiT3Cyo2vBzP8RvMK7FUPgwwrzeq3ZtaGbVNUNn21QzeLcwu9eKy7s94Sp5Ly fql9DU1jW2l24fSxjLDNAbJ3cmgEw6ub4V5oDm3hXuPxlcYY7NFo7D6aEO1eDr9eQ/BuGRT0JMET h9GF1GSDyztL96U3Agi5NNMO/AJBwKZUptM5x+kmoTyKlj74G8FjdeXfctf24mfkmXL9VdUOIhmc EAey/tTKb3ZhLQQE9CGWm+CuiYxeUJiIvqQ3AEQQZ92gLUfAYpKBzja/ApKQuh2GOda2FXsSUwio tz4+oxrvmJjGhCskUMadPRQdqdW0DGnnnKfDhVFHwwQTRhKweZ8eSX+uJHTMFzh95OeDQ254L0wL MIaZTNsfLs7ycK84crPkfw8J73b3oayqo8FzSmKDTfKg9TrvhGHYuAr0GBNciXQdxF4C/A4KkS90 As9E96W8qFBobZGKhMuiswVVaP4J/hswhLe8R0mFsIViYVZrBclzbglsDfi1VsjmKrMoQdXsKxq1 DySSxZhSplzXxoFW1VXD3tUxhWevfRDN7mQ+BGrGqx/lAdgXPIBUlNCtrFkZqs9Vig3qP7MnrfHj QgXNeq/t3xdRLIkz07UI5vILfAG4wdtzwy3S434KDG0NrANNHQA8/Fx4loT7Dd/wbUMw86Ny9s4n pOG1fpiQxEi2cZwyrHyi/tFDxjLevy0MSWb3d3wp8eWDVI7LsccqH2JtH5Jqr46KnHIaLFmpCM/d GVRkZcxS1ENAGc+5Bd6DNiODgk1Cp+c/77jEX95fRfxkQag8rOPWCCLpefI8HBJ69aEZX72DC0kM YI9NYhmuzGm7MSppNmxHmibXjn38Fokkz9ljUXXlsEHJ/0P7b78mhaIG3V+akhVjssnauQQ6iLEu 7uQgAY55xYT0vYs+fNIV3Fo0HNtY+sQHXhHRZtuyISRBrEjBpnYS6Ohj/PRGZUAydCIwJUw2nKpL W4y45SnymmSIk/Rc3+FtQakCPqJv0MlU6PHzHaGEh1IUE9CBgnVgxf/f3ZtW7Uo/bdGmrDq/YHTO aQnuyxst6QZlxgL9lw2Yh2l2kgzg7TGPYf/fqgMsh+22ZJI8IF1JITrib0brQDbMUU27ZsfCBEO2 kX7EwJwya0obO9sWWHG98ABU7auhlAyxeBozaYC1o/ByMNZP3jCJLk6ADuCtoMPaNPe2D92t59Du iv8CMNI5Ww/Q58HL+QeVD6XEYXALVJ6ojn8eejVWQfy5yMeIFcOIFtXfCKrrsVEldLP2DxVU9MLr t87KD8gceSuVdiM2D2RAJYJVim07iPYlFBpkKHaTgnICGUdANtsCZh2kwcNgA9Ln3z0sAM7i5J/K hFtKqJbAAfCafrp6PQhvVNr9SwKHExL2fL90aWGb0Mz00Hnk51tvUAH3jWUKqU2yxqQnvn/xBPnk Rq9AtcypCIxfKr14Ow91eN9xyL70ibcKb3D5jJKj7SzbLRTl6vNKzSOx2j/P1TyRWFsLsTbvU7Id cCU2vvTTVem1KST+QezWbDJ8LcGw26DEW7mibmsXGNueOqJr9P4mKj9ovWTsH/t6B9iWwCXKLsOG 6KHGDIEZIN+1PoqFBMVGrYal7rl1PbP/egeRy6UwusDHHC175dh8teKLKDJX4eTn2M0ddvkq1lCc y/eNyQ9Z+OzP8+CNis2QToHrGTGBTDHCw3iNPZq1a3cm9sdWrbMHn0OvPbNypSYyhIqgAp8n/S4k ySqwOw7zJj0jSWH1IbEFaSlH4VG6q/x96+Z6aYsSrse+8I5SQcM1Qt2GCFwad8pSsX8D+4XRARsw jCDsz/7tP0JEvORrD7gxkrVApBusZ47frsu09GwVeghe7NrYUhLFNUjwGwdA4WrGNx8tejOjDDeR mYSaNvXWGz/W+oeZE6xV/9LjH09aNZYJXpw9ELCOwgpDATOPkjKSQ2DCmg/3Z8k4N8OIQZrubqNZ W10754KqwsmrThyDXifvdfz3WeQrQPvm51Px/tjq6LKhy1oNnyajg6sY89NkuiGZpTSNJwVQUS6E hbvwCgIvYxlBf+hPNFdpTqLuSjFalIlBTcO2gzu4rgLIWlWz5nw/sjWTNcVrczOk3hlHeMHXTC/8 Oidsau+HVdIezLmoVQB2Dwbr8SjJIPWs5mK5QFc06Y4kAQaApyTPlmUBwiRdVtMr7b/V+A3pjk8N dn3yMlDU4DTZLrhxB6XvLQUrhUY4w7subcL2XVLnaCMTpJ8QfjgQTcpPJBEKyHyEb17qEDU0vmOs JUkHiw0Lvg21OcaPB5Ep2mTPStVoVBHynUhkXLv5oL1TR5QjgwYP/85nzJCLwVJGze9h7aqeMw+h gJ39fCv72nIoOTMtz0tONYkEoZwa8RyuLVv+nkoB/LoYgQcai5gp1oNjqVKTLN4/qyqK12OyD87H sdmtNLkFdh1bd1upw0rVOTqt6NimvpclxosW4Lw6dC/v5Xlq1/q8pcG/WJVqaER805sWHqlIkzLU YO/mD5WMxdmCVEfHhw8x2bFbnIidAUq82f+Jo19k+MSntFynkFbskGQrI5+RVd0LojJAsu7kkS4m 0PVBQtn3CoppT8NdFcoN3Ws/cXdtUU6L5v6JgA8sK6fHcKGaqBd1dj7XD3wj+uM2PIvyLKUPcFnS O4v8iIOQKBUGN/osyEmO/zqvU7+CkWJTaaam9LFErgKZGLCLl3448C9pJi5TBnMMG+6FHIEw0UKu wpTseZTFTD7pN2ayWuLAY7qPQ1V0H1u9zLeI6L7cDHRfs65UjBT/aEch9eWuVyb8+salN3mh4ttC QW21L1JraYiOFS3Cyozgc6D06ljNn0H49REHTuelpA24/dD8tStvuMT4myyNokS577e5ObZANE1R woxmjDf5ZpxGVvFw3Dyro8lJ31Op2MHq2BbgzstNf+zWKDsutzcqLs5T0eYH2s7j9lNI6L3cvhBa 6Ki53IKV58dG/5FbeaTmiIxLqjvPUUCbaPgncQB6FF3K7H1zzNVkiZnquoftBEJUE+PBc7/BUJGC vdRXsLvBCOeRwYmbb+N5hiBbxjYcy/AIE3xRf6VxKqVi6eTaplqcY3zzD8pjG0IZun6T8dhP7KzA 2umMDjkdtNbeRB8h+fXiD0qVpxK7ll4ZPM27xvvl2Pd/yBmuzagABmAN9Xh9HZPo/vho4e+waoCH SVR7YXnnzKo26nS6jkDGFOI+/JLxezSip+jCYia2m+PRGs52tyGtdR0Vg7WFFLC9RZi6SZBe5++v 6HxZgNsBIbKcA7K+5VXpkiVGa3mdOV8EXjPxGgiIqburtbR5hWvVzDyaZ84/HzID1P+eD0vPj48e TfQif10DeUTl+iJAEmCUa46DgoPyDkAKlCYt5qS0CGVf0GYDdAYTy68BQ3+1eeeWLAvfRjsm7mfs 0n2dms3y+Q9dcnSxAd23iNSUj3RZuEIyq4QpZqSNvlEnc/0XKjr6aHPo4SF6/IcJdK0dKxNImaAL F3yj9sJqtsJpGGye9Pc3NCep0iKtgs+K2FQ6sqAsiztgGPu2Ht9b3K0vEewrL1kfbsBZG7W8Ykzx 4aNlXhvJzGSpp6rPagezJ5n7K6I7Ufy/RWiVGsh0p6Ri3UqlqZL3obOdyBrxMIjm55wQ9F8iAhLX CtVvIixCG0HUFrKh0sdxN5WJUzp9MTQUXEBh9eU885fTQLUnlQ2eR4Tz+rwX1dq8Nz8n0YfXGQZu y5xDMz7W1Jmms8NHjaUsFL+mUhGyHSz28yfYVZGaHqIQiWPw3qAE069hNxohLlL290DHHvqbNZpG 5wB2FYbOv36tbhFcS82xGjP/I97acsDjQE9TZOP1DUX/3n76EHCGkgdWhDrKF7SbcHO76JVQoliI pJ+CQddSllJQqXmH6fLffz+FQMjlmbi+0QXWBKCEheRey0VugQTzOy8sJQcIOMrn1SwQFa17M883 onxvOwHzBUcSQ2oeNhPZLeX+0UMQ9uzBD5s1GBcZuWnVNM1XgZo0ps2pLVwYiF5qCEQ5HSkMu39u hVkZA+Py+C75DDNqrA7VpRDyL2tyRTGmewq5VqdqpuvWJJnRR8X1vaEdnEcowwQoWyoSBkMYG/Tc AC96MLIZwvZbg4CREBmVNH8fLk3tW+3p9FKx1PMxKhcuIy6K8eM01boQq3Ksp2tSKPNiy6OPKJLJ h35XO3bJ5wBND+vtmskW6WVZ90IJurxbH7+XC9QMgIs2On2iaSWe0B9W3oYIgDzk8pICdBDqgKe5 dla/ctCqBKKFod0hXS95f6LRSVQ+m9xGP6CkpERmwWS1bPtTeOpkXxnuUWvW0w1r/1VE+dva5Gl5 DET5fkRwTVB3K/Hx2bE+yf6KuEHn4LxQJm8ogsNvSnzer5Pd04ZItsu+Zh1TCSHm+2gu2RMo629P KFX5HJiuzVQdZHOP62D2pONUgejaJdRgHsKiDR271wsXqek+JhrHsrGRJm0ma9TQeVnJRGTiJTvG h20Viu8sLNrafUJNQw5ULcv5kZPQLeEy0ae9tzoIhARvPsH9okn22SqQA+G+QRNSg6W8igy9k+/+ Z+sglJF7ebqiSz1FHr1FrEE7mNKYOhVVdxjW7Vv2B5+tuIXJ3GtW/o4S+pDZOPQScq7HGdcB+hvc DUYPtBQYC022ykF8ZBAibgYdGOa0Vo9XTYrRCWDmYxzTj+ud0o6+UmJ7OEFTNqyzuonu0tBor3Wk eXN/uKf4Xee3tPKpPaieTTj4JrPAcNruGNlkCCtf/OXY50F47CpCR4CnvkU9brUgxsbL28EuyMkF 18DHc55bnb8zVKRS3LTAuv5OrdFhZiEzi/2Lzhjzb594Lqo9uYZI5U/8yS4CpkZQBt8VfD3eC3xh IKmGh6xhtATwO5d8qlaXnTnNduVbXGrJJhBtd4QafbWQu6AZGb14LLkPcL2/SIUg0g8wULIpZuCp F0IXWabzaMOvWbZdz0zBNgXL6rpC5j4TnxKhCGrDBz2vBEkxhR5lKDpKILdPxNTnAW/eMOYT0xfS MelOUzZ078PsuwSsuJrqsT/tAygDlcIR83iQljIFVIX5cRZtzI4vrKSn3kHdNBF1/ojvQrWVFIK6 VNZwFhvK97f47qIXm9MfjIVQKWlAF2AJhAXBbrd00CiL9JKDrx4AY4xt6Z/XoErEDeg/dR3s7CRs OvJOoZCMgNAWUPNPbCXPoXpbrQ8LJ7mdEU63EitbK2IL1OcLVg7aDRR4IoBO8wxvT9QhNqafW4ta BbKTS/dfpNZDGH+UsGJibcXIfONRa3yqv/AhMUP/bng/LC/BX9MN2eNPX8+XaH0DghvL8AupSn+N 7f2jH0imcYVOHhBKaj35khw7ke6c1CQ4pOkVEeYtGXbZScPLk++27+6xCuFgNA2xZ/8DY6rKFJwO hcRw781ySEwlLxKZnm4riYGyiDEGbQ08zJDGXIzUr06+YiXXsi1cPk79uRMUttwP+SPT5d21XpYK v0Hkv/8HN3vfmC6amg9+A7iqADnjRe6Kqedc3Ckf/IMVBfkL7NfxKIIW4qdiW9C1Vxc02/BJMY11 dqwDHP/iPCeS2FkFZ3P3YeUflz6SAf9u/0Cgj35uG2tv1AhTSOyyeyFFe0YWUjEdjhm8cy39alHY vRhGit/T+o1U52082qtJysvDDlsP3IqrxRivs91meCe/N8Mab7gaJEg6FK7P7DyczvdNAth+3CTx 8QmkwCiMQ22cJi/tuThqF3cOYIrfffY/7ebavUNtB3QuVClq0KLsgm0gDRvs7efR5gfhxGkxqWTg GaPM6qEL0OwYzYCZPU4UQ6E0e+3yXHv2ZXbRXk7NNHZqD/mY7RtAZ5QrYO7Es8joIhAmFs210zss 5eRTBupy5okQuZN+9phDv9ZiCnc0vUSQURVtjVJYOdURYq0CkO3bMgBIuCo3lL3K1NyPI/XnF4lZ OBTBbsbDvmoZD708kR1uoc2XwGJvvz9u3TjpI7km83x2L/72lDew18vi/oaHbiN4fHtROjUrI82J NGii5h9BHlMp/aO3/QvWV4kmRW0SGqOkktLp7sSCWG4bGpA3SVHoUwTSeLqBfL9IlAT0bI6ozNuh nP+oSlAk8mU8qSZFFsV4aEhWFrY49txmgVgjP4fFrDxjAlThF4D5jF5m0IehZTX6thIc32V1za5Q aP6Oo/M4v7bEEdQG1vODU70FMuLn/Po2oldDcGAMUi/xlCrByFN/XfTcW47wYDKdhRb9OaEwDkLT jmvcFlfOp9JspJ5z1yN7XnYau2fQyACfo1rYc6YgM2mw88vQF0WvldFaS55wt070z/HProHBmq2I OZdXpQFaG0+tXeViSDFujwbPTKTlnUqW7tA936WyruPcj7gtKIC+QnkEdfWRW0Zh264qYaUeLbM2 55nBGhhvMa9hlsBb6wPy9y9Nj95mizLmWZ1qye73fLiwV6jDFXSP6unOEbRVt4h3b2wqUpXYUOHY E/kh11FHbK8PbHYqPjk4d6dOlzrtVqzd4MWYqGdmzBF127YisHic+0yho8VZxqpBFt3R0wwUVFBO WiAPXX/2Tr5bKgRjSBwBq4sq07JAFumkQd57MuHAOxJsckN6Qgmgez+9+Z++7N7NqDImV+fYl9xP DVHjiexRAKFwkwjk6w3jy2Wz+zySAjVFEciKb9GYlUb0kHmNKoaXXUKN6p84HAEkfFbnmSffSSS/ PjTnrS9Lf7Dlc3ttTqGemYWi5R3gGvztq15kLt6w55/tybsAO0YrQ3IRuheHnD038UKA36eb03zH B8Jvkwvn9/w2Gqa/Qg4JGgLGGFAWOuJtMSyg/7K64f/38O25fRN6Yke1hiv9Uda8DniiKbShF1cM kGX7hlSSTLQTuedS9hSzXUMtoPDBePqN9uNE5NWYI+v7TFWyDo3dUN69TXqIdLMMqbKkrHp7T1En U7poh1j3wUsSq+Nn+dzxqT+cbO9I2Rp/mPiMkC5cpzvEhGo3bZimBM1mcWRFYkNY8rvHoNh+5zLL juap6YEId5wpV/Vpg5BYEmOwr4usDNwJE2eTi3+Zvn+tceysUPp5hmUY/MnrA7Y6fo24v1ItqvD2 E7u5k0+0VuWJ4VzZx0Nw4n6CnY9gCrfxWFaLNqijv4aNyxQr5QPAFaoUWhbx0xZ+91Ci2gylV955 uCiLkA6jJ02B3CkWxH0i2PVteT2FCdRbYBeWmXVhc9lcBjiRXBIH+UBH+khuceiIjC+BOmlFauhD Yt2npd/5LAbBcOVFNNtopVKTULX6M9g5hRLS6jUQluLwu/SXzIzqsIDI8A0XIa3XXEEPlr2YS9Qi 2ByLivatg9qan/hxxAeSc9noxXnXfWwKPu1K6tSPNG+3rcvYFep+ypRNC8hP2iHvZ1VE6aLsuKK5 zLcu5gwAixhOWCe3DErevafiaizNYvDZ07cBoA4BV/aXZ6lcpPnb9mgFW5R0Jg4+UZYpnm/Yho4E TwuFdshFXC+HEStw/d98JL4nBXbmyAmAgLzU+GFA882WPd7wiVvoLDnicZUGMSGy79SBsOW7UJU4 pfX4nfdJtU14B9n3K28vwr1gMR0v4RotJa8JMcTxejnA4OLc+yml/+QxrdQ08T37xomZAreJ13/V oiMaYmUUiBDY7mqDNo/mKYgvF4O1KbmegPuf3aHbtRSkahpxouHMAOxjLlqoRcLe3F2+fXn14/yF eMlVQQdeB4AHG2eG65YV9nkMD5tjjrCOnPir60FwImbs68VFt+m4co8PiHQ18cJoBKEGlPhyT3u2 5O2O642DFJkNciubhiFnV2kvqjCiSC2kxyunWtm7JvMjRWH80jHlcBIdEEwYj8TxHzuLmRuX56zH ZrB1RPLN5ij+6tYUQCm+KkMVKue7wnUP9Un36t9H5Nt7i3qnEKGaN9hjVp15huMdrgpihscQk4CF 07pLry4+LVrFvDOhNOIPSQPTf/W9yNvVJluQcia1SOPmS6ASKiMffCOyNplFU3UNISmUazmitJ1h wazznUj+ZW7QlF51moQItVkEXqQ64uniXY35xoRaO69V2SuKv44Jd4w9MGjwtS4uef8vkbC9PrKK sjUaA/xSmakGVio79szCPhSOdTXXY00LVKdmgjIkVlxHpdfF3We27DDYFP7DqBjznSR+DHUNqdEe 31grcUnLqzIqMqAop1ZQhaTohy/5xxTEgoIM6U+sNApim0GPCjGsTAgC/dmAOnEOQtA5rKFSlfXY QSEbBuXDvgzfHkZLSICiSmZVxLpBR8YT/ALOvl1K7+iQbiKkVxhK3/1st503YBRpIKANLtx6ewsO 5PplnwiRaKBsziCMaHiRsSdk/j4+WeZOJ8JXqYww0JjODJbKkk3BsrN7S0Mmogt4W74m3V+2ZZQj VQ6xFa5qQNttUntq1kkbPADKLY6Y2nf17ADasGWVQpl4VWoqpCumYj8CwIjIqAUOWk8zLiXmYoyB dEkgR8VvZZlJq7SZnw6TCB3Ij1FFRdQfvdqUTYOj9sZJX0aqBwYwuowJstDvoDS+PNSWKVv3njiN 2LGQIltU5xAq+rv0WmL0yS4bSn4fSELg33lfdl+OStcKnQ8O6qCJt92St8maFO16w0lIPRacK6h1 yMCcFsdGk3K4GHbpIqIWloo0CaYFolrbEVRMqjwAGK13H3O2LrJOaJgDdzttMwi9DyJu6L/CP3h7 xzBqukdcYZ8wGd7o88E1nMGPj6UhQwOqFaz2ioajy0X3SPVPsjTM8okznvjntuOHqpSXiPk3hiyj wKYrsHHwIrIcTi56M6eTcnRlsnCzwBUUVAR7ruJUHtY6hiNcHZgsgLnKtxYK3dz6eYjS9y7sJIAr rg143Pq+4+oh/FcSlh3n+bPR0GA0RiRSIH3sdBqjf66laOVLHQ/ApIw10GGy3eO7LZraueu7ZQLB kKMWIrrXBpV02XxfqNiBm+IPCnWkbGXpzxi59COPjoo0TuZ91JS4G93r2yAGBEHpvlVgd58nK9GZ Ul69ooscP9e0CD/STC5wJPGjLovG7BSGvVbQQsNSnmnVrAsu86gSF88flPgJNc5E4gwQDF4sp1fN H2omAy+VAXb9kG46A6PJ+tgX9V7phcI+GHm194OVHjcQxvmm4HxlK1YQ805FUPD2OXyBvx2Ur8Fz RsPBK1fjfnyAduw6YnVxlZMV02ZsyCFk6EjecQxH8M0qhIGVbJ26HbvE0NyTfj8bn6bHu4mu/vfc cqAD1jCozqv6yOB7mxfIDYl6FOd7g8dfx5y1470hu/kzADwy0jPD1VoqKaED2ukkn3FrSIALS9/K K/Dht0HACJtfbvwknrFcEtYgB1tj8WjcEmojO1Q9Ddk6Ww7bzdUGTJp7Lz1Ojs0UqQbWmUSZ5GLI VeZs+OPs1sZok4XjoiDncdnIJoCtHINFvOGiwZ8AQAYOxjQsunHLC55c49c07a4sF3JCV1PMsS7H U+IdY3ACmPfhVTm76FoGAe0yY4JL6LaLxgcyYIEtBLGsM9EG0sN16v7YhQZRzE4Il6mf8FPTVIgB nYH0cTcuExN6VeGn9CtdyteoQP8uvss2eJk494njlDeR8Z0JeuQRScxbS//L9dZHFN+JK3t0CL0b Nezgsx2D36GqbCwl8uwH4AueQsOflrT/5ZAn4tog7CcXWN9wdXc28AUSa71BszsUU5D8foWdGUbM aIQxk5+Cgsxn5aWhe4Q25pkMGhS+PPJ5EawakCWy25LAcKGZ1Q4fsjE/YmuQKvXcBeDCMevHP/Nx O9ITSt1MuPgcZtKtLePzyqWLqSJDz4ywmOvnhlVwXOXIWMMUk3ybzVifWWtVyOcy4sjvIAyjZOrL k+0pt75s6R4yLfIacwiLu17Dhf8KAGamYNCWzj0aBRGcnpblW9vInSvGQKfsQELaLMeVGIYqm7ro g44VJoA14m8ZVmU59CfZLKLUUnzE1BA6mJIZEULKNxuwoLUftAyELQTn6oU5docBhrEJ/E3PkcoG 9p8Oli5JmN5HbOrdmTlyIPuVcnnZKax/ML818b0LG9pQxhCBWgrMPr1GZ47c/P35jyH8bvwsLWM4 ok3GRRXCgDoW0CHjlFzl7WhhrRIuxHCaP3kURa9PP8cHHf0C/NnckXuYJqoxTU62GzDhNE875xzB xNKfkO/eEiYDqvsk7v+jdI+SOSXfOOmc71eGP6+CyAn7I9R4zhlislNkcdkHCfcwnT7Ng5HXCC5w 4LHtDW9b+5hTWdccnLbH5Vx4fBm3dT6J99apUOHoJ4OSip9gbQq2csJGKTFrRNbfSiDinjjPzCde R3nuPQxsRvd5D70Qu2/8vNo17mbUlavJARgNHkxGwrWxWgWA8Da3UucSUAB3iNSANHc+OvwT6vFs nmMxLolV40aQrhvsPyotK2pZhvM/Y8B/ifxkjbckOHrAXAp4mbpYXVLfc+WEbkJD+GGfxDBH9DZX 2HsmjN7VGhDorVKc/ocOriGdj1PuJTnTCow/aDQOpKLdd4fYTeZIVl3X9adEMCmz+hG1niDrbOrf Z+9hASWv9fPfwMmNH8IVyi/aO8qOz44pAimSaiYHiJEl0aqzcOiLyel/ycFc0hhhyNSZuqZwAY5Y atPzOYB7VxqTkxgDe4eNmJCLKxZDV/xmRQwNuxcasQ7vlRJfgyvMc5lktZt/tn8gWqXZQE3TJN/v UtPhwqEEYtq9oxKehHcRHVtGTlhMc/O3SGqifw3w03sAgjP3rvOt6QNB2WRMj2rBsjmaAiN2NNJH PszgwAdpmjX242pQcfbAdTD50IP2yvd0+o7kuNggUXGudJrpzLvkzxYy5tbJ5gPK9y1D6Rl3uYbc lIhL1BSizwfzbGKk8JFyk0AN50uuLR5O1M2kl/f+oZQbk42oyv56/1ti8vYfYG/2j7+YHtkf88VI 1yWdoFjHNPuik2lvrFduV+4+9QepWLt3EZb2lCnklhsxwX5kHntJttg74y+T2u52t+PvaI+LpL0b Ujgvv2W5wtHJojKr0Glq4aI9Kd2SGLuvO3KX2tAeGRHDIr2vmwj7ss42f0Y1nAuQi0mB4lVawU0M aG9B8U1+9DPzMFh29lv4BP2yc1pb8fSSeqlNdjo+tNRwttQQXdrEEZ7kHfSkfjV6nCf9jGMDYWIc 92c17wmKMcYFssVu+ORE2Jewmw9+tKqjoNAg9knprOgF2kwLGgB0vYXZd8C1fA4C5v5x9Yvs+1j8 RSSU9zjNPUt09fZYCDtC4FX2E4Pkegv0r7Fe7p/EbmpnoqC/DX9iUCccd6XZu3M4QKHBZ8tvzkfN U0NLolWnd3uERGs+cnMKmw+Ilmf5KzE/WBP1XiOrg5Y0YdbUSWgF2hmJJmT2sBaLFPV5KZI4h3HO q/LYEydyUYUji2EgJZwh7EITmEuITHAnEP34dR+XNPqsqSU+U1L0Md+oYUQV/WHx1DeHQIZBXQn5 i42MzjITTkn0m3pq2NJuHK4utEKyeSudl6ET3jQ1VDiPC8lq632x4NQd6Xrgyil62bOroO/CxpCt ixsb9QGicpHL7LFMbmiqxKkM/qzyGCRl26mltDFT/dR6BBnW/2CZrr1T2rN3GaxFWjx3FwjqZvTr uH4ZHa0kY9ZDRqCKhxl22Cb9qsNvE7NFoF/bPktPoCtwvQ7sIiKv5AKcEfjHMEJsK1iq+vBiJo+Z xfA0AROSquTfcsMYpQ74VorOSkba7mPX+RbS+hdDtLe70BtzodHGtVfpA6BgFZP2tSojS3VS0Knk bhj3Kl81xjI/5qgM3DGFU36/Xa92PAolyGBQAl+AY9OP78VxtTHqLp1G3OBEWbyyJDbIGQGYUzzN ZoofmrfhOe8iV0ItANRIlqs71dhb9hNMXFAHrbOkRAfJ4xSUj8d/6R5jc5Sf/8eYNKW96QMGPH/W pMLc55PFjCkgv5ieMse1TDTy7+elicuC2Intlfj07c6PU4ysK9elxUMrS62akODQco216zpwidJO Vbj38E8RQowQjHaJQL9ayMVLpH7UYXmREcQMItH0gO+2dDyo4QjCaCu0d/lG9+XEcIb5boinslyY JRl4FL8KprSaagz8zrPmk0ErMBXNIAUZdCqsl7UOw1egk24UPFqNoPYZLhZdypymbeXi/gbQ0Tqr 6wyB+KotM777X6NQX8cWhfcFVgTjmoyCbw9ML5/QUxELvjmYizoQb/WaEMkOHKTbzJBDfTdkPlKa FYHibgvJ2z0Qf/bLQXBEtTxLxMRZPP8Nz4MUi8nFsMs6HhZy+AN3+W3tLnWsc+2rAii1nQ8pACVD gLtqQ8w7qNOV3nNlDFD1U0H1C+a7U3Giwmxl9liETWhQzS/U+d6W5GiKPc8HXXnOKl2bHk+DFUDW jXyCDiaUlxQdZw0P1VAvnIIf8GIclfcni/Vyuxh20y74yeW8FnRPPygljiuURJBYazeFnHWhpHW+ cUppzXiFKmLDf3yOvO3ztTnVBF96zpWXSU2j5CMz/ryV0Ie4BtFKTZqj0wP5eeQ8r1dwY4vtNiIt JOOWXvHQKWwrDbWrbitiOb0C6Lp8d/0q0IrUsaTMxUNoMR7VeV4U2ZaGyVZ9UKdnSOiJ7xFOFhnf XOg7hZ64uVMTkOs69I57T/ffVgaVhMQ88zL1OXyrs05kT81cwi4rtpDHrCasGFy6SCUHleV5IHCW zhm8O0/Y9wvx2kfI+yPoh6kEscCIOTrhTGIEY5O5bFr4E6reVYYC96p1qYOOFn/qkFT6fvg4MAJa bB7l3auFdIY/er63jOmB7kA16ExT9IM7Q8dXDEFDJyG7c7f0MiaMoy8upvuR1bHoipa0kjxh81B1 gWtje7NKDKOpAyq9sMgf2qQrR4+v8aY3Os1armh8WxvwCiOc8cB+ZbaRwPSXhQyyfBIjOUi0stUH j3Eb60q2KQMAIUTTDhli6gv219ij1F7geLNy4YraQ9KyVKx+2QdeFrugBicrIThqMEZdT0UXcIgX pQlLWTjsxRhqo024fdjbb3hDQadNE/dYqysnLTuqPbpEmVT3FGaP8DCuJ0ehrl1jlwrgsSITE5f1 iPt9neq3CRLSY0cxpdnCw1ZM/DTZcbDIEI1CrpY51ijW9bNzLCTBE3ZXNtaFA6JjCmZECOp4MsWf 9WcQLFXXqvrui+zysg1N+rhs4Q3tx9UQTr2tbxFSfINBNLFeOCfRGAEkz5Qs+gOl+o/A6ov5I+kq fqJx+ZFfEkvgi6CqbqRMatjKbZ/0838MMWGNkJXT6si2oPlh5Fup5H8Tijc6T0Hm8kyLeM//QtAi iy8bnwghaqnMe4Ldbgii5na6fMCO/zlT7wteCB38/eOt1v/p4f4UQzIibD6Zj58abpTUwLVtwv7X 9ynR1o1tJ41GdGoLCS2WmbOmH2MPn30juSrYmUwZgAr3vaXSAPw230tFEXJqZ3ntP0JltBzy/1JC 7pi0aSVXYICHt2g9Arj2FZlssbPuvNMB3e1jUAbh1wToZvMdKfGuqDaiJEW2IA+Cx7NE9jp2fsS7 RycUoJBpDNk77GU72ShqS+DsNlEYEdTQ6233nceFhCiqTRyJl8Q8xqYlno0oFzFAQdqYRMHDn6Xs y8RKkvoZVIwxFAKR2M2f3BzD0XShOXdErbKRnlQrZCyHjq3mum5NoH40XpefkTccZU/kLwvw91vX 8JDGshhhPM8+DQVRPzd3oZPwzEUeAwGllfw1jn1JK8idmgglgZjqNcHqgyC8CVcs8mLkiUXv/1XG ukH+ZLnESzEky+jue6WeBdyln6x3+YKeiwinpOJ8jqa4ogBcFwGOGA/LONKkVkOO0YlOQmKef/33 txgcZZHCBbA4ZmbSGAM+AxNDKowao3LXpNpwmncYZpVV032GOEqjOONlPzH6gTS/kDDo5bfOqSCf MGvtb+rEA02J31+FAdOlv7YoyzjH5yybLpaQv6Z5xYrKKy3SSAF2TZtRojeuzdQiEH3wIqLhMfH/ 0IrC/m5tkhoWRJ57t4gpGF0fQkXwb0TPbVmnNFAjyUQMjsPElBwypvgxubMp7rAiCQvNkxQuR4KS sdy92ERunYkWsuvEnZrpvw6lDlim9TEHhps/6YWWW01DMLW/vI52Wf4U6gE1gNf2gO95CqMuq/pF U9cATr4Gl2INLdhHC4Dm8kCiwSveyiQM3fOAVRL9Z2/+RwQ8Tw5r4ChLfFyDP8l04ehVdRMQH1uJ 672RJWk3eFXn9v5niFUIiy95zWENj/L3Ack2FxDmYcPpx0y/2ce+min+rf77NgwhN1mTYJIjD46p pNT1VRcnIu1MKqIcWLgpFzrDV5DxiJi+Wso/pJAKmVSx5pEEa2Wt/NSlC+9sMoy8PLTsbck66g9m xRWHTZTUW4rvs6KfG7d2BIYj6ezWfruFddx3O0m004DZTkqA1HFNhRegAyfe9PUfwhKvbvi9BMmO SmXD0VBi+/W69/sIMVxOIwyNAPvPBvrD7YvvATyzP2H54RLLMY0fgBcmCT5CNY+2KB5oJGKWiGRk XSXKPu8Id2FG++5h73N+y+2bImL4lyqD9GSwYd1ej6MjUQwrNDaCah3n2FuZzUoIyPOlCTRVnUXv 3HwNp1FVzWvLlhEzx2eBW4yTTKZnRTAz8HtQv2/X/dFLozprd0EgvGoqZSs9WDgyQ1t1EoGHq1Gj fhCjH/dFiHzbRlgoLJLt/hdd31/D/q6OqOvWZyBi6OVyAVvAylpkPdN0uLbrIel5aAw/9mOnkSJ2 bri9EP7WcfAP8mstUeUrTKHzx7MOk3p8X8WMFiWSaF8pySe47tf9mU2EMdnWZeV2RfO9fu8x70cV 9QS+TZj+RbzVAyw1ELsavbLNB9nKaQIrSWG7iDO3xJgTplU/rg2utQpyH9UdsiLGgk8vs63UqDpI OTWmWVU9oYz1kTPugiIsgfM4NnarQzZUVJTWdl1I63D4cFryMIL6gn2fpk1Xe3J0OqH1otb/b7My 5PvJp90YhpJuUNqg+Aipfq1+YHLIuMgLHkPlrbbsYrAgOKukz/0fWxAqWgc/NrACY50sHQfi0pEr EF31+z/1+jc0zbkqz5Uq2aX1AhK8IWPgafvgfiqsjfUxYmWEKyNsg6FUCHraX5uDccnh1LDfVXsL tHG6nqOdXZC+boXMwSlzrSk7qlIRdWLKBwyX96mEdNo1tbNgVf73HFQE+41xb0cF611phTc4CDtW NljclVlZ1vDOLRX2btRmjHuSRXAQzI6BSUyN8niQ8nw5zNzFaPWYCgexNIj5+4qRwj6xn5zdCuYu n5rYvQBYv8HgCROqzOZyfSYr1tkAruPQUtmRPEPIfXmQ2JsG+p017VlL3OrDBpShhGL/wC96Q521 vFq4je7mRzdn3j4RNO2v9UcQ/s6mVKttxWXqmPGlvknb3g4T7RExqnZiHqikrhGO0BiRG53E9/RN skP/cLbXtN6AfIoaCnGDLUPctzMaEPjVq/EPRcnjtNl2irUd0ZcVUFs9RFDUET49r8KoIldaodS+ OPzMn+9fvjoWVrQVDHKFt0HPVhrCWJC0Iav8MCJoRUnF9D4fK7qGRA9GPbCZ5fRD7kinGGAB8Wzq CYuZA/f3g5G8MxFo6IyqP/juWH38J3QrndQ+Ch0tn6chwCey2aUV2fx0i0peWX9/r+4eqkAkrrNN bfMNo90IX7id9sar+iPFWgJkpan/pjchbvRH3tes+zcOPp44hVdds6uTiDrSuZl00X9X0Tg/z7CU 7JySoTijGhTHyHBmpFbghC77eZ2aqj8hh6opyJld7exxC00oBWxwhJP8NhZK2v2gGrzQ1lZ3huma vV6YZhW1T/vqVw0gfwF5jEsLMIh8vp2XcEv0MzvLLKmReN9vpvnbAR56zVIKqKEOcEX2Yz6081kl vxKv4ak0hWpxLeO8smXg/LQMaQG4eKKh1eHeiLM7IOTYgzQIj+waoC2/0xV2o54w9TNphkN6Y+Xh dEtqxHTv4RI6WazQTS9hS4WMyGRqG6ocxjPT7Qrk2TEZfs5HsfbELZWExqkOc6POSx87jYfd76kb N88p5RTnaFwnIMgDwR3vEk7onjVji77xz6juvZNbPBRLqJLZEfMQZ9WAsX9xK4zYsY7IiNxKMJvk PgFDe2aitjxqcn1gn9irN6ay0GUj26S/entTsKSGK5YJijIQ5r+uWCMSwr/HThKE7h5lzn/aVmFE UM+RjgCpkuMVsHPHG4q9HJepHfMy8c87tbWRdHtvbk5q3w8xff2A3L5ezQFZ/qfcR0GUhTWcleDS JZETKGV4yK0uFjCfz/E+6dyEHeX+pXV3mfDukOebo5V5SFnGOZ2cqlJRapPQB+zWchZz/Ao/t4JF m6CiPybEZd39vlb4oxPVsNRh0GwAaomvQgXNNda+n3S9A1sULH5gVugCstz2I9aTJ6SjBmQEHbLG GHry1cDghGiGFKAmmllzI8qWnrSuIQk3oE5JqyiEE2QWauZ1NuS29GgFwg//ohQCLwyzTuCTnsUO q8Nhq5JXjz1rUMOpvavGMH9fbAGL7bx+pYCUPXevkapoQswrIrSCKZDzgSgXPF5jTGxrr7RzDNWr L9Ur8DrQnUOztYPYRYnPKswayybGWBNgDyu+LnYZsQ32DPTCc2TJ7GsSN+dki0Bbwlos6eSIsJpK QUaVaUkoe+jgW0kjKDIStGgbuCH3lG4A12Aj8E5v6Si6dKT/3b8Uhq6/D+rnvBH07W1McyXS5LKf XCfep5P29iasM/cPEz2WVKg9WS67ifTBNbovuEy4Oxkm76dFY10RTapo8+yCkfIVC9L6nqGK35qr foPAXan3HiQf3vh2z9vQM6eLyFxaymHr3J1pppQoa9zZVUtLLRqCXmP1isEVoPBbW7h48pDyR/g1 HpavXsA4ioXhjEdtIrLkIbnQO6eH/b3uAxljnzueDuZ9sorEaUh9Dz6mkxb9N0vBm9Jb1j/C/7gy KQ24xCzeD4/V/8qabsoBLZOxZOXnl91xS1ujcGqZBEjxZqoKjuuCumvK49Fo4dhlTG2hwh+jHrGT jU2DQ/T8btZu0HsgGU4MeSNZ1r1ztMCOQQjVud8CJYQehRqMzG7gZ1hfU4U76OZAfjphKNeErbHp cCf8doSFvt/qQ+pAGsSNRf/Hxv1dj10x6jbf5OOAGmX0ycChoGn/61YV4f7wZN3jonj1mxyxUbvu tF1CYixQ7+br+ZproEYiiVWEzmdFLjR+djS5pnCV/E9OYemuQ9Pgnsf6fbPIFweJx/8w7KnN0D/U ATPsA3Vrzd9HbV0gtdhvg6LQNs15lLZTPB/GznGxxQv73TbiQZuq1jRwki+50b9WuQRhSfuJ1x0d zp5edPkqgwUJkhNpOTOVlA6CGyIl5JP8iA9AsIKPD408V9Ygia1YFoITCt2Y95jWle0zhht9oXmw MiZxmSuOsh6MNzO/Z8Ft7CjABSaK7QsjkEWKZuOC45cN5H+X3IOzgLggHxTvy9QcYozZ9xj+Y/97 ItbULI5Aw+5TND0twwMWa0wuyGqaLYEAHV2aRFbWbaZ1M6oIlf96ISaKQlZdPNykFlKlG41lk36Z pZrJ5uB2TW4i+8Y8Jczy6paWI6AzFyKAlz3xhP2gM/h1XZKh4JylpCUQ+QPD7+VvYqjxa64GAaHH 8BZv0H19EVDcB4PyysLnhouk0mh+oYeKe6gWHxEPuhuh2zb7LpjwJpNF8LwTIMX9b62+wyAi0N3z uBmHOB3zOxIFlsmTmjoDAC/IngItmMA7FzxHlAQPIlXmP5PTuT7p5jXqZQgUw+82PnzUvnt+rS8b BQfZkcNdE3O9/kOKErR4uEG0D5zIEdl1wK351pjWxumLdmlxwktx/U57RIsNACy14OWrN4NiGRO/ hIjC+O0AoSKGq/UEFot7KAXNfiSxjk2sLjhlslaTLpyl083Yid2mipfrFTpeDOelP9YdW/jJZGsM v6uMg/OZBD/mreP8WO2d/R2/Fr0S5CBzLGgizqG1fWuIxBAkc7lWivKgaKYmN1m9ThFNmeUzJxhc GKZxi51SN1VFonA6paj1Hixz1JS6JzyiHx1FF8LrCLVGDdb2hIZ3v3SFQ5gRR6bH55L94v+xbMY4 3BJEib20UxOhB6NiT8foGSpWeriyFXcr/vdb7xVTvyJ5BGkPIHVUyn9rPAJgnqIdkB8bPqOZXrxl JRWGelOo50umhNRzNS36EwfWI1rNdC7uXRpg8AiGA4K8zSa8ZXB7h7iCvEARhIl+iTXEixK8AzuQ hgiEchryqB4AGhx57k5+zirYeSZJqOrUQ19myqcPhbaiTdfWH8v1a4UQ9uiNidOgS9UtGvCRYIjc wunKGoDszunCsKAXpqyDFEiVf7kWeIhHWkCq7wMJyRgJCGt6VJ1JCxtVlvVFquO+cuCMU/WOW2mq 7zcDSWuxWwUXYNe0HZbJA2v8W+SVUgpYiAfZSSfqVzOKqgZJfhi5U2BpqIyTKY99eMKQ29yQn6T6 9vW1aGRDVPCO1e5iGK18NybYkw3hj8++uLiEHIQifDpSiRouR3Egl5sMJla88ZbaAuBvsKQcMYDz DijZk9+xLVBJA5sTvBruJSGJpBEeliLzUDkWyRUcYAsu6/eU8bspPqvHKQXpagYE+RaN9YbwcZM9 kicYA+qmeZiiRudKKO7zjIV02Vc0SkrEf23ovFp1z3luzu/Wu2wp5rarAIOPhRo+J+9sV2NEX/CH 1uzH5d3YzN3G3INMbvrFhN+H7xpal+pYzVYSlXmPfcJmeEWIuAYf/c9DU4TExDzzxzstBFQTT+Ol cwMs9OL3xo7Sq5Mv/9pLo4zWt9GFngxuUq314SbEYlMUeBHnbmY/imYZ6LISabu9Q0llKEbLHmmK ti2qoqklzjnSO7TOU7arKu39XXZkH4Q5QJ+CFvQIGVLHMDyvDyT+9To8yYxfmrQ1th+Ufp//U3l9 WUN4fJ1FP5Eo1Q4OHplLYYzsP7TPi7B1zoOm3m/Cj8wr9+WLcGScMluZKHgNj3w7Ywh/o9Op+6kI qxb5JYVQgRGHWQi2L2m4Ss7ocY7FdLKx9WVkbMnxz6Ho2i46I9BdIjsyABazoWctL7zVgk/3sgK1 06wq8Q64pn9mH6GFyn9bPXdyWBeuHDRsbXEn6zEzZtN522pTiRN94a83DTfqhdoWKOGjzxdFxLoN /8ALr6JGNbT2j8upvzTysD8eTBZhlRIqaoMRyVFVu6JpvbkxTewxXoTYqu7ohv67Uv6a7sC1Iddi owl1Uu4KnJQCdv5bOKFPmuBlgPFxxxdCxhkiQgGmhAlM29NTCAkQz2B9BXYWxcuda/glMspH9KO0 b/tK7VjJX7iWR7WsW8st1EwypLjCwS3Tv+2W8XLXYvBLfvZ3gHv6WNNeBquZ40CgRMZV1ecaEO0o qLFdgEjESR1E0dM/Gv1IKpN5BygTJGTKpRbax6kN4KTj1jcKbdIlawAk3gagiA1NVidlFsyoaWwd rrHwy096pttIvCyzhgTln4yzc+1wswhufDg3XTsPO9q8EIoYF/RFlyuN5zTwWHocftoNG/QoHjAj hpwdxDn0y9KbBRQU/5rw74Qnfke5PYO7MRI11bDl1fI3UieQrsp+HJnPTLuSMz1ieMd3HcWNJACs ZbSy1KhJ+tv1NNKTRPJAUKgTkLMYRr+aZCiMC+KGlAKUxZX1ndNtcuhRDVfa5f3B2iPsG+qc7NuI yJrRKBJGlBBWgiJv4Co9WCdOwttrik+wgqJWZyeMcmUoKCs8/AIvAy3sbNsW4N3/GjFI/0lIxSpd ItGj1Z+pUFyCIIpPRTHFQRcRm07p5uFuhSHELhFkFvxscqpIbEB9Ng75WwEBG7a4vbCMXFZpFxYT epaqgNKjjIiYwqNKx/DU69JF5YbDiCR/4JWoooIa3PaYSdJE2kvUll+TWQST539Ii1MiP8QG5MxO 0bVuSDKPNTcqkj0Aj2syOtmz4kVCC4Brzp0xfI5hTivhfYFWiQLS5GqBYTBJsTPySfRISLVclt8u qwVw9l9S4FXoaRnrFuoBUkuIddEqd+5FA55UVoVpnKq4lYFMgZjFN9kaPWDiGPXAQ6Bd/bhgOXrI fFFLF2sLX85L7XHRKrX+SiOHUcJqyzrRwvczZWJaOQFX4RFt9RggV8l/wfRtamDrGD0MLpdmJxc4 MTk+UI9uiG8uRr0QjHLYFn+CrFuOziTCQ62/WOZq2vpXK/NDzbVmKjaokoOsrPGQQ+0QErxNZEzD 2107GtyOJXydThb9SiKoarF/A3YE2ADKiHqaQw9nfPIlSs5Y7BUjPzvNIW3NhIm4yLYo64IjGx63 RHoGwTFTnaR5rcKIpcUVyW7nW8z8jiruF9jrG1guiKNTYz3861J1FKtcUgq1hxKKNqsVnY8X5fuP sRckrs28ALjk7KEaWHof2meccy9guHmXoyVZ61x23giwoHPVomxrGKZN+lqAoUOUVpWes0UL3wdE BAKv99xTg684Wm2kjQmQMJADrb3jTR8frwSb+7uVuUI9/fcIm6PJnSrWEQWbMEuy/Mi8NpgJCoHX 6DN4PSy1QGzw983Po50iPBQYRSrE/0olX1sV8vfH2cFDprUCvH014jYTIerWzol7Z7O0U6c+mgsa c2cHyLx8Q7ndNCl7Sqas6OMP/MK4qxa4vwMhLK2g9qHKBZC4pcxQlEgnjlW4RNZ4VjU9LAMG93AI AmsoEw2BGOcl2eL8loD9jDZDPcdBn6LWsDjzs64b7I4ioSqfXvs3k3NSbmnBLI2AqR+N2bO+QdBn ouAgYXPCXKAmF6yupxGvTN7WBgtkLlUi9gBf55SF7gu9seZUlfHjcBeFcgr76zpI3+BWgwcU6Nle xOVkO4T+a2MWhZKYjgnGa2bshIoORVX4uUFqTbNyZ/vlNhUuozQ22hnW2t9CxgcvekHdzQYxtTv9 A6VR4oKQ6w1D/cXWVKLC8zcmhxIygd88jxI6xNwav9oUa0LVC1omPq4Mm8gKxsOxqbKneb4jMp0x BqNGmIwlKA3mtWzVlLkcX3Uf0d7E5VO1f5qACO9yDDSHcDGd2Wvcon6Oj4UEhV3jaw4fEwCelrxr yD3SA4G7awdIapKqEnqmg79M8/0FNnnzeMoxpFYgek4a+1pfxrA+nq54Ql4YYcitQcL0zEn864+F 3BR5tc7EzxtJJdCxTJfiFCaxAc73a6iyT3A9RVcKhXUAYnyy3LeH2dD3aY5T51XiCz8EtufKlO3Q SR7QiVUQEJJVu75+ivJIjdxMScFv9ufpIJtswuBNe+Q0qUBk4/kBNDlMwz+krZsO0aMEQUTSStLr 0xOsizwHcPmTMI/0GbHs6nymkGI0CMGMvYHmgHDAGVhdIfqx9vwxt8Y64nqhZm9GOw0u+vuEV4Ea k4YPgZgKaieZCN4vdEfaeUw4We0rf82C73+yYrM+ai8RVgZnHO4LdQbNpaoMK+j2o5dsKXmIP5E0 9lK1/oVW7p3kLzouq44ca+cv6JXeLx521lM6a/AaWUwk6pP34rlyQbZEqeyK8arasWkDH8RX0xok 90kfHhMECiX0SiAfspCnceUL6zYGrKVxl/AeRDPCwv4RzzskFpJaiB/MbqOGdYEr00UFqwk+dogp aAlvG6V5d4tn43WtBno/XRyEHM/GqmdV2nM81Vavbyr1hmuCx7MVGhV2oG+xT7Ombt/I2A46THWr aS/QNo9hOMjp1P6CTCKh02LDhmZa2AQWh83wkUvXUbGAi6nGbuybX5AltGenoOZ42AnNgiG/qUW3 8ary4v5xwcquv4soEGXevNb06/zYTymc0pHGqrD14JtqiU+OcjOMLOXQ9DW5WdNSsJbZ9pZw4T70 v7YE8ykwxcKM9E36LDr6CHV11gYNxMmmCDlg/b01qNypc3SBl04Bds04Na+havGh28cXo0WvrOEc 0+7Mpzuy+d/LiRspwAD9lLWlZoLHzVgzfOYDvgmp48CyazfuqgUrSz6MUWuPv98TR2hAid8bS+bj jBeWzHVELwuRPoqgu6KS/k+19wIllqN8TEmP/HhVP6iN/dSCafdk3P9HWc+kpPsOL+OeeE3yjbGG 9qq3tiGkce3TCVSez4ZSHXbIsjcrWX41BGa4pHrGr9u6a25s+SFH+DUImiZPWkWrT2JE8Xo4q04g o+Chj5g+Drfx4QGvexVFuHNgBGv21wMk96Ptp99JVLvWh6/OWbq86Ud0GjX3j0u2cC1oauTozPZ5 zbQk6Ivu9Nz4Y7ICDZsxr1b+jAcfOVlDtqepx1tkfUuj68bAP7tMyr0BGoaEfGGe3XZ1zOjC4uJT QB/szV7kRoVLuCQ3ouHbjPG7M2B40WcAAlETb+kU/PNMyJ8beOKhA7IMo7UHn/gduh7ZVC/Cx6pA Ng1925AEzpvDYPaDwUtEPBjYKpuBv8Xxn4F8eRXcUvLXKVE5bopRB45nyKBDkYjPDUG8ymQyKFP9 FBL9uZoRYaKMX9/n8KVsDx6v8aHfx+zQvL3KVv2lJwezyduafyFo39W79MRrghrzhE4bVEnNhrny ksz504Njqpav+1YkGF1+X7xxExQHgIQIXgC87ftHBZ/cdq5tPJGa+ENOj7ZkHZuXegCmSubbJxBL 0fZD58vNg649RXTaxISphBkIQs1F6n9ViZMYmgPpJyvRKez73eXOEVd7pu81R7ogDGj5pu3wXCRa Hz5J9r0C60JWonWzN/6kJLkXALT1/VU75oWvsRHys6oWtJNcZL5Pa3jjGGL4V8OBO1PTknwIa4qo eiPioCWFsAXdzXovWn9vcgf4Zs7+nKkVM2Z6UPU5hydJc69l5Z6CBB+zfaRImmwQYcXUD6YLTknc VV78OQWkQ3WS2NaIx/XLJQ61eBLZjVV9BPH/W3WW7Lmx5gNXnpDy2ZIn5aeM7MEA8uakgufgcnWE ggWDTiVVYslUJJRheRl+mGhE5ccBn/qSV6If2TGNjRd4z5Gj9TOP/4FGcl5Pc/mAxejOaRBUvQKn WlZExMEkO0NJmkKTsKbMIkg9/oe0Zu9LF4ldkj0NjAknlKELmqDJcqaJEz7VTMzdA3+WuzWpt1DL urY7zX50QZRv/U8mTknC/8rm3sfLMypz0RMlU0SM2UBj4QTHgmbjGTnHJZRy9P1S2Ju7Rq7CmvT9 ymt9eORwDuTh5D3Hz6ZrLyJuVxQHLwiuYmRNB0XoE5Q6M5N/Gi7EoVUjczIRyv1yBMrOM25BHuYR AJbXNk5LRZE5zQrZwR4N2L+XXj6jDwB44MS1Cydj6gvaz8bK6kU/Izq19j4Im9Q2RnK+Za1IMcqk 2HRMRXB4VbZcavKBxaKXgXwriV6WjvsvETWWb931dbAbCnQmktEOvxsjYq/bJ56KXqSWo+LL5mJJ KHwBqSM/hnxZO+JFmEFQZObwLWxOtJgnOhD7fC4FZ7sRSylHnSPx0SDInTeKMbuHBffm07JKyhFE rDh+mVgNcoZTtp28LYfF3HRdYSPQNzHP2ZKd8zJkNtefaPhtdW2KgtEfFaUeyngTOXkk26U5XAi9 bfWuikWh3/2VlFw2tRlgsJet7gi57fk3+Go8D349vaSgNZHBlMBEFXrSDs2XUBcM8A6lItK4j79P /D+Vu/4+WroKYtvuMJH6HDHcapHioY7wwq4anafc53auGSZqUdgPNTBmf0UxmXQBWBUdRtS/8dz6 6ySsS3kNwgmnFbGIzJdQg9Gs0UiNKIaj7b5iDQ6YMz9g44B0/0sETYzZdAspZWLSPyC7oSpIad4X aZvTmHX7XOMicfiQlYKK8fV5Nvz7OLjUtZTFbkspC498b6WOnN/PJOV8TrcDk3yTynf4geKNmusl dWMhFF2yUuDfGUt5mH6oq6IiZDFaqAhLo/tVx4bq5Q/XR8Xxt34smje0gM/M6xXj2Q+uJRoIxth/ U4hGcLv/qVpOadauHo/m2C2fPDNTr44KzzJjHKTt36W6nd14lxQxUx6I8p7xhUbzasRbVROIU216 Zjd4cWagdfnEFuNPlAYufh0+Y6aXSWoyW4fqnJOtYHFKsZIBl48KzhI4cdj+Ph+RIh/7tpCaTlIc WrobB7vGyY9mUF3sdpPZzhP7wEpq08mN2E1s0up5WsiXkEykn1wS0ALSDWqXDUhywh54pre+rLdn I8KlOLtJsMDa1MdDXpZ5Z2lZfPWwH5RV29TTrnafFb4QVuR0Jt2RYHQ3c0QSp+qmPKQGmV/i9EVl GQMlD+UnjI/I9i95z1r3YH54XLpduSKjWE0BytUzRw6fHg5IrR3gnze21t1FKkesU5E8hJziDJyV FbXlCgc4iVq+KpUzlIEUWtIn7KGJm2hmWjyyqvLaLakoY3l6347sTYWdXa1pUbKhxE1r7P0++odb ++a+gQDboUN+7cvYUN0MHbWMCYDZzfXh9g3QkvNLfgHRgyvx5GRwVJ2OON0k+YLiyWXpFif0uDvP CK5xSXiU9V/n2gSikSFkaKPb5e8F+c/RnCcZov+JWT4cZeijwyIAIinF2NXWhVXN/z0KIZvOpQGs vFZ0NMMmWYFxCql9QZbKHpM4zLomRV3wLgPjDtrkfN9+CLhvdUxMFEvKvwqQpxuTkjwVKqyVm9S1 NLx9Cd2a+9eGv+NtzFy7AkmMApF5Cowi8MKID3nzCYSLAalSuO2/AADcefrazK/LbjlNOcj34MOL ix+1aJGKZAIPc8W+TU+4ONT+cSc0AiIvabr6KJqFZ6gE3ICYIK1pGpMSTBssjnuNjFp+or7kx5qi xyzv3LfmFBToAoWIdotHn+YleTGsJRezYACFCe21/6sIBSOhV83dXa2iU9XdBn/ciN5tujeYXXzO mmz356/ShKmhKKRIJr2/QcZf4hkqlYQzxLMGCkyoUZnvYh1zNjO53RxTeI5QCKq7umE/qjsJT4dK VNsQisvaTLYsczgE/lYzkgF35SHC250wXWeSk88360TtNrwPzARi3xTkODRkwSjtreq685mrDJR6 YbJhK568ask1siUt3HsP+yk+MjNVaNlw1olkgDEu4kQ4zSCUQpyhhpH/jEYo76L9qGAWsAQKgCyy rk10d7zogFVmXHy1V82067SqBSFcvbpqgTs4G7+Oibi5zNyGztYCV4KdpwTjSqUW0z4Em5Yz8kRO RrecgObch6UsQkuWAapVDJTdR4WZSE6sQ9XOPMRxv5tMzAcsCeRRABxFmK/NGzrqdYiBVu4yRaQd sBWELOjxswigRfFGFPD8wDYCJLGMpU2Bpu6JQs8cwwzfH3Pv6MvEKKL/ro7bpOO1ycFD5EheP8At 7hEejaR8vZhlYbb/eJJ5fJB3Dtywe+29Jn3q7n3VPvwV1SQReH86Vp/6uWu1qBhKLVnGeiH56uBy FtkhPSUCpuZGxAsVDjfle0qosKFXASDCEl69GtTheGXer/6axZ7DJJgEJBssWZoZr6drYyfVGNZ0 356MoK2m/tRWV+s9uiJYahrPKJ6rxN3uP2Z0O6xi0PvuiJYpxTZpca+e07cs4C3jwkLcXj/dVbiS Q3q9Ck5zISNAmMQNX9Qgz2gFjsP+jo06ynmmTMdnG0tmcrl8Ojt2rn/pAtGEZBSrIGk/Mxh7PASI VP/XB/khZ2B3ADHz3cMi1WhlPlLtZGTHFrpE7jqzyKmUx5HhhDkIO/nPKwIZ8KWKKqGryuG6n23l mN6g7Bon3RXNejCHkp5QfP6+PIGQyevmOmF4sZzd0BvgQX7f+UfDzm3Y4JImte3G0ck1uWUlCwqQ k07xiq3n3kMs/CLl5mslJLPaPbyJlt5qz0C2H9huRCLifi1oqFIuikZJp6zGKk9737993qv/6UuU 1fuTtmspLKXyZoZrG5nY4Mb0lAz/aw4yYDXdGNuaL7gKVP6KGGqJH5u69HJtvHEzQ3tHVAiKbrzt vcSQ+ClSrmH5faSy8x4+S5XnV4lrCUJ7jmyfhat+EyejEjlJPWfOgEx4AWQmDgjFh5rRLhc5HtCa sBrKxSzsNc7DAIvtQUUPumEmLbI03ZpIfWivLPLiwTo6EMf6GG41pt0NAgxBFiOf5tYmFIYpgilX u5Ijwu/DGbEHFRuITtUpyK64Y9OobLuKqCJSLm/lJZfd0oq8CYN4Ecplt8ze5eZvsukDdwhSmcDH HLBDm72AlDMHhBWE05+TlAGTmtZBZoYqv+0mD9K3gLbEO7VK57+7BKvq2Xj3YLOtRs/6YSnrPs5p yjPxIHhWfsrDCsPxmLF2qS3CcjQ+TMpyfUnvD9J1Z4FUDcp8FL4miVrmDi7s263lHQDd7sTmP7m8 UO7mF3QHIPi+0algmffCgy87qI+X8Y3MOop64pJKaXO6FXJ+J5QVKOabMFoMA3EuBBpQ8XA5HT+t GesF3QE0X/GLEp7dh/nJS96cD2VC0H/H+Lf4EcaoaIIAj2gxbfXP+Gk5WOdiIsreBLTo3QO/j7bj fpMrBR05qR4O1O+FhIlZ1WyMX4+kDgOkKitKFsz2IMSjxOtdaiO200suHYTbCUh6DzstUsi3V9S8 Bx/Hr+SaZyTJauryUPiJhZ5ISTik55eut/ClILZiGRptlvmovrWuGFon6Paey6nr57V7IyWOnyxr aczldhNm0ncrilyyJ4L288ELGgUO7L0bTPzJsmG4+zpLwvHb3Mj9mXd1yV1VxR+Vr3w5u7p2Ziy9 sMiGAKbaV/u0d1UUPXjqwmFlWIkDX/yA11m+LflD4R6TcIdlniVNx9nBUbLWfoco7h38pgSbZgG+ ZEv+UU3W+a7l9M3ohM37iFUSP9YiUjkly3kibYQGZk4SQDh6OExlzKsY7cQfekbpgPzXn5V389Qi pfUl9SmT9uiMfzrOwQDmFSEMCjXmChyTLlQgoG3x70TtHkr4qJtMxoQS5l+qKU5Rqr/afLOTTFOm aBv+jeopfJjKGL/8t55i87aXb6ne5MkZVm+uww5fKeUm0OznGYxHSvF3LpgYMRcrGqNOq2X0fIY3 VKVWUweYtr/pxGpu+aGXrfVOJT7DznuBAY+KB/yEaxN502bwseTgl0lPko4sxvA9HnWUTFLve8IE OL7rnCCpk48/xVwV/YYsqwZBuETm9JtAFNrBbHVzhpW+lE4R5SxQM4ssFIo83tfNcpsie7OfTW16 pIZnL+KTMHBygP1vYPI3DMBGv3u+uQmdkv8EvGxDIZV5uEglxzdbSqdDtoMqk/tFsf4O2HVDkJee LzBqp6ptd2wFyUmKlqnsUQ2DubldMZNjm7XJyjm1hHR6sKR9aFVWONyC4fGtNoKeU2dz7R27oRsn Cc117gLPOT2PU45PSXv0LTZXMU46GLp5XXZZnSjQs1nV1Zb2aIO5ds04pC/fWuNYT6zM8aCL49I3 TwmffZnib3Z3oS3VWu0+YhAytEkHRJGIhHtGZCEsHnQRbcDe8GNI8VeLwEq7SsXgaOFih2np+V4o aygvXi2zxHzks4qJVQyackvxxkXGAKTeMlQQiVKhfQ/c7XANcoKy8+pY7neYWRxYnPAQmGxZZp6H 60+wfC6AyE37DZoyNk7oR9h3GQBwWBBUAutAdjMawGPbyboeYu13cuAXK9XiksW/VQ6/5fCvqnT3 4tP0A8ewgwwfRtiTr5hu6JvLN8ieMzj2O1bnUJTw35332vH0asI0rkbF3Twwj208ofPCJwfuiPUz /Z4Dh2FzkULxN7rN3lonu7L2qotS/4AnA6Qn99dq+dgRhKgVm1W83EufuQePGzemL+4+NvJAk8Fr RYk0ddrmWCQnrLZxYjMWABvJ3JnpRGXxV4TwEcvAO3Vv3wTxoep66XNyUzO68bvZ2m6tvqsPpNNd /gK64mYTN7+Dd+e3LI16pEuRMtg58CBVHSmFU7BqKCCqTh7RzazPLMwk+m7NNupTXaJzw4O/KKYf 1xjLA2hLw/Rvqj43bGCVoTmhKTIeLf3JkFsBNrhZvjqh7HqDMqbhTU79OYP+d5X0VLqg9V65m2jQ G6qZinlHBxDRVQm5cWy6dKfssfDDQwB+5AHbipFdeG9w99bo2lTZuQ26Xgkgedsv9A2JQ6NYW+9M 1Pz54UfP2E46PcXEKrQcP4FuFrYS9omz4StLhjHErlZr0tnOwMBQjcTQL2ZlzCYBKZWo+9/ggaG5 lShs1DzMo+gIHebpY3b6U3F+Xl+/pIXntnNbWXUnBgrJhzRb925yCo2D5aYLp154CdoVOgKjEx7j /zxb0VJZEIovxCY86sQAE0efbSJADN4utO4Q8cX4jRK565p9mNOgvCB1z+uPvr2UKqR68pNsO7GI PK+spAhvt/ybtESupj6t16TW/wGdZnBe4BrmL5Ttyygx1CU1GDosxia1IP1qtF/tYZUrpO+eJRVN k7m6LHlpKTMiq0ANrLMoP40wDPIWraKht7n4N56q1vmM0mO6Op6EtsC1KuDNQ24VcMDk0fDcMRgC AYWR8o/Zr21NZtdEJoXentPwfqQ53uvo3yip3/x/qxZoDiTsO4xCbYeNJAWjCracsHNnaxZnPaCG vbeWRajrWOe2V6FyUsZnSFDvLbWLysWg/qEwYrXWRrykd0IVp0b7JXr/a27rBn2vYGspJG2UH4KU qqOGhN3Y7HRHvBMUp+KS7phVhmDI59aDwJKcXABEDb6gLvRaK0wnOD98/+3mgBin3QBQHGiFT5cN aA9anutmZurFaMX+RHaBsy1EUgMEPF/zpZB+O1orbjwXEGSpXuTBQyg/WyPG2LpgestfZ18EKM8r Y5uqwy/Pgkfp6+LMWxuxyYhtZq7tsn/teA+ATJyazp6KDXAqw8d4A1wf85RZXeslLfskZmTe/01q gKVK/2eqo4zgqfAiqAeNRKItcH7pZZwtG8GV2ohr+e7uE52nzS8xGKZOdT3LvMhJSTFvLNDVGU3D CXGLgrVWicYkHR+VclSUJK3/7bSxCaxRbV0gGtMwJJo8mi+E+G4W7DXR6icwdoIiI2wlj6GSmUDF zW88sut8YABw+x0y4HHdj/AgF33tbFbcYNOakb5tCj4BRl4eJuFie7yBQiTKAmWDO5m9jsIDzzmE t+vBtYpAjYpl/LnQvy6dB2BnGzVletnVoibkqRamCT9ienUXFSviawbwyTweviwmb7a1kPpn1G49 813GwiYLGuXp/k8tCehH1G9nxQkf38qvlrLJnBJhxEVXwoWMSM8b2HUu5FSy3OUu/F8Ncmd3xdEO x4+AtSCZ8SZTVR29vz7dcecUfMev8/AyKdZno+Wlex7hrJiovenU22VOkWITj8D3+dbnrdB8GncA Y24298LLwAnL34tMS6aVggZdZ8mDFlNnKC4P6TyGK3S6FqgxDx3c7TuIrCOSZGQVgcB6UpS/gFDo WtHcfzaK1zleCLFLgBfk3JbwHoVyl8r3WDVuH4NrYjmzykJlftxyFsX0YnDwhuB0jlt85BhAtvIR JQiN1GIUAWWSd9yvVwTTgdjbfv5fOXdzYDwNFJT2wuLk7jGyZNK1Jzl8ZW3d2yRlPrxTEaCtdkQW Zb09LLxYTP7FuNuVsY+TbGhLVpJpTjDqjYGNd6df9DTDJLeA3quGqQAfRZgr4emkxXMAB9EucJzX mZFLFu0aIzVZlegIg0WZTaBjq0vTdEloaaTCF55iBlGoTNMTi7RlYm7CLScEi7iMlXWylfJYeu50 gTQx5m6CBWsjHeC06rwQtO5BttRurtbp5WvnhNUeGGv166L5koVrxNwtRljjS/Ox2XmKeE1aHCD0 zPABWAcfVcO6r9Cdo1/2vslp47sohO2rZX16meyP4kisQHfJj+jTMW73ub66NQFB2X3dCDveVQY5 zGHkTrXXFOTf0XbeuRwUgMGWrYA4i38kj+bjdIZG9TDDGklFK+7aBn9eyYQWs316q4/vweUADdxV N1VJwo1JPskg80RySh8CCDngxF8nOph8O0FRT9r8LzubTCb4fQ9moUrcEDcM+871llqxL2zqYZuD 2TAXrp6APq8izg54AMtPUVPQy9KH9CBMM1EUTTAn6L4S3IhgremWbZoaRmyCd0Vkl/mpfv5zvW+o lDw3E41PMyj/sBVYfu65kbbCqzUYFqkIDIduPtV1xsdbeaxYeStvA0ujb2fivBu952jhgmVzDLv1 6FP8zSqvPN56QD8R2x01NXjLvNS52qvWJeL7jxobgM/bKvIVlFPuLotM8z65+wHJN6Fsk2cCrm8R mip19KCtuSEoajSpQtqLBCL8vpUYYc05kOrHnWkRVA8Sr8rqbWZW5stK3FZoFTIxyGN8UhDSezIf 9Z5uUB/PzbGE4APgCOmZUoZo9octw4HgXZgk3nhv2DTgCJmCmR17oH1HXXOsz6L0m57Eft0hacsH A8reA2GJ3L6nZTqLgLEbFQS5VHaHwXeATTd1v8zQB1jeiWtbwHyfb2FXq7ZlUQHoHp8SKBa+Dj7n ZhlC5PoIh8GuUZa0V2AH/aB/C3M9wTbPksxYxBkNYEo9ySKXBETMJPcyzvCQvGmy95MGSeGOLWJm YDacHt/IhS4YAGEWDqMzb0BGNqPaJEu/JRs+puB6WQ2ko4OKMpqN9jdSW0Hgl6GAMborBM5Sf7Eh Pj46Z6/DS1GP0yzvQR5fGCTFjjetC28ehc8+1Zy1VXRv0wGmKYX5xCiUrsGBNYypo9dDPCDbY1F9 n6xH92Q7ekvEz5bKBe/NPv0gVhJPGo3aUlNQdcGg+Uf+Y7tC9Fc01fDMGq0g0rnstmFg7P61SOo/ FxhUDX6Rix4THORUAJeWyBA111Z/hqojlbDLKZdthdB4bd147Yv+qGCajMoxqurC7nsOGafg1bF3 yhZYenn9C2McD3faZRLBwoioVdZw/J8AxUuwsRpHaKNWhaOdnuvfPO+7LlTRPFQ7pm8zSfrLO5A6 RN0AdMbdgNigktYOpyXYesBpgzcd290c5w7gKUiUU2z0KzdgV2HyQHRJcyRShYK6vfKwoYZeekxw vhQRpuIELLG10+6EKoNNOAS8YgGFEKSqCT8hqGLhfjR+8zy2fyINicapHQQYoSE9BIeiv1jt54gW JFz3bMnn/PmAKdfK60HCr6aaREAcaETevL3LxdHlCfoDXumbbK75QsacKzroZT89OlmjZueMX1V8 q676Gdc70HVdUXa3ywB6LkBpuCt2ugsnEljtm/ck9dJRz/xn8okOfP8D2Pz/F344mrHE/pFdIKFG MDxFNob7Q/H3eL6oelHDOTRhEinqmm+RDjdrNqWNG0ZIS9gcrBH5fUyIpU80k0VQA+rfJrB81Ht9 N2Rxcf42nk3luemLGgGfhQLDOvLOVPIVWRSvWuu1GwCMMZoUPL1t0glom2LIR1VgxYF+yGmtmmOs 3Z4Tapc3/ptJ/R6O7kCHawSYxWIn+9PPOSMm5V1U0AYj5PpjojcxtKOJ1Ty2wJoyw1ZvDtDvZrQY 4ULQ9/XYg4NOpUcpsgfjNt1XZUEtuCtQuMZNYTihTfc49vSWuImHFvjOJX168Py2wMnhccey9mf1 yy8dN2cgb4OyCMSpyBUwPB74xM4vJrfJsGhbxZxg43LxPd8DKJAjOcvtdQfbYWXxw1SdtmRcou4p Gd9glD4BhSBUloBnQCn8fbtaYWu2r8kEzwrzIaFOe3AvN+v8xFokxFUn38hk1UvYG+3DM4kiVz3Q 5lviQ9BKCHxf56koxLHsPsx3qE430ZX9gtmXBBUW72xlhLc9Pjbx3RnyYrKK7ObJh9n6ECqvaQCQ RUwPP+ggWRzlz0u3fMNfUOD+pFALiH/lYKh/C5CzpvsuQSGKTRMcMqxKcTyF+06SsKe8P047pdl2 cEqwV7RvWmtFy0pfaaypscuJiD8cB+L+iwiyZiIZgNC0NEDUdF+cm3qcKnns3U1bh2ivsfTKlSQ7 Xlk22vV295XrQ+GAe8393DxVCAeRSb1gOeaQZTDhR1lDnbLSkAToy/xs8wRUdkvcPJKYb1CvZUMm p4IFuRuchy6oSuYKcI+A4i5yJzxIrXiUjGRFS456ux5ALt4AGLZl1EMw3DH3xcO2/AFzFcbnMsVB NyCUv+6M+x6faQO2gZxIOLaxE4O2Zca6mjHJViwG+qeEXV5GyoIFwmPvlJ+DjCUHKVUFaSwXr9PT kYEh7KSeIlfDqxsAb4Z7lFM14vMUdeFo1+ClBRacA7uP+rO0/M5rCwy6hM72OD+MQYXmRijfSae7 lQrhDs8QgZ7rYgQXTj8MidZul6IR15qQwn0CHIBtzt/klEh58hgW4yIN3DRd1rXYVSC2ElLryg+B CAgiQjgyUkNGWEK/oykbqIZRnXtqIfmxBLxQKypAEwSfYqAvFzesS1PI3toxOKmiesN+Vby06hqj LPT+cPGQCjUTjEHMj21cX1AhqJpYEzpetxSyBJK4RHJbXY1c4gEPhrEh20mp091JPZHKNVUF32EY EaG7ynA6R2D92Awva7phWPJSpQm/pNpxp+XcqeTxRdgN/Q4csluXdLlThfIQMb45zJVJqh2bBgcQ rsSkx46FsdyU1JIlL0bsDgA0hme0r+RmedVk1fXiJ4dOwja9O7SeMZkJ2Np1sJWeGDOAyHZfz02q 6Q1kc6Ev0YCNWV7h98inYybSte49uMk9QHkoWPuxOV56xLHYPj7eSIy1K9wKEjryAJJPvJv26tWp f/1BPykGz2YqBRyDsoF4hw7EgPVWqz5VvAzRLWlyTDuw6nLx+29zh1Xf5yDTiVa0WdDTaHNbABnv ObU896jO+BBi2blE9uk50CjaSopAme28oHRSmcJVrLgVvE+fjXkkglJRErnxsPiQT1GNKQNbOWxW rTh/Irz9Z4DHOBqLrJc1gO7jil5xTUmGAmpT4euzij4nXp+J3b+73T/1/3rCdBsXONfH5GTYCjtT JjJAtlZtECk9MAqoc5R8QR6EeLADE4LqjS+JiDA6Ukac//9IOUhP8glGI84rijD4e8LD9DXZ7mwm 6s189OpNQZbk321o/XxxM4E2e/fqKo8xdenXYRf76Nj6DQqvpdP4NN7yAXsYG9708iU4NXHK0eme 8NKM/3b1IWzeqMFBIsdUR2TCSGt/DFq7h64BDYQcWhb3HVzWjgT8w73pfWR4LgwjVT4nTByYojwv 7bvTj10oTINqD0WC0Ub1Lv4a2hiKwcyY12VAmN31WkVR5dSG2267ahtssY89OwMXV7SnqdCK0275 fQaW1C40nGSUdMbP4LTnUXxwPmeEIsyOm5WtB/JOBgjyk+sPaDc2bFsT7P+qGz0B4usTJGcfSjiM wNGZxNHAqmXvTyX9aS+TW0f99ztaVvnqUQXMmOfMybCcxz/l3GC08SdVqDVXacTmpL/BsLTpPYpR N6ySAN/6Rdpz73PxesbTu24MOfTesg7iHIXBkkUCzRd1JB1G7oKYce7u2Hq/vKTuOzXtflVcfs7E Okvk5CR4S+hvKWxfTrS1L2yb5DrBa+VwBCN5Kt3vyoPv5gUymnxW8RHXQyv6A6UbycFPGteHiZHU oGmtmhC0MZXWYIHNMuKjWHDpZ76UgQQdOyoNY45sf5ujoB+VtyqBCEFS3FCU2xbM9E5ahj+SaIxM XJ8mYjwX3hqqTVf4eMaKNyjEWw3i/gRW7Bf3ASyQJzfu0XZ5+OOJ/iUix0O2iy8U8mZ7JX0+w2YV T/bxBzGIZ1a6T06ciupBvoU2h6Fo1qMu/mCr7d46BdiAe2nHravdkV92iKp+MMGzNgQWn/eGVaVa 4Mr/CsQpc58x0IUVo1HOwkF79492ReOjdb4DV9KprcXsnGncPNs9z5Wf/5p55Cf1ZR0FIoSeTTFJ mGyHEMIYClSnnQan8YgV+fSrsPkdLWI27kpfAgeZHnMHaFcqTjQb0ixDOxmxU70RkSjM+Fisqp5M PYtY7RcLy1fKp9tPJnkeoDdiJp7Bf7Ru5iTbh24/ybmiU8BFqrzblmOUlV8IZlmSGAG3todAl5RK m9hLs1sFmjhWMnS4p5hU3E3NBm16WurQWZy14/sDYkCkdbJ+8Uqn8BdU0Erycwb7AS1PZvV42Czr JWF0UcOwxVS0ftofXrBcT1T+wQeWCkQEnhhFycm/Q393i6wimm47kSRGLv2tJpg1weIUefxPluAn gQa+4+xs8fDUzVEhaZ8xsvE4wnquVya6RCmmZgmMwJTojgDAxhxCeQI1XoSp7XHweDSjwLHI7k5i di7k1p0jii4LdK8hkOtEhH+i6x493uNHVaNG03H+Z9JG/AapX5wLHBM+1lP8LVIJLCdECNoCtttM 5RUMB5uQpn5i0ApT2gyMvmZLOSSsoQQg8XJSuSPhogBveArWCSQbuIDfNxb7nUZdcqyYaY6cTDq+ BoPkga2NT14+GRvcNt1Yl8/OvNiBa1EmF0oOaxoHrzOwU5faePKeYEUvXOfWo4T6/zzVMbjD5cPa eHY4HhbQOJoTHCAhCBKxkr1mzCOc4+kRR9djDCbC11R60ZPIHHUk3l5Bim4FqbwbiVyJm4Kr13Kt cfIM2eLafSj6nlv3Gw+N6dNq+eBXft+kFPain2c0q2BYonpck9HtQFfmBH6l1q9df7kk7AhmxCcB cKi40GFYaskQlcZMNtpKA4ZajTeL4gyzCy4gg0jR46Ch7EB6k18Yt0eL1Vkf57u4+MnxMi37H3HZ J5W7dl5b+HoXW9Kn5P6gXZHaDIrSm5PGpV2tbU/feHpxAIzS9ZEaFMlPTxqsw9OawQa3DJK/wzuZ 6YWIYS1iIkcjenNf7zqZ0le28XPyfAbG7/v3d3r1HbQ3m76aAczHGio4HzzyFHmzqwz+6qMbu2rv Nn6vn6CtZ2hSRWLfk7i69K92GLOqsmCCDUSG+A5ChJ8GL9BkfOHs1II1UbYEQ375BZqsyh+ezWEl 44eVzCR1w5yztS9leDBK0o/+9aU1m3ZdjHMolcuPc46rtdqgT47eeeTd8uzNhMWTS5rBe1JmqCLY tDasL495IwOW9x1cwJG/zg5e6Z7IqJCVm+9ofB6xiDLaTvXqW8Hn62mVu7n7mutkrmR7ERD/GJTw J8b/K8124UKYqSz7uqWa+a7gxtoEJl9Pax9MCxb1mNFboSaR7HQBZSgYesKfgKY+CxhwBSxgFVT9 IDJRYEOCoWLLXCmQzm0Sh6Z4w+P++Y7XfeFBBTDtNhqh0RYgGuOYgtBa9x8mUJikidc3Wu5TKrgU jrkb4Hvs/cySh3s4Hb1OwDfmLwYSl2NjilslnoZB0XqLDDXYpcp5LidHujMIxxymjhoPm+rk8R/t kh5hs39zm4jiB+F56291GDnMxrv87yU4d2dDyuyTRrfUc8ApxQs13c62QsjRSLJL3y34xQ2zHQGP aZzBt4JwalVmU2rzxHlriJ5FHGiTW3lNxQD93QvcFdCfOMOCHa6hoB6bzmcG2aC+46lj/pQRL9B2 ka4JXl3OFLK8bFG2Gly8OEorHBkN4nb+R69DMkMLBuUiqqDcemKCzIg/4SsUXojz7akuvDVv0Xo7 Qsp5ybyutzhtUykQqTfdmSmWkMmrQtkm9zIw1k1BtI4CmOxlWDpU+YxvWihmQ6U6uDoveAEUNRpy 3von7KmYEeXDeFqErnPoTzM/t9I+euU9Ns6mOUd1pK+t+67yjUYUCXt4M51aWaZ7Svqhg/nYN4V5 RtT/Z8+tY0SBRoM//VQobrqadn3R1nvIxyT+jWfzvTn6ZC66Fvchv74QeOcJVKgwfWLa4w5jifow GRzTYHnoji8heU2dZEdTtBccWye9VaHDwT6evyVVYVuqHw3H83RmnFDre3BJNRnga6UznC2PgFtK 8GJ2vXNgKcZi5jTSUOL3R7ZwPCK+atfdpx0gUnugQL7l66oWE98VT/Lkb2cP3/d3pf/jY+TPejjx WRu+/FA7rp9bcueEoUB6z4jEsmVboTAhfnLUh0iH07eTyWJF0z1wPs93jvjlkXyjVo+Mwh0JzjqT 5pOhnbQlGQ6XNGpJeO+hF8BvpBKZstlm2k3ozyWFC/D1IHlmIfuwHoVLblekJqLrup+E/zQwjgHY FiSh3hokXUG05nKCCQMqX07h+lV/547qT1gsR9UEwmCpb+OK7nHhMsBPIu6B8y4YS8SMWi7g+vJw cYeCToff+opf3F7eQFDuGmqNVN27rSQKIUOSZ6SDQ6OGf1zmpnxJ/4JIaX7qyEPafUBA8fqGg7JF 7ERWwk6+Eb9R9Z0tS9lF3giv6QN9tMPPzBGCwI8HNYNDAhchunk0UUgpGD0BUZBeJraJpVecoOvo T9/PqSyFhbQpYUCctdEMINLjUCo5/ESQ9P6YgKp6S80IkX7gfsAcCK3AZXdetQ58Duls2PwoS6Cn KVyHZZbeVvBFOGJ5yQmnV9tVeJbkKG02PxDzRm8B5R8a07hJB3tsLpfMd3bLKAXuJox8vvQhEAuy oJ691jf+tiNJjWOFVCTSUB1F/QqNfKxahBV8cCVijKji8uwXgX/r9APf9XaUIF3v+QIcl0Ri8Gs6 aZO9tngSiVgdH6YgJp18q4LQVz8/7G9Ui+nOt28WhH0Iicy6pFaLRBux/VJN597LwBhKDT0ieeFP 4hdfWRSMsqmg3Mr7K2gihMIvb8ex1F4wLi8Uv9nJkKuthgwyR16jNxxxK7IcG6Tt2HmxHjiaDiCD n6TckOnAoZKGDfy7HxYlPxLQ4KKpaTkB0po7GjFB707Sr9UF08O3RZAbBRWG4koY0akjN30tNmKN NBjedHyYQyVLho49FrzSPrsw6hRa+85veJuhqtzVOvKOoaS26rlsiJbcBQf5ZMz5OyVGChzBQYvp F7IgNsS0wnuy9c1XHAbmxk8El16I7DZIALD8WvdFOyOxtZFArkkVWjDFxmVhRkl+j/f9uSXawN1K JZ8u167bVm+IRU/6AA3Fp2Ha1hG8xGO62Y8HBraxHzdrYD2F5FlasHFrZbLNppVRoWdbyH1mq9L/ wZJ1cZH0aTp/YCSofWNr53TC29zFdFNXRFsiWrcse+x2ZMDkAbhAfZZIxvAABGor/S4ilnTlp1Sa KNYS3FoEuxWJstnk31uVdzB4eGbqg76p9cvS1f7biu5H9pTqnawYxcOumj9+2UxVJFElIvm2z4uZ Og4dekt4vn8lJFPWXGVRJ7ovQzTPAs1e3EXFND8PfGy9+2SfU1UdZhtPxpDK4UfJQ57XRn2T4yPX 2aiOFk3HRV5f4iZAiXKmpMhlVTtLAbRbRizIl8yDSDNGnATz2PLZTnPo+rok6zKsqKJ2vvTf9jSH RaZZkfFcj/bxwNTPJSMdA+xUpWGJ7AKFCQmJZf3hQyBk9wASzIXU17mydpQgjo98Aco5UGFQh9FP sqhXEXPKLbm3Pm8xfd+SkT+SALPxw88ddqEeo+lRfF+EHYuoRCFbZStyhl71eT2Qq8u1GKzeHvpz Q4/18ydihzoknOJb1G4BR7+366LtMi61MvCglILUXrwBJgpT9z9jXAXDBPeQecR8kPV0Ar4OjB6h FjeR+tQbke5rcV+ZkeUq6c1QoL1BBcqPaPuXlWcmBvuau8b4pxi+jsZo3HRqatQ/Ku0QhmdCYV70 ViO2tQzESOvqpJGpIKdcuwSmswhfoAzJeaHWRNNig7akPVAhPR8Uey2EI58tGzNwaUS9PmxetEVU qsJc/H03n6/gsHGvpoxu+exQje3ryf5SfFvMYQhO2X1kXmtrTaaytLq2QJwyG5UskyR2qMyrkX2I ENX8hQU8W3YCWWR77clMviuTXNzQwGR/aEiVO6cw87veXSOmd6EEh7HUEHAKhpbfZanVWWaSbC3j t4Y0PAphFsbCv6n1Cmqu4ovqrnL9EWTcc0Uqgli/K0WOL3m5yph85t9FGqzeYteno+cQMSGflG5q Q/KepVayQhHDl4v4hq0+gS4ewVUkt+cS1Uf9kVPRHvtR8xnl+rJ/6imXhTeRgFQTsDPmLSMY3+if y2PMIHgqfJrWxEpJv0ER5QTlY4xMI5nDX/CHUDd26SD+9evrbEFkVbGt8hbXFWFHXivafIiUXFwY IJ0Y2s/sAPlv4C1rf5HIkSf57/YLPW55bj8GuEHi3QjW8H9oct2loixF7GSQ6bDc65s8PDUbgDq9 7M7jPZimZXaAP7z8eQGT+LE59ub0gy6dHJX7mTjIkZNXJlNzBiB++YJABvK15uXtPO8ZZWWV9lLu G7BrmUfeKS2Umz2ndcZmHWuJ2m70muw1PucWsTpPL+9E8ZpesMGTrd3E+ACS9wOgg8IfujY452KM sdM7f7LQ+gIHTEQqWn0f0DmzPnyYB94SUfZWJCjAQy1QgnQQcL9ek0ukmeqJNq12nlbGvwrQLwud xg0WbbOz5WWd/uM9gkf24gtTKGeoxGqzNVzDTELV2vOJD9v4nj7d22n5vXNmBEIVgMZs87BRzT48 vSo1B+DD4Av9NV9T7qJ7vrxxCyY50/p6BL11BWDAMbf6MRk4NKav1w4InLO1bj/Stjj4CLHYwgNu hQB6RyCtrLrfZLzgs/Z9vaBuDB4eG/H62Jj9YUNpmd9XDEzxUdmbuhhBLgDshHVosW7/3dRqgJCs rWYEn3oDyEm3xcLaZw38+qZgrZK49kyavmjzMIXkns1WX6YkKv0LqbaZ0jACk1qv9lOgi7rz6VEI S+glV7ygMfrjZRmiOG0//QonJjMqH3qwgXgrhUyEbTVSj4skRcLvcNjrbsl26KyAx0Diw0p3MSP7 zAJ+enLEobn1HxJszppJv5cip+ybubY9vAmbz8CbaHkmzbdN8oCnaxTqrv3P7x7Z6p9sVrN36GP3 aBzqQwAnpN8ni0nrMhMLF7q54mB62QCOJI3PN44q7maFyp+HxkG59db70l775skjcCmhunqxQq56 qu+DRkfuJq7BwlQSOKZzul8R06MQffjTPovlpd8HJGVAUyv06Azwyw6yubsl9nqKDz4WAkFI27xe OIIKjpdAFP1+ktI/7upX+x6C6t9oDtFvyDS/RKX+FbK4QndCnBgJbBm17Vf6+V5YDXfhf6QlgzBk Lxk8B4TL1MD8UHpZ/FwYp88o8zBPBOamky1gZVv0otutEOS8CHtTTG5oYx3ACpJlhl00KkGXad1I 7bhOprOQ1o7gQEsbOrN2Kw+byJoFwXXFqALv4mjPzzIQCICIoxPlYaszwM9DfvPxjiq6W1b/GeG5 ehhn0HisWl2fJhIRtwIQqqPkI0H/dTUhPjxWgM5j3JKDC10mDPdlCOTSvORFQKc3PNhDuXjT0kVh 8XUMxnxwIFrMtiiZ2lKMRGKmqC5dohC6S+wahgpDqwYLm7TFZrxhq0HXEby4XeuVj/mHNyVhMRs0 UMgM3tkvCrQ8pMk0wIQlvb7Ph/THLUb0IVG5w/T5arC1byrn16F6sGO6U38VTJzRRjrJnh+mMvJr 4MMW+Lb98+NRGJT4p9vYZlM4Mcdpq+bDKBWkAogB19pqyOX5cobAqEtZr0HZZi6ROn9pWJHWzp0k XAJtmfd0+EaHK7h2nNV4wqs2Q+5SkTfDIgF0G7YneMEzPD+nlmG2j2IIESCQK0GpElsc9QhUGKSl CsNAYWcNXGgCEDdJTZy9e9IEp28S3VOdpJwbPrcNALq8U3WCIsavVD8ttufEIlT43skWm4eySlSl nx0PbxYzlAScl/98CrKZKhobNSwvMrcj63x0On+0aB8Du19F+3KV0GW7M4a6Waan5/vUO969pWXr gTlls2fhA7GwBN22WxJTFHG9xPXz6cmtz1LO3nOsD78RZ5pUcnX9a5ZcKmuAQyVfE4u5Wo7g3nrT xE6serj3L2iOp2dbzUWyQpCw7oacreGXDpHuKjIQ8ET6KBASfaBck8X6JjK+xH3rhYhMoE07qmKe bh3FDUR4xhtGLUSSKpwkREbT27n6wLyWFfyKuE4XQslpMOE4pz9GDtWjWOuoC9YOBsa+ACYMAbse RGDTqT5JEMaQPQwnTjLC/4oLxBlmYTPm3G8qnSsbgUJZPFXLxAF/gJEJ+KwoiHpUy1lOt3UBaI4p 2Y7oN5pH7no5dsoYTn/Mdrd5wqWVT82IwBwOsCUWqQloKZ+zlV4ZOfTLchvRQudA6Kw36Nv+kGS4 3hJGNC0ASXlzR5MHwUTsmjuR4vsw5ya7p4Evtzchg29bDIjuaB3oc3oWrMpp1bmcznix0kH7XTWM KaqZ1rTnN3f1ad+lQ2Q8/8CLKg9o+uR9l70WQ6rHGA9BhlAnchVD/noB8DYREi22lAv/SXtymnGh WXjge5L8G1pzsazly6AX68IgKaLNAOCLC+3QxoyFEBXIjdx40VOX8STWsvof2R0HN6hwJpGkvFDv Gfy5ioCsJ49s2GJ/WFWvEAeFXiQFOss94v9MRSxuJBboIfniC3j8PS7WN9HXMeZHN4QIejHuqCpV /yMWw6ewekk9Q8bxRsVsThBsebPOX+G+z//yZM+i2Od+GbrDfiWtmRi7XGvYDuk+SU33RDIkhK8u dhx58Uz5v7b/MVRHN3iSp7jLJ/N6bZRspVmV7Gf1XThcReXO4Yl/kyeB09pvPjNAtRBNar9mYlEM GdwbQkCfp642VqbKkKteJJz+7AzaUZhKF5OT21E671e+7g2Vr0cUnAuXd67pNxCVyVgvB13vRW1O PQeXLEVjQkN7V4BtJg3ASTWYKWjiJZKe5YhLBgUxBmRkST0Ul0ty+XJGjX21yVHdhEvWH+g51kQ+ jEbdmK8qLFO1s85u0FdGt8V7x3U6K+6UIKP43rdiDw3xi7UDv5xCPCvn0M8tJwjvEZmIPl7S1FJ8 oyFi1uDCrrCrhMXOJ9oczO/SR1zGfCEHzEsv4huoR84XFo8zb869rug4dQK53cvd+V0Cwc5AfsJr PVzDz8qLmd6Y9Z+lKdaibNfJAjo3lfs8+MYPGJkKqT0hWt3WmC2YAWuOJJwS/9O71WuvVi48rj5O bbLlXwAjdz+1hk3a6N17wJ41OxyN0Zc51oa5bN0+GYh0p3wOl8F581k0tA++qeAEg8J/1wKjNWw5 ACptQRuMs85j4AIfgm8jSVAJsIcQc5XMCpPMONnAOWX18+XxxOdEdkGy3IV0eNSMvwnJ7F9Cb6dj xGNaGrjDMURO1ewyEpqYEFi5f6zvQ3WPX0sjoUAkVOcE4slJNZUUwSdmz+y3acYGIEevl/pGeQoQ UTv1Ni/rGww7cL7mL/3iqDrsQXGnenKAsNO06I4pKd4hBdBA+KrWfaK5KPg/bsh+4FE9TjLRd7/Z +/kX1XNvW++qA8/qSYBHDY4oSxdZLPcui8Og3K4mdwwBTzk09MdK8p9I79BZOQaCsGqQzwgauWjR nd6H3VSw21eiKVPuOGVlRlQ28lBdrqpxdif2O/rreusRoAAhB7BP7Us4saqKXTMSRHTYjX2kG98b EzBNDbLiBVGbNV95PD9/r9Kv575udf9nVv1AaaVSDyFDESOXwh+DsCsr7Wkj0j+lV/kj2S+RO2tF PBc7Z2DKP6r0IRV7ghsZc8N6YaqI2PsxRVFdLChvF1vzjhaHZyNxbE0mnKz3H5ILwH5fkUdcliKc I3G9K7w5/LHN2nBTyqJ1t7QXD2SxrbXMTEPj9onYhS8ZhlbxyrVjGt+j7wfVhX5NZNKjNQmz59F1 qRrZG5Ckw3rjZCpWroxdXC21ECgt7x5HYsBBVoSGipGBjBy2W9gq8HG/VJ0Diq3PneawZvq9Jnmv Vn4e/isai88iUTkeWiPPFln92RwSaf5TtbUEAGwR+pbz+lLLdQTYZTQ0757P3d4utIdY5ItwZ1lc tjGAREgQWXKeY/And/N7Bgv4Jzc8/yG1pt2nVy6Yi92SWiQZh4n+lubbX99oTGonlCLs2Ea/HeVJ +LhBehE1w/kjQjGkgbhkH7J6BmJAwnhQFl8LwRAV4DI88g+gvTowGq966x+2kGnoo7MtsfG3+WnW Ue7C8OPwhSgw5sP9OniM2EylqQiNte+35RYWnyBVXIWfvl3XDlHuTU4nY1KlEjnDiNbAXDJUnLjS dfNbQkFvfjyEjFU/Ip4gdbLnMyXOu7FMpqOAS3a/e+ou/iNX1MO8y4EeeYVuUFSP84zWR+vvRio4 6LkDMJdk2fPjVd0WILopRjTiBu7e7PQV5lqIoe7PylHwlhYXND7BuwJuVqWx+HYffrCH45AqlvaL q+ymkymNkoSt3CkME7r/lHiiiBHv2BB+nT701LdVjoRdoCC6yDuLir2Xbg+e4pLszBUfbAOvhU2Q S/cRO7NEHt4IrnX5wzQFaimoJH0kD+6skJXylGOpXIY3FzX5RGrmyGUDzs+4MYu9h0B8GPGYPTtX wUNDHpuRmVrvb565sJB8rMU6URY/yTtcQC2MENKUnwsgzmuAkB2XUKSb+Cwk1vU4rjvFsLEDjXmB h7L5VU+GGQ3bLfy11Vo2iW9uVNRHa7Brr6NDet6gCqE21U0TNM03swv1THzhxUfZEOP9xxr3PTzH vvF6ZRz+3nGb/UdUh8CKM2+hImhsDsiNYyd1kV0n6/kohlWHS9utPa44QCBEOhDfiUsvHrvbHgri AgML19xontYEK6i8sxtDxnxet+lYQkzZRG54oxEWU0a9fDHNSE+UFQK/fN/4eMgFLSb9BcVK9hKA CP2KwlLT/j8+IRHslf3NrXuW3oJdZrQMfz6ig2lvl5N/Rw82oNlQ6j/tJfgpSKSu6iUHF0GME6B3 jztwMqsmWI6shflwTcKUzGfT9DBc2Irib/fRbBlZGj6MDxmjQfLFVI2utQEbqCNOo68PvBQDbxmh vXXSKVg6QkOmh+mke9VICCBPAsVVBScn1BOYfKmnVJ9HdVoQsnS9zCtyCUVJKRQwVpM3VV6MNnuL OWJK543jqvovE56/9+jDIJtXK56YkPLzXQWxOF5xzRZ0/Gk314cDOapXG22PNMgL/nlDYoFfoHs6 L2uImLQX6Fd/PDkO17W6bKRTuPQ8VpHpL2zLRgcMDb8Chs4s8ida87ABk0QyXoR0ZSVGcfi8WBeo zTMBX25xb+wbtuyWk2gbajKcssvZonnTN/rEpaMaahzRjZUR2rj9S/aFTuqxY3GB6yxHSxaBInyB dhMAyLlAVFDcyqDgIVJXpcWdFePlctp1NgWWelHvvwyl8JBd6Y6XVTH+0qpItpAPynRlJCCk/hb6 78i3TkahOz4Y0z3Da3uvk5avIG8/K++KwgvHu5QxcD/lfFbyVuFz36K0nShSpxv9z+jys5brfH7U 4c86dwoBh2NltJnoJfPVmM1NAlb9GI7PyXDJobQSQq6wpjObaQ/anrD0fMJes3zdiVjL28AU1ntF SaoNLYzQ84CRvYdrfu5gQQOlWavo1zmCVJ5b6xttF9waKZJOWRKyIiahoJJJ2F6vC9rDsCSHv/je gpGP2blv5AH3EMuGkCVreeiDODrwGHIfgAJ3IFsaSt8z8sdaRX+aU8s+H6jW2zwRPYe5b9s9UdCo 6NsPYP4kIUHaT29yh5JNwSoko3WGN46g7XF1j9DRvQFKAUiRC7kXLB4tdaU/+48yKyPetUm00Ak8 KujP8agHKxEhJqPCFTbnCe0CTNxRgTp0KATwX2chCSIE/BlFAkv1BaQnNFxV/0lJsnweDRygKYRM Afjfo1ILq3XZ17wFF9IYOcwywFw2MQy3Zg4m8F7G02thMQKkihWSUdNty1MJTXZl1FFZPlXgGwo/ UBufcMQ83rB+3tSORCAWvKQW5vseuKlY2l4Ym4puP+d2IVjHuUlnMyF3J4Yin1tj8vcWmvmEiKi1 zRZz/krmoagW1IYTNsLwQEecZ4gYkqpEYPJOJ3HCEMy7I/xEPWgmCYT7gUKdADnqr+iWoNE+0bOx 2cFdd+tFEmnatRNjl2iYPvnSGu5QIizb2ppF2MeqUPeSPGVmFskKNwQaBBBzy86P1r0XMF9AY9LU R2EC6HpnGKfmKmphvgfBeDQ0ERB6SUQTPGItD9WcNiOvSRDPxTbkVIy6rPWOb7TbjbOOhbn6iyl8 7qRK2rcKLSeEauksXlZOKXq8KsLWOjVqL2HTBWCEbRWF79EInXRFRnawO+qhKECDyiAy+q1skHd7 HY64/LNFAg21ZIYf+C8rGTNvSPO/Qp9/Y3pSoClGy0dxoQoAp0v1aP+h+U+bmlZTKkBzsBKrhTwV Q7cckhGVgWDW6tBC0cFYBZn8q/1Zj2fFGPb6X3gYKHo5A5liDliT2caANUIuvb2G3HGce76grAYA iXy855VZ1fXqOFcfMZLIl4pTDsYRgGvsd+59tKv60C3/mad4RFCWD5VNMf3bsvbCruQG9dOPEOh+ LRbvW40f89YhgekjMtL5HN7ZAKKpa/6OZJ4SPUylZ7+N+nL1rMdCDEfS+hvF1JCnC+25AjThRi5p DMDkShWN836xNPc5YP7tOAqBpKvZvC6+TVkCPommElWKvkMJWZtcxppnZ2bJ76aeozFPllNeJiQS rJOhAiGLZJUhjUskad0P1H9ve/ZL0tzbNShS5p6p++PB6xzeLDmykW686NVr+tF+s3n1T//85j7r 3DbidgwImdWXxS3TBmqF6gO7+H7PpxBOYWj8g7wLd5q73ODvfXOLBELpfaYfAQxisWZ3YZ3ENBWn 7IAX9qjl0PbD+QiJfQG/Y3jbuqS9yCwMiv7JgY3bIklpxSL3mWDG6skuMsMCfzwfSzUEtBOhq04R vElKuMXQuztduEJ7SirMdm3LODOZp00wYGrYX9fzhiJndKpU4+eOgOCiZcZHFfyzVdHEX95jpeLJ ew8duIlHHMzj8VUHQWL+7p24ff85dksMuoWAYaC3zugX8GR9AtUExctBA8X6E8e+BdETtp4wWoPp cHOUeU4IwJqwX1VI532oIYTSesExcWJDHOy4SDBq9sE0yxYSLINBojJvSmM9LQoi66PQE07ySuAr pbQWGaOJt9LPWkr/3bH0wjtwuhvXdsHVyW5xbhu3s1FCTSTcgzakVwD+F/GXqPqLUseLLU1QY09x 6jaFG3i33XZ76WiKHeZ1XwHdnBumnpAYdIpB9+oUasDq62ecgGNtqbp7eowTn9rw2vov6ITNSFCj mp7X56aBVI89nGtj84/9v+uL4k0Ed+8P6W+a2MoRkz780JEfg/17memkIuqHTG6IFJ6rmSJ8DzbJ EYvQH9Y26Ez9YY3B4tfke4+OG5ssUtF5SNe41upTiO3CkgpGKSy0h2hE073agKOmh6HSuWwXdIOf 4UMC/380/JsfVz8RP3LyB0QHfXG4+oN5Ffj1KEThxOHndfVnNlpAQtk+OaWPBLEkCnlXTQ0WNDq5 r3mQrzBV8dozuo5gfMsyQ46i2d8yIVpCsLaDHr4DMaVQol/RnnOpqSSi7u2TyW67RWuv3M9poKbF +kXP2t3drWaOXWd6YjEa35r+7ToKFYuC2/SgwK7lgYANAIkHsJvFX73axfiXEOq7tVFydYigfJZ1 JI9YMYkowmsMvxBICOqW5Clj18ZsPOLDb6UAhPrek0zJ+ntLsGQusSXjRK1EJyvy0nzVBFmZu5Dq qqCLb8vR9uF7ZMcf9E7mUTk2vZA31ywQIDkZ9hNfhd+7952+Ldse8tzaZ2DKjyvLSrLcrZoGhPKI qZFl3bXR8Hy5a4kZCcrm4DSTkjhJskKF3hbEO3XT9PZvFGB0d8AGfCZkGEOXXZoO4SECj68YoXrK 2Ow8RLkq5bYHhIBh/YXUkgMEmE0Wt2EL2+Y8mz0rsAwnoXTGby65kopcCViKcvegdhLa7/uNFKtG ju3qAr+03tdsb6mJuUOhOiEaEXoKFqoJJV/Pwc7yASUzADc/sbPbU3ikRjrBLSUiYfn1TxeZuCDA fM+EvCr9vucfJ/nxPWlGCsFyUhZShNMySfZ/s5PzjJlx4TT2fTBkNavw4JGIvQli+xPWHAizGkQX pAdRBk38Va8sBeM8IWN2KwHps0KyOcJBn2fXNyXqOI8UtKVM3Lv4UnNOYJF/Ee4maDzh5BplQx7+ GVhvUMS69nPTtKDGrj0qPtQHHO0MyQqeSofi5Q2h9lRJIj1vTBGWoM9DXbDMrg+Kmc54zYn5rYSU 27NHkhZsq2DSV1gnE0WO9PIQ4MlA1G7Iv0AMST3VNleU1Se8pk3m183pSXR9b3Fy/MNG1RrXEHTv 4B7Crw2z4kMkeQ0UQJxuQUXBjM8tyH7pEn7cS/Mc4htJpS4P2g0TR0d3cA0SscIkwcCaUxOW6nzo Ve++ok4mJsR+TtsZWboxN01F8OUDYyHh1AurrCJlDQrfBZO2zC93PP3Da6mN0nJFfMFTtrOxVdjW zRZMNFe7R0+bFLb1LNNU7D82xbz3G4sJWws1EwtenWMKgky+1FklQ+4WhtDSoJvaCLSsPRpk7owS 5gwKwProbrLSOkhzzQF3cpGcScGwYUvMe/sovvbagiEs/e70BVgoN6SU0m7StZdMQeYuNe/yygJU N2vm8KwcaDjTnjUQmjyRRzPTwO1w7pM/usn8VKPgX/3hJ2oN5HChw1RvUpRKs9oa03Z0cPqW6omM pXIiafEiS4x3HHKudf594pLp7xpL/9e+zzNx48DHNRKVIGDbSE1cEKPEC4/SbEKnJzCadZRPgn7J BYRKyCpER9ma5vKIuZZu5I9JT/tU7RMdPTeH6THi1DIBsi2nv8wJ4djZPUp7bzwNZbSEQY3COjr2 YEiSmpMZkem05kYPIsXhGwBFITnIqJBvmV8c45XLWBRUkZXOEJj2/WVxIBfEkJr7jC6pAWUwOzUg KvJNyVnbyfBTzLRUFq0Wr98/8lXGeN95wRf10QTL+i7RzLdc9lHs0RqnCH9fDe7+1jzkCMsjwtfM tc6B9IeHHwpx8NDlOVTcz7GpYuGqG/+7lVdt5Wz5kKkvd17wLghIYjXwQCI0+Bh7J+bNO254baU2 NhECXgDVxQ79pyc0csD0tk9gGu9iFd27/650msePRmIdoN4AhSUg3Qa5B6NfQ682Ux2eHQ8YENk6 nuaH3xQDkneiWQUPd9dU8r6Xpa5xliBUmd/NsQlR7HR0pYRDRfoSVTfXAxWBXaUHce2CbECXyuiD gQnQEo9nOkLEbDkSZTlW0gJh8ERjRj6LfxkmMm5wEFoR2tRNggmhIO7Jor9Zo/owRdZVZZKkAMAm Ut/6QE7D/r/kei2e7AdUjFbw4jYLaUZvYZPB68EekYqEMVFu/sFw4dEGdBVmXiURWYatr1wgmWTZ +L0QpbRNg82RW4PQIgy9Z1x4WbY7mijppermUl1y2VnMJtPJJu+ik/DMYoWTKsag4KsBikSYKiSW EUx5Vw2/ZlnSWngCcmwyGu9j9CalScjKbuaf9icbg10IBxuCBKW460Wc3UpG4tf1T+D1FeuhqLfs SWo5EoE82XvwsFyjn73m5GYLrKv+aXxV9eAUM0UrpZYGSV1tWjbYJHuM4P7QfUPurvSYx6i33pJs Tz/SkuWT7Yw1Kwu4qtTc1XVo7spkz2OKmtTOZYLH4Ib7d03Xyxx3GXMM4bWU9L5939BmuMhqiglR 1RVLqy+ynBosdazp0IS5xO0boZO28ulHN7FR1lACu7DrDY0YadqBuFCphYo8hpDy4IV+T+gAMZZg R4+y8/Q5FHQSShiFhBi+qR6ktpiPv3e+GYR6sBFEH5jU2/ct9aVvM5Qdm4j0MDAjoTHep7F3LbBM QziQ4yCLUoSdBx4HMob92+ud0Fmbx/2P3++eV1bDlfLyeEVBr0FYE9qn61hudRoCw9pjre/Qz1o7 rk1XV58r8OZr0uzFtEku5XHI9FRL300OCFiuZ6Ihl5LNmGzXcLaTTiyk3PGyvja9yqWqYRkdq+02 fPOHUVXXQL72No0qPPcM3GFuzBlroQUxORSK/X23V/L2z9z7UVirMnU7VpuNYE2CbaXCjwirwRsP rvLRVuOUXbZ8l05clWaGwPe3G4oZl8lUnQxnlJ8zz46JjVPcBN2JgD+A2HGEADV5qThke3RVNmA9 BQclMMxZCP97P8s6YBsBGV+gvnFtV1278yE6UZeLccnI5AllJhKXu6thqgsrHGS/2BO9coenU7X/ 22Nf8ICyfQEPnbwSsJzdFnOsmO9U4sl/s/bVoKmLi8xC8IFaEDMCerRenp7Wjmw3wCrWng7J59jw mMjBgCLbvlhFyXzBIenXIjH5HmQtTJ1XDvdzY0PWWVG1aNZVr4VhQQ7S8ZUjstp6/glGPZUNKbVb A1RJlyuadjqQ+bDX/d8bU/rz8XK29VzObxFFLZLCaycVkh8SNVkmFysBH65aP6jQS6K0+Rwz/ixr OoPxVDfVJl0dBcv7IMCciZeKZZmvOb5i9jopqhwtTckifF2guf4aZuhrU+XmsDBi+VpMLZGyZDic 0IOuPcS1BuiZAQzmoOszgLWXX//uXEvsYqZJJG2s8LdmO25Lsr9p1fjqRaw22gaN0CVJ4awoD7ks jcOYgWYe5RgEpdbjf6LKfDtpR4f5BCT3fcIg9G2mplfqW62qwv/rAQATKf+lEfSR0QPjxQeCgSNs +mAirFqSFH/PCDhKV31PBpUiuDBR+bb1OBt4u6ODlQXm2l9rCi52nFMx9j+c7YGNRP0JgQaUdznt 1nY1ZKn/OnpNmAjZ9uo6WFA1bHgv9dMS8vy/HMj1OK0LJojjdSf0DZ4kACkNt31BH5AQGpKRSoQQ DXQ5DrpOK7lN2vENrQxyc3wiCD4ew150Iod0Zxy35kYNV2/zQ3GVrC4NarAKOqHJyuxHRC8KYPhw c5JDSQAJBqfOyKvsQtBrK0k0ICxxUfZGPBbOfpMJhHj0DTJrL4jKnm1/MD3oBqQK2bIhjGYKCpOa S40az7H2FDrnI8pSG9coRi0cvU3tTxB3vT5AwmyJXfWnT1HEVxPqzuE1176xmQgp0PsCQvAD2wd/ uRyTgcFeF4vB2HbAPi8QAX7qz2LUzVbKgv0D6aK4s500wr8aLe8wqSpxzvEWkgvD55RrN4iRr7OV umhwiIgM0KMPoL3zTmVA/Ev1H9zcq/t8EOyFZTpTGkAqYprdgEoGGb6N+PNNLd3cjv7KRwkChxjw UuFYnppnSrpIIGQ3hTW0qGazfKjIr0Ffz7E8koZ20gXDL4HTz+dwfzmT3VRYCM5QJoalY38rHSP8 19LIgknUwiRG0Xjs57NSp9RF+31vOscJBvhsQL8RN5Q+TuRcL4pTPie9Za0+Ou3tayN7UIGFBUBI 5pLnqJKr6/S5DkSJfi3Ysme39ik+ksLzelEUnI1ozl4dPSqdKBrswTkVpx2sAs1LTB1qYqNm+Lvk qmJYu0GeP4E1DaO77FqDgIl+qGWjdeSnBNBSax6kb0fA7pvAib/f4eKY40Dqz/krQPrxCVYJIdyW 6+KzhTIU/8iGX2pYtxqw4r/yM5QndymtVRHVXYasTrvfDhoC2jnU8PKQIC0Vo2kXBcUWG/pnpP8P /VsgYATZi4WF1QGvpgNGRYLcF7EILlF/5XI0fsFua2AePNaoYqSaGiRSl5Gjn4WNaTH1xhWB9DrR PHTvLG6546KkUZfmkh6/js2JbzerdFxnA7Ec2zr6h99WK5j7qjM7C8o37Nw50zNaBRzSVn7g9+yh rE0w59xqIAbFG25HjmrXcJtG0vD+TOqfKR9RuNtfR3YVHCwjocTn80lplbbfv866ZO4FxXm+BK5C 3WANUkIwzt6X670oisleqb6E6Qknu56RPB2l60w0MA8uI3jcb0kwhQbIunwRxzkWd474YwUkEVS5 NeT+Zfi3pDQbYvnFx+lXGoIufgG1L7OuTn3ITWQjyrMZ09bNDqfFmiahtte2/I255PJs/0jrAZjP 7dyP4LP73+uCWAHSjvwEQeAsi/W9K3IcdftpblW++sHxINpTGeif2mVjo2Mh3DoI8/ZGLnZc6+62 hSlvtKJ4DKmZNINvGwAmmqIMYKTUtiOwid/w4reKVpnlgwF21lj75iEOT1G5vfD8MS/GKlVDprhX r7G06teHIgrZ0wp6Hxy/jrFWeEXFPsiG+4FXju2jJN+dsqIaQeisZPVXQSKIG8aMn4IHLctTa9L1 NqMH8Y9FRW6704K1+60Yj2fjwP7j7y4yf9duDBbujqotgCihuc23JdEHpXeA6dIVYA4QjzYUo/mz +j0yrcPM7z6uIBRdDjo06qzW/Ih9beeTzKV1Zg7zt8+k+1NrxXZx5mU6DDKyFw+TktMEOH7VcPJs 4jBZz5yZzd5wuCVNtSk915UVGSP63Mq7BnusskDkJTHQcVqL8XtArTDId03fNcLJnPJFKdsCSmMp C025XjwYpvd2izo0FM5Ekh8bHQcT9LaffJoLkwW4HWN28WCdCVD0zsQtvGdz1sBuqXHOpNnAafOh SPHShdfpa+hSv/TJ6LNlhxFDlfw3zX9YTA+AZu2mmTv+BBtKs5MiznN7jGOKDjcQgozIvCjq657b sFEEfmwF/FTX/+73oIy7WjYC+cisS2/35uStNkTYstL3Jvcwl8Ruw8h2BnfA7WBOq2yu9BkIGhiL aBwjHQPR9K7t3lQ4kwQTZXDhgYNjBDUM9HHtj2K3lQSX8YLmyUf7zG6vNfx6zJYD4Os8xnKx5K6m nxJIgOJ87pnLKDWxTYdKAWxDGd3tY6mOKrMpBxQfJUWHXEpbXQ0yF+WOOrH1Fn4B6nSgDbtKAlDL 4WZrVr+vOeYcFlBz2VagXnNEybMC/Xym2lvzn2cLhTrYSXXxsqMWfZqjhCslvYv7lPTOn1AHrlJa yhQG1UdFglzdhq9gCVFkpC63dYrxWVRiXLAy4qHAxmCRF7Fo2+jGYVlILfE4qb1oNuzYv8eD47uX q6XqwAyB6+TgPJ1gBKlsmoWYksMZnw2wkKcDByoeFi2N7tWrwEl9AppcrHj7YT5OfeR4KrfgLueN ZoMvrQDgNKqhVb4typbCeLA1EpPzAhdxP59EVgmHW82dxsviqLyslS9wTbGOCv0tuXUTedyd+a8k JnXFiLEZzkdEvatoiLO9Fo6ya6oVRItKf7k+mSWPMWw02Y4kGUcV0i40CorxLMCkPa6vL9J/TzYy N+vAdh9/ejQEvW0cNjmW685S7sF3MtpiKnGjic/TotyXqo9Tn8S11lKwA33q82AGnolqhw27jqzz Uuz7cADQX6FkQXUCcMIusxU0n57gmNGyTahu5ow7rCulA+jes9/2gfiipkzyWWnhrVZPiSy29Cb6 TvVEvItfqAuahc79iMKyBUktGN5jXx6eKmDzEObGjCW74iVC2/WKC0AG+5y/ccF4E/0Yh2L0AXGA Xdc8M0LVVEVxihD/0AwoyiLK5fNf4Qna5OtH0936hicAw2mRK4TplE/+yGJMuDtBOWgH1fBBd28t cooxo7eSJY9mSRo4waE8xEHBmhUdICFyCOBc+hLXBsrqkJufn6Q0NOn9eSx0JIek0WNpvTYPvoAC Mwn0z763C8PwNp9PgKYA8rGbg5nsPz4cw7D+Ih+XlIWsp2TZsvvYaRhm3YS9JtX3aE5kJZgkUk4B GZS39Fb1M14JnLYCdK2TPkTAQ0HrobtTn+/ojXyRjzc/j7n1nXLGXec9r4sbF8uXBon8pMKAXg1s X+HDVziM5mfzXvc/Y6whUmI8AF4lM49f4ToVaPDIpRdLm4gHHjYhBPauc4yYyCggV+nNe3bLrUlQ 5GR941CN+keHQlFY8Wcxn/KrtqFALhrBnpIZwnHmVd46s1XT+Csg9bGs9okxsvYbNHFiF66w50c8 2qR6nKXmLTzImZVs/Tg1xQhWZR9coAz6e/gSZ99ZynxXEtR6L5dKaTVchWBGyIhm8O/i0XuUP/9E oW6SWT2mwDPO1phAQBJYaKqJwm5eKOifSnKkdIm4kCTPEZmX0OlSC8AYj5rVcTNvmltPj+KTGR2j w61go9l15/lIAXtMlcuV2GIBmKgXEM+k75de6dejQ1tVmOgd0JH/KNT95JaNX19wMqBLdBcnNE3n I+2DDMvLUbNQVTw2ScAAZ1OOX5AR4aMdBNarPmTtZcLM6qBpWic5x7yufVoGCiZqfjmDKXGe3ssw 5dxH3MjBz9nmh5iS7x97Sr6DdLxHUrR99JKVe4dKAjbKICxBjIedqaixlByoQbj544ceABtvjLlG 7g3QqJsHE9cZXK77yr15NE+ATnqoWbKV6lf8b/pfqQdp1g1s191PJdNiPxdUTcT/PWabPfDu0p64 8/7vplRwOVCkFMdlG274pjIV4dVImeDpyiugngszPDD3UUH5dYgM6we04zUQOCdW40rhKZqRZZfw nekb/YSC6dmzKkARMDl2863wrKL9gEIHrvUcI+v0jGLe658k4Px8GOVq6L1e3MhmuAhHvsKSAo++ iFShJnfNxyKOSSJlgxyP4B7VSJVAbc8kt8OogZ8mSpP9DqBExICMAuJ6gEKwQmI3wWawPOhX44ud l0OVVig4/4la/3p7NmSt43AwdfbcvIFc2PoMb+l0tLpMie5tUT0KNywuNyHSPhiH0K+Occ1x4p+b b+rqsGr3WQopu+M5d0wY0cPBSAUlfy64KBvRL8LOQ2AOh6Yq1U+8JA/3lmJ0+Ig3yW3qdRT9hI8f 1X3BmE8XMd8MgHgZRQ3BgUeDYWcThFhrp05aSNGcndn9HsdFuL2wg9FClL1ZZhHQP5l9uvfSZgMS Ydx50xbjgrpfF197fmAKVGdXKl65SJcXELzhtfxnbHth0gBexlMdLoYIdsTSt0s4m309Crdl9Ap4 JvQPsjSeL/1Mt7Ud8DaXTVZhG1kGoqAWR23SV9bHgizxGbYVycbD0x7X2iJW+aokuSAyozuJv7Dd zn+eF0srchbD36HjjUOqPejCJZVKOiLVG4FuCopKT1NXfXqvxD/KvLjIp2RjHOOr9teEMeqDONxx Jjctx0R+3cDJAknA/wqrDaXart+kGxVzBEj9bkBr24enz7e+RTdB8nY5/UJq6LOkj7GsQdX+RHj+ 89qMdNAAvsh3P2tgD3+w38d0pX0p5DDn5etO7DcifEaJRi0iE3qWDiMbWD8p4W9tuULPWoCMkkfi kbUbX631BATuxBxl9Jt0q+6pA/UIzkNfk1Uz97vRFcYOoMMqCfFg3t9PjFJj73UMgAV7Ezm+ij2H b43mz0964Ces6Q49TT0Q3xea+n6IaWZeSczDlsz/Lf1l/QLScR3OF2m9Dx+5EkTuHx9aA4IJsZXh GigMXyDtRZ/tF1niDxcEe3QTl5x5rWiezitephJOx+6AdSXNO6ODoQZhYi/JLZq0yJQSm/icprTq D2/htiihbLPk69TfGsz6LYcOgx2yrTCytCPD9sdxHOdZKmWft5y1lEQNx4femk+6yR8g790HZ2yh Ad3kvo9bJ02JNzFbfrN8xhi0I1cCX/LEzh/Tv5t2vIXTEQc1IJMZ3qlln4Yf70nU+ALSroZDykUV mACu5bULdNQaS00pAkRvVj4HXRE0GNMYu04JzVj8AfdOuydHZEeeTR28uE5cvPlGadEiW/WRyr6S p+zzTwr357gLcKjMO4DUU4adOtcPGuEBcrSljYN8WNGFn5lLWUqddx2o5f16nMuyEPBuyLqV06wZ AyhCX+1t8GBIFnC477MC3LEoWAhBdgl03VN+XyoVAbb99kfvoYxu6BZL5AI9EMYr0HJQUbVySwt4 dC+LX/UQ3Y3QWqVXi2Cozqs3yrtVmB129LtNDAp1NbHs8BXbSzQ90sXoKYOdBr/d9Zl21FrZSbP6 r7euNEfCUoAa+KnL7C2GaY9bjXzX71QQXMiVtTyml+YgjTob64gZTCLCf/0OWHGBoV+8T9ryCe7y iwPlRAKrevbnCNtlGoWATutiV7eQo83qzRNYXrK57sxm2LYVK4SaBz5Ehqkjn9jIvDJ0ErpYAsFv 7KFoloyrYOfFMh3nf+3SXhn6oEER9nmGeXuOxfcLwzgqbmkKj6wz/FQWeqT0wCkWeBYBH145Fict /54F9MFIuRU+hV3Imi6oHYfPbZvK066ky/W5CQ3UvPKBmkZcRw1vrCIUaCWclHJNoipjinNg1a6D +qvASym08xDY/0LvfH3NGMBHysbEm8vzDo61vXia6reLy95Yztls22XR+plvETWcZsDm5OL34Q1s im5A73XPX59TZyq7iybZCwpaiMbYmNr2kSScTYkXxeDJW02HOM/7/9h9NhlETxrrkQEghdGbiYZV yQaNz5kZPUQMYz30VY2R2yoXgX3TkTXDqaFXmqvU09usmbEh4y4a+UzczlOUbfbrfieBcVylZjlb 03ouxJFWkndNjGY0TJcsatZsw0pj2o9tliSuu80tB6NZqTZJ1PzUuBKPh6aZBQ3UOkWVQzxeY01y PqDVmJl6hD+HodUAk5WURBHypfDFPYlmpxHvG6zRgFnqdYSNIJHfXLgTusC4ZcJKJAe7aS1PVeeJ zPhFSHqU8n9y8KlAd39AbQFAmtJwnMfUUqYCJTtlh8ODgjMDvSYnHyVRdhXzxv9fo7vHV3gNH3FR 2TMC/ld+EzDYeLRFTvDzSDdsU8Rhpkok4iP4RzJaETxIg0oI64DFwVJctPG6w0eE/hcMSg6JUII6 3BMDhyvZk2F5nDrpZQ9QEz3m83B0+htkmzCLrkqImWys38Hy1dNFMPmW9wOES1UcexjGiiSt05iF t4OWcTS9tit8RrOjrEc0z/O1UUnycbmyX0ifYRii+bR52bzcCX82jjnddwnks8lwvr23aYt06QgD F65DQpVfvdB9wwrVvqUc/BqBeIjQVIRAATiIaQE8z11eXAUQbDSziXBGjQpxG9cpamB7MoznkjFS Gb3FhpbgBuYD4tT2FoV2mTlk6plkKPu3rnGtgp7XQlBN6VmwULD8kC9hqYUuQUPgBSOrSH/jRjWA jXko668Q17n4gVhzy+AK2QzeKwCi9BXnbhXsHws0bstmw+MWgvZuoYKW/4flRdbm8y+Kfyk2uQDs dHCmM0djfR/M4XlOjB6tG9ToIqTuUtajYeCP/q9BAgZe0JBR1No5J8QtK41aO+zUKVEru9aAOoCd OPOcp4AuwybJhjFSxK27TcRJhkjxdZ7UMHIZMACZm7tXTEbTg4D+WaquJaib/bXr1oN5hvC3n5Eg 6Q54iXp25X/D2zoKiOq7fgbHaqdp0Mit8aU9yAdhhgkgCKY8bLtAQad5jxUHZMjTVI9iiveBUMaU us1YdeB5AG87oYPZan+t95zzh4ROLjbkk/+xbGOTZ4u74Ez2aM/bS1NuoQK9dv7vO8OL+5KJlaPL QlhEm6rYqXQr2KAr77AtWrLtDlVQ4C0QAq+dnvWzfvgaGR+R1K/6P15Nrk7EkrPVt2QbbmQJkUS7 zHlHD9vfxNTJqya7wzH7s+dXs4mrCVm7IEXG+Qku3QDGhtyKUrorh4fgfZKrU985j3s3ix5opnz2 1YLHbelNoRLoF+vNZBhlePh26vxd873PEo4e65HexaTtKEhRmj15qF/DiHH0TmSpsHGTdJav18Hz JyrfHSxlle0POhTDzM5maSu03BQ7DkAMs16L+cJpmCZXU8XQq3RElYbkqQGcS1xX1U7Kd6Ywux21 Psb8R2xubvBAezWxYE2J9SPNqhZouxw3D9gjEyZPoe1kM6cgOQelA557UhWo/lfFImTMV7P77x/3 U0UK4V1eXIn12LYzlD38RsMHf8MVWZjagZ/DmHLsU4CO98jw4ZHRWOLoNy/hytvJDMQjrcqyK7pF U5BeNun+EnMcMA9Vm4OpWmWpF3JPpQ12nqxK0klA2K7r+4mb3YhpUiPn8Aoo7R6+F32U49YpZCiF 8wmTPVM5GTpVvPHO6dFPPBYcDfkgMcfuxxpCG4JKZAym8vI10rCgv4Ms3RicvAUAH3xs4GAzTIfg PZypWtc7QkAZ+ROsg89+0g7e9dCW6fXOSWNLPE534jUzjAt3O84ezsBY3Wt86TdcrYaCGvVXAik2 M012d3Hh+4dP55l12OHjdJHW9yyJCCcVOzwQhAc7REffX5APDoxdnQeGVf2H6DxQkw+By03TlQCO 7JjBUA5VJWgY71zKpFJAPXbuSQ48R0GNoQGVMqRcNng2PtGrA7Ij1R9fY+xKrHqW4zFTyb/mjQ+n tiT58fl+qxAkSk7dMT6svwGFjjm9gXkphz4KStgZFNaBd9f1AzGo7P85IheAhFlJ11wi1f6a65WD VR5zlUqd09CHbxu07LnVGxm+u/kbSeM7Em0aVZeJZHzdl8Fey9UW9s34VSayLwIZN44l2iPbrVkd 3LZVnmNBRzaBeI3oYVX5q61oy+SdEo+ok/OBULuKX7KNh3EUP7IZTb7PLhNPC/BgbYhEapnVVsYp gQsYflBS1IOm+bgOKHnvSS+z6yh8PpxiJnrIswSaPnaxYpWPPRjQh68q9qAk384Yq4qmrQ1ptDMS 9CsVdH/Wii2JvtYEps4GijdVIYMuDLriuy9WunIVnO9cjLZY0XmZ6misCuSAJF/TfES+kKtVXphC hJLUCaftcsSE1ey/NfIKLqGhMa/prdi7YUnaqjBxe13gTp6jehc/pxuAWlP8kdx5DbZA5X8Q0C+k ne3iw4R94ylQYFQdcT9yp4Ya02rTLwGuxl7/SAmC8ZzLF15jEIqNBRanAfM+aYNMetMM2tImgZcj udwVDtvK5sItua5zcyBw2Kc9TwmLz9HBWM9F7SLUsRVrqyGI3MiSdMvAGrXTrcWjELwZjSkuN52o 2GrJEYX0qtfbiQ7lkDblEWyDdhnoG8oq/t/Yc9N87Qfy0LWwAArmH9q9NwJMdJJJKWu/YPjnbZ7E Mn7uYJgbgYNCjltkKtMkV/llt844p44VjSZWLccZk4uCdJosiyZRDVCR82xjhKmqbmRgxEBmNaYl SzvHbRcJpJ2yCIhPjPPP4A7pHhrzKZuRTXKqgmobGje+Y6LZi62/I6msOqeT+t6Uq+E/NkQ6bcm5 ym2T2Fw34iK3Jf8dGzvlFN898yd1VTGmJC4GXA2yWGLrIJcWxF9tPQZvbyZnwbtyqwtJR4Ypw8oB yM/yKoB1YvudGrmQpGy416jf69BU0hFufTNdXvOWQaIy0VW9DTt/MlDxhTgBO8/g5jFzLpcR6T9y IZXVIpAPKO5BgQCNDlKuXmmQ5CHnb0FWwX9tpt4ERzyaPSf8aQLh9nwzNzYNKUS39jq3TdxRxt6g 2okw0V00h3V284Fi0yIEE56KI4SYKotuKgy7aRaC6bQLhOZG9sufNGAWCLSQB6pZehj/mwKQpyXR ZwbQulN4ay77g7yLQ/SG2O8AsMeCCsrRzt1ks8z/2t7V7/EJ1OQFbEUzFY8QfQWq+p9c+gK5d5ov a4DLPQcRyRTrZ/rjj+vNSGtb5rztlDm9W0cT9yvcHGMbxw1mZyhL9NT8lX4FTeB0gdHQMVc863ax QsxRGmkz0lEFDG8gxBq5nKYVT6ZaVDqphGfjoAyiL6590q0o4RQPFnD6z9k37ZoLQvbdpL2Pbm1H jZlvSQQTN3rIUPGc7S7wEqLUdl9kw5iilPZNPIBXzIqdiO1wi9DZL1QfR9ZqGLFxUcfkbeEzWwnU RX0oK2DvAhFI667ipqS5nRwACirPjxMGzWwPAxpL0IR9vv3neMpLXox0RglSmGKMYGzxFHiO62KK 3WbTXf+4cgKjBJM+EVVH1kTFAZ0rpiKCc+xqmVdYVwTQlFbG7Ujda1G5eMKJ/e3ozd/iY8pm/PJP zL9SDXHTA04hkeFKvtDr9IPt7NkYHIhyJA1vULxS8hugvtZtyZC6k0XNM7UgIngmr0qvaTPkfh4s 6LBHAS9HOXMJdNxkiffdmqNsYK05+FY75bBZfIrZHOgeF3pWAb5afidZI1dAGh4PiIgD2PP7w1Vx wCMWx8kk+A5JAyV0Zw5IyV9hb49jO2askOtAVcvsy4g2VNMQWZ3uOzSp05N1fEStsuhqxOUpM9vh aSYHBuMUc76QLcwgn29W1W4w0e5221qZXJ2k4Hbzx4KoSjrTsroz/qRIHp2Gy65op6pqu1cisIEG WOlepkll/dDYvw8tkt2ysKcsb4E4d+C3RgBGQ85lm+e1oCzOobnXiLNa1CMNEY8FkfkAQcN7MadG +P717qEoz9vxcAYdU+5EFT5VRBmHi3Op2lmdSNisdrgguC3VC4uQaFZCnbKc46oE2Wpmvmshhg8l 00BiRMEUVdHsJpsyAMB2ww0NSwlQLcYVK65ZCbTsMXu/1s7d/lRO9x+7fAVa8IlIha597BPjFWr5 tICZy35TTaFStap246Ab0yY9eoj0/fSrLkOjzwIbJT78LCRRhFr67QxCno8Ku10Rh4CK/VnVv+bD hILQOOyAzy/THDfB7p6XTTJqmsXKR2W3A1oRhjzHgETeDTgKF66QsngnUD6w+KqwKOoVnOOBiwUz WmuwtQ3sK8KvyGTH0lvSUcLFKTPT0y3vokGHZ7wElJT0+iaA3DU7BXy5bCnhF+mMtc/klRfY+3fM ZGJJramrriwuB8DsLSjtHJ4RwqnUoCjZPb1DdozgLKKWx1Mm568yZzZTYiAswHU0W7psWLwUC1fH 3ITQV5TKES820zXKna2lJVGQ4ayG+Wzix52q0tEG14NGH77hIn2FK/rPGj+bAHr1HAVjSyWQABTB Q+Lt2vAYt/sLGXWPgiuLHFV3M9BSW2wCbXNsF382mSHz+qFacjhFMkvaC1IFjRcxS/g3iYjFWuIv UYgzCc1Ii6+tv3NJdQqwtocnR/q5DTDn4KR2OR8YX3F/HsbrtCkLfLFPF2P4SgngNcGS/6vaG0ba FTpyfEpxT2hwjCEv+F6m4/fwnm3UqyoHJDZGssOZv/BDUu9xQOrMhr9Ec7foKouYIo2YAu43iNa/ r7K6AoToo1bIOFq0Ol8VVheOGGVroE0rHBiLSA7n+8TW48wn3Zh2K8j7vLJ9pDDEnqGG/5I05mL+ K+luRaT5jDmtbIm5UGd9vgE+Nkqlow8lhdbFvUjtO9z5+o+ysAd7aC+MWbLrm75w/s3kQygV4HPw pgRv5qX6unq3jBGRpn4ETJ4vYxAOXs4de8I1d5AanDokSAUApe55zgHho0klYzsjcqQAsRUYs/CE zuKAIfRVq7husmLi/KO6G/rlF867guTQIyBIsHuUNz6U9xU1F4F6v8PFqN5qqGI3nKd+Y/fN6ZMJ u40AvxYe7fOM3ZXK20Me6R6pg1LetQCVtNvDJL/shP7hXsDNNqusM7JIlL0EX9Xfb0iX54XtizSh ArVHRuLrO511XHn37g6C97dFZQJ5TouKLKc9OIdN3ka4Y3Pm5WOBuq4aABUTD+Z11qyURfdhpB7O Nr0B2RrafqMvJDAolXXYBnF7jpss2kqNdK17Iv6C9oZ7avoQLIaFXDGJm8ERNFPgKjpAeSxius0r U9biFbJYmY3Wq7tDj4Y33oZvj8Yh763lu51tBOhM9hOeg0U0du5FgX8EHZXFx1ofqP6xvLShlFz/ TaUQ2grxEZVodOZK/grRwhTj4lCE1rdHVWv7EJjgrClVO9R5wrzbwPpV7FtzYMoKvcVXrxwIXbtm 5/RoKAjEF79Iy1WpI7FfL+jKWuROvtl5zLrB0UTcYzJHx+97Sq2zuStME6g13K3JuNDPdYUMV76W p2BZfF+tb1is63IVKlr8Mzdbi4/UTDf5ZkKH4soFe64M0WgSzwJLdaj5lq1fLQT4dQrEIzLbh5EZ dFJLuDQUhTkjwAoU8WFx2m1qJqlJhw0XSk3+9f4BkT9YW5mhe97q8QSPQ8Kvs+0fodHXzUTP0nhs pxJEssLJ2qejRJx43qIN4d6g0WwWQDlN8mjKGLw/PxAc53pxLCjxfrpmz08uZi6Xr1CPT9uwV54m AijHpYlX+SukzJ3Nv44jhLvkTWXbvA6WIzox9JsI3LxzfUYZhlfuahdVyCP0+Z0gGrOIk5+2a6W+ +1Q6cLbjQOf+YPwGPmW4VChWiAD57Dv0q2SKmseqKfF+qS1Bt9aC93xFOj03kgdUs0kfsPlMz0Cm f0BOHOMsxYxK7fnHNbcOdVGRu+dIcKW8YBF7fkWbLL10/yvx5LmPDWmijiniK6pPQ7O52PijsHa2 E3nudbb6FhKdRY2Rf37qJl1MCKJqmAQkQ394s9Yo+nuG+jSynjx5wcrsSQRPUII+BOlipM3fpeDf DqA6pOzTCFavKgOBuDj/OJM1TL0lYCsqotIeGZRxyY4BH7h6icbNP/xI4njpF2fjVWwoEp5R3o0+ 8AYuopLlI8UxtuS5T1wsWmeVXKGKqtQ6mlDHgFssHTtzsZK41IPbmOBvgudflEJ3+iKpqGTsijuI 7JlQSxBwRGmXoIAmCwHnSTiDJVwCnWsG3TqjUwMHg5racuC1/QThv7XiCmNZVlY84gK/kbqIt3yb ghH544sCTaX8M3ZxuaQnQo5T2J717/CuhyOdXDk5oeUPLpjeRAzkHCoaGZbyIy9YX53hms6uZ6Ot pJx3i0hcuEfraT0bmOzny9HPlv6eJGa76IVAbkEDNMqD3xHjADzl1U3ZNWopcUAjBeTUTSpP+7u9 es7S/WoaqfNS0MhkUkNlhFNvILj2I5pahhxQwvDXhh18JkM9BSatP25HIESKMtcRun9dHA/Ab/4Q crBEUy9uLO+nuLi6tn/RcoFWBiTWJKTl7ZBRcia+/fNko4uGrSc5123r3IaMlcM+SQovMkBeDt4W oprQQofIqRPmFDVMEeV4MHjsX+BzrWWjyUqQ4JOUi7gXm83C9l+YUG2qG4npVAEC9f+QRdvfLirm gspj0CRTfO+NtequMv0X+8pljgz0f20CHBzGk4tOOM2PfY5zqB22FaJ06xVWr3cq1X/xCP3g8qLH HsL/YUvJ9KK+uGeVN6UzTAE8p7ZpTV5DzkchRekpdbLNZm/z1ji1mFDR0oUe6Rugfu8QAoY2BwAT wufbXiv+1FjgPf323r8NOIc5PGAWVxP3LXqr8whsDjiqXvbjEBFfNcvhWhlS/NeX70x01xCRYKYu +NbyzayHnYNvm0s2wvsAMIVkao69SVHIjcncMPspFt9vivb1Pqa5I5UwfjKOFEsSXLaPOyhR3qPi ychL6vJtIZyRuazJhTPzcYHD3O4QFJaMHochOQDcQ9VkJnTUkp6BviN7W3OPXZWwD9RpiWOa5e32 0bJq+9Qt73neSChH3neazCVYG+K9bOc+XG/+2WKFGuxEvoOMNcQSvvFS9xprxYHnTxwCEdgoHREC 3cmBg39AOD1f3h+1iCxcrRD2Opv2hqj9u7fBSX2hfCfxP0JP6yN+gu+//faL0rugwA5mNnUaYoqj VUTgP3dwBdwaiduLPCEz5iI1LDHQDcIBlV/nnoFPJJunCUybMSrpfTwf+MeiCFHunEpFWXcgYsMm Nrzom8W7D0tC5wSMmmcuFkWsnwSJpniQR44wsnvoSmzgMlVURKIo6x2trEMhV5GJMiCzjuORb4UF 6yQwt8yzgUdUAWl3vaSLejNcuVX1SAo29WVfCplUBVhLnyg3qpkcWFntAUH3HCs5psksNc5NkQfh 7MLZtvLrkjJ6XUxGmwlTa3j0gTOjBBxGYuodtle+TVrMVqMJ5hK2k6rM0msRKiGBdWxONlszJLka zfZpZZizjtDyKCyatioUWi8T8bzKNoOBVyPLYuSYAR3dY8Bjks5bTzBdg0oEVheVTqw+tGaPrV0A 5jJiLClkOowUWL/Ke6qGbVqxJ/OJN49Yc7rfHjRizCeS7Fm9PcDDLNuORAa8DgXaeAQriM72KxnS 5VZtaiiEvrlAdE6l18xoQdD2iX4QLom+dNuEeObEoAzQQh0NqMTuokKSZl9cMJ6IanDG3gKJ1RiM +eC4/PvlkWNhySXXhIMI7suTps1P3wu6Y6ybon65L0QK9WOzg2DNFYSc0+N3CDyCOEfLXD3keUBp Dx8biSUcmXz2GC88Ye2cOTgXMtbDAdd9mFvnUGRUQwE0aeqK8akFaOddvQAVKa/D0XAt5aa7h9P4 I3rSOIhL+AAtl/oa5ZdQBFJGkqYsiI/R8knG/4ftsw50E+MtDieb5pdkjhFdbgOQwF2ua5GEi8PR SX72Vv5TVwvmo7mB2Eq0OussImOvnnFNd/vUm6+kVbbtdhiuKFdPhvbeoLeXsb6VSXxu9nSTPQjy u4RWoqJ18JB6Ctt3+9SNbnku6rp0J0Ylg+2uhyL/ku19TcH7zpxrIfOBRF2sNcKLKH3z3sDQ38QT zf5b1xwyJudkhFjcenXXpvS4MoXh4ojwQxb5nM37Q4F3WhcTGh7D0zcENWb6Ti6ddK4YWw6TSez9 1cS4eqYu52XcXhJ0iQwdJhjUA8+S9JEcVFDo2fMt0z2QkMPoX2d3OUv4YZkgGLUfv7K1cEdkv/84 v1XG9bnbRKK8XVnQ1S03caTHVayHcEhvtaaJDQCz7bdM7QUAoTQ+w8QARGnJYqDLIhpbd8BtpnFB 7aK+VYSEx+MvjbWSMHVT9VdwTSZ+AFZnnOHpclk3bJv6J57+0NJ9h4XxoDx0DlwtxQtKMSFCXN8a zQQrBqcqMmWF94CiconBKcm+YGuAbYAlXgO1YGbrTQkzpwQrTN1SNkGN16dYj/Uuyg154FQZxUir x/DtY76zxfJJoxO34LFtyPmApyg1AL7Xp8jYqqfVz50qIj2zlP5J39CRYyfe7YVOzGVZHCgb4oTB QMvN8ImCeELlibhE1Ni4eP9eU/vGgFFzQxCZYP9o+xUPLL5ThVXK6sTSBcHfdukmGeLGAJmixPHK 2BJfWJvgc37sYaEdW1TfBujqxIEbLQQ9qAjVHTTL9GP8uWTOBzmcihJIz3e4SHn2AxNOFdyaZhLk +L+FSgQsFFntZ2eLYyj/QE9XPnAberjw77FggQpbR11aQ3dMjQgQPCTI/U4HwPovrBh0u/aaP+Lx 36eVIszTvApukfmk+b+ypgxVRPrXPmafm+ifbPxbPcvymOlFzlKJK3SatgvStC6BYjRllfzxuUsx anckK1kOMZcFtd+xvW4EK6WXcVMs5RNYNSetHUo3CE4FgCZb47gkF5ShTRX9ZdptPR64T/THLESu nt2E9cJ4cpqSS/8OKIOf9D+huDlp1RZ2YWSQaU7Vi+BLNzl93jaDtLTGoFRibQCptUJUchC3ElpY 0g+awu+WbHNJB0ecXFI5HROxy1E+fnivoyd1MPnFphU72QTGvt0V1B93MJjW2BHUxSOlejmtM/cU wZsat6k5f2Qyy+T1U8MahOUA+E5fX5/svITmiyTNdOX9cIxxNiy0AenTQNygA9m3JPEKM2efEhZl vojr5nSt8aGm/bmKx//sRlvE/4mNeu5TahFBo1xH0YF+ejG4MhXoc33sG/UMJP1qG6ADmRUxgSHM HCXH51rOCnFhAPlC7ZxYpg0iSVm8Mbj6Y0NkU8/0csdFQhTPDr4kSCz+IpFWWZXVQYsBplWeO4FF 3u3ueiHih41Wb4PENNrAVGf8JsFWPaEXjICUz2PmTI7uP98w2XLwQNYpG3LJjZRHm/e5HtkN91Jo sxUJkabh0PYBjxQJyQZjEb+7q15H6oJA7RVzkmqBqVPvrzDH8q9598MmLC2FSCnEHW5yXrFsR3HY MxYYxRv4EEjeU8I4Lt/mb4x47gI5Gpp3Sd5ErNhUg8nhaz+jCn5xQwR2qmmfTk8Ka3bH9LbrJqq/ Ph6+7oW2EonOb2FPohD2CFJHYz3vOlujmC3h5P4MU3eSw8GHmWMWHws+RnRYPqVluEkXZp8Um2CU jTCgPRC0tVt2wC3yeymt+z5CwdZApMYgeW/SqbFI1Y+qm/BPZtPPM6YCuGjvZZl3CDxB1FPxsOzA 62OYE/tl0U6v9MAFgKTprnhW7DNDSvOfpNh81P4t3unQ1QSeMktR13U+oWlqbMO6XQDWWOoPiSFh UsMp/CioxUl1X7qcaeruB+ECW7+rOjub6Sa6P98+imWdTt71TYEhlkzP1wPCyS0xPigHCAJbm6xG rz8Vu8YOMAM8nxr/Bwl5mlzW/L5obuE30iYDCVbRJO7jSktaVypYkAyjd+QaS03ahpNtJnfPPFPR VYgMp84uxPB6Dtm1ycex5TQC/iB1hSn4NXmnzjDWx0zx8ihm+hYrkfOYVAVcKWL9XEDPnPl17Kcy OklB7TJCYm2XEnNEb1HtfopPlFV7eMLOCEvgdmhv07S4Y1pvRUVAivc+SzYIFNvg2iUVEuhVbLOC O4HUE5Qw6RLQ+O3Qn+xyI8sGcl/deEGQcvd1JizCcRuy98SAFyYqtFkFe+YJ9UayZs/HZQr4fduR xGufXIb5uYhkhgHA6z5dBrD7U2ney4Q23XLH7Zg+W+uVcoVwxsVWwKIKzNebqAAMBLBVRnFNxe5i Jp33mdweCe4RvhncTLDy4RlfomNqrTL/Qe4uRok7nYtMAzjKsKD/m0WWVl//NONU2QZm5Yi4oOOl 12Jv9ApImUYkyFar0uDPTVoB+FVVuNznTpNfbQkhEkChGYX3Wy1HUGmjH5dSVU+DHhwWiMkgAxl0 6FKf4tN3+r2GxSbo6enhwh3rhk0F/bcC9/Ephy9T+G/ZDSOgNnvzHNkux5WvCJNnltALRU72BCFI ttXvszHCmCYA9ZNU05zdNAbNurv+qTsny1a1f/+z34UhgCkwgZKi/LCNYVBYamcLZEb+BkybsKS5 JvHfWOHEKENdJ16T9ReeCyH7sAcfimMPXWuITpmNDpcGsNjlyTXCHB1sLHIbxH80KmcA+OR/Wigs wqnxEIvthqslgbT28ZpGlN7Fj+friwKZVwah6xwDYVw2X6vxrG3NJY7KmFlEEwKGzgjHhR4X9zdk 5R4seIFiW0jwe8Fm6Z+IHFdWuH/K+eSp2bwaPhQHJ8hN4cf1GyWxVDdXVqWcikeTU7G0IjnFYWjC ruXojjhiui42c/c8CCOlPeudWwZ1D2xIwaXrGHLtfsQmg2MC7b0mEVOlO2nu1bsThdU830lbAlQo 1vEmHklpg1XmqmbWysolxngXMzCgOhAGL82waW0WAoTG5nqJBhQGmVwH9kroMkmr+eIx/uXh4uLe UDzJYPspH8JiTqHdn/a4nm/Xf6wmDPxV8N67W/0vJwGSbYsx3TKgvEkEtV05DeypD1RDruBjwSTn JxnDlGj8Pvzm/D303SrGHMfUUALWQPZyrrHO7G8BCjOid2sslcdI2W5ceH4o4bMNTECvKpwhwSFN btvANxdmT4MoiLJNmdY+/Qh42oBCZflmyr4zdXVL1+t8xOljoAkQGcA3TC0y6A56T7iYudGBgn0T M3Hv9hC31ezif4hjj74WfBGWQ38ZZH9HVyGeLCLl/Vhw8MWT/ROKOo42hI6ag8XfOEqi/FHXPlZ/ QN5Ui7oSR+g6Q657/+Y2as+H16VNrMivcwbKmbDrtwq8mV1/ya781ScUitGZ9HEF5+F8+ZPo3HzD Ty7sB44QrmUlROM1fbqy0HZ1Umays6atefk1W+03fdDwYMvKdBlZcx3FVwX+vs239HIhD9VQbWMg CaCfFgtB2TLWjFTkCwnYUVNb1DYuDynDygfE1KfB7QEZwgzj/rMijizdMKk/7uRDbOkcUO1A8RmW HkedbYxWg4EHvYtRlCS6Yosfc+fWACQzshYy41gAo4c2gPBegv5scJsFqRmwreDDQ87LbfLukfze 5br3udnMHzb2IfuJuCDNnA09mYlxYgnFC7vox5Ed1cxpIk//rjseD6Gies7NAGEUOcg0BGeZMuya c4MAQA7G4q3VxDTLTD3SJZxsEbWLliueGYc3KivKAyAJ09sPdNS6qNW9tWYzmOpUsWIWlAw3Od29 mrRMmrnugbJDznogNPcDZ6sBBxAGZJjs1VsODT72/hU+c920ev+cY8GYAHPxI6MVLLG39WN3Ik9Q MeURgaPD1ygVAvGT3kf9Zvlz7y6jCBhoNj1vjRI6ihwDYel8fp29OgkGe5DA38IjRJRN20Tf4wu3 j0tXca7UtDWZkotWQ4tzanmQ782WO9BQdWnAFu3TVLB15CDvN6vSz0pWeHScjqgAOGSFlzPrGGoX QFv2Fpg8V2y1CAnfwAM9PqxKD9X3Ujrt35GhkGSzrlfDZ6Dr5xNyvkpBeSjq5ZMvb+bP6wDmda4a ld5Ib5amXp9NgY6UV0KsDwitOSYBvWSKzJ2ZWX9kkGiv8ji4eUJ8jJGdEcyIiCG+DfktmBeF8VH6 Q9DzrLi7c7emQX6h2/W25cdNfG5Ov38NnEA3ihKtCcv8cDZOqDVGLsJ+n5FM1cAHmreo+UE7gtdJ 1b/JX8wqFGDvXr16HUGPuuLJ0oiBejkMbnBoQLMg/urTiDZrUn5kAeh1qQVekhW2E9lP1v7/+5MK m27XvOLwFLsYzJ+cLiRFXPCIXUq4FQnicmRVLjOaltYduxyIwUyVkcRJGgw0HsDjRM5o5YXuOFTo /sqhcU31oDIrlpCjjOIJKCquSebYAkqFo/DJVHW+GdiTJmVkPa35zosA5YI7J5K1aPMcgcBGwZbF EnmaIHh56BCcDNrho7yw18r7zSUBq3k6EllLGxXtVQg4/tIEklolBrsubzuRe/9gODkIE1yQBN2E JdZOQ6gXuhsdw2reZOvhD5zVctBUYcN5+VXDXZ0wcuLj9y1t95iDnRC0h76KnObHAU79k/pIAqrt bqSMbwITziPnD8uEldqX3aC9a2DegUaAkHCBuWx3iSd4n8KUgI95nmWL0E1yG64N13rJy29/XiW8 6YiDqy3Yt4Webwl4Rneuk6Kia0da5Sq7GW9d42/vpKgGbrQUpBE6qIo0qbrmU1gr2lOHnWAzJZ5K 5mVt9WHs/m6dVuamoM3ELTwfM4FJaS1ijpPkc1zlq9NWfToyQFNvrfHj3lmPws/pWpbCqy22C6je nbsBurxlyn7TF3EeNuEd1t2LqgCLbws+ETd1ehMss1yQ1fuG4yqF9jTYh5AmFFTjSrO/7rUL4D4V ikHBOW0J6UIiyACcS/sjnc7giDB30BpNogt6fLqTyXvqxTfnbFSDgD6OmAQU6AKBXvY5XqZO58E6 D2XWn5+AXvOvj1qHfzprFsxRknzKRJsjwJU0F7N5KKIgn6x6HuuON8hPnhNET/KWwQqKA9O7yPoK 9AoKOgL3VceDUpJf4ZW96R/QHwVXHMKZ0cMaV9YiQN8/ZH/IL4QFmokIoF9O0cynlTU/R57SWqP8 wIl2cQs5koE5EQmvTuWltopTb7RA5HgK1QurhEXoDrbrwSCYHiFnV7zOajA3fJWJJGvONbNpMvKs eQdosEoH/bQgikvWY5sM8GL1dP7AonV/at4IuXvvlFGRfweQIuGFz8ag+7PNbk+nnbnfS8c2T4ja cyi82m9wOx73PYcFzVLPj7VSCWeFom+BxrAVsaNuoM9OLpLY44gT16JIHzdq92S0Z5DQSgh13Ilo 1zf7XkO2Nsbt6RIgQRnB9IMbkv1aPJZd2MMpqm+7bcALpM3X6/Vl70Ac6QTIu54SDnwvjgIzKkkh 3al5cI5/IsRBtX7xLnZ0sfyS7fn6el8ZJTXxP5UUqCZqyLeCsoxRZnFOs641gjA5V07DWFmkR+Xf qGLLBueSqRytl4fe9QO6C/1Q/6vMkmTQvjYTGaImtgNlYhjvIzSuOO/4cVh58PEDjxnJj1X/M8Ws SfrkkjGgGdpDQ6MR0NfEtJT1vCsRu3Tm1WAmio//Uth/AcVXcvWnp5dhljbu9GqR4GJVsWxi6Xy2 aGm/T8Z0DFMMEk0c8L45mmkMY68S/st+E40FXq4U/sxc0UMKNL6Zk+uLXCE8rOYuyIIVZb6xuZ8Q G95BL/wcjA7SnqycClevpKWg8bTzz3pTYKB72NpOF48woVz2GVD3WWqrFYn0O9oVV/w98j/Afx+G /QJ7QkcMrbLMZEbrP51y6NG1+Hvj/KvrqA87LKtQGyMTmsbSlFopDOMuaHoJsIw45EAcSsUs1/76 dok092XGnZGSf3nNUwYFCF3mGYup4gMr8+spESs8G88LIBI3o9Dtyhm9vbNvBfuU6MVZaKyUn7OR BU2uC5G1koJ49aDybV6XdRyMWRW3Wd7soCepNB62BX/+hANLNY02M/hexpJC627F7PhPE6OLGkPL 1ByRQ39w9eGlvruHRD1Nk0V0bIyTdd66fUGgE0MM1bUtdJ2YePHUrRClpQy+4Lbcr3HSWh9zbfyD Z5WOyoOblg8c/Lv4ZXYJHkcuOCmC1SdAr4/aqxyvocqLd5J6y9af8Que5iuLhjO+ICdpHhs1oPez y2DPNhWk1X6nx0M3S7U/ydFsPK5YoyhRwcRWgM4owmn9RuoNuZa+FXo9/P7Jaen2++OKZ//z5iG2 e3RPjdJmc0aUjiw8UGLIe5Zfg7z68rTU64qtjzkFonHquC2pWKdLAlmyS0qGkJiT7Vu4d+Iqdvap MMlTGjj3cDnJak7AKNxII4CnQ9a0BpZeJstcBYnctMshdYplMQpSfFZvgVrNLJj2fZoQx47vAkPf 7n6DP8p9S1EXvUVMzp/WUi9a7f3QLU3+8hdUtECb0LIlU4uksAp5kbsClnfY8CVJuBiLsIRlbcXe p+YdfuSfD0Ipp84yCTSBqJ9nNCNjWkRQLIRiBYt+a16BQZAQU2MBC4hzm3xeagKbtMKPfNcUTJgr ty5ZpJuzHtYkMfrrDW+TQTVRhQxauJ9+C1TZTR0zbrHqSgQmScNr3jH7AkkaQsadB3PDXwce2LiS dG5sIzxbP5LyVu4uafh1BhREMVQfZIkJHtYqI/KlGWk3plRPWWhKww0G9x8CFVybMnOuAq6faD84 P3fBXpvREi2eVPwy98/IIISbO3SpNTKcwgLbq+OMLoogCAZ3a5JzBw4UMjseuJ4r8XBuyxh9f3U/ cphs0UChvkgt8gyqtBqWCfYqquXkt+P5O912C+NppNPkrTIqfn3kttsSLjoS+H2Gzinqt6ohmYKD HAPhaVGcDcWp8dBcsrIcWXNJlLl1FrTQPf0UJpbQj+9Lv895oP4riyJstQWRg0DXeneYrjKdV26v LoKXPvdaeIu5YrV0S6u1/krd4oGJqkp6nGDUShqbR/Tpgnh+/b6+Wgwty12x4tFwpq2oXUTgnY1g ePafpQ0CvK4edx0uQKAp2dJgup+qeegb9c0ALryIvR7FJrnoPU6pgZGw/R+SqBjPilqC68sFsvv9 CnPm65GiAzwFgxz6IMBXG+d8ulHe3CoR8OgUvYRNQdbMJ6gc0NnOczj6lf3+9lGD6A1P97sWMOMs 7qGgpqFettxFEr1Mwls7ycCUEYrtCVLCU+PyEvllL5rDFDelL0Z5yD2QBtswDOfP95VaCi0aNWKh 3s67T7wbeB+XUaPqOE+a9HoCLycIVGWA5iB0DgQEg3yKXeZe6It2Nh8lqH5s+tLKucFsbgMQ3EHT 1INAJy3jP/JpE3NJl/XP5zqMg3Ulcqm3ZpNMUHwDRsCDpQIes7/E69RptnvlqjMzVvKOfIzWW3mS SsZ4bvh30RxHjzsC7V72Nd641nvkRLKNDW3IVI27dw2eWdSViMtnN+lkn79H7i95Tr41/W4TC2mX IVY5T0kGa3VwON3QeBu/DgzSBOPk3OTPmPaGWH4MNSK6J1BIKL7NSAWmeyTqxFcBTp3MohOVFiRM UkUcXSIsQj9M0SVa2rAh2pAq/fNBNR9VVM5FlsSer6F0cUcjuKRK2e0U2hQ+S+smDT5u24bUOCTx 1u/Agca4pwPPPqLCA/TQbfYpzOUEFibZB9DLuH+b3K66nnubDZsCakftINebOEtWnvL2Ju6HqymL 1SunyjEXe/wkPsVCw9XSpzn8yrYlOq1fwleBiOUEHYEdafP/3FRfIjZSQCOVEG4rhZ6+Y8FitqvA RgQvfAZkzX0RGosKb3U1enPgApW9nRf5qOjbTOYlKfdutib4uo1LSAHdEXQnebLQRMkfbIoVZ7tl MlCf88R5DZ9DFs/fmymlX2F/JT3h9maDeKVeDc7JJ8OEUyRofibfP8KgJBZNm4sDgmb+0uYBaAfU ltVxFFBUWHudzA4ttRlXrXgKanOo9HC5c8syzGBrk0rWR9STLXPjYbMbKDtNK6Wf9cObHGBrL5r9 dmPx8597sqMuQ0xosNHPRW5NyuLf6rAYktFeKtFlGGMxkAId+0inDvx7XR/0r20sxOZmToz1QQ5l FMWTs7fhMEpv1TGkZucPKCHIDPrVaxXkieud8sLdQZkm+PQ8JGvl+khlcA3/7cJ8sKBzGXmtnTVP 7r5TZ4gxn85EG14K8cDV9v9cs+48/eGki5cw8uBm8Xej3x8CklItsOIL+Qn0GFKcY4IU0XFdBk+y pWyMjxsrM2LYz/4SnsYDRyxuHe4j5CkZd0OPnpZ0BqwCjk1A6of2WGqr+1NnM6yXN0ZACf1Z4P6Q K2/ud4RWWf6t+hr+o8sjQpjJv4DqyGuQTPNBnK28v+293sDxHG+AAwhP1nSAh5+yGHOtWzinHVOw hQTGvZ+1hK9xDH5G4M+3BHMmhbLcZyPyh67km2frSCAXiJYCiXjVFfGFqvi4ibQNQUsawkp0LWWC 69xxpMpeF16tmUiGx1tsb+igwiiPYuIGZuWGhf6GYdEGxKsMllXxA/V30/qsJp/arxrWPOEw/lm8 UArrNDExMZFkzANHuCfd/GCMlb4KB9C0AzK+Wb8HGK10EbnrGbyniUuWOVJnW1nLux11x0akcsUc tQg7qN76keY0PrhGDRxyIiPA/It8PoYYauBeP0FQDZEn8oGWX6FbHBQm0MANMc7E1LMHgJ5yA6On oPBY6qW5Q8bdQXw2IwPs1Q1t0IuvjtBky2f3SUaHxScsm4L8SdUmz9wF5qj8jBXupgTd+qhv7WEL AlF1JgL/0vaITzRgYNf/1E5qq7UzDCU0klYw9JVVul7pdKOly0vKsKougGZpCNGsEaglh3+AxrCr ti9sjBpHy91feKYRvhszGANBkfwX2fLQ3Dl0B1ifvxEdMlRlAhSMxFrr64g5PCm+DRxnw0aUxrIz ROh66cG+yEy/mWt9D3KXzt/3Uk6GXBYMzo06qUis7O8sNtOYJPULOjkoRr+w5nc+tPzrffV77A6U MXY9/drrx/cHyhg88Vx6Ca51JyrBhudHjfEcpKtAVdqa0wUl1NZFupowphUDuU5vmha1rDBdDshW OZoUr9IvABLf8uidDYiLzoWpHZS3FHtCGXsNoSsWluJS1mLZHjFnORv0F9XuigcCA9S+3+5Zt+YO N9aKxIRw/OSTJICdoQMi0xeXMdIkLzUk8aDNc6wlGkRn6Od/lDbVOW1E1Wn6zhCNwxFor+fry89j sWm+6FmzvYddVhiR5Qw0U2JP2AZ3XR9kMIpSb0xhr3upCKPPe8DVEY2xVp6rxCuuxF2RrbKDhbg4 Fqk85pyFoR6GzY1F5rIFXle/1GJ7bzO+LJ7ZMSQgXFgYSkOjfFK91G2XNTZu+2bJ0aQRqr9W+YA5 8rwCrXsrejU/XYkfTJjD97/Ih/szm3xvAQvyGzo/FSi2y5ZPWYKy4ZXj5OgN7vV/51U5cqr5i5I9 8o3bo1kS/dw0870DTLwNlouuUS/m5xJqtdxquZFQFopipQvwBU6Ne2EaWBMIJrLojJFnRzF8aXnX Ux0Cy7kkyrRPDSGRDE5mtl37AGsUSsOIs5wUJxY3opYPTjsFVgngb2tXXB8tY0iVCAlsi9d1QAJA /ogc19Gu1GwHbuxbZAeNYgxorir5kNhnw1rg3dWk7eSqIuyXMZOFdEyhW+72eDcv929GMp1TgD0n b5YpDsZV1fmGhCo68g65SqugCB+0Bi5enJWUGv3pMmX6AYo591BV+GzN9LQ+i9B8fm71f3rcNZV2 2GO2kfnuJREN9LoCddPa+2KmOQsn9c8b3RLjfHJYShTZONn6NX8MVan7KIt/YkqWRIsprqFTmOrd iZ5AQSQbbzQngs6A0k+ocwece+bXSd/PWsXFfQOqSZwfzg/fqYSlODuHxxEEmOMHz7UdbpOOtoEL n3wNtd4ovbGJxXKXb9zc/27JHeVZ71eN3W/a/KWiSZbElg3WOjcQy+cvwBUCYizf7M1g0rV/rMVd xZNt9RWILk/G/wqwQ60leZN2tEdikUwk7rx5ZhXEfq9Q1b5fYKHjTOabe0cPMD9WLpEnH7aT4y8i 3WMGywd2EtuQi3RVGL6UGQZ/viKjpxxCdIWzFOo5/2oVGa/kOxg5CgyDbTqa+bRIhPM8BZEYy1w4 DO269QQgwWm0/dihVFjRA2sj+o/Js/doPBlnchlkXQiNwG2ybH7Exm/O57yJp0Q7a9jffyAWf3Gl tRqqe1rtmdzf7nf4gKHEyJjSDWcCm7kgSeERv0ej9VLn1zKBWSYrJlV+qzZ2Ako+w+Gqjbo0MAn+ jcKndfL6tRY+bPQHCAVLCP8mEKaHLHe9nex45S/zVJ01XHeA/TIoRK6E2zFThnX5brUxyrmrzJmf 01kvyNkAfoHhaKBDkpkkGoawZ9R3PCxiejSrVpvIds6dOsSbWNBh60szkzDwa5UnnR6oyZRNjq/4 Xq0PLozizqeV103jEtJtxAJ0+g3QRjxbzUdU8IlgnHnscEVQfHwU0ZL1vMF7tZwJO3U7BaueVJC5 qf/aBLdmKMdyR23XPGzCRstC0LK69JgK/beNTLNeSOOPILIinn4rNDheSJcLevD5til/fTshunrI lUyNTKj6u3+dZcAoK393Q4f4jd6smZz/qEqGUfXlhqQ+ctOfsPI+eAzmjAdpb6KbzCW9bL3ggVzt gKW/YhGcopGTIQceztxgByio7mGMwoaUH/jO08AA1VPpwMbspm9/dno/QWo5jyUebTmNzyD9SJY0 EFFO9wv/tTNkcNMsVX974p3riyHfyE2hom1Vh62b9dTU2H9r8xcYZmioOaN6e0GfIbXyBLrczb5A bIpWo9oRhU3TJDu56K5bPp0ynkajBRX2shwn+GdjB1OGbtF3OzzYHqOTXFyYaMDn6bjQtwWYtOD/ 6Yvk9EvqEeqE5N8ndYelfqfYsgOiJSeiUpQCHttxHXslf7pU2iUnjootj0/oFO/0p17Nr3XeH4hq 0EWdre1kT/Bn6LCJZsabcbbtS3EAdp/TT3qHKP+YUiFnp81LdXfZi4UkSAZ9Owx/T4y8pXVV96rt 2HLTifSVaIXyjrhgcrpu1Grx6FYEoOOHpLthn56qmxP5aa6rSLhblCFoHxALxZF8Frv6P9XpgQd8 wReHELD+Ltep60NYGICRnDtMeRfWQtfcSARjMt328FHIlexdiU3HdomPks3iLQ1Q0PFtHqf4fG5z HrPnyFo8KKOmp21qetgwY9G7c0mdJxgETEPPHLKOLKD3WuiGT0pUcJJuRvlqtqIboOB/9hmyabf7 q8g4JY1ABT6Yezf9ro94NEBb+66yFPeFTy0W2rmyQW5olwkT4eY/G+VDgCxFAH4O9lXlNUej75vk C9ode6F2oIN2fUVEzruJ8f0PE0lT6pFukVm79HK5RCbab50R+1tO8mz6qNpLOm+KYDb6SM8WHS8o 6pyU5Trc2Xmzc8bzwWDb89+LN1YgfD3vW2heWpa2bvh4k/qCoFS3b2Z2xL8W2iLb97J5y9hlVMxq KNVzq48KPqeU6wjbzeI2Cby7+gMMz5LtTOWfIYeu1TXq+frlcI2SX7MU7xT1Qq51JODcbrKcRjB0 iEv9UPx0taQ0VzvtFxx/pGpze+gSxkFxmN7+qtWoZf7psca9is7EmYh9pt5s7ovFQpv2fLnTigca ELOYFk1vKmBwADXJjMZyF/ulgcD4+lyyP5/gGmVuoV+V7C32akA5KvwYUe8MmWzNou1x2BFjJHvg 6uGc2HSYdzY/Ap+T7IiTKAvBjxt88pJ9Pbyw8ga94XaT1usLmDS2KgmdLjuzTi0dIHsw1K6Ef1Nc JKnYcmSbqTIUwkDU4G3dc3qQuz9UOEtCTGYvAX4cHVqwNqvHFu7qs7uCMHAXgDvTirSwEKD6C49J bbuDgTP9+kGXokDhozHTYKcxXcxASyWwf98QWNL/Ax+EG3s7rQiQe6ajo73HdW4jj71XCjs55+0d DXxIIm76ErIdkyATFR3q1xerBriup/dQrgkPhw53Wp7cvew9qygZjoIoz+795pUVhgVpXjZTMNUl rW14trImfkEwiiQvEe8rQX+cCA4D3OI3u2Nb6TJTAhg5VVQDb2vfgvbsC4RnLdNlY1ZFcd046UYC G9mm9QZWPu4K8++JE037wrdqPRnJj0aOk6HUsFDuXqE3unbY9mzf40kTJgk/k5cncgReIlFfsd4W a/p6Bgc5MUiPLgOv4MjvsHUyqa1qPREmOZsjp5Qhc7lIihr0TdDZfdDYR/e/l28BuxwygfE+WyCN nEX0C/UdTqVQza81nP2xbiPRiWRDR7RgfKKzje0KX4pAd4Ob7PsDeOwN5W7qMZvGhtd4zyMZNCUB 9y7qvFk9hEv/oQrmL52t9C55j5NXvCBpYz0oYYA0DC9Bn7JbnDko2SK/BkPytXui/ehGolaWf7DR e/85dU2E1Ncv/WzAPzZyRXv5YdI2jy+DD/WvMvYpMPnOxYafpvzVsqwrCRmbZPi1SGCzqVxE8ZkA A55oAYHDQetb85+RJ/hwq7pbBA5+BFGRLdKLzH4kzF8g/N45DWrtnvWHp9sNsYhop/ZeFUj/O4yF w1MM1zbiRjJkLDTPm6cjKNAXYsYU8EWtWzTnwOKFGMQSln8J/EfEj2tqWlOaVfFuPYE6L5WbjS5v 0LWkJYt2zmKrRftDrs8A44OMYCYgOxTK49cF1ynz1f4URfyn+WhU6Ruxr0KXw+oRmaUYSHDSNQmj 7gUsHHN6V8/l/Pit6Tdl9tGgwQ23pev+tMis7DZiBP3XIUdrcWn4RDPx3xBV3vME9lXAR2jHN+bU wftLMERj/z0zI320z48NDNg2rsIybrNF8umJJgwNuDuwfzWJk7tdYGf6cUI9JSm9J/aTAd5429RS N8+xS4PwbbCJ7/YJDnpmi4HFoo5N4Dp1yCTPaQ+bXgXSKtdYShTGFaKVJdVs1gS87sOBLBaZdIwr g1nhtycrFE/q7wvyT8q1WQXZQNqyxQz1hDx0mdoMCEY5fvd3+YtI3LKC+tEq6x4sN+K/3Zxn4eFa LYdwusLIyUxB6j4QEZBL2aqRNY7Ym5FY2fC9ps7Yruha5YV1brcGbsizsBODwBx62OfPQBizHaak 34HHDsD9jhB1qoWOhgg+9Whf3s6cwEH0piEK0TmfMA4NrDW7uXqk7DATrEGfNmOn6RV3jKlhW3/2 +vnGAP7z+HHeoqOtUQ+KNS5IlyRiQjMQJhlJCJ+VW7BC7ir0r8FybbkWSNQHWjdi0iruf8+n37uy Z1xfJXNsASA2R/3+wtKJGm4EVB2BCDg5QO1Ch/5ra5/PZj21+C5U2I51fLJWebR5nPu8EasiUXV9 Qh2mD5zbYfuZqHIEJbpxqWvjxrGphnth8VyQxoGBo6DaruDiSu+ux8T0GGOJYAy5gthZLwqXaOix Obh99NLo8JFL0zqf5ju5JeMLCI6ZGBi2CYA6L+Ht1Wlvn+XzFwfpboPy+UOaT+ORyPj3QwiniSjs qXvfnS5VCPewXEaNPzk0FN3pwRowa87CnvuhJ2nVNEGQlAW/3aJesWtaZ/6yI1OcnYKLyAn6sma8 bribtWCx4xsBClttzN8sx61lYU0G2EgwSBXkIQTX6oIL/buWcetLIMtaTesQHyW0mb0hNmXsbMC6 LBtzHGHFINeAV472a6IpDnvOCvzGQbiTxJcAbgcI1OaBe6hAAsWP7LkO5IYemBViyMRkFfOLg7Dp yKCnFDRgj2JsdiEs/oQ+jbIFIev6U0NfLG0hv7DXPBzIK2B0Jdp9seyGAOb1V4B0tUOojSy2a2TX EXhxtgAmhz/UKrgPRfsKGCCN0TUdOAZOi7cCI0PxmrlqbO8RahnZKwaed3rclDYCoyO/FVgD45Pd lbXxYIvPFg5OPj4m78zmyX3M/slKG61/xSOx0REmUhtgTnMs5PSwEowI71/lxCFVl9KkHMrhr6Pw SHqSsECuqLs7yaayviykxvsxTw06mgHc1U1I+RI6zJqLS5MuWebHbJw3aJObBcr2OJmGnd+dmHki D7n9QOwigyjlN9lhhPG2B1QUp3s12FklpyQnEDiMjIER03m4/s/2OFKk/8Bjb6LUxXQkYyXycCtx VggIvqe7XL2VegyUrLcjN7ewKfIrD3rIAZqBcMvowY2SR1y2YFN9xqWqMM5ABFgmWceLi3mSd6Xh 1a7rvLdnIlN4Fv2W0e8B3ACgwXrE+OO2yIm8NsSjYy/2mTQc6kcqS0wH1lVCIFyfRP18pOgltCb7 iylgl1Lp6tUOcVD4HpI2nGkdnLOu3LtoGGeFM025GKPSiQp+D5thnqku04MR5spWowKAHt4p3Mbu RdVwAv3Go6zajOZQj17jUi9hFTXXYWopvjDJemDE4PZCgqKVv6iT8RbAMJg8Xg3ENBXzxB8Xu95Q nSlXP7i20Wn0KafO1XViaGIxURXcgwJ2yK6//QnvVu7cDNtJgv8eD46h6W83QJ2wK2Be9XKM9m4X BQwkk2aBRW0SnAUM8LGcwRNcyd5hHQHO4xtZb1OuOyEv/sQtppp3FPvDimE8ac2gd4vCZdNL/lYN gVfX5doNoW3nfPFVT8L+pywnMMXntVI3kZFCu7eLX+HlhP4OsgpyVJ9ogRcAqqor+Rb0jvvv8vDM XMBi/Qw/6CpgVXGPIlbgdauue50aECLoU++4qzYaw8cFuFGE7cAB1gYt+LTyFufq2zru0vggSmTS 8nIzyoBO0x7b1gLH4XjwSCqoFAh4EB8CLVX+Gdr5npnqn7+/z56hJa1OAhTacX/Q8qTj7xyc2/mJ q4mJSJx13VW2XLEcQ5V7IWPxettYSm/4XksboN/7ZC9PwL72kir1C/uuaWFgkenbZhSDKH8iTcOs 6oZ3FGzeiNJSe5FdgRtkRHCry/s8vpqpnDGD0oPjPrC67cBgP+l6RUEpvJdDgAqA39x/V0eBgkpn gSskxn45uRb3RdWH3p3JqRahDyfSQxkjWJ4LZFi9rKTZKw+obpbrWAk10pcqaVAh5vsolAquwTSL RTy/ZNokk6qsoGQ/ZIqqdDHH5KM9qwUAcB+oZ5Ka0XF8H88SsKlAyjXC4gncV1nP/9aUGY4erNa+ V1iYGvpt5f5QjzmAqs2MTUYEAO8Vm689JfIZ56mQF5K9SFtwCTOv72SWkCe3GSiaDZsbRZHD9ham h+j7zs3XUXvoqiL7E1FfjuzKh5V/4UAUSVPnpcpT0iZBCKPl6B5LcS6+8XoY29aUKdoKguhI9Klc jbnGgwEVvoWoRz9y6uhCBAIg8C0r9jJfEFyclJRlrTGQNapk5sPzSdc+14Ryzw31FqozAaNKvK2D EeSmLCFz7CJDcyhjorvsIwIulORGqQpzY3SSCoCdnuDqrGu6f7iTXpooxuLKy6bOz6uPtahAHMEt 3zBMyvB1NdnvwzorsExm1IE/pWDnGGtJ7xesyUZpTkQGf3OieI9/QhVghpZhHReVse8IcluHp3hC KSvOn3oIRTfeKFCJora9yt6hFpi3GuCjCScyk5ll4JoeTiwRs04PVq3YDzzBee5aABLiGIoKA6x+ t7Pp/zaDHVi6Fy/VUI0S9uLSuZkeC3BmFohh4Htgjsm9chKaaVAZWiKZUXCXSemomGXp7NZp4go1 9BlmSiK4/lD+jQ2xS3ULHqGtQo67BkpOuAoN3rGPQfxPcZrZhk4RzOnpp9Ifo2JghBSHWWBzFYco wBygHBWbUf5rXLHjX9BSNkqOxHgjdZz/pDagSQfXdT0EZDYK76oYC9hBuhi15YpAM8CWfcMwuTqa UTzwgpHWrjtrH7KUsa90dgqrQQroOzI7SjVAkxWuB6aqVNraSOUNnvvua8oPL/7LY2VGbYx2vnWJ rGcqRw9aLnhMOKqVRp12mM7VRQ1pBGBwZVl6r/QCb0Nar/BRbpmjQeoD2Sc/8iFy2stfZme0xhJC ltZjdAFG1lzAU+pW9kSnjKQIR/K3qhv8WmeQndzm5xISgpDFMKL5lOPIO4HYK3nU9ua6rVHJgPVH CEQ5pC3Ee7DBQroyW89wD41nt37ZFQ38+m5Iue+T28ymsC7QaCkc3gwmvMVTqUhrK5eCBv8Y6GtI 1X9zYKXUjsH8m5HxeuY/4ael11pb03w94LLnLf0a5rz9cWWOiYL011yZIX3pNJAhoQs8Ti3Shw2A 6Kiwe/a0MR9ZRX8SiAYXe+Ek2wNDc/ZAwTlnIZGNa+BCqEw2gKslX74CIzYEmdEvf38IjiyRZsox cYF0OyFmXOcnfRcrDbeghHrSywTfxBVYPhfFRIB6oEUSJNPGR6kOrY9Nks3JhBnkeHhi+TBWhGlE pcMdWNSh+o2Rshl8g6eCzpTW4RXYFIg/Z7T+CXB3E2AF+nz3yURp+iEyrhR9AYS1sxWwt4vPzcll QFyhtyRUxaIWnKcGHPhJkT8XCjMqXZoM/Wn/urd34KC+eIqX+dzfsyxTW7eMVtcGL9zfqW/xoQzq x8TA5EPjJHUhNSWcXLnpCYmLJhWeCQGlHk6OjYNgz5y+2U7pCSoaZs8pn0fQC8OhzsI/ZqNVA4AI hmxO4f7Xo9UAQ5YzME07DvgCgzNnZBuVBOO9FpI5DxP1IJB3J79NJotzhgg6XP0sBZdQb0wqaU4e qXWWl7jMqMZDNhA67HlLnnhmIhzt52BrLZz6FtoEOp0mQFO0PAOL9JdWOIKod2w1KlthNgda+AJG vGVxsIbogd3RjTnQ6tghEh6hgoCShSpaESwjGQ4+x6UKJwjhcV4r/DE5t+tqlZoy7QnwU3fwpTug AZJBA5woFOgrBN4ERaPXFnbJNvClSTqJAwkPNRw5Na1pa8cDGE81pGcj0+84Hn2SakrmxW1i77mQ yR+RbaHy0S8HWpyzyEFF50td4x8YIXUbr53zCP5FrtgPYWUGBljT5qTlcrhevGdQZdcV+4Ceql9X PtZWIjkI+DQ6jTixG0RMeCTs6OgFXreyUpkod6/68/0jfJPh82zUWNEAiOORwuAfoEa40s2EHi0f jVWHl5qbVpQiPuG65UTrAJoXJvUCLBWeeu2p+Jn7t+m8+IrwlkHaZ+8GDNWzhPWeOBjPDhkZ5tkA exO0doa04a2Jn8EibjNMDN5lVwrcQprkPNsWLIb7rAMhGsHq7bSwKAkUPdW/6H2yJ9qIIcVbhtuo hKWAX13fCcJgUSAMMVrrmUgUB2zGivL0s/GwLvN/L2oih6fz7dPQSqcP4rFvmhFFBQkVV1Xs2gWY +hZovZ/4HtB1AUSSzKaFwCgRihgaLt776Z+9FlyRW8ApvWJr4oSpJXwHYrCk0/wK0vLRtoB/xWyb K+9T6t4IIQ/ESyMz2srGHhAkakW2aG9eUAlzcqGfe++pX6pcOM8qjmWS0W78Y6U6mSMoORX58Qru Qe3gcKIG/SyZyfvfvNvljdlkyOf00RtL0UIZ3psKs4R3DASxKcdbUlcGvoNSsxVRpI2YM4vlh4Dl bluv1/WGtz+JWNNQIeXTTmJT2ZPYv2ErzZCXyHKg/pHlZ4ei/Jf/2I8y9qala78LyIlzHAZnqKqX S21aaOE2vOMNycIztWWY3Fw2AmY718T8luHPekyMg5SxdimsARGVAf432JQm6nGcMY+YajZvCPJ8 GzCR9wQqma+1+KokEU3N/W4eDgGI5iilQsNngV6vfHjktkiEp3II+1ylq4HHgUylJom8sA6g3qZt mRMo1xS10BJIQlGiQJajXF/e9Q4KfgrgHX04LplcZH7aLlPTo6/sp+bKtr6dQOLsiykoelf50O8U GVh34pSJSDNkuLQtC9fNlOb2YBNxhXBfquT4QbNDz3x6GIwWbeRgdYukVy+4P4L95bbyDI9TLXJs gFDyHnR/Bcd/kZzG7Gh0Hq+B6nDjalCL+rq1AXnOLF84wF24t2gvGQddyVgEh/Vzn2oys7ALoT9I TMHeO8RleBecxowUpXNYZBJV/xY2CUpl7W1jyA5qaXfUnvSdIwqrlhyfNqCa9nm/1kIeYdXS/dfy HbXWflB3LQvZiGhztHsNDLkS+5QpoVsw5IA6+fdfireUPOTLAw3pUeAVJCHGmoO9DDc4Qnh7GOqc i5J2SQcZbolHApnXMEq9pp4BGrOdY3/ifxOEFBHWRS9avw303dAZkPtLG9YbcmM71lATC/bscRXk e9xzxzhREKrxRDkdTpjzPlkcY20cC1npdkbVmGCwiZ7ROsK0GyCliU8mJ7PERx6h9Us8nFFqSXuT guGxz+TP4Alp0yrpUq8UmW+TIw01VfvlXAypVY9pSGe/ZVjPYwxvPweg/1sXJTiotwCoFzhvUgpS F2bBq7OrH20St6Yy+ebvBda76K2Icth5dMYF8MdwT2fSA0GPA3dENxpVc5mg5M7cq4Ut3SncBaG5 CtiJGh/dWHR4Co7J+KPX77GlBZwh8v93ZbTMq/f7T0UsWt9vRNdyf32gQKWExPf68gvBzeFQg77h bq8RsrDyyyR5v4+YiVJRzSY9xkqwAiXfnEgmKIN8eka60gilWN3L5mOdil8rhwDkPJEq6yEjZLIw i0rfYq2Jcuy1iiGmymYbPmY9AedNURS71Fwt29xeZ8vQtgDMEPixjKeLXzgWNySyTxhOQ5W+QhMW 3Lw5lTnXszs55TYRzg8TEl/eyWk+nSB++Q6bwQTa6RhkrTKCo0u0C3DMBTrUKL1kVhyuwgbX5lAK tXDuayLcFm93bg84OpdKqqAtjkrc6jBXL0cwEWohRwyUrT1Xqf6tvq1GRh48iejUCWYQLymF/CUe yJOHmPDBrYrwL/eTXxIJwwwdUC8AQbVcU/WizGg/+riN8YcZBMA6zj7sqpIevHp7bWB034y0toVb QISOiNOAEhxKiIWwmLA6HdAiuAlMv1NmZlpmBYDG9r5om4KE1Cun+r8rdqMHJC1deew3DJ+kYrLo Vbj239VdvKnByKJSojElWvDN7pArboy+ffhE0LjgXfWOX3L4OtY5fRvKbLmoWPelWfUBl4rbjCJr OiqlwwSnZfhepyyLdzRegCGQcUOt1px1tKkZG8sCbjGg1V5dczDLK6GneoNg62QmCmX3h7eOSnD2 4BFRJ4i+cEac86egzQsYsIxXP1I8Q0ovqj8Ehoj2u++uKzNWcYMYoflm/OQBfygFGJVTqG27L7VX 4bAdjOvoouVNClscxQCfPh8j2/IalchypeMw4DxNy5iIwAuWWK1El211q4vtMt4OhMveDCyVxQNk Rq8pMVfa3OZkYU/JFD8emjypvXA643xM0Re8iNiyB53bXADK7Io/H2jVm18aCCvsyxh+IXU+X0Ls jEO8/bwpPnQgrQCFGvtei0j3Ynj6cdNYkagl8TOaa0JaATwSLiW6W5sb8C/CX7B6+2V5GTENz7yY Q5VpAxl08yWxpWsAST57Xxhd0T9coIJFZ1Z5YXDVwC5VCHKB62FCayNNXYLSGOt+nFM/2T20+Kbh /iSczF1r4jyIw1gxYKOZaZGjwvQyQCe9Z8WEMXkq39Wy+njtMFL51oZqTEgeRAn4YIpPT5zrsoNY cFbkLO+18R7HUQYdk9VaR93fY90/YRXKVwX2lyHuHUQ9lD3pBYIOt51teN1+IhIlSgnFNSYQDqCb h1l2BJ7AcJ2v1Ec1VzT8uwM1JBKYAcPYe3iU3PtXSfmyhmvvX6Dl0IantTM/Wl1f4BnPjntBU6D3 GNnl7wSR3bZJlbGefI9cKqzQZCkflyEAiaSeIQo25iXpR939Kh8tSgoO/0VB3In1c0vN0VPASleB EobWfvn4nkHlscaNHIi374q+NYQvrnKMjvZArE5VvH0GmBq3qD09QJ9XiNbovoOZ6CmyIceniD33 zn+5aVsnO7Td5uep0hrvZv0gpA4a627g4pjVRA7YhbimBVlhdMPceevTzV5FgrIjMlcp+1twlZ6t Erfsgu3GQjxggaLIw5251ZXLc7fX6SZW3M8TNFmsfLXRY5wV2kzcC37VmAMU0u1EWOlQiwL1uiTu jAJc0/KDUoiO+cVwaIsVGe3LTV/acckDu7UCx5wbM/D4OGHadj31+ClmM/VMNLDOAoKNjLKUU5fq URI5fycsGBf3E0Zy36YfAQvOPjG+GAdVSNH6uuAnBiB2KPKuUgqGYqOUwOjJudgEWXV9qk++SuQM pR5nG5mWirWunl9L1awrE2Dqg8k+DDdsgkC0234bDQi3yHsX7DMcp6UrgO+4c/YW2lBKgPhscgVw VUNPD8eHtmISUJ9QNFVa8NexGd39KoP6gAfgXsk3eY75gETBFOKA4kQ9sYl0lsmWTUOwu5IdNhu8 MXGW9WN0PaIYxhMnvq0cA2kkN+g9EKUs1yOrsFFg+Clibk/QLp4uIuS8T0VS8SE6hlWSZYUGFR9U YxPFRE8o9V++lZpD/gYRcTnOVVSko5ZXPHHqeLVv2ylDBxjTntedaERX5X1ob0Sy+g5iV6tq6Di8 TAhfj2HU+yk+kg8PjXiNZEUlMNjlUL3gpWnO+4muFF9TuGhVsyhJ9ilbUO6vATNeYLNdmlJfozTg nDszAM89N1y6eZ3r6av2PJ2nuCiKXkXTsG+5C8TJn4MYB5z06V5IpMWMz+fQcjRRbGSQ9rQca6tN cZStXmCZJy7L4PFWdByEiOsORm6/k/tRFQB8Gs/4eOGJKpsLPiFMlGAdgSvTg8S61KZhv5JN+wx1 TaXI6yF2fKvAl4OGRKUV5nau3s/WxfaRa53/DMvmxZErEDHlSUAFu/w8sIVk6PsVPhbjuzO3AQ92 qqLpT2A4014x9nINO4IvPcrKPo1RHf/eNp41LVhjd/rykigJ+vqXLwg2j0DGtkxzTsD0aQx/QT1+ F76HrxPOdemD+bIx3PMQ9GtafUl5YFsQXXCuqrnH8d1YFSa1dbjlrKj63YHp3MAijNVvb9+xFHqd vFyddH30SVKiKc5JQrQ7/xBJn4t4u7+ndwHMPpvV2JlvP6YQXWXRmTWlJsDV1G31ONjkJ/Bp1hTI +b/z0dzn2FXIQI7d4eS6FvglvPeiWbFEogw13L0gYis0Crs2QmlPjLxDBawzowGwsnUtgjMVxmaE iRNuMAz2C+fdAyng1Cikb85yJuyiiYK379aQ7fzn1WVAGtyk5NqB9NU525LdbSgV5krNOMtrjjgm YFAIixaWWCLBY7pB7FcqGTd2gM3R0GnbA9kh/rlu026v3tQpZ3TKZwOYi5AGLqEt20ZxqgFkKtRe oGvAsSj9H9eaJAN9keEhRUTPxKP9XEzCYKHkUPBZmq++4O+nL5FDH8sR+xvnU0RlToFM0YtmtJ4S D3D2tnA+fZ/SXgWmfBlKnKncJh1RHd8tgG0al6IEhZ7DekhMmDIEkmZkA3zWNweDM5r13R5LvKNp mlRPwd/bCEr5+c7cTysZGLrV/q0dctOVk1lcoMqeYpoqmIoWIoA8WLlVuF12S13aNdMiKEI4dbR/ k4azOQDofHciZhy4YZQxyfIMFeQ/RWpKfHYT8688XbjRHHcbLcd0lsAou1xZampiCTbtJqPKyHXf VdODXIGYUMuibLXGWOP3B7ytofZ1SjIlAcB1epVx2MYncnhnQ50HUUWaRN1i0Lqqm+lRCCvlXEZI 9iWcNGvIs+kiaOYitkxtvmBPMtw0ok3KoIs3pET4rJHqpTY2Iw2Pn0GIyA2Ls1n12NkYf9Y4U3rR YfXzuHDZbeW51H0avTR6ajXKclVCaVFO+EdkBzL/fTSFTvevV3Mq8Mz+0ziinpb4Q59hz+rCHGic SlY8l1knXHlI4KcnHicGYhhu1h0yDYeX4B8CRQDZuB8fdj4NqUihMiJFEVLCTK51GN2frivVlFaE iluRihyOXcUzOlHKyZMe9xDnBiRjDIdJV9U87VS06qeSPNWrPvzUaYoGztHltO3O4VWt+WV07m+Q EVP14bCP0Va5ldw6+KJtXzi67luc1CgtOqoNHnPfPGb/ixnebJTIv7PQ/jHxFw6lpzoBywzuoxDL +Eazjl/QZIZ0P477hkK4SVSBWO/pv56JZRrFbwwBLUQjaf6c+OMC91i5djz5rd6tJgh16OQkYbz4 hRvAu/xa2KNtJ4CdtXzhB/CZCyGGhDsqNCeZyKiASiVoque1kQ5PR4hUavm/DAHKP01zuKtFelA9 rDRCbFP3l1lRuG29P5fqgvPlCsxuHvsQnkfBMnRo3Hiw+AlaxJdCnOOU98+bFkNO0QXvsaeIfFdW l4maqR66YNyQDouDWcSnn3eJ0mK+7EMIgskSPKSZNjFsv7lO2Wgeqc0bp6hqTo8iJhSg/UX18jDp yI9/9p9CIUx6lRKDNvjt86kbyJFtnz5shFcZ85pH31QUPkRbNItA314aqCekdMnDozqx34SayOfm Jo0RwOwnjAiU8MZ/hoBSpsJxMwZKEOZWgAVPckXWqDy/dPpDHVMOcd1Wl4YC+mj4jbo6Dcgr/6C5 F/s88SjCMAGpjJaBkBvmxKGhnYMvccA6wzSEbq6NJQqPVQwgerq9nWdmrRMT8xhYnPVp5lvU9OgO XqfRtziMU9Qw4K2btjWH8rkEWYrgRuQJ81NG2oiw5LtEmlbVKOc+DBj8rzLnYNhELD3dGHFVO6rP 0B1kAafMPJrI21Jshz/uXm0acmy6OB4R/Nt/Kylu28xWmd+b1ql027cbo2fhyzSB0pg8/i5kKL5P 0q5hxEy81DU4EH/ARDwFKrh6BptB/rxW/XH4EK2NlkwlWFgddCrZCRYFXk8b9lJumc2PvkBt8Vl2 ScbQ4GcjPodI6jZSR3qMPexAbcYRedT7FQ38uSOaRySVpW/50QtatF0wHcDpNMlqKzkLznjiudla ESy38D/xbUqvqL+r9GyYJrRfgfPn5sXD7B6cl0EGuTrSpUC2fLDPancRASg6KRNbxMcQaQ8exhnP d1jEzW0sZbtsWuKhvxJN/A5mTEbxWVbwAwpodZss6dBHizkUC5vTWfMMMDH/6xEuGrvVFg4WMeCw wwTjy2VjkY8shw0FcYBOeDF30Sdw5G2tQMtpX2GcpUE9jcgr5EwUebqRPwAKIdsRqpO47NrU5R9b /zvoHlH4889K2blcaw3wVBopcqukHifX+TV+br8PyxZhUHtKHLhSapRjm27+xusV0TkxqJI/CLTL pEmsmZRPiaRlFOftZ/rb28liFlxTeqDaae3p4HlfMcCE3i2f1b+NkfwA8Ek5kReo1W3o7QY0GcBD IHz9yhjlsaSBBz+HrMUaTPRX9jZpiIxPE3MVX83c2YszQjs1n3k+lupv1wdb/QQF9U6mXRJslRC5 tBZaFfVqCitgAGUeISs4g/oiepb4vzzdLix9WKef5JrtCDSQB1c8MggD4VJ1M6PXZHoIRQn703jo rBK7AOGkJq4gRFWBmlDoKayYZr44tE1zkzslADepFDKATXoVgBi11Q3j/D9JQRaQOOQZ9ITp3ky6 NTvs+DLEwEKPguRYmaJD4nSI0CZ+AeKGNw3KYiM6W5ls35KfmPitMoeMErE0o2V7OGyHuaHlv8n7 RSSO6plzENps5Iaw0c+13SU9dB69aDS8h+o3Fv/InRg1d9QlUe4sKNMDWH6aTUHy7rGF+aQp5N2l YVjoPU7hmbH1aKL+N9szJaIEGorR3eab10FC2xJJnxat06Kw65EqSMFjHtBRsmku7WpFX5AEke00 G3pG9uOXXxhTkttZezS7gZkMaMBnHPJJMl82DgQ6oCeC1qmTUZFFP+lU9v3hBiysbe3a5zJUZPkh LS+qtPmtAtVSfdBuktqw1++73dYDeqbLLUzZiRJoVHTrPGnjhiBPCcLFpyfpbgktLXNttDN5/KAS FYtesocBsAAIA/UmULInhVfTVB7kG5WbSo1KR1P3Ygqv4xBaoJVsiqFXFyesqyrnbb3hBZBMQEjP oX0H/Rf8UXgL3Bd9qjVWnLJHg/Apcm32/kzWX1FbU6dA5l3OEhtYvwCnWNDrI1f7TbppjabIWAUo GmWHVb9zEzZZ4VJ+OMIio8sm7KPPnMWS1NmokcXFyXKbVNqvMtfI4gyZnKuchngQGMNrav5hktqD EH3WprdFuGY+gHlQPjbiOiSQYK6pHvbcgW8aaIiXNwHy4ag6iJuJvzxCyOxY4o2kbNaFWP82ZtzC MiYd7qsHiqHEqlLn1imhP8X+vcyHVymoxWpoIaPrPYINAFlkEabY65Y9RDOOyqpnbq47q7GRrSeL uIhT0h5fMTx7JpFXiEgh0dzrGdmds9BglazI/Eqb0/jvKEnjYtWGui6X4XkUF+4NZyRdSE4RajyJ xfifQB2k2wqME3VtbCmUE22Mh8yT+60GKyvfZ+4K3mAlLlxVmFhrLmVXeifGcAbHanC59ImIM7QN QhJmL2Ess1Qdh39ESzcImgwhcBE3EMkkHq2F1K9Et/n8eT7PtjZpq/Cxq8hwDeiGQRk6QNepu4rc q5kgd0mdxtuhwIpd9POqZoCpU9Ndpi4McnL/gy8h8Ryb13XSD9us1cPbwq2YcDL5jlbhkUvIaQuw VVdu6539UBj0HGAK4S46XA3j+qCD0TOGtoIRZm8qhlUk1Nzc6aA2OWXa0ew00bR6TF8nt/+1Zqgq +5q9mIeegR0ecegJ9UXq1qbxmJ1N2vgJkGLpPNC04+93NZvwdwDhQTv8sPjNijamI+VTKXQ09oSb xIo6Tn/8qAJuNCo+2ocFnhLRZ6/YA1gsMYve+A5TuEuEqXdWVG4u+I1ElZ3/v9zbtG60sZUxQgSi /crXuenvB4M4G+RppBQwi/93xycZCCR9nRt8yb20aCLbwNsApRa8VATDM2mBybk6p8XN/zoa84Tn 5tyfZbLyKdHnk0CJoTTxW5DcXcieUuord80jwa+PIAQW0HmOpFoF0gGjZvWd3i91cLzLWmBrEbkw k+9Iw0OYZMGdr06gnE3hPzuLkHn8n0uHw2TdNxVctFUA9/FyZPlleQvZ5cT2LoTtCgF0VtEvkeCs CgGyeoByuoZxjSIya+ImHkIPCol/xN5eCSkbWKm2yowXnkRFFsY86AXNJvL83nFAcaY/LFl6idGK CLnkJyrOD8RVwo0UcbksLaQa9Uf6uvsQ3iW/QI4jt3UJR7GhfO1ifBxAXOIAvhEuwkX4wcSUZKXf G1WjEgYscbHXn4vPTTdNPAvYo6mi3Vnkwoktgl6rVaGRH/n/E81x+UW6diN2h3nwyA9s31dE4ScO DDh9tga3dr80AsroymN+RqM9TazarjvHaMbqeLAyzz+ef+K5HAteeD+LK+JgaHxuNvHJQA3s17kq sbwXHymjB3HIWLksJsTARI7Abp00DeFqqs1XHdFSjK+eEEA7fux8STIxnV7qnCPhWVdB+WFC+SWa WrSEV4s4txIob5eXOqN2NaXvJjMK4GNvZG6oDicliDagwUjCTv3E5PTfgmLWDKhpbg7AH4VYm65d F2EBFqo0sbw68P2RVBTdTLmJrmzogiGMK8nXPp11AkEzO8/ad+yCWgmvBtFkZG0e+XIVqlSB1hQy Z04zy8iFfxyUnLTRh92xrnnCBJdf2eItEc8sqq+nr1+ES8smi7J6dIHGXvJgRpl/1aBFHMyd20aB e3nGkFohuVlJoD1GgkAxxj6cNNseH+0Cg+q5v6BN/MfO9g0/7TSfTHH1leWhdPZQcnuNHzJVKEVM 3LoiUMLzISNqueyr6WlO18OMQ8upV3hvSXidcOEPgVS+EymRdYZbA5od5oPHQmRnRYfa2vj6RTfO G87TP5HATBTz26VxFg11cczaL7IzFG/ymITLLzrBWJJw2/YFPzNC2ZdHGmHpy2Bb6KpEW8IMFyvn yJBRJH8oV2151JEBlHQ+yRPs1R8R/UuSZWzkN+APRM8v43kb1R4SXqJRdmCIYMn9E8HPQhfs6PO2 TXAcs6hLZz+74ThU+72NXAD832LYH3o+bQpiDlWh3XHH3xzcNLDCWeHzG3wpyK4TCNE2e1KAxM7w hRAqYQ5l4BxaizioQlhHYJ9tpp4k59gmyzV/X/4p2a22ayn9ALBT6agz9V7ILHGwKx1vudoih04X 5AJyi1pIcJJTR1P3IRiQHmU9xXulXFYMe76/Muahgj/xFqZufSK9JeplCeInGI8U8o+cmj4EkNBu wbRq750mrfhfDiARr0DDvvieybiutn2+4gviwN0FVtl2Qog0qYndTw8HxyjpFkELhp+j7R7ZoJC4 clX0BqkJTkhem/QCvnFngfpu2ml+fe/lzoZQ2rH0R4XxOc19fwXfJcBHD3Dnk/qlHd5OCobMpjwX 9p3yuXEzZNn8ihmDSaIp0fvmB8gNZ+TQZnfsBj5QeDWh+neUvLrbl8Do0FWy/CiSIzdUi5EBCPi3 /so3pqafVN0kf3Uew/2NIyFZSAQYg8HUw3nKszsV9RqpfgR5HOzK5yFnEYZhhEQHWC1qiWPK3F6y 1GEnvgSRiOUeVFARvHknUmLE8w1bxdlhKtydbhZ7lqrShXmMn4uoqjzmT5KUsJJirKHkjaBtOizo hkCe+E8FHObD7a4rYTTgOAWhjeNW7bwjxu+3KD9Igh4DTu5tqeyf3x/+sqy5sj3/qRTJTm+es6Dh BSDplg5TA+mpvOjkTqgxh/cBPmPNZUsGck8PP9lnKyS9WYVg+zqGMqjcG13QihTJe/gWf8OfUYtg zaxM9DesHE/KvminZuP/sRK0cBaYrQxNVF+IM5MZ2IvLZEIdWXc5hgIC03gPh0y4Uk0945nikLOX vEqwQIwuZZ5HpnPY8lXq2T89Kw25lS834uvQE7mH/F8xuVzHRdy6Qx9qsCn9oZyN8rlDCu92Ur32 OhXPCz6xY70KTvugU7U06v+vThYNsXUDbzUwVul1lpYXv90fLFZ1s5h5pNVD9Tx1kAp90KuOwCdM 6tWQnmDQDK/AZFeIIthRSGBcB5owcYXd6Ro9pQ/4psxlBEE2O05M35MAhHjJghEOFbrCClQRxUvm QYuK49dtNOQtht3TTe5toNllg+9f7Uzi9a+lM9BMzW6Z6KhWLFP8njc2WWJyEM+UjgKdrcLIXTgE AW5AznxLjB19rpM56RlV5TM/NoFHJ3sN7/DDTKn01TJFrbqm+zeE2dSTrurW3dol7FEhf58DwRc8 El2JCMb5A1Yw3YeS2pLqi6MxqCLHrg0WRHAn1UCUHe04Ffwcbxb0Mw5xKmIo9SUHGr+s1hY9jZ3E 0o+0eTiiTmfCiiOxrSWgEHOJHzDU3C5nuDosiUt/KzIRUvqOlwhd+9Xl3Swy/Om1XSsVQ+s1iybL n+sGqLVudTWl044W+tviagcd98TotZkpxXwPFwQ7+Ax0fnzWhDRxcnvWb575XMoc3z5HEgAQsfwt F/XfhBOg8wI597NrN08NQiqQqdEUCZUxjUgJP1kRl4BKgsKelGXlBDh/12qaaGMugFia0PoUOfZR rEHsghlYcgqgULe0KNx76KTACQzSictyXlQExhX3X0ZsZ2WuXl8Y9EfpN00Xgg+ApBp6yfSm9aGz z8nbKmpIZVlhTE1soYOkmZJm18ajST5ceY9XfXzoB41CKor70MhGJ9ek7Y8YYEEjkqGHcvRopjq5 vkp7lv+wRrd4hES5QTfkNe1sjuDwIueCdcSozsSLmzgQnz0b4U+SDF5MC7LMgq8e8HPCHPgB1zlj sB+j8Rg5K6ea0MZAKTXA++SZZln/+GH3KScIPwTFI0/sqcQknN8953af5e/5ifWObNdVC79NjQ0d bPVmrcQyja8oS1TsrtE4MADOHodfQ/xKK1VlCE7UQ2LPUIsEEOvT7RAjA7kIgxciIDz3r/1bdIOE lC4sAOxf/kKXTw5Qbnn/TFqkIme52mUb2eUO/nHDB0JtaR74M831oAY1i5P9rR8CgddjbNyMTyOT Dx7aJHqUD4MXGVbEkL/3FmL/gMTogdJcOyAh4ql4RBsuIXDdbmhfcnIhjCfI0IvIRAiHZ3jQJO2R 41tfPy85xZUj1cHZYHA99GgxRKWkj9l3v5NS85FJW5Y/hOrb/Gf48Q3bRosnmj/F4HVs5IWN3vhy fcrK59j2qT/3K8GlyUg7ujc+HIfOtpfII+RdGfp/TZCHX8my/B4QCTZhj+gLjMPClzpTcIi6WS67 qzYfj5hjTJSZNg2St3DqT/lbDKAfSccz8QswF9Eqb477h8kjuWg8IhO8oAr9BPu7xPE2y6QT5hJ8 srHBL5vfIEboTnCMxKrkXYh1Aw4CtVR5ZqeipRk96/c2a1wM7V576waW3+0Os4vwIcavyaFIQzhu wHl9eFPO2nb0xgLFs/5UAxVEZNXvVw7Kj2s6CfuwVFD6Q9yhSTC+O2K6fkgBX9Tt1mYNEC8i8bHb Q9+rnzvIybBLr8MAovk3HOHJwGyqp8R62CvJxlOkdou6O9BnOy06A3xHfdzRdC7FRt2u64RQF4ur EI55LdHWn0LQib2dcBlEl/nqj3ho6qNyRqksu83Sfg2EAGIBJ6/SAjwX/bjHpqLAhQ6qxYO5vxFg ngEj94BMm4oye82PPF53PKqa+ZjB+vZEY37AQFxoYj4qvpRME1q4IZszGwtirj+/4Accpn09yYAp g/9EmnJf2kKGZldupotQPrb6dX7AdWURTSsSnqyXJoRvHd+7zD/26/PH4gvthoWLU3CBWyVn6SmL 9alGgdCzOSoCeNVCyTl3xZL5IpgflK3TahJKjEBZyKS9rQKHEs1FJm3vLJWD+SOvzOQNwOzupnus dX/YgzLqqzWV6uwYSgyJNGYZhNJbfVPjHI37ExLSzFGnZtSvCdM5yFgR8gylbBP128YIZPX6Af4v yBOcS+nIH0NHQ4dvgYUqVOO4ObzYmhjiAr5Simk8gboK4NA0GTuxOWA+FAF82zU3LdzOLHJ2aVrp 51pSfJmSe6WuJLe3Em8gE7Ucig5yBjcR1G3CeseODpfuZO/1UT3GVl299hDCFPDCrqTkiNXs0Bxd p895dH1NRAFgGp+oxcNsdeMo3r90cas0bBr71T1olWHOehiY5G8ZEGm5RtGQ0qxF+gyNWsPidzk5 WbPHaRGizM+I/nw6ZwmPaCNNmGlVso1bGAbIXiApeKxqhihlyEhrtQMKyC21R8NzIeC7cfH2ek2l rl3Hay2B5ER6ReVISLnrndT9aiP2yLg5zIapaVjBcgYsgUXqB1DgsVF8mRG1QrSw0JTj17+fbkPp 4Q9+8SdFrLeLUHq8gwWRQRsUk54st3CIlObI4AFr92WPXvDzm1W8Ajh0EL6wRlJELUonehjiuWF7 0DToRbJa/puSfelSphK1tIhsnh9ROmv8N0LL0N00ZMBuewSYrE3pwzayZ0IdFm8TloCSTHbcVn8g GgtQMhBSKnxJd7KU1ksOlQxBvjqbz40GbIAMnojwycrpva5E3/fhwg9UNs48RBD4qGJpKXntbpTT E5SAXfVA5YlIdNOfszklLerh3m0VKvBZg3wE1fMU8Hx+lWH7IFHlCfbOUpDvPRu0cLOJ7MYMO1MQ 5zVhEh15xuKRdEHZQm9OdxkOm9DQf4praBVAa8kgNE3DJXoodrz3eGdplks5SIER97sSYPakIxil pKH4e8yln+QmdWyfoKGKg8wm7OFuXwVWDbytow1OQ0xz+LZKW6w97pRoPZwVGhOsjm6jnLFuScr8 uK4tSSRqlDXxQDSggFObwQDMDAbJh/yiVUJBAONM4r+Qf1c7B/s5alecQdNINdlZrbzYIcEqo2Ut cPUzA+Fe0GRm9Sh0L8WBAvySZezBKNuawyYdw3bbLck6/IQCjiIrVdhxvYJ1LWw5ZNf/Sp2Saffk /Tc9DnZ7Mi9F60QLiNirhO4kjMaLuF7hrHGsSVAg8+2J3Syuhk4VlgiJdbzLzA/Blgx00T9xI4DV cawkkKlacrBWkop7DH9G8bqgN7ePkJdeORp3+aK9+gQKhK7gltgmDkzkUhn3A1qEj4Xal3ZuT2Fz XOo25XLkmmnUb1fUcdcqFs1Wl9aqhIHX1kCJhAltU5z0wEmYRR8buwCQjHUGgsRgpTtQUDpR5/Fz YDdT16R+jwpX7MUM57mQ1eS/ZngxeAFLg0K1HiDrsIZGfeEM13eV3cD4t9Sce2rJBsT7TJf8ur2Z wzyNw0a0adZ5fp8eETcrByl4RhUcR6BTiDChXZFHG2O5c1SrbCMXcf0PKIDeo+JpjNcgotg889LL YkEd6itKpD/TTkxaBZvg77nq5+eeVfgm6/kix+4kzYsOJDF0ndDSHVzaAtKnvpzLfEZz81EmBHg8 e0Xbg03BOecB7k7kaAeiLo86/LpwCUnnedHOkVUxHTVw0xT94xE6wbLmZSisMw2LGsOFHjajgSDW 0Zt/8TX//KxKnjHTmbVBmBWb6Kav6E3UP7d857DiiH4KxYpOeRiXGBLXy3j5zYiDJIJQfU5a7usA v2t03LS3H5cKt0F48JrMCMHC6+fONCb9gYuqHvEe4XBd2G6SdpjxJeN8RDxY3RkmhIj5vio5bMx/ XwSkc+sGEkdUCRdAuUMLiM1jFkTd8GTh4UAMXn53Y7uZSJb+rRXDzrRELv1OckfJ2IpVGAH5tCrr c4qN43cbKDxi2t2aaF5mBcDONgtcQnvEe2333O7hODyg57e8IrE/awbT1eUn8TXtsWoIVDg+WC4p 6fu0MwXMgIutpyiZVhHLNgMbvTm1V36feKzj/VQ27aFKkUGh511s33QJeSQQ73KIdx3LJLAGYubX gSk/5sSOlc8aAOECq46Y6KXjHEj3Z9n2vrtkzPWrRCwt2h8Uy1mgzsqgHYxOTZJrFop68RQ6SfdR oiBEHW16KTdidUEZgcp4nw2a54eQ+PL7TUBEKDuZfztwfrOyG2OiweWua8Rsja8Mlu/0e4mfn/83 J/sGrL+vNia+qSFyTXgKgjR52Y8FW5+QpJClJEDZXge4YN0BslQXwE9s3vu9kbkHVOAHXfHK+yqz i3iBeshNnAVwwEvCULQji2p5bsE+C7589o0CwtWlsh3Ov7LeUbxrc7kEMPwTlx6PfXbQ/R6oGXnW S8HnN7ktwJVjEfAnMVE6qFzb0pYjt4oz46U936GIQzj1AHUALxVLde3BmZ3XgGbfrV1hTsefcqn0 /hpVnkc80ueBRdnh2gecGKfCrAiDecGCb5EMlugFHOXz+21WIKAn/wr+XoU/KOhtldQB7IpzeWvE 2OpKLaJVt18Zjgss5isvN47v2c2wP8v28Q+hnsr9M6jz64SM/Rw87jeJwG/fOabT8/nBKpxwV601 jKEVPDBZhK04E/cKwAeWxBohla9CSMzPKJ508mqPUDMJgHYVQREsvTT7ACDl1K1WCV0l4xqkpMsp ZMRP9Jck+WNY/ZtUJs3olG73HzlwdEvikiYDlSkMP4UI1/IjFFsl7i5biypP2rdKqosvFh0v0cbL alRyMySVpSV36wt0jqT3GkG923aPudytYlD7FNXHwz6j6NOnsi+Llx/OT8jFJj2PKMoQPpMuvPqN F1ZqSkie9KBCTq2Py6uJRxWM4hbr8VPT3ciGa+q8GVzoni0FY1kgDP/clAq2IQEO05sTSeNNiKKf 9aO6XUlDQ+fMmAqv+NgwqpaMyzR899muo2G2LgABNsh1i8pWYFY0ZnHGp+8L8s38qJOo/MdB2FYQ MmIggfdFvCp3uZHxrAzaNzwx9Pq1JzkQF4s6vDA3EHCxWJL6uRWD1tSCxZHjOhTzCILzodIwCoQh d/bZzbqNxoj+Nfj/ciPEdLsTabguGY8SQ3hWVauyHNt3fYcXFOdWRHErxNEVxFbaBASCnIO/S26Q O+hdYOXRUKddUwWa24lmVCZ1mjh7OWcDfwQvszpHl2e4+RlWUnUX6NfF23emGJ+cmVF99+vX/ABF HwblTspD89SiKj6PsT3sZymTKLJ470fxM8CWT1KzzZrchM7oce4TXUBJlvaqYlwmunV5rTdL58CK dQpAuqKi5WIAvEuzwPd6V5gmyY7UED7AcOiOARLKd8C8cHGnWfXY95mRu6vOXhMI4vb5mcoAclug /c6RpjGqNUsWntqfpWFd1KMnp5W2wHlWEvBKB55eIIjLsLK5soBFKATlrefkBCYMQcOynILA67Tk r1aLnq8KDWwSnYKDYhaZXb1dI5MoQkY5/0AEtLNxK3CeQEFCycspdTBRTeaBeZriCYmhMKsrsijL biUr65EyWNHml9bAuv2rx1XgZEM0PKarhYAzkDsj7+21JaG7sHU32GCV++S8RssVYANiRjO29VGk LfUdicDRTrUfsVHiUFZyzrfR4CAfubKm+DFSuGgMaMfWXiNo0lNI/erd `pragma protect end_protected `ifndef GLBL `define GLBL `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; parameter GRES_WIDTH = 10000; parameter GRES_START = 10000; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; wire GRESTORE; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; reg GRESTORE_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (strong1, weak0) GSR = GSR_int; assign (strong1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; assign (strong1, weak0) GRESTORE = GRESTORE_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end initial begin GRESTORE_int = 1'b0; #(GRES_START); GRESTORE_int = 1'b1; #(GRES_WIDTH); GRESTORE_int = 1'b0; end endmodule `endif