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-- IP VLNV: xilinx.com:ip:axi_chip2chip:5.0
-- IP Revision: 9

-- The following code must appear in the VHDL architecture header.

------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
COMPONENT axi_chip2chip_64B66B
  PORT (
    m_aclk : IN STD_LOGIC;
    m_aresetn : IN STD_LOGIC;
    m_axi_awid : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
    m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
    m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
    m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
    m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
    m_axi_awvalid : OUT STD_LOGIC;
    m_axi_awready : IN STD_LOGIC;
    m_axi_wuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
    m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    m_axi_wlast : OUT STD_LOGIC;
    m_axi_wvalid : OUT STD_LOGIC;
    m_axi_wready : IN STD_LOGIC;
    m_axi_bid : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
    m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
    m_axi_bvalid : IN STD_LOGIC;
    m_axi_bready : OUT STD_LOGIC;
    m_axi_arid : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
    m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
    m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
    m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
    m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
    m_axi_arvalid : OUT STD_LOGIC;
    m_axi_arready : IN STD_LOGIC;
    m_axi_rid : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
    m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
    m_axi_rlast : IN STD_LOGIC;
    m_axi_rvalid : IN STD_LOGIC;
    m_axi_rready : OUT STD_LOGIC;
    axi_c2c_s2m_intr_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    axi_c2c_m2s_intr_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    axi_c2c_phy_clk : IN STD_LOGIC;
    axi_c2c_aurora_channel_up : IN STD_LOGIC;
    axi_c2c_aurora_tx_tready : IN STD_LOGIC;
    axi_c2c_aurora_tx_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
    axi_c2c_aurora_tx_tvalid : OUT STD_LOGIC;
    axi_c2c_aurora_rx_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
    axi_c2c_aurora_rx_tvalid : IN STD_LOGIC;
    aurora_do_cc : OUT STD_LOGIC;
    aurora_pma_init_in : IN STD_LOGIC;
    aurora_init_clk : IN STD_LOGIC;
    aurora_pma_init_out : OUT STD_LOGIC;
    aurora_mmcm_not_locked : IN STD_LOGIC;
    aurora_reset_pb : OUT STD_LOGIC;
    axi_c2c_config_error_out : OUT STD_LOGIC;
    axi_c2c_link_status_out : OUT STD_LOGIC;
    axi_c2c_multi_bit_error_out : OUT STD_LOGIC
  );
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------

-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.

------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : axi_chip2chip_64B66B
  PORT MAP (
    m_aclk => m_aclk,
    m_aresetn => m_aresetn,
    m_axi_awid => m_axi_awid,
    m_axi_awaddr => m_axi_awaddr,
    m_axi_awlen => m_axi_awlen,
    m_axi_awsize => m_axi_awsize,
    m_axi_awburst => m_axi_awburst,
    m_axi_awvalid => m_axi_awvalid,
    m_axi_awready => m_axi_awready,
    m_axi_wuser => m_axi_wuser,
    m_axi_wdata => m_axi_wdata,
    m_axi_wstrb => m_axi_wstrb,
    m_axi_wlast => m_axi_wlast,
    m_axi_wvalid => m_axi_wvalid,
    m_axi_wready => m_axi_wready,
    m_axi_bid => m_axi_bid,
    m_axi_bresp => m_axi_bresp,
    m_axi_bvalid => m_axi_bvalid,
    m_axi_bready => m_axi_bready,
    m_axi_arid => m_axi_arid,
    m_axi_araddr => m_axi_araddr,
    m_axi_arlen => m_axi_arlen,
    m_axi_arsize => m_axi_arsize,
    m_axi_arburst => m_axi_arburst,
    m_axi_arvalid => m_axi_arvalid,
    m_axi_arready => m_axi_arready,
    m_axi_rid => m_axi_rid,
    m_axi_rdata => m_axi_rdata,
    m_axi_rresp => m_axi_rresp,
    m_axi_rlast => m_axi_rlast,
    m_axi_rvalid => m_axi_rvalid,
    m_axi_rready => m_axi_rready,
    axi_c2c_s2m_intr_in => axi_c2c_s2m_intr_in,
    axi_c2c_m2s_intr_out => axi_c2c_m2s_intr_out,
    axi_c2c_phy_clk => axi_c2c_phy_clk,
    axi_c2c_aurora_channel_up => axi_c2c_aurora_channel_up,
    axi_c2c_aurora_tx_tready => axi_c2c_aurora_tx_tready,
    axi_c2c_aurora_tx_tdata => axi_c2c_aurora_tx_tdata,
    axi_c2c_aurora_tx_tvalid => axi_c2c_aurora_tx_tvalid,
    axi_c2c_aurora_rx_tdata => axi_c2c_aurora_rx_tdata,
    axi_c2c_aurora_rx_tvalid => axi_c2c_aurora_rx_tvalid,
    aurora_do_cc => aurora_do_cc,
    aurora_pma_init_in => aurora_pma_init_in,
    aurora_init_clk => aurora_init_clk,
    aurora_pma_init_out => aurora_pma_init_out,
    aurora_mmcm_not_locked => aurora_mmcm_not_locked,
    aurora_reset_pb => aurora_reset_pb,
    axi_c2c_config_error_out => axi_c2c_config_error_out,
    axi_c2c_link_status_out => axi_c2c_link_status_out,
    axi_c2c_multi_bit_error_out => axi_c2c_multi_bit_error_out
  );
-- INST_TAG_END ------ End INSTANTIATION Template ---------

-- You must compile the wrapper file axi_chip2chip_64B66B.vhd when simulating
-- the core, axi_chip2chip_64B66B. When compiling the wrapper file, be sure to
-- reference the VHDL simulation library.