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// IP VLNV: xilinx.com:ip:axi_chip2chip:5.0
// IP Revision: 9

// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
axi_chip2chip_64B66B your_instance_name (
  .m_aclk(m_aclk),                                            // input wire m_aclk
  .m_aresetn(m_aresetn),                                      // input wire m_aresetn
  .m_axi_awid(m_axi_awid),                                    // output wire [5 : 0] m_axi_awid
  .m_axi_awaddr(m_axi_awaddr),                                // output wire [31 : 0] m_axi_awaddr
  .m_axi_awlen(m_axi_awlen),                                  // output wire [7 : 0] m_axi_awlen
  .m_axi_awsize(m_axi_awsize),                                // output wire [2 : 0] m_axi_awsize
  .m_axi_awburst(m_axi_awburst),                              // output wire [1 : 0] m_axi_awburst
  .m_axi_awvalid(m_axi_awvalid),                              // output wire m_axi_awvalid
  .m_axi_awready(m_axi_awready),                              // input wire m_axi_awready
  .m_axi_wuser(m_axi_wuser),                                  // output wire [3 : 0] m_axi_wuser
  .m_axi_wdata(m_axi_wdata),                                  // output wire [31 : 0] m_axi_wdata
  .m_axi_wstrb(m_axi_wstrb),                                  // output wire [3 : 0] m_axi_wstrb
  .m_axi_wlast(m_axi_wlast),                                  // output wire m_axi_wlast
  .m_axi_wvalid(m_axi_wvalid),                                // output wire m_axi_wvalid
  .m_axi_wready(m_axi_wready),                                // input wire m_axi_wready
  .m_axi_bid(m_axi_bid),                                      // input wire [5 : 0] m_axi_bid
  .m_axi_bresp(m_axi_bresp),                                  // input wire [1 : 0] m_axi_bresp
  .m_axi_bvalid(m_axi_bvalid),                                // input wire m_axi_bvalid
  .m_axi_bready(m_axi_bready),                                // output wire m_axi_bready
  .m_axi_arid(m_axi_arid),                                    // output wire [5 : 0] m_axi_arid
  .m_axi_araddr(m_axi_araddr),                                // output wire [31 : 0] m_axi_araddr
  .m_axi_arlen(m_axi_arlen),                                  // output wire [7 : 0] m_axi_arlen
  .m_axi_arsize(m_axi_arsize),                                // output wire [2 : 0] m_axi_arsize
  .m_axi_arburst(m_axi_arburst),                              // output wire [1 : 0] m_axi_arburst
  .m_axi_arvalid(m_axi_arvalid),                              // output wire m_axi_arvalid
  .m_axi_arready(m_axi_arready),                              // input wire m_axi_arready
  .m_axi_rid(m_axi_rid),                                      // input wire [5 : 0] m_axi_rid
  .m_axi_rdata(m_axi_rdata),                                  // input wire [31 : 0] m_axi_rdata
  .m_axi_rresp(m_axi_rresp),                                  // input wire [1 : 0] m_axi_rresp
  .m_axi_rlast(m_axi_rlast),                                  // input wire m_axi_rlast
  .m_axi_rvalid(m_axi_rvalid),                                // input wire m_axi_rvalid
  .m_axi_rready(m_axi_rready),                                // output wire m_axi_rready
  .axi_c2c_s2m_intr_in(axi_c2c_s2m_intr_in),                  // input wire [3 : 0] axi_c2c_s2m_intr_in
  .axi_c2c_m2s_intr_out(axi_c2c_m2s_intr_out),                // output wire [3 : 0] axi_c2c_m2s_intr_out
  .axi_c2c_phy_clk(axi_c2c_phy_clk),                          // input wire axi_c2c_phy_clk
  .axi_c2c_aurora_channel_up(axi_c2c_aurora_channel_up),      // input wire axi_c2c_aurora_channel_up
  .axi_c2c_aurora_tx_tready(axi_c2c_aurora_tx_tready),        // input wire axi_c2c_aurora_tx_tready
  .axi_c2c_aurora_tx_tdata(axi_c2c_aurora_tx_tdata),          // output wire [63 : 0] axi_c2c_aurora_tx_tdata
  .axi_c2c_aurora_tx_tvalid(axi_c2c_aurora_tx_tvalid),        // output wire axi_c2c_aurora_tx_tvalid
  .axi_c2c_aurora_rx_tdata(axi_c2c_aurora_rx_tdata),          // input wire [63 : 0] axi_c2c_aurora_rx_tdata
  .axi_c2c_aurora_rx_tvalid(axi_c2c_aurora_rx_tvalid),        // input wire axi_c2c_aurora_rx_tvalid
  .aurora_do_cc(aurora_do_cc),                                // output wire aurora_do_cc
  .aurora_pma_init_in(aurora_pma_init_in),                    // input wire aurora_pma_init_in
  .aurora_init_clk(aurora_init_clk),                          // input wire aurora_init_clk
  .aurora_pma_init_out(aurora_pma_init_out),                  // output wire aurora_pma_init_out
  .aurora_mmcm_not_locked(aurora_mmcm_not_locked),            // input wire aurora_mmcm_not_locked
  .aurora_reset_pb(aurora_reset_pb),                          // output wire aurora_reset_pb
  .axi_c2c_config_error_out(axi_c2c_config_error_out),        // output wire axi_c2c_config_error_out
  .axi_c2c_link_status_out(axi_c2c_link_status_out),          // output wire axi_c2c_link_status_out
  .axi_c2c_multi_bit_error_out(axi_c2c_multi_bit_error_out)  // output wire axi_c2c_multi_bit_error_out
);
// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file axi_chip2chip_64B66B.v when simulating
// the core, axi_chip2chip_64B66B. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.