// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2020.2 (win64) Build 3064766 Wed Nov 18 09:12:45 MST 2020 // Date : Fri Mar 12 21:32:42 2021 // Host : baby running 64-bit major release (build 9200) // Command : write_verilog -force -mode funcsim // d:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/ip/aurora_64b66b_0/aurora_64b66b_0_sim_netlist.v // Design : aurora_64b66b_0 // Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified // or synthesized. This netlist cannot be used for SDF annotated simulation. // Device : xcku115-flva2104-1-c // -------------------------------------------------------------------------------- `timescale 1 ps / 1 ps (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "aurora_64b66b_v12_0_3, Coregen v14.3_ip3, Number of lanes = 1, Line rate is double5.0Gbps, Reference Clock is double125.0MHz, Interface is Streaming, Flow Control is None and is operating in DUPLEX configuration" *) (* NotValidForBitStream *) module aurora_64b66b_0 (s_axi_tx_tdata, s_axi_tx_tvalid, s_axi_tx_tready, m_axi_rx_tdata, m_axi_rx_tvalid, rxp, rxn, txp, txn, refclk1_in, hard_err, soft_err, channel_up, lane_up, user_clk_out, mmcm_not_locked_out, sync_clk_out, reset_pb, gt_rxcdrovrden_in, power_down, loopback, pma_init, gt_pll_lock, gt0_drpaddr, gt0_drpdi, gt0_drpdo, gt0_drprdy, gt0_drpen, gt0_drpwe, init_clk, link_reset_out, gt_powergood, sys_reset_out, gt_reset_out, tx_out_clk); input [0:63]s_axi_tx_tdata; input s_axi_tx_tvalid; output s_axi_tx_tready; output [0:63]m_axi_rx_tdata; output m_axi_rx_tvalid; input [0:0]rxp; input [0:0]rxn; output [0:0]txp; output [0:0]txn; input refclk1_in; output hard_err; output soft_err; output channel_up; output [0:0]lane_up; output user_clk_out; output mmcm_not_locked_out; output sync_clk_out; input reset_pb; input gt_rxcdrovrden_in; input power_down; input [2:0]loopback; input pma_init; output gt_pll_lock; input [8:0]gt0_drpaddr; input [15:0]gt0_drpdi; output [15:0]gt0_drpdo; output gt0_drprdy; input gt0_drpen; input gt0_drpwe; input init_clk; output link_reset_out; output [0:0]gt_powergood; output sys_reset_out; output gt_reset_out; output tx_out_clk; wire channel_up; wire [8:0]gt0_drpaddr; wire [15:0]gt0_drpdi; wire [15:0]gt0_drpdo; wire gt0_drpen; wire gt0_drprdy; wire gt0_drpwe; wire gt_pll_lock; wire [0:0]gt_powergood; wire gt_reset_out; wire gt_rxcdrovrden_in; wire hard_err; wire init_clk; wire [0:0]lane_up; wire link_reset_out; wire [2:0]loopback; wire [0:63]m_axi_rx_tdata; wire m_axi_rx_tvalid; wire mmcm_not_locked_out; wire pma_init; wire power_down; wire refclk1_in; wire reset_pb; wire [0:0]rxn; wire [0:0]rxp; wire [0:63]s_axi_tx_tdata; wire s_axi_tx_tready; wire s_axi_tx_tvalid; wire soft_err; wire sync_clk_out; wire sys_reset_out; wire tx_out_clk; wire [0:0]txn; wire [0:0]txp; wire user_clk_out; wire NLW_inst_mmcm_not_locked_out_UNCONNECTED; (* DowngradeIPIdentifiedWarnings = "yes" *) aurora_64b66b_0_aurora_64b66b_0_support inst (.channel_up(channel_up), .gt0_drpaddr(gt0_drpaddr), .gt0_drpdi(gt0_drpdi), .gt0_drpdo(gt0_drpdo), .gt0_drpen(gt0_drpen), .gt0_drprdy(gt0_drprdy), .gt0_drpwe(gt0_drpwe), .gt_pll_lock(gt_pll_lock), .gt_powergood(gt_powergood), .gt_reset_out(gt_reset_out), .gt_rxcdrovrden_in(gt_rxcdrovrden_in), .hard_err(hard_err), .init_clk(init_clk), .lane_up(lane_up), .link_reset_out(link_reset_out), .loopback(loopback), .m_axi_rx_tdata(m_axi_rx_tdata), .m_axi_rx_tvalid(m_axi_rx_tvalid), .mmcm_not_locked_out(NLW_inst_mmcm_not_locked_out_UNCONNECTED), .mmcm_not_locked_out2(mmcm_not_locked_out), .pma_init(pma_init), .power_down(power_down), .refclk1_in(refclk1_in), .reset_pb(reset_pb), .rxn(rxn), .rxp(rxp), .s_axi_tx_tdata(s_axi_tx_tdata), .s_axi_tx_tready(s_axi_tx_tready), .s_axi_tx_tvalid(s_axi_tx_tvalid), .soft_err(soft_err), .sync_clk_out(sync_clk_out), .sys_reset_out(sys_reset_out), .tx_out_clk(tx_out_clk), .txn(txn), .txp(txp), .user_clk_out(user_clk_out)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_AURORA_LANE" *) module aurora_64b66b_0_aurora_64b66b_0_AURORA_LANE (lane_up_flop_i, tx_reset_i, enable_err_detect_i, rst_pma_init_usrclk, rx_pe_data_v_i, illegal_btf_i, RX_IDLE, rx_polarity_r_reg, in0, hard_err_i, D, remote_ready_i, SOFT_ERR_reg, reset_lanes_c, tempData, \TX_DATA_reg[63] , \RX_PE_DATA_reg[0] , s_level_out_d1_aurora_64b66b_0_cdc_to_reg, stg5_reg, SR, stg1_aurora_64b66b_0_cdc_to_reg, reset_count_r0, ready_r_reg0, rxdatavalid_i, SOFT_ERR_reg_0, \RX_DATA_REG_reg[0] , dout, HARD_ERR_reg, txdatavalid_symgen_i, gen_na_idles_i, tx_pe_data_v_i, TX_HEADER_1_reg, channel_up_tx_if, rx_lossofsync_i, reset_lanes_i, Q, scrambler, \TX_DATA_reg[59] , \TX_DATA_reg[55] , \TX_DATA_reg[63]_0 , gen_ch_bond_i, gen_cc_i); output lane_up_flop_i; output tx_reset_i; output enable_err_detect_i; output rst_pma_init_usrclk; output rx_pe_data_v_i; output illegal_btf_i; output RX_IDLE; output rx_polarity_r_reg; output in0; output hard_err_i; output [1:0]D; output remote_ready_i; output SOFT_ERR_reg; output reset_lanes_c; output [5:0]tempData; output [57:0]\TX_DATA_reg[63] ; output [63:0]\RX_PE_DATA_reg[0] ; input s_level_out_d1_aurora_64b66b_0_cdc_to_reg; input stg5_reg; input [0:0]SR; input stg1_aurora_64b66b_0_cdc_to_reg; input reset_count_r0; input ready_r_reg0; input rxdatavalid_i; input SOFT_ERR_reg_0; input \RX_DATA_REG_reg[0] ; input [65:0]dout; input HARD_ERR_reg; input txdatavalid_symgen_i; input gen_na_idles_i; input tx_pe_data_v_i; input TX_HEADER_1_reg; input channel_up_tx_if; input rx_lossofsync_i; input reset_lanes_i; input [59:0]Q; input [11:0]scrambler; input \TX_DATA_reg[59] ; input [3:0]\TX_DATA_reg[55] ; input \TX_DATA_reg[63]_0 ; input gen_ch_bond_i; input gen_cc_i; wire [1:0]D; wire HARD_ERR_reg; wire [59:0]Q; wire \RX_DATA_REG_reg[0] ; wire RX_IDLE; wire [63:0]\RX_PE_DATA_reg[0] ; wire SOFT_ERR_reg; wire SOFT_ERR_reg_0; wire [0:0]SR; wire [3:0]\TX_DATA_reg[55] ; wire \TX_DATA_reg[59] ; wire [57:0]\TX_DATA_reg[63] ; wire \TX_DATA_reg[63]_0 ; wire TX_HEADER_1_reg; wire channel_up_tx_if; wire [65:0]dout; wire enable_err_detect_i; wire gen_cc_i; wire gen_ch_bond_i; wire gen_na_idles_i; wire hard_err_i; wire illegal_btf_i; wire in0; wire lane_up_flop_i; wire ready_r_reg0; wire remote_ready_i; wire reset_count_r0; wire reset_lanes_c; wire reset_lanes_i; wire rst_pma_init_usrclk; wire rx_lossofsync_i; wire rx_pe_data_v_i; wire rx_polarity_r_reg; wire rxdatavalid_i; wire s_level_out_d1_aurora_64b66b_0_cdc_to_reg; wire [11:0]scrambler; wire stg1_aurora_64b66b_0_cdc_to_reg; wire stg5_reg; wire [5:0]tempData; wire tx_pe_data_v_i; wire tx_reset_i; wire txdatavalid_symgen_i; aurora_64b66b_0_aurora_64b66b_0_ERR_DETECT err_detect_i (.HARD_ERR_reg_0(stg5_reg), .HARD_ERR_reg_1(HARD_ERR_reg), .SOFT_ERR_reg_0(SOFT_ERR_reg), .SOFT_ERR_reg_1(SOFT_ERR_reg_0), .channel_up_tx_if(channel_up_tx_if), .hard_err_i(hard_err_i)); aurora_64b66b_0_aurora_64b66b_0_LANE_INIT_SM lane_init_sm_i (.SR(SR), .enable_err_detect_i(enable_err_detect_i), .gen_na_idles_i(gen_na_idles_i), .in0(in0), .lane_up_flop_i_0(lane_up_flop_i), .ready_r_reg0(ready_r_reg0), .reset_count_r0(reset_count_r0), .reset_lanes_c(reset_lanes_c), .reset_lanes_i(reset_lanes_i), .rst_r_reg_0(tx_reset_i), .rx_lossofsync_i(rx_lossofsync_i), .rx_polarity_r_reg_0(rx_polarity_r_reg), .s_level_out_d1_aurora_64b66b_0_cdc_to_reg(s_level_out_d1_aurora_64b66b_0_cdc_to_reg), .s_level_out_d5_reg(stg5_reg)); aurora_64b66b_0_aurora_64b66b_0_SYM_DEC sym_dec_i (.\RX_DATA_REG_reg[0]_0 (stg5_reg), .\RX_DATA_REG_reg[0]_1 (\RX_DATA_REG_reg[0] ), .RX_IDLE(RX_IDLE), .\RX_PE_DATA_reg[0]_0 (\RX_PE_DATA_reg[0] ), .SR(SR), .dout(dout), .illegal_btf_i(illegal_btf_i), .\remote_rdy_cntr_reg[2]_0 (lane_up_flop_i), .remote_ready_i(remote_ready_i), .rx_pe_data_v_i(rx_pe_data_v_i), .rxdatavalid_i(rxdatavalid_i)); aurora_64b66b_0_aurora_64b66b_0_SYM_GEN sym_gen_i (.D(D), .Q(Q), .\TX_DATA_reg[55]_0 (\TX_DATA_reg[55] ), .\TX_DATA_reg[59]_0 (\TX_DATA_reg[59] ), .\TX_DATA_reg[63]_0 (\TX_DATA_reg[63] ), .\TX_DATA_reg[63]_1 (\TX_DATA_reg[63]_0 ), .TX_HEADER_1_reg_0(TX_HEADER_1_reg), .channel_up_tx_if(channel_up_tx_if), .gen_cc_i(gen_cc_i), .gen_ch_bond_i(gen_ch_bond_i), .gen_na_idles_i(gen_na_idles_i), .scrambler(scrambler), .stg1_aurora_64b66b_0_cdc_to_reg(stg1_aurora_64b66b_0_cdc_to_reg), .stg5_reg(rst_pma_init_usrclk), .stg5_reg_0(stg5_reg), .tempData(tempData), .tx_pe_data_v_i(tx_pe_data_v_i), .txdatavalid_symgen_i(txdatavalid_symgen_i)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_BLOCK_SYNC_SM" *) module aurora_64b66b_0_aurora_64b66b_0_BLOCK_SYNC_SM (D, blocksync_out_i, SR, gtwiz_userclk_rx_usrclk_out, Q, rxheadervalid_i); output [0:0]D; output blocksync_out_i; input [0:0]SR; input gtwiz_userclk_rx_usrclk_out; input [1:0]Q; input rxheadervalid_i; wire BLOCKSYNC_OUT_i_1_n_0; wire [0:0]D; wire [1:0]Q; wire RXGEARBOXSLIP_OUT_i_2_n_0; wire RXGEARBOXSLIP_OUT_i_3_n_0; wire RXGEARBOXSLIP_OUT_i_4_n_0; wire RXGEARBOXSLIP_OUT_i_5_n_0; wire RXGEARBOXSLIP_OUT_i_6_n_0; wire [0:0]SR; wire begin_r; wire begin_r_i_2__0_n_0; wire blocksync_out_i; wire gtwiz_userclk_rx_usrclk_out; wire next_begin_c; wire next_sh_invalid_c; wire next_sh_valid_c; wire next_slip_c; wire next_sync_done_c; wire next_test_sh_c; wire [15:0]p_0_in__6; wire [9:0]p_0_in__7; wire [3:1]p_1_in; wire rxheadervalid_i; wire sh_count_equals_max_i__14; wire sh_invalid_cnt_equals_zero_i__4; wire sh_valid_r_i_2_n_0; wire \slip_count_i[15]_i_1_n_0 ; wire \slip_count_i_reg_n_0_[0] ; wire \slip_count_i_reg_n_0_[10] ; wire \slip_count_i_reg_n_0_[11] ; wire \slip_count_i_reg_n_0_[12] ; wire \slip_count_i_reg_n_0_[13] ; wire \slip_count_i_reg_n_0_[14] ; wire \slip_count_i_reg_n_0_[1] ; wire \slip_count_i_reg_n_0_[2] ; wire \slip_count_i_reg_n_0_[3] ; wire \slip_count_i_reg_n_0_[4] ; wire \slip_count_i_reg_n_0_[5] ; wire \slip_count_i_reg_n_0_[6] ; wire \slip_count_i_reg_n_0_[7] ; wire \slip_count_i_reg_n_0_[8] ; wire \slip_count_i_reg_n_0_[9] ; wire slip_done_i; wire slip_pulse_i; wire slip_r_i_2_n_0; wire sync_done_r; wire sync_done_r_i_3_n_0; wire sync_done_r_i_5_n_0; wire sync_done_r_i_6_n_0; wire sync_done_r_i_7_n_0; wire sync_done_r_i_8_n_0; wire sync_done_r_i_9_n_0; wire sync_header_count_i0_carry__0_n_2; wire sync_header_count_i0_carry__0_n_3; wire sync_header_count_i0_carry__0_n_4; wire sync_header_count_i0_carry__0_n_5; wire sync_header_count_i0_carry__0_n_6; wire sync_header_count_i0_carry__0_n_7; wire sync_header_count_i0_carry_n_0; wire sync_header_count_i0_carry_n_1; wire sync_header_count_i0_carry_n_2; wire sync_header_count_i0_carry_n_3; wire sync_header_count_i0_carry_n_4; wire sync_header_count_i0_carry_n_5; wire sync_header_count_i0_carry_n_6; wire sync_header_count_i0_carry_n_7; wire \sync_header_count_i[15]_i_1_n_0 ; wire [15:0]sync_header_count_i_reg; wire \sync_header_invalid_count_i[9]_i_2_n_0 ; wire [9:0]sync_header_invalid_count_i_reg; wire system_reset_r; wire system_reset_r2; wire test_sh_r; wire test_sh_r_i_2_n_0; wire [7:6]NLW_sync_header_count_i0_carry__0_CO_UNCONNECTED; wire [7:7]NLW_sync_header_count_i0_carry__0_O_UNCONNECTED; LUT4 #( .INIT(16'h1110)) BLOCKSYNC_OUT_i_1 (.I0(p_1_in[1]), .I1(system_reset_r2), .I2(blocksync_out_i), .I3(sync_done_r), .O(BLOCKSYNC_OUT_i_1_n_0)); FDRE BLOCKSYNC_OUT_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(BLOCKSYNC_OUT_i_1_n_0), .Q(blocksync_out_i), .R(1'b0)); LUT6 #( .INIT(64'hAAAAAAAA20000000)) RXGEARBOXSLIP_OUT_i_1 (.I0(RXGEARBOXSLIP_OUT_i_2_n_0), .I1(sh_invalid_cnt_equals_zero_i__4), .I2(sh_count_equals_max_i__14), .I3(p_1_in[3]), .I4(RXGEARBOXSLIP_OUT_i_3_n_0), .I5(RXGEARBOXSLIP_OUT_i_4_n_0), .O(slip_pulse_i)); (* SOFT_HLUTNM = "soft_lutpair36" *) LUT2 #( .INIT(4'h2)) RXGEARBOXSLIP_OUT_i_2 (.I0(slip_r_i_2_n_0), .I1(p_1_in[1]), .O(RXGEARBOXSLIP_OUT_i_2_n_0)); LUT5 #( .INIT(32'h2000FFFF)) RXGEARBOXSLIP_OUT_i_3 (.I0(sync_done_r_i_9_n_0), .I1(sync_header_invalid_count_i_reg[3]), .I2(sync_header_invalid_count_i_reg[4]), .I3(RXGEARBOXSLIP_OUT_i_5_n_0), .I4(blocksync_out_i), .O(RXGEARBOXSLIP_OUT_i_3_n_0)); LUT6 #( .INIT(64'hF4444444F4F4F4F4)) RXGEARBOXSLIP_OUT_i_4 (.I0(slip_done_i), .I1(p_1_in[1]), .I2(p_1_in[2]), .I3(sync_done_r_i_9_n_0), .I4(RXGEARBOXSLIP_OUT_i_6_n_0), .I5(blocksync_out_i), .O(RXGEARBOXSLIP_OUT_i_4_n_0)); (* SOFT_HLUTNM = "soft_lutpair38" *) LUT3 #( .INIT(8'h01)) RXGEARBOXSLIP_OUT_i_5 (.I0(sync_header_invalid_count_i_reg[2]), .I1(sync_header_invalid_count_i_reg[1]), .I2(sync_header_invalid_count_i_reg[0]), .O(RXGEARBOXSLIP_OUT_i_5_n_0)); (* SOFT_HLUTNM = "soft_lutpair34" *) LUT5 #( .INIT(32'h00000004)) RXGEARBOXSLIP_OUT_i_6 (.I0(sync_header_invalid_count_i_reg[3]), .I1(sync_header_invalid_count_i_reg[4]), .I2(sync_header_invalid_count_i_reg[0]), .I3(sync_header_invalid_count_i_reg[1]), .I4(sync_header_invalid_count_i_reg[2]), .O(RXGEARBOXSLIP_OUT_i_6_n_0)); FDRE RXGEARBOXSLIP_OUT_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(slip_pulse_i), .Q(D), .R(1'b0)); LUT6 #( .INIT(64'hAAAAAAAAFFBAAAAA)) begin_r_i_1__0 (.I0(begin_r_i_2__0_n_0), .I1(sh_invalid_cnt_equals_zero_i__4), .I2(p_1_in[3]), .I3(p_1_in[2]), .I4(sh_count_equals_max_i__14), .I5(RXGEARBOXSLIP_OUT_i_3_n_0), .O(next_begin_c)); (* SOFT_HLUTNM = "soft_lutpair36" *) LUT4 #( .INIT(16'hFDDD)) begin_r_i_2__0 (.I0(slip_r_i_2_n_0), .I1(sync_done_r), .I2(slip_done_i), .I3(p_1_in[1]), .O(begin_r_i_2__0_n_0)); FDSE begin_r_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(next_begin_c), .Q(begin_r), .S(system_reset_r2)); LUT6 #( .INIT(64'h0000000000009000)) sh_invalid_r_i_1 (.I0(Q[0]), .I1(Q[1]), .I2(sh_valid_r_i_2_n_0), .I3(test_sh_r), .I4(begin_r), .I5(p_1_in[1]), .O(next_sh_invalid_c)); FDRE sh_invalid_r_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(next_sh_invalid_c), .Q(p_1_in[2]), .R(system_reset_r2)); LUT6 #( .INIT(64'h0000000000006000)) sh_valid_r_i_1 (.I0(Q[0]), .I1(Q[1]), .I2(sh_valid_r_i_2_n_0), .I3(test_sh_r), .I4(begin_r), .I5(p_1_in[1]), .O(next_sh_valid_c)); LUT4 #( .INIT(16'h0004)) sh_valid_r_i_2 (.I0(sync_done_r), .I1(rxheadervalid_i), .I2(p_1_in[3]), .I3(p_1_in[2]), .O(sh_valid_r_i_2_n_0)); FDRE sh_valid_r_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(next_sh_valid_c), .Q(p_1_in[3]), .R(system_reset_r2)); LUT1 #( .INIT(2'h1)) \slip_count_i[15]_i_1 (.I0(p_1_in[1]), .O(\slip_count_i[15]_i_1_n_0 )); FDRE \slip_count_i_reg[0] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(D), .Q(\slip_count_i_reg_n_0_[0] ), .R(\slip_count_i[15]_i_1_n_0 )); FDRE \slip_count_i_reg[10] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\slip_count_i_reg_n_0_[9] ), .Q(\slip_count_i_reg_n_0_[10] ), .R(\slip_count_i[15]_i_1_n_0 )); FDRE \slip_count_i_reg[11] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\slip_count_i_reg_n_0_[10] ), .Q(\slip_count_i_reg_n_0_[11] ), .R(\slip_count_i[15]_i_1_n_0 )); FDRE \slip_count_i_reg[12] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\slip_count_i_reg_n_0_[11] ), .Q(\slip_count_i_reg_n_0_[12] ), .R(\slip_count_i[15]_i_1_n_0 )); FDRE \slip_count_i_reg[13] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\slip_count_i_reg_n_0_[12] ), .Q(\slip_count_i_reg_n_0_[13] ), .R(\slip_count_i[15]_i_1_n_0 )); FDRE \slip_count_i_reg[14] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\slip_count_i_reg_n_0_[13] ), .Q(\slip_count_i_reg_n_0_[14] ), .R(\slip_count_i[15]_i_1_n_0 )); FDRE \slip_count_i_reg[15] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\slip_count_i_reg_n_0_[14] ), .Q(slip_done_i), .R(\slip_count_i[15]_i_1_n_0 )); FDRE \slip_count_i_reg[1] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\slip_count_i_reg_n_0_[0] ), .Q(\slip_count_i_reg_n_0_[1] ), .R(\slip_count_i[15]_i_1_n_0 )); FDRE \slip_count_i_reg[2] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\slip_count_i_reg_n_0_[1] ), .Q(\slip_count_i_reg_n_0_[2] ), .R(\slip_count_i[15]_i_1_n_0 )); FDRE \slip_count_i_reg[3] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\slip_count_i_reg_n_0_[2] ), .Q(\slip_count_i_reg_n_0_[3] ), .R(\slip_count_i[15]_i_1_n_0 )); FDRE \slip_count_i_reg[4] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\slip_count_i_reg_n_0_[3] ), .Q(\slip_count_i_reg_n_0_[4] ), .R(\slip_count_i[15]_i_1_n_0 )); FDRE \slip_count_i_reg[5] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\slip_count_i_reg_n_0_[4] ), .Q(\slip_count_i_reg_n_0_[5] ), .R(\slip_count_i[15]_i_1_n_0 )); FDRE \slip_count_i_reg[6] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\slip_count_i_reg_n_0_[5] ), .Q(\slip_count_i_reg_n_0_[6] ), .R(\slip_count_i[15]_i_1_n_0 )); FDRE \slip_count_i_reg[7] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\slip_count_i_reg_n_0_[6] ), .Q(\slip_count_i_reg_n_0_[7] ), .R(\slip_count_i[15]_i_1_n_0 )); FDRE \slip_count_i_reg[8] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\slip_count_i_reg_n_0_[7] ), .Q(\slip_count_i_reg_n_0_[8] ), .R(\slip_count_i[15]_i_1_n_0 )); FDRE \slip_count_i_reg[9] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\slip_count_i_reg_n_0_[8] ), .Q(\slip_count_i_reg_n_0_[9] ), .R(\slip_count_i[15]_i_1_n_0 )); LUT6 #( .INIT(64'hAAAAAAAA20000000)) slip_r_i_1 (.I0(slip_r_i_2_n_0), .I1(sh_invalid_cnt_equals_zero_i__4), .I2(sh_count_equals_max_i__14), .I3(p_1_in[3]), .I4(RXGEARBOXSLIP_OUT_i_3_n_0), .I5(RXGEARBOXSLIP_OUT_i_4_n_0), .O(next_slip_c)); LUT6 #( .INIT(64'h0000000100010116)) slip_r_i_2 (.I0(sync_done_r), .I1(p_1_in[1]), .I2(p_1_in[2]), .I3(p_1_in[3]), .I4(test_sh_r), .I5(begin_r), .O(slip_r_i_2_n_0)); FDRE slip_r_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(next_slip_c), .Q(p_1_in[1]), .R(system_reset_r2)); LUT3 #( .INIT(8'h80)) sync_done_r_i_1 (.I0(sh_count_equals_max_i__14), .I1(sync_done_r_i_3_n_0), .I2(sh_invalid_cnt_equals_zero_i__4), .O(next_sync_done_c)); LUT4 #( .INIT(16'h8000)) sync_done_r_i_2 (.I0(sync_done_r_i_5_n_0), .I1(sync_done_r_i_6_n_0), .I2(sync_done_r_i_7_n_0), .I3(sync_done_r_i_8_n_0), .O(sh_count_equals_max_i__14)); LUT6 #( .INIT(64'h0000000000000002)) sync_done_r_i_3 (.I0(p_1_in[3]), .I1(p_1_in[2]), .I2(sync_done_r), .I3(p_1_in[1]), .I4(begin_r), .I5(test_sh_r), .O(sync_done_r_i_3_n_0)); LUT6 #( .INIT(64'h0000000100000000)) sync_done_r_i_4 (.I0(sync_header_invalid_count_i_reg[2]), .I1(sync_header_invalid_count_i_reg[1]), .I2(sync_header_invalid_count_i_reg[0]), .I3(sync_header_invalid_count_i_reg[3]), .I4(sync_header_invalid_count_i_reg[4]), .I5(sync_done_r_i_9_n_0), .O(sh_invalid_cnt_equals_zero_i__4)); LUT4 #( .INIT(16'h0400)) sync_done_r_i_5 (.I0(sync_header_count_i_reg[7]), .I1(sync_header_count_i_reg[6]), .I2(sync_header_count_i_reg[4]), .I3(sync_header_count_i_reg[5]), .O(sync_done_r_i_5_n_0)); (* SOFT_HLUTNM = "soft_lutpair37" *) LUT4 #( .INIT(16'h0001)) sync_done_r_i_6 (.I0(sync_header_count_i_reg[1]), .I1(sync_header_count_i_reg[0]), .I2(sync_header_count_i_reg[3]), .I3(sync_header_count_i_reg[2]), .O(sync_done_r_i_6_n_0)); LUT4 #( .INIT(16'h0400)) sync_done_r_i_7 (.I0(sync_header_count_i_reg[10]), .I1(sync_header_count_i_reg[11]), .I2(sync_header_count_i_reg[8]), .I3(sync_header_count_i_reg[9]), .O(sync_done_r_i_7_n_0)); LUT4 #( .INIT(16'h0800)) sync_done_r_i_8 (.I0(sync_header_count_i_reg[15]), .I1(sync_header_count_i_reg[14]), .I2(sync_header_count_i_reg[12]), .I3(sync_header_count_i_reg[13]), .O(sync_done_r_i_8_n_0)); LUT5 #( .INIT(32'h00000001)) sync_done_r_i_9 (.I0(sync_header_invalid_count_i_reg[5]), .I1(sync_header_invalid_count_i_reg[6]), .I2(sync_header_invalid_count_i_reg[7]), .I3(sync_header_invalid_count_i_reg[9]), .I4(sync_header_invalid_count_i_reg[8]), .O(sync_done_r_i_9_n_0)); FDRE sync_done_r_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(next_sync_done_c), .Q(sync_done_r), .R(system_reset_r2)); (* ADDER_THRESHOLD = "35" *) CARRY8 sync_header_count_i0_carry (.CI(sync_header_count_i_reg[0]), .CI_TOP(1'b0), .CO({sync_header_count_i0_carry_n_0,sync_header_count_i0_carry_n_1,sync_header_count_i0_carry_n_2,sync_header_count_i0_carry_n_3,sync_header_count_i0_carry_n_4,sync_header_count_i0_carry_n_5,sync_header_count_i0_carry_n_6,sync_header_count_i0_carry_n_7}), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .O(p_0_in__6[8:1]), .S(sync_header_count_i_reg[8:1])); (* ADDER_THRESHOLD = "35" *) CARRY8 sync_header_count_i0_carry__0 (.CI(sync_header_count_i0_carry_n_0), .CI_TOP(1'b0), .CO({NLW_sync_header_count_i0_carry__0_CO_UNCONNECTED[7:6],sync_header_count_i0_carry__0_n_2,sync_header_count_i0_carry__0_n_3,sync_header_count_i0_carry__0_n_4,sync_header_count_i0_carry__0_n_5,sync_header_count_i0_carry__0_n_6,sync_header_count_i0_carry__0_n_7}), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .O({NLW_sync_header_count_i0_carry__0_O_UNCONNECTED[7],p_0_in__6[15:9]}), .S({1'b0,sync_header_count_i_reg[15:9]})); (* SOFT_HLUTNM = "soft_lutpair37" *) LUT1 #( .INIT(2'h1)) \sync_header_count_i[0]_i_1 (.I0(sync_header_count_i_reg[0]), .O(p_0_in__6[0])); LUT2 #( .INIT(4'hE)) \sync_header_count_i[15]_i_1 (.I0(p_1_in[3]), .I1(p_1_in[2]), .O(\sync_header_count_i[15]_i_1_n_0 )); FDRE \sync_header_count_i_reg[0] (.C(gtwiz_userclk_rx_usrclk_out), .CE(\sync_header_count_i[15]_i_1_n_0 ), .D(p_0_in__6[0]), .Q(sync_header_count_i_reg[0]), .R(begin_r)); FDRE \sync_header_count_i_reg[10] (.C(gtwiz_userclk_rx_usrclk_out), .CE(\sync_header_count_i[15]_i_1_n_0 ), .D(p_0_in__6[10]), .Q(sync_header_count_i_reg[10]), .R(begin_r)); FDRE \sync_header_count_i_reg[11] (.C(gtwiz_userclk_rx_usrclk_out), .CE(\sync_header_count_i[15]_i_1_n_0 ), .D(p_0_in__6[11]), .Q(sync_header_count_i_reg[11]), .R(begin_r)); FDRE \sync_header_count_i_reg[12] (.C(gtwiz_userclk_rx_usrclk_out), .CE(\sync_header_count_i[15]_i_1_n_0 ), .D(p_0_in__6[12]), .Q(sync_header_count_i_reg[12]), .R(begin_r)); FDRE \sync_header_count_i_reg[13] (.C(gtwiz_userclk_rx_usrclk_out), .CE(\sync_header_count_i[15]_i_1_n_0 ), .D(p_0_in__6[13]), .Q(sync_header_count_i_reg[13]), .R(begin_r)); FDRE \sync_header_count_i_reg[14] (.C(gtwiz_userclk_rx_usrclk_out), .CE(\sync_header_count_i[15]_i_1_n_0 ), .D(p_0_in__6[14]), .Q(sync_header_count_i_reg[14]), .R(begin_r)); FDRE \sync_header_count_i_reg[15] (.C(gtwiz_userclk_rx_usrclk_out), .CE(\sync_header_count_i[15]_i_1_n_0 ), .D(p_0_in__6[15]), .Q(sync_header_count_i_reg[15]), .R(begin_r)); FDRE \sync_header_count_i_reg[1] (.C(gtwiz_userclk_rx_usrclk_out), .CE(\sync_header_count_i[15]_i_1_n_0 ), .D(p_0_in__6[1]), .Q(sync_header_count_i_reg[1]), .R(begin_r)); FDRE \sync_header_count_i_reg[2] (.C(gtwiz_userclk_rx_usrclk_out), .CE(\sync_header_count_i[15]_i_1_n_0 ), .D(p_0_in__6[2]), .Q(sync_header_count_i_reg[2]), .R(begin_r)); FDRE \sync_header_count_i_reg[3] (.C(gtwiz_userclk_rx_usrclk_out), .CE(\sync_header_count_i[15]_i_1_n_0 ), .D(p_0_in__6[3]), .Q(sync_header_count_i_reg[3]), .R(begin_r)); FDRE \sync_header_count_i_reg[4] (.C(gtwiz_userclk_rx_usrclk_out), .CE(\sync_header_count_i[15]_i_1_n_0 ), .D(p_0_in__6[4]), .Q(sync_header_count_i_reg[4]), .R(begin_r)); FDRE \sync_header_count_i_reg[5] (.C(gtwiz_userclk_rx_usrclk_out), .CE(\sync_header_count_i[15]_i_1_n_0 ), .D(p_0_in__6[5]), .Q(sync_header_count_i_reg[5]), .R(begin_r)); FDRE \sync_header_count_i_reg[6] (.C(gtwiz_userclk_rx_usrclk_out), .CE(\sync_header_count_i[15]_i_1_n_0 ), .D(p_0_in__6[6]), .Q(sync_header_count_i_reg[6]), .R(begin_r)); FDRE \sync_header_count_i_reg[7] (.C(gtwiz_userclk_rx_usrclk_out), .CE(\sync_header_count_i[15]_i_1_n_0 ), .D(p_0_in__6[7]), .Q(sync_header_count_i_reg[7]), .R(begin_r)); FDRE \sync_header_count_i_reg[8] (.C(gtwiz_userclk_rx_usrclk_out), .CE(\sync_header_count_i[15]_i_1_n_0 ), .D(p_0_in__6[8]), .Q(sync_header_count_i_reg[8]), .R(begin_r)); FDRE \sync_header_count_i_reg[9] (.C(gtwiz_userclk_rx_usrclk_out), .CE(\sync_header_count_i[15]_i_1_n_0 ), .D(p_0_in__6[9]), .Q(sync_header_count_i_reg[9]), .R(begin_r)); LUT1 #( .INIT(2'h1)) \sync_header_invalid_count_i[0]_i_1 (.I0(sync_header_invalid_count_i_reg[0]), .O(p_0_in__7[0])); (* SOFT_HLUTNM = "soft_lutpair40" *) LUT2 #( .INIT(4'h6)) \sync_header_invalid_count_i[1]_i_1 (.I0(sync_header_invalid_count_i_reg[0]), .I1(sync_header_invalid_count_i_reg[1]), .O(p_0_in__7[1])); (* SOFT_HLUTNM = "soft_lutpair40" *) LUT3 #( .INIT(8'h78)) \sync_header_invalid_count_i[2]_i_1 (.I0(sync_header_invalid_count_i_reg[0]), .I1(sync_header_invalid_count_i_reg[1]), .I2(sync_header_invalid_count_i_reg[2]), .O(p_0_in__7[2])); (* SOFT_HLUTNM = "soft_lutpair38" *) LUT4 #( .INIT(16'h7F80)) \sync_header_invalid_count_i[3]_i_1 (.I0(sync_header_invalid_count_i_reg[1]), .I1(sync_header_invalid_count_i_reg[0]), .I2(sync_header_invalid_count_i_reg[2]), .I3(sync_header_invalid_count_i_reg[3]), .O(p_0_in__7[3])); (* SOFT_HLUTNM = "soft_lutpair34" *) LUT5 #( .INIT(32'h7FFF8000)) \sync_header_invalid_count_i[4]_i_1 (.I0(sync_header_invalid_count_i_reg[2]), .I1(sync_header_invalid_count_i_reg[0]), .I2(sync_header_invalid_count_i_reg[1]), .I3(sync_header_invalid_count_i_reg[3]), .I4(sync_header_invalid_count_i_reg[4]), .O(p_0_in__7[4])); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \sync_header_invalid_count_i[5]_i_1 (.I0(sync_header_invalid_count_i_reg[3]), .I1(sync_header_invalid_count_i_reg[1]), .I2(sync_header_invalid_count_i_reg[0]), .I3(sync_header_invalid_count_i_reg[2]), .I4(sync_header_invalid_count_i_reg[4]), .I5(sync_header_invalid_count_i_reg[5]), .O(p_0_in__7[5])); (* SOFT_HLUTNM = "soft_lutpair39" *) LUT2 #( .INIT(4'h6)) \sync_header_invalid_count_i[6]_i_1 (.I0(\sync_header_invalid_count_i[9]_i_2_n_0 ), .I1(sync_header_invalid_count_i_reg[6]), .O(p_0_in__7[6])); (* SOFT_HLUTNM = "soft_lutpair39" *) LUT3 #( .INIT(8'h78)) \sync_header_invalid_count_i[7]_i_1 (.I0(\sync_header_invalid_count_i[9]_i_2_n_0 ), .I1(sync_header_invalid_count_i_reg[6]), .I2(sync_header_invalid_count_i_reg[7]), .O(p_0_in__7[7])); (* SOFT_HLUTNM = "soft_lutpair35" *) LUT4 #( .INIT(16'h7F80)) \sync_header_invalid_count_i[8]_i_1 (.I0(sync_header_invalid_count_i_reg[6]), .I1(\sync_header_invalid_count_i[9]_i_2_n_0 ), .I2(sync_header_invalid_count_i_reg[7]), .I3(sync_header_invalid_count_i_reg[8]), .O(p_0_in__7[8])); (* SOFT_HLUTNM = "soft_lutpair35" *) LUT5 #( .INIT(32'h7FFF8000)) \sync_header_invalid_count_i[9]_i_1 (.I0(sync_header_invalid_count_i_reg[7]), .I1(\sync_header_invalid_count_i[9]_i_2_n_0 ), .I2(sync_header_invalid_count_i_reg[6]), .I3(sync_header_invalid_count_i_reg[8]), .I4(sync_header_invalid_count_i_reg[9]), .O(p_0_in__7[9])); LUT6 #( .INIT(64'h8000000000000000)) \sync_header_invalid_count_i[9]_i_2 (.I0(sync_header_invalid_count_i_reg[5]), .I1(sync_header_invalid_count_i_reg[3]), .I2(sync_header_invalid_count_i_reg[1]), .I3(sync_header_invalid_count_i_reg[0]), .I4(sync_header_invalid_count_i_reg[2]), .I5(sync_header_invalid_count_i_reg[4]), .O(\sync_header_invalid_count_i[9]_i_2_n_0 )); FDRE \sync_header_invalid_count_i_reg[0] (.C(gtwiz_userclk_rx_usrclk_out), .CE(p_1_in[2]), .D(p_0_in__7[0]), .Q(sync_header_invalid_count_i_reg[0]), .R(begin_r)); FDRE \sync_header_invalid_count_i_reg[1] (.C(gtwiz_userclk_rx_usrclk_out), .CE(p_1_in[2]), .D(p_0_in__7[1]), .Q(sync_header_invalid_count_i_reg[1]), .R(begin_r)); FDRE \sync_header_invalid_count_i_reg[2] (.C(gtwiz_userclk_rx_usrclk_out), .CE(p_1_in[2]), .D(p_0_in__7[2]), .Q(sync_header_invalid_count_i_reg[2]), .R(begin_r)); FDRE \sync_header_invalid_count_i_reg[3] (.C(gtwiz_userclk_rx_usrclk_out), .CE(p_1_in[2]), .D(p_0_in__7[3]), .Q(sync_header_invalid_count_i_reg[3]), .R(begin_r)); FDRE \sync_header_invalid_count_i_reg[4] (.C(gtwiz_userclk_rx_usrclk_out), .CE(p_1_in[2]), .D(p_0_in__7[4]), .Q(sync_header_invalid_count_i_reg[4]), .R(begin_r)); FDRE \sync_header_invalid_count_i_reg[5] (.C(gtwiz_userclk_rx_usrclk_out), .CE(p_1_in[2]), .D(p_0_in__7[5]), .Q(sync_header_invalid_count_i_reg[5]), .R(begin_r)); FDRE \sync_header_invalid_count_i_reg[6] (.C(gtwiz_userclk_rx_usrclk_out), .CE(p_1_in[2]), .D(p_0_in__7[6]), .Q(sync_header_invalid_count_i_reg[6]), .R(begin_r)); FDRE \sync_header_invalid_count_i_reg[7] (.C(gtwiz_userclk_rx_usrclk_out), .CE(p_1_in[2]), .D(p_0_in__7[7]), .Q(sync_header_invalid_count_i_reg[7]), .R(begin_r)); FDRE \sync_header_invalid_count_i_reg[8] (.C(gtwiz_userclk_rx_usrclk_out), .CE(p_1_in[2]), .D(p_0_in__7[8]), .Q(sync_header_invalid_count_i_reg[8]), .R(begin_r)); FDRE \sync_header_invalid_count_i_reg[9] (.C(gtwiz_userclk_rx_usrclk_out), .CE(p_1_in[2]), .D(p_0_in__7[9]), .Q(sync_header_invalid_count_i_reg[9]), .R(begin_r)); FDRE system_reset_r2_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(system_reset_r), .Q(system_reset_r2), .R(1'b0)); FDRE system_reset_r_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(SR), .Q(system_reset_r), .R(1'b0)); LUT6 #( .INIT(64'hAAAA2222AAAA0020)) test_sh_r_i_1 (.I0(slip_r_i_2_n_0), .I1(sh_count_equals_max_i__14), .I2(p_1_in[2]), .I3(RXGEARBOXSLIP_OUT_i_3_n_0), .I4(test_sh_r_i_2_n_0), .I5(p_1_in[3]), .O(next_test_sh_c)); LUT3 #( .INIT(8'hF4)) test_sh_r_i_2 (.I0(rxheadervalid_i), .I1(test_sh_r), .I2(begin_r), .O(test_sh_r_i_2_n_0)); FDRE test_sh_r_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(next_test_sh_c), .Q(test_sh_r), .R(system_reset_r2)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_CHANNEL_BOND_GEN" *) module aurora_64b66b_0_aurora_64b66b_0_CHANNEL_BOND_GEN (gen_ch_bond_int_reg_0, data_v_r_reg_0, TXDATAVALID_IN, \free_count_r_reg[4]_0 , gen_ch_bond_int_reg_1); output gen_ch_bond_int_reg_0; input data_v_r_reg_0; input TXDATAVALID_IN; input [0:0]\free_count_r_reg[4]_0 ; input gen_ch_bond_int_reg_1; wire TXDATAVALID_IN; wire data_v_r; wire data_v_r_reg_0; wire \free_count_r[0]_i_1_n_0 ; wire \free_count_r[0]_i_3_n_0 ; wire [0:4]free_count_r_reg; wire [0:0]\free_count_r_reg[4]_0 ; wire gen_ch_bond_int_i_1_n_0; wire gen_ch_bond_int_reg_0; wire gen_ch_bond_int_reg_1; wire [4:0]p_0_in__3; FDRE data_v_r_reg (.C(data_v_r_reg_0), .CE(1'b1), .D(TXDATAVALID_IN), .Q(data_v_r), .R(1'b0)); LUT4 #( .INIT(16'hFF20)) \free_count_r[0]_i_1 (.I0(data_v_r), .I1(free_count_r_reg[0]), .I2(\free_count_r[0]_i_3_n_0 ), .I3(\free_count_r_reg[4]_0 ), .O(\free_count_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair117" *) LUT5 #( .INIT(32'h7FFF8000)) \free_count_r[0]_i_2 (.I0(free_count_r_reg[1]), .I1(free_count_r_reg[3]), .I2(free_count_r_reg[4]), .I3(free_count_r_reg[2]), .I4(free_count_r_reg[0]), .O(p_0_in__3[4])); (* SOFT_HLUTNM = "soft_lutpair117" *) LUT4 #( .INIT(16'h0400)) \free_count_r[0]_i_3 (.I0(free_count_r_reg[3]), .I1(free_count_r_reg[4]), .I2(free_count_r_reg[2]), .I3(free_count_r_reg[1]), .O(\free_count_r[0]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair118" *) LUT4 #( .INIT(16'h7F80)) \free_count_r[1]_i_1 (.I0(free_count_r_reg[2]), .I1(free_count_r_reg[4]), .I2(free_count_r_reg[3]), .I3(free_count_r_reg[1]), .O(p_0_in__3[3])); (* SOFT_HLUTNM = "soft_lutpair118" *) LUT3 #( .INIT(8'h78)) \free_count_r[2]_i_1 (.I0(free_count_r_reg[3]), .I1(free_count_r_reg[4]), .I2(free_count_r_reg[2]), .O(p_0_in__3[2])); (* SOFT_HLUTNM = "soft_lutpair119" *) LUT2 #( .INIT(4'h6)) \free_count_r[3]_i_1 (.I0(free_count_r_reg[4]), .I1(free_count_r_reg[3]), .O(p_0_in__3[1])); (* SOFT_HLUTNM = "soft_lutpair119" *) LUT1 #( .INIT(2'h1)) \free_count_r[4]_i_1 (.I0(free_count_r_reg[4]), .O(p_0_in__3[0])); FDRE #( .INIT(1'b0)) \free_count_r_reg[0] (.C(data_v_r_reg_0), .CE(data_v_r), .D(p_0_in__3[4]), .Q(free_count_r_reg[0]), .R(\free_count_r[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \free_count_r_reg[1] (.C(data_v_r_reg_0), .CE(data_v_r), .D(p_0_in__3[3]), .Q(free_count_r_reg[1]), .R(\free_count_r[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \free_count_r_reg[2] (.C(data_v_r_reg_0), .CE(data_v_r), .D(p_0_in__3[2]), .Q(free_count_r_reg[2]), .R(\free_count_r[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \free_count_r_reg[3] (.C(data_v_r_reg_0), .CE(data_v_r), .D(p_0_in__3[1]), .Q(free_count_r_reg[3]), .R(\free_count_r[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \free_count_r_reg[4] (.C(data_v_r_reg_0), .CE(data_v_r), .D(p_0_in__3[0]), .Q(free_count_r_reg[4]), .R(\free_count_r[0]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000020)) gen_ch_bond_int_i_1 (.I0(free_count_r_reg[1]), .I1(free_count_r_reg[2]), .I2(free_count_r_reg[4]), .I3(free_count_r_reg[3]), .I4(gen_ch_bond_int_reg_1), .I5(free_count_r_reg[0]), .O(gen_ch_bond_int_i_1_n_0)); FDRE gen_ch_bond_int_reg (.C(data_v_r_reg_0), .CE(1'b1), .D(gen_ch_bond_int_i_1_n_0), .Q(gen_ch_bond_int_reg_0), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_CHANNEL_ERR_DETECT" *) module aurora_64b66b_0_aurora_64b66b_0_CHANNEL_ERR_DETECT (hard_err, hard_err_i, CHANNEL_HARD_ERR_reg_0); output hard_err; input hard_err_i; input CHANNEL_HARD_ERR_reg_0; wire CHANNEL_HARD_ERR_reg_0; wire hard_err; wire hard_err_i; FDRE CHANNEL_HARD_ERR_reg (.C(CHANNEL_HARD_ERR_reg_0), .CE(1'b1), .D(hard_err_i), .Q(hard_err), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_CHANNEL_INIT_SM" *) module aurora_64b66b_0_aurora_64b66b_0_CHANNEL_INIT_SM (SR, wait_for_lane_up_r_reg_0, CHANNEL_UP_RX_IF_reg_0, CHANNEL_UP_TX_IF_reg_0, gen_cc_flop_0_i, E, CHANNEL_UP_RX_IF_reg_1, R0, gen_ch_bond_int_reg, CHANNEL_UP_RX_IF_reg_2, reset_lanes_c, CHANNEL_UP_RX_IF_reg_3, wait_for_lane_up_r_reg_1, remote_ready_i, RX_IDLE, CHANNEL_UP_RX_IF_reg_4, \TX_DATA_reg[63] , rst_pma_init_usrclk, gen_cc_i, Q, tx_pe_data_v_i, rx_pe_data_v_i, \TX_DATA_reg[63]_0 ); output [0:0]SR; output [0:0]wait_for_lane_up_r_reg_0; output CHANNEL_UP_RX_IF_reg_0; output CHANNEL_UP_TX_IF_reg_0; output [1:0]gen_cc_flop_0_i; output [0:0]E; output CHANNEL_UP_RX_IF_reg_1; output R0; output gen_ch_bond_int_reg; output CHANNEL_UP_RX_IF_reg_2; input reset_lanes_c; input CHANNEL_UP_RX_IF_reg_3; input wait_for_lane_up_r_reg_1; input remote_ready_i; input RX_IDLE; input [0:0]CHANNEL_UP_RX_IF_reg_4; input \TX_DATA_reg[63] ; input rst_pma_init_usrclk; input gen_cc_i; input [1:0]Q; input tx_pe_data_v_i; input rx_pe_data_v_i; input \TX_DATA_reg[63]_0 ; wire CHANNEL_UP_RX_IF_reg_0; wire CHANNEL_UP_RX_IF_reg_1; wire CHANNEL_UP_RX_IF_reg_2; wire CHANNEL_UP_RX_IF_reg_3; wire [0:0]CHANNEL_UP_RX_IF_reg_4; wire CHANNEL_UP_TX_IF_reg_0; wire [0:0]E; wire [1:0]Q; wire R0; wire RX_IDLE; wire [0:0]SR; wire \TX_DATA[55]_i_4_n_0 ; wire \TX_DATA[63]_i_2_n_0 ; wire \TX_DATA_reg[63] ; wire \TX_DATA_reg[63]_0 ; wire any_idles_r; (* RTL_KEEP = "true" *) wire [8:0]chan_bond_timeout_val; wire channel_up_c; wire [1:0]gen_cc_flop_0_i; wire gen_cc_i; wire gen_ch_bond_int_reg; wire idle_xmit_cntr; wire \idle_xmit_cntr[0]_i_2_n_0 ; wire \idle_xmit_cntr[0]_i_3_n_0 ; wire \idle_xmit_cntr[0]_i_4_n_0 ; wire \idle_xmit_cntr[1]_i_1_n_0 ; wire \idle_xmit_cntr[2]_i_1_n_0 ; wire \idle_xmit_cntr[3]_i_1_n_0 ; wire \idle_xmit_cntr[4]_i_1_n_0 ; wire \idle_xmit_cntr[5]_i_1_n_0 ; wire \idle_xmit_cntr_reg_n_0_[0] ; wire \idle_xmit_cntr_reg_n_0_[1] ; wire \idle_xmit_cntr_reg_n_0_[2] ; wire \idle_xmit_cntr_reg_n_0_[3] ; wire \idle_xmit_cntr_reg_n_0_[4] ; wire \idle_xmit_cntr_reg_n_0_[5] ; wire next_ready_c; wire next_wait_for_remote_c; wire ready_r; wire ready_r_i_2_n_0; wire remote_ready_i; wire remote_ready_r; wire reset_lanes_c; wire rst_pma_init_usrclk; wire rx_pe_data_v_i; wire tx_pe_data_v_i; wire [0:0]wait_for_lane_up_r_reg_0; wire wait_for_lane_up_r_reg_1; wire wait_for_remote_r; FDRE #( .INIT(1'b0)) CHANNEL_UP_RX_IF_reg (.C(CHANNEL_UP_RX_IF_reg_3), .CE(1'b1), .D(remote_ready_r), .Q(CHANNEL_UP_RX_IF_reg_0), .R(CHANNEL_UP_RX_IF_reg_4)); LUT5 #( .INIT(32'h00404040)) CHANNEL_UP_TX_IF_i_1 (.I0(wait_for_lane_up_r_reg_0), .I1(remote_ready_r), .I2(ready_r), .I3(wait_for_remote_r), .I4(\idle_xmit_cntr[0]_i_3_n_0 ), .O(channel_up_c)); FDRE #( .INIT(1'b0)) CHANNEL_UP_TX_IF_reg (.C(CHANNEL_UP_RX_IF_reg_3), .CE(1'b1), .D(channel_up_c), .Q(CHANNEL_UP_TX_IF_reg_0), .R(CHANNEL_UP_RX_IF_reg_4)); LUT1 #( .INIT(2'h1)) DO_CC_i_1 (.I0(CHANNEL_UP_RX_IF_reg_0), .O(CHANNEL_UP_RX_IF_reg_1)); (* SOFT_HLUTNM = "soft_lutpair120" *) LUT2 #( .INIT(4'h8)) \RX_D[0]_i_1 (.I0(CHANNEL_UP_RX_IF_reg_0), .I1(rx_pe_data_v_i), .O(E)); (* SOFT_HLUTNM = "soft_lutpair120" *) LUT3 #( .INIT(8'h08)) RX_SRC_RDY_N_inv_i_1 (.I0(CHANNEL_UP_RX_IF_reg_0), .I1(rx_pe_data_v_i), .I2(SR), .O(CHANNEL_UP_RX_IF_reg_2)); LUT6 #( .INIT(64'h000A000A000E000A)) \TX_DATA[54]_i_1 (.I0(\TX_DATA_reg[63] ), .I1(CHANNEL_UP_TX_IF_reg_0), .I2(rst_pma_init_usrclk), .I3(gen_cc_i), .I4(Q[0]), .I5(\TX_DATA[55]_i_4_n_0 ), .O(gen_cc_flop_0_i[0])); LUT6 #( .INIT(64'h0A0A0A0A0A0E0A0A)) \TX_DATA[55]_i_2 (.I0(gen_cc_i), .I1(CHANNEL_UP_TX_IF_reg_0), .I2(rst_pma_init_usrclk), .I3(\TX_DATA_reg[63] ), .I4(Q[1]), .I5(\TX_DATA[55]_i_4_n_0 ), .O(gen_cc_flop_0_i[1])); LUT2 #( .INIT(4'hB)) \TX_DATA[55]_i_4 (.I0(wait_for_lane_up_r_reg_0), .I1(tx_pe_data_v_i), .O(\TX_DATA[55]_i_4_n_0 )); LUT6 #( .INIT(64'hAAAAA8AAAAAAAAAA)) \TX_DATA[63]_i_1 (.I0(\TX_DATA_reg[63]_0 ), .I1(\TX_DATA_reg[63] ), .I2(gen_cc_i), .I3(tx_pe_data_v_i), .I4(wait_for_lane_up_r_reg_0), .I5(\TX_DATA[63]_i_2_n_0 ), .O(gen_ch_bond_int_reg)); (* SOFT_HLUTNM = "soft_lutpair121" *) LUT2 #( .INIT(4'h2)) \TX_DATA[63]_i_2 (.I0(CHANNEL_UP_TX_IF_reg_0), .I1(rst_pma_init_usrclk), .O(\TX_DATA[63]_i_2_n_0 )); FDRE #( .INIT(1'b0)) any_idles_r_reg (.C(CHANNEL_UP_RX_IF_reg_3), .CE(1'b1), .D(RX_IDLE), .Q(any_idles_r), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair121" *) LUT1 #( .INIT(2'h1)) gen_cc_flop_0_i_i_1 (.I0(CHANNEL_UP_TX_IF_reg_0), .O(R0)); LUT1 #( .INIT(2'h2)) i_0 (.I0(1'b1), .O(chan_bond_timeout_val[8])); LUT1 #( .INIT(2'h2)) i_1 (.I0(1'b1), .O(chan_bond_timeout_val[7])); LUT1 #( .INIT(2'h2)) i_2 (.I0(1'b1), .O(chan_bond_timeout_val[6])); LUT1 #( .INIT(2'h2)) i_3 (.I0(1'b1), .O(chan_bond_timeout_val[5])); LUT1 #( .INIT(2'h2)) i_4 (.I0(1'b1), .O(chan_bond_timeout_val[4])); LUT1 #( .INIT(2'h2)) i_5 (.I0(1'b0), .O(chan_bond_timeout_val[3])); LUT1 #( .INIT(2'h2)) i_6 (.I0(1'b1), .O(chan_bond_timeout_val[2])); LUT1 #( .INIT(2'h2)) i_7 (.I0(1'b0), .O(chan_bond_timeout_val[1])); LUT1 #( .INIT(2'h2)) i_8 (.I0(1'b0), .O(chan_bond_timeout_val[0])); LUT5 #( .INIT(32'hFFFFC8FF)) \idle_xmit_cntr[0]_i_1 (.I0(\idle_xmit_cntr_reg_n_0_[5] ), .I1(wait_for_remote_r), .I2(any_idles_r), .I3(\idle_xmit_cntr[0]_i_3_n_0 ), .I4(\idle_xmit_cntr[0]_i_4_n_0 ), .O(idle_xmit_cntr)); LUT6 #( .INIT(64'hFFFFFFFF80000000)) \idle_xmit_cntr[0]_i_2 (.I0(\idle_xmit_cntr_reg_n_0_[3] ), .I1(\idle_xmit_cntr_reg_n_0_[5] ), .I2(\idle_xmit_cntr_reg_n_0_[4] ), .I3(\idle_xmit_cntr_reg_n_0_[2] ), .I4(\idle_xmit_cntr_reg_n_0_[1] ), .I5(\idle_xmit_cntr_reg_n_0_[0] ), .O(\idle_xmit_cntr[0]_i_2_n_0 )); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) \idle_xmit_cntr[0]_i_3 (.I0(\idle_xmit_cntr_reg_n_0_[0] ), .I1(\idle_xmit_cntr_reg_n_0_[1] ), .I2(\idle_xmit_cntr_reg_n_0_[2] ), .I3(\idle_xmit_cntr_reg_n_0_[4] ), .I4(\idle_xmit_cntr_reg_n_0_[5] ), .I5(\idle_xmit_cntr_reg_n_0_[3] ), .O(\idle_xmit_cntr[0]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFF0000FFFE0000)) \idle_xmit_cntr[0]_i_4 (.I0(\idle_xmit_cntr_reg_n_0_[4] ), .I1(\idle_xmit_cntr_reg_n_0_[1] ), .I2(\idle_xmit_cntr_reg_n_0_[0] ), .I3(\idle_xmit_cntr_reg_n_0_[2] ), .I4(wait_for_remote_r), .I5(\idle_xmit_cntr_reg_n_0_[3] ), .O(\idle_xmit_cntr[0]_i_4_n_0 )); LUT6 #( .INIT(64'hEAAAAAAA6AAAAAAA)) \idle_xmit_cntr[1]_i_1 (.I0(\idle_xmit_cntr_reg_n_0_[1] ), .I1(\idle_xmit_cntr_reg_n_0_[3] ), .I2(\idle_xmit_cntr_reg_n_0_[5] ), .I3(\idle_xmit_cntr_reg_n_0_[4] ), .I4(\idle_xmit_cntr_reg_n_0_[2] ), .I5(\idle_xmit_cntr_reg_n_0_[0] ), .O(\idle_xmit_cntr[1]_i_1_n_0 )); LUT6 #( .INIT(64'hEAAA6AAA6AAA6AAA)) \idle_xmit_cntr[2]_i_1 (.I0(\idle_xmit_cntr_reg_n_0_[2] ), .I1(\idle_xmit_cntr_reg_n_0_[4] ), .I2(\idle_xmit_cntr_reg_n_0_[5] ), .I3(\idle_xmit_cntr_reg_n_0_[3] ), .I4(\idle_xmit_cntr_reg_n_0_[1] ), .I5(\idle_xmit_cntr_reg_n_0_[0] ), .O(\idle_xmit_cntr[2]_i_1_n_0 )); LUT6 #( .INIT(64'hEA6A6A6A6A6A6A6A)) \idle_xmit_cntr[3]_i_1 (.I0(\idle_xmit_cntr_reg_n_0_[3] ), .I1(\idle_xmit_cntr_reg_n_0_[5] ), .I2(\idle_xmit_cntr_reg_n_0_[4] ), .I3(\idle_xmit_cntr_reg_n_0_[2] ), .I4(\idle_xmit_cntr_reg_n_0_[0] ), .I5(\idle_xmit_cntr_reg_n_0_[1] ), .O(\idle_xmit_cntr[3]_i_1_n_0 )); LUT6 #( .INIT(64'hD5555555AAAAAAAA)) \idle_xmit_cntr[4]_i_1 (.I0(\idle_xmit_cntr_reg_n_0_[5] ), .I1(\idle_xmit_cntr_reg_n_0_[1] ), .I2(\idle_xmit_cntr_reg_n_0_[0] ), .I3(\idle_xmit_cntr_reg_n_0_[2] ), .I4(\idle_xmit_cntr_reg_n_0_[3] ), .I5(\idle_xmit_cntr_reg_n_0_[4] ), .O(\idle_xmit_cntr[4]_i_1_n_0 )); LUT6 #( .INIT(64'h80000000FFFFFFFF)) \idle_xmit_cntr[5]_i_1 (.I0(\idle_xmit_cntr_reg_n_0_[1] ), .I1(\idle_xmit_cntr_reg_n_0_[0] ), .I2(\idle_xmit_cntr_reg_n_0_[2] ), .I3(\idle_xmit_cntr_reg_n_0_[3] ), .I4(\idle_xmit_cntr_reg_n_0_[4] ), .I5(\idle_xmit_cntr_reg_n_0_[5] ), .O(\idle_xmit_cntr[5]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \idle_xmit_cntr_reg[0] (.C(CHANNEL_UP_RX_IF_reg_3), .CE(idle_xmit_cntr), .D(\idle_xmit_cntr[0]_i_2_n_0 ), .Q(\idle_xmit_cntr_reg_n_0_[0] ), .R(wait_for_lane_up_r_reg_0)); FDRE #( .INIT(1'b0)) \idle_xmit_cntr_reg[1] (.C(CHANNEL_UP_RX_IF_reg_3), .CE(idle_xmit_cntr), .D(\idle_xmit_cntr[1]_i_1_n_0 ), .Q(\idle_xmit_cntr_reg_n_0_[1] ), .R(wait_for_lane_up_r_reg_0)); FDRE #( .INIT(1'b0)) \idle_xmit_cntr_reg[2] (.C(CHANNEL_UP_RX_IF_reg_3), .CE(idle_xmit_cntr), .D(\idle_xmit_cntr[2]_i_1_n_0 ), .Q(\idle_xmit_cntr_reg_n_0_[2] ), .R(wait_for_lane_up_r_reg_0)); FDRE #( .INIT(1'b0)) \idle_xmit_cntr_reg[3] (.C(CHANNEL_UP_RX_IF_reg_3), .CE(idle_xmit_cntr), .D(\idle_xmit_cntr[3]_i_1_n_0 ), .Q(\idle_xmit_cntr_reg_n_0_[3] ), .R(wait_for_lane_up_r_reg_0)); FDRE #( .INIT(1'b0)) \idle_xmit_cntr_reg[4] (.C(CHANNEL_UP_RX_IF_reg_3), .CE(idle_xmit_cntr), .D(\idle_xmit_cntr[4]_i_1_n_0 ), .Q(\idle_xmit_cntr_reg_n_0_[4] ), .R(wait_for_lane_up_r_reg_0)); FDRE #( .INIT(1'b0)) \idle_xmit_cntr_reg[5] (.C(CHANNEL_UP_RX_IF_reg_3), .CE(idle_xmit_cntr), .D(\idle_xmit_cntr[5]_i_1_n_0 ), .Q(\idle_xmit_cntr_reg_n_0_[5] ), .R(wait_for_lane_up_r_reg_0)); LUT6 #( .INIT(64'hAAEA0000AAAA0000)) ready_r_i_1__0 (.I0(ready_r), .I1(\idle_xmit_cntr_reg_n_0_[0] ), .I2(\idle_xmit_cntr_reg_n_0_[1] ), .I3(ready_r_i_2_n_0), .I4(remote_ready_r), .I5(wait_for_remote_r), .O(next_ready_c)); LUT4 #( .INIT(16'h7FFF)) ready_r_i_2 (.I0(\idle_xmit_cntr_reg_n_0_[3] ), .I1(\idle_xmit_cntr_reg_n_0_[5] ), .I2(\idle_xmit_cntr_reg_n_0_[4] ), .I3(\idle_xmit_cntr_reg_n_0_[2] ), .O(ready_r_i_2_n_0)); FDRE #( .INIT(1'b0)) ready_r_reg (.C(CHANNEL_UP_RX_IF_reg_3), .CE(1'b1), .D(next_ready_c), .Q(ready_r), .R(wait_for_lane_up_r_reg_1)); FDRE #( .INIT(1'b0)) remote_ready_r_reg (.C(CHANNEL_UP_RX_IF_reg_3), .CE(1'b1), .D(remote_ready_i), .Q(remote_ready_r), .R(1'b0)); (* BOX_TYPE = "PRIMITIVE" *) (* XILINX_LEGACY_PRIM = "FD" *) FDRE #( .INIT(1'b1)) reset_lanes_flop_0_i (.C(CHANNEL_UP_RX_IF_reg_3), .CE(1'b1), .D(reset_lanes_c), .Q(SR), .R(1'b0)); FDRE #( .INIT(1'b0)) wait_for_lane_up_r_reg (.C(CHANNEL_UP_RX_IF_reg_3), .CE(1'b1), .D(wait_for_lane_up_r_reg_1), .Q(wait_for_lane_up_r_reg_0), .R(1'b0)); LUT5 #( .INIT(32'hFFFFF544)) wait_for_remote_r_i_1 (.I0(remote_ready_r), .I1(ready_r), .I2(\idle_xmit_cntr[0]_i_3_n_0 ), .I3(wait_for_remote_r), .I4(wait_for_lane_up_r_reg_0), .O(next_wait_for_remote_c)); FDRE #( .INIT(1'b0)) wait_for_remote_r_reg (.C(CHANNEL_UP_RX_IF_reg_3), .CE(1'b1), .D(next_wait_for_remote_c), .Q(wait_for_remote_r), .R(wait_for_lane_up_r_reg_1)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_CLOCK_CORRECTION_CHANNEL_BONDING" *) module aurora_64b66b_0_aurora_64b66b_0_CLOCK_CORRECTION_CHANNEL_BONDING (dout, do_rd_en_i, rx_lossofsync_i, CC_detect_dlyd1, CB_detect_dlyd0p5, bit_err_chan_bond_i, valid_btf_detect_dlyd1, ILLEGAL_BTF_reg, rxdatavalid_i, wr_err_rd_clk_sync_reg_0, hard_err_usr0, hold_reg_reg_0, rxfsm_reset_i, \LINK_RESET_reg[0]_0 , LINK_RESET_OUT0, final_gater_for_fifo_din_i, START_CB_WRITES_OUT, ANY_VLD_BTF_FLAG, srst, gtwiz_userclk_rx_usrclk_out, s_level_out_d5_reg, out, in0, UNSCRAMBLED_DATA_OUT, Q, rxdatavalid_to_fifo_i, cbcc_fifo_reset_rd_clk, init_clk, cbcc_reset_cbstg2_rd_clk, CC_RXLOSSOFSYNC_OUT_reg_0, SR, valid_btf_detect_c, CB_detect0, D, \count_for_reset_r_reg[23]_0 , illegal_btf_i, enable_err_detect_i, HARD_ERR_reg, txbufstatus_out, hard_err_usr_reg, channel_up_tx_if, allow_block_sync_propagation_reg, LINK_RESET_OUT_reg, hard_err_rst_int, FINAL_GATER_FOR_FIFO_DIN_reg_0, \wr_monitor_flag_reg[4]_0 , \valid_btf_detect_extend_r_reg[4]_0 , START_CB_WRITES_OUT_reg_0); output [65:0]dout; output do_rd_en_i; output rx_lossofsync_i; output CC_detect_dlyd1; output CB_detect_dlyd0p5; output bit_err_chan_bond_i; output valid_btf_detect_dlyd1; output ILLEGAL_BTF_reg; output rxdatavalid_i; output wr_err_rd_clk_sync_reg_0; output hard_err_usr0; output hold_reg_reg_0; output rxfsm_reset_i; output [0:0]\LINK_RESET_reg[0]_0 ; output LINK_RESET_OUT0; output final_gater_for_fifo_din_i; output START_CB_WRITES_OUT; output ANY_VLD_BTF_FLAG; input srst; input gtwiz_userclk_rx_usrclk_out; input s_level_out_d5_reg; input out; input in0; input [31:0]UNSCRAMBLED_DATA_OUT; input [1:0]Q; input rxdatavalid_to_fifo_i; input cbcc_fifo_reset_rd_clk; input init_clk; input cbcc_reset_cbstg2_rd_clk; input CC_RXLOSSOFSYNC_OUT_reg_0; input [0:0]SR; input valid_btf_detect_c; input CB_detect0; input [1:0]D; input \count_for_reset_r_reg[23]_0 ; input illegal_btf_i; input enable_err_detect_i; input HARD_ERR_reg; input [0:0]txbufstatus_out; input hard_err_usr_reg; input channel_up_tx_if; input allow_block_sync_propagation_reg; input LINK_RESET_OUT_reg; input hard_err_rst_int; input FINAL_GATER_FOR_FIFO_DIN_reg_0; input [0:0]\wr_monitor_flag_reg[4]_0 ; input [0:0]\valid_btf_detect_extend_r_reg[4]_0 ; input START_CB_WRITES_OUT_reg_0; wire ANY_VLD_BTF_FLAG; wire ANY_VLD_BTF_FLAG_i_1_n_0; wire CB_detect0; wire CB_detect_dlyd0p5; wire CB_detect_dlyd1; wire CB_detect_dlyd10; wire CB_detect_dlyd1p0; wire CC_RXLOSSOFSYNC_OUT_reg_0; wire CC_detect_dlyd1; wire CC_detect_pulse_r; wire [1:0]D; wire FINAL_GATER_FOR_FIFO_DIN0; wire FINAL_GATER_FOR_FIFO_DIN_i_1_n_0; wire FINAL_GATER_FOR_FIFO_DIN_reg_0; wire FIRST_CB_BITERR_CB_RESET_OUT1__15; wire FIRST_CB_BITERR_CB_RESET_OUT_i_1_n_0; wire FIRST_CB_BITERR_CB_RESET_OUT_i_3_n_0; wire FIRST_CB_BITERR_CB_RESET_OUT_i_4_n_0; wire FIRST_CB_BITERR_CB_RESET_OUT_i_5_n_0; wire FIRST_CB_BITERR_CB_RESET_OUT_i_6_n_0; wire FIRST_CB_BITERR_CB_RESET_OUT_i_7_n_0; wire HARD_ERR_reg; wire ILLEGAL_BTF_reg; wire \LINK_RESET[0]_i_2_n_0 ; wire \LINK_RESET[0]_i_3_n_0 ; wire \LINK_RESET[0]_i_4_n_0 ; wire \LINK_RESET[0]_i_5_n_0 ; wire \LINK_RESET[0]_i_6_n_0 ; wire LINK_RESET_OUT0; wire LINK_RESET_OUT_reg; wire [0:0]\LINK_RESET_reg[0]_0 ; wire [1:0]Q; wire SOFT_ERR_i_2_n_0; wire [0:0]SR; wire START_CB_WRITES_OUT; wire START_CB_WRITES_OUT_i_1_n_0; wire START_CB_WRITES_OUT_reg_0; wire [31:0]UNSCRAMBLED_DATA_OUT; wire allow_block_sync_propagation_reg; wire any_vld_btf_fifo_din_detect; wire any_vld_btf_fifo_din_detect_dlyd; wire any_vld_btf_fifo_din_detect_dlyd_i_1_n_0; wire any_vld_btf_fifo_din_detect_dlyd_i_3_n_0; wire any_vld_btf_fifo_din_detect_dlyd_i_4_n_0; wire any_vld_btf_fifo_din_detect_dlyd_i_5_n_0; wire any_vld_btf_fifo_din_detect_dlyd_i_6_n_0; wire any_vld_btf_fifo_din_detect_dlyd_i_7_n_0; wire bit80_prsnt; wire bit_err_chan_bond_i; wire buffer_too_empty_c; wire cb_fifo_din_detect_q; wire cbcc_fifo_reset_rd_clk; wire cbcc_reset_cbstg2_rd_clk; wire channel_up_tx_if; wire \count_for_reset_r[0]_i_3_n_0 ; wire [23:0]count_for_reset_r_reg; wire \count_for_reset_r_reg[0]_i_2_n_0 ; wire \count_for_reset_r_reg[0]_i_2_n_1 ; wire \count_for_reset_r_reg[0]_i_2_n_10 ; wire \count_for_reset_r_reg[0]_i_2_n_11 ; wire \count_for_reset_r_reg[0]_i_2_n_12 ; wire \count_for_reset_r_reg[0]_i_2_n_13 ; wire \count_for_reset_r_reg[0]_i_2_n_14 ; wire \count_for_reset_r_reg[0]_i_2_n_15 ; wire \count_for_reset_r_reg[0]_i_2_n_2 ; wire \count_for_reset_r_reg[0]_i_2_n_3 ; wire \count_for_reset_r_reg[0]_i_2_n_4 ; wire \count_for_reset_r_reg[0]_i_2_n_5 ; wire \count_for_reset_r_reg[0]_i_2_n_6 ; wire \count_for_reset_r_reg[0]_i_2_n_7 ; wire \count_for_reset_r_reg[0]_i_2_n_8 ; wire \count_for_reset_r_reg[0]_i_2_n_9 ; wire \count_for_reset_r_reg[16]_i_1_n_1 ; wire \count_for_reset_r_reg[16]_i_1_n_10 ; wire \count_for_reset_r_reg[16]_i_1_n_11 ; wire \count_for_reset_r_reg[16]_i_1_n_12 ; wire \count_for_reset_r_reg[16]_i_1_n_13 ; wire \count_for_reset_r_reg[16]_i_1_n_14 ; wire \count_for_reset_r_reg[16]_i_1_n_15 ; wire \count_for_reset_r_reg[16]_i_1_n_2 ; wire \count_for_reset_r_reg[16]_i_1_n_3 ; wire \count_for_reset_r_reg[16]_i_1_n_4 ; wire \count_for_reset_r_reg[16]_i_1_n_5 ; wire \count_for_reset_r_reg[16]_i_1_n_6 ; wire \count_for_reset_r_reg[16]_i_1_n_7 ; wire \count_for_reset_r_reg[16]_i_1_n_8 ; wire \count_for_reset_r_reg[16]_i_1_n_9 ; wire \count_for_reset_r_reg[23]_0 ; wire \count_for_reset_r_reg[8]_i_1_n_0 ; wire \count_for_reset_r_reg[8]_i_1_n_1 ; wire \count_for_reset_r_reg[8]_i_1_n_10 ; wire \count_for_reset_r_reg[8]_i_1_n_11 ; wire \count_for_reset_r_reg[8]_i_1_n_12 ; wire \count_for_reset_r_reg[8]_i_1_n_13 ; wire \count_for_reset_r_reg[8]_i_1_n_14 ; wire \count_for_reset_r_reg[8]_i_1_n_15 ; wire \count_for_reset_r_reg[8]_i_1_n_2 ; wire \count_for_reset_r_reg[8]_i_1_n_3 ; wire \count_for_reset_r_reg[8]_i_1_n_4 ; wire \count_for_reset_r_reg[8]_i_1_n_5 ; wire \count_for_reset_r_reg[8]_i_1_n_6 ; wire \count_for_reset_r_reg[8]_i_1_n_7 ; wire \count_for_reset_r_reg[8]_i_1_n_8 ; wire \count_for_reset_r_reg[8]_i_1_n_9 ; wire do_rd_en; wire do_rd_en_i; wire do_wr_en; wire do_wr_en_i_1_n_0; wire [65:0]dout; wire [79:0]en32_fifo_din_i; wire enable_err_detect_i; wire final_gater_for_fifo_din_i; wire first_cb_to_write_to_fifo; wire first_cb_to_write_to_fifo_dlyd; wire first_cb_to_write_to_fifo_dlyd_i_2_n_0; wire first_cb_to_write_to_fifo_dlyd_i_3_n_0; wire first_cb_to_write_to_fifo_dlyd_i_4_n_0; wire first_cb_to_write_to_fifo_dlyd_i_5_n_0; wire gtwiz_userclk_rx_usrclk_out; wire hard_err_rst_int; wire hard_err_usr0; wire hard_err_usr_reg; wire hold_reg; wire hold_reg_i_1_n_0; wire hold_reg_reg_0; wire illegal_btf_i; wire in0; wire init_clk; wire link_reset_0; wire link_reset_0_c; wire master_do_rd_en_q; wire mod_do_wr_en; wire new_do_wr_en; wire new_do_wr_en_i_1_n_0; wire new_underflow_flag_c; wire new_underflow_flag_c0; wire out; wire overflow_flag_c; wire p_0_in0_in; wire p_0_in4_in; wire [5:0]p_0_in__8; wire [4:0]p_0_in__9; wire p_1_in; wire [1:0]p_2_in; wire \raw_data_r_r_reg_n_0_[0] ; wire \raw_data_r_r_reg_n_0_[10] ; wire \raw_data_r_r_reg_n_0_[11] ; wire \raw_data_r_r_reg_n_0_[12] ; wire \raw_data_r_r_reg_n_0_[13] ; wire \raw_data_r_r_reg_n_0_[14] ; wire \raw_data_r_r_reg_n_0_[15] ; wire \raw_data_r_r_reg_n_0_[16] ; wire \raw_data_r_r_reg_n_0_[17] ; wire \raw_data_r_r_reg_n_0_[18] ; wire \raw_data_r_r_reg_n_0_[19] ; wire \raw_data_r_r_reg_n_0_[1] ; wire \raw_data_r_r_reg_n_0_[20] ; wire \raw_data_r_r_reg_n_0_[21] ; wire \raw_data_r_r_reg_n_0_[22] ; wire \raw_data_r_r_reg_n_0_[23] ; wire \raw_data_r_r_reg_n_0_[24] ; wire \raw_data_r_r_reg_n_0_[25] ; wire \raw_data_r_r_reg_n_0_[26] ; wire \raw_data_r_r_reg_n_0_[27] ; wire \raw_data_r_r_reg_n_0_[28] ; wire \raw_data_r_r_reg_n_0_[29] ; wire \raw_data_r_r_reg_n_0_[2] ; wire \raw_data_r_r_reg_n_0_[30] ; wire \raw_data_r_r_reg_n_0_[31] ; wire \raw_data_r_r_reg_n_0_[32] ; wire \raw_data_r_r_reg_n_0_[33] ; wire \raw_data_r_r_reg_n_0_[3] ; wire \raw_data_r_r_reg_n_0_[4] ; wire \raw_data_r_r_reg_n_0_[5] ; wire \raw_data_r_r_reg_n_0_[6] ; wire \raw_data_r_r_reg_n_0_[7] ; wire \raw_data_r_r_reg_n_0_[8] ; wire \raw_data_r_r_reg_n_0_[9] ; wire \raw_data_r_reg_n_0_[0] ; wire \raw_data_r_reg_n_0_[10] ; wire \raw_data_r_reg_n_0_[11] ; wire \raw_data_r_reg_n_0_[12] ; wire \raw_data_r_reg_n_0_[13] ; wire \raw_data_r_reg_n_0_[14] ; wire \raw_data_r_reg_n_0_[15] ; wire \raw_data_r_reg_n_0_[16] ; wire \raw_data_r_reg_n_0_[17] ; wire \raw_data_r_reg_n_0_[18] ; wire \raw_data_r_reg_n_0_[19] ; wire \raw_data_r_reg_n_0_[1] ; wire \raw_data_r_reg_n_0_[20] ; wire \raw_data_r_reg_n_0_[21] ; wire \raw_data_r_reg_n_0_[22] ; wire \raw_data_r_reg_n_0_[23] ; wire \raw_data_r_reg_n_0_[24] ; wire \raw_data_r_reg_n_0_[25] ; wire \raw_data_r_reg_n_0_[26] ; wire \raw_data_r_reg_n_0_[27] ; wire \raw_data_r_reg_n_0_[28] ; wire \raw_data_r_reg_n_0_[29] ; wire \raw_data_r_reg_n_0_[2] ; wire \raw_data_r_reg_n_0_[30] ; wire \raw_data_r_reg_n_0_[31] ; wire \raw_data_r_reg_n_0_[32] ; wire \raw_data_r_reg_n_0_[33] ; wire \raw_data_r_reg_n_0_[3] ; wire \raw_data_r_reg_n_0_[4] ; wire \raw_data_r_reg_n_0_[5] ; wire \raw_data_r_reg_n_0_[6] ; wire \raw_data_r_reg_n_0_[7] ; wire \raw_data_r_reg_n_0_[8] ; wire \raw_data_r_reg_n_0_[9] ; wire [34:0]raw_data_srl_out; wire rd_err_c; wire rd_err_pre; wire rx_lossofsync_i; wire [1:0]rxbuferr_out_i; wire rxdatavalid_i; wire rxdatavalid_lookahead_i; wire rxdatavalid_to_fifo_i; wire rxfsm_reset_i; wire s_level_out_d5_reg; wire srst; wire [0:0]txbufstatus_out; wire u_cdc_rxlossofsync_in_n_0; wire u_rst_sync_btf_sync_n_0; wire underflow_flag_c; wire underflow_flag_r1; wire underflow_flag_r10; wire underflow_flag_r2; wire underflow_flag_r3; wire valid_btf_detect; wire valid_btf_detect_c; wire valid_btf_detect_dlyd1; wire [4:0]valid_btf_detect_extend_r; wire valid_btf_detect_extend_r2; wire valid_btf_detect_extend_r20_n_0; wire [0:0]\valid_btf_detect_extend_r_reg[4]_0 ; wire [2:0]wait_for_rd_en; wire \wait_for_rd_en[0]_i_1_n_0 ; wire \wait_for_rd_en[1]_i_1_n_0 ; wire \wait_for_rd_en[2]_i_1_n_0 ; wire \wait_for_rd_en[2]_i_2_n_0 ; wire \wait_for_wr_en[5]_i_1_n_0 ; wire [5:0]wait_for_wr_en_reg; wire \wait_for_wr_en_wr3_reg[0]_srl3_n_0 ; wire \wait_for_wr_en_wr3_reg[1]_srl3_n_0 ; wire \wait_for_wr_en_wr3_reg[2]_srl3_n_0 ; wire \wait_for_wr_en_wr3_reg[3]_srl3_n_0 ; wire \wait_for_wr_en_wr3_reg[4]_srl3_n_0 ; wire \wait_for_wr_en_wr3_reg[5]_srl3_n_0 ; wire [5:0]wait_for_wr_en_wr4; wire [39:0]wdth_conv_1stage; wire [39:32]wdth_conv_2stage; wire \wdth_conv_count[1]_i_1_n_0 ; wire \wdth_conv_count_reg_n_0_[0] ; wire wr_err_c; wire wr_err_rd_clk_pre; wire wr_err_rd_clk_sync_reg_0; wire wr_monitor_flag; wire [4:0]wr_monitor_flag_reg; wire [0:0]\wr_monitor_flag_reg[4]_0 ; wire NLW_SRLC32E_inst_4_Q31_UNCONNECTED; wire [7:7]\NLW_count_for_reset_r_reg[16]_i_1_CO_UNCONNECTED ; wire \NLW_master_fifo.data_fifo_prog_full_UNCONNECTED ; wire \NLW_master_fifo.data_fifo_rd_rst_busy_UNCONNECTED ; wire \NLW_master_fifo.data_fifo_wr_rst_busy_UNCONNECTED ; wire [71:66]\NLW_master_fifo.data_fifo_dout_UNCONNECTED ; wire \NLW_srlc32e[0].SRLC32E_inst_1_Q31_UNCONNECTED ; wire \NLW_srlc32e[10].SRLC32E_inst_1_Q31_UNCONNECTED ; wire \NLW_srlc32e[11].SRLC32E_inst_1_Q31_UNCONNECTED ; wire \NLW_srlc32e[12].SRLC32E_inst_1_Q31_UNCONNECTED ; wire \NLW_srlc32e[13].SRLC32E_inst_1_Q31_UNCONNECTED ; wire \NLW_srlc32e[14].SRLC32E_inst_1_Q31_UNCONNECTED ; wire \NLW_srlc32e[15].SRLC32E_inst_1_Q31_UNCONNECTED ; wire \NLW_srlc32e[16].SRLC32E_inst_1_Q31_UNCONNECTED ; wire \NLW_srlc32e[17].SRLC32E_inst_1_Q31_UNCONNECTED ; wire \NLW_srlc32e[18].SRLC32E_inst_1_Q31_UNCONNECTED ; wire \NLW_srlc32e[19].SRLC32E_inst_1_Q31_UNCONNECTED ; wire \NLW_srlc32e[1].SRLC32E_inst_1_Q31_UNCONNECTED ; wire \NLW_srlc32e[20].SRLC32E_inst_1_Q31_UNCONNECTED ; wire \NLW_srlc32e[21].SRLC32E_inst_1_Q31_UNCONNECTED ; wire \NLW_srlc32e[22].SRLC32E_inst_1_Q31_UNCONNECTED ; wire \NLW_srlc32e[23].SRLC32E_inst_1_Q31_UNCONNECTED ; wire \NLW_srlc32e[24].SRLC32E_inst_1_Q31_UNCONNECTED ; wire \NLW_srlc32e[25].SRLC32E_inst_1_Q31_UNCONNECTED ; wire \NLW_srlc32e[26].SRLC32E_inst_1_Q31_UNCONNECTED ; wire \NLW_srlc32e[27].SRLC32E_inst_1_Q31_UNCONNECTED ; wire \NLW_srlc32e[28].SRLC32E_inst_1_Q31_UNCONNECTED ; wire \NLW_srlc32e[29].SRLC32E_inst_1_Q31_UNCONNECTED ; wire \NLW_srlc32e[2].SRLC32E_inst_1_Q31_UNCONNECTED ; wire \NLW_srlc32e[30].SRLC32E_inst_1_Q31_UNCONNECTED ; wire \NLW_srlc32e[31].SRLC32E_inst_1_Q31_UNCONNECTED ; wire \NLW_srlc32e[32].SRLC32E_inst_1_Q31_UNCONNECTED ; wire \NLW_srlc32e[33].SRLC32E_inst_1_Q31_UNCONNECTED ; wire \NLW_srlc32e[34].SRLC32E_inst_1_Q31_UNCONNECTED ; wire \NLW_srlc32e[3].SRLC32E_inst_1_Q31_UNCONNECTED ; wire \NLW_srlc32e[4].SRLC32E_inst_1_Q31_UNCONNECTED ; wire \NLW_srlc32e[5].SRLC32E_inst_1_Q31_UNCONNECTED ; wire \NLW_srlc32e[6].SRLC32E_inst_1_Q31_UNCONNECTED ; wire \NLW_srlc32e[7].SRLC32E_inst_1_Q31_UNCONNECTED ; wire \NLW_srlc32e[8].SRLC32E_inst_1_Q31_UNCONNECTED ; wire \NLW_srlc32e[9].SRLC32E_inst_1_Q31_UNCONNECTED ; LUT3 #( .INIT(8'hF8)) ANY_VLD_BTF_FLAG_i_1 (.I0(p_0_in0_in), .I1(any_vld_btf_fifo_din_detect_dlyd), .I2(ANY_VLD_BTF_FLAG), .O(ANY_VLD_BTF_FLAG_i_1_n_0)); FDRE #( .INIT(1'b0)) ANY_VLD_BTF_FLAG_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(ANY_VLD_BTF_FLAG_i_1_n_0), .Q(ANY_VLD_BTF_FLAG), .R(any_vld_btf_fifo_din_detect_dlyd_i_1_n_0)); FDRE CB_detect_dlyd0p5_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(CB_detect0), .Q(CB_detect_dlyd0p5), .R(SR)); LUT2 #( .INIT(4'hE)) CB_detect_dlyd1_i_1 (.I0(CB_detect_dlyd1p0), .I1(CB_detect_dlyd0p5), .O(CB_detect_dlyd10)); FDRE CB_detect_dlyd1_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(CB_detect_dlyd10), .Q(CB_detect_dlyd1), .R(SR)); FDRE CB_detect_dlyd1p0_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(CB_detect_dlyd0p5), .Q(CB_detect_dlyd1p0), .R(SR)); FDSE CC_RXLOSSOFSYNC_OUT_reg (.C(s_level_out_d5_reg), .CE(1'b1), .D(u_cdc_rxlossofsync_in_n_0), .Q(rx_lossofsync_i), .S(CC_RXLOSSOFSYNC_OUT_reg_0)); FDRE CC_detect_dlyd1_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(valid_btf_detect_c), .Q(CC_detect_dlyd1), .R(SR)); FDRE CC_detect_pulse_r_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(D[1]), .Q(CC_detect_pulse_r), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair46" *) LUT4 #( .INIT(16'hFF80)) FINAL_GATER_FOR_FIFO_DIN_i_1 (.I0(FINAL_GATER_FOR_FIFO_DIN_reg_0), .I1(cb_fifo_din_detect_q), .I2(p_0_in0_in), .I3(final_gater_for_fifo_din_i), .O(FINAL_GATER_FOR_FIFO_DIN_i_1_n_0)); FDRE #( .INIT(1'b0)) FINAL_GATER_FOR_FIFO_DIN_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(FINAL_GATER_FOR_FIFO_DIN_i_1_n_0), .Q(final_gater_for_fifo_din_i), .R(SR)); LUT5 #( .INIT(32'h0000E22E)) FIRST_CB_BITERR_CB_RESET_OUT_i_1 (.I0(bit_err_chan_bond_i), .I1(new_do_wr_en), .I2(FIRST_CB_BITERR_CB_RESET_OUT1__15), .I3(FIRST_CB_BITERR_CB_RESET_OUT_i_3_n_0), .I4(FIRST_CB_BITERR_CB_RESET_OUT_i_4_n_0), .O(FIRST_CB_BITERR_CB_RESET_OUT_i_1_n_0)); LUT6 #( .INIT(64'h0100000000000000)) FIRST_CB_BITERR_CB_RESET_OUT_i_2 (.I0(en32_fifo_din_i[58]), .I1(en32_fifo_din_i[57]), .I2(en32_fifo_din_i[56]), .I3(FIRST_CB_BITERR_CB_RESET_OUT_i_5_n_0), .I4(FIRST_CB_BITERR_CB_RESET_OUT_i_6_n_0), .I5(FIRST_CB_BITERR_CB_RESET_OUT_i_7_n_0), .O(FIRST_CB_BITERR_CB_RESET_OUT1__15)); (* SOFT_HLUTNM = "soft_lutpair41" *) LUT5 #( .INIT(32'hFFFDFFFF)) FIRST_CB_BITERR_CB_RESET_OUT_i_3 (.I0(wr_monitor_flag_reg[3]), .I1(wr_monitor_flag_reg[4]), .I2(wr_monitor_flag_reg[0]), .I3(wr_monitor_flag_reg[2]), .I4(wr_monitor_flag_reg[1]), .O(FIRST_CB_BITERR_CB_RESET_OUT_i_3_n_0)); LUT6 #( .INIT(64'hFEFEFEFAFEFAFEFB)) FIRST_CB_BITERR_CB_RESET_OUT_i_4 (.I0(\wr_monitor_flag_reg[4]_0 ), .I1(wr_monitor_flag_reg[3]), .I2(wr_monitor_flag_reg[4]), .I3(wr_monitor_flag_reg[2]), .I4(wr_monitor_flag_reg[1]), .I5(wr_monitor_flag_reg[0]), .O(FIRST_CB_BITERR_CB_RESET_OUT_i_4_n_0)); LUT4 #( .INIT(16'h0004)) FIRST_CB_BITERR_CB_RESET_OUT_i_5 (.I0(en32_fifo_din_i[61]), .I1(en32_fifo_din_i[62]), .I2(en32_fifo_din_i[60]), .I3(en32_fifo_din_i[59]), .O(FIRST_CB_BITERR_CB_RESET_OUT_i_5_n_0)); LUT4 #( .INIT(16'h0001)) FIRST_CB_BITERR_CB_RESET_OUT_i_6 (.I0(en32_fifo_din_i[66]), .I1(en32_fifo_din_i[65]), .I2(en32_fifo_din_i[64]), .I3(en32_fifo_din_i[63]), .O(FIRST_CB_BITERR_CB_RESET_OUT_i_6_n_0)); LUT6 #( .INIT(64'h0000800000000000)) FIRST_CB_BITERR_CB_RESET_OUT_i_7 (.I0(en32_fifo_din_i[67]), .I1(en32_fifo_din_i[68]), .I2(en32_fifo_din_i[69]), .I3(en32_fifo_din_i[70]), .I4(en32_fifo_din_i[71]), .I5(en32_fifo_din_i[76]), .O(FIRST_CB_BITERR_CB_RESET_OUT_i_7_n_0)); FDRE #( .INIT(1'b0)) FIRST_CB_BITERR_CB_RESET_OUT_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(FIRST_CB_BITERR_CB_RESET_OUT_i_1_n_0), .Q(bit_err_chan_bond_i), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair47" *) LUT3 #( .INIT(8'hFE)) \FSM_onehot_cdr_reset_fsm_r[2]_i_1 (.I0(link_reset_0_c), .I1(allow_block_sync_propagation_reg), .I2(hard_err_rst_int), .O(\LINK_RESET_reg[0]_0 )); LUT5 #( .INIT(32'hFFFE0000)) HARD_ERR_i_1 (.I0(rxbuferr_out_i[1]), .I1(rxbuferr_out_i[0]), .I2(HARD_ERR_reg), .I3(txbufstatus_out), .I4(enable_err_detect_i), .O(wr_err_rd_clk_sync_reg_0)); LUT6 #( .INIT(64'hABA8000000000000)) \LINK_RESET[0]_i_1 (.I0(\LINK_RESET[0]_i_2_n_0 ), .I1(count_for_reset_r_reg[1]), .I2(count_for_reset_r_reg[2]), .I3(\LINK_RESET[0]_i_3_n_0 ), .I4(\LINK_RESET[0]_i_4_n_0 ), .I5(\LINK_RESET[0]_i_5_n_0 ), .O(link_reset_0)); LUT5 #( .INIT(32'h7FFFFFFF)) \LINK_RESET[0]_i_2 (.I0(count_for_reset_r_reg[3]), .I1(count_for_reset_r_reg[6]), .I2(count_for_reset_r_reg[7]), .I3(count_for_reset_r_reg[5]), .I4(count_for_reset_r_reg[4]), .O(\LINK_RESET[0]_i_2_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \LINK_RESET[0]_i_3 (.I0(count_for_reset_r_reg[6]), .I1(count_for_reset_r_reg[7]), .I2(count_for_reset_r_reg[4]), .I3(count_for_reset_r_reg[5]), .I4(count_for_reset_r_reg[3]), .I5(count_for_reset_r_reg[0]), .O(\LINK_RESET[0]_i_3_n_0 )); LUT5 #( .INIT(32'h80000000)) \LINK_RESET[0]_i_4 (.I0(count_for_reset_r_reg[10]), .I1(count_for_reset_r_reg[11]), .I2(count_for_reset_r_reg[8]), .I3(count_for_reset_r_reg[9]), .I4(\LINK_RESET[0]_i_6_n_0 ), .O(\LINK_RESET[0]_i_4_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \LINK_RESET[0]_i_5 (.I0(count_for_reset_r_reg[20]), .I1(count_for_reset_r_reg[21]), .I2(count_for_reset_r_reg[18]), .I3(count_for_reset_r_reg[19]), .I4(count_for_reset_r_reg[23]), .I5(count_for_reset_r_reg[22]), .O(\LINK_RESET[0]_i_5_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \LINK_RESET[0]_i_6 (.I0(count_for_reset_r_reg[14]), .I1(count_for_reset_r_reg[15]), .I2(count_for_reset_r_reg[12]), .I3(count_for_reset_r_reg[13]), .I4(count_for_reset_r_reg[17]), .I5(count_for_reset_r_reg[16]), .O(\LINK_RESET[0]_i_6_n_0 )); LUT2 #( .INIT(4'hE)) LINK_RESET_OUT_i_1 (.I0(LINK_RESET_OUT_reg), .I1(link_reset_0_c), .O(LINK_RESET_OUT0)); FDRE \LINK_RESET_reg[0] (.C(init_clk), .CE(1'b1), .D(link_reset_0), .Q(link_reset_0_c), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair49" *) LUT2 #( .INIT(4'h8)) RXDATAVALID_IN_REG_i_1 (.I0(master_do_rd_en_q), .I1(p_0_in4_in), .O(rxdatavalid_i)); (* SOFT_HLUTNM = "soft_lutpair43" *) LUT1 #( .INIT(2'h1)) \RX_DATA_REG[63]_i_1 (.I0(hold_reg), .O(hold_reg_reg_0)); (* SOFT_HLUTNM = "soft_lutpair43" *) LUT5 #( .INIT(32'hFBBF0000)) SOFT_ERR_i_1 (.I0(illegal_btf_i), .I1(hold_reg), .I2(dout[65]), .I3(dout[64]), .I4(SOFT_ERR_i_2_n_0), .O(ILLEGAL_BTF_reg)); (* SOFT_HLUTNM = "soft_lutpair49" *) LUT3 #( .INIT(8'h80)) SOFT_ERR_i_2 (.I0(p_0_in4_in), .I1(master_do_rd_en_q), .I2(enable_err_detect_i), .O(SOFT_ERR_i_2_n_0)); (* BOX_TYPE = "PRIMITIVE" *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/SRLC32E_inst_4 " *) SRLC32E #( .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0)) SRLC32E_inst_4 (.A({1'b0,1'b0,1'b0,1'b1,1'b0}), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(rxdatavalid_to_fifo_i), .Q(rxdatavalid_lookahead_i), .Q31(NLW_SRLC32E_inst_4_Q31_UNCONNECTED)); LUT4 #( .INIT(16'hFF80)) START_CB_WRITES_OUT_i_1 (.I0(START_CB_WRITES_OUT_reg_0), .I1(cb_fifo_din_detect_q), .I2(p_0_in0_in), .I3(START_CB_WRITES_OUT), .O(START_CB_WRITES_OUT_i_1_n_0)); FDRE #( .INIT(1'b0)) START_CB_WRITES_OUT_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(START_CB_WRITES_OUT_i_1_n_0), .Q(START_CB_WRITES_OUT), .R(SR)); LUT4 #( .INIT(16'hFFFE)) any_vld_btf_fifo_din_detect_dlyd_i_1 (.I0(any_vld_btf_fifo_din_detect_dlyd_i_3_n_0), .I1(SR), .I2(wait_for_wr_en_wr4[3]), .I3(wait_for_wr_en_wr4[1]), .O(any_vld_btf_fifo_din_detect_dlyd_i_1_n_0)); LUT5 #( .INIT(32'h01000000)) any_vld_btf_fifo_din_detect_dlyd_i_2 (.I0(\raw_data_r_r_reg_n_0_[18] ), .I1(\raw_data_r_r_reg_n_0_[17] ), .I2(\raw_data_r_r_reg_n_0_[16] ), .I3(any_vld_btf_fifo_din_detect_dlyd_i_4_n_0), .I4(any_vld_btf_fifo_din_detect_dlyd_i_5_n_0), .O(any_vld_btf_fifo_din_detect)); LUT4 #( .INIT(16'hFFEF)) any_vld_btf_fifo_din_detect_dlyd_i_3 (.I0(wait_for_wr_en_wr4[2]), .I1(wait_for_wr_en_wr4[4]), .I2(wait_for_wr_en_wr4[5]), .I3(wait_for_wr_en_wr4[0]), .O(any_vld_btf_fifo_din_detect_dlyd_i_3_n_0)); LUT5 #( .INIT(32'h00100000)) any_vld_btf_fifo_din_detect_dlyd_i_4 (.I0(\raw_data_r_r_reg_n_0_[19] ), .I1(\raw_data_r_r_reg_n_0_[20] ), .I2(\raw_data_r_r_reg_n_0_[22] ), .I3(\raw_data_r_r_reg_n_0_[21] ), .I4(any_vld_btf_fifo_din_detect_dlyd_i_6_n_0), .O(any_vld_btf_fifo_din_detect_dlyd_i_4_n_0)); LUT5 #( .INIT(32'h10000000)) any_vld_btf_fifo_din_detect_dlyd_i_5 (.I0(\raw_data_r_r_reg_n_0_[31] ), .I1(\raw_data_r_r_reg_n_0_[32] ), .I2(\raw_data_r_r_reg_n_0_[33] ), .I3(p_0_in0_in), .I4(any_vld_btf_fifo_din_detect_dlyd_i_7_n_0), .O(any_vld_btf_fifo_din_detect_dlyd_i_5_n_0)); LUT4 #( .INIT(16'h0001)) any_vld_btf_fifo_din_detect_dlyd_i_6 (.I0(\raw_data_r_r_reg_n_0_[26] ), .I1(\raw_data_r_r_reg_n_0_[25] ), .I2(\raw_data_r_r_reg_n_0_[24] ), .I3(\raw_data_r_r_reg_n_0_[23] ), .O(any_vld_btf_fifo_din_detect_dlyd_i_6_n_0)); LUT4 #( .INIT(16'h8000)) any_vld_btf_fifo_din_detect_dlyd_i_7 (.I0(\raw_data_r_r_reg_n_0_[30] ), .I1(\raw_data_r_r_reg_n_0_[29] ), .I2(\raw_data_r_r_reg_n_0_[28] ), .I3(\raw_data_r_r_reg_n_0_[27] ), .O(any_vld_btf_fifo_din_detect_dlyd_i_7_n_0)); FDRE #( .INIT(1'b1)) any_vld_btf_fifo_din_detect_dlyd_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(any_vld_btf_fifo_din_detect), .Q(any_vld_btf_fifo_din_detect_dlyd), .R(any_vld_btf_fifo_din_detect_dlyd_i_1_n_0)); FDRE #( .INIT(1'b0)) cb_fifo_din_detect_q_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(any_vld_btf_fifo_din_detect), .Q(cb_fifo_din_detect_q), .R(SR)); LUT1 #( .INIT(2'h1)) \count_for_reset_r[0]_i_3 (.I0(count_for_reset_r_reg[0]), .O(\count_for_reset_r[0]_i_3_n_0 )); FDRE \count_for_reset_r_reg[0] (.C(init_clk), .CE(1'b1), .D(\count_for_reset_r_reg[0]_i_2_n_15 ), .Q(count_for_reset_r_reg[0]), .R(\count_for_reset_r_reg[23]_0 )); (* ADDER_THRESHOLD = "16" *) CARRY8 \count_for_reset_r_reg[0]_i_2 (.CI(1'b0), .CI_TOP(1'b0), .CO({\count_for_reset_r_reg[0]_i_2_n_0 ,\count_for_reset_r_reg[0]_i_2_n_1 ,\count_for_reset_r_reg[0]_i_2_n_2 ,\count_for_reset_r_reg[0]_i_2_n_3 ,\count_for_reset_r_reg[0]_i_2_n_4 ,\count_for_reset_r_reg[0]_i_2_n_5 ,\count_for_reset_r_reg[0]_i_2_n_6 ,\count_for_reset_r_reg[0]_i_2_n_7 }), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}), .O({\count_for_reset_r_reg[0]_i_2_n_8 ,\count_for_reset_r_reg[0]_i_2_n_9 ,\count_for_reset_r_reg[0]_i_2_n_10 ,\count_for_reset_r_reg[0]_i_2_n_11 ,\count_for_reset_r_reg[0]_i_2_n_12 ,\count_for_reset_r_reg[0]_i_2_n_13 ,\count_for_reset_r_reg[0]_i_2_n_14 ,\count_for_reset_r_reg[0]_i_2_n_15 }), .S({count_for_reset_r_reg[7:1],\count_for_reset_r[0]_i_3_n_0 })); FDRE \count_for_reset_r_reg[10] (.C(init_clk), .CE(1'b1), .D(\count_for_reset_r_reg[8]_i_1_n_13 ), .Q(count_for_reset_r_reg[10]), .R(\count_for_reset_r_reg[23]_0 )); FDRE \count_for_reset_r_reg[11] (.C(init_clk), .CE(1'b1), .D(\count_for_reset_r_reg[8]_i_1_n_12 ), .Q(count_for_reset_r_reg[11]), .R(\count_for_reset_r_reg[23]_0 )); FDRE \count_for_reset_r_reg[12] (.C(init_clk), .CE(1'b1), .D(\count_for_reset_r_reg[8]_i_1_n_11 ), .Q(count_for_reset_r_reg[12]), .R(\count_for_reset_r_reg[23]_0 )); FDRE \count_for_reset_r_reg[13] (.C(init_clk), .CE(1'b1), .D(\count_for_reset_r_reg[8]_i_1_n_10 ), .Q(count_for_reset_r_reg[13]), .R(\count_for_reset_r_reg[23]_0 )); FDRE \count_for_reset_r_reg[14] (.C(init_clk), .CE(1'b1), .D(\count_for_reset_r_reg[8]_i_1_n_9 ), .Q(count_for_reset_r_reg[14]), .R(\count_for_reset_r_reg[23]_0 )); FDRE \count_for_reset_r_reg[15] (.C(init_clk), .CE(1'b1), .D(\count_for_reset_r_reg[8]_i_1_n_8 ), .Q(count_for_reset_r_reg[15]), .R(\count_for_reset_r_reg[23]_0 )); FDRE \count_for_reset_r_reg[16] (.C(init_clk), .CE(1'b1), .D(\count_for_reset_r_reg[16]_i_1_n_15 ), .Q(count_for_reset_r_reg[16]), .R(\count_for_reset_r_reg[23]_0 )); (* ADDER_THRESHOLD = "16" *) CARRY8 \count_for_reset_r_reg[16]_i_1 (.CI(\count_for_reset_r_reg[8]_i_1_n_0 ), .CI_TOP(1'b0), .CO({\NLW_count_for_reset_r_reg[16]_i_1_CO_UNCONNECTED [7],\count_for_reset_r_reg[16]_i_1_n_1 ,\count_for_reset_r_reg[16]_i_1_n_2 ,\count_for_reset_r_reg[16]_i_1_n_3 ,\count_for_reset_r_reg[16]_i_1_n_4 ,\count_for_reset_r_reg[16]_i_1_n_5 ,\count_for_reset_r_reg[16]_i_1_n_6 ,\count_for_reset_r_reg[16]_i_1_n_7 }), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .O({\count_for_reset_r_reg[16]_i_1_n_8 ,\count_for_reset_r_reg[16]_i_1_n_9 ,\count_for_reset_r_reg[16]_i_1_n_10 ,\count_for_reset_r_reg[16]_i_1_n_11 ,\count_for_reset_r_reg[16]_i_1_n_12 ,\count_for_reset_r_reg[16]_i_1_n_13 ,\count_for_reset_r_reg[16]_i_1_n_14 ,\count_for_reset_r_reg[16]_i_1_n_15 }), .S(count_for_reset_r_reg[23:16])); FDRE \count_for_reset_r_reg[17] (.C(init_clk), .CE(1'b1), .D(\count_for_reset_r_reg[16]_i_1_n_14 ), .Q(count_for_reset_r_reg[17]), .R(\count_for_reset_r_reg[23]_0 )); FDRE \count_for_reset_r_reg[18] (.C(init_clk), .CE(1'b1), .D(\count_for_reset_r_reg[16]_i_1_n_13 ), .Q(count_for_reset_r_reg[18]), .R(\count_for_reset_r_reg[23]_0 )); FDRE \count_for_reset_r_reg[19] (.C(init_clk), .CE(1'b1), .D(\count_for_reset_r_reg[16]_i_1_n_12 ), .Q(count_for_reset_r_reg[19]), .R(\count_for_reset_r_reg[23]_0 )); FDRE \count_for_reset_r_reg[1] (.C(init_clk), .CE(1'b1), .D(\count_for_reset_r_reg[0]_i_2_n_14 ), .Q(count_for_reset_r_reg[1]), .R(\count_for_reset_r_reg[23]_0 )); FDRE \count_for_reset_r_reg[20] (.C(init_clk), .CE(1'b1), .D(\count_for_reset_r_reg[16]_i_1_n_11 ), .Q(count_for_reset_r_reg[20]), .R(\count_for_reset_r_reg[23]_0 )); FDRE \count_for_reset_r_reg[21] (.C(init_clk), .CE(1'b1), .D(\count_for_reset_r_reg[16]_i_1_n_10 ), .Q(count_for_reset_r_reg[21]), .R(\count_for_reset_r_reg[23]_0 )); FDRE \count_for_reset_r_reg[22] (.C(init_clk), .CE(1'b1), .D(\count_for_reset_r_reg[16]_i_1_n_9 ), .Q(count_for_reset_r_reg[22]), .R(\count_for_reset_r_reg[23]_0 )); FDRE \count_for_reset_r_reg[23] (.C(init_clk), .CE(1'b1), .D(\count_for_reset_r_reg[16]_i_1_n_8 ), .Q(count_for_reset_r_reg[23]), .R(\count_for_reset_r_reg[23]_0 )); FDRE \count_for_reset_r_reg[2] (.C(init_clk), .CE(1'b1), .D(\count_for_reset_r_reg[0]_i_2_n_13 ), .Q(count_for_reset_r_reg[2]), .R(\count_for_reset_r_reg[23]_0 )); FDRE \count_for_reset_r_reg[3] (.C(init_clk), .CE(1'b1), .D(\count_for_reset_r_reg[0]_i_2_n_12 ), .Q(count_for_reset_r_reg[3]), .R(\count_for_reset_r_reg[23]_0 )); FDRE \count_for_reset_r_reg[4] (.C(init_clk), .CE(1'b1), .D(\count_for_reset_r_reg[0]_i_2_n_11 ), .Q(count_for_reset_r_reg[4]), .R(\count_for_reset_r_reg[23]_0 )); FDRE \count_for_reset_r_reg[5] (.C(init_clk), .CE(1'b1), .D(\count_for_reset_r_reg[0]_i_2_n_10 ), .Q(count_for_reset_r_reg[5]), .R(\count_for_reset_r_reg[23]_0 )); FDRE \count_for_reset_r_reg[6] (.C(init_clk), .CE(1'b1), .D(\count_for_reset_r_reg[0]_i_2_n_9 ), .Q(count_for_reset_r_reg[6]), .R(\count_for_reset_r_reg[23]_0 )); FDRE \count_for_reset_r_reg[7] (.C(init_clk), .CE(1'b1), .D(\count_for_reset_r_reg[0]_i_2_n_8 ), .Q(count_for_reset_r_reg[7]), .R(\count_for_reset_r_reg[23]_0 )); FDRE \count_for_reset_r_reg[8] (.C(init_clk), .CE(1'b1), .D(\count_for_reset_r_reg[8]_i_1_n_15 ), .Q(count_for_reset_r_reg[8]), .R(\count_for_reset_r_reg[23]_0 )); (* ADDER_THRESHOLD = "16" *) CARRY8 \count_for_reset_r_reg[8]_i_1 (.CI(\count_for_reset_r_reg[0]_i_2_n_0 ), .CI_TOP(1'b0), .CO({\count_for_reset_r_reg[8]_i_1_n_0 ,\count_for_reset_r_reg[8]_i_1_n_1 ,\count_for_reset_r_reg[8]_i_1_n_2 ,\count_for_reset_r_reg[8]_i_1_n_3 ,\count_for_reset_r_reg[8]_i_1_n_4 ,\count_for_reset_r_reg[8]_i_1_n_5 ,\count_for_reset_r_reg[8]_i_1_n_6 ,\count_for_reset_r_reg[8]_i_1_n_7 }), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .O({\count_for_reset_r_reg[8]_i_1_n_8 ,\count_for_reset_r_reg[8]_i_1_n_9 ,\count_for_reset_r_reg[8]_i_1_n_10 ,\count_for_reset_r_reg[8]_i_1_n_11 ,\count_for_reset_r_reg[8]_i_1_n_12 ,\count_for_reset_r_reg[8]_i_1_n_13 ,\count_for_reset_r_reg[8]_i_1_n_14 ,\count_for_reset_r_reg[8]_i_1_n_15 }), .S(count_for_reset_r_reg[15:8])); FDRE \count_for_reset_r_reg[9] (.C(init_clk), .CE(1'b1), .D(\count_for_reset_r_reg[8]_i_1_n_14 ), .Q(count_for_reset_r_reg[9]), .R(\count_for_reset_r_reg[23]_0 )); LUT3 #( .INIT(8'hBF)) do_rd_en_i_1 (.I0(cbcc_fifo_reset_rd_clk), .I1(wait_for_rd_en[2]), .I2(wait_for_rd_en[1]), .O(do_rd_en)); FDRE #( .INIT(1'b0)) do_rd_en_reg (.C(s_level_out_d5_reg), .CE(1'b1), .D(new_underflow_flag_c), .Q(do_rd_en_i), .R(do_rd_en)); LUT5 #( .INIT(32'h000C0008)) do_wr_en_i_1 (.I0(FINAL_GATER_FOR_FIFO_DIN0), .I1(p_1_in), .I2(overflow_flag_c), .I3(any_vld_btf_fifo_din_detect_dlyd_i_1_n_0), .I4(final_gater_for_fifo_din_i), .O(do_wr_en_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair46" *) LUT3 #( .INIT(8'h80)) do_wr_en_i_2 (.I0(p_0_in0_in), .I1(cb_fifo_din_detect_q), .I2(FINAL_GATER_FOR_FIFO_DIN_reg_0), .O(FINAL_GATER_FOR_FIFO_DIN0)); FDRE #( .INIT(1'b0)) do_wr_en_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(do_wr_en_i_1_n_0), .Q(do_wr_en), .R(1'b0)); LUT5 #( .INIT(32'h01000000)) first_cb_to_write_to_fifo_dlyd_i_1 (.I0(\raw_data_r_reg_n_0_[18] ), .I1(\raw_data_r_reg_n_0_[17] ), .I2(\raw_data_r_reg_n_0_[16] ), .I3(first_cb_to_write_to_fifo_dlyd_i_2_n_0), .I4(first_cb_to_write_to_fifo_dlyd_i_3_n_0), .O(first_cb_to_write_to_fifo)); LUT5 #( .INIT(32'h00100000)) first_cb_to_write_to_fifo_dlyd_i_2 (.I0(\raw_data_r_reg_n_0_[19] ), .I1(\raw_data_r_reg_n_0_[20] ), .I2(\raw_data_r_reg_n_0_[22] ), .I3(\raw_data_r_reg_n_0_[21] ), .I4(first_cb_to_write_to_fifo_dlyd_i_4_n_0), .O(first_cb_to_write_to_fifo_dlyd_i_2_n_0)); LUT5 #( .INIT(32'h10000000)) first_cb_to_write_to_fifo_dlyd_i_3 (.I0(\raw_data_r_reg_n_0_[31] ), .I1(\raw_data_r_reg_n_0_[32] ), .I2(\raw_data_r_reg_n_0_[33] ), .I3(p_1_in), .I4(first_cb_to_write_to_fifo_dlyd_i_5_n_0), .O(first_cb_to_write_to_fifo_dlyd_i_3_n_0)); LUT4 #( .INIT(16'h0001)) first_cb_to_write_to_fifo_dlyd_i_4 (.I0(\raw_data_r_reg_n_0_[26] ), .I1(\raw_data_r_reg_n_0_[25] ), .I2(\raw_data_r_reg_n_0_[24] ), .I3(\raw_data_r_reg_n_0_[23] ), .O(first_cb_to_write_to_fifo_dlyd_i_4_n_0)); LUT4 #( .INIT(16'h8000)) first_cb_to_write_to_fifo_dlyd_i_5 (.I0(\raw_data_r_reg_n_0_[30] ), .I1(\raw_data_r_reg_n_0_[29] ), .I2(\raw_data_r_reg_n_0_[28] ), .I3(\raw_data_r_reg_n_0_[27] ), .O(first_cb_to_write_to_fifo_dlyd_i_5_n_0)); FDRE #( .INIT(1'b0)) first_cb_to_write_to_fifo_dlyd_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(first_cb_to_write_to_fifo), .Q(first_cb_to_write_to_fifo_dlyd), .R(SR)); LUT6 #( .INIT(64'hFFFFAAA8AAA8AAA8)) hard_err_usr_i_1 (.I0(hard_err_usr_reg), .I1(rxbuferr_out_i[1]), .I2(rxbuferr_out_i[0]), .I3(HARD_ERR_reg), .I4(channel_up_tx_if), .I5(txbufstatus_out), .O(hard_err_usr0)); LUT2 #( .INIT(4'hE)) hold_reg_i_1 (.I0(do_rd_en_i), .I1(hold_reg), .O(hold_reg_i_1_n_0)); FDRE hold_reg_reg (.C(s_level_out_d5_reg), .CE(1'b1), .D(hold_reg_i_1_n_0), .Q(hold_reg), .R(CC_RXLOSSOFSYNC_OUT_reg_0)); (* shift_extract = "{no}" *) FDRE master_do_rd_en_q_reg (.C(s_level_out_d5_reg), .CE(1'b1), .D(out), .Q(master_do_rd_en_q), .R(cbcc_fifo_reset_rd_clk)); (* CHECK_LICENSE_TYPE = "aurora_64b66b_0_fifo_gen_master,fifo_generator_v13_2_5,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "fifo_generator_v13_2_5,Vivado 2020.2" *) aurora_64b66b_0_aurora_64b66b_0_fifo_gen_master \master_fifo.data_fifo (.din({en32_fifo_din_i[79:40],en32_fifo_din_i[31:0]}), .dout({\NLW_master_fifo.data_fifo_dout_UNCONNECTED [71:69],p_0_in4_in,\NLW_master_fifo.data_fifo_dout_UNCONNECTED [67:66],dout}), .empty(underflow_flag_c), .full(overflow_flag_c), .overflow(wr_err_c), .prog_empty(buffer_too_empty_c), .prog_full(\NLW_master_fifo.data_fifo_prog_full_UNCONNECTED ), .rd_clk(s_level_out_d5_reg), .rd_en(out), .rd_rst_busy(\NLW_master_fifo.data_fifo_rd_rst_busy_UNCONNECTED ), .srst(srst), .underflow(rd_err_c), .wr_clk(gtwiz_userclk_rx_usrclk_out), .wr_en(new_do_wr_en), .wr_rst_busy(\NLW_master_fifo.data_fifo_wr_rst_busy_UNCONNECTED )); LUT2 #( .INIT(4'h2)) new_do_wr_en_i_1 (.I0(bit80_prsnt), .I1(any_vld_btf_fifo_din_detect_dlyd_i_1_n_0), .O(new_do_wr_en_i_1_n_0)); FDRE #( .INIT(1'b0)) new_do_wr_en_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(new_do_wr_en_i_1_n_0), .Q(new_do_wr_en), .R(1'b0)); LUT3 #( .INIT(8'h57)) new_underflow_flag_c_inv_i_1 (.I0(underflow_flag_r3), .I1(buffer_too_empty_c), .I2(underflow_flag_c), .O(new_underflow_flag_c0)); (* inverted = "yes" *) FDRE new_underflow_flag_c_reg_inv (.C(s_level_out_d5_reg), .CE(1'b1), .D(new_underflow_flag_c0), .Q(new_underflow_flag_c), .R(cbcc_fifo_reset_rd_clk)); (* shift_extract = "{no}" *) FDRE \raw_data_r_r_reg[0] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\raw_data_r_reg_n_0_[0] ), .Q(\raw_data_r_r_reg_n_0_[0] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_r_reg[10] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\raw_data_r_reg_n_0_[10] ), .Q(\raw_data_r_r_reg_n_0_[10] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_r_reg[11] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\raw_data_r_reg_n_0_[11] ), .Q(\raw_data_r_r_reg_n_0_[11] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_r_reg[12] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\raw_data_r_reg_n_0_[12] ), .Q(\raw_data_r_r_reg_n_0_[12] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_r_reg[13] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\raw_data_r_reg_n_0_[13] ), .Q(\raw_data_r_r_reg_n_0_[13] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_r_reg[14] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\raw_data_r_reg_n_0_[14] ), .Q(\raw_data_r_r_reg_n_0_[14] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_r_reg[15] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\raw_data_r_reg_n_0_[15] ), .Q(\raw_data_r_r_reg_n_0_[15] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_r_reg[16] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\raw_data_r_reg_n_0_[16] ), .Q(\raw_data_r_r_reg_n_0_[16] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_r_reg[17] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\raw_data_r_reg_n_0_[17] ), .Q(\raw_data_r_r_reg_n_0_[17] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_r_reg[18] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\raw_data_r_reg_n_0_[18] ), .Q(\raw_data_r_r_reg_n_0_[18] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_r_reg[19] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\raw_data_r_reg_n_0_[19] ), .Q(\raw_data_r_r_reg_n_0_[19] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_r_reg[1] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\raw_data_r_reg_n_0_[1] ), .Q(\raw_data_r_r_reg_n_0_[1] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_r_reg[20] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\raw_data_r_reg_n_0_[20] ), .Q(\raw_data_r_r_reg_n_0_[20] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_r_reg[21] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\raw_data_r_reg_n_0_[21] ), .Q(\raw_data_r_r_reg_n_0_[21] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_r_reg[22] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\raw_data_r_reg_n_0_[22] ), .Q(\raw_data_r_r_reg_n_0_[22] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_r_reg[23] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\raw_data_r_reg_n_0_[23] ), .Q(\raw_data_r_r_reg_n_0_[23] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_r_reg[24] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\raw_data_r_reg_n_0_[24] ), .Q(\raw_data_r_r_reg_n_0_[24] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_r_reg[25] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\raw_data_r_reg_n_0_[25] ), .Q(\raw_data_r_r_reg_n_0_[25] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_r_reg[26] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\raw_data_r_reg_n_0_[26] ), .Q(\raw_data_r_r_reg_n_0_[26] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_r_reg[27] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\raw_data_r_reg_n_0_[27] ), .Q(\raw_data_r_r_reg_n_0_[27] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_r_reg[28] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\raw_data_r_reg_n_0_[28] ), .Q(\raw_data_r_r_reg_n_0_[28] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_r_reg[29] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\raw_data_r_reg_n_0_[29] ), .Q(\raw_data_r_r_reg_n_0_[29] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_r_reg[2] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\raw_data_r_reg_n_0_[2] ), .Q(\raw_data_r_r_reg_n_0_[2] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_r_reg[30] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\raw_data_r_reg_n_0_[30] ), .Q(\raw_data_r_r_reg_n_0_[30] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_r_reg[31] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\raw_data_r_reg_n_0_[31] ), .Q(\raw_data_r_r_reg_n_0_[31] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_r_reg[32] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\raw_data_r_reg_n_0_[32] ), .Q(\raw_data_r_r_reg_n_0_[32] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_r_reg[33] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\raw_data_r_reg_n_0_[33] ), .Q(\raw_data_r_r_reg_n_0_[33] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_r_reg[34] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(p_1_in), .Q(p_0_in0_in), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_r_reg[3] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\raw_data_r_reg_n_0_[3] ), .Q(\raw_data_r_r_reg_n_0_[3] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_r_reg[4] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\raw_data_r_reg_n_0_[4] ), .Q(\raw_data_r_r_reg_n_0_[4] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_r_reg[5] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\raw_data_r_reg_n_0_[5] ), .Q(\raw_data_r_r_reg_n_0_[5] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_r_reg[6] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\raw_data_r_reg_n_0_[6] ), .Q(\raw_data_r_r_reg_n_0_[6] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_r_reg[7] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\raw_data_r_reg_n_0_[7] ), .Q(\raw_data_r_r_reg_n_0_[7] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_r_reg[8] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\raw_data_r_reg_n_0_[8] ), .Q(\raw_data_r_r_reg_n_0_[8] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_r_reg[9] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\raw_data_r_reg_n_0_[9] ), .Q(\raw_data_r_r_reg_n_0_[9] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_reg[0] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(raw_data_srl_out[0]), .Q(\raw_data_r_reg_n_0_[0] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_reg[10] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(raw_data_srl_out[10]), .Q(\raw_data_r_reg_n_0_[10] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_reg[11] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(raw_data_srl_out[11]), .Q(\raw_data_r_reg_n_0_[11] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_reg[12] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(raw_data_srl_out[12]), .Q(\raw_data_r_reg_n_0_[12] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_reg[13] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(raw_data_srl_out[13]), .Q(\raw_data_r_reg_n_0_[13] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_reg[14] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(raw_data_srl_out[14]), .Q(\raw_data_r_reg_n_0_[14] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_reg[15] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(raw_data_srl_out[15]), .Q(\raw_data_r_reg_n_0_[15] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_reg[16] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(raw_data_srl_out[16]), .Q(\raw_data_r_reg_n_0_[16] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_reg[17] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(raw_data_srl_out[17]), .Q(\raw_data_r_reg_n_0_[17] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_reg[18] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(raw_data_srl_out[18]), .Q(\raw_data_r_reg_n_0_[18] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_reg[19] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(raw_data_srl_out[19]), .Q(\raw_data_r_reg_n_0_[19] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_reg[1] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(raw_data_srl_out[1]), .Q(\raw_data_r_reg_n_0_[1] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_reg[20] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(raw_data_srl_out[20]), .Q(\raw_data_r_reg_n_0_[20] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_reg[21] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(raw_data_srl_out[21]), .Q(\raw_data_r_reg_n_0_[21] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_reg[22] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(raw_data_srl_out[22]), .Q(\raw_data_r_reg_n_0_[22] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_reg[23] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(raw_data_srl_out[23]), .Q(\raw_data_r_reg_n_0_[23] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_reg[24] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(raw_data_srl_out[24]), .Q(\raw_data_r_reg_n_0_[24] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_reg[25] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(raw_data_srl_out[25]), .Q(\raw_data_r_reg_n_0_[25] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_reg[26] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(raw_data_srl_out[26]), .Q(\raw_data_r_reg_n_0_[26] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_reg[27] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(raw_data_srl_out[27]), .Q(\raw_data_r_reg_n_0_[27] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_reg[28] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(raw_data_srl_out[28]), .Q(\raw_data_r_reg_n_0_[28] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_reg[29] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(raw_data_srl_out[29]), .Q(\raw_data_r_reg_n_0_[29] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_reg[2] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(raw_data_srl_out[2]), .Q(\raw_data_r_reg_n_0_[2] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_reg[30] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(raw_data_srl_out[30]), .Q(\raw_data_r_reg_n_0_[30] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_reg[31] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(raw_data_srl_out[31]), .Q(\raw_data_r_reg_n_0_[31] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_reg[32] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(raw_data_srl_out[32]), .Q(\raw_data_r_reg_n_0_[32] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_reg[33] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(raw_data_srl_out[33]), .Q(\raw_data_r_reg_n_0_[33] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_reg[34] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(raw_data_srl_out[34]), .Q(p_1_in), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_reg[3] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(raw_data_srl_out[3]), .Q(\raw_data_r_reg_n_0_[3] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_reg[4] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(raw_data_srl_out[4]), .Q(\raw_data_r_reg_n_0_[4] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_reg[5] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(raw_data_srl_out[5]), .Q(\raw_data_r_reg_n_0_[5] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_reg[6] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(raw_data_srl_out[6]), .Q(\raw_data_r_reg_n_0_[6] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_reg[7] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(raw_data_srl_out[7]), .Q(\raw_data_r_reg_n_0_[7] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_reg[8] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(raw_data_srl_out[8]), .Q(\raw_data_r_reg_n_0_[8] ), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \raw_data_r_reg[9] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(raw_data_srl_out[9]), .Q(\raw_data_r_reg_n_0_[9] ), .R(1'b0)); FDRE rd_err_pre_reg (.C(s_level_out_d5_reg), .CE(1'b1), .D(rd_err_c), .Q(rd_err_pre), .R(do_rd_en)); FDRE rd_err_q_reg (.C(s_level_out_d5_reg), .CE(1'b1), .D(rd_err_pre), .Q(rxbuferr_out_i[0]), .R(do_rd_en)); (* SOFT_HLUTNM = "soft_lutpair47" *) LUT4 #( .INIT(16'hFFFE)) rxfsm_reset_i_inferred_i_1 (.I0(allow_block_sync_propagation_reg), .I1(LINK_RESET_OUT_reg), .I2(link_reset_0_c), .I3(hard_err_rst_int), .O(rxfsm_reset_i)); (* BOX_TYPE = "PRIMITIVE" *) (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[0].SRLC32E_inst_1 " *) SRLC32E #( .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0)) \srlc32e[0].SRLC32E_inst_1 (.A({1'b0,1'b0,1'b1,1'b0,1'b0}), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(UNSCRAMBLED_DATA_OUT[0]), .Q(raw_data_srl_out[0]), .Q31(\NLW_srlc32e[0].SRLC32E_inst_1_Q31_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[10].SRLC32E_inst_1 " *) SRLC32E #( .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0)) \srlc32e[10].SRLC32E_inst_1 (.A({1'b0,1'b0,1'b1,1'b0,1'b0}), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(UNSCRAMBLED_DATA_OUT[10]), .Q(raw_data_srl_out[10]), .Q31(\NLW_srlc32e[10].SRLC32E_inst_1_Q31_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[11].SRLC32E_inst_1 " *) SRLC32E #( .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0)) \srlc32e[11].SRLC32E_inst_1 (.A({1'b0,1'b0,1'b1,1'b0,1'b0}), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(UNSCRAMBLED_DATA_OUT[11]), .Q(raw_data_srl_out[11]), .Q31(\NLW_srlc32e[11].SRLC32E_inst_1_Q31_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[12].SRLC32E_inst_1 " *) SRLC32E #( .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0)) \srlc32e[12].SRLC32E_inst_1 (.A({1'b0,1'b0,1'b1,1'b0,1'b0}), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(UNSCRAMBLED_DATA_OUT[12]), .Q(raw_data_srl_out[12]), .Q31(\NLW_srlc32e[12].SRLC32E_inst_1_Q31_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[13].SRLC32E_inst_1 " *) SRLC32E #( .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0)) \srlc32e[13].SRLC32E_inst_1 (.A({1'b0,1'b0,1'b1,1'b0,1'b0}), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(UNSCRAMBLED_DATA_OUT[13]), .Q(raw_data_srl_out[13]), .Q31(\NLW_srlc32e[13].SRLC32E_inst_1_Q31_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[14].SRLC32E_inst_1 " *) SRLC32E #( .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0)) \srlc32e[14].SRLC32E_inst_1 (.A({1'b0,1'b0,1'b1,1'b0,1'b0}), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(UNSCRAMBLED_DATA_OUT[14]), .Q(raw_data_srl_out[14]), .Q31(\NLW_srlc32e[14].SRLC32E_inst_1_Q31_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[15].SRLC32E_inst_1 " *) SRLC32E #( .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0)) \srlc32e[15].SRLC32E_inst_1 (.A({1'b0,1'b0,1'b1,1'b0,1'b0}), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(UNSCRAMBLED_DATA_OUT[15]), .Q(raw_data_srl_out[15]), .Q31(\NLW_srlc32e[15].SRLC32E_inst_1_Q31_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[16].SRLC32E_inst_1 " *) SRLC32E #( .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0)) \srlc32e[16].SRLC32E_inst_1 (.A({1'b0,1'b0,1'b1,1'b0,1'b0}), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(UNSCRAMBLED_DATA_OUT[16]), .Q(raw_data_srl_out[16]), .Q31(\NLW_srlc32e[16].SRLC32E_inst_1_Q31_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[17].SRLC32E_inst_1 " *) SRLC32E #( .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0)) \srlc32e[17].SRLC32E_inst_1 (.A({1'b0,1'b0,1'b1,1'b0,1'b0}), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(UNSCRAMBLED_DATA_OUT[17]), .Q(raw_data_srl_out[17]), .Q31(\NLW_srlc32e[17].SRLC32E_inst_1_Q31_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[18].SRLC32E_inst_1 " *) SRLC32E #( .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0)) \srlc32e[18].SRLC32E_inst_1 (.A({1'b0,1'b0,1'b1,1'b0,1'b0}), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(UNSCRAMBLED_DATA_OUT[18]), .Q(raw_data_srl_out[18]), .Q31(\NLW_srlc32e[18].SRLC32E_inst_1_Q31_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[19].SRLC32E_inst_1 " *) SRLC32E #( .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0)) \srlc32e[19].SRLC32E_inst_1 (.A({1'b0,1'b0,1'b1,1'b0,1'b0}), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(UNSCRAMBLED_DATA_OUT[19]), .Q(raw_data_srl_out[19]), .Q31(\NLW_srlc32e[19].SRLC32E_inst_1_Q31_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[1].SRLC32E_inst_1 " *) SRLC32E #( .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0)) \srlc32e[1].SRLC32E_inst_1 (.A({1'b0,1'b0,1'b1,1'b0,1'b0}), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(UNSCRAMBLED_DATA_OUT[1]), .Q(raw_data_srl_out[1]), .Q31(\NLW_srlc32e[1].SRLC32E_inst_1_Q31_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[20].SRLC32E_inst_1 " *) SRLC32E #( .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0)) \srlc32e[20].SRLC32E_inst_1 (.A({1'b0,1'b0,1'b1,1'b0,1'b0}), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(UNSCRAMBLED_DATA_OUT[20]), .Q(raw_data_srl_out[20]), .Q31(\NLW_srlc32e[20].SRLC32E_inst_1_Q31_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[21].SRLC32E_inst_1 " *) SRLC32E #( .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0)) \srlc32e[21].SRLC32E_inst_1 (.A({1'b0,1'b0,1'b1,1'b0,1'b0}), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(UNSCRAMBLED_DATA_OUT[21]), .Q(raw_data_srl_out[21]), .Q31(\NLW_srlc32e[21].SRLC32E_inst_1_Q31_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[22].SRLC32E_inst_1 " *) SRLC32E #( .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0)) \srlc32e[22].SRLC32E_inst_1 (.A({1'b0,1'b0,1'b1,1'b0,1'b0}), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(UNSCRAMBLED_DATA_OUT[22]), .Q(raw_data_srl_out[22]), .Q31(\NLW_srlc32e[22].SRLC32E_inst_1_Q31_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[23].SRLC32E_inst_1 " *) SRLC32E #( .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0)) \srlc32e[23].SRLC32E_inst_1 (.A({1'b0,1'b0,1'b1,1'b0,1'b0}), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(UNSCRAMBLED_DATA_OUT[23]), .Q(raw_data_srl_out[23]), .Q31(\NLW_srlc32e[23].SRLC32E_inst_1_Q31_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[24].SRLC32E_inst_1 " *) SRLC32E #( .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0)) \srlc32e[24].SRLC32E_inst_1 (.A({1'b0,1'b0,1'b1,1'b0,1'b0}), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(UNSCRAMBLED_DATA_OUT[24]), .Q(raw_data_srl_out[24]), .Q31(\NLW_srlc32e[24].SRLC32E_inst_1_Q31_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[25].SRLC32E_inst_1 " *) SRLC32E #( .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0)) \srlc32e[25].SRLC32E_inst_1 (.A({1'b0,1'b0,1'b1,1'b0,1'b0}), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(UNSCRAMBLED_DATA_OUT[25]), .Q(raw_data_srl_out[25]), .Q31(\NLW_srlc32e[25].SRLC32E_inst_1_Q31_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[26].SRLC32E_inst_1 " *) SRLC32E #( .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0)) \srlc32e[26].SRLC32E_inst_1 (.A({1'b0,1'b0,1'b1,1'b0,1'b0}), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(UNSCRAMBLED_DATA_OUT[26]), .Q(raw_data_srl_out[26]), .Q31(\NLW_srlc32e[26].SRLC32E_inst_1_Q31_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[27].SRLC32E_inst_1 " *) SRLC32E #( .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0)) \srlc32e[27].SRLC32E_inst_1 (.A({1'b0,1'b0,1'b1,1'b0,1'b0}), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(UNSCRAMBLED_DATA_OUT[27]), .Q(raw_data_srl_out[27]), .Q31(\NLW_srlc32e[27].SRLC32E_inst_1_Q31_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[28].SRLC32E_inst_1 " *) SRLC32E #( .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0)) \srlc32e[28].SRLC32E_inst_1 (.A({1'b0,1'b0,1'b1,1'b0,1'b0}), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(UNSCRAMBLED_DATA_OUT[28]), .Q(raw_data_srl_out[28]), .Q31(\NLW_srlc32e[28].SRLC32E_inst_1_Q31_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[29].SRLC32E_inst_1 " *) SRLC32E #( .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0)) \srlc32e[29].SRLC32E_inst_1 (.A({1'b0,1'b0,1'b1,1'b0,1'b0}), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(UNSCRAMBLED_DATA_OUT[29]), .Q(raw_data_srl_out[29]), .Q31(\NLW_srlc32e[29].SRLC32E_inst_1_Q31_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[2].SRLC32E_inst_1 " *) SRLC32E #( .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0)) \srlc32e[2].SRLC32E_inst_1 (.A({1'b0,1'b0,1'b1,1'b0,1'b0}), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(UNSCRAMBLED_DATA_OUT[2]), .Q(raw_data_srl_out[2]), .Q31(\NLW_srlc32e[2].SRLC32E_inst_1_Q31_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[30].SRLC32E_inst_1 " *) SRLC32E #( .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0)) \srlc32e[30].SRLC32E_inst_1 (.A({1'b0,1'b0,1'b1,1'b0,1'b0}), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(UNSCRAMBLED_DATA_OUT[30]), .Q(raw_data_srl_out[30]), .Q31(\NLW_srlc32e[30].SRLC32E_inst_1_Q31_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[31].SRLC32E_inst_1 " *) SRLC32E #( .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0)) \srlc32e[31].SRLC32E_inst_1 (.A({1'b0,1'b0,1'b1,1'b0,1'b0}), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(UNSCRAMBLED_DATA_OUT[31]), .Q(raw_data_srl_out[31]), .Q31(\NLW_srlc32e[31].SRLC32E_inst_1_Q31_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[32].SRLC32E_inst_1 " *) SRLC32E #( .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0)) \srlc32e[32].SRLC32E_inst_1 (.A({1'b0,1'b0,1'b1,1'b0,1'b0}), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(Q[0]), .Q(raw_data_srl_out[32]), .Q31(\NLW_srlc32e[32].SRLC32E_inst_1_Q31_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[33].SRLC32E_inst_1 " *) SRLC32E #( .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0)) \srlc32e[33].SRLC32E_inst_1 (.A({1'b0,1'b0,1'b1,1'b0,1'b0}), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(Q[1]), .Q(raw_data_srl_out[33]), .Q31(\NLW_srlc32e[33].SRLC32E_inst_1_Q31_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[34].SRLC32E_inst_1 " *) SRLC32E #( .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0)) \srlc32e[34].SRLC32E_inst_1 (.A({1'b0,1'b0,1'b1,1'b0,1'b0}), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(rxdatavalid_to_fifo_i), .Q(raw_data_srl_out[34]), .Q31(\NLW_srlc32e[34].SRLC32E_inst_1_Q31_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[3].SRLC32E_inst_1 " *) SRLC32E #( .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0)) \srlc32e[3].SRLC32E_inst_1 (.A({1'b0,1'b0,1'b1,1'b0,1'b0}), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(UNSCRAMBLED_DATA_OUT[3]), .Q(raw_data_srl_out[3]), .Q31(\NLW_srlc32e[3].SRLC32E_inst_1_Q31_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[4].SRLC32E_inst_1 " *) SRLC32E #( .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0)) \srlc32e[4].SRLC32E_inst_1 (.A({1'b0,1'b0,1'b1,1'b0,1'b0}), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(UNSCRAMBLED_DATA_OUT[4]), .Q(raw_data_srl_out[4]), .Q31(\NLW_srlc32e[4].SRLC32E_inst_1_Q31_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[5].SRLC32E_inst_1 " *) SRLC32E #( .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0)) \srlc32e[5].SRLC32E_inst_1 (.A({1'b0,1'b0,1'b1,1'b0,1'b0}), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(UNSCRAMBLED_DATA_OUT[5]), .Q(raw_data_srl_out[5]), .Q31(\NLW_srlc32e[5].SRLC32E_inst_1_Q31_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[6].SRLC32E_inst_1 " *) SRLC32E #( .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0)) \srlc32e[6].SRLC32E_inst_1 (.A({1'b0,1'b0,1'b1,1'b0,1'b0}), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(UNSCRAMBLED_DATA_OUT[6]), .Q(raw_data_srl_out[6]), .Q31(\NLW_srlc32e[6].SRLC32E_inst_1_Q31_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[7].SRLC32E_inst_1 " *) SRLC32E #( .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0)) \srlc32e[7].SRLC32E_inst_1 (.A({1'b0,1'b0,1'b1,1'b0,1'b0}), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(UNSCRAMBLED_DATA_OUT[7]), .Q(raw_data_srl_out[7]), .Q31(\NLW_srlc32e[7].SRLC32E_inst_1_Q31_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[8].SRLC32E_inst_1 " *) SRLC32E #( .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0)) \srlc32e[8].SRLC32E_inst_1 (.A({1'b0,1'b0,1'b1,1'b0,1'b0}), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(UNSCRAMBLED_DATA_OUT[8]), .Q(raw_data_srl_out[8]), .Q31(\NLW_srlc32e[8].SRLC32E_inst_1_Q31_UNCONNECTED )); (* BOX_TYPE = "PRIMITIVE" *) (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/srlc32e[9].SRLC32E_inst_1 " *) SRLC32E #( .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0)) \srlc32e[9].SRLC32E_inst_1 (.A({1'b0,1'b0,1'b1,1'b0,1'b0}), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(UNSCRAMBLED_DATA_OUT[9]), .Q(raw_data_srl_out[9]), .Q31(\NLW_srlc32e[9].SRLC32E_inst_1_Q31_UNCONNECTED )); aurora_64b66b_0_aurora_64b66b_0_cdc_sync__parameterized3 u_cdc_overflow_flag_c (.cbcc_reset_cbstg2_rd_clk(cbcc_reset_cbstg2_rd_clk), .full(overflow_flag_c), .s_level_out_d5_reg_0(s_level_out_d5_reg)); aurora_64b66b_0_aurora_64b66b_0_cdc_sync__parameterized0_27 u_cdc_rxlossofsync_in (.in0(in0), .s_level_out_d5_reg_0(u_cdc_rxlossofsync_in_n_0), .s_level_out_d5_reg_1(s_level_out_d5_reg)); aurora_64b66b_0_aurora_64b66b_0_cdc_sync__parameterized3_28 u_cdc_wr_err_rd_clk (.cbcc_fifo_reset_rd_clk(cbcc_fifo_reset_rd_clk), .out(wr_err_rd_clk_pre), .overflow(wr_err_c), .s_level_out_d5_reg_0(s_level_out_d5_reg)); aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized1_29 u_rst_sync_btf_sync (.in0(valid_btf_detect_extend_r2), .init_clk(init_clk), .stg3_reg_0(u_rst_sync_btf_sync_n_0)); LUT2 #( .INIT(4'hE)) underflow_flag_r1_i_1 (.I0(underflow_flag_c), .I1(buffer_too_empty_c), .O(underflow_flag_r10)); FDSE underflow_flag_r1_reg (.C(s_level_out_d5_reg), .CE(1'b1), .D(underflow_flag_r10), .Q(underflow_flag_r1), .S(cbcc_fifo_reset_rd_clk)); FDSE underflow_flag_r2_reg (.C(s_level_out_d5_reg), .CE(1'b1), .D(underflow_flag_r1), .Q(underflow_flag_r2), .S(cbcc_fifo_reset_rd_clk)); FDSE underflow_flag_r3_reg (.C(s_level_out_d5_reg), .CE(1'b1), .D(underflow_flag_r2), .Q(underflow_flag_r3), .S(cbcc_fifo_reset_rd_clk)); FDRE #( .INIT(1'b0)) valid_btf_detect_dlyd1_reg (.C(init_clk), .CE(1'b1), .D(u_rst_sync_btf_sync_n_0), .Q(valid_btf_detect_dlyd1), .R(1'b0)); LUT5 #( .INIT(32'hFFFFFFFE)) valid_btf_detect_extend_r20 (.I0(valid_btf_detect_extend_r[0]), .I1(valid_btf_detect_extend_r[3]), .I2(valid_btf_detect_extend_r[4]), .I3(valid_btf_detect_extend_r[1]), .I4(valid_btf_detect_extend_r[2]), .O(valid_btf_detect_extend_r20_n_0)); FDRE valid_btf_detect_extend_r2_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(valid_btf_detect_extend_r20_n_0), .Q(valid_btf_detect_extend_r2), .R(1'b0)); FDRE #( .INIT(1'b0)) \valid_btf_detect_extend_r_reg[0] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(valid_btf_detect_extend_r[1]), .Q(valid_btf_detect_extend_r[0]), .R(\valid_btf_detect_extend_r_reg[4]_0 )); FDRE #( .INIT(1'b0)) \valid_btf_detect_extend_r_reg[1] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(valid_btf_detect_extend_r[2]), .Q(valid_btf_detect_extend_r[1]), .R(\valid_btf_detect_extend_r_reg[4]_0 )); FDRE #( .INIT(1'b0)) \valid_btf_detect_extend_r_reg[2] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(valid_btf_detect_extend_r[3]), .Q(valid_btf_detect_extend_r[2]), .R(\valid_btf_detect_extend_r_reg[4]_0 )); FDRE #( .INIT(1'b0)) \valid_btf_detect_extend_r_reg[3] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(valid_btf_detect_extend_r[4]), .Q(valid_btf_detect_extend_r[3]), .R(\valid_btf_detect_extend_r_reg[4]_0 )); FDRE #( .INIT(1'b0)) \valid_btf_detect_extend_r_reg[4] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(valid_btf_detect), .Q(valid_btf_detect_extend_r[4]), .R(\valid_btf_detect_extend_r_reg[4]_0 )); (* shift_extract = "{no}" *) FDRE valid_btf_detect_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(valid_btf_detect_c), .Q(valid_btf_detect), .R(1'b0)); LUT1 #( .INIT(2'h1)) \wait_for_rd_en[0]_i_1 (.I0(wait_for_rd_en[0]), .O(\wait_for_rd_en[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair50" *) LUT2 #( .INIT(4'h6)) \wait_for_rd_en[1]_i_1 (.I0(wait_for_rd_en[0]), .I1(wait_for_rd_en[1]), .O(\wait_for_rd_en[1]_i_1_n_0 )); LUT2 #( .INIT(4'h7)) \wait_for_rd_en[2]_i_1 (.I0(wait_for_rd_en[1]), .I1(wait_for_rd_en[2]), .O(\wait_for_rd_en[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair50" *) LUT3 #( .INIT(8'h78)) \wait_for_rd_en[2]_i_2 (.I0(wait_for_rd_en[0]), .I1(wait_for_rd_en[1]), .I2(wait_for_rd_en[2]), .O(\wait_for_rd_en[2]_i_2_n_0 )); FDRE #( .INIT(1'b0)) \wait_for_rd_en_reg[0] (.C(s_level_out_d5_reg), .CE(\wait_for_rd_en[2]_i_1_n_0 ), .D(\wait_for_rd_en[0]_i_1_n_0 ), .Q(wait_for_rd_en[0]), .R(cbcc_fifo_reset_rd_clk)); FDRE #( .INIT(1'b0)) \wait_for_rd_en_reg[1] (.C(s_level_out_d5_reg), .CE(\wait_for_rd_en[2]_i_1_n_0 ), .D(\wait_for_rd_en[1]_i_1_n_0 ), .Q(wait_for_rd_en[1]), .R(cbcc_fifo_reset_rd_clk)); FDRE #( .INIT(1'b0)) \wait_for_rd_en_reg[2] (.C(s_level_out_d5_reg), .CE(\wait_for_rd_en[2]_i_1_n_0 ), .D(\wait_for_rd_en[2]_i_2_n_0 ), .Q(wait_for_rd_en[2]), .R(cbcc_fifo_reset_rd_clk)); (* SOFT_HLUTNM = "soft_lutpair52" *) LUT1 #( .INIT(2'h1)) \wait_for_wr_en[0]_i_1 (.I0(wait_for_wr_en_reg[0]), .O(p_0_in__8[0])); (* SOFT_HLUTNM = "soft_lutpair52" *) LUT2 #( .INIT(4'h6)) \wait_for_wr_en[1]_i_1 (.I0(wait_for_wr_en_reg[0]), .I1(wait_for_wr_en_reg[1]), .O(p_0_in__8[1])); (* SOFT_HLUTNM = "soft_lutpair45" *) LUT3 #( .INIT(8'h78)) \wait_for_wr_en[2]_i_1 (.I0(wait_for_wr_en_reg[0]), .I1(wait_for_wr_en_reg[1]), .I2(wait_for_wr_en_reg[2]), .O(p_0_in__8[2])); (* SOFT_HLUTNM = "soft_lutpair45" *) LUT4 #( .INIT(16'h7F80)) \wait_for_wr_en[3]_i_1 (.I0(wait_for_wr_en_reg[1]), .I1(wait_for_wr_en_reg[0]), .I2(wait_for_wr_en_reg[2]), .I3(wait_for_wr_en_reg[3]), .O(p_0_in__8[3])); (* SOFT_HLUTNM = "soft_lutpair42" *) LUT5 #( .INIT(32'h7FFF8000)) \wait_for_wr_en[4]_i_1 (.I0(wait_for_wr_en_reg[2]), .I1(wait_for_wr_en_reg[0]), .I2(wait_for_wr_en_reg[1]), .I3(wait_for_wr_en_reg[3]), .I4(wait_for_wr_en_reg[4]), .O(p_0_in__8[4])); LUT1 #( .INIT(2'h1)) \wait_for_wr_en[5]_i_1 (.I0(wait_for_wr_en_reg[5]), .O(\wait_for_wr_en[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair42" *) LUT5 #( .INIT(32'h80000000)) \wait_for_wr_en[5]_i_2 (.I0(wait_for_wr_en_reg[3]), .I1(wait_for_wr_en_reg[1]), .I2(wait_for_wr_en_reg[0]), .I3(wait_for_wr_en_reg[2]), .I4(wait_for_wr_en_reg[4]), .O(p_0_in__8[5])); FDRE #( .INIT(1'b0)) \wait_for_wr_en_reg[0] (.C(gtwiz_userclk_rx_usrclk_out), .CE(\wait_for_wr_en[5]_i_1_n_0 ), .D(p_0_in__8[0]), .Q(wait_for_wr_en_reg[0]), .R(SR)); FDRE #( .INIT(1'b0)) \wait_for_wr_en_reg[1] (.C(gtwiz_userclk_rx_usrclk_out), .CE(\wait_for_wr_en[5]_i_1_n_0 ), .D(p_0_in__8[1]), .Q(wait_for_wr_en_reg[1]), .R(SR)); FDRE #( .INIT(1'b0)) \wait_for_wr_en_reg[2] (.C(gtwiz_userclk_rx_usrclk_out), .CE(\wait_for_wr_en[5]_i_1_n_0 ), .D(p_0_in__8[2]), .Q(wait_for_wr_en_reg[2]), .R(SR)); FDRE #( .INIT(1'b0)) \wait_for_wr_en_reg[3] (.C(gtwiz_userclk_rx_usrclk_out), .CE(\wait_for_wr_en[5]_i_1_n_0 ), .D(p_0_in__8[3]), .Q(wait_for_wr_en_reg[3]), .R(SR)); FDRE #( .INIT(1'b0)) \wait_for_wr_en_reg[4] (.C(gtwiz_userclk_rx_usrclk_out), .CE(\wait_for_wr_en[5]_i_1_n_0 ), .D(p_0_in__8[4]), .Q(wait_for_wr_en_reg[4]), .R(SR)); FDRE #( .INIT(1'b0)) \wait_for_wr_en_reg[5] (.C(gtwiz_userclk_rx_usrclk_out), .CE(\wait_for_wr_en[5]_i_1_n_0 ), .D(p_0_in__8[5]), .Q(wait_for_wr_en_reg[5]), .R(SR)); (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wait_for_wr_en_wr3_reg " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wait_for_wr_en_wr3_reg[0]_srl3 " *) SRL16E #( .INIT(16'h0000)) \wait_for_wr_en_wr3_reg[0]_srl3 (.A0(1'b0), .A1(1'b1), .A2(1'b0), .A3(1'b0), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(wait_for_wr_en_reg[0]), .Q(\wait_for_wr_en_wr3_reg[0]_srl3_n_0 )); (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wait_for_wr_en_wr3_reg " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wait_for_wr_en_wr3_reg[1]_srl3 " *) SRL16E #( .INIT(16'h0000)) \wait_for_wr_en_wr3_reg[1]_srl3 (.A0(1'b0), .A1(1'b1), .A2(1'b0), .A3(1'b0), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(wait_for_wr_en_reg[1]), .Q(\wait_for_wr_en_wr3_reg[1]_srl3_n_0 )); (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wait_for_wr_en_wr3_reg " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wait_for_wr_en_wr3_reg[2]_srl3 " *) SRL16E #( .INIT(16'h0000)) \wait_for_wr_en_wr3_reg[2]_srl3 (.A0(1'b0), .A1(1'b1), .A2(1'b0), .A3(1'b0), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(wait_for_wr_en_reg[2]), .Q(\wait_for_wr_en_wr3_reg[2]_srl3_n_0 )); (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wait_for_wr_en_wr3_reg " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wait_for_wr_en_wr3_reg[3]_srl3 " *) SRL16E #( .INIT(16'h0000)) \wait_for_wr_en_wr3_reg[3]_srl3 (.A0(1'b0), .A1(1'b1), .A2(1'b0), .A3(1'b0), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(wait_for_wr_en_reg[3]), .Q(\wait_for_wr_en_wr3_reg[3]_srl3_n_0 )); (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wait_for_wr_en_wr3_reg " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wait_for_wr_en_wr3_reg[4]_srl3 " *) SRL16E #( .INIT(16'h0000)) \wait_for_wr_en_wr3_reg[4]_srl3 (.A0(1'b0), .A1(1'b1), .A2(1'b0), .A3(1'b0), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(wait_for_wr_en_reg[4]), .Q(\wait_for_wr_en_wr3_reg[4]_srl3_n_0 )); (* srl_bus_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wait_for_wr_en_wr3_reg " *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/wait_for_wr_en_wr3_reg[5]_srl3 " *) SRL16E #( .INIT(16'h0000)) \wait_for_wr_en_wr3_reg[5]_srl3 (.A0(1'b0), .A1(1'b1), .A2(1'b0), .A3(1'b0), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(wait_for_wr_en_reg[5]), .Q(\wait_for_wr_en_wr3_reg[5]_srl3_n_0 )); FDRE #( .INIT(1'b0)) \wait_for_wr_en_wr4_reg[0] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\wait_for_wr_en_wr3_reg[0]_srl3_n_0 ), .Q(wait_for_wr_en_wr4[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wait_for_wr_en_wr4_reg[1] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\wait_for_wr_en_wr3_reg[1]_srl3_n_0 ), .Q(wait_for_wr_en_wr4[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wait_for_wr_en_wr4_reg[2] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\wait_for_wr_en_wr3_reg[2]_srl3_n_0 ), .Q(wait_for_wr_en_wr4[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wait_for_wr_en_wr4_reg[3] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\wait_for_wr_en_wr3_reg[3]_srl3_n_0 ), .Q(wait_for_wr_en_wr4[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wait_for_wr_en_wr4_reg[4] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\wait_for_wr_en_wr3_reg[4]_srl3_n_0 ), .Q(wait_for_wr_en_wr4[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \wait_for_wr_en_wr4_reg[5] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\wait_for_wr_en_wr3_reg[5]_srl3_n_0 ), .Q(wait_for_wr_en_wr4[5]), .R(1'b0)); LUT6 #( .INIT(64'hFFF8F8F8F0F0F0F0)) \wdth_conv_1stage[39]_i_1 (.I0(p_0_in0_in), .I1(cb_fifo_din_detect_q), .I2(do_wr_en), .I3(first_cb_to_write_to_fifo_dlyd), .I4(p_1_in), .I5(FINAL_GATER_FOR_FIFO_DIN_reg_0), .O(mod_do_wr_en)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_1stage_reg[0] (.C(gtwiz_userclk_rx_usrclk_out), .CE(mod_do_wr_en), .D(\raw_data_r_r_reg_n_0_[0] ), .Q(wdth_conv_1stage[0]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_1stage_reg[10] (.C(gtwiz_userclk_rx_usrclk_out), .CE(mod_do_wr_en), .D(\raw_data_r_r_reg_n_0_[10] ), .Q(wdth_conv_1stage[10]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_1stage_reg[11] (.C(gtwiz_userclk_rx_usrclk_out), .CE(mod_do_wr_en), .D(\raw_data_r_r_reg_n_0_[11] ), .Q(wdth_conv_1stage[11]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_1stage_reg[12] (.C(gtwiz_userclk_rx_usrclk_out), .CE(mod_do_wr_en), .D(\raw_data_r_r_reg_n_0_[12] ), .Q(wdth_conv_1stage[12]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_1stage_reg[13] (.C(gtwiz_userclk_rx_usrclk_out), .CE(mod_do_wr_en), .D(\raw_data_r_r_reg_n_0_[13] ), .Q(wdth_conv_1stage[13]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_1stage_reg[14] (.C(gtwiz_userclk_rx_usrclk_out), .CE(mod_do_wr_en), .D(\raw_data_r_r_reg_n_0_[14] ), .Q(wdth_conv_1stage[14]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_1stage_reg[15] (.C(gtwiz_userclk_rx_usrclk_out), .CE(mod_do_wr_en), .D(\raw_data_r_r_reg_n_0_[15] ), .Q(wdth_conv_1stage[15]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_1stage_reg[16] (.C(gtwiz_userclk_rx_usrclk_out), .CE(mod_do_wr_en), .D(\raw_data_r_r_reg_n_0_[16] ), .Q(wdth_conv_1stage[16]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_1stage_reg[17] (.C(gtwiz_userclk_rx_usrclk_out), .CE(mod_do_wr_en), .D(\raw_data_r_r_reg_n_0_[17] ), .Q(wdth_conv_1stage[17]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_1stage_reg[18] (.C(gtwiz_userclk_rx_usrclk_out), .CE(mod_do_wr_en), .D(\raw_data_r_r_reg_n_0_[18] ), .Q(wdth_conv_1stage[18]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_1stage_reg[19] (.C(gtwiz_userclk_rx_usrclk_out), .CE(mod_do_wr_en), .D(\raw_data_r_r_reg_n_0_[19] ), .Q(wdth_conv_1stage[19]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_1stage_reg[1] (.C(gtwiz_userclk_rx_usrclk_out), .CE(mod_do_wr_en), .D(\raw_data_r_r_reg_n_0_[1] ), .Q(wdth_conv_1stage[1]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_1stage_reg[20] (.C(gtwiz_userclk_rx_usrclk_out), .CE(mod_do_wr_en), .D(\raw_data_r_r_reg_n_0_[20] ), .Q(wdth_conv_1stage[20]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_1stage_reg[21] (.C(gtwiz_userclk_rx_usrclk_out), .CE(mod_do_wr_en), .D(\raw_data_r_r_reg_n_0_[21] ), .Q(wdth_conv_1stage[21]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_1stage_reg[22] (.C(gtwiz_userclk_rx_usrclk_out), .CE(mod_do_wr_en), .D(\raw_data_r_r_reg_n_0_[22] ), .Q(wdth_conv_1stage[22]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_1stage_reg[23] (.C(gtwiz_userclk_rx_usrclk_out), .CE(mod_do_wr_en), .D(\raw_data_r_r_reg_n_0_[23] ), .Q(wdth_conv_1stage[23]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_1stage_reg[24] (.C(gtwiz_userclk_rx_usrclk_out), .CE(mod_do_wr_en), .D(\raw_data_r_r_reg_n_0_[24] ), .Q(wdth_conv_1stage[24]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_1stage_reg[25] (.C(gtwiz_userclk_rx_usrclk_out), .CE(mod_do_wr_en), .D(\raw_data_r_r_reg_n_0_[25] ), .Q(wdth_conv_1stage[25]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_1stage_reg[26] (.C(gtwiz_userclk_rx_usrclk_out), .CE(mod_do_wr_en), .D(\raw_data_r_r_reg_n_0_[26] ), .Q(wdth_conv_1stage[26]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_1stage_reg[27] (.C(gtwiz_userclk_rx_usrclk_out), .CE(mod_do_wr_en), .D(\raw_data_r_r_reg_n_0_[27] ), .Q(wdth_conv_1stage[27]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_1stage_reg[28] (.C(gtwiz_userclk_rx_usrclk_out), .CE(mod_do_wr_en), .D(\raw_data_r_r_reg_n_0_[28] ), .Q(wdth_conv_1stage[28]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_1stage_reg[29] (.C(gtwiz_userclk_rx_usrclk_out), .CE(mod_do_wr_en), .D(\raw_data_r_r_reg_n_0_[29] ), .Q(wdth_conv_1stage[29]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_1stage_reg[2] (.C(gtwiz_userclk_rx_usrclk_out), .CE(mod_do_wr_en), .D(\raw_data_r_r_reg_n_0_[2] ), .Q(wdth_conv_1stage[2]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_1stage_reg[30] (.C(gtwiz_userclk_rx_usrclk_out), .CE(mod_do_wr_en), .D(\raw_data_r_r_reg_n_0_[30] ), .Q(wdth_conv_1stage[30]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_1stage_reg[31] (.C(gtwiz_userclk_rx_usrclk_out), .CE(mod_do_wr_en), .D(\raw_data_r_r_reg_n_0_[31] ), .Q(wdth_conv_1stage[31]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_1stage_reg[32] (.C(gtwiz_userclk_rx_usrclk_out), .CE(mod_do_wr_en), .D(\raw_data_r_r_reg_n_0_[32] ), .Q(wdth_conv_1stage[32]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_1stage_reg[33] (.C(gtwiz_userclk_rx_usrclk_out), .CE(mod_do_wr_en), .D(\raw_data_r_r_reg_n_0_[33] ), .Q(wdth_conv_1stage[33]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_1stage_reg[34] (.C(gtwiz_userclk_rx_usrclk_out), .CE(mod_do_wr_en), .D(rxdatavalid_lookahead_i), .Q(wdth_conv_1stage[34]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_1stage_reg[35] (.C(gtwiz_userclk_rx_usrclk_out), .CE(mod_do_wr_en), .D(CC_detect_pulse_r), .Q(wdth_conv_1stage[35]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_1stage_reg[36] (.C(gtwiz_userclk_rx_usrclk_out), .CE(mod_do_wr_en), .D(p_0_in0_in), .Q(wdth_conv_1stage[36]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_1stage_reg[37] (.C(gtwiz_userclk_rx_usrclk_out), .CE(mod_do_wr_en), .D(CB_detect_dlyd1), .Q(wdth_conv_1stage[37]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_1stage_reg[38] (.C(gtwiz_userclk_rx_usrclk_out), .CE(mod_do_wr_en), .D(D[0]), .Q(wdth_conv_1stage[38]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_1stage_reg[39] (.C(gtwiz_userclk_rx_usrclk_out), .CE(mod_do_wr_en), .D(D[1]), .Q(wdth_conv_1stage[39]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_1stage_reg[3] (.C(gtwiz_userclk_rx_usrclk_out), .CE(mod_do_wr_en), .D(\raw_data_r_r_reg_n_0_[3] ), .Q(wdth_conv_1stage[3]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_1stage_reg[4] (.C(gtwiz_userclk_rx_usrclk_out), .CE(mod_do_wr_en), .D(\raw_data_r_r_reg_n_0_[4] ), .Q(wdth_conv_1stage[4]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_1stage_reg[5] (.C(gtwiz_userclk_rx_usrclk_out), .CE(mod_do_wr_en), .D(\raw_data_r_r_reg_n_0_[5] ), .Q(wdth_conv_1stage[5]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_1stage_reg[6] (.C(gtwiz_userclk_rx_usrclk_out), .CE(mod_do_wr_en), .D(\raw_data_r_r_reg_n_0_[6] ), .Q(wdth_conv_1stage[6]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_1stage_reg[7] (.C(gtwiz_userclk_rx_usrclk_out), .CE(mod_do_wr_en), .D(\raw_data_r_r_reg_n_0_[7] ), .Q(wdth_conv_1stage[7]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_1stage_reg[8] (.C(gtwiz_userclk_rx_usrclk_out), .CE(mod_do_wr_en), .D(\raw_data_r_r_reg_n_0_[8] ), .Q(wdth_conv_1stage[8]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_1stage_reg[9] (.C(gtwiz_userclk_rx_usrclk_out), .CE(mod_do_wr_en), .D(\raw_data_r_r_reg_n_0_[9] ), .Q(wdth_conv_1stage[9]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_2stage_reg[0] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_1stage[0]), .Q(en32_fifo_din_i[0]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_2stage_reg[10] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_1stage[10]), .Q(en32_fifo_din_i[10]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_2stage_reg[11] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_1stage[11]), .Q(en32_fifo_din_i[11]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_2stage_reg[12] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_1stage[12]), .Q(en32_fifo_din_i[12]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_2stage_reg[13] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_1stage[13]), .Q(en32_fifo_din_i[13]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_2stage_reg[14] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_1stage[14]), .Q(en32_fifo_din_i[14]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_2stage_reg[15] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_1stage[15]), .Q(en32_fifo_din_i[15]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_2stage_reg[16] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_1stage[16]), .Q(en32_fifo_din_i[16]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_2stage_reg[17] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_1stage[17]), .Q(en32_fifo_din_i[17]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_2stage_reg[18] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_1stage[18]), .Q(en32_fifo_din_i[18]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_2stage_reg[19] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_1stage[19]), .Q(en32_fifo_din_i[19]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_2stage_reg[1] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_1stage[1]), .Q(en32_fifo_din_i[1]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_2stage_reg[20] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_1stage[20]), .Q(en32_fifo_din_i[20]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_2stage_reg[21] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_1stage[21]), .Q(en32_fifo_din_i[21]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_2stage_reg[22] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_1stage[22]), .Q(en32_fifo_din_i[22]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_2stage_reg[23] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_1stage[23]), .Q(en32_fifo_din_i[23]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_2stage_reg[24] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_1stage[24]), .Q(en32_fifo_din_i[24]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_2stage_reg[25] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_1stage[25]), .Q(en32_fifo_din_i[25]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_2stage_reg[26] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_1stage[26]), .Q(en32_fifo_din_i[26]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_2stage_reg[27] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_1stage[27]), .Q(en32_fifo_din_i[27]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_2stage_reg[28] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_1stage[28]), .Q(en32_fifo_din_i[28]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_2stage_reg[29] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_1stage[29]), .Q(en32_fifo_din_i[29]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_2stage_reg[2] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_1stage[2]), .Q(en32_fifo_din_i[2]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_2stage_reg[30] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_1stage[30]), .Q(en32_fifo_din_i[30]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_2stage_reg[31] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_1stage[31]), .Q(en32_fifo_din_i[31]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_2stage_reg[32] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_1stage[32]), .Q(wdth_conv_2stage[32]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_2stage_reg[33] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_1stage[33]), .Q(wdth_conv_2stage[33]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_2stage_reg[34] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_1stage[34]), .Q(wdth_conv_2stage[34]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_2stage_reg[35] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_1stage[35]), .Q(wdth_conv_2stage[35]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_2stage_reg[36] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_1stage[36]), .Q(wdth_conv_2stage[36]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_2stage_reg[37] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_1stage[37]), .Q(wdth_conv_2stage[37]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_2stage_reg[38] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_1stage[38]), .Q(wdth_conv_2stage[38]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_2stage_reg[39] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_1stage[39]), .Q(wdth_conv_2stage[39]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_2stage_reg[3] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_1stage[3]), .Q(en32_fifo_din_i[3]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_2stage_reg[4] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_1stage[4]), .Q(en32_fifo_din_i[4]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_2stage_reg[5] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_1stage[5]), .Q(en32_fifo_din_i[5]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_2stage_reg[6] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_1stage[6]), .Q(en32_fifo_din_i[6]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_2stage_reg[7] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_1stage[7]), .Q(en32_fifo_din_i[7]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_2stage_reg[8] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_1stage[8]), .Q(en32_fifo_din_i[8]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_2stage_reg[9] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_1stage[9]), .Q(en32_fifo_din_i[9]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_3stage_reg[0] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(en32_fifo_din_i[0]), .Q(en32_fifo_din_i[40]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_3stage_reg[10] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(en32_fifo_din_i[10]), .Q(en32_fifo_din_i[50]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_3stage_reg[11] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(en32_fifo_din_i[11]), .Q(en32_fifo_din_i[51]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_3stage_reg[12] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(en32_fifo_din_i[12]), .Q(en32_fifo_din_i[52]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_3stage_reg[13] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(en32_fifo_din_i[13]), .Q(en32_fifo_din_i[53]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_3stage_reg[14] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(en32_fifo_din_i[14]), .Q(en32_fifo_din_i[54]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_3stage_reg[15] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(en32_fifo_din_i[15]), .Q(en32_fifo_din_i[55]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_3stage_reg[16] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(en32_fifo_din_i[16]), .Q(en32_fifo_din_i[56]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_3stage_reg[17] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(en32_fifo_din_i[17]), .Q(en32_fifo_din_i[57]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_3stage_reg[18] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(en32_fifo_din_i[18]), .Q(en32_fifo_din_i[58]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_3stage_reg[19] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(en32_fifo_din_i[19]), .Q(en32_fifo_din_i[59]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_3stage_reg[1] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(en32_fifo_din_i[1]), .Q(en32_fifo_din_i[41]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_3stage_reg[20] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(en32_fifo_din_i[20]), .Q(en32_fifo_din_i[60]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_3stage_reg[21] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(en32_fifo_din_i[21]), .Q(en32_fifo_din_i[61]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_3stage_reg[22] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(en32_fifo_din_i[22]), .Q(en32_fifo_din_i[62]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_3stage_reg[23] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(en32_fifo_din_i[23]), .Q(en32_fifo_din_i[63]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_3stage_reg[24] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(en32_fifo_din_i[24]), .Q(en32_fifo_din_i[64]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_3stage_reg[25] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(en32_fifo_din_i[25]), .Q(en32_fifo_din_i[65]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_3stage_reg[26] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(en32_fifo_din_i[26]), .Q(en32_fifo_din_i[66]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_3stage_reg[27] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(en32_fifo_din_i[27]), .Q(en32_fifo_din_i[67]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_3stage_reg[28] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(en32_fifo_din_i[28]), .Q(en32_fifo_din_i[68]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_3stage_reg[29] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(en32_fifo_din_i[29]), .Q(en32_fifo_din_i[69]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_3stage_reg[2] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(en32_fifo_din_i[2]), .Q(en32_fifo_din_i[42]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_3stage_reg[30] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(en32_fifo_din_i[30]), .Q(en32_fifo_din_i[70]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_3stage_reg[31] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(en32_fifo_din_i[31]), .Q(en32_fifo_din_i[71]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_3stage_reg[32] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_2stage[32]), .Q(en32_fifo_din_i[72]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_3stage_reg[33] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_2stage[33]), .Q(en32_fifo_din_i[73]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_3stage_reg[34] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_2stage[34]), .Q(en32_fifo_din_i[74]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_3stage_reg[35] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_2stage[35]), .Q(en32_fifo_din_i[75]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_3stage_reg[36] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_2stage[36]), .Q(en32_fifo_din_i[76]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_3stage_reg[37] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_2stage[37]), .Q(en32_fifo_din_i[77]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_3stage_reg[38] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_2stage[38]), .Q(en32_fifo_din_i[78]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_3stage_reg[39] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(wdth_conv_2stage[39]), .Q(en32_fifo_din_i[79]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_3stage_reg[3] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(en32_fifo_din_i[3]), .Q(en32_fifo_din_i[43]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_3stage_reg[4] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(en32_fifo_din_i[4]), .Q(en32_fifo_din_i[44]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_3stage_reg[5] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(en32_fifo_din_i[5]), .Q(en32_fifo_din_i[45]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_3stage_reg[6] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(en32_fifo_din_i[6]), .Q(en32_fifo_din_i[46]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_3stage_reg[7] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(en32_fifo_din_i[7]), .Q(en32_fifo_din_i[47]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_3stage_reg[8] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(en32_fifo_din_i[8]), .Q(en32_fifo_din_i[48]), .R(SR)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \wdth_conv_3stage_reg[9] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(en32_fifo_din_i[9]), .Q(en32_fifo_din_i[49]), .R(SR)); (* SOFT_HLUTNM = "soft_lutpair48" *) LUT3 #( .INIT(8'h2D)) \wdth_conv_count[0]_i_1 (.I0(bit80_prsnt), .I1(mod_do_wr_en), .I2(\wdth_conv_count_reg_n_0_[0] ), .O(p_2_in[0])); LUT2 #( .INIT(4'hE)) \wdth_conv_count[1]_i_1 (.I0(bit80_prsnt), .I1(mod_do_wr_en), .O(\wdth_conv_count[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair48" *) LUT3 #( .INIT(8'hB0)) \wdth_conv_count[1]_i_2 (.I0(mod_do_wr_en), .I1(bit80_prsnt), .I2(\wdth_conv_count_reg_n_0_[0] ), .O(p_2_in[1])); FDRE #( .INIT(1'b0)) \wdth_conv_count_reg[0] (.C(gtwiz_userclk_rx_usrclk_out), .CE(\wdth_conv_count[1]_i_1_n_0 ), .D(p_2_in[0]), .Q(\wdth_conv_count_reg_n_0_[0] ), .R(any_vld_btf_fifo_din_detect_dlyd_i_1_n_0)); FDRE #( .INIT(1'b0)) \wdth_conv_count_reg[1] (.C(gtwiz_userclk_rx_usrclk_out), .CE(\wdth_conv_count[1]_i_1_n_0 ), .D(p_2_in[1]), .Q(bit80_prsnt), .R(any_vld_btf_fifo_din_detect_dlyd_i_1_n_0)); (* shift_extract = "{no}" *) FDRE wr_err_rd_clk_sync_reg (.C(s_level_out_d5_reg), .CE(1'b1), .D(wr_err_rd_clk_pre), .Q(rxbuferr_out_i[1]), .R(do_rd_en)); (* SOFT_HLUTNM = "soft_lutpair51" *) LUT1 #( .INIT(2'h1)) \wr_monitor_flag[0]_i_1 (.I0(wr_monitor_flag_reg[0]), .O(p_0_in__9[0])); (* SOFT_HLUTNM = "soft_lutpair51" *) LUT2 #( .INIT(4'h6)) \wr_monitor_flag[1]_i_1 (.I0(wr_monitor_flag_reg[0]), .I1(wr_monitor_flag_reg[1]), .O(p_0_in__9[1])); (* SOFT_HLUTNM = "soft_lutpair44" *) LUT3 #( .INIT(8'h78)) \wr_monitor_flag[2]_i_1 (.I0(wr_monitor_flag_reg[0]), .I1(wr_monitor_flag_reg[1]), .I2(wr_monitor_flag_reg[2]), .O(p_0_in__9[2])); (* SOFT_HLUTNM = "soft_lutpair41" *) LUT4 #( .INIT(16'h7F80)) \wr_monitor_flag[3]_i_1 (.I0(wr_monitor_flag_reg[1]), .I1(wr_monitor_flag_reg[0]), .I2(wr_monitor_flag_reg[2]), .I3(wr_monitor_flag_reg[3]), .O(p_0_in__9[3])); LUT6 #( .INIT(64'h0000000000AA2AAA)) \wr_monitor_flag[4]_i_1 (.I0(new_do_wr_en), .I1(wr_monitor_flag_reg[0]), .I2(wr_monitor_flag_reg[1]), .I3(wr_monitor_flag_reg[3]), .I4(wr_monitor_flag_reg[2]), .I5(wr_monitor_flag_reg[4]), .O(wr_monitor_flag)); (* SOFT_HLUTNM = "soft_lutpair44" *) LUT4 #( .INIT(16'h8000)) \wr_monitor_flag[4]_i_2 (.I0(wr_monitor_flag_reg[2]), .I1(wr_monitor_flag_reg[0]), .I2(wr_monitor_flag_reg[1]), .I3(wr_monitor_flag_reg[3]), .O(p_0_in__9[4])); FDRE \wr_monitor_flag_reg[0] (.C(gtwiz_userclk_rx_usrclk_out), .CE(wr_monitor_flag), .D(p_0_in__9[0]), .Q(wr_monitor_flag_reg[0]), .R(\wr_monitor_flag_reg[4]_0 )); FDRE \wr_monitor_flag_reg[1] (.C(gtwiz_userclk_rx_usrclk_out), .CE(wr_monitor_flag), .D(p_0_in__9[1]), .Q(wr_monitor_flag_reg[1]), .R(\wr_monitor_flag_reg[4]_0 )); FDRE \wr_monitor_flag_reg[2] (.C(gtwiz_userclk_rx_usrclk_out), .CE(wr_monitor_flag), .D(p_0_in__9[2]), .Q(wr_monitor_flag_reg[2]), .R(\wr_monitor_flag_reg[4]_0 )); FDRE \wr_monitor_flag_reg[3] (.C(gtwiz_userclk_rx_usrclk_out), .CE(wr_monitor_flag), .D(p_0_in__9[3]), .Q(wr_monitor_flag_reg[3]), .R(\wr_monitor_flag_reg[4]_0 )); FDRE \wr_monitor_flag_reg[4] (.C(gtwiz_userclk_rx_usrclk_out), .CE(wr_monitor_flag), .D(p_0_in__9[4]), .Q(wr_monitor_flag_reg[4]), .R(\wr_monitor_flag_reg[4]_0 )); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_CLOCK_MODULE" *) module aurora_64b66b_0_aurora_64b66b_0_CLOCK_MODULE (CLK, sync_clk_out, mmcm_not_locked_out, mmcm_not_locked_out2, bufg_gt_clr_out, tx_out_clk, lopt, lopt_1, lopt_2); output CLK; output sync_clk_out; output mmcm_not_locked_out; output mmcm_not_locked_out2; input bufg_gt_clr_out; input tx_out_clk; output lopt; input lopt_1; input lopt_2; wire CLK; wire bufg_gt_clr_out; wire lopt; wire lopt_1; wire lopt_2; wire mmcm_not_locked_out; wire mmcm_not_locked_out2; wire sync_clk_out; wire tx_out_clk; aurora_64b66b_0_aurora_64b66b_0_ultrascale_tx_userclk ultrascale_tx_userclk_1 (.bufg_gt_clr_out(bufg_gt_clr_out), .init_clk(CLK), .lopt(lopt), .lopt_1(lopt_1), .lopt_2(lopt_2), .mmcm_not_locked_out(mmcm_not_locked_out), .mmcm_not_locked_out2(mmcm_not_locked_out2), .sync_clk_out(sync_clk_out), .tx_out_clk(tx_out_clk)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_DESCRAMBLER_64B66B" *) module aurora_64b66b_0_aurora_64b66b_0_DESCRAMBLER_64B66B (D, valid_btf_detect_c, Q, CB_detect0, \descrambler_reg[39]_0 , in0, CC_detect_dlyd1, rxdatavalid_to_fifo_i, CB_detect_dlyd0p5, CB_detect_dlyd0p5_reg, E, gtwiz_userclk_rx_usrclk_out, \descrambler_reg[31]_0 , \unscrambled_data_i_reg[13]_0 ); output [1:0]D; output valid_btf_detect_c; output [31:0]Q; output CB_detect0; output [1:0]\descrambler_reg[39]_0 ; input in0; input CC_detect_dlyd1; input rxdatavalid_to_fifo_i; input CB_detect_dlyd0p5; input [1:0]CB_detect_dlyd0p5_reg; input [0:0]E; input gtwiz_userclk_rx_usrclk_out; input [31:0]\descrambler_reg[31]_0 ; input [0:0]\unscrambled_data_i_reg[13]_0 ; wire CB_detect0; wire CB_detect_dlyd0p5; wire [1:0]CB_detect_dlyd0p5_reg; wire CC_detect_dlyd1; wire CC_detect_dlyd1_i_2_n_0; wire CC_detect_dlyd1_i_3_n_0; wire CC_detect_dlyd1_i_4_n_0; wire CC_detect_dlyd1_i_5_n_0; wire CC_detect_pulse_r_i_2_n_0; wire [1:0]D; wire [0:0]E; wire [31:0]Q; wire \descrambler[57]_i_1_n_0 ; wire [31:0]\descrambler_reg[31]_0 ; wire [1:0]\descrambler_reg[39]_0 ; wire \descrambler_reg_n_0_[40] ; wire \descrambler_reg_n_0_[41] ; wire \descrambler_reg_n_0_[42] ; wire \descrambler_reg_n_0_[43] ; wire \descrambler_reg_n_0_[44] ; wire \descrambler_reg_n_0_[45] ; wire \descrambler_reg_n_0_[46] ; wire \descrambler_reg_n_0_[47] ; wire \descrambler_reg_n_0_[48] ; wire \descrambler_reg_n_0_[49] ; wire \descrambler_reg_n_0_[50] ; wire \descrambler_reg_n_0_[51] ; wire \descrambler_reg_n_0_[52] ; wire \descrambler_reg_n_0_[53] ; wire \descrambler_reg_n_0_[54] ; wire \descrambler_reg_n_0_[55] ; wire \descrambler_reg_n_0_[56] ; wire \descrambler_reg_n_0_[57] ; wire gtwiz_userclk_rx_usrclk_out; wire in0; wire p_100_in; wire p_67_in; wire p_69_in; wire p_73_in; wire p_75_in; wire p_78_in; wire p_80_in; wire p_84_in; wire p_86_in; wire p_89_in; wire p_91_in; wire p_95_in; wire p_97_in; wire [57:32]poly; wire rxdatavalid_to_fifo_i; wire [0:17]tempData; wire unscrambled_data_i0; wire unscrambled_data_i012_out; wire unscrambled_data_i016_out; wire unscrambled_data_i020_out; wire unscrambled_data_i024_out; wire unscrambled_data_i028_out; wire unscrambled_data_i032_out; wire unscrambled_data_i036_out; wire unscrambled_data_i040_out; wire unscrambled_data_i044_out; wire unscrambled_data_i048_out; wire unscrambled_data_i04_out; wire unscrambled_data_i08_out; wire [0:0]\unscrambled_data_i_reg[13]_0 ; wire valid_btf_detect_c; wire \wdth_conv_1stage[38]_i_2_n_0 ; LUT6 #( .INIT(64'h0000000000200000)) CB_detect_dlyd0p5_i_1 (.I0(CC_detect_dlyd1_i_2_n_0), .I1(CC_detect_dlyd1_i_4_n_0), .I2(Q[22]), .I3(Q[23]), .I4(rxdatavalid_to_fifo_i), .I5(CC_detect_dlyd1_i_3_n_0), .O(CB_detect0)); LUT6 #( .INIT(64'h0000000000200000)) CC_detect_dlyd1_i_1 (.I0(CC_detect_dlyd1_i_2_n_0), .I1(CC_detect_dlyd1_i_3_n_0), .I2(rxdatavalid_to_fifo_i), .I3(Q[22]), .I4(Q[23]), .I5(CC_detect_dlyd1_i_4_n_0), .O(valid_btf_detect_c)); LUT5 #( .INIT(32'h00000001)) CC_detect_dlyd1_i_2 (.I0(Q[24]), .I1(Q[26]), .I2(Q[16]), .I3(Q[20]), .I4(CC_detect_dlyd1_i_5_n_0), .O(CC_detect_dlyd1_i_2_n_0)); LUT4 #( .INIT(16'hFF7F)) CC_detect_dlyd1_i_3 (.I0(Q[28]), .I1(CB_detect_dlyd0p5_reg[1]), .I2(Q[29]), .I3(CB_detect_dlyd0p5_reg[0]), .O(CC_detect_dlyd1_i_3_n_0)); LUT4 #( .INIT(16'hFFF7)) CC_detect_dlyd1_i_4 (.I0(Q[27]), .I1(Q[30]), .I2(Q[19]), .I3(Q[21]), .O(CC_detect_dlyd1_i_4_n_0)); LUT4 #( .INIT(16'hFFFE)) CC_detect_dlyd1_i_5 (.I0(Q[18]), .I1(Q[25]), .I2(Q[31]), .I3(Q[17]), .O(CC_detect_dlyd1_i_5_n_0)); (* SOFT_HLUTNM = "soft_lutpair58" *) LUT3 #( .INIT(8'h04)) CC_detect_pulse_r_i_1 (.I0(CC_detect_pulse_r_i_2_n_0), .I1(CC_detect_dlyd1_i_2_n_0), .I2(CC_detect_dlyd1), .O(D[1])); (* SOFT_HLUTNM = "soft_lutpair57" *) LUT5 #( .INIT(32'hFFFFFBFF)) CC_detect_pulse_r_i_2 (.I0(CC_detect_dlyd1_i_4_n_0), .I1(Q[23]), .I2(Q[22]), .I3(rxdatavalid_to_fifo_i), .I4(CC_detect_dlyd1_i_3_n_0), .O(CC_detect_pulse_r_i_2_n_0)); LUT1 #( .INIT(2'h1)) \descrambler[57]_i_1 (.I0(in0), .O(\descrambler[57]_i_1_n_0 )); FDSE \descrambler_reg[0] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(\descrambler_reg[31]_0 [0]), .Q(poly[32]), .S(\descrambler[57]_i_1_n_0 )); FDSE \descrambler_reg[10] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(\descrambler_reg[31]_0 [10]), .Q(poly[42]), .S(\descrambler[57]_i_1_n_0 )); FDRE \descrambler_reg[11] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(\descrambler_reg[31]_0 [11]), .Q(poly[43]), .R(\descrambler[57]_i_1_n_0 )); FDSE \descrambler_reg[12] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(\descrambler_reg[31]_0 [12]), .Q(poly[44]), .S(\descrambler[57]_i_1_n_0 )); FDRE \descrambler_reg[13] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(\descrambler_reg[31]_0 [13]), .Q(poly[45]), .R(\descrambler[57]_i_1_n_0 )); FDSE \descrambler_reg[14] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(\descrambler_reg[31]_0 [14]), .Q(poly[46]), .S(\descrambler[57]_i_1_n_0 )); FDRE \descrambler_reg[15] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(\descrambler_reg[31]_0 [15]), .Q(poly[47]), .R(\descrambler[57]_i_1_n_0 )); FDSE \descrambler_reg[16] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(\descrambler_reg[31]_0 [16]), .Q(poly[48]), .S(\descrambler[57]_i_1_n_0 )); FDRE \descrambler_reg[17] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(\descrambler_reg[31]_0 [17]), .Q(poly[49]), .R(\descrambler[57]_i_1_n_0 )); FDSE \descrambler_reg[18] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(\descrambler_reg[31]_0 [18]), .Q(poly[50]), .S(\descrambler[57]_i_1_n_0 )); FDRE \descrambler_reg[19] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(\descrambler_reg[31]_0 [19]), .Q(poly[51]), .R(\descrambler[57]_i_1_n_0 )); FDRE \descrambler_reg[1] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(\descrambler_reg[31]_0 [1]), .Q(poly[33]), .R(\descrambler[57]_i_1_n_0 )); FDSE \descrambler_reg[20] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(\descrambler_reg[31]_0 [20]), .Q(\descrambler_reg[39]_0 [0]), .S(\descrambler[57]_i_1_n_0 )); FDRE \descrambler_reg[21] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(\descrambler_reg[31]_0 [21]), .Q(poly[53]), .R(\descrambler[57]_i_1_n_0 )); FDSE \descrambler_reg[22] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(\descrambler_reg[31]_0 [22]), .Q(poly[54]), .S(\descrambler[57]_i_1_n_0 )); FDRE \descrambler_reg[23] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(\descrambler_reg[31]_0 [23]), .Q(poly[55]), .R(\descrambler[57]_i_1_n_0 )); FDSE \descrambler_reg[24] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(\descrambler_reg[31]_0 [24]), .Q(poly[56]), .S(\descrambler[57]_i_1_n_0 )); FDRE \descrambler_reg[25] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(\descrambler_reg[31]_0 [25]), .Q(poly[57]), .R(\descrambler[57]_i_1_n_0 )); FDSE \descrambler_reg[26] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(\descrambler_reg[31]_0 [26]), .Q(p_67_in), .S(\descrambler[57]_i_1_n_0 )); FDRE \descrambler_reg[27] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(\descrambler_reg[31]_0 [27]), .Q(p_69_in), .R(\descrambler[57]_i_1_n_0 )); FDSE \descrambler_reg[28] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(\descrambler_reg[31]_0 [28]), .Q(p_73_in), .S(\descrambler[57]_i_1_n_0 )); FDRE \descrambler_reg[29] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(\descrambler_reg[31]_0 [29]), .Q(p_75_in), .R(\descrambler[57]_i_1_n_0 )); FDSE \descrambler_reg[2] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(\descrambler_reg[31]_0 [2]), .Q(poly[34]), .S(\descrambler[57]_i_1_n_0 )); FDSE \descrambler_reg[30] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(\descrambler_reg[31]_0 [30]), .Q(p_78_in), .S(\descrambler[57]_i_1_n_0 )); FDRE \descrambler_reg[31] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(\descrambler_reg[31]_0 [31]), .Q(p_80_in), .R(\descrambler[57]_i_1_n_0 )); FDSE \descrambler_reg[32] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(poly[32]), .Q(p_84_in), .S(\descrambler[57]_i_1_n_0 )); FDRE \descrambler_reg[33] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(poly[33]), .Q(p_86_in), .R(\descrambler[57]_i_1_n_0 )); FDSE \descrambler_reg[34] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(poly[34]), .Q(p_89_in), .S(\descrambler[57]_i_1_n_0 )); FDRE \descrambler_reg[35] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(poly[35]), .Q(p_91_in), .R(\descrambler[57]_i_1_n_0 )); FDSE \descrambler_reg[36] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(poly[36]), .Q(p_95_in), .S(\descrambler[57]_i_1_n_0 )); FDRE \descrambler_reg[37] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(poly[37]), .Q(p_97_in), .R(\descrambler[57]_i_1_n_0 )); FDSE \descrambler_reg[38] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(poly[38]), .Q(p_100_in), .S(\descrambler[57]_i_1_n_0 )); FDRE \descrambler_reg[39] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(poly[39]), .Q(\descrambler_reg[39]_0 [1]), .R(\descrambler[57]_i_1_n_0 )); FDRE \descrambler_reg[3] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(\descrambler_reg[31]_0 [3]), .Q(poly[35]), .R(\descrambler[57]_i_1_n_0 )); FDSE \descrambler_reg[40] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(poly[40]), .Q(\descrambler_reg_n_0_[40] ), .S(\descrambler[57]_i_1_n_0 )); FDRE \descrambler_reg[41] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(poly[41]), .Q(\descrambler_reg_n_0_[41] ), .R(\descrambler[57]_i_1_n_0 )); FDSE \descrambler_reg[42] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(poly[42]), .Q(\descrambler_reg_n_0_[42] ), .S(\descrambler[57]_i_1_n_0 )); FDRE \descrambler_reg[43] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(poly[43]), .Q(\descrambler_reg_n_0_[43] ), .R(\descrambler[57]_i_1_n_0 )); FDSE \descrambler_reg[44] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(poly[44]), .Q(\descrambler_reg_n_0_[44] ), .S(\descrambler[57]_i_1_n_0 )); FDRE \descrambler_reg[45] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(poly[45]), .Q(\descrambler_reg_n_0_[45] ), .R(\descrambler[57]_i_1_n_0 )); FDSE \descrambler_reg[46] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(poly[46]), .Q(\descrambler_reg_n_0_[46] ), .S(\descrambler[57]_i_1_n_0 )); FDRE \descrambler_reg[47] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(poly[47]), .Q(\descrambler_reg_n_0_[47] ), .R(\descrambler[57]_i_1_n_0 )); FDSE \descrambler_reg[48] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(poly[48]), .Q(\descrambler_reg_n_0_[48] ), .S(\descrambler[57]_i_1_n_0 )); FDRE \descrambler_reg[49] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(poly[49]), .Q(\descrambler_reg_n_0_[49] ), .R(\descrambler[57]_i_1_n_0 )); FDSE \descrambler_reg[4] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(\descrambler_reg[31]_0 [4]), .Q(poly[36]), .S(\descrambler[57]_i_1_n_0 )); FDSE \descrambler_reg[50] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(poly[50]), .Q(\descrambler_reg_n_0_[50] ), .S(\descrambler[57]_i_1_n_0 )); FDRE \descrambler_reg[51] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(poly[51]), .Q(\descrambler_reg_n_0_[51] ), .R(\descrambler[57]_i_1_n_0 )); FDSE \descrambler_reg[52] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(\descrambler_reg[39]_0 [0]), .Q(\descrambler_reg_n_0_[52] ), .S(\descrambler[57]_i_1_n_0 )); FDRE \descrambler_reg[53] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(poly[53]), .Q(\descrambler_reg_n_0_[53] ), .R(\descrambler[57]_i_1_n_0 )); FDSE \descrambler_reg[54] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(poly[54]), .Q(\descrambler_reg_n_0_[54] ), .S(\descrambler[57]_i_1_n_0 )); FDRE \descrambler_reg[55] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(poly[55]), .Q(\descrambler_reg_n_0_[55] ), .R(\descrambler[57]_i_1_n_0 )); FDSE \descrambler_reg[56] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(poly[56]), .Q(\descrambler_reg_n_0_[56] ), .S(\descrambler[57]_i_1_n_0 )); FDRE \descrambler_reg[57] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(poly[57]), .Q(\descrambler_reg_n_0_[57] ), .R(\descrambler[57]_i_1_n_0 )); FDRE \descrambler_reg[5] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(\descrambler_reg[31]_0 [5]), .Q(poly[37]), .R(\descrambler[57]_i_1_n_0 )); FDSE \descrambler_reg[6] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(\descrambler_reg[31]_0 [6]), .Q(poly[38]), .S(\descrambler[57]_i_1_n_0 )); FDRE \descrambler_reg[7] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(\descrambler_reg[31]_0 [7]), .Q(poly[39]), .R(\descrambler[57]_i_1_n_0 )); FDSE \descrambler_reg[8] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(\descrambler_reg[31]_0 [8]), .Q(poly[40]), .S(\descrambler[57]_i_1_n_0 )); FDRE \descrambler_reg[9] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(\descrambler_reg[31]_0 [9]), .Q(poly[41]), .R(\descrambler[57]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair59" *) LUT3 #( .INIT(8'h96)) \unscrambled_data_i[0]_i_1 (.I0(poly[39]), .I1(\descrambler_reg[31]_0 [0]), .I2(p_67_in), .O(unscrambled_data_i0)); (* SOFT_HLUTNM = "soft_lutpair69" *) LUT3 #( .INIT(8'h96)) \unscrambled_data_i[10]_i_1 (.I0(poly[49]), .I1(\descrambler_reg[31]_0 [10]), .I2(p_95_in), .O(unscrambled_data_i040_out)); (* SOFT_HLUTNM = "soft_lutpair70" *) LUT3 #( .INIT(8'h96)) \unscrambled_data_i[11]_i_1 (.I0(poly[50]), .I1(\descrambler_reg[31]_0 [11]), .I2(p_97_in), .O(unscrambled_data_i044_out)); (* SOFT_HLUTNM = "soft_lutpair71" *) LUT3 #( .INIT(8'h96)) \unscrambled_data_i[12]_i_1 (.I0(poly[51]), .I1(\descrambler_reg[31]_0 [12]), .I2(p_100_in), .O(unscrambled_data_i048_out)); LUT3 #( .INIT(8'h96)) \unscrambled_data_i[14]_i_1 (.I0(poly[53]), .I1(\descrambler_reg[31]_0 [14]), .I2(\descrambler_reg_n_0_[40] ), .O(tempData[17])); LUT3 #( .INIT(8'h96)) \unscrambled_data_i[15]_i_1 (.I0(poly[54]), .I1(\descrambler_reg[31]_0 [15]), .I2(\descrambler_reg_n_0_[41] ), .O(tempData[16])); LUT3 #( .INIT(8'h96)) \unscrambled_data_i[16]_i_1 (.I0(poly[55]), .I1(\descrambler_reg[31]_0 [16]), .I2(\descrambler_reg_n_0_[42] ), .O(tempData[15])); LUT3 #( .INIT(8'h96)) \unscrambled_data_i[17]_i_1 (.I0(poly[56]), .I1(\descrambler_reg[31]_0 [17]), .I2(\descrambler_reg_n_0_[43] ), .O(tempData[14])); LUT3 #( .INIT(8'h96)) \unscrambled_data_i[18]_i_1 (.I0(poly[57]), .I1(\descrambler_reg[31]_0 [18]), .I2(\descrambler_reg_n_0_[44] ), .O(tempData[13])); (* SOFT_HLUTNM = "soft_lutpair59" *) LUT3 #( .INIT(8'h96)) \unscrambled_data_i[19]_i_1 (.I0(p_67_in), .I1(\descrambler_reg[31]_0 [19]), .I2(\descrambler_reg_n_0_[45] ), .O(tempData[12])); (* SOFT_HLUTNM = "soft_lutpair60" *) LUT3 #( .INIT(8'h96)) \unscrambled_data_i[1]_i_1 (.I0(poly[40]), .I1(\descrambler_reg[31]_0 [1]), .I2(p_69_in), .O(unscrambled_data_i04_out)); (* SOFT_HLUTNM = "soft_lutpair60" *) LUT3 #( .INIT(8'h96)) \unscrambled_data_i[20]_i_1 (.I0(p_69_in), .I1(\descrambler_reg[31]_0 [20]), .I2(\descrambler_reg_n_0_[46] ), .O(tempData[11])); (* SOFT_HLUTNM = "soft_lutpair61" *) LUT3 #( .INIT(8'h96)) \unscrambled_data_i[21]_i_1 (.I0(p_73_in), .I1(\descrambler_reg[31]_0 [21]), .I2(\descrambler_reg_n_0_[47] ), .O(tempData[10])); (* SOFT_HLUTNM = "soft_lutpair62" *) LUT3 #( .INIT(8'h96)) \unscrambled_data_i[22]_i_1 (.I0(p_75_in), .I1(\descrambler_reg[31]_0 [22]), .I2(\descrambler_reg_n_0_[48] ), .O(tempData[9])); (* SOFT_HLUTNM = "soft_lutpair63" *) LUT3 #( .INIT(8'h96)) \unscrambled_data_i[23]_i_1 (.I0(p_78_in), .I1(\descrambler_reg[31]_0 [23]), .I2(\descrambler_reg_n_0_[49] ), .O(tempData[8])); (* SOFT_HLUTNM = "soft_lutpair64" *) LUT3 #( .INIT(8'h96)) \unscrambled_data_i[24]_i_1 (.I0(p_80_in), .I1(\descrambler_reg[31]_0 [24]), .I2(\descrambler_reg_n_0_[50] ), .O(tempData[7])); (* SOFT_HLUTNM = "soft_lutpair65" *) LUT3 #( .INIT(8'h96)) \unscrambled_data_i[25]_i_1 (.I0(p_84_in), .I1(\descrambler_reg[31]_0 [25]), .I2(\descrambler_reg_n_0_[51] ), .O(tempData[6])); (* SOFT_HLUTNM = "soft_lutpair66" *) LUT3 #( .INIT(8'h96)) \unscrambled_data_i[26]_i_1 (.I0(p_86_in), .I1(\descrambler_reg[31]_0 [26]), .I2(\descrambler_reg_n_0_[52] ), .O(tempData[5])); (* SOFT_HLUTNM = "soft_lutpair67" *) LUT3 #( .INIT(8'h96)) \unscrambled_data_i[27]_i_1 (.I0(p_89_in), .I1(\descrambler_reg[31]_0 [27]), .I2(\descrambler_reg_n_0_[53] ), .O(tempData[4])); (* SOFT_HLUTNM = "soft_lutpair68" *) LUT3 #( .INIT(8'h96)) \unscrambled_data_i[28]_i_1 (.I0(p_91_in), .I1(\descrambler_reg[31]_0 [28]), .I2(\descrambler_reg_n_0_[54] ), .O(tempData[3])); (* SOFT_HLUTNM = "soft_lutpair69" *) LUT3 #( .INIT(8'h96)) \unscrambled_data_i[29]_i_1 (.I0(p_95_in), .I1(\descrambler_reg[31]_0 [29]), .I2(\descrambler_reg_n_0_[55] ), .O(tempData[2])); (* SOFT_HLUTNM = "soft_lutpair61" *) LUT3 #( .INIT(8'h96)) \unscrambled_data_i[2]_i_1 (.I0(poly[41]), .I1(\descrambler_reg[31]_0 [2]), .I2(p_73_in), .O(unscrambled_data_i08_out)); (* SOFT_HLUTNM = "soft_lutpair70" *) LUT3 #( .INIT(8'h96)) \unscrambled_data_i[30]_i_1 (.I0(p_97_in), .I1(\descrambler_reg[31]_0 [30]), .I2(\descrambler_reg_n_0_[56] ), .O(tempData[1])); (* SOFT_HLUTNM = "soft_lutpair71" *) LUT3 #( .INIT(8'h96)) \unscrambled_data_i[31]_i_1 (.I0(p_100_in), .I1(\descrambler_reg[31]_0 [31]), .I2(\descrambler_reg_n_0_[57] ), .O(tempData[0])); (* SOFT_HLUTNM = "soft_lutpair62" *) LUT3 #( .INIT(8'h96)) \unscrambled_data_i[3]_i_1 (.I0(poly[42]), .I1(\descrambler_reg[31]_0 [3]), .I2(p_75_in), .O(unscrambled_data_i012_out)); (* SOFT_HLUTNM = "soft_lutpair63" *) LUT3 #( .INIT(8'h96)) \unscrambled_data_i[4]_i_1 (.I0(poly[43]), .I1(\descrambler_reg[31]_0 [4]), .I2(p_78_in), .O(unscrambled_data_i016_out)); (* SOFT_HLUTNM = "soft_lutpair64" *) LUT3 #( .INIT(8'h96)) \unscrambled_data_i[5]_i_1 (.I0(poly[44]), .I1(\descrambler_reg[31]_0 [5]), .I2(p_80_in), .O(unscrambled_data_i020_out)); (* SOFT_HLUTNM = "soft_lutpair65" *) LUT3 #( .INIT(8'h96)) \unscrambled_data_i[6]_i_1 (.I0(poly[45]), .I1(\descrambler_reg[31]_0 [6]), .I2(p_84_in), .O(unscrambled_data_i024_out)); (* SOFT_HLUTNM = "soft_lutpair66" *) LUT3 #( .INIT(8'h96)) \unscrambled_data_i[7]_i_1 (.I0(poly[46]), .I1(\descrambler_reg[31]_0 [7]), .I2(p_86_in), .O(unscrambled_data_i028_out)); (* SOFT_HLUTNM = "soft_lutpair67" *) LUT3 #( .INIT(8'h96)) \unscrambled_data_i[8]_i_1 (.I0(poly[47]), .I1(\descrambler_reg[31]_0 [8]), .I2(p_89_in), .O(unscrambled_data_i032_out)); (* SOFT_HLUTNM = "soft_lutpair68" *) LUT3 #( .INIT(8'h96)) \unscrambled_data_i[9]_i_1 (.I0(poly[48]), .I1(\descrambler_reg[31]_0 [9]), .I2(p_91_in), .O(unscrambled_data_i036_out)); FDRE \unscrambled_data_i_reg[0] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(unscrambled_data_i0), .Q(Q[0]), .R(\descrambler[57]_i_1_n_0 )); FDRE \unscrambled_data_i_reg[10] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(unscrambled_data_i040_out), .Q(Q[10]), .R(\descrambler[57]_i_1_n_0 )); FDRE \unscrambled_data_i_reg[11] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(unscrambled_data_i044_out), .Q(Q[11]), .R(\descrambler[57]_i_1_n_0 )); FDRE \unscrambled_data_i_reg[12] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(unscrambled_data_i048_out), .Q(Q[12]), .R(\descrambler[57]_i_1_n_0 )); FDRE \unscrambled_data_i_reg[13] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(\unscrambled_data_i_reg[13]_0 ), .Q(Q[13]), .R(\descrambler[57]_i_1_n_0 )); FDRE \unscrambled_data_i_reg[14] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(tempData[17]), .Q(Q[14]), .R(\descrambler[57]_i_1_n_0 )); FDRE \unscrambled_data_i_reg[15] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(tempData[16]), .Q(Q[15]), .R(\descrambler[57]_i_1_n_0 )); FDRE \unscrambled_data_i_reg[16] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(tempData[15]), .Q(Q[16]), .R(\descrambler[57]_i_1_n_0 )); FDRE \unscrambled_data_i_reg[17] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(tempData[14]), .Q(Q[17]), .R(\descrambler[57]_i_1_n_0 )); FDRE \unscrambled_data_i_reg[18] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(tempData[13]), .Q(Q[18]), .R(\descrambler[57]_i_1_n_0 )); FDRE \unscrambled_data_i_reg[19] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(tempData[12]), .Q(Q[19]), .R(\descrambler[57]_i_1_n_0 )); FDRE \unscrambled_data_i_reg[1] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(unscrambled_data_i04_out), .Q(Q[1]), .R(\descrambler[57]_i_1_n_0 )); FDRE \unscrambled_data_i_reg[20] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(tempData[11]), .Q(Q[20]), .R(\descrambler[57]_i_1_n_0 )); FDRE \unscrambled_data_i_reg[21] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(tempData[10]), .Q(Q[21]), .R(\descrambler[57]_i_1_n_0 )); FDRE \unscrambled_data_i_reg[22] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(tempData[9]), .Q(Q[22]), .R(\descrambler[57]_i_1_n_0 )); FDRE \unscrambled_data_i_reg[23] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(tempData[8]), .Q(Q[23]), .R(\descrambler[57]_i_1_n_0 )); FDRE \unscrambled_data_i_reg[24] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(tempData[7]), .Q(Q[24]), .R(\descrambler[57]_i_1_n_0 )); FDRE \unscrambled_data_i_reg[25] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(tempData[6]), .Q(Q[25]), .R(\descrambler[57]_i_1_n_0 )); FDRE \unscrambled_data_i_reg[26] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(tempData[5]), .Q(Q[26]), .R(\descrambler[57]_i_1_n_0 )); FDRE \unscrambled_data_i_reg[27] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(tempData[4]), .Q(Q[27]), .R(\descrambler[57]_i_1_n_0 )); FDRE \unscrambled_data_i_reg[28] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(tempData[3]), .Q(Q[28]), .R(\descrambler[57]_i_1_n_0 )); FDRE \unscrambled_data_i_reg[29] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(tempData[2]), .Q(Q[29]), .R(\descrambler[57]_i_1_n_0 )); FDRE \unscrambled_data_i_reg[2] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(unscrambled_data_i08_out), .Q(Q[2]), .R(\descrambler[57]_i_1_n_0 )); FDRE \unscrambled_data_i_reg[30] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(tempData[1]), .Q(Q[30]), .R(\descrambler[57]_i_1_n_0 )); FDRE \unscrambled_data_i_reg[31] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(tempData[0]), .Q(Q[31]), .R(\descrambler[57]_i_1_n_0 )); FDRE \unscrambled_data_i_reg[3] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(unscrambled_data_i012_out), .Q(Q[3]), .R(\descrambler[57]_i_1_n_0 )); FDRE \unscrambled_data_i_reg[4] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(unscrambled_data_i016_out), .Q(Q[4]), .R(\descrambler[57]_i_1_n_0 )); FDRE \unscrambled_data_i_reg[5] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(unscrambled_data_i020_out), .Q(Q[5]), .R(\descrambler[57]_i_1_n_0 )); FDRE \unscrambled_data_i_reg[6] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(unscrambled_data_i024_out), .Q(Q[6]), .R(\descrambler[57]_i_1_n_0 )); FDRE \unscrambled_data_i_reg[7] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(unscrambled_data_i028_out), .Q(Q[7]), .R(\descrambler[57]_i_1_n_0 )); FDRE \unscrambled_data_i_reg[8] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(unscrambled_data_i032_out), .Q(Q[8]), .R(\descrambler[57]_i_1_n_0 )); FDRE \unscrambled_data_i_reg[9] (.C(gtwiz_userclk_rx_usrclk_out), .CE(E), .D(unscrambled_data_i036_out), .Q(Q[9]), .R(\descrambler[57]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair58" *) LUT3 #( .INIT(8'hBA)) \wdth_conv_1stage[38]_i_1 (.I0(CB_detect_dlyd0p5), .I1(\wdth_conv_1stage[38]_i_2_n_0 ), .I2(CC_detect_dlyd1_i_2_n_0), .O(D[0])); (* SOFT_HLUTNM = "soft_lutpair57" *) LUT5 #( .INIT(32'hFFFFFBFF)) \wdth_conv_1stage[38]_i_2 (.I0(CC_detect_dlyd1_i_3_n_0), .I1(rxdatavalid_to_fifo_i), .I2(Q[23]), .I3(Q[22]), .I4(CC_detect_dlyd1_i_4_n_0), .O(\wdth_conv_1stage[38]_i_2_n_0 )); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_ERR_DETECT" *) module aurora_64b66b_0_aurora_64b66b_0_ERR_DETECT (hard_err_i, SOFT_ERR_reg_0, SOFT_ERR_reg_1, HARD_ERR_reg_0, HARD_ERR_reg_1, channel_up_tx_if); output hard_err_i; output SOFT_ERR_reg_0; input SOFT_ERR_reg_1; input HARD_ERR_reg_0; input HARD_ERR_reg_1; input channel_up_tx_if; wire HARD_ERR_reg_0; wire HARD_ERR_reg_1; wire SOFT_ERR_reg_0; wire SOFT_ERR_reg_1; wire channel_up_tx_if; wire hard_err_i; wire soft_err_i; FDRE HARD_ERR_reg (.C(HARD_ERR_reg_0), .CE(1'b1), .D(HARD_ERR_reg_1), .Q(hard_err_i), .R(1'b0)); FDRE SOFT_ERR_reg (.C(HARD_ERR_reg_0), .CE(1'b1), .D(SOFT_ERR_reg_1), .Q(soft_err_i), .R(1'b0)); LUT2 #( .INIT(4'h8)) soft_err_i_1 (.I0(soft_err_i), .I1(channel_up_tx_if), .O(SOFT_ERR_reg_0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_GLOBAL_LOGIC" *) module aurora_64b66b_0_aurora_64b66b_0_GLOBAL_LOGIC (SR, gen_na_idles_i, gen_ch_bond_i, CHANNEL_UP_RX_IF_reg, channel_up_tx_if, hard_err, gen_cc_flop_0_i, E, CHANNEL_UP_RX_IF_reg_0, R0, gen_ch_bond_int_reg, CHANNEL_UP_RX_IF_reg_1, reset_lanes_c, CHANNEL_UP_RX_IF_reg_2, wait_for_lane_up_r_reg, remote_ready_i, RX_IDLE, CHANNEL_UP_RX_IF_reg_3, TXDATAVALID_IN, hard_err_i, rst_pma_init_usrclk, gen_cc_i, Q, tx_pe_data_v_i, rx_pe_data_v_i, \TX_DATA_reg[63] ); output [0:0]SR; output gen_na_idles_i; output gen_ch_bond_i; output CHANNEL_UP_RX_IF_reg; output channel_up_tx_if; output hard_err; output [1:0]gen_cc_flop_0_i; output [0:0]E; output CHANNEL_UP_RX_IF_reg_0; output R0; output gen_ch_bond_int_reg; output CHANNEL_UP_RX_IF_reg_1; input reset_lanes_c; input CHANNEL_UP_RX_IF_reg_2; input wait_for_lane_up_r_reg; input remote_ready_i; input RX_IDLE; input [0:0]CHANNEL_UP_RX_IF_reg_3; input TXDATAVALID_IN; input hard_err_i; input rst_pma_init_usrclk; input gen_cc_i; input [1:0]Q; input tx_pe_data_v_i; input rx_pe_data_v_i; input \TX_DATA_reg[63] ; wire CHANNEL_UP_RX_IF_reg; wire CHANNEL_UP_RX_IF_reg_0; wire CHANNEL_UP_RX_IF_reg_1; wire CHANNEL_UP_RX_IF_reg_2; wire [0:0]CHANNEL_UP_RX_IF_reg_3; wire [0:0]E; wire [1:0]Q; wire R0; wire RX_IDLE; wire [0:0]SR; wire TXDATAVALID_IN; wire \TX_DATA_reg[63] ; wire channel_up_tx_if; wire [1:0]gen_cc_flop_0_i; wire gen_cc_i; wire gen_ch_bond_i; wire gen_ch_bond_int_reg; wire gen_na_idles_i; wire hard_err; wire hard_err_i; wire remote_ready_i; wire reset_lanes_c; wire rst_pma_init_usrclk; wire rx_pe_data_v_i; wire tx_pe_data_v_i; wire wait_for_lane_up_r_reg; aurora_64b66b_0_aurora_64b66b_0_CHANNEL_BOND_GEN channel_bond_gen_i (.TXDATAVALID_IN(TXDATAVALID_IN), .data_v_r_reg_0(CHANNEL_UP_RX_IF_reg_2), .\free_count_r_reg[4]_0 (CHANNEL_UP_RX_IF_reg_3), .gen_ch_bond_int_reg_0(gen_ch_bond_i), .gen_ch_bond_int_reg_1(channel_up_tx_if)); aurora_64b66b_0_aurora_64b66b_0_CHANNEL_ERR_DETECT channel_err_detect_i (.CHANNEL_HARD_ERR_reg_0(CHANNEL_UP_RX_IF_reg_2), .hard_err(hard_err), .hard_err_i(hard_err_i)); aurora_64b66b_0_aurora_64b66b_0_CHANNEL_INIT_SM channel_init_sm_i (.CHANNEL_UP_RX_IF_reg_0(CHANNEL_UP_RX_IF_reg), .CHANNEL_UP_RX_IF_reg_1(CHANNEL_UP_RX_IF_reg_0), .CHANNEL_UP_RX_IF_reg_2(CHANNEL_UP_RX_IF_reg_1), .CHANNEL_UP_RX_IF_reg_3(CHANNEL_UP_RX_IF_reg_2), .CHANNEL_UP_RX_IF_reg_4(CHANNEL_UP_RX_IF_reg_3), .CHANNEL_UP_TX_IF_reg_0(channel_up_tx_if), .E(E), .Q(Q), .R0(R0), .RX_IDLE(RX_IDLE), .SR(SR), .\TX_DATA_reg[63] (gen_ch_bond_i), .\TX_DATA_reg[63]_0 (\TX_DATA_reg[63] ), .gen_cc_flop_0_i(gen_cc_flop_0_i), .gen_cc_i(gen_cc_i), .gen_ch_bond_int_reg(gen_ch_bond_int_reg), .remote_ready_i(remote_ready_i), .reset_lanes_c(reset_lanes_c), .rst_pma_init_usrclk(rst_pma_init_usrclk), .rx_pe_data_v_i(rx_pe_data_v_i), .tx_pe_data_v_i(tx_pe_data_v_i), .wait_for_lane_up_r_reg_0(gen_na_idles_i), .wait_for_lane_up_r_reg_1(wait_for_lane_up_r_reg)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_LANE_INIT_SM" *) module aurora_64b66b_0_aurora_64b66b_0_LANE_INIT_SM (lane_up_flop_i_0, rst_r_reg_0, enable_err_detect_i, rx_polarity_r_reg_0, in0, reset_lanes_c, s_level_out_d1_aurora_64b66b_0_cdc_to_reg, s_level_out_d5_reg, SR, reset_count_r0, ready_r_reg0, rx_lossofsync_i, reset_lanes_i, gen_na_idles_i); output lane_up_flop_i_0; output rst_r_reg_0; output enable_err_detect_i; output rx_polarity_r_reg_0; output in0; output reset_lanes_c; input s_level_out_d1_aurora_64b66b_0_cdc_to_reg; input s_level_out_d5_reg; input [0:0]SR; input reset_count_r0; input ready_r_reg0; input rx_lossofsync_i; input reset_lanes_i; input gen_na_idles_i; wire [0:0]SR; wire align_r; wire align_r_i_2_n_0; wire begin_r; wire check_polarity_r_i_1_n_0; wire count_8d_done_r; wire \counter1_r_reg_n_0_[1] ; wire \counter1_r_reg_n_0_[2] ; wire \counter1_r_reg_n_0_[3] ; wire enable_err_detect_i; wire gen_na_idles_i; wire in0; wire lane_up_flop_i_0; wire next_align_c; wire next_begin_c; wire \next_begin_c_inferred__1/i__n_0 ; wire next_polarity_c; wire next_ready_c; wire next_rst_c; wire [3:0]p_0_in; wire polarity_r; wire prev_rx_polarity_r; wire prev_rx_polarity_r_i_1_n_0; wire ready_r; wire ready_r_i_4_n_0; wire ready_r_reg0; wire reset_count_r; wire reset_count_r0; wire reset_lanes_c; wire reset_lanes_i; wire rst_r_i_2_n_0; wire rst_r_reg_0; wire rx_lossofsync_i; wire rx_polarity_dlyd_i; wire rx_polarity_r_reg_0; wire s_level_out_d1_aurora_64b66b_0_cdc_to_reg; wire s_level_out_d5_reg; wire u_cdc_rxlossofsync_in_n_2; wire NLW_SRLC32E_inst_0_Q31_UNCONNECTED; FDRE ENABLE_ERR_DETECT_reg (.C(s_level_out_d5_reg), .CE(1'b1), .D(ready_r), .Q(enable_err_detect_i), .R(1'b0)); (* BOX_TYPE = "PRIMITIVE" *) (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_lane_0_i/lane_init_sm_i/SRLC32E_inst_0 " *) SRLC32E #( .INIT(32'h00000000), .IS_CLK_INVERTED(1'b0)) SRLC32E_inst_0 (.A({1'b0,1'b0,1'b1,1'b0,1'b0}), .CE(1'b1), .CLK(s_level_out_d5_reg), .D(polarity_r), .Q(rx_polarity_dlyd_i), .Q31(NLW_SRLC32E_inst_0_Q31_UNCONNECTED)); LUT6 #( .INIT(64'h00000C0000000A0A)) align_r_i_1 (.I0(align_r_i_2_n_0), .I1(ready_r_i_4_n_0), .I2(ready_r), .I3(rx_lossofsync_i), .I4(polarity_r), .I5(align_r), .O(next_align_c)); (* SOFT_HLUTNM = "soft_lutpair106" *) LUT4 #( .INIT(16'h0040)) align_r_i_2 (.I0(begin_r), .I1(rst_r_reg_0), .I2(count_8d_done_r), .I3(reset_lanes_i), .O(align_r_i_2_n_0)); FDRE align_r_reg (.C(s_level_out_d5_reg), .CE(1'b1), .D(next_align_c), .Q(align_r), .R(ready_r_reg0)); FDSE begin_r_reg (.C(s_level_out_d5_reg), .CE(1'b1), .D(next_begin_c), .Q(begin_r), .S(ready_r_reg0)); LUT3 #( .INIT(8'hBA)) check_polarity_r_i_1 (.I0(polarity_r), .I1(rx_polarity_dlyd_i), .I2(in0), .O(check_polarity_r_i_1_n_0)); FDRE check_polarity_r_reg (.C(s_level_out_d5_reg), .CE(1'b1), .D(check_polarity_r_i_1_n_0), .Q(in0), .R(SR)); (* SOFT_HLUTNM = "soft_lutpair107" *) LUT4 #( .INIT(16'h7F80)) \counter1_r[0]_i_1 (.I0(\counter1_r_reg_n_0_[1] ), .I1(\counter1_r_reg_n_0_[3] ), .I2(\counter1_r_reg_n_0_[2] ), .I3(count_8d_done_r), .O(p_0_in[3])); (* SOFT_HLUTNM = "soft_lutpair107" *) LUT3 #( .INIT(8'h78)) \counter1_r[1]_i_1 (.I0(\counter1_r_reg_n_0_[2] ), .I1(\counter1_r_reg_n_0_[3] ), .I2(\counter1_r_reg_n_0_[1] ), .O(p_0_in[2])); LUT2 #( .INIT(4'h6)) \counter1_r[2]_i_1 (.I0(\counter1_r_reg_n_0_[3] ), .I1(\counter1_r_reg_n_0_[2] ), .O(p_0_in[1])); LUT1 #( .INIT(2'h1)) \counter1_r[3]_i_1 (.I0(\counter1_r_reg_n_0_[3] ), .O(p_0_in[0])); FDRE #( .INIT(1'b0)) \counter1_r_reg[0] (.C(s_level_out_d5_reg), .CE(1'b1), .D(p_0_in[3]), .Q(count_8d_done_r), .R(reset_count_r)); FDRE #( .INIT(1'b0)) \counter1_r_reg[1] (.C(s_level_out_d5_reg), .CE(1'b1), .D(p_0_in[2]), .Q(\counter1_r_reg_n_0_[1] ), .R(reset_count_r)); FDRE #( .INIT(1'b0)) \counter1_r_reg[2] (.C(s_level_out_d5_reg), .CE(1'b1), .D(p_0_in[1]), .Q(\counter1_r_reg_n_0_[2] ), .R(reset_count_r)); FDSE #( .INIT(1'b1)) \counter1_r_reg[3] (.C(s_level_out_d5_reg), .CE(1'b1), .D(p_0_in[0]), .Q(\counter1_r_reg_n_0_[3] ), .S(reset_count_r)); (* BOX_TYPE = "PRIMITIVE" *) (* XILINX_LEGACY_PRIM = "FDR" *) FDRE #( .INIT(1'b0)) lane_up_flop_i (.C(s_level_out_d5_reg), .CE(1'b1), .D(ready_r), .Q(lane_up_flop_i_0), .R(SR)); (* SOFT_HLUTNM = "soft_lutpair105" *) LUT5 #( .INIT(32'h00010116)) \next_begin_c_inferred__1/i_ (.I0(ready_r), .I1(polarity_r), .I2(align_r), .I3(rst_r_reg_0), .I4(begin_r), .O(\next_begin_c_inferred__1/i__n_0 )); LUT6 #( .INIT(64'h0000000C04040000)) polarity_r_i_1 (.I0(rx_polarity_dlyd_i), .I1(ready_r_i_4_n_0), .I2(ready_r), .I3(rx_lossofsync_i), .I4(polarity_r), .I5(align_r), .O(next_polarity_c)); FDRE polarity_r_reg (.C(s_level_out_d5_reg), .CE(1'b1), .D(next_polarity_c), .Q(polarity_r), .R(ready_r_reg0)); LUT5 #( .INIT(32'hFFEF0020)) prev_rx_polarity_r_i_1 (.I0(rx_polarity_r_reg_0), .I1(polarity_r), .I2(rst_r_reg_0), .I3(rx_polarity_dlyd_i), .I4(prev_rx_polarity_r), .O(prev_rx_polarity_r_i_1_n_0)); FDRE #( .INIT(1'b0)) prev_rx_polarity_r_reg (.C(s_level_out_d5_reg), .CE(1'b1), .D(prev_rx_polarity_r_i_1_n_0), .Q(prev_rx_polarity_r), .R(SR)); LUT3 #( .INIT(8'h01)) ready_r_i_4 (.I0(rst_r_reg_0), .I1(reset_lanes_i), .I2(begin_r), .O(ready_r_i_4_n_0)); FDRE ready_r_reg (.C(s_level_out_d5_reg), .CE(1'b1), .D(next_ready_c), .Q(ready_r), .R(ready_r_reg0)); FDRE reset_count_r_reg (.C(s_level_out_d5_reg), .CE(1'b1), .D(reset_count_r0), .Q(reset_count_r), .R(1'b0)); LUT3 #( .INIT(8'hF1)) reset_lanes_flop_0_i_i_1 (.I0(lane_up_flop_i_0), .I1(gen_na_idles_i), .I2(SR), .O(reset_lanes_c)); (* SOFT_HLUTNM = "soft_lutpair106" *) LUT5 #( .INIT(32'h14140414)) rst_r_i_1 (.I0(rst_r_i_2_n_0), .I1(begin_r), .I2(rst_r_reg_0), .I3(count_8d_done_r), .I4(reset_lanes_i), .O(next_rst_c)); (* SOFT_HLUTNM = "soft_lutpair105" *) LUT3 #( .INIT(8'hFE)) rst_r_i_2 (.I0(align_r), .I1(ready_r), .I2(polarity_r), .O(rst_r_i_2_n_0)); FDRE rst_r_reg (.C(s_level_out_d5_reg), .CE(1'b1), .D(next_rst_c), .Q(rst_r_reg_0), .R(ready_r_reg0)); FDRE #( .INIT(1'b0)) rx_polarity_r_reg (.C(s_level_out_d5_reg), .CE(1'b1), .D(u_cdc_rxlossofsync_in_n_2), .Q(rx_polarity_r_reg_0), .R(1'b0)); aurora_64b66b_0_aurora_64b66b_0_cdc_sync u_cdc_rxlossofsync_in (.SR(SR), .SYSTEM_RESET_reg(u_cdc_rxlossofsync_in_n_2), .align_r(align_r), .begin_r_reg(\next_begin_c_inferred__1/i__n_0 ), .next_begin_c(next_begin_c), .next_ready_c(next_ready_c), .polarity_r(polarity_r), .prev_rx_polarity_r(prev_rx_polarity_r), .ready_r(ready_r), .ready_r_reg(ready_r_i_4_n_0), .reset_lanes_i(reset_lanes_i), .rx_lossofsync_i(rx_lossofsync_i), .rx_polarity_dlyd_i(rx_polarity_dlyd_i), .rx_polarity_r_reg(rx_polarity_r_reg_0), .s_level_out_d1_aurora_64b66b_0_cdc_to_reg_0(s_level_out_d1_aurora_64b66b_0_cdc_to_reg), .s_level_out_d5_reg_0(s_level_out_d5_reg)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_MULTI_GT" *) module aurora_64b66b_0_aurora_64b66b_0_MULTI_GT (gtwiz_userclk_rx_usrclk_out, gtwiz_reset_tx_done_out, gtwiz_reset_rx_done_out, D, cplllock_out, gt0_drpdo, gt0_drprdy, txn, txp, gt_powergood, rxbufstatus_out, rxdatavalid_out, init_clk_0, rxheadervalid_out, txbufstatus_out, tx_out_clk, out, E, bufg_gt_clr_out, rst_in_out_reg, rst_in_out_reg_0, SCRAMBLED_DATA_OUT, gt0_drpaddr, init_clk, gt0_drpdi, gt0_drpen, gt0_drpwe, rxn, rxp, refclk1_in, loopback, gt_rxcdrovrden_in, i_in_meta_reg, i_in_meta_reg_0, Q, i_in_meta_reg_1, sync_clk_out, rst_in_out_reg_1, mmcm_not_locked_out2, lopt, lopt_1, lopt_2, lopt_3); output gtwiz_userclk_rx_usrclk_out; output [0:0]gtwiz_reset_tx_done_out; output [0:0]gtwiz_reset_rx_done_out; output [31:0]D; output [0:0]cplllock_out; output [15:0]gt0_drpdo; output gt0_drprdy; output txn; output txp; output [0:0]gt_powergood; output [0:0]rxbufstatus_out; output [0:0]rxdatavalid_out; output [1:0]init_clk_0; output [0:0]rxheadervalid_out; output [0:0]txbufstatus_out; output tx_out_clk; output [0:0]out; output [0:0]E; output bufg_gt_clr_out; input rst_in_out_reg; input rst_in_out_reg_0; input [63:0]SCRAMBLED_DATA_OUT; input [8:0]gt0_drpaddr; input init_clk; input [15:0]gt0_drpdi; input gt0_drpen; input gt0_drpwe; input rxn; input rxp; input refclk1_in; input [2:0]loopback; input gt_rxcdrovrden_in; input [0:0]i_in_meta_reg; input i_in_meta_reg_0; input [1:0]Q; input [6:0]i_in_meta_reg_1; input sync_clk_out; input rst_in_out_reg_1; input mmcm_not_locked_out2; input lopt; input lopt_1; output lopt_2; output lopt_3; wire [31:0]D; wire [0:0]E; wire [1:0]Q; wire [63:0]SCRAMBLED_DATA_OUT; wire aurora_64b66b_0_gt_i_n_87; wire aurora_64b66b_0_gt_i_n_88; wire bufg_gt_clr_out; wire [0:0]cplllock_out; wire \fabric_pcs_rst_extend_cntr[8]_i_2_n_0 ; wire \fabric_pcs_rst_extend_cntr_reg_n_0_[0] ; wire \fabric_pcs_rst_extend_cntr_reg_n_0_[1] ; wire \fabric_pcs_rst_extend_cntr_reg_n_0_[2] ; wire \fabric_pcs_rst_extend_cntr_reg_n_0_[3] ; wire \fabric_pcs_rst_extend_cntr_reg_n_0_[4] ; wire \fabric_pcs_rst_extend_cntr_reg_n_0_[5] ; wire \fabric_pcs_rst_extend_cntr_reg_n_0_[6] ; wire \fabric_pcs_rst_extend_cntr_reg_n_0_[7] ; wire \fabric_pcs_rst_extend_cntr_reg_n_0_[8] ; wire [8:0]gt0_drpaddr; wire [15:0]gt0_drpdi; wire [15:0]gt0_drpdo; wire gt0_drpen; wire gt0_drprdy; wire gt0_drpwe; wire [0:0]gt_powergood; wire gt_rxcdrovrden_in; wire [0:0]gtwiz_reset_rx_done_out; wire [0:0]gtwiz_reset_tx_done_out; wire gtwiz_userclk_rx_active_out; wire gtwiz_userclk_rx_reset_in; wire gtwiz_userclk_rx_reset_in_r; wire gtwiz_userclk_rx_usrclk_out; wire gtwiz_userclk_tx_active_in; wire gtx_rx_pcsreset_comb; wire [0:0]i_in_meta_reg; wire i_in_meta_reg_0; wire [6:0]i_in_meta_reg_1; wire init_clk; wire [1:0]init_clk_0; wire [2:0]loopback; wire \^lopt ; wire \^lopt_1 ; wire \^lopt_2 ; wire \^lopt_3 ; wire lopt_4; wire lopt_5; wire lopt_6; wire mmcm_not_locked_out2; wire [0:0]out; wire [9:0]p_0_in__1; wire [7:0]p_0_in__10; wire [7:0]p_0_in__2; wire refclk1_in; wire rst_in_out_reg; wire rst_in_out_reg_0; wire rst_in_out_reg_1; wire [0:0]rxbufstatus_out; wire [0:0]rxdatavalid_out; wire [0:0]rxheadervalid_out; wire rxn; wire rxp; wire sync_clk_out; wire tx_out_clk; wire [0:0]txbufstatus_out; wire txn; wire txp; wire txpmaresetdone_out; wire ultrascale_rx_userclk_n_1; wire \usrclk_rx_active_in_extend_cntr[7]_i_3_n_0 ; wire \usrclk_rx_active_in_extend_cntr[7]_i_4_n_0 ; wire \usrclk_rx_active_in_extend_cntr_reg_n_0_[0] ; wire \usrclk_rx_active_in_extend_cntr_reg_n_0_[1] ; wire \usrclk_rx_active_in_extend_cntr_reg_n_0_[2] ; wire \usrclk_rx_active_in_extend_cntr_reg_n_0_[3] ; wire \usrclk_rx_active_in_extend_cntr_reg_n_0_[4] ; wire \usrclk_rx_active_in_extend_cntr_reg_n_0_[5] ; wire \usrclk_rx_active_in_extend_cntr_reg_n_0_[6] ; wire \usrclk_tx_active_in_extend_cntr[7]_i_1_n_0 ; wire \usrclk_tx_active_in_extend_cntr[7]_i_3_n_0 ; wire \usrclk_tx_active_in_extend_cntr_reg_n_0_[0] ; wire \usrclk_tx_active_in_extend_cntr_reg_n_0_[1] ; wire \usrclk_tx_active_in_extend_cntr_reg_n_0_[2] ; wire \usrclk_tx_active_in_extend_cntr_reg_n_0_[3] ; wire \usrclk_tx_active_in_extend_cntr_reg_n_0_[4] ; wire \usrclk_tx_active_in_extend_cntr_reg_n_0_[5] ; wire \usrclk_tx_active_in_extend_cntr_reg_n_0_[6] ; wire [16:0]NLW_aurora_64b66b_0_gt_i_dmonitorout_out_UNCONNECTED; wire [0:0]NLW_aurora_64b66b_0_gt_i_eyescandataerror_out_UNCONNECTED; wire [0:0]NLW_aurora_64b66b_0_gt_i_gtwiz_reset_rx_cdr_stable_out_UNCONNECTED; wire [1:0]NLW_aurora_64b66b_0_gt_i_rxbufstatus_out_UNCONNECTED; wire [1:1]NLW_aurora_64b66b_0_gt_i_rxdatavalid_out_UNCONNECTED; wire [5:2]NLW_aurora_64b66b_0_gt_i_rxheader_out_UNCONNECTED; wire [1:1]NLW_aurora_64b66b_0_gt_i_rxheadervalid_out_UNCONNECTED; wire [0:0]NLW_aurora_64b66b_0_gt_i_rxprbserr_out_UNCONNECTED; wire [0:0]NLW_aurora_64b66b_0_gt_i_rxresetdone_out_UNCONNECTED; wire [1:0]NLW_aurora_64b66b_0_gt_i_rxstartofseq_out_UNCONNECTED; wire [0:0]NLW_aurora_64b66b_0_gt_i_txbufstatus_out_UNCONNECTED; wire [0:0]NLW_aurora_64b66b_0_gt_i_txoutclkfabric_out_UNCONNECTED; wire [0:0]NLW_aurora_64b66b_0_gt_i_txoutclkpcs_out_UNCONNECTED; wire [0:0]NLW_aurora_64b66b_0_gt_i_txresetdone_out_UNCONNECTED; assign \^lopt_3 = lopt; assign lopt_2 = lopt_5; assign lopt_3 = lopt_6; assign lopt_4 = lopt_1; (* CHECK_LICENSE_TYPE = "aurora_64b66b_0_gt,aurora_64b66b_0_gt_gtwizard_top,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "aurora_64b66b_0_gt_gtwizard_top,Vivado 2020.2" *) aurora_64b66b_0_aurora_64b66b_0_gt aurora_64b66b_0_gt_i (.cplllock_out(cplllock_out), .dmonitorout_out(NLW_aurora_64b66b_0_gt_i_dmonitorout_out_UNCONNECTED[16:0]), .drpaddr_in(gt0_drpaddr), .drpclk_in(init_clk), .drpdi_in(gt0_drpdi), .drpdo_out(gt0_drpdo), .drpen_in(gt0_drpen), .drprdy_out(gt0_drprdy), .drpwe_in(gt0_drpwe), .eyescandataerror_out(NLW_aurora_64b66b_0_gt_i_eyescandataerror_out_UNCONNECTED[0]), .eyescanreset_in(1'b0), .eyescantrigger_in(1'b0), .gthrxn_in(rxn), .gthrxp_in(rxp), .gthtxn_out(txn), .gthtxp_out(txp), .gtpowergood_out(gt_powergood), .gtrefclk0_in(refclk1_in), .gtwiz_reset_all_in(1'b0), .gtwiz_reset_clk_freerun_in(1'b0), .gtwiz_reset_rx_cdr_stable_out(NLW_aurora_64b66b_0_gt_i_gtwiz_reset_rx_cdr_stable_out_UNCONNECTED[0]), .gtwiz_reset_rx_datapath_in(rst_in_out_reg_0), .gtwiz_reset_rx_done_out(gtwiz_reset_rx_done_out), .gtwiz_reset_rx_pll_and_datapath_in(rst_in_out_reg), .gtwiz_reset_tx_datapath_in(1'b0), .gtwiz_reset_tx_done_out(gtwiz_reset_tx_done_out), .gtwiz_reset_tx_pll_and_datapath_in(1'b0), .gtwiz_userclk_rx_active_in(out), .gtwiz_userclk_tx_active_in(gtwiz_userclk_tx_active_in), .gtwiz_userdata_rx_out(D), .gtwiz_userdata_tx_in(SCRAMBLED_DATA_OUT), .loopback_in(loopback), .lopt(\^lopt ), .lopt_1(gtwiz_userclk_rx_reset_in_r), .lopt_2(\^lopt_1 ), .lopt_3(\^lopt_2 ), .lopt_4(\^lopt_3 ), .lopt_5(lopt_4), .lopt_6(lopt_5), .lopt_7(lopt_6), .pcsrsvdin_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .rxbufreset_in(1'b0), .rxbufstatus_out({rxbufstatus_out,NLW_aurora_64b66b_0_gt_i_rxbufstatus_out_UNCONNECTED[1:0]}), .rxcdrhold_in(1'b0), .rxcdrovrden_in(gt_rxcdrovrden_in), .rxdatavalid_out({NLW_aurora_64b66b_0_gt_i_rxdatavalid_out_UNCONNECTED[1],rxdatavalid_out}), .rxdfelpmreset_in(1'b0), .rxgearboxslip_in(i_in_meta_reg), .rxheader_out({NLW_aurora_64b66b_0_gt_i_rxheader_out_UNCONNECTED[5:2],init_clk_0}), .rxheadervalid_out({NLW_aurora_64b66b_0_gt_i_rxheadervalid_out_UNCONNECTED[1],rxheadervalid_out}), .rxlpmen_in(1'b0), .rxoutclk_out(aurora_64b66b_0_gt_i_n_87), .rxpcsreset_in(1'b0), .rxpmareset_in(1'b0), .rxpmaresetdone_out(aurora_64b66b_0_gt_i_n_88), .rxpolarity_in(i_in_meta_reg_0), .rxprbscntreset_in(1'b0), .rxprbserr_out(NLW_aurora_64b66b_0_gt_i_rxprbserr_out_UNCONNECTED[0]), .rxprbssel_in({1'b0,1'b0,1'b0,1'b0}), .rxresetdone_out(NLW_aurora_64b66b_0_gt_i_rxresetdone_out_UNCONNECTED[0]), .rxstartofseq_out(NLW_aurora_64b66b_0_gt_i_rxstartofseq_out_UNCONNECTED[1:0]), .rxusrclk2_in(ultrascale_rx_userclk_n_1), .rxusrclk_in(gtwiz_userclk_rx_usrclk_out), .txbufstatus_out({txbufstatus_out,NLW_aurora_64b66b_0_gt_i_txbufstatus_out_UNCONNECTED[0]}), .txdiffctrl_in({1'b1,1'b0,1'b0,1'b0}), .txheader_in({1'b0,1'b0,1'b0,1'b0,Q}), .txinhibit_in(1'b0), .txoutclk_out(tx_out_clk), .txoutclkfabric_out(NLW_aurora_64b66b_0_gt_i_txoutclkfabric_out_UNCONNECTED[0]), .txoutclkpcs_out(NLW_aurora_64b66b_0_gt_i_txoutclkpcs_out_UNCONNECTED[0]), .txpcsreset_in(1'b0), .txpmareset_in(1'b0), .txpmaresetdone_out(txpmaresetdone_out), .txpolarity_in(1'b0), .txpostcursor_in({1'b0,1'b0,1'b0,1'b0,1'b0}), .txprbsforceerr_in(1'b0), .txprbssel_in({1'b0,1'b0,1'b0,1'b0}), .txprecursor_in({1'b0,1'b0,1'b0,1'b0,1'b0}), .txresetdone_out(NLW_aurora_64b66b_0_gt_i_txresetdone_out_UNCONNECTED[0]), .txsequence_in(i_in_meta_reg_1), .txusrclk2_in(rst_in_out_reg_1), .txusrclk_in(sync_clk_out)); LUT1 #( .INIT(2'h1)) \fabric_pcs_rst_extend_cntr[0]_i_1 (.I0(\fabric_pcs_rst_extend_cntr_reg_n_0_[0] ), .O(p_0_in__1[0])); (* SOFT_HLUTNM = "soft_lutpair30" *) LUT2 #( .INIT(4'h6)) \fabric_pcs_rst_extend_cntr[1]_i_1 (.I0(\fabric_pcs_rst_extend_cntr_reg_n_0_[0] ), .I1(\fabric_pcs_rst_extend_cntr_reg_n_0_[1] ), .O(p_0_in__1[1])); (* SOFT_HLUTNM = "soft_lutpair30" *) LUT3 #( .INIT(8'h78)) \fabric_pcs_rst_extend_cntr[2]_i_1 (.I0(\fabric_pcs_rst_extend_cntr_reg_n_0_[1] ), .I1(\fabric_pcs_rst_extend_cntr_reg_n_0_[0] ), .I2(\fabric_pcs_rst_extend_cntr_reg_n_0_[2] ), .O(p_0_in__1[2])); (* SOFT_HLUTNM = "soft_lutpair26" *) LUT4 #( .INIT(16'h7F80)) \fabric_pcs_rst_extend_cntr[3]_i_1 (.I0(\fabric_pcs_rst_extend_cntr_reg_n_0_[2] ), .I1(\fabric_pcs_rst_extend_cntr_reg_n_0_[0] ), .I2(\fabric_pcs_rst_extend_cntr_reg_n_0_[1] ), .I3(\fabric_pcs_rst_extend_cntr_reg_n_0_[3] ), .O(p_0_in__1[3])); (* SOFT_HLUTNM = "soft_lutpair26" *) LUT5 #( .INIT(32'h7FFF8000)) \fabric_pcs_rst_extend_cntr[4]_i_1 (.I0(\fabric_pcs_rst_extend_cntr_reg_n_0_[3] ), .I1(\fabric_pcs_rst_extend_cntr_reg_n_0_[1] ), .I2(\fabric_pcs_rst_extend_cntr_reg_n_0_[0] ), .I3(\fabric_pcs_rst_extend_cntr_reg_n_0_[2] ), .I4(\fabric_pcs_rst_extend_cntr_reg_n_0_[4] ), .O(p_0_in__1[4])); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \fabric_pcs_rst_extend_cntr[5]_i_1 (.I0(\fabric_pcs_rst_extend_cntr_reg_n_0_[4] ), .I1(\fabric_pcs_rst_extend_cntr_reg_n_0_[2] ), .I2(\fabric_pcs_rst_extend_cntr_reg_n_0_[0] ), .I3(\fabric_pcs_rst_extend_cntr_reg_n_0_[1] ), .I4(\fabric_pcs_rst_extend_cntr_reg_n_0_[3] ), .I5(\fabric_pcs_rst_extend_cntr_reg_n_0_[5] ), .O(p_0_in__1[5])); LUT2 #( .INIT(4'h9)) \fabric_pcs_rst_extend_cntr[6]_i_1 (.I0(\fabric_pcs_rst_extend_cntr[8]_i_2_n_0 ), .I1(\fabric_pcs_rst_extend_cntr_reg_n_0_[6] ), .O(p_0_in__1[6])); (* SOFT_HLUTNM = "soft_lutpair28" *) LUT3 #( .INIT(8'hD2)) \fabric_pcs_rst_extend_cntr[7]_i_1 (.I0(\fabric_pcs_rst_extend_cntr_reg_n_0_[6] ), .I1(\fabric_pcs_rst_extend_cntr[8]_i_2_n_0 ), .I2(\fabric_pcs_rst_extend_cntr_reg_n_0_[7] ), .O(p_0_in__1[7])); (* SOFT_HLUTNM = "soft_lutpair28" *) LUT4 #( .INIT(16'hDF20)) \fabric_pcs_rst_extend_cntr[8]_i_1 (.I0(\fabric_pcs_rst_extend_cntr_reg_n_0_[7] ), .I1(\fabric_pcs_rst_extend_cntr[8]_i_2_n_0 ), .I2(\fabric_pcs_rst_extend_cntr_reg_n_0_[6] ), .I3(\fabric_pcs_rst_extend_cntr_reg_n_0_[8] ), .O(p_0_in__1[8])); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) \fabric_pcs_rst_extend_cntr[8]_i_2 (.I0(\fabric_pcs_rst_extend_cntr_reg_n_0_[4] ), .I1(\fabric_pcs_rst_extend_cntr_reg_n_0_[2] ), .I2(\fabric_pcs_rst_extend_cntr_reg_n_0_[0] ), .I3(\fabric_pcs_rst_extend_cntr_reg_n_0_[1] ), .I4(\fabric_pcs_rst_extend_cntr_reg_n_0_[3] ), .I5(\fabric_pcs_rst_extend_cntr_reg_n_0_[5] ), .O(\fabric_pcs_rst_extend_cntr[8]_i_2_n_0 )); LUT4 #( .INIT(16'hF7FF)) \fabric_pcs_rst_extend_cntr[9]_inv_i_1 (.I0(\fabric_pcs_rst_extend_cntr_reg_n_0_[8] ), .I1(\fabric_pcs_rst_extend_cntr_reg_n_0_[6] ), .I2(\fabric_pcs_rst_extend_cntr[8]_i_2_n_0 ), .I3(\fabric_pcs_rst_extend_cntr_reg_n_0_[7] ), .O(p_0_in__1[9])); FDCE #( .INIT(1'b0)) \fabric_pcs_rst_extend_cntr_reg[0] (.C(rst_in_out_reg_1), .CE(E), .CLR(mmcm_not_locked_out2), .D(p_0_in__1[0]), .Q(\fabric_pcs_rst_extend_cntr_reg_n_0_[0] )); FDCE #( .INIT(1'b0)) \fabric_pcs_rst_extend_cntr_reg[1] (.C(rst_in_out_reg_1), .CE(E), .CLR(mmcm_not_locked_out2), .D(p_0_in__1[1]), .Q(\fabric_pcs_rst_extend_cntr_reg_n_0_[1] )); FDCE #( .INIT(1'b0)) \fabric_pcs_rst_extend_cntr_reg[2] (.C(rst_in_out_reg_1), .CE(E), .CLR(mmcm_not_locked_out2), .D(p_0_in__1[2]), .Q(\fabric_pcs_rst_extend_cntr_reg_n_0_[2] )); FDCE #( .INIT(1'b0)) \fabric_pcs_rst_extend_cntr_reg[3] (.C(rst_in_out_reg_1), .CE(E), .CLR(mmcm_not_locked_out2), .D(p_0_in__1[3]), .Q(\fabric_pcs_rst_extend_cntr_reg_n_0_[3] )); FDCE #( .INIT(1'b0)) \fabric_pcs_rst_extend_cntr_reg[4] (.C(rst_in_out_reg_1), .CE(E), .CLR(mmcm_not_locked_out2), .D(p_0_in__1[4]), .Q(\fabric_pcs_rst_extend_cntr_reg_n_0_[4] )); FDCE #( .INIT(1'b0)) \fabric_pcs_rst_extend_cntr_reg[5] (.C(rst_in_out_reg_1), .CE(E), .CLR(mmcm_not_locked_out2), .D(p_0_in__1[5]), .Q(\fabric_pcs_rst_extend_cntr_reg_n_0_[5] )); FDCE #( .INIT(1'b0)) \fabric_pcs_rst_extend_cntr_reg[6] (.C(rst_in_out_reg_1), .CE(E), .CLR(mmcm_not_locked_out2), .D(p_0_in__1[6]), .Q(\fabric_pcs_rst_extend_cntr_reg_n_0_[6] )); FDCE #( .INIT(1'b0)) \fabric_pcs_rst_extend_cntr_reg[7] (.C(rst_in_out_reg_1), .CE(E), .CLR(mmcm_not_locked_out2), .D(p_0_in__1[7]), .Q(\fabric_pcs_rst_extend_cntr_reg_n_0_[7] )); FDCE #( .INIT(1'b0)) \fabric_pcs_rst_extend_cntr_reg[8] (.C(rst_in_out_reg_1), .CE(E), .CLR(mmcm_not_locked_out2), .D(p_0_in__1[8]), .Q(\fabric_pcs_rst_extend_cntr_reg_n_0_[8] )); (* inverted = "yes" *) FDPE #( .INIT(1'b1)) \fabric_pcs_rst_extend_cntr_reg[9]_inv (.C(rst_in_out_reg_1), .CE(E), .D(p_0_in__1[9]), .PRE(mmcm_not_locked_out2), .Q(E)); LUT1 #( .INIT(2'h1)) \gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst_i_1 (.I0(txpmaresetdone_out), .O(bufg_gt_clr_out)); LUT1 #( .INIT(2'h1)) gtwiz_userclk_rx_reset_in_r_i_1 (.I0(aurora_64b66b_0_gt_i_n_88), .O(gtwiz_userclk_rx_reset_in)); FDRE #( .INIT(1'b0)) gtwiz_userclk_rx_reset_in_r_reg (.C(init_clk), .CE(1'b1), .D(gtwiz_userclk_rx_reset_in), .Q(gtwiz_userclk_rx_reset_in_r), .R(1'b0)); (* DowngradeIPIdentifiedWarnings = "yes" *) (* KEEP_HIERARCHY = "soft" *) (* P_CONTENTS = "0" *) (* P_FREQ_RATIO_SOURCE_TO_USRCLK = "1" *) (* P_FREQ_RATIO_USRCLK_TO_USRCLK2 = "1" *) (* P_USRCLK2_DIV = "3'b000" *) (* P_USRCLK2_INT_DIV = "0" *) (* P_USRCLK_DIV = "3'b000" *) (* P_USRCLK_INT_DIV = "0" *) aurora_64b66b_0_aurora_64b66b_0_ultrascale_rx_userclk ultrascale_rx_userclk (.gtwiz_reset_clk_freerun_in(1'b0), .gtwiz_userclk_rx_active_out(gtwiz_userclk_rx_active_out), .gtwiz_userclk_rx_reset_in(gtwiz_userclk_rx_reset_in_r), .gtwiz_userclk_rx_srcclk_in(aurora_64b66b_0_gt_i_n_87), .gtwiz_userclk_rx_usrclk2_out(ultrascale_rx_userclk_n_1), .gtwiz_userclk_rx_usrclk_out(gtwiz_userclk_rx_usrclk_out), .lopt(\^lopt ), .lopt_1(\^lopt_1 ), .lopt_2(\^lopt_2 )); LUT1 #( .INIT(2'h1)) \usrclk_rx_active_in_extend_cntr[0]_i_1 (.I0(\usrclk_rx_active_in_extend_cntr_reg_n_0_[0] ), .O(p_0_in__10[0])); (* SOFT_HLUTNM = "soft_lutpair29" *) LUT2 #( .INIT(4'h6)) \usrclk_rx_active_in_extend_cntr[1]_i_1 (.I0(\usrclk_rx_active_in_extend_cntr_reg_n_0_[0] ), .I1(\usrclk_rx_active_in_extend_cntr_reg_n_0_[1] ), .O(p_0_in__10[1])); (* SOFT_HLUTNM = "soft_lutpair29" *) LUT3 #( .INIT(8'h78)) \usrclk_rx_active_in_extend_cntr[2]_i_1 (.I0(\usrclk_rx_active_in_extend_cntr_reg_n_0_[0] ), .I1(\usrclk_rx_active_in_extend_cntr_reg_n_0_[1] ), .I2(\usrclk_rx_active_in_extend_cntr_reg_n_0_[2] ), .O(p_0_in__10[2])); (* SOFT_HLUTNM = "soft_lutpair25" *) LUT4 #( .INIT(16'h7F80)) \usrclk_rx_active_in_extend_cntr[3]_i_1 (.I0(\usrclk_rx_active_in_extend_cntr_reg_n_0_[1] ), .I1(\usrclk_rx_active_in_extend_cntr_reg_n_0_[0] ), .I2(\usrclk_rx_active_in_extend_cntr_reg_n_0_[2] ), .I3(\usrclk_rx_active_in_extend_cntr_reg_n_0_[3] ), .O(p_0_in__10[3])); (* SOFT_HLUTNM = "soft_lutpair25" *) LUT5 #( .INIT(32'h7FFF8000)) \usrclk_rx_active_in_extend_cntr[4]_i_1 (.I0(\usrclk_rx_active_in_extend_cntr_reg_n_0_[2] ), .I1(\usrclk_rx_active_in_extend_cntr_reg_n_0_[0] ), .I2(\usrclk_rx_active_in_extend_cntr_reg_n_0_[1] ), .I3(\usrclk_rx_active_in_extend_cntr_reg_n_0_[3] ), .I4(\usrclk_rx_active_in_extend_cntr_reg_n_0_[4] ), .O(p_0_in__10[4])); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \usrclk_rx_active_in_extend_cntr[5]_i_1 (.I0(\usrclk_rx_active_in_extend_cntr_reg_n_0_[3] ), .I1(\usrclk_rx_active_in_extend_cntr_reg_n_0_[1] ), .I2(\usrclk_rx_active_in_extend_cntr_reg_n_0_[0] ), .I3(\usrclk_rx_active_in_extend_cntr_reg_n_0_[2] ), .I4(\usrclk_rx_active_in_extend_cntr_reg_n_0_[4] ), .I5(\usrclk_rx_active_in_extend_cntr_reg_n_0_[5] ), .O(p_0_in__10[5])); (* SOFT_HLUTNM = "soft_lutpair32" *) LUT2 #( .INIT(4'h6)) \usrclk_rx_active_in_extend_cntr[6]_i_1 (.I0(\usrclk_rx_active_in_extend_cntr[7]_i_4_n_0 ), .I1(\usrclk_rx_active_in_extend_cntr_reg_n_0_[6] ), .O(p_0_in__10[6])); LUT1 #( .INIT(2'h1)) \usrclk_rx_active_in_extend_cntr[7]_i_1 (.I0(out), .O(gtx_rx_pcsreset_comb)); (* SOFT_HLUTNM = "soft_lutpair32" *) LUT2 #( .INIT(4'h8)) \usrclk_rx_active_in_extend_cntr[7]_i_2 (.I0(\usrclk_rx_active_in_extend_cntr[7]_i_4_n_0 ), .I1(\usrclk_rx_active_in_extend_cntr_reg_n_0_[6] ), .O(p_0_in__10[7])); LUT1 #( .INIT(2'h1)) \usrclk_rx_active_in_extend_cntr[7]_i_3 (.I0(gtwiz_userclk_rx_active_out), .O(\usrclk_rx_active_in_extend_cntr[7]_i_3_n_0 )); LUT6 #( .INIT(64'h8000000000000000)) \usrclk_rx_active_in_extend_cntr[7]_i_4 (.I0(\usrclk_rx_active_in_extend_cntr_reg_n_0_[5] ), .I1(\usrclk_rx_active_in_extend_cntr_reg_n_0_[3] ), .I2(\usrclk_rx_active_in_extend_cntr_reg_n_0_[1] ), .I3(\usrclk_rx_active_in_extend_cntr_reg_n_0_[0] ), .I4(\usrclk_rx_active_in_extend_cntr_reg_n_0_[2] ), .I5(\usrclk_rx_active_in_extend_cntr_reg_n_0_[4] ), .O(\usrclk_rx_active_in_extend_cntr[7]_i_4_n_0 )); FDCE #( .INIT(1'b0)) \usrclk_rx_active_in_extend_cntr_reg[0] (.C(ultrascale_rx_userclk_n_1), .CE(gtx_rx_pcsreset_comb), .CLR(\usrclk_rx_active_in_extend_cntr[7]_i_3_n_0 ), .D(p_0_in__10[0]), .Q(\usrclk_rx_active_in_extend_cntr_reg_n_0_[0] )); FDCE #( .INIT(1'b0)) \usrclk_rx_active_in_extend_cntr_reg[1] (.C(ultrascale_rx_userclk_n_1), .CE(gtx_rx_pcsreset_comb), .CLR(\usrclk_rx_active_in_extend_cntr[7]_i_3_n_0 ), .D(p_0_in__10[1]), .Q(\usrclk_rx_active_in_extend_cntr_reg_n_0_[1] )); FDCE #( .INIT(1'b0)) \usrclk_rx_active_in_extend_cntr_reg[2] (.C(ultrascale_rx_userclk_n_1), .CE(gtx_rx_pcsreset_comb), .CLR(\usrclk_rx_active_in_extend_cntr[7]_i_3_n_0 ), .D(p_0_in__10[2]), .Q(\usrclk_rx_active_in_extend_cntr_reg_n_0_[2] )); FDCE #( .INIT(1'b0)) \usrclk_rx_active_in_extend_cntr_reg[3] (.C(ultrascale_rx_userclk_n_1), .CE(gtx_rx_pcsreset_comb), .CLR(\usrclk_rx_active_in_extend_cntr[7]_i_3_n_0 ), .D(p_0_in__10[3]), .Q(\usrclk_rx_active_in_extend_cntr_reg_n_0_[3] )); FDCE #( .INIT(1'b0)) \usrclk_rx_active_in_extend_cntr_reg[4] (.C(ultrascale_rx_userclk_n_1), .CE(gtx_rx_pcsreset_comb), .CLR(\usrclk_rx_active_in_extend_cntr[7]_i_3_n_0 ), .D(p_0_in__10[4]), .Q(\usrclk_rx_active_in_extend_cntr_reg_n_0_[4] )); FDCE #( .INIT(1'b0)) \usrclk_rx_active_in_extend_cntr_reg[5] (.C(ultrascale_rx_userclk_n_1), .CE(gtx_rx_pcsreset_comb), .CLR(\usrclk_rx_active_in_extend_cntr[7]_i_3_n_0 ), .D(p_0_in__10[5]), .Q(\usrclk_rx_active_in_extend_cntr_reg_n_0_[5] )); FDCE #( .INIT(1'b0)) \usrclk_rx_active_in_extend_cntr_reg[6] (.C(ultrascale_rx_userclk_n_1), .CE(gtx_rx_pcsreset_comb), .CLR(\usrclk_rx_active_in_extend_cntr[7]_i_3_n_0 ), .D(p_0_in__10[6]), .Q(\usrclk_rx_active_in_extend_cntr_reg_n_0_[6] )); FDCE #( .INIT(1'b0)) \usrclk_rx_active_in_extend_cntr_reg[7] (.C(ultrascale_rx_userclk_n_1), .CE(gtx_rx_pcsreset_comb), .CLR(\usrclk_rx_active_in_extend_cntr[7]_i_3_n_0 ), .D(p_0_in__10[7]), .Q(out)); LUT1 #( .INIT(2'h1)) \usrclk_tx_active_in_extend_cntr[0]_i_1 (.I0(\usrclk_tx_active_in_extend_cntr_reg_n_0_[0] ), .O(p_0_in__2[0])); (* SOFT_HLUTNM = "soft_lutpair31" *) LUT2 #( .INIT(4'h6)) \usrclk_tx_active_in_extend_cntr[1]_i_1 (.I0(\usrclk_tx_active_in_extend_cntr_reg_n_0_[0] ), .I1(\usrclk_tx_active_in_extend_cntr_reg_n_0_[1] ), .O(p_0_in__2[1])); (* SOFT_HLUTNM = "soft_lutpair31" *) LUT3 #( .INIT(8'h78)) \usrclk_tx_active_in_extend_cntr[2]_i_1 (.I0(\usrclk_tx_active_in_extend_cntr_reg_n_0_[1] ), .I1(\usrclk_tx_active_in_extend_cntr_reg_n_0_[0] ), .I2(\usrclk_tx_active_in_extend_cntr_reg_n_0_[2] ), .O(p_0_in__2[2])); (* SOFT_HLUTNM = "soft_lutpair27" *) LUT4 #( .INIT(16'h7F80)) \usrclk_tx_active_in_extend_cntr[3]_i_1 (.I0(\usrclk_tx_active_in_extend_cntr_reg_n_0_[2] ), .I1(\usrclk_tx_active_in_extend_cntr_reg_n_0_[0] ), .I2(\usrclk_tx_active_in_extend_cntr_reg_n_0_[1] ), .I3(\usrclk_tx_active_in_extend_cntr_reg_n_0_[3] ), .O(p_0_in__2[3])); (* SOFT_HLUTNM = "soft_lutpair27" *) LUT5 #( .INIT(32'h7FFF8000)) \usrclk_tx_active_in_extend_cntr[4]_i_1 (.I0(\usrclk_tx_active_in_extend_cntr_reg_n_0_[3] ), .I1(\usrclk_tx_active_in_extend_cntr_reg_n_0_[1] ), .I2(\usrclk_tx_active_in_extend_cntr_reg_n_0_[0] ), .I3(\usrclk_tx_active_in_extend_cntr_reg_n_0_[2] ), .I4(\usrclk_tx_active_in_extend_cntr_reg_n_0_[4] ), .O(p_0_in__2[4])); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \usrclk_tx_active_in_extend_cntr[5]_i_1 (.I0(\usrclk_tx_active_in_extend_cntr_reg_n_0_[4] ), .I1(\usrclk_tx_active_in_extend_cntr_reg_n_0_[2] ), .I2(\usrclk_tx_active_in_extend_cntr_reg_n_0_[0] ), .I3(\usrclk_tx_active_in_extend_cntr_reg_n_0_[1] ), .I4(\usrclk_tx_active_in_extend_cntr_reg_n_0_[3] ), .I5(\usrclk_tx_active_in_extend_cntr_reg_n_0_[5] ), .O(p_0_in__2[5])); (* SOFT_HLUTNM = "soft_lutpair33" *) LUT2 #( .INIT(4'h9)) \usrclk_tx_active_in_extend_cntr[6]_i_1 (.I0(\usrclk_tx_active_in_extend_cntr[7]_i_3_n_0 ), .I1(\usrclk_tx_active_in_extend_cntr_reg_n_0_[6] ), .O(p_0_in__2[6])); LUT2 #( .INIT(4'h1)) \usrclk_tx_active_in_extend_cntr[7]_i_1 (.I0(E), .I1(gtwiz_userclk_tx_active_in), .O(\usrclk_tx_active_in_extend_cntr[7]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair33" *) LUT2 #( .INIT(4'h2)) \usrclk_tx_active_in_extend_cntr[7]_i_2 (.I0(\usrclk_tx_active_in_extend_cntr_reg_n_0_[6] ), .I1(\usrclk_tx_active_in_extend_cntr[7]_i_3_n_0 ), .O(p_0_in__2[7])); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) \usrclk_tx_active_in_extend_cntr[7]_i_3 (.I0(\usrclk_tx_active_in_extend_cntr_reg_n_0_[4] ), .I1(\usrclk_tx_active_in_extend_cntr_reg_n_0_[2] ), .I2(\usrclk_tx_active_in_extend_cntr_reg_n_0_[0] ), .I3(\usrclk_tx_active_in_extend_cntr_reg_n_0_[1] ), .I4(\usrclk_tx_active_in_extend_cntr_reg_n_0_[3] ), .I5(\usrclk_tx_active_in_extend_cntr_reg_n_0_[5] ), .O(\usrclk_tx_active_in_extend_cntr[7]_i_3_n_0 )); FDCE #( .INIT(1'b0)) \usrclk_tx_active_in_extend_cntr_reg[0] (.C(rst_in_out_reg_1), .CE(\usrclk_tx_active_in_extend_cntr[7]_i_1_n_0 ), .CLR(mmcm_not_locked_out2), .D(p_0_in__2[0]), .Q(\usrclk_tx_active_in_extend_cntr_reg_n_0_[0] )); FDCE #( .INIT(1'b0)) \usrclk_tx_active_in_extend_cntr_reg[1] (.C(rst_in_out_reg_1), .CE(\usrclk_tx_active_in_extend_cntr[7]_i_1_n_0 ), .CLR(mmcm_not_locked_out2), .D(p_0_in__2[1]), .Q(\usrclk_tx_active_in_extend_cntr_reg_n_0_[1] )); FDCE #( .INIT(1'b0)) \usrclk_tx_active_in_extend_cntr_reg[2] (.C(rst_in_out_reg_1), .CE(\usrclk_tx_active_in_extend_cntr[7]_i_1_n_0 ), .CLR(mmcm_not_locked_out2), .D(p_0_in__2[2]), .Q(\usrclk_tx_active_in_extend_cntr_reg_n_0_[2] )); FDCE #( .INIT(1'b0)) \usrclk_tx_active_in_extend_cntr_reg[3] (.C(rst_in_out_reg_1), .CE(\usrclk_tx_active_in_extend_cntr[7]_i_1_n_0 ), .CLR(mmcm_not_locked_out2), .D(p_0_in__2[3]), .Q(\usrclk_tx_active_in_extend_cntr_reg_n_0_[3] )); FDCE #( .INIT(1'b0)) \usrclk_tx_active_in_extend_cntr_reg[4] (.C(rst_in_out_reg_1), .CE(\usrclk_tx_active_in_extend_cntr[7]_i_1_n_0 ), .CLR(mmcm_not_locked_out2), .D(p_0_in__2[4]), .Q(\usrclk_tx_active_in_extend_cntr_reg_n_0_[4] )); FDCE #( .INIT(1'b0)) \usrclk_tx_active_in_extend_cntr_reg[5] (.C(rst_in_out_reg_1), .CE(\usrclk_tx_active_in_extend_cntr[7]_i_1_n_0 ), .CLR(mmcm_not_locked_out2), .D(p_0_in__2[5]), .Q(\usrclk_tx_active_in_extend_cntr_reg_n_0_[5] )); FDCE #( .INIT(1'b0)) \usrclk_tx_active_in_extend_cntr_reg[6] (.C(rst_in_out_reg_1), .CE(\usrclk_tx_active_in_extend_cntr[7]_i_1_n_0 ), .CLR(mmcm_not_locked_out2), .D(p_0_in__2[6]), .Q(\usrclk_tx_active_in_extend_cntr_reg_n_0_[6] )); FDCE #( .INIT(1'b0)) \usrclk_tx_active_in_extend_cntr_reg[7] (.C(rst_in_out_reg_1), .CE(\usrclk_tx_active_in_extend_cntr[7]_i_1_n_0 ), .CLR(mmcm_not_locked_out2), .D(p_0_in__2[7]), .Q(gtwiz_userclk_tx_active_in)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_RESET_LOGIC" *) module aurora_64b66b_0_aurora_64b66b_0_RESET_LOGIC (SR, ready_r_reg0, reset_count_r0, SYSTEM_RESET_reg_0, stg1_aurora_64b66b_0_cdc_to_reg, link_reset_out, power_down, sysreset_from_support, stg4_reg, hard_err_i, tx_reset_i, wait_for_lane_up_r_reg); output [0:0]SR; output ready_r_reg0; output reset_count_r0; output SYSTEM_RESET_reg_0; input stg1_aurora_64b66b_0_cdc_to_reg; input link_reset_out; input power_down; input sysreset_from_support; input stg4_reg; input hard_err_i; input tx_reset_i; input wait_for_lane_up_r_reg; wire [0:0]SR; wire SYSTEM_RESET0_n_0; wire SYSTEM_RESET_reg_0; wire fsm_resetdone_sync; wire hard_err_i; wire link_reset_out; wire link_reset_sync; wire power_down; wire power_down_sync; wire ready_r_reg0; wire reset_count_r0; wire stg1_aurora_64b66b_0_cdc_to_reg; wire stg4_reg; wire sysreset_from_support; wire tx_reset_i; wire wait_for_lane_up_r_reg; LUT4 #( .INIT(16'hFFEF)) SYSTEM_RESET0 (.I0(link_reset_sync), .I1(sysreset_from_support), .I2(fsm_resetdone_sync), .I3(power_down_sync), .O(SYSTEM_RESET0_n_0)); FDRE #( .INIT(1'b1)) SYSTEM_RESET_reg (.C(stg4_reg), .CE(1'b1), .D(SYSTEM_RESET0_n_0), .Q(SR), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair116" *) LUT2 #( .INIT(4'hE)) ready_r_i_1 (.I0(SR), .I1(hard_err_i), .O(ready_r_reg0)); LUT2 #( .INIT(4'hB)) reset_count_r_i_1 (.I0(SR), .I1(tx_reset_i), .O(reset_count_r0)); aurora_64b66b_0_aurora_64b66b_0_rst_sync_2 u_link_rst_sync (.link_reset_out(link_reset_out), .link_reset_sync(link_reset_sync), .stg5_reg_0(stg4_reg)); aurora_64b66b_0_aurora_64b66b_0_rst_sync_3 u_pd_sync (.power_down(power_down), .power_down_sync(power_down_sync), .stg4_reg_0(stg4_reg)); aurora_64b66b_0_aurora_64b66b_0_rst_sync_4 u_rst_done_sync (.fsm_resetdone_sync(fsm_resetdone_sync), .stg1_aurora_64b66b_0_cdc_to_reg_0(stg1_aurora_64b66b_0_cdc_to_reg), .stg4_reg_0(stg4_reg)); (* SOFT_HLUTNM = "soft_lutpair116" *) LUT2 #( .INIT(4'hB)) wait_for_lane_up_r_i_1 (.I0(SR), .I1(wait_for_lane_up_r_reg), .O(SYSTEM_RESET_reg_0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_RX_STREAM" *) module aurora_64b66b_0_aurora_64b66b_0_RX_STREAM (m_axi_rx_tvalid, m_axi_rx_tdata, RX_SRC_RDY_N_reg_inv, RX_SRC_RDY_N_reg_inv_0, SR, E, D); output m_axi_rx_tvalid; output [0:63]m_axi_rx_tdata; input RX_SRC_RDY_N_reg_inv; input RX_SRC_RDY_N_reg_inv_0; input [0:0]SR; input [0:0]E; input [63:0]D; wire [63:0]D; wire [0:0]E; wire RX_SRC_RDY_N_reg_inv; wire RX_SRC_RDY_N_reg_inv_0; wire [0:0]SR; wire [0:63]m_axi_rx_tdata; wire m_axi_rx_tvalid; aurora_64b66b_0_aurora_64b66b_0_RX_STREAM_DATAPATH rx_stream_datapath_i (.D(D), .E(E), .RX_SRC_RDY_N_reg_inv_0(RX_SRC_RDY_N_reg_inv), .RX_SRC_RDY_N_reg_inv_1(RX_SRC_RDY_N_reg_inv_0), .SR(SR), .m_axi_rx_tdata(m_axi_rx_tdata), .m_axi_rx_tvalid(m_axi_rx_tvalid)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_RX_STREAM_DATAPATH" *) module aurora_64b66b_0_aurora_64b66b_0_RX_STREAM_DATAPATH (m_axi_rx_tvalid, m_axi_rx_tdata, RX_SRC_RDY_N_reg_inv_0, RX_SRC_RDY_N_reg_inv_1, SR, E, D); output m_axi_rx_tvalid; output [0:63]m_axi_rx_tdata; input RX_SRC_RDY_N_reg_inv_0; input RX_SRC_RDY_N_reg_inv_1; input [0:0]SR; input [0:0]E; input [63:0]D; wire [63:0]D; wire [0:0]E; wire RX_SRC_RDY_N_reg_inv_0; wire RX_SRC_RDY_N_reg_inv_1; wire [0:0]SR; wire [0:63]m_axi_rx_tdata; wire m_axi_rx_tvalid; FDRE \RX_D_reg[0] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[63]), .Q(m_axi_rx_tdata[0]), .R(SR)); FDRE \RX_D_reg[10] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[53]), .Q(m_axi_rx_tdata[10]), .R(SR)); FDRE \RX_D_reg[11] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[52]), .Q(m_axi_rx_tdata[11]), .R(SR)); FDRE \RX_D_reg[12] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[51]), .Q(m_axi_rx_tdata[12]), .R(SR)); FDRE \RX_D_reg[13] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[50]), .Q(m_axi_rx_tdata[13]), .R(SR)); FDRE \RX_D_reg[14] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[49]), .Q(m_axi_rx_tdata[14]), .R(SR)); FDRE \RX_D_reg[15] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[48]), .Q(m_axi_rx_tdata[15]), .R(SR)); FDRE \RX_D_reg[16] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[47]), .Q(m_axi_rx_tdata[16]), .R(SR)); FDRE \RX_D_reg[17] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[46]), .Q(m_axi_rx_tdata[17]), .R(SR)); FDRE \RX_D_reg[18] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[45]), .Q(m_axi_rx_tdata[18]), .R(SR)); FDRE \RX_D_reg[19] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[44]), .Q(m_axi_rx_tdata[19]), .R(SR)); FDRE \RX_D_reg[1] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[62]), .Q(m_axi_rx_tdata[1]), .R(SR)); FDRE \RX_D_reg[20] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[43]), .Q(m_axi_rx_tdata[20]), .R(SR)); FDRE \RX_D_reg[21] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[42]), .Q(m_axi_rx_tdata[21]), .R(SR)); FDRE \RX_D_reg[22] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[41]), .Q(m_axi_rx_tdata[22]), .R(SR)); FDRE \RX_D_reg[23] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[40]), .Q(m_axi_rx_tdata[23]), .R(SR)); FDRE \RX_D_reg[24] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[39]), .Q(m_axi_rx_tdata[24]), .R(SR)); FDRE \RX_D_reg[25] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[38]), .Q(m_axi_rx_tdata[25]), .R(SR)); FDRE \RX_D_reg[26] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[37]), .Q(m_axi_rx_tdata[26]), .R(SR)); FDRE \RX_D_reg[27] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[36]), .Q(m_axi_rx_tdata[27]), .R(SR)); FDRE \RX_D_reg[28] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[35]), .Q(m_axi_rx_tdata[28]), .R(SR)); FDRE \RX_D_reg[29] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[34]), .Q(m_axi_rx_tdata[29]), .R(SR)); FDRE \RX_D_reg[2] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[61]), .Q(m_axi_rx_tdata[2]), .R(SR)); FDRE \RX_D_reg[30] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[33]), .Q(m_axi_rx_tdata[30]), .R(SR)); FDRE \RX_D_reg[31] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[32]), .Q(m_axi_rx_tdata[31]), .R(SR)); FDRE \RX_D_reg[32] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[31]), .Q(m_axi_rx_tdata[32]), .R(SR)); FDRE \RX_D_reg[33] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[30]), .Q(m_axi_rx_tdata[33]), .R(SR)); FDRE \RX_D_reg[34] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[29]), .Q(m_axi_rx_tdata[34]), .R(SR)); FDRE \RX_D_reg[35] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[28]), .Q(m_axi_rx_tdata[35]), .R(SR)); FDRE \RX_D_reg[36] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[27]), .Q(m_axi_rx_tdata[36]), .R(SR)); FDRE \RX_D_reg[37] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[26]), .Q(m_axi_rx_tdata[37]), .R(SR)); FDRE \RX_D_reg[38] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[25]), .Q(m_axi_rx_tdata[38]), .R(SR)); FDRE \RX_D_reg[39] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[24]), .Q(m_axi_rx_tdata[39]), .R(SR)); FDRE \RX_D_reg[3] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[60]), .Q(m_axi_rx_tdata[3]), .R(SR)); FDRE \RX_D_reg[40] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[23]), .Q(m_axi_rx_tdata[40]), .R(SR)); FDRE \RX_D_reg[41] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[22]), .Q(m_axi_rx_tdata[41]), .R(SR)); FDRE \RX_D_reg[42] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[21]), .Q(m_axi_rx_tdata[42]), .R(SR)); FDRE \RX_D_reg[43] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[20]), .Q(m_axi_rx_tdata[43]), .R(SR)); FDRE \RX_D_reg[44] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[19]), .Q(m_axi_rx_tdata[44]), .R(SR)); FDRE \RX_D_reg[45] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[18]), .Q(m_axi_rx_tdata[45]), .R(SR)); FDRE \RX_D_reg[46] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[17]), .Q(m_axi_rx_tdata[46]), .R(SR)); FDRE \RX_D_reg[47] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[16]), .Q(m_axi_rx_tdata[47]), .R(SR)); FDRE \RX_D_reg[48] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[15]), .Q(m_axi_rx_tdata[48]), .R(SR)); FDRE \RX_D_reg[49] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[14]), .Q(m_axi_rx_tdata[49]), .R(SR)); FDRE \RX_D_reg[4] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[59]), .Q(m_axi_rx_tdata[4]), .R(SR)); FDRE \RX_D_reg[50] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[13]), .Q(m_axi_rx_tdata[50]), .R(SR)); FDRE \RX_D_reg[51] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[12]), .Q(m_axi_rx_tdata[51]), .R(SR)); FDRE \RX_D_reg[52] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[11]), .Q(m_axi_rx_tdata[52]), .R(SR)); FDRE \RX_D_reg[53] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[10]), .Q(m_axi_rx_tdata[53]), .R(SR)); FDRE \RX_D_reg[54] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[9]), .Q(m_axi_rx_tdata[54]), .R(SR)); FDRE \RX_D_reg[55] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[8]), .Q(m_axi_rx_tdata[55]), .R(SR)); FDRE \RX_D_reg[56] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[7]), .Q(m_axi_rx_tdata[56]), .R(SR)); FDRE \RX_D_reg[57] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[6]), .Q(m_axi_rx_tdata[57]), .R(SR)); FDRE \RX_D_reg[58] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[5]), .Q(m_axi_rx_tdata[58]), .R(SR)); FDRE \RX_D_reg[59] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[4]), .Q(m_axi_rx_tdata[59]), .R(SR)); FDRE \RX_D_reg[5] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[58]), .Q(m_axi_rx_tdata[5]), .R(SR)); FDRE \RX_D_reg[60] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[3]), .Q(m_axi_rx_tdata[60]), .R(SR)); FDRE \RX_D_reg[61] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[2]), .Q(m_axi_rx_tdata[61]), .R(SR)); FDRE \RX_D_reg[62] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[1]), .Q(m_axi_rx_tdata[62]), .R(SR)); FDRE \RX_D_reg[63] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[0]), .Q(m_axi_rx_tdata[63]), .R(SR)); FDRE \RX_D_reg[6] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[57]), .Q(m_axi_rx_tdata[6]), .R(SR)); FDRE \RX_D_reg[7] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[56]), .Q(m_axi_rx_tdata[7]), .R(SR)); FDRE \RX_D_reg[8] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[55]), .Q(m_axi_rx_tdata[8]), .R(SR)); FDRE \RX_D_reg[9] (.C(RX_SRC_RDY_N_reg_inv_1), .CE(E), .D(D[54]), .Q(m_axi_rx_tdata[9]), .R(SR)); (* inverted = "yes" *) FDRE #( .INIT(1'b1)) RX_SRC_RDY_N_reg_inv (.C(RX_SRC_RDY_N_reg_inv_1), .CE(1'b1), .D(RX_SRC_RDY_N_reg_inv_0), .Q(m_axi_rx_tvalid), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_SCRAMBLER_64B66B" *) module aurora_64b66b_0_aurora_64b66b_0_SCRAMBLER_64B66B (\txseq_counter_i_reg[0] , scrambler, \SCRAMBLED_DATA_OUT_reg[63]_0 , Q, tx_data_i, \SCRAMBLED_DATA_OUT_reg[63]_1 , tempData); output \txseq_counter_i_reg[0] ; output [11:0]scrambler; output [63:0]\SCRAMBLED_DATA_OUT_reg[63]_0 ; input [6:0]Q; input [57:0]tx_data_i; input \SCRAMBLED_DATA_OUT_reg[63]_1 ; input [5:0]tempData; wire [6:0]Q; wire [63:0]\SCRAMBLED_DATA_OUT_reg[63]_0 ; wire \SCRAMBLED_DATA_OUT_reg[63]_1 ; wire data_valid_i; wire p_101_in; wire p_105_in; wire p_109_in; wire p_113_in; wire p_117_in; wire p_121_in; wire p_125_in; wire p_129_in; wire p_133_in; wire p_137_in; wire p_141_in; wire p_145_in; wire p_149_in; wire p_177_in; wire p_181_in; wire p_185_in; wire p_189_in; wire p_193_in; wire p_197_in; wire p_201_in; wire p_205_in; wire p_209_in; wire p_213_in; wire p_217_in; wire p_221_in; wire p_225_in; wire p_229_in; wire p_233_in; wire p_237_in; wire p_241_in; wire p_245_in; wire p_249_in; wire p_97_in; wire [11:0]scrambler; wire \scrambler_reg_n_0_[39] ; wire \scrambler_reg_n_0_[40] ; wire \scrambler_reg_n_0_[41] ; wire \scrambler_reg_n_0_[42] ; wire \scrambler_reg_n_0_[43] ; wire \scrambler_reg_n_0_[44] ; wire \scrambler_reg_n_0_[45] ; wire \scrambler_reg_n_0_[46] ; wire \scrambler_reg_n_0_[47] ; wire \scrambler_reg_n_0_[48] ; wire \scrambler_reg_n_0_[49] ; wire \scrambler_reg_n_0_[50] ; wire \scrambler_reg_n_0_[51] ; wire [5:0]tempData; wire tempData0100_out; wire tempData0104_out; wire tempData0108_out; wire tempData0112_out; wire tempData0116_out; wire tempData0120_out; wire tempData0124_out; wire tempData0128_out; wire tempData0132_out; wire tempData0136_out; wire tempData0140_out; wire tempData0144_out; wire tempData0148_out; wire tempData0152_out; wire tempData0156_out; wire tempData0160_out; wire tempData0164_out; wire tempData0168_out; wire tempData0172_out; wire tempData0176_out; wire tempData0180_out; wire tempData0184_out; wire tempData0188_out; wire tempData0192_out; wire tempData0196_out; wire tempData0200_out; wire tempData0204_out; wire tempData0208_out; wire tempData0212_out; wire tempData0216_out; wire tempData0220_out; wire tempData0224_out; wire tempData0228_out; wire tempData0232_out; wire tempData0236_out; wire tempData0240_out; wire tempData0244_out; wire tempData0248_out; wire tempData024_out; wire tempData0252_out; wire tempData028_out; wire tempData032_out; wire tempData036_out; wire tempData040_out; wire tempData044_out; wire tempData048_out; wire tempData052_out; wire tempData056_out; wire tempData060_out; wire tempData064_out; wire tempData068_out; wire tempData072_out; wire tempData076_out; wire tempData080_out; wire tempData084_out; wire tempData088_out; wire tempData092_out; wire tempData096_out; wire [57:0]tx_data_i; wire \txseq_counter_i_reg[0] ; (* SOFT_HLUTNM = "soft_lutpair77" *) LUT3 #( .INIT(8'h96)) \SCRAMBLED_DATA_OUT[58]_i_1 (.I0(p_229_in), .I1(tx_data_i[52]), .I2(scrambler[6]), .O(tempData0232_out)); (* SOFT_HLUTNM = "soft_lutpair76" *) LUT3 #( .INIT(8'h96)) \SCRAMBLED_DATA_OUT[59]_i_1 (.I0(p_233_in), .I1(tx_data_i[53]), .I2(scrambler[7]), .O(tempData0236_out)); (* SOFT_HLUTNM = "soft_lutpair75" *) LUT3 #( .INIT(8'h96)) \SCRAMBLED_DATA_OUT[60]_i_1 (.I0(p_237_in), .I1(tx_data_i[54]), .I2(scrambler[8]), .O(tempData0240_out)); (* SOFT_HLUTNM = "soft_lutpair74" *) LUT3 #( .INIT(8'h96)) \SCRAMBLED_DATA_OUT[61]_i_1 (.I0(p_241_in), .I1(tx_data_i[55]), .I2(scrambler[9]), .O(tempData0244_out)); (* SOFT_HLUTNM = "soft_lutpair73" *) LUT3 #( .INIT(8'h96)) \SCRAMBLED_DATA_OUT[62]_i_1 (.I0(p_245_in), .I1(tx_data_i[56]), .I2(scrambler[10]), .O(tempData0248_out)); (* SOFT_HLUTNM = "soft_lutpair72" *) LUT3 #( .INIT(8'h96)) \SCRAMBLED_DATA_OUT[63]_i_1 (.I0(p_249_in), .I1(tx_data_i[57]), .I2(scrambler[11]), .O(tempData0252_out)); FDRE \SCRAMBLED_DATA_OUT_reg[0] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData[0]), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [0]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[10] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData040_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [10]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[11] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData044_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [11]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[12] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData048_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [12]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[13] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData052_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [13]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[14] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData056_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [14]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[15] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData060_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [15]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[16] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData064_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [16]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[17] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData068_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [17]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[18] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData072_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [18]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[19] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData076_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [19]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[1] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData[1]), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [1]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[20] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData080_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [20]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[21] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData084_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [21]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[22] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData088_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [22]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[23] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData092_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [23]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[24] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData096_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [24]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[25] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0100_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [25]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[26] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0104_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [26]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[27] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0108_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [27]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[28] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0112_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [28]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[29] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0116_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [29]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[2] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData[2]), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [2]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[30] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0120_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [30]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[31] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0124_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [31]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[32] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0128_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [32]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[33] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0132_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [33]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[34] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0136_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [34]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[35] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0140_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [35]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[36] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0144_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [36]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[37] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0148_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [37]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[38] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0152_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [38]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[39] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0156_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [39]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[3] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData[3]), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [3]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[40] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0160_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [40]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[41] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0164_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [41]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[42] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0168_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [42]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[43] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0172_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [43]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[44] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0176_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [44]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[45] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0180_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [45]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[46] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0184_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [46]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[47] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0188_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [47]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[48] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0192_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [48]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[49] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0196_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [49]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[4] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData[4]), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [4]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[50] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0200_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [50]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[51] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0204_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [51]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[52] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0208_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [52]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[53] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0212_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [53]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[54] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0216_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [54]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[55] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0220_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [55]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[56] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0224_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [56]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[57] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0228_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [57]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[58] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0232_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [58]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[59] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0236_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [59]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[5] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData[5]), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [5]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[60] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0240_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [60]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[61] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0244_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [61]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[62] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0248_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [62]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[63] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0252_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [63]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[6] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData024_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [6]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[7] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData028_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [7]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[8] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData032_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [8]), .R(1'b0)); FDRE \SCRAMBLED_DATA_OUT_reg[9] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData036_out), .Q(\SCRAMBLED_DATA_OUT_reg[63]_0 [9]), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair86" *) LUT5 #( .INIT(32'h96696996)) \scrambler[10]_i_1 (.I0(\scrambler_reg_n_0_[43] ), .I1(tx_data_i[43]), .I2(p_193_in), .I3(tx_data_i[4]), .I4(p_113_in), .O(tempData040_out)); (* SOFT_HLUTNM = "soft_lutpair85" *) LUT5 #( .INIT(32'h96696996)) \scrambler[11]_i_1 (.I0(\scrambler_reg_n_0_[44] ), .I1(tx_data_i[44]), .I2(p_197_in), .I3(tx_data_i[5]), .I4(p_117_in), .O(tempData044_out)); (* SOFT_HLUTNM = "soft_lutpair84" *) LUT5 #( .INIT(32'h96696996)) \scrambler[12]_i_1 (.I0(\scrambler_reg_n_0_[45] ), .I1(tx_data_i[45]), .I2(p_201_in), .I3(tx_data_i[6]), .I4(p_121_in), .O(tempData048_out)); (* SOFT_HLUTNM = "soft_lutpair83" *) LUT5 #( .INIT(32'h96696996)) \scrambler[13]_i_1 (.I0(\scrambler_reg_n_0_[46] ), .I1(tx_data_i[46]), .I2(p_205_in), .I3(tx_data_i[7]), .I4(p_125_in), .O(tempData052_out)); (* SOFT_HLUTNM = "soft_lutpair82" *) LUT5 #( .INIT(32'h96696996)) \scrambler[14]_i_1 (.I0(\scrambler_reg_n_0_[47] ), .I1(tx_data_i[47]), .I2(p_209_in), .I3(tx_data_i[8]), .I4(p_129_in), .O(tempData056_out)); (* SOFT_HLUTNM = "soft_lutpair81" *) LUT5 #( .INIT(32'h96696996)) \scrambler[15]_i_1 (.I0(\scrambler_reg_n_0_[48] ), .I1(tx_data_i[48]), .I2(p_213_in), .I3(tx_data_i[9]), .I4(p_133_in), .O(tempData060_out)); (* SOFT_HLUTNM = "soft_lutpair80" *) LUT5 #( .INIT(32'h96696996)) \scrambler[16]_i_1 (.I0(\scrambler_reg_n_0_[49] ), .I1(tx_data_i[49]), .I2(p_217_in), .I3(tx_data_i[10]), .I4(p_137_in), .O(tempData064_out)); (* SOFT_HLUTNM = "soft_lutpair79" *) LUT5 #( .INIT(32'h96696996)) \scrambler[17]_i_1 (.I0(\scrambler_reg_n_0_[50] ), .I1(tx_data_i[50]), .I2(p_221_in), .I3(tx_data_i[11]), .I4(p_141_in), .O(tempData068_out)); (* SOFT_HLUTNM = "soft_lutpair78" *) LUT5 #( .INIT(32'h96696996)) \scrambler[18]_i_1 (.I0(\scrambler_reg_n_0_[51] ), .I1(tx_data_i[51]), .I2(p_225_in), .I3(tx_data_i[12]), .I4(p_145_in), .O(tempData072_out)); (* SOFT_HLUTNM = "soft_lutpair77" *) LUT5 #( .INIT(32'h96696996)) \scrambler[19]_i_1 (.I0(scrambler[6]), .I1(tx_data_i[52]), .I2(p_229_in), .I3(tx_data_i[13]), .I4(p_149_in), .O(tempData076_out)); (* SOFT_HLUTNM = "soft_lutpair76" *) LUT5 #( .INIT(32'h96696996)) \scrambler[20]_i_1 (.I0(scrambler[7]), .I1(tx_data_i[53]), .I2(p_233_in), .I3(tx_data_i[14]), .I4(scrambler[0]), .O(tempData080_out)); (* SOFT_HLUTNM = "soft_lutpair75" *) LUT5 #( .INIT(32'h96696996)) \scrambler[21]_i_1 (.I0(scrambler[8]), .I1(tx_data_i[54]), .I2(p_237_in), .I3(tx_data_i[15]), .I4(scrambler[1]), .O(tempData084_out)); (* SOFT_HLUTNM = "soft_lutpair74" *) LUT5 #( .INIT(32'h96696996)) \scrambler[22]_i_1 (.I0(scrambler[9]), .I1(tx_data_i[55]), .I2(p_241_in), .I3(tx_data_i[16]), .I4(scrambler[2]), .O(tempData088_out)); (* SOFT_HLUTNM = "soft_lutpair73" *) LUT5 #( .INIT(32'h96696996)) \scrambler[23]_i_1 (.I0(scrambler[10]), .I1(tx_data_i[56]), .I2(p_245_in), .I3(tx_data_i[17]), .I4(scrambler[3]), .O(tempData092_out)); (* SOFT_HLUTNM = "soft_lutpair72" *) LUT5 #( .INIT(32'h96696996)) \scrambler[24]_i_1 (.I0(scrambler[11]), .I1(tx_data_i[57]), .I2(p_249_in), .I3(tx_data_i[18]), .I4(scrambler[4]), .O(tempData096_out)); (* SOFT_HLUTNM = "soft_lutpair91" *) LUT3 #( .INIT(8'h96)) \scrambler[25]_i_1 (.I0(p_97_in), .I1(tx_data_i[19]), .I2(scrambler[5]), .O(tempData0100_out)); LUT3 #( .INIT(8'h96)) \scrambler[26]_i_1 (.I0(p_101_in), .I1(tx_data_i[20]), .I2(p_177_in), .O(tempData0104_out)); LUT3 #( .INIT(8'h96)) \scrambler[27]_i_1 (.I0(p_105_in), .I1(tx_data_i[21]), .I2(p_181_in), .O(tempData0108_out)); LUT3 #( .INIT(8'h96)) \scrambler[28]_i_1 (.I0(p_109_in), .I1(tx_data_i[22]), .I2(p_185_in), .O(tempData0112_out)); LUT3 #( .INIT(8'h96)) \scrambler[29]_i_1 (.I0(p_113_in), .I1(tx_data_i[23]), .I2(p_189_in), .O(tempData0116_out)); LUT3 #( .INIT(8'h96)) \scrambler[30]_i_1 (.I0(p_117_in), .I1(tx_data_i[24]), .I2(p_193_in), .O(tempData0120_out)); LUT3 #( .INIT(8'h96)) \scrambler[31]_i_1 (.I0(p_121_in), .I1(tx_data_i[25]), .I2(p_197_in), .O(tempData0124_out)); LUT3 #( .INIT(8'h96)) \scrambler[32]_i_1 (.I0(p_125_in), .I1(tx_data_i[26]), .I2(p_201_in), .O(tempData0128_out)); LUT3 #( .INIT(8'h96)) \scrambler[33]_i_1 (.I0(p_129_in), .I1(tx_data_i[27]), .I2(p_205_in), .O(tempData0132_out)); LUT3 #( .INIT(8'h96)) \scrambler[34]_i_1 (.I0(p_133_in), .I1(tx_data_i[28]), .I2(p_209_in), .O(tempData0136_out)); LUT3 #( .INIT(8'h96)) \scrambler[35]_i_1 (.I0(p_137_in), .I1(tx_data_i[29]), .I2(p_213_in), .O(tempData0140_out)); LUT3 #( .INIT(8'h96)) \scrambler[36]_i_1 (.I0(p_141_in), .I1(tx_data_i[30]), .I2(p_217_in), .O(tempData0144_out)); LUT3 #( .INIT(8'h96)) \scrambler[37]_i_1 (.I0(p_145_in), .I1(tx_data_i[31]), .I2(p_221_in), .O(tempData0148_out)); LUT3 #( .INIT(8'h96)) \scrambler[38]_i_1 (.I0(p_149_in), .I1(tx_data_i[32]), .I2(p_225_in), .O(tempData0152_out)); LUT3 #( .INIT(8'h96)) \scrambler[39]_i_1 (.I0(scrambler[0]), .I1(tx_data_i[33]), .I2(p_229_in), .O(tempData0156_out)); LUT3 #( .INIT(8'h96)) \scrambler[40]_i_1 (.I0(scrambler[1]), .I1(tx_data_i[34]), .I2(p_233_in), .O(tempData0160_out)); LUT3 #( .INIT(8'h96)) \scrambler[41]_i_1 (.I0(scrambler[2]), .I1(tx_data_i[35]), .I2(p_237_in), .O(tempData0164_out)); LUT3 #( .INIT(8'h96)) \scrambler[42]_i_1 (.I0(scrambler[3]), .I1(tx_data_i[36]), .I2(p_241_in), .O(tempData0168_out)); LUT3 #( .INIT(8'h96)) \scrambler[43]_i_1 (.I0(scrambler[4]), .I1(tx_data_i[37]), .I2(p_245_in), .O(tempData0172_out)); (* SOFT_HLUTNM = "soft_lutpair91" *) LUT3 #( .INIT(8'h96)) \scrambler[44]_i_1 (.I0(scrambler[5]), .I1(tx_data_i[38]), .I2(p_249_in), .O(tempData0176_out)); (* SOFT_HLUTNM = "soft_lutpair90" *) LUT3 #( .INIT(8'h96)) \scrambler[45]_i_1 (.I0(p_177_in), .I1(tx_data_i[39]), .I2(\scrambler_reg_n_0_[39] ), .O(tempData0180_out)); (* SOFT_HLUTNM = "soft_lutpair89" *) LUT3 #( .INIT(8'h96)) \scrambler[46]_i_1 (.I0(p_181_in), .I1(tx_data_i[40]), .I2(\scrambler_reg_n_0_[40] ), .O(tempData0184_out)); (* SOFT_HLUTNM = "soft_lutpair88" *) LUT3 #( .INIT(8'h96)) \scrambler[47]_i_1 (.I0(p_185_in), .I1(tx_data_i[41]), .I2(\scrambler_reg_n_0_[41] ), .O(tempData0188_out)); (* SOFT_HLUTNM = "soft_lutpair87" *) LUT3 #( .INIT(8'h96)) \scrambler[48]_i_1 (.I0(p_189_in), .I1(tx_data_i[42]), .I2(\scrambler_reg_n_0_[42] ), .O(tempData0192_out)); (* SOFT_HLUTNM = "soft_lutpair86" *) LUT3 #( .INIT(8'h96)) \scrambler[49]_i_1 (.I0(p_193_in), .I1(tx_data_i[43]), .I2(\scrambler_reg_n_0_[43] ), .O(tempData0196_out)); (* SOFT_HLUTNM = "soft_lutpair85" *) LUT3 #( .INIT(8'h96)) \scrambler[50]_i_1 (.I0(p_197_in), .I1(tx_data_i[44]), .I2(\scrambler_reg_n_0_[44] ), .O(tempData0200_out)); (* SOFT_HLUTNM = "soft_lutpair84" *) LUT3 #( .INIT(8'h96)) \scrambler[51]_i_1 (.I0(p_201_in), .I1(tx_data_i[45]), .I2(\scrambler_reg_n_0_[45] ), .O(tempData0204_out)); (* SOFT_HLUTNM = "soft_lutpair83" *) LUT3 #( .INIT(8'h96)) \scrambler[52]_i_1 (.I0(p_205_in), .I1(tx_data_i[46]), .I2(\scrambler_reg_n_0_[46] ), .O(tempData0208_out)); (* SOFT_HLUTNM = "soft_lutpair82" *) LUT3 #( .INIT(8'h96)) \scrambler[53]_i_1 (.I0(p_209_in), .I1(tx_data_i[47]), .I2(\scrambler_reg_n_0_[47] ), .O(tempData0212_out)); (* SOFT_HLUTNM = "soft_lutpair81" *) LUT3 #( .INIT(8'h96)) \scrambler[54]_i_1 (.I0(p_213_in), .I1(tx_data_i[48]), .I2(\scrambler_reg_n_0_[48] ), .O(tempData0216_out)); (* SOFT_HLUTNM = "soft_lutpair80" *) LUT3 #( .INIT(8'h96)) \scrambler[55]_i_1 (.I0(p_217_in), .I1(tx_data_i[49]), .I2(\scrambler_reg_n_0_[49] ), .O(tempData0220_out)); (* SOFT_HLUTNM = "soft_lutpair79" *) LUT3 #( .INIT(8'h96)) \scrambler[56]_i_1 (.I0(p_221_in), .I1(tx_data_i[50]), .I2(\scrambler_reg_n_0_[50] ), .O(tempData0224_out)); LUT6 #( .INIT(64'hFEFFFFFFFFFFFFFF)) \scrambler[57]_i_1 (.I0(Q[6]), .I1(\txseq_counter_i_reg[0] ), .I2(Q[5]), .I3(Q[3]), .I4(Q[2]), .I5(Q[4]), .O(data_valid_i)); (* SOFT_HLUTNM = "soft_lutpair78" *) LUT3 #( .INIT(8'h96)) \scrambler[57]_i_2 (.I0(p_225_in), .I1(tx_data_i[51]), .I2(\scrambler_reg_n_0_[51] ), .O(tempData0228_out)); LUT2 #( .INIT(4'h7)) \scrambler[57]_i_3 (.I0(Q[0]), .I1(Q[1]), .O(\txseq_counter_i_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair90" *) LUT5 #( .INIT(32'h96696996)) \scrambler[6]_i_1 (.I0(\scrambler_reg_n_0_[39] ), .I1(tx_data_i[39]), .I2(p_177_in), .I3(tx_data_i[0]), .I4(p_97_in), .O(tempData024_out)); (* SOFT_HLUTNM = "soft_lutpair89" *) LUT5 #( .INIT(32'h96696996)) \scrambler[7]_i_1 (.I0(\scrambler_reg_n_0_[40] ), .I1(tx_data_i[40]), .I2(p_181_in), .I3(tx_data_i[1]), .I4(p_101_in), .O(tempData028_out)); (* SOFT_HLUTNM = "soft_lutpair88" *) LUT5 #( .INIT(32'h96696996)) \scrambler[8]_i_1 (.I0(\scrambler_reg_n_0_[41] ), .I1(tx_data_i[41]), .I2(p_185_in), .I3(tx_data_i[2]), .I4(p_105_in), .O(tempData032_out)); (* SOFT_HLUTNM = "soft_lutpair87" *) LUT5 #( .INIT(32'h96696996)) \scrambler[9]_i_1 (.I0(\scrambler_reg_n_0_[42] ), .I1(tx_data_i[42]), .I2(p_189_in), .I3(tx_data_i[3]), .I4(p_109_in), .O(tempData036_out)); FDRE #( .INIT(1'b1)) \scrambler_reg[0] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData[0]), .Q(p_97_in), .R(1'b0)); FDRE #( .INIT(1'b1)) \scrambler_reg[10] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData040_out), .Q(p_137_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \scrambler_reg[11] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData044_out), .Q(p_141_in), .R(1'b0)); FDRE #( .INIT(1'b1)) \scrambler_reg[12] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData048_out), .Q(p_145_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \scrambler_reg[13] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData052_out), .Q(p_149_in), .R(1'b0)); FDRE #( .INIT(1'b1)) \scrambler_reg[14] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData056_out), .Q(scrambler[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \scrambler_reg[15] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData060_out), .Q(scrambler[1]), .R(1'b0)); FDRE #( .INIT(1'b1)) \scrambler_reg[16] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData064_out), .Q(scrambler[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \scrambler_reg[17] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData068_out), .Q(scrambler[3]), .R(1'b0)); FDRE #( .INIT(1'b1)) \scrambler_reg[18] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData072_out), .Q(scrambler[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \scrambler_reg[19] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData076_out), .Q(scrambler[5]), .R(1'b0)); FDRE #( .INIT(1'b0)) \scrambler_reg[1] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData[1]), .Q(p_101_in), .R(1'b0)); FDRE #( .INIT(1'b1)) \scrambler_reg[20] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData080_out), .Q(p_177_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \scrambler_reg[21] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData084_out), .Q(p_181_in), .R(1'b0)); FDRE #( .INIT(1'b1)) \scrambler_reg[22] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData088_out), .Q(p_185_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \scrambler_reg[23] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData092_out), .Q(p_189_in), .R(1'b0)); FDRE #( .INIT(1'b1)) \scrambler_reg[24] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData096_out), .Q(p_193_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \scrambler_reg[25] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0100_out), .Q(p_197_in), .R(1'b0)); FDRE #( .INIT(1'b1)) \scrambler_reg[26] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0104_out), .Q(p_201_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \scrambler_reg[27] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0108_out), .Q(p_205_in), .R(1'b0)); FDRE #( .INIT(1'b1)) \scrambler_reg[28] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0112_out), .Q(p_209_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \scrambler_reg[29] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0116_out), .Q(p_213_in), .R(1'b0)); FDRE #( .INIT(1'b1)) \scrambler_reg[2] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData[2]), .Q(p_105_in), .R(1'b0)); FDRE #( .INIT(1'b1)) \scrambler_reg[30] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0120_out), .Q(p_217_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \scrambler_reg[31] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0124_out), .Q(p_221_in), .R(1'b0)); FDRE #( .INIT(1'b1)) \scrambler_reg[32] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0128_out), .Q(p_225_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \scrambler_reg[33] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0132_out), .Q(p_229_in), .R(1'b0)); FDRE #( .INIT(1'b1)) \scrambler_reg[34] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0136_out), .Q(p_233_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \scrambler_reg[35] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0140_out), .Q(p_237_in), .R(1'b0)); FDRE #( .INIT(1'b1)) \scrambler_reg[36] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0144_out), .Q(p_241_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \scrambler_reg[37] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0148_out), .Q(p_245_in), .R(1'b0)); FDRE #( .INIT(1'b1)) \scrambler_reg[38] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0152_out), .Q(p_249_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \scrambler_reg[39] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0156_out), .Q(\scrambler_reg_n_0_[39] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \scrambler_reg[3] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData[3]), .Q(p_109_in), .R(1'b0)); FDRE #( .INIT(1'b1)) \scrambler_reg[40] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0160_out), .Q(\scrambler_reg_n_0_[40] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \scrambler_reg[41] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0164_out), .Q(\scrambler_reg_n_0_[41] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \scrambler_reg[42] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0168_out), .Q(\scrambler_reg_n_0_[42] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \scrambler_reg[43] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0172_out), .Q(\scrambler_reg_n_0_[43] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \scrambler_reg[44] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0176_out), .Q(\scrambler_reg_n_0_[44] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \scrambler_reg[45] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0180_out), .Q(\scrambler_reg_n_0_[45] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \scrambler_reg[46] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0184_out), .Q(\scrambler_reg_n_0_[46] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \scrambler_reg[47] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0188_out), .Q(\scrambler_reg_n_0_[47] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \scrambler_reg[48] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0192_out), .Q(\scrambler_reg_n_0_[48] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \scrambler_reg[49] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0196_out), .Q(\scrambler_reg_n_0_[49] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \scrambler_reg[4] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData[4]), .Q(p_113_in), .R(1'b0)); FDRE #( .INIT(1'b1)) \scrambler_reg[50] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0200_out), .Q(\scrambler_reg_n_0_[50] ), .R(1'b0)); FDRE #( .INIT(1'b0)) \scrambler_reg[51] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0204_out), .Q(\scrambler_reg_n_0_[51] ), .R(1'b0)); FDRE #( .INIT(1'b1)) \scrambler_reg[52] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0208_out), .Q(scrambler[6]), .R(1'b0)); FDRE #( .INIT(1'b0)) \scrambler_reg[53] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0212_out), .Q(scrambler[7]), .R(1'b0)); FDRE #( .INIT(1'b1)) \scrambler_reg[54] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0216_out), .Q(scrambler[8]), .R(1'b0)); FDRE #( .INIT(1'b0)) \scrambler_reg[55] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0220_out), .Q(scrambler[9]), .R(1'b0)); FDRE #( .INIT(1'b1)) \scrambler_reg[56] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0224_out), .Q(scrambler[10]), .R(1'b0)); FDRE #( .INIT(1'b0)) \scrambler_reg[57] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData0228_out), .Q(scrambler[11]), .R(1'b0)); FDRE #( .INIT(1'b0)) \scrambler_reg[5] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData[5]), .Q(p_117_in), .R(1'b0)); FDRE #( .INIT(1'b1)) \scrambler_reg[6] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData024_out), .Q(p_121_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \scrambler_reg[7] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData028_out), .Q(p_125_in), .R(1'b0)); FDRE #( .INIT(1'b1)) \scrambler_reg[8] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData032_out), .Q(p_129_in), .R(1'b0)); FDRE #( .INIT(1'b0)) \scrambler_reg[9] (.C(\SCRAMBLED_DATA_OUT_reg[63]_1 ), .CE(data_valid_i), .D(tempData036_out), .Q(p_133_in), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_STANDARD_CC_MODULE" *) module aurora_64b66b_0_aurora_64b66b_0_STANDARD_CC_MODULE (do_cc_r_reg0, Q, SR, \count_24d_srl_r_reg[0]_0 , extend_cc_r, \count_16d_srl_r_reg[0]_0 ); output do_cc_r_reg0; output Q; input SR; input \count_24d_srl_r_reg[0]_0 ; input extend_cc_r; input \count_16d_srl_r_reg[0]_0 ; wire DO_CC0_n_0; wire DO_CC_i_2_n_0; wire Q; wire SR; wire \cc_count_r_reg_n_0_[5] ; wire count_13d_flop_r; wire count_13d_flop_r_i_1_n_0; wire count_13d_flop_r_i_2_n_0; wire count_13d_flop_r_i_3_n_0; wire \count_13d_srl_r_reg_n_0_[0] ; wire \count_13d_srl_r_reg_n_0_[10] ; wire \count_13d_srl_r_reg_n_0_[11] ; wire \count_13d_srl_r_reg_n_0_[1] ; wire \count_13d_srl_r_reg_n_0_[2] ; wire \count_13d_srl_r_reg_n_0_[3] ; wire \count_13d_srl_r_reg_n_0_[4] ; wire \count_13d_srl_r_reg_n_0_[5] ; wire \count_13d_srl_r_reg_n_0_[6] ; wire \count_13d_srl_r_reg_n_0_[7] ; wire \count_13d_srl_r_reg_n_0_[8] ; wire \count_13d_srl_r_reg_n_0_[9] ; wire count_16d_flop_r; wire count_16d_flop_r0; wire count_16d_flop_r_i_1_n_0; wire count_16d_flop_r_i_3_n_0; wire count_16d_flop_r_i_4_n_0; wire \count_16d_srl_r[0]_i_1_n_0 ; wire \count_16d_srl_r_reg[0]_0 ; wire \count_16d_srl_r_reg_n_0_[0] ; wire \count_16d_srl_r_reg_n_0_[10] ; wire \count_16d_srl_r_reg_n_0_[11] ; wire \count_16d_srl_r_reg_n_0_[12] ; wire \count_16d_srl_r_reg_n_0_[13] ; wire \count_16d_srl_r_reg_n_0_[14] ; wire \count_16d_srl_r_reg_n_0_[1] ; wire \count_16d_srl_r_reg_n_0_[2] ; wire \count_16d_srl_r_reg_n_0_[3] ; wire \count_16d_srl_r_reg_n_0_[4] ; wire \count_16d_srl_r_reg_n_0_[5] ; wire \count_16d_srl_r_reg_n_0_[6] ; wire \count_16d_srl_r_reg_n_0_[7] ; wire \count_16d_srl_r_reg_n_0_[8] ; wire \count_16d_srl_r_reg_n_0_[9] ; wire count_24d_flop_r; wire count_24d_flop_r0; wire count_24d_flop_r_i_1_n_0; wire count_24d_flop_r_i_3_n_0; wire count_24d_flop_r_i_4_n_0; wire count_24d_flop_r_i_5_n_0; wire count_24d_flop_r_i_6_n_0; wire count_24d_srl_r0; wire \count_24d_srl_r_reg[0]_0 ; wire \count_24d_srl_r_reg_n_0_[0] ; wire \count_24d_srl_r_reg_n_0_[10] ; wire \count_24d_srl_r_reg_n_0_[11] ; wire \count_24d_srl_r_reg_n_0_[12] ; wire \count_24d_srl_r_reg_n_0_[13] ; wire \count_24d_srl_r_reg_n_0_[14] ; wire \count_24d_srl_r_reg_n_0_[15] ; wire \count_24d_srl_r_reg_n_0_[16] ; wire \count_24d_srl_r_reg_n_0_[17] ; wire \count_24d_srl_r_reg_n_0_[18] ; wire \count_24d_srl_r_reg_n_0_[19] ; wire \count_24d_srl_r_reg_n_0_[1] ; wire \count_24d_srl_r_reg_n_0_[20] ; wire \count_24d_srl_r_reg_n_0_[21] ; wire \count_24d_srl_r_reg_n_0_[22] ; wire \count_24d_srl_r_reg_n_0_[2] ; wire \count_24d_srl_r_reg_n_0_[3] ; wire \count_24d_srl_r_reg_n_0_[4] ; wire \count_24d_srl_r_reg_n_0_[5] ; wire \count_24d_srl_r_reg_n_0_[6] ; wire \count_24d_srl_r_reg_n_0_[7] ; wire \count_24d_srl_r_reg_n_0_[8] ; wire \count_24d_srl_r_reg_n_0_[9] ; wire do_cc_r_reg0; wire extend_cc_r; wire [4:0]p_1_in; wire [5:5]p_2_out; wire reset_r; LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) DO_CC0 (.I0(p_1_in[0]), .I1(\cc_count_r_reg_n_0_[5] ), .I2(p_1_in[3]), .I3(p_1_in[4]), .I4(p_1_in[1]), .I5(p_1_in[2]), .O(DO_CC0_n_0)); LUT5 #( .INIT(32'hFEEEEEEE)) DO_CC_i_2 (.I0(DO_CC0_n_0), .I1(reset_r), .I2(\count_13d_srl_r_reg_n_0_[11] ), .I3(\count_16d_srl_r_reg_n_0_[14] ), .I4(\count_24d_srl_r_reg_n_0_[22] ), .O(DO_CC_i_2_n_0)); FDRE DO_CC_reg (.C(\count_24d_srl_r_reg[0]_0 ), .CE(1'b1), .D(DO_CC_i_2_n_0), .Q(Q), .R(SR)); LUT4 #( .INIT(16'h80FF)) \cc_count_r[0]_i_1 (.I0(\count_24d_srl_r_reg_n_0_[22] ), .I1(\count_16d_srl_r_reg_n_0_[14] ), .I2(\count_13d_srl_r_reg_n_0_[11] ), .I3(\count_16d_srl_r_reg[0]_0 ), .O(p_2_out)); FDRE #( .INIT(1'b0)) \cc_count_r_reg[0] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(1'b1), .D(p_2_out), .Q(p_1_in[4]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cc_count_r_reg[1] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(1'b1), .D(p_1_in[4]), .Q(p_1_in[3]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cc_count_r_reg[2] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(1'b1), .D(p_1_in[3]), .Q(p_1_in[2]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cc_count_r_reg[3] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(1'b1), .D(p_1_in[2]), .Q(p_1_in[1]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cc_count_r_reg[4] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(1'b1), .D(p_1_in[1]), .Q(p_1_in[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) \cc_count_r_reg[5] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(1'b1), .D(p_1_in[0]), .Q(\cc_count_r_reg_n_0_[5] ), .R(1'b0)); LUT4 #( .INIT(16'hEAAA)) count_13d_flop_r_i_1 (.I0(\count_13d_srl_r_reg_n_0_[11] ), .I1(count_13d_flop_r_i_2_n_0), .I2(count_13d_flop_r_i_3_n_0), .I3(reset_r), .O(count_13d_flop_r_i_1_n_0)); LUT6 #( .INIT(64'h0000000000000001)) count_13d_flop_r_i_2 (.I0(\count_13d_srl_r_reg_n_0_[9] ), .I1(\count_13d_srl_r_reg_n_0_[8] ), .I2(\count_13d_srl_r_reg_n_0_[11] ), .I3(\count_13d_srl_r_reg_n_0_[10] ), .I4(\count_13d_srl_r_reg_n_0_[6] ), .I5(\count_13d_srl_r_reg_n_0_[7] ), .O(count_13d_flop_r_i_2_n_0)); LUT6 #( .INIT(64'h0000000000000001)) count_13d_flop_r_i_3 (.I0(\count_13d_srl_r_reg_n_0_[3] ), .I1(\count_13d_srl_r_reg_n_0_[2] ), .I2(\count_13d_srl_r_reg_n_0_[5] ), .I3(\count_13d_srl_r_reg_n_0_[4] ), .I4(\count_13d_srl_r_reg_n_0_[0] ), .I5(\count_13d_srl_r_reg_n_0_[1] ), .O(count_13d_flop_r_i_3_n_0)); FDRE count_13d_flop_r_reg (.C(\count_24d_srl_r_reg[0]_0 ), .CE(1'b1), .D(count_13d_flop_r_i_1_n_0), .Q(count_13d_flop_r), .R(SR)); FDRE \count_13d_srl_r_reg[0] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(1'b1), .D(count_13d_flop_r), .Q(\count_13d_srl_r_reg_n_0_[0] ), .R(1'b0)); FDRE \count_13d_srl_r_reg[10] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(1'b1), .D(\count_13d_srl_r_reg_n_0_[9] ), .Q(\count_13d_srl_r_reg_n_0_[10] ), .R(1'b0)); FDRE \count_13d_srl_r_reg[11] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(1'b1), .D(\count_13d_srl_r_reg_n_0_[10] ), .Q(\count_13d_srl_r_reg_n_0_[11] ), .R(1'b0)); FDRE \count_13d_srl_r_reg[1] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(1'b1), .D(\count_13d_srl_r_reg_n_0_[0] ), .Q(\count_13d_srl_r_reg_n_0_[1] ), .R(1'b0)); FDRE \count_13d_srl_r_reg[2] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(1'b1), .D(\count_13d_srl_r_reg_n_0_[1] ), .Q(\count_13d_srl_r_reg_n_0_[2] ), .R(1'b0)); FDRE \count_13d_srl_r_reg[3] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(1'b1), .D(\count_13d_srl_r_reg_n_0_[2] ), .Q(\count_13d_srl_r_reg_n_0_[3] ), .R(1'b0)); FDRE \count_13d_srl_r_reg[4] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(1'b1), .D(\count_13d_srl_r_reg_n_0_[3] ), .Q(\count_13d_srl_r_reg_n_0_[4] ), .R(1'b0)); FDRE \count_13d_srl_r_reg[5] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(1'b1), .D(\count_13d_srl_r_reg_n_0_[4] ), .Q(\count_13d_srl_r_reg_n_0_[5] ), .R(1'b0)); FDRE \count_13d_srl_r_reg[6] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(1'b1), .D(\count_13d_srl_r_reg_n_0_[5] ), .Q(\count_13d_srl_r_reg_n_0_[6] ), .R(1'b0)); FDRE \count_13d_srl_r_reg[7] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(1'b1), .D(\count_13d_srl_r_reg_n_0_[6] ), .Q(\count_13d_srl_r_reg_n_0_[7] ), .R(1'b0)); FDRE \count_13d_srl_r_reg[8] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(1'b1), .D(\count_13d_srl_r_reg_n_0_[7] ), .Q(\count_13d_srl_r_reg_n_0_[8] ), .R(1'b0)); FDRE \count_13d_srl_r_reg[9] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(1'b1), .D(\count_13d_srl_r_reg_n_0_[8] ), .Q(\count_13d_srl_r_reg_n_0_[9] ), .R(1'b0)); LUT4 #( .INIT(16'hFBF8)) count_16d_flop_r_i_1 (.I0(\count_16d_srl_r_reg_n_0_[14] ), .I1(\count_13d_srl_r_reg_n_0_[11] ), .I2(count_16d_flop_r0), .I3(count_16d_flop_r), .O(count_16d_flop_r_i_1_n_0)); LUT6 #( .INIT(64'h0000002000000000)) count_16d_flop_r_i_2 (.I0(count_16d_flop_r_i_3_n_0), .I1(\count_16d_srl_r_reg_n_0_[14] ), .I2(reset_r), .I3(\count_16d_srl_r_reg_n_0_[12] ), .I4(\count_16d_srl_r_reg_n_0_[13] ), .I5(count_16d_flop_r_i_4_n_0), .O(count_16d_flop_r0)); LUT6 #( .INIT(64'h0000000000000001)) count_16d_flop_r_i_3 (.I0(\count_16d_srl_r_reg_n_0_[3] ), .I1(\count_16d_srl_r_reg_n_0_[2] ), .I2(\count_16d_srl_r_reg_n_0_[5] ), .I3(\count_16d_srl_r_reg_n_0_[4] ), .I4(\count_16d_srl_r_reg_n_0_[0] ), .I5(\count_16d_srl_r_reg_n_0_[1] ), .O(count_16d_flop_r_i_3_n_0)); LUT6 #( .INIT(64'h0000000000000001)) count_16d_flop_r_i_4 (.I0(\count_16d_srl_r_reg_n_0_[9] ), .I1(\count_16d_srl_r_reg_n_0_[8] ), .I2(\count_16d_srl_r_reg_n_0_[11] ), .I3(\count_16d_srl_r_reg_n_0_[10] ), .I4(\count_16d_srl_r_reg_n_0_[6] ), .I5(\count_16d_srl_r_reg_n_0_[7] ), .O(count_16d_flop_r_i_4_n_0)); FDRE count_16d_flop_r_reg (.C(\count_24d_srl_r_reg[0]_0 ), .CE(1'b1), .D(count_16d_flop_r_i_1_n_0), .Q(count_16d_flop_r), .R(SR)); LUT2 #( .INIT(4'hB)) \count_16d_srl_r[0]_i_1 (.I0(\count_13d_srl_r_reg_n_0_[11] ), .I1(\count_16d_srl_r_reg[0]_0 ), .O(\count_16d_srl_r[0]_i_1_n_0 )); FDRE \count_16d_srl_r_reg[0] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(\count_16d_srl_r[0]_i_1_n_0 ), .D(count_16d_flop_r), .Q(\count_16d_srl_r_reg_n_0_[0] ), .R(1'b0)); FDRE \count_16d_srl_r_reg[10] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(\count_16d_srl_r[0]_i_1_n_0 ), .D(\count_16d_srl_r_reg_n_0_[9] ), .Q(\count_16d_srl_r_reg_n_0_[10] ), .R(1'b0)); FDRE \count_16d_srl_r_reg[11] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(\count_16d_srl_r[0]_i_1_n_0 ), .D(\count_16d_srl_r_reg_n_0_[10] ), .Q(\count_16d_srl_r_reg_n_0_[11] ), .R(1'b0)); FDRE \count_16d_srl_r_reg[12] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(\count_16d_srl_r[0]_i_1_n_0 ), .D(\count_16d_srl_r_reg_n_0_[11] ), .Q(\count_16d_srl_r_reg_n_0_[12] ), .R(1'b0)); FDRE \count_16d_srl_r_reg[13] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(\count_16d_srl_r[0]_i_1_n_0 ), .D(\count_16d_srl_r_reg_n_0_[12] ), .Q(\count_16d_srl_r_reg_n_0_[13] ), .R(1'b0)); FDRE \count_16d_srl_r_reg[14] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(\count_16d_srl_r[0]_i_1_n_0 ), .D(\count_16d_srl_r_reg_n_0_[13] ), .Q(\count_16d_srl_r_reg_n_0_[14] ), .R(1'b0)); FDRE \count_16d_srl_r_reg[1] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(\count_16d_srl_r[0]_i_1_n_0 ), .D(\count_16d_srl_r_reg_n_0_[0] ), .Q(\count_16d_srl_r_reg_n_0_[1] ), .R(1'b0)); FDRE \count_16d_srl_r_reg[2] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(\count_16d_srl_r[0]_i_1_n_0 ), .D(\count_16d_srl_r_reg_n_0_[1] ), .Q(\count_16d_srl_r_reg_n_0_[2] ), .R(1'b0)); FDRE \count_16d_srl_r_reg[3] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(\count_16d_srl_r[0]_i_1_n_0 ), .D(\count_16d_srl_r_reg_n_0_[2] ), .Q(\count_16d_srl_r_reg_n_0_[3] ), .R(1'b0)); FDRE \count_16d_srl_r_reg[4] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(\count_16d_srl_r[0]_i_1_n_0 ), .D(\count_16d_srl_r_reg_n_0_[3] ), .Q(\count_16d_srl_r_reg_n_0_[4] ), .R(1'b0)); FDRE \count_16d_srl_r_reg[5] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(\count_16d_srl_r[0]_i_1_n_0 ), .D(\count_16d_srl_r_reg_n_0_[4] ), .Q(\count_16d_srl_r_reg_n_0_[5] ), .R(1'b0)); FDRE \count_16d_srl_r_reg[6] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(\count_16d_srl_r[0]_i_1_n_0 ), .D(\count_16d_srl_r_reg_n_0_[5] ), .Q(\count_16d_srl_r_reg_n_0_[6] ), .R(1'b0)); FDRE \count_16d_srl_r_reg[7] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(\count_16d_srl_r[0]_i_1_n_0 ), .D(\count_16d_srl_r_reg_n_0_[6] ), .Q(\count_16d_srl_r_reg_n_0_[7] ), .R(1'b0)); FDRE \count_16d_srl_r_reg[8] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(\count_16d_srl_r[0]_i_1_n_0 ), .D(\count_16d_srl_r_reg_n_0_[7] ), .Q(\count_16d_srl_r_reg_n_0_[8] ), .R(1'b0)); FDRE \count_16d_srl_r_reg[9] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(\count_16d_srl_r[0]_i_1_n_0 ), .D(\count_16d_srl_r_reg_n_0_[8] ), .Q(\count_16d_srl_r_reg_n_0_[9] ), .R(1'b0)); LUT5 #( .INIT(32'hFFBFFF80)) count_24d_flop_r_i_1 (.I0(\count_24d_srl_r_reg_n_0_[22] ), .I1(\count_13d_srl_r_reg_n_0_[11] ), .I2(\count_16d_srl_r_reg_n_0_[14] ), .I3(count_24d_flop_r0), .I4(count_24d_flop_r), .O(count_24d_flop_r_i_1_n_0)); LUT4 #( .INIT(16'h8000)) count_24d_flop_r_i_2 (.I0(count_24d_flop_r_i_3_n_0), .I1(count_24d_flop_r_i_4_n_0), .I2(count_24d_flop_r_i_5_n_0), .I3(count_24d_flop_r_i_6_n_0), .O(count_24d_flop_r0)); LUT6 #( .INIT(64'h0000000000000001)) count_24d_flop_r_i_3 (.I0(\count_24d_srl_r_reg_n_0_[9] ), .I1(\count_24d_srl_r_reg_n_0_[8] ), .I2(\count_24d_srl_r_reg_n_0_[11] ), .I3(\count_24d_srl_r_reg_n_0_[10] ), .I4(\count_24d_srl_r_reg_n_0_[6] ), .I5(\count_24d_srl_r_reg_n_0_[7] ), .O(count_24d_flop_r_i_3_n_0)); LUT6 #( .INIT(64'h0000000000000010)) count_24d_flop_r_i_4 (.I0(\count_24d_srl_r_reg_n_0_[21] ), .I1(\count_24d_srl_r_reg_n_0_[20] ), .I2(reset_r), .I3(\count_24d_srl_r_reg_n_0_[22] ), .I4(\count_24d_srl_r_reg_n_0_[18] ), .I5(\count_24d_srl_r_reg_n_0_[19] ), .O(count_24d_flop_r_i_4_n_0)); LUT6 #( .INIT(64'h0000000000000001)) count_24d_flop_r_i_5 (.I0(\count_24d_srl_r_reg_n_0_[15] ), .I1(\count_24d_srl_r_reg_n_0_[14] ), .I2(\count_24d_srl_r_reg_n_0_[17] ), .I3(\count_24d_srl_r_reg_n_0_[16] ), .I4(\count_24d_srl_r_reg_n_0_[12] ), .I5(\count_24d_srl_r_reg_n_0_[13] ), .O(count_24d_flop_r_i_5_n_0)); LUT6 #( .INIT(64'h0000000000000001)) count_24d_flop_r_i_6 (.I0(\count_24d_srl_r_reg_n_0_[3] ), .I1(\count_24d_srl_r_reg_n_0_[2] ), .I2(\count_24d_srl_r_reg_n_0_[5] ), .I3(\count_24d_srl_r_reg_n_0_[4] ), .I4(\count_24d_srl_r_reg_n_0_[0] ), .I5(\count_24d_srl_r_reg_n_0_[1] ), .O(count_24d_flop_r_i_6_n_0)); FDRE count_24d_flop_r_reg (.C(\count_24d_srl_r_reg[0]_0 ), .CE(1'b1), .D(count_24d_flop_r_i_1_n_0), .Q(count_24d_flop_r), .R(SR)); LUT3 #( .INIT(8'h8F)) \count_24d_srl_r[0]_i_1 (.I0(\count_13d_srl_r_reg_n_0_[11] ), .I1(\count_16d_srl_r_reg_n_0_[14] ), .I2(\count_16d_srl_r_reg[0]_0 ), .O(count_24d_srl_r0)); FDRE \count_24d_srl_r_reg[0] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(count_24d_srl_r0), .D(count_24d_flop_r), .Q(\count_24d_srl_r_reg_n_0_[0] ), .R(1'b0)); FDRE \count_24d_srl_r_reg[10] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(count_24d_srl_r0), .D(\count_24d_srl_r_reg_n_0_[9] ), .Q(\count_24d_srl_r_reg_n_0_[10] ), .R(1'b0)); FDRE \count_24d_srl_r_reg[11] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(count_24d_srl_r0), .D(\count_24d_srl_r_reg_n_0_[10] ), .Q(\count_24d_srl_r_reg_n_0_[11] ), .R(1'b0)); FDRE \count_24d_srl_r_reg[12] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(count_24d_srl_r0), .D(\count_24d_srl_r_reg_n_0_[11] ), .Q(\count_24d_srl_r_reg_n_0_[12] ), .R(1'b0)); FDRE \count_24d_srl_r_reg[13] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(count_24d_srl_r0), .D(\count_24d_srl_r_reg_n_0_[12] ), .Q(\count_24d_srl_r_reg_n_0_[13] ), .R(1'b0)); FDRE \count_24d_srl_r_reg[14] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(count_24d_srl_r0), .D(\count_24d_srl_r_reg_n_0_[13] ), .Q(\count_24d_srl_r_reg_n_0_[14] ), .R(1'b0)); FDRE \count_24d_srl_r_reg[15] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(count_24d_srl_r0), .D(\count_24d_srl_r_reg_n_0_[14] ), .Q(\count_24d_srl_r_reg_n_0_[15] ), .R(1'b0)); FDRE \count_24d_srl_r_reg[16] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(count_24d_srl_r0), .D(\count_24d_srl_r_reg_n_0_[15] ), .Q(\count_24d_srl_r_reg_n_0_[16] ), .R(1'b0)); FDRE \count_24d_srl_r_reg[17] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(count_24d_srl_r0), .D(\count_24d_srl_r_reg_n_0_[16] ), .Q(\count_24d_srl_r_reg_n_0_[17] ), .R(1'b0)); FDRE \count_24d_srl_r_reg[18] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(count_24d_srl_r0), .D(\count_24d_srl_r_reg_n_0_[17] ), .Q(\count_24d_srl_r_reg_n_0_[18] ), .R(1'b0)); FDRE \count_24d_srl_r_reg[19] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(count_24d_srl_r0), .D(\count_24d_srl_r_reg_n_0_[18] ), .Q(\count_24d_srl_r_reg_n_0_[19] ), .R(1'b0)); FDRE \count_24d_srl_r_reg[1] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(count_24d_srl_r0), .D(\count_24d_srl_r_reg_n_0_[0] ), .Q(\count_24d_srl_r_reg_n_0_[1] ), .R(1'b0)); FDRE \count_24d_srl_r_reg[20] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(count_24d_srl_r0), .D(\count_24d_srl_r_reg_n_0_[19] ), .Q(\count_24d_srl_r_reg_n_0_[20] ), .R(1'b0)); FDRE \count_24d_srl_r_reg[21] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(count_24d_srl_r0), .D(\count_24d_srl_r_reg_n_0_[20] ), .Q(\count_24d_srl_r_reg_n_0_[21] ), .R(1'b0)); FDRE \count_24d_srl_r_reg[22] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(count_24d_srl_r0), .D(\count_24d_srl_r_reg_n_0_[21] ), .Q(\count_24d_srl_r_reg_n_0_[22] ), .R(1'b0)); FDRE \count_24d_srl_r_reg[2] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(count_24d_srl_r0), .D(\count_24d_srl_r_reg_n_0_[1] ), .Q(\count_24d_srl_r_reg_n_0_[2] ), .R(1'b0)); FDRE \count_24d_srl_r_reg[3] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(count_24d_srl_r0), .D(\count_24d_srl_r_reg_n_0_[2] ), .Q(\count_24d_srl_r_reg_n_0_[3] ), .R(1'b0)); FDRE \count_24d_srl_r_reg[4] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(count_24d_srl_r0), .D(\count_24d_srl_r_reg_n_0_[3] ), .Q(\count_24d_srl_r_reg_n_0_[4] ), .R(1'b0)); FDRE \count_24d_srl_r_reg[5] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(count_24d_srl_r0), .D(\count_24d_srl_r_reg_n_0_[4] ), .Q(\count_24d_srl_r_reg_n_0_[5] ), .R(1'b0)); FDRE \count_24d_srl_r_reg[6] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(count_24d_srl_r0), .D(\count_24d_srl_r_reg_n_0_[5] ), .Q(\count_24d_srl_r_reg_n_0_[6] ), .R(1'b0)); FDRE \count_24d_srl_r_reg[7] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(count_24d_srl_r0), .D(\count_24d_srl_r_reg_n_0_[6] ), .Q(\count_24d_srl_r_reg_n_0_[7] ), .R(1'b0)); FDRE \count_24d_srl_r_reg[8] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(count_24d_srl_r0), .D(\count_24d_srl_r_reg_n_0_[7] ), .Q(\count_24d_srl_r_reg_n_0_[8] ), .R(1'b0)); FDRE \count_24d_srl_r_reg[9] (.C(\count_24d_srl_r_reg[0]_0 ), .CE(count_24d_srl_r0), .D(\count_24d_srl_r_reg_n_0_[8] ), .Q(\count_24d_srl_r_reg_n_0_[9] ), .R(1'b0)); LUT2 #( .INIT(4'hE)) do_cc_r_i_1 (.I0(Q), .I1(extend_cc_r), .O(do_cc_r_reg0)); FDRE reset_r_reg (.C(\count_24d_srl_r_reg[0]_0 ), .CE(1'b1), .D(SR), .Q(reset_r), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_SUPPORT_RESET_LOGIC" *) module aurora_64b66b_0_aurora_64b66b_0_SUPPORT_RESET_LOGIC (sysreset_from_support, gt_reset_out, CLK, init_clk, D, \debounce_gt_rst_r_reg[0]_0 ); output sysreset_from_support; output gt_reset_out; input CLK; input init_clk; input [0:0]D; input [0:0]\debounce_gt_rst_r_reg[0]_0 ; wire CLK; wire [0:0]D; wire SYSTEM_RESET0_n_0; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [0:3]debounce_gt_rst_r; wire [0:0]\debounce_gt_rst_r_reg[0]_0 ; wire \dly_gt_rst_r_reg[17]_srl18_n_0 ; wire gt_reset_out; wire gt_rst_r; wire gt_rst_r0_n_0; wire init_clk; wire [0:3]reset_debounce_r; wire sysreset_from_support; wire u_rst_sync_gt_n_0; wire \NLW_dly_gt_rst_r_reg[17]_srl18_Q31_UNCONNECTED ; LUT4 #( .INIT(16'h8000)) SYSTEM_RESET0 (.I0(reset_debounce_r[2]), .I1(reset_debounce_r[3]), .I2(reset_debounce_r[0]), .I3(reset_debounce_r[1]), .O(SYSTEM_RESET0_n_0)); FDRE #( .INIT(1'b1)) SYSTEM_RESET_reg (.C(CLK), .CE(1'b1), .D(SYSTEM_RESET0_n_0), .Q(sysreset_from_support), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \debounce_gt_rst_r_reg[0] (.C(init_clk), .CE(1'b1), .D(\debounce_gt_rst_r_reg[0]_0 ), .Q(debounce_gt_rst_r[0]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \debounce_gt_rst_r_reg[1] (.C(init_clk), .CE(1'b1), .D(debounce_gt_rst_r[0]), .Q(debounce_gt_rst_r[1]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \debounce_gt_rst_r_reg[2] (.C(init_clk), .CE(1'b1), .D(debounce_gt_rst_r[1]), .Q(debounce_gt_rst_r[2]), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b0)) \debounce_gt_rst_r_reg[3] (.C(init_clk), .CE(1'b1), .D(debounce_gt_rst_r[2]), .Q(debounce_gt_rst_r[3]), .R(1'b0)); (* srl_bus_name = "inst/\support_reset_logic_i/dly_gt_rst_r_reg " *) (* srl_name = "inst/\support_reset_logic_i/dly_gt_rst_r_reg[17]_srl18 " *) SRLC32E #( .INIT(32'h00000000)) \dly_gt_rst_r_reg[17]_srl18 (.A({1'b1,1'b0,1'b0,1'b0,1'b1}), .CE(1'b1), .CLK(init_clk), .D(gt_rst_r), .Q(\dly_gt_rst_r_reg[17]_srl18_n_0 ), .Q31(\NLW_dly_gt_rst_r_reg[17]_srl18_Q31_UNCONNECTED )); FDRE #( .INIT(1'b0)) \dly_gt_rst_r_reg[18] (.C(init_clk), .CE(1'b1), .D(\dly_gt_rst_r_reg[17]_srl18_n_0 ), .Q(gt_reset_out), .R(1'b0)); LUT4 #( .INIT(16'h8000)) gt_rst_r0 (.I0(debounce_gt_rst_r[2]), .I1(debounce_gt_rst_r[3]), .I2(debounce_gt_rst_r[0]), .I3(debounce_gt_rst_r[1]), .O(gt_rst_r0_n_0)); FDRE #( .INIT(1'b0)) gt_rst_r_reg (.C(init_clk), .CE(1'b1), .D(gt_rst_r0_n_0), .Q(gt_rst_r), .R(1'b0)); FDSE #( .INIT(1'b0)) \reset_debounce_r_reg[0] (.C(CLK), .CE(1'b1), .D(D), .Q(reset_debounce_r[0]), .S(u_rst_sync_gt_n_0)); FDSE #( .INIT(1'b0)) \reset_debounce_r_reg[1] (.C(CLK), .CE(1'b1), .D(reset_debounce_r[0]), .Q(reset_debounce_r[1]), .S(u_rst_sync_gt_n_0)); FDSE #( .INIT(1'b0)) \reset_debounce_r_reg[2] (.C(CLK), .CE(1'b1), .D(reset_debounce_r[1]), .Q(reset_debounce_r[2]), .S(u_rst_sync_gt_n_0)); FDSE #( .INIT(1'b0)) \reset_debounce_r_reg[3] (.C(CLK), .CE(1'b1), .D(reset_debounce_r[2]), .Q(reset_debounce_r[3]), .S(u_rst_sync_gt_n_0)); aurora_64b66b_0_aurora_64b66b_0_rst_sync_1 u_rst_sync_gt (.CLK(CLK), .SS(u_rst_sync_gt_n_0), .in0(gt_rst_r)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_SYM_DEC" *) module aurora_64b66b_0_aurora_64b66b_0_SYM_DEC (rx_pe_data_v_i, illegal_btf_i, RX_IDLE, remote_ready_i, \RX_PE_DATA_reg[0]_0 , rxdatavalid_i, \RX_DATA_REG_reg[0]_0 , SR, \RX_DATA_REG_reg[0]_1 , dout, \remote_rdy_cntr_reg[2]_0 ); output rx_pe_data_v_i; output illegal_btf_i; output RX_IDLE; output remote_ready_i; output [63:0]\RX_PE_DATA_reg[0]_0 ; input rxdatavalid_i; input \RX_DATA_REG_reg[0]_0 ; input [0:0]SR; input \RX_DATA_REG_reg[0]_1 ; input [65:0]dout; input \remote_rdy_cntr_reg[2]_0 ; wire ILLEGAL_BTF0; wire ILLEGAL_BTF_i_2_n_0; wire ILLEGAL_BTF_i_3_n_0; wire ILLEGAL_BTF_i_4_n_0; wire ILLEGAL_BTF_i_5_n_0; wire RXDATAVALID_IN_REG; wire \RX_DATA_REG_reg[0]_0 ; wire \RX_DATA_REG_reg[0]_1 ; wire RX_IDLE; wire RX_IDLE_i_2_n_0; wire RX_NA_IDLE; wire RX_NA_IDLE_i_2_n_0; wire [63:0]\RX_PE_DATA_reg[0]_0 ; wire [0:0]SR; wire [65:0]dout; wire illegal_btf_i; wire [15:0]p_0_in; wire [4:0]p_0_in__0; wire [0:2]remote_rdy_cntr; wire remote_rdy_cntr01_out; wire \remote_rdy_cntr[0]_i_1_n_0 ; wire \remote_rdy_cntr[0]_i_3_n_0 ; wire \remote_rdy_cntr[0]_i_4_n_0 ; wire \remote_rdy_cntr[1]_i_1_n_0 ; wire \remote_rdy_cntr[2]_i_1_n_0 ; wire \remote_rdy_cntr_reg[2]_0 ; wire remote_ready_det; wire remote_ready_det0; wire remote_ready_i; wire rx_idle_c; wire rx_na_idle_c; wire \rx_na_idles_cntr[4]_i_1_n_0 ; wire [4:0]rx_na_idles_cntr_reg; wire rx_pe_data_v_i; wire [63:16]rxdata_s; wire rxdatavalid_i; wire [0:1]sync_header_c; wire valid_d; LUT6 #( .INIT(64'hFFEF0000EEEB0000)) ILLEGAL_BTF_i_1 (.I0(ILLEGAL_BTF_i_2_n_0), .I1(p_0_in[6]), .I2(p_0_in[4]), .I3(p_0_in[7]), .I4(ILLEGAL_BTF_i_3_n_0), .I5(p_0_in[5]), .O(ILLEGAL_BTF0)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFEFF)) ILLEGAL_BTF_i_2 (.I0(ILLEGAL_BTF_i_4_n_0), .I1(p_0_in[9]), .I2(p_0_in[8]), .I3(p_0_in[11]), .I4(p_0_in[10]), .I5(ILLEGAL_BTF_i_5_n_0), .O(ILLEGAL_BTF_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair109" *) LUT4 #( .INIT(16'h0800)) ILLEGAL_BTF_i_3 (.I0(RXDATAVALID_IN_REG), .I1(sync_header_c[0]), .I2(sync_header_c[1]), .I3(\remote_rdy_cntr_reg[2]_0 ), .O(ILLEGAL_BTF_i_3_n_0)); LUT4 #( .INIT(16'hFF7F)) ILLEGAL_BTF_i_4 (.I0(p_0_in[13]), .I1(p_0_in[12]), .I2(p_0_in[14]), .I3(p_0_in[15]), .O(ILLEGAL_BTF_i_4_n_0)); LUT4 #( .INIT(16'hFFFE)) ILLEGAL_BTF_i_5 (.I0(p_0_in[1]), .I1(p_0_in[0]), .I2(p_0_in[3]), .I3(p_0_in[2]), .O(ILLEGAL_BTF_i_5_n_0)); FDRE ILLEGAL_BTF_reg (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(ILLEGAL_BTF0), .Q(illegal_btf_i), .R(SR)); FDRE RXDATAVALID_IN_REG_reg (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(rxdatavalid_i), .Q(RXDATAVALID_IN_REG), .R(1'b0)); FDRE \RX_DATA_REG_reg[0] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[0]), .Q(rxdata_s[56]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[10] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[10]), .Q(rxdata_s[50]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[11] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[11]), .Q(rxdata_s[51]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[12] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[12]), .Q(rxdata_s[52]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[13] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[13]), .Q(rxdata_s[53]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[14] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[14]), .Q(rxdata_s[54]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[15] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[15]), .Q(rxdata_s[55]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[16] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[16]), .Q(rxdata_s[40]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[17] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[17]), .Q(rxdata_s[41]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[18] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[18]), .Q(rxdata_s[42]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[19] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[19]), .Q(rxdata_s[43]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[1] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[1]), .Q(rxdata_s[57]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[20] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[20]), .Q(rxdata_s[44]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[21] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[21]), .Q(rxdata_s[45]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[22] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[22]), .Q(rxdata_s[46]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[23] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[23]), .Q(rxdata_s[47]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[24] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[24]), .Q(rxdata_s[32]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[25] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[25]), .Q(rxdata_s[33]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[26] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[26]), .Q(rxdata_s[34]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[27] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[27]), .Q(rxdata_s[35]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[28] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[28]), .Q(rxdata_s[36]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[29] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[29]), .Q(rxdata_s[37]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[2] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[2]), .Q(rxdata_s[58]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[30] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[30]), .Q(rxdata_s[38]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[31] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[31]), .Q(rxdata_s[39]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[32] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[32]), .Q(rxdata_s[24]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[33] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[33]), .Q(rxdata_s[25]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[34] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[34]), .Q(rxdata_s[26]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[35] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[35]), .Q(rxdata_s[27]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[36] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[36]), .Q(rxdata_s[28]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[37] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[37]), .Q(rxdata_s[29]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[38] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[38]), .Q(rxdata_s[30]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[39] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[39]), .Q(rxdata_s[31]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[3] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[3]), .Q(rxdata_s[59]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[40] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[40]), .Q(rxdata_s[16]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[41] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[41]), .Q(rxdata_s[17]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[42] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[42]), .Q(rxdata_s[18]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[43] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[43]), .Q(rxdata_s[19]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[44] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[44]), .Q(rxdata_s[20]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[45] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[45]), .Q(rxdata_s[21]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[46] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[46]), .Q(rxdata_s[22]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[47] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[47]), .Q(rxdata_s[23]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[48] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[48]), .Q(p_0_in[0]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[49] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[49]), .Q(p_0_in[1]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[4] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[4]), .Q(rxdata_s[60]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[50] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[50]), .Q(p_0_in[2]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[51] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[51]), .Q(p_0_in[3]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[52] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[52]), .Q(p_0_in[4]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[53] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[53]), .Q(p_0_in[5]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[54] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[54]), .Q(p_0_in[6]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[55] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[55]), .Q(p_0_in[7]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[56] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[56]), .Q(p_0_in[8]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[57] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[57]), .Q(p_0_in[9]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[58] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[58]), .Q(p_0_in[10]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[59] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[59]), .Q(p_0_in[11]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[5] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[5]), .Q(rxdata_s[61]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[60] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[60]), .Q(p_0_in[12]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[61] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[61]), .Q(p_0_in[13]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[62] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[62]), .Q(p_0_in[14]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[63] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[63]), .Q(p_0_in[15]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[6] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[6]), .Q(rxdata_s[62]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[7] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[7]), .Q(rxdata_s[63]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[8] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[8]), .Q(rxdata_s[48]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE \RX_DATA_REG_reg[9] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[9]), .Q(rxdata_s[49]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE RX_HEADER_0_REG_reg (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[64]), .Q(sync_header_c[1]), .R(\RX_DATA_REG_reg[0]_1 )); FDRE RX_HEADER_1_REG_reg (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(dout[65]), .Q(sync_header_c[0]), .R(\RX_DATA_REG_reg[0]_1 )); LUT6 #( .INIT(64'h0000000000100000)) RX_IDLE_i_1 (.I0(RX_IDLE_i_2_n_0), .I1(p_0_in[5]), .I2(p_0_in[4]), .I3(sync_header_c[1]), .I4(sync_header_c[0]), .I5(ILLEGAL_BTF_i_2_n_0), .O(rx_idle_c)); LUT2 #( .INIT(4'hE)) RX_IDLE_i_2 (.I0(p_0_in[6]), .I1(p_0_in[7]), .O(RX_IDLE_i_2_n_0)); FDRE RX_IDLE_reg (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(rx_idle_c), .Q(RX_IDLE), .R(SR)); LUT6 #( .INIT(64'h0000000000000080)) RX_NA_IDLE_i_1 (.I0(RX_NA_IDLE_i_2_n_0), .I1(p_0_in[5]), .I2(p_0_in[4]), .I3(p_0_in[7]), .I4(p_0_in[6]), .I5(ILLEGAL_BTF_i_2_n_0), .O(rx_na_idle_c)); (* SOFT_HLUTNM = "soft_lutpair109" *) LUT3 #( .INIT(8'h40)) RX_NA_IDLE_i_2 (.I0(sync_header_c[1]), .I1(sync_header_c[0]), .I2(RXDATAVALID_IN_REG), .O(RX_NA_IDLE_i_2_n_0)); FDRE RX_NA_IDLE_reg (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(rx_na_idle_c), .Q(RX_NA_IDLE), .R(SR)); LUT3 #( .INIT(8'h40)) RX_PE_DATA_V_i_1 (.I0(sync_header_c[0]), .I1(RXDATAVALID_IN_REG), .I2(sync_header_c[1]), .O(valid_d)); FDRE RX_PE_DATA_V_reg (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(valid_d), .Q(rx_pe_data_v_i), .R(SR)); FDRE \RX_PE_DATA_reg[0] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[63]), .Q(\RX_PE_DATA_reg[0]_0 [63]), .R(SR)); FDRE \RX_PE_DATA_reg[10] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[53]), .Q(\RX_PE_DATA_reg[0]_0 [53]), .R(SR)); FDRE \RX_PE_DATA_reg[11] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[52]), .Q(\RX_PE_DATA_reg[0]_0 [52]), .R(SR)); FDRE \RX_PE_DATA_reg[12] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[51]), .Q(\RX_PE_DATA_reg[0]_0 [51]), .R(SR)); FDRE \RX_PE_DATA_reg[13] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[50]), .Q(\RX_PE_DATA_reg[0]_0 [50]), .R(SR)); FDRE \RX_PE_DATA_reg[14] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[49]), .Q(\RX_PE_DATA_reg[0]_0 [49]), .R(SR)); FDRE \RX_PE_DATA_reg[15] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[48]), .Q(\RX_PE_DATA_reg[0]_0 [48]), .R(SR)); FDRE \RX_PE_DATA_reg[16] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[47]), .Q(\RX_PE_DATA_reg[0]_0 [47]), .R(SR)); FDRE \RX_PE_DATA_reg[17] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[46]), .Q(\RX_PE_DATA_reg[0]_0 [46]), .R(SR)); FDRE \RX_PE_DATA_reg[18] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[45]), .Q(\RX_PE_DATA_reg[0]_0 [45]), .R(SR)); FDRE \RX_PE_DATA_reg[19] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[44]), .Q(\RX_PE_DATA_reg[0]_0 [44]), .R(SR)); FDRE \RX_PE_DATA_reg[1] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[62]), .Q(\RX_PE_DATA_reg[0]_0 [62]), .R(SR)); FDRE \RX_PE_DATA_reg[20] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[43]), .Q(\RX_PE_DATA_reg[0]_0 [43]), .R(SR)); FDRE \RX_PE_DATA_reg[21] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[42]), .Q(\RX_PE_DATA_reg[0]_0 [42]), .R(SR)); FDRE \RX_PE_DATA_reg[22] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[41]), .Q(\RX_PE_DATA_reg[0]_0 [41]), .R(SR)); FDRE \RX_PE_DATA_reg[23] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[40]), .Q(\RX_PE_DATA_reg[0]_0 [40]), .R(SR)); FDRE \RX_PE_DATA_reg[24] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[39]), .Q(\RX_PE_DATA_reg[0]_0 [39]), .R(SR)); FDRE \RX_PE_DATA_reg[25] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[38]), .Q(\RX_PE_DATA_reg[0]_0 [38]), .R(SR)); FDRE \RX_PE_DATA_reg[26] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[37]), .Q(\RX_PE_DATA_reg[0]_0 [37]), .R(SR)); FDRE \RX_PE_DATA_reg[27] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[36]), .Q(\RX_PE_DATA_reg[0]_0 [36]), .R(SR)); FDRE \RX_PE_DATA_reg[28] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[35]), .Q(\RX_PE_DATA_reg[0]_0 [35]), .R(SR)); FDRE \RX_PE_DATA_reg[29] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[34]), .Q(\RX_PE_DATA_reg[0]_0 [34]), .R(SR)); FDRE \RX_PE_DATA_reg[2] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[61]), .Q(\RX_PE_DATA_reg[0]_0 [61]), .R(SR)); FDRE \RX_PE_DATA_reg[30] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[33]), .Q(\RX_PE_DATA_reg[0]_0 [33]), .R(SR)); FDRE \RX_PE_DATA_reg[31] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[32]), .Q(\RX_PE_DATA_reg[0]_0 [32]), .R(SR)); FDRE \RX_PE_DATA_reg[32] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[31]), .Q(\RX_PE_DATA_reg[0]_0 [31]), .R(SR)); FDRE \RX_PE_DATA_reg[33] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[30]), .Q(\RX_PE_DATA_reg[0]_0 [30]), .R(SR)); FDRE \RX_PE_DATA_reg[34] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[29]), .Q(\RX_PE_DATA_reg[0]_0 [29]), .R(SR)); FDRE \RX_PE_DATA_reg[35] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[28]), .Q(\RX_PE_DATA_reg[0]_0 [28]), .R(SR)); FDRE \RX_PE_DATA_reg[36] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[27]), .Q(\RX_PE_DATA_reg[0]_0 [27]), .R(SR)); FDRE \RX_PE_DATA_reg[37] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[26]), .Q(\RX_PE_DATA_reg[0]_0 [26]), .R(SR)); FDRE \RX_PE_DATA_reg[38] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[25]), .Q(\RX_PE_DATA_reg[0]_0 [25]), .R(SR)); FDRE \RX_PE_DATA_reg[39] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[24]), .Q(\RX_PE_DATA_reg[0]_0 [24]), .R(SR)); FDRE \RX_PE_DATA_reg[3] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[60]), .Q(\RX_PE_DATA_reg[0]_0 [60]), .R(SR)); FDRE \RX_PE_DATA_reg[40] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[23]), .Q(\RX_PE_DATA_reg[0]_0 [23]), .R(SR)); FDRE \RX_PE_DATA_reg[41] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[22]), .Q(\RX_PE_DATA_reg[0]_0 [22]), .R(SR)); FDRE \RX_PE_DATA_reg[42] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[21]), .Q(\RX_PE_DATA_reg[0]_0 [21]), .R(SR)); FDRE \RX_PE_DATA_reg[43] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[20]), .Q(\RX_PE_DATA_reg[0]_0 [20]), .R(SR)); FDRE \RX_PE_DATA_reg[44] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[19]), .Q(\RX_PE_DATA_reg[0]_0 [19]), .R(SR)); FDRE \RX_PE_DATA_reg[45] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[18]), .Q(\RX_PE_DATA_reg[0]_0 [18]), .R(SR)); FDRE \RX_PE_DATA_reg[46] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[17]), .Q(\RX_PE_DATA_reg[0]_0 [17]), .R(SR)); FDRE \RX_PE_DATA_reg[47] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[16]), .Q(\RX_PE_DATA_reg[0]_0 [16]), .R(SR)); FDRE \RX_PE_DATA_reg[48] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(p_0_in[7]), .Q(\RX_PE_DATA_reg[0]_0 [15]), .R(SR)); FDRE \RX_PE_DATA_reg[49] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(p_0_in[6]), .Q(\RX_PE_DATA_reg[0]_0 [14]), .R(SR)); FDRE \RX_PE_DATA_reg[4] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[59]), .Q(\RX_PE_DATA_reg[0]_0 [59]), .R(SR)); FDRE \RX_PE_DATA_reg[50] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(p_0_in[5]), .Q(\RX_PE_DATA_reg[0]_0 [13]), .R(SR)); FDRE \RX_PE_DATA_reg[51] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(p_0_in[4]), .Q(\RX_PE_DATA_reg[0]_0 [12]), .R(SR)); FDRE \RX_PE_DATA_reg[52] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(p_0_in[3]), .Q(\RX_PE_DATA_reg[0]_0 [11]), .R(SR)); FDRE \RX_PE_DATA_reg[53] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(p_0_in[2]), .Q(\RX_PE_DATA_reg[0]_0 [10]), .R(SR)); FDRE \RX_PE_DATA_reg[54] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(p_0_in[1]), .Q(\RX_PE_DATA_reg[0]_0 [9]), .R(SR)); FDRE \RX_PE_DATA_reg[55] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(p_0_in[0]), .Q(\RX_PE_DATA_reg[0]_0 [8]), .R(SR)); FDRE \RX_PE_DATA_reg[56] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(p_0_in[15]), .Q(\RX_PE_DATA_reg[0]_0 [7]), .R(SR)); FDRE \RX_PE_DATA_reg[57] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(p_0_in[14]), .Q(\RX_PE_DATA_reg[0]_0 [6]), .R(SR)); FDRE \RX_PE_DATA_reg[58] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(p_0_in[13]), .Q(\RX_PE_DATA_reg[0]_0 [5]), .R(SR)); FDRE \RX_PE_DATA_reg[59] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(p_0_in[12]), .Q(\RX_PE_DATA_reg[0]_0 [4]), .R(SR)); FDRE \RX_PE_DATA_reg[5] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[58]), .Q(\RX_PE_DATA_reg[0]_0 [58]), .R(SR)); FDRE \RX_PE_DATA_reg[60] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(p_0_in[11]), .Q(\RX_PE_DATA_reg[0]_0 [3]), .R(SR)); FDRE \RX_PE_DATA_reg[61] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(p_0_in[10]), .Q(\RX_PE_DATA_reg[0]_0 [2]), .R(SR)); FDRE \RX_PE_DATA_reg[62] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(p_0_in[9]), .Q(\RX_PE_DATA_reg[0]_0 [1]), .R(SR)); FDRE \RX_PE_DATA_reg[63] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(p_0_in[8]), .Q(\RX_PE_DATA_reg[0]_0 [0]), .R(SR)); FDRE \RX_PE_DATA_reg[6] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[57]), .Q(\RX_PE_DATA_reg[0]_0 [57]), .R(SR)); FDRE \RX_PE_DATA_reg[7] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[56]), .Q(\RX_PE_DATA_reg[0]_0 [56]), .R(SR)); FDRE \RX_PE_DATA_reg[8] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[55]), .Q(\RX_PE_DATA_reg[0]_0 [55]), .R(SR)); FDRE \RX_PE_DATA_reg[9] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(valid_d), .D(rxdata_s[54]), .Q(\RX_PE_DATA_reg[0]_0 [54]), .R(SR)); LUT6 #( .INIT(64'h00004000FFFFFFFF)) \remote_rdy_cntr[0]_i_1 (.I0(\remote_rdy_cntr[0]_i_4_n_0 ), .I1(remote_rdy_cntr[0]), .I2(remote_rdy_cntr[2]), .I3(remote_rdy_cntr[1]), .I4(rx_na_idles_cntr_reg[4]), .I5(\remote_rdy_cntr_reg[2]_0 ), .O(\remote_rdy_cntr[0]_i_1_n_0 )); LUT4 #( .INIT(16'h7F00)) \remote_rdy_cntr[0]_i_2 (.I0(remote_rdy_cntr[0]), .I1(remote_rdy_cntr[2]), .I2(remote_rdy_cntr[1]), .I3(remote_ready_det), .O(remote_rdy_cntr01_out)); (* SOFT_HLUTNM = "soft_lutpair111" *) LUT3 #( .INIT(8'h78)) \remote_rdy_cntr[0]_i_3 (.I0(remote_rdy_cntr[1]), .I1(remote_rdy_cntr[2]), .I2(remote_rdy_cntr[0]), .O(\remote_rdy_cntr[0]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair108" *) LUT4 #( .INIT(16'h7FFF)) \remote_rdy_cntr[0]_i_4 (.I0(rx_na_idles_cntr_reg[2]), .I1(rx_na_idles_cntr_reg[0]), .I2(rx_na_idles_cntr_reg[1]), .I3(rx_na_idles_cntr_reg[3]), .O(\remote_rdy_cntr[0]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair112" *) LUT2 #( .INIT(4'h6)) \remote_rdy_cntr[1]_i_1 (.I0(remote_rdy_cntr[2]), .I1(remote_rdy_cntr[1]), .O(\remote_rdy_cntr[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair112" *) LUT1 #( .INIT(2'h1)) \remote_rdy_cntr[2]_i_1 (.I0(remote_rdy_cntr[2]), .O(\remote_rdy_cntr[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \remote_rdy_cntr_reg[0] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(remote_rdy_cntr01_out), .D(\remote_rdy_cntr[0]_i_3_n_0 ), .Q(remote_rdy_cntr[0]), .R(\remote_rdy_cntr[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \remote_rdy_cntr_reg[1] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(remote_rdy_cntr01_out), .D(\remote_rdy_cntr[1]_i_1_n_0 ), .Q(remote_rdy_cntr[1]), .R(\remote_rdy_cntr[0]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \remote_rdy_cntr_reg[2] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(remote_rdy_cntr01_out), .D(\remote_rdy_cntr[2]_i_1_n_0 ), .Q(remote_rdy_cntr[2]), .R(\remote_rdy_cntr[0]_i_1_n_0 )); LUT6 #( .INIT(64'h0000000000000020)) remote_ready_det_i_1 (.I0(ILLEGAL_BTF_i_3_n_0), .I1(p_0_in[5]), .I2(p_0_in[4]), .I3(p_0_in[7]), .I4(p_0_in[6]), .I5(ILLEGAL_BTF_i_2_n_0), .O(remote_ready_det0)); FDRE remote_ready_det_reg (.C(\RX_DATA_REG_reg[0]_0 ), .CE(1'b1), .D(remote_ready_det0), .Q(remote_ready_det), .R(SR)); (* SOFT_HLUTNM = "soft_lutpair111" *) LUT3 #( .INIT(8'h80)) remote_ready_r_i_1 (.I0(remote_rdy_cntr[0]), .I1(remote_rdy_cntr[2]), .I2(remote_rdy_cntr[1]), .O(remote_ready_i)); (* SOFT_HLUTNM = "soft_lutpair113" *) LUT1 #( .INIT(2'h1)) \rx_na_idles_cntr[0]_i_1 (.I0(rx_na_idles_cntr_reg[0]), .O(p_0_in__0[0])); (* SOFT_HLUTNM = "soft_lutpair113" *) LUT2 #( .INIT(4'h6)) \rx_na_idles_cntr[1]_i_1 (.I0(rx_na_idles_cntr_reg[0]), .I1(rx_na_idles_cntr_reg[1]), .O(p_0_in__0[1])); (* SOFT_HLUTNM = "soft_lutpair110" *) LUT3 #( .INIT(8'h78)) \rx_na_idles_cntr[2]_i_1 (.I0(rx_na_idles_cntr_reg[1]), .I1(rx_na_idles_cntr_reg[0]), .I2(rx_na_idles_cntr_reg[2]), .O(p_0_in__0[2])); (* SOFT_HLUTNM = "soft_lutpair110" *) LUT4 #( .INIT(16'h7F80)) \rx_na_idles_cntr[3]_i_1 (.I0(rx_na_idles_cntr_reg[2]), .I1(rx_na_idles_cntr_reg[0]), .I2(rx_na_idles_cntr_reg[1]), .I3(rx_na_idles_cntr_reg[3]), .O(p_0_in__0[3])); LUT4 #( .INIT(16'h7FFF)) \rx_na_idles_cntr[4]_i_1 (.I0(remote_rdy_cntr[0]), .I1(remote_rdy_cntr[2]), .I2(remote_rdy_cntr[1]), .I3(\remote_rdy_cntr_reg[2]_0 ), .O(\rx_na_idles_cntr[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair108" *) LUT5 #( .INIT(32'h7FFF8000)) \rx_na_idles_cntr[4]_i_2 (.I0(rx_na_idles_cntr_reg[3]), .I1(rx_na_idles_cntr_reg[1]), .I2(rx_na_idles_cntr_reg[0]), .I3(rx_na_idles_cntr_reg[2]), .I4(rx_na_idles_cntr_reg[4]), .O(p_0_in__0[4])); FDRE #( .INIT(1'b0)) \rx_na_idles_cntr_reg[0] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(RX_NA_IDLE), .D(p_0_in__0[0]), .Q(rx_na_idles_cntr_reg[0]), .R(\rx_na_idles_cntr[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \rx_na_idles_cntr_reg[1] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(RX_NA_IDLE), .D(p_0_in__0[1]), .Q(rx_na_idles_cntr_reg[1]), .R(\rx_na_idles_cntr[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \rx_na_idles_cntr_reg[2] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(RX_NA_IDLE), .D(p_0_in__0[2]), .Q(rx_na_idles_cntr_reg[2]), .R(\rx_na_idles_cntr[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \rx_na_idles_cntr_reg[3] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(RX_NA_IDLE), .D(p_0_in__0[3]), .Q(rx_na_idles_cntr_reg[3]), .R(\rx_na_idles_cntr[4]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \rx_na_idles_cntr_reg[4] (.C(\RX_DATA_REG_reg[0]_0 ), .CE(RX_NA_IDLE), .D(p_0_in__0[4]), .Q(rx_na_idles_cntr_reg[4]), .R(\rx_na_idles_cntr[4]_i_1_n_0 )); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_SYM_GEN" *) module aurora_64b66b_0_aurora_64b66b_0_SYM_GEN (stg5_reg, D, tempData, \TX_DATA_reg[63]_0 , stg1_aurora_64b66b_0_cdc_to_reg, stg5_reg_0, txdatavalid_symgen_i, gen_na_idles_i, tx_pe_data_v_i, TX_HEADER_1_reg_0, channel_up_tx_if, Q, scrambler, \TX_DATA_reg[59]_0 , \TX_DATA_reg[55]_0 , \TX_DATA_reg[63]_1 , gen_ch_bond_i, gen_cc_i); output stg5_reg; output [1:0]D; output [5:0]tempData; output [57:0]\TX_DATA_reg[63]_0 ; input stg1_aurora_64b66b_0_cdc_to_reg; input stg5_reg_0; input txdatavalid_symgen_i; input gen_na_idles_i; input tx_pe_data_v_i; input TX_HEADER_1_reg_0; input channel_up_tx_if; input [59:0]Q; input [11:0]scrambler; input \TX_DATA_reg[59]_0 ; input [3:0]\TX_DATA_reg[55]_0 ; input \TX_DATA_reg[63]_1 ; input gen_ch_bond_i; input gen_cc_i; wire [1:0]D; wire [59:0]Q; wire \TX_DATA[62]_i_1_n_0 ; wire [3:0]\TX_DATA_reg[55]_0 ; wire \TX_DATA_reg[59]_0 ; wire [57:0]\TX_DATA_reg[63]_0 ; wire \TX_DATA_reg[63]_1 ; wire TX_HEADER_1_reg_0; wire channel_up_tx_if; wire gen_cc_i; wire gen_ch_bond_i; wire gen_na_idles_i; wire [11:0]scrambler; wire stg1_aurora_64b66b_0_cdc_to_reg; wire stg5_reg; wire stg5_reg_0; wire [5:0]tempData; wire [58:63]tx_data_i; wire tx_pe_data_v_i; wire txdatavalid_symgen_i; wire u_pma_init_data_sync_n_1; wire u_pma_init_data_sync_n_2; wire u_pma_init_data_sync_n_3; wire u_pma_init_data_sync_n_4; wire u_pma_init_data_sync_n_5; wire u_pma_init_data_sync_n_6; LUT6 #( .INIT(64'h5555545500000000)) \TX_DATA[62]_i_1 (.I0(stg5_reg), .I1(gen_ch_bond_i), .I2(gen_cc_i), .I3(tx_pe_data_v_i), .I4(gen_na_idles_i), .I5(\TX_DATA_reg[59]_0 ), .O(\TX_DATA[62]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[0] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[52]), .Q(tx_data_i[63]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[10] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[46]), .Q(\TX_DATA_reg[63]_0 [4]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[11] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[47]), .Q(\TX_DATA_reg[63]_0 [5]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[12] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[48]), .Q(\TX_DATA_reg[63]_0 [6]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[13] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[49]), .Q(\TX_DATA_reg[63]_0 [7]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[14] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[50]), .Q(\TX_DATA_reg[63]_0 [8]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[15] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[51]), .Q(\TX_DATA_reg[63]_0 [9]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[16] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[36]), .Q(\TX_DATA_reg[63]_0 [10]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[17] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[37]), .Q(\TX_DATA_reg[63]_0 [11]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[18] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[38]), .Q(\TX_DATA_reg[63]_0 [12]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[19] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[39]), .Q(\TX_DATA_reg[63]_0 [13]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[1] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[53]), .Q(tx_data_i[62]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[20] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[40]), .Q(\TX_DATA_reg[63]_0 [14]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[21] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[41]), .Q(\TX_DATA_reg[63]_0 [15]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[22] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[42]), .Q(\TX_DATA_reg[63]_0 [16]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[23] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[43]), .Q(\TX_DATA_reg[63]_0 [17]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[24] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[28]), .Q(\TX_DATA_reg[63]_0 [18]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[25] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[29]), .Q(\TX_DATA_reg[63]_0 [19]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[26] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[30]), .Q(\TX_DATA_reg[63]_0 [20]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[27] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[31]), .Q(\TX_DATA_reg[63]_0 [21]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[28] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[32]), .Q(\TX_DATA_reg[63]_0 [22]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[29] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[33]), .Q(\TX_DATA_reg[63]_0 [23]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[2] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[54]), .Q(tx_data_i[61]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[30] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[34]), .Q(\TX_DATA_reg[63]_0 [24]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[31] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[35]), .Q(\TX_DATA_reg[63]_0 [25]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[32] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[20]), .Q(\TX_DATA_reg[63]_0 [26]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[33] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[21]), .Q(\TX_DATA_reg[63]_0 [27]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[34] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[22]), .Q(\TX_DATA_reg[63]_0 [28]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[35] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[23]), .Q(\TX_DATA_reg[63]_0 [29]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[36] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[24]), .Q(\TX_DATA_reg[63]_0 [30]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[37] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[25]), .Q(\TX_DATA_reg[63]_0 [31]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[38] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[26]), .Q(\TX_DATA_reg[63]_0 [32]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[39] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[27]), .Q(\TX_DATA_reg[63]_0 [33]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[3] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[55]), .Q(tx_data_i[60]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[40] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[12]), .Q(\TX_DATA_reg[63]_0 [34]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[41] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[13]), .Q(\TX_DATA_reg[63]_0 [35]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[42] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[14]), .Q(\TX_DATA_reg[63]_0 [36]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[43] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[15]), .Q(\TX_DATA_reg[63]_0 [37]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[44] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[16]), .Q(\TX_DATA_reg[63]_0 [38]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[45] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[17]), .Q(\TX_DATA_reg[63]_0 [39]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[46] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[18]), .Q(\TX_DATA_reg[63]_0 [40]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[47] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[19]), .Q(\TX_DATA_reg[63]_0 [41]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[48] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[8]), .Q(\TX_DATA_reg[63]_0 [42]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[49] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[9]), .Q(\TX_DATA_reg[63]_0 [43]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[4] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[56]), .Q(tx_data_i[59]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[50] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[10]), .Q(\TX_DATA_reg[63]_0 [44]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[51] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[11]), .Q(\TX_DATA_reg[63]_0 [45]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[52] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(\TX_DATA_reg[55]_0 [0]), .Q(\TX_DATA_reg[63]_0 [46]), .R(1'b0)); FDRE #( .INIT(1'b0)) \TX_DATA_reg[53] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(\TX_DATA_reg[55]_0 [1]), .Q(\TX_DATA_reg[63]_0 [47]), .R(1'b0)); FDRE #( .INIT(1'b0)) \TX_DATA_reg[54] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(\TX_DATA_reg[55]_0 [2]), .Q(\TX_DATA_reg[63]_0 [48]), .R(1'b0)); FDRE #( .INIT(1'b0)) \TX_DATA_reg[55] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(\TX_DATA_reg[55]_0 [3]), .Q(\TX_DATA_reg[63]_0 [49]), .R(1'b0)); FDRE #( .INIT(1'b0)) \TX_DATA_reg[56] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[0]), .Q(\TX_DATA_reg[63]_0 [50]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[57] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[1]), .Q(\TX_DATA_reg[63]_0 [51]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[58] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[2]), .Q(\TX_DATA_reg[63]_0 [52]), .R(\TX_DATA_reg[63]_1 )); FDSE #( .INIT(1'b0)) \TX_DATA_reg[59] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(u_pma_init_data_sync_n_3), .Q(\TX_DATA_reg[63]_0 [53]), .S(\TX_DATA[62]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[5] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[57]), .Q(tx_data_i[58]), .R(\TX_DATA_reg[63]_1 )); FDSE #( .INIT(1'b0)) \TX_DATA_reg[60] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(u_pma_init_data_sync_n_4), .Q(\TX_DATA_reg[63]_0 [54]), .S(\TX_DATA[62]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \TX_DATA_reg[61] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(u_pma_init_data_sync_n_5), .Q(\TX_DATA_reg[63]_0 [55]), .S(\TX_DATA[62]_i_1_n_0 )); FDSE #( .INIT(1'b0)) \TX_DATA_reg[62] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(u_pma_init_data_sync_n_6), .Q(\TX_DATA_reg[63]_0 [56]), .S(\TX_DATA[62]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[63] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[7]), .Q(\TX_DATA_reg[63]_0 [57]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[6] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[58]), .Q(\TX_DATA_reg[63]_0 [0]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[7] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[59]), .Q(\TX_DATA_reg[63]_0 [1]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[8] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[44]), .Q(\TX_DATA_reg[63]_0 [2]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b0)) \TX_DATA_reg[9] (.C(stg5_reg_0), .CE(\TX_DATA_reg[59]_0 ), .D(Q[45]), .Q(\TX_DATA_reg[63]_0 [3]), .R(\TX_DATA_reg[63]_1 )); FDRE #( .INIT(1'b1)) TX_HEADER_0_reg (.C(stg5_reg_0), .CE(1'b1), .D(u_pma_init_data_sync_n_2), .Q(D[0]), .R(1'b0)); FDRE #( .INIT(1'b0)) TX_HEADER_1_reg (.C(stg5_reg_0), .CE(1'b1), .D(u_pma_init_data_sync_n_1), .Q(D[1]), .R(1'b0)); LUT5 #( .INIT(32'h96696996)) \scrambler[0]_i_1 (.I0(\TX_DATA_reg[63]_0 [33]), .I1(scrambler[0]), .I2(tx_data_i[63]), .I3(\TX_DATA_reg[63]_0 [52]), .I4(scrambler[6]), .O(tempData[0])); LUT5 #( .INIT(32'h96696996)) \scrambler[1]_i_1 (.I0(\TX_DATA_reg[63]_0 [34]), .I1(scrambler[1]), .I2(tx_data_i[62]), .I3(\TX_DATA_reg[63]_0 [53]), .I4(scrambler[7]), .O(tempData[1])); LUT5 #( .INIT(32'h96696996)) \scrambler[2]_i_1 (.I0(\TX_DATA_reg[63]_0 [35]), .I1(scrambler[2]), .I2(tx_data_i[61]), .I3(\TX_DATA_reg[63]_0 [54]), .I4(scrambler[8]), .O(tempData[2])); LUT5 #( .INIT(32'h96696996)) \scrambler[3]_i_1 (.I0(\TX_DATA_reg[63]_0 [36]), .I1(scrambler[3]), .I2(tx_data_i[60]), .I3(\TX_DATA_reg[63]_0 [55]), .I4(scrambler[9]), .O(tempData[3])); LUT5 #( .INIT(32'h96696996)) \scrambler[4]_i_1 (.I0(\TX_DATA_reg[63]_0 [37]), .I1(scrambler[4]), .I2(tx_data_i[59]), .I3(\TX_DATA_reg[63]_0 [56]), .I4(scrambler[10]), .O(tempData[4])); LUT5 #( .INIT(32'h96696996)) \scrambler[5]_i_1 (.I0(\TX_DATA_reg[63]_0 [38]), .I1(scrambler[5]), .I2(tx_data_i[58]), .I3(\TX_DATA_reg[63]_0 [57]), .I4(scrambler[11]), .O(tempData[5])); aurora_64b66b_0_aurora_64b66b_0_rst_sync_5 u_pma_init_data_sync (.D(D), .Q(Q[6:3]), .TX_HEADER_1_reg(u_pma_init_data_sync_n_1), .TX_HEADER_1_reg_0(TX_HEADER_1_reg_0), .channel_up_tx_if(channel_up_tx_if), .gen_na_idles_i(gen_na_idles_i), .stg1_aurora_64b66b_0_cdc_to_reg_0(stg1_aurora_64b66b_0_cdc_to_reg), .stg5_reg_0(stg5_reg), .stg5_reg_1(u_pma_init_data_sync_n_2), .stg5_reg_2(u_pma_init_data_sync_n_3), .stg5_reg_3(u_pma_init_data_sync_n_4), .stg5_reg_4(u_pma_init_data_sync_n_5), .stg5_reg_5(u_pma_init_data_sync_n_6), .stg5_reg_6(stg5_reg_0), .tx_pe_data_v_i(tx_pe_data_v_i), .txdatavalid_symgen_i(txdatavalid_symgen_i)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_TX_STREAM" *) module aurora_64b66b_0_aurora_64b66b_0_TX_STREAM (gen_cc_i, do_cc_r, tx_pe_data_v_i, extend_cc_r, wait_for_lane_up_r_reg, gen_cc_flop_0_i, Q, s_axi_tx_tready, R0, TX_PE_DATA_V_reg, tx_dst_rdy_n_r0, do_cc_r_reg0, extend_cc_r_reg, gen_na_idles_i, rst_pma_init_usrclk, channel_up_tx_if, gen_ch_bond_i, s_axi_tx_tvalid, s_axi_tx_tdata); output gen_cc_i; output do_cc_r; output tx_pe_data_v_i; output extend_cc_r; output [1:0]wait_for_lane_up_r_reg; output gen_cc_flop_0_i; output [61:0]Q; output s_axi_tx_tready; input R0; input TX_PE_DATA_V_reg; input tx_dst_rdy_n_r0; input do_cc_r_reg0; input extend_cc_r_reg; input gen_na_idles_i; input rst_pma_init_usrclk; input channel_up_tx_if; input gen_ch_bond_i; input s_axi_tx_tvalid; input [0:63]s_axi_tx_tdata; wire [61:0]Q; wire R0; wire TX_PE_DATA_V_reg; wire channel_up_tx_if; wire do_cc_r; wire do_cc_r_reg0; wire extend_cc_r; wire extend_cc_r_reg; wire gen_cc_flop_0_i; wire gen_cc_i; wire gen_ch_bond_i; wire gen_na_idles_i; wire rst_pma_init_usrclk; wire [0:63]s_axi_tx_tdata; wire s_axi_tx_tready; wire s_axi_tx_tvalid; wire tx_dst_rdy_n_r0; wire tx_pe_data_v_i; wire tx_stream_control_sm_i_n_5; wire [1:0]wait_for_lane_up_r_reg; aurora_64b66b_0_aurora_64b66b_0_TX_STREAM_CONTROL_SM tx_stream_control_sm_i (.R0(R0), .do_cc_r(do_cc_r), .do_cc_r_reg0(do_cc_r_reg0), .do_cc_r_reg_0(TX_PE_DATA_V_reg), .extend_cc_r(extend_cc_r), .extend_cc_r_reg_0(extend_cc_r_reg), .gen_cc_flop_0_i_0(gen_cc_flop_0_i), .gen_cc_i(gen_cc_i), .gen_ch_bond_i(gen_ch_bond_i), .s_axi_tx_tready(s_axi_tx_tready), .s_axi_tx_tvalid(s_axi_tx_tvalid), .s_axi_tx_tvalid_0(tx_stream_control_sm_i_n_5), .tx_dst_rdy_n_r0(tx_dst_rdy_n_r0)); aurora_64b66b_0_aurora_64b66b_0_TX_STREAM_DATAPATH tx_stream_datapath_i (.Q(Q), .\TX_DATA_reg[53] (gen_cc_flop_0_i), .TX_PE_DATA_V_reg_0(tx_stream_control_sm_i_n_5), .TX_PE_DATA_V_reg_1(TX_PE_DATA_V_reg), .channel_up_tx_if(channel_up_tx_if), .gen_na_idles_i(gen_na_idles_i), .rst_pma_init_usrclk(rst_pma_init_usrclk), .s_axi_tx_tdata(s_axi_tx_tdata), .tx_pe_data_v_i(tx_pe_data_v_i), .wait_for_lane_up_r_reg(wait_for_lane_up_r_reg)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_TX_STREAM_CONTROL_SM" *) module aurora_64b66b_0_aurora_64b66b_0_TX_STREAM_CONTROL_SM (gen_cc_i, do_cc_r, extend_cc_r, gen_cc_flop_0_i_0, s_axi_tx_tready, s_axi_tx_tvalid_0, R0, do_cc_r_reg_0, tx_dst_rdy_n_r0, do_cc_r_reg0, extend_cc_r_reg_0, gen_ch_bond_i, s_axi_tx_tvalid); output gen_cc_i; output do_cc_r; output extend_cc_r; output gen_cc_flop_0_i_0; output s_axi_tx_tready; output s_axi_tx_tvalid_0; input R0; input do_cc_r_reg_0; input tx_dst_rdy_n_r0; input do_cc_r_reg0; input extend_cc_r_reg_0; input gen_ch_bond_i; input s_axi_tx_tvalid; wire R0; wire do_cc_r; wire do_cc_r_reg0; wire do_cc_r_reg_0; wire extend_cc_r; wire extend_cc_r_reg_0; wire gen_cc_flop_0_i_0; wire gen_cc_i; wire gen_ch_bond_i; wire s_axi_tx_tready; wire s_axi_tx_tvalid; wire s_axi_tx_tvalid_0; wire tx_dst_rdy_n_i; wire tx_dst_rdy_n_r0; LUT2 #( .INIT(4'hE)) \TX_DATA[53]_i_2 (.I0(gen_cc_i), .I1(gen_ch_bond_i), .O(gen_cc_flop_0_i_0)); (* SOFT_HLUTNM = "soft_lutpair122" *) LUT2 #( .INIT(4'h2)) TX_PE_DATA_V_i_1 (.I0(s_axi_tx_tvalid), .I1(tx_dst_rdy_n_i), .O(s_axi_tx_tvalid_0)); FDRE #( .INIT(1'b0)) do_cc_r_reg (.C(do_cc_r_reg_0), .CE(1'b1), .D(do_cc_r_reg0), .Q(do_cc_r), .R(1'b0)); FDRE extend_cc_r_reg (.C(do_cc_r_reg_0), .CE(1'b1), .D(extend_cc_r_reg_0), .Q(extend_cc_r), .R(1'b0)); (* BOX_TYPE = "PRIMITIVE" *) (* XILINX_LEGACY_PRIM = "FDR" *) FDRE #( .INIT(1'b0)) gen_cc_flop_0_i (.C(do_cc_r_reg_0), .CE(1'b1), .D(do_cc_r), .Q(gen_cc_i), .R(R0)); (* SOFT_HLUTNM = "soft_lutpair122" *) LUT1 #( .INIT(2'h1)) s_axi_tx_tready_INST_0 (.I0(tx_dst_rdy_n_i), .O(s_axi_tx_tready)); FDSE tx_dst_rdy_n_r_reg (.C(do_cc_r_reg_0), .CE(1'b1), .D(tx_dst_rdy_n_r0), .Q(tx_dst_rdy_n_i), .S(R0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_TX_STREAM_DATAPATH" *) module aurora_64b66b_0_aurora_64b66b_0_TX_STREAM_DATAPATH (tx_pe_data_v_i, wait_for_lane_up_r_reg, Q, TX_PE_DATA_V_reg_0, TX_PE_DATA_V_reg_1, gen_na_idles_i, \TX_DATA_reg[53] , rst_pma_init_usrclk, channel_up_tx_if, s_axi_tx_tdata); output tx_pe_data_v_i; output [1:0]wait_for_lane_up_r_reg; output [61:0]Q; input TX_PE_DATA_V_reg_0; input TX_PE_DATA_V_reg_1; input gen_na_idles_i; input \TX_DATA_reg[53] ; input rst_pma_init_usrclk; input channel_up_tx_if; input [0:63]s_axi_tx_tdata; wire [61:0]Q; wire \TX_DATA_reg[53] ; wire [50:51]TX_PE_DATA; wire TX_PE_DATA_V_reg_0; wire TX_PE_DATA_V_reg_1; wire channel_up_tx_if; wire gen_na_idles_i; wire rst_pma_init_usrclk; wire [0:63]s_axi_tx_tdata; wire tx_pe_data_v_i; wire [1:0]wait_for_lane_up_r_reg; LUT6 #( .INIT(64'h000F000D000D000D)) \TX_DATA[52]_i_1 (.I0(tx_pe_data_v_i), .I1(gen_na_idles_i), .I2(\TX_DATA_reg[53] ), .I3(rst_pma_init_usrclk), .I4(channel_up_tx_if), .I5(TX_PE_DATA[51]), .O(wait_for_lane_up_r_reg[0])); LUT6 #( .INIT(64'h0000322200002222)) \TX_DATA[53]_i_1 (.I0(gen_na_idles_i), .I1(\TX_DATA_reg[53] ), .I2(tx_pe_data_v_i), .I3(TX_PE_DATA[50]), .I4(rst_pma_init_usrclk), .I5(channel_up_tx_if), .O(wait_for_lane_up_r_reg[1])); FDRE TX_PE_DATA_V_reg (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(TX_PE_DATA_V_reg_0), .Q(tx_pe_data_v_i), .R(1'b0)); FDRE \TX_PE_DATA_reg[0] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[0]), .Q(Q[61]), .R(1'b0)); FDRE \TX_PE_DATA_reg[10] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[10]), .Q(Q[51]), .R(1'b0)); FDRE \TX_PE_DATA_reg[11] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[11]), .Q(Q[50]), .R(1'b0)); FDRE \TX_PE_DATA_reg[12] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[12]), .Q(Q[49]), .R(1'b0)); FDRE \TX_PE_DATA_reg[13] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[13]), .Q(Q[48]), .R(1'b0)); FDRE \TX_PE_DATA_reg[14] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[14]), .Q(Q[47]), .R(1'b0)); FDRE \TX_PE_DATA_reg[15] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[15]), .Q(Q[46]), .R(1'b0)); FDRE \TX_PE_DATA_reg[16] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[16]), .Q(Q[45]), .R(1'b0)); FDRE \TX_PE_DATA_reg[17] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[17]), .Q(Q[44]), .R(1'b0)); FDRE \TX_PE_DATA_reg[18] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[18]), .Q(Q[43]), .R(1'b0)); FDRE \TX_PE_DATA_reg[19] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[19]), .Q(Q[42]), .R(1'b0)); FDRE \TX_PE_DATA_reg[1] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[1]), .Q(Q[60]), .R(1'b0)); FDRE \TX_PE_DATA_reg[20] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[20]), .Q(Q[41]), .R(1'b0)); FDRE \TX_PE_DATA_reg[21] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[21]), .Q(Q[40]), .R(1'b0)); FDRE \TX_PE_DATA_reg[22] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[22]), .Q(Q[39]), .R(1'b0)); FDRE \TX_PE_DATA_reg[23] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[23]), .Q(Q[38]), .R(1'b0)); FDRE \TX_PE_DATA_reg[24] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[24]), .Q(Q[37]), .R(1'b0)); FDRE \TX_PE_DATA_reg[25] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[25]), .Q(Q[36]), .R(1'b0)); FDRE \TX_PE_DATA_reg[26] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[26]), .Q(Q[35]), .R(1'b0)); FDRE \TX_PE_DATA_reg[27] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[27]), .Q(Q[34]), .R(1'b0)); FDRE \TX_PE_DATA_reg[28] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[28]), .Q(Q[33]), .R(1'b0)); FDRE \TX_PE_DATA_reg[29] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[29]), .Q(Q[32]), .R(1'b0)); FDRE \TX_PE_DATA_reg[2] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[2]), .Q(Q[59]), .R(1'b0)); FDRE \TX_PE_DATA_reg[30] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[30]), .Q(Q[31]), .R(1'b0)); FDRE \TX_PE_DATA_reg[31] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[31]), .Q(Q[30]), .R(1'b0)); FDRE \TX_PE_DATA_reg[32] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[32]), .Q(Q[29]), .R(1'b0)); FDRE \TX_PE_DATA_reg[33] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[33]), .Q(Q[28]), .R(1'b0)); FDRE \TX_PE_DATA_reg[34] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[34]), .Q(Q[27]), .R(1'b0)); FDRE \TX_PE_DATA_reg[35] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[35]), .Q(Q[26]), .R(1'b0)); FDRE \TX_PE_DATA_reg[36] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[36]), .Q(Q[25]), .R(1'b0)); FDRE \TX_PE_DATA_reg[37] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[37]), .Q(Q[24]), .R(1'b0)); FDRE \TX_PE_DATA_reg[38] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[38]), .Q(Q[23]), .R(1'b0)); FDRE \TX_PE_DATA_reg[39] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[39]), .Q(Q[22]), .R(1'b0)); FDRE \TX_PE_DATA_reg[3] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[3]), .Q(Q[58]), .R(1'b0)); FDRE \TX_PE_DATA_reg[40] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[40]), .Q(Q[21]), .R(1'b0)); FDRE \TX_PE_DATA_reg[41] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[41]), .Q(Q[20]), .R(1'b0)); FDRE \TX_PE_DATA_reg[42] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[42]), .Q(Q[19]), .R(1'b0)); FDRE \TX_PE_DATA_reg[43] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[43]), .Q(Q[18]), .R(1'b0)); FDRE \TX_PE_DATA_reg[44] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[44]), .Q(Q[17]), .R(1'b0)); FDRE \TX_PE_DATA_reg[45] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[45]), .Q(Q[16]), .R(1'b0)); FDRE \TX_PE_DATA_reg[46] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[46]), .Q(Q[15]), .R(1'b0)); FDRE \TX_PE_DATA_reg[47] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[47]), .Q(Q[14]), .R(1'b0)); FDRE \TX_PE_DATA_reg[48] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[48]), .Q(Q[13]), .R(1'b0)); FDRE \TX_PE_DATA_reg[49] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[49]), .Q(Q[12]), .R(1'b0)); FDRE \TX_PE_DATA_reg[4] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[4]), .Q(Q[57]), .R(1'b0)); FDRE \TX_PE_DATA_reg[50] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[50]), .Q(TX_PE_DATA[50]), .R(1'b0)); FDRE \TX_PE_DATA_reg[51] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[51]), .Q(TX_PE_DATA[51]), .R(1'b0)); FDRE \TX_PE_DATA_reg[52] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[52]), .Q(Q[11]), .R(1'b0)); FDRE \TX_PE_DATA_reg[53] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[53]), .Q(Q[10]), .R(1'b0)); FDRE \TX_PE_DATA_reg[54] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[54]), .Q(Q[9]), .R(1'b0)); FDRE \TX_PE_DATA_reg[55] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[55]), .Q(Q[8]), .R(1'b0)); FDRE \TX_PE_DATA_reg[56] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[56]), .Q(Q[7]), .R(1'b0)); FDRE \TX_PE_DATA_reg[57] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[57]), .Q(Q[6]), .R(1'b0)); FDRE \TX_PE_DATA_reg[58] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[58]), .Q(Q[5]), .R(1'b0)); FDRE \TX_PE_DATA_reg[59] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[59]), .Q(Q[4]), .R(1'b0)); FDRE \TX_PE_DATA_reg[5] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[5]), .Q(Q[56]), .R(1'b0)); FDRE \TX_PE_DATA_reg[60] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[60]), .Q(Q[3]), .R(1'b0)); FDRE \TX_PE_DATA_reg[61] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[61]), .Q(Q[2]), .R(1'b0)); FDRE \TX_PE_DATA_reg[62] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[62]), .Q(Q[1]), .R(1'b0)); FDRE \TX_PE_DATA_reg[63] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[63]), .Q(Q[0]), .R(1'b0)); FDRE \TX_PE_DATA_reg[6] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[6]), .Q(Q[55]), .R(1'b0)); FDRE \TX_PE_DATA_reg[7] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[7]), .Q(Q[54]), .R(1'b0)); FDRE \TX_PE_DATA_reg[8] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[8]), .Q(Q[53]), .R(1'b0)); FDRE \TX_PE_DATA_reg[9] (.C(TX_PE_DATA_V_reg_1), .CE(1'b1), .D(s_axi_tx_tdata[9]), .Q(Q[52]), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_WRAPPER" *) module aurora_64b66b_0_aurora_64b66b_0_WRAPPER (gt0_drpdo, gt0_drprdy, txn, txp, gt_powergood, tx_out_clk, dout, gt_pll_lock, rx_lossofsync_i, link_reset_out, stg3_reg, RX_NEG_OUT_reg_0, \txseq_counter_i_reg[0]_0 , TXDATAVALID_IN, \txseq_counter_i_reg[1]_0 , txdatavalid_symgen_i, ILLEGAL_BTF_reg, rxdatavalid_i, wr_err_rd_clk_sync_reg, bufg_gt_clr_out, hold_reg_reg, tx_dst_rdy_n_r0, scrambler, rst_in_out_reg, gt0_drpaddr, init_clk, gt0_drpdi, gt0_drpen, gt0_drpwe, rxn, rxp, refclk1_in, loopback, gt_rxcdrovrden_in, sync_clk_out, stg3_reg_0, in0, s_level_out_d1_aurora_64b66b_0_cdc_to_reg, SR, tx_reset_i, extend_cc_r, Q, rst_pma_init_usrclk, illegal_btf_i, enable_err_detect_i, hard_err_usr_reg_0, channel_up_tx_if, do_cc_r, tx_data_i, D, mmcm_not_locked_out2, tempData, lopt, lopt_1, lopt_2, lopt_3); output [15:0]gt0_drpdo; output gt0_drprdy; output txn; output txp; output [0:0]gt_powergood; output tx_out_clk; output [65:0]dout; output gt_pll_lock; output rx_lossofsync_i; output link_reset_out; output stg3_reg; output RX_NEG_OUT_reg_0; output \txseq_counter_i_reg[0]_0 ; output TXDATAVALID_IN; output \txseq_counter_i_reg[1]_0 ; output txdatavalid_symgen_i; output ILLEGAL_BTF_reg; output rxdatavalid_i; output wr_err_rd_clk_sync_reg; output bufg_gt_clr_out; output hold_reg_reg; output tx_dst_rdy_n_r0; output [11:0]scrambler; input rst_in_out_reg; input [8:0]gt0_drpaddr; input init_clk; input [15:0]gt0_drpdi; input gt0_drpen; input gt0_drpwe; input rxn; input rxp; input refclk1_in; input [2:0]loopback; input gt_rxcdrovrden_in; input sync_clk_out; input stg3_reg_0; input in0; input s_level_out_d1_aurora_64b66b_0_cdc_to_reg; input [0:0]SR; input tx_reset_i; input extend_cc_r; input Q; input rst_pma_init_usrclk; input illegal_btf_i; input enable_err_detect_i; input hard_err_usr_reg_0; input channel_up_tx_if; input do_cc_r; input [57:0]tx_data_i; input [1:0]D; input mmcm_not_locked_out2; input [5:0]tempData; input lopt; input lopt_1; output lopt_2; output lopt_3; wire ANY_VLD_BTF_FLAG; wire CB_detect; wire CB_detect0; wire CB_detect_dlyd0p5; wire CC_detect_dlyd1; wire CC_detect_pulse_i; wire [1:0]D; wire FSM_RESETDONE_j; wire \FSM_onehot_cdr_reset_fsm_r[2]_i_3_n_0 ; wire \FSM_onehot_cdr_reset_fsm_r[2]_i_4_n_0 ; wire \FSM_onehot_cdr_reset_fsm_r_reg_n_0_[0] ; wire HPCNT_RESET_IN; wire ILLEGAL_BTF_reg; wire LINK_RESET_OUT0; wire Q; wire RX_NEG_OUT_reg_0; wire [0:0]SR; wire START_CB_WRITES_OUT; wire TXDATAVALID_IN; wire \TX_DATA[55]_i_3_n_0 ; (* RTL_KEEP = "true" *) wire all_start_cb_writes_i; (* RTL_KEEP = "true" *) wire all_vld_btf_flag_i; wire allow_block_sync_propagation; wire allow_block_sync_propagation_reg_n_0; (* RTL_KEEP = "true" *) wire bit_err_chan_bond_i; wire blocksync_all_lanes_inrxclk_q; wire blocksync_out_i; wire bufg_gt_clr_out; wire cb_bit_err_out; wire cbcc_data_srst; wire cbcc_fifo_reset_rd_clk; wire cbcc_fifo_reset_to_fifo_wr_clk; wire cbcc_fifo_reset_wr_clk; wire cbcc_reset_cbstg2_rd_clk; wire [7:0]cdr_reset_fsm_cntr_r; wire \cdr_reset_fsm_cntr_r[0]_i_1_n_0 ; wire \cdr_reset_fsm_cntr_r[1]_i_1_n_0 ; wire \cdr_reset_fsm_cntr_r[2]_i_1_n_0 ; wire \cdr_reset_fsm_cntr_r[3]_i_1_n_0 ; wire \cdr_reset_fsm_cntr_r[4]_i_1_n_0 ; wire \cdr_reset_fsm_cntr_r[5]_i_1_n_0 ; wire \cdr_reset_fsm_cntr_r[6]_i_1_n_0 ; wire \cdr_reset_fsm_cntr_r[7]_i_1_n_0 ; wire \cdr_reset_fsm_cntr_r[7]_i_2_n_0 ; wire \cdr_reset_fsm_cntr_r[7]_i_3_n_0 ; wire \cdr_reset_fsm_cntr_r[7]_i_4_n_0 ; wire cdr_reset_fsm_lnkreset; wire cdr_reset_fsm_lnkreset_i_1_n_0; wire cdr_reset_fsm_lnkreset_reg_n_0; wire channel_up_tx_if; wire common_reset_cbcc_i_n_0; wire descrambler_64b66b_gtx0_i_n_36; wire do_cc_r; (* RTL_KEEP = "true" *) wire do_rd_en_i; wire [65:0]dout; wire enable_err_detect_i; wire extend_cc_r; (* RTL_KEEP = "true" *) wire final_gater_for_fifo_din_i; wire fsm_resetdone_initclk; wire fsm_resetdone_to_rxreset_in; wire [8:0]gt0_drpaddr; wire [15:0]gt0_drpdi; wire [15:0]gt0_drpdo; wire gt0_drpen; wire gt0_drprdy; wire gt0_drpwe; wire gt_cplllock_i; wire gt_cplllock_j; wire gt_pll_lock; wire [0:0]gt_powergood; wire gt_rxcdrovrden_in; wire gtwiz_userclk_rx_active_in; wire gtx_reset_comb; wire hard_err_cntr_r; wire \hard_err_cntr_r[7]_i_4_n_0 ; wire \hard_err_cntr_r[7]_i_5_n_0 ; wire \hard_err_cntr_r[7]_i_6_n_0 ; wire [7:0]hard_err_cntr_r_reg; wire hard_err_rst_int; wire hard_err_rst_int0; wire hard_err_rst_int_i_4_n_0; wire hard_err_usr; wire hard_err_usr0; wire hard_err_usr_reg_0; wire hold_reg_reg; wire illegal_btf_i; wire in0; wire init_clk; wire [2:2]int_gt_rxbufstatus; wire link_reset_out; wire [2:0]loopback; wire lopt; wire lopt_1; wire lopt_2; wire lopt_3; (* RTL_KEEP = "true" *) wire master_do_rd_en_i; wire mmcm_not_locked_out2; wire new_gtx_rx_pcsreset_comb; wire [7:0]p_0_in__4; wire p_2_in_1; wire [52:52]poly; wire [31:0]pos_rxdata_from_gtx_i; wire pos_rxdatavalid_i; wire [1:0]pos_rxheader_from_gtx_i; wire pos_rxheadervalid_i; wire [31:0]pre_r1_rxdata_from_gtx_i; wire pre_r1_rxdatavalid_i; wire [1:0]pre_r1_rxheader_from_gtx_i; wire pre_r1_rxheadervalid_i; wire [31:0]pre_rxdata_from_gtx_i; wire pre_rxdatavalid_i; wire [1:0]pre_rxheader_from_gtx_i; wire pre_rxheadervalid_i; wire refclk1_in; wire reset_initclk; wire rst_in_out_reg; wire rst_pma_init_usrclk; wire rx_elastic_buf_err; (* RTL_KEEP = "true" *) wire rx_fsm_resetdone_i; wire rx_fsm_resetdone_i_i; (* RTL_KEEP = "true" *) wire rx_fsm_resetdone_ii; wire rx_lossofsync_i; wire [31:0]rxdata_from_gtx_i; wire [31:0]rxdata_to_fifo_i; wire rxdatavalid_i; wire rxdatavalid_i_0; wire rxdatavalid_to_fifo_i; (* RTL_KEEP = "true" *) wire rxfsm_reset_i; wire rxgearboxslip_i; wire [1:0]rxheader_from_gtx_i; wire [1:0]rxheader_to_fifo_i; wire rxheadervalid_i; wire rxlossofsync_out_i; wire rxlossofsync_out_q; wire rxn; wire rxp; wire rxreset_for_lanes_q; wire rxusrclk_out; wire s_level_out_d1_aurora_64b66b_0_cdc_to_reg; wire [63:0]scrambled_data_i; wire [11:0]scrambler; wire scrambler_64b66b_gtx0_i_n_0; wire sel; wire stableclk_gtx_reset_comb; wire stg3_reg; wire stg3_reg_0; wire sync_clk_out; wire sync_rx_polarity_r; wire [5:0]tempData; wire tx_buf_err_i; wire [57:0]tx_data_i; wire tx_dst_rdy_n_r0; (* RTL_KEEP = "true" *) wire tx_fsm_resetdone_i; (* RTL_KEEP = "true" *) wire tx_fsm_resetdone_ii; wire [1:0]tx_hdr_r; wire tx_out_clk; wire tx_reset_i; wire txdatavalid_symgen_i; wire txn; wire txp; wire [6:0]txseq_counter_i; wire \txseq_counter_i[0]_i_2_n_0 ; wire \txseq_counter_i[5]_i_2_n_0 ; wire \txseq_counter_i[5]_i_3_n_0 ; wire \txseq_counter_i_reg[0]_0 ; wire \txseq_counter_i_reg[1]_0 ; wire \txseq_counter_i_reg_n_0_[0] ; wire \txseq_counter_i_reg_n_0_[1] ; wire \txseq_counter_i_reg_n_0_[2] ; wire \txseq_counter_i_reg_n_0_[3] ; wire \txseq_counter_i_reg_n_0_[4] ; wire \txseq_counter_i_reg_n_0_[5] ; wire \txseq_counter_i_reg_n_0_[6] ; wire u_cdc__check_polarity_n_0; wire u_cdc_hard_err_init_n_0; wire u_rst_sync_blocksyncall_initclk_sync_n_0; wire u_rst_sync_fsm_resetdone_initclk_n_1; wire u_rst_sync_fsm_resetdone_n_0; wire unscrambled_data_i052_out; wire valid_btf_detect_c; wire valid_btf_detect_dlyd1; wire wr_err_rd_clk_sync_reg; FDRE FSM_RESETDONE_j_reg (.C(stg3_reg_0), .CE(1'b1), .D(stg3_reg), .Q(FSM_RESETDONE_j), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair104" *) LUT2 #( .INIT(4'hE)) \FSM_onehot_cdr_reset_fsm_r[2]_i_3 (.I0(allow_block_sync_propagation), .I1(cdr_reset_fsm_lnkreset), .O(\FSM_onehot_cdr_reset_fsm_r[2]_i_3_n_0 )); LUT5 #( .INIT(32'h80000000)) \FSM_onehot_cdr_reset_fsm_r[2]_i_4 (.I0(\cdr_reset_fsm_cntr_r[7]_i_4_n_0 ), .I1(cdr_reset_fsm_cntr_r[7]), .I2(cdr_reset_fsm_cntr_r[6]), .I3(cdr_reset_fsm_cntr_r[4]), .I4(cdr_reset_fsm_cntr_r[5]), .O(\FSM_onehot_cdr_reset_fsm_r[2]_i_4_n_0 )); (* FSM_ENCODED_STATES = "IDLE:001,ASSERT_RXRESET:010,DONE:100," *) FDSE #( .INIT(1'b1)) \FSM_onehot_cdr_reset_fsm_r_reg[0] (.C(init_clk), .CE(u_rst_sync_blocksyncall_initclk_sync_n_0), .D(1'b0), .Q(\FSM_onehot_cdr_reset_fsm_r_reg_n_0_[0] ), .S(p_2_in_1)); (* FSM_ENCODED_STATES = "IDLE:001,ASSERT_RXRESET:010,DONE:100," *) FDRE #( .INIT(1'b0)) \FSM_onehot_cdr_reset_fsm_r_reg[1] (.C(init_clk), .CE(u_rst_sync_blocksyncall_initclk_sync_n_0), .D(\FSM_onehot_cdr_reset_fsm_r_reg_n_0_[0] ), .Q(cdr_reset_fsm_lnkreset), .R(p_2_in_1)); (* FSM_ENCODED_STATES = "IDLE:001,ASSERT_RXRESET:010,DONE:100," *) FDRE #( .INIT(1'b0)) \FSM_onehot_cdr_reset_fsm_r_reg[2] (.C(init_clk), .CE(u_rst_sync_blocksyncall_initclk_sync_n_0), .D(\FSM_onehot_cdr_reset_fsm_r[2]_i_3_n_0 ), .Q(allow_block_sync_propagation), .R(p_2_in_1)); FDRE LINK_RESET_OUT_reg (.C(init_clk), .CE(1'b1), .D(LINK_RESET_OUT0), .Q(link_reset_out), .R(1'b0)); LUT3 #( .INIT(8'h80)) PLLLKDET_OUT (.I0(gt_cplllock_i), .I1(rx_fsm_resetdone_ii), .I2(tx_fsm_resetdone_ii), .O(gt_pll_lock)); FDRE RX_NEG_OUT_reg (.C(rxusrclk_out), .CE(1'b1), .D(u_cdc__check_polarity_n_0), .Q(RX_NEG_OUT_reg_0), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair92" *) LUT5 #( .INIT(32'hFFFFFFFD)) \TX_DATA[55]_i_1 (.I0(\txseq_counter_i_reg_n_0_[1] ), .I1(\TX_DATA[55]_i_3_n_0 ), .I2(\txseq_counter_i_reg_n_0_[6] ), .I3(\txseq_counter_i_reg_n_0_[0] ), .I4(rst_pma_init_usrclk), .O(\txseq_counter_i_reg[1]_0 )); (* SOFT_HLUTNM = "soft_lutpair98" *) LUT4 #( .INIT(16'hFF7F)) \TX_DATA[55]_i_3 (.I0(\txseq_counter_i_reg_n_0_[4] ), .I1(\txseq_counter_i_reg_n_0_[2] ), .I2(\txseq_counter_i_reg_n_0_[3] ), .I3(\txseq_counter_i_reg_n_0_[5] ), .O(\TX_DATA[55]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair92" *) LUT4 #( .INIT(16'hFEFF)) TX_HEADER_0_i_2 (.I0(\txseq_counter_i_reg_n_0_[0] ), .I1(\txseq_counter_i_reg_n_0_[6] ), .I2(\TX_DATA[55]_i_3_n_0 ), .I3(\txseq_counter_i_reg_n_0_[1] ), .O(txdatavalid_symgen_i)); FDRE #( .INIT(1'b0)) allow_block_sync_propagation_reg (.C(init_clk), .CE(cdr_reset_fsm_lnkreset_i_1_n_0), .D(allow_block_sync_propagation), .Q(allow_block_sync_propagation_reg_n_0), .R(p_2_in_1)); aurora_64b66b_0_aurora_64b66b_0_MULTI_GT aurora_64b66b_0_multi_gt_i (.D(pre_rxdata_from_gtx_i), .E(sel), .Q(tx_hdr_r), .SCRAMBLED_DATA_OUT(scrambled_data_i), .bufg_gt_clr_out(bufg_gt_clr_out), .cplllock_out(gt_cplllock_j), .gt0_drpaddr(gt0_drpaddr), .gt0_drpdi(gt0_drpdi), .gt0_drpdo(gt0_drpdo), .gt0_drpen(gt0_drpen), .gt0_drprdy(gt0_drprdy), .gt0_drpwe(gt0_drpwe), .gt_powergood(gt_powergood), .gt_rxcdrovrden_in(gt_rxcdrovrden_in), .gtwiz_reset_rx_done_out(rx_fsm_resetdone_i), .gtwiz_reset_tx_done_out(tx_fsm_resetdone_i), .gtwiz_userclk_rx_usrclk_out(rxusrclk_out), .i_in_meta_reg(rxgearboxslip_i), .i_in_meta_reg_0(sync_rx_polarity_r), .i_in_meta_reg_1({\txseq_counter_i_reg_n_0_[6] ,\txseq_counter_i_reg_n_0_[5] ,\txseq_counter_i_reg_n_0_[4] ,\txseq_counter_i_reg_n_0_[3] ,\txseq_counter_i_reg_n_0_[2] ,\txseq_counter_i_reg_n_0_[1] ,\txseq_counter_i_reg_n_0_[0] }), .init_clk(init_clk), .init_clk_0(pre_rxheader_from_gtx_i), .loopback(loopback), .lopt(lopt), .lopt_1(lopt_1), .lopt_2(lopt_2), .lopt_3(lopt_3), .mmcm_not_locked_out2(mmcm_not_locked_out2), .out(gtwiz_userclk_rx_active_in), .refclk1_in(refclk1_in), .rst_in_out_reg(rst_in_out_reg), .rst_in_out_reg_0(rxfsm_reset_i), .rst_in_out_reg_1(stg3_reg_0), .rxbufstatus_out(int_gt_rxbufstatus), .rxdatavalid_out(pre_rxdatavalid_i), .rxheadervalid_out(pre_rxheadervalid_i), .rxn(rxn), .rxp(rxp), .sync_clk_out(sync_clk_out), .tx_out_clk(tx_out_clk), .txbufstatus_out(tx_buf_err_i), .txn(txn), .txp(txp)); aurora_64b66b_0_aurora_64b66b_0_BLOCK_SYNC_SM block_sync_sm_gtx0_i (.D(rxgearboxslip_i), .Q(rxheader_from_gtx_i), .SR(new_gtx_rx_pcsreset_comb), .blocksync_out_i(blocksync_out_i), .gtwiz_userclk_rx_usrclk_out(rxusrclk_out), .rxheadervalid_i(rxheadervalid_i)); FDRE #( .INIT(1'b0)) blocksync_all_lanes_inrxclk_q_reg (.C(rxusrclk_out), .CE(1'b1), .D(blocksync_out_i), .Q(blocksync_all_lanes_inrxclk_q), .R(1'b0)); aurora_64b66b_0_aurora_64b66b_0_CLOCK_CORRECTION_CHANNEL_BONDING cbcc_gtx0_i (.ANY_VLD_BTF_FLAG(ANY_VLD_BTF_FLAG), .CB_detect0(CB_detect0), .CB_detect_dlyd0p5(CB_detect_dlyd0p5), .CC_RXLOSSOFSYNC_OUT_reg_0(common_reset_cbcc_i_n_0), .CC_detect_dlyd1(CC_detect_dlyd1), .D({CC_detect_pulse_i,CB_detect}), .FINAL_GATER_FOR_FIFO_DIN_reg_0(all_start_cb_writes_i), .HARD_ERR_reg(rx_elastic_buf_err), .ILLEGAL_BTF_reg(ILLEGAL_BTF_reg), .LINK_RESET_OUT0(LINK_RESET_OUT0), .LINK_RESET_OUT_reg(cdr_reset_fsm_lnkreset_reg_n_0), .\LINK_RESET_reg[0]_0 (p_2_in_1), .Q(rxheader_to_fifo_i), .SR(cbcc_fifo_reset_wr_clk), .START_CB_WRITES_OUT(START_CB_WRITES_OUT), .START_CB_WRITES_OUT_reg_0(all_vld_btf_flag_i), .UNSCRAMBLED_DATA_OUT(rxdata_to_fifo_i), .allow_block_sync_propagation_reg(rst_in_out_reg), .bit_err_chan_bond_i(bit_err_chan_bond_i), .cbcc_fifo_reset_rd_clk(cbcc_fifo_reset_rd_clk), .cbcc_reset_cbstg2_rd_clk(cbcc_reset_cbstg2_rd_clk), .channel_up_tx_if(channel_up_tx_if), .\count_for_reset_r_reg[23]_0 (u_rst_sync_fsm_resetdone_initclk_n_1), .do_rd_en_i(do_rd_en_i), .dout(dout), .enable_err_detect_i(enable_err_detect_i), .final_gater_for_fifo_din_i(final_gater_for_fifo_din_i), .gtwiz_userclk_rx_usrclk_out(rxusrclk_out), .hard_err_rst_int(hard_err_rst_int), .hard_err_usr0(hard_err_usr0), .hard_err_usr_reg(hard_err_usr_reg_0), .hold_reg_reg_0(hold_reg_reg), .illegal_btf_i(illegal_btf_i), .in0(rxlossofsync_out_q), .init_clk(init_clk), .out(master_do_rd_en_i), .rx_lossofsync_i(rx_lossofsync_i), .rxdatavalid_i(rxdatavalid_i), .rxdatavalid_to_fifo_i(rxdatavalid_to_fifo_i), .rxfsm_reset_i(rxfsm_reset_i), .s_level_out_d5_reg(stg3_reg_0), .srst(cbcc_data_srst), .txbufstatus_out(tx_buf_err_i), .valid_btf_detect_c(valid_btf_detect_c), .valid_btf_detect_dlyd1(valid_btf_detect_dlyd1), .\valid_btf_detect_extend_r_reg[4]_0 (new_gtx_rx_pcsreset_comb), .wr_err_rd_clk_sync_reg_0(wr_err_rd_clk_sync_reg), .\wr_monitor_flag_reg[4]_0 (cbcc_fifo_reset_to_fifo_wr_clk)); (* SOFT_HLUTNM = "soft_lutpair104" *) LUT2 #( .INIT(4'h2)) \cdr_reset_fsm_cntr_r[0]_i_1 (.I0(cdr_reset_fsm_lnkreset), .I1(cdr_reset_fsm_cntr_r[0]), .O(\cdr_reset_fsm_cntr_r[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair100" *) LUT3 #( .INIT(8'h60)) \cdr_reset_fsm_cntr_r[1]_i_1 (.I0(cdr_reset_fsm_cntr_r[1]), .I1(cdr_reset_fsm_cntr_r[0]), .I2(cdr_reset_fsm_lnkreset), .O(\cdr_reset_fsm_cntr_r[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair96" *) LUT4 #( .INIT(16'h7800)) \cdr_reset_fsm_cntr_r[2]_i_1 (.I0(cdr_reset_fsm_cntr_r[0]), .I1(cdr_reset_fsm_cntr_r[1]), .I2(cdr_reset_fsm_cntr_r[2]), .I3(cdr_reset_fsm_lnkreset), .O(\cdr_reset_fsm_cntr_r[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair96" *) LUT5 #( .INIT(32'h2AAA8000)) \cdr_reset_fsm_cntr_r[3]_i_1 (.I0(cdr_reset_fsm_lnkreset), .I1(cdr_reset_fsm_cntr_r[2]), .I2(cdr_reset_fsm_cntr_r[1]), .I3(cdr_reset_fsm_cntr_r[0]), .I4(cdr_reset_fsm_cntr_r[3]), .O(\cdr_reset_fsm_cntr_r[3]_i_1_n_0 )); LUT6 #( .INIT(64'h7FFF800000000000)) \cdr_reset_fsm_cntr_r[4]_i_1 (.I0(cdr_reset_fsm_cntr_r[1]), .I1(cdr_reset_fsm_cntr_r[0]), .I2(cdr_reset_fsm_cntr_r[3]), .I3(cdr_reset_fsm_cntr_r[2]), .I4(cdr_reset_fsm_cntr_r[4]), .I5(cdr_reset_fsm_lnkreset), .O(\cdr_reset_fsm_cntr_r[4]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair95" *) LUT4 #( .INIT(16'h2A80)) \cdr_reset_fsm_cntr_r[5]_i_1 (.I0(cdr_reset_fsm_lnkreset), .I1(cdr_reset_fsm_cntr_r[4]), .I2(\cdr_reset_fsm_cntr_r[7]_i_4_n_0 ), .I3(cdr_reset_fsm_cntr_r[5]), .O(\cdr_reset_fsm_cntr_r[5]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair95" *) LUT5 #( .INIT(32'h2AAA8000)) \cdr_reset_fsm_cntr_r[6]_i_1 (.I0(cdr_reset_fsm_lnkreset), .I1(cdr_reset_fsm_cntr_r[5]), .I2(\cdr_reset_fsm_cntr_r[7]_i_4_n_0 ), .I3(cdr_reset_fsm_cntr_r[4]), .I4(cdr_reset_fsm_cntr_r[6]), .O(\cdr_reset_fsm_cntr_r[6]_i_1_n_0 )); LUT3 #( .INIT(8'hFE)) \cdr_reset_fsm_cntr_r[7]_i_1 (.I0(\FSM_onehot_cdr_reset_fsm_r_reg_n_0_[0] ), .I1(allow_block_sync_propagation), .I2(\cdr_reset_fsm_cntr_r[7]_i_3_n_0 ), .O(\cdr_reset_fsm_cntr_r[7]_i_1_n_0 )); LUT6 #( .INIT(64'h2AAAAAAA80000000)) \cdr_reset_fsm_cntr_r[7]_i_2 (.I0(cdr_reset_fsm_lnkreset), .I1(cdr_reset_fsm_cntr_r[4]), .I2(\cdr_reset_fsm_cntr_r[7]_i_4_n_0 ), .I3(cdr_reset_fsm_cntr_r[5]), .I4(cdr_reset_fsm_cntr_r[6]), .I5(cdr_reset_fsm_cntr_r[7]), .O(\cdr_reset_fsm_cntr_r[7]_i_2_n_0 )); LUT6 #( .INIT(64'h2AAAAAAAAAAAAAAA)) \cdr_reset_fsm_cntr_r[7]_i_3 (.I0(cdr_reset_fsm_lnkreset), .I1(cdr_reset_fsm_cntr_r[5]), .I2(cdr_reset_fsm_cntr_r[4]), .I3(cdr_reset_fsm_cntr_r[6]), .I4(cdr_reset_fsm_cntr_r[7]), .I5(\cdr_reset_fsm_cntr_r[7]_i_4_n_0 ), .O(\cdr_reset_fsm_cntr_r[7]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair100" *) LUT4 #( .INIT(16'h8000)) \cdr_reset_fsm_cntr_r[7]_i_4 (.I0(cdr_reset_fsm_cntr_r[1]), .I1(cdr_reset_fsm_cntr_r[0]), .I2(cdr_reset_fsm_cntr_r[3]), .I3(cdr_reset_fsm_cntr_r[2]), .O(\cdr_reset_fsm_cntr_r[7]_i_4_n_0 )); FDRE #( .INIT(1'b0)) \cdr_reset_fsm_cntr_r_reg[0] (.C(init_clk), .CE(\cdr_reset_fsm_cntr_r[7]_i_1_n_0 ), .D(\cdr_reset_fsm_cntr_r[0]_i_1_n_0 ), .Q(cdr_reset_fsm_cntr_r[0]), .R(p_2_in_1)); FDRE #( .INIT(1'b0)) \cdr_reset_fsm_cntr_r_reg[1] (.C(init_clk), .CE(\cdr_reset_fsm_cntr_r[7]_i_1_n_0 ), .D(\cdr_reset_fsm_cntr_r[1]_i_1_n_0 ), .Q(cdr_reset_fsm_cntr_r[1]), .R(p_2_in_1)); FDRE #( .INIT(1'b0)) \cdr_reset_fsm_cntr_r_reg[2] (.C(init_clk), .CE(\cdr_reset_fsm_cntr_r[7]_i_1_n_0 ), .D(\cdr_reset_fsm_cntr_r[2]_i_1_n_0 ), .Q(cdr_reset_fsm_cntr_r[2]), .R(p_2_in_1)); FDRE #( .INIT(1'b0)) \cdr_reset_fsm_cntr_r_reg[3] (.C(init_clk), .CE(\cdr_reset_fsm_cntr_r[7]_i_1_n_0 ), .D(\cdr_reset_fsm_cntr_r[3]_i_1_n_0 ), .Q(cdr_reset_fsm_cntr_r[3]), .R(p_2_in_1)); FDRE #( .INIT(1'b0)) \cdr_reset_fsm_cntr_r_reg[4] (.C(init_clk), .CE(\cdr_reset_fsm_cntr_r[7]_i_1_n_0 ), .D(\cdr_reset_fsm_cntr_r[4]_i_1_n_0 ), .Q(cdr_reset_fsm_cntr_r[4]), .R(p_2_in_1)); FDRE #( .INIT(1'b0)) \cdr_reset_fsm_cntr_r_reg[5] (.C(init_clk), .CE(\cdr_reset_fsm_cntr_r[7]_i_1_n_0 ), .D(\cdr_reset_fsm_cntr_r[5]_i_1_n_0 ), .Q(cdr_reset_fsm_cntr_r[5]), .R(p_2_in_1)); FDRE #( .INIT(1'b0)) \cdr_reset_fsm_cntr_r_reg[6] (.C(init_clk), .CE(\cdr_reset_fsm_cntr_r[7]_i_1_n_0 ), .D(\cdr_reset_fsm_cntr_r[6]_i_1_n_0 ), .Q(cdr_reset_fsm_cntr_r[6]), .R(p_2_in_1)); FDRE #( .INIT(1'b0)) \cdr_reset_fsm_cntr_r_reg[7] (.C(init_clk), .CE(\cdr_reset_fsm_cntr_r[7]_i_1_n_0 ), .D(\cdr_reset_fsm_cntr_r[7]_i_2_n_0 ), .Q(cdr_reset_fsm_cntr_r[7]), .R(p_2_in_1)); LUT3 #( .INIT(8'hFE)) cdr_reset_fsm_lnkreset_i_1 (.I0(cdr_reset_fsm_lnkreset), .I1(\FSM_onehot_cdr_reset_fsm_r_reg_n_0_[0] ), .I2(allow_block_sync_propagation), .O(cdr_reset_fsm_lnkreset_i_1_n_0)); FDRE #( .INIT(1'b0)) cdr_reset_fsm_lnkreset_reg (.C(init_clk), .CE(cdr_reset_fsm_lnkreset_i_1_n_0), .D(cdr_reset_fsm_lnkreset), .Q(cdr_reset_fsm_lnkreset_reg_n_0), .R(p_2_in_1)); aurora_64b66b_0_aurora_64b66b_0_common_logic_cbcc common_logic_cbcc_i (.ANY_VLD_BTF_FLAG(ANY_VLD_BTF_FLAG), .SR(cbcc_fifo_reset_wr_clk), .START_CB_WRITES_OUT(START_CB_WRITES_OUT), .all_vld_btf_flag_i(all_vld_btf_flag_i), .cb_bit_err_out(cb_bit_err_out), .cbcc_fifo_reset_rd_clk(cbcc_fifo_reset_rd_clk), .gtwiz_userclk_rx_usrclk_out(rxusrclk_out), .in0(all_start_cb_writes_i), .master_do_rd_en_i(master_do_rd_en_i), .master_do_rd_en_out_reg_0(do_rd_en_i), .master_do_rd_en_out_reg_1(stg3_reg_0), .out(bit_err_chan_bond_i)); aurora_64b66b_0_aurora_64b66b_0_common_reset_cbcc common_reset_cbcc_i (.SR(cbcc_fifo_reset_wr_clk), .cb_bit_err_out(cb_bit_err_out), .cbcc_fifo_reset_rd_clk(cbcc_fifo_reset_rd_clk), .cbcc_reset_cbstg2_rd_clk(cbcc_reset_cbstg2_rd_clk), .gtwiz_userclk_rx_usrclk_out(rxusrclk_out), .srst(cbcc_data_srst), .stg1_aurora_64b66b_0_cdc_to_reg(new_gtx_rx_pcsreset_comb), .stg5_reg(common_reset_cbcc_i_n_0), .stg5_reg_0(stg3_reg_0), .stg9_reg(cbcc_fifo_reset_to_fifo_wr_clk)); (* SOFT_HLUTNM = "soft_lutpair99" *) LUT4 #( .INIT(16'hFFFE)) data_v_r_i_1 (.I0(\txseq_counter_i_reg_n_0_[0] ), .I1(\txseq_counter_i_reg_n_0_[6] ), .I2(\TX_DATA[55]_i_3_n_0 ), .I3(\txseq_counter_i_reg_n_0_[1] ), .O(TXDATAVALID_IN)); aurora_64b66b_0_aurora_64b66b_0_DESCRAMBLER_64B66B descrambler_64b66b_gtx0_i (.CB_detect0(CB_detect0), .CB_detect_dlyd0p5(CB_detect_dlyd0p5), .CB_detect_dlyd0p5_reg(rxheader_to_fifo_i), .CC_detect_dlyd1(CC_detect_dlyd1), .D({CC_detect_pulse_i,CB_detect}), .E(rxdatavalid_i_0), .Q(rxdata_to_fifo_i), .\descrambler_reg[31]_0 (rxdata_from_gtx_i), .\descrambler_reg[39]_0 ({descrambler_64b66b_gtx0_i_n_36,poly}), .gtwiz_userclk_rx_usrclk_out(rxusrclk_out), .in0(rxlossofsync_out_q), .rxdatavalid_to_fifo_i(rxdatavalid_to_fifo_i), .\unscrambled_data_i_reg[13]_0 (unscrambled_data_i052_out), .valid_btf_detect_c(valid_btf_detect_c)); LUT6 #( .INIT(64'hFFFF000100000000)) extend_cc_r_i_1 (.I0(\txseq_counter_i_reg_n_0_[0] ), .I1(\txseq_counter_i_reg_n_0_[6] ), .I2(\TX_DATA[55]_i_3_n_0 ), .I3(\txseq_counter_i_reg_n_0_[1] ), .I4(extend_cc_r), .I5(Q), .O(\txseq_counter_i_reg[0]_0 )); LUT1 #( .INIT(2'h1)) \hard_err_cntr_r[0]_i_1 (.I0(hard_err_cntr_r_reg[0]), .O(p_0_in__4[0])); (* SOFT_HLUTNM = "soft_lutpair102" *) LUT2 #( .INIT(4'h6)) \hard_err_cntr_r[1]_i_1 (.I0(hard_err_cntr_r_reg[0]), .I1(hard_err_cntr_r_reg[1]), .O(p_0_in__4[1])); (* SOFT_HLUTNM = "soft_lutpair102" *) LUT3 #( .INIT(8'h78)) \hard_err_cntr_r[2]_i_1 (.I0(hard_err_cntr_r_reg[1]), .I1(hard_err_cntr_r_reg[0]), .I2(hard_err_cntr_r_reg[2]), .O(p_0_in__4[2])); (* SOFT_HLUTNM = "soft_lutpair97" *) LUT4 #( .INIT(16'h7F80)) \hard_err_cntr_r[3]_i_1 (.I0(hard_err_cntr_r_reg[2]), .I1(hard_err_cntr_r_reg[0]), .I2(hard_err_cntr_r_reg[1]), .I3(hard_err_cntr_r_reg[3]), .O(p_0_in__4[3])); (* SOFT_HLUTNM = "soft_lutpair97" *) LUT5 #( .INIT(32'h7FFF8000)) \hard_err_cntr_r[4]_i_1 (.I0(hard_err_cntr_r_reg[3]), .I1(hard_err_cntr_r_reg[1]), .I2(hard_err_cntr_r_reg[0]), .I3(hard_err_cntr_r_reg[2]), .I4(hard_err_cntr_r_reg[4]), .O(p_0_in__4[4])); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \hard_err_cntr_r[5]_i_1 (.I0(hard_err_cntr_r_reg[1]), .I1(hard_err_cntr_r_reg[0]), .I2(hard_err_cntr_r_reg[2]), .I3(hard_err_cntr_r_reg[3]), .I4(hard_err_cntr_r_reg[4]), .I5(hard_err_cntr_r_reg[5]), .O(p_0_in__4[5])); LUT5 #( .INIT(32'hBFFF4000)) \hard_err_cntr_r[6]_i_1 (.I0(\hard_err_cntr_r[7]_i_6_n_0 ), .I1(hard_err_cntr_r_reg[4]), .I2(hard_err_cntr_r_reg[3]), .I3(hard_err_cntr_r_reg[5]), .I4(hard_err_cntr_r_reg[6]), .O(p_0_in__4[6])); LUT6 #( .INIT(64'hBFFFFFFF40000000)) \hard_err_cntr_r[7]_i_3 (.I0(\hard_err_cntr_r[7]_i_6_n_0 ), .I1(hard_err_cntr_r_reg[5]), .I2(hard_err_cntr_r_reg[3]), .I3(hard_err_cntr_r_reg[4]), .I4(hard_err_cntr_r_reg[6]), .I5(hard_err_cntr_r_reg[7]), .O(p_0_in__4[7])); (* SOFT_HLUTNM = "soft_lutpair94" *) LUT5 #( .INIT(32'h7FFFFFFF)) \hard_err_cntr_r[7]_i_4 (.I0(hard_err_cntr_r_reg[6]), .I1(hard_err_cntr_r_reg[4]), .I2(hard_err_cntr_r_reg[3]), .I3(hard_err_cntr_r_reg[5]), .I4(hard_err_cntr_r_reg[7]), .O(\hard_err_cntr_r[7]_i_4_n_0 )); (* SOFT_HLUTNM = "soft_lutpair94" *) LUT5 #( .INIT(32'hFFFFFFFE)) \hard_err_cntr_r[7]_i_5 (.I0(hard_err_cntr_r_reg[3]), .I1(hard_err_cntr_r_reg[6]), .I2(hard_err_cntr_r_reg[7]), .I3(hard_err_cntr_r_reg[5]), .I4(hard_err_cntr_r_reg[4]), .O(\hard_err_cntr_r[7]_i_5_n_0 )); (* SOFT_HLUTNM = "soft_lutpair101" *) LUT3 #( .INIT(8'h7F)) \hard_err_cntr_r[7]_i_6 (.I0(hard_err_cntr_r_reg[1]), .I1(hard_err_cntr_r_reg[0]), .I2(hard_err_cntr_r_reg[2]), .O(\hard_err_cntr_r[7]_i_6_n_0 )); FDRE #( .INIT(1'b0)) \hard_err_cntr_r_reg[0] (.C(init_clk), .CE(hard_err_cntr_r), .D(p_0_in__4[0]), .Q(hard_err_cntr_r_reg[0]), .R(HPCNT_RESET_IN)); FDRE #( .INIT(1'b0)) \hard_err_cntr_r_reg[1] (.C(init_clk), .CE(hard_err_cntr_r), .D(p_0_in__4[1]), .Q(hard_err_cntr_r_reg[1]), .R(HPCNT_RESET_IN)); FDRE #( .INIT(1'b0)) \hard_err_cntr_r_reg[2] (.C(init_clk), .CE(hard_err_cntr_r), .D(p_0_in__4[2]), .Q(hard_err_cntr_r_reg[2]), .R(HPCNT_RESET_IN)); FDRE #( .INIT(1'b0)) \hard_err_cntr_r_reg[3] (.C(init_clk), .CE(hard_err_cntr_r), .D(p_0_in__4[3]), .Q(hard_err_cntr_r_reg[3]), .R(HPCNT_RESET_IN)); FDRE #( .INIT(1'b0)) \hard_err_cntr_r_reg[4] (.C(init_clk), .CE(hard_err_cntr_r), .D(p_0_in__4[4]), .Q(hard_err_cntr_r_reg[4]), .R(HPCNT_RESET_IN)); FDRE #( .INIT(1'b0)) \hard_err_cntr_r_reg[5] (.C(init_clk), .CE(hard_err_cntr_r), .D(p_0_in__4[5]), .Q(hard_err_cntr_r_reg[5]), .R(HPCNT_RESET_IN)); FDRE #( .INIT(1'b0)) \hard_err_cntr_r_reg[6] (.C(init_clk), .CE(hard_err_cntr_r), .D(p_0_in__4[6]), .Q(hard_err_cntr_r_reg[6]), .R(HPCNT_RESET_IN)); FDRE #( .INIT(1'b0)) \hard_err_cntr_r_reg[7] (.C(init_clk), .CE(hard_err_cntr_r), .D(p_0_in__4[7]), .Q(hard_err_cntr_r_reg[7]), .R(HPCNT_RESET_IN)); (* SOFT_HLUTNM = "soft_lutpair101" *) LUT4 #( .INIT(16'hAAAE)) hard_err_rst_int_i_3 (.I0(hard_err_rst_int_i_4_n_0), .I1(hard_err_cntr_r_reg[2]), .I2(hard_err_cntr_r_reg[0]), .I3(hard_err_cntr_r_reg[1]), .O(hard_err_rst_int0)); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFE)) hard_err_rst_int_i_4 (.I0(hard_err_cntr_r_reg[2]), .I1(hard_err_cntr_r_reg[6]), .I2(hard_err_cntr_r_reg[4]), .I3(hard_err_cntr_r_reg[3]), .I4(hard_err_cntr_r_reg[5]), .I5(hard_err_cntr_r_reg[7]), .O(hard_err_rst_int_i_4_n_0)); FDRE hard_err_rst_int_reg (.C(init_clk), .CE(1'b1), .D(u_cdc_hard_err_init_n_0), .Q(hard_err_rst_int), .R(1'b0)); FDRE #( .INIT(1'b0)) hard_err_usr_reg (.C(stg3_reg_0), .CE(1'b1), .D(hard_err_usr0), .Q(hard_err_usr), .R(1'b0)); FDRE #( .INIT(1'b1)) new_gtx_rx_pcsreset_comb_reg (.C(rxusrclk_out), .CE(1'b1), .D(u_rst_sync_fsm_resetdone_n_0), .Q(new_gtx_rx_pcsreset_comb), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pos_rxdata_from_gtx_i_reg[0] (.C(rxusrclk_out), .CE(pre_r1_rxdatavalid_i), .D(pre_r1_rxdata_from_gtx_i[0]), .Q(pos_rxdata_from_gtx_i[0]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pos_rxdata_from_gtx_i_reg[10] (.C(rxusrclk_out), .CE(pre_r1_rxdatavalid_i), .D(pre_r1_rxdata_from_gtx_i[10]), .Q(pos_rxdata_from_gtx_i[10]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pos_rxdata_from_gtx_i_reg[11] (.C(rxusrclk_out), .CE(pre_r1_rxdatavalid_i), .D(pre_r1_rxdata_from_gtx_i[11]), .Q(pos_rxdata_from_gtx_i[11]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pos_rxdata_from_gtx_i_reg[12] (.C(rxusrclk_out), .CE(pre_r1_rxdatavalid_i), .D(pre_r1_rxdata_from_gtx_i[12]), .Q(pos_rxdata_from_gtx_i[12]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pos_rxdata_from_gtx_i_reg[13] (.C(rxusrclk_out), .CE(pre_r1_rxdatavalid_i), .D(pre_r1_rxdata_from_gtx_i[13]), .Q(pos_rxdata_from_gtx_i[13]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pos_rxdata_from_gtx_i_reg[14] (.C(rxusrclk_out), .CE(pre_r1_rxdatavalid_i), .D(pre_r1_rxdata_from_gtx_i[14]), .Q(pos_rxdata_from_gtx_i[14]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pos_rxdata_from_gtx_i_reg[15] (.C(rxusrclk_out), .CE(pre_r1_rxdatavalid_i), .D(pre_r1_rxdata_from_gtx_i[15]), .Q(pos_rxdata_from_gtx_i[15]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pos_rxdata_from_gtx_i_reg[16] (.C(rxusrclk_out), .CE(pre_r1_rxdatavalid_i), .D(pre_r1_rxdata_from_gtx_i[16]), .Q(pos_rxdata_from_gtx_i[16]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pos_rxdata_from_gtx_i_reg[17] (.C(rxusrclk_out), .CE(pre_r1_rxdatavalid_i), .D(pre_r1_rxdata_from_gtx_i[17]), .Q(pos_rxdata_from_gtx_i[17]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pos_rxdata_from_gtx_i_reg[18] (.C(rxusrclk_out), .CE(pre_r1_rxdatavalid_i), .D(pre_r1_rxdata_from_gtx_i[18]), .Q(pos_rxdata_from_gtx_i[18]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pos_rxdata_from_gtx_i_reg[19] (.C(rxusrclk_out), .CE(pre_r1_rxdatavalid_i), .D(pre_r1_rxdata_from_gtx_i[19]), .Q(pos_rxdata_from_gtx_i[19]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pos_rxdata_from_gtx_i_reg[1] (.C(rxusrclk_out), .CE(pre_r1_rxdatavalid_i), .D(pre_r1_rxdata_from_gtx_i[1]), .Q(pos_rxdata_from_gtx_i[1]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pos_rxdata_from_gtx_i_reg[20] (.C(rxusrclk_out), .CE(pre_r1_rxdatavalid_i), .D(pre_r1_rxdata_from_gtx_i[20]), .Q(pos_rxdata_from_gtx_i[20]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pos_rxdata_from_gtx_i_reg[21] (.C(rxusrclk_out), .CE(pre_r1_rxdatavalid_i), .D(pre_r1_rxdata_from_gtx_i[21]), .Q(pos_rxdata_from_gtx_i[21]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pos_rxdata_from_gtx_i_reg[22] (.C(rxusrclk_out), .CE(pre_r1_rxdatavalid_i), .D(pre_r1_rxdata_from_gtx_i[22]), .Q(pos_rxdata_from_gtx_i[22]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pos_rxdata_from_gtx_i_reg[23] (.C(rxusrclk_out), .CE(pre_r1_rxdatavalid_i), .D(pre_r1_rxdata_from_gtx_i[23]), .Q(pos_rxdata_from_gtx_i[23]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pos_rxdata_from_gtx_i_reg[24] (.C(rxusrclk_out), .CE(pre_r1_rxdatavalid_i), .D(pre_r1_rxdata_from_gtx_i[24]), .Q(pos_rxdata_from_gtx_i[24]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pos_rxdata_from_gtx_i_reg[25] (.C(rxusrclk_out), .CE(pre_r1_rxdatavalid_i), .D(pre_r1_rxdata_from_gtx_i[25]), .Q(pos_rxdata_from_gtx_i[25]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pos_rxdata_from_gtx_i_reg[26] (.C(rxusrclk_out), .CE(pre_r1_rxdatavalid_i), .D(pre_r1_rxdata_from_gtx_i[26]), .Q(pos_rxdata_from_gtx_i[26]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pos_rxdata_from_gtx_i_reg[27] (.C(rxusrclk_out), .CE(pre_r1_rxdatavalid_i), .D(pre_r1_rxdata_from_gtx_i[27]), .Q(pos_rxdata_from_gtx_i[27]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pos_rxdata_from_gtx_i_reg[28] (.C(rxusrclk_out), .CE(pre_r1_rxdatavalid_i), .D(pre_r1_rxdata_from_gtx_i[28]), .Q(pos_rxdata_from_gtx_i[28]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pos_rxdata_from_gtx_i_reg[29] (.C(rxusrclk_out), .CE(pre_r1_rxdatavalid_i), .D(pre_r1_rxdata_from_gtx_i[29]), .Q(pos_rxdata_from_gtx_i[29]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pos_rxdata_from_gtx_i_reg[2] (.C(rxusrclk_out), .CE(pre_r1_rxdatavalid_i), .D(pre_r1_rxdata_from_gtx_i[2]), .Q(pos_rxdata_from_gtx_i[2]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pos_rxdata_from_gtx_i_reg[30] (.C(rxusrclk_out), .CE(pre_r1_rxdatavalid_i), .D(pre_r1_rxdata_from_gtx_i[30]), .Q(pos_rxdata_from_gtx_i[30]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pos_rxdata_from_gtx_i_reg[31] (.C(rxusrclk_out), .CE(pre_r1_rxdatavalid_i), .D(pre_r1_rxdata_from_gtx_i[31]), .Q(pos_rxdata_from_gtx_i[31]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pos_rxdata_from_gtx_i_reg[3] (.C(rxusrclk_out), .CE(pre_r1_rxdatavalid_i), .D(pre_r1_rxdata_from_gtx_i[3]), .Q(pos_rxdata_from_gtx_i[3]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pos_rxdata_from_gtx_i_reg[4] (.C(rxusrclk_out), .CE(pre_r1_rxdatavalid_i), .D(pre_r1_rxdata_from_gtx_i[4]), .Q(pos_rxdata_from_gtx_i[4]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pos_rxdata_from_gtx_i_reg[5] (.C(rxusrclk_out), .CE(pre_r1_rxdatavalid_i), .D(pre_r1_rxdata_from_gtx_i[5]), .Q(pos_rxdata_from_gtx_i[5]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pos_rxdata_from_gtx_i_reg[6] (.C(rxusrclk_out), .CE(pre_r1_rxdatavalid_i), .D(pre_r1_rxdata_from_gtx_i[6]), .Q(pos_rxdata_from_gtx_i[6]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pos_rxdata_from_gtx_i_reg[7] (.C(rxusrclk_out), .CE(pre_r1_rxdatavalid_i), .D(pre_r1_rxdata_from_gtx_i[7]), .Q(pos_rxdata_from_gtx_i[7]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pos_rxdata_from_gtx_i_reg[8] (.C(rxusrclk_out), .CE(pre_r1_rxdatavalid_i), .D(pre_r1_rxdata_from_gtx_i[8]), .Q(pos_rxdata_from_gtx_i[8]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pos_rxdata_from_gtx_i_reg[9] (.C(rxusrclk_out), .CE(pre_r1_rxdatavalid_i), .D(pre_r1_rxdata_from_gtx_i[9]), .Q(pos_rxdata_from_gtx_i[9]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE pos_rxdatavalid_i_reg (.C(rxusrclk_out), .CE(1'b1), .D(pre_r1_rxdatavalid_i), .Q(pos_rxdatavalid_i), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pos_rxheader_from_gtx_i_reg[0] (.C(rxusrclk_out), .CE(pre_r1_rxheadervalid_i), .D(pre_r1_rxheader_from_gtx_i[0]), .Q(pos_rxheader_from_gtx_i[0]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pos_rxheader_from_gtx_i_reg[1] (.C(rxusrclk_out), .CE(pre_r1_rxheadervalid_i), .D(pre_r1_rxheader_from_gtx_i[1]), .Q(pos_rxheader_from_gtx_i[1]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE pos_rxheadervalid_i_reg (.C(rxusrclk_out), .CE(1'b1), .D(pre_r1_rxheadervalid_i), .Q(pos_rxheadervalid_i), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pre_r1_rxdata_from_gtx_i_reg[0] (.C(rxusrclk_out), .CE(1'b1), .D(pre_rxdata_from_gtx_i[0]), .Q(pre_r1_rxdata_from_gtx_i[0]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pre_r1_rxdata_from_gtx_i_reg[10] (.C(rxusrclk_out), .CE(1'b1), .D(pre_rxdata_from_gtx_i[10]), .Q(pre_r1_rxdata_from_gtx_i[10]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pre_r1_rxdata_from_gtx_i_reg[11] (.C(rxusrclk_out), .CE(1'b1), .D(pre_rxdata_from_gtx_i[11]), .Q(pre_r1_rxdata_from_gtx_i[11]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pre_r1_rxdata_from_gtx_i_reg[12] (.C(rxusrclk_out), .CE(1'b1), .D(pre_rxdata_from_gtx_i[12]), .Q(pre_r1_rxdata_from_gtx_i[12]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pre_r1_rxdata_from_gtx_i_reg[13] (.C(rxusrclk_out), .CE(1'b1), .D(pre_rxdata_from_gtx_i[13]), .Q(pre_r1_rxdata_from_gtx_i[13]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pre_r1_rxdata_from_gtx_i_reg[14] (.C(rxusrclk_out), .CE(1'b1), .D(pre_rxdata_from_gtx_i[14]), .Q(pre_r1_rxdata_from_gtx_i[14]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pre_r1_rxdata_from_gtx_i_reg[15] (.C(rxusrclk_out), .CE(1'b1), .D(pre_rxdata_from_gtx_i[15]), .Q(pre_r1_rxdata_from_gtx_i[15]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pre_r1_rxdata_from_gtx_i_reg[16] (.C(rxusrclk_out), .CE(1'b1), .D(pre_rxdata_from_gtx_i[16]), .Q(pre_r1_rxdata_from_gtx_i[16]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pre_r1_rxdata_from_gtx_i_reg[17] (.C(rxusrclk_out), .CE(1'b1), .D(pre_rxdata_from_gtx_i[17]), .Q(pre_r1_rxdata_from_gtx_i[17]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pre_r1_rxdata_from_gtx_i_reg[18] (.C(rxusrclk_out), .CE(1'b1), .D(pre_rxdata_from_gtx_i[18]), .Q(pre_r1_rxdata_from_gtx_i[18]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pre_r1_rxdata_from_gtx_i_reg[19] (.C(rxusrclk_out), .CE(1'b1), .D(pre_rxdata_from_gtx_i[19]), .Q(pre_r1_rxdata_from_gtx_i[19]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pre_r1_rxdata_from_gtx_i_reg[1] (.C(rxusrclk_out), .CE(1'b1), .D(pre_rxdata_from_gtx_i[1]), .Q(pre_r1_rxdata_from_gtx_i[1]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pre_r1_rxdata_from_gtx_i_reg[20] (.C(rxusrclk_out), .CE(1'b1), .D(pre_rxdata_from_gtx_i[20]), .Q(pre_r1_rxdata_from_gtx_i[20]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pre_r1_rxdata_from_gtx_i_reg[21] (.C(rxusrclk_out), .CE(1'b1), .D(pre_rxdata_from_gtx_i[21]), .Q(pre_r1_rxdata_from_gtx_i[21]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pre_r1_rxdata_from_gtx_i_reg[22] (.C(rxusrclk_out), .CE(1'b1), .D(pre_rxdata_from_gtx_i[22]), .Q(pre_r1_rxdata_from_gtx_i[22]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pre_r1_rxdata_from_gtx_i_reg[23] (.C(rxusrclk_out), .CE(1'b1), .D(pre_rxdata_from_gtx_i[23]), .Q(pre_r1_rxdata_from_gtx_i[23]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pre_r1_rxdata_from_gtx_i_reg[24] (.C(rxusrclk_out), .CE(1'b1), .D(pre_rxdata_from_gtx_i[24]), .Q(pre_r1_rxdata_from_gtx_i[24]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pre_r1_rxdata_from_gtx_i_reg[25] (.C(rxusrclk_out), .CE(1'b1), .D(pre_rxdata_from_gtx_i[25]), .Q(pre_r1_rxdata_from_gtx_i[25]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pre_r1_rxdata_from_gtx_i_reg[26] (.C(rxusrclk_out), .CE(1'b1), .D(pre_rxdata_from_gtx_i[26]), .Q(pre_r1_rxdata_from_gtx_i[26]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pre_r1_rxdata_from_gtx_i_reg[27] (.C(rxusrclk_out), .CE(1'b1), .D(pre_rxdata_from_gtx_i[27]), .Q(pre_r1_rxdata_from_gtx_i[27]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pre_r1_rxdata_from_gtx_i_reg[28] (.C(rxusrclk_out), .CE(1'b1), .D(pre_rxdata_from_gtx_i[28]), .Q(pre_r1_rxdata_from_gtx_i[28]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pre_r1_rxdata_from_gtx_i_reg[29] (.C(rxusrclk_out), .CE(1'b1), .D(pre_rxdata_from_gtx_i[29]), .Q(pre_r1_rxdata_from_gtx_i[29]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pre_r1_rxdata_from_gtx_i_reg[2] (.C(rxusrclk_out), .CE(1'b1), .D(pre_rxdata_from_gtx_i[2]), .Q(pre_r1_rxdata_from_gtx_i[2]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pre_r1_rxdata_from_gtx_i_reg[30] (.C(rxusrclk_out), .CE(1'b1), .D(pre_rxdata_from_gtx_i[30]), .Q(pre_r1_rxdata_from_gtx_i[30]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pre_r1_rxdata_from_gtx_i_reg[31] (.C(rxusrclk_out), .CE(1'b1), .D(pre_rxdata_from_gtx_i[31]), .Q(pre_r1_rxdata_from_gtx_i[31]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pre_r1_rxdata_from_gtx_i_reg[3] (.C(rxusrclk_out), .CE(1'b1), .D(pre_rxdata_from_gtx_i[3]), .Q(pre_r1_rxdata_from_gtx_i[3]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pre_r1_rxdata_from_gtx_i_reg[4] (.C(rxusrclk_out), .CE(1'b1), .D(pre_rxdata_from_gtx_i[4]), .Q(pre_r1_rxdata_from_gtx_i[4]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pre_r1_rxdata_from_gtx_i_reg[5] (.C(rxusrclk_out), .CE(1'b1), .D(pre_rxdata_from_gtx_i[5]), .Q(pre_r1_rxdata_from_gtx_i[5]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pre_r1_rxdata_from_gtx_i_reg[6] (.C(rxusrclk_out), .CE(1'b1), .D(pre_rxdata_from_gtx_i[6]), .Q(pre_r1_rxdata_from_gtx_i[6]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pre_r1_rxdata_from_gtx_i_reg[7] (.C(rxusrclk_out), .CE(1'b1), .D(pre_rxdata_from_gtx_i[7]), .Q(pre_r1_rxdata_from_gtx_i[7]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pre_r1_rxdata_from_gtx_i_reg[8] (.C(rxusrclk_out), .CE(1'b1), .D(pre_rxdata_from_gtx_i[8]), .Q(pre_r1_rxdata_from_gtx_i[8]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pre_r1_rxdata_from_gtx_i_reg[9] (.C(rxusrclk_out), .CE(1'b1), .D(pre_rxdata_from_gtx_i[9]), .Q(pre_r1_rxdata_from_gtx_i[9]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE pre_r1_rxdatavalid_i_reg (.C(rxusrclk_out), .CE(1'b1), .D(pre_rxdatavalid_i), .Q(pre_r1_rxdatavalid_i), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pre_r1_rxheader_from_gtx_i_reg[0] (.C(rxusrclk_out), .CE(1'b1), .D(pre_rxheader_from_gtx_i[0]), .Q(pre_r1_rxheader_from_gtx_i[0]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \pre_r1_rxheader_from_gtx_i_reg[1] (.C(rxusrclk_out), .CE(1'b1), .D(pre_rxheader_from_gtx_i[1]), .Q(pre_r1_rxheader_from_gtx_i[1]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE pre_r1_rxheadervalid_i_reg (.C(rxusrclk_out), .CE(1'b1), .D(pre_rxheadervalid_i), .Q(pre_r1_rxheadervalid_i), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \rxdata_from_gtx_i_reg[0] (.C(rxusrclk_out), .CE(1'b1), .D(pos_rxdata_from_gtx_i[0]), .Q(rxdata_from_gtx_i[0]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \rxdata_from_gtx_i_reg[10] (.C(rxusrclk_out), .CE(1'b1), .D(pos_rxdata_from_gtx_i[10]), .Q(rxdata_from_gtx_i[10]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \rxdata_from_gtx_i_reg[11] (.C(rxusrclk_out), .CE(1'b1), .D(pos_rxdata_from_gtx_i[11]), .Q(rxdata_from_gtx_i[11]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \rxdata_from_gtx_i_reg[12] (.C(rxusrclk_out), .CE(1'b1), .D(pos_rxdata_from_gtx_i[12]), .Q(rxdata_from_gtx_i[12]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \rxdata_from_gtx_i_reg[13] (.C(rxusrclk_out), .CE(1'b1), .D(pos_rxdata_from_gtx_i[13]), .Q(rxdata_from_gtx_i[13]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \rxdata_from_gtx_i_reg[14] (.C(rxusrclk_out), .CE(1'b1), .D(pos_rxdata_from_gtx_i[14]), .Q(rxdata_from_gtx_i[14]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \rxdata_from_gtx_i_reg[15] (.C(rxusrclk_out), .CE(1'b1), .D(pos_rxdata_from_gtx_i[15]), .Q(rxdata_from_gtx_i[15]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \rxdata_from_gtx_i_reg[16] (.C(rxusrclk_out), .CE(1'b1), .D(pos_rxdata_from_gtx_i[16]), .Q(rxdata_from_gtx_i[16]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \rxdata_from_gtx_i_reg[17] (.C(rxusrclk_out), .CE(1'b1), .D(pos_rxdata_from_gtx_i[17]), .Q(rxdata_from_gtx_i[17]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \rxdata_from_gtx_i_reg[18] (.C(rxusrclk_out), .CE(1'b1), .D(pos_rxdata_from_gtx_i[18]), .Q(rxdata_from_gtx_i[18]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \rxdata_from_gtx_i_reg[19] (.C(rxusrclk_out), .CE(1'b1), .D(pos_rxdata_from_gtx_i[19]), .Q(rxdata_from_gtx_i[19]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \rxdata_from_gtx_i_reg[1] (.C(rxusrclk_out), .CE(1'b1), .D(pos_rxdata_from_gtx_i[1]), .Q(rxdata_from_gtx_i[1]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \rxdata_from_gtx_i_reg[20] (.C(rxusrclk_out), .CE(1'b1), .D(pos_rxdata_from_gtx_i[20]), .Q(rxdata_from_gtx_i[20]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \rxdata_from_gtx_i_reg[21] (.C(rxusrclk_out), .CE(1'b1), .D(pos_rxdata_from_gtx_i[21]), .Q(rxdata_from_gtx_i[21]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \rxdata_from_gtx_i_reg[22] (.C(rxusrclk_out), .CE(1'b1), .D(pos_rxdata_from_gtx_i[22]), .Q(rxdata_from_gtx_i[22]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \rxdata_from_gtx_i_reg[23] (.C(rxusrclk_out), .CE(1'b1), .D(pos_rxdata_from_gtx_i[23]), .Q(rxdata_from_gtx_i[23]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \rxdata_from_gtx_i_reg[24] (.C(rxusrclk_out), .CE(1'b1), .D(pos_rxdata_from_gtx_i[24]), .Q(rxdata_from_gtx_i[24]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \rxdata_from_gtx_i_reg[25] (.C(rxusrclk_out), .CE(1'b1), .D(pos_rxdata_from_gtx_i[25]), .Q(rxdata_from_gtx_i[25]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \rxdata_from_gtx_i_reg[26] (.C(rxusrclk_out), .CE(1'b1), .D(pos_rxdata_from_gtx_i[26]), .Q(rxdata_from_gtx_i[26]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \rxdata_from_gtx_i_reg[27] (.C(rxusrclk_out), .CE(1'b1), .D(pos_rxdata_from_gtx_i[27]), .Q(rxdata_from_gtx_i[27]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \rxdata_from_gtx_i_reg[28] (.C(rxusrclk_out), .CE(1'b1), .D(pos_rxdata_from_gtx_i[28]), .Q(rxdata_from_gtx_i[28]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \rxdata_from_gtx_i_reg[29] (.C(rxusrclk_out), .CE(1'b1), .D(pos_rxdata_from_gtx_i[29]), .Q(rxdata_from_gtx_i[29]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \rxdata_from_gtx_i_reg[2] (.C(rxusrclk_out), .CE(1'b1), .D(pos_rxdata_from_gtx_i[2]), .Q(rxdata_from_gtx_i[2]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \rxdata_from_gtx_i_reg[30] (.C(rxusrclk_out), .CE(1'b1), .D(pos_rxdata_from_gtx_i[30]), .Q(rxdata_from_gtx_i[30]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \rxdata_from_gtx_i_reg[31] (.C(rxusrclk_out), .CE(1'b1), .D(pos_rxdata_from_gtx_i[31]), .Q(rxdata_from_gtx_i[31]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \rxdata_from_gtx_i_reg[3] (.C(rxusrclk_out), .CE(1'b1), .D(pos_rxdata_from_gtx_i[3]), .Q(rxdata_from_gtx_i[3]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \rxdata_from_gtx_i_reg[4] (.C(rxusrclk_out), .CE(1'b1), .D(pos_rxdata_from_gtx_i[4]), .Q(rxdata_from_gtx_i[4]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \rxdata_from_gtx_i_reg[5] (.C(rxusrclk_out), .CE(1'b1), .D(pos_rxdata_from_gtx_i[5]), .Q(rxdata_from_gtx_i[5]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \rxdata_from_gtx_i_reg[6] (.C(rxusrclk_out), .CE(1'b1), .D(pos_rxdata_from_gtx_i[6]), .Q(rxdata_from_gtx_i[6]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \rxdata_from_gtx_i_reg[7] (.C(rxusrclk_out), .CE(1'b1), .D(pos_rxdata_from_gtx_i[7]), .Q(rxdata_from_gtx_i[7]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \rxdata_from_gtx_i_reg[8] (.C(rxusrclk_out), .CE(1'b1), .D(pos_rxdata_from_gtx_i[8]), .Q(rxdata_from_gtx_i[8]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \rxdata_from_gtx_i_reg[9] (.C(rxusrclk_out), .CE(1'b1), .D(pos_rxdata_from_gtx_i[9]), .Q(rxdata_from_gtx_i[9]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE rxdatavalid_i_reg (.C(rxusrclk_out), .CE(1'b1), .D(pos_rxdatavalid_i), .Q(rxdatavalid_i_0), .R(1'b0)); FDRE rxdatavalid_to_fifo_i_reg (.C(rxusrclk_out), .CE(1'b1), .D(rxdatavalid_i_0), .Q(rxdatavalid_to_fifo_i), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \rxheader_from_gtx_i_reg[0] (.C(rxusrclk_out), .CE(1'b1), .D(pos_rxheader_from_gtx_i[0]), .Q(rxheader_from_gtx_i[0]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE \rxheader_from_gtx_i_reg[1] (.C(rxusrclk_out), .CE(1'b1), .D(pos_rxheader_from_gtx_i[1]), .Q(rxheader_from_gtx_i[1]), .R(1'b0)); FDRE \rxheader_to_fifo_i_reg[0] (.C(rxusrclk_out), .CE(1'b1), .D(rxheader_from_gtx_i[0]), .Q(rxheader_to_fifo_i[0]), .R(1'b0)); FDRE \rxheader_to_fifo_i_reg[1] (.C(rxusrclk_out), .CE(1'b1), .D(rxheader_from_gtx_i[1]), .Q(rxheader_to_fifo_i[1]), .R(1'b0)); (* shift_extract = "{no}" *) FDRE rxheadervalid_i_reg (.C(rxusrclk_out), .CE(1'b1), .D(pos_rxheadervalid_i), .Q(rxheadervalid_i), .R(1'b0)); FDRE rxlossofsync_out_q_reg (.C(rxusrclk_out), .CE(1'b1), .D(rxlossofsync_out_i), .Q(rxlossofsync_out_q), .R(1'b0)); FDRE rxreset_for_lanes_q_reg (.C(stg3_reg_0), .CE(1'b1), .D(tx_reset_i), .Q(rxreset_for_lanes_q), .R(1'b0)); aurora_64b66b_0_aurora_64b66b_0_SCRAMBLER_64B66B scrambler_64b66b_gtx0_i (.Q({\txseq_counter_i_reg_n_0_[6] ,\txseq_counter_i_reg_n_0_[5] ,\txseq_counter_i_reg_n_0_[4] ,\txseq_counter_i_reg_n_0_[3] ,\txseq_counter_i_reg_n_0_[2] ,\txseq_counter_i_reg_n_0_[1] ,\txseq_counter_i_reg_n_0_[0] }), .\SCRAMBLED_DATA_OUT_reg[63]_0 (scrambled_data_i), .\SCRAMBLED_DATA_OUT_reg[63]_1 (stg3_reg_0), .scrambler(scrambler), .tempData(tempData), .tx_data_i(tx_data_i), .\txseq_counter_i_reg[0] (scrambler_64b66b_gtx0_i_n_0)); LUT6 #( .INIT(64'hFFFFFFFFFFFF0001)) tx_dst_rdy_n_r_i_1 (.I0(\txseq_counter_i_reg_n_0_[0] ), .I1(\txseq_counter_i_reg_n_0_[6] ), .I2(\TX_DATA[55]_i_3_n_0 ), .I3(\txseq_counter_i_reg_n_0_[1] ), .I4(do_cc_r), .I5(Q), .O(tx_dst_rdy_n_r0)); FDRE \tx_hdr_r_reg[0] (.C(stg3_reg_0), .CE(1'b1), .D(D[0]), .Q(tx_hdr_r[0]), .R(1'b0)); FDRE \tx_hdr_r_reg[1] (.C(stg3_reg_0), .CE(1'b1), .D(D[1]), .Q(tx_hdr_r[1]), .R(1'b0)); LUT6 #( .INIT(64'h0F0F0F0F0F0F0F0E)) \txseq_counter_i[0]_i_1 (.I0(\txseq_counter_i_reg_n_0_[6] ), .I1(\txseq_counter_i[0]_i_2_n_0 ), .I2(\txseq_counter_i_reg_n_0_[0] ), .I3(\txseq_counter_i_reg_n_0_[4] ), .I4(\txseq_counter_i_reg_n_0_[3] ), .I5(\txseq_counter_i_reg_n_0_[2] ), .O(txseq_counter_i[0])); (* SOFT_HLUTNM = "soft_lutpair103" *) LUT2 #( .INIT(4'hB)) \txseq_counter_i[0]_i_2 (.I0(\txseq_counter_i_reg_n_0_[1] ), .I1(\txseq_counter_i_reg_n_0_[5] ), .O(\txseq_counter_i[0]_i_2_n_0 )); (* SOFT_HLUTNM = "soft_lutpair103" *) LUT2 #( .INIT(4'h6)) \txseq_counter_i[1]_i_1 (.I0(\txseq_counter_i_reg_n_0_[0] ), .I1(\txseq_counter_i_reg_n_0_[1] ), .O(txseq_counter_i[1])); (* SOFT_HLUTNM = "soft_lutpair99" *) LUT3 #( .INIT(8'h78)) \txseq_counter_i[2]_i_1 (.I0(\txseq_counter_i_reg_n_0_[1] ), .I1(\txseq_counter_i_reg_n_0_[0] ), .I2(\txseq_counter_i_reg_n_0_[2] ), .O(txseq_counter_i[2])); (* SOFT_HLUTNM = "soft_lutpair93" *) LUT4 #( .INIT(16'h7F80)) \txseq_counter_i[3]_i_1 (.I0(\txseq_counter_i_reg_n_0_[2] ), .I1(\txseq_counter_i_reg_n_0_[0] ), .I2(\txseq_counter_i_reg_n_0_[1] ), .I3(\txseq_counter_i_reg_n_0_[3] ), .O(txseq_counter_i[3])); (* SOFT_HLUTNM = "soft_lutpair93" *) LUT5 #( .INIT(32'h7FFF8000)) \txseq_counter_i[4]_i_1 (.I0(\txseq_counter_i_reg_n_0_[2] ), .I1(\txseq_counter_i_reg_n_0_[3] ), .I2(\txseq_counter_i_reg_n_0_[0] ), .I3(\txseq_counter_i_reg_n_0_[1] ), .I4(\txseq_counter_i_reg_n_0_[4] ), .O(txseq_counter_i[4])); LUT6 #( .INIT(64'hCCCC3C3CCCC8CCC8)) \txseq_counter_i[5]_i_1 (.I0(\txseq_counter_i[5]_i_2_n_0 ), .I1(\txseq_counter_i_reg_n_0_[5] ), .I2(\txseq_counter_i_reg_n_0_[1] ), .I3(\txseq_counter_i_reg_n_0_[6] ), .I4(\txseq_counter_i[5]_i_3_n_0 ), .I5(\txseq_counter_i_reg_n_0_[0] ), .O(txseq_counter_i[5])); (* SOFT_HLUTNM = "soft_lutpair98" *) LUT3 #( .INIT(8'hFE)) \txseq_counter_i[5]_i_2 (.I0(\txseq_counter_i_reg_n_0_[4] ), .I1(\txseq_counter_i_reg_n_0_[3] ), .I2(\txseq_counter_i_reg_n_0_[2] ), .O(\txseq_counter_i[5]_i_2_n_0 )); LUT3 #( .INIT(8'h7F)) \txseq_counter_i[5]_i_3 (.I0(\txseq_counter_i_reg_n_0_[3] ), .I1(\txseq_counter_i_reg_n_0_[2] ), .I2(\txseq_counter_i_reg_n_0_[4] ), .O(\txseq_counter_i[5]_i_3_n_0 )); LUT6 #( .INIT(64'hFF7FFFFF00800000)) \txseq_counter_i[6]_i_1 (.I0(\txseq_counter_i_reg_n_0_[3] ), .I1(\txseq_counter_i_reg_n_0_[2] ), .I2(\txseq_counter_i_reg_n_0_[4] ), .I3(scrambler_64b66b_gtx0_i_n_0), .I4(\txseq_counter_i_reg_n_0_[5] ), .I5(\txseq_counter_i_reg_n_0_[6] ), .O(txseq_counter_i[6])); FDRE \txseq_counter_i_reg[0] (.C(stg3_reg_0), .CE(1'b1), .D(txseq_counter_i[0]), .Q(\txseq_counter_i_reg_n_0_[0] ), .R(gtx_reset_comb)); FDRE \txseq_counter_i_reg[1] (.C(stg3_reg_0), .CE(1'b1), .D(txseq_counter_i[1]), .Q(\txseq_counter_i_reg_n_0_[1] ), .R(gtx_reset_comb)); FDRE \txseq_counter_i_reg[2] (.C(stg3_reg_0), .CE(1'b1), .D(txseq_counter_i[2]), .Q(\txseq_counter_i_reg_n_0_[2] ), .R(gtx_reset_comb)); FDRE \txseq_counter_i_reg[3] (.C(stg3_reg_0), .CE(1'b1), .D(txseq_counter_i[3]), .Q(\txseq_counter_i_reg_n_0_[3] ), .R(gtx_reset_comb)); FDRE \txseq_counter_i_reg[4] (.C(stg3_reg_0), .CE(1'b1), .D(txseq_counter_i[4]), .Q(\txseq_counter_i_reg_n_0_[4] ), .R(gtx_reset_comb)); FDRE \txseq_counter_i_reg[5] (.C(stg3_reg_0), .CE(1'b1), .D(txseq_counter_i[5]), .Q(\txseq_counter_i_reg_n_0_[5] ), .R(gtx_reset_comb)); FDRE \txseq_counter_i_reg[6] (.C(stg3_reg_0), .CE(1'b1), .D(txseq_counter_i[6]), .Q(\txseq_counter_i_reg_n_0_[6] ), .R(gtx_reset_comb)); aurora_64b66b_0_aurora_64b66b_0_cdc_sync_6 u_cdc__check_polarity (.Q(rxheader_from_gtx_i), .RX_NEG_OUT_reg(RX_NEG_OUT_reg_0), .gtwiz_userclk_rx_usrclk_out(rxusrclk_out), .in0(in0), .\rxheader_from_gtx_i_reg[0] (u_cdc__check_polarity_n_0), .rxheadervalid_i(rxheadervalid_i)); aurora_64b66b_0_aurora_64b66b_0_cdc_sync__parameterized0 u_cdc_gt_cplllock_i (.cplllock_out(gt_cplllock_j), .init_clk(init_clk), .out(gt_cplllock_i)); aurora_64b66b_0_aurora_64b66b_0_cdc_sync__parameterized0_7 u_cdc_hard_err_init (.E(hard_err_cntr_r), .Q(hard_err_cntr_r_reg[2:0]), .SR(HPCNT_RESET_IN), .\hard_err_cntr_r_reg[0] (\hard_err_cntr_r[7]_i_4_n_0 ), .\hard_err_cntr_r_reg[0]_0 (\hard_err_cntr_r[7]_i_5_n_0 ), .hard_err_rst_int(hard_err_rst_int), .hard_err_rst_int0(hard_err_rst_int0), .hard_err_rst_int_reg(u_cdc_hard_err_init_n_0), .in0(hard_err_usr), .init_clk(init_clk)); aurora_64b66b_0_aurora_64b66b_0_cdc_sync__parameterized1 u_cdc_rx_elastic_buferr (.gtwiz_userclk_rx_usrclk_out(rxusrclk_out), .out(rx_elastic_buf_err), .rxbufstatus_out(int_gt_rxbufstatus), .s_level_out_d5_reg_0(stg3_reg_0)); aurora_64b66b_0_aurora_64b66b_0_cdc_sync__parameterized0_8 u_cdc_rx_fsm_resetdone_i (.init_clk(init_clk), .out(rx_fsm_resetdone_i), .rx_fsm_resetdone_ii(rx_fsm_resetdone_ii)); aurora_64b66b_0_aurora_64b66b_0_cdc_sync__parameterized2 u_cdc_rxpolarity_ (.gtwiz_userclk_rx_usrclk_out(rxusrclk_out), .out(sync_rx_polarity_r), .s_level_out_d1_aurora_64b66b_0_cdc_to_reg_0(s_level_out_d1_aurora_64b66b_0_cdc_to_reg)); aurora_64b66b_0_aurora_64b66b_0_cdc_sync__parameterized0_9 u_cdc_tx_fsm_resetdone_i (.init_clk(init_clk), .out(tx_fsm_resetdone_i), .tx_fsm_resetdone_ii(tx_fsm_resetdone_ii)); aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized0 u_rst_done_sync_rx (.out(rx_fsm_resetdone_i), .stg3_reg_0(rx_fsm_resetdone_i_i), .stg3_reg_1(stg3_reg_0)); aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized0_10 u_rst_done_sync_rx1 (.gtwiz_userclk_rx_usrclk_out(rxusrclk_out), .out(rx_fsm_resetdone_i)); aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized0_11 u_rst_done_sync_tx (.FSM_RESETDONE_j_reg(rx_fsm_resetdone_i_i), .out(tx_fsm_resetdone_i), .stg2_reg_0(stg3_reg_0), .stg3_reg_0(stg3_reg)); aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized0_12 u_rst_done_sync_tx1 (.gtwiz_userclk_rx_usrclk_out(rxusrclk_out), .out(tx_fsm_resetdone_i)); aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized1 u_rst_sync_blocksyncall_initclk_sync (.E(u_rst_sync_blocksyncall_initclk_sync_n_0), .\FSM_onehot_cdr_reset_fsm_r_reg[0] (\FSM_onehot_cdr_reset_fsm_r[2]_i_4_n_0 ), .Q({allow_block_sync_propagation,cdr_reset_fsm_lnkreset,\FSM_onehot_cdr_reset_fsm_r_reg_n_0_[0] }), .in0(blocksync_all_lanes_inrxclk_q), .init_clk(init_clk)); aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized1_13 u_rst_sync_blocksyncprop_inrxclk_sync (.blocksync_out_i(blocksync_out_i), .gtwiz_userclk_rx_usrclk_out(rxusrclk_out), .in0(allow_block_sync_propagation_reg_n_0), .rxlossofsync_out_i(rxlossofsync_out_i)); aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized1_14 u_rst_sync_fsm_resetdone (.fsm_resetdone_to_rxreset_in(fsm_resetdone_to_rxreset_in), .gtwiz_userclk_rx_usrclk_out(rxusrclk_out), .in0(FSM_RESETDONE_j), .out(gtwiz_userclk_rx_active_in), .stg5_reg_0(u_rst_sync_fsm_resetdone_n_0)); aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized1_15 u_rst_sync_fsm_resetdone_initclk (.\count_for_reset_r_reg[23] (rst_in_out_reg), .\count_for_reset_r_reg[23]_0 (cdr_reset_fsm_lnkreset_reg_n_0), .\dly_gt_rst_r_reg[18] (u_rst_sync_fsm_resetdone_initclk_n_1), .fsm_resetdone_initclk(fsm_resetdone_initclk), .in0(FSM_RESETDONE_j), .init_clk(init_clk), .out(rxfsm_reset_i), .reset_initclk(reset_initclk), .valid_btf_detect_dlyd1(valid_btf_detect_dlyd1)); aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized1_16 u_rst_sync_gtx_reset_comb (.SR(gtx_reset_comb), .in0(stableclk_gtx_reset_comb), .stg3_reg_0(stg3_reg_0)); aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized1_17 u_rst_sync_reset_initclk (.SR(SR), .fsm_resetdone_initclk(fsm_resetdone_initclk), .\hard_err_cntr_r_reg[7] (cdr_reset_fsm_lnkreset_reg_n_0), .\hard_err_cntr_r_reg[7]_0 (rst_in_out_reg), .init_clk(init_clk), .out(rxfsm_reset_i), .reset_initclk(reset_initclk), .stg5_reg_0(HPCNT_RESET_IN)); aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized1_18 u_rst_sync_rxreset_in (.fsm_resetdone_to_rxreset_in(fsm_resetdone_to_rxreset_in), .gtwiz_userclk_rx_usrclk_out(rxusrclk_out), .in0(rxreset_for_lanes_q)); aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized1_19 u_rst_sync_txusrclk_gtx_reset_comb (.E(sel), .in0(stableclk_gtx_reset_comb), .init_clk(init_clk)); LUT3 #( .INIT(8'h96)) \unscrambled_data_i[13]_i_1 (.I0(poly), .I1(rxdata_from_gtx_i[13]), .I2(descrambler_64b66b_gtx0_i_n_36), .O(unscrambled_data_i052_out)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_cdc_sync" *) module aurora_64b66b_0_aurora_64b66b_0_cdc_sync (next_ready_c, next_begin_c, SYSTEM_RESET_reg, s_level_out_d1_aurora_64b66b_0_cdc_to_reg_0, s_level_out_d5_reg_0, ready_r_reg, rx_lossofsync_i, ready_r, align_r, polarity_r, rx_polarity_dlyd_i, reset_lanes_i, begin_r_reg, SR, rx_polarity_r_reg, prev_rx_polarity_r); output next_ready_c; output next_begin_c; output SYSTEM_RESET_reg; input s_level_out_d1_aurora_64b66b_0_cdc_to_reg_0; input s_level_out_d5_reg_0; input ready_r_reg; input rx_lossofsync_i; input ready_r; input align_r; input polarity_r; input rx_polarity_dlyd_i; input reset_lanes_i; input begin_r_reg; input [0:0]SR; input rx_polarity_r_reg; input prev_rx_polarity_r; wire [0:0]SR; wire SYSTEM_RESET_reg; wire align_r; wire begin_r_i_2_n_0; wire begin_r_reg; wire next_begin_c; wire next_ready_c; wire p_level_in_int; wire polarity_r; wire prev_rx_polarity_r; wire ready_r; wire ready_r_i_3_n_0; wire ready_r_reg; wire reset_lanes_i; wire rx_lossofsync_i; wire rx_polarity_dlyd_i; wire rx_polarity_r_reg; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d3; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d4; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d5; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d6; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d3; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d4; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d5; wire s_level_out_d5_reg_0; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d6; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d3; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d4; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d5; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d6; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d7; assign p_level_in_int = s_level_out_d1_aurora_64b66b_0_cdc_to_reg_0; LUT6 #( .INIT(64'hFFFFFFFFFFFCA0A0)) begin_r_i_1 (.I0(rx_lossofsync_i), .I1(polarity_r), .I2(ready_r), .I3(align_r), .I4(reset_lanes_i), .I5(begin_r_i_2_n_0), .O(next_begin_c)); LUT4 #( .INIT(16'h80FF)) begin_r_i_2 (.I0(s_level_out_d2), .I1(rx_polarity_dlyd_i), .I2(polarity_r), .I3(begin_r_reg), .O(begin_r_i_2_n_0)); LUT1 #( .INIT(2'h2)) i_0 (.I0(1'b0), .O(s_out_d1_aurora_64b66b_0_cdc_to)); LUT1 #( .INIT(2'h2)) i_1 (.I0(1'b0), .O(s_out_d2)); LUT1 #( .INIT(2'h2)) i_10 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[28])); LUT1 #( .INIT(2'h2)) i_100 (.I0(1'b0), .O(s_level_out_bus_d3[2])); LUT1 #( .INIT(2'h2)) i_101 (.I0(1'b0), .O(s_level_out_bus_d3[1])); LUT1 #( .INIT(2'h2)) i_102 (.I0(1'b0), .O(s_level_out_bus_d3[0])); LUT1 #( .INIT(2'h2)) i_103 (.I0(1'b0), .O(s_level_out_bus_d4[31])); LUT1 #( .INIT(2'h2)) i_104 (.I0(1'b0), .O(s_level_out_bus_d4[30])); LUT1 #( .INIT(2'h2)) i_105 (.I0(1'b0), .O(s_level_out_bus_d4[29])); LUT1 #( .INIT(2'h2)) i_106 (.I0(1'b0), .O(s_level_out_bus_d4[28])); LUT1 #( .INIT(2'h2)) i_107 (.I0(1'b0), .O(s_level_out_bus_d4[27])); LUT1 #( .INIT(2'h2)) i_108 (.I0(1'b0), .O(s_level_out_bus_d4[26])); LUT1 #( .INIT(2'h2)) i_109 (.I0(1'b0), .O(s_level_out_bus_d4[25])); LUT1 #( .INIT(2'h2)) i_11 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[27])); LUT1 #( .INIT(2'h2)) i_110 (.I0(1'b0), .O(s_level_out_bus_d4[24])); LUT1 #( .INIT(2'h2)) i_111 (.I0(1'b0), .O(s_level_out_bus_d4[23])); LUT1 #( .INIT(2'h2)) i_112 (.I0(1'b0), .O(s_level_out_bus_d4[22])); LUT1 #( .INIT(2'h2)) i_113 (.I0(1'b0), .O(s_level_out_bus_d4[21])); LUT1 #( .INIT(2'h2)) i_114 (.I0(1'b0), .O(s_level_out_bus_d4[20])); LUT1 #( .INIT(2'h2)) i_115 (.I0(1'b0), .O(s_level_out_bus_d4[19])); LUT1 #( .INIT(2'h2)) i_116 (.I0(1'b0), .O(s_level_out_bus_d4[18])); LUT1 #( .INIT(2'h2)) i_117 (.I0(1'b0), .O(s_level_out_bus_d4[17])); LUT1 #( .INIT(2'h2)) i_118 (.I0(1'b0), .O(s_level_out_bus_d4[16])); LUT1 #( .INIT(2'h2)) i_119 (.I0(1'b0), .O(s_level_out_bus_d4[15])); LUT1 #( .INIT(2'h2)) i_12 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[26])); LUT1 #( .INIT(2'h2)) i_120 (.I0(1'b0), .O(s_level_out_bus_d4[14])); LUT1 #( .INIT(2'h2)) i_121 (.I0(1'b0), .O(s_level_out_bus_d4[13])); LUT1 #( .INIT(2'h2)) i_122 (.I0(1'b0), .O(s_level_out_bus_d4[12])); LUT1 #( .INIT(2'h2)) i_123 (.I0(1'b0), .O(s_level_out_bus_d4[11])); LUT1 #( .INIT(2'h2)) i_124 (.I0(1'b0), .O(s_level_out_bus_d4[10])); LUT1 #( .INIT(2'h2)) i_125 (.I0(1'b0), .O(s_level_out_bus_d4[9])); LUT1 #( .INIT(2'h2)) i_126 (.I0(1'b0), .O(s_level_out_bus_d4[8])); LUT1 #( .INIT(2'h2)) i_127 (.I0(1'b0), .O(s_level_out_bus_d4[7])); LUT1 #( .INIT(2'h2)) i_128 (.I0(1'b0), .O(s_level_out_bus_d4[6])); LUT1 #( .INIT(2'h2)) i_129 (.I0(1'b0), .O(s_level_out_bus_d4[5])); LUT1 #( .INIT(2'h2)) i_13 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[25])); LUT1 #( .INIT(2'h2)) i_130 (.I0(1'b0), .O(s_level_out_bus_d4[4])); LUT1 #( .INIT(2'h2)) i_131 (.I0(1'b0), .O(s_level_out_bus_d4[3])); LUT1 #( .INIT(2'h2)) i_132 (.I0(1'b0), .O(s_level_out_bus_d4[2])); LUT1 #( .INIT(2'h2)) i_133 (.I0(1'b0), .O(s_level_out_bus_d4[1])); LUT1 #( .INIT(2'h2)) i_134 (.I0(1'b0), .O(s_level_out_bus_d4[0])); LUT1 #( .INIT(2'h2)) i_135 (.I0(1'b0), .O(s_level_out_bus_d5[31])); LUT1 #( .INIT(2'h2)) i_136 (.I0(1'b0), .O(s_level_out_bus_d5[30])); LUT1 #( .INIT(2'h2)) i_137 (.I0(1'b0), .O(s_level_out_bus_d5[29])); LUT1 #( .INIT(2'h2)) i_138 (.I0(1'b0), .O(s_level_out_bus_d5[28])); LUT1 #( .INIT(2'h2)) i_139 (.I0(1'b0), .O(s_level_out_bus_d5[27])); LUT1 #( .INIT(2'h2)) i_14 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[24])); LUT1 #( .INIT(2'h2)) i_140 (.I0(1'b0), .O(s_level_out_bus_d5[26])); LUT1 #( .INIT(2'h2)) i_141 (.I0(1'b0), .O(s_level_out_bus_d5[25])); LUT1 #( .INIT(2'h2)) i_142 (.I0(1'b0), .O(s_level_out_bus_d5[24])); LUT1 #( .INIT(2'h2)) i_143 (.I0(1'b0), .O(s_level_out_bus_d5[23])); LUT1 #( .INIT(2'h2)) i_144 (.I0(1'b0), .O(s_level_out_bus_d5[22])); LUT1 #( .INIT(2'h2)) i_145 (.I0(1'b0), .O(s_level_out_bus_d5[21])); LUT1 #( .INIT(2'h2)) i_146 (.I0(1'b0), .O(s_level_out_bus_d5[20])); LUT1 #( .INIT(2'h2)) i_147 (.I0(1'b0), .O(s_level_out_bus_d5[19])); LUT1 #( .INIT(2'h2)) i_148 (.I0(1'b0), .O(s_level_out_bus_d5[18])); LUT1 #( .INIT(2'h2)) i_149 (.I0(1'b0), .O(s_level_out_bus_d5[17])); LUT1 #( .INIT(2'h2)) i_15 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[23])); LUT1 #( .INIT(2'h2)) i_150 (.I0(1'b0), .O(s_level_out_bus_d5[16])); LUT1 #( .INIT(2'h2)) i_151 (.I0(1'b0), .O(s_level_out_bus_d5[15])); LUT1 #( .INIT(2'h2)) i_152 (.I0(1'b0), .O(s_level_out_bus_d5[14])); LUT1 #( .INIT(2'h2)) i_153 (.I0(1'b0), .O(s_level_out_bus_d5[13])); LUT1 #( .INIT(2'h2)) i_154 (.I0(1'b0), .O(s_level_out_bus_d5[12])); LUT1 #( .INIT(2'h2)) i_155 (.I0(1'b0), .O(s_level_out_bus_d5[11])); LUT1 #( .INIT(2'h2)) i_156 (.I0(1'b0), .O(s_level_out_bus_d5[10])); LUT1 #( .INIT(2'h2)) i_157 (.I0(1'b0), .O(s_level_out_bus_d5[9])); LUT1 #( .INIT(2'h2)) i_158 (.I0(1'b0), .O(s_level_out_bus_d5[8])); LUT1 #( .INIT(2'h2)) i_159 (.I0(1'b0), .O(s_level_out_bus_d5[7])); LUT1 #( .INIT(2'h2)) i_16 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[22])); LUT1 #( .INIT(2'h2)) i_160 (.I0(1'b0), .O(s_level_out_bus_d5[6])); LUT1 #( .INIT(2'h2)) i_161 (.I0(1'b0), .O(s_level_out_bus_d5[5])); LUT1 #( .INIT(2'h2)) i_162 (.I0(1'b0), .O(s_level_out_bus_d5[4])); LUT1 #( .INIT(2'h2)) i_163 (.I0(1'b0), .O(s_level_out_bus_d5[3])); LUT1 #( .INIT(2'h2)) i_164 (.I0(1'b0), .O(s_level_out_bus_d5[2])); LUT1 #( .INIT(2'h2)) i_165 (.I0(1'b0), .O(s_level_out_bus_d5[1])); LUT1 #( .INIT(2'h2)) i_166 (.I0(1'b0), .O(s_level_out_bus_d5[0])); LUT1 #( .INIT(2'h2)) i_167 (.I0(1'b0), .O(s_level_out_bus_d6[31])); LUT1 #( .INIT(2'h2)) i_168 (.I0(1'b0), .O(s_level_out_bus_d6[30])); LUT1 #( .INIT(2'h2)) i_169 (.I0(1'b0), .O(s_level_out_bus_d6[29])); LUT1 #( .INIT(2'h2)) i_17 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[21])); LUT1 #( .INIT(2'h2)) i_170 (.I0(1'b0), .O(s_level_out_bus_d6[28])); LUT1 #( .INIT(2'h2)) i_171 (.I0(1'b0), .O(s_level_out_bus_d6[27])); LUT1 #( .INIT(2'h2)) i_172 (.I0(1'b0), .O(s_level_out_bus_d6[26])); LUT1 #( .INIT(2'h2)) i_173 (.I0(1'b0), .O(s_level_out_bus_d6[25])); LUT1 #( .INIT(2'h2)) i_174 (.I0(1'b0), .O(s_level_out_bus_d6[24])); LUT1 #( .INIT(2'h2)) i_175 (.I0(1'b0), .O(s_level_out_bus_d6[23])); LUT1 #( .INIT(2'h2)) i_176 (.I0(1'b0), .O(s_level_out_bus_d6[22])); LUT1 #( .INIT(2'h2)) i_177 (.I0(1'b0), .O(s_level_out_bus_d6[21])); LUT1 #( .INIT(2'h2)) i_178 (.I0(1'b0), .O(s_level_out_bus_d6[20])); LUT1 #( .INIT(2'h2)) i_179 (.I0(1'b0), .O(s_level_out_bus_d6[19])); LUT1 #( .INIT(2'h2)) i_18 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[20])); LUT1 #( .INIT(2'h2)) i_180 (.I0(1'b0), .O(s_level_out_bus_d6[18])); LUT1 #( .INIT(2'h2)) i_181 (.I0(1'b0), .O(s_level_out_bus_d6[17])); LUT1 #( .INIT(2'h2)) i_182 (.I0(1'b0), .O(s_level_out_bus_d6[16])); LUT1 #( .INIT(2'h2)) i_183 (.I0(1'b0), .O(s_level_out_bus_d6[15])); LUT1 #( .INIT(2'h2)) i_184 (.I0(1'b0), .O(s_level_out_bus_d6[14])); LUT1 #( .INIT(2'h2)) i_185 (.I0(1'b0), .O(s_level_out_bus_d6[13])); LUT1 #( .INIT(2'h2)) i_186 (.I0(1'b0), .O(s_level_out_bus_d6[12])); LUT1 #( .INIT(2'h2)) i_187 (.I0(1'b0), .O(s_level_out_bus_d6[11])); LUT1 #( .INIT(2'h2)) i_188 (.I0(1'b0), .O(s_level_out_bus_d6[10])); LUT1 #( .INIT(2'h2)) i_189 (.I0(1'b0), .O(s_level_out_bus_d6[9])); LUT1 #( .INIT(2'h2)) i_19 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[19])); LUT1 #( .INIT(2'h2)) i_190 (.I0(1'b0), .O(s_level_out_bus_d6[8])); LUT1 #( .INIT(2'h2)) i_191 (.I0(1'b0), .O(s_level_out_bus_d6[7])); LUT1 #( .INIT(2'h2)) i_192 (.I0(1'b0), .O(s_level_out_bus_d6[6])); LUT1 #( .INIT(2'h2)) i_193 (.I0(1'b0), .O(s_level_out_bus_d6[5])); LUT1 #( .INIT(2'h2)) i_194 (.I0(1'b0), .O(s_level_out_bus_d6[4])); LUT1 #( .INIT(2'h2)) i_195 (.I0(1'b0), .O(s_level_out_bus_d6[3])); LUT1 #( .INIT(2'h2)) i_196 (.I0(1'b0), .O(s_level_out_bus_d6[2])); LUT1 #( .INIT(2'h2)) i_197 (.I0(1'b0), .O(s_level_out_bus_d6[1])); LUT1 #( .INIT(2'h2)) i_198 (.I0(1'b0), .O(s_level_out_bus_d6[0])); LUT1 #( .INIT(2'h2)) i_2 (.I0(1'b0), .O(s_out_d3)); LUT1 #( .INIT(2'h2)) i_20 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[18])); LUT1 #( .INIT(2'h2)) i_21 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[17])); LUT1 #( .INIT(2'h2)) i_22 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[16])); LUT1 #( .INIT(2'h2)) i_23 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[15])); LUT1 #( .INIT(2'h2)) i_24 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[14])); LUT1 #( .INIT(2'h2)) i_25 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[13])); LUT1 #( .INIT(2'h2)) i_26 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[12])); LUT1 #( .INIT(2'h2)) i_27 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[11])); LUT1 #( .INIT(2'h2)) i_28 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[10])); LUT1 #( .INIT(2'h2)) i_29 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[9])); LUT1 #( .INIT(2'h2)) i_3 (.I0(1'b0), .O(s_out_d4)); LUT1 #( .INIT(2'h2)) i_30 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[8])); LUT1 #( .INIT(2'h2)) i_31 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[7])); LUT1 #( .INIT(2'h2)) i_32 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[6])); LUT1 #( .INIT(2'h2)) i_33 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[5])); LUT1 #( .INIT(2'h2)) i_34 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[4])); LUT1 #( .INIT(2'h2)) i_35 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[3])); LUT1 #( .INIT(2'h2)) i_36 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[2])); LUT1 #( .INIT(2'h2)) i_37 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[1])); LUT1 #( .INIT(2'h2)) i_38 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[0])); LUT1 #( .INIT(2'h2)) i_39 (.I0(1'b0), .O(s_level_out_bus_d2[31])); LUT1 #( .INIT(2'h2)) i_4 (.I0(1'b0), .O(s_out_d5)); LUT1 #( .INIT(2'h2)) i_40 (.I0(1'b0), .O(s_level_out_bus_d2[30])); LUT1 #( .INIT(2'h2)) i_41 (.I0(1'b0), .O(s_level_out_bus_d2[29])); LUT1 #( .INIT(2'h2)) i_42 (.I0(1'b0), .O(s_level_out_bus_d2[28])); LUT1 #( .INIT(2'h2)) i_43 (.I0(1'b0), .O(s_level_out_bus_d2[27])); LUT1 #( .INIT(2'h2)) i_44 (.I0(1'b0), .O(s_level_out_bus_d2[26])); LUT1 #( .INIT(2'h2)) i_45 (.I0(1'b0), .O(s_level_out_bus_d2[25])); LUT1 #( .INIT(2'h2)) i_46 (.I0(1'b0), .O(s_level_out_bus_d2[24])); LUT1 #( .INIT(2'h2)) i_47 (.I0(1'b0), .O(s_level_out_bus_d2[23])); LUT1 #( .INIT(2'h2)) i_48 (.I0(1'b0), .O(s_level_out_bus_d2[22])); LUT1 #( .INIT(2'h2)) i_49 (.I0(1'b0), .O(s_level_out_bus_d2[21])); LUT1 #( .INIT(2'h2)) i_5 (.I0(1'b0), .O(s_out_d6)); LUT1 #( .INIT(2'h2)) i_50 (.I0(1'b0), .O(s_level_out_bus_d2[20])); LUT1 #( .INIT(2'h2)) i_51 (.I0(1'b0), .O(s_level_out_bus_d2[19])); LUT1 #( .INIT(2'h2)) i_52 (.I0(1'b0), .O(s_level_out_bus_d2[18])); LUT1 #( .INIT(2'h2)) i_53 (.I0(1'b0), .O(s_level_out_bus_d2[17])); LUT1 #( .INIT(2'h2)) i_54 (.I0(1'b0), .O(s_level_out_bus_d2[16])); LUT1 #( .INIT(2'h2)) i_55 (.I0(1'b0), .O(s_level_out_bus_d2[15])); LUT1 #( .INIT(2'h2)) i_56 (.I0(1'b0), .O(s_level_out_bus_d2[14])); LUT1 #( .INIT(2'h2)) i_57 (.I0(1'b0), .O(s_level_out_bus_d2[13])); LUT1 #( .INIT(2'h2)) i_58 (.I0(1'b0), .O(s_level_out_bus_d2[12])); LUT1 #( .INIT(2'h2)) i_59 (.I0(1'b0), .O(s_level_out_bus_d2[11])); LUT1 #( .INIT(2'h2)) i_6 (.I0(1'b0), .O(s_out_d7)); LUT1 #( .INIT(2'h2)) i_60 (.I0(1'b0), .O(s_level_out_bus_d2[10])); LUT1 #( .INIT(2'h2)) i_61 (.I0(1'b0), .O(s_level_out_bus_d2[9])); LUT1 #( .INIT(2'h2)) i_62 (.I0(1'b0), .O(s_level_out_bus_d2[8])); LUT1 #( .INIT(2'h2)) i_63 (.I0(1'b0), .O(s_level_out_bus_d2[7])); LUT1 #( .INIT(2'h2)) i_64 (.I0(1'b0), .O(s_level_out_bus_d2[6])); LUT1 #( .INIT(2'h2)) i_65 (.I0(1'b0), .O(s_level_out_bus_d2[5])); LUT1 #( .INIT(2'h2)) i_66 (.I0(1'b0), .O(s_level_out_bus_d2[4])); LUT1 #( .INIT(2'h2)) i_67 (.I0(1'b0), .O(s_level_out_bus_d2[3])); LUT1 #( .INIT(2'h2)) i_68 (.I0(1'b0), .O(s_level_out_bus_d2[2])); LUT1 #( .INIT(2'h2)) i_69 (.I0(1'b0), .O(s_level_out_bus_d2[1])); LUT1 #( .INIT(2'h2)) i_7 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[31])); LUT1 #( .INIT(2'h2)) i_70 (.I0(1'b0), .O(s_level_out_bus_d2[0])); LUT1 #( .INIT(2'h2)) i_71 (.I0(1'b0), .O(s_level_out_bus_d3[31])); LUT1 #( .INIT(2'h2)) i_72 (.I0(1'b0), .O(s_level_out_bus_d3[30])); LUT1 #( .INIT(2'h2)) i_73 (.I0(1'b0), .O(s_level_out_bus_d3[29])); LUT1 #( .INIT(2'h2)) i_74 (.I0(1'b0), .O(s_level_out_bus_d3[28])); LUT1 #( .INIT(2'h2)) i_75 (.I0(1'b0), .O(s_level_out_bus_d3[27])); LUT1 #( .INIT(2'h2)) i_76 (.I0(1'b0), .O(s_level_out_bus_d3[26])); LUT1 #( .INIT(2'h2)) i_77 (.I0(1'b0), .O(s_level_out_bus_d3[25])); LUT1 #( .INIT(2'h2)) i_78 (.I0(1'b0), .O(s_level_out_bus_d3[24])); LUT1 #( .INIT(2'h2)) i_79 (.I0(1'b0), .O(s_level_out_bus_d3[23])); LUT1 #( .INIT(2'h2)) i_8 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[30])); LUT1 #( .INIT(2'h2)) i_80 (.I0(1'b0), .O(s_level_out_bus_d3[22])); LUT1 #( .INIT(2'h2)) i_81 (.I0(1'b0), .O(s_level_out_bus_d3[21])); LUT1 #( .INIT(2'h2)) i_82 (.I0(1'b0), .O(s_level_out_bus_d3[20])); LUT1 #( .INIT(2'h2)) i_83 (.I0(1'b0), .O(s_level_out_bus_d3[19])); LUT1 #( .INIT(2'h2)) i_84 (.I0(1'b0), .O(s_level_out_bus_d3[18])); LUT1 #( .INIT(2'h2)) i_85 (.I0(1'b0), .O(s_level_out_bus_d3[17])); LUT1 #( .INIT(2'h2)) i_86 (.I0(1'b0), .O(s_level_out_bus_d3[16])); LUT1 #( .INIT(2'h2)) i_87 (.I0(1'b0), .O(s_level_out_bus_d3[15])); LUT1 #( .INIT(2'h2)) i_88 (.I0(1'b0), .O(s_level_out_bus_d3[14])); LUT1 #( .INIT(2'h2)) i_89 (.I0(1'b0), .O(s_level_out_bus_d3[13])); LUT1 #( .INIT(2'h2)) i_9 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[29])); LUT1 #( .INIT(2'h2)) i_90 (.I0(1'b0), .O(s_level_out_bus_d3[12])); LUT1 #( .INIT(2'h2)) i_91 (.I0(1'b0), .O(s_level_out_bus_d3[11])); LUT1 #( .INIT(2'h2)) i_92 (.I0(1'b0), .O(s_level_out_bus_d3[10])); LUT1 #( .INIT(2'h2)) i_93 (.I0(1'b0), .O(s_level_out_bus_d3[9])); LUT1 #( .INIT(2'h2)) i_94 (.I0(1'b0), .O(s_level_out_bus_d3[8])); LUT1 #( .INIT(2'h2)) i_95 (.I0(1'b0), .O(s_level_out_bus_d3[7])); LUT1 #( .INIT(2'h2)) i_96 (.I0(1'b0), .O(s_level_out_bus_d3[6])); LUT1 #( .INIT(2'h2)) i_97 (.I0(1'b0), .O(s_level_out_bus_d3[5])); LUT1 #( .INIT(2'h2)) i_98 (.I0(1'b0), .O(s_level_out_bus_d3[4])); LUT1 #( .INIT(2'h2)) i_99 (.I0(1'b0), .O(s_level_out_bus_d3[3])); LUT6 #( .INIT(64'h8888888888888C88)) ready_r_i_2__0 (.I0(ready_r_i_3_n_0), .I1(ready_r_reg), .I2(rx_lossofsync_i), .I3(ready_r), .I4(align_r), .I5(polarity_r), .O(next_ready_c)); LUT5 #( .INIT(32'h00000040)) ready_r_i_3 (.I0(s_level_out_d2), .I1(rx_polarity_dlyd_i), .I2(polarity_r), .I3(align_r), .I4(ready_r), .O(ready_r_i_3_n_0)); LUT4 #( .INIT(16'h0454)) rx_polarity_r_i_1 (.I0(SR), .I1(rx_polarity_r_reg), .I2(s_level_out_d2), .I3(prev_rx_polarity_r), .O(SYSTEM_RESET_reg)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d1_aurora_64b66b_0_cdc_to_reg (.C(s_level_out_d5_reg_0), .CE(1'b1), .D(p_level_in_int), .Q(s_level_out_d1_aurora_64b66b_0_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d2_reg (.C(s_level_out_d5_reg_0), .CE(1'b1), .D(s_level_out_d1_aurora_64b66b_0_cdc_to), .Q(s_level_out_d2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d3_reg (.C(s_level_out_d5_reg_0), .CE(1'b1), .D(s_level_out_d2), .Q(s_level_out_d3), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d4_reg (.C(s_level_out_d5_reg_0), .CE(1'b1), .D(s_level_out_d3), .Q(s_level_out_d4), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d5_reg (.C(s_level_out_d5_reg_0), .CE(1'b1), .D(s_level_out_d4), .Q(s_level_out_d5), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d6_reg (.C(s_level_out_d5_reg_0), .CE(1'b1), .D(s_level_out_d5), .Q(s_level_out_d6), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_cdc_sync" *) module aurora_64b66b_0_aurora_64b66b_0_cdc_sync_6 (\rxheader_from_gtx_i_reg[0] , in0, gtwiz_userclk_rx_usrclk_out, Q, rxheadervalid_i, RX_NEG_OUT_reg); output \rxheader_from_gtx_i_reg[0] ; input in0; input gtwiz_userclk_rx_usrclk_out; input [1:0]Q; input rxheadervalid_i; input RX_NEG_OUT_reg; wire [1:0]Q; wire RX_NEG_OUT_reg; wire gtwiz_userclk_rx_usrclk_out; wire p_level_in_int; wire \rxheader_from_gtx_i_reg[0] ; wire rxheadervalid_i; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d3; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d4; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d5; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d6; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d3; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d4; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d5; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d6; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d3; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d4; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d5; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d6; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d7; assign p_level_in_int = in0; LUT5 #( .INIT(32'hFF002000)) RX_NEG_OUT_i_1 (.I0(Q[0]), .I1(Q[1]), .I2(rxheadervalid_i), .I3(s_level_out_d2), .I4(RX_NEG_OUT_reg), .O(\rxheader_from_gtx_i_reg[0] )); LUT1 #( .INIT(2'h2)) i_0 (.I0(1'b0), .O(s_out_d1_aurora_64b66b_0_cdc_to)); LUT1 #( .INIT(2'h2)) i_1 (.I0(1'b0), .O(s_out_d2)); LUT1 #( .INIT(2'h2)) i_10 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[28])); LUT1 #( .INIT(2'h2)) i_100 (.I0(1'b0), .O(s_level_out_bus_d3[2])); LUT1 #( .INIT(2'h2)) i_101 (.I0(1'b0), .O(s_level_out_bus_d3[1])); LUT1 #( .INIT(2'h2)) i_102 (.I0(1'b0), .O(s_level_out_bus_d3[0])); LUT1 #( .INIT(2'h2)) i_103 (.I0(1'b0), .O(s_level_out_bus_d4[31])); LUT1 #( .INIT(2'h2)) i_104 (.I0(1'b0), .O(s_level_out_bus_d4[30])); LUT1 #( .INIT(2'h2)) i_105 (.I0(1'b0), .O(s_level_out_bus_d4[29])); LUT1 #( .INIT(2'h2)) i_106 (.I0(1'b0), .O(s_level_out_bus_d4[28])); LUT1 #( .INIT(2'h2)) i_107 (.I0(1'b0), .O(s_level_out_bus_d4[27])); LUT1 #( .INIT(2'h2)) i_108 (.I0(1'b0), .O(s_level_out_bus_d4[26])); LUT1 #( .INIT(2'h2)) i_109 (.I0(1'b0), .O(s_level_out_bus_d4[25])); LUT1 #( .INIT(2'h2)) i_11 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[27])); LUT1 #( .INIT(2'h2)) i_110 (.I0(1'b0), .O(s_level_out_bus_d4[24])); LUT1 #( .INIT(2'h2)) i_111 (.I0(1'b0), .O(s_level_out_bus_d4[23])); LUT1 #( .INIT(2'h2)) i_112 (.I0(1'b0), .O(s_level_out_bus_d4[22])); LUT1 #( .INIT(2'h2)) i_113 (.I0(1'b0), .O(s_level_out_bus_d4[21])); LUT1 #( .INIT(2'h2)) i_114 (.I0(1'b0), .O(s_level_out_bus_d4[20])); LUT1 #( .INIT(2'h2)) i_115 (.I0(1'b0), .O(s_level_out_bus_d4[19])); LUT1 #( .INIT(2'h2)) i_116 (.I0(1'b0), .O(s_level_out_bus_d4[18])); LUT1 #( .INIT(2'h2)) i_117 (.I0(1'b0), .O(s_level_out_bus_d4[17])); LUT1 #( .INIT(2'h2)) i_118 (.I0(1'b0), .O(s_level_out_bus_d4[16])); LUT1 #( .INIT(2'h2)) i_119 (.I0(1'b0), .O(s_level_out_bus_d4[15])); LUT1 #( .INIT(2'h2)) i_12 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[26])); LUT1 #( .INIT(2'h2)) i_120 (.I0(1'b0), .O(s_level_out_bus_d4[14])); LUT1 #( .INIT(2'h2)) i_121 (.I0(1'b0), .O(s_level_out_bus_d4[13])); LUT1 #( .INIT(2'h2)) i_122 (.I0(1'b0), .O(s_level_out_bus_d4[12])); LUT1 #( .INIT(2'h2)) i_123 (.I0(1'b0), .O(s_level_out_bus_d4[11])); LUT1 #( .INIT(2'h2)) i_124 (.I0(1'b0), .O(s_level_out_bus_d4[10])); LUT1 #( .INIT(2'h2)) i_125 (.I0(1'b0), .O(s_level_out_bus_d4[9])); LUT1 #( .INIT(2'h2)) i_126 (.I0(1'b0), .O(s_level_out_bus_d4[8])); LUT1 #( .INIT(2'h2)) i_127 (.I0(1'b0), .O(s_level_out_bus_d4[7])); LUT1 #( .INIT(2'h2)) i_128 (.I0(1'b0), .O(s_level_out_bus_d4[6])); LUT1 #( .INIT(2'h2)) i_129 (.I0(1'b0), .O(s_level_out_bus_d4[5])); LUT1 #( .INIT(2'h2)) i_13 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[25])); LUT1 #( .INIT(2'h2)) i_130 (.I0(1'b0), .O(s_level_out_bus_d4[4])); LUT1 #( .INIT(2'h2)) i_131 (.I0(1'b0), .O(s_level_out_bus_d4[3])); LUT1 #( .INIT(2'h2)) i_132 (.I0(1'b0), .O(s_level_out_bus_d4[2])); LUT1 #( .INIT(2'h2)) i_133 (.I0(1'b0), .O(s_level_out_bus_d4[1])); LUT1 #( .INIT(2'h2)) i_134 (.I0(1'b0), .O(s_level_out_bus_d4[0])); LUT1 #( .INIT(2'h2)) i_135 (.I0(1'b0), .O(s_level_out_bus_d5[31])); LUT1 #( .INIT(2'h2)) i_136 (.I0(1'b0), .O(s_level_out_bus_d5[30])); LUT1 #( .INIT(2'h2)) i_137 (.I0(1'b0), .O(s_level_out_bus_d5[29])); LUT1 #( .INIT(2'h2)) i_138 (.I0(1'b0), .O(s_level_out_bus_d5[28])); LUT1 #( .INIT(2'h2)) i_139 (.I0(1'b0), .O(s_level_out_bus_d5[27])); LUT1 #( .INIT(2'h2)) i_14 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[24])); LUT1 #( .INIT(2'h2)) i_140 (.I0(1'b0), .O(s_level_out_bus_d5[26])); LUT1 #( .INIT(2'h2)) i_141 (.I0(1'b0), .O(s_level_out_bus_d5[25])); LUT1 #( .INIT(2'h2)) i_142 (.I0(1'b0), .O(s_level_out_bus_d5[24])); LUT1 #( .INIT(2'h2)) i_143 (.I0(1'b0), .O(s_level_out_bus_d5[23])); LUT1 #( .INIT(2'h2)) i_144 (.I0(1'b0), .O(s_level_out_bus_d5[22])); LUT1 #( .INIT(2'h2)) i_145 (.I0(1'b0), .O(s_level_out_bus_d5[21])); LUT1 #( .INIT(2'h2)) i_146 (.I0(1'b0), .O(s_level_out_bus_d5[20])); LUT1 #( .INIT(2'h2)) i_147 (.I0(1'b0), .O(s_level_out_bus_d5[19])); LUT1 #( .INIT(2'h2)) i_148 (.I0(1'b0), .O(s_level_out_bus_d5[18])); LUT1 #( .INIT(2'h2)) i_149 (.I0(1'b0), .O(s_level_out_bus_d5[17])); LUT1 #( .INIT(2'h2)) i_15 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[23])); LUT1 #( .INIT(2'h2)) i_150 (.I0(1'b0), .O(s_level_out_bus_d5[16])); LUT1 #( .INIT(2'h2)) i_151 (.I0(1'b0), .O(s_level_out_bus_d5[15])); LUT1 #( .INIT(2'h2)) i_152 (.I0(1'b0), .O(s_level_out_bus_d5[14])); LUT1 #( .INIT(2'h2)) i_153 (.I0(1'b0), .O(s_level_out_bus_d5[13])); LUT1 #( .INIT(2'h2)) i_154 (.I0(1'b0), .O(s_level_out_bus_d5[12])); LUT1 #( .INIT(2'h2)) i_155 (.I0(1'b0), .O(s_level_out_bus_d5[11])); LUT1 #( .INIT(2'h2)) i_156 (.I0(1'b0), .O(s_level_out_bus_d5[10])); LUT1 #( .INIT(2'h2)) i_157 (.I0(1'b0), .O(s_level_out_bus_d5[9])); LUT1 #( .INIT(2'h2)) i_158 (.I0(1'b0), .O(s_level_out_bus_d5[8])); LUT1 #( .INIT(2'h2)) i_159 (.I0(1'b0), .O(s_level_out_bus_d5[7])); LUT1 #( .INIT(2'h2)) i_16 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[22])); LUT1 #( .INIT(2'h2)) i_160 (.I0(1'b0), .O(s_level_out_bus_d5[6])); LUT1 #( .INIT(2'h2)) i_161 (.I0(1'b0), .O(s_level_out_bus_d5[5])); LUT1 #( .INIT(2'h2)) i_162 (.I0(1'b0), .O(s_level_out_bus_d5[4])); LUT1 #( .INIT(2'h2)) i_163 (.I0(1'b0), .O(s_level_out_bus_d5[3])); LUT1 #( .INIT(2'h2)) i_164 (.I0(1'b0), .O(s_level_out_bus_d5[2])); LUT1 #( .INIT(2'h2)) i_165 (.I0(1'b0), .O(s_level_out_bus_d5[1])); LUT1 #( .INIT(2'h2)) i_166 (.I0(1'b0), .O(s_level_out_bus_d5[0])); LUT1 #( .INIT(2'h2)) i_167 (.I0(1'b0), .O(s_level_out_bus_d6[31])); LUT1 #( .INIT(2'h2)) i_168 (.I0(1'b0), .O(s_level_out_bus_d6[30])); LUT1 #( .INIT(2'h2)) i_169 (.I0(1'b0), .O(s_level_out_bus_d6[29])); LUT1 #( .INIT(2'h2)) i_17 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[21])); LUT1 #( .INIT(2'h2)) i_170 (.I0(1'b0), .O(s_level_out_bus_d6[28])); LUT1 #( .INIT(2'h2)) i_171 (.I0(1'b0), .O(s_level_out_bus_d6[27])); LUT1 #( .INIT(2'h2)) i_172 (.I0(1'b0), .O(s_level_out_bus_d6[26])); LUT1 #( .INIT(2'h2)) i_173 (.I0(1'b0), .O(s_level_out_bus_d6[25])); LUT1 #( .INIT(2'h2)) i_174 (.I0(1'b0), .O(s_level_out_bus_d6[24])); LUT1 #( .INIT(2'h2)) i_175 (.I0(1'b0), .O(s_level_out_bus_d6[23])); LUT1 #( .INIT(2'h2)) i_176 (.I0(1'b0), .O(s_level_out_bus_d6[22])); LUT1 #( .INIT(2'h2)) i_177 (.I0(1'b0), .O(s_level_out_bus_d6[21])); LUT1 #( .INIT(2'h2)) i_178 (.I0(1'b0), .O(s_level_out_bus_d6[20])); LUT1 #( .INIT(2'h2)) i_179 (.I0(1'b0), .O(s_level_out_bus_d6[19])); LUT1 #( .INIT(2'h2)) i_18 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[20])); LUT1 #( .INIT(2'h2)) i_180 (.I0(1'b0), .O(s_level_out_bus_d6[18])); LUT1 #( .INIT(2'h2)) i_181 (.I0(1'b0), .O(s_level_out_bus_d6[17])); LUT1 #( .INIT(2'h2)) i_182 (.I0(1'b0), .O(s_level_out_bus_d6[16])); LUT1 #( .INIT(2'h2)) i_183 (.I0(1'b0), .O(s_level_out_bus_d6[15])); LUT1 #( .INIT(2'h2)) i_184 (.I0(1'b0), .O(s_level_out_bus_d6[14])); LUT1 #( .INIT(2'h2)) i_185 (.I0(1'b0), .O(s_level_out_bus_d6[13])); LUT1 #( .INIT(2'h2)) i_186 (.I0(1'b0), .O(s_level_out_bus_d6[12])); LUT1 #( .INIT(2'h2)) i_187 (.I0(1'b0), .O(s_level_out_bus_d6[11])); LUT1 #( .INIT(2'h2)) i_188 (.I0(1'b0), .O(s_level_out_bus_d6[10])); LUT1 #( .INIT(2'h2)) i_189 (.I0(1'b0), .O(s_level_out_bus_d6[9])); LUT1 #( .INIT(2'h2)) i_19 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[19])); LUT1 #( .INIT(2'h2)) i_190 (.I0(1'b0), .O(s_level_out_bus_d6[8])); LUT1 #( .INIT(2'h2)) i_191 (.I0(1'b0), .O(s_level_out_bus_d6[7])); LUT1 #( .INIT(2'h2)) i_192 (.I0(1'b0), .O(s_level_out_bus_d6[6])); LUT1 #( .INIT(2'h2)) i_193 (.I0(1'b0), .O(s_level_out_bus_d6[5])); LUT1 #( .INIT(2'h2)) i_194 (.I0(1'b0), .O(s_level_out_bus_d6[4])); LUT1 #( .INIT(2'h2)) i_195 (.I0(1'b0), .O(s_level_out_bus_d6[3])); LUT1 #( .INIT(2'h2)) i_196 (.I0(1'b0), .O(s_level_out_bus_d6[2])); LUT1 #( .INIT(2'h2)) i_197 (.I0(1'b0), .O(s_level_out_bus_d6[1])); LUT1 #( .INIT(2'h2)) i_198 (.I0(1'b0), .O(s_level_out_bus_d6[0])); LUT1 #( .INIT(2'h2)) i_2 (.I0(1'b0), .O(s_out_d3)); LUT1 #( .INIT(2'h2)) i_20 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[18])); LUT1 #( .INIT(2'h2)) i_21 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[17])); LUT1 #( .INIT(2'h2)) i_22 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[16])); LUT1 #( .INIT(2'h2)) i_23 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[15])); LUT1 #( .INIT(2'h2)) i_24 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[14])); LUT1 #( .INIT(2'h2)) i_25 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[13])); LUT1 #( .INIT(2'h2)) i_26 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[12])); LUT1 #( .INIT(2'h2)) i_27 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[11])); LUT1 #( .INIT(2'h2)) i_28 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[10])); LUT1 #( .INIT(2'h2)) i_29 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[9])); LUT1 #( .INIT(2'h2)) i_3 (.I0(1'b0), .O(s_out_d4)); LUT1 #( .INIT(2'h2)) i_30 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[8])); LUT1 #( .INIT(2'h2)) i_31 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[7])); LUT1 #( .INIT(2'h2)) i_32 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[6])); LUT1 #( .INIT(2'h2)) i_33 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[5])); LUT1 #( .INIT(2'h2)) i_34 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[4])); LUT1 #( .INIT(2'h2)) i_35 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[3])); LUT1 #( .INIT(2'h2)) i_36 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[2])); LUT1 #( .INIT(2'h2)) i_37 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[1])); LUT1 #( .INIT(2'h2)) i_38 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[0])); LUT1 #( .INIT(2'h2)) i_39 (.I0(1'b0), .O(s_level_out_bus_d2[31])); LUT1 #( .INIT(2'h2)) i_4 (.I0(1'b0), .O(s_out_d5)); LUT1 #( .INIT(2'h2)) i_40 (.I0(1'b0), .O(s_level_out_bus_d2[30])); LUT1 #( .INIT(2'h2)) i_41 (.I0(1'b0), .O(s_level_out_bus_d2[29])); LUT1 #( .INIT(2'h2)) i_42 (.I0(1'b0), .O(s_level_out_bus_d2[28])); LUT1 #( .INIT(2'h2)) i_43 (.I0(1'b0), .O(s_level_out_bus_d2[27])); LUT1 #( .INIT(2'h2)) i_44 (.I0(1'b0), .O(s_level_out_bus_d2[26])); LUT1 #( .INIT(2'h2)) i_45 (.I0(1'b0), .O(s_level_out_bus_d2[25])); LUT1 #( .INIT(2'h2)) i_46 (.I0(1'b0), .O(s_level_out_bus_d2[24])); LUT1 #( .INIT(2'h2)) i_47 (.I0(1'b0), .O(s_level_out_bus_d2[23])); LUT1 #( .INIT(2'h2)) i_48 (.I0(1'b0), .O(s_level_out_bus_d2[22])); LUT1 #( .INIT(2'h2)) i_49 (.I0(1'b0), .O(s_level_out_bus_d2[21])); LUT1 #( .INIT(2'h2)) i_5 (.I0(1'b0), .O(s_out_d6)); LUT1 #( .INIT(2'h2)) i_50 (.I0(1'b0), .O(s_level_out_bus_d2[20])); LUT1 #( .INIT(2'h2)) i_51 (.I0(1'b0), .O(s_level_out_bus_d2[19])); LUT1 #( .INIT(2'h2)) i_52 (.I0(1'b0), .O(s_level_out_bus_d2[18])); LUT1 #( .INIT(2'h2)) i_53 (.I0(1'b0), .O(s_level_out_bus_d2[17])); LUT1 #( .INIT(2'h2)) i_54 (.I0(1'b0), .O(s_level_out_bus_d2[16])); LUT1 #( .INIT(2'h2)) i_55 (.I0(1'b0), .O(s_level_out_bus_d2[15])); LUT1 #( .INIT(2'h2)) i_56 (.I0(1'b0), .O(s_level_out_bus_d2[14])); LUT1 #( .INIT(2'h2)) i_57 (.I0(1'b0), .O(s_level_out_bus_d2[13])); LUT1 #( .INIT(2'h2)) i_58 (.I0(1'b0), .O(s_level_out_bus_d2[12])); LUT1 #( .INIT(2'h2)) i_59 (.I0(1'b0), .O(s_level_out_bus_d2[11])); LUT1 #( .INIT(2'h2)) i_6 (.I0(1'b0), .O(s_out_d7)); LUT1 #( .INIT(2'h2)) i_60 (.I0(1'b0), .O(s_level_out_bus_d2[10])); LUT1 #( .INIT(2'h2)) i_61 (.I0(1'b0), .O(s_level_out_bus_d2[9])); LUT1 #( .INIT(2'h2)) i_62 (.I0(1'b0), .O(s_level_out_bus_d2[8])); LUT1 #( .INIT(2'h2)) i_63 (.I0(1'b0), .O(s_level_out_bus_d2[7])); LUT1 #( .INIT(2'h2)) i_64 (.I0(1'b0), .O(s_level_out_bus_d2[6])); LUT1 #( .INIT(2'h2)) i_65 (.I0(1'b0), .O(s_level_out_bus_d2[5])); LUT1 #( .INIT(2'h2)) i_66 (.I0(1'b0), .O(s_level_out_bus_d2[4])); LUT1 #( .INIT(2'h2)) i_67 (.I0(1'b0), .O(s_level_out_bus_d2[3])); LUT1 #( .INIT(2'h2)) i_68 (.I0(1'b0), .O(s_level_out_bus_d2[2])); LUT1 #( .INIT(2'h2)) i_69 (.I0(1'b0), .O(s_level_out_bus_d2[1])); LUT1 #( .INIT(2'h2)) i_7 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[31])); LUT1 #( .INIT(2'h2)) i_70 (.I0(1'b0), .O(s_level_out_bus_d2[0])); LUT1 #( .INIT(2'h2)) i_71 (.I0(1'b0), .O(s_level_out_bus_d3[31])); LUT1 #( .INIT(2'h2)) i_72 (.I0(1'b0), .O(s_level_out_bus_d3[30])); LUT1 #( .INIT(2'h2)) i_73 (.I0(1'b0), .O(s_level_out_bus_d3[29])); LUT1 #( .INIT(2'h2)) i_74 (.I0(1'b0), .O(s_level_out_bus_d3[28])); LUT1 #( .INIT(2'h2)) i_75 (.I0(1'b0), .O(s_level_out_bus_d3[27])); LUT1 #( .INIT(2'h2)) i_76 (.I0(1'b0), .O(s_level_out_bus_d3[26])); LUT1 #( .INIT(2'h2)) i_77 (.I0(1'b0), .O(s_level_out_bus_d3[25])); LUT1 #( .INIT(2'h2)) i_78 (.I0(1'b0), .O(s_level_out_bus_d3[24])); LUT1 #( .INIT(2'h2)) i_79 (.I0(1'b0), .O(s_level_out_bus_d3[23])); LUT1 #( .INIT(2'h2)) i_8 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[30])); LUT1 #( .INIT(2'h2)) i_80 (.I0(1'b0), .O(s_level_out_bus_d3[22])); LUT1 #( .INIT(2'h2)) i_81 (.I0(1'b0), .O(s_level_out_bus_d3[21])); LUT1 #( .INIT(2'h2)) i_82 (.I0(1'b0), .O(s_level_out_bus_d3[20])); LUT1 #( .INIT(2'h2)) i_83 (.I0(1'b0), .O(s_level_out_bus_d3[19])); LUT1 #( .INIT(2'h2)) i_84 (.I0(1'b0), .O(s_level_out_bus_d3[18])); LUT1 #( .INIT(2'h2)) i_85 (.I0(1'b0), .O(s_level_out_bus_d3[17])); LUT1 #( .INIT(2'h2)) i_86 (.I0(1'b0), .O(s_level_out_bus_d3[16])); LUT1 #( .INIT(2'h2)) i_87 (.I0(1'b0), .O(s_level_out_bus_d3[15])); LUT1 #( .INIT(2'h2)) i_88 (.I0(1'b0), .O(s_level_out_bus_d3[14])); LUT1 #( .INIT(2'h2)) i_89 (.I0(1'b0), .O(s_level_out_bus_d3[13])); LUT1 #( .INIT(2'h2)) i_9 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[29])); LUT1 #( .INIT(2'h2)) i_90 (.I0(1'b0), .O(s_level_out_bus_d3[12])); LUT1 #( .INIT(2'h2)) i_91 (.I0(1'b0), .O(s_level_out_bus_d3[11])); LUT1 #( .INIT(2'h2)) i_92 (.I0(1'b0), .O(s_level_out_bus_d3[10])); LUT1 #( .INIT(2'h2)) i_93 (.I0(1'b0), .O(s_level_out_bus_d3[9])); LUT1 #( .INIT(2'h2)) i_94 (.I0(1'b0), .O(s_level_out_bus_d3[8])); LUT1 #( .INIT(2'h2)) i_95 (.I0(1'b0), .O(s_level_out_bus_d3[7])); LUT1 #( .INIT(2'h2)) i_96 (.I0(1'b0), .O(s_level_out_bus_d3[6])); LUT1 #( .INIT(2'h2)) i_97 (.I0(1'b0), .O(s_level_out_bus_d3[5])); LUT1 #( .INIT(2'h2)) i_98 (.I0(1'b0), .O(s_level_out_bus_d3[4])); LUT1 #( .INIT(2'h2)) i_99 (.I0(1'b0), .O(s_level_out_bus_d3[3])); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d1_aurora_64b66b_0_cdc_to_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(p_level_in_int), .Q(s_level_out_d1_aurora_64b66b_0_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d2_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(s_level_out_d1_aurora_64b66b_0_cdc_to), .Q(s_level_out_d2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d3_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(s_level_out_d2), .Q(s_level_out_d3), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d4_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(s_level_out_d3), .Q(s_level_out_d4), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d5_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(s_level_out_d4), .Q(s_level_out_d5), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d6_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(s_level_out_d5), .Q(s_level_out_d6), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_cdc_sync" *) module aurora_64b66b_0_aurora_64b66b_0_cdc_sync__parameterized0 (out, cplllock_out, init_clk); output out; input [0:0]cplllock_out; input init_clk; wire init_clk; wire p_level_in_int; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d3; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d4; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d5; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d6; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d3; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d4; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d5; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d6; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d3; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d4; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d5; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d6; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d7; assign out = s_level_out_d5; assign p_level_in_int = cplllock_out[0]; LUT1 #( .INIT(2'h2)) i_0 (.I0(1'b0), .O(s_out_d1_aurora_64b66b_0_cdc_to)); LUT1 #( .INIT(2'h2)) i_1 (.I0(1'b0), .O(s_out_d2)); LUT1 #( .INIT(2'h2)) i_10 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[28])); LUT1 #( .INIT(2'h2)) i_100 (.I0(1'b0), .O(s_level_out_bus_d3[2])); LUT1 #( .INIT(2'h2)) i_101 (.I0(1'b0), .O(s_level_out_bus_d3[1])); LUT1 #( .INIT(2'h2)) i_102 (.I0(1'b0), .O(s_level_out_bus_d3[0])); LUT1 #( .INIT(2'h2)) i_103 (.I0(1'b0), .O(s_level_out_bus_d4[31])); LUT1 #( .INIT(2'h2)) i_104 (.I0(1'b0), .O(s_level_out_bus_d4[30])); LUT1 #( .INIT(2'h2)) i_105 (.I0(1'b0), .O(s_level_out_bus_d4[29])); LUT1 #( .INIT(2'h2)) i_106 (.I0(1'b0), .O(s_level_out_bus_d4[28])); LUT1 #( .INIT(2'h2)) i_107 (.I0(1'b0), .O(s_level_out_bus_d4[27])); LUT1 #( .INIT(2'h2)) i_108 (.I0(1'b0), .O(s_level_out_bus_d4[26])); LUT1 #( .INIT(2'h2)) i_109 (.I0(1'b0), .O(s_level_out_bus_d4[25])); LUT1 #( .INIT(2'h2)) i_11 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[27])); LUT1 #( .INIT(2'h2)) i_110 (.I0(1'b0), .O(s_level_out_bus_d4[24])); LUT1 #( .INIT(2'h2)) i_111 (.I0(1'b0), .O(s_level_out_bus_d4[23])); LUT1 #( .INIT(2'h2)) i_112 (.I0(1'b0), .O(s_level_out_bus_d4[22])); LUT1 #( .INIT(2'h2)) i_113 (.I0(1'b0), .O(s_level_out_bus_d4[21])); LUT1 #( .INIT(2'h2)) i_114 (.I0(1'b0), .O(s_level_out_bus_d4[20])); LUT1 #( .INIT(2'h2)) i_115 (.I0(1'b0), .O(s_level_out_bus_d4[19])); LUT1 #( .INIT(2'h2)) i_116 (.I0(1'b0), .O(s_level_out_bus_d4[18])); LUT1 #( .INIT(2'h2)) i_117 (.I0(1'b0), .O(s_level_out_bus_d4[17])); LUT1 #( .INIT(2'h2)) i_118 (.I0(1'b0), .O(s_level_out_bus_d4[16])); LUT1 #( .INIT(2'h2)) i_119 (.I0(1'b0), .O(s_level_out_bus_d4[15])); LUT1 #( .INIT(2'h2)) i_12 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[26])); LUT1 #( .INIT(2'h2)) i_120 (.I0(1'b0), .O(s_level_out_bus_d4[14])); LUT1 #( .INIT(2'h2)) i_121 (.I0(1'b0), .O(s_level_out_bus_d4[13])); LUT1 #( .INIT(2'h2)) i_122 (.I0(1'b0), .O(s_level_out_bus_d4[12])); LUT1 #( .INIT(2'h2)) i_123 (.I0(1'b0), .O(s_level_out_bus_d4[11])); LUT1 #( .INIT(2'h2)) i_124 (.I0(1'b0), .O(s_level_out_bus_d4[10])); LUT1 #( .INIT(2'h2)) i_125 (.I0(1'b0), .O(s_level_out_bus_d4[9])); LUT1 #( .INIT(2'h2)) i_126 (.I0(1'b0), .O(s_level_out_bus_d4[8])); LUT1 #( .INIT(2'h2)) i_127 (.I0(1'b0), .O(s_level_out_bus_d4[7])); LUT1 #( .INIT(2'h2)) i_128 (.I0(1'b0), .O(s_level_out_bus_d4[6])); LUT1 #( .INIT(2'h2)) i_129 (.I0(1'b0), .O(s_level_out_bus_d4[5])); LUT1 #( .INIT(2'h2)) i_13 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[25])); LUT1 #( .INIT(2'h2)) i_130 (.I0(1'b0), .O(s_level_out_bus_d4[4])); LUT1 #( .INIT(2'h2)) i_131 (.I0(1'b0), .O(s_level_out_bus_d4[3])); LUT1 #( .INIT(2'h2)) i_132 (.I0(1'b0), .O(s_level_out_bus_d4[2])); LUT1 #( .INIT(2'h2)) i_133 (.I0(1'b0), .O(s_level_out_bus_d4[1])); LUT1 #( .INIT(2'h2)) i_134 (.I0(1'b0), .O(s_level_out_bus_d4[0])); LUT1 #( .INIT(2'h2)) i_135 (.I0(1'b0), .O(s_level_out_bus_d5[31])); LUT1 #( .INIT(2'h2)) i_136 (.I0(1'b0), .O(s_level_out_bus_d5[30])); LUT1 #( .INIT(2'h2)) i_137 (.I0(1'b0), .O(s_level_out_bus_d5[29])); LUT1 #( .INIT(2'h2)) i_138 (.I0(1'b0), .O(s_level_out_bus_d5[28])); LUT1 #( .INIT(2'h2)) i_139 (.I0(1'b0), .O(s_level_out_bus_d5[27])); LUT1 #( .INIT(2'h2)) i_14 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[24])); LUT1 #( .INIT(2'h2)) i_140 (.I0(1'b0), .O(s_level_out_bus_d5[26])); LUT1 #( .INIT(2'h2)) i_141 (.I0(1'b0), .O(s_level_out_bus_d5[25])); LUT1 #( .INIT(2'h2)) i_142 (.I0(1'b0), .O(s_level_out_bus_d5[24])); LUT1 #( .INIT(2'h2)) i_143 (.I0(1'b0), .O(s_level_out_bus_d5[23])); LUT1 #( .INIT(2'h2)) i_144 (.I0(1'b0), .O(s_level_out_bus_d5[22])); LUT1 #( .INIT(2'h2)) i_145 (.I0(1'b0), .O(s_level_out_bus_d5[21])); LUT1 #( .INIT(2'h2)) i_146 (.I0(1'b0), .O(s_level_out_bus_d5[20])); LUT1 #( .INIT(2'h2)) i_147 (.I0(1'b0), .O(s_level_out_bus_d5[19])); LUT1 #( .INIT(2'h2)) i_148 (.I0(1'b0), .O(s_level_out_bus_d5[18])); LUT1 #( .INIT(2'h2)) i_149 (.I0(1'b0), .O(s_level_out_bus_d5[17])); LUT1 #( .INIT(2'h2)) i_15 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[23])); LUT1 #( .INIT(2'h2)) i_150 (.I0(1'b0), .O(s_level_out_bus_d5[16])); LUT1 #( .INIT(2'h2)) i_151 (.I0(1'b0), .O(s_level_out_bus_d5[15])); LUT1 #( .INIT(2'h2)) i_152 (.I0(1'b0), .O(s_level_out_bus_d5[14])); LUT1 #( .INIT(2'h2)) i_153 (.I0(1'b0), .O(s_level_out_bus_d5[13])); LUT1 #( .INIT(2'h2)) i_154 (.I0(1'b0), .O(s_level_out_bus_d5[12])); LUT1 #( .INIT(2'h2)) i_155 (.I0(1'b0), .O(s_level_out_bus_d5[11])); LUT1 #( .INIT(2'h2)) i_156 (.I0(1'b0), .O(s_level_out_bus_d5[10])); LUT1 #( .INIT(2'h2)) i_157 (.I0(1'b0), .O(s_level_out_bus_d5[9])); LUT1 #( .INIT(2'h2)) i_158 (.I0(1'b0), .O(s_level_out_bus_d5[8])); LUT1 #( .INIT(2'h2)) i_159 (.I0(1'b0), .O(s_level_out_bus_d5[7])); LUT1 #( .INIT(2'h2)) i_16 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[22])); LUT1 #( .INIT(2'h2)) i_160 (.I0(1'b0), .O(s_level_out_bus_d5[6])); LUT1 #( .INIT(2'h2)) i_161 (.I0(1'b0), .O(s_level_out_bus_d5[5])); LUT1 #( .INIT(2'h2)) i_162 (.I0(1'b0), .O(s_level_out_bus_d5[4])); LUT1 #( .INIT(2'h2)) i_163 (.I0(1'b0), .O(s_level_out_bus_d5[3])); LUT1 #( .INIT(2'h2)) i_164 (.I0(1'b0), .O(s_level_out_bus_d5[2])); LUT1 #( .INIT(2'h2)) i_165 (.I0(1'b0), .O(s_level_out_bus_d5[1])); LUT1 #( .INIT(2'h2)) i_166 (.I0(1'b0), .O(s_level_out_bus_d5[0])); LUT1 #( .INIT(2'h2)) i_167 (.I0(1'b0), .O(s_level_out_bus_d6[31])); LUT1 #( .INIT(2'h2)) i_168 (.I0(1'b0), .O(s_level_out_bus_d6[30])); LUT1 #( .INIT(2'h2)) i_169 (.I0(1'b0), .O(s_level_out_bus_d6[29])); LUT1 #( .INIT(2'h2)) i_17 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[21])); LUT1 #( .INIT(2'h2)) i_170 (.I0(1'b0), .O(s_level_out_bus_d6[28])); LUT1 #( .INIT(2'h2)) i_171 (.I0(1'b0), .O(s_level_out_bus_d6[27])); LUT1 #( .INIT(2'h2)) i_172 (.I0(1'b0), .O(s_level_out_bus_d6[26])); LUT1 #( .INIT(2'h2)) i_173 (.I0(1'b0), .O(s_level_out_bus_d6[25])); LUT1 #( .INIT(2'h2)) i_174 (.I0(1'b0), .O(s_level_out_bus_d6[24])); LUT1 #( .INIT(2'h2)) i_175 (.I0(1'b0), .O(s_level_out_bus_d6[23])); LUT1 #( .INIT(2'h2)) i_176 (.I0(1'b0), .O(s_level_out_bus_d6[22])); LUT1 #( .INIT(2'h2)) i_177 (.I0(1'b0), .O(s_level_out_bus_d6[21])); LUT1 #( .INIT(2'h2)) i_178 (.I0(1'b0), .O(s_level_out_bus_d6[20])); LUT1 #( .INIT(2'h2)) i_179 (.I0(1'b0), .O(s_level_out_bus_d6[19])); LUT1 #( .INIT(2'h2)) i_18 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[20])); LUT1 #( .INIT(2'h2)) i_180 (.I0(1'b0), .O(s_level_out_bus_d6[18])); LUT1 #( .INIT(2'h2)) i_181 (.I0(1'b0), .O(s_level_out_bus_d6[17])); LUT1 #( .INIT(2'h2)) i_182 (.I0(1'b0), .O(s_level_out_bus_d6[16])); LUT1 #( .INIT(2'h2)) i_183 (.I0(1'b0), .O(s_level_out_bus_d6[15])); LUT1 #( .INIT(2'h2)) i_184 (.I0(1'b0), .O(s_level_out_bus_d6[14])); LUT1 #( .INIT(2'h2)) i_185 (.I0(1'b0), .O(s_level_out_bus_d6[13])); LUT1 #( .INIT(2'h2)) i_186 (.I0(1'b0), .O(s_level_out_bus_d6[12])); LUT1 #( .INIT(2'h2)) i_187 (.I0(1'b0), .O(s_level_out_bus_d6[11])); LUT1 #( .INIT(2'h2)) i_188 (.I0(1'b0), .O(s_level_out_bus_d6[10])); LUT1 #( .INIT(2'h2)) i_189 (.I0(1'b0), .O(s_level_out_bus_d6[9])); LUT1 #( .INIT(2'h2)) i_19 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[19])); LUT1 #( .INIT(2'h2)) i_190 (.I0(1'b0), .O(s_level_out_bus_d6[8])); LUT1 #( .INIT(2'h2)) i_191 (.I0(1'b0), .O(s_level_out_bus_d6[7])); LUT1 #( .INIT(2'h2)) i_192 (.I0(1'b0), .O(s_level_out_bus_d6[6])); LUT1 #( .INIT(2'h2)) i_193 (.I0(1'b0), .O(s_level_out_bus_d6[5])); LUT1 #( .INIT(2'h2)) i_194 (.I0(1'b0), .O(s_level_out_bus_d6[4])); LUT1 #( .INIT(2'h2)) i_195 (.I0(1'b0), .O(s_level_out_bus_d6[3])); LUT1 #( .INIT(2'h2)) i_196 (.I0(1'b0), .O(s_level_out_bus_d6[2])); LUT1 #( .INIT(2'h2)) i_197 (.I0(1'b0), .O(s_level_out_bus_d6[1])); LUT1 #( .INIT(2'h2)) i_198 (.I0(1'b0), .O(s_level_out_bus_d6[0])); LUT1 #( .INIT(2'h2)) i_2 (.I0(1'b0), .O(s_out_d3)); LUT1 #( .INIT(2'h2)) i_20 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[18])); LUT1 #( .INIT(2'h2)) i_21 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[17])); LUT1 #( .INIT(2'h2)) i_22 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[16])); LUT1 #( .INIT(2'h2)) i_23 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[15])); LUT1 #( .INIT(2'h2)) i_24 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[14])); LUT1 #( .INIT(2'h2)) i_25 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[13])); LUT1 #( .INIT(2'h2)) i_26 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[12])); LUT1 #( .INIT(2'h2)) i_27 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[11])); LUT1 #( .INIT(2'h2)) i_28 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[10])); LUT1 #( .INIT(2'h2)) i_29 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[9])); LUT1 #( .INIT(2'h2)) i_3 (.I0(1'b0), .O(s_out_d4)); LUT1 #( .INIT(2'h2)) i_30 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[8])); LUT1 #( .INIT(2'h2)) i_31 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[7])); LUT1 #( .INIT(2'h2)) i_32 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[6])); LUT1 #( .INIT(2'h2)) i_33 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[5])); LUT1 #( .INIT(2'h2)) i_34 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[4])); LUT1 #( .INIT(2'h2)) i_35 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[3])); LUT1 #( .INIT(2'h2)) i_36 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[2])); LUT1 #( .INIT(2'h2)) i_37 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[1])); LUT1 #( .INIT(2'h2)) i_38 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[0])); LUT1 #( .INIT(2'h2)) i_39 (.I0(1'b0), .O(s_level_out_bus_d2[31])); LUT1 #( .INIT(2'h2)) i_4 (.I0(1'b0), .O(s_out_d5)); LUT1 #( .INIT(2'h2)) i_40 (.I0(1'b0), .O(s_level_out_bus_d2[30])); LUT1 #( .INIT(2'h2)) i_41 (.I0(1'b0), .O(s_level_out_bus_d2[29])); LUT1 #( .INIT(2'h2)) i_42 (.I0(1'b0), .O(s_level_out_bus_d2[28])); LUT1 #( .INIT(2'h2)) i_43 (.I0(1'b0), .O(s_level_out_bus_d2[27])); LUT1 #( .INIT(2'h2)) i_44 (.I0(1'b0), .O(s_level_out_bus_d2[26])); LUT1 #( .INIT(2'h2)) i_45 (.I0(1'b0), .O(s_level_out_bus_d2[25])); LUT1 #( .INIT(2'h2)) i_46 (.I0(1'b0), .O(s_level_out_bus_d2[24])); LUT1 #( .INIT(2'h2)) i_47 (.I0(1'b0), .O(s_level_out_bus_d2[23])); LUT1 #( .INIT(2'h2)) i_48 (.I0(1'b0), .O(s_level_out_bus_d2[22])); LUT1 #( .INIT(2'h2)) i_49 (.I0(1'b0), .O(s_level_out_bus_d2[21])); LUT1 #( .INIT(2'h2)) i_5 (.I0(1'b0), .O(s_out_d6)); LUT1 #( .INIT(2'h2)) i_50 (.I0(1'b0), .O(s_level_out_bus_d2[20])); LUT1 #( .INIT(2'h2)) i_51 (.I0(1'b0), .O(s_level_out_bus_d2[19])); LUT1 #( .INIT(2'h2)) i_52 (.I0(1'b0), .O(s_level_out_bus_d2[18])); LUT1 #( .INIT(2'h2)) i_53 (.I0(1'b0), .O(s_level_out_bus_d2[17])); LUT1 #( .INIT(2'h2)) i_54 (.I0(1'b0), .O(s_level_out_bus_d2[16])); LUT1 #( .INIT(2'h2)) i_55 (.I0(1'b0), .O(s_level_out_bus_d2[15])); LUT1 #( .INIT(2'h2)) i_56 (.I0(1'b0), .O(s_level_out_bus_d2[14])); LUT1 #( .INIT(2'h2)) i_57 (.I0(1'b0), .O(s_level_out_bus_d2[13])); LUT1 #( .INIT(2'h2)) i_58 (.I0(1'b0), .O(s_level_out_bus_d2[12])); LUT1 #( .INIT(2'h2)) i_59 (.I0(1'b0), .O(s_level_out_bus_d2[11])); LUT1 #( .INIT(2'h2)) i_6 (.I0(1'b0), .O(s_out_d7)); LUT1 #( .INIT(2'h2)) i_60 (.I0(1'b0), .O(s_level_out_bus_d2[10])); LUT1 #( .INIT(2'h2)) i_61 (.I0(1'b0), .O(s_level_out_bus_d2[9])); LUT1 #( .INIT(2'h2)) i_62 (.I0(1'b0), .O(s_level_out_bus_d2[8])); LUT1 #( .INIT(2'h2)) i_63 (.I0(1'b0), .O(s_level_out_bus_d2[7])); LUT1 #( .INIT(2'h2)) i_64 (.I0(1'b0), .O(s_level_out_bus_d2[6])); LUT1 #( .INIT(2'h2)) i_65 (.I0(1'b0), .O(s_level_out_bus_d2[5])); LUT1 #( .INIT(2'h2)) i_66 (.I0(1'b0), .O(s_level_out_bus_d2[4])); LUT1 #( .INIT(2'h2)) i_67 (.I0(1'b0), .O(s_level_out_bus_d2[3])); LUT1 #( .INIT(2'h2)) i_68 (.I0(1'b0), .O(s_level_out_bus_d2[2])); LUT1 #( .INIT(2'h2)) i_69 (.I0(1'b0), .O(s_level_out_bus_d2[1])); LUT1 #( .INIT(2'h2)) i_7 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[31])); LUT1 #( .INIT(2'h2)) i_70 (.I0(1'b0), .O(s_level_out_bus_d2[0])); LUT1 #( .INIT(2'h2)) i_71 (.I0(1'b0), .O(s_level_out_bus_d3[31])); LUT1 #( .INIT(2'h2)) i_72 (.I0(1'b0), .O(s_level_out_bus_d3[30])); LUT1 #( .INIT(2'h2)) i_73 (.I0(1'b0), .O(s_level_out_bus_d3[29])); LUT1 #( .INIT(2'h2)) i_74 (.I0(1'b0), .O(s_level_out_bus_d3[28])); LUT1 #( .INIT(2'h2)) i_75 (.I0(1'b0), .O(s_level_out_bus_d3[27])); LUT1 #( .INIT(2'h2)) i_76 (.I0(1'b0), .O(s_level_out_bus_d3[26])); LUT1 #( .INIT(2'h2)) i_77 (.I0(1'b0), .O(s_level_out_bus_d3[25])); LUT1 #( .INIT(2'h2)) i_78 (.I0(1'b0), .O(s_level_out_bus_d3[24])); LUT1 #( .INIT(2'h2)) i_79 (.I0(1'b0), .O(s_level_out_bus_d3[23])); LUT1 #( .INIT(2'h2)) i_8 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[30])); LUT1 #( .INIT(2'h2)) i_80 (.I0(1'b0), .O(s_level_out_bus_d3[22])); LUT1 #( .INIT(2'h2)) i_81 (.I0(1'b0), .O(s_level_out_bus_d3[21])); LUT1 #( .INIT(2'h2)) i_82 (.I0(1'b0), .O(s_level_out_bus_d3[20])); LUT1 #( .INIT(2'h2)) i_83 (.I0(1'b0), .O(s_level_out_bus_d3[19])); LUT1 #( .INIT(2'h2)) i_84 (.I0(1'b0), .O(s_level_out_bus_d3[18])); LUT1 #( .INIT(2'h2)) i_85 (.I0(1'b0), .O(s_level_out_bus_d3[17])); LUT1 #( .INIT(2'h2)) i_86 (.I0(1'b0), .O(s_level_out_bus_d3[16])); LUT1 #( .INIT(2'h2)) i_87 (.I0(1'b0), .O(s_level_out_bus_d3[15])); LUT1 #( .INIT(2'h2)) i_88 (.I0(1'b0), .O(s_level_out_bus_d3[14])); LUT1 #( .INIT(2'h2)) i_89 (.I0(1'b0), .O(s_level_out_bus_d3[13])); LUT1 #( .INIT(2'h2)) i_9 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[29])); LUT1 #( .INIT(2'h2)) i_90 (.I0(1'b0), .O(s_level_out_bus_d3[12])); LUT1 #( .INIT(2'h2)) i_91 (.I0(1'b0), .O(s_level_out_bus_d3[11])); LUT1 #( .INIT(2'h2)) i_92 (.I0(1'b0), .O(s_level_out_bus_d3[10])); LUT1 #( .INIT(2'h2)) i_93 (.I0(1'b0), .O(s_level_out_bus_d3[9])); LUT1 #( .INIT(2'h2)) i_94 (.I0(1'b0), .O(s_level_out_bus_d3[8])); LUT1 #( .INIT(2'h2)) i_95 (.I0(1'b0), .O(s_level_out_bus_d3[7])); LUT1 #( .INIT(2'h2)) i_96 (.I0(1'b0), .O(s_level_out_bus_d3[6])); LUT1 #( .INIT(2'h2)) i_97 (.I0(1'b0), .O(s_level_out_bus_d3[5])); LUT1 #( .INIT(2'h2)) i_98 (.I0(1'b0), .O(s_level_out_bus_d3[4])); LUT1 #( .INIT(2'h2)) i_99 (.I0(1'b0), .O(s_level_out_bus_d3[3])); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d1_aurora_64b66b_0_cdc_to_reg (.C(init_clk), .CE(1'b1), .D(p_level_in_int), .Q(s_level_out_d1_aurora_64b66b_0_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d2_reg (.C(init_clk), .CE(1'b1), .D(s_level_out_d1_aurora_64b66b_0_cdc_to), .Q(s_level_out_d2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d3_reg (.C(init_clk), .CE(1'b1), .D(s_level_out_d2), .Q(s_level_out_d3), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d4_reg (.C(init_clk), .CE(1'b1), .D(s_level_out_d3), .Q(s_level_out_d4), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d5_reg (.C(init_clk), .CE(1'b1), .D(s_level_out_d4), .Q(s_level_out_d5), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d6_reg (.C(init_clk), .CE(1'b1), .D(s_level_out_d5), .Q(s_level_out_d6), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_cdc_sync" *) module aurora_64b66b_0_aurora_64b66b_0_cdc_sync__parameterized0_20 (\cb_bit_err_ext_cnt_reg[3] , gtwiz_userclk_rx_usrclk_out, Q, reset_cbcc_comb_reg); output \cb_bit_err_ext_cnt_reg[3] ; input gtwiz_userclk_rx_usrclk_out; input [3:0]Q; input [0:0]reset_cbcc_comb_reg; wire [3:0]Q; wire \cb_bit_err_ext_cnt_reg[3] ; wire gtwiz_userclk_rx_usrclk_out; wire p_level_in_int; wire [0:0]reset_cbcc_comb_reg; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d3; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d4; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d5; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d6; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d3; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d4; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d5; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d6; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d3; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d4; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d5; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d6; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d7; LUT1 #( .INIT(2'h2)) i_0 (.I0(1'b0), .O(p_level_in_int)); LUT1 #( .INIT(2'h2)) i_1 (.I0(1'b0), .O(s_out_d1_aurora_64b66b_0_cdc_to)); LUT1 #( .INIT(2'h2)) i_10 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[29])); LUT1 #( .INIT(2'h2)) i_100 (.I0(1'b0), .O(s_level_out_bus_d3[3])); LUT1 #( .INIT(2'h2)) i_101 (.I0(1'b0), .O(s_level_out_bus_d3[2])); LUT1 #( .INIT(2'h2)) i_102 (.I0(1'b0), .O(s_level_out_bus_d3[1])); LUT1 #( .INIT(2'h2)) i_103 (.I0(1'b0), .O(s_level_out_bus_d3[0])); LUT1 #( .INIT(2'h2)) i_104 (.I0(1'b0), .O(s_level_out_bus_d4[31])); LUT1 #( .INIT(2'h2)) i_105 (.I0(1'b0), .O(s_level_out_bus_d4[30])); LUT1 #( .INIT(2'h2)) i_106 (.I0(1'b0), .O(s_level_out_bus_d4[29])); LUT1 #( .INIT(2'h2)) i_107 (.I0(1'b0), .O(s_level_out_bus_d4[28])); LUT1 #( .INIT(2'h2)) i_108 (.I0(1'b0), .O(s_level_out_bus_d4[27])); LUT1 #( .INIT(2'h2)) i_109 (.I0(1'b0), .O(s_level_out_bus_d4[26])); LUT1 #( .INIT(2'h2)) i_11 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[28])); LUT1 #( .INIT(2'h2)) i_110 (.I0(1'b0), .O(s_level_out_bus_d4[25])); LUT1 #( .INIT(2'h2)) i_111 (.I0(1'b0), .O(s_level_out_bus_d4[24])); LUT1 #( .INIT(2'h2)) i_112 (.I0(1'b0), .O(s_level_out_bus_d4[23])); LUT1 #( .INIT(2'h2)) i_113 (.I0(1'b0), .O(s_level_out_bus_d4[22])); LUT1 #( .INIT(2'h2)) i_114 (.I0(1'b0), .O(s_level_out_bus_d4[21])); LUT1 #( .INIT(2'h2)) i_115 (.I0(1'b0), .O(s_level_out_bus_d4[20])); LUT1 #( .INIT(2'h2)) i_116 (.I0(1'b0), .O(s_level_out_bus_d4[19])); LUT1 #( .INIT(2'h2)) i_117 (.I0(1'b0), .O(s_level_out_bus_d4[18])); LUT1 #( .INIT(2'h2)) i_118 (.I0(1'b0), .O(s_level_out_bus_d4[17])); LUT1 #( .INIT(2'h2)) i_119 (.I0(1'b0), .O(s_level_out_bus_d4[16])); LUT1 #( .INIT(2'h2)) i_12 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[27])); LUT1 #( .INIT(2'h2)) i_120 (.I0(1'b0), .O(s_level_out_bus_d4[15])); LUT1 #( .INIT(2'h2)) i_121 (.I0(1'b0), .O(s_level_out_bus_d4[14])); LUT1 #( .INIT(2'h2)) i_122 (.I0(1'b0), .O(s_level_out_bus_d4[13])); LUT1 #( .INIT(2'h2)) i_123 (.I0(1'b0), .O(s_level_out_bus_d4[12])); LUT1 #( .INIT(2'h2)) i_124 (.I0(1'b0), .O(s_level_out_bus_d4[11])); LUT1 #( .INIT(2'h2)) i_125 (.I0(1'b0), .O(s_level_out_bus_d4[10])); LUT1 #( .INIT(2'h2)) i_126 (.I0(1'b0), .O(s_level_out_bus_d4[9])); LUT1 #( .INIT(2'h2)) i_127 (.I0(1'b0), .O(s_level_out_bus_d4[8])); LUT1 #( .INIT(2'h2)) i_128 (.I0(1'b0), .O(s_level_out_bus_d4[7])); LUT1 #( .INIT(2'h2)) i_129 (.I0(1'b0), .O(s_level_out_bus_d4[6])); LUT1 #( .INIT(2'h2)) i_13 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[26])); LUT1 #( .INIT(2'h2)) i_130 (.I0(1'b0), .O(s_level_out_bus_d4[5])); LUT1 #( .INIT(2'h2)) i_131 (.I0(1'b0), .O(s_level_out_bus_d4[4])); LUT1 #( .INIT(2'h2)) i_132 (.I0(1'b0), .O(s_level_out_bus_d4[3])); LUT1 #( .INIT(2'h2)) i_133 (.I0(1'b0), .O(s_level_out_bus_d4[2])); LUT1 #( .INIT(2'h2)) i_134 (.I0(1'b0), .O(s_level_out_bus_d4[1])); LUT1 #( .INIT(2'h2)) i_135 (.I0(1'b0), .O(s_level_out_bus_d4[0])); LUT1 #( .INIT(2'h2)) i_136 (.I0(1'b0), .O(s_level_out_bus_d5[31])); LUT1 #( .INIT(2'h2)) i_137 (.I0(1'b0), .O(s_level_out_bus_d5[30])); LUT1 #( .INIT(2'h2)) i_138 (.I0(1'b0), .O(s_level_out_bus_d5[29])); LUT1 #( .INIT(2'h2)) i_139 (.I0(1'b0), .O(s_level_out_bus_d5[28])); LUT1 #( .INIT(2'h2)) i_14 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[25])); LUT1 #( .INIT(2'h2)) i_140 (.I0(1'b0), .O(s_level_out_bus_d5[27])); LUT1 #( .INIT(2'h2)) i_141 (.I0(1'b0), .O(s_level_out_bus_d5[26])); LUT1 #( .INIT(2'h2)) i_142 (.I0(1'b0), .O(s_level_out_bus_d5[25])); LUT1 #( .INIT(2'h2)) i_143 (.I0(1'b0), .O(s_level_out_bus_d5[24])); LUT1 #( .INIT(2'h2)) i_144 (.I0(1'b0), .O(s_level_out_bus_d5[23])); LUT1 #( .INIT(2'h2)) i_145 (.I0(1'b0), .O(s_level_out_bus_d5[22])); LUT1 #( .INIT(2'h2)) i_146 (.I0(1'b0), .O(s_level_out_bus_d5[21])); LUT1 #( .INIT(2'h2)) i_147 (.I0(1'b0), .O(s_level_out_bus_d5[20])); LUT1 #( .INIT(2'h2)) i_148 (.I0(1'b0), .O(s_level_out_bus_d5[19])); LUT1 #( .INIT(2'h2)) i_149 (.I0(1'b0), .O(s_level_out_bus_d5[18])); LUT1 #( .INIT(2'h2)) i_15 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[24])); LUT1 #( .INIT(2'h2)) i_150 (.I0(1'b0), .O(s_level_out_bus_d5[17])); LUT1 #( .INIT(2'h2)) i_151 (.I0(1'b0), .O(s_level_out_bus_d5[16])); LUT1 #( .INIT(2'h2)) i_152 (.I0(1'b0), .O(s_level_out_bus_d5[15])); LUT1 #( .INIT(2'h2)) i_153 (.I0(1'b0), .O(s_level_out_bus_d5[14])); LUT1 #( .INIT(2'h2)) i_154 (.I0(1'b0), .O(s_level_out_bus_d5[13])); LUT1 #( .INIT(2'h2)) i_155 (.I0(1'b0), .O(s_level_out_bus_d5[12])); LUT1 #( .INIT(2'h2)) i_156 (.I0(1'b0), .O(s_level_out_bus_d5[11])); LUT1 #( .INIT(2'h2)) i_157 (.I0(1'b0), .O(s_level_out_bus_d5[10])); LUT1 #( .INIT(2'h2)) i_158 (.I0(1'b0), .O(s_level_out_bus_d5[9])); LUT1 #( .INIT(2'h2)) i_159 (.I0(1'b0), .O(s_level_out_bus_d5[8])); LUT1 #( .INIT(2'h2)) i_16 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[23])); LUT1 #( .INIT(2'h2)) i_160 (.I0(1'b0), .O(s_level_out_bus_d5[7])); LUT1 #( .INIT(2'h2)) i_161 (.I0(1'b0), .O(s_level_out_bus_d5[6])); LUT1 #( .INIT(2'h2)) i_162 (.I0(1'b0), .O(s_level_out_bus_d5[5])); LUT1 #( .INIT(2'h2)) i_163 (.I0(1'b0), .O(s_level_out_bus_d5[4])); LUT1 #( .INIT(2'h2)) i_164 (.I0(1'b0), .O(s_level_out_bus_d5[3])); LUT1 #( .INIT(2'h2)) i_165 (.I0(1'b0), .O(s_level_out_bus_d5[2])); LUT1 #( .INIT(2'h2)) i_166 (.I0(1'b0), .O(s_level_out_bus_d5[1])); LUT1 #( .INIT(2'h2)) i_167 (.I0(1'b0), .O(s_level_out_bus_d5[0])); LUT1 #( .INIT(2'h2)) i_168 (.I0(1'b0), .O(s_level_out_bus_d6[31])); LUT1 #( .INIT(2'h2)) i_169 (.I0(1'b0), .O(s_level_out_bus_d6[30])); LUT1 #( .INIT(2'h2)) i_17 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[22])); LUT1 #( .INIT(2'h2)) i_170 (.I0(1'b0), .O(s_level_out_bus_d6[29])); LUT1 #( .INIT(2'h2)) i_171 (.I0(1'b0), .O(s_level_out_bus_d6[28])); LUT1 #( .INIT(2'h2)) i_172 (.I0(1'b0), .O(s_level_out_bus_d6[27])); LUT1 #( .INIT(2'h2)) i_173 (.I0(1'b0), .O(s_level_out_bus_d6[26])); LUT1 #( .INIT(2'h2)) i_174 (.I0(1'b0), .O(s_level_out_bus_d6[25])); LUT1 #( .INIT(2'h2)) i_175 (.I0(1'b0), .O(s_level_out_bus_d6[24])); LUT1 #( .INIT(2'h2)) i_176 (.I0(1'b0), .O(s_level_out_bus_d6[23])); LUT1 #( .INIT(2'h2)) i_177 (.I0(1'b0), .O(s_level_out_bus_d6[22])); LUT1 #( .INIT(2'h2)) i_178 (.I0(1'b0), .O(s_level_out_bus_d6[21])); LUT1 #( .INIT(2'h2)) i_179 (.I0(1'b0), .O(s_level_out_bus_d6[20])); LUT1 #( .INIT(2'h2)) i_18 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[21])); LUT1 #( .INIT(2'h2)) i_180 (.I0(1'b0), .O(s_level_out_bus_d6[19])); LUT1 #( .INIT(2'h2)) i_181 (.I0(1'b0), .O(s_level_out_bus_d6[18])); LUT1 #( .INIT(2'h2)) i_182 (.I0(1'b0), .O(s_level_out_bus_d6[17])); LUT1 #( .INIT(2'h2)) i_183 (.I0(1'b0), .O(s_level_out_bus_d6[16])); LUT1 #( .INIT(2'h2)) i_184 (.I0(1'b0), .O(s_level_out_bus_d6[15])); LUT1 #( .INIT(2'h2)) i_185 (.I0(1'b0), .O(s_level_out_bus_d6[14])); LUT1 #( .INIT(2'h2)) i_186 (.I0(1'b0), .O(s_level_out_bus_d6[13])); LUT1 #( .INIT(2'h2)) i_187 (.I0(1'b0), .O(s_level_out_bus_d6[12])); LUT1 #( .INIT(2'h2)) i_188 (.I0(1'b0), .O(s_level_out_bus_d6[11])); LUT1 #( .INIT(2'h2)) i_189 (.I0(1'b0), .O(s_level_out_bus_d6[10])); LUT1 #( .INIT(2'h2)) i_19 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[20])); LUT1 #( .INIT(2'h2)) i_190 (.I0(1'b0), .O(s_level_out_bus_d6[9])); LUT1 #( .INIT(2'h2)) i_191 (.I0(1'b0), .O(s_level_out_bus_d6[8])); LUT1 #( .INIT(2'h2)) i_192 (.I0(1'b0), .O(s_level_out_bus_d6[7])); LUT1 #( .INIT(2'h2)) i_193 (.I0(1'b0), .O(s_level_out_bus_d6[6])); LUT1 #( .INIT(2'h2)) i_194 (.I0(1'b0), .O(s_level_out_bus_d6[5])); LUT1 #( .INIT(2'h2)) i_195 (.I0(1'b0), .O(s_level_out_bus_d6[4])); LUT1 #( .INIT(2'h2)) i_196 (.I0(1'b0), .O(s_level_out_bus_d6[3])); LUT1 #( .INIT(2'h2)) i_197 (.I0(1'b0), .O(s_level_out_bus_d6[2])); LUT1 #( .INIT(2'h2)) i_198 (.I0(1'b0), .O(s_level_out_bus_d6[1])); LUT1 #( .INIT(2'h2)) i_199 (.I0(1'b0), .O(s_level_out_bus_d6[0])); LUT1 #( .INIT(2'h2)) i_2 (.I0(1'b0), .O(s_out_d2)); LUT1 #( .INIT(2'h2)) i_20 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[19])); LUT1 #( .INIT(2'h2)) i_21 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[18])); LUT1 #( .INIT(2'h2)) i_22 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[17])); LUT1 #( .INIT(2'h2)) i_23 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[16])); LUT1 #( .INIT(2'h2)) i_24 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[15])); LUT1 #( .INIT(2'h2)) i_25 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[14])); LUT1 #( .INIT(2'h2)) i_26 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[13])); LUT1 #( .INIT(2'h2)) i_27 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[12])); LUT1 #( .INIT(2'h2)) i_28 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[11])); LUT1 #( .INIT(2'h2)) i_29 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[10])); LUT1 #( .INIT(2'h2)) i_3 (.I0(1'b0), .O(s_out_d3)); LUT1 #( .INIT(2'h2)) i_30 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[9])); LUT1 #( .INIT(2'h2)) i_31 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[8])); LUT1 #( .INIT(2'h2)) i_32 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[7])); LUT1 #( .INIT(2'h2)) i_33 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[6])); LUT1 #( .INIT(2'h2)) i_34 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[5])); LUT1 #( .INIT(2'h2)) i_35 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[4])); LUT1 #( .INIT(2'h2)) i_36 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[3])); LUT1 #( .INIT(2'h2)) i_37 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[2])); LUT1 #( .INIT(2'h2)) i_38 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[1])); LUT1 #( .INIT(2'h2)) i_39 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[0])); LUT1 #( .INIT(2'h2)) i_4 (.I0(1'b0), .O(s_out_d4)); LUT1 #( .INIT(2'h2)) i_40 (.I0(1'b0), .O(s_level_out_bus_d2[31])); LUT1 #( .INIT(2'h2)) i_41 (.I0(1'b0), .O(s_level_out_bus_d2[30])); LUT1 #( .INIT(2'h2)) i_42 (.I0(1'b0), .O(s_level_out_bus_d2[29])); LUT1 #( .INIT(2'h2)) i_43 (.I0(1'b0), .O(s_level_out_bus_d2[28])); LUT1 #( .INIT(2'h2)) i_44 (.I0(1'b0), .O(s_level_out_bus_d2[27])); LUT1 #( .INIT(2'h2)) i_45 (.I0(1'b0), .O(s_level_out_bus_d2[26])); LUT1 #( .INIT(2'h2)) i_46 (.I0(1'b0), .O(s_level_out_bus_d2[25])); LUT1 #( .INIT(2'h2)) i_47 (.I0(1'b0), .O(s_level_out_bus_d2[24])); LUT1 #( .INIT(2'h2)) i_48 (.I0(1'b0), .O(s_level_out_bus_d2[23])); LUT1 #( .INIT(2'h2)) i_49 (.I0(1'b0), .O(s_level_out_bus_d2[22])); LUT1 #( .INIT(2'h2)) i_5 (.I0(1'b0), .O(s_out_d5)); LUT1 #( .INIT(2'h2)) i_50 (.I0(1'b0), .O(s_level_out_bus_d2[21])); LUT1 #( .INIT(2'h2)) i_51 (.I0(1'b0), .O(s_level_out_bus_d2[20])); LUT1 #( .INIT(2'h2)) i_52 (.I0(1'b0), .O(s_level_out_bus_d2[19])); LUT1 #( .INIT(2'h2)) i_53 (.I0(1'b0), .O(s_level_out_bus_d2[18])); LUT1 #( .INIT(2'h2)) i_54 (.I0(1'b0), .O(s_level_out_bus_d2[17])); LUT1 #( .INIT(2'h2)) i_55 (.I0(1'b0), .O(s_level_out_bus_d2[16])); LUT1 #( .INIT(2'h2)) i_56 (.I0(1'b0), .O(s_level_out_bus_d2[15])); LUT1 #( .INIT(2'h2)) i_57 (.I0(1'b0), .O(s_level_out_bus_d2[14])); LUT1 #( .INIT(2'h2)) i_58 (.I0(1'b0), .O(s_level_out_bus_d2[13])); LUT1 #( .INIT(2'h2)) i_59 (.I0(1'b0), .O(s_level_out_bus_d2[12])); LUT1 #( .INIT(2'h2)) i_6 (.I0(1'b0), .O(s_out_d6)); LUT1 #( .INIT(2'h2)) i_60 (.I0(1'b0), .O(s_level_out_bus_d2[11])); LUT1 #( .INIT(2'h2)) i_61 (.I0(1'b0), .O(s_level_out_bus_d2[10])); LUT1 #( .INIT(2'h2)) i_62 (.I0(1'b0), .O(s_level_out_bus_d2[9])); LUT1 #( .INIT(2'h2)) i_63 (.I0(1'b0), .O(s_level_out_bus_d2[8])); LUT1 #( .INIT(2'h2)) i_64 (.I0(1'b0), .O(s_level_out_bus_d2[7])); LUT1 #( .INIT(2'h2)) i_65 (.I0(1'b0), .O(s_level_out_bus_d2[6])); LUT1 #( .INIT(2'h2)) i_66 (.I0(1'b0), .O(s_level_out_bus_d2[5])); LUT1 #( .INIT(2'h2)) i_67 (.I0(1'b0), .O(s_level_out_bus_d2[4])); LUT1 #( .INIT(2'h2)) i_68 (.I0(1'b0), .O(s_level_out_bus_d2[3])); LUT1 #( .INIT(2'h2)) i_69 (.I0(1'b0), .O(s_level_out_bus_d2[2])); LUT1 #( .INIT(2'h2)) i_7 (.I0(1'b0), .O(s_out_d7)); LUT1 #( .INIT(2'h2)) i_70 (.I0(1'b0), .O(s_level_out_bus_d2[1])); LUT1 #( .INIT(2'h2)) i_71 (.I0(1'b0), .O(s_level_out_bus_d2[0])); LUT1 #( .INIT(2'h2)) i_72 (.I0(1'b0), .O(s_level_out_bus_d3[31])); LUT1 #( .INIT(2'h2)) i_73 (.I0(1'b0), .O(s_level_out_bus_d3[30])); LUT1 #( .INIT(2'h2)) i_74 (.I0(1'b0), .O(s_level_out_bus_d3[29])); LUT1 #( .INIT(2'h2)) i_75 (.I0(1'b0), .O(s_level_out_bus_d3[28])); LUT1 #( .INIT(2'h2)) i_76 (.I0(1'b0), .O(s_level_out_bus_d3[27])); LUT1 #( .INIT(2'h2)) i_77 (.I0(1'b0), .O(s_level_out_bus_d3[26])); LUT1 #( .INIT(2'h2)) i_78 (.I0(1'b0), .O(s_level_out_bus_d3[25])); LUT1 #( .INIT(2'h2)) i_79 (.I0(1'b0), .O(s_level_out_bus_d3[24])); LUT1 #( .INIT(2'h2)) i_8 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[31])); LUT1 #( .INIT(2'h2)) i_80 (.I0(1'b0), .O(s_level_out_bus_d3[23])); LUT1 #( .INIT(2'h2)) i_81 (.I0(1'b0), .O(s_level_out_bus_d3[22])); LUT1 #( .INIT(2'h2)) i_82 (.I0(1'b0), .O(s_level_out_bus_d3[21])); LUT1 #( .INIT(2'h2)) i_83 (.I0(1'b0), .O(s_level_out_bus_d3[20])); LUT1 #( .INIT(2'h2)) i_84 (.I0(1'b0), .O(s_level_out_bus_d3[19])); LUT1 #( .INIT(2'h2)) i_85 (.I0(1'b0), .O(s_level_out_bus_d3[18])); LUT1 #( .INIT(2'h2)) i_86 (.I0(1'b0), .O(s_level_out_bus_d3[17])); LUT1 #( .INIT(2'h2)) i_87 (.I0(1'b0), .O(s_level_out_bus_d3[16])); LUT1 #( .INIT(2'h2)) i_88 (.I0(1'b0), .O(s_level_out_bus_d3[15])); LUT1 #( .INIT(2'h2)) i_89 (.I0(1'b0), .O(s_level_out_bus_d3[14])); LUT1 #( .INIT(2'h2)) i_9 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[30])); LUT1 #( .INIT(2'h2)) i_90 (.I0(1'b0), .O(s_level_out_bus_d3[13])); LUT1 #( .INIT(2'h2)) i_91 (.I0(1'b0), .O(s_level_out_bus_d3[12])); LUT1 #( .INIT(2'h2)) i_92 (.I0(1'b0), .O(s_level_out_bus_d3[11])); LUT1 #( .INIT(2'h2)) i_93 (.I0(1'b0), .O(s_level_out_bus_d3[10])); LUT1 #( .INIT(2'h2)) i_94 (.I0(1'b0), .O(s_level_out_bus_d3[9])); LUT1 #( .INIT(2'h2)) i_95 (.I0(1'b0), .O(s_level_out_bus_d3[8])); LUT1 #( .INIT(2'h2)) i_96 (.I0(1'b0), .O(s_level_out_bus_d3[7])); LUT1 #( .INIT(2'h2)) i_97 (.I0(1'b0), .O(s_level_out_bus_d3[6])); LUT1 #( .INIT(2'h2)) i_98 (.I0(1'b0), .O(s_level_out_bus_d3[5])); LUT1 #( .INIT(2'h2)) i_99 (.I0(1'b0), .O(s_level_out_bus_d3[4])); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) reset_cbcc_comb_i_1 (.I0(Q[3]), .I1(Q[2]), .I2(Q[0]), .I3(Q[1]), .I4(s_level_out_d5), .I5(reset_cbcc_comb_reg), .O(\cb_bit_err_ext_cnt_reg[3] )); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d1_aurora_64b66b_0_cdc_to_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(p_level_in_int), .Q(s_level_out_d1_aurora_64b66b_0_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d2_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(s_level_out_d1_aurora_64b66b_0_cdc_to), .Q(s_level_out_d2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d3_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(s_level_out_d2), .Q(s_level_out_d3), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d4_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(s_level_out_d3), .Q(s_level_out_d4), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d5_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(s_level_out_d4), .Q(s_level_out_d5), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d6_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(s_level_out_d5), .Q(s_level_out_d6), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_cdc_sync" *) module aurora_64b66b_0_aurora_64b66b_0_cdc_sync__parameterized0_27 (s_level_out_d5_reg_0, in0, s_level_out_d5_reg_1); output s_level_out_d5_reg_0; input in0; input s_level_out_d5_reg_1; wire p_level_in_int; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d3; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d4; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d5; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d6; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d3; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d4; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d5; wire s_level_out_d5_reg_0; wire s_level_out_d5_reg_1; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d6; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d3; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d4; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d5; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d6; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d7; assign p_level_in_int = in0; LUT1 #( .INIT(2'h1)) CC_RXLOSSOFSYNC_OUT_i_1 (.I0(s_level_out_d5), .O(s_level_out_d5_reg_0)); LUT1 #( .INIT(2'h2)) i_0 (.I0(1'b0), .O(s_out_d1_aurora_64b66b_0_cdc_to)); LUT1 #( .INIT(2'h2)) i_1 (.I0(1'b0), .O(s_out_d2)); LUT1 #( .INIT(2'h2)) i_10 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[28])); LUT1 #( .INIT(2'h2)) i_100 (.I0(1'b0), .O(s_level_out_bus_d3[2])); LUT1 #( .INIT(2'h2)) i_101 (.I0(1'b0), .O(s_level_out_bus_d3[1])); LUT1 #( .INIT(2'h2)) i_102 (.I0(1'b0), .O(s_level_out_bus_d3[0])); LUT1 #( .INIT(2'h2)) i_103 (.I0(1'b0), .O(s_level_out_bus_d4[31])); LUT1 #( .INIT(2'h2)) i_104 (.I0(1'b0), .O(s_level_out_bus_d4[30])); LUT1 #( .INIT(2'h2)) i_105 (.I0(1'b0), .O(s_level_out_bus_d4[29])); LUT1 #( .INIT(2'h2)) i_106 (.I0(1'b0), .O(s_level_out_bus_d4[28])); LUT1 #( .INIT(2'h2)) i_107 (.I0(1'b0), .O(s_level_out_bus_d4[27])); LUT1 #( .INIT(2'h2)) i_108 (.I0(1'b0), .O(s_level_out_bus_d4[26])); LUT1 #( .INIT(2'h2)) i_109 (.I0(1'b0), .O(s_level_out_bus_d4[25])); LUT1 #( .INIT(2'h2)) i_11 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[27])); LUT1 #( .INIT(2'h2)) i_110 (.I0(1'b0), .O(s_level_out_bus_d4[24])); LUT1 #( .INIT(2'h2)) i_111 (.I0(1'b0), .O(s_level_out_bus_d4[23])); LUT1 #( .INIT(2'h2)) i_112 (.I0(1'b0), .O(s_level_out_bus_d4[22])); LUT1 #( .INIT(2'h2)) i_113 (.I0(1'b0), .O(s_level_out_bus_d4[21])); LUT1 #( .INIT(2'h2)) i_114 (.I0(1'b0), .O(s_level_out_bus_d4[20])); LUT1 #( .INIT(2'h2)) i_115 (.I0(1'b0), .O(s_level_out_bus_d4[19])); LUT1 #( .INIT(2'h2)) i_116 (.I0(1'b0), .O(s_level_out_bus_d4[18])); LUT1 #( .INIT(2'h2)) i_117 (.I0(1'b0), .O(s_level_out_bus_d4[17])); LUT1 #( .INIT(2'h2)) i_118 (.I0(1'b0), .O(s_level_out_bus_d4[16])); LUT1 #( .INIT(2'h2)) i_119 (.I0(1'b0), .O(s_level_out_bus_d4[15])); LUT1 #( .INIT(2'h2)) i_12 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[26])); LUT1 #( .INIT(2'h2)) i_120 (.I0(1'b0), .O(s_level_out_bus_d4[14])); LUT1 #( .INIT(2'h2)) i_121 (.I0(1'b0), .O(s_level_out_bus_d4[13])); LUT1 #( .INIT(2'h2)) i_122 (.I0(1'b0), .O(s_level_out_bus_d4[12])); LUT1 #( .INIT(2'h2)) i_123 (.I0(1'b0), .O(s_level_out_bus_d4[11])); LUT1 #( .INIT(2'h2)) i_124 (.I0(1'b0), .O(s_level_out_bus_d4[10])); LUT1 #( .INIT(2'h2)) i_125 (.I0(1'b0), .O(s_level_out_bus_d4[9])); LUT1 #( .INIT(2'h2)) i_126 (.I0(1'b0), .O(s_level_out_bus_d4[8])); LUT1 #( .INIT(2'h2)) i_127 (.I0(1'b0), .O(s_level_out_bus_d4[7])); LUT1 #( .INIT(2'h2)) i_128 (.I0(1'b0), .O(s_level_out_bus_d4[6])); LUT1 #( .INIT(2'h2)) i_129 (.I0(1'b0), .O(s_level_out_bus_d4[5])); LUT1 #( .INIT(2'h2)) i_13 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[25])); LUT1 #( .INIT(2'h2)) i_130 (.I0(1'b0), .O(s_level_out_bus_d4[4])); LUT1 #( .INIT(2'h2)) i_131 (.I0(1'b0), .O(s_level_out_bus_d4[3])); LUT1 #( .INIT(2'h2)) i_132 (.I0(1'b0), .O(s_level_out_bus_d4[2])); LUT1 #( .INIT(2'h2)) i_133 (.I0(1'b0), .O(s_level_out_bus_d4[1])); LUT1 #( .INIT(2'h2)) i_134 (.I0(1'b0), .O(s_level_out_bus_d4[0])); LUT1 #( .INIT(2'h2)) i_135 (.I0(1'b0), .O(s_level_out_bus_d5[31])); LUT1 #( .INIT(2'h2)) i_136 (.I0(1'b0), .O(s_level_out_bus_d5[30])); LUT1 #( .INIT(2'h2)) i_137 (.I0(1'b0), .O(s_level_out_bus_d5[29])); LUT1 #( .INIT(2'h2)) i_138 (.I0(1'b0), .O(s_level_out_bus_d5[28])); LUT1 #( .INIT(2'h2)) i_139 (.I0(1'b0), .O(s_level_out_bus_d5[27])); LUT1 #( .INIT(2'h2)) i_14 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[24])); LUT1 #( .INIT(2'h2)) i_140 (.I0(1'b0), .O(s_level_out_bus_d5[26])); LUT1 #( .INIT(2'h2)) i_141 (.I0(1'b0), .O(s_level_out_bus_d5[25])); LUT1 #( .INIT(2'h2)) i_142 (.I0(1'b0), .O(s_level_out_bus_d5[24])); LUT1 #( .INIT(2'h2)) i_143 (.I0(1'b0), .O(s_level_out_bus_d5[23])); LUT1 #( .INIT(2'h2)) i_144 (.I0(1'b0), .O(s_level_out_bus_d5[22])); LUT1 #( .INIT(2'h2)) i_145 (.I0(1'b0), .O(s_level_out_bus_d5[21])); LUT1 #( .INIT(2'h2)) i_146 (.I0(1'b0), .O(s_level_out_bus_d5[20])); LUT1 #( .INIT(2'h2)) i_147 (.I0(1'b0), .O(s_level_out_bus_d5[19])); LUT1 #( .INIT(2'h2)) i_148 (.I0(1'b0), .O(s_level_out_bus_d5[18])); LUT1 #( .INIT(2'h2)) i_149 (.I0(1'b0), .O(s_level_out_bus_d5[17])); LUT1 #( .INIT(2'h2)) i_15 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[23])); LUT1 #( .INIT(2'h2)) i_150 (.I0(1'b0), .O(s_level_out_bus_d5[16])); LUT1 #( .INIT(2'h2)) i_151 (.I0(1'b0), .O(s_level_out_bus_d5[15])); LUT1 #( .INIT(2'h2)) i_152 (.I0(1'b0), .O(s_level_out_bus_d5[14])); LUT1 #( .INIT(2'h2)) i_153 (.I0(1'b0), .O(s_level_out_bus_d5[13])); LUT1 #( .INIT(2'h2)) i_154 (.I0(1'b0), .O(s_level_out_bus_d5[12])); LUT1 #( .INIT(2'h2)) i_155 (.I0(1'b0), .O(s_level_out_bus_d5[11])); LUT1 #( .INIT(2'h2)) i_156 (.I0(1'b0), .O(s_level_out_bus_d5[10])); LUT1 #( .INIT(2'h2)) i_157 (.I0(1'b0), .O(s_level_out_bus_d5[9])); LUT1 #( .INIT(2'h2)) i_158 (.I0(1'b0), .O(s_level_out_bus_d5[8])); LUT1 #( .INIT(2'h2)) i_159 (.I0(1'b0), .O(s_level_out_bus_d5[7])); LUT1 #( .INIT(2'h2)) i_16 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[22])); LUT1 #( .INIT(2'h2)) i_160 (.I0(1'b0), .O(s_level_out_bus_d5[6])); LUT1 #( .INIT(2'h2)) i_161 (.I0(1'b0), .O(s_level_out_bus_d5[5])); LUT1 #( .INIT(2'h2)) i_162 (.I0(1'b0), .O(s_level_out_bus_d5[4])); LUT1 #( .INIT(2'h2)) i_163 (.I0(1'b0), .O(s_level_out_bus_d5[3])); LUT1 #( .INIT(2'h2)) i_164 (.I0(1'b0), .O(s_level_out_bus_d5[2])); LUT1 #( .INIT(2'h2)) i_165 (.I0(1'b0), .O(s_level_out_bus_d5[1])); LUT1 #( .INIT(2'h2)) i_166 (.I0(1'b0), .O(s_level_out_bus_d5[0])); LUT1 #( .INIT(2'h2)) i_167 (.I0(1'b0), .O(s_level_out_bus_d6[31])); LUT1 #( .INIT(2'h2)) i_168 (.I0(1'b0), .O(s_level_out_bus_d6[30])); LUT1 #( .INIT(2'h2)) i_169 (.I0(1'b0), .O(s_level_out_bus_d6[29])); LUT1 #( .INIT(2'h2)) i_17 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[21])); LUT1 #( .INIT(2'h2)) i_170 (.I0(1'b0), .O(s_level_out_bus_d6[28])); LUT1 #( .INIT(2'h2)) i_171 (.I0(1'b0), .O(s_level_out_bus_d6[27])); LUT1 #( .INIT(2'h2)) i_172 (.I0(1'b0), .O(s_level_out_bus_d6[26])); LUT1 #( .INIT(2'h2)) i_173 (.I0(1'b0), .O(s_level_out_bus_d6[25])); LUT1 #( .INIT(2'h2)) i_174 (.I0(1'b0), .O(s_level_out_bus_d6[24])); LUT1 #( .INIT(2'h2)) i_175 (.I0(1'b0), .O(s_level_out_bus_d6[23])); LUT1 #( .INIT(2'h2)) i_176 (.I0(1'b0), .O(s_level_out_bus_d6[22])); LUT1 #( .INIT(2'h2)) i_177 (.I0(1'b0), .O(s_level_out_bus_d6[21])); LUT1 #( .INIT(2'h2)) i_178 (.I0(1'b0), .O(s_level_out_bus_d6[20])); LUT1 #( .INIT(2'h2)) i_179 (.I0(1'b0), .O(s_level_out_bus_d6[19])); LUT1 #( .INIT(2'h2)) i_18 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[20])); LUT1 #( .INIT(2'h2)) i_180 (.I0(1'b0), .O(s_level_out_bus_d6[18])); LUT1 #( .INIT(2'h2)) i_181 (.I0(1'b0), .O(s_level_out_bus_d6[17])); LUT1 #( .INIT(2'h2)) i_182 (.I0(1'b0), .O(s_level_out_bus_d6[16])); LUT1 #( .INIT(2'h2)) i_183 (.I0(1'b0), .O(s_level_out_bus_d6[15])); LUT1 #( .INIT(2'h2)) i_184 (.I0(1'b0), .O(s_level_out_bus_d6[14])); LUT1 #( .INIT(2'h2)) i_185 (.I0(1'b0), .O(s_level_out_bus_d6[13])); LUT1 #( .INIT(2'h2)) i_186 (.I0(1'b0), .O(s_level_out_bus_d6[12])); LUT1 #( .INIT(2'h2)) i_187 (.I0(1'b0), .O(s_level_out_bus_d6[11])); LUT1 #( .INIT(2'h2)) i_188 (.I0(1'b0), .O(s_level_out_bus_d6[10])); LUT1 #( .INIT(2'h2)) i_189 (.I0(1'b0), .O(s_level_out_bus_d6[9])); LUT1 #( .INIT(2'h2)) i_19 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[19])); LUT1 #( .INIT(2'h2)) i_190 (.I0(1'b0), .O(s_level_out_bus_d6[8])); LUT1 #( .INIT(2'h2)) i_191 (.I0(1'b0), .O(s_level_out_bus_d6[7])); LUT1 #( .INIT(2'h2)) i_192 (.I0(1'b0), .O(s_level_out_bus_d6[6])); LUT1 #( .INIT(2'h2)) i_193 (.I0(1'b0), .O(s_level_out_bus_d6[5])); LUT1 #( .INIT(2'h2)) i_194 (.I0(1'b0), .O(s_level_out_bus_d6[4])); LUT1 #( .INIT(2'h2)) i_195 (.I0(1'b0), .O(s_level_out_bus_d6[3])); LUT1 #( .INIT(2'h2)) i_196 (.I0(1'b0), .O(s_level_out_bus_d6[2])); LUT1 #( .INIT(2'h2)) i_197 (.I0(1'b0), .O(s_level_out_bus_d6[1])); LUT1 #( .INIT(2'h2)) i_198 (.I0(1'b0), .O(s_level_out_bus_d6[0])); LUT1 #( .INIT(2'h2)) i_2 (.I0(1'b0), .O(s_out_d3)); LUT1 #( .INIT(2'h2)) i_20 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[18])); LUT1 #( .INIT(2'h2)) i_21 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[17])); LUT1 #( .INIT(2'h2)) i_22 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[16])); LUT1 #( .INIT(2'h2)) i_23 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[15])); LUT1 #( .INIT(2'h2)) i_24 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[14])); LUT1 #( .INIT(2'h2)) i_25 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[13])); LUT1 #( .INIT(2'h2)) i_26 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[12])); LUT1 #( .INIT(2'h2)) i_27 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[11])); LUT1 #( .INIT(2'h2)) i_28 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[10])); LUT1 #( .INIT(2'h2)) i_29 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[9])); LUT1 #( .INIT(2'h2)) i_3 (.I0(1'b0), .O(s_out_d4)); LUT1 #( .INIT(2'h2)) i_30 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[8])); LUT1 #( .INIT(2'h2)) i_31 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[7])); LUT1 #( .INIT(2'h2)) i_32 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[6])); LUT1 #( .INIT(2'h2)) i_33 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[5])); LUT1 #( .INIT(2'h2)) i_34 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[4])); LUT1 #( .INIT(2'h2)) i_35 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[3])); LUT1 #( .INIT(2'h2)) i_36 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[2])); LUT1 #( .INIT(2'h2)) i_37 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[1])); LUT1 #( .INIT(2'h2)) i_38 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[0])); LUT1 #( .INIT(2'h2)) i_39 (.I0(1'b0), .O(s_level_out_bus_d2[31])); LUT1 #( .INIT(2'h2)) i_4 (.I0(1'b0), .O(s_out_d5)); LUT1 #( .INIT(2'h2)) i_40 (.I0(1'b0), .O(s_level_out_bus_d2[30])); LUT1 #( .INIT(2'h2)) i_41 (.I0(1'b0), .O(s_level_out_bus_d2[29])); LUT1 #( .INIT(2'h2)) i_42 (.I0(1'b0), .O(s_level_out_bus_d2[28])); LUT1 #( .INIT(2'h2)) i_43 (.I0(1'b0), .O(s_level_out_bus_d2[27])); LUT1 #( .INIT(2'h2)) i_44 (.I0(1'b0), .O(s_level_out_bus_d2[26])); LUT1 #( .INIT(2'h2)) i_45 (.I0(1'b0), .O(s_level_out_bus_d2[25])); LUT1 #( .INIT(2'h2)) i_46 (.I0(1'b0), .O(s_level_out_bus_d2[24])); LUT1 #( .INIT(2'h2)) i_47 (.I0(1'b0), .O(s_level_out_bus_d2[23])); LUT1 #( .INIT(2'h2)) i_48 (.I0(1'b0), .O(s_level_out_bus_d2[22])); LUT1 #( .INIT(2'h2)) i_49 (.I0(1'b0), .O(s_level_out_bus_d2[21])); LUT1 #( .INIT(2'h2)) i_5 (.I0(1'b0), .O(s_out_d6)); LUT1 #( .INIT(2'h2)) i_50 (.I0(1'b0), .O(s_level_out_bus_d2[20])); LUT1 #( .INIT(2'h2)) i_51 (.I0(1'b0), .O(s_level_out_bus_d2[19])); LUT1 #( .INIT(2'h2)) i_52 (.I0(1'b0), .O(s_level_out_bus_d2[18])); LUT1 #( .INIT(2'h2)) i_53 (.I0(1'b0), .O(s_level_out_bus_d2[17])); LUT1 #( .INIT(2'h2)) i_54 (.I0(1'b0), .O(s_level_out_bus_d2[16])); LUT1 #( .INIT(2'h2)) i_55 (.I0(1'b0), .O(s_level_out_bus_d2[15])); LUT1 #( .INIT(2'h2)) i_56 (.I0(1'b0), .O(s_level_out_bus_d2[14])); LUT1 #( .INIT(2'h2)) i_57 (.I0(1'b0), .O(s_level_out_bus_d2[13])); LUT1 #( .INIT(2'h2)) i_58 (.I0(1'b0), .O(s_level_out_bus_d2[12])); LUT1 #( .INIT(2'h2)) i_59 (.I0(1'b0), .O(s_level_out_bus_d2[11])); LUT1 #( .INIT(2'h2)) i_6 (.I0(1'b0), .O(s_out_d7)); LUT1 #( .INIT(2'h2)) i_60 (.I0(1'b0), .O(s_level_out_bus_d2[10])); LUT1 #( .INIT(2'h2)) i_61 (.I0(1'b0), .O(s_level_out_bus_d2[9])); LUT1 #( .INIT(2'h2)) i_62 (.I0(1'b0), .O(s_level_out_bus_d2[8])); LUT1 #( .INIT(2'h2)) i_63 (.I0(1'b0), .O(s_level_out_bus_d2[7])); LUT1 #( .INIT(2'h2)) i_64 (.I0(1'b0), .O(s_level_out_bus_d2[6])); LUT1 #( .INIT(2'h2)) i_65 (.I0(1'b0), .O(s_level_out_bus_d2[5])); LUT1 #( .INIT(2'h2)) i_66 (.I0(1'b0), .O(s_level_out_bus_d2[4])); LUT1 #( .INIT(2'h2)) i_67 (.I0(1'b0), .O(s_level_out_bus_d2[3])); LUT1 #( .INIT(2'h2)) i_68 (.I0(1'b0), .O(s_level_out_bus_d2[2])); LUT1 #( .INIT(2'h2)) i_69 (.I0(1'b0), .O(s_level_out_bus_d2[1])); LUT1 #( .INIT(2'h2)) i_7 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[31])); LUT1 #( .INIT(2'h2)) i_70 (.I0(1'b0), .O(s_level_out_bus_d2[0])); LUT1 #( .INIT(2'h2)) i_71 (.I0(1'b0), .O(s_level_out_bus_d3[31])); LUT1 #( .INIT(2'h2)) i_72 (.I0(1'b0), .O(s_level_out_bus_d3[30])); LUT1 #( .INIT(2'h2)) i_73 (.I0(1'b0), .O(s_level_out_bus_d3[29])); LUT1 #( .INIT(2'h2)) i_74 (.I0(1'b0), .O(s_level_out_bus_d3[28])); LUT1 #( .INIT(2'h2)) i_75 (.I0(1'b0), .O(s_level_out_bus_d3[27])); LUT1 #( .INIT(2'h2)) i_76 (.I0(1'b0), .O(s_level_out_bus_d3[26])); LUT1 #( .INIT(2'h2)) i_77 (.I0(1'b0), .O(s_level_out_bus_d3[25])); LUT1 #( .INIT(2'h2)) i_78 (.I0(1'b0), .O(s_level_out_bus_d3[24])); LUT1 #( .INIT(2'h2)) i_79 (.I0(1'b0), .O(s_level_out_bus_d3[23])); LUT1 #( .INIT(2'h2)) i_8 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[30])); LUT1 #( .INIT(2'h2)) i_80 (.I0(1'b0), .O(s_level_out_bus_d3[22])); LUT1 #( .INIT(2'h2)) i_81 (.I0(1'b0), .O(s_level_out_bus_d3[21])); LUT1 #( .INIT(2'h2)) i_82 (.I0(1'b0), .O(s_level_out_bus_d3[20])); LUT1 #( .INIT(2'h2)) i_83 (.I0(1'b0), .O(s_level_out_bus_d3[19])); LUT1 #( .INIT(2'h2)) i_84 (.I0(1'b0), .O(s_level_out_bus_d3[18])); LUT1 #( .INIT(2'h2)) i_85 (.I0(1'b0), .O(s_level_out_bus_d3[17])); LUT1 #( .INIT(2'h2)) i_86 (.I0(1'b0), .O(s_level_out_bus_d3[16])); LUT1 #( .INIT(2'h2)) i_87 (.I0(1'b0), .O(s_level_out_bus_d3[15])); LUT1 #( .INIT(2'h2)) i_88 (.I0(1'b0), .O(s_level_out_bus_d3[14])); LUT1 #( .INIT(2'h2)) i_89 (.I0(1'b0), .O(s_level_out_bus_d3[13])); LUT1 #( .INIT(2'h2)) i_9 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[29])); LUT1 #( .INIT(2'h2)) i_90 (.I0(1'b0), .O(s_level_out_bus_d3[12])); LUT1 #( .INIT(2'h2)) i_91 (.I0(1'b0), .O(s_level_out_bus_d3[11])); LUT1 #( .INIT(2'h2)) i_92 (.I0(1'b0), .O(s_level_out_bus_d3[10])); LUT1 #( .INIT(2'h2)) i_93 (.I0(1'b0), .O(s_level_out_bus_d3[9])); LUT1 #( .INIT(2'h2)) i_94 (.I0(1'b0), .O(s_level_out_bus_d3[8])); LUT1 #( .INIT(2'h2)) i_95 (.I0(1'b0), .O(s_level_out_bus_d3[7])); LUT1 #( .INIT(2'h2)) i_96 (.I0(1'b0), .O(s_level_out_bus_d3[6])); LUT1 #( .INIT(2'h2)) i_97 (.I0(1'b0), .O(s_level_out_bus_d3[5])); LUT1 #( .INIT(2'h2)) i_98 (.I0(1'b0), .O(s_level_out_bus_d3[4])); LUT1 #( .INIT(2'h2)) i_99 (.I0(1'b0), .O(s_level_out_bus_d3[3])); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d1_aurora_64b66b_0_cdc_to_reg (.C(s_level_out_d5_reg_1), .CE(1'b1), .D(p_level_in_int), .Q(s_level_out_d1_aurora_64b66b_0_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d2_reg (.C(s_level_out_d5_reg_1), .CE(1'b1), .D(s_level_out_d1_aurora_64b66b_0_cdc_to), .Q(s_level_out_d2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d3_reg (.C(s_level_out_d5_reg_1), .CE(1'b1), .D(s_level_out_d2), .Q(s_level_out_d3), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d4_reg (.C(s_level_out_d5_reg_1), .CE(1'b1), .D(s_level_out_d3), .Q(s_level_out_d4), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d5_reg (.C(s_level_out_d5_reg_1), .CE(1'b1), .D(s_level_out_d4), .Q(s_level_out_d5), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d6_reg (.C(s_level_out_d5_reg_1), .CE(1'b1), .D(s_level_out_d5), .Q(s_level_out_d6), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_cdc_sync" *) module aurora_64b66b_0_aurora_64b66b_0_cdc_sync__parameterized0_7 (hard_err_rst_int_reg, E, in0, init_clk, hard_err_rst_int, Q, hard_err_rst_int0, SR, \hard_err_cntr_r_reg[0] , \hard_err_cntr_r_reg[0]_0 ); output hard_err_rst_int_reg; output [0:0]E; input in0; input init_clk; input hard_err_rst_int; input [2:0]Q; input hard_err_rst_int0; input [0:0]SR; input \hard_err_cntr_r_reg[0] ; input \hard_err_cntr_r_reg[0]_0 ; wire [0:0]E; wire [2:0]Q; wire [0:0]SR; wire \hard_err_cntr_r_reg[0] ; wire \hard_err_cntr_r_reg[0]_0 ; wire hard_err_rst_int; wire hard_err_rst_int0; wire hard_err_rst_int_i_2_n_0; wire hard_err_rst_int_reg; wire init_clk; wire p_level_in_int; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d3; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d4; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d5; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d6; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d3; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d4; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d5; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d6; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d3; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d4; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d5; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d6; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d7; assign p_level_in_int = in0; LUT6 #( .INIT(64'hAAFFFFFFFFFFFFFC)) \hard_err_cntr_r[7]_i_2 (.I0(\hard_err_cntr_r_reg[0] ), .I1(\hard_err_cntr_r_reg[0]_0 ), .I2(s_level_out_d5), .I3(Q[0]), .I4(Q[1]), .I5(Q[2]), .O(E)); LUT6 #( .INIT(64'h00000000FFFE0002)) hard_err_rst_int_i_1 (.I0(hard_err_rst_int), .I1(Q[0]), .I2(Q[1]), .I3(hard_err_rst_int_i_2_n_0), .I4(hard_err_rst_int0), .I5(SR), .O(hard_err_rst_int_reg)); LUT3 #( .INIT(8'hFE)) hard_err_rst_int_i_2 (.I0(s_level_out_d5), .I1(Q[2]), .I2(\hard_err_cntr_r_reg[0]_0 ), .O(hard_err_rst_int_i_2_n_0)); LUT1 #( .INIT(2'h2)) i_0 (.I0(1'b0), .O(s_out_d1_aurora_64b66b_0_cdc_to)); LUT1 #( .INIT(2'h2)) i_1 (.I0(1'b0), .O(s_out_d2)); LUT1 #( .INIT(2'h2)) i_10 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[28])); LUT1 #( .INIT(2'h2)) i_100 (.I0(1'b0), .O(s_level_out_bus_d3[2])); LUT1 #( .INIT(2'h2)) i_101 (.I0(1'b0), .O(s_level_out_bus_d3[1])); LUT1 #( .INIT(2'h2)) i_102 (.I0(1'b0), .O(s_level_out_bus_d3[0])); LUT1 #( .INIT(2'h2)) i_103 (.I0(1'b0), .O(s_level_out_bus_d4[31])); LUT1 #( .INIT(2'h2)) i_104 (.I0(1'b0), .O(s_level_out_bus_d4[30])); LUT1 #( .INIT(2'h2)) i_105 (.I0(1'b0), .O(s_level_out_bus_d4[29])); LUT1 #( .INIT(2'h2)) i_106 (.I0(1'b0), .O(s_level_out_bus_d4[28])); LUT1 #( .INIT(2'h2)) i_107 (.I0(1'b0), .O(s_level_out_bus_d4[27])); LUT1 #( .INIT(2'h2)) i_108 (.I0(1'b0), .O(s_level_out_bus_d4[26])); LUT1 #( .INIT(2'h2)) i_109 (.I0(1'b0), .O(s_level_out_bus_d4[25])); LUT1 #( .INIT(2'h2)) i_11 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[27])); LUT1 #( .INIT(2'h2)) i_110 (.I0(1'b0), .O(s_level_out_bus_d4[24])); LUT1 #( .INIT(2'h2)) i_111 (.I0(1'b0), .O(s_level_out_bus_d4[23])); LUT1 #( .INIT(2'h2)) i_112 (.I0(1'b0), .O(s_level_out_bus_d4[22])); LUT1 #( .INIT(2'h2)) i_113 (.I0(1'b0), .O(s_level_out_bus_d4[21])); LUT1 #( .INIT(2'h2)) i_114 (.I0(1'b0), .O(s_level_out_bus_d4[20])); LUT1 #( .INIT(2'h2)) i_115 (.I0(1'b0), .O(s_level_out_bus_d4[19])); LUT1 #( .INIT(2'h2)) i_116 (.I0(1'b0), .O(s_level_out_bus_d4[18])); LUT1 #( .INIT(2'h2)) i_117 (.I0(1'b0), .O(s_level_out_bus_d4[17])); LUT1 #( .INIT(2'h2)) i_118 (.I0(1'b0), .O(s_level_out_bus_d4[16])); LUT1 #( .INIT(2'h2)) i_119 (.I0(1'b0), .O(s_level_out_bus_d4[15])); LUT1 #( .INIT(2'h2)) i_12 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[26])); LUT1 #( .INIT(2'h2)) i_120 (.I0(1'b0), .O(s_level_out_bus_d4[14])); LUT1 #( .INIT(2'h2)) i_121 (.I0(1'b0), .O(s_level_out_bus_d4[13])); LUT1 #( .INIT(2'h2)) i_122 (.I0(1'b0), .O(s_level_out_bus_d4[12])); LUT1 #( .INIT(2'h2)) i_123 (.I0(1'b0), .O(s_level_out_bus_d4[11])); LUT1 #( .INIT(2'h2)) i_124 (.I0(1'b0), .O(s_level_out_bus_d4[10])); LUT1 #( .INIT(2'h2)) i_125 (.I0(1'b0), .O(s_level_out_bus_d4[9])); LUT1 #( .INIT(2'h2)) i_126 (.I0(1'b0), .O(s_level_out_bus_d4[8])); LUT1 #( .INIT(2'h2)) i_127 (.I0(1'b0), .O(s_level_out_bus_d4[7])); LUT1 #( .INIT(2'h2)) i_128 (.I0(1'b0), .O(s_level_out_bus_d4[6])); LUT1 #( .INIT(2'h2)) i_129 (.I0(1'b0), .O(s_level_out_bus_d4[5])); LUT1 #( .INIT(2'h2)) i_13 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[25])); LUT1 #( .INIT(2'h2)) i_130 (.I0(1'b0), .O(s_level_out_bus_d4[4])); LUT1 #( .INIT(2'h2)) i_131 (.I0(1'b0), .O(s_level_out_bus_d4[3])); LUT1 #( .INIT(2'h2)) i_132 (.I0(1'b0), .O(s_level_out_bus_d4[2])); LUT1 #( .INIT(2'h2)) i_133 (.I0(1'b0), .O(s_level_out_bus_d4[1])); LUT1 #( .INIT(2'h2)) i_134 (.I0(1'b0), .O(s_level_out_bus_d4[0])); LUT1 #( .INIT(2'h2)) i_135 (.I0(1'b0), .O(s_level_out_bus_d5[31])); LUT1 #( .INIT(2'h2)) i_136 (.I0(1'b0), .O(s_level_out_bus_d5[30])); LUT1 #( .INIT(2'h2)) i_137 (.I0(1'b0), .O(s_level_out_bus_d5[29])); LUT1 #( .INIT(2'h2)) i_138 (.I0(1'b0), .O(s_level_out_bus_d5[28])); LUT1 #( .INIT(2'h2)) i_139 (.I0(1'b0), .O(s_level_out_bus_d5[27])); LUT1 #( .INIT(2'h2)) i_14 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[24])); LUT1 #( .INIT(2'h2)) i_140 (.I0(1'b0), .O(s_level_out_bus_d5[26])); LUT1 #( .INIT(2'h2)) i_141 (.I0(1'b0), .O(s_level_out_bus_d5[25])); LUT1 #( .INIT(2'h2)) i_142 (.I0(1'b0), .O(s_level_out_bus_d5[24])); LUT1 #( .INIT(2'h2)) i_143 (.I0(1'b0), .O(s_level_out_bus_d5[23])); LUT1 #( .INIT(2'h2)) i_144 (.I0(1'b0), .O(s_level_out_bus_d5[22])); LUT1 #( .INIT(2'h2)) i_145 (.I0(1'b0), .O(s_level_out_bus_d5[21])); LUT1 #( .INIT(2'h2)) i_146 (.I0(1'b0), .O(s_level_out_bus_d5[20])); LUT1 #( .INIT(2'h2)) i_147 (.I0(1'b0), .O(s_level_out_bus_d5[19])); LUT1 #( .INIT(2'h2)) i_148 (.I0(1'b0), .O(s_level_out_bus_d5[18])); LUT1 #( .INIT(2'h2)) i_149 (.I0(1'b0), .O(s_level_out_bus_d5[17])); LUT1 #( .INIT(2'h2)) i_15 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[23])); LUT1 #( .INIT(2'h2)) i_150 (.I0(1'b0), .O(s_level_out_bus_d5[16])); LUT1 #( .INIT(2'h2)) i_151 (.I0(1'b0), .O(s_level_out_bus_d5[15])); LUT1 #( .INIT(2'h2)) i_152 (.I0(1'b0), .O(s_level_out_bus_d5[14])); LUT1 #( .INIT(2'h2)) i_153 (.I0(1'b0), .O(s_level_out_bus_d5[13])); LUT1 #( .INIT(2'h2)) i_154 (.I0(1'b0), .O(s_level_out_bus_d5[12])); LUT1 #( .INIT(2'h2)) i_155 (.I0(1'b0), .O(s_level_out_bus_d5[11])); LUT1 #( .INIT(2'h2)) i_156 (.I0(1'b0), .O(s_level_out_bus_d5[10])); LUT1 #( .INIT(2'h2)) i_157 (.I0(1'b0), .O(s_level_out_bus_d5[9])); LUT1 #( .INIT(2'h2)) i_158 (.I0(1'b0), .O(s_level_out_bus_d5[8])); LUT1 #( .INIT(2'h2)) i_159 (.I0(1'b0), .O(s_level_out_bus_d5[7])); LUT1 #( .INIT(2'h2)) i_16 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[22])); LUT1 #( .INIT(2'h2)) i_160 (.I0(1'b0), .O(s_level_out_bus_d5[6])); LUT1 #( .INIT(2'h2)) i_161 (.I0(1'b0), .O(s_level_out_bus_d5[5])); LUT1 #( .INIT(2'h2)) i_162 (.I0(1'b0), .O(s_level_out_bus_d5[4])); LUT1 #( .INIT(2'h2)) i_163 (.I0(1'b0), .O(s_level_out_bus_d5[3])); LUT1 #( .INIT(2'h2)) i_164 (.I0(1'b0), .O(s_level_out_bus_d5[2])); LUT1 #( .INIT(2'h2)) i_165 (.I0(1'b0), .O(s_level_out_bus_d5[1])); LUT1 #( .INIT(2'h2)) i_166 (.I0(1'b0), .O(s_level_out_bus_d5[0])); LUT1 #( .INIT(2'h2)) i_167 (.I0(1'b0), .O(s_level_out_bus_d6[31])); LUT1 #( .INIT(2'h2)) i_168 (.I0(1'b0), .O(s_level_out_bus_d6[30])); LUT1 #( .INIT(2'h2)) i_169 (.I0(1'b0), .O(s_level_out_bus_d6[29])); LUT1 #( .INIT(2'h2)) i_17 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[21])); LUT1 #( .INIT(2'h2)) i_170 (.I0(1'b0), .O(s_level_out_bus_d6[28])); LUT1 #( .INIT(2'h2)) i_171 (.I0(1'b0), .O(s_level_out_bus_d6[27])); LUT1 #( .INIT(2'h2)) i_172 (.I0(1'b0), .O(s_level_out_bus_d6[26])); LUT1 #( .INIT(2'h2)) i_173 (.I0(1'b0), .O(s_level_out_bus_d6[25])); LUT1 #( .INIT(2'h2)) i_174 (.I0(1'b0), .O(s_level_out_bus_d6[24])); LUT1 #( .INIT(2'h2)) i_175 (.I0(1'b0), .O(s_level_out_bus_d6[23])); LUT1 #( .INIT(2'h2)) i_176 (.I0(1'b0), .O(s_level_out_bus_d6[22])); LUT1 #( .INIT(2'h2)) i_177 (.I0(1'b0), .O(s_level_out_bus_d6[21])); LUT1 #( .INIT(2'h2)) i_178 (.I0(1'b0), .O(s_level_out_bus_d6[20])); LUT1 #( .INIT(2'h2)) i_179 (.I0(1'b0), .O(s_level_out_bus_d6[19])); LUT1 #( .INIT(2'h2)) i_18 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[20])); LUT1 #( .INIT(2'h2)) i_180 (.I0(1'b0), .O(s_level_out_bus_d6[18])); LUT1 #( .INIT(2'h2)) i_181 (.I0(1'b0), .O(s_level_out_bus_d6[17])); LUT1 #( .INIT(2'h2)) i_182 (.I0(1'b0), .O(s_level_out_bus_d6[16])); LUT1 #( .INIT(2'h2)) i_183 (.I0(1'b0), .O(s_level_out_bus_d6[15])); LUT1 #( .INIT(2'h2)) i_184 (.I0(1'b0), .O(s_level_out_bus_d6[14])); LUT1 #( .INIT(2'h2)) i_185 (.I0(1'b0), .O(s_level_out_bus_d6[13])); LUT1 #( .INIT(2'h2)) i_186 (.I0(1'b0), .O(s_level_out_bus_d6[12])); LUT1 #( .INIT(2'h2)) i_187 (.I0(1'b0), .O(s_level_out_bus_d6[11])); LUT1 #( .INIT(2'h2)) i_188 (.I0(1'b0), .O(s_level_out_bus_d6[10])); LUT1 #( .INIT(2'h2)) i_189 (.I0(1'b0), .O(s_level_out_bus_d6[9])); LUT1 #( .INIT(2'h2)) i_19 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[19])); LUT1 #( .INIT(2'h2)) i_190 (.I0(1'b0), .O(s_level_out_bus_d6[8])); LUT1 #( .INIT(2'h2)) i_191 (.I0(1'b0), .O(s_level_out_bus_d6[7])); LUT1 #( .INIT(2'h2)) i_192 (.I0(1'b0), .O(s_level_out_bus_d6[6])); LUT1 #( .INIT(2'h2)) i_193 (.I0(1'b0), .O(s_level_out_bus_d6[5])); LUT1 #( .INIT(2'h2)) i_194 (.I0(1'b0), .O(s_level_out_bus_d6[4])); LUT1 #( .INIT(2'h2)) i_195 (.I0(1'b0), .O(s_level_out_bus_d6[3])); LUT1 #( .INIT(2'h2)) i_196 (.I0(1'b0), .O(s_level_out_bus_d6[2])); LUT1 #( .INIT(2'h2)) i_197 (.I0(1'b0), .O(s_level_out_bus_d6[1])); LUT1 #( .INIT(2'h2)) i_198 (.I0(1'b0), .O(s_level_out_bus_d6[0])); LUT1 #( .INIT(2'h2)) i_2 (.I0(1'b0), .O(s_out_d3)); LUT1 #( .INIT(2'h2)) i_20 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[18])); LUT1 #( .INIT(2'h2)) i_21 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[17])); LUT1 #( .INIT(2'h2)) i_22 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[16])); LUT1 #( .INIT(2'h2)) i_23 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[15])); LUT1 #( .INIT(2'h2)) i_24 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[14])); LUT1 #( .INIT(2'h2)) i_25 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[13])); LUT1 #( .INIT(2'h2)) i_26 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[12])); LUT1 #( .INIT(2'h2)) i_27 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[11])); LUT1 #( .INIT(2'h2)) i_28 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[10])); LUT1 #( .INIT(2'h2)) i_29 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[9])); LUT1 #( .INIT(2'h2)) i_3 (.I0(1'b0), .O(s_out_d4)); LUT1 #( .INIT(2'h2)) i_30 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[8])); LUT1 #( .INIT(2'h2)) i_31 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[7])); LUT1 #( .INIT(2'h2)) i_32 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[6])); LUT1 #( .INIT(2'h2)) i_33 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[5])); LUT1 #( .INIT(2'h2)) i_34 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[4])); LUT1 #( .INIT(2'h2)) i_35 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[3])); LUT1 #( .INIT(2'h2)) i_36 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[2])); LUT1 #( .INIT(2'h2)) i_37 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[1])); LUT1 #( .INIT(2'h2)) i_38 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[0])); LUT1 #( .INIT(2'h2)) i_39 (.I0(1'b0), .O(s_level_out_bus_d2[31])); LUT1 #( .INIT(2'h2)) i_4 (.I0(1'b0), .O(s_out_d5)); LUT1 #( .INIT(2'h2)) i_40 (.I0(1'b0), .O(s_level_out_bus_d2[30])); LUT1 #( .INIT(2'h2)) i_41 (.I0(1'b0), .O(s_level_out_bus_d2[29])); LUT1 #( .INIT(2'h2)) i_42 (.I0(1'b0), .O(s_level_out_bus_d2[28])); LUT1 #( .INIT(2'h2)) i_43 (.I0(1'b0), .O(s_level_out_bus_d2[27])); LUT1 #( .INIT(2'h2)) i_44 (.I0(1'b0), .O(s_level_out_bus_d2[26])); LUT1 #( .INIT(2'h2)) i_45 (.I0(1'b0), .O(s_level_out_bus_d2[25])); LUT1 #( .INIT(2'h2)) i_46 (.I0(1'b0), .O(s_level_out_bus_d2[24])); LUT1 #( .INIT(2'h2)) i_47 (.I0(1'b0), .O(s_level_out_bus_d2[23])); LUT1 #( .INIT(2'h2)) i_48 (.I0(1'b0), .O(s_level_out_bus_d2[22])); LUT1 #( .INIT(2'h2)) i_49 (.I0(1'b0), .O(s_level_out_bus_d2[21])); LUT1 #( .INIT(2'h2)) i_5 (.I0(1'b0), .O(s_out_d6)); LUT1 #( .INIT(2'h2)) i_50 (.I0(1'b0), .O(s_level_out_bus_d2[20])); LUT1 #( .INIT(2'h2)) i_51 (.I0(1'b0), .O(s_level_out_bus_d2[19])); LUT1 #( .INIT(2'h2)) i_52 (.I0(1'b0), .O(s_level_out_bus_d2[18])); LUT1 #( .INIT(2'h2)) i_53 (.I0(1'b0), .O(s_level_out_bus_d2[17])); LUT1 #( .INIT(2'h2)) i_54 (.I0(1'b0), .O(s_level_out_bus_d2[16])); LUT1 #( .INIT(2'h2)) i_55 (.I0(1'b0), .O(s_level_out_bus_d2[15])); LUT1 #( .INIT(2'h2)) i_56 (.I0(1'b0), .O(s_level_out_bus_d2[14])); LUT1 #( .INIT(2'h2)) i_57 (.I0(1'b0), .O(s_level_out_bus_d2[13])); LUT1 #( .INIT(2'h2)) i_58 (.I0(1'b0), .O(s_level_out_bus_d2[12])); LUT1 #( .INIT(2'h2)) i_59 (.I0(1'b0), .O(s_level_out_bus_d2[11])); LUT1 #( .INIT(2'h2)) i_6 (.I0(1'b0), .O(s_out_d7)); LUT1 #( .INIT(2'h2)) i_60 (.I0(1'b0), .O(s_level_out_bus_d2[10])); LUT1 #( .INIT(2'h2)) i_61 (.I0(1'b0), .O(s_level_out_bus_d2[9])); LUT1 #( .INIT(2'h2)) i_62 (.I0(1'b0), .O(s_level_out_bus_d2[8])); LUT1 #( .INIT(2'h2)) i_63 (.I0(1'b0), .O(s_level_out_bus_d2[7])); LUT1 #( .INIT(2'h2)) i_64 (.I0(1'b0), .O(s_level_out_bus_d2[6])); LUT1 #( .INIT(2'h2)) i_65 (.I0(1'b0), .O(s_level_out_bus_d2[5])); LUT1 #( .INIT(2'h2)) i_66 (.I0(1'b0), .O(s_level_out_bus_d2[4])); LUT1 #( .INIT(2'h2)) i_67 (.I0(1'b0), .O(s_level_out_bus_d2[3])); LUT1 #( .INIT(2'h2)) i_68 (.I0(1'b0), .O(s_level_out_bus_d2[2])); LUT1 #( .INIT(2'h2)) i_69 (.I0(1'b0), .O(s_level_out_bus_d2[1])); LUT1 #( .INIT(2'h2)) i_7 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[31])); LUT1 #( .INIT(2'h2)) i_70 (.I0(1'b0), .O(s_level_out_bus_d2[0])); LUT1 #( .INIT(2'h2)) i_71 (.I0(1'b0), .O(s_level_out_bus_d3[31])); LUT1 #( .INIT(2'h2)) i_72 (.I0(1'b0), .O(s_level_out_bus_d3[30])); LUT1 #( .INIT(2'h2)) i_73 (.I0(1'b0), .O(s_level_out_bus_d3[29])); LUT1 #( .INIT(2'h2)) i_74 (.I0(1'b0), .O(s_level_out_bus_d3[28])); LUT1 #( .INIT(2'h2)) i_75 (.I0(1'b0), .O(s_level_out_bus_d3[27])); LUT1 #( .INIT(2'h2)) i_76 (.I0(1'b0), .O(s_level_out_bus_d3[26])); LUT1 #( .INIT(2'h2)) i_77 (.I0(1'b0), .O(s_level_out_bus_d3[25])); LUT1 #( .INIT(2'h2)) i_78 (.I0(1'b0), .O(s_level_out_bus_d3[24])); LUT1 #( .INIT(2'h2)) i_79 (.I0(1'b0), .O(s_level_out_bus_d3[23])); LUT1 #( .INIT(2'h2)) i_8 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[30])); LUT1 #( .INIT(2'h2)) i_80 (.I0(1'b0), .O(s_level_out_bus_d3[22])); LUT1 #( .INIT(2'h2)) i_81 (.I0(1'b0), .O(s_level_out_bus_d3[21])); LUT1 #( .INIT(2'h2)) i_82 (.I0(1'b0), .O(s_level_out_bus_d3[20])); LUT1 #( .INIT(2'h2)) i_83 (.I0(1'b0), .O(s_level_out_bus_d3[19])); LUT1 #( .INIT(2'h2)) i_84 (.I0(1'b0), .O(s_level_out_bus_d3[18])); LUT1 #( .INIT(2'h2)) i_85 (.I0(1'b0), .O(s_level_out_bus_d3[17])); LUT1 #( .INIT(2'h2)) i_86 (.I0(1'b0), .O(s_level_out_bus_d3[16])); LUT1 #( .INIT(2'h2)) i_87 (.I0(1'b0), .O(s_level_out_bus_d3[15])); LUT1 #( .INIT(2'h2)) i_88 (.I0(1'b0), .O(s_level_out_bus_d3[14])); LUT1 #( .INIT(2'h2)) i_89 (.I0(1'b0), .O(s_level_out_bus_d3[13])); LUT1 #( .INIT(2'h2)) i_9 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[29])); LUT1 #( .INIT(2'h2)) i_90 (.I0(1'b0), .O(s_level_out_bus_d3[12])); LUT1 #( .INIT(2'h2)) i_91 (.I0(1'b0), .O(s_level_out_bus_d3[11])); LUT1 #( .INIT(2'h2)) i_92 (.I0(1'b0), .O(s_level_out_bus_d3[10])); LUT1 #( .INIT(2'h2)) i_93 (.I0(1'b0), .O(s_level_out_bus_d3[9])); LUT1 #( .INIT(2'h2)) i_94 (.I0(1'b0), .O(s_level_out_bus_d3[8])); LUT1 #( .INIT(2'h2)) i_95 (.I0(1'b0), .O(s_level_out_bus_d3[7])); LUT1 #( .INIT(2'h2)) i_96 (.I0(1'b0), .O(s_level_out_bus_d3[6])); LUT1 #( .INIT(2'h2)) i_97 (.I0(1'b0), .O(s_level_out_bus_d3[5])); LUT1 #( .INIT(2'h2)) i_98 (.I0(1'b0), .O(s_level_out_bus_d3[4])); LUT1 #( .INIT(2'h2)) i_99 (.I0(1'b0), .O(s_level_out_bus_d3[3])); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d1_aurora_64b66b_0_cdc_to_reg (.C(init_clk), .CE(1'b1), .D(p_level_in_int), .Q(s_level_out_d1_aurora_64b66b_0_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d2_reg (.C(init_clk), .CE(1'b1), .D(s_level_out_d1_aurora_64b66b_0_cdc_to), .Q(s_level_out_d2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d3_reg (.C(init_clk), .CE(1'b1), .D(s_level_out_d2), .Q(s_level_out_d3), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d4_reg (.C(init_clk), .CE(1'b1), .D(s_level_out_d3), .Q(s_level_out_d4), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d5_reg (.C(init_clk), .CE(1'b1), .D(s_level_out_d4), .Q(s_level_out_d5), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d6_reg (.C(init_clk), .CE(1'b1), .D(s_level_out_d5), .Q(s_level_out_d6), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_cdc_sync" *) module aurora_64b66b_0_aurora_64b66b_0_cdc_sync__parameterized0_8 (rx_fsm_resetdone_ii, out, init_clk); output rx_fsm_resetdone_ii; input out; input init_clk; wire init_clk; wire p_level_in_int; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d3; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d4; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d5; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d6; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d3; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d4; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d5; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d6; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d3; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d4; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d5; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d6; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d7; assign p_level_in_int = out; assign rx_fsm_resetdone_ii = s_level_out_d5; LUT1 #( .INIT(2'h2)) i_0 (.I0(1'b0), .O(s_out_d1_aurora_64b66b_0_cdc_to)); LUT1 #( .INIT(2'h2)) i_1 (.I0(1'b0), .O(s_out_d2)); LUT1 #( .INIT(2'h2)) i_10 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[28])); LUT1 #( .INIT(2'h2)) i_100 (.I0(1'b0), .O(s_level_out_bus_d3[2])); LUT1 #( .INIT(2'h2)) i_101 (.I0(1'b0), .O(s_level_out_bus_d3[1])); LUT1 #( .INIT(2'h2)) i_102 (.I0(1'b0), .O(s_level_out_bus_d3[0])); LUT1 #( .INIT(2'h2)) i_103 (.I0(1'b0), .O(s_level_out_bus_d4[31])); LUT1 #( .INIT(2'h2)) i_104 (.I0(1'b0), .O(s_level_out_bus_d4[30])); LUT1 #( .INIT(2'h2)) i_105 (.I0(1'b0), .O(s_level_out_bus_d4[29])); LUT1 #( .INIT(2'h2)) i_106 (.I0(1'b0), .O(s_level_out_bus_d4[28])); LUT1 #( .INIT(2'h2)) i_107 (.I0(1'b0), .O(s_level_out_bus_d4[27])); LUT1 #( .INIT(2'h2)) i_108 (.I0(1'b0), .O(s_level_out_bus_d4[26])); LUT1 #( .INIT(2'h2)) i_109 (.I0(1'b0), .O(s_level_out_bus_d4[25])); LUT1 #( .INIT(2'h2)) i_11 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[27])); LUT1 #( .INIT(2'h2)) i_110 (.I0(1'b0), .O(s_level_out_bus_d4[24])); LUT1 #( .INIT(2'h2)) i_111 (.I0(1'b0), .O(s_level_out_bus_d4[23])); LUT1 #( .INIT(2'h2)) i_112 (.I0(1'b0), .O(s_level_out_bus_d4[22])); LUT1 #( .INIT(2'h2)) i_113 (.I0(1'b0), .O(s_level_out_bus_d4[21])); LUT1 #( .INIT(2'h2)) i_114 (.I0(1'b0), .O(s_level_out_bus_d4[20])); LUT1 #( .INIT(2'h2)) i_115 (.I0(1'b0), .O(s_level_out_bus_d4[19])); LUT1 #( .INIT(2'h2)) i_116 (.I0(1'b0), .O(s_level_out_bus_d4[18])); LUT1 #( .INIT(2'h2)) i_117 (.I0(1'b0), .O(s_level_out_bus_d4[17])); LUT1 #( .INIT(2'h2)) i_118 (.I0(1'b0), .O(s_level_out_bus_d4[16])); LUT1 #( .INIT(2'h2)) i_119 (.I0(1'b0), .O(s_level_out_bus_d4[15])); LUT1 #( .INIT(2'h2)) i_12 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[26])); LUT1 #( .INIT(2'h2)) i_120 (.I0(1'b0), .O(s_level_out_bus_d4[14])); LUT1 #( .INIT(2'h2)) i_121 (.I0(1'b0), .O(s_level_out_bus_d4[13])); LUT1 #( .INIT(2'h2)) i_122 (.I0(1'b0), .O(s_level_out_bus_d4[12])); LUT1 #( .INIT(2'h2)) i_123 (.I0(1'b0), .O(s_level_out_bus_d4[11])); LUT1 #( .INIT(2'h2)) i_124 (.I0(1'b0), .O(s_level_out_bus_d4[10])); LUT1 #( .INIT(2'h2)) i_125 (.I0(1'b0), .O(s_level_out_bus_d4[9])); LUT1 #( .INIT(2'h2)) i_126 (.I0(1'b0), .O(s_level_out_bus_d4[8])); LUT1 #( .INIT(2'h2)) i_127 (.I0(1'b0), .O(s_level_out_bus_d4[7])); LUT1 #( .INIT(2'h2)) i_128 (.I0(1'b0), .O(s_level_out_bus_d4[6])); LUT1 #( .INIT(2'h2)) i_129 (.I0(1'b0), .O(s_level_out_bus_d4[5])); LUT1 #( .INIT(2'h2)) i_13 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[25])); LUT1 #( .INIT(2'h2)) i_130 (.I0(1'b0), .O(s_level_out_bus_d4[4])); LUT1 #( .INIT(2'h2)) i_131 (.I0(1'b0), .O(s_level_out_bus_d4[3])); LUT1 #( .INIT(2'h2)) i_132 (.I0(1'b0), .O(s_level_out_bus_d4[2])); LUT1 #( .INIT(2'h2)) i_133 (.I0(1'b0), .O(s_level_out_bus_d4[1])); LUT1 #( .INIT(2'h2)) i_134 (.I0(1'b0), .O(s_level_out_bus_d4[0])); LUT1 #( .INIT(2'h2)) i_135 (.I0(1'b0), .O(s_level_out_bus_d5[31])); LUT1 #( .INIT(2'h2)) i_136 (.I0(1'b0), .O(s_level_out_bus_d5[30])); LUT1 #( .INIT(2'h2)) i_137 (.I0(1'b0), .O(s_level_out_bus_d5[29])); LUT1 #( .INIT(2'h2)) i_138 (.I0(1'b0), .O(s_level_out_bus_d5[28])); LUT1 #( .INIT(2'h2)) i_139 (.I0(1'b0), .O(s_level_out_bus_d5[27])); LUT1 #( .INIT(2'h2)) i_14 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[24])); LUT1 #( .INIT(2'h2)) i_140 (.I0(1'b0), .O(s_level_out_bus_d5[26])); LUT1 #( .INIT(2'h2)) i_141 (.I0(1'b0), .O(s_level_out_bus_d5[25])); LUT1 #( .INIT(2'h2)) i_142 (.I0(1'b0), .O(s_level_out_bus_d5[24])); LUT1 #( .INIT(2'h2)) i_143 (.I0(1'b0), .O(s_level_out_bus_d5[23])); LUT1 #( .INIT(2'h2)) i_144 (.I0(1'b0), .O(s_level_out_bus_d5[22])); LUT1 #( .INIT(2'h2)) i_145 (.I0(1'b0), .O(s_level_out_bus_d5[21])); LUT1 #( .INIT(2'h2)) i_146 (.I0(1'b0), .O(s_level_out_bus_d5[20])); LUT1 #( .INIT(2'h2)) i_147 (.I0(1'b0), .O(s_level_out_bus_d5[19])); LUT1 #( .INIT(2'h2)) i_148 (.I0(1'b0), .O(s_level_out_bus_d5[18])); LUT1 #( .INIT(2'h2)) i_149 (.I0(1'b0), .O(s_level_out_bus_d5[17])); LUT1 #( .INIT(2'h2)) i_15 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[23])); LUT1 #( .INIT(2'h2)) i_150 (.I0(1'b0), .O(s_level_out_bus_d5[16])); LUT1 #( .INIT(2'h2)) i_151 (.I0(1'b0), .O(s_level_out_bus_d5[15])); LUT1 #( .INIT(2'h2)) i_152 (.I0(1'b0), .O(s_level_out_bus_d5[14])); LUT1 #( .INIT(2'h2)) i_153 (.I0(1'b0), .O(s_level_out_bus_d5[13])); LUT1 #( .INIT(2'h2)) i_154 (.I0(1'b0), .O(s_level_out_bus_d5[12])); LUT1 #( .INIT(2'h2)) i_155 (.I0(1'b0), .O(s_level_out_bus_d5[11])); LUT1 #( .INIT(2'h2)) i_156 (.I0(1'b0), .O(s_level_out_bus_d5[10])); LUT1 #( .INIT(2'h2)) i_157 (.I0(1'b0), .O(s_level_out_bus_d5[9])); LUT1 #( .INIT(2'h2)) i_158 (.I0(1'b0), .O(s_level_out_bus_d5[8])); LUT1 #( .INIT(2'h2)) i_159 (.I0(1'b0), .O(s_level_out_bus_d5[7])); LUT1 #( .INIT(2'h2)) i_16 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[22])); LUT1 #( .INIT(2'h2)) i_160 (.I0(1'b0), .O(s_level_out_bus_d5[6])); LUT1 #( .INIT(2'h2)) i_161 (.I0(1'b0), .O(s_level_out_bus_d5[5])); LUT1 #( .INIT(2'h2)) i_162 (.I0(1'b0), .O(s_level_out_bus_d5[4])); LUT1 #( .INIT(2'h2)) i_163 (.I0(1'b0), .O(s_level_out_bus_d5[3])); LUT1 #( .INIT(2'h2)) i_164 (.I0(1'b0), .O(s_level_out_bus_d5[2])); LUT1 #( .INIT(2'h2)) i_165 (.I0(1'b0), .O(s_level_out_bus_d5[1])); LUT1 #( .INIT(2'h2)) i_166 (.I0(1'b0), .O(s_level_out_bus_d5[0])); LUT1 #( .INIT(2'h2)) i_167 (.I0(1'b0), .O(s_level_out_bus_d6[31])); LUT1 #( .INIT(2'h2)) i_168 (.I0(1'b0), .O(s_level_out_bus_d6[30])); LUT1 #( .INIT(2'h2)) i_169 (.I0(1'b0), .O(s_level_out_bus_d6[29])); LUT1 #( .INIT(2'h2)) i_17 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[21])); LUT1 #( .INIT(2'h2)) i_170 (.I0(1'b0), .O(s_level_out_bus_d6[28])); LUT1 #( .INIT(2'h2)) i_171 (.I0(1'b0), .O(s_level_out_bus_d6[27])); LUT1 #( .INIT(2'h2)) i_172 (.I0(1'b0), .O(s_level_out_bus_d6[26])); LUT1 #( .INIT(2'h2)) i_173 (.I0(1'b0), .O(s_level_out_bus_d6[25])); LUT1 #( .INIT(2'h2)) i_174 (.I0(1'b0), .O(s_level_out_bus_d6[24])); LUT1 #( .INIT(2'h2)) i_175 (.I0(1'b0), .O(s_level_out_bus_d6[23])); LUT1 #( .INIT(2'h2)) i_176 (.I0(1'b0), .O(s_level_out_bus_d6[22])); LUT1 #( .INIT(2'h2)) i_177 (.I0(1'b0), .O(s_level_out_bus_d6[21])); LUT1 #( .INIT(2'h2)) i_178 (.I0(1'b0), .O(s_level_out_bus_d6[20])); LUT1 #( .INIT(2'h2)) i_179 (.I0(1'b0), .O(s_level_out_bus_d6[19])); LUT1 #( .INIT(2'h2)) i_18 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[20])); LUT1 #( .INIT(2'h2)) i_180 (.I0(1'b0), .O(s_level_out_bus_d6[18])); LUT1 #( .INIT(2'h2)) i_181 (.I0(1'b0), .O(s_level_out_bus_d6[17])); LUT1 #( .INIT(2'h2)) i_182 (.I0(1'b0), .O(s_level_out_bus_d6[16])); LUT1 #( .INIT(2'h2)) i_183 (.I0(1'b0), .O(s_level_out_bus_d6[15])); LUT1 #( .INIT(2'h2)) i_184 (.I0(1'b0), .O(s_level_out_bus_d6[14])); LUT1 #( .INIT(2'h2)) i_185 (.I0(1'b0), .O(s_level_out_bus_d6[13])); LUT1 #( .INIT(2'h2)) i_186 (.I0(1'b0), .O(s_level_out_bus_d6[12])); LUT1 #( .INIT(2'h2)) i_187 (.I0(1'b0), .O(s_level_out_bus_d6[11])); LUT1 #( .INIT(2'h2)) i_188 (.I0(1'b0), .O(s_level_out_bus_d6[10])); LUT1 #( .INIT(2'h2)) i_189 (.I0(1'b0), .O(s_level_out_bus_d6[9])); LUT1 #( .INIT(2'h2)) i_19 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[19])); LUT1 #( .INIT(2'h2)) i_190 (.I0(1'b0), .O(s_level_out_bus_d6[8])); LUT1 #( .INIT(2'h2)) i_191 (.I0(1'b0), .O(s_level_out_bus_d6[7])); LUT1 #( .INIT(2'h2)) i_192 (.I0(1'b0), .O(s_level_out_bus_d6[6])); LUT1 #( .INIT(2'h2)) i_193 (.I0(1'b0), .O(s_level_out_bus_d6[5])); LUT1 #( .INIT(2'h2)) i_194 (.I0(1'b0), .O(s_level_out_bus_d6[4])); LUT1 #( .INIT(2'h2)) i_195 (.I0(1'b0), .O(s_level_out_bus_d6[3])); LUT1 #( .INIT(2'h2)) i_196 (.I0(1'b0), .O(s_level_out_bus_d6[2])); LUT1 #( .INIT(2'h2)) i_197 (.I0(1'b0), .O(s_level_out_bus_d6[1])); LUT1 #( .INIT(2'h2)) i_198 (.I0(1'b0), .O(s_level_out_bus_d6[0])); LUT1 #( .INIT(2'h2)) i_2 (.I0(1'b0), .O(s_out_d3)); LUT1 #( .INIT(2'h2)) i_20 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[18])); LUT1 #( .INIT(2'h2)) i_21 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[17])); LUT1 #( .INIT(2'h2)) i_22 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[16])); LUT1 #( .INIT(2'h2)) i_23 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[15])); LUT1 #( .INIT(2'h2)) i_24 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[14])); LUT1 #( .INIT(2'h2)) i_25 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[13])); LUT1 #( .INIT(2'h2)) i_26 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[12])); LUT1 #( .INIT(2'h2)) i_27 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[11])); LUT1 #( .INIT(2'h2)) i_28 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[10])); LUT1 #( .INIT(2'h2)) i_29 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[9])); LUT1 #( .INIT(2'h2)) i_3 (.I0(1'b0), .O(s_out_d4)); LUT1 #( .INIT(2'h2)) i_30 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[8])); LUT1 #( .INIT(2'h2)) i_31 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[7])); LUT1 #( .INIT(2'h2)) i_32 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[6])); LUT1 #( .INIT(2'h2)) i_33 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[5])); LUT1 #( .INIT(2'h2)) i_34 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[4])); LUT1 #( .INIT(2'h2)) i_35 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[3])); LUT1 #( .INIT(2'h2)) i_36 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[2])); LUT1 #( .INIT(2'h2)) i_37 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[1])); LUT1 #( .INIT(2'h2)) i_38 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[0])); LUT1 #( .INIT(2'h2)) i_39 (.I0(1'b0), .O(s_level_out_bus_d2[31])); LUT1 #( .INIT(2'h2)) i_4 (.I0(1'b0), .O(s_out_d5)); LUT1 #( .INIT(2'h2)) i_40 (.I0(1'b0), .O(s_level_out_bus_d2[30])); LUT1 #( .INIT(2'h2)) i_41 (.I0(1'b0), .O(s_level_out_bus_d2[29])); LUT1 #( .INIT(2'h2)) i_42 (.I0(1'b0), .O(s_level_out_bus_d2[28])); LUT1 #( .INIT(2'h2)) i_43 (.I0(1'b0), .O(s_level_out_bus_d2[27])); LUT1 #( .INIT(2'h2)) i_44 (.I0(1'b0), .O(s_level_out_bus_d2[26])); LUT1 #( .INIT(2'h2)) i_45 (.I0(1'b0), .O(s_level_out_bus_d2[25])); LUT1 #( .INIT(2'h2)) i_46 (.I0(1'b0), .O(s_level_out_bus_d2[24])); LUT1 #( .INIT(2'h2)) i_47 (.I0(1'b0), .O(s_level_out_bus_d2[23])); LUT1 #( .INIT(2'h2)) i_48 (.I0(1'b0), .O(s_level_out_bus_d2[22])); LUT1 #( .INIT(2'h2)) i_49 (.I0(1'b0), .O(s_level_out_bus_d2[21])); LUT1 #( .INIT(2'h2)) i_5 (.I0(1'b0), .O(s_out_d6)); LUT1 #( .INIT(2'h2)) i_50 (.I0(1'b0), .O(s_level_out_bus_d2[20])); LUT1 #( .INIT(2'h2)) i_51 (.I0(1'b0), .O(s_level_out_bus_d2[19])); LUT1 #( .INIT(2'h2)) i_52 (.I0(1'b0), .O(s_level_out_bus_d2[18])); LUT1 #( .INIT(2'h2)) i_53 (.I0(1'b0), .O(s_level_out_bus_d2[17])); LUT1 #( .INIT(2'h2)) i_54 (.I0(1'b0), .O(s_level_out_bus_d2[16])); LUT1 #( .INIT(2'h2)) i_55 (.I0(1'b0), .O(s_level_out_bus_d2[15])); LUT1 #( .INIT(2'h2)) i_56 (.I0(1'b0), .O(s_level_out_bus_d2[14])); LUT1 #( .INIT(2'h2)) i_57 (.I0(1'b0), .O(s_level_out_bus_d2[13])); LUT1 #( .INIT(2'h2)) i_58 (.I0(1'b0), .O(s_level_out_bus_d2[12])); LUT1 #( .INIT(2'h2)) i_59 (.I0(1'b0), .O(s_level_out_bus_d2[11])); LUT1 #( .INIT(2'h2)) i_6 (.I0(1'b0), .O(s_out_d7)); LUT1 #( .INIT(2'h2)) i_60 (.I0(1'b0), .O(s_level_out_bus_d2[10])); LUT1 #( .INIT(2'h2)) i_61 (.I0(1'b0), .O(s_level_out_bus_d2[9])); LUT1 #( .INIT(2'h2)) i_62 (.I0(1'b0), .O(s_level_out_bus_d2[8])); LUT1 #( .INIT(2'h2)) i_63 (.I0(1'b0), .O(s_level_out_bus_d2[7])); LUT1 #( .INIT(2'h2)) i_64 (.I0(1'b0), .O(s_level_out_bus_d2[6])); LUT1 #( .INIT(2'h2)) i_65 (.I0(1'b0), .O(s_level_out_bus_d2[5])); LUT1 #( .INIT(2'h2)) i_66 (.I0(1'b0), .O(s_level_out_bus_d2[4])); LUT1 #( .INIT(2'h2)) i_67 (.I0(1'b0), .O(s_level_out_bus_d2[3])); LUT1 #( .INIT(2'h2)) i_68 (.I0(1'b0), .O(s_level_out_bus_d2[2])); LUT1 #( .INIT(2'h2)) i_69 (.I0(1'b0), .O(s_level_out_bus_d2[1])); LUT1 #( .INIT(2'h2)) i_7 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[31])); LUT1 #( .INIT(2'h2)) i_70 (.I0(1'b0), .O(s_level_out_bus_d2[0])); LUT1 #( .INIT(2'h2)) i_71 (.I0(1'b0), .O(s_level_out_bus_d3[31])); LUT1 #( .INIT(2'h2)) i_72 (.I0(1'b0), .O(s_level_out_bus_d3[30])); LUT1 #( .INIT(2'h2)) i_73 (.I0(1'b0), .O(s_level_out_bus_d3[29])); LUT1 #( .INIT(2'h2)) i_74 (.I0(1'b0), .O(s_level_out_bus_d3[28])); LUT1 #( .INIT(2'h2)) i_75 (.I0(1'b0), .O(s_level_out_bus_d3[27])); LUT1 #( .INIT(2'h2)) i_76 (.I0(1'b0), .O(s_level_out_bus_d3[26])); LUT1 #( .INIT(2'h2)) i_77 (.I0(1'b0), .O(s_level_out_bus_d3[25])); LUT1 #( .INIT(2'h2)) i_78 (.I0(1'b0), .O(s_level_out_bus_d3[24])); LUT1 #( .INIT(2'h2)) i_79 (.I0(1'b0), .O(s_level_out_bus_d3[23])); LUT1 #( .INIT(2'h2)) i_8 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[30])); LUT1 #( .INIT(2'h2)) i_80 (.I0(1'b0), .O(s_level_out_bus_d3[22])); LUT1 #( .INIT(2'h2)) i_81 (.I0(1'b0), .O(s_level_out_bus_d3[21])); LUT1 #( .INIT(2'h2)) i_82 (.I0(1'b0), .O(s_level_out_bus_d3[20])); LUT1 #( .INIT(2'h2)) i_83 (.I0(1'b0), .O(s_level_out_bus_d3[19])); LUT1 #( .INIT(2'h2)) i_84 (.I0(1'b0), .O(s_level_out_bus_d3[18])); LUT1 #( .INIT(2'h2)) i_85 (.I0(1'b0), .O(s_level_out_bus_d3[17])); LUT1 #( .INIT(2'h2)) i_86 (.I0(1'b0), .O(s_level_out_bus_d3[16])); LUT1 #( .INIT(2'h2)) i_87 (.I0(1'b0), .O(s_level_out_bus_d3[15])); LUT1 #( .INIT(2'h2)) i_88 (.I0(1'b0), .O(s_level_out_bus_d3[14])); LUT1 #( .INIT(2'h2)) i_89 (.I0(1'b0), .O(s_level_out_bus_d3[13])); LUT1 #( .INIT(2'h2)) i_9 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[29])); LUT1 #( .INIT(2'h2)) i_90 (.I0(1'b0), .O(s_level_out_bus_d3[12])); LUT1 #( .INIT(2'h2)) i_91 (.I0(1'b0), .O(s_level_out_bus_d3[11])); LUT1 #( .INIT(2'h2)) i_92 (.I0(1'b0), .O(s_level_out_bus_d3[10])); LUT1 #( .INIT(2'h2)) i_93 (.I0(1'b0), .O(s_level_out_bus_d3[9])); LUT1 #( .INIT(2'h2)) i_94 (.I0(1'b0), .O(s_level_out_bus_d3[8])); LUT1 #( .INIT(2'h2)) i_95 (.I0(1'b0), .O(s_level_out_bus_d3[7])); LUT1 #( .INIT(2'h2)) i_96 (.I0(1'b0), .O(s_level_out_bus_d3[6])); LUT1 #( .INIT(2'h2)) i_97 (.I0(1'b0), .O(s_level_out_bus_d3[5])); LUT1 #( .INIT(2'h2)) i_98 (.I0(1'b0), .O(s_level_out_bus_d3[4])); LUT1 #( .INIT(2'h2)) i_99 (.I0(1'b0), .O(s_level_out_bus_d3[3])); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d1_aurora_64b66b_0_cdc_to_reg (.C(init_clk), .CE(1'b1), .D(p_level_in_int), .Q(s_level_out_d1_aurora_64b66b_0_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d2_reg (.C(init_clk), .CE(1'b1), .D(s_level_out_d1_aurora_64b66b_0_cdc_to), .Q(s_level_out_d2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d3_reg (.C(init_clk), .CE(1'b1), .D(s_level_out_d2), .Q(s_level_out_d3), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d4_reg (.C(init_clk), .CE(1'b1), .D(s_level_out_d3), .Q(s_level_out_d4), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d5_reg (.C(init_clk), .CE(1'b1), .D(s_level_out_d4), .Q(s_level_out_d5), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d6_reg (.C(init_clk), .CE(1'b1), .D(s_level_out_d5), .Q(s_level_out_d6), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_cdc_sync" *) module aurora_64b66b_0_aurora_64b66b_0_cdc_sync__parameterized0_9 (tx_fsm_resetdone_ii, out, init_clk); output tx_fsm_resetdone_ii; input out; input init_clk; wire init_clk; wire p_level_in_int; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d3; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d4; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d5; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d6; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d3; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d4; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d5; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d6; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d3; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d4; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d5; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d6; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d7; assign p_level_in_int = out; assign tx_fsm_resetdone_ii = s_level_out_d5; LUT1 #( .INIT(2'h2)) i_0 (.I0(1'b0), .O(s_out_d1_aurora_64b66b_0_cdc_to)); LUT1 #( .INIT(2'h2)) i_1 (.I0(1'b0), .O(s_out_d2)); LUT1 #( .INIT(2'h2)) i_10 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[28])); LUT1 #( .INIT(2'h2)) i_100 (.I0(1'b0), .O(s_level_out_bus_d3[2])); LUT1 #( .INIT(2'h2)) i_101 (.I0(1'b0), .O(s_level_out_bus_d3[1])); LUT1 #( .INIT(2'h2)) i_102 (.I0(1'b0), .O(s_level_out_bus_d3[0])); LUT1 #( .INIT(2'h2)) i_103 (.I0(1'b0), .O(s_level_out_bus_d4[31])); LUT1 #( .INIT(2'h2)) i_104 (.I0(1'b0), .O(s_level_out_bus_d4[30])); LUT1 #( .INIT(2'h2)) i_105 (.I0(1'b0), .O(s_level_out_bus_d4[29])); LUT1 #( .INIT(2'h2)) i_106 (.I0(1'b0), .O(s_level_out_bus_d4[28])); LUT1 #( .INIT(2'h2)) i_107 (.I0(1'b0), .O(s_level_out_bus_d4[27])); LUT1 #( .INIT(2'h2)) i_108 (.I0(1'b0), .O(s_level_out_bus_d4[26])); LUT1 #( .INIT(2'h2)) i_109 (.I0(1'b0), .O(s_level_out_bus_d4[25])); LUT1 #( .INIT(2'h2)) i_11 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[27])); LUT1 #( .INIT(2'h2)) i_110 (.I0(1'b0), .O(s_level_out_bus_d4[24])); LUT1 #( .INIT(2'h2)) i_111 (.I0(1'b0), .O(s_level_out_bus_d4[23])); LUT1 #( .INIT(2'h2)) i_112 (.I0(1'b0), .O(s_level_out_bus_d4[22])); LUT1 #( .INIT(2'h2)) i_113 (.I0(1'b0), .O(s_level_out_bus_d4[21])); LUT1 #( .INIT(2'h2)) i_114 (.I0(1'b0), .O(s_level_out_bus_d4[20])); LUT1 #( .INIT(2'h2)) i_115 (.I0(1'b0), .O(s_level_out_bus_d4[19])); LUT1 #( .INIT(2'h2)) i_116 (.I0(1'b0), .O(s_level_out_bus_d4[18])); LUT1 #( .INIT(2'h2)) i_117 (.I0(1'b0), .O(s_level_out_bus_d4[17])); LUT1 #( .INIT(2'h2)) i_118 (.I0(1'b0), .O(s_level_out_bus_d4[16])); LUT1 #( .INIT(2'h2)) i_119 (.I0(1'b0), .O(s_level_out_bus_d4[15])); LUT1 #( .INIT(2'h2)) i_12 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[26])); LUT1 #( .INIT(2'h2)) i_120 (.I0(1'b0), .O(s_level_out_bus_d4[14])); LUT1 #( .INIT(2'h2)) i_121 (.I0(1'b0), .O(s_level_out_bus_d4[13])); LUT1 #( .INIT(2'h2)) i_122 (.I0(1'b0), .O(s_level_out_bus_d4[12])); LUT1 #( .INIT(2'h2)) i_123 (.I0(1'b0), .O(s_level_out_bus_d4[11])); LUT1 #( .INIT(2'h2)) i_124 (.I0(1'b0), .O(s_level_out_bus_d4[10])); LUT1 #( .INIT(2'h2)) i_125 (.I0(1'b0), .O(s_level_out_bus_d4[9])); LUT1 #( .INIT(2'h2)) i_126 (.I0(1'b0), .O(s_level_out_bus_d4[8])); LUT1 #( .INIT(2'h2)) i_127 (.I0(1'b0), .O(s_level_out_bus_d4[7])); LUT1 #( .INIT(2'h2)) i_128 (.I0(1'b0), .O(s_level_out_bus_d4[6])); LUT1 #( .INIT(2'h2)) i_129 (.I0(1'b0), .O(s_level_out_bus_d4[5])); LUT1 #( .INIT(2'h2)) i_13 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[25])); LUT1 #( .INIT(2'h2)) i_130 (.I0(1'b0), .O(s_level_out_bus_d4[4])); LUT1 #( .INIT(2'h2)) i_131 (.I0(1'b0), .O(s_level_out_bus_d4[3])); LUT1 #( .INIT(2'h2)) i_132 (.I0(1'b0), .O(s_level_out_bus_d4[2])); LUT1 #( .INIT(2'h2)) i_133 (.I0(1'b0), .O(s_level_out_bus_d4[1])); LUT1 #( .INIT(2'h2)) i_134 (.I0(1'b0), .O(s_level_out_bus_d4[0])); LUT1 #( .INIT(2'h2)) i_135 (.I0(1'b0), .O(s_level_out_bus_d5[31])); LUT1 #( .INIT(2'h2)) i_136 (.I0(1'b0), .O(s_level_out_bus_d5[30])); LUT1 #( .INIT(2'h2)) i_137 (.I0(1'b0), .O(s_level_out_bus_d5[29])); LUT1 #( .INIT(2'h2)) i_138 (.I0(1'b0), .O(s_level_out_bus_d5[28])); LUT1 #( .INIT(2'h2)) i_139 (.I0(1'b0), .O(s_level_out_bus_d5[27])); LUT1 #( .INIT(2'h2)) i_14 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[24])); LUT1 #( .INIT(2'h2)) i_140 (.I0(1'b0), .O(s_level_out_bus_d5[26])); LUT1 #( .INIT(2'h2)) i_141 (.I0(1'b0), .O(s_level_out_bus_d5[25])); LUT1 #( .INIT(2'h2)) i_142 (.I0(1'b0), .O(s_level_out_bus_d5[24])); LUT1 #( .INIT(2'h2)) i_143 (.I0(1'b0), .O(s_level_out_bus_d5[23])); LUT1 #( .INIT(2'h2)) i_144 (.I0(1'b0), .O(s_level_out_bus_d5[22])); LUT1 #( .INIT(2'h2)) i_145 (.I0(1'b0), .O(s_level_out_bus_d5[21])); LUT1 #( .INIT(2'h2)) i_146 (.I0(1'b0), .O(s_level_out_bus_d5[20])); LUT1 #( .INIT(2'h2)) i_147 (.I0(1'b0), .O(s_level_out_bus_d5[19])); LUT1 #( .INIT(2'h2)) i_148 (.I0(1'b0), .O(s_level_out_bus_d5[18])); LUT1 #( .INIT(2'h2)) i_149 (.I0(1'b0), .O(s_level_out_bus_d5[17])); LUT1 #( .INIT(2'h2)) i_15 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[23])); LUT1 #( .INIT(2'h2)) i_150 (.I0(1'b0), .O(s_level_out_bus_d5[16])); LUT1 #( .INIT(2'h2)) i_151 (.I0(1'b0), .O(s_level_out_bus_d5[15])); LUT1 #( .INIT(2'h2)) i_152 (.I0(1'b0), .O(s_level_out_bus_d5[14])); LUT1 #( .INIT(2'h2)) i_153 (.I0(1'b0), .O(s_level_out_bus_d5[13])); LUT1 #( .INIT(2'h2)) i_154 (.I0(1'b0), .O(s_level_out_bus_d5[12])); LUT1 #( .INIT(2'h2)) i_155 (.I0(1'b0), .O(s_level_out_bus_d5[11])); LUT1 #( .INIT(2'h2)) i_156 (.I0(1'b0), .O(s_level_out_bus_d5[10])); LUT1 #( .INIT(2'h2)) i_157 (.I0(1'b0), .O(s_level_out_bus_d5[9])); LUT1 #( .INIT(2'h2)) i_158 (.I0(1'b0), .O(s_level_out_bus_d5[8])); LUT1 #( .INIT(2'h2)) i_159 (.I0(1'b0), .O(s_level_out_bus_d5[7])); LUT1 #( .INIT(2'h2)) i_16 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[22])); LUT1 #( .INIT(2'h2)) i_160 (.I0(1'b0), .O(s_level_out_bus_d5[6])); LUT1 #( .INIT(2'h2)) i_161 (.I0(1'b0), .O(s_level_out_bus_d5[5])); LUT1 #( .INIT(2'h2)) i_162 (.I0(1'b0), .O(s_level_out_bus_d5[4])); LUT1 #( .INIT(2'h2)) i_163 (.I0(1'b0), .O(s_level_out_bus_d5[3])); LUT1 #( .INIT(2'h2)) i_164 (.I0(1'b0), .O(s_level_out_bus_d5[2])); LUT1 #( .INIT(2'h2)) i_165 (.I0(1'b0), .O(s_level_out_bus_d5[1])); LUT1 #( .INIT(2'h2)) i_166 (.I0(1'b0), .O(s_level_out_bus_d5[0])); LUT1 #( .INIT(2'h2)) i_167 (.I0(1'b0), .O(s_level_out_bus_d6[31])); LUT1 #( .INIT(2'h2)) i_168 (.I0(1'b0), .O(s_level_out_bus_d6[30])); LUT1 #( .INIT(2'h2)) i_169 (.I0(1'b0), .O(s_level_out_bus_d6[29])); LUT1 #( .INIT(2'h2)) i_17 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[21])); LUT1 #( .INIT(2'h2)) i_170 (.I0(1'b0), .O(s_level_out_bus_d6[28])); LUT1 #( .INIT(2'h2)) i_171 (.I0(1'b0), .O(s_level_out_bus_d6[27])); LUT1 #( .INIT(2'h2)) i_172 (.I0(1'b0), .O(s_level_out_bus_d6[26])); LUT1 #( .INIT(2'h2)) i_173 (.I0(1'b0), .O(s_level_out_bus_d6[25])); LUT1 #( .INIT(2'h2)) i_174 (.I0(1'b0), .O(s_level_out_bus_d6[24])); LUT1 #( .INIT(2'h2)) i_175 (.I0(1'b0), .O(s_level_out_bus_d6[23])); LUT1 #( .INIT(2'h2)) i_176 (.I0(1'b0), .O(s_level_out_bus_d6[22])); LUT1 #( .INIT(2'h2)) i_177 (.I0(1'b0), .O(s_level_out_bus_d6[21])); LUT1 #( .INIT(2'h2)) i_178 (.I0(1'b0), .O(s_level_out_bus_d6[20])); LUT1 #( .INIT(2'h2)) i_179 (.I0(1'b0), .O(s_level_out_bus_d6[19])); LUT1 #( .INIT(2'h2)) i_18 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[20])); LUT1 #( .INIT(2'h2)) i_180 (.I0(1'b0), .O(s_level_out_bus_d6[18])); LUT1 #( .INIT(2'h2)) i_181 (.I0(1'b0), .O(s_level_out_bus_d6[17])); LUT1 #( .INIT(2'h2)) i_182 (.I0(1'b0), .O(s_level_out_bus_d6[16])); LUT1 #( .INIT(2'h2)) i_183 (.I0(1'b0), .O(s_level_out_bus_d6[15])); LUT1 #( .INIT(2'h2)) i_184 (.I0(1'b0), .O(s_level_out_bus_d6[14])); LUT1 #( .INIT(2'h2)) i_185 (.I0(1'b0), .O(s_level_out_bus_d6[13])); LUT1 #( .INIT(2'h2)) i_186 (.I0(1'b0), .O(s_level_out_bus_d6[12])); LUT1 #( .INIT(2'h2)) i_187 (.I0(1'b0), .O(s_level_out_bus_d6[11])); LUT1 #( .INIT(2'h2)) i_188 (.I0(1'b0), .O(s_level_out_bus_d6[10])); LUT1 #( .INIT(2'h2)) i_189 (.I0(1'b0), .O(s_level_out_bus_d6[9])); LUT1 #( .INIT(2'h2)) i_19 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[19])); LUT1 #( .INIT(2'h2)) i_190 (.I0(1'b0), .O(s_level_out_bus_d6[8])); LUT1 #( .INIT(2'h2)) i_191 (.I0(1'b0), .O(s_level_out_bus_d6[7])); LUT1 #( .INIT(2'h2)) i_192 (.I0(1'b0), .O(s_level_out_bus_d6[6])); LUT1 #( .INIT(2'h2)) i_193 (.I0(1'b0), .O(s_level_out_bus_d6[5])); LUT1 #( .INIT(2'h2)) i_194 (.I0(1'b0), .O(s_level_out_bus_d6[4])); LUT1 #( .INIT(2'h2)) i_195 (.I0(1'b0), .O(s_level_out_bus_d6[3])); LUT1 #( .INIT(2'h2)) i_196 (.I0(1'b0), .O(s_level_out_bus_d6[2])); LUT1 #( .INIT(2'h2)) i_197 (.I0(1'b0), .O(s_level_out_bus_d6[1])); LUT1 #( .INIT(2'h2)) i_198 (.I0(1'b0), .O(s_level_out_bus_d6[0])); LUT1 #( .INIT(2'h2)) i_2 (.I0(1'b0), .O(s_out_d3)); LUT1 #( .INIT(2'h2)) i_20 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[18])); LUT1 #( .INIT(2'h2)) i_21 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[17])); LUT1 #( .INIT(2'h2)) i_22 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[16])); LUT1 #( .INIT(2'h2)) i_23 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[15])); LUT1 #( .INIT(2'h2)) i_24 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[14])); LUT1 #( .INIT(2'h2)) i_25 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[13])); LUT1 #( .INIT(2'h2)) i_26 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[12])); LUT1 #( .INIT(2'h2)) i_27 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[11])); LUT1 #( .INIT(2'h2)) i_28 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[10])); LUT1 #( .INIT(2'h2)) i_29 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[9])); LUT1 #( .INIT(2'h2)) i_3 (.I0(1'b0), .O(s_out_d4)); LUT1 #( .INIT(2'h2)) i_30 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[8])); LUT1 #( .INIT(2'h2)) i_31 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[7])); LUT1 #( .INIT(2'h2)) i_32 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[6])); LUT1 #( .INIT(2'h2)) i_33 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[5])); LUT1 #( .INIT(2'h2)) i_34 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[4])); LUT1 #( .INIT(2'h2)) i_35 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[3])); LUT1 #( .INIT(2'h2)) i_36 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[2])); LUT1 #( .INIT(2'h2)) i_37 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[1])); LUT1 #( .INIT(2'h2)) i_38 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[0])); LUT1 #( .INIT(2'h2)) i_39 (.I0(1'b0), .O(s_level_out_bus_d2[31])); LUT1 #( .INIT(2'h2)) i_4 (.I0(1'b0), .O(s_out_d5)); LUT1 #( .INIT(2'h2)) i_40 (.I0(1'b0), .O(s_level_out_bus_d2[30])); LUT1 #( .INIT(2'h2)) i_41 (.I0(1'b0), .O(s_level_out_bus_d2[29])); LUT1 #( .INIT(2'h2)) i_42 (.I0(1'b0), .O(s_level_out_bus_d2[28])); LUT1 #( .INIT(2'h2)) i_43 (.I0(1'b0), .O(s_level_out_bus_d2[27])); LUT1 #( .INIT(2'h2)) i_44 (.I0(1'b0), .O(s_level_out_bus_d2[26])); LUT1 #( .INIT(2'h2)) i_45 (.I0(1'b0), .O(s_level_out_bus_d2[25])); LUT1 #( .INIT(2'h2)) i_46 (.I0(1'b0), .O(s_level_out_bus_d2[24])); LUT1 #( .INIT(2'h2)) i_47 (.I0(1'b0), .O(s_level_out_bus_d2[23])); LUT1 #( .INIT(2'h2)) i_48 (.I0(1'b0), .O(s_level_out_bus_d2[22])); LUT1 #( .INIT(2'h2)) i_49 (.I0(1'b0), .O(s_level_out_bus_d2[21])); LUT1 #( .INIT(2'h2)) i_5 (.I0(1'b0), .O(s_out_d6)); LUT1 #( .INIT(2'h2)) i_50 (.I0(1'b0), .O(s_level_out_bus_d2[20])); LUT1 #( .INIT(2'h2)) i_51 (.I0(1'b0), .O(s_level_out_bus_d2[19])); LUT1 #( .INIT(2'h2)) i_52 (.I0(1'b0), .O(s_level_out_bus_d2[18])); LUT1 #( .INIT(2'h2)) i_53 (.I0(1'b0), .O(s_level_out_bus_d2[17])); LUT1 #( .INIT(2'h2)) i_54 (.I0(1'b0), .O(s_level_out_bus_d2[16])); LUT1 #( .INIT(2'h2)) i_55 (.I0(1'b0), .O(s_level_out_bus_d2[15])); LUT1 #( .INIT(2'h2)) i_56 (.I0(1'b0), .O(s_level_out_bus_d2[14])); LUT1 #( .INIT(2'h2)) i_57 (.I0(1'b0), .O(s_level_out_bus_d2[13])); LUT1 #( .INIT(2'h2)) i_58 (.I0(1'b0), .O(s_level_out_bus_d2[12])); LUT1 #( .INIT(2'h2)) i_59 (.I0(1'b0), .O(s_level_out_bus_d2[11])); LUT1 #( .INIT(2'h2)) i_6 (.I0(1'b0), .O(s_out_d7)); LUT1 #( .INIT(2'h2)) i_60 (.I0(1'b0), .O(s_level_out_bus_d2[10])); LUT1 #( .INIT(2'h2)) i_61 (.I0(1'b0), .O(s_level_out_bus_d2[9])); LUT1 #( .INIT(2'h2)) i_62 (.I0(1'b0), .O(s_level_out_bus_d2[8])); LUT1 #( .INIT(2'h2)) i_63 (.I0(1'b0), .O(s_level_out_bus_d2[7])); LUT1 #( .INIT(2'h2)) i_64 (.I0(1'b0), .O(s_level_out_bus_d2[6])); LUT1 #( .INIT(2'h2)) i_65 (.I0(1'b0), .O(s_level_out_bus_d2[5])); LUT1 #( .INIT(2'h2)) i_66 (.I0(1'b0), .O(s_level_out_bus_d2[4])); LUT1 #( .INIT(2'h2)) i_67 (.I0(1'b0), .O(s_level_out_bus_d2[3])); LUT1 #( .INIT(2'h2)) i_68 (.I0(1'b0), .O(s_level_out_bus_d2[2])); LUT1 #( .INIT(2'h2)) i_69 (.I0(1'b0), .O(s_level_out_bus_d2[1])); LUT1 #( .INIT(2'h2)) i_7 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[31])); LUT1 #( .INIT(2'h2)) i_70 (.I0(1'b0), .O(s_level_out_bus_d2[0])); LUT1 #( .INIT(2'h2)) i_71 (.I0(1'b0), .O(s_level_out_bus_d3[31])); LUT1 #( .INIT(2'h2)) i_72 (.I0(1'b0), .O(s_level_out_bus_d3[30])); LUT1 #( .INIT(2'h2)) i_73 (.I0(1'b0), .O(s_level_out_bus_d3[29])); LUT1 #( .INIT(2'h2)) i_74 (.I0(1'b0), .O(s_level_out_bus_d3[28])); LUT1 #( .INIT(2'h2)) i_75 (.I0(1'b0), .O(s_level_out_bus_d3[27])); LUT1 #( .INIT(2'h2)) i_76 (.I0(1'b0), .O(s_level_out_bus_d3[26])); LUT1 #( .INIT(2'h2)) i_77 (.I0(1'b0), .O(s_level_out_bus_d3[25])); LUT1 #( .INIT(2'h2)) i_78 (.I0(1'b0), .O(s_level_out_bus_d3[24])); LUT1 #( .INIT(2'h2)) i_79 (.I0(1'b0), .O(s_level_out_bus_d3[23])); LUT1 #( .INIT(2'h2)) i_8 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[30])); LUT1 #( .INIT(2'h2)) i_80 (.I0(1'b0), .O(s_level_out_bus_d3[22])); LUT1 #( .INIT(2'h2)) i_81 (.I0(1'b0), .O(s_level_out_bus_d3[21])); LUT1 #( .INIT(2'h2)) i_82 (.I0(1'b0), .O(s_level_out_bus_d3[20])); LUT1 #( .INIT(2'h2)) i_83 (.I0(1'b0), .O(s_level_out_bus_d3[19])); LUT1 #( .INIT(2'h2)) i_84 (.I0(1'b0), .O(s_level_out_bus_d3[18])); LUT1 #( .INIT(2'h2)) i_85 (.I0(1'b0), .O(s_level_out_bus_d3[17])); LUT1 #( .INIT(2'h2)) i_86 (.I0(1'b0), .O(s_level_out_bus_d3[16])); LUT1 #( .INIT(2'h2)) i_87 (.I0(1'b0), .O(s_level_out_bus_d3[15])); LUT1 #( .INIT(2'h2)) i_88 (.I0(1'b0), .O(s_level_out_bus_d3[14])); LUT1 #( .INIT(2'h2)) i_89 (.I0(1'b0), .O(s_level_out_bus_d3[13])); LUT1 #( .INIT(2'h2)) i_9 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[29])); LUT1 #( .INIT(2'h2)) i_90 (.I0(1'b0), .O(s_level_out_bus_d3[12])); LUT1 #( .INIT(2'h2)) i_91 (.I0(1'b0), .O(s_level_out_bus_d3[11])); LUT1 #( .INIT(2'h2)) i_92 (.I0(1'b0), .O(s_level_out_bus_d3[10])); LUT1 #( .INIT(2'h2)) i_93 (.I0(1'b0), .O(s_level_out_bus_d3[9])); LUT1 #( .INIT(2'h2)) i_94 (.I0(1'b0), .O(s_level_out_bus_d3[8])); LUT1 #( .INIT(2'h2)) i_95 (.I0(1'b0), .O(s_level_out_bus_d3[7])); LUT1 #( .INIT(2'h2)) i_96 (.I0(1'b0), .O(s_level_out_bus_d3[6])); LUT1 #( .INIT(2'h2)) i_97 (.I0(1'b0), .O(s_level_out_bus_d3[5])); LUT1 #( .INIT(2'h2)) i_98 (.I0(1'b0), .O(s_level_out_bus_d3[4])); LUT1 #( .INIT(2'h2)) i_99 (.I0(1'b0), .O(s_level_out_bus_d3[3])); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d1_aurora_64b66b_0_cdc_to_reg (.C(init_clk), .CE(1'b1), .D(p_level_in_int), .Q(s_level_out_d1_aurora_64b66b_0_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d2_reg (.C(init_clk), .CE(1'b1), .D(s_level_out_d1_aurora_64b66b_0_cdc_to), .Q(s_level_out_d2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d3_reg (.C(init_clk), .CE(1'b1), .D(s_level_out_d2), .Q(s_level_out_d3), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d4_reg (.C(init_clk), .CE(1'b1), .D(s_level_out_d3), .Q(s_level_out_d4), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d5_reg (.C(init_clk), .CE(1'b1), .D(s_level_out_d4), .Q(s_level_out_d5), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d6_reg (.C(init_clk), .CE(1'b1), .D(s_level_out_d5), .Q(s_level_out_d6), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_cdc_sync" *) module aurora_64b66b_0_aurora_64b66b_0_cdc_sync__parameterized1 (out, rxbufstatus_out, gtwiz_userclk_rx_usrclk_out, s_level_out_d5_reg_0); output out; input [0:0]rxbufstatus_out; input gtwiz_userclk_rx_usrclk_out; input s_level_out_d5_reg_0; wire gtwiz_userclk_rx_usrclk_out; wire p_level_in_int; wire [0:0]rxbufstatus_out; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d3; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d4; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d5; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d6; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d3; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d4; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d5; wire s_level_out_d5_reg_0; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d6; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d3; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d4; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d5; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d6; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d7; assign out = s_level_out_d5; LUT1 #( .INIT(2'h2)) i_0 (.I0(1'b0), .O(s_out_d1_aurora_64b66b_0_cdc_to)); LUT1 #( .INIT(2'h2)) i_1 (.I0(1'b0), .O(s_out_d2)); LUT1 #( .INIT(2'h2)) i_10 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[28])); LUT1 #( .INIT(2'h2)) i_100 (.I0(1'b0), .O(s_level_out_bus_d3[2])); LUT1 #( .INIT(2'h2)) i_101 (.I0(1'b0), .O(s_level_out_bus_d3[1])); LUT1 #( .INIT(2'h2)) i_102 (.I0(1'b0), .O(s_level_out_bus_d3[0])); LUT1 #( .INIT(2'h2)) i_103 (.I0(1'b0), .O(s_level_out_bus_d4[31])); LUT1 #( .INIT(2'h2)) i_104 (.I0(1'b0), .O(s_level_out_bus_d4[30])); LUT1 #( .INIT(2'h2)) i_105 (.I0(1'b0), .O(s_level_out_bus_d4[29])); LUT1 #( .INIT(2'h2)) i_106 (.I0(1'b0), .O(s_level_out_bus_d4[28])); LUT1 #( .INIT(2'h2)) i_107 (.I0(1'b0), .O(s_level_out_bus_d4[27])); LUT1 #( .INIT(2'h2)) i_108 (.I0(1'b0), .O(s_level_out_bus_d4[26])); LUT1 #( .INIT(2'h2)) i_109 (.I0(1'b0), .O(s_level_out_bus_d4[25])); LUT1 #( .INIT(2'h2)) i_11 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[27])); LUT1 #( .INIT(2'h2)) i_110 (.I0(1'b0), .O(s_level_out_bus_d4[24])); LUT1 #( .INIT(2'h2)) i_111 (.I0(1'b0), .O(s_level_out_bus_d4[23])); LUT1 #( .INIT(2'h2)) i_112 (.I0(1'b0), .O(s_level_out_bus_d4[22])); LUT1 #( .INIT(2'h2)) i_113 (.I0(1'b0), .O(s_level_out_bus_d4[21])); LUT1 #( .INIT(2'h2)) i_114 (.I0(1'b0), .O(s_level_out_bus_d4[20])); LUT1 #( .INIT(2'h2)) i_115 (.I0(1'b0), .O(s_level_out_bus_d4[19])); LUT1 #( .INIT(2'h2)) i_116 (.I0(1'b0), .O(s_level_out_bus_d4[18])); LUT1 #( .INIT(2'h2)) i_117 (.I0(1'b0), .O(s_level_out_bus_d4[17])); LUT1 #( .INIT(2'h2)) i_118 (.I0(1'b0), .O(s_level_out_bus_d4[16])); LUT1 #( .INIT(2'h2)) i_119 (.I0(1'b0), .O(s_level_out_bus_d4[15])); LUT1 #( .INIT(2'h2)) i_12 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[26])); LUT1 #( .INIT(2'h2)) i_120 (.I0(1'b0), .O(s_level_out_bus_d4[14])); LUT1 #( .INIT(2'h2)) i_121 (.I0(1'b0), .O(s_level_out_bus_d4[13])); LUT1 #( .INIT(2'h2)) i_122 (.I0(1'b0), .O(s_level_out_bus_d4[12])); LUT1 #( .INIT(2'h2)) i_123 (.I0(1'b0), .O(s_level_out_bus_d4[11])); LUT1 #( .INIT(2'h2)) i_124 (.I0(1'b0), .O(s_level_out_bus_d4[10])); LUT1 #( .INIT(2'h2)) i_125 (.I0(1'b0), .O(s_level_out_bus_d4[9])); LUT1 #( .INIT(2'h2)) i_126 (.I0(1'b0), .O(s_level_out_bus_d4[8])); LUT1 #( .INIT(2'h2)) i_127 (.I0(1'b0), .O(s_level_out_bus_d4[7])); LUT1 #( .INIT(2'h2)) i_128 (.I0(1'b0), .O(s_level_out_bus_d4[6])); LUT1 #( .INIT(2'h2)) i_129 (.I0(1'b0), .O(s_level_out_bus_d4[5])); LUT1 #( .INIT(2'h2)) i_13 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[25])); LUT1 #( .INIT(2'h2)) i_130 (.I0(1'b0), .O(s_level_out_bus_d4[4])); LUT1 #( .INIT(2'h2)) i_131 (.I0(1'b0), .O(s_level_out_bus_d4[3])); LUT1 #( .INIT(2'h2)) i_132 (.I0(1'b0), .O(s_level_out_bus_d4[2])); LUT1 #( .INIT(2'h2)) i_133 (.I0(1'b0), .O(s_level_out_bus_d4[1])); LUT1 #( .INIT(2'h2)) i_134 (.I0(1'b0), .O(s_level_out_bus_d4[0])); LUT1 #( .INIT(2'h2)) i_135 (.I0(1'b0), .O(s_level_out_bus_d5[31])); LUT1 #( .INIT(2'h2)) i_136 (.I0(1'b0), .O(s_level_out_bus_d5[30])); LUT1 #( .INIT(2'h2)) i_137 (.I0(1'b0), .O(s_level_out_bus_d5[29])); LUT1 #( .INIT(2'h2)) i_138 (.I0(1'b0), .O(s_level_out_bus_d5[28])); LUT1 #( .INIT(2'h2)) i_139 (.I0(1'b0), .O(s_level_out_bus_d5[27])); LUT1 #( .INIT(2'h2)) i_14 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[24])); LUT1 #( .INIT(2'h2)) i_140 (.I0(1'b0), .O(s_level_out_bus_d5[26])); LUT1 #( .INIT(2'h2)) i_141 (.I0(1'b0), .O(s_level_out_bus_d5[25])); LUT1 #( .INIT(2'h2)) i_142 (.I0(1'b0), .O(s_level_out_bus_d5[24])); LUT1 #( .INIT(2'h2)) i_143 (.I0(1'b0), .O(s_level_out_bus_d5[23])); LUT1 #( .INIT(2'h2)) i_144 (.I0(1'b0), .O(s_level_out_bus_d5[22])); LUT1 #( .INIT(2'h2)) i_145 (.I0(1'b0), .O(s_level_out_bus_d5[21])); LUT1 #( .INIT(2'h2)) i_146 (.I0(1'b0), .O(s_level_out_bus_d5[20])); LUT1 #( .INIT(2'h2)) i_147 (.I0(1'b0), .O(s_level_out_bus_d5[19])); LUT1 #( .INIT(2'h2)) i_148 (.I0(1'b0), .O(s_level_out_bus_d5[18])); LUT1 #( .INIT(2'h2)) i_149 (.I0(1'b0), .O(s_level_out_bus_d5[17])); LUT1 #( .INIT(2'h2)) i_15 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[23])); LUT1 #( .INIT(2'h2)) i_150 (.I0(1'b0), .O(s_level_out_bus_d5[16])); LUT1 #( .INIT(2'h2)) i_151 (.I0(1'b0), .O(s_level_out_bus_d5[15])); LUT1 #( .INIT(2'h2)) i_152 (.I0(1'b0), .O(s_level_out_bus_d5[14])); LUT1 #( .INIT(2'h2)) i_153 (.I0(1'b0), .O(s_level_out_bus_d5[13])); LUT1 #( .INIT(2'h2)) i_154 (.I0(1'b0), .O(s_level_out_bus_d5[12])); LUT1 #( .INIT(2'h2)) i_155 (.I0(1'b0), .O(s_level_out_bus_d5[11])); LUT1 #( .INIT(2'h2)) i_156 (.I0(1'b0), .O(s_level_out_bus_d5[10])); LUT1 #( .INIT(2'h2)) i_157 (.I0(1'b0), .O(s_level_out_bus_d5[9])); LUT1 #( .INIT(2'h2)) i_158 (.I0(1'b0), .O(s_level_out_bus_d5[8])); LUT1 #( .INIT(2'h2)) i_159 (.I0(1'b0), .O(s_level_out_bus_d5[7])); LUT1 #( .INIT(2'h2)) i_16 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[22])); LUT1 #( .INIT(2'h2)) i_160 (.I0(1'b0), .O(s_level_out_bus_d5[6])); LUT1 #( .INIT(2'h2)) i_161 (.I0(1'b0), .O(s_level_out_bus_d5[5])); LUT1 #( .INIT(2'h2)) i_162 (.I0(1'b0), .O(s_level_out_bus_d5[4])); LUT1 #( .INIT(2'h2)) i_163 (.I0(1'b0), .O(s_level_out_bus_d5[3])); LUT1 #( .INIT(2'h2)) i_164 (.I0(1'b0), .O(s_level_out_bus_d5[2])); LUT1 #( .INIT(2'h2)) i_165 (.I0(1'b0), .O(s_level_out_bus_d5[1])); LUT1 #( .INIT(2'h2)) i_166 (.I0(1'b0), .O(s_level_out_bus_d5[0])); LUT1 #( .INIT(2'h2)) i_167 (.I0(1'b0), .O(s_level_out_bus_d6[31])); LUT1 #( .INIT(2'h2)) i_168 (.I0(1'b0), .O(s_level_out_bus_d6[30])); LUT1 #( .INIT(2'h2)) i_169 (.I0(1'b0), .O(s_level_out_bus_d6[29])); LUT1 #( .INIT(2'h2)) i_17 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[21])); LUT1 #( .INIT(2'h2)) i_170 (.I0(1'b0), .O(s_level_out_bus_d6[28])); LUT1 #( .INIT(2'h2)) i_171 (.I0(1'b0), .O(s_level_out_bus_d6[27])); LUT1 #( .INIT(2'h2)) i_172 (.I0(1'b0), .O(s_level_out_bus_d6[26])); LUT1 #( .INIT(2'h2)) i_173 (.I0(1'b0), .O(s_level_out_bus_d6[25])); LUT1 #( .INIT(2'h2)) i_174 (.I0(1'b0), .O(s_level_out_bus_d6[24])); LUT1 #( .INIT(2'h2)) i_175 (.I0(1'b0), .O(s_level_out_bus_d6[23])); LUT1 #( .INIT(2'h2)) i_176 (.I0(1'b0), .O(s_level_out_bus_d6[22])); LUT1 #( .INIT(2'h2)) i_177 (.I0(1'b0), .O(s_level_out_bus_d6[21])); LUT1 #( .INIT(2'h2)) i_178 (.I0(1'b0), .O(s_level_out_bus_d6[20])); LUT1 #( .INIT(2'h2)) i_179 (.I0(1'b0), .O(s_level_out_bus_d6[19])); LUT1 #( .INIT(2'h2)) i_18 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[20])); LUT1 #( .INIT(2'h2)) i_180 (.I0(1'b0), .O(s_level_out_bus_d6[18])); LUT1 #( .INIT(2'h2)) i_181 (.I0(1'b0), .O(s_level_out_bus_d6[17])); LUT1 #( .INIT(2'h2)) i_182 (.I0(1'b0), .O(s_level_out_bus_d6[16])); LUT1 #( .INIT(2'h2)) i_183 (.I0(1'b0), .O(s_level_out_bus_d6[15])); LUT1 #( .INIT(2'h2)) i_184 (.I0(1'b0), .O(s_level_out_bus_d6[14])); LUT1 #( .INIT(2'h2)) i_185 (.I0(1'b0), .O(s_level_out_bus_d6[13])); LUT1 #( .INIT(2'h2)) i_186 (.I0(1'b0), .O(s_level_out_bus_d6[12])); LUT1 #( .INIT(2'h2)) i_187 (.I0(1'b0), .O(s_level_out_bus_d6[11])); LUT1 #( .INIT(2'h2)) i_188 (.I0(1'b0), .O(s_level_out_bus_d6[10])); LUT1 #( .INIT(2'h2)) i_189 (.I0(1'b0), .O(s_level_out_bus_d6[9])); LUT1 #( .INIT(2'h2)) i_19 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[19])); LUT1 #( .INIT(2'h2)) i_190 (.I0(1'b0), .O(s_level_out_bus_d6[8])); LUT1 #( .INIT(2'h2)) i_191 (.I0(1'b0), .O(s_level_out_bus_d6[7])); LUT1 #( .INIT(2'h2)) i_192 (.I0(1'b0), .O(s_level_out_bus_d6[6])); LUT1 #( .INIT(2'h2)) i_193 (.I0(1'b0), .O(s_level_out_bus_d6[5])); LUT1 #( .INIT(2'h2)) i_194 (.I0(1'b0), .O(s_level_out_bus_d6[4])); LUT1 #( .INIT(2'h2)) i_195 (.I0(1'b0), .O(s_level_out_bus_d6[3])); LUT1 #( .INIT(2'h2)) i_196 (.I0(1'b0), .O(s_level_out_bus_d6[2])); LUT1 #( .INIT(2'h2)) i_197 (.I0(1'b0), .O(s_level_out_bus_d6[1])); LUT1 #( .INIT(2'h2)) i_198 (.I0(1'b0), .O(s_level_out_bus_d6[0])); LUT1 #( .INIT(2'h2)) i_2 (.I0(1'b0), .O(s_out_d3)); LUT1 #( .INIT(2'h2)) i_20 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[18])); LUT1 #( .INIT(2'h2)) i_21 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[17])); LUT1 #( .INIT(2'h2)) i_22 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[16])); LUT1 #( .INIT(2'h2)) i_23 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[15])); LUT1 #( .INIT(2'h2)) i_24 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[14])); LUT1 #( .INIT(2'h2)) i_25 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[13])); LUT1 #( .INIT(2'h2)) i_26 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[12])); LUT1 #( .INIT(2'h2)) i_27 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[11])); LUT1 #( .INIT(2'h2)) i_28 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[10])); LUT1 #( .INIT(2'h2)) i_29 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[9])); LUT1 #( .INIT(2'h2)) i_3 (.I0(1'b0), .O(s_out_d4)); LUT1 #( .INIT(2'h2)) i_30 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[8])); LUT1 #( .INIT(2'h2)) i_31 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[7])); LUT1 #( .INIT(2'h2)) i_32 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[6])); LUT1 #( .INIT(2'h2)) i_33 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[5])); LUT1 #( .INIT(2'h2)) i_34 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[4])); LUT1 #( .INIT(2'h2)) i_35 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[3])); LUT1 #( .INIT(2'h2)) i_36 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[2])); LUT1 #( .INIT(2'h2)) i_37 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[1])); LUT1 #( .INIT(2'h2)) i_38 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[0])); LUT1 #( .INIT(2'h2)) i_39 (.I0(1'b0), .O(s_level_out_bus_d2[31])); LUT1 #( .INIT(2'h2)) i_4 (.I0(1'b0), .O(s_out_d5)); LUT1 #( .INIT(2'h2)) i_40 (.I0(1'b0), .O(s_level_out_bus_d2[30])); LUT1 #( .INIT(2'h2)) i_41 (.I0(1'b0), .O(s_level_out_bus_d2[29])); LUT1 #( .INIT(2'h2)) i_42 (.I0(1'b0), .O(s_level_out_bus_d2[28])); LUT1 #( .INIT(2'h2)) i_43 (.I0(1'b0), .O(s_level_out_bus_d2[27])); LUT1 #( .INIT(2'h2)) i_44 (.I0(1'b0), .O(s_level_out_bus_d2[26])); LUT1 #( .INIT(2'h2)) i_45 (.I0(1'b0), .O(s_level_out_bus_d2[25])); LUT1 #( .INIT(2'h2)) i_46 (.I0(1'b0), .O(s_level_out_bus_d2[24])); LUT1 #( .INIT(2'h2)) i_47 (.I0(1'b0), .O(s_level_out_bus_d2[23])); LUT1 #( .INIT(2'h2)) i_48 (.I0(1'b0), .O(s_level_out_bus_d2[22])); LUT1 #( .INIT(2'h2)) i_49 (.I0(1'b0), .O(s_level_out_bus_d2[21])); LUT1 #( .INIT(2'h2)) i_5 (.I0(1'b0), .O(s_out_d6)); LUT1 #( .INIT(2'h2)) i_50 (.I0(1'b0), .O(s_level_out_bus_d2[20])); LUT1 #( .INIT(2'h2)) i_51 (.I0(1'b0), .O(s_level_out_bus_d2[19])); LUT1 #( .INIT(2'h2)) i_52 (.I0(1'b0), .O(s_level_out_bus_d2[18])); LUT1 #( .INIT(2'h2)) i_53 (.I0(1'b0), .O(s_level_out_bus_d2[17])); LUT1 #( .INIT(2'h2)) i_54 (.I0(1'b0), .O(s_level_out_bus_d2[16])); LUT1 #( .INIT(2'h2)) i_55 (.I0(1'b0), .O(s_level_out_bus_d2[15])); LUT1 #( .INIT(2'h2)) i_56 (.I0(1'b0), .O(s_level_out_bus_d2[14])); LUT1 #( .INIT(2'h2)) i_57 (.I0(1'b0), .O(s_level_out_bus_d2[13])); LUT1 #( .INIT(2'h2)) i_58 (.I0(1'b0), .O(s_level_out_bus_d2[12])); LUT1 #( .INIT(2'h2)) i_59 (.I0(1'b0), .O(s_level_out_bus_d2[11])); LUT1 #( .INIT(2'h2)) i_6 (.I0(1'b0), .O(s_out_d7)); LUT1 #( .INIT(2'h2)) i_60 (.I0(1'b0), .O(s_level_out_bus_d2[10])); LUT1 #( .INIT(2'h2)) i_61 (.I0(1'b0), .O(s_level_out_bus_d2[9])); LUT1 #( .INIT(2'h2)) i_62 (.I0(1'b0), .O(s_level_out_bus_d2[8])); LUT1 #( .INIT(2'h2)) i_63 (.I0(1'b0), .O(s_level_out_bus_d2[7])); LUT1 #( .INIT(2'h2)) i_64 (.I0(1'b0), .O(s_level_out_bus_d2[6])); LUT1 #( .INIT(2'h2)) i_65 (.I0(1'b0), .O(s_level_out_bus_d2[5])); LUT1 #( .INIT(2'h2)) i_66 (.I0(1'b0), .O(s_level_out_bus_d2[4])); LUT1 #( .INIT(2'h2)) i_67 (.I0(1'b0), .O(s_level_out_bus_d2[3])); LUT1 #( .INIT(2'h2)) i_68 (.I0(1'b0), .O(s_level_out_bus_d2[2])); LUT1 #( .INIT(2'h2)) i_69 (.I0(1'b0), .O(s_level_out_bus_d2[1])); LUT1 #( .INIT(2'h2)) i_7 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[31])); LUT1 #( .INIT(2'h2)) i_70 (.I0(1'b0), .O(s_level_out_bus_d2[0])); LUT1 #( .INIT(2'h2)) i_71 (.I0(1'b0), .O(s_level_out_bus_d3[31])); LUT1 #( .INIT(2'h2)) i_72 (.I0(1'b0), .O(s_level_out_bus_d3[30])); LUT1 #( .INIT(2'h2)) i_73 (.I0(1'b0), .O(s_level_out_bus_d3[29])); LUT1 #( .INIT(2'h2)) i_74 (.I0(1'b0), .O(s_level_out_bus_d3[28])); LUT1 #( .INIT(2'h2)) i_75 (.I0(1'b0), .O(s_level_out_bus_d3[27])); LUT1 #( .INIT(2'h2)) i_76 (.I0(1'b0), .O(s_level_out_bus_d3[26])); LUT1 #( .INIT(2'h2)) i_77 (.I0(1'b0), .O(s_level_out_bus_d3[25])); LUT1 #( .INIT(2'h2)) i_78 (.I0(1'b0), .O(s_level_out_bus_d3[24])); LUT1 #( .INIT(2'h2)) i_79 (.I0(1'b0), .O(s_level_out_bus_d3[23])); LUT1 #( .INIT(2'h2)) i_8 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[30])); LUT1 #( .INIT(2'h2)) i_80 (.I0(1'b0), .O(s_level_out_bus_d3[22])); LUT1 #( .INIT(2'h2)) i_81 (.I0(1'b0), .O(s_level_out_bus_d3[21])); LUT1 #( .INIT(2'h2)) i_82 (.I0(1'b0), .O(s_level_out_bus_d3[20])); LUT1 #( .INIT(2'h2)) i_83 (.I0(1'b0), .O(s_level_out_bus_d3[19])); LUT1 #( .INIT(2'h2)) i_84 (.I0(1'b0), .O(s_level_out_bus_d3[18])); LUT1 #( .INIT(2'h2)) i_85 (.I0(1'b0), .O(s_level_out_bus_d3[17])); LUT1 #( .INIT(2'h2)) i_86 (.I0(1'b0), .O(s_level_out_bus_d3[16])); LUT1 #( .INIT(2'h2)) i_87 (.I0(1'b0), .O(s_level_out_bus_d3[15])); LUT1 #( .INIT(2'h2)) i_88 (.I0(1'b0), .O(s_level_out_bus_d3[14])); LUT1 #( .INIT(2'h2)) i_89 (.I0(1'b0), .O(s_level_out_bus_d3[13])); LUT1 #( .INIT(2'h2)) i_9 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[29])); LUT1 #( .INIT(2'h2)) i_90 (.I0(1'b0), .O(s_level_out_bus_d3[12])); LUT1 #( .INIT(2'h2)) i_91 (.I0(1'b0), .O(s_level_out_bus_d3[11])); LUT1 #( .INIT(2'h2)) i_92 (.I0(1'b0), .O(s_level_out_bus_d3[10])); LUT1 #( .INIT(2'h2)) i_93 (.I0(1'b0), .O(s_level_out_bus_d3[9])); LUT1 #( .INIT(2'h2)) i_94 (.I0(1'b0), .O(s_level_out_bus_d3[8])); LUT1 #( .INIT(2'h2)) i_95 (.I0(1'b0), .O(s_level_out_bus_d3[7])); LUT1 #( .INIT(2'h2)) i_96 (.I0(1'b0), .O(s_level_out_bus_d3[6])); LUT1 #( .INIT(2'h2)) i_97 (.I0(1'b0), .O(s_level_out_bus_d3[5])); LUT1 #( .INIT(2'h2)) i_98 (.I0(1'b0), .O(s_level_out_bus_d3[4])); LUT1 #( .INIT(2'h2)) i_99 (.I0(1'b0), .O(s_level_out_bus_d3[3])); FDRE p_level_in_d1_cdc_from_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(rxbufstatus_out), .Q(p_level_in_int), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d1_aurora_64b66b_0_cdc_to_reg (.C(s_level_out_d5_reg_0), .CE(1'b1), .D(p_level_in_int), .Q(s_level_out_d1_aurora_64b66b_0_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d2_reg (.C(s_level_out_d5_reg_0), .CE(1'b1), .D(s_level_out_d1_aurora_64b66b_0_cdc_to), .Q(s_level_out_d2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d3_reg (.C(s_level_out_d5_reg_0), .CE(1'b1), .D(s_level_out_d2), .Q(s_level_out_d3), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d4_reg (.C(s_level_out_d5_reg_0), .CE(1'b1), .D(s_level_out_d3), .Q(s_level_out_d4), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d5_reg (.C(s_level_out_d5_reg_0), .CE(1'b1), .D(s_level_out_d4), .Q(s_level_out_d5), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d6_reg (.C(s_level_out_d5_reg_0), .CE(1'b1), .D(s_level_out_d5), .Q(s_level_out_d6), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_cdc_sync" *) module aurora_64b66b_0_aurora_64b66b_0_cdc_sync__parameterized2 (out, s_level_out_d1_aurora_64b66b_0_cdc_to_reg_0, gtwiz_userclk_rx_usrclk_out); output out; input s_level_out_d1_aurora_64b66b_0_cdc_to_reg_0; input gtwiz_userclk_rx_usrclk_out; wire gtwiz_userclk_rx_usrclk_out; wire p_level_in_int; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d3; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d4; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d5; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d6; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d3; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d4; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d5; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d6; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d3; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d4; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d5; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d6; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d7; assign out = s_level_out_d3; assign p_level_in_int = s_level_out_d1_aurora_64b66b_0_cdc_to_reg_0; LUT1 #( .INIT(2'h2)) i_0 (.I0(1'b0), .O(s_out_d1_aurora_64b66b_0_cdc_to)); LUT1 #( .INIT(2'h2)) i_1 (.I0(1'b0), .O(s_out_d2)); LUT1 #( .INIT(2'h2)) i_10 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[28])); LUT1 #( .INIT(2'h2)) i_100 (.I0(1'b0), .O(s_level_out_bus_d3[2])); LUT1 #( .INIT(2'h2)) i_101 (.I0(1'b0), .O(s_level_out_bus_d3[1])); LUT1 #( .INIT(2'h2)) i_102 (.I0(1'b0), .O(s_level_out_bus_d3[0])); LUT1 #( .INIT(2'h2)) i_103 (.I0(1'b0), .O(s_level_out_bus_d4[31])); LUT1 #( .INIT(2'h2)) i_104 (.I0(1'b0), .O(s_level_out_bus_d4[30])); LUT1 #( .INIT(2'h2)) i_105 (.I0(1'b0), .O(s_level_out_bus_d4[29])); LUT1 #( .INIT(2'h2)) i_106 (.I0(1'b0), .O(s_level_out_bus_d4[28])); LUT1 #( .INIT(2'h2)) i_107 (.I0(1'b0), .O(s_level_out_bus_d4[27])); LUT1 #( .INIT(2'h2)) i_108 (.I0(1'b0), .O(s_level_out_bus_d4[26])); LUT1 #( .INIT(2'h2)) i_109 (.I0(1'b0), .O(s_level_out_bus_d4[25])); LUT1 #( .INIT(2'h2)) i_11 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[27])); LUT1 #( .INIT(2'h2)) i_110 (.I0(1'b0), .O(s_level_out_bus_d4[24])); LUT1 #( .INIT(2'h2)) i_111 (.I0(1'b0), .O(s_level_out_bus_d4[23])); LUT1 #( .INIT(2'h2)) i_112 (.I0(1'b0), .O(s_level_out_bus_d4[22])); LUT1 #( .INIT(2'h2)) i_113 (.I0(1'b0), .O(s_level_out_bus_d4[21])); LUT1 #( .INIT(2'h2)) i_114 (.I0(1'b0), .O(s_level_out_bus_d4[20])); LUT1 #( .INIT(2'h2)) i_115 (.I0(1'b0), .O(s_level_out_bus_d4[19])); LUT1 #( .INIT(2'h2)) i_116 (.I0(1'b0), .O(s_level_out_bus_d4[18])); LUT1 #( .INIT(2'h2)) i_117 (.I0(1'b0), .O(s_level_out_bus_d4[17])); LUT1 #( .INIT(2'h2)) i_118 (.I0(1'b0), .O(s_level_out_bus_d4[16])); LUT1 #( .INIT(2'h2)) i_119 (.I0(1'b0), .O(s_level_out_bus_d4[15])); LUT1 #( .INIT(2'h2)) i_12 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[26])); LUT1 #( .INIT(2'h2)) i_120 (.I0(1'b0), .O(s_level_out_bus_d4[14])); LUT1 #( .INIT(2'h2)) i_121 (.I0(1'b0), .O(s_level_out_bus_d4[13])); LUT1 #( .INIT(2'h2)) i_122 (.I0(1'b0), .O(s_level_out_bus_d4[12])); LUT1 #( .INIT(2'h2)) i_123 (.I0(1'b0), .O(s_level_out_bus_d4[11])); LUT1 #( .INIT(2'h2)) i_124 (.I0(1'b0), .O(s_level_out_bus_d4[10])); LUT1 #( .INIT(2'h2)) i_125 (.I0(1'b0), .O(s_level_out_bus_d4[9])); LUT1 #( .INIT(2'h2)) i_126 (.I0(1'b0), .O(s_level_out_bus_d4[8])); LUT1 #( .INIT(2'h2)) i_127 (.I0(1'b0), .O(s_level_out_bus_d4[7])); LUT1 #( .INIT(2'h2)) i_128 (.I0(1'b0), .O(s_level_out_bus_d4[6])); LUT1 #( .INIT(2'h2)) i_129 (.I0(1'b0), .O(s_level_out_bus_d4[5])); LUT1 #( .INIT(2'h2)) i_13 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[25])); LUT1 #( .INIT(2'h2)) i_130 (.I0(1'b0), .O(s_level_out_bus_d4[4])); LUT1 #( .INIT(2'h2)) i_131 (.I0(1'b0), .O(s_level_out_bus_d4[3])); LUT1 #( .INIT(2'h2)) i_132 (.I0(1'b0), .O(s_level_out_bus_d4[2])); LUT1 #( .INIT(2'h2)) i_133 (.I0(1'b0), .O(s_level_out_bus_d4[1])); LUT1 #( .INIT(2'h2)) i_134 (.I0(1'b0), .O(s_level_out_bus_d4[0])); LUT1 #( .INIT(2'h2)) i_135 (.I0(1'b0), .O(s_level_out_bus_d5[31])); LUT1 #( .INIT(2'h2)) i_136 (.I0(1'b0), .O(s_level_out_bus_d5[30])); LUT1 #( .INIT(2'h2)) i_137 (.I0(1'b0), .O(s_level_out_bus_d5[29])); LUT1 #( .INIT(2'h2)) i_138 (.I0(1'b0), .O(s_level_out_bus_d5[28])); LUT1 #( .INIT(2'h2)) i_139 (.I0(1'b0), .O(s_level_out_bus_d5[27])); LUT1 #( .INIT(2'h2)) i_14 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[24])); LUT1 #( .INIT(2'h2)) i_140 (.I0(1'b0), .O(s_level_out_bus_d5[26])); LUT1 #( .INIT(2'h2)) i_141 (.I0(1'b0), .O(s_level_out_bus_d5[25])); LUT1 #( .INIT(2'h2)) i_142 (.I0(1'b0), .O(s_level_out_bus_d5[24])); LUT1 #( .INIT(2'h2)) i_143 (.I0(1'b0), .O(s_level_out_bus_d5[23])); LUT1 #( .INIT(2'h2)) i_144 (.I0(1'b0), .O(s_level_out_bus_d5[22])); LUT1 #( .INIT(2'h2)) i_145 (.I0(1'b0), .O(s_level_out_bus_d5[21])); LUT1 #( .INIT(2'h2)) i_146 (.I0(1'b0), .O(s_level_out_bus_d5[20])); LUT1 #( .INIT(2'h2)) i_147 (.I0(1'b0), .O(s_level_out_bus_d5[19])); LUT1 #( .INIT(2'h2)) i_148 (.I0(1'b0), .O(s_level_out_bus_d5[18])); LUT1 #( .INIT(2'h2)) i_149 (.I0(1'b0), .O(s_level_out_bus_d5[17])); LUT1 #( .INIT(2'h2)) i_15 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[23])); LUT1 #( .INIT(2'h2)) i_150 (.I0(1'b0), .O(s_level_out_bus_d5[16])); LUT1 #( .INIT(2'h2)) i_151 (.I0(1'b0), .O(s_level_out_bus_d5[15])); LUT1 #( .INIT(2'h2)) i_152 (.I0(1'b0), .O(s_level_out_bus_d5[14])); LUT1 #( .INIT(2'h2)) i_153 (.I0(1'b0), .O(s_level_out_bus_d5[13])); LUT1 #( .INIT(2'h2)) i_154 (.I0(1'b0), .O(s_level_out_bus_d5[12])); LUT1 #( .INIT(2'h2)) i_155 (.I0(1'b0), .O(s_level_out_bus_d5[11])); LUT1 #( .INIT(2'h2)) i_156 (.I0(1'b0), .O(s_level_out_bus_d5[10])); LUT1 #( .INIT(2'h2)) i_157 (.I0(1'b0), .O(s_level_out_bus_d5[9])); LUT1 #( .INIT(2'h2)) i_158 (.I0(1'b0), .O(s_level_out_bus_d5[8])); LUT1 #( .INIT(2'h2)) i_159 (.I0(1'b0), .O(s_level_out_bus_d5[7])); LUT1 #( .INIT(2'h2)) i_16 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[22])); LUT1 #( .INIT(2'h2)) i_160 (.I0(1'b0), .O(s_level_out_bus_d5[6])); LUT1 #( .INIT(2'h2)) i_161 (.I0(1'b0), .O(s_level_out_bus_d5[5])); LUT1 #( .INIT(2'h2)) i_162 (.I0(1'b0), .O(s_level_out_bus_d5[4])); LUT1 #( .INIT(2'h2)) i_163 (.I0(1'b0), .O(s_level_out_bus_d5[3])); LUT1 #( .INIT(2'h2)) i_164 (.I0(1'b0), .O(s_level_out_bus_d5[2])); LUT1 #( .INIT(2'h2)) i_165 (.I0(1'b0), .O(s_level_out_bus_d5[1])); LUT1 #( .INIT(2'h2)) i_166 (.I0(1'b0), .O(s_level_out_bus_d5[0])); LUT1 #( .INIT(2'h2)) i_167 (.I0(1'b0), .O(s_level_out_bus_d6[31])); LUT1 #( .INIT(2'h2)) i_168 (.I0(1'b0), .O(s_level_out_bus_d6[30])); LUT1 #( .INIT(2'h2)) i_169 (.I0(1'b0), .O(s_level_out_bus_d6[29])); LUT1 #( .INIT(2'h2)) i_17 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[21])); LUT1 #( .INIT(2'h2)) i_170 (.I0(1'b0), .O(s_level_out_bus_d6[28])); LUT1 #( .INIT(2'h2)) i_171 (.I0(1'b0), .O(s_level_out_bus_d6[27])); LUT1 #( .INIT(2'h2)) i_172 (.I0(1'b0), .O(s_level_out_bus_d6[26])); LUT1 #( .INIT(2'h2)) i_173 (.I0(1'b0), .O(s_level_out_bus_d6[25])); LUT1 #( .INIT(2'h2)) i_174 (.I0(1'b0), .O(s_level_out_bus_d6[24])); LUT1 #( .INIT(2'h2)) i_175 (.I0(1'b0), .O(s_level_out_bus_d6[23])); LUT1 #( .INIT(2'h2)) i_176 (.I0(1'b0), .O(s_level_out_bus_d6[22])); LUT1 #( .INIT(2'h2)) i_177 (.I0(1'b0), .O(s_level_out_bus_d6[21])); LUT1 #( .INIT(2'h2)) i_178 (.I0(1'b0), .O(s_level_out_bus_d6[20])); LUT1 #( .INIT(2'h2)) i_179 (.I0(1'b0), .O(s_level_out_bus_d6[19])); LUT1 #( .INIT(2'h2)) i_18 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[20])); LUT1 #( .INIT(2'h2)) i_180 (.I0(1'b0), .O(s_level_out_bus_d6[18])); LUT1 #( .INIT(2'h2)) i_181 (.I0(1'b0), .O(s_level_out_bus_d6[17])); LUT1 #( .INIT(2'h2)) i_182 (.I0(1'b0), .O(s_level_out_bus_d6[16])); LUT1 #( .INIT(2'h2)) i_183 (.I0(1'b0), .O(s_level_out_bus_d6[15])); LUT1 #( .INIT(2'h2)) i_184 (.I0(1'b0), .O(s_level_out_bus_d6[14])); LUT1 #( .INIT(2'h2)) i_185 (.I0(1'b0), .O(s_level_out_bus_d6[13])); LUT1 #( .INIT(2'h2)) i_186 (.I0(1'b0), .O(s_level_out_bus_d6[12])); LUT1 #( .INIT(2'h2)) i_187 (.I0(1'b0), .O(s_level_out_bus_d6[11])); LUT1 #( .INIT(2'h2)) i_188 (.I0(1'b0), .O(s_level_out_bus_d6[10])); LUT1 #( .INIT(2'h2)) i_189 (.I0(1'b0), .O(s_level_out_bus_d6[9])); LUT1 #( .INIT(2'h2)) i_19 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[19])); LUT1 #( .INIT(2'h2)) i_190 (.I0(1'b0), .O(s_level_out_bus_d6[8])); LUT1 #( .INIT(2'h2)) i_191 (.I0(1'b0), .O(s_level_out_bus_d6[7])); LUT1 #( .INIT(2'h2)) i_192 (.I0(1'b0), .O(s_level_out_bus_d6[6])); LUT1 #( .INIT(2'h2)) i_193 (.I0(1'b0), .O(s_level_out_bus_d6[5])); LUT1 #( .INIT(2'h2)) i_194 (.I0(1'b0), .O(s_level_out_bus_d6[4])); LUT1 #( .INIT(2'h2)) i_195 (.I0(1'b0), .O(s_level_out_bus_d6[3])); LUT1 #( .INIT(2'h2)) i_196 (.I0(1'b0), .O(s_level_out_bus_d6[2])); LUT1 #( .INIT(2'h2)) i_197 (.I0(1'b0), .O(s_level_out_bus_d6[1])); LUT1 #( .INIT(2'h2)) i_198 (.I0(1'b0), .O(s_level_out_bus_d6[0])); LUT1 #( .INIT(2'h2)) i_2 (.I0(1'b0), .O(s_out_d3)); LUT1 #( .INIT(2'h2)) i_20 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[18])); LUT1 #( .INIT(2'h2)) i_21 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[17])); LUT1 #( .INIT(2'h2)) i_22 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[16])); LUT1 #( .INIT(2'h2)) i_23 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[15])); LUT1 #( .INIT(2'h2)) i_24 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[14])); LUT1 #( .INIT(2'h2)) i_25 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[13])); LUT1 #( .INIT(2'h2)) i_26 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[12])); LUT1 #( .INIT(2'h2)) i_27 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[11])); LUT1 #( .INIT(2'h2)) i_28 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[10])); LUT1 #( .INIT(2'h2)) i_29 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[9])); LUT1 #( .INIT(2'h2)) i_3 (.I0(1'b0), .O(s_out_d4)); LUT1 #( .INIT(2'h2)) i_30 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[8])); LUT1 #( .INIT(2'h2)) i_31 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[7])); LUT1 #( .INIT(2'h2)) i_32 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[6])); LUT1 #( .INIT(2'h2)) i_33 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[5])); LUT1 #( .INIT(2'h2)) i_34 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[4])); LUT1 #( .INIT(2'h2)) i_35 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[3])); LUT1 #( .INIT(2'h2)) i_36 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[2])); LUT1 #( .INIT(2'h2)) i_37 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[1])); LUT1 #( .INIT(2'h2)) i_38 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[0])); LUT1 #( .INIT(2'h2)) i_39 (.I0(1'b0), .O(s_level_out_bus_d2[31])); LUT1 #( .INIT(2'h2)) i_4 (.I0(1'b0), .O(s_out_d5)); LUT1 #( .INIT(2'h2)) i_40 (.I0(1'b0), .O(s_level_out_bus_d2[30])); LUT1 #( .INIT(2'h2)) i_41 (.I0(1'b0), .O(s_level_out_bus_d2[29])); LUT1 #( .INIT(2'h2)) i_42 (.I0(1'b0), .O(s_level_out_bus_d2[28])); LUT1 #( .INIT(2'h2)) i_43 (.I0(1'b0), .O(s_level_out_bus_d2[27])); LUT1 #( .INIT(2'h2)) i_44 (.I0(1'b0), .O(s_level_out_bus_d2[26])); LUT1 #( .INIT(2'h2)) i_45 (.I0(1'b0), .O(s_level_out_bus_d2[25])); LUT1 #( .INIT(2'h2)) i_46 (.I0(1'b0), .O(s_level_out_bus_d2[24])); LUT1 #( .INIT(2'h2)) i_47 (.I0(1'b0), .O(s_level_out_bus_d2[23])); LUT1 #( .INIT(2'h2)) i_48 (.I0(1'b0), .O(s_level_out_bus_d2[22])); LUT1 #( .INIT(2'h2)) i_49 (.I0(1'b0), .O(s_level_out_bus_d2[21])); LUT1 #( .INIT(2'h2)) i_5 (.I0(1'b0), .O(s_out_d6)); LUT1 #( .INIT(2'h2)) i_50 (.I0(1'b0), .O(s_level_out_bus_d2[20])); LUT1 #( .INIT(2'h2)) i_51 (.I0(1'b0), .O(s_level_out_bus_d2[19])); LUT1 #( .INIT(2'h2)) i_52 (.I0(1'b0), .O(s_level_out_bus_d2[18])); LUT1 #( .INIT(2'h2)) i_53 (.I0(1'b0), .O(s_level_out_bus_d2[17])); LUT1 #( .INIT(2'h2)) i_54 (.I0(1'b0), .O(s_level_out_bus_d2[16])); LUT1 #( .INIT(2'h2)) i_55 (.I0(1'b0), .O(s_level_out_bus_d2[15])); LUT1 #( .INIT(2'h2)) i_56 (.I0(1'b0), .O(s_level_out_bus_d2[14])); LUT1 #( .INIT(2'h2)) i_57 (.I0(1'b0), .O(s_level_out_bus_d2[13])); LUT1 #( .INIT(2'h2)) i_58 (.I0(1'b0), .O(s_level_out_bus_d2[12])); LUT1 #( .INIT(2'h2)) i_59 (.I0(1'b0), .O(s_level_out_bus_d2[11])); LUT1 #( .INIT(2'h2)) i_6 (.I0(1'b0), .O(s_out_d7)); LUT1 #( .INIT(2'h2)) i_60 (.I0(1'b0), .O(s_level_out_bus_d2[10])); LUT1 #( .INIT(2'h2)) i_61 (.I0(1'b0), .O(s_level_out_bus_d2[9])); LUT1 #( .INIT(2'h2)) i_62 (.I0(1'b0), .O(s_level_out_bus_d2[8])); LUT1 #( .INIT(2'h2)) i_63 (.I0(1'b0), .O(s_level_out_bus_d2[7])); LUT1 #( .INIT(2'h2)) i_64 (.I0(1'b0), .O(s_level_out_bus_d2[6])); LUT1 #( .INIT(2'h2)) i_65 (.I0(1'b0), .O(s_level_out_bus_d2[5])); LUT1 #( .INIT(2'h2)) i_66 (.I0(1'b0), .O(s_level_out_bus_d2[4])); LUT1 #( .INIT(2'h2)) i_67 (.I0(1'b0), .O(s_level_out_bus_d2[3])); LUT1 #( .INIT(2'h2)) i_68 (.I0(1'b0), .O(s_level_out_bus_d2[2])); LUT1 #( .INIT(2'h2)) i_69 (.I0(1'b0), .O(s_level_out_bus_d2[1])); LUT1 #( .INIT(2'h2)) i_7 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[31])); LUT1 #( .INIT(2'h2)) i_70 (.I0(1'b0), .O(s_level_out_bus_d2[0])); LUT1 #( .INIT(2'h2)) i_71 (.I0(1'b0), .O(s_level_out_bus_d3[31])); LUT1 #( .INIT(2'h2)) i_72 (.I0(1'b0), .O(s_level_out_bus_d3[30])); LUT1 #( .INIT(2'h2)) i_73 (.I0(1'b0), .O(s_level_out_bus_d3[29])); LUT1 #( .INIT(2'h2)) i_74 (.I0(1'b0), .O(s_level_out_bus_d3[28])); LUT1 #( .INIT(2'h2)) i_75 (.I0(1'b0), .O(s_level_out_bus_d3[27])); LUT1 #( .INIT(2'h2)) i_76 (.I0(1'b0), .O(s_level_out_bus_d3[26])); LUT1 #( .INIT(2'h2)) i_77 (.I0(1'b0), .O(s_level_out_bus_d3[25])); LUT1 #( .INIT(2'h2)) i_78 (.I0(1'b0), .O(s_level_out_bus_d3[24])); LUT1 #( .INIT(2'h2)) i_79 (.I0(1'b0), .O(s_level_out_bus_d3[23])); LUT1 #( .INIT(2'h2)) i_8 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[30])); LUT1 #( .INIT(2'h2)) i_80 (.I0(1'b0), .O(s_level_out_bus_d3[22])); LUT1 #( .INIT(2'h2)) i_81 (.I0(1'b0), .O(s_level_out_bus_d3[21])); LUT1 #( .INIT(2'h2)) i_82 (.I0(1'b0), .O(s_level_out_bus_d3[20])); LUT1 #( .INIT(2'h2)) i_83 (.I0(1'b0), .O(s_level_out_bus_d3[19])); LUT1 #( .INIT(2'h2)) i_84 (.I0(1'b0), .O(s_level_out_bus_d3[18])); LUT1 #( .INIT(2'h2)) i_85 (.I0(1'b0), .O(s_level_out_bus_d3[17])); LUT1 #( .INIT(2'h2)) i_86 (.I0(1'b0), .O(s_level_out_bus_d3[16])); LUT1 #( .INIT(2'h2)) i_87 (.I0(1'b0), .O(s_level_out_bus_d3[15])); LUT1 #( .INIT(2'h2)) i_88 (.I0(1'b0), .O(s_level_out_bus_d3[14])); LUT1 #( .INIT(2'h2)) i_89 (.I0(1'b0), .O(s_level_out_bus_d3[13])); LUT1 #( .INIT(2'h2)) i_9 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[29])); LUT1 #( .INIT(2'h2)) i_90 (.I0(1'b0), .O(s_level_out_bus_d3[12])); LUT1 #( .INIT(2'h2)) i_91 (.I0(1'b0), .O(s_level_out_bus_d3[11])); LUT1 #( .INIT(2'h2)) i_92 (.I0(1'b0), .O(s_level_out_bus_d3[10])); LUT1 #( .INIT(2'h2)) i_93 (.I0(1'b0), .O(s_level_out_bus_d3[9])); LUT1 #( .INIT(2'h2)) i_94 (.I0(1'b0), .O(s_level_out_bus_d3[8])); LUT1 #( .INIT(2'h2)) i_95 (.I0(1'b0), .O(s_level_out_bus_d3[7])); LUT1 #( .INIT(2'h2)) i_96 (.I0(1'b0), .O(s_level_out_bus_d3[6])); LUT1 #( .INIT(2'h2)) i_97 (.I0(1'b0), .O(s_level_out_bus_d3[5])); LUT1 #( .INIT(2'h2)) i_98 (.I0(1'b0), .O(s_level_out_bus_d3[4])); LUT1 #( .INIT(2'h2)) i_99 (.I0(1'b0), .O(s_level_out_bus_d3[3])); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d1_aurora_64b66b_0_cdc_to_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(p_level_in_int), .Q(s_level_out_d1_aurora_64b66b_0_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d2_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(s_level_out_d1_aurora_64b66b_0_cdc_to), .Q(s_level_out_d2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d3_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(s_level_out_d2), .Q(s_level_out_d3), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d4_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(s_level_out_d3), .Q(s_level_out_d4), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d5_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(s_level_out_d4), .Q(s_level_out_d5), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d6_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(s_level_out_d5), .Q(s_level_out_d6), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_cdc_sync" *) module aurora_64b66b_0_aurora_64b66b_0_cdc_sync__parameterized3 (cbcc_reset_cbstg2_rd_clk, full, s_level_out_d5_reg_0); input cbcc_reset_cbstg2_rd_clk; input full; input s_level_out_d5_reg_0; wire cbcc_reset_cbstg2_rd_clk; wire full; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d3; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d4; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d5; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d6; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d3; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d4; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d5; wire s_level_out_d5_reg_0; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d6; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d3; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d4; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d5; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d6; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d7; LUT1 #( .INIT(2'h2)) i_0 (.I0(1'b0), .O(s_out_d1_aurora_64b66b_0_cdc_to)); LUT1 #( .INIT(2'h2)) i_1 (.I0(1'b0), .O(s_out_d2)); LUT1 #( .INIT(2'h2)) i_10 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[28])); LUT1 #( .INIT(2'h2)) i_100 (.I0(1'b0), .O(s_level_out_bus_d3[2])); LUT1 #( .INIT(2'h2)) i_101 (.I0(1'b0), .O(s_level_out_bus_d3[1])); LUT1 #( .INIT(2'h2)) i_102 (.I0(1'b0), .O(s_level_out_bus_d3[0])); LUT1 #( .INIT(2'h2)) i_103 (.I0(1'b0), .O(s_level_out_bus_d4[31])); LUT1 #( .INIT(2'h2)) i_104 (.I0(1'b0), .O(s_level_out_bus_d4[30])); LUT1 #( .INIT(2'h2)) i_105 (.I0(1'b0), .O(s_level_out_bus_d4[29])); LUT1 #( .INIT(2'h2)) i_106 (.I0(1'b0), .O(s_level_out_bus_d4[28])); LUT1 #( .INIT(2'h2)) i_107 (.I0(1'b0), .O(s_level_out_bus_d4[27])); LUT1 #( .INIT(2'h2)) i_108 (.I0(1'b0), .O(s_level_out_bus_d4[26])); LUT1 #( .INIT(2'h2)) i_109 (.I0(1'b0), .O(s_level_out_bus_d4[25])); LUT1 #( .INIT(2'h2)) i_11 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[27])); LUT1 #( .INIT(2'h2)) i_110 (.I0(1'b0), .O(s_level_out_bus_d4[24])); LUT1 #( .INIT(2'h2)) i_111 (.I0(1'b0), .O(s_level_out_bus_d4[23])); LUT1 #( .INIT(2'h2)) i_112 (.I0(1'b0), .O(s_level_out_bus_d4[22])); LUT1 #( .INIT(2'h2)) i_113 (.I0(1'b0), .O(s_level_out_bus_d4[21])); LUT1 #( .INIT(2'h2)) i_114 (.I0(1'b0), .O(s_level_out_bus_d4[20])); LUT1 #( .INIT(2'h2)) i_115 (.I0(1'b0), .O(s_level_out_bus_d4[19])); LUT1 #( .INIT(2'h2)) i_116 (.I0(1'b0), .O(s_level_out_bus_d4[18])); LUT1 #( .INIT(2'h2)) i_117 (.I0(1'b0), .O(s_level_out_bus_d4[17])); LUT1 #( .INIT(2'h2)) i_118 (.I0(1'b0), .O(s_level_out_bus_d4[16])); LUT1 #( .INIT(2'h2)) i_119 (.I0(1'b0), .O(s_level_out_bus_d4[15])); LUT1 #( .INIT(2'h2)) i_12 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[26])); LUT1 #( .INIT(2'h2)) i_120 (.I0(1'b0), .O(s_level_out_bus_d4[14])); LUT1 #( .INIT(2'h2)) i_121 (.I0(1'b0), .O(s_level_out_bus_d4[13])); LUT1 #( .INIT(2'h2)) i_122 (.I0(1'b0), .O(s_level_out_bus_d4[12])); LUT1 #( .INIT(2'h2)) i_123 (.I0(1'b0), .O(s_level_out_bus_d4[11])); LUT1 #( .INIT(2'h2)) i_124 (.I0(1'b0), .O(s_level_out_bus_d4[10])); LUT1 #( .INIT(2'h2)) i_125 (.I0(1'b0), .O(s_level_out_bus_d4[9])); LUT1 #( .INIT(2'h2)) i_126 (.I0(1'b0), .O(s_level_out_bus_d4[8])); LUT1 #( .INIT(2'h2)) i_127 (.I0(1'b0), .O(s_level_out_bus_d4[7])); LUT1 #( .INIT(2'h2)) i_128 (.I0(1'b0), .O(s_level_out_bus_d4[6])); LUT1 #( .INIT(2'h2)) i_129 (.I0(1'b0), .O(s_level_out_bus_d4[5])); LUT1 #( .INIT(2'h2)) i_13 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[25])); LUT1 #( .INIT(2'h2)) i_130 (.I0(1'b0), .O(s_level_out_bus_d4[4])); LUT1 #( .INIT(2'h2)) i_131 (.I0(1'b0), .O(s_level_out_bus_d4[3])); LUT1 #( .INIT(2'h2)) i_132 (.I0(1'b0), .O(s_level_out_bus_d4[2])); LUT1 #( .INIT(2'h2)) i_133 (.I0(1'b0), .O(s_level_out_bus_d4[1])); LUT1 #( .INIT(2'h2)) i_134 (.I0(1'b0), .O(s_level_out_bus_d4[0])); LUT1 #( .INIT(2'h2)) i_135 (.I0(1'b0), .O(s_level_out_bus_d5[31])); LUT1 #( .INIT(2'h2)) i_136 (.I0(1'b0), .O(s_level_out_bus_d5[30])); LUT1 #( .INIT(2'h2)) i_137 (.I0(1'b0), .O(s_level_out_bus_d5[29])); LUT1 #( .INIT(2'h2)) i_138 (.I0(1'b0), .O(s_level_out_bus_d5[28])); LUT1 #( .INIT(2'h2)) i_139 (.I0(1'b0), .O(s_level_out_bus_d5[27])); LUT1 #( .INIT(2'h2)) i_14 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[24])); LUT1 #( .INIT(2'h2)) i_140 (.I0(1'b0), .O(s_level_out_bus_d5[26])); LUT1 #( .INIT(2'h2)) i_141 (.I0(1'b0), .O(s_level_out_bus_d5[25])); LUT1 #( .INIT(2'h2)) i_142 (.I0(1'b0), .O(s_level_out_bus_d5[24])); LUT1 #( .INIT(2'h2)) i_143 (.I0(1'b0), .O(s_level_out_bus_d5[23])); LUT1 #( .INIT(2'h2)) i_144 (.I0(1'b0), .O(s_level_out_bus_d5[22])); LUT1 #( .INIT(2'h2)) i_145 (.I0(1'b0), .O(s_level_out_bus_d5[21])); LUT1 #( .INIT(2'h2)) i_146 (.I0(1'b0), .O(s_level_out_bus_d5[20])); LUT1 #( .INIT(2'h2)) i_147 (.I0(1'b0), .O(s_level_out_bus_d5[19])); LUT1 #( .INIT(2'h2)) i_148 (.I0(1'b0), .O(s_level_out_bus_d5[18])); LUT1 #( .INIT(2'h2)) i_149 (.I0(1'b0), .O(s_level_out_bus_d5[17])); LUT1 #( .INIT(2'h2)) i_15 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[23])); LUT1 #( .INIT(2'h2)) i_150 (.I0(1'b0), .O(s_level_out_bus_d5[16])); LUT1 #( .INIT(2'h2)) i_151 (.I0(1'b0), .O(s_level_out_bus_d5[15])); LUT1 #( .INIT(2'h2)) i_152 (.I0(1'b0), .O(s_level_out_bus_d5[14])); LUT1 #( .INIT(2'h2)) i_153 (.I0(1'b0), .O(s_level_out_bus_d5[13])); LUT1 #( .INIT(2'h2)) i_154 (.I0(1'b0), .O(s_level_out_bus_d5[12])); LUT1 #( .INIT(2'h2)) i_155 (.I0(1'b0), .O(s_level_out_bus_d5[11])); LUT1 #( .INIT(2'h2)) i_156 (.I0(1'b0), .O(s_level_out_bus_d5[10])); LUT1 #( .INIT(2'h2)) i_157 (.I0(1'b0), .O(s_level_out_bus_d5[9])); LUT1 #( .INIT(2'h2)) i_158 (.I0(1'b0), .O(s_level_out_bus_d5[8])); LUT1 #( .INIT(2'h2)) i_159 (.I0(1'b0), .O(s_level_out_bus_d5[7])); LUT1 #( .INIT(2'h2)) i_16 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[22])); LUT1 #( .INIT(2'h2)) i_160 (.I0(1'b0), .O(s_level_out_bus_d5[6])); LUT1 #( .INIT(2'h2)) i_161 (.I0(1'b0), .O(s_level_out_bus_d5[5])); LUT1 #( .INIT(2'h2)) i_162 (.I0(1'b0), .O(s_level_out_bus_d5[4])); LUT1 #( .INIT(2'h2)) i_163 (.I0(1'b0), .O(s_level_out_bus_d5[3])); LUT1 #( .INIT(2'h2)) i_164 (.I0(1'b0), .O(s_level_out_bus_d5[2])); LUT1 #( .INIT(2'h2)) i_165 (.I0(1'b0), .O(s_level_out_bus_d5[1])); LUT1 #( .INIT(2'h2)) i_166 (.I0(1'b0), .O(s_level_out_bus_d5[0])); LUT1 #( .INIT(2'h2)) i_167 (.I0(1'b0), .O(s_level_out_bus_d6[31])); LUT1 #( .INIT(2'h2)) i_168 (.I0(1'b0), .O(s_level_out_bus_d6[30])); LUT1 #( .INIT(2'h2)) i_169 (.I0(1'b0), .O(s_level_out_bus_d6[29])); LUT1 #( .INIT(2'h2)) i_17 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[21])); LUT1 #( .INIT(2'h2)) i_170 (.I0(1'b0), .O(s_level_out_bus_d6[28])); LUT1 #( .INIT(2'h2)) i_171 (.I0(1'b0), .O(s_level_out_bus_d6[27])); LUT1 #( .INIT(2'h2)) i_172 (.I0(1'b0), .O(s_level_out_bus_d6[26])); LUT1 #( .INIT(2'h2)) i_173 (.I0(1'b0), .O(s_level_out_bus_d6[25])); LUT1 #( .INIT(2'h2)) i_174 (.I0(1'b0), .O(s_level_out_bus_d6[24])); LUT1 #( .INIT(2'h2)) i_175 (.I0(1'b0), .O(s_level_out_bus_d6[23])); LUT1 #( .INIT(2'h2)) i_176 (.I0(1'b0), .O(s_level_out_bus_d6[22])); LUT1 #( .INIT(2'h2)) i_177 (.I0(1'b0), .O(s_level_out_bus_d6[21])); LUT1 #( .INIT(2'h2)) i_178 (.I0(1'b0), .O(s_level_out_bus_d6[20])); LUT1 #( .INIT(2'h2)) i_179 (.I0(1'b0), .O(s_level_out_bus_d6[19])); LUT1 #( .INIT(2'h2)) i_18 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[20])); LUT1 #( .INIT(2'h2)) i_180 (.I0(1'b0), .O(s_level_out_bus_d6[18])); LUT1 #( .INIT(2'h2)) i_181 (.I0(1'b0), .O(s_level_out_bus_d6[17])); LUT1 #( .INIT(2'h2)) i_182 (.I0(1'b0), .O(s_level_out_bus_d6[16])); LUT1 #( .INIT(2'h2)) i_183 (.I0(1'b0), .O(s_level_out_bus_d6[15])); LUT1 #( .INIT(2'h2)) i_184 (.I0(1'b0), .O(s_level_out_bus_d6[14])); LUT1 #( .INIT(2'h2)) i_185 (.I0(1'b0), .O(s_level_out_bus_d6[13])); LUT1 #( .INIT(2'h2)) i_186 (.I0(1'b0), .O(s_level_out_bus_d6[12])); LUT1 #( .INIT(2'h2)) i_187 (.I0(1'b0), .O(s_level_out_bus_d6[11])); LUT1 #( .INIT(2'h2)) i_188 (.I0(1'b0), .O(s_level_out_bus_d6[10])); LUT1 #( .INIT(2'h2)) i_189 (.I0(1'b0), .O(s_level_out_bus_d6[9])); LUT1 #( .INIT(2'h2)) i_19 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[19])); LUT1 #( .INIT(2'h2)) i_190 (.I0(1'b0), .O(s_level_out_bus_d6[8])); LUT1 #( .INIT(2'h2)) i_191 (.I0(1'b0), .O(s_level_out_bus_d6[7])); LUT1 #( .INIT(2'h2)) i_192 (.I0(1'b0), .O(s_level_out_bus_d6[6])); LUT1 #( .INIT(2'h2)) i_193 (.I0(1'b0), .O(s_level_out_bus_d6[5])); LUT1 #( .INIT(2'h2)) i_194 (.I0(1'b0), .O(s_level_out_bus_d6[4])); LUT1 #( .INIT(2'h2)) i_195 (.I0(1'b0), .O(s_level_out_bus_d6[3])); LUT1 #( .INIT(2'h2)) i_196 (.I0(1'b0), .O(s_level_out_bus_d6[2])); LUT1 #( .INIT(2'h2)) i_197 (.I0(1'b0), .O(s_level_out_bus_d6[1])); LUT1 #( .INIT(2'h2)) i_198 (.I0(1'b0), .O(s_level_out_bus_d6[0])); LUT1 #( .INIT(2'h2)) i_2 (.I0(1'b0), .O(s_out_d3)); LUT1 #( .INIT(2'h2)) i_20 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[18])); LUT1 #( .INIT(2'h2)) i_21 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[17])); LUT1 #( .INIT(2'h2)) i_22 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[16])); LUT1 #( .INIT(2'h2)) i_23 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[15])); LUT1 #( .INIT(2'h2)) i_24 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[14])); LUT1 #( .INIT(2'h2)) i_25 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[13])); LUT1 #( .INIT(2'h2)) i_26 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[12])); LUT1 #( .INIT(2'h2)) i_27 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[11])); LUT1 #( .INIT(2'h2)) i_28 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[10])); LUT1 #( .INIT(2'h2)) i_29 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[9])); LUT1 #( .INIT(2'h2)) i_3 (.I0(1'b0), .O(s_out_d4)); LUT1 #( .INIT(2'h2)) i_30 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[8])); LUT1 #( .INIT(2'h2)) i_31 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[7])); LUT1 #( .INIT(2'h2)) i_32 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[6])); LUT1 #( .INIT(2'h2)) i_33 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[5])); LUT1 #( .INIT(2'h2)) i_34 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[4])); LUT1 #( .INIT(2'h2)) i_35 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[3])); LUT1 #( .INIT(2'h2)) i_36 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[2])); LUT1 #( .INIT(2'h2)) i_37 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[1])); LUT1 #( .INIT(2'h2)) i_38 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[0])); LUT1 #( .INIT(2'h2)) i_39 (.I0(1'b0), .O(s_level_out_bus_d2[31])); LUT1 #( .INIT(2'h2)) i_4 (.I0(1'b0), .O(s_out_d5)); LUT1 #( .INIT(2'h2)) i_40 (.I0(1'b0), .O(s_level_out_bus_d2[30])); LUT1 #( .INIT(2'h2)) i_41 (.I0(1'b0), .O(s_level_out_bus_d2[29])); LUT1 #( .INIT(2'h2)) i_42 (.I0(1'b0), .O(s_level_out_bus_d2[28])); LUT1 #( .INIT(2'h2)) i_43 (.I0(1'b0), .O(s_level_out_bus_d2[27])); LUT1 #( .INIT(2'h2)) i_44 (.I0(1'b0), .O(s_level_out_bus_d2[26])); LUT1 #( .INIT(2'h2)) i_45 (.I0(1'b0), .O(s_level_out_bus_d2[25])); LUT1 #( .INIT(2'h2)) i_46 (.I0(1'b0), .O(s_level_out_bus_d2[24])); LUT1 #( .INIT(2'h2)) i_47 (.I0(1'b0), .O(s_level_out_bus_d2[23])); LUT1 #( .INIT(2'h2)) i_48 (.I0(1'b0), .O(s_level_out_bus_d2[22])); LUT1 #( .INIT(2'h2)) i_49 (.I0(1'b0), .O(s_level_out_bus_d2[21])); LUT1 #( .INIT(2'h2)) i_5 (.I0(1'b0), .O(s_out_d6)); LUT1 #( .INIT(2'h2)) i_50 (.I0(1'b0), .O(s_level_out_bus_d2[20])); LUT1 #( .INIT(2'h2)) i_51 (.I0(1'b0), .O(s_level_out_bus_d2[19])); LUT1 #( .INIT(2'h2)) i_52 (.I0(1'b0), .O(s_level_out_bus_d2[18])); LUT1 #( .INIT(2'h2)) i_53 (.I0(1'b0), .O(s_level_out_bus_d2[17])); LUT1 #( .INIT(2'h2)) i_54 (.I0(1'b0), .O(s_level_out_bus_d2[16])); LUT1 #( .INIT(2'h2)) i_55 (.I0(1'b0), .O(s_level_out_bus_d2[15])); LUT1 #( .INIT(2'h2)) i_56 (.I0(1'b0), .O(s_level_out_bus_d2[14])); LUT1 #( .INIT(2'h2)) i_57 (.I0(1'b0), .O(s_level_out_bus_d2[13])); LUT1 #( .INIT(2'h2)) i_58 (.I0(1'b0), .O(s_level_out_bus_d2[12])); LUT1 #( .INIT(2'h2)) i_59 (.I0(1'b0), .O(s_level_out_bus_d2[11])); LUT1 #( .INIT(2'h2)) i_6 (.I0(1'b0), .O(s_out_d7)); LUT1 #( .INIT(2'h2)) i_60 (.I0(1'b0), .O(s_level_out_bus_d2[10])); LUT1 #( .INIT(2'h2)) i_61 (.I0(1'b0), .O(s_level_out_bus_d2[9])); LUT1 #( .INIT(2'h2)) i_62 (.I0(1'b0), .O(s_level_out_bus_d2[8])); LUT1 #( .INIT(2'h2)) i_63 (.I0(1'b0), .O(s_level_out_bus_d2[7])); LUT1 #( .INIT(2'h2)) i_64 (.I0(1'b0), .O(s_level_out_bus_d2[6])); LUT1 #( .INIT(2'h2)) i_65 (.I0(1'b0), .O(s_level_out_bus_d2[5])); LUT1 #( .INIT(2'h2)) i_66 (.I0(1'b0), .O(s_level_out_bus_d2[4])); LUT1 #( .INIT(2'h2)) i_67 (.I0(1'b0), .O(s_level_out_bus_d2[3])); LUT1 #( .INIT(2'h2)) i_68 (.I0(1'b0), .O(s_level_out_bus_d2[2])); LUT1 #( .INIT(2'h2)) i_69 (.I0(1'b0), .O(s_level_out_bus_d2[1])); LUT1 #( .INIT(2'h2)) i_7 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[31])); LUT1 #( .INIT(2'h2)) i_70 (.I0(1'b0), .O(s_level_out_bus_d2[0])); LUT1 #( .INIT(2'h2)) i_71 (.I0(1'b0), .O(s_level_out_bus_d3[31])); LUT1 #( .INIT(2'h2)) i_72 (.I0(1'b0), .O(s_level_out_bus_d3[30])); LUT1 #( .INIT(2'h2)) i_73 (.I0(1'b0), .O(s_level_out_bus_d3[29])); LUT1 #( .INIT(2'h2)) i_74 (.I0(1'b0), .O(s_level_out_bus_d3[28])); LUT1 #( .INIT(2'h2)) i_75 (.I0(1'b0), .O(s_level_out_bus_d3[27])); LUT1 #( .INIT(2'h2)) i_76 (.I0(1'b0), .O(s_level_out_bus_d3[26])); LUT1 #( .INIT(2'h2)) i_77 (.I0(1'b0), .O(s_level_out_bus_d3[25])); LUT1 #( .INIT(2'h2)) i_78 (.I0(1'b0), .O(s_level_out_bus_d3[24])); LUT1 #( .INIT(2'h2)) i_79 (.I0(1'b0), .O(s_level_out_bus_d3[23])); LUT1 #( .INIT(2'h2)) i_8 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[30])); LUT1 #( .INIT(2'h2)) i_80 (.I0(1'b0), .O(s_level_out_bus_d3[22])); LUT1 #( .INIT(2'h2)) i_81 (.I0(1'b0), .O(s_level_out_bus_d3[21])); LUT1 #( .INIT(2'h2)) i_82 (.I0(1'b0), .O(s_level_out_bus_d3[20])); LUT1 #( .INIT(2'h2)) i_83 (.I0(1'b0), .O(s_level_out_bus_d3[19])); LUT1 #( .INIT(2'h2)) i_84 (.I0(1'b0), .O(s_level_out_bus_d3[18])); LUT1 #( .INIT(2'h2)) i_85 (.I0(1'b0), .O(s_level_out_bus_d3[17])); LUT1 #( .INIT(2'h2)) i_86 (.I0(1'b0), .O(s_level_out_bus_d3[16])); LUT1 #( .INIT(2'h2)) i_87 (.I0(1'b0), .O(s_level_out_bus_d3[15])); LUT1 #( .INIT(2'h2)) i_88 (.I0(1'b0), .O(s_level_out_bus_d3[14])); LUT1 #( .INIT(2'h2)) i_89 (.I0(1'b0), .O(s_level_out_bus_d3[13])); LUT1 #( .INIT(2'h2)) i_9 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[29])); LUT1 #( .INIT(2'h2)) i_90 (.I0(1'b0), .O(s_level_out_bus_d3[12])); LUT1 #( .INIT(2'h2)) i_91 (.I0(1'b0), .O(s_level_out_bus_d3[11])); LUT1 #( .INIT(2'h2)) i_92 (.I0(1'b0), .O(s_level_out_bus_d3[10])); LUT1 #( .INIT(2'h2)) i_93 (.I0(1'b0), .O(s_level_out_bus_d3[9])); LUT1 #( .INIT(2'h2)) i_94 (.I0(1'b0), .O(s_level_out_bus_d3[8])); LUT1 #( .INIT(2'h2)) i_95 (.I0(1'b0), .O(s_level_out_bus_d3[7])); LUT1 #( .INIT(2'h2)) i_96 (.I0(1'b0), .O(s_level_out_bus_d3[6])); LUT1 #( .INIT(2'h2)) i_97 (.I0(1'b0), .O(s_level_out_bus_d3[5])); LUT1 #( .INIT(2'h2)) i_98 (.I0(1'b0), .O(s_level_out_bus_d3[4])); LUT1 #( .INIT(2'h2)) i_99 (.I0(1'b0), .O(s_level_out_bus_d3[3])); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d1_aurora_64b66b_0_cdc_to_reg (.C(s_level_out_d5_reg_0), .CE(1'b1), .D(full), .Q(s_level_out_d1_aurora_64b66b_0_cdc_to), .R(cbcc_reset_cbstg2_rd_clk)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d2_reg (.C(s_level_out_d5_reg_0), .CE(1'b1), .D(s_level_out_d1_aurora_64b66b_0_cdc_to), .Q(s_level_out_d2), .R(cbcc_reset_cbstg2_rd_clk)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d3_reg (.C(s_level_out_d5_reg_0), .CE(1'b1), .D(s_level_out_d2), .Q(s_level_out_d3), .R(cbcc_reset_cbstg2_rd_clk)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d4_reg (.C(s_level_out_d5_reg_0), .CE(1'b1), .D(s_level_out_d3), .Q(s_level_out_d4), .R(cbcc_reset_cbstg2_rd_clk)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d5_reg (.C(s_level_out_d5_reg_0), .CE(1'b1), .D(s_level_out_d4), .Q(s_level_out_d5), .R(cbcc_reset_cbstg2_rd_clk)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d6_reg (.C(s_level_out_d5_reg_0), .CE(1'b1), .D(s_level_out_d5), .Q(s_level_out_d6), .R(cbcc_reset_cbstg2_rd_clk)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_cdc_sync" *) module aurora_64b66b_0_aurora_64b66b_0_cdc_sync__parameterized3_28 (out, cbcc_fifo_reset_rd_clk, overflow, s_level_out_d5_reg_0); output out; input cbcc_fifo_reset_rd_clk; input overflow; input s_level_out_d5_reg_0; wire cbcc_fifo_reset_rd_clk; wire overflow; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d3; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d4; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d5; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire [31:0]s_level_out_bus_d6; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d3; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d4; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d5; wire s_level_out_d5_reg_0; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_level_out_d6; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d3; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d4; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d5; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d6; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire s_out_d7; assign out = s_level_out_d5; LUT1 #( .INIT(2'h2)) i_0 (.I0(1'b0), .O(s_out_d1_aurora_64b66b_0_cdc_to)); LUT1 #( .INIT(2'h2)) i_1 (.I0(1'b0), .O(s_out_d2)); LUT1 #( .INIT(2'h2)) i_10 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[28])); LUT1 #( .INIT(2'h2)) i_100 (.I0(1'b0), .O(s_level_out_bus_d3[2])); LUT1 #( .INIT(2'h2)) i_101 (.I0(1'b0), .O(s_level_out_bus_d3[1])); LUT1 #( .INIT(2'h2)) i_102 (.I0(1'b0), .O(s_level_out_bus_d3[0])); LUT1 #( .INIT(2'h2)) i_103 (.I0(1'b0), .O(s_level_out_bus_d4[31])); LUT1 #( .INIT(2'h2)) i_104 (.I0(1'b0), .O(s_level_out_bus_d4[30])); LUT1 #( .INIT(2'h2)) i_105 (.I0(1'b0), .O(s_level_out_bus_d4[29])); LUT1 #( .INIT(2'h2)) i_106 (.I0(1'b0), .O(s_level_out_bus_d4[28])); LUT1 #( .INIT(2'h2)) i_107 (.I0(1'b0), .O(s_level_out_bus_d4[27])); LUT1 #( .INIT(2'h2)) i_108 (.I0(1'b0), .O(s_level_out_bus_d4[26])); LUT1 #( .INIT(2'h2)) i_109 (.I0(1'b0), .O(s_level_out_bus_d4[25])); LUT1 #( .INIT(2'h2)) i_11 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[27])); LUT1 #( .INIT(2'h2)) i_110 (.I0(1'b0), .O(s_level_out_bus_d4[24])); LUT1 #( .INIT(2'h2)) i_111 (.I0(1'b0), .O(s_level_out_bus_d4[23])); LUT1 #( .INIT(2'h2)) i_112 (.I0(1'b0), .O(s_level_out_bus_d4[22])); LUT1 #( .INIT(2'h2)) i_113 (.I0(1'b0), .O(s_level_out_bus_d4[21])); LUT1 #( .INIT(2'h2)) i_114 (.I0(1'b0), .O(s_level_out_bus_d4[20])); LUT1 #( .INIT(2'h2)) i_115 (.I0(1'b0), .O(s_level_out_bus_d4[19])); LUT1 #( .INIT(2'h2)) i_116 (.I0(1'b0), .O(s_level_out_bus_d4[18])); LUT1 #( .INIT(2'h2)) i_117 (.I0(1'b0), .O(s_level_out_bus_d4[17])); LUT1 #( .INIT(2'h2)) i_118 (.I0(1'b0), .O(s_level_out_bus_d4[16])); LUT1 #( .INIT(2'h2)) i_119 (.I0(1'b0), .O(s_level_out_bus_d4[15])); LUT1 #( .INIT(2'h2)) i_12 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[26])); LUT1 #( .INIT(2'h2)) i_120 (.I0(1'b0), .O(s_level_out_bus_d4[14])); LUT1 #( .INIT(2'h2)) i_121 (.I0(1'b0), .O(s_level_out_bus_d4[13])); LUT1 #( .INIT(2'h2)) i_122 (.I0(1'b0), .O(s_level_out_bus_d4[12])); LUT1 #( .INIT(2'h2)) i_123 (.I0(1'b0), .O(s_level_out_bus_d4[11])); LUT1 #( .INIT(2'h2)) i_124 (.I0(1'b0), .O(s_level_out_bus_d4[10])); LUT1 #( .INIT(2'h2)) i_125 (.I0(1'b0), .O(s_level_out_bus_d4[9])); LUT1 #( .INIT(2'h2)) i_126 (.I0(1'b0), .O(s_level_out_bus_d4[8])); LUT1 #( .INIT(2'h2)) i_127 (.I0(1'b0), .O(s_level_out_bus_d4[7])); LUT1 #( .INIT(2'h2)) i_128 (.I0(1'b0), .O(s_level_out_bus_d4[6])); LUT1 #( .INIT(2'h2)) i_129 (.I0(1'b0), .O(s_level_out_bus_d4[5])); LUT1 #( .INIT(2'h2)) i_13 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[25])); LUT1 #( .INIT(2'h2)) i_130 (.I0(1'b0), .O(s_level_out_bus_d4[4])); LUT1 #( .INIT(2'h2)) i_131 (.I0(1'b0), .O(s_level_out_bus_d4[3])); LUT1 #( .INIT(2'h2)) i_132 (.I0(1'b0), .O(s_level_out_bus_d4[2])); LUT1 #( .INIT(2'h2)) i_133 (.I0(1'b0), .O(s_level_out_bus_d4[1])); LUT1 #( .INIT(2'h2)) i_134 (.I0(1'b0), .O(s_level_out_bus_d4[0])); LUT1 #( .INIT(2'h2)) i_135 (.I0(1'b0), .O(s_level_out_bus_d5[31])); LUT1 #( .INIT(2'h2)) i_136 (.I0(1'b0), .O(s_level_out_bus_d5[30])); LUT1 #( .INIT(2'h2)) i_137 (.I0(1'b0), .O(s_level_out_bus_d5[29])); LUT1 #( .INIT(2'h2)) i_138 (.I0(1'b0), .O(s_level_out_bus_d5[28])); LUT1 #( .INIT(2'h2)) i_139 (.I0(1'b0), .O(s_level_out_bus_d5[27])); LUT1 #( .INIT(2'h2)) i_14 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[24])); LUT1 #( .INIT(2'h2)) i_140 (.I0(1'b0), .O(s_level_out_bus_d5[26])); LUT1 #( .INIT(2'h2)) i_141 (.I0(1'b0), .O(s_level_out_bus_d5[25])); LUT1 #( .INIT(2'h2)) i_142 (.I0(1'b0), .O(s_level_out_bus_d5[24])); LUT1 #( .INIT(2'h2)) i_143 (.I0(1'b0), .O(s_level_out_bus_d5[23])); LUT1 #( .INIT(2'h2)) i_144 (.I0(1'b0), .O(s_level_out_bus_d5[22])); LUT1 #( .INIT(2'h2)) i_145 (.I0(1'b0), .O(s_level_out_bus_d5[21])); LUT1 #( .INIT(2'h2)) i_146 (.I0(1'b0), .O(s_level_out_bus_d5[20])); LUT1 #( .INIT(2'h2)) i_147 (.I0(1'b0), .O(s_level_out_bus_d5[19])); LUT1 #( .INIT(2'h2)) i_148 (.I0(1'b0), .O(s_level_out_bus_d5[18])); LUT1 #( .INIT(2'h2)) i_149 (.I0(1'b0), .O(s_level_out_bus_d5[17])); LUT1 #( .INIT(2'h2)) i_15 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[23])); LUT1 #( .INIT(2'h2)) i_150 (.I0(1'b0), .O(s_level_out_bus_d5[16])); LUT1 #( .INIT(2'h2)) i_151 (.I0(1'b0), .O(s_level_out_bus_d5[15])); LUT1 #( .INIT(2'h2)) i_152 (.I0(1'b0), .O(s_level_out_bus_d5[14])); LUT1 #( .INIT(2'h2)) i_153 (.I0(1'b0), .O(s_level_out_bus_d5[13])); LUT1 #( .INIT(2'h2)) i_154 (.I0(1'b0), .O(s_level_out_bus_d5[12])); LUT1 #( .INIT(2'h2)) i_155 (.I0(1'b0), .O(s_level_out_bus_d5[11])); LUT1 #( .INIT(2'h2)) i_156 (.I0(1'b0), .O(s_level_out_bus_d5[10])); LUT1 #( .INIT(2'h2)) i_157 (.I0(1'b0), .O(s_level_out_bus_d5[9])); LUT1 #( .INIT(2'h2)) i_158 (.I0(1'b0), .O(s_level_out_bus_d5[8])); LUT1 #( .INIT(2'h2)) i_159 (.I0(1'b0), .O(s_level_out_bus_d5[7])); LUT1 #( .INIT(2'h2)) i_16 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[22])); LUT1 #( .INIT(2'h2)) i_160 (.I0(1'b0), .O(s_level_out_bus_d5[6])); LUT1 #( .INIT(2'h2)) i_161 (.I0(1'b0), .O(s_level_out_bus_d5[5])); LUT1 #( .INIT(2'h2)) i_162 (.I0(1'b0), .O(s_level_out_bus_d5[4])); LUT1 #( .INIT(2'h2)) i_163 (.I0(1'b0), .O(s_level_out_bus_d5[3])); LUT1 #( .INIT(2'h2)) i_164 (.I0(1'b0), .O(s_level_out_bus_d5[2])); LUT1 #( .INIT(2'h2)) i_165 (.I0(1'b0), .O(s_level_out_bus_d5[1])); LUT1 #( .INIT(2'h2)) i_166 (.I0(1'b0), .O(s_level_out_bus_d5[0])); LUT1 #( .INIT(2'h2)) i_167 (.I0(1'b0), .O(s_level_out_bus_d6[31])); LUT1 #( .INIT(2'h2)) i_168 (.I0(1'b0), .O(s_level_out_bus_d6[30])); LUT1 #( .INIT(2'h2)) i_169 (.I0(1'b0), .O(s_level_out_bus_d6[29])); LUT1 #( .INIT(2'h2)) i_17 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[21])); LUT1 #( .INIT(2'h2)) i_170 (.I0(1'b0), .O(s_level_out_bus_d6[28])); LUT1 #( .INIT(2'h2)) i_171 (.I0(1'b0), .O(s_level_out_bus_d6[27])); LUT1 #( .INIT(2'h2)) i_172 (.I0(1'b0), .O(s_level_out_bus_d6[26])); LUT1 #( .INIT(2'h2)) i_173 (.I0(1'b0), .O(s_level_out_bus_d6[25])); LUT1 #( .INIT(2'h2)) i_174 (.I0(1'b0), .O(s_level_out_bus_d6[24])); LUT1 #( .INIT(2'h2)) i_175 (.I0(1'b0), .O(s_level_out_bus_d6[23])); LUT1 #( .INIT(2'h2)) i_176 (.I0(1'b0), .O(s_level_out_bus_d6[22])); LUT1 #( .INIT(2'h2)) i_177 (.I0(1'b0), .O(s_level_out_bus_d6[21])); LUT1 #( .INIT(2'h2)) i_178 (.I0(1'b0), .O(s_level_out_bus_d6[20])); LUT1 #( .INIT(2'h2)) i_179 (.I0(1'b0), .O(s_level_out_bus_d6[19])); LUT1 #( .INIT(2'h2)) i_18 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[20])); LUT1 #( .INIT(2'h2)) i_180 (.I0(1'b0), .O(s_level_out_bus_d6[18])); LUT1 #( .INIT(2'h2)) i_181 (.I0(1'b0), .O(s_level_out_bus_d6[17])); LUT1 #( .INIT(2'h2)) i_182 (.I0(1'b0), .O(s_level_out_bus_d6[16])); LUT1 #( .INIT(2'h2)) i_183 (.I0(1'b0), .O(s_level_out_bus_d6[15])); LUT1 #( .INIT(2'h2)) i_184 (.I0(1'b0), .O(s_level_out_bus_d6[14])); LUT1 #( .INIT(2'h2)) i_185 (.I0(1'b0), .O(s_level_out_bus_d6[13])); LUT1 #( .INIT(2'h2)) i_186 (.I0(1'b0), .O(s_level_out_bus_d6[12])); LUT1 #( .INIT(2'h2)) i_187 (.I0(1'b0), .O(s_level_out_bus_d6[11])); LUT1 #( .INIT(2'h2)) i_188 (.I0(1'b0), .O(s_level_out_bus_d6[10])); LUT1 #( .INIT(2'h2)) i_189 (.I0(1'b0), .O(s_level_out_bus_d6[9])); LUT1 #( .INIT(2'h2)) i_19 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[19])); LUT1 #( .INIT(2'h2)) i_190 (.I0(1'b0), .O(s_level_out_bus_d6[8])); LUT1 #( .INIT(2'h2)) i_191 (.I0(1'b0), .O(s_level_out_bus_d6[7])); LUT1 #( .INIT(2'h2)) i_192 (.I0(1'b0), .O(s_level_out_bus_d6[6])); LUT1 #( .INIT(2'h2)) i_193 (.I0(1'b0), .O(s_level_out_bus_d6[5])); LUT1 #( .INIT(2'h2)) i_194 (.I0(1'b0), .O(s_level_out_bus_d6[4])); LUT1 #( .INIT(2'h2)) i_195 (.I0(1'b0), .O(s_level_out_bus_d6[3])); LUT1 #( .INIT(2'h2)) i_196 (.I0(1'b0), .O(s_level_out_bus_d6[2])); LUT1 #( .INIT(2'h2)) i_197 (.I0(1'b0), .O(s_level_out_bus_d6[1])); LUT1 #( .INIT(2'h2)) i_198 (.I0(1'b0), .O(s_level_out_bus_d6[0])); LUT1 #( .INIT(2'h2)) i_2 (.I0(1'b0), .O(s_out_d3)); LUT1 #( .INIT(2'h2)) i_20 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[18])); LUT1 #( .INIT(2'h2)) i_21 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[17])); LUT1 #( .INIT(2'h2)) i_22 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[16])); LUT1 #( .INIT(2'h2)) i_23 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[15])); LUT1 #( .INIT(2'h2)) i_24 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[14])); LUT1 #( .INIT(2'h2)) i_25 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[13])); LUT1 #( .INIT(2'h2)) i_26 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[12])); LUT1 #( .INIT(2'h2)) i_27 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[11])); LUT1 #( .INIT(2'h2)) i_28 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[10])); LUT1 #( .INIT(2'h2)) i_29 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[9])); LUT1 #( .INIT(2'h2)) i_3 (.I0(1'b0), .O(s_out_d4)); LUT1 #( .INIT(2'h2)) i_30 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[8])); LUT1 #( .INIT(2'h2)) i_31 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[7])); LUT1 #( .INIT(2'h2)) i_32 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[6])); LUT1 #( .INIT(2'h2)) i_33 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[5])); LUT1 #( .INIT(2'h2)) i_34 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[4])); LUT1 #( .INIT(2'h2)) i_35 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[3])); LUT1 #( .INIT(2'h2)) i_36 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[2])); LUT1 #( .INIT(2'h2)) i_37 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[1])); LUT1 #( .INIT(2'h2)) i_38 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[0])); LUT1 #( .INIT(2'h2)) i_39 (.I0(1'b0), .O(s_level_out_bus_d2[31])); LUT1 #( .INIT(2'h2)) i_4 (.I0(1'b0), .O(s_out_d5)); LUT1 #( .INIT(2'h2)) i_40 (.I0(1'b0), .O(s_level_out_bus_d2[30])); LUT1 #( .INIT(2'h2)) i_41 (.I0(1'b0), .O(s_level_out_bus_d2[29])); LUT1 #( .INIT(2'h2)) i_42 (.I0(1'b0), .O(s_level_out_bus_d2[28])); LUT1 #( .INIT(2'h2)) i_43 (.I0(1'b0), .O(s_level_out_bus_d2[27])); LUT1 #( .INIT(2'h2)) i_44 (.I0(1'b0), .O(s_level_out_bus_d2[26])); LUT1 #( .INIT(2'h2)) i_45 (.I0(1'b0), .O(s_level_out_bus_d2[25])); LUT1 #( .INIT(2'h2)) i_46 (.I0(1'b0), .O(s_level_out_bus_d2[24])); LUT1 #( .INIT(2'h2)) i_47 (.I0(1'b0), .O(s_level_out_bus_d2[23])); LUT1 #( .INIT(2'h2)) i_48 (.I0(1'b0), .O(s_level_out_bus_d2[22])); LUT1 #( .INIT(2'h2)) i_49 (.I0(1'b0), .O(s_level_out_bus_d2[21])); LUT1 #( .INIT(2'h2)) i_5 (.I0(1'b0), .O(s_out_d6)); LUT1 #( .INIT(2'h2)) i_50 (.I0(1'b0), .O(s_level_out_bus_d2[20])); LUT1 #( .INIT(2'h2)) i_51 (.I0(1'b0), .O(s_level_out_bus_d2[19])); LUT1 #( .INIT(2'h2)) i_52 (.I0(1'b0), .O(s_level_out_bus_d2[18])); LUT1 #( .INIT(2'h2)) i_53 (.I0(1'b0), .O(s_level_out_bus_d2[17])); LUT1 #( .INIT(2'h2)) i_54 (.I0(1'b0), .O(s_level_out_bus_d2[16])); LUT1 #( .INIT(2'h2)) i_55 (.I0(1'b0), .O(s_level_out_bus_d2[15])); LUT1 #( .INIT(2'h2)) i_56 (.I0(1'b0), .O(s_level_out_bus_d2[14])); LUT1 #( .INIT(2'h2)) i_57 (.I0(1'b0), .O(s_level_out_bus_d2[13])); LUT1 #( .INIT(2'h2)) i_58 (.I0(1'b0), .O(s_level_out_bus_d2[12])); LUT1 #( .INIT(2'h2)) i_59 (.I0(1'b0), .O(s_level_out_bus_d2[11])); LUT1 #( .INIT(2'h2)) i_6 (.I0(1'b0), .O(s_out_d7)); LUT1 #( .INIT(2'h2)) i_60 (.I0(1'b0), .O(s_level_out_bus_d2[10])); LUT1 #( .INIT(2'h2)) i_61 (.I0(1'b0), .O(s_level_out_bus_d2[9])); LUT1 #( .INIT(2'h2)) i_62 (.I0(1'b0), .O(s_level_out_bus_d2[8])); LUT1 #( .INIT(2'h2)) i_63 (.I0(1'b0), .O(s_level_out_bus_d2[7])); LUT1 #( .INIT(2'h2)) i_64 (.I0(1'b0), .O(s_level_out_bus_d2[6])); LUT1 #( .INIT(2'h2)) i_65 (.I0(1'b0), .O(s_level_out_bus_d2[5])); LUT1 #( .INIT(2'h2)) i_66 (.I0(1'b0), .O(s_level_out_bus_d2[4])); LUT1 #( .INIT(2'h2)) i_67 (.I0(1'b0), .O(s_level_out_bus_d2[3])); LUT1 #( .INIT(2'h2)) i_68 (.I0(1'b0), .O(s_level_out_bus_d2[2])); LUT1 #( .INIT(2'h2)) i_69 (.I0(1'b0), .O(s_level_out_bus_d2[1])); LUT1 #( .INIT(2'h2)) i_7 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[31])); LUT1 #( .INIT(2'h2)) i_70 (.I0(1'b0), .O(s_level_out_bus_d2[0])); LUT1 #( .INIT(2'h2)) i_71 (.I0(1'b0), .O(s_level_out_bus_d3[31])); LUT1 #( .INIT(2'h2)) i_72 (.I0(1'b0), .O(s_level_out_bus_d3[30])); LUT1 #( .INIT(2'h2)) i_73 (.I0(1'b0), .O(s_level_out_bus_d3[29])); LUT1 #( .INIT(2'h2)) i_74 (.I0(1'b0), .O(s_level_out_bus_d3[28])); LUT1 #( .INIT(2'h2)) i_75 (.I0(1'b0), .O(s_level_out_bus_d3[27])); LUT1 #( .INIT(2'h2)) i_76 (.I0(1'b0), .O(s_level_out_bus_d3[26])); LUT1 #( .INIT(2'h2)) i_77 (.I0(1'b0), .O(s_level_out_bus_d3[25])); LUT1 #( .INIT(2'h2)) i_78 (.I0(1'b0), .O(s_level_out_bus_d3[24])); LUT1 #( .INIT(2'h2)) i_79 (.I0(1'b0), .O(s_level_out_bus_d3[23])); LUT1 #( .INIT(2'h2)) i_8 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[30])); LUT1 #( .INIT(2'h2)) i_80 (.I0(1'b0), .O(s_level_out_bus_d3[22])); LUT1 #( .INIT(2'h2)) i_81 (.I0(1'b0), .O(s_level_out_bus_d3[21])); LUT1 #( .INIT(2'h2)) i_82 (.I0(1'b0), .O(s_level_out_bus_d3[20])); LUT1 #( .INIT(2'h2)) i_83 (.I0(1'b0), .O(s_level_out_bus_d3[19])); LUT1 #( .INIT(2'h2)) i_84 (.I0(1'b0), .O(s_level_out_bus_d3[18])); LUT1 #( .INIT(2'h2)) i_85 (.I0(1'b0), .O(s_level_out_bus_d3[17])); LUT1 #( .INIT(2'h2)) i_86 (.I0(1'b0), .O(s_level_out_bus_d3[16])); LUT1 #( .INIT(2'h2)) i_87 (.I0(1'b0), .O(s_level_out_bus_d3[15])); LUT1 #( .INIT(2'h2)) i_88 (.I0(1'b0), .O(s_level_out_bus_d3[14])); LUT1 #( .INIT(2'h2)) i_89 (.I0(1'b0), .O(s_level_out_bus_d3[13])); LUT1 #( .INIT(2'h2)) i_9 (.I0(1'b0), .O(s_level_out_bus_d1_aurora_64b66b_0_cdc_to[29])); LUT1 #( .INIT(2'h2)) i_90 (.I0(1'b0), .O(s_level_out_bus_d3[12])); LUT1 #( .INIT(2'h2)) i_91 (.I0(1'b0), .O(s_level_out_bus_d3[11])); LUT1 #( .INIT(2'h2)) i_92 (.I0(1'b0), .O(s_level_out_bus_d3[10])); LUT1 #( .INIT(2'h2)) i_93 (.I0(1'b0), .O(s_level_out_bus_d3[9])); LUT1 #( .INIT(2'h2)) i_94 (.I0(1'b0), .O(s_level_out_bus_d3[8])); LUT1 #( .INIT(2'h2)) i_95 (.I0(1'b0), .O(s_level_out_bus_d3[7])); LUT1 #( .INIT(2'h2)) i_96 (.I0(1'b0), .O(s_level_out_bus_d3[6])); LUT1 #( .INIT(2'h2)) i_97 (.I0(1'b0), .O(s_level_out_bus_d3[5])); LUT1 #( .INIT(2'h2)) i_98 (.I0(1'b0), .O(s_level_out_bus_d3[4])); LUT1 #( .INIT(2'h2)) i_99 (.I0(1'b0), .O(s_level_out_bus_d3[3])); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d1_aurora_64b66b_0_cdc_to_reg (.C(s_level_out_d5_reg_0), .CE(1'b1), .D(overflow), .Q(s_level_out_d1_aurora_64b66b_0_cdc_to), .R(cbcc_fifo_reset_rd_clk)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d2_reg (.C(s_level_out_d5_reg_0), .CE(1'b1), .D(s_level_out_d1_aurora_64b66b_0_cdc_to), .Q(s_level_out_d2), .R(cbcc_fifo_reset_rd_clk)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d3_reg (.C(s_level_out_d5_reg_0), .CE(1'b1), .D(s_level_out_d2), .Q(s_level_out_d3), .R(cbcc_fifo_reset_rd_clk)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d4_reg (.C(s_level_out_d5_reg_0), .CE(1'b1), .D(s_level_out_d3), .Q(s_level_out_d4), .R(cbcc_fifo_reset_rd_clk)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d5_reg (.C(s_level_out_d5_reg_0), .CE(1'b1), .D(s_level_out_d4), .Q(s_level_out_d5), .R(cbcc_fifo_reset_rd_clk)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE s_level_out_d6_reg (.C(s_level_out_d5_reg_0), .CE(1'b1), .D(s_level_out_d5), .Q(s_level_out_d6), .R(cbcc_fifo_reset_rd_clk)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_common_logic_cbcc" *) module aurora_64b66b_0_aurora_64b66b_0_common_logic_cbcc (cb_bit_err_out, in0, master_do_rd_en_i, all_vld_btf_flag_i, SR, out, gtwiz_userclk_rx_usrclk_out, START_CB_WRITES_OUT, cbcc_fifo_reset_rd_clk, master_do_rd_en_out_reg_0, master_do_rd_en_out_reg_1, ANY_VLD_BTF_FLAG); output cb_bit_err_out; output in0; output master_do_rd_en_i; output all_vld_btf_flag_i; input [0:0]SR; input out; input gtwiz_userclk_rx_usrclk_out; input START_CB_WRITES_OUT; input cbcc_fifo_reset_rd_clk; input master_do_rd_en_out_reg_0; input master_do_rd_en_out_reg_1; input ANY_VLD_BTF_FLAG; wire ANY_VLD_BTF_FLAG; wire [0:0]SR; wire START_CB_WRITES_OUT; wire all_vld_btf_flag_i; wire cb_bit_err_out; wire cbcc_fifo_reset_rd_clk; wire gtwiz_userclk_rx_usrclk_out; wire in0; wire master_do_rd_en_i; wire master_do_rd_en_out_reg_0; wire master_do_rd_en_out_reg_1; wire out; wire second_cb_write_failed; FDRE all_start_cb_writes_out_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(START_CB_WRITES_OUT), .Q(in0), .R(SR)); FDRE all_vld_btf_out_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(ANY_VLD_BTF_FLAG), .Q(all_vld_btf_flag_i), .R(SR)); FDRE cb_bit_err_out_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(second_cb_write_failed), .Q(cb_bit_err_out), .R(SR)); FDRE master_do_rd_en_out_reg (.C(master_do_rd_en_out_reg_1), .CE(1'b1), .D(master_do_rd_en_out_reg_0), .Q(master_do_rd_en_i), .R(cbcc_fifo_reset_rd_clk)); FDRE #( .INIT(1'b0)) second_cb_write_failed_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(out), .Q(second_cb_write_failed), .R(SR)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_common_reset_cbcc" *) module aurora_64b66b_0_aurora_64b66b_0_common_reset_cbcc (stg5_reg, srst, stg9_reg, cbcc_reset_cbstg2_rd_clk, cbcc_fifo_reset_rd_clk, SR, stg1_aurora_64b66b_0_cdc_to_reg, stg5_reg_0, gtwiz_userclk_rx_usrclk_out, cb_bit_err_out); output stg5_reg; output srst; output [0:0]stg9_reg; output cbcc_reset_cbstg2_rd_clk; output cbcc_fifo_reset_rd_clk; output [0:0]SR; input [0:0]stg1_aurora_64b66b_0_cdc_to_reg; input stg5_reg_0; input gtwiz_userclk_rx_usrclk_out; input cb_bit_err_out; wire [0:0]SR; wire [3:0]cb_bit_err_ext_cnt; wire \cb_bit_err_ext_cnt[0]_i_1_n_0 ; wire \cb_bit_err_ext_cnt[1]_i_1_n_0 ; wire \cb_bit_err_ext_cnt[2]_i_1_n_0 ; wire \cb_bit_err_ext_cnt[3]_i_1_n_0 ; wire cb_bit_err_out; wire cbc_rd_if_reset; wire cbc_rd_if_reset_i_1_n_0; wire cbc_wr_if_reset; wire cbc_wr_if_reset_i_1_n_0; wire cbcc_data_srst0; wire cbcc_fifo_reset_rd_clk; wire cbcc_fifo_reset_to_fifo_rd_clk; wire cbcc_fifo_reset_to_fifo_rd_clk_dlyd; wire cbcc_fifo_reset_to_fifo_wr_clk_dlyd; wire cbcc_reset_cbstg2_rd_clk; wire dbg_extend_srst0; wire [3:0]dbg_extend_srst_reg; wire dbg_srst_assert; wire dbg_srst_assert0; wire fifo_reset_comb; wire fifo_reset_comb_read_clk; wire fifo_reset_comb_user_clk; wire fifo_reset_comb_user_clk_int; wire fifo_reset_comb_user_clk_int_22q; wire fifo_reset_rd; wire gtwiz_userclk_rx_usrclk_out; wire [3:0]p_0_in__5; wire rd_stg1; wire reset_cbcc_comb; wire srst; wire [0:0]stg1_aurora_64b66b_0_cdc_to_reg; wire stg5_reg; wire stg5_reg_0; wire [0:0]stg9_reg; wire u_cdc_chan_bond_reset_n_0; wire u_rst_sync_reset_rd_clk_n_0; wire u_rst_sync_reset_wr_clk_n_0; wire u_rst_sync_rst_cbcc_rd_clk_n_0; wire u_rst_sync_rst_cbcc_rd_clk_n_1; (* SOFT_HLUTNM = "soft_lutpair54" *) LUT5 #( .INIT(32'hFFFF5554)) \cb_bit_err_ext_cnt[0]_i_1 (.I0(cb_bit_err_ext_cnt[0]), .I1(cb_bit_err_ext_cnt[2]), .I2(cb_bit_err_ext_cnt[3]), .I3(cb_bit_err_ext_cnt[1]), .I4(cb_bit_err_out), .O(\cb_bit_err_ext_cnt[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair54" *) LUT5 #( .INIT(32'hFFFF9998)) \cb_bit_err_ext_cnt[1]_i_1 (.I0(cb_bit_err_ext_cnt[0]), .I1(cb_bit_err_ext_cnt[1]), .I2(cb_bit_err_ext_cnt[2]), .I3(cb_bit_err_ext_cnt[3]), .I4(cb_bit_err_out), .O(\cb_bit_err_ext_cnt[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair53" *) LUT5 #( .INIT(32'hFFFFE1E0)) \cb_bit_err_ext_cnt[2]_i_1 (.I0(cb_bit_err_ext_cnt[1]), .I1(cb_bit_err_ext_cnt[0]), .I2(cb_bit_err_ext_cnt[2]), .I3(cb_bit_err_ext_cnt[3]), .I4(cb_bit_err_out), .O(\cb_bit_err_ext_cnt[2]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair53" *) LUT5 #( .INIT(32'hFFFFFE00)) \cb_bit_err_ext_cnt[3]_i_1 (.I0(cb_bit_err_ext_cnt[0]), .I1(cb_bit_err_ext_cnt[1]), .I2(cb_bit_err_ext_cnt[2]), .I3(cb_bit_err_ext_cnt[3]), .I4(cb_bit_err_out), .O(\cb_bit_err_ext_cnt[3]_i_1_n_0 )); FDRE \cb_bit_err_ext_cnt_reg[0] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\cb_bit_err_ext_cnt[0]_i_1_n_0 ), .Q(cb_bit_err_ext_cnt[0]), .R(stg1_aurora_64b66b_0_cdc_to_reg)); FDRE \cb_bit_err_ext_cnt_reg[1] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\cb_bit_err_ext_cnt[1]_i_1_n_0 ), .Q(cb_bit_err_ext_cnt[1]), .R(stg1_aurora_64b66b_0_cdc_to_reg)); FDRE \cb_bit_err_ext_cnt_reg[2] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\cb_bit_err_ext_cnt[2]_i_1_n_0 ), .Q(cb_bit_err_ext_cnt[2]), .R(stg1_aurora_64b66b_0_cdc_to_reg)); FDRE \cb_bit_err_ext_cnt_reg[3] (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(\cb_bit_err_ext_cnt[3]_i_1_n_0 ), .Q(cb_bit_err_ext_cnt[3]), .R(stg1_aurora_64b66b_0_cdc_to_reg)); LUT4 #( .INIT(16'hFFD0)) cbc_rd_if_reset_i_1 (.I0(cbcc_fifo_reset_to_fifo_rd_clk_dlyd), .I1(cbcc_fifo_reset_to_fifo_rd_clk), .I2(cbc_rd_if_reset), .I3(fifo_reset_comb_read_clk), .O(cbc_rd_if_reset_i_1_n_0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) cbc_rd_if_reset_reg (.C(stg5_reg_0), .CE(1'b1), .D(cbc_rd_if_reset_i_1_n_0), .Q(cbc_rd_if_reset), .R(1'b0)); LUT4 #( .INIT(16'hFFD0)) cbc_wr_if_reset_i_1 (.I0(cbcc_fifo_reset_to_fifo_wr_clk_dlyd), .I1(stg9_reg), .I2(cbc_wr_if_reset), .I3(fifo_reset_comb_user_clk), .O(cbc_wr_if_reset_i_1_n_0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) cbc_wr_if_reset_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(cbc_wr_if_reset_i_1_n_0), .Q(cbc_wr_if_reset), .R(1'b0)); LUT5 #( .INIT(32'hBBBBBFFF)) cbcc_data_srst_i_1 (.I0(dbg_srst_assert), .I1(dbg_extend_srst_reg[3]), .I2(dbg_extend_srst_reg[0]), .I3(dbg_extend_srst_reg[1]), .I4(dbg_extend_srst_reg[2]), .O(cbcc_data_srst0)); FDRE #( .INIT(1'b0)) cbcc_data_srst_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(cbcc_data_srst0), .Q(srst), .R(1'b0)); FDRE #( .INIT(1'b0)) cbcc_fifo_reset_rd_clk_reg (.C(stg5_reg_0), .CE(1'b1), .D(u_rst_sync_reset_rd_clk_n_0), .Q(cbcc_fifo_reset_rd_clk), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) cbcc_fifo_reset_to_fifo_rd_clk_dlyd_reg (.C(stg5_reg_0), .CE(1'b1), .D(cbcc_fifo_reset_to_fifo_rd_clk), .Q(cbcc_fifo_reset_to_fifo_rd_clk_dlyd), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) cbcc_fifo_reset_to_fifo_wr_clk_dlyd_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(stg9_reg), .Q(cbcc_fifo_reset_to_fifo_wr_clk_dlyd), .R(1'b0)); FDRE #( .INIT(1'b0)) cbcc_fifo_reset_wr_clk_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(u_rst_sync_reset_wr_clk_n_0), .Q(SR), .R(1'b0)); (* shift_extract = "{no}" *) FDRE cbcc_reset_cbstg2_rd_clk_reg (.C(stg5_reg_0), .CE(1'b1), .D(u_rst_sync_rst_cbcc_rd_clk_n_1), .Q(cbcc_reset_cbstg2_rd_clk), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair56" *) LUT1 #( .INIT(2'h1)) \dbg_extend_srst[0]_i_1 (.I0(dbg_extend_srst_reg[0]), .O(p_0_in__5[0])); (* SOFT_HLUTNM = "soft_lutpair56" *) LUT2 #( .INIT(4'h6)) \dbg_extend_srst[1]_i_1 (.I0(dbg_extend_srst_reg[0]), .I1(dbg_extend_srst_reg[1]), .O(p_0_in__5[1])); (* SOFT_HLUTNM = "soft_lutpair55" *) LUT3 #( .INIT(8'h6A)) \dbg_extend_srst[2]_i_1 (.I0(dbg_extend_srst_reg[2]), .I1(dbg_extend_srst_reg[0]), .I2(dbg_extend_srst_reg[1]), .O(p_0_in__5[2])); LUT4 #( .INIT(16'h15FF)) \dbg_extend_srst[3]_i_1 (.I0(dbg_extend_srst_reg[2]), .I1(dbg_extend_srst_reg[1]), .I2(dbg_extend_srst_reg[0]), .I3(dbg_extend_srst_reg[3]), .O(dbg_extend_srst0)); (* SOFT_HLUTNM = "soft_lutpair55" *) LUT4 #( .INIT(16'h7F80)) \dbg_extend_srst[3]_i_2 (.I0(dbg_extend_srst_reg[1]), .I1(dbg_extend_srst_reg[0]), .I2(dbg_extend_srst_reg[2]), .I3(dbg_extend_srst_reg[3]), .O(p_0_in__5[3])); FDRE #( .INIT(1'b1)) \dbg_extend_srst_reg[0] (.C(gtwiz_userclk_rx_usrclk_out), .CE(dbg_extend_srst0), .D(p_0_in__5[0]), .Q(dbg_extend_srst_reg[0]), .R(dbg_srst_assert)); FDRE #( .INIT(1'b1)) \dbg_extend_srst_reg[1] (.C(gtwiz_userclk_rx_usrclk_out), .CE(dbg_extend_srst0), .D(p_0_in__5[1]), .Q(dbg_extend_srst_reg[1]), .R(dbg_srst_assert)); FDRE #( .INIT(1'b0)) \dbg_extend_srst_reg[2] (.C(gtwiz_userclk_rx_usrclk_out), .CE(dbg_extend_srst0), .D(p_0_in__5[2]), .Q(dbg_extend_srst_reg[2]), .R(dbg_srst_assert)); FDRE #( .INIT(1'b1)) \dbg_extend_srst_reg[3] (.C(gtwiz_userclk_rx_usrclk_out), .CE(dbg_extend_srst0), .D(p_0_in__5[3]), .Q(dbg_extend_srst_reg[3]), .R(dbg_srst_assert)); FDRE #( .INIT(1'b0)) dbg_srst_assert_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(dbg_srst_assert0), .Q(dbg_srst_assert), .R(1'b0)); FDRE #( .INIT(1'b1)) fifo_reset_comb_user_clk_int_22q_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(fifo_reset_comb_user_clk_int), .Q(fifo_reset_comb_user_clk_int_22q), .R(1'b0)); FDSE #( .INIT(1'b1)) fifo_reset_rd_reg (.C(stg5_reg_0), .CE(1'b1), .D(1'b0), .Q(fifo_reset_rd), .S(cbcc_reset_cbstg2_rd_clk)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) rd_stg1_reg (.C(stg5_reg_0), .CE(1'b1), .D(u_rst_sync_rst_cbcc_rd_clk_n_0), .Q(rd_stg1), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) reset_cbcc_comb_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(u_cdc_chan_bond_reset_n_0), .Q(reset_cbcc_comb), .R(1'b0)); aurora_64b66b_0_aurora_64b66b_0_cdc_sync__parameterized0_20 u_cdc_chan_bond_reset (.Q(cb_bit_err_ext_cnt), .\cb_bit_err_ext_cnt_reg[3] (u_cdc_chan_bond_reset_n_0), .gtwiz_userclk_rx_usrclk_out(gtwiz_userclk_rx_usrclk_out), .reset_cbcc_comb_reg(stg1_aurora_64b66b_0_cdc_to_reg)); aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized1_21 u_rst_sync_cbcc_fifo_reset_rd_clk (.in0(fifo_reset_comb_user_clk), .stg5_reg_0(fifo_reset_comb_read_clk), .stg5_reg_1(stg5_reg_0)); aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized1_22 u_rst_sync_cbcc_only_reset_rd_clk (.stg1_aurora_64b66b_0_cdc_to_reg_0(stg1_aurora_64b66b_0_cdc_to_reg), .stg3_reg_0(stg5_reg_0), .stg5_reg_0(stg5_reg)); aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized3 u_rst_sync_fifo_reset_comb_user_clk_in (.dbg_srst_assert0(dbg_srst_assert0), .dbg_srst_assert_reg(fifo_reset_comb_user_clk_int_22q), .fifo_reset_comb_user_clk_int(fifo_reset_comb_user_clk_int), .gtwiz_userclk_rx_usrclk_out(gtwiz_userclk_rx_usrclk_out), .in0(fifo_reset_comb_user_clk)); aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized2 u_rst_sync_fifo_reset_user_clk (.gtwiz_userclk_rx_usrclk_out(gtwiz_userclk_rx_usrclk_out), .in0(fifo_reset_comb), .stg11_reg_0(fifo_reset_comb_user_clk)); aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized1_23 u_rst_sync_r_sync3 (.gtwiz_userclk_rx_usrclk_out(gtwiz_userclk_rx_usrclk_out), .in0(fifo_reset_rd), .stg1_aurora_64b66b_0_cdc_to_reg_0(reset_cbcc_comb), .stg5_reg_0(fifo_reset_comb)); aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized1_24 u_rst_sync_reset_rd_clk (.in0(cbc_rd_if_reset), .stg3_reg_0(u_rst_sync_reset_rd_clk_n_0), .stg3_reg_1(stg5_reg_0)); aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized5 u_rst_sync_reset_to_fifo_rd_clk (.cbcc_fifo_reset_to_fifo_rd_clk(cbcc_fifo_reset_to_fifo_rd_clk), .stg1_aurora_64b66b_0_cdc_to_reg_0(fifo_reset_comb_read_clk), .stg31_reg_0(stg5_reg_0)); aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized4 u_rst_sync_reset_to_fifo_wr_clk (.gtwiz_userclk_rx_usrclk_out(gtwiz_userclk_rx_usrclk_out), .stg1_aurora_64b66b_0_cdc_to_reg_0(fifo_reset_comb_user_clk_int_22q), .stg9_reg_0(stg9_reg)); aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized1_25 u_rst_sync_reset_wr_clk (.gtwiz_userclk_rx_usrclk_out(gtwiz_userclk_rx_usrclk_out), .in0(cbc_wr_if_reset), .stg3_reg_0(u_rst_sync_reset_wr_clk_n_0)); aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized1_26 u_rst_sync_rst_cbcc_rd_clk (.rd_stg1(rd_stg1), .rd_stg1_reg(u_rst_sync_rst_cbcc_rd_clk_n_1), .stg1_aurora_64b66b_0_cdc_to_reg_0(reset_cbcc_comb), .stg5_reg_0(u_rst_sync_rst_cbcc_rd_clk_n_0), .stg5_reg_1(stg5_reg_0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_core" *) module aurora_64b66b_0_aurora_64b66b_0_core (link_reset_out, lane_up_flop_i, SYSTEM_RESET_reg, gt0_drpdo, gt0_drprdy, txn, txp, gt_powergood, tx_out_clk, gt_pll_lock, CHANNEL_UP_RX_IF_reg, hard_err, soft_err, m_axi_rx_tvalid, bufg_gt_clr_out, s_axi_tx_tready, m_axi_rx_tdata, power_down, sysreset_from_support, TX_PE_DATA_V_reg, stg1_aurora_64b66b_0_cdc_to_reg, gt0_drpaddr, init_clk, gt0_drpdi, gt0_drpen, gt0_drpwe, rxn, rxp, refclk1_in, loopback, gt_rxcdrovrden_in, sync_clk_out, s_axi_tx_tvalid, s_axi_tx_tdata, mmcm_not_locked_out2, lopt, lopt_1, lopt_2, lopt_3); output link_reset_out; output lane_up_flop_i; output SYSTEM_RESET_reg; output [15:0]gt0_drpdo; output gt0_drprdy; output txn; output txp; output [0:0]gt_powergood; output tx_out_clk; output gt_pll_lock; output CHANNEL_UP_RX_IF_reg; output hard_err; output soft_err; output m_axi_rx_tvalid; output bufg_gt_clr_out; output s_axi_tx_tready; output [0:63]m_axi_rx_tdata; input power_down; input sysreset_from_support; input TX_PE_DATA_V_reg; input stg1_aurora_64b66b_0_cdc_to_reg; input [8:0]gt0_drpaddr; input init_clk; input [15:0]gt0_drpdi; input gt0_drpen; input gt0_drpwe; input rxn; input rxp; input refclk1_in; input [2:0]loopback; input gt_rxcdrovrden_in; input sync_clk_out; input s_axi_tx_tvalid; input [0:63]s_axi_tx_tdata; input mmcm_not_locked_out2; input lopt; input lopt_1; output lopt_2; output lopt_3; wire CHANNEL_UP_RX_IF_reg; wire RX_IDLE; wire [0:63]RX_PE_DATA; wire SYSTEM_RESET_reg; wire TXDATAVALID_IN; wire [1:0]TXHEADER_IN; wire [0:63]TX_PE_DATA; wire TX_PE_DATA_V_reg; wire aurora_64b66b_0_wrapper_i_n_100; wire aurora_64b66b_0_wrapper_i_n_102; wire aurora_64b66b_0_wrapper_i_n_103; wire aurora_64b66b_0_wrapper_i_n_104; wire aurora_64b66b_0_wrapper_i_n_105; wire aurora_64b66b_0_wrapper_i_n_106; wire aurora_64b66b_0_wrapper_i_n_107; wire aurora_64b66b_0_wrapper_i_n_21; wire aurora_64b66b_0_wrapper_i_n_22; wire aurora_64b66b_0_wrapper_i_n_23; wire aurora_64b66b_0_wrapper_i_n_24; wire aurora_64b66b_0_wrapper_i_n_25; wire aurora_64b66b_0_wrapper_i_n_26; wire aurora_64b66b_0_wrapper_i_n_27; wire aurora_64b66b_0_wrapper_i_n_28; wire aurora_64b66b_0_wrapper_i_n_29; wire aurora_64b66b_0_wrapper_i_n_30; wire aurora_64b66b_0_wrapper_i_n_31; wire aurora_64b66b_0_wrapper_i_n_32; wire aurora_64b66b_0_wrapper_i_n_33; wire aurora_64b66b_0_wrapper_i_n_34; wire aurora_64b66b_0_wrapper_i_n_35; wire aurora_64b66b_0_wrapper_i_n_36; wire aurora_64b66b_0_wrapper_i_n_37; wire aurora_64b66b_0_wrapper_i_n_38; wire aurora_64b66b_0_wrapper_i_n_39; wire aurora_64b66b_0_wrapper_i_n_40; wire aurora_64b66b_0_wrapper_i_n_41; wire aurora_64b66b_0_wrapper_i_n_42; wire aurora_64b66b_0_wrapper_i_n_43; wire aurora_64b66b_0_wrapper_i_n_44; wire aurora_64b66b_0_wrapper_i_n_45; wire aurora_64b66b_0_wrapper_i_n_46; wire aurora_64b66b_0_wrapper_i_n_47; wire aurora_64b66b_0_wrapper_i_n_48; wire aurora_64b66b_0_wrapper_i_n_49; wire aurora_64b66b_0_wrapper_i_n_50; wire aurora_64b66b_0_wrapper_i_n_51; wire aurora_64b66b_0_wrapper_i_n_52; wire aurora_64b66b_0_wrapper_i_n_53; wire aurora_64b66b_0_wrapper_i_n_54; wire aurora_64b66b_0_wrapper_i_n_55; wire aurora_64b66b_0_wrapper_i_n_56; wire aurora_64b66b_0_wrapper_i_n_57; wire aurora_64b66b_0_wrapper_i_n_58; wire aurora_64b66b_0_wrapper_i_n_59; wire aurora_64b66b_0_wrapper_i_n_60; wire aurora_64b66b_0_wrapper_i_n_61; wire aurora_64b66b_0_wrapper_i_n_62; wire aurora_64b66b_0_wrapper_i_n_63; wire aurora_64b66b_0_wrapper_i_n_64; wire aurora_64b66b_0_wrapper_i_n_65; wire aurora_64b66b_0_wrapper_i_n_66; wire aurora_64b66b_0_wrapper_i_n_67; wire aurora_64b66b_0_wrapper_i_n_68; wire aurora_64b66b_0_wrapper_i_n_69; wire aurora_64b66b_0_wrapper_i_n_70; wire aurora_64b66b_0_wrapper_i_n_71; wire aurora_64b66b_0_wrapper_i_n_72; wire aurora_64b66b_0_wrapper_i_n_73; wire aurora_64b66b_0_wrapper_i_n_74; wire aurora_64b66b_0_wrapper_i_n_75; wire aurora_64b66b_0_wrapper_i_n_76; wire aurora_64b66b_0_wrapper_i_n_77; wire aurora_64b66b_0_wrapper_i_n_78; wire aurora_64b66b_0_wrapper_i_n_79; wire aurora_64b66b_0_wrapper_i_n_80; wire aurora_64b66b_0_wrapper_i_n_81; wire aurora_64b66b_0_wrapper_i_n_82; wire aurora_64b66b_0_wrapper_i_n_83; wire aurora_64b66b_0_wrapper_i_n_84; wire aurora_64b66b_0_wrapper_i_n_85; wire aurora_64b66b_0_wrapper_i_n_86; wire aurora_64b66b_0_wrapper_i_n_92; wire aurora_64b66b_0_wrapper_i_n_94; wire aurora_64b66b_0_wrapper_i_n_96; wire aurora_64b66b_0_wrapper_i_n_98; wire aurora_lane_0_i_n_13; wire bufg_gt_clr_out; wire \channel_init_sm_i/reset_lanes_c ; wire channel_up_tx_if; wire check_polarity_i; wire core_reset_logic_i_n_3; wire do_cc_i; wire enable_err_detect_i; wire fsm_resetdone; wire gen_cc_i; wire gen_ch_bond_i; wire gen_na_idles_i; wire global_logic_i_n_11; wire global_logic_i_n_12; wire global_logic_i_n_6; wire global_logic_i_n_7; wire global_logic_i_n_9; wire [8:0]gt0_drpaddr; wire [15:0]gt0_drpdi; wire [15:0]gt0_drpdo; wire gt0_drpen; wire gt0_drprdy; wire gt0_drpwe; wire gt_pll_lock; wire [0:0]gt_powergood; wire gt_rxcdrovrden_in; wire hard_err; wire hard_err_i; wire illegal_btf_i; wire init_clk; wire \lane_init_sm_i/ready_r_reg0 ; wire \lane_init_sm_i/reset_count_r0 ; wire lane_up_flop_i; wire link_reset_out; wire [2:0]loopback; wire lopt; wire lopt_1; wire lopt_2; wire lopt_3; wire [0:63]m_axi_rx_tdata; wire m_axi_rx_tvalid; wire mmcm_not_locked_out2; wire power_down; wire refclk1_in; wire remote_ready_i; wire reset_lanes_i; wire rx_lossofsync_i; wire rx_neg_i; wire rx_pe_data_v_i; wire rx_polarity_i; wire \rx_stream_datapath_i/RX_D0 ; wire rxdatavalid_i; wire rxn; wire rxp; wire [0:63]s_axi_tx_tdata; wire s_axi_tx_tready; wire s_axi_tx_tvalid; wire \scrambler_64b66b_gtx0_i/p_153_in ; wire \scrambler_64b66b_gtx0_i/p_157_in ; wire \scrambler_64b66b_gtx0_i/p_161_in ; wire \scrambler_64b66b_gtx0_i/p_165_in ; wire \scrambler_64b66b_gtx0_i/p_169_in ; wire \scrambler_64b66b_gtx0_i/p_173_in ; wire \scrambler_64b66b_gtx0_i/tempData0 ; wire \scrambler_64b66b_gtx0_i/tempData012_out ; wire \scrambler_64b66b_gtx0_i/tempData016_out ; wire \scrambler_64b66b_gtx0_i/tempData020_out ; wire \scrambler_64b66b_gtx0_i/tempData04_out ; wire \scrambler_64b66b_gtx0_i/tempData08_out ; wire soft_err; wire stg1_aurora_64b66b_0_cdc_to_reg; wire \sym_gen_i/rst_pma_init_usrclk ; wire sync_clk_out; wire sysreset_from_support; wire [0:57]tx_data_i; wire tx_out_clk; wire tx_pe_data_v_i; wire tx_reset_i; wire \tx_stream_control_sm_i/R0 ; wire \tx_stream_control_sm_i/do_cc_r ; wire \tx_stream_control_sm_i/do_cc_r_reg0 ; wire \tx_stream_control_sm_i/extend_cc_r ; wire \tx_stream_control_sm_i/tx_dst_rdy_n_r0 ; wire tx_stream_i_n_4; wire tx_stream_i_n_5; wire tx_stream_i_n_6; wire txdatavalid_symgen_i; wire txn; wire txp; aurora_64b66b_0_aurora_64b66b_0_WRAPPER aurora_64b66b_0_wrapper_i (.D(TXHEADER_IN), .ILLEGAL_BTF_reg(aurora_64b66b_0_wrapper_i_n_96), .Q(do_cc_i), .RX_NEG_OUT_reg_0(rx_neg_i), .SR(SYSTEM_RESET_reg), .TXDATAVALID_IN(TXDATAVALID_IN), .bufg_gt_clr_out(bufg_gt_clr_out), .channel_up_tx_if(channel_up_tx_if), .do_cc_r(\tx_stream_control_sm_i/do_cc_r ), .dout({aurora_64b66b_0_wrapper_i_n_21,aurora_64b66b_0_wrapper_i_n_22,aurora_64b66b_0_wrapper_i_n_23,aurora_64b66b_0_wrapper_i_n_24,aurora_64b66b_0_wrapper_i_n_25,aurora_64b66b_0_wrapper_i_n_26,aurora_64b66b_0_wrapper_i_n_27,aurora_64b66b_0_wrapper_i_n_28,aurora_64b66b_0_wrapper_i_n_29,aurora_64b66b_0_wrapper_i_n_30,aurora_64b66b_0_wrapper_i_n_31,aurora_64b66b_0_wrapper_i_n_32,aurora_64b66b_0_wrapper_i_n_33,aurora_64b66b_0_wrapper_i_n_34,aurora_64b66b_0_wrapper_i_n_35,aurora_64b66b_0_wrapper_i_n_36,aurora_64b66b_0_wrapper_i_n_37,aurora_64b66b_0_wrapper_i_n_38,aurora_64b66b_0_wrapper_i_n_39,aurora_64b66b_0_wrapper_i_n_40,aurora_64b66b_0_wrapper_i_n_41,aurora_64b66b_0_wrapper_i_n_42,aurora_64b66b_0_wrapper_i_n_43,aurora_64b66b_0_wrapper_i_n_44,aurora_64b66b_0_wrapper_i_n_45,aurora_64b66b_0_wrapper_i_n_46,aurora_64b66b_0_wrapper_i_n_47,aurora_64b66b_0_wrapper_i_n_48,aurora_64b66b_0_wrapper_i_n_49,aurora_64b66b_0_wrapper_i_n_50,aurora_64b66b_0_wrapper_i_n_51,aurora_64b66b_0_wrapper_i_n_52,aurora_64b66b_0_wrapper_i_n_53,aurora_64b66b_0_wrapper_i_n_54,aurora_64b66b_0_wrapper_i_n_55,aurora_64b66b_0_wrapper_i_n_56,aurora_64b66b_0_wrapper_i_n_57,aurora_64b66b_0_wrapper_i_n_58,aurora_64b66b_0_wrapper_i_n_59,aurora_64b66b_0_wrapper_i_n_60,aurora_64b66b_0_wrapper_i_n_61,aurora_64b66b_0_wrapper_i_n_62,aurora_64b66b_0_wrapper_i_n_63,aurora_64b66b_0_wrapper_i_n_64,aurora_64b66b_0_wrapper_i_n_65,aurora_64b66b_0_wrapper_i_n_66,aurora_64b66b_0_wrapper_i_n_67,aurora_64b66b_0_wrapper_i_n_68,aurora_64b66b_0_wrapper_i_n_69,aurora_64b66b_0_wrapper_i_n_70,aurora_64b66b_0_wrapper_i_n_71,aurora_64b66b_0_wrapper_i_n_72,aurora_64b66b_0_wrapper_i_n_73,aurora_64b66b_0_wrapper_i_n_74,aurora_64b66b_0_wrapper_i_n_75,aurora_64b66b_0_wrapper_i_n_76,aurora_64b66b_0_wrapper_i_n_77,aurora_64b66b_0_wrapper_i_n_78,aurora_64b66b_0_wrapper_i_n_79,aurora_64b66b_0_wrapper_i_n_80,aurora_64b66b_0_wrapper_i_n_81,aurora_64b66b_0_wrapper_i_n_82,aurora_64b66b_0_wrapper_i_n_83,aurora_64b66b_0_wrapper_i_n_84,aurora_64b66b_0_wrapper_i_n_85,aurora_64b66b_0_wrapper_i_n_86}), .enable_err_detect_i(enable_err_detect_i), .extend_cc_r(\tx_stream_control_sm_i/extend_cc_r ), .gt0_drpaddr(gt0_drpaddr), .gt0_drpdi(gt0_drpdi), .gt0_drpdo(gt0_drpdo), .gt0_drpen(gt0_drpen), .gt0_drprdy(gt0_drprdy), .gt0_drpwe(gt0_drpwe), .gt_pll_lock(gt_pll_lock), .gt_powergood(gt_powergood), .gt_rxcdrovrden_in(gt_rxcdrovrden_in), .hard_err_usr_reg_0(CHANNEL_UP_RX_IF_reg), .hold_reg_reg(aurora_64b66b_0_wrapper_i_n_100), .illegal_btf_i(illegal_btf_i), .in0(check_polarity_i), .init_clk(init_clk), .link_reset_out(link_reset_out), .loopback(loopback), .lopt(lopt), .lopt_1(lopt_1), .lopt_2(lopt_2), .lopt_3(lopt_3), .mmcm_not_locked_out2(mmcm_not_locked_out2), .refclk1_in(refclk1_in), .rst_in_out_reg(stg1_aurora_64b66b_0_cdc_to_reg), .rst_pma_init_usrclk(\sym_gen_i/rst_pma_init_usrclk ), .rx_lossofsync_i(rx_lossofsync_i), .rxdatavalid_i(rxdatavalid_i), .rxn(rxn), .rxp(rxp), .s_level_out_d1_aurora_64b66b_0_cdc_to_reg(rx_polarity_i), .scrambler({aurora_64b66b_0_wrapper_i_n_102,aurora_64b66b_0_wrapper_i_n_103,aurora_64b66b_0_wrapper_i_n_104,aurora_64b66b_0_wrapper_i_n_105,aurora_64b66b_0_wrapper_i_n_106,aurora_64b66b_0_wrapper_i_n_107,\scrambler_64b66b_gtx0_i/p_173_in ,\scrambler_64b66b_gtx0_i/p_169_in ,\scrambler_64b66b_gtx0_i/p_165_in ,\scrambler_64b66b_gtx0_i/p_161_in ,\scrambler_64b66b_gtx0_i/p_157_in ,\scrambler_64b66b_gtx0_i/p_153_in }), .stg3_reg(fsm_resetdone), .stg3_reg_0(TX_PE_DATA_V_reg), .sync_clk_out(sync_clk_out), .tempData({\scrambler_64b66b_gtx0_i/tempData020_out ,\scrambler_64b66b_gtx0_i/tempData016_out ,\scrambler_64b66b_gtx0_i/tempData012_out ,\scrambler_64b66b_gtx0_i/tempData08_out ,\scrambler_64b66b_gtx0_i/tempData04_out ,\scrambler_64b66b_gtx0_i/tempData0 }), .tx_data_i({tx_data_i[0],tx_data_i[1],tx_data_i[2],tx_data_i[3],tx_data_i[4],tx_data_i[5],tx_data_i[6],tx_data_i[7],tx_data_i[8],tx_data_i[9],tx_data_i[10],tx_data_i[11],tx_data_i[12],tx_data_i[13],tx_data_i[14],tx_data_i[15],tx_data_i[16],tx_data_i[17],tx_data_i[18],tx_data_i[19],tx_data_i[20],tx_data_i[21],tx_data_i[22],tx_data_i[23],tx_data_i[24],tx_data_i[25],tx_data_i[26],tx_data_i[27],tx_data_i[28],tx_data_i[29],tx_data_i[30],tx_data_i[31],tx_data_i[32],tx_data_i[33],tx_data_i[34],tx_data_i[35],tx_data_i[36],tx_data_i[37],tx_data_i[38],tx_data_i[39],tx_data_i[40],tx_data_i[41],tx_data_i[42],tx_data_i[43],tx_data_i[44],tx_data_i[45],tx_data_i[46],tx_data_i[47],tx_data_i[48],tx_data_i[49],tx_data_i[50],tx_data_i[51],tx_data_i[52],tx_data_i[53],tx_data_i[54],tx_data_i[55],tx_data_i[56],tx_data_i[57]}), .tx_dst_rdy_n_r0(\tx_stream_control_sm_i/tx_dst_rdy_n_r0 ), .tx_out_clk(tx_out_clk), .tx_reset_i(tx_reset_i), .txdatavalid_symgen_i(txdatavalid_symgen_i), .txn(txn), .txp(txp), .\txseq_counter_i_reg[0]_0 (aurora_64b66b_0_wrapper_i_n_92), .\txseq_counter_i_reg[1]_0 (aurora_64b66b_0_wrapper_i_n_94), .wr_err_rd_clk_sync_reg(aurora_64b66b_0_wrapper_i_n_98)); aurora_64b66b_0_aurora_64b66b_0_AURORA_LANE aurora_lane_0_i (.D(TXHEADER_IN), .HARD_ERR_reg(aurora_64b66b_0_wrapper_i_n_98), .Q({TX_PE_DATA[0],TX_PE_DATA[1],TX_PE_DATA[2],TX_PE_DATA[3],TX_PE_DATA[4],TX_PE_DATA[5],TX_PE_DATA[6],TX_PE_DATA[7],TX_PE_DATA[8],TX_PE_DATA[9],TX_PE_DATA[10],TX_PE_DATA[11],TX_PE_DATA[12],TX_PE_DATA[13],TX_PE_DATA[14],TX_PE_DATA[15],TX_PE_DATA[16],TX_PE_DATA[17],TX_PE_DATA[18],TX_PE_DATA[19],TX_PE_DATA[20],TX_PE_DATA[21],TX_PE_DATA[22],TX_PE_DATA[23],TX_PE_DATA[24],TX_PE_DATA[25],TX_PE_DATA[26],TX_PE_DATA[27],TX_PE_DATA[28],TX_PE_DATA[29],TX_PE_DATA[30],TX_PE_DATA[31],TX_PE_DATA[32],TX_PE_DATA[33],TX_PE_DATA[34],TX_PE_DATA[35],TX_PE_DATA[36],TX_PE_DATA[37],TX_PE_DATA[38],TX_PE_DATA[39],TX_PE_DATA[40],TX_PE_DATA[41],TX_PE_DATA[42],TX_PE_DATA[43],TX_PE_DATA[44],TX_PE_DATA[45],TX_PE_DATA[46],TX_PE_DATA[47],TX_PE_DATA[52],TX_PE_DATA[53],TX_PE_DATA[54],TX_PE_DATA[55],TX_PE_DATA[56],TX_PE_DATA[57],TX_PE_DATA[58],TX_PE_DATA[59],TX_PE_DATA[60],TX_PE_DATA[61],TX_PE_DATA[62],TX_PE_DATA[63]}), .\RX_DATA_REG_reg[0] (aurora_64b66b_0_wrapper_i_n_100), .RX_IDLE(RX_IDLE), .\RX_PE_DATA_reg[0] ({RX_PE_DATA[0],RX_PE_DATA[1],RX_PE_DATA[2],RX_PE_DATA[3],RX_PE_DATA[4],RX_PE_DATA[5],RX_PE_DATA[6],RX_PE_DATA[7],RX_PE_DATA[8],RX_PE_DATA[9],RX_PE_DATA[10],RX_PE_DATA[11],RX_PE_DATA[12],RX_PE_DATA[13],RX_PE_DATA[14],RX_PE_DATA[15],RX_PE_DATA[16],RX_PE_DATA[17],RX_PE_DATA[18],RX_PE_DATA[19],RX_PE_DATA[20],RX_PE_DATA[21],RX_PE_DATA[22],RX_PE_DATA[23],RX_PE_DATA[24],RX_PE_DATA[25],RX_PE_DATA[26],RX_PE_DATA[27],RX_PE_DATA[28],RX_PE_DATA[29],RX_PE_DATA[30],RX_PE_DATA[31],RX_PE_DATA[32],RX_PE_DATA[33],RX_PE_DATA[34],RX_PE_DATA[35],RX_PE_DATA[36],RX_PE_DATA[37],RX_PE_DATA[38],RX_PE_DATA[39],RX_PE_DATA[40],RX_PE_DATA[41],RX_PE_DATA[42],RX_PE_DATA[43],RX_PE_DATA[44],RX_PE_DATA[45],RX_PE_DATA[46],RX_PE_DATA[47],RX_PE_DATA[48],RX_PE_DATA[49],RX_PE_DATA[50],RX_PE_DATA[51],RX_PE_DATA[52],RX_PE_DATA[53],RX_PE_DATA[54],RX_PE_DATA[55],RX_PE_DATA[56],RX_PE_DATA[57],RX_PE_DATA[58],RX_PE_DATA[59],RX_PE_DATA[60],RX_PE_DATA[61],RX_PE_DATA[62],RX_PE_DATA[63]}), .SOFT_ERR_reg(aurora_lane_0_i_n_13), .SOFT_ERR_reg_0(aurora_64b66b_0_wrapper_i_n_96), .SR(SYSTEM_RESET_reg), .\TX_DATA_reg[55] ({global_logic_i_n_6,global_logic_i_n_7,tx_stream_i_n_4,tx_stream_i_n_5}), .\TX_DATA_reg[59] (aurora_64b66b_0_wrapper_i_n_94), .\TX_DATA_reg[63] ({tx_data_i[0],tx_data_i[1],tx_data_i[2],tx_data_i[3],tx_data_i[4],tx_data_i[5],tx_data_i[6],tx_data_i[7],tx_data_i[8],tx_data_i[9],tx_data_i[10],tx_data_i[11],tx_data_i[12],tx_data_i[13],tx_data_i[14],tx_data_i[15],tx_data_i[16],tx_data_i[17],tx_data_i[18],tx_data_i[19],tx_data_i[20],tx_data_i[21],tx_data_i[22],tx_data_i[23],tx_data_i[24],tx_data_i[25],tx_data_i[26],tx_data_i[27],tx_data_i[28],tx_data_i[29],tx_data_i[30],tx_data_i[31],tx_data_i[32],tx_data_i[33],tx_data_i[34],tx_data_i[35],tx_data_i[36],tx_data_i[37],tx_data_i[38],tx_data_i[39],tx_data_i[40],tx_data_i[41],tx_data_i[42],tx_data_i[43],tx_data_i[44],tx_data_i[45],tx_data_i[46],tx_data_i[47],tx_data_i[48],tx_data_i[49],tx_data_i[50],tx_data_i[51],tx_data_i[52],tx_data_i[53],tx_data_i[54],tx_data_i[55],tx_data_i[56],tx_data_i[57]}), .\TX_DATA_reg[63]_0 (global_logic_i_n_11), .TX_HEADER_1_reg(tx_stream_i_n_6), .channel_up_tx_if(channel_up_tx_if), .dout({aurora_64b66b_0_wrapper_i_n_21,aurora_64b66b_0_wrapper_i_n_22,aurora_64b66b_0_wrapper_i_n_23,aurora_64b66b_0_wrapper_i_n_24,aurora_64b66b_0_wrapper_i_n_25,aurora_64b66b_0_wrapper_i_n_26,aurora_64b66b_0_wrapper_i_n_27,aurora_64b66b_0_wrapper_i_n_28,aurora_64b66b_0_wrapper_i_n_29,aurora_64b66b_0_wrapper_i_n_30,aurora_64b66b_0_wrapper_i_n_31,aurora_64b66b_0_wrapper_i_n_32,aurora_64b66b_0_wrapper_i_n_33,aurora_64b66b_0_wrapper_i_n_34,aurora_64b66b_0_wrapper_i_n_35,aurora_64b66b_0_wrapper_i_n_36,aurora_64b66b_0_wrapper_i_n_37,aurora_64b66b_0_wrapper_i_n_38,aurora_64b66b_0_wrapper_i_n_39,aurora_64b66b_0_wrapper_i_n_40,aurora_64b66b_0_wrapper_i_n_41,aurora_64b66b_0_wrapper_i_n_42,aurora_64b66b_0_wrapper_i_n_43,aurora_64b66b_0_wrapper_i_n_44,aurora_64b66b_0_wrapper_i_n_45,aurora_64b66b_0_wrapper_i_n_46,aurora_64b66b_0_wrapper_i_n_47,aurora_64b66b_0_wrapper_i_n_48,aurora_64b66b_0_wrapper_i_n_49,aurora_64b66b_0_wrapper_i_n_50,aurora_64b66b_0_wrapper_i_n_51,aurora_64b66b_0_wrapper_i_n_52,aurora_64b66b_0_wrapper_i_n_53,aurora_64b66b_0_wrapper_i_n_54,aurora_64b66b_0_wrapper_i_n_55,aurora_64b66b_0_wrapper_i_n_56,aurora_64b66b_0_wrapper_i_n_57,aurora_64b66b_0_wrapper_i_n_58,aurora_64b66b_0_wrapper_i_n_59,aurora_64b66b_0_wrapper_i_n_60,aurora_64b66b_0_wrapper_i_n_61,aurora_64b66b_0_wrapper_i_n_62,aurora_64b66b_0_wrapper_i_n_63,aurora_64b66b_0_wrapper_i_n_64,aurora_64b66b_0_wrapper_i_n_65,aurora_64b66b_0_wrapper_i_n_66,aurora_64b66b_0_wrapper_i_n_67,aurora_64b66b_0_wrapper_i_n_68,aurora_64b66b_0_wrapper_i_n_69,aurora_64b66b_0_wrapper_i_n_70,aurora_64b66b_0_wrapper_i_n_71,aurora_64b66b_0_wrapper_i_n_72,aurora_64b66b_0_wrapper_i_n_73,aurora_64b66b_0_wrapper_i_n_74,aurora_64b66b_0_wrapper_i_n_75,aurora_64b66b_0_wrapper_i_n_76,aurora_64b66b_0_wrapper_i_n_77,aurora_64b66b_0_wrapper_i_n_78,aurora_64b66b_0_wrapper_i_n_79,aurora_64b66b_0_wrapper_i_n_80,aurora_64b66b_0_wrapper_i_n_81,aurora_64b66b_0_wrapper_i_n_82,aurora_64b66b_0_wrapper_i_n_83,aurora_64b66b_0_wrapper_i_n_84,aurora_64b66b_0_wrapper_i_n_85,aurora_64b66b_0_wrapper_i_n_86}), .enable_err_detect_i(enable_err_detect_i), .gen_cc_i(gen_cc_i), .gen_ch_bond_i(gen_ch_bond_i), .gen_na_idles_i(gen_na_idles_i), .hard_err_i(hard_err_i), .illegal_btf_i(illegal_btf_i), .in0(check_polarity_i), .lane_up_flop_i(lane_up_flop_i), .ready_r_reg0(\lane_init_sm_i/ready_r_reg0 ), .remote_ready_i(remote_ready_i), .reset_count_r0(\lane_init_sm_i/reset_count_r0 ), .reset_lanes_c(\channel_init_sm_i/reset_lanes_c ), .reset_lanes_i(reset_lanes_i), .rst_pma_init_usrclk(\sym_gen_i/rst_pma_init_usrclk ), .rx_lossofsync_i(rx_lossofsync_i), .rx_pe_data_v_i(rx_pe_data_v_i), .rx_polarity_r_reg(rx_polarity_i), .rxdatavalid_i(rxdatavalid_i), .s_level_out_d1_aurora_64b66b_0_cdc_to_reg(rx_neg_i), .scrambler({aurora_64b66b_0_wrapper_i_n_102,aurora_64b66b_0_wrapper_i_n_103,aurora_64b66b_0_wrapper_i_n_104,aurora_64b66b_0_wrapper_i_n_105,aurora_64b66b_0_wrapper_i_n_106,aurora_64b66b_0_wrapper_i_n_107,\scrambler_64b66b_gtx0_i/p_173_in ,\scrambler_64b66b_gtx0_i/p_169_in ,\scrambler_64b66b_gtx0_i/p_165_in ,\scrambler_64b66b_gtx0_i/p_161_in ,\scrambler_64b66b_gtx0_i/p_157_in ,\scrambler_64b66b_gtx0_i/p_153_in }), .stg1_aurora_64b66b_0_cdc_to_reg(stg1_aurora_64b66b_0_cdc_to_reg), .stg5_reg(TX_PE_DATA_V_reg), .tempData({\scrambler_64b66b_gtx0_i/tempData020_out ,\scrambler_64b66b_gtx0_i/tempData016_out ,\scrambler_64b66b_gtx0_i/tempData012_out ,\scrambler_64b66b_gtx0_i/tempData08_out ,\scrambler_64b66b_gtx0_i/tempData04_out ,\scrambler_64b66b_gtx0_i/tempData0 }), .tx_pe_data_v_i(tx_pe_data_v_i), .tx_reset_i(tx_reset_i), .txdatavalid_symgen_i(txdatavalid_symgen_i)); aurora_64b66b_0_aurora_64b66b_0_RESET_LOGIC core_reset_logic_i (.SR(SYSTEM_RESET_reg), .SYSTEM_RESET_reg_0(core_reset_logic_i_n_3), .hard_err_i(hard_err_i), .link_reset_out(link_reset_out), .power_down(power_down), .ready_r_reg0(\lane_init_sm_i/ready_r_reg0 ), .reset_count_r0(\lane_init_sm_i/reset_count_r0 ), .stg1_aurora_64b66b_0_cdc_to_reg(fsm_resetdone), .stg4_reg(TX_PE_DATA_V_reg), .sysreset_from_support(sysreset_from_support), .tx_reset_i(tx_reset_i), .wait_for_lane_up_r_reg(lane_up_flop_i)); aurora_64b66b_0_aurora_64b66b_0_GLOBAL_LOGIC global_logic_i (.CHANNEL_UP_RX_IF_reg(CHANNEL_UP_RX_IF_reg), .CHANNEL_UP_RX_IF_reg_0(global_logic_i_n_9), .CHANNEL_UP_RX_IF_reg_1(global_logic_i_n_12), .CHANNEL_UP_RX_IF_reg_2(TX_PE_DATA_V_reg), .CHANNEL_UP_RX_IF_reg_3(SYSTEM_RESET_reg), .E(\rx_stream_datapath_i/RX_D0 ), .Q({TX_PE_DATA[48],TX_PE_DATA[49]}), .R0(\tx_stream_control_sm_i/R0 ), .RX_IDLE(RX_IDLE), .SR(reset_lanes_i), .TXDATAVALID_IN(TXDATAVALID_IN), .\TX_DATA_reg[63] (aurora_64b66b_0_wrapper_i_n_94), .channel_up_tx_if(channel_up_tx_if), .gen_cc_flop_0_i({global_logic_i_n_6,global_logic_i_n_7}), .gen_cc_i(gen_cc_i), .gen_ch_bond_i(gen_ch_bond_i), .gen_ch_bond_int_reg(global_logic_i_n_11), .gen_na_idles_i(gen_na_idles_i), .hard_err(hard_err), .hard_err_i(hard_err_i), .remote_ready_i(remote_ready_i), .reset_lanes_c(\channel_init_sm_i/reset_lanes_c ), .rst_pma_init_usrclk(\sym_gen_i/rst_pma_init_usrclk ), .rx_pe_data_v_i(rx_pe_data_v_i), .tx_pe_data_v_i(tx_pe_data_v_i), .wait_for_lane_up_r_reg(core_reset_logic_i_n_3)); aurora_64b66b_0_aurora_64b66b_0_RX_STREAM rx_stream_i (.D({RX_PE_DATA[0],RX_PE_DATA[1],RX_PE_DATA[2],RX_PE_DATA[3],RX_PE_DATA[4],RX_PE_DATA[5],RX_PE_DATA[6],RX_PE_DATA[7],RX_PE_DATA[8],RX_PE_DATA[9],RX_PE_DATA[10],RX_PE_DATA[11],RX_PE_DATA[12],RX_PE_DATA[13],RX_PE_DATA[14],RX_PE_DATA[15],RX_PE_DATA[16],RX_PE_DATA[17],RX_PE_DATA[18],RX_PE_DATA[19],RX_PE_DATA[20],RX_PE_DATA[21],RX_PE_DATA[22],RX_PE_DATA[23],RX_PE_DATA[24],RX_PE_DATA[25],RX_PE_DATA[26],RX_PE_DATA[27],RX_PE_DATA[28],RX_PE_DATA[29],RX_PE_DATA[30],RX_PE_DATA[31],RX_PE_DATA[32],RX_PE_DATA[33],RX_PE_DATA[34],RX_PE_DATA[35],RX_PE_DATA[36],RX_PE_DATA[37],RX_PE_DATA[38],RX_PE_DATA[39],RX_PE_DATA[40],RX_PE_DATA[41],RX_PE_DATA[42],RX_PE_DATA[43],RX_PE_DATA[44],RX_PE_DATA[45],RX_PE_DATA[46],RX_PE_DATA[47],RX_PE_DATA[48],RX_PE_DATA[49],RX_PE_DATA[50],RX_PE_DATA[51],RX_PE_DATA[52],RX_PE_DATA[53],RX_PE_DATA[54],RX_PE_DATA[55],RX_PE_DATA[56],RX_PE_DATA[57],RX_PE_DATA[58],RX_PE_DATA[59],RX_PE_DATA[60],RX_PE_DATA[61],RX_PE_DATA[62],RX_PE_DATA[63]}), .E(\rx_stream_datapath_i/RX_D0 ), .RX_SRC_RDY_N_reg_inv(global_logic_i_n_12), .RX_SRC_RDY_N_reg_inv_0(TX_PE_DATA_V_reg), .SR(reset_lanes_i), .m_axi_rx_tdata(m_axi_rx_tdata), .m_axi_rx_tvalid(m_axi_rx_tvalid)); FDRE soft_err_reg (.C(TX_PE_DATA_V_reg), .CE(1'b1), .D(aurora_lane_0_i_n_13), .Q(soft_err), .R(SYSTEM_RESET_reg)); aurora_64b66b_0_aurora_64b66b_0_STANDARD_CC_MODULE standard_cc_module_i (.Q(do_cc_i), .SR(global_logic_i_n_9), .\count_16d_srl_r_reg[0]_0 (CHANNEL_UP_RX_IF_reg), .\count_24d_srl_r_reg[0]_0 (TX_PE_DATA_V_reg), .do_cc_r_reg0(\tx_stream_control_sm_i/do_cc_r_reg0 ), .extend_cc_r(\tx_stream_control_sm_i/extend_cc_r )); aurora_64b66b_0_aurora_64b66b_0_TX_STREAM tx_stream_i (.Q({TX_PE_DATA[0],TX_PE_DATA[1],TX_PE_DATA[2],TX_PE_DATA[3],TX_PE_DATA[4],TX_PE_DATA[5],TX_PE_DATA[6],TX_PE_DATA[7],TX_PE_DATA[8],TX_PE_DATA[9],TX_PE_DATA[10],TX_PE_DATA[11],TX_PE_DATA[12],TX_PE_DATA[13],TX_PE_DATA[14],TX_PE_DATA[15],TX_PE_DATA[16],TX_PE_DATA[17],TX_PE_DATA[18],TX_PE_DATA[19],TX_PE_DATA[20],TX_PE_DATA[21],TX_PE_DATA[22],TX_PE_DATA[23],TX_PE_DATA[24],TX_PE_DATA[25],TX_PE_DATA[26],TX_PE_DATA[27],TX_PE_DATA[28],TX_PE_DATA[29],TX_PE_DATA[30],TX_PE_DATA[31],TX_PE_DATA[32],TX_PE_DATA[33],TX_PE_DATA[34],TX_PE_DATA[35],TX_PE_DATA[36],TX_PE_DATA[37],TX_PE_DATA[38],TX_PE_DATA[39],TX_PE_DATA[40],TX_PE_DATA[41],TX_PE_DATA[42],TX_PE_DATA[43],TX_PE_DATA[44],TX_PE_DATA[45],TX_PE_DATA[46],TX_PE_DATA[47],TX_PE_DATA[48],TX_PE_DATA[49],TX_PE_DATA[52],TX_PE_DATA[53],TX_PE_DATA[54],TX_PE_DATA[55],TX_PE_DATA[56],TX_PE_DATA[57],TX_PE_DATA[58],TX_PE_DATA[59],TX_PE_DATA[60],TX_PE_DATA[61],TX_PE_DATA[62],TX_PE_DATA[63]}), .R0(\tx_stream_control_sm_i/R0 ), .TX_PE_DATA_V_reg(TX_PE_DATA_V_reg), .channel_up_tx_if(channel_up_tx_if), .do_cc_r(\tx_stream_control_sm_i/do_cc_r ), .do_cc_r_reg0(\tx_stream_control_sm_i/do_cc_r_reg0 ), .extend_cc_r(\tx_stream_control_sm_i/extend_cc_r ), .extend_cc_r_reg(aurora_64b66b_0_wrapper_i_n_92), .gen_cc_flop_0_i(tx_stream_i_n_6), .gen_cc_i(gen_cc_i), .gen_ch_bond_i(gen_ch_bond_i), .gen_na_idles_i(gen_na_idles_i), .rst_pma_init_usrclk(\sym_gen_i/rst_pma_init_usrclk ), .s_axi_tx_tdata(s_axi_tx_tdata), .s_axi_tx_tready(s_axi_tx_tready), .s_axi_tx_tvalid(s_axi_tx_tvalid), .tx_dst_rdy_n_r0(\tx_stream_control_sm_i/tx_dst_rdy_n_r0 ), .tx_pe_data_v_i(tx_pe_data_v_i), .wait_for_lane_up_r_reg({tx_stream_i_n_4,tx_stream_i_n_5})); endmodule (* CHECK_LICENSE_TYPE = "aurora_64b66b_0_fifo_gen_master,fifo_generator_v13_2_5,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* ORIG_REF_NAME = "aurora_64b66b_0_fifo_gen_master" *) (* X_CORE_INFO = "fifo_generator_v13_2_5,Vivado 2020.2" *) module aurora_64b66b_0_aurora_64b66b_0_fifo_gen_master (srst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, overflow, empty, underflow, prog_full, prog_empty, wr_rst_busy, rd_rst_busy); input srst; (* x_interface_info = "xilinx.com:signal:clock:1.0 write_clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME write_clk, FREQ_HZ 1000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0" *) input wr_clk; (* x_interface_info = "xilinx.com:signal:clock:1.0 read_clk CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME read_clk, FREQ_HZ 1000000, FREQ_TOLERANCE_HZ 0, PHASE 0.000, INSERT_VIP 0" *) input rd_clk; (* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *) input [71:0]din; (* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *) input wr_en; (* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *) input rd_en; (* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *) output [71:0]dout; (* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *) output full; output overflow; (* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *) output empty; output underflow; output prog_full; output prog_empty; output wr_rst_busy; output rd_rst_busy; wire \ ; wire [71:0]din; wire [68:0]\^dout ; wire empty; wire full; wire overflow; wire prog_empty; wire rd_clk; wire rd_en; wire srst; wire underflow; wire wr_clk; wire wr_en; wire NLW_U0_almost_empty_UNCONNECTED; wire NLW_U0_almost_full_UNCONNECTED; wire NLW_U0_axi_ar_dbiterr_UNCONNECTED; wire NLW_U0_axi_ar_overflow_UNCONNECTED; wire NLW_U0_axi_ar_prog_empty_UNCONNECTED; wire NLW_U0_axi_ar_prog_full_UNCONNECTED; wire NLW_U0_axi_ar_sbiterr_UNCONNECTED; wire NLW_U0_axi_ar_underflow_UNCONNECTED; wire NLW_U0_axi_aw_dbiterr_UNCONNECTED; wire NLW_U0_axi_aw_overflow_UNCONNECTED; wire NLW_U0_axi_aw_prog_empty_UNCONNECTED; wire NLW_U0_axi_aw_prog_full_UNCONNECTED; wire NLW_U0_axi_aw_sbiterr_UNCONNECTED; wire NLW_U0_axi_aw_underflow_UNCONNECTED; wire NLW_U0_axi_b_dbiterr_UNCONNECTED; wire NLW_U0_axi_b_overflow_UNCONNECTED; wire NLW_U0_axi_b_prog_empty_UNCONNECTED; wire NLW_U0_axi_b_prog_full_UNCONNECTED; wire NLW_U0_axi_b_sbiterr_UNCONNECTED; wire NLW_U0_axi_b_underflow_UNCONNECTED; wire NLW_U0_axi_r_dbiterr_UNCONNECTED; wire NLW_U0_axi_r_overflow_UNCONNECTED; wire NLW_U0_axi_r_prog_empty_UNCONNECTED; wire NLW_U0_axi_r_prog_full_UNCONNECTED; wire NLW_U0_axi_r_sbiterr_UNCONNECTED; wire NLW_U0_axi_r_underflow_UNCONNECTED; wire NLW_U0_axi_w_dbiterr_UNCONNECTED; wire NLW_U0_axi_w_overflow_UNCONNECTED; wire NLW_U0_axi_w_prog_empty_UNCONNECTED; wire NLW_U0_axi_w_prog_full_UNCONNECTED; wire NLW_U0_axi_w_sbiterr_UNCONNECTED; wire NLW_U0_axi_w_underflow_UNCONNECTED; wire NLW_U0_axis_dbiterr_UNCONNECTED; wire NLW_U0_axis_overflow_UNCONNECTED; wire NLW_U0_axis_prog_empty_UNCONNECTED; wire NLW_U0_axis_prog_full_UNCONNECTED; wire NLW_U0_axis_sbiterr_UNCONNECTED; wire NLW_U0_axis_underflow_UNCONNECTED; wire NLW_U0_dbiterr_UNCONNECTED; wire NLW_U0_m_axi_arvalid_UNCONNECTED; wire NLW_U0_m_axi_awvalid_UNCONNECTED; wire NLW_U0_m_axi_bready_UNCONNECTED; wire NLW_U0_m_axi_rready_UNCONNECTED; wire NLW_U0_m_axi_wlast_UNCONNECTED; wire NLW_U0_m_axi_wvalid_UNCONNECTED; wire NLW_U0_m_axis_tlast_UNCONNECTED; wire NLW_U0_m_axis_tvalid_UNCONNECTED; wire NLW_U0_prog_full_UNCONNECTED; wire NLW_U0_rd_rst_busy_UNCONNECTED; wire NLW_U0_s_axi_arready_UNCONNECTED; wire NLW_U0_s_axi_awready_UNCONNECTED; wire NLW_U0_s_axi_bvalid_UNCONNECTED; wire NLW_U0_s_axi_rlast_UNCONNECTED; wire NLW_U0_s_axi_rvalid_UNCONNECTED; wire NLW_U0_s_axi_wready_UNCONNECTED; wire NLW_U0_s_axis_tready_UNCONNECTED; wire NLW_U0_sbiterr_UNCONNECTED; wire NLW_U0_valid_UNCONNECTED; wire NLW_U0_wr_ack_UNCONNECTED; wire NLW_U0_wr_rst_busy_UNCONNECTED; wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED; wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED; wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED; wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED; wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED; wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED; wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED; wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED; wire [10:0]NLW_U0_axis_data_count_UNCONNECTED; wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED; wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED; wire [8:0]NLW_U0_data_count_UNCONNECTED; wire [71:66]NLW_U0_dout_UNCONNECTED; wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED; wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED; wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED; wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED; wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED; wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED; wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED; wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED; wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED; wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED; wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED; wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED; wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED; wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED; wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED; wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED; wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED; wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED; wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED; wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED; wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED; wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED; wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED; wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED; wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED; wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED; wire [7:0]NLW_U0_m_axis_tdata_UNCONNECTED; wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED; wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED; wire [0:0]NLW_U0_m_axis_tkeep_UNCONNECTED; wire [0:0]NLW_U0_m_axis_tstrb_UNCONNECTED; wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED; wire [8:0]NLW_U0_rd_data_count_UNCONNECTED; wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED; wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED; wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED; wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED; wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED; wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED; wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED; wire [8:0]NLW_U0_wr_data_count_UNCONNECTED; assign dout[71] = \ ; assign dout[70] = \ ; assign dout[69] = \ ; assign dout[68] = \^dout [68]; assign dout[67] = \ ; assign dout[66] = \ ; assign dout[65:0] = \^dout [65:0]; assign prog_full = \ ; assign rd_rst_busy = \ ; assign wr_rst_busy = \ ; GND GND (.G(\ )); (* C_ADD_NGC_CONSTRAINT = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *) (* C_APPLICATION_TYPE_RACH = "0" *) (* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *) (* C_APPLICATION_TYPE_WRCH = "0" *) (* C_AXIS_TDATA_WIDTH = "8" *) (* C_AXIS_TDEST_WIDTH = "1" *) (* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TKEEP_WIDTH = "1" *) (* C_AXIS_TSTRB_WIDTH = "1" *) (* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TYPE = "0" *) (* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) (* C_AXI_LEN_WIDTH = "8" *) (* C_AXI_LOCK_WIDTH = "1" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "1" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "0" *) (* C_COUNT_TYPE = "0" *) (* C_DATA_COUNT_WIDTH = "9" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "72" *) (* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *) (* C_DIN_WIDTH_WACH = "1" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *) (* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "72" *) (* C_ENABLE_RLOCS = "0" *) (* C_ENABLE_RST_SYNC = "1" *) (* C_EN_SAFETY_CKT = "0" *) (* C_ERROR_INJECTION_TYPE = "0" *) (* C_ERROR_INJECTION_TYPE_AXIS = "0" *) (* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WACH = "0" *) (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *) (* C_FAMILY = "kintexu" *) (* C_FULL_FLAGS_RST_VAL = "0" *) (* C_HAS_ALMOST_EMPTY = "0" *) (* C_HAS_ALMOST_FULL = "0" *) (* C_HAS_AXIS_TDATA = "1" *) (* C_HAS_AXIS_TDEST = "0" *) (* C_HAS_AXIS_TID = "0" *) (* C_HAS_AXIS_TKEEP = "0" *) (* C_HAS_AXIS_TLAST = "0" *) (* C_HAS_AXIS_TREADY = "1" *) (* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TUSER = "1" *) (* C_HAS_AXI_ARUSER = "0" *) (* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_AXI_RD_CHANNEL = "1" *) (* C_HAS_AXI_RUSER = "0" *) (* C_HAS_AXI_WR_CHANNEL = "1" *) (* C_HAS_AXI_WUSER = "0" *) (* C_HAS_BACKUP = "0" *) (* C_HAS_DATA_COUNT = "0" *) (* C_HAS_DATA_COUNTS_AXIS = "0" *) (* C_HAS_DATA_COUNTS_RACH = "0" *) (* C_HAS_DATA_COUNTS_RDCH = "0" *) (* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *) (* C_HAS_DATA_COUNTS_WRCH = "0" *) (* C_HAS_INT_CLK = "0" *) (* C_HAS_MASTER_CE = "0" *) (* C_HAS_MEMINIT_FILE = "0" *) (* C_HAS_OVERFLOW = "1" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *) (* C_HAS_PROG_FLAGS_RACH = "0" *) (* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_WACH = "0" *) (* C_HAS_PROG_FLAGS_WDCH = "0" *) (* C_HAS_PROG_FLAGS_WRCH = "0" *) (* C_HAS_RD_DATA_COUNT = "0" *) (* C_HAS_RD_RST = "0" *) (* C_HAS_RST = "0" *) (* C_HAS_SLAVE_CE = "0" *) (* C_HAS_SRST = "1" *) (* C_HAS_UNDERFLOW = "1" *) (* C_HAS_VALID = "0" *) (* C_HAS_WR_ACK = "0" *) (* C_HAS_WR_DATA_COUNT = "0" *) (* C_HAS_WR_RST = "0" *) (* C_IMPLEMENTATION_TYPE = "6" *) (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) (* C_IMPLEMENTATION_TYPE_RACH = "1" *) (* C_IMPLEMENTATION_TYPE_RDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WACH = "1" *) (* C_IMPLEMENTATION_TYPE_WDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WRCH = "1" *) (* C_INIT_WR_PNTR_VAL = "0" *) (* C_INTERFACE_TYPE = "0" *) (* C_MEMORY_TYPE = "4" *) (* C_MIF_FILE_NAME = "BlankString" *) (* C_MSGON_VAL = "1" *) (* C_OPTIMIZATION_MODE = "0" *) (* C_OVERFLOW_LOW = "0" *) (* C_POWER_SAVING_MODE = "0" *) (* C_PRELOAD_LATENCY = "2" *) (* C_PRELOAD_REGS = "1" *) (* C_PRIM_FIFO_TYPE = "512x72" *) (* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *) (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "512x72" *) (* C_PRIM_FIFO_TYPE_WACH = "512x36" *) (* C_PRIM_FIFO_TYPE_WDCH = "512x72" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL = "8" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "9" *) (* C_PROG_EMPTY_TYPE = "1" *) (* C_PROG_EMPTY_TYPE_AXIS = "0" *) (* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *) (* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *) (* C_PROG_FULL_THRESH_ASSERT_VAL = "450" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "449" *) (* C_PROG_FULL_TYPE = "1" *) (* C_PROG_FULL_TYPE_AXIS = "0" *) (* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *) (* C_PROG_FULL_TYPE_WACH = "0" *) (* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *) (* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "9" *) (* C_RD_DEPTH = "512" *) (* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "9" *) (* C_REG_SLICE_MODE_AXIS = "0" *) (* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *) (* C_REG_SLICE_MODE_WACH = "0" *) (* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *) (* C_SELECT_XPM = "0" *) (* C_SYNCHRONIZER_STAGE = "2" *) (* C_UNDERFLOW_LOW = "0" *) (* C_USE_COMMON_OVERFLOW = "0" *) (* C_USE_COMMON_UNDERFLOW = "0" *) (* C_USE_DEFAULT_SETTINGS = "0" *) (* C_USE_DOUT_RST = "1" *) (* C_USE_ECC = "0" *) (* C_USE_ECC_AXIS = "0" *) (* C_USE_ECC_RACH = "0" *) (* C_USE_ECC_RDCH = "0" *) (* C_USE_ECC_WACH = "0" *) (* C_USE_ECC_WDCH = "0" *) (* C_USE_ECC_WRCH = "0" *) (* C_USE_EMBEDDED_REG = "1" *) (* C_USE_FIFO16_FLAGS = "0" *) (* C_USE_FWFT_DATA_COUNT = "0" *) (* C_USE_PIPELINE_REG = "0" *) (* C_VALID_LOW = "0" *) (* C_WACH_TYPE = "0" *) (* C_WDCH_TYPE = "0" *) (* C_WRCH_TYPE = "0" *) (* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "9" *) (* C_WR_DEPTH = "512" *) (* C_WR_DEPTH_AXIS = "1024" *) (* C_WR_DEPTH_RACH = "16" *) (* C_WR_DEPTH_RDCH = "1024" *) (* C_WR_DEPTH_WACH = "16" *) (* C_WR_DEPTH_WDCH = "1024" *) (* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "9" *) (* C_WR_PNTR_WIDTH_AXIS = "10" *) (* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "10" *) (* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "10" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *) (* C_WR_RESPONSE_LATENCY = "1" *) (* is_du_within_envelope = "true" *) aurora_64b66b_0_fifo_generator_v13_2_5 U0 (.almost_empty(NLW_U0_almost_empty_UNCONNECTED), .almost_full(NLW_U0_almost_full_UNCONNECTED), .axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]), .axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED), .axi_ar_injectdbiterr(1'b0), .axi_ar_injectsbiterr(1'b0), .axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED), .axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED), .axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}), .axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED), .axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}), .axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]), .axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED), .axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED), .axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]), .axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]), .axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED), .axi_aw_injectdbiterr(1'b0), .axi_aw_injectsbiterr(1'b0), .axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED), .axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED), .axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}), .axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED), .axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}), .axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]), .axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED), .axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED), .axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]), .axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]), .axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED), .axi_b_injectdbiterr(1'b0), .axi_b_injectsbiterr(1'b0), .axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED), .axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED), .axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}), .axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED), .axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}), .axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]), .axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED), .axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED), .axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]), .axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]), .axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED), .axi_r_injectdbiterr(1'b0), .axi_r_injectsbiterr(1'b0), .axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED), .axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED), .axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED), .axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]), .axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED), .axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED), .axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]), .axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]), .axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED), .axi_w_injectdbiterr(1'b0), .axi_w_injectsbiterr(1'b0), .axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED), .axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED), .axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED), .axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]), .axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED), .axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED), .axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]), .axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[10:0]), .axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED), .axis_injectdbiterr(1'b0), .axis_injectsbiterr(1'b0), .axis_overflow(NLW_U0_axis_overflow_UNCONNECTED), .axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED), .axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED), .axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[10:0]), .axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED), .axis_underflow(NLW_U0_axis_underflow_UNCONNECTED), .axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[10:0]), .backup(1'b0), .backup_marker(1'b0), .clk(1'b0), .data_count(NLW_U0_data_count_UNCONNECTED[8:0]), .dbiterr(NLW_U0_dbiterr_UNCONNECTED), .din(din), .dout({NLW_U0_dout_UNCONNECTED[71:69],\^dout }), .empty(empty), .full(full), .injectdbiterr(1'b0), .injectsbiterr(1'b0), .int_clk(1'b0), .m_aclk(1'b0), .m_aclk_en(1'b0), .m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]), .m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]), .m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]), .m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]), .m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]), .m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]), .m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]), .m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]), .m_axi_arready(1'b0), .m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]), .m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]), .m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]), .m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED), .m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]), .m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]), .m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]), .m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]), .m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]), .m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]), .m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]), .m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]), .m_axi_awready(1'b0), .m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]), .m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]), .m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]), .m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED), .m_axi_bid(1'b0), .m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED), .m_axi_bresp({1'b0,1'b0}), .m_axi_buser(1'b0), .m_axi_bvalid(1'b0), .m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .m_axi_rid(1'b0), .m_axi_rlast(1'b0), .m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED), .m_axi_rresp({1'b0,1'b0}), .m_axi_ruser(1'b0), .m_axi_rvalid(1'b0), .m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]), .m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]), .m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED), .m_axi_wready(1'b0), .m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]), .m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]), .m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED), .m_axis_tdata(NLW_U0_m_axis_tdata_UNCONNECTED[7:0]), .m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]), .m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]), .m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[0]), .m_axis_tlast(NLW_U0_m_axis_tlast_UNCONNECTED), .m_axis_tready(1'b0), .m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[0]), .m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[3:0]), .m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED), .overflow(overflow), .prog_empty(prog_empty), .prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .prog_full(NLW_U0_prog_full_UNCONNECTED), .prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .rd_clk(rd_clk), .rd_data_count(NLW_U0_rd_data_count_UNCONNECTED[8:0]), .rd_en(rd_en), .rd_rst(1'b0), .rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED), .rst(1'b0), .s_aclk(1'b0), .s_aclk_en(1'b0), .s_aresetn(1'b0), .s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_arburst({1'b0,1'b0}), .s_axi_arcache({1'b0,1'b0,1'b0,1'b0}), .s_axi_arid(1'b0), .s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_arlock(1'b0), .s_axi_arprot({1'b0,1'b0,1'b0}), .s_axi_arqos({1'b0,1'b0,1'b0,1'b0}), .s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED), .s_axi_arregion({1'b0,1'b0,1'b0,1'b0}), .s_axi_arsize({1'b0,1'b0,1'b0}), .s_axi_aruser(1'b0), .s_axi_arvalid(1'b0), .s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_awburst({1'b0,1'b0}), .s_axi_awcache({1'b0,1'b0,1'b0,1'b0}), .s_axi_awid(1'b0), .s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_awlock(1'b0), .s_axi_awprot({1'b0,1'b0,1'b0}), .s_axi_awqos({1'b0,1'b0,1'b0,1'b0}), .s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED), .s_axi_awregion({1'b0,1'b0,1'b0,1'b0}), .s_axi_awsize({1'b0,1'b0,1'b0}), .s_axi_awuser(1'b0), .s_axi_awvalid(1'b0), .s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]), .s_axi_bready(1'b0), .s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]), .s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]), .s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED), .s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]), .s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]), .s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED), .s_axi_rready(1'b0), .s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]), .s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]), .s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED), .s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_wid(1'b0), .s_axi_wlast(1'b0), .s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED), .s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axi_wuser(1'b0), .s_axi_wvalid(1'b0), .s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .s_axis_tdest(1'b0), .s_axis_tid(1'b0), .s_axis_tkeep(1'b0), .s_axis_tlast(1'b0), .s_axis_tready(NLW_U0_s_axis_tready_UNCONNECTED), .s_axis_tstrb(1'b0), .s_axis_tuser({1'b0,1'b0,1'b0,1'b0}), .s_axis_tvalid(1'b0), .sbiterr(NLW_U0_sbiterr_UNCONNECTED), .sleep(1'b0), .srst(srst), .underflow(underflow), .valid(NLW_U0_valid_UNCONNECTED), .wr_ack(NLW_U0_wr_ack_UNCONNECTED), .wr_clk(wr_clk), .wr_data_count(NLW_U0_wr_data_count_UNCONNECTED[8:0]), .wr_en(wr_en), .wr_rst(1'b0), .wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED)); endmodule (* CHECK_LICENSE_TYPE = "aurora_64b66b_0_gt,aurora_64b66b_0_gt_gtwizard_top,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* ORIG_REF_NAME = "aurora_64b66b_0_gt" *) (* X_CORE_INFO = "aurora_64b66b_0_gt_gtwizard_top,Vivado 2020.2" *) module aurora_64b66b_0_aurora_64b66b_0_gt (gtwiz_userclk_tx_active_in, gtwiz_userclk_rx_active_in, gtwiz_reset_clk_freerun_in, gtwiz_reset_all_in, gtwiz_reset_tx_pll_and_datapath_in, gtwiz_reset_tx_datapath_in, gtwiz_reset_rx_pll_and_datapath_in, gtwiz_reset_rx_datapath_in, gtwiz_reset_rx_cdr_stable_out, gtwiz_reset_tx_done_out, gtwiz_reset_rx_done_out, gtwiz_userdata_tx_in, gtwiz_userdata_rx_out, drpaddr_in, drpclk_in, drpdi_in, drpen_in, drpwe_in, eyescanreset_in, eyescantrigger_in, gthrxn_in, gthrxp_in, gtrefclk0_in, loopback_in, pcsrsvdin_in, rxbufreset_in, rxcdrhold_in, rxcdrovrden_in, rxdfelpmreset_in, rxgearboxslip_in, rxlpmen_in, rxpcsreset_in, rxpmareset_in, rxpolarity_in, rxprbscntreset_in, rxprbssel_in, rxusrclk_in, rxusrclk2_in, txdiffctrl_in, txheader_in, txinhibit_in, txpcsreset_in, txpmareset_in, txpolarity_in, txpostcursor_in, txprbsforceerr_in, txprbssel_in, txprecursor_in, txsequence_in, txusrclk_in, txusrclk2_in, cplllock_out, dmonitorout_out, drpdo_out, drprdy_out, eyescandataerror_out, gthtxn_out, gthtxp_out, gtpowergood_out, rxbufstatus_out, rxdatavalid_out, rxheader_out, rxheadervalid_out, rxoutclk_out, rxpmaresetdone_out, rxprbserr_out, rxresetdone_out, rxstartofseq_out, txbufstatus_out, txoutclk_out, txoutclkfabric_out, txoutclkpcs_out, txpmaresetdone_out, txresetdone_out, lopt, lopt_1, lopt_2, lopt_3, lopt_4, lopt_5, lopt_6, lopt_7); input [0:0]gtwiz_userclk_tx_active_in; input [0:0]gtwiz_userclk_rx_active_in; input [0:0]gtwiz_reset_clk_freerun_in; input [0:0]gtwiz_reset_all_in; input [0:0]gtwiz_reset_tx_pll_and_datapath_in; input [0:0]gtwiz_reset_tx_datapath_in; input [0:0]gtwiz_reset_rx_pll_and_datapath_in; input [0:0]gtwiz_reset_rx_datapath_in; output [0:0]gtwiz_reset_rx_cdr_stable_out; output [0:0]gtwiz_reset_tx_done_out; output [0:0]gtwiz_reset_rx_done_out; input [63:0]gtwiz_userdata_tx_in; output [31:0]gtwiz_userdata_rx_out; input [8:0]drpaddr_in; input [0:0]drpclk_in; input [15:0]drpdi_in; input [0:0]drpen_in; input [0:0]drpwe_in; input [0:0]eyescanreset_in; input [0:0]eyescantrigger_in; input [0:0]gthrxn_in; input [0:0]gthrxp_in; input [0:0]gtrefclk0_in; input [2:0]loopback_in; input [15:0]pcsrsvdin_in; input [0:0]rxbufreset_in; input [0:0]rxcdrhold_in; input [0:0]rxcdrovrden_in; input [0:0]rxdfelpmreset_in; input [0:0]rxgearboxslip_in; input [0:0]rxlpmen_in; input [0:0]rxpcsreset_in; input [0:0]rxpmareset_in; input [0:0]rxpolarity_in; input [0:0]rxprbscntreset_in; input [3:0]rxprbssel_in; input [0:0]rxusrclk_in; input [0:0]rxusrclk2_in; input [3:0]txdiffctrl_in; input [5:0]txheader_in; input [0:0]txinhibit_in; input [0:0]txpcsreset_in; input [0:0]txpmareset_in; input [0:0]txpolarity_in; input [4:0]txpostcursor_in; input [0:0]txprbsforceerr_in; input [3:0]txprbssel_in; input [4:0]txprecursor_in; input [6:0]txsequence_in; input [0:0]txusrclk_in; input [0:0]txusrclk2_in; output [0:0]cplllock_out; output [16:0]dmonitorout_out; output [15:0]drpdo_out; output [0:0]drprdy_out; output [0:0]eyescandataerror_out; output [0:0]gthtxn_out; output [0:0]gthtxp_out; output [0:0]gtpowergood_out; output [2:0]rxbufstatus_out; output [1:0]rxdatavalid_out; output [5:0]rxheader_out; output [1:0]rxheadervalid_out; output [0:0]rxoutclk_out; output [0:0]rxpmaresetdone_out; output [0:0]rxprbserr_out; output [0:0]rxresetdone_out; output [1:0]rxstartofseq_out; output [1:0]txbufstatus_out; output [0:0]txoutclk_out; output [0:0]txoutclkfabric_out; output [0:0]txoutclkpcs_out; output [0:0]txpmaresetdone_out; output [0:0]txresetdone_out; input lopt; input lopt_1; output lopt_2; output lopt_3; input lopt_4; input lopt_5; output lopt_6; output lopt_7; wire \ ; wire [0:0]cplllock_out; wire [8:0]drpaddr_in; wire [0:0]drpclk_in; wire [15:0]drpdi_in; wire [15:0]drpdo_out; wire [0:0]drpen_in; wire [0:0]drprdy_out; wire [0:0]drpwe_in; wire [0:0]gthrxn_in; wire [0:0]gthrxp_in; wire [0:0]gthtxn_out; wire [0:0]gthtxp_out; wire [0:0]gtpowergood_out; wire [0:0]gtrefclk0_in; wire [0:0]gtwiz_reset_rx_datapath_in; wire [0:0]gtwiz_reset_rx_done_out; wire [0:0]gtwiz_reset_rx_pll_and_datapath_in; wire [0:0]gtwiz_reset_tx_done_out; wire [0:0]gtwiz_userclk_rx_active_in; wire [0:0]gtwiz_userclk_tx_active_in; wire [31:0]gtwiz_userdata_rx_out; wire [63:0]gtwiz_userdata_tx_in; wire [2:0]loopback_in; wire lopt; wire lopt_1; wire lopt_2; wire lopt_3; wire lopt_4; wire lopt_5; wire lopt_6; wire lopt_7; wire [2:2]\^rxbufstatus_out ; wire [0:0]rxcdrovrden_in; wire [0:0]\^rxdatavalid_out ; wire [0:0]rxgearboxslip_in; wire [1:0]\^rxheader_out ; wire [0:0]\^rxheadervalid_out ; wire [0:0]rxoutclk_out; wire [0:0]rxpmaresetdone_out; wire [0:0]rxpolarity_in; wire [0:0]rxusrclk2_in; wire [0:0]rxusrclk_in; wire [1:1]\^txbufstatus_out ; wire [5:0]txheader_in; wire [0:0]txoutclk_out; wire [0:0]txpmaresetdone_out; wire [6:0]txsequence_in; wire [0:0]txusrclk2_in; wire [0:0]txusrclk_in; wire [2:0]NLW_inst_bufgtce_out_UNCONNECTED; wire [2:0]NLW_inst_bufgtcemask_out_UNCONNECTED; wire [8:0]NLW_inst_bufgtdiv_out_UNCONNECTED; wire [2:0]NLW_inst_bufgtreset_out_UNCONNECTED; wire [2:0]NLW_inst_bufgtrstmask_out_UNCONNECTED; wire [0:0]NLW_inst_cpllfbclklost_out_UNCONNECTED; wire [0:0]NLW_inst_cpllrefclklost_out_UNCONNECTED; wire [16:0]NLW_inst_dmonitorout_out_UNCONNECTED; wire [0:0]NLW_inst_dmonitoroutclk_out_UNCONNECTED; wire [15:0]NLW_inst_drpdo_common_out_UNCONNECTED; wire [0:0]NLW_inst_drprdy_common_out_UNCONNECTED; wire [0:0]NLW_inst_eyescandataerror_out_UNCONNECTED; wire [0:0]NLW_inst_gtrefclkmonitor_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_buffbypass_rx_done_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_buffbypass_rx_error_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_buffbypass_tx_done_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_buffbypass_tx_error_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_reset_qpll0reset_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_reset_qpll1reset_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_reset_rx_cdr_stable_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_userclk_rx_active_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_userclk_rx_srcclk_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_userclk_rx_usrclk2_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_userclk_rx_usrclk_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_userclk_tx_active_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_userclk_tx_srcclk_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_userclk_tx_usrclk2_out_UNCONNECTED; wire [0:0]NLW_inst_gtwiz_userclk_tx_usrclk_out_UNCONNECTED; wire [0:0]NLW_inst_gtytxn_out_UNCONNECTED; wire [0:0]NLW_inst_gtytxp_out_UNCONNECTED; wire [0:0]NLW_inst_pcierategen3_out_UNCONNECTED; wire [0:0]NLW_inst_pcierateidle_out_UNCONNECTED; wire [1:0]NLW_inst_pcierateqpllpd_out_UNCONNECTED; wire [1:0]NLW_inst_pcierateqpllreset_out_UNCONNECTED; wire [0:0]NLW_inst_pciesynctxsyncdone_out_UNCONNECTED; wire [0:0]NLW_inst_pcieusergen3rdy_out_UNCONNECTED; wire [0:0]NLW_inst_pcieuserphystatusrst_out_UNCONNECTED; wire [0:0]NLW_inst_pcieuserratestart_out_UNCONNECTED; wire [11:0]NLW_inst_pcsrsvdout_out_UNCONNECTED; wire [0:0]NLW_inst_phystatus_out_UNCONNECTED; wire [7:0]NLW_inst_pinrsrvdas_out_UNCONNECTED; wire [7:0]NLW_inst_pmarsvdout0_out_UNCONNECTED; wire [7:0]NLW_inst_pmarsvdout1_out_UNCONNECTED; wire [0:0]NLW_inst_powerpresent_out_UNCONNECTED; wire [0:0]NLW_inst_qpll0fbclklost_out_UNCONNECTED; wire [0:0]NLW_inst_qpll0lock_out_UNCONNECTED; wire [0:0]NLW_inst_qpll0outclk_out_UNCONNECTED; wire [0:0]NLW_inst_qpll0outrefclk_out_UNCONNECTED; wire [0:0]NLW_inst_qpll0refclklost_out_UNCONNECTED; wire [0:0]NLW_inst_qpll1fbclklost_out_UNCONNECTED; wire [0:0]NLW_inst_qpll1lock_out_UNCONNECTED; wire [0:0]NLW_inst_qpll1outclk_out_UNCONNECTED; wire [0:0]NLW_inst_qpll1outrefclk_out_UNCONNECTED; wire [0:0]NLW_inst_qpll1refclklost_out_UNCONNECTED; wire [7:0]NLW_inst_qplldmonitor0_out_UNCONNECTED; wire [7:0]NLW_inst_qplldmonitor1_out_UNCONNECTED; wire [0:0]NLW_inst_refclkoutmonitor0_out_UNCONNECTED; wire [0:0]NLW_inst_refclkoutmonitor1_out_UNCONNECTED; wire [0:0]NLW_inst_resetexception_out_UNCONNECTED; wire [1:0]NLW_inst_rxbufstatus_out_UNCONNECTED; wire [0:0]NLW_inst_rxbyteisaligned_out_UNCONNECTED; wire [0:0]NLW_inst_rxbyterealign_out_UNCONNECTED; wire [0:0]NLW_inst_rxcdrlock_out_UNCONNECTED; wire [0:0]NLW_inst_rxcdrphdone_out_UNCONNECTED; wire [0:0]NLW_inst_rxchanbondseq_out_UNCONNECTED; wire [0:0]NLW_inst_rxchanisaligned_out_UNCONNECTED; wire [0:0]NLW_inst_rxchanrealign_out_UNCONNECTED; wire [4:0]NLW_inst_rxchbondo_out_UNCONNECTED; wire [0:0]NLW_inst_rxckcaldone_out_UNCONNECTED; wire [1:0]NLW_inst_rxclkcorcnt_out_UNCONNECTED; wire [0:0]NLW_inst_rxcominitdet_out_UNCONNECTED; wire [0:0]NLW_inst_rxcommadet_out_UNCONNECTED; wire [0:0]NLW_inst_rxcomsasdet_out_UNCONNECTED; wire [0:0]NLW_inst_rxcomwakedet_out_UNCONNECTED; wire [15:0]NLW_inst_rxctrl0_out_UNCONNECTED; wire [15:0]NLW_inst_rxctrl1_out_UNCONNECTED; wire [7:0]NLW_inst_rxctrl2_out_UNCONNECTED; wire [7:0]NLW_inst_rxctrl3_out_UNCONNECTED; wire [127:0]NLW_inst_rxdata_out_UNCONNECTED; wire [7:0]NLW_inst_rxdataextendrsvd_out_UNCONNECTED; wire [1:1]NLW_inst_rxdatavalid_out_UNCONNECTED; wire [0:0]NLW_inst_rxdlysresetdone_out_UNCONNECTED; wire [0:0]NLW_inst_rxelecidle_out_UNCONNECTED; wire [5:2]NLW_inst_rxheader_out_UNCONNECTED; wire [1:1]NLW_inst_rxheadervalid_out_UNCONNECTED; wire [0:0]NLW_inst_rxlfpstresetdet_out_UNCONNECTED; wire [0:0]NLW_inst_rxlfpsu2lpexitdet_out_UNCONNECTED; wire [0:0]NLW_inst_rxlfpsu3wakedet_out_UNCONNECTED; wire [6:0]NLW_inst_rxmonitorout_out_UNCONNECTED; wire [0:0]NLW_inst_rxosintdone_out_UNCONNECTED; wire [0:0]NLW_inst_rxosintstarted_out_UNCONNECTED; wire [0:0]NLW_inst_rxosintstrobedone_out_UNCONNECTED; wire [0:0]NLW_inst_rxosintstrobestarted_out_UNCONNECTED; wire [0:0]NLW_inst_rxoutclkfabric_out_UNCONNECTED; wire [0:0]NLW_inst_rxoutclkpcs_out_UNCONNECTED; wire [0:0]NLW_inst_rxphaligndone_out_UNCONNECTED; wire [0:0]NLW_inst_rxphalignerr_out_UNCONNECTED; wire [0:0]NLW_inst_rxprbserr_out_UNCONNECTED; wire [0:0]NLW_inst_rxprbslocked_out_UNCONNECTED; wire [0:0]NLW_inst_rxprgdivresetdone_out_UNCONNECTED; wire [0:0]NLW_inst_rxqpisenn_out_UNCONNECTED; wire [0:0]NLW_inst_rxqpisenp_out_UNCONNECTED; wire [0:0]NLW_inst_rxratedone_out_UNCONNECTED; wire [1:0]NLW_inst_rxrecclk0_sel_out_UNCONNECTED; wire [0:0]NLW_inst_rxrecclk0sel_out_UNCONNECTED; wire [1:0]NLW_inst_rxrecclk1_sel_out_UNCONNECTED; wire [0:0]NLW_inst_rxrecclk1sel_out_UNCONNECTED; wire [0:0]NLW_inst_rxrecclkout_out_UNCONNECTED; wire [0:0]NLW_inst_rxresetdone_out_UNCONNECTED; wire [0:0]NLW_inst_rxsliderdy_out_UNCONNECTED; wire [0:0]NLW_inst_rxslipdone_out_UNCONNECTED; wire [0:0]NLW_inst_rxslipoutclkrdy_out_UNCONNECTED; wire [0:0]NLW_inst_rxslippmardy_out_UNCONNECTED; wire [1:0]NLW_inst_rxstartofseq_out_UNCONNECTED; wire [2:0]NLW_inst_rxstatus_out_UNCONNECTED; wire [0:0]NLW_inst_rxsyncdone_out_UNCONNECTED; wire [0:0]NLW_inst_rxsyncout_out_UNCONNECTED; wire [0:0]NLW_inst_rxvalid_out_UNCONNECTED; wire [0:0]NLW_inst_sdm0finalout_out_UNCONNECTED; wire [0:0]NLW_inst_sdm0testdata_out_UNCONNECTED; wire [0:0]NLW_inst_sdm1finalout_out_UNCONNECTED; wire [0:0]NLW_inst_sdm1testdata_out_UNCONNECTED; wire [0:0]NLW_inst_tcongpo_out_UNCONNECTED; wire [0:0]NLW_inst_tconrsvdout0_out_UNCONNECTED; wire [0:0]NLW_inst_txbufstatus_out_UNCONNECTED; wire [0:0]NLW_inst_txcomfinish_out_UNCONNECTED; wire [0:0]NLW_inst_txdccdone_out_UNCONNECTED; wire [0:0]NLW_inst_txdlysresetdone_out_UNCONNECTED; wire [0:0]NLW_inst_txoutclkfabric_out_UNCONNECTED; wire [0:0]NLW_inst_txoutclkpcs_out_UNCONNECTED; wire [0:0]NLW_inst_txphaligndone_out_UNCONNECTED; wire [0:0]NLW_inst_txphinitdone_out_UNCONNECTED; wire [0:0]NLW_inst_txprgdivresetdone_out_UNCONNECTED; wire [0:0]NLW_inst_txqpisenn_out_UNCONNECTED; wire [0:0]NLW_inst_txqpisenp_out_UNCONNECTED; wire [0:0]NLW_inst_txratedone_out_UNCONNECTED; wire [0:0]NLW_inst_txresetdone_out_UNCONNECTED; wire [0:0]NLW_inst_txsyncdone_out_UNCONNECTED; wire [0:0]NLW_inst_txsyncout_out_UNCONNECTED; wire [0:0]NLW_inst_ubdaddr_out_UNCONNECTED; wire [0:0]NLW_inst_ubden_out_UNCONNECTED; wire [0:0]NLW_inst_ubdi_out_UNCONNECTED; wire [0:0]NLW_inst_ubdwe_out_UNCONNECTED; wire [0:0]NLW_inst_ubmdmtdo_out_UNCONNECTED; wire [0:0]NLW_inst_ubrsvdout_out_UNCONNECTED; wire [0:0]NLW_inst_ubtxuart_out_UNCONNECTED; assign dmonitorout_out[16] = \ ; assign dmonitorout_out[15] = \ ; assign dmonitorout_out[14] = \ ; assign dmonitorout_out[13] = \ ; assign dmonitorout_out[12] = \ ; assign dmonitorout_out[11] = \ ; assign dmonitorout_out[10] = \ ; assign dmonitorout_out[9] = \ ; assign dmonitorout_out[8] = \ ; assign dmonitorout_out[7] = \ ; assign dmonitorout_out[6] = \ ; assign dmonitorout_out[5] = \ ; assign dmonitorout_out[4] = \ ; assign dmonitorout_out[3] = \ ; assign dmonitorout_out[2] = \ ; assign dmonitorout_out[1] = \ ; assign dmonitorout_out[0] = \ ; assign eyescandataerror_out[0] = \ ; assign gtwiz_reset_rx_cdr_stable_out[0] = \ ; assign rxbufstatus_out[2] = \^rxbufstatus_out [2]; assign rxbufstatus_out[1] = \ ; assign rxbufstatus_out[0] = \ ; assign rxdatavalid_out[1] = \ ; assign rxdatavalid_out[0] = \^rxdatavalid_out [0]; assign rxheader_out[5] = \ ; assign rxheader_out[4] = \ ; assign rxheader_out[3] = \ ; assign rxheader_out[2] = \ ; assign rxheader_out[1:0] = \^rxheader_out [1:0]; assign rxheadervalid_out[1] = \ ; assign rxheadervalid_out[0] = \^rxheadervalid_out [0]; assign rxprbserr_out[0] = \ ; assign rxresetdone_out[0] = \ ; assign rxstartofseq_out[1] = \ ; assign rxstartofseq_out[0] = \ ; assign txbufstatus_out[1] = \^txbufstatus_out [1]; assign txbufstatus_out[0] = \ ; assign txoutclkfabric_out[0] = \ ; assign txoutclkpcs_out[0] = \ ; assign txresetdone_out[0] = \ ; GND GND (.G(\ )); (* C_CHANNEL_ENABLE = "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_COMMON_SCALING_FACTOR = "1" *) (* C_CPLL_VCO_FREQUENCY = "2500.000000" *) (* C_ENABLE_COMMON_USRCLK = "0" *) (* C_FORCE_COMMONS = "0" *) (* C_FREERUN_FREQUENCY = "50.000000" *) (* C_GT_REV = "17" *) (* C_GT_TYPE = "0" *) (* C_INCLUDE_CPLL_CAL = "2" *) (* C_LOCATE_COMMON = "0" *) (* C_LOCATE_IN_SYSTEM_IBERT_CORE = "2" *) (* C_LOCATE_RESET_CONTROLLER = "0" *) (* C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER = "0" *) (* C_LOCATE_RX_USER_CLOCKING = "1" *) (* C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER = "0" *) (* C_LOCATE_TX_USER_CLOCKING = "1" *) (* C_LOCATE_USER_DATA_WIDTH_SIZING = "0" *) (* C_PCIE_CORECLK_FREQ = "250" *) (* C_PCIE_ENABLE = "0" *) (* C_RESET_CONTROLLER_INSTANCE_CTRL = "0" *) (* C_RESET_SEQUENCE_INTERVAL = "0" *) (* C_RX_BUFFBYPASS_MODE = "0" *) (* C_RX_BUFFER_BYPASS_INSTANCE_CTRL = "0" *) (* C_RX_BUFFER_MODE = "1" *) (* C_RX_CB_DISP = "8'b00000000" *) (* C_RX_CB_K = "8'b00000000" *) (* C_RX_CB_LEN_SEQ = "1" *) (* C_RX_CB_MAX_LEVEL = "1" *) (* C_RX_CB_NUM_SEQ = "0" *) (* C_RX_CB_VAL = "80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_RX_CC_DISP = "8'b00000000" *) (* C_RX_CC_ENABLE = "0" *) (* C_RX_CC_K = "8'b00000000" *) (* C_RX_CC_LEN_SEQ = "1" *) (* C_RX_CC_NUM_SEQ = "0" *) (* C_RX_CC_PERIODICITY = "5000" *) (* C_RX_CC_VAL = "80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_RX_COMMA_M_ENABLE = "0" *) (* C_RX_COMMA_M_VAL = "10'b1010000011" *) (* C_RX_COMMA_P_ENABLE = "0" *) (* C_RX_COMMA_P_VAL = "10'b0101111100" *) (* C_RX_DATA_DECODING = "2" *) (* C_RX_ENABLE = "1" *) (* C_RX_INT_DATA_WIDTH = "32" *) (* C_RX_LINE_RATE = "5.000000" *) (* C_RX_MASTER_CHANNEL_IDX = "96" *) (* C_RX_OUTCLK_BUFG_GT_DIV = "1" *) (* C_RX_OUTCLK_FREQUENCY = "156.250000" *) (* C_RX_OUTCLK_SOURCE = "1" *) (* C_RX_PLL_TYPE = "2" *) (* C_RX_RECCLK_OUTPUT = "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_RX_REFCLK_FREQUENCY = "125.000000" *) (* C_RX_SLIDE_MODE = "0" *) (* C_RX_USER_CLOCKING_CONTENTS = "0" *) (* C_RX_USER_CLOCKING_INSTANCE_CTRL = "0" *) (* C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK = "1" *) (* C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 = "1" *) (* C_RX_USER_CLOCKING_SOURCE = "0" *) (* C_RX_USER_DATA_WIDTH = "32" *) (* C_RX_USRCLK2_FREQUENCY = "156.250000" *) (* C_RX_USRCLK_FREQUENCY = "156.250000" *) (* C_SECONDARY_QPLL_ENABLE = "0" *) (* C_SECONDARY_QPLL_REFCLK_FREQUENCY = "257.812500" *) (* C_SIM_CPLL_CAL_BYPASS = "1" *) (* C_TOTAL_NUM_CHANNELS = "1" *) (* C_TOTAL_NUM_COMMONS = "0" *) (* C_TOTAL_NUM_COMMONS_EXAMPLE = "0" *) (* C_TXPROGDIV_FREQ_ENABLE = "0" *) (* C_TXPROGDIV_FREQ_SOURCE = "2" *) (* C_TXPROGDIV_FREQ_VAL = "156.250000" *) (* C_TX_BUFFBYPASS_MODE = "0" *) (* C_TX_BUFFER_BYPASS_INSTANCE_CTRL = "0" *) (* C_TX_BUFFER_MODE = "1" *) (* C_TX_DATA_ENCODING = "2" *) (* C_TX_ENABLE = "1" *) (* C_TX_INT_DATA_WIDTH = "32" *) (* C_TX_LINE_RATE = "5.000000" *) (* C_TX_MASTER_CHANNEL_IDX = "96" *) (* C_TX_OUTCLK_BUFG_GT_DIV = "1" *) (* C_TX_OUTCLK_FREQUENCY = "156.250000" *) (* C_TX_OUTCLK_SOURCE = "1" *) (* C_TX_PLL_TYPE = "2" *) (* C_TX_REFCLK_FREQUENCY = "125.000000" *) (* C_TX_USER_CLOCKING_CONTENTS = "0" *) (* C_TX_USER_CLOCKING_INSTANCE_CTRL = "0" *) (* C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK = "1" *) (* C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 = "2" *) (* C_TX_USER_CLOCKING_SOURCE = "0" *) (* C_TX_USER_DATA_WIDTH = "64" *) (* C_TX_USRCLK2_FREQUENCY = "78.125000" *) (* C_TX_USRCLK_FREQUENCY = "156.250000" *) (* C_USER_GTPOWERGOOD_DELAY_EN = "0" *) aurora_64b66b_0_aurora_64b66b_0_gt_gtwizard_top inst (.bgbypassb_in(1'b1), .bgmonitorenb_in(1'b1), .bgpdb_in(1'b1), .bgrcalovrd_in({1'b1,1'b1,1'b1,1'b1,1'b1}), .bgrcalovrdenb_in(1'b1), .bufgtce_out(NLW_inst_bufgtce_out_UNCONNECTED[2:0]), .bufgtcemask_out(NLW_inst_bufgtcemask_out_UNCONNECTED[2:0]), .bufgtdiv_out(NLW_inst_bufgtdiv_out_UNCONNECTED[8:0]), .bufgtreset_out(NLW_inst_bufgtreset_out_UNCONNECTED[2:0]), .bufgtrstmask_out(NLW_inst_bufgtrstmask_out_UNCONNECTED[2:0]), .cdrstepdir_in(1'b0), .cdrstepsq_in(1'b0), .cdrstepsx_in(1'b0), .cfgreset_in(1'b0), .clkrsvd0_in(1'b0), .clkrsvd1_in(1'b0), .cpllfbclklost_out(NLW_inst_cpllfbclklost_out_UNCONNECTED[0]), .cpllfreqlock_in(1'b0), .cplllock_out(cplllock_out), .cplllockdetclk_in(1'b0), .cplllocken_in(1'b1), .cpllpd_in(1'b0), .cpllrefclklost_out(NLW_inst_cpllrefclklost_out_UNCONNECTED[0]), .cpllrefclksel_in({1'b0,1'b0,1'b1}), .cpllreset_in(1'b0), .dmonfiforeset_in(1'b0), .dmonitorclk_in(1'b0), .dmonitorout_out(NLW_inst_dmonitorout_out_UNCONNECTED[16:0]), .dmonitoroutclk_out(NLW_inst_dmonitoroutclk_out_UNCONNECTED[0]), .drpaddr_common_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .drpaddr_in(drpaddr_in), .drpclk_common_in(1'b0), .drpclk_in(drpclk_in), .drpdi_common_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .drpdi_in(drpdi_in), .drpdo_common_out(NLW_inst_drpdo_common_out_UNCONNECTED[15:0]), .drpdo_out(drpdo_out), .drpen_common_in(1'b0), .drpen_in(drpen_in), .drprdy_common_out(NLW_inst_drprdy_common_out_UNCONNECTED[0]), .drprdy_out(drprdy_out), .drprst_in(1'b0), .drpwe_common_in(1'b0), .drpwe_in(drpwe_in), .elpcaldvorwren_in(1'b0), .elpcalpaorwren_in(1'b0), .evoddphicaldone_in(1'b0), .evoddphicalstart_in(1'b0), .evoddphidrden_in(1'b0), .evoddphidwren_in(1'b0), .evoddphixrden_in(1'b0), .evoddphixwren_in(1'b0), .eyescandataerror_out(NLW_inst_eyescandataerror_out_UNCONNECTED[0]), .eyescanmode_in(1'b0), .eyescanreset_in(1'b0), .eyescantrigger_in(1'b0), .freqos_in(1'b0), .gtgrefclk0_in(1'b0), .gtgrefclk1_in(1'b0), .gtgrefclk_in(1'b0), .gthrxn_in(gthrxn_in), .gthrxp_in(gthrxp_in), .gthtxn_out(gthtxn_out), .gthtxp_out(gthtxp_out), .gtnorthrefclk00_in(1'b0), .gtnorthrefclk01_in(1'b0), .gtnorthrefclk0_in(1'b0), .gtnorthrefclk10_in(1'b0), .gtnorthrefclk11_in(1'b0), .gtnorthrefclk1_in(1'b0), .gtpowergood_out(gtpowergood_out), .gtrefclk00_in(1'b0), .gtrefclk01_in(1'b0), .gtrefclk0_in(gtrefclk0_in), .gtrefclk10_in(1'b0), .gtrefclk11_in(1'b0), .gtrefclk1_in(1'b0), .gtrefclkmonitor_out(NLW_inst_gtrefclkmonitor_out_UNCONNECTED[0]), .gtresetsel_in(1'b0), .gtrsvd_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .gtrxreset_in(1'b0), .gtrxresetsel_in(1'b0), .gtsouthrefclk00_in(1'b0), .gtsouthrefclk01_in(1'b0), .gtsouthrefclk0_in(1'b0), .gtsouthrefclk10_in(1'b0), .gtsouthrefclk11_in(1'b0), .gtsouthrefclk1_in(1'b0), .gttxreset_in(1'b0), .gttxresetsel_in(1'b0), .gtwiz_buffbypass_rx_done_out(NLW_inst_gtwiz_buffbypass_rx_done_out_UNCONNECTED[0]), .gtwiz_buffbypass_rx_error_out(NLW_inst_gtwiz_buffbypass_rx_error_out_UNCONNECTED[0]), .gtwiz_buffbypass_rx_reset_in(1'b0), .gtwiz_buffbypass_rx_start_user_in(1'b0), .gtwiz_buffbypass_tx_done_out(NLW_inst_gtwiz_buffbypass_tx_done_out_UNCONNECTED[0]), .gtwiz_buffbypass_tx_error_out(NLW_inst_gtwiz_buffbypass_tx_error_out_UNCONNECTED[0]), .gtwiz_buffbypass_tx_reset_in(1'b0), .gtwiz_buffbypass_tx_start_user_in(1'b0), .gtwiz_gthe3_cpll_cal_bufg_ce_in(1'b0), .gtwiz_gthe3_cpll_cal_cnt_tol_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .gtwiz_gthe3_cpll_cal_txoutclk_period_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .gtwiz_gthe4_cpll_cal_bufg_ce_in(1'b0), .gtwiz_gthe4_cpll_cal_cnt_tol_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .gtwiz_gthe4_cpll_cal_txoutclk_period_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .gtwiz_gtye4_cpll_cal_bufg_ce_in(1'b0), .gtwiz_gtye4_cpll_cal_cnt_tol_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .gtwiz_gtye4_cpll_cal_txoutclk_period_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .gtwiz_reset_all_in(1'b0), .gtwiz_reset_clk_freerun_in(1'b0), .gtwiz_reset_qpll0lock_in(1'b0), .gtwiz_reset_qpll0reset_out(NLW_inst_gtwiz_reset_qpll0reset_out_UNCONNECTED[0]), .gtwiz_reset_qpll1lock_in(1'b0), .gtwiz_reset_qpll1reset_out(NLW_inst_gtwiz_reset_qpll1reset_out_UNCONNECTED[0]), .gtwiz_reset_rx_cdr_stable_out(NLW_inst_gtwiz_reset_rx_cdr_stable_out_UNCONNECTED[0]), .gtwiz_reset_rx_datapath_in(gtwiz_reset_rx_datapath_in), .gtwiz_reset_rx_done_in(1'b0), .gtwiz_reset_rx_done_out(gtwiz_reset_rx_done_out), .gtwiz_reset_rx_pll_and_datapath_in(gtwiz_reset_rx_pll_and_datapath_in), .gtwiz_reset_tx_datapath_in(1'b0), .gtwiz_reset_tx_done_in(1'b0), .gtwiz_reset_tx_done_out(gtwiz_reset_tx_done_out), .gtwiz_reset_tx_pll_and_datapath_in(1'b0), .gtwiz_userclk_rx_active_in(gtwiz_userclk_rx_active_in), .gtwiz_userclk_rx_active_out(NLW_inst_gtwiz_userclk_rx_active_out_UNCONNECTED[0]), .gtwiz_userclk_rx_reset_in(1'b0), .gtwiz_userclk_rx_srcclk_out(NLW_inst_gtwiz_userclk_rx_srcclk_out_UNCONNECTED[0]), .gtwiz_userclk_rx_usrclk2_out(NLW_inst_gtwiz_userclk_rx_usrclk2_out_UNCONNECTED[0]), .gtwiz_userclk_rx_usrclk_out(NLW_inst_gtwiz_userclk_rx_usrclk_out_UNCONNECTED[0]), .gtwiz_userclk_tx_active_in(gtwiz_userclk_tx_active_in), .gtwiz_userclk_tx_active_out(NLW_inst_gtwiz_userclk_tx_active_out_UNCONNECTED[0]), .gtwiz_userclk_tx_reset_in(1'b0), .gtwiz_userclk_tx_srcclk_out(NLW_inst_gtwiz_userclk_tx_srcclk_out_UNCONNECTED[0]), .gtwiz_userclk_tx_usrclk2_out(NLW_inst_gtwiz_userclk_tx_usrclk2_out_UNCONNECTED[0]), .gtwiz_userclk_tx_usrclk_out(NLW_inst_gtwiz_userclk_tx_usrclk_out_UNCONNECTED[0]), .gtwiz_userdata_rx_out(gtwiz_userdata_rx_out), .gtwiz_userdata_tx_in(gtwiz_userdata_tx_in), .gtyrxn_in(1'b0), .gtyrxp_in(1'b0), .gtytxn_out(NLW_inst_gtytxn_out_UNCONNECTED[0]), .gtytxp_out(NLW_inst_gtytxp_out_UNCONNECTED[0]), .incpctrl_in(1'b0), .loopback_in(loopback_in), .looprsvd_in(1'b0), .lopt(lopt), .lopt_1(lopt_1), .lopt_2(lopt_2), .lopt_3(lopt_3), .lopt_4(lopt_4), .lopt_5(lopt_5), .lopt_6(lopt_6), .lopt_7(lopt_7), .lpbkrxtxseren_in(1'b0), .lpbktxrxseren_in(1'b0), .pcieeqrxeqadaptdone_in(1'b0), .pcierategen3_out(NLW_inst_pcierategen3_out_UNCONNECTED[0]), .pcierateidle_out(NLW_inst_pcierateidle_out_UNCONNECTED[0]), .pcierateqpll0_in(1'b0), .pcierateqpll1_in(1'b0), .pcierateqpllpd_out(NLW_inst_pcierateqpllpd_out_UNCONNECTED[1:0]), .pcierateqpllreset_out(NLW_inst_pcierateqpllreset_out_UNCONNECTED[1:0]), .pcierstidle_in(1'b0), .pciersttxsyncstart_in(1'b0), .pciesynctxsyncdone_out(NLW_inst_pciesynctxsyncdone_out_UNCONNECTED[0]), .pcieusergen3rdy_out(NLW_inst_pcieusergen3rdy_out_UNCONNECTED[0]), .pcieuserphystatusrst_out(NLW_inst_pcieuserphystatusrst_out_UNCONNECTED[0]), .pcieuserratedone_in(1'b0), .pcieuserratestart_out(NLW_inst_pcieuserratestart_out_UNCONNECTED[0]), .pcsrsvdin2_in({1'b0,1'b0,1'b0,1'b0,1'b0}), .pcsrsvdin_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .pcsrsvdout_out(NLW_inst_pcsrsvdout_out_UNCONNECTED[11:0]), .phystatus_out(NLW_inst_phystatus_out_UNCONNECTED[0]), .pinrsrvdas_out(NLW_inst_pinrsrvdas_out_UNCONNECTED[7:0]), .pmarsvd0_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .pmarsvd1_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .pmarsvdin_in({1'b0,1'b0,1'b0,1'b0,1'b0}), .pmarsvdout0_out(NLW_inst_pmarsvdout0_out_UNCONNECTED[7:0]), .pmarsvdout1_out(NLW_inst_pmarsvdout1_out_UNCONNECTED[7:0]), .powerpresent_out(NLW_inst_powerpresent_out_UNCONNECTED[0]), .qpll0clk_in(1'b0), .qpll0clkrsvd0_in(1'b0), .qpll0clkrsvd1_in(1'b0), .qpll0fbclklost_out(NLW_inst_qpll0fbclklost_out_UNCONNECTED[0]), .qpll0fbdiv_in(1'b0), .qpll0freqlock_in(1'b0), .qpll0lock_out(NLW_inst_qpll0lock_out_UNCONNECTED[0]), .qpll0lockdetclk_in(1'b0), .qpll0locken_in(1'b0), .qpll0outclk_out(NLW_inst_qpll0outclk_out_UNCONNECTED[0]), .qpll0outrefclk_out(NLW_inst_qpll0outrefclk_out_UNCONNECTED[0]), .qpll0pd_in(1'b1), .qpll0refclk_in(1'b0), .qpll0refclklost_out(NLW_inst_qpll0refclklost_out_UNCONNECTED[0]), .qpll0refclksel_in({1'b0,1'b0,1'b1}), .qpll0reset_in(1'b1), .qpll1clk_in(1'b0), .qpll1clkrsvd0_in(1'b0), .qpll1clkrsvd1_in(1'b0), .qpll1fbclklost_out(NLW_inst_qpll1fbclklost_out_UNCONNECTED[0]), .qpll1fbdiv_in(1'b0), .qpll1freqlock_in(1'b0), .qpll1lock_out(NLW_inst_qpll1lock_out_UNCONNECTED[0]), .qpll1lockdetclk_in(1'b0), .qpll1locken_in(1'b0), .qpll1outclk_out(NLW_inst_qpll1outclk_out_UNCONNECTED[0]), .qpll1outrefclk_out(NLW_inst_qpll1outrefclk_out_UNCONNECTED[0]), .qpll1pd_in(1'b1), .qpll1refclk_in(1'b0), .qpll1refclklost_out(NLW_inst_qpll1refclklost_out_UNCONNECTED[0]), .qpll1refclksel_in({1'b0,1'b0,1'b1}), .qpll1reset_in(1'b1), .qplldmonitor0_out(NLW_inst_qplldmonitor0_out_UNCONNECTED[7:0]), .qplldmonitor1_out(NLW_inst_qplldmonitor1_out_UNCONNECTED[7:0]), .qpllrsvd1_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .qpllrsvd2_in({1'b0,1'b0,1'b0,1'b0,1'b0}), .qpllrsvd3_in({1'b0,1'b0,1'b0,1'b0,1'b0}), .qpllrsvd4_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .rcalenb_in(1'b1), .refclkoutmonitor0_out(NLW_inst_refclkoutmonitor0_out_UNCONNECTED[0]), .refclkoutmonitor1_out(NLW_inst_refclkoutmonitor1_out_UNCONNECTED[0]), .resetexception_out(NLW_inst_resetexception_out_UNCONNECTED[0]), .resetovrd_in(1'b0), .rstclkentx_in(1'b0), .rx8b10ben_in(1'b0), .rxafecfoken_in(1'b0), .rxbufreset_in(1'b0), .rxbufstatus_out({\^rxbufstatus_out ,NLW_inst_rxbufstatus_out_UNCONNECTED[1:0]}), .rxbyteisaligned_out(NLW_inst_rxbyteisaligned_out_UNCONNECTED[0]), .rxbyterealign_out(NLW_inst_rxbyterealign_out_UNCONNECTED[0]), .rxcdrfreqreset_in(1'b0), .rxcdrhold_in(1'b0), .rxcdrlock_out(NLW_inst_rxcdrlock_out_UNCONNECTED[0]), .rxcdrovrden_in(rxcdrovrden_in), .rxcdrphdone_out(NLW_inst_rxcdrphdone_out_UNCONNECTED[0]), .rxcdrreset_in(1'b0), .rxcdrresetrsv_in(1'b0), .rxchanbondseq_out(NLW_inst_rxchanbondseq_out_UNCONNECTED[0]), .rxchanisaligned_out(NLW_inst_rxchanisaligned_out_UNCONNECTED[0]), .rxchanrealign_out(NLW_inst_rxchanrealign_out_UNCONNECTED[0]), .rxchbonden_in(1'b0), .rxchbondi_in({1'b0,1'b0,1'b0,1'b0,1'b0}), .rxchbondlevel_in({1'b0,1'b0,1'b0}), .rxchbondmaster_in(1'b0), .rxchbondo_out(NLW_inst_rxchbondo_out_UNCONNECTED[4:0]), .rxchbondslave_in(1'b0), .rxckcaldone_out(NLW_inst_rxckcaldone_out_UNCONNECTED[0]), .rxckcalreset_in(1'b0), .rxckcalstart_in(1'b0), .rxclkcorcnt_out(NLW_inst_rxclkcorcnt_out_UNCONNECTED[1:0]), .rxcominitdet_out(NLW_inst_rxcominitdet_out_UNCONNECTED[0]), .rxcommadet_out(NLW_inst_rxcommadet_out_UNCONNECTED[0]), .rxcommadeten_in(1'b0), .rxcomsasdet_out(NLW_inst_rxcomsasdet_out_UNCONNECTED[0]), .rxcomwakedet_out(NLW_inst_rxcomwakedet_out_UNCONNECTED[0]), .rxctrl0_out(NLW_inst_rxctrl0_out_UNCONNECTED[15:0]), .rxctrl1_out(NLW_inst_rxctrl1_out_UNCONNECTED[15:0]), .rxctrl2_out(NLW_inst_rxctrl2_out_UNCONNECTED[7:0]), .rxctrl3_out(NLW_inst_rxctrl3_out_UNCONNECTED[7:0]), .rxdata_out(NLW_inst_rxdata_out_UNCONNECTED[127:0]), .rxdataextendrsvd_out(NLW_inst_rxdataextendrsvd_out_UNCONNECTED[7:0]), .rxdatavalid_out({NLW_inst_rxdatavalid_out_UNCONNECTED[1],\^rxdatavalid_out }), .rxdccforcestart_in(1'b0), .rxdfeagcctrl_in({1'b0,1'b1}), .rxdfeagchold_in(1'b0), .rxdfeagcovrden_in(1'b0), .rxdfecfokfcnum_in(1'b0), .rxdfecfokfen_in(1'b0), .rxdfecfokfpulse_in(1'b0), .rxdfecfokhold_in(1'b0), .rxdfecfokovren_in(1'b0), .rxdfekhhold_in(1'b0), .rxdfekhovrden_in(1'b0), .rxdfelfhold_in(1'b0), .rxdfelfovrden_in(1'b0), .rxdfelpmreset_in(1'b0), .rxdfetap10hold_in(1'b0), .rxdfetap10ovrden_in(1'b0), .rxdfetap11hold_in(1'b0), .rxdfetap11ovrden_in(1'b0), .rxdfetap12hold_in(1'b0), .rxdfetap12ovrden_in(1'b0), .rxdfetap13hold_in(1'b0), .rxdfetap13ovrden_in(1'b0), .rxdfetap14hold_in(1'b0), .rxdfetap14ovrden_in(1'b0), .rxdfetap15hold_in(1'b0), .rxdfetap15ovrden_in(1'b0), .rxdfetap2hold_in(1'b0), .rxdfetap2ovrden_in(1'b0), .rxdfetap3hold_in(1'b0), .rxdfetap3ovrden_in(1'b0), .rxdfetap4hold_in(1'b0), .rxdfetap4ovrden_in(1'b0), .rxdfetap5hold_in(1'b0), .rxdfetap5ovrden_in(1'b0), .rxdfetap6hold_in(1'b0), .rxdfetap6ovrden_in(1'b0), .rxdfetap7hold_in(1'b0), .rxdfetap7ovrden_in(1'b0), .rxdfetap8hold_in(1'b0), .rxdfetap8ovrden_in(1'b0), .rxdfetap9hold_in(1'b0), .rxdfetap9ovrden_in(1'b0), .rxdfeuthold_in(1'b0), .rxdfeutovrden_in(1'b0), .rxdfevphold_in(1'b0), .rxdfevpovrden_in(1'b0), .rxdfevsen_in(1'b0), .rxdfexyden_in(1'b1), .rxdlybypass_in(1'b1), .rxdlyen_in(1'b0), .rxdlyovrden_in(1'b0), .rxdlysreset_in(1'b0), .rxdlysresetdone_out(NLW_inst_rxdlysresetdone_out_UNCONNECTED[0]), .rxelecidle_out(NLW_inst_rxelecidle_out_UNCONNECTED[0]), .rxelecidlemode_in({1'b1,1'b1}), .rxeqtraining_in(1'b0), .rxgearboxslip_in(rxgearboxslip_in), .rxheader_out({NLW_inst_rxheader_out_UNCONNECTED[5:2],\^rxheader_out }), .rxheadervalid_out({NLW_inst_rxheadervalid_out_UNCONNECTED[1],\^rxheadervalid_out }), .rxlatclk_in(1'b0), .rxlfpstresetdet_out(NLW_inst_rxlfpstresetdet_out_UNCONNECTED[0]), .rxlfpsu2lpexitdet_out(NLW_inst_rxlfpsu2lpexitdet_out_UNCONNECTED[0]), .rxlfpsu3wakedet_out(NLW_inst_rxlfpsu3wakedet_out_UNCONNECTED[0]), .rxlpmen_in(1'b0), .rxlpmgchold_in(1'b0), .rxlpmgcovrden_in(1'b0), .rxlpmhfhold_in(1'b0), .rxlpmhfovrden_in(1'b0), .rxlpmlfhold_in(1'b0), .rxlpmlfklovrden_in(1'b0), .rxlpmoshold_in(1'b0), .rxlpmosovrden_in(1'b0), .rxmcommaalignen_in(1'b0), .rxmonitorout_out(NLW_inst_rxmonitorout_out_UNCONNECTED[6:0]), .rxmonitorsel_in({1'b0,1'b0}), .rxoobreset_in(1'b0), .rxoscalreset_in(1'b0), .rxoshold_in(1'b0), .rxosintcfg_in({1'b1,1'b1,1'b0,1'b1}), .rxosintdone_out(NLW_inst_rxosintdone_out_UNCONNECTED[0]), .rxosinten_in(1'b1), .rxosinthold_in(1'b0), .rxosintovrden_in(1'b0), .rxosintstarted_out(NLW_inst_rxosintstarted_out_UNCONNECTED[0]), .rxosintstrobe_in(1'b0), .rxosintstrobedone_out(NLW_inst_rxosintstrobedone_out_UNCONNECTED[0]), .rxosintstrobestarted_out(NLW_inst_rxosintstrobestarted_out_UNCONNECTED[0]), .rxosinttestovrden_in(1'b0), .rxosovrden_in(1'b0), .rxoutclk_out(rxoutclk_out), .rxoutclkfabric_out(NLW_inst_rxoutclkfabric_out_UNCONNECTED[0]), .rxoutclkpcs_out(NLW_inst_rxoutclkpcs_out_UNCONNECTED[0]), .rxoutclksel_in({1'b0,1'b1,1'b0}), .rxpcommaalignen_in(1'b0), .rxpcsreset_in(1'b0), .rxpd_in({1'b0,1'b0}), .rxphalign_in(1'b0), .rxphaligndone_out(NLW_inst_rxphaligndone_out_UNCONNECTED[0]), .rxphalignen_in(1'b0), .rxphalignerr_out(NLW_inst_rxphalignerr_out_UNCONNECTED[0]), .rxphdlypd_in(1'b1), .rxphdlyreset_in(1'b0), .rxphovrden_in(1'b0), .rxpllclksel_in({1'b0,1'b0}), .rxpmareset_in(1'b0), .rxpmaresetdone_out(rxpmaresetdone_out), .rxpolarity_in(rxpolarity_in), .rxprbscntreset_in(1'b0), .rxprbserr_out(NLW_inst_rxprbserr_out_UNCONNECTED[0]), .rxprbslocked_out(NLW_inst_rxprbslocked_out_UNCONNECTED[0]), .rxprbssel_in({1'b0,1'b0,1'b0,1'b0}), .rxprgdivresetdone_out(NLW_inst_rxprgdivresetdone_out_UNCONNECTED[0]), .rxprogdivreset_in(1'b0), .rxqpien_in(1'b0), .rxqpisenn_out(NLW_inst_rxqpisenn_out_UNCONNECTED[0]), .rxqpisenp_out(NLW_inst_rxqpisenp_out_UNCONNECTED[0]), .rxrate_in({1'b0,1'b0,1'b0}), .rxratedone_out(NLW_inst_rxratedone_out_UNCONNECTED[0]), .rxratemode_in(1'b0), .rxrecclk0_sel_out(NLW_inst_rxrecclk0_sel_out_UNCONNECTED[1:0]), .rxrecclk0sel_out(NLW_inst_rxrecclk0sel_out_UNCONNECTED[0]), .rxrecclk1_sel_out(NLW_inst_rxrecclk1_sel_out_UNCONNECTED[1:0]), .rxrecclk1sel_out(NLW_inst_rxrecclk1sel_out_UNCONNECTED[0]), .rxrecclkout_out(NLW_inst_rxrecclkout_out_UNCONNECTED[0]), .rxresetdone_out(NLW_inst_rxresetdone_out_UNCONNECTED[0]), .rxslide_in(1'b0), .rxsliderdy_out(NLW_inst_rxsliderdy_out_UNCONNECTED[0]), .rxslipdone_out(NLW_inst_rxslipdone_out_UNCONNECTED[0]), .rxslipoutclk_in(1'b0), .rxslipoutclkrdy_out(NLW_inst_rxslipoutclkrdy_out_UNCONNECTED[0]), .rxslippma_in(1'b0), .rxslippmardy_out(NLW_inst_rxslippmardy_out_UNCONNECTED[0]), .rxstartofseq_out(NLW_inst_rxstartofseq_out_UNCONNECTED[1:0]), .rxstatus_out(NLW_inst_rxstatus_out_UNCONNECTED[2:0]), .rxsyncallin_in(1'b0), .rxsyncdone_out(NLW_inst_rxsyncdone_out_UNCONNECTED[0]), .rxsyncin_in(1'b0), .rxsyncmode_in(1'b0), .rxsyncout_out(NLW_inst_rxsyncout_out_UNCONNECTED[0]), .rxsysclksel_in({1'b0,1'b0}), .rxtermination_in(1'b0), .rxuserrdy_in(1'b1), .rxusrclk2_in(rxusrclk2_in), .rxusrclk_in(rxusrclk_in), .rxvalid_out(NLW_inst_rxvalid_out_UNCONNECTED[0]), .sdm0data_in(1'b0), .sdm0finalout_out(NLW_inst_sdm0finalout_out_UNCONNECTED[0]), .sdm0reset_in(1'b0), .sdm0testdata_out(NLW_inst_sdm0testdata_out_UNCONNECTED[0]), .sdm0toggle_in(1'b0), .sdm0width_in(1'b0), .sdm1data_in(1'b0), .sdm1finalout_out(NLW_inst_sdm1finalout_out_UNCONNECTED[0]), .sdm1reset_in(1'b0), .sdm1testdata_out(NLW_inst_sdm1testdata_out_UNCONNECTED[0]), .sdm1toggle_in(1'b0), .sdm1width_in(1'b0), .sigvalidclk_in(1'b0), .tcongpi_in(1'b0), .tcongpo_out(NLW_inst_tcongpo_out_UNCONNECTED[0]), .tconpowerup_in(1'b0), .tconreset_in(1'b0), .tconrsvdin1_in(1'b0), .tconrsvdout0_out(NLW_inst_tconrsvdout0_out_UNCONNECTED[0]), .tstin_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .tx8b10bbypass_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .tx8b10ben_in(1'b0), .txbufdiffctrl_in({1'b0,1'b0,1'b0}), .txbufstatus_out({\^txbufstatus_out ,NLW_inst_txbufstatus_out_UNCONNECTED[0]}), .txcomfinish_out(NLW_inst_txcomfinish_out_UNCONNECTED[0]), .txcominit_in(1'b0), .txcomsas_in(1'b0), .txcomwake_in(1'b0), .txctrl0_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .txctrl1_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .txctrl2_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .txdata_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .txdataextendrsvd_in({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .txdccdone_out(NLW_inst_txdccdone_out_UNCONNECTED[0]), .txdccforcestart_in(1'b0), .txdccreset_in(1'b0), .txdeemph_in(1'b0), .txdetectrx_in(1'b0), .txdiffctrl_in({1'b1,1'b0,1'b0,1'b0}), .txdiffpd_in(1'b0), .txdlybypass_in(1'b1), .txdlyen_in(1'b0), .txdlyhold_in(1'b0), .txdlyovrden_in(1'b0), .txdlysreset_in(1'b0), .txdlysresetdone_out(NLW_inst_txdlysresetdone_out_UNCONNECTED[0]), .txdlyupdown_in(1'b0), .txelecidle_in(1'b0), .txelforcestart_in(1'b0), .txheader_in({1'b0,1'b0,1'b0,1'b0,txheader_in[1:0]}), .txinhibit_in(1'b0), .txlatclk_in(1'b0), .txlfpstreset_in(1'b0), .txlfpsu2lpexit_in(1'b0), .txlfpsu3wake_in(1'b0), .txmaincursor_in({1'b1,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .txmargin_in({1'b0,1'b0,1'b0}), .txmuxdcdexhold_in(1'b0), .txmuxdcdorwren_in(1'b0), .txoneszeros_in(1'b0), .txoutclk_out(txoutclk_out), .txoutclkfabric_out(NLW_inst_txoutclkfabric_out_UNCONNECTED[0]), .txoutclkpcs_out(NLW_inst_txoutclkpcs_out_UNCONNECTED[0]), .txoutclksel_in({1'b0,1'b1,1'b0}), .txpcsreset_in(1'b0), .txpd_in({1'b0,1'b0}), .txpdelecidlemode_in(1'b0), .txphalign_in(1'b0), .txphaligndone_out(NLW_inst_txphaligndone_out_UNCONNECTED[0]), .txphalignen_in(1'b0), .txphdlypd_in(1'b1), .txphdlyreset_in(1'b0), .txphdlytstclk_in(1'b0), .txphinit_in(1'b0), .txphinitdone_out(NLW_inst_txphinitdone_out_UNCONNECTED[0]), .txphovrden_in(1'b0), .txpippmen_in(1'b0), .txpippmovrden_in(1'b0), .txpippmpd_in(1'b0), .txpippmsel_in(1'b0), .txpippmstepsize_in({1'b0,1'b0,1'b0,1'b0,1'b0}), .txpisopd_in(1'b0), .txpllclksel_in({1'b0,1'b0}), .txpmareset_in(1'b0), .txpmaresetdone_out(txpmaresetdone_out), .txpolarity_in(1'b0), .txpostcursor_in({1'b0,1'b0,1'b0,1'b0,1'b0}), .txpostcursorinv_in(1'b0), .txprbsforceerr_in(1'b0), .txprbssel_in({1'b0,1'b0,1'b0,1'b0}), .txprecursor_in({1'b0,1'b0,1'b0,1'b0,1'b0}), .txprecursorinv_in(1'b0), .txprgdivresetdone_out(NLW_inst_txprgdivresetdone_out_UNCONNECTED[0]), .txprogdivreset_in(1'b0), .txqpibiasen_in(1'b0), .txqpisenn_out(NLW_inst_txqpisenn_out_UNCONNECTED[0]), .txqpisenp_out(NLW_inst_txqpisenp_out_UNCONNECTED[0]), .txqpistrongpdown_in(1'b0), .txqpiweakpup_in(1'b0), .txrate_in({1'b0,1'b0,1'b0}), .txratedone_out(NLW_inst_txratedone_out_UNCONNECTED[0]), .txratemode_in(1'b0), .txresetdone_out(NLW_inst_txresetdone_out_UNCONNECTED[0]), .txsequence_in(txsequence_in), .txswing_in(1'b0), .txsyncallin_in(1'b0), .txsyncdone_out(NLW_inst_txsyncdone_out_UNCONNECTED[0]), .txsyncin_in(1'b0), .txsyncmode_in(1'b0), .txsyncout_out(NLW_inst_txsyncout_out_UNCONNECTED[0]), .txsysclksel_in({1'b0,1'b0}), .txuserrdy_in(1'b1), .txusrclk2_in(txusrclk2_in), .txusrclk_in(txusrclk_in), .ubcfgstreamen_in(1'b0), .ubdaddr_out(NLW_inst_ubdaddr_out_UNCONNECTED[0]), .ubden_out(NLW_inst_ubden_out_UNCONNECTED[0]), .ubdi_out(NLW_inst_ubdi_out_UNCONNECTED[0]), .ubdo_in(1'b0), .ubdrdy_in(1'b0), .ubdwe_out(NLW_inst_ubdwe_out_UNCONNECTED[0]), .ubenable_in(1'b0), .ubgpi_in(1'b0), .ubintr_in(1'b0), .ubiolmbrst_in(1'b0), .ubmbrst_in(1'b0), .ubmdmcapture_in(1'b0), .ubmdmdbgrst_in(1'b0), .ubmdmdbgupdate_in(1'b0), .ubmdmregen_in(1'b0), .ubmdmshift_in(1'b0), .ubmdmsysrst_in(1'b0), .ubmdmtck_in(1'b0), .ubmdmtdi_in(1'b0), .ubmdmtdo_out(NLW_inst_ubmdmtdo_out_UNCONNECTED[0]), .ubrsvdout_out(NLW_inst_ubrsvdout_out_UNCONNECTED[0]), .ubtxuart_out(NLW_inst_ubtxuart_out_UNCONNECTED[0])); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_gt_gthe3_channel_wrapper" *) module aurora_64b66b_0_aurora_64b66b_0_gt_gthe3_channel_wrapper (cplllock_out, drprdy_out, gthtxn_out, gthtxp_out, gtpowergood_out, rxcdrlock_out, rxoutclk_out, rxpmaresetdone_out, rxresetdone_out, txoutclk_out, txpmaresetdone_out, txresetdone_out, gtwiz_userdata_rx_out, drpdo_out, rxdatavalid_out, rxheadervalid_out, txbufstatus_out, rxbufstatus_out, rxheader_out, rst_in0, \gen_gtwizard_gthe3.cpllpd_ch_int , drpclk_in, drpen_in, drpwe_in, gthrxn_in, gthrxp_in, gtrefclk0_in, \gen_gtwizard_gthe3.gtrxreset_int , \gen_gtwizard_gthe3.gttxreset_int , rxcdrovrden_in, rxgearboxslip_in, rxpolarity_in, \gen_gtwizard_gthe3.rxprogdivreset_int , \gen_gtwizard_gthe3.rxuserrdy_int , rxusrclk_in, rxusrclk2_in, \gen_gtwizard_gthe3.txprogdivreset_int , \gen_gtwizard_gthe3.txuserrdy_int , txusrclk_in, txusrclk2_in, gtwiz_userdata_tx_in, drpdi_in, loopback_in, txheader_in, txsequence_in, drpaddr_in, lopt, lopt_1, lopt_2, lopt_3, lopt_4, lopt_5, lopt_6, lopt_7); output [0:0]cplllock_out; output [0:0]drprdy_out; output [0:0]gthtxn_out; output [0:0]gthtxp_out; output [0:0]gtpowergood_out; output [0:0]rxcdrlock_out; output [0:0]rxoutclk_out; output [0:0]rxpmaresetdone_out; output [0:0]rxresetdone_out; output [0:0]txoutclk_out; output [0:0]txpmaresetdone_out; output [0:0]txresetdone_out; output [31:0]gtwiz_userdata_rx_out; output [15:0]drpdo_out; output [0:0]rxdatavalid_out; output [0:0]rxheadervalid_out; output [0:0]txbufstatus_out; output [0:0]rxbufstatus_out; output [1:0]rxheader_out; output rst_in0; input \gen_gtwizard_gthe3.cpllpd_ch_int ; input [0:0]drpclk_in; input [0:0]drpen_in; input [0:0]drpwe_in; input [0:0]gthrxn_in; input [0:0]gthrxp_in; input [0:0]gtrefclk0_in; input \gen_gtwizard_gthe3.gtrxreset_int ; input \gen_gtwizard_gthe3.gttxreset_int ; input [0:0]rxcdrovrden_in; input [0:0]rxgearboxslip_in; input [0:0]rxpolarity_in; input \gen_gtwizard_gthe3.rxprogdivreset_int ; input \gen_gtwizard_gthe3.rxuserrdy_int ; input [0:0]rxusrclk_in; input [0:0]rxusrclk2_in; input \gen_gtwizard_gthe3.txprogdivreset_int ; input \gen_gtwizard_gthe3.txuserrdy_int ; input [0:0]txusrclk_in; input [0:0]txusrclk2_in; input [63:0]gtwiz_userdata_tx_in; input [15:0]drpdi_in; input [2:0]loopback_in; input [1:0]txheader_in; input [6:0]txsequence_in; input [8:0]drpaddr_in; input lopt; input lopt_1; output lopt_2; output lopt_3; input lopt_4; input lopt_5; output lopt_6; output lopt_7; wire [0:0]cplllock_out; wire [8:0]drpaddr_in; wire [0:0]drpclk_in; wire [15:0]drpdi_in; wire [15:0]drpdo_out; wire [0:0]drpen_in; wire [0:0]drprdy_out; wire [0:0]drpwe_in; wire \gen_gtwizard_gthe3.cpllpd_ch_int ; wire \gen_gtwizard_gthe3.gtrxreset_int ; wire \gen_gtwizard_gthe3.gttxreset_int ; wire \gen_gtwizard_gthe3.rxprogdivreset_int ; wire \gen_gtwizard_gthe3.rxuserrdy_int ; wire \gen_gtwizard_gthe3.txprogdivreset_int ; wire \gen_gtwizard_gthe3.txuserrdy_int ; wire [0:0]gthrxn_in; wire [0:0]gthrxp_in; wire [0:0]gthtxn_out; wire [0:0]gthtxp_out; wire [0:0]gtpowergood_out; wire [0:0]gtrefclk0_in; wire [31:0]gtwiz_userdata_rx_out; wire [63:0]gtwiz_userdata_tx_in; wire [2:0]loopback_in; wire lopt; wire lopt_1; wire lopt_2; wire lopt_3; wire lopt_4; wire lopt_5; wire lopt_6; wire lopt_7; wire rst_in0; wire [0:0]rxbufstatus_out; wire [0:0]rxcdrlock_out; wire [0:0]rxcdrovrden_in; wire [0:0]rxdatavalid_out; wire [0:0]rxgearboxslip_in; wire [1:0]rxheader_out; wire [0:0]rxheadervalid_out; wire [0:0]rxoutclk_out; wire [0:0]rxpmaresetdone_out; wire [0:0]rxpolarity_in; wire [0:0]rxresetdone_out; wire [0:0]rxusrclk2_in; wire [0:0]rxusrclk_in; wire [0:0]txbufstatus_out; wire [1:0]txheader_in; wire [0:0]txoutclk_out; wire [0:0]txpmaresetdone_out; wire [0:0]txresetdone_out; wire [6:0]txsequence_in; wire [0:0]txusrclk2_in; wire [0:0]txusrclk_in; aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_gthe3_channel channel_inst (.cplllock_out(cplllock_out), .drpaddr_in(drpaddr_in), .drpclk_in(drpclk_in), .drpdi_in(drpdi_in), .drpdo_out(drpdo_out), .drpen_in(drpen_in), .drprdy_out(drprdy_out), .drpwe_in(drpwe_in), .\gen_gtwizard_gthe3.cpllpd_ch_int (\gen_gtwizard_gthe3.cpllpd_ch_int ), .\gen_gtwizard_gthe3.gtrxreset_int (\gen_gtwizard_gthe3.gtrxreset_int ), .\gen_gtwizard_gthe3.gttxreset_int (\gen_gtwizard_gthe3.gttxreset_int ), .\gen_gtwizard_gthe3.rxprogdivreset_int (\gen_gtwizard_gthe3.rxprogdivreset_int ), .\gen_gtwizard_gthe3.rxuserrdy_int (\gen_gtwizard_gthe3.rxuserrdy_int ), .\gen_gtwizard_gthe3.txprogdivreset_int (\gen_gtwizard_gthe3.txprogdivreset_int ), .\gen_gtwizard_gthe3.txuserrdy_int (\gen_gtwizard_gthe3.txuserrdy_int ), .gthrxn_in(gthrxn_in), .gthrxp_in(gthrxp_in), .gthtxn_out(gthtxn_out), .gthtxp_out(gthtxp_out), .gtpowergood_out(gtpowergood_out), .gtrefclk0_in(gtrefclk0_in), .gtwiz_userdata_rx_out(gtwiz_userdata_rx_out), .gtwiz_userdata_tx_in(gtwiz_userdata_tx_in), .loopback_in(loopback_in), .lopt(lopt), .lopt_1(lopt_1), .lopt_2(lopt_2), .lopt_3(lopt_3), .lopt_4(lopt_4), .lopt_5(lopt_5), .lopt_6(lopt_6), .lopt_7(lopt_7), .rst_in0(rst_in0), .rxbufstatus_out(rxbufstatus_out), .rxcdrlock_out(rxcdrlock_out), .rxcdrovrden_in(rxcdrovrden_in), .rxdatavalid_out(rxdatavalid_out), .rxgearboxslip_in(rxgearboxslip_in), .rxheader_out(rxheader_out), .rxheadervalid_out(rxheadervalid_out), .rxoutclk_out(rxoutclk_out), .rxpmaresetdone_out(rxpmaresetdone_out), .rxpolarity_in(rxpolarity_in), .rxresetdone_out(rxresetdone_out), .rxusrclk2_in(rxusrclk2_in), .rxusrclk_in(rxusrclk_in), .txbufstatus_out(txbufstatus_out), .txheader_in(txheader_in), .txoutclk_out(txoutclk_out), .txpmaresetdone_out(txpmaresetdone_out), .txresetdone_out(txresetdone_out), .txsequence_in(txsequence_in), .txusrclk2_in(txusrclk2_in), .txusrclk_in(txusrclk_in)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_gt_gtwizard_gthe3" *) module aurora_64b66b_0_aurora_64b66b_0_gt_gtwizard_gthe3 (cplllock_out, drprdy_out, gthtxn_out, gthtxp_out, gtpowergood_out, rxoutclk_out, rxpmaresetdone_out, txoutclk_out, txpmaresetdone_out, gtwiz_userdata_rx_out, drpdo_out, rxdatavalid_out, rxheadervalid_out, txbufstatus_out, rxbufstatus_out, rxheader_out, gtwiz_reset_tx_done_out, gtwiz_reset_rx_done_out, drpclk_in, drpen_in, drpwe_in, gthrxn_in, gthrxp_in, gtrefclk0_in, rxcdrovrden_in, rxgearboxslip_in, rxpolarity_in, rxusrclk_in, rxusrclk2_in, txusrclk_in, txusrclk2_in, gtwiz_userdata_tx_in, drpdi_in, loopback_in, txheader_in, txsequence_in, drpaddr_in, gtwiz_userclk_tx_active_in, gtwiz_userclk_rx_active_in, gtwiz_reset_rx_pll_and_datapath_in, gtwiz_reset_rx_datapath_in, lopt, lopt_1, lopt_2, lopt_3, lopt_4, lopt_5, lopt_6, lopt_7); output [0:0]cplllock_out; output [0:0]drprdy_out; output [0:0]gthtxn_out; output [0:0]gthtxp_out; output [0:0]gtpowergood_out; output [0:0]rxoutclk_out; output [0:0]rxpmaresetdone_out; output [0:0]txoutclk_out; output [0:0]txpmaresetdone_out; output [31:0]gtwiz_userdata_rx_out; output [15:0]drpdo_out; output [0:0]rxdatavalid_out; output [0:0]rxheadervalid_out; output [0:0]txbufstatus_out; output [0:0]rxbufstatus_out; output [1:0]rxheader_out; output [0:0]gtwiz_reset_tx_done_out; output [0:0]gtwiz_reset_rx_done_out; input [0:0]drpclk_in; input [0:0]drpen_in; input [0:0]drpwe_in; input [0:0]gthrxn_in; input [0:0]gthrxp_in; input [0:0]gtrefclk0_in; input [0:0]rxcdrovrden_in; input [0:0]rxgearboxslip_in; input [0:0]rxpolarity_in; input [0:0]rxusrclk_in; input [0:0]rxusrclk2_in; input [0:0]txusrclk_in; input [0:0]txusrclk2_in; input [63:0]gtwiz_userdata_tx_in; input [15:0]drpdi_in; input [2:0]loopback_in; input [1:0]txheader_in; input [6:0]txsequence_in; input [8:0]drpaddr_in; input [0:0]gtwiz_userclk_tx_active_in; input [0:0]gtwiz_userclk_rx_active_in; input [0:0]gtwiz_reset_rx_pll_and_datapath_in; input [0:0]gtwiz_reset_rx_datapath_in; input lopt; input lopt_1; output lopt_2; output lopt_3; input lopt_4; input lopt_5; output lopt_6; output lopt_7; wire [0:0]cplllock_out; wire [8:0]drpaddr_in; wire [0:0]drpclk_in; wire [15:0]drpdi_in; wire [15:0]drpdo_out; wire [0:0]drpen_in; wire [0:0]drprdy_out; wire [0:0]drpwe_in; wire \gen_gtwizard_gthe3.cpllpd_ch_int ; wire \gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_11 ; wire \gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_5 ; wire \gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_8 ; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ; wire \gen_gtwizard_gthe3.gtrxreset_int ; wire \gen_gtwizard_gthe3.gttxreset_int ; wire \gen_gtwizard_gthe3.rxprogdivreset_int ; wire \gen_gtwizard_gthe3.rxuserrdy_int ; wire \gen_gtwizard_gthe3.txprogdivreset_int ; wire \gen_gtwizard_gthe3.txuserrdy_int ; wire [0:0]gthrxn_in; wire [0:0]gthrxp_in; wire [0:0]gthtxn_out; wire [0:0]gthtxp_out; wire [0:0]gtpowergood_out; wire [0:0]gtrefclk0_in; wire [0:0]gtwiz_reset_rx_datapath_in; wire [0:0]gtwiz_reset_rx_done_out; wire [0:0]gtwiz_reset_rx_pll_and_datapath_in; wire [0:0]gtwiz_reset_tx_done_out; wire [0:0]gtwiz_userclk_rx_active_in; wire [0:0]gtwiz_userclk_tx_active_in; wire [31:0]gtwiz_userdata_rx_out; wire [63:0]gtwiz_userdata_tx_in; wire [2:0]loopback_in; wire lopt; wire lopt_1; wire lopt_2; wire lopt_3; wire lopt_4; wire lopt_5; wire lopt_6; wire lopt_7; wire rst_in0; wire [0:0]rxbufstatus_out; wire [0:0]rxcdrovrden_in; wire [0:0]rxdatavalid_out; wire [0:0]rxgearboxslip_in; wire [1:0]rxheader_out; wire [0:0]rxheadervalid_out; wire [0:0]rxoutclk_out; wire [0:0]rxpmaresetdone_out; wire [0:0]rxpolarity_in; wire [0:0]rxusrclk2_in; wire [0:0]rxusrclk_in; wire [0:0]txbufstatus_out; wire [1:0]txheader_in; wire [0:0]txoutclk_out; wire [0:0]txpmaresetdone_out; wire [6:0]txsequence_in; wire [0:0]txusrclk2_in; wire [0:0]txusrclk_in; aurora_64b66b_0_aurora_64b66b_0_gt_gthe3_channel_wrapper \gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst (.cplllock_out(cplllock_out), .drpaddr_in(drpaddr_in), .drpclk_in(drpclk_in), .drpdi_in(drpdi_in), .drpdo_out(drpdo_out), .drpen_in(drpen_in), .drprdy_out(drprdy_out), .drpwe_in(drpwe_in), .\gen_gtwizard_gthe3.cpllpd_ch_int (\gen_gtwizard_gthe3.cpllpd_ch_int ), .\gen_gtwizard_gthe3.gtrxreset_int (\gen_gtwizard_gthe3.gtrxreset_int ), .\gen_gtwizard_gthe3.gttxreset_int (\gen_gtwizard_gthe3.gttxreset_int ), .\gen_gtwizard_gthe3.rxprogdivreset_int (\gen_gtwizard_gthe3.rxprogdivreset_int ), .\gen_gtwizard_gthe3.rxuserrdy_int (\gen_gtwizard_gthe3.rxuserrdy_int ), .\gen_gtwizard_gthe3.txprogdivreset_int (\gen_gtwizard_gthe3.txprogdivreset_int ), .\gen_gtwizard_gthe3.txuserrdy_int (\gen_gtwizard_gthe3.txuserrdy_int ), .gthrxn_in(gthrxn_in), .gthrxp_in(gthrxp_in), .gthtxn_out(gthtxn_out), .gthtxp_out(gthtxp_out), .gtpowergood_out(gtpowergood_out), .gtrefclk0_in(gtrefclk0_in), .gtwiz_userdata_rx_out(gtwiz_userdata_rx_out), .gtwiz_userdata_tx_in(gtwiz_userdata_tx_in), .loopback_in(loopback_in), .lopt(lopt), .lopt_1(lopt_1), .lopt_2(lopt_2), .lopt_3(lopt_3), .lopt_4(lopt_4), .lopt_5(lopt_5), .lopt_6(lopt_6), .lopt_7(lopt_7), .rst_in0(rst_in0), .rxbufstatus_out(rxbufstatus_out), .rxcdrlock_out(\gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_5 ), .rxcdrovrden_in(rxcdrovrden_in), .rxdatavalid_out(rxdatavalid_out), .rxgearboxslip_in(rxgearboxslip_in), .rxheader_out(rxheader_out), .rxheadervalid_out(rxheadervalid_out), .rxoutclk_out(rxoutclk_out), .rxpmaresetdone_out(rxpmaresetdone_out), .rxpolarity_in(rxpolarity_in), .rxresetdone_out(\gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_8 ), .rxusrclk2_in(rxusrclk2_in), .rxusrclk_in(rxusrclk_in), .txbufstatus_out(txbufstatus_out), .txheader_in(txheader_in), .txoutclk_out(txoutclk_out), .txpmaresetdone_out(txpmaresetdone_out), .txresetdone_out(\gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_11 ), .txsequence_in(txsequence_in), .txusrclk2_in(txusrclk2_in), .txusrclk_in(txusrclk_in)); aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gen_ch_xrd[0].bit_synchronizer_rxresetdone_inst (.drpclk_in(drpclk_in), .\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync (\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ), .rxresetdone_out(\gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_8 )); aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_30 \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gen_ch_xrd[0].bit_synchronizer_txresetdone_inst (.drpclk_in(drpclk_in), .\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync (\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ), .txresetdone_out(\gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_11 )); aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_gtwiz_reset \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_inst (.cplllock_out(cplllock_out), .drpclk_in(drpclk_in), .\gen_gtwizard_gthe3.cpllpd_ch_int (\gen_gtwizard_gthe3.cpllpd_ch_int ), .\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync (\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ), .\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync (\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ), .\gen_gtwizard_gthe3.gtrxreset_int (\gen_gtwizard_gthe3.gtrxreset_int ), .\gen_gtwizard_gthe3.gttxreset_int (\gen_gtwizard_gthe3.gttxreset_int ), .\gen_gtwizard_gthe3.rxprogdivreset_int (\gen_gtwizard_gthe3.rxprogdivreset_int ), .\gen_gtwizard_gthe3.rxuserrdy_int (\gen_gtwizard_gthe3.rxuserrdy_int ), .\gen_gtwizard_gthe3.txprogdivreset_int (\gen_gtwizard_gthe3.txprogdivreset_int ), .\gen_gtwizard_gthe3.txuserrdy_int (\gen_gtwizard_gthe3.txuserrdy_int ), .gtpowergood_out(gtpowergood_out), .gtwiz_reset_rx_datapath_in(gtwiz_reset_rx_datapath_in), .gtwiz_reset_rx_done_out(gtwiz_reset_rx_done_out), .gtwiz_reset_rx_pll_and_datapath_in(gtwiz_reset_rx_pll_and_datapath_in), .gtwiz_reset_tx_done_out(gtwiz_reset_tx_done_out), .gtwiz_userclk_rx_active_in(gtwiz_userclk_rx_active_in), .gtwiz_userclk_tx_active_in(gtwiz_userclk_tx_active_in), .rst_in0(rst_in0), .rxcdrlock_out(\gen_gtwizard_gthe3.gen_channel_container[24].gen_enabled_channel.gthe3_channel_wrapper_inst_n_5 ), .rxusrclk2_in(rxusrclk2_in), .txusrclk2_in(txusrclk2_in)); endmodule (* C_CHANNEL_ENABLE = "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_COMMON_SCALING_FACTOR = "1" *) (* C_CPLL_VCO_FREQUENCY = "2500.000000" *) (* C_ENABLE_COMMON_USRCLK = "0" *) (* C_FORCE_COMMONS = "0" *) (* C_FREERUN_FREQUENCY = "50.000000" *) (* C_GT_REV = "17" *) (* C_GT_TYPE = "0" *) (* C_INCLUDE_CPLL_CAL = "2" *) (* C_LOCATE_COMMON = "0" *) (* C_LOCATE_IN_SYSTEM_IBERT_CORE = "2" *) (* C_LOCATE_RESET_CONTROLLER = "0" *) (* C_LOCATE_RX_BUFFER_BYPASS_CONTROLLER = "0" *) (* C_LOCATE_RX_USER_CLOCKING = "1" *) (* C_LOCATE_TX_BUFFER_BYPASS_CONTROLLER = "0" *) (* C_LOCATE_TX_USER_CLOCKING = "1" *) (* C_LOCATE_USER_DATA_WIDTH_SIZING = "0" *) (* C_PCIE_CORECLK_FREQ = "250" *) (* C_PCIE_ENABLE = "0" *) (* C_RESET_CONTROLLER_INSTANCE_CTRL = "0" *) (* C_RESET_SEQUENCE_INTERVAL = "0" *) (* C_RX_BUFFBYPASS_MODE = "0" *) (* C_RX_BUFFER_BYPASS_INSTANCE_CTRL = "0" *) (* C_RX_BUFFER_MODE = "1" *) (* C_RX_CB_DISP = "8'b00000000" *) (* C_RX_CB_K = "8'b00000000" *) (* C_RX_CB_LEN_SEQ = "1" *) (* C_RX_CB_MAX_LEVEL = "1" *) (* C_RX_CB_NUM_SEQ = "0" *) (* C_RX_CB_VAL = "80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_RX_CC_DISP = "8'b00000000" *) (* C_RX_CC_ENABLE = "0" *) (* C_RX_CC_K = "8'b00000000" *) (* C_RX_CC_LEN_SEQ = "1" *) (* C_RX_CC_NUM_SEQ = "0" *) (* C_RX_CC_PERIODICITY = "5000" *) (* C_RX_CC_VAL = "80'b00000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_RX_COMMA_M_ENABLE = "0" *) (* C_RX_COMMA_M_VAL = "10'b1010000011" *) (* C_RX_COMMA_P_ENABLE = "0" *) (* C_RX_COMMA_P_VAL = "10'b0101111100" *) (* C_RX_DATA_DECODING = "2" *) (* C_RX_ENABLE = "1" *) (* C_RX_INT_DATA_WIDTH = "32" *) (* C_RX_LINE_RATE = "5.000000" *) (* C_RX_MASTER_CHANNEL_IDX = "96" *) (* C_RX_OUTCLK_BUFG_GT_DIV = "1" *) (* C_RX_OUTCLK_FREQUENCY = "156.250000" *) (* C_RX_OUTCLK_SOURCE = "1" *) (* C_RX_PLL_TYPE = "2" *) (* C_RX_RECCLK_OUTPUT = "192'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_RX_REFCLK_FREQUENCY = "125.000000" *) (* C_RX_SLIDE_MODE = "0" *) (* C_RX_USER_CLOCKING_CONTENTS = "0" *) (* C_RX_USER_CLOCKING_INSTANCE_CTRL = "0" *) (* C_RX_USER_CLOCKING_RATIO_FSRC_FUSRCLK = "1" *) (* C_RX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 = "1" *) (* C_RX_USER_CLOCKING_SOURCE = "0" *) (* C_RX_USER_DATA_WIDTH = "32" *) (* C_RX_USRCLK2_FREQUENCY = "156.250000" *) (* C_RX_USRCLK_FREQUENCY = "156.250000" *) (* C_SECONDARY_QPLL_ENABLE = "0" *) (* C_SECONDARY_QPLL_REFCLK_FREQUENCY = "257.812500" *) (* C_SIM_CPLL_CAL_BYPASS = "1" *) (* C_TOTAL_NUM_CHANNELS = "1" *) (* C_TOTAL_NUM_COMMONS = "0" *) (* C_TOTAL_NUM_COMMONS_EXAMPLE = "0" *) (* C_TXPROGDIV_FREQ_ENABLE = "0" *) (* C_TXPROGDIV_FREQ_SOURCE = "2" *) (* C_TXPROGDIV_FREQ_VAL = "156.250000" *) (* C_TX_BUFFBYPASS_MODE = "0" *) (* C_TX_BUFFER_BYPASS_INSTANCE_CTRL = "0" *) (* C_TX_BUFFER_MODE = "1" *) (* C_TX_DATA_ENCODING = "2" *) (* C_TX_ENABLE = "1" *) (* C_TX_INT_DATA_WIDTH = "32" *) (* C_TX_LINE_RATE = "5.000000" *) (* C_TX_MASTER_CHANNEL_IDX = "96" *) (* C_TX_OUTCLK_BUFG_GT_DIV = "1" *) (* C_TX_OUTCLK_FREQUENCY = "156.250000" *) (* C_TX_OUTCLK_SOURCE = "1" *) (* C_TX_PLL_TYPE = "2" *) (* C_TX_REFCLK_FREQUENCY = "125.000000" *) (* C_TX_USER_CLOCKING_CONTENTS = "0" *) (* C_TX_USER_CLOCKING_INSTANCE_CTRL = "0" *) (* C_TX_USER_CLOCKING_RATIO_FSRC_FUSRCLK = "1" *) (* C_TX_USER_CLOCKING_RATIO_FUSRCLK_FUSRCLK2 = "2" *) (* C_TX_USER_CLOCKING_SOURCE = "0" *) (* C_TX_USER_DATA_WIDTH = "64" *) (* C_TX_USRCLK2_FREQUENCY = "78.125000" *) (* C_TX_USRCLK_FREQUENCY = "156.250000" *) (* C_USER_GTPOWERGOOD_DELAY_EN = "0" *) (* ORIG_REF_NAME = "aurora_64b66b_0_gt_gtwizard_top" *) module aurora_64b66b_0_aurora_64b66b_0_gt_gtwizard_top (gtwiz_userclk_tx_reset_in, gtwiz_userclk_tx_active_in, gtwiz_userclk_tx_srcclk_out, gtwiz_userclk_tx_usrclk_out, gtwiz_userclk_tx_usrclk2_out, gtwiz_userclk_tx_active_out, gtwiz_userclk_rx_reset_in, gtwiz_userclk_rx_active_in, gtwiz_userclk_rx_srcclk_out, gtwiz_userclk_rx_usrclk_out, gtwiz_userclk_rx_usrclk2_out, gtwiz_userclk_rx_active_out, gtwiz_buffbypass_tx_reset_in, gtwiz_buffbypass_tx_start_user_in, gtwiz_buffbypass_tx_done_out, gtwiz_buffbypass_tx_error_out, gtwiz_buffbypass_rx_reset_in, gtwiz_buffbypass_rx_start_user_in, gtwiz_buffbypass_rx_done_out, gtwiz_buffbypass_rx_error_out, gtwiz_reset_clk_freerun_in, gtwiz_reset_all_in, gtwiz_reset_tx_pll_and_datapath_in, gtwiz_reset_tx_datapath_in, gtwiz_reset_rx_pll_and_datapath_in, gtwiz_reset_rx_datapath_in, gtwiz_reset_tx_done_in, gtwiz_reset_rx_done_in, gtwiz_reset_qpll0lock_in, gtwiz_reset_qpll1lock_in, gtwiz_reset_rx_cdr_stable_out, gtwiz_reset_tx_done_out, gtwiz_reset_rx_done_out, gtwiz_reset_qpll0reset_out, gtwiz_reset_qpll1reset_out, gtwiz_gthe3_cpll_cal_txoutclk_period_in, gtwiz_gthe3_cpll_cal_cnt_tol_in, gtwiz_gthe3_cpll_cal_bufg_ce_in, gtwiz_gthe4_cpll_cal_txoutclk_period_in, gtwiz_gthe4_cpll_cal_cnt_tol_in, gtwiz_gthe4_cpll_cal_bufg_ce_in, gtwiz_gtye4_cpll_cal_txoutclk_period_in, gtwiz_gtye4_cpll_cal_cnt_tol_in, gtwiz_gtye4_cpll_cal_bufg_ce_in, gtwiz_userdata_tx_in, gtwiz_userdata_rx_out, bgbypassb_in, bgmonitorenb_in, bgpdb_in, bgrcalovrd_in, bgrcalovrdenb_in, drpaddr_common_in, drpclk_common_in, drpdi_common_in, drpen_common_in, drpwe_common_in, gtgrefclk0_in, gtgrefclk1_in, gtnorthrefclk00_in, gtnorthrefclk01_in, gtnorthrefclk10_in, gtnorthrefclk11_in, gtrefclk00_in, gtrefclk01_in, gtrefclk10_in, gtrefclk11_in, gtsouthrefclk00_in, gtsouthrefclk01_in, gtsouthrefclk10_in, gtsouthrefclk11_in, pcierateqpll0_in, pcierateqpll1_in, pmarsvd0_in, pmarsvd1_in, qpll0clkrsvd0_in, qpll0clkrsvd1_in, qpll0fbdiv_in, qpll0lockdetclk_in, qpll0locken_in, qpll0pd_in, qpll0refclksel_in, qpll0reset_in, qpll1clkrsvd0_in, qpll1clkrsvd1_in, qpll1fbdiv_in, qpll1lockdetclk_in, qpll1locken_in, qpll1pd_in, qpll1refclksel_in, qpll1reset_in, qpllrsvd1_in, qpllrsvd2_in, qpllrsvd3_in, qpllrsvd4_in, rcalenb_in, sdm0data_in, sdm0reset_in, sdm0toggle_in, sdm0width_in, sdm1data_in, sdm1reset_in, sdm1toggle_in, sdm1width_in, tcongpi_in, tconpowerup_in, tconreset_in, tconrsvdin1_in, ubcfgstreamen_in, ubdo_in, ubdrdy_in, ubenable_in, ubgpi_in, ubintr_in, ubiolmbrst_in, ubmbrst_in, ubmdmcapture_in, ubmdmdbgrst_in, ubmdmdbgupdate_in, ubmdmregen_in, ubmdmshift_in, ubmdmsysrst_in, ubmdmtck_in, ubmdmtdi_in, drpdo_common_out, drprdy_common_out, pmarsvdout0_out, pmarsvdout1_out, qpll0fbclklost_out, qpll0lock_out, qpll0outclk_out, qpll0outrefclk_out, qpll0refclklost_out, qpll1fbclklost_out, qpll1lock_out, qpll1outclk_out, qpll1outrefclk_out, qpll1refclklost_out, qplldmonitor0_out, qplldmonitor1_out, refclkoutmonitor0_out, refclkoutmonitor1_out, rxrecclk0_sel_out, rxrecclk1_sel_out, rxrecclk0sel_out, rxrecclk1sel_out, sdm0finalout_out, sdm0testdata_out, sdm1finalout_out, sdm1testdata_out, tcongpo_out, tconrsvdout0_out, ubdaddr_out, ubden_out, ubdi_out, ubdwe_out, ubmdmtdo_out, ubrsvdout_out, ubtxuart_out, cdrstepdir_in, cdrstepsq_in, cdrstepsx_in, cfgreset_in, clkrsvd0_in, clkrsvd1_in, cpllfreqlock_in, cplllockdetclk_in, cplllocken_in, cpllpd_in, cpllrefclksel_in, cpllreset_in, dmonfiforeset_in, dmonitorclk_in, drpaddr_in, drpclk_in, drpdi_in, drpen_in, drprst_in, drpwe_in, elpcaldvorwren_in, elpcalpaorwren_in, evoddphicaldone_in, evoddphicalstart_in, evoddphidrden_in, evoddphidwren_in, evoddphixrden_in, evoddphixwren_in, eyescanmode_in, eyescanreset_in, eyescantrigger_in, freqos_in, gtgrefclk_in, gthrxn_in, gthrxp_in, gtnorthrefclk0_in, gtnorthrefclk1_in, gtrefclk0_in, gtrefclk1_in, gtresetsel_in, gtrsvd_in, gtrxreset_in, gtrxresetsel_in, gtsouthrefclk0_in, gtsouthrefclk1_in, gttxreset_in, gttxresetsel_in, incpctrl_in, gtyrxn_in, gtyrxp_in, loopback_in, looprsvd_in, lpbkrxtxseren_in, lpbktxrxseren_in, pcieeqrxeqadaptdone_in, pcierstidle_in, pciersttxsyncstart_in, pcieuserratedone_in, pcsrsvdin_in, pcsrsvdin2_in, pmarsvdin_in, qpll0clk_in, qpll0freqlock_in, qpll0refclk_in, qpll1clk_in, qpll1freqlock_in, qpll1refclk_in, resetovrd_in, rstclkentx_in, rx8b10ben_in, rxafecfoken_in, rxbufreset_in, rxcdrfreqreset_in, rxcdrhold_in, rxcdrovrden_in, rxcdrreset_in, rxcdrresetrsv_in, rxchbonden_in, rxchbondi_in, rxchbondlevel_in, rxchbondmaster_in, rxchbondslave_in, rxckcalreset_in, rxckcalstart_in, rxcommadeten_in, rxdfeagcctrl_in, rxdccforcestart_in, rxdfeagchold_in, rxdfeagcovrden_in, rxdfecfokfcnum_in, rxdfecfokfen_in, rxdfecfokfpulse_in, rxdfecfokhold_in, rxdfecfokovren_in, rxdfekhhold_in, rxdfekhovrden_in, rxdfelfhold_in, rxdfelfovrden_in, rxdfelpmreset_in, rxdfetap10hold_in, rxdfetap10ovrden_in, rxdfetap11hold_in, rxdfetap11ovrden_in, rxdfetap12hold_in, rxdfetap12ovrden_in, rxdfetap13hold_in, rxdfetap13ovrden_in, rxdfetap14hold_in, rxdfetap14ovrden_in, rxdfetap15hold_in, rxdfetap15ovrden_in, rxdfetap2hold_in, rxdfetap2ovrden_in, rxdfetap3hold_in, rxdfetap3ovrden_in, rxdfetap4hold_in, rxdfetap4ovrden_in, rxdfetap5hold_in, rxdfetap5ovrden_in, rxdfetap6hold_in, rxdfetap6ovrden_in, rxdfetap7hold_in, rxdfetap7ovrden_in, rxdfetap8hold_in, rxdfetap8ovrden_in, rxdfetap9hold_in, rxdfetap9ovrden_in, rxdfeuthold_in, rxdfeutovrden_in, rxdfevphold_in, rxdfevpovrden_in, rxdfevsen_in, rxdfexyden_in, rxdlybypass_in, rxdlyen_in, rxdlyovrden_in, rxdlysreset_in, rxelecidlemode_in, rxeqtraining_in, rxgearboxslip_in, rxlatclk_in, rxlpmen_in, rxlpmgchold_in, rxlpmgcovrden_in, rxlpmhfhold_in, rxlpmhfovrden_in, rxlpmlfhold_in, rxlpmlfklovrden_in, rxlpmoshold_in, rxlpmosovrden_in, rxmcommaalignen_in, rxmonitorsel_in, rxoobreset_in, rxoscalreset_in, rxoshold_in, rxosintcfg_in, rxosinten_in, rxosinthold_in, rxosintovrden_in, rxosintstrobe_in, rxosinttestovrden_in, rxosovrden_in, rxoutclksel_in, rxpcommaalignen_in, rxpcsreset_in, rxpd_in, rxphalign_in, rxphalignen_in, rxphdlypd_in, rxphdlyreset_in, rxphovrden_in, rxpllclksel_in, rxpmareset_in, rxpolarity_in, rxprbscntreset_in, rxprbssel_in, rxprogdivreset_in, rxqpien_in, rxrate_in, rxratemode_in, rxslide_in, rxslipoutclk_in, rxslippma_in, rxsyncallin_in, rxsyncin_in, rxsyncmode_in, rxsysclksel_in, rxtermination_in, rxuserrdy_in, rxusrclk_in, rxusrclk2_in, sigvalidclk_in, tstin_in, tx8b10bbypass_in, tx8b10ben_in, txbufdiffctrl_in, txcominit_in, txcomsas_in, txcomwake_in, txctrl0_in, txctrl1_in, txctrl2_in, txdata_in, txdataextendrsvd_in, txdccforcestart_in, txdccreset_in, txdeemph_in, txdetectrx_in, txdiffctrl_in, txdiffpd_in, txdlybypass_in, txdlyen_in, txdlyhold_in, txdlyovrden_in, txdlysreset_in, txdlyupdown_in, txelecidle_in, txelforcestart_in, txheader_in, txinhibit_in, txlatclk_in, txlfpstreset_in, txlfpsu2lpexit_in, txlfpsu3wake_in, txmaincursor_in, txmargin_in, txmuxdcdexhold_in, txmuxdcdorwren_in, txoneszeros_in, txoutclksel_in, txpcsreset_in, txpd_in, txpdelecidlemode_in, txphalign_in, txphalignen_in, txphdlypd_in, txphdlyreset_in, txphdlytstclk_in, txphinit_in, txphovrden_in, txpippmen_in, txpippmovrden_in, txpippmpd_in, txpippmsel_in, txpippmstepsize_in, txpisopd_in, txpllclksel_in, txpmareset_in, txpolarity_in, txpostcursor_in, txpostcursorinv_in, txprbsforceerr_in, txprbssel_in, txprecursor_in, txprecursorinv_in, txprogdivreset_in, txqpibiasen_in, txqpistrongpdown_in, txqpiweakpup_in, txrate_in, txratemode_in, txsequence_in, txswing_in, txsyncallin_in, txsyncin_in, txsyncmode_in, txsysclksel_in, txuserrdy_in, txusrclk_in, txusrclk2_in, bufgtce_out, bufgtcemask_out, bufgtdiv_out, bufgtreset_out, bufgtrstmask_out, cpllfbclklost_out, cplllock_out, cpllrefclklost_out, dmonitorout_out, dmonitoroutclk_out, drpdo_out, drprdy_out, eyescandataerror_out, gthtxn_out, gthtxp_out, gtpowergood_out, gtrefclkmonitor_out, gtytxn_out, gtytxp_out, pcierategen3_out, pcierateidle_out, pcierateqpllpd_out, pcierateqpllreset_out, pciesynctxsyncdone_out, pcieusergen3rdy_out, pcieuserphystatusrst_out, pcieuserratestart_out, pcsrsvdout_out, phystatus_out, pinrsrvdas_out, powerpresent_out, resetexception_out, rxbufstatus_out, rxbyteisaligned_out, rxbyterealign_out, rxcdrlock_out, rxcdrphdone_out, rxchanbondseq_out, rxchanisaligned_out, rxchanrealign_out, rxchbondo_out, rxckcaldone_out, rxclkcorcnt_out, rxcominitdet_out, rxcommadet_out, rxcomsasdet_out, rxcomwakedet_out, rxctrl0_out, rxctrl1_out, rxctrl2_out, rxctrl3_out, rxdata_out, rxdataextendrsvd_out, rxdatavalid_out, rxdlysresetdone_out, rxelecidle_out, rxheader_out, rxheadervalid_out, rxlfpstresetdet_out, rxlfpsu2lpexitdet_out, rxlfpsu3wakedet_out, rxmonitorout_out, rxosintdone_out, rxosintstarted_out, rxosintstrobedone_out, rxosintstrobestarted_out, rxoutclk_out, rxoutclkfabric_out, rxoutclkpcs_out, rxphaligndone_out, rxphalignerr_out, rxpmaresetdone_out, rxprbserr_out, rxprbslocked_out, rxprgdivresetdone_out, rxqpisenn_out, rxqpisenp_out, rxratedone_out, rxrecclkout_out, rxresetdone_out, rxsliderdy_out, rxslipdone_out, rxslipoutclkrdy_out, rxslippmardy_out, rxstartofseq_out, rxstatus_out, rxsyncdone_out, rxsyncout_out, rxvalid_out, txbufstatus_out, txcomfinish_out, txdccdone_out, txdlysresetdone_out, txoutclk_out, txoutclkfabric_out, txoutclkpcs_out, txphaligndone_out, txphinitdone_out, txpmaresetdone_out, txprgdivresetdone_out, txqpisenn_out, txqpisenp_out, txratedone_out, txresetdone_out, txsyncdone_out, txsyncout_out, lopt, lopt_1, lopt_2, lopt_3, lopt_4, lopt_5, lopt_6, lopt_7); input [0:0]gtwiz_userclk_tx_reset_in; input [0:0]gtwiz_userclk_tx_active_in; output [0:0]gtwiz_userclk_tx_srcclk_out; output [0:0]gtwiz_userclk_tx_usrclk_out; output [0:0]gtwiz_userclk_tx_usrclk2_out; output [0:0]gtwiz_userclk_tx_active_out; input [0:0]gtwiz_userclk_rx_reset_in; input [0:0]gtwiz_userclk_rx_active_in; output [0:0]gtwiz_userclk_rx_srcclk_out; output [0:0]gtwiz_userclk_rx_usrclk_out; output [0:0]gtwiz_userclk_rx_usrclk2_out; output [0:0]gtwiz_userclk_rx_active_out; input [0:0]gtwiz_buffbypass_tx_reset_in; input [0:0]gtwiz_buffbypass_tx_start_user_in; output [0:0]gtwiz_buffbypass_tx_done_out; output [0:0]gtwiz_buffbypass_tx_error_out; input [0:0]gtwiz_buffbypass_rx_reset_in; input [0:0]gtwiz_buffbypass_rx_start_user_in; output [0:0]gtwiz_buffbypass_rx_done_out; output [0:0]gtwiz_buffbypass_rx_error_out; input [0:0]gtwiz_reset_clk_freerun_in; input [0:0]gtwiz_reset_all_in; input [0:0]gtwiz_reset_tx_pll_and_datapath_in; input [0:0]gtwiz_reset_tx_datapath_in; input [0:0]gtwiz_reset_rx_pll_and_datapath_in; input [0:0]gtwiz_reset_rx_datapath_in; input [0:0]gtwiz_reset_tx_done_in; input [0:0]gtwiz_reset_rx_done_in; input [0:0]gtwiz_reset_qpll0lock_in; input [0:0]gtwiz_reset_qpll1lock_in; output [0:0]gtwiz_reset_rx_cdr_stable_out; output [0:0]gtwiz_reset_tx_done_out; output [0:0]gtwiz_reset_rx_done_out; output [0:0]gtwiz_reset_qpll0reset_out; output [0:0]gtwiz_reset_qpll1reset_out; input [17:0]gtwiz_gthe3_cpll_cal_txoutclk_period_in; input [17:0]gtwiz_gthe3_cpll_cal_cnt_tol_in; input [0:0]gtwiz_gthe3_cpll_cal_bufg_ce_in; input [17:0]gtwiz_gthe4_cpll_cal_txoutclk_period_in; input [17:0]gtwiz_gthe4_cpll_cal_cnt_tol_in; input [0:0]gtwiz_gthe4_cpll_cal_bufg_ce_in; input [17:0]gtwiz_gtye4_cpll_cal_txoutclk_period_in; input [17:0]gtwiz_gtye4_cpll_cal_cnt_tol_in; input [0:0]gtwiz_gtye4_cpll_cal_bufg_ce_in; input [63:0]gtwiz_userdata_tx_in; output [31:0]gtwiz_userdata_rx_out; input [0:0]bgbypassb_in; input [0:0]bgmonitorenb_in; input [0:0]bgpdb_in; input [4:0]bgrcalovrd_in; input [0:0]bgrcalovrdenb_in; input [8:0]drpaddr_common_in; input [0:0]drpclk_common_in; input [15:0]drpdi_common_in; input [0:0]drpen_common_in; input [0:0]drpwe_common_in; input [0:0]gtgrefclk0_in; input [0:0]gtgrefclk1_in; input [0:0]gtnorthrefclk00_in; input [0:0]gtnorthrefclk01_in; input [0:0]gtnorthrefclk10_in; input [0:0]gtnorthrefclk11_in; input [0:0]gtrefclk00_in; input [0:0]gtrefclk01_in; input [0:0]gtrefclk10_in; input [0:0]gtrefclk11_in; input [0:0]gtsouthrefclk00_in; input [0:0]gtsouthrefclk01_in; input [0:0]gtsouthrefclk10_in; input [0:0]gtsouthrefclk11_in; input [0:0]pcierateqpll0_in; input [0:0]pcierateqpll1_in; input [7:0]pmarsvd0_in; input [7:0]pmarsvd1_in; input [0:0]qpll0clkrsvd0_in; input [0:0]qpll0clkrsvd1_in; input [0:0]qpll0fbdiv_in; input [0:0]qpll0lockdetclk_in; input [0:0]qpll0locken_in; input [0:0]qpll0pd_in; input [2:0]qpll0refclksel_in; input [0:0]qpll0reset_in; input [0:0]qpll1clkrsvd0_in; input [0:0]qpll1clkrsvd1_in; input [0:0]qpll1fbdiv_in; input [0:0]qpll1lockdetclk_in; input [0:0]qpll1locken_in; input [0:0]qpll1pd_in; input [2:0]qpll1refclksel_in; input [0:0]qpll1reset_in; input [7:0]qpllrsvd1_in; input [4:0]qpllrsvd2_in; input [4:0]qpllrsvd3_in; input [7:0]qpllrsvd4_in; input [0:0]rcalenb_in; input [0:0]sdm0data_in; input [0:0]sdm0reset_in; input [0:0]sdm0toggle_in; input [0:0]sdm0width_in; input [0:0]sdm1data_in; input [0:0]sdm1reset_in; input [0:0]sdm1toggle_in; input [0:0]sdm1width_in; input [0:0]tcongpi_in; input [0:0]tconpowerup_in; input [0:0]tconreset_in; input [0:0]tconrsvdin1_in; input [0:0]ubcfgstreamen_in; input [0:0]ubdo_in; input [0:0]ubdrdy_in; input [0:0]ubenable_in; input [0:0]ubgpi_in; input [0:0]ubintr_in; input [0:0]ubiolmbrst_in; input [0:0]ubmbrst_in; input [0:0]ubmdmcapture_in; input [0:0]ubmdmdbgrst_in; input [0:0]ubmdmdbgupdate_in; input [0:0]ubmdmregen_in; input [0:0]ubmdmshift_in; input [0:0]ubmdmsysrst_in; input [0:0]ubmdmtck_in; input [0:0]ubmdmtdi_in; output [15:0]drpdo_common_out; output [0:0]drprdy_common_out; output [7:0]pmarsvdout0_out; output [7:0]pmarsvdout1_out; output [0:0]qpll0fbclklost_out; output [0:0]qpll0lock_out; output [0:0]qpll0outclk_out; output [0:0]qpll0outrefclk_out; output [0:0]qpll0refclklost_out; output [0:0]qpll1fbclklost_out; output [0:0]qpll1lock_out; output [0:0]qpll1outclk_out; output [0:0]qpll1outrefclk_out; output [0:0]qpll1refclklost_out; output [7:0]qplldmonitor0_out; output [7:0]qplldmonitor1_out; output [0:0]refclkoutmonitor0_out; output [0:0]refclkoutmonitor1_out; output [1:0]rxrecclk0_sel_out; output [1:0]rxrecclk1_sel_out; output [0:0]rxrecclk0sel_out; output [0:0]rxrecclk1sel_out; output [0:0]sdm0finalout_out; output [0:0]sdm0testdata_out; output [0:0]sdm1finalout_out; output [0:0]sdm1testdata_out; output [0:0]tcongpo_out; output [0:0]tconrsvdout0_out; output [0:0]ubdaddr_out; output [0:0]ubden_out; output [0:0]ubdi_out; output [0:0]ubdwe_out; output [0:0]ubmdmtdo_out; output [0:0]ubrsvdout_out; output [0:0]ubtxuart_out; input [0:0]cdrstepdir_in; input [0:0]cdrstepsq_in; input [0:0]cdrstepsx_in; input [0:0]cfgreset_in; input [0:0]clkrsvd0_in; input [0:0]clkrsvd1_in; input [0:0]cpllfreqlock_in; input [0:0]cplllockdetclk_in; input [0:0]cplllocken_in; input [0:0]cpllpd_in; input [2:0]cpllrefclksel_in; input [0:0]cpllreset_in; input [0:0]dmonfiforeset_in; input [0:0]dmonitorclk_in; input [8:0]drpaddr_in; input [0:0]drpclk_in; input [15:0]drpdi_in; input [0:0]drpen_in; input [0:0]drprst_in; input [0:0]drpwe_in; input [0:0]elpcaldvorwren_in; input [0:0]elpcalpaorwren_in; input [0:0]evoddphicaldone_in; input [0:0]evoddphicalstart_in; input [0:0]evoddphidrden_in; input [0:0]evoddphidwren_in; input [0:0]evoddphixrden_in; input [0:0]evoddphixwren_in; input [0:0]eyescanmode_in; input [0:0]eyescanreset_in; input [0:0]eyescantrigger_in; input [0:0]freqos_in; input [0:0]gtgrefclk_in; input [0:0]gthrxn_in; input [0:0]gthrxp_in; input [0:0]gtnorthrefclk0_in; input [0:0]gtnorthrefclk1_in; input [0:0]gtrefclk0_in; input [0:0]gtrefclk1_in; input [0:0]gtresetsel_in; input [15:0]gtrsvd_in; input [0:0]gtrxreset_in; input [0:0]gtrxresetsel_in; input [0:0]gtsouthrefclk0_in; input [0:0]gtsouthrefclk1_in; input [0:0]gttxreset_in; input [0:0]gttxresetsel_in; input [0:0]incpctrl_in; input [0:0]gtyrxn_in; input [0:0]gtyrxp_in; input [2:0]loopback_in; input [0:0]looprsvd_in; input [0:0]lpbkrxtxseren_in; input [0:0]lpbktxrxseren_in; input [0:0]pcieeqrxeqadaptdone_in; input [0:0]pcierstidle_in; input [0:0]pciersttxsyncstart_in; input [0:0]pcieuserratedone_in; input [15:0]pcsrsvdin_in; input [4:0]pcsrsvdin2_in; input [4:0]pmarsvdin_in; input [0:0]qpll0clk_in; input [0:0]qpll0freqlock_in; input [0:0]qpll0refclk_in; input [0:0]qpll1clk_in; input [0:0]qpll1freqlock_in; input [0:0]qpll1refclk_in; input [0:0]resetovrd_in; input [0:0]rstclkentx_in; input [0:0]rx8b10ben_in; input [0:0]rxafecfoken_in; input [0:0]rxbufreset_in; input [0:0]rxcdrfreqreset_in; input [0:0]rxcdrhold_in; input [0:0]rxcdrovrden_in; input [0:0]rxcdrreset_in; input [0:0]rxcdrresetrsv_in; input [0:0]rxchbonden_in; input [4:0]rxchbondi_in; input [2:0]rxchbondlevel_in; input [0:0]rxchbondmaster_in; input [0:0]rxchbondslave_in; input [0:0]rxckcalreset_in; input [0:0]rxckcalstart_in; input [0:0]rxcommadeten_in; input [1:0]rxdfeagcctrl_in; input [0:0]rxdccforcestart_in; input [0:0]rxdfeagchold_in; input [0:0]rxdfeagcovrden_in; input [0:0]rxdfecfokfcnum_in; input [0:0]rxdfecfokfen_in; input [0:0]rxdfecfokfpulse_in; input [0:0]rxdfecfokhold_in; input [0:0]rxdfecfokovren_in; input [0:0]rxdfekhhold_in; input [0:0]rxdfekhovrden_in; input [0:0]rxdfelfhold_in; input [0:0]rxdfelfovrden_in; input [0:0]rxdfelpmreset_in; input [0:0]rxdfetap10hold_in; input [0:0]rxdfetap10ovrden_in; input [0:0]rxdfetap11hold_in; input [0:0]rxdfetap11ovrden_in; input [0:0]rxdfetap12hold_in; input [0:0]rxdfetap12ovrden_in; input [0:0]rxdfetap13hold_in; input [0:0]rxdfetap13ovrden_in; input [0:0]rxdfetap14hold_in; input [0:0]rxdfetap14ovrden_in; input [0:0]rxdfetap15hold_in; input [0:0]rxdfetap15ovrden_in; input [0:0]rxdfetap2hold_in; input [0:0]rxdfetap2ovrden_in; input [0:0]rxdfetap3hold_in; input [0:0]rxdfetap3ovrden_in; input [0:0]rxdfetap4hold_in; input [0:0]rxdfetap4ovrden_in; input [0:0]rxdfetap5hold_in; input [0:0]rxdfetap5ovrden_in; input [0:0]rxdfetap6hold_in; input [0:0]rxdfetap6ovrden_in; input [0:0]rxdfetap7hold_in; input [0:0]rxdfetap7ovrden_in; input [0:0]rxdfetap8hold_in; input [0:0]rxdfetap8ovrden_in; input [0:0]rxdfetap9hold_in; input [0:0]rxdfetap9ovrden_in; input [0:0]rxdfeuthold_in; input [0:0]rxdfeutovrden_in; input [0:0]rxdfevphold_in; input [0:0]rxdfevpovrden_in; input [0:0]rxdfevsen_in; input [0:0]rxdfexyden_in; input [0:0]rxdlybypass_in; input [0:0]rxdlyen_in; input [0:0]rxdlyovrden_in; input [0:0]rxdlysreset_in; input [1:0]rxelecidlemode_in; input [0:0]rxeqtraining_in; input [0:0]rxgearboxslip_in; input [0:0]rxlatclk_in; input [0:0]rxlpmen_in; input [0:0]rxlpmgchold_in; input [0:0]rxlpmgcovrden_in; input [0:0]rxlpmhfhold_in; input [0:0]rxlpmhfovrden_in; input [0:0]rxlpmlfhold_in; input [0:0]rxlpmlfklovrden_in; input [0:0]rxlpmoshold_in; input [0:0]rxlpmosovrden_in; input [0:0]rxmcommaalignen_in; input [1:0]rxmonitorsel_in; input [0:0]rxoobreset_in; input [0:0]rxoscalreset_in; input [0:0]rxoshold_in; input [3:0]rxosintcfg_in; input [0:0]rxosinten_in; input [0:0]rxosinthold_in; input [0:0]rxosintovrden_in; input [0:0]rxosintstrobe_in; input [0:0]rxosinttestovrden_in; input [0:0]rxosovrden_in; input [2:0]rxoutclksel_in; input [0:0]rxpcommaalignen_in; input [0:0]rxpcsreset_in; input [1:0]rxpd_in; input [0:0]rxphalign_in; input [0:0]rxphalignen_in; input [0:0]rxphdlypd_in; input [0:0]rxphdlyreset_in; input [0:0]rxphovrden_in; input [1:0]rxpllclksel_in; input [0:0]rxpmareset_in; input [0:0]rxpolarity_in; input [0:0]rxprbscntreset_in; input [3:0]rxprbssel_in; input [0:0]rxprogdivreset_in; input [0:0]rxqpien_in; input [2:0]rxrate_in; input [0:0]rxratemode_in; input [0:0]rxslide_in; input [0:0]rxslipoutclk_in; input [0:0]rxslippma_in; input [0:0]rxsyncallin_in; input [0:0]rxsyncin_in; input [0:0]rxsyncmode_in; input [1:0]rxsysclksel_in; input [0:0]rxtermination_in; input [0:0]rxuserrdy_in; input [0:0]rxusrclk_in; input [0:0]rxusrclk2_in; input [0:0]sigvalidclk_in; input [19:0]tstin_in; input [7:0]tx8b10bbypass_in; input [0:0]tx8b10ben_in; input [2:0]txbufdiffctrl_in; input [0:0]txcominit_in; input [0:0]txcomsas_in; input [0:0]txcomwake_in; input [15:0]txctrl0_in; input [15:0]txctrl1_in; input [7:0]txctrl2_in; input [127:0]txdata_in; input [7:0]txdataextendrsvd_in; input [0:0]txdccforcestart_in; input [0:0]txdccreset_in; input [0:0]txdeemph_in; input [0:0]txdetectrx_in; input [3:0]txdiffctrl_in; input [0:0]txdiffpd_in; input [0:0]txdlybypass_in; input [0:0]txdlyen_in; input [0:0]txdlyhold_in; input [0:0]txdlyovrden_in; input [0:0]txdlysreset_in; input [0:0]txdlyupdown_in; input [0:0]txelecidle_in; input [0:0]txelforcestart_in; input [5:0]txheader_in; input [0:0]txinhibit_in; input [0:0]txlatclk_in; input [0:0]txlfpstreset_in; input [0:0]txlfpsu2lpexit_in; input [0:0]txlfpsu3wake_in; input [6:0]txmaincursor_in; input [2:0]txmargin_in; input [0:0]txmuxdcdexhold_in; input [0:0]txmuxdcdorwren_in; input [0:0]txoneszeros_in; input [2:0]txoutclksel_in; input [0:0]txpcsreset_in; input [1:0]txpd_in; input [0:0]txpdelecidlemode_in; input [0:0]txphalign_in; input [0:0]txphalignen_in; input [0:0]txphdlypd_in; input [0:0]txphdlyreset_in; input [0:0]txphdlytstclk_in; input [0:0]txphinit_in; input [0:0]txphovrden_in; input [0:0]txpippmen_in; input [0:0]txpippmovrden_in; input [0:0]txpippmpd_in; input [0:0]txpippmsel_in; input [4:0]txpippmstepsize_in; input [0:0]txpisopd_in; input [1:0]txpllclksel_in; input [0:0]txpmareset_in; input [0:0]txpolarity_in; input [4:0]txpostcursor_in; input [0:0]txpostcursorinv_in; input [0:0]txprbsforceerr_in; input [3:0]txprbssel_in; input [4:0]txprecursor_in; input [0:0]txprecursorinv_in; input [0:0]txprogdivreset_in; input [0:0]txqpibiasen_in; input [0:0]txqpistrongpdown_in; input [0:0]txqpiweakpup_in; input [2:0]txrate_in; input [0:0]txratemode_in; input [6:0]txsequence_in; input [0:0]txswing_in; input [0:0]txsyncallin_in; input [0:0]txsyncin_in; input [0:0]txsyncmode_in; input [1:0]txsysclksel_in; input [0:0]txuserrdy_in; input [0:0]txusrclk_in; input [0:0]txusrclk2_in; output [2:0]bufgtce_out; output [2:0]bufgtcemask_out; output [8:0]bufgtdiv_out; output [2:0]bufgtreset_out; output [2:0]bufgtrstmask_out; output [0:0]cpllfbclklost_out; output [0:0]cplllock_out; output [0:0]cpllrefclklost_out; output [16:0]dmonitorout_out; output [0:0]dmonitoroutclk_out; output [15:0]drpdo_out; output [0:0]drprdy_out; output [0:0]eyescandataerror_out; output [0:0]gthtxn_out; output [0:0]gthtxp_out; output [0:0]gtpowergood_out; output [0:0]gtrefclkmonitor_out; output [0:0]gtytxn_out; output [0:0]gtytxp_out; output [0:0]pcierategen3_out; output [0:0]pcierateidle_out; output [1:0]pcierateqpllpd_out; output [1:0]pcierateqpllreset_out; output [0:0]pciesynctxsyncdone_out; output [0:0]pcieusergen3rdy_out; output [0:0]pcieuserphystatusrst_out; output [0:0]pcieuserratestart_out; output [11:0]pcsrsvdout_out; output [0:0]phystatus_out; output [7:0]pinrsrvdas_out; output [0:0]powerpresent_out; output [0:0]resetexception_out; output [2:0]rxbufstatus_out; output [0:0]rxbyteisaligned_out; output [0:0]rxbyterealign_out; output [0:0]rxcdrlock_out; output [0:0]rxcdrphdone_out; output [0:0]rxchanbondseq_out; output [0:0]rxchanisaligned_out; output [0:0]rxchanrealign_out; output [4:0]rxchbondo_out; output [0:0]rxckcaldone_out; output [1:0]rxclkcorcnt_out; output [0:0]rxcominitdet_out; output [0:0]rxcommadet_out; output [0:0]rxcomsasdet_out; output [0:0]rxcomwakedet_out; output [15:0]rxctrl0_out; output [15:0]rxctrl1_out; output [7:0]rxctrl2_out; output [7:0]rxctrl3_out; output [127:0]rxdata_out; output [7:0]rxdataextendrsvd_out; output [1:0]rxdatavalid_out; output [0:0]rxdlysresetdone_out; output [0:0]rxelecidle_out; output [5:0]rxheader_out; output [1:0]rxheadervalid_out; output [0:0]rxlfpstresetdet_out; output [0:0]rxlfpsu2lpexitdet_out; output [0:0]rxlfpsu3wakedet_out; output [6:0]rxmonitorout_out; output [0:0]rxosintdone_out; output [0:0]rxosintstarted_out; output [0:0]rxosintstrobedone_out; output [0:0]rxosintstrobestarted_out; output [0:0]rxoutclk_out; output [0:0]rxoutclkfabric_out; output [0:0]rxoutclkpcs_out; output [0:0]rxphaligndone_out; output [0:0]rxphalignerr_out; output [0:0]rxpmaresetdone_out; output [0:0]rxprbserr_out; output [0:0]rxprbslocked_out; output [0:0]rxprgdivresetdone_out; output [0:0]rxqpisenn_out; output [0:0]rxqpisenp_out; output [0:0]rxratedone_out; output [0:0]rxrecclkout_out; output [0:0]rxresetdone_out; output [0:0]rxsliderdy_out; output [0:0]rxslipdone_out; output [0:0]rxslipoutclkrdy_out; output [0:0]rxslippmardy_out; output [1:0]rxstartofseq_out; output [2:0]rxstatus_out; output [0:0]rxsyncdone_out; output [0:0]rxsyncout_out; output [0:0]rxvalid_out; output [1:0]txbufstatus_out; output [0:0]txcomfinish_out; output [0:0]txdccdone_out; output [0:0]txdlysresetdone_out; output [0:0]txoutclk_out; output [0:0]txoutclkfabric_out; output [0:0]txoutclkpcs_out; output [0:0]txphaligndone_out; output [0:0]txphinitdone_out; output [0:0]txpmaresetdone_out; output [0:0]txprgdivresetdone_out; output [0:0]txqpisenn_out; output [0:0]txqpisenp_out; output [0:0]txratedone_out; output [0:0]txresetdone_out; output [0:0]txsyncdone_out; output [0:0]txsyncout_out; input lopt; input lopt_1; output lopt_2; output lopt_3; input lopt_4; input lopt_5; output lopt_6; output lopt_7; wire \ ; wire [0:0]cplllock_out; wire [8:0]drpaddr_in; wire [0:0]drpclk_in; wire [15:0]drpdi_in; wire [15:0]drpdo_out; wire [0:0]drpen_in; wire [0:0]drprdy_out; wire [0:0]drpwe_in; wire [0:0]gthrxn_in; wire [0:0]gthrxp_in; wire [0:0]gthtxn_out; wire [0:0]gthtxp_out; wire [0:0]gtpowergood_out; wire [0:0]gtrefclk0_in; wire [0:0]gtwiz_reset_rx_datapath_in; wire [0:0]gtwiz_reset_rx_done_out; wire [0:0]gtwiz_reset_rx_pll_and_datapath_in; wire [0:0]gtwiz_reset_tx_done_out; wire [0:0]gtwiz_userclk_rx_active_in; wire [0:0]gtwiz_userclk_tx_active_in; wire [31:0]gtwiz_userdata_rx_out; wire [63:0]gtwiz_userdata_tx_in; wire [2:0]loopback_in; wire lopt; wire lopt_1; wire lopt_2; wire lopt_3; wire lopt_4; wire lopt_5; wire lopt_6; wire lopt_7; wire [2:2]\^rxbufstatus_out ; wire [0:0]rxcdrovrden_in; wire [0:0]\^rxdatavalid_out ; wire [0:0]rxgearboxslip_in; wire [1:0]\^rxheader_out ; wire [0:0]\^rxheadervalid_out ; wire [0:0]rxoutclk_out; wire [0:0]rxpmaresetdone_out; wire [0:0]rxpolarity_in; wire [0:0]rxusrclk2_in; wire [0:0]rxusrclk_in; wire [1:1]\^txbufstatus_out ; wire [5:0]txheader_in; wire [0:0]txoutclk_out; wire [0:0]txpmaresetdone_out; wire [6:0]txsequence_in; wire [0:0]txusrclk2_in; wire [0:0]txusrclk_in; assign bufgtce_out[2] = \ ; assign bufgtce_out[1] = \ ; assign bufgtce_out[0] = \ ; assign bufgtcemask_out[2] = \ ; assign bufgtcemask_out[1] = \ ; assign bufgtcemask_out[0] = \ ; assign bufgtdiv_out[8] = \ ; assign bufgtdiv_out[7] = \ ; assign bufgtdiv_out[6] = \ ; assign bufgtdiv_out[5] = \ ; assign bufgtdiv_out[4] = \ ; assign bufgtdiv_out[3] = \ ; assign bufgtdiv_out[2] = \ ; assign bufgtdiv_out[1] = \ ; assign bufgtdiv_out[0] = \ ; assign bufgtreset_out[2] = \ ; assign bufgtreset_out[1] = \ ; assign bufgtreset_out[0] = \ ; assign bufgtrstmask_out[2] = \ ; assign bufgtrstmask_out[1] = \ ; assign bufgtrstmask_out[0] = \ ; assign cpllfbclklost_out[0] = \ ; assign cpllrefclklost_out[0] = \ ; assign dmonitorout_out[16] = \ ; assign dmonitorout_out[15] = \ ; assign dmonitorout_out[14] = \ ; assign dmonitorout_out[13] = \ ; assign dmonitorout_out[12] = \ ; assign dmonitorout_out[11] = \ ; assign dmonitorout_out[10] = \ ; assign dmonitorout_out[9] = \ ; assign dmonitorout_out[8] = \ ; assign dmonitorout_out[7] = \ ; assign dmonitorout_out[6] = \ ; assign dmonitorout_out[5] = \ ; assign dmonitorout_out[4] = \ ; assign dmonitorout_out[3] = \ ; assign dmonitorout_out[2] = \ ; assign dmonitorout_out[1] = \ ; assign dmonitorout_out[0] = \ ; assign dmonitoroutclk_out[0] = \ ; assign drpdo_common_out[15] = \ ; assign drpdo_common_out[14] = \ ; assign drpdo_common_out[13] = \ ; assign drpdo_common_out[12] = \ ; assign drpdo_common_out[11] = \ ; assign drpdo_common_out[10] = \ ; assign drpdo_common_out[9] = \ ; assign drpdo_common_out[8] = \ ; assign drpdo_common_out[7] = \ ; assign drpdo_common_out[6] = \ ; assign drpdo_common_out[5] = \ ; assign drpdo_common_out[4] = \ ; assign drpdo_common_out[3] = \ ; assign drpdo_common_out[2] = \ ; assign drpdo_common_out[1] = \ ; assign drpdo_common_out[0] = \ ; assign drprdy_common_out[0] = \ ; assign eyescandataerror_out[0] = \ ; assign gtrefclkmonitor_out[0] = \ ; assign gtwiz_buffbypass_rx_done_out[0] = \ ; assign gtwiz_buffbypass_rx_error_out[0] = \ ; assign gtwiz_buffbypass_tx_done_out[0] = \ ; assign gtwiz_buffbypass_tx_error_out[0] = \ ; assign gtwiz_reset_qpll0reset_out[0] = \ ; assign gtwiz_reset_qpll1reset_out[0] = \ ; assign gtwiz_reset_rx_cdr_stable_out[0] = \ ; assign gtwiz_userclk_rx_active_out[0] = \ ; assign gtwiz_userclk_rx_srcclk_out[0] = \ ; assign gtwiz_userclk_rx_usrclk2_out[0] = \ ; assign gtwiz_userclk_rx_usrclk_out[0] = \ ; assign gtwiz_userclk_tx_active_out[0] = \ ; assign gtwiz_userclk_tx_srcclk_out[0] = \ ; assign gtwiz_userclk_tx_usrclk2_out[0] = \ ; assign gtwiz_userclk_tx_usrclk_out[0] = \ ; assign gtytxn_out[0] = \ ; assign gtytxp_out[0] = \ ; assign pcierategen3_out[0] = \ ; assign pcierateidle_out[0] = \ ; assign pcierateqpllpd_out[1] = \ ; assign pcierateqpllpd_out[0] = \ ; assign pcierateqpllreset_out[1] = \ ; assign pcierateqpllreset_out[0] = \ ; assign pciesynctxsyncdone_out[0] = \ ; assign pcieusergen3rdy_out[0] = \ ; assign pcieuserphystatusrst_out[0] = \ ; assign pcieuserratestart_out[0] = \ ; assign pcsrsvdout_out[11] = \ ; assign pcsrsvdout_out[10] = \ ; assign pcsrsvdout_out[9] = \ ; assign pcsrsvdout_out[8] = \ ; assign pcsrsvdout_out[7] = \ ; assign pcsrsvdout_out[6] = \ ; assign pcsrsvdout_out[5] = \ ; assign pcsrsvdout_out[4] = \ ; assign pcsrsvdout_out[3] = \ ; assign pcsrsvdout_out[2] = \ ; assign pcsrsvdout_out[1] = \ ; assign pcsrsvdout_out[0] = \ ; assign phystatus_out[0] = \ ; assign pinrsrvdas_out[7] = \ ; assign pinrsrvdas_out[6] = \ ; assign pinrsrvdas_out[5] = \ ; assign pinrsrvdas_out[4] = \ ; assign pinrsrvdas_out[3] = \ ; assign pinrsrvdas_out[2] = \ ; assign pinrsrvdas_out[1] = \ ; assign pinrsrvdas_out[0] = \ ; assign pmarsvdout0_out[7] = \ ; assign pmarsvdout0_out[6] = \ ; assign pmarsvdout0_out[5] = \ ; assign pmarsvdout0_out[4] = \ ; assign pmarsvdout0_out[3] = \ ; assign pmarsvdout0_out[2] = \ ; assign pmarsvdout0_out[1] = \ ; assign pmarsvdout0_out[0] = \ ; assign pmarsvdout1_out[7] = \ ; assign pmarsvdout1_out[6] = \ ; assign pmarsvdout1_out[5] = \ ; assign pmarsvdout1_out[4] = \ ; assign pmarsvdout1_out[3] = \ ; assign pmarsvdout1_out[2] = \ ; assign pmarsvdout1_out[1] = \ ; assign pmarsvdout1_out[0] = \ ; assign powerpresent_out[0] = \ ; assign qpll0fbclklost_out[0] = \ ; assign qpll0lock_out[0] = \ ; assign qpll0outclk_out[0] = \ ; assign qpll0outrefclk_out[0] = \ ; assign qpll0refclklost_out[0] = \ ; assign qpll1fbclklost_out[0] = \ ; assign qpll1lock_out[0] = \ ; assign qpll1outclk_out[0] = \ ; assign qpll1outrefclk_out[0] = \ ; assign qpll1refclklost_out[0] = \ ; assign qplldmonitor0_out[7] = \ ; assign qplldmonitor0_out[6] = \ ; assign qplldmonitor0_out[5] = \ ; assign qplldmonitor0_out[4] = \ ; assign qplldmonitor0_out[3] = \ ; assign qplldmonitor0_out[2] = \ ; assign qplldmonitor0_out[1] = \ ; assign qplldmonitor0_out[0] = \ ; assign qplldmonitor1_out[7] = \ ; assign qplldmonitor1_out[6] = \ ; assign qplldmonitor1_out[5] = \ ; assign qplldmonitor1_out[4] = \ ; assign qplldmonitor1_out[3] = \ ; assign qplldmonitor1_out[2] = \ ; assign qplldmonitor1_out[1] = \ ; assign qplldmonitor1_out[0] = \ ; assign refclkoutmonitor0_out[0] = \ ; assign refclkoutmonitor1_out[0] = \ ; assign resetexception_out[0] = \ ; assign rxbufstatus_out[2] = \^rxbufstatus_out [2]; assign rxbufstatus_out[1] = \ ; assign rxbufstatus_out[0] = \ ; assign rxbyteisaligned_out[0] = \ ; assign rxbyterealign_out[0] = \ ; assign rxcdrlock_out[0] = \ ; assign rxcdrphdone_out[0] = \ ; assign rxchanbondseq_out[0] = \ ; assign rxchanisaligned_out[0] = \ ; assign rxchanrealign_out[0] = \ ; assign rxchbondo_out[4] = \ ; assign rxchbondo_out[3] = \ ; assign rxchbondo_out[2] = \ ; assign rxchbondo_out[1] = \ ; assign rxchbondo_out[0] = \ ; assign rxckcaldone_out[0] = \ ; assign rxclkcorcnt_out[1] = \ ; assign rxclkcorcnt_out[0] = \ ; assign rxcominitdet_out[0] = \ ; assign rxcommadet_out[0] = \ ; assign rxcomsasdet_out[0] = \ ; assign rxcomwakedet_out[0] = \ ; assign rxctrl0_out[15] = \ ; assign rxctrl0_out[14] = \ ; assign rxctrl0_out[13] = \ ; assign rxctrl0_out[12] = \ ; assign rxctrl0_out[11] = \ ; assign rxctrl0_out[10] = \ ; assign rxctrl0_out[9] = \ ; assign rxctrl0_out[8] = \ ; assign rxctrl0_out[7] = \ ; assign rxctrl0_out[6] = \ ; assign rxctrl0_out[5] = \ ; assign rxctrl0_out[4] = \ ; assign rxctrl0_out[3] = \ ; assign rxctrl0_out[2] = \ ; assign rxctrl0_out[1] = \ ; assign rxctrl0_out[0] = \ ; assign rxctrl1_out[15] = \ ; assign rxctrl1_out[14] = \ ; assign rxctrl1_out[13] = \ ; assign rxctrl1_out[12] = \ ; assign rxctrl1_out[11] = \ ; assign rxctrl1_out[10] = \ ; assign rxctrl1_out[9] = \ ; assign rxctrl1_out[8] = \ ; assign rxctrl1_out[7] = \ ; assign rxctrl1_out[6] = \ ; assign rxctrl1_out[5] = \ ; assign rxctrl1_out[4] = \ ; assign rxctrl1_out[3] = \ ; assign rxctrl1_out[2] = \ ; assign rxctrl1_out[1] = \ ; assign rxctrl1_out[0] = \ ; assign rxctrl2_out[7] = \ ; assign rxctrl2_out[6] = \ ; assign rxctrl2_out[5] = \ ; assign rxctrl2_out[4] = \ ; assign rxctrl2_out[3] = \ ; assign rxctrl2_out[2] = \ ; assign rxctrl2_out[1] = \ ; assign rxctrl2_out[0] = \ ; assign rxctrl3_out[7] = \ ; assign rxctrl3_out[6] = \ ; assign rxctrl3_out[5] = \ ; assign rxctrl3_out[4] = \ ; assign rxctrl3_out[3] = \ ; assign rxctrl3_out[2] = \ ; assign rxctrl3_out[1] = \ ; assign rxctrl3_out[0] = \ ; assign rxdata_out[127] = \ ; assign rxdata_out[126] = \ ; assign rxdata_out[125] = \ ; assign rxdata_out[124] = \ ; assign rxdata_out[123] = \ ; assign rxdata_out[122] = \ ; assign rxdata_out[121] = \ ; assign rxdata_out[120] = \ ; assign rxdata_out[119] = \ ; assign rxdata_out[118] = \ ; assign rxdata_out[117] = \ ; assign rxdata_out[116] = \ ; assign rxdata_out[115] = \ ; assign rxdata_out[114] = \ ; assign rxdata_out[113] = \ ; assign rxdata_out[112] = \ ; assign rxdata_out[111] = \ ; assign rxdata_out[110] = \ ; assign rxdata_out[109] = \ ; assign rxdata_out[108] = \ ; assign rxdata_out[107] = \ ; assign rxdata_out[106] = \ ; assign rxdata_out[105] = \ ; assign rxdata_out[104] = \ ; assign rxdata_out[103] = \ ; assign rxdata_out[102] = \ ; assign rxdata_out[101] = \ ; assign rxdata_out[100] = \ ; assign rxdata_out[99] = \ ; assign rxdata_out[98] = \ ; assign rxdata_out[97] = \ ; assign rxdata_out[96] = \ ; assign rxdata_out[95] = \ ; assign rxdata_out[94] = \ ; assign rxdata_out[93] = \ ; assign rxdata_out[92] = \ ; assign rxdata_out[91] = \ ; assign rxdata_out[90] = \ ; assign rxdata_out[89] = \ ; assign rxdata_out[88] = \ ; assign rxdata_out[87] = \ ; assign rxdata_out[86] = \ ; assign rxdata_out[85] = \ ; assign rxdata_out[84] = \ ; assign rxdata_out[83] = \ ; assign rxdata_out[82] = \ ; assign rxdata_out[81] = \ ; assign rxdata_out[80] = \ ; assign rxdata_out[79] = \ ; assign rxdata_out[78] = \ ; assign rxdata_out[77] = \ ; assign rxdata_out[76] = \ ; assign rxdata_out[75] = \ ; assign rxdata_out[74] = \ ; assign rxdata_out[73] = \ ; assign rxdata_out[72] = \ ; assign rxdata_out[71] = \ ; assign rxdata_out[70] = \ ; assign rxdata_out[69] = \ ; assign rxdata_out[68] = \ ; assign rxdata_out[67] = \ ; assign rxdata_out[66] = \ ; assign rxdata_out[65] = \ ; assign rxdata_out[64] = \ ; assign rxdata_out[63] = \ ; assign rxdata_out[62] = \ ; assign rxdata_out[61] = \ ; assign rxdata_out[60] = \ ; assign rxdata_out[59] = \ ; assign rxdata_out[58] = \ ; assign rxdata_out[57] = \ ; assign rxdata_out[56] = \ ; assign rxdata_out[55] = \ ; assign rxdata_out[54] = \ ; assign rxdata_out[53] = \ ; assign rxdata_out[52] = \ ; assign rxdata_out[51] = \ ; assign rxdata_out[50] = \ ; assign rxdata_out[49] = \ ; assign rxdata_out[48] = \ ; assign rxdata_out[47] = \ ; assign rxdata_out[46] = \ ; assign rxdata_out[45] = \ ; assign rxdata_out[44] = \ ; assign rxdata_out[43] = \ ; assign rxdata_out[42] = \ ; assign rxdata_out[41] = \ ; assign rxdata_out[40] = \ ; assign rxdata_out[39] = \ ; assign rxdata_out[38] = \ ; assign rxdata_out[37] = \ ; assign rxdata_out[36] = \ ; assign rxdata_out[35] = \ ; assign rxdata_out[34] = \ ; assign rxdata_out[33] = \ ; assign rxdata_out[32] = \ ; assign rxdata_out[31] = \ ; assign rxdata_out[30] = \ ; assign rxdata_out[29] = \ ; assign rxdata_out[28] = \ ; assign rxdata_out[27] = \ ; assign rxdata_out[26] = \ ; assign rxdata_out[25] = \ ; assign rxdata_out[24] = \ ; assign rxdata_out[23] = \ ; assign rxdata_out[22] = \ ; assign rxdata_out[21] = \ ; assign rxdata_out[20] = \ ; assign rxdata_out[19] = \ ; assign rxdata_out[18] = \ ; assign rxdata_out[17] = \ ; assign rxdata_out[16] = \ ; assign rxdata_out[15] = \ ; assign rxdata_out[14] = \ ; assign rxdata_out[13] = \ ; assign rxdata_out[12] = \ ; assign rxdata_out[11] = \ ; assign rxdata_out[10] = \ ; assign rxdata_out[9] = \ ; assign rxdata_out[8] = \ ; assign rxdata_out[7] = \ ; assign rxdata_out[6] = \ ; assign rxdata_out[5] = \ ; assign rxdata_out[4] = \ ; assign rxdata_out[3] = \ ; assign rxdata_out[2] = \ ; assign rxdata_out[1] = \ ; assign rxdata_out[0] = \ ; assign rxdataextendrsvd_out[7] = \ ; assign rxdataextendrsvd_out[6] = \ ; assign rxdataextendrsvd_out[5] = \ ; assign rxdataextendrsvd_out[4] = \ ; assign rxdataextendrsvd_out[3] = \ ; assign rxdataextendrsvd_out[2] = \ ; assign rxdataextendrsvd_out[1] = \ ; assign rxdataextendrsvd_out[0] = \ ; assign rxdatavalid_out[1] = \ ; assign rxdatavalid_out[0] = \^rxdatavalid_out [0]; assign rxdlysresetdone_out[0] = \ ; assign rxelecidle_out[0] = \ ; assign rxheader_out[5] = \ ; assign rxheader_out[4] = \ ; assign rxheader_out[3] = \ ; assign rxheader_out[2] = \ ; assign rxheader_out[1:0] = \^rxheader_out [1:0]; assign rxheadervalid_out[1] = \ ; assign rxheadervalid_out[0] = \^rxheadervalid_out [0]; assign rxlfpstresetdet_out[0] = \ ; assign rxlfpsu2lpexitdet_out[0] = \ ; assign rxlfpsu3wakedet_out[0] = \ ; assign rxmonitorout_out[6] = \ ; assign rxmonitorout_out[5] = \ ; assign rxmonitorout_out[4] = \ ; assign rxmonitorout_out[3] = \ ; assign rxmonitorout_out[2] = \ ; assign rxmonitorout_out[1] = \ ; assign rxmonitorout_out[0] = \ ; assign rxosintdone_out[0] = \ ; assign rxosintstarted_out[0] = \ ; assign rxosintstrobedone_out[0] = \ ; assign rxosintstrobestarted_out[0] = \ ; assign rxoutclkfabric_out[0] = \ ; assign rxoutclkpcs_out[0] = \ ; assign rxphaligndone_out[0] = \ ; assign rxphalignerr_out[0] = \ ; assign rxprbserr_out[0] = \ ; assign rxprbslocked_out[0] = \ ; assign rxprgdivresetdone_out[0] = \ ; assign rxqpisenn_out[0] = \ ; assign rxqpisenp_out[0] = \ ; assign rxratedone_out[0] = \ ; assign rxrecclk0_sel_out[1] = \ ; assign rxrecclk0_sel_out[0] = \ ; assign rxrecclk0sel_out[0] = \ ; assign rxrecclk1_sel_out[1] = \ ; assign rxrecclk1_sel_out[0] = \ ; assign rxrecclk1sel_out[0] = \ ; assign rxrecclkout_out[0] = \ ; assign rxresetdone_out[0] = \ ; assign rxsliderdy_out[0] = \ ; assign rxslipdone_out[0] = \ ; assign rxslipoutclkrdy_out[0] = \ ; assign rxslippmardy_out[0] = \ ; assign rxstartofseq_out[1] = \ ; assign rxstartofseq_out[0] = \ ; assign rxstatus_out[2] = \ ; assign rxstatus_out[1] = \ ; assign rxstatus_out[0] = \ ; assign rxsyncdone_out[0] = \ ; assign rxsyncout_out[0] = \ ; assign rxvalid_out[0] = \ ; assign sdm0finalout_out[0] = \ ; assign sdm0testdata_out[0] = \ ; assign sdm1finalout_out[0] = \ ; assign sdm1testdata_out[0] = \ ; assign tcongpo_out[0] = \ ; assign tconrsvdout0_out[0] = \ ; assign txbufstatus_out[1] = \^txbufstatus_out [1]; assign txbufstatus_out[0] = \ ; assign txcomfinish_out[0] = \ ; assign txdccdone_out[0] = \ ; assign txdlysresetdone_out[0] = \ ; assign txoutclkfabric_out[0] = \ ; assign txoutclkpcs_out[0] = \ ; assign txphaligndone_out[0] = \ ; assign txphinitdone_out[0] = \ ; assign txprgdivresetdone_out[0] = \ ; assign txqpisenn_out[0] = \ ; assign txqpisenp_out[0] = \ ; assign txratedone_out[0] = \ ; assign txresetdone_out[0] = \ ; assign txsyncdone_out[0] = \ ; assign txsyncout_out[0] = \ ; assign ubdaddr_out[0] = \ ; assign ubden_out[0] = \ ; assign ubdi_out[0] = \ ; assign ubdwe_out[0] = \ ; assign ubmdmtdo_out[0] = \ ; assign ubrsvdout_out[0] = \ ; assign ubtxuart_out[0] = \ ; GND GND (.G(\ )); aurora_64b66b_0_aurora_64b66b_0_gt_gtwizard_gthe3 \gen_gtwizard_gthe3_top.aurora_64b66b_0_gt_gtwizard_gthe3_inst (.cplllock_out(cplllock_out), .drpaddr_in(drpaddr_in), .drpclk_in(drpclk_in), .drpdi_in(drpdi_in), .drpdo_out(drpdo_out), .drpen_in(drpen_in), .drprdy_out(drprdy_out), .drpwe_in(drpwe_in), .gthrxn_in(gthrxn_in), .gthrxp_in(gthrxp_in), .gthtxn_out(gthtxn_out), .gthtxp_out(gthtxp_out), .gtpowergood_out(gtpowergood_out), .gtrefclk0_in(gtrefclk0_in), .gtwiz_reset_rx_datapath_in(gtwiz_reset_rx_datapath_in), .gtwiz_reset_rx_done_out(gtwiz_reset_rx_done_out), .gtwiz_reset_rx_pll_and_datapath_in(gtwiz_reset_rx_pll_and_datapath_in), .gtwiz_reset_tx_done_out(gtwiz_reset_tx_done_out), .gtwiz_userclk_rx_active_in(gtwiz_userclk_rx_active_in), .gtwiz_userclk_tx_active_in(gtwiz_userclk_tx_active_in), .gtwiz_userdata_rx_out(gtwiz_userdata_rx_out), .gtwiz_userdata_tx_in(gtwiz_userdata_tx_in), .loopback_in(loopback_in), .lopt(lopt), .lopt_1(lopt_1), .lopt_2(lopt_2), .lopt_3(lopt_3), .lopt_4(lopt_4), .lopt_5(lopt_5), .lopt_6(lopt_6), .lopt_7(lopt_7), .rxbufstatus_out(\^rxbufstatus_out ), .rxcdrovrden_in(rxcdrovrden_in), .rxdatavalid_out(\^rxdatavalid_out ), .rxgearboxslip_in(rxgearboxslip_in), .rxheader_out(\^rxheader_out ), .rxheadervalid_out(\^rxheadervalid_out ), .rxoutclk_out(rxoutclk_out), .rxpmaresetdone_out(rxpmaresetdone_out), .rxpolarity_in(rxpolarity_in), .rxusrclk2_in(rxusrclk2_in), .rxusrclk_in(rxusrclk_in), .txbufstatus_out(\^txbufstatus_out ), .txheader_in(txheader_in[1:0]), .txoutclk_out(txoutclk_out), .txpmaresetdone_out(txpmaresetdone_out), .txsequence_in(txsequence_in), .txusrclk2_in(txusrclk2_in), .txusrclk_in(txusrclk_in)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_rst_sync" *) module aurora_64b66b_0_aurora_64b66b_0_rst_sync (D, pma_init, init_clk); output [0:0]D; input pma_init; input init_clk; wire [0:0]D; wire init_clk; wire pma_init; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg3; wire stg4_reg_n_0; (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg1_aurora_64b66b_0_cdc_to_reg (.C(init_clk), .CE(1'b1), .D(pma_init), .Q(stg1_aurora_64b66b_0_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg2_reg (.C(init_clk), .CE(1'b1), .D(stg1_aurora_64b66b_0_cdc_to), .Q(stg2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg3_reg (.C(init_clk), .CE(1'b1), .D(stg2), .Q(stg3), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg4_reg (.C(init_clk), .CE(1'b1), .D(stg3), .Q(stg4_reg_n_0), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg5_reg (.C(init_clk), .CE(1'b1), .D(stg4_reg_n_0), .Q(D), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_rst_sync" *) module aurora_64b66b_0_aurora_64b66b_0_rst_sync_0 (D, reset_pb, CLK); output [0:0]D; input reset_pb; input CLK; wire CLK; wire [0:0]D; wire reset_pb; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg3; wire stg4; (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg1_aurora_64b66b_0_cdc_to_reg (.C(CLK), .CE(1'b1), .D(reset_pb), .Q(stg1_aurora_64b66b_0_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg2_reg (.C(CLK), .CE(1'b1), .D(stg1_aurora_64b66b_0_cdc_to), .Q(stg2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg3_reg (.C(CLK), .CE(1'b1), .D(stg2), .Q(stg3), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg4_reg (.C(CLK), .CE(1'b1), .D(stg3), .Q(stg4), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg5_reg (.C(CLK), .CE(1'b1), .D(stg4), .Q(D), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_rst_sync" *) module aurora_64b66b_0_aurora_64b66b_0_rst_sync_1 (SS, in0, CLK); output [0:0]SS; input in0; input CLK; wire CLK; wire [0:0]SS; wire in0; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg3; wire stg4_reg_n_0; (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg1_aurora_64b66b_0_cdc_to_reg (.C(CLK), .CE(1'b1), .D(in0), .Q(stg1_aurora_64b66b_0_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg2_reg (.C(CLK), .CE(1'b1), .D(stg1_aurora_64b66b_0_cdc_to), .Q(stg2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg3_reg (.C(CLK), .CE(1'b1), .D(stg2), .Q(stg3), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg4_reg (.C(CLK), .CE(1'b1), .D(stg3), .Q(stg4_reg_n_0), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg5_reg (.C(CLK), .CE(1'b1), .D(stg4_reg_n_0), .Q(SS), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_rst_sync" *) module aurora_64b66b_0_aurora_64b66b_0_rst_sync_2 (link_reset_sync, link_reset_out, stg5_reg_0); output link_reset_sync; input link_reset_out; input stg5_reg_0; wire link_reset_out; wire link_reset_sync; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg3; wire stg4_reg_n_0; wire stg5_reg_0; (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg1_aurora_64b66b_0_cdc_to_reg (.C(stg5_reg_0), .CE(1'b1), .D(link_reset_out), .Q(stg1_aurora_64b66b_0_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg2_reg (.C(stg5_reg_0), .CE(1'b1), .D(stg1_aurora_64b66b_0_cdc_to), .Q(stg2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg3_reg (.C(stg5_reg_0), .CE(1'b1), .D(stg2), .Q(stg3), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg4_reg (.C(stg5_reg_0), .CE(1'b1), .D(stg3), .Q(stg4_reg_n_0), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg5_reg (.C(stg5_reg_0), .CE(1'b1), .D(stg4_reg_n_0), .Q(link_reset_sync), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_rst_sync" *) module aurora_64b66b_0_aurora_64b66b_0_rst_sync_3 (power_down_sync, power_down, stg4_reg_0); output power_down_sync; input power_down; input stg4_reg_0; wire power_down; wire power_down_sync; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg3; wire stg4_reg_0; wire stg4_reg_n_0; (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg1_aurora_64b66b_0_cdc_to_reg (.C(stg4_reg_0), .CE(1'b1), .D(power_down), .Q(stg1_aurora_64b66b_0_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg2_reg (.C(stg4_reg_0), .CE(1'b1), .D(stg1_aurora_64b66b_0_cdc_to), .Q(stg2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg3_reg (.C(stg4_reg_0), .CE(1'b1), .D(stg2), .Q(stg3), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg4_reg (.C(stg4_reg_0), .CE(1'b1), .D(stg3), .Q(stg4_reg_n_0), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg5_reg (.C(stg4_reg_0), .CE(1'b1), .D(stg4_reg_n_0), .Q(power_down_sync), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_rst_sync" *) module aurora_64b66b_0_aurora_64b66b_0_rst_sync_4 (fsm_resetdone_sync, stg1_aurora_64b66b_0_cdc_to_reg_0, stg4_reg_0); output fsm_resetdone_sync; input stg1_aurora_64b66b_0_cdc_to_reg_0; input stg4_reg_0; wire fsm_resetdone_sync; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg1_aurora_64b66b_0_cdc_to; wire stg1_aurora_64b66b_0_cdc_to_reg_0; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg3; wire stg4_reg_0; wire stg4_reg_n_0; (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg1_aurora_64b66b_0_cdc_to_reg (.C(stg4_reg_0), .CE(1'b1), .D(stg1_aurora_64b66b_0_cdc_to_reg_0), .Q(stg1_aurora_64b66b_0_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg2_reg (.C(stg4_reg_0), .CE(1'b1), .D(stg1_aurora_64b66b_0_cdc_to), .Q(stg2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg3_reg (.C(stg4_reg_0), .CE(1'b1), .D(stg2), .Q(stg3), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg4_reg (.C(stg4_reg_0), .CE(1'b1), .D(stg3), .Q(stg4_reg_n_0), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg5_reg (.C(stg4_reg_0), .CE(1'b1), .D(stg4_reg_n_0), .Q(fsm_resetdone_sync), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_rst_sync" *) module aurora_64b66b_0_aurora_64b66b_0_rst_sync_5 (stg5_reg_0, TX_HEADER_1_reg, stg5_reg_1, stg5_reg_2, stg5_reg_3, stg5_reg_4, stg5_reg_5, stg1_aurora_64b66b_0_cdc_to_reg_0, stg5_reg_6, D, txdatavalid_symgen_i, gen_na_idles_i, tx_pe_data_v_i, TX_HEADER_1_reg_0, channel_up_tx_if, Q); output stg5_reg_0; output TX_HEADER_1_reg; output stg5_reg_1; output stg5_reg_2; output stg5_reg_3; output stg5_reg_4; output stg5_reg_5; input stg1_aurora_64b66b_0_cdc_to_reg_0; input stg5_reg_6; input [1:0]D; input txdatavalid_symgen_i; input gen_na_idles_i; input tx_pe_data_v_i; input TX_HEADER_1_reg_0; input channel_up_tx_if; input [3:0]Q; wire [1:0]D; wire [3:0]Q; wire TX_HEADER_1_reg; wire TX_HEADER_1_reg_0; wire channel_up_tx_if; wire gen_na_idles_i; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg1_aurora_64b66b_0_cdc_to; wire stg1_aurora_64b66b_0_cdc_to_reg_0; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg3; wire stg4_reg_n_0; wire stg5_reg_0; wire stg5_reg_1; wire stg5_reg_2; wire stg5_reg_3; wire stg5_reg_4; wire stg5_reg_5; wire stg5_reg_6; wire tx_pe_data_v_i; wire txdatavalid_symgen_i; (* SOFT_HLUTNM = "soft_lutpair114" *) LUT3 #( .INIT(8'h40)) \TX_DATA[59]_i_1 (.I0(stg5_reg_0), .I1(channel_up_tx_if), .I2(Q[0]), .O(stg5_reg_2)); (* SOFT_HLUTNM = "soft_lutpair114" *) LUT3 #( .INIT(8'h40)) \TX_DATA[60]_i_1 (.I0(stg5_reg_0), .I1(channel_up_tx_if), .I2(Q[1]), .O(stg5_reg_3)); (* SOFT_HLUTNM = "soft_lutpair115" *) LUT3 #( .INIT(8'h40)) \TX_DATA[61]_i_1 (.I0(stg5_reg_0), .I1(channel_up_tx_if), .I2(Q[2]), .O(stg5_reg_4)); (* SOFT_HLUTNM = "soft_lutpair115" *) LUT3 #( .INIT(8'h40)) \TX_DATA[62]_i_2 (.I0(stg5_reg_0), .I1(channel_up_tx_if), .I2(Q[3]), .O(stg5_reg_5)); LUT6 #( .INIT(64'h0000050044444444)) TX_HEADER_0_i_1 (.I0(stg5_reg_0), .I1(D[0]), .I2(TX_HEADER_1_reg_0), .I3(tx_pe_data_v_i), .I4(gen_na_idles_i), .I5(txdatavalid_symgen_i), .O(stg5_reg_1)); LUT6 #( .INIT(64'h00000000EEEEE2EE)) TX_HEADER_1_i_1 (.I0(D[1]), .I1(txdatavalid_symgen_i), .I2(gen_na_idles_i), .I3(tx_pe_data_v_i), .I4(TX_HEADER_1_reg_0), .I5(stg5_reg_0), .O(TX_HEADER_1_reg)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg1_aurora_64b66b_0_cdc_to_reg (.C(stg5_reg_6), .CE(1'b1), .D(stg1_aurora_64b66b_0_cdc_to_reg_0), .Q(stg1_aurora_64b66b_0_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg2_reg (.C(stg5_reg_6), .CE(1'b1), .D(stg1_aurora_64b66b_0_cdc_to), .Q(stg2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg3_reg (.C(stg5_reg_6), .CE(1'b1), .D(stg2), .Q(stg3), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg4_reg (.C(stg5_reg_6), .CE(1'b1), .D(stg3), .Q(stg4_reg_n_0), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg5_reg (.C(stg5_reg_6), .CE(1'b1), .D(stg4_reg_n_0), .Q(stg5_reg_0), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_rst_sync" *) module aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized0 (stg3_reg_0, out, stg3_reg_1); output stg3_reg_0; input out; input stg3_reg_1; wire out; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg3; wire stg3_reg_1; assign stg3_reg_0 = stg3; (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg1_aurora_64b66b_0_cdc_to_reg (.C(stg3_reg_1), .CE(1'b1), .D(out), .Q(stg1_aurora_64b66b_0_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg2_reg (.C(stg3_reg_1), .CE(1'b1), .D(stg1_aurora_64b66b_0_cdc_to), .Q(stg2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg3_reg (.C(stg3_reg_1), .CE(1'b1), .D(stg2), .Q(stg3), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_rst_sync" *) module aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized0_10 (out, gtwiz_userclk_rx_usrclk_out); input out; input gtwiz_userclk_rx_usrclk_out; wire gtwiz_userclk_rx_usrclk_out; wire out; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg3; (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg1_aurora_64b66b_0_cdc_to_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(out), .Q(stg1_aurora_64b66b_0_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg2_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(stg1_aurora_64b66b_0_cdc_to), .Q(stg2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg3_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(stg2), .Q(stg3), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_rst_sync" *) module aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized0_11 (stg3_reg_0, out, stg2_reg_0, FSM_RESETDONE_j_reg); output stg3_reg_0; input out; input stg2_reg_0; input FSM_RESETDONE_j_reg; wire FSM_RESETDONE_j_reg; wire out; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg2; wire stg2_reg_0; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg3; wire stg3_reg_0; LUT2 #( .INIT(4'h8)) prmry_in_inferred_i_1__0 (.I0(stg3), .I1(FSM_RESETDONE_j_reg), .O(stg3_reg_0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg1_aurora_64b66b_0_cdc_to_reg (.C(stg2_reg_0), .CE(1'b1), .D(out), .Q(stg1_aurora_64b66b_0_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg2_reg (.C(stg2_reg_0), .CE(1'b1), .D(stg1_aurora_64b66b_0_cdc_to), .Q(stg2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg3_reg (.C(stg2_reg_0), .CE(1'b1), .D(stg2), .Q(stg3), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_rst_sync" *) module aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized0_12 (out, gtwiz_userclk_rx_usrclk_out); input out; input gtwiz_userclk_rx_usrclk_out; wire gtwiz_userclk_rx_usrclk_out; wire out; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg3; (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg1_aurora_64b66b_0_cdc_to_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(out), .Q(stg1_aurora_64b66b_0_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg2_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(stg1_aurora_64b66b_0_cdc_to), .Q(stg2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg3_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(stg2), .Q(stg3), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_rst_sync" *) module aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized1 (E, in0, init_clk, Q, \FSM_onehot_cdr_reset_fsm_r_reg[0] ); output [0:0]E; input in0; input init_clk; input [2:0]Q; input \FSM_onehot_cdr_reset_fsm_r_reg[0] ; wire [0:0]E; wire \FSM_onehot_cdr_reset_fsm_r_reg[0] ; wire [2:0]Q; wire blocksync_all_lanes_instableclk; wire in0; wire init_clk; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg3; wire stg4_reg_n_0; LUT5 #( .INIT(32'hFFFFF888)) \FSM_onehot_cdr_reset_fsm_r[2]_i_2 (.I0(Q[1]), .I1(\FSM_onehot_cdr_reset_fsm_r_reg[0] ), .I2(blocksync_all_lanes_instableclk), .I3(Q[0]), .I4(Q[2]), .O(E)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg1_aurora_64b66b_0_cdc_to_reg (.C(init_clk), .CE(1'b1), .D(in0), .Q(stg1_aurora_64b66b_0_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg2_reg (.C(init_clk), .CE(1'b1), .D(stg1_aurora_64b66b_0_cdc_to), .Q(stg2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg3_reg (.C(init_clk), .CE(1'b1), .D(stg2), .Q(stg3), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg4_reg (.C(init_clk), .CE(1'b1), .D(stg3), .Q(stg4_reg_n_0), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg5_reg (.C(init_clk), .CE(1'b1), .D(stg4_reg_n_0), .Q(blocksync_all_lanes_instableclk), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_rst_sync" *) module aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized1_13 (rxlossofsync_out_i, in0, gtwiz_userclk_rx_usrclk_out, blocksync_out_i); output rxlossofsync_out_i; input in0; input gtwiz_userclk_rx_usrclk_out; input blocksync_out_i; wire allow_block_sync_propagation_inrxclk; wire blocksync_out_i; wire gtwiz_userclk_rx_usrclk_out; wire in0; wire rxlossofsync_out_i; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg3; wire stg4_reg_n_0; LUT2 #( .INIT(4'h8)) rxlossofsync_out_q_i_1 (.I0(allow_block_sync_propagation_inrxclk), .I1(blocksync_out_i), .O(rxlossofsync_out_i)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg1_aurora_64b66b_0_cdc_to_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(in0), .Q(stg1_aurora_64b66b_0_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg2_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(stg1_aurora_64b66b_0_cdc_to), .Q(stg2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg3_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(stg2), .Q(stg3), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg4_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(stg3), .Q(stg4_reg_n_0), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg5_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(stg4_reg_n_0), .Q(allow_block_sync_propagation_inrxclk), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_rst_sync" *) module aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized1_14 (stg5_reg_0, in0, gtwiz_userclk_rx_usrclk_out, fsm_resetdone_to_rxreset_in, out); output stg5_reg_0; input in0; input gtwiz_userclk_rx_usrclk_out; input fsm_resetdone_to_rxreset_in; input [0:0]out; wire fsm_resetdone_to_new_gtx_rx_comb; wire fsm_resetdone_to_rxreset_in; wire gtwiz_userclk_rx_usrclk_out; wire in0; wire [0:0]out; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg3; wire stg4_reg_n_0; wire stg5_reg_0; LUT3 #( .INIT(8'hDF)) new_gtx_rx_pcsreset_comb_i_1 (.I0(fsm_resetdone_to_new_gtx_rx_comb), .I1(fsm_resetdone_to_rxreset_in), .I2(out), .O(stg5_reg_0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg1_aurora_64b66b_0_cdc_to_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(in0), .Q(stg1_aurora_64b66b_0_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg2_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(stg1_aurora_64b66b_0_cdc_to), .Q(stg2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg3_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(stg2), .Q(stg3), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg4_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(stg3), .Q(stg4_reg_n_0), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg5_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(stg4_reg_n_0), .Q(fsm_resetdone_to_new_gtx_rx_comb), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_rst_sync" *) module aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized1_15 (fsm_resetdone_initclk, \dly_gt_rst_r_reg[18] , in0, init_clk, \count_for_reset_r_reg[23] , \count_for_reset_r_reg[23]_0 , reset_initclk, out, valid_btf_detect_dlyd1); output fsm_resetdone_initclk; output \dly_gt_rst_r_reg[18] ; input in0; input init_clk; input \count_for_reset_r_reg[23] ; input \count_for_reset_r_reg[23]_0 ; input reset_initclk; input out; input valid_btf_detect_dlyd1; wire \count_for_reset_r_reg[23] ; wire \count_for_reset_r_reg[23]_0 ; wire \dly_gt_rst_r_reg[18] ; wire fsm_resetdone_initclk; wire in0; wire init_clk; wire out; wire reset_initclk; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg3; wire stg4_reg_n_0; wire valid_btf_detect_dlyd1; LUT6 #( .INIT(64'hFFFFFFFFEEEEFFEF)) \count_for_reset_r[0]_i_1 (.I0(\count_for_reset_r_reg[23] ), .I1(\count_for_reset_r_reg[23]_0 ), .I2(fsm_resetdone_initclk), .I3(reset_initclk), .I4(out), .I5(valid_btf_detect_dlyd1), .O(\dly_gt_rst_r_reg[18] )); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg1_aurora_64b66b_0_cdc_to_reg (.C(init_clk), .CE(1'b1), .D(in0), .Q(stg1_aurora_64b66b_0_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg2_reg (.C(init_clk), .CE(1'b1), .D(stg1_aurora_64b66b_0_cdc_to), .Q(stg2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg3_reg (.C(init_clk), .CE(1'b1), .D(stg2), .Q(stg3), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg4_reg (.C(init_clk), .CE(1'b1), .D(stg3), .Q(stg4_reg_n_0), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg5_reg (.C(init_clk), .CE(1'b1), .D(stg4_reg_n_0), .Q(fsm_resetdone_initclk), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_rst_sync" *) module aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized1_16 (SR, in0, stg3_reg_0); output [0:0]SR; input in0; input stg3_reg_0; wire [0:0]SR; wire in0; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg3; wire stg3_reg_0; wire stg4_reg_n_0; (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg1_aurora_64b66b_0_cdc_to_reg (.C(stg3_reg_0), .CE(1'b1), .D(in0), .Q(stg1_aurora_64b66b_0_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg2_reg (.C(stg3_reg_0), .CE(1'b1), .D(stg1_aurora_64b66b_0_cdc_to), .Q(stg2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg3_reg (.C(stg3_reg_0), .CE(1'b1), .D(stg2), .Q(stg3), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg4_reg (.C(stg3_reg_0), .CE(1'b1), .D(stg3), .Q(stg4_reg_n_0), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg5_reg (.C(stg3_reg_0), .CE(1'b1), .D(stg4_reg_n_0), .Q(SR), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_rst_sync" *) module aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized1_17 (reset_initclk, stg5_reg_0, SR, init_clk, out, fsm_resetdone_initclk, \hard_err_cntr_r_reg[7] , \hard_err_cntr_r_reg[7]_0 ); output reset_initclk; output [0:0]stg5_reg_0; input [0:0]SR; input init_clk; input out; input fsm_resetdone_initclk; input \hard_err_cntr_r_reg[7] ; input \hard_err_cntr_r_reg[7]_0 ; wire [0:0]SR; wire fsm_resetdone_initclk; wire \hard_err_cntr_r_reg[7] ; wire \hard_err_cntr_r_reg[7]_0 ; wire init_clk; wire out; wire reset_initclk; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg3; wire stg4_reg_n_0; wire [0:0]stg5_reg_0; LUT5 #( .INIT(32'hFFFFFF45)) \hard_err_cntr_r[7]_i_1 (.I0(out), .I1(reset_initclk), .I2(fsm_resetdone_initclk), .I3(\hard_err_cntr_r_reg[7] ), .I4(\hard_err_cntr_r_reg[7]_0 ), .O(stg5_reg_0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg1_aurora_64b66b_0_cdc_to_reg (.C(init_clk), .CE(1'b1), .D(SR), .Q(stg1_aurora_64b66b_0_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg2_reg (.C(init_clk), .CE(1'b1), .D(stg1_aurora_64b66b_0_cdc_to), .Q(stg2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg3_reg (.C(init_clk), .CE(1'b1), .D(stg2), .Q(stg3), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg4_reg (.C(init_clk), .CE(1'b1), .D(stg3), .Q(stg4_reg_n_0), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg5_reg (.C(init_clk), .CE(1'b1), .D(stg4_reg_n_0), .Q(reset_initclk), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_rst_sync" *) module aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized1_18 (fsm_resetdone_to_rxreset_in, in0, gtwiz_userclk_rx_usrclk_out); output fsm_resetdone_to_rxreset_in; input in0; input gtwiz_userclk_rx_usrclk_out; wire fsm_resetdone_to_rxreset_in; wire gtwiz_userclk_rx_usrclk_out; wire in0; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg3; wire stg4_reg_n_0; (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg1_aurora_64b66b_0_cdc_to_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(in0), .Q(stg1_aurora_64b66b_0_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg2_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(stg1_aurora_64b66b_0_cdc_to), .Q(stg2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg3_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(stg2), .Q(stg3), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg4_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(stg3), .Q(stg4_reg_n_0), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg5_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(stg4_reg_n_0), .Q(fsm_resetdone_to_rxreset_in), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_rst_sync" *) module aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized1_19 (in0, E, init_clk); output in0; input [0:0]E; input init_clk; wire [0:0]E; wire in0; wire init_clk; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg3; wire stg4_reg_n_0; (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg1_aurora_64b66b_0_cdc_to_reg (.C(init_clk), .CE(1'b1), .D(E), .Q(stg1_aurora_64b66b_0_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg2_reg (.C(init_clk), .CE(1'b1), .D(stg1_aurora_64b66b_0_cdc_to), .Q(stg2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg3_reg (.C(init_clk), .CE(1'b1), .D(stg2), .Q(stg3), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg4_reg (.C(init_clk), .CE(1'b1), .D(stg3), .Q(stg4_reg_n_0), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg5_reg (.C(init_clk), .CE(1'b1), .D(stg4_reg_n_0), .Q(in0), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_rst_sync" *) module aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized1_21 (stg5_reg_0, in0, stg5_reg_1); output stg5_reg_0; input in0; input stg5_reg_1; wire in0; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg3; wire stg4_reg_n_0; wire stg5_reg_0; wire stg5_reg_1; (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg1_aurora_64b66b_0_cdc_to_reg (.C(stg5_reg_1), .CE(1'b1), .D(in0), .Q(stg1_aurora_64b66b_0_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg2_reg (.C(stg5_reg_1), .CE(1'b1), .D(stg1_aurora_64b66b_0_cdc_to), .Q(stg2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg3_reg (.C(stg5_reg_1), .CE(1'b1), .D(stg2), .Q(stg3), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg4_reg (.C(stg5_reg_1), .CE(1'b1), .D(stg3), .Q(stg4_reg_n_0), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg5_reg (.C(stg5_reg_1), .CE(1'b1), .D(stg4_reg_n_0), .Q(stg5_reg_0), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_rst_sync" *) module aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized1_22 (stg5_reg_0, stg1_aurora_64b66b_0_cdc_to_reg_0, stg3_reg_0); output stg5_reg_0; input [0:0]stg1_aurora_64b66b_0_cdc_to_reg_0; input stg3_reg_0; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg1_aurora_64b66b_0_cdc_to; wire [0:0]stg1_aurora_64b66b_0_cdc_to_reg_0; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg3; wire stg3_reg_0; wire stg4_reg_n_0; wire stg5_reg_0; (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg1_aurora_64b66b_0_cdc_to_reg (.C(stg3_reg_0), .CE(1'b1), .D(stg1_aurora_64b66b_0_cdc_to_reg_0), .Q(stg1_aurora_64b66b_0_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg2_reg (.C(stg3_reg_0), .CE(1'b1), .D(stg1_aurora_64b66b_0_cdc_to), .Q(stg2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg3_reg (.C(stg3_reg_0), .CE(1'b1), .D(stg2), .Q(stg3), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg4_reg (.C(stg3_reg_0), .CE(1'b1), .D(stg3), .Q(stg4_reg_n_0), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg5_reg (.C(stg3_reg_0), .CE(1'b1), .D(stg4_reg_n_0), .Q(stg5_reg_0), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_rst_sync" *) module aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized1_23 (stg5_reg_0, in0, gtwiz_userclk_rx_usrclk_out, stg1_aurora_64b66b_0_cdc_to_reg_0); output stg5_reg_0; input in0; input gtwiz_userclk_rx_usrclk_out; input stg1_aurora_64b66b_0_cdc_to_reg_0; wire fifo_reset_wr_sync3; wire gtwiz_userclk_rx_usrclk_out; wire in0; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg1_aurora_64b66b_0_cdc_to; wire stg1_aurora_64b66b_0_cdc_to_reg_0; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg3; wire stg4_reg_n_0; wire stg5_reg_0; LUT2 #( .INIT(4'hE)) prmry_in_inferred_i_1 (.I0(fifo_reset_wr_sync3), .I1(stg1_aurora_64b66b_0_cdc_to_reg_0), .O(stg5_reg_0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg1_aurora_64b66b_0_cdc_to_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(in0), .Q(stg1_aurora_64b66b_0_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg2_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(stg1_aurora_64b66b_0_cdc_to), .Q(stg2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg3_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(stg2), .Q(stg3), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg4_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(stg3), .Q(stg4_reg_n_0), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg5_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(stg4_reg_n_0), .Q(fifo_reset_wr_sync3), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_rst_sync" *) module aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized1_24 (stg3_reg_0, in0, stg3_reg_1); output stg3_reg_0; input in0; input stg3_reg_1; wire in0; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg3; wire stg3_reg_0; wire stg3_reg_1; (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg1_aurora_64b66b_0_cdc_to_reg (.C(stg3_reg_1), .CE(1'b1), .D(in0), .Q(stg1_aurora_64b66b_0_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg2_reg (.C(stg3_reg_1), .CE(1'b1), .D(stg1_aurora_64b66b_0_cdc_to), .Q(stg2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg3_reg (.C(stg3_reg_1), .CE(1'b1), .D(stg2), .Q(stg3), .R(1'b0)); (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/common_reset_cbcc_i/u_rst_sync_reset_rd_clk/stg5_reg_srl2 " *) SRL16E #( .INIT(16'h0003)) stg5_reg_srl2 (.A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b0), .CE(1'b1), .CLK(stg3_reg_1), .D(stg3), .Q(stg3_reg_0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_rst_sync" *) module aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized1_25 (stg3_reg_0, in0, gtwiz_userclk_rx_usrclk_out); output stg3_reg_0; input in0; input gtwiz_userclk_rx_usrclk_out; wire gtwiz_userclk_rx_usrclk_out; wire in0; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg3; wire stg3_reg_0; (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg1_aurora_64b66b_0_cdc_to_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(in0), .Q(stg1_aurora_64b66b_0_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg2_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(stg1_aurora_64b66b_0_cdc_to), .Q(stg2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg3_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(stg2), .Q(stg3), .R(1'b0)); (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/common_reset_cbcc_i/u_rst_sync_reset_wr_clk/stg5_reg_srl2 " *) SRL16E #( .INIT(16'h0003)) stg5_reg_srl2 (.A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b0), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(stg3), .Q(stg3_reg_0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_rst_sync" *) module aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized1_26 (stg5_reg_0, rd_stg1_reg, stg1_aurora_64b66b_0_cdc_to_reg_0, stg5_reg_1, rd_stg1); output stg5_reg_0; output rd_stg1_reg; input stg1_aurora_64b66b_0_cdc_to_reg_0; input stg5_reg_1; input rd_stg1; wire rd_stg1; wire rd_stg1_reg; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg1_aurora_64b66b_0_cdc_to; wire stg1_aurora_64b66b_0_cdc_to_reg_0; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg3; wire stg4_reg_n_0; wire stg5_reg_0; wire stg5_reg_1; LUT2 #( .INIT(4'hE)) cbcc_reset_cbstg2_rd_clk_i_1 (.I0(rd_stg1), .I1(stg5_reg_0), .O(rd_stg1_reg)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg1_aurora_64b66b_0_cdc_to_reg (.C(stg5_reg_1), .CE(1'b1), .D(stg1_aurora_64b66b_0_cdc_to_reg_0), .Q(stg1_aurora_64b66b_0_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg2_reg (.C(stg5_reg_1), .CE(1'b1), .D(stg1_aurora_64b66b_0_cdc_to), .Q(stg2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg3_reg (.C(stg5_reg_1), .CE(1'b1), .D(stg2), .Q(stg3), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg4_reg (.C(stg5_reg_1), .CE(1'b1), .D(stg3), .Q(stg4_reg_n_0), .R(1'b0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg5_reg (.C(stg5_reg_1), .CE(1'b1), .D(stg4_reg_n_0), .Q(stg5_reg_0), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_rst_sync" *) module aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized1_29 (stg3_reg_0, in0, init_clk); output stg3_reg_0; input in0; input init_clk; wire in0; wire init_clk; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg3; wire stg3_reg_0; (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg1_aurora_64b66b_0_cdc_to_reg (.C(init_clk), .CE(1'b1), .D(in0), .Q(stg1_aurora_64b66b_0_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg2_reg (.C(init_clk), .CE(1'b1), .D(stg1_aurora_64b66b_0_cdc_to), .Q(stg2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg3_reg (.C(init_clk), .CE(1'b1), .D(stg2), .Q(stg3), .R(1'b0)); (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/cbcc_gtx0_i/u_rst_sync_btf_sync/stg5_reg_srl2 " *) SRL16E #( .INIT(16'h0003)) stg5_reg_srl2 (.A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b0), .CE(1'b1), .CLK(init_clk), .D(stg3), .Q(stg3_reg_0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_rst_sync" *) module aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized2 (stg11_reg_0, in0, gtwiz_userclk_rx_usrclk_out); output stg11_reg_0; input in0; input gtwiz_userclk_rx_usrclk_out; wire gtwiz_userclk_rx_usrclk_out; wire in0; wire stg10_reg_srl7_n_0; wire stg11_reg_0; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg3; (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/common_reset_cbcc_i/u_rst_sync_fifo_reset_user_clk/stg10_reg_srl7 " *) SRL16E #( .INIT(16'h007F)) stg10_reg_srl7 (.A0(1'b0), .A1(1'b1), .A2(1'b1), .A3(1'b0), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(stg3), .Q(stg10_reg_srl7_n_0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg11_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(stg10_reg_srl7_n_0), .Q(stg11_reg_0), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg1_aurora_64b66b_0_cdc_to_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(in0), .Q(stg1_aurora_64b66b_0_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg2_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(stg1_aurora_64b66b_0_cdc_to), .Q(stg2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg3_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(stg2), .Q(stg3), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_rst_sync" *) module aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized3 (fifo_reset_comb_user_clk_int, dbg_srst_assert0, in0, gtwiz_userclk_rx_usrclk_out, dbg_srst_assert_reg); output fifo_reset_comb_user_clk_int; output dbg_srst_assert0; input in0; input gtwiz_userclk_rx_usrclk_out; input dbg_srst_assert_reg; wire dbg_srst_assert0; wire dbg_srst_assert_reg; wire fifo_reset_comb_user_clk_int; wire gtwiz_userclk_rx_usrclk_out; wire in0; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg1_aurora_64b66b_0_cdc_to; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg2; wire stg20_reg_srl17_n_0; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg3; wire NLW_stg20_reg_srl17_Q31_UNCONNECTED; LUT2 #( .INIT(4'h2)) dbg_srst_assert_i_1 (.I0(dbg_srst_assert_reg), .I1(fifo_reset_comb_user_clk_int), .O(dbg_srst_assert0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg1_aurora_64b66b_0_cdc_to_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(in0), .Q(stg1_aurora_64b66b_0_cdc_to), .R(1'b0)); (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/common_reset_cbcc_i/u_rst_sync_fifo_reset_comb_user_clk_in/stg20_reg_srl17 " *) SRLC32E #( .INIT(32'h0001FFFF)) stg20_reg_srl17 (.A({1'b1,1'b0,1'b0,1'b0,1'b0}), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(stg3), .Q(stg20_reg_srl17_n_0), .Q31(NLW_stg20_reg_srl17_Q31_UNCONNECTED)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg21_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(stg20_reg_srl17_n_0), .Q(fifo_reset_comb_user_clk_int), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg2_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(stg1_aurora_64b66b_0_cdc_to), .Q(stg2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg3_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(stg2), .Q(stg3), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_rst_sync" *) module aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized4 (stg9_reg_0, stg1_aurora_64b66b_0_cdc_to_reg_0, gtwiz_userclk_rx_usrclk_out); output [0:0]stg9_reg_0; input stg1_aurora_64b66b_0_cdc_to_reg_0; input gtwiz_userclk_rx_usrclk_out; wire gtwiz_userclk_rx_usrclk_out; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg1_aurora_64b66b_0_cdc_to; wire stg1_aurora_64b66b_0_cdc_to_reg_0; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg3; wire stg8_reg_srl5_n_0; wire [0:0]stg9_reg_0; (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg1_aurora_64b66b_0_cdc_to_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(stg1_aurora_64b66b_0_cdc_to_reg_0), .Q(stg1_aurora_64b66b_0_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg2_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(stg1_aurora_64b66b_0_cdc_to), .Q(stg2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg3_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(stg2), .Q(stg3), .R(1'b0)); (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/common_reset_cbcc_i/u_rst_sync_reset_to_fifo_wr_clk/stg8_reg_srl5 " *) SRL16E #( .INIT(16'h001F)) stg8_reg_srl5 (.A0(1'b0), .A1(1'b0), .A2(1'b1), .A3(1'b0), .CE(1'b1), .CLK(gtwiz_userclk_rx_usrclk_out), .D(stg3), .Q(stg8_reg_srl5_n_0)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg9_reg (.C(gtwiz_userclk_rx_usrclk_out), .CE(1'b1), .D(stg8_reg_srl5_n_0), .Q(stg9_reg_0), .R(1'b0)); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_rst_sync" *) module aurora_64b66b_0_aurora_64b66b_0_rst_sync__parameterized5 (cbcc_fifo_reset_to_fifo_rd_clk, stg1_aurora_64b66b_0_cdc_to_reg_0, stg31_reg_0); output cbcc_fifo_reset_to_fifo_rd_clk; input stg1_aurora_64b66b_0_cdc_to_reg_0; input stg31_reg_0; wire cbcc_fifo_reset_to_fifo_rd_clk; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg1_aurora_64b66b_0_cdc_to; wire stg1_aurora_64b66b_0_cdc_to_reg_0; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg2; (* async_reg = "true" *) (* shift_extract = "{no}" *) wire stg3; wire stg30_reg_srl27_n_0; wire stg31_reg_0; wire NLW_stg30_reg_srl27_Q31_UNCONNECTED; (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg1_aurora_64b66b_0_cdc_to_reg (.C(stg31_reg_0), .CE(1'b1), .D(stg1_aurora_64b66b_0_cdc_to_reg_0), .Q(stg1_aurora_64b66b_0_cdc_to), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg2_reg (.C(stg31_reg_0), .CE(1'b1), .D(stg1_aurora_64b66b_0_cdc_to), .Q(stg2), .R(1'b0)); (* srl_name = "inst/\aurora_64b66b_0_core_i/aurora_64b66b_0_wrapper_i/common_reset_cbcc_i/u_rst_sync_reset_to_fifo_rd_clk/stg30_reg_srl27 " *) SRLC32E #( .INIT(32'h07FFFFFF)) stg30_reg_srl27 (.A({1'b1,1'b1,1'b0,1'b1,1'b0}), .CE(1'b1), .CLK(stg31_reg_0), .D(stg3), .Q(stg30_reg_srl27_n_0), .Q31(NLW_stg30_reg_srl27_Q31_UNCONNECTED)); (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg31_reg (.C(stg31_reg_0), .CE(1'b1), .D(stg30_reg_srl27_n_0), .Q(cbcc_fifo_reset_to_fifo_rd_clk), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) (* shift_extract = "{no}" *) FDRE #( .INIT(1'b1)) stg3_reg (.C(stg31_reg_0), .CE(1'b1), .D(stg2), .Q(stg3), .R(1'b0)); endmodule (* DowngradeIPIdentifiedWarnings = "yes" *) (* ORIG_REF_NAME = "aurora_64b66b_0_support" *) module aurora_64b66b_0_aurora_64b66b_0_support (s_axi_tx_tdata, s_axi_tx_tvalid, s_axi_tx_tready, m_axi_rx_tdata, m_axi_rx_tvalid, rxp, rxn, txp, txn, hard_err, soft_err, channel_up, lane_up, user_clk_out, sync_clk_out, reset_pb, gt_rxcdrovrden_in, power_down, loopback, pma_init, gt0_drpdo, gt0_drprdy, gt0_drpaddr, gt0_drpdi, gt0_drpen, gt0_drpwe, init_clk, link_reset_out, gt_pll_lock, sys_reset_out, gt_reset_out, refclk1_in, gt_powergood, mmcm_not_locked_out, mmcm_not_locked_out2, tx_out_clk); input [0:63]s_axi_tx_tdata; input s_axi_tx_tvalid; output s_axi_tx_tready; output [0:63]m_axi_rx_tdata; output m_axi_rx_tvalid; input rxp; input rxn; output txp; output txn; output hard_err; output soft_err; output channel_up; output lane_up; output user_clk_out; output sync_clk_out; input reset_pb; input gt_rxcdrovrden_in; input power_down; input [2:0]loopback; input pma_init; output [15:0]gt0_drpdo; output gt0_drprdy; input [8:0]gt0_drpaddr; input [15:0]gt0_drpdi; input gt0_drpen; input gt0_drpwe; input init_clk; output link_reset_out; output gt_pll_lock; output sys_reset_out; output gt_reset_out; input refclk1_in; output [0:0]gt_powergood; output mmcm_not_locked_out; output mmcm_not_locked_out2; output tx_out_clk; wire bufg_gt_clr_out; wire channel_up; wire [8:0]gt0_drpaddr; wire [15:0]gt0_drpdi; wire [15:0]gt0_drpdo; wire gt0_drpen; wire gt0_drprdy; wire gt0_drpwe; wire gt_pll_lock; wire [0:0]gt_powergood; wire gt_reset_out; wire gt_reset_sync_n_0; wire gt_rxcdrovrden_in; wire hard_err; wire init_clk; wire lane_up; wire link_reset_out; wire [2:0]loopback; wire lopt; wire lopt_1; wire lopt_2; wire [0:63]m_axi_rx_tdata; wire m_axi_rx_tvalid; wire mmcm_not_locked_out; wire mmcm_not_locked_out2; wire pma_init; wire power_down; wire refclk1_in; wire reset_pb; wire rxn; wire rxp; wire [0:63]s_axi_tx_tdata; wire s_axi_tx_tready; wire s_axi_tx_tvalid; wire soft_err; wire stg5; wire sync_clk_out; wire sys_reset_out; wire sysreset_from_support; wire tx_out_clk; wire txn; wire txp; wire user_clk_out; aurora_64b66b_0_aurora_64b66b_0_core aurora_64b66b_0_core_i (.CHANNEL_UP_RX_IF_reg(channel_up), .SYSTEM_RESET_reg(sys_reset_out), .TX_PE_DATA_V_reg(user_clk_out), .bufg_gt_clr_out(bufg_gt_clr_out), .gt0_drpaddr(gt0_drpaddr), .gt0_drpdi(gt0_drpdi), .gt0_drpdo(gt0_drpdo), .gt0_drpen(gt0_drpen), .gt0_drprdy(gt0_drprdy), .gt0_drpwe(gt0_drpwe), .gt_pll_lock(gt_pll_lock), .gt_powergood(gt_powergood), .gt_rxcdrovrden_in(gt_rxcdrovrden_in), .hard_err(hard_err), .init_clk(init_clk), .lane_up_flop_i(lane_up), .link_reset_out(link_reset_out), .loopback(loopback), .lopt(lopt), .lopt_1(bufg_gt_clr_out), .lopt_2(lopt_1), .lopt_3(lopt_2), .m_axi_rx_tdata(m_axi_rx_tdata), .m_axi_rx_tvalid(m_axi_rx_tvalid), .mmcm_not_locked_out2(mmcm_not_locked_out2), .power_down(power_down), .refclk1_in(refclk1_in), .rxn(rxn), .rxp(rxp), .s_axi_tx_tdata(s_axi_tx_tdata), .s_axi_tx_tready(s_axi_tx_tready), .s_axi_tx_tvalid(s_axi_tx_tvalid), .soft_err(soft_err), .stg1_aurora_64b66b_0_cdc_to_reg(gt_reset_out), .sync_clk_out(sync_clk_out), .sysreset_from_support(sysreset_from_support), .tx_out_clk(tx_out_clk), .txn(txn), .txp(txp)); aurora_64b66b_0_aurora_64b66b_0_CLOCK_MODULE clock_module_i (.CLK(user_clk_out), .bufg_gt_clr_out(bufg_gt_clr_out), .lopt(lopt), .lopt_1(lopt_1), .lopt_2(lopt_2), .mmcm_not_locked_out(mmcm_not_locked_out), .mmcm_not_locked_out2(mmcm_not_locked_out2), .sync_clk_out(sync_clk_out), .tx_out_clk(tx_out_clk)); aurora_64b66b_0_aurora_64b66b_0_rst_sync gt_reset_sync (.D(gt_reset_sync_n_0), .init_clk(init_clk), .pma_init(pma_init)); aurora_64b66b_0_aurora_64b66b_0_rst_sync_0 reset_pb_sync (.CLK(user_clk_out), .D(stg5), .reset_pb(reset_pb)); aurora_64b66b_0_aurora_64b66b_0_SUPPORT_RESET_LOGIC support_reset_logic_i (.CLK(user_clk_out), .D(stg5), .\debounce_gt_rst_r_reg[0]_0 (gt_reset_sync_n_0), .gt_reset_out(gt_reset_out), .init_clk(init_clk), .sysreset_from_support(sysreset_from_support)); endmodule (* DowngradeIPIdentifiedWarnings = "yes" *) (* ORIG_REF_NAME = "aurora_64b66b_0_ultrascale_rx_userclk" *) (* P_CONTENTS = "0" *) (* P_FREQ_RATIO_SOURCE_TO_USRCLK = "1" *) (* P_FREQ_RATIO_USRCLK_TO_USRCLK2 = "1" *) (* P_USRCLK2_DIV = "3'b000" *) (* P_USRCLK2_INT_DIV = "0" *) (* P_USRCLK_DIV = "3'b000" *) (* P_USRCLK_INT_DIV = "0" *) (* keep_hierarchy = "soft" *) module aurora_64b66b_0_aurora_64b66b_0_ultrascale_rx_userclk (gtwiz_reset_clk_freerun_in, gtwiz_userclk_rx_srcclk_in, gtwiz_userclk_rx_reset_in, gtwiz_userclk_rx_usrclk_out, gtwiz_userclk_rx_usrclk2_out, gtwiz_userclk_rx_active_out, lopt, lopt_1, lopt_2); input gtwiz_reset_clk_freerun_in; input gtwiz_userclk_rx_srcclk_in; input gtwiz_userclk_rx_reset_in; output gtwiz_userclk_rx_usrclk_out; output gtwiz_userclk_rx_usrclk2_out; output gtwiz_userclk_rx_active_out; output lopt; input lopt_1; input lopt_2; wire \ ; (* async_reg = "true" *) wire \gen_gtwiz_userclk_rx_main.rx_active_aurora_64b66b_0_cdc_to ; (* async_reg = "true" *) wire \gen_gtwiz_userclk_rx_main.rx_active_cdc_to_stg2 ; wire gtwiz_userclk_rx_active_out; wire gtwiz_userclk_rx_reset_in; wire gtwiz_userclk_rx_srcclk_in; wire gtwiz_userclk_rx_usrclk2_out; wire \^lopt ; wire \^lopt_1 ; assign \^lopt = lopt_1; assign \^lopt_1 = lopt_2; assign gtwiz_userclk_rx_usrclk_out = gtwiz_userclk_rx_usrclk2_out; assign lopt = \ ; VCC VCC (.P(\ )); (* BOX_TYPE = "PRIMITIVE" *) (* OPT_MODIFIED = "MLO" *) BUFG_GT #( .SIM_DEVICE("ULTRASCALE"), .STARTUP_SYNC("FALSE")) \gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst (.CE(\^lopt ), .CEMASK(1'b0), .CLR(\^lopt_1 ), .CLRMASK(1'b0), .DIV({1'b0,1'b0,1'b0}), .I(gtwiz_userclk_rx_srcclk_in), .O(gtwiz_userclk_rx_usrclk2_out)); FDCE #( .INIT(1'b0)) \gen_gtwiz_userclk_rx_main.gtwiz_userclk_rx_active_out_reg (.C(gtwiz_userclk_rx_usrclk2_out), .CE(1'b1), .CLR(gtwiz_userclk_rx_reset_in), .D(\gen_gtwiz_userclk_rx_main.rx_active_cdc_to_stg2 ), .Q(gtwiz_userclk_rx_active_out)); (* ASYNC_REG *) (* KEEP = "yes" *) FDCE #( .INIT(1'b0)) \gen_gtwiz_userclk_rx_main.rx_active_aurora_64b66b_0_cdc_to_reg (.C(gtwiz_userclk_rx_usrclk2_out), .CE(1'b1), .CLR(gtwiz_userclk_rx_reset_in), .D(1'b1), .Q(\gen_gtwiz_userclk_rx_main.rx_active_aurora_64b66b_0_cdc_to )); (* ASYNC_REG *) (* KEEP = "yes" *) FDCE #( .INIT(1'b0)) \gen_gtwiz_userclk_rx_main.rx_active_cdc_to_stg2_reg (.C(gtwiz_userclk_rx_usrclk2_out), .CE(1'b1), .CLR(gtwiz_userclk_rx_reset_in), .D(\gen_gtwiz_userclk_rx_main.rx_active_aurora_64b66b_0_cdc_to ), .Q(\gen_gtwiz_userclk_rx_main.rx_active_cdc_to_stg2 )); endmodule (* ORIG_REF_NAME = "aurora_64b66b_0_ultrascale_tx_userclk" *) module aurora_64b66b_0_aurora_64b66b_0_ultrascale_tx_userclk (init_clk, sync_clk_out, mmcm_not_locked_out, mmcm_not_locked_out2, bufg_gt_clr_out, tx_out_clk, lopt, lopt_1, lopt_2); output init_clk; output sync_clk_out; output mmcm_not_locked_out; output mmcm_not_locked_out2; input bufg_gt_clr_out; input tx_out_clk; output lopt; input lopt_1; input lopt_2; wire \ ; wire bufg_gt_clr_out; (* async_reg = "true" *) wire \gen_gtwiz_userclk_tx_main.tx_active_aurora_64b66b_0_cdc_to ; (* async_reg = "true" *) wire \gen_gtwiz_userclk_tx_main.tx_active_cdc_to_stg2 ; wire init_clk; wire \^lopt ; wire \^lopt_1 ; (* async_reg = "true" *) wire mmcm_not_locked_out; wire mmcm_not_locked_out2; wire sync_clk_out; wire tx_out_clk; assign \^lopt = lopt_1; assign \^lopt_1 = lopt_2; assign lopt = \ ; VCC VCC (.P(\ )); (* BOX_TYPE = "PRIMITIVE" *) (* OPT_MODIFIED = "MLO" *) BUFG_GT #( .SIM_DEVICE("ULTRASCALE"), .STARTUP_SYNC("FALSE")) \gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst (.CE(\^lopt ), .CEMASK(1'b0), .CLR(\^lopt_1 ), .CLRMASK(1'b0), .DIV({1'b0,1'b0,1'b1}), .I(tx_out_clk), .O(init_clk)); (* BOX_TYPE = "PRIMITIVE" *) (* OPT_MODIFIED = "MLO" *) BUFG_GT #( .SIM_DEVICE("ULTRASCALE"), .STARTUP_SYNC("FALSE")) \gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst (.CE(\^lopt ), .CEMASK(1'b0), .CLR(\^lopt_1 ), .CLRMASK(1'b0), .DIV({1'b0,1'b0,1'b0}), .I(tx_out_clk), .O(sync_clk_out)); (* ASYNC_REG *) (* KEEP = "yes" *) FDCE #( .INIT(1'b0)) \gen_gtwiz_userclk_tx_main.gtwiz_userclk_tx_active_out_reg (.C(init_clk), .CE(1'b1), .CLR(bufg_gt_clr_out), .D(\gen_gtwiz_userclk_tx_main.tx_active_cdc_to_stg2 ), .Q(mmcm_not_locked_out)); (* ASYNC_REG *) (* KEEP = "yes" *) FDCE #( .INIT(1'b0)) \gen_gtwiz_userclk_tx_main.tx_active_aurora_64b66b_0_cdc_to_reg (.C(init_clk), .CE(1'b1), .CLR(bufg_gt_clr_out), .D(1'b1), .Q(\gen_gtwiz_userclk_tx_main.tx_active_aurora_64b66b_0_cdc_to )); (* ASYNC_REG *) (* KEEP = "yes" *) FDCE #( .INIT(1'b0)) \gen_gtwiz_userclk_tx_main.tx_active_cdc_to_stg2_reg (.C(init_clk), .CE(1'b1), .CLR(bufg_gt_clr_out), .D(\gen_gtwiz_userclk_tx_main.tx_active_aurora_64b66b_0_cdc_to ), .Q(\gen_gtwiz_userclk_tx_main.tx_active_cdc_to_stg2 )); LUT1 #( .INIT(2'h1)) mmcm_not_locked_out2_INST_0 (.I0(mmcm_not_locked_out), .O(mmcm_not_locked_out2)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_bit_synchronizer" *) module aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer (\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync , rxresetdone_out, drpclk_in); output \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ; input [0:0]rxresetdone_out; input [0:0]drpclk_in; wire [0:0]drpclk_in; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ; (* async_reg = "true" *) wire i_in_meta; (* async_reg = "true" *) wire i_in_sync1; (* async_reg = "true" *) wire i_in_sync2; (* async_reg = "true" *) wire i_in_sync3; wire [0:0]rxresetdone_out; (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(rxresetdone_out), .Q(i_in_meta), .R(1'b0)); FDRE #( .INIT(1'b0)) i_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync3), .Q(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_meta), .Q(i_in_sync1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync1), .Q(i_in_sync2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync2), .Q(i_in_sync3), .R(1'b0)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_bit_synchronizer" *) module aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_30 (\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync , txresetdone_out, drpclk_in); output \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ; input [0:0]txresetdone_out; input [0:0]drpclk_in; wire [0:0]drpclk_in; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ; (* async_reg = "true" *) wire i_in_meta; (* async_reg = "true" *) wire i_in_sync1; (* async_reg = "true" *) wire i_in_sync2; (* async_reg = "true" *) wire i_in_sync3; wire [0:0]txresetdone_out; (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(txresetdone_out), .Q(i_in_meta), .R(1'b0)); FDRE #( .INIT(1'b0)) i_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync3), .Q(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_meta), .Q(i_in_sync1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync1), .Q(i_in_sync2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync2), .Q(i_in_sync3), .R(1'b0)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_bit_synchronizer" *) module aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_31 (E, gtpowergood_out, drpclk_in, \FSM_sequential_sm_reset_all_reg[0] , Q, \FSM_sequential_sm_reset_all_reg[0]_0 ); output [0:0]E; input [0:0]gtpowergood_out; input [0:0]drpclk_in; input \FSM_sequential_sm_reset_all_reg[0] ; input [2:0]Q; input \FSM_sequential_sm_reset_all_reg[0]_0 ; wire [0:0]E; wire \FSM_sequential_sm_reset_all_reg[0] ; wire \FSM_sequential_sm_reset_all_reg[0]_0 ; wire [2:0]Q; wire [0:0]drpclk_in; wire [0:0]gtpowergood_out; wire gtpowergood_sync; (* async_reg = "true" *) wire i_in_meta; (* async_reg = "true" *) wire i_in_sync1; (* async_reg = "true" *) wire i_in_sync2; (* async_reg = "true" *) wire i_in_sync3; LUT6 #( .INIT(64'hAF0FAF00CFFFCFFF)) \FSM_sequential_sm_reset_all[2]_i_1 (.I0(gtpowergood_sync), .I1(\FSM_sequential_sm_reset_all_reg[0] ), .I2(Q[2]), .I3(Q[0]), .I4(\FSM_sequential_sm_reset_all_reg[0]_0 ), .I5(Q[1]), .O(E)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(gtpowergood_out), .Q(i_in_meta), .R(1'b0)); FDRE #( .INIT(1'b0)) i_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync3), .Q(gtpowergood_sync), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_meta), .Q(i_in_sync1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync1), .Q(i_in_sync2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync2), .Q(i_in_sync3), .R(1'b0)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_bit_synchronizer" *) module aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_32 (gtwiz_reset_rx_datapath_dly, in0, drpclk_in); output gtwiz_reset_rx_datapath_dly; input in0; input [0:0]drpclk_in; wire [0:0]drpclk_in; wire gtwiz_reset_rx_datapath_dly; (* async_reg = "true" *) wire i_in_meta; (* async_reg = "true" *) wire i_in_sync1; (* async_reg = "true" *) wire i_in_sync2; (* async_reg = "true" *) wire i_in_sync3; wire in0; (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(in0), .Q(i_in_meta), .R(1'b0)); FDRE #( .INIT(1'b0)) i_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync3), .Q(gtwiz_reset_rx_datapath_dly), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_meta), .Q(i_in_sync1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync1), .Q(i_in_sync2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync2), .Q(i_in_sync3), .R(1'b0)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_bit_synchronizer" *) module aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_33 (D, i_in_out_reg_0, in0, drpclk_in, \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync , \FSM_sequential_sm_reset_rx_reg[0] , Q, gtwiz_reset_rx_datapath_dly, \FSM_sequential_sm_reset_rx_reg[0]_0 ); output [1:0]D; output i_in_out_reg_0; input in0; input [0:0]drpclk_in; input \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ; input \FSM_sequential_sm_reset_rx_reg[0] ; input [2:0]Q; input gtwiz_reset_rx_datapath_dly; input \FSM_sequential_sm_reset_rx_reg[0]_0 ; wire [1:0]D; wire \FSM_sequential_sm_reset_rx_reg[0] ; wire \FSM_sequential_sm_reset_rx_reg[0]_0 ; wire [2:0]Q; wire [0:0]drpclk_in; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ; wire gtwiz_reset_rx_datapath_dly; wire gtwiz_reset_rx_pll_and_datapath_dly; (* async_reg = "true" *) wire i_in_meta; wire i_in_out_reg_0; (* async_reg = "true" *) wire i_in_sync1; (* async_reg = "true" *) wire i_in_sync2; (* async_reg = "true" *) wire i_in_sync3; wire in0; LUT6 #( .INIT(64'hFF0088FF00FFFFF0)) \FSM_sequential_sm_reset_rx[0]_i_1 (.I0(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ), .I1(\FSM_sequential_sm_reset_rx_reg[0] ), .I2(gtwiz_reset_rx_pll_and_datapath_dly), .I3(Q[2]), .I4(Q[0]), .I5(Q[1]), .O(D[0])); LUT6 #( .INIT(64'h0000FFFF8F8F000F)) \FSM_sequential_sm_reset_rx[1]_i_1 (.I0(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ), .I1(\FSM_sequential_sm_reset_rx_reg[0] ), .I2(Q[2]), .I3(gtwiz_reset_rx_pll_and_datapath_dly), .I4(Q[1]), .I5(Q[0]), .O(D[1])); LUT6 #( .INIT(64'hFFFFFFFF0000000E)) \FSM_sequential_sm_reset_rx[2]_i_5 (.I0(gtwiz_reset_rx_pll_and_datapath_dly), .I1(gtwiz_reset_rx_datapath_dly), .I2(Q[2]), .I3(Q[1]), .I4(Q[0]), .I5(\FSM_sequential_sm_reset_rx_reg[0]_0 ), .O(i_in_out_reg_0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(in0), .Q(i_in_meta), .R(1'b0)); FDRE #( .INIT(1'b0)) i_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync3), .Q(gtwiz_reset_rx_pll_and_datapath_dly), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_meta), .Q(i_in_sync1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync1), .Q(i_in_sync2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync2), .Q(i_in_sync3), .R(1'b0)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_bit_synchronizer" *) module aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_34 (E, in0, drpclk_in, Q, \FSM_sequential_sm_reset_tx_reg[0] , gtwiz_reset_tx_pll_and_datapath_dly, \FSM_sequential_sm_reset_tx_reg[0]_0 , \FSM_sequential_sm_reset_tx_reg[0]_1 ); output [0:0]E; input in0; input [0:0]drpclk_in; input [0:0]Q; input \FSM_sequential_sm_reset_tx_reg[0] ; input gtwiz_reset_tx_pll_and_datapath_dly; input \FSM_sequential_sm_reset_tx_reg[0]_0 ; input \FSM_sequential_sm_reset_tx_reg[0]_1 ; wire [0:0]E; wire \FSM_sequential_sm_reset_tx_reg[0] ; wire \FSM_sequential_sm_reset_tx_reg[0]_0 ; wire \FSM_sequential_sm_reset_tx_reg[0]_1 ; wire [0:0]Q; wire [0:0]drpclk_in; wire gtwiz_reset_tx_datapath_dly; wire gtwiz_reset_tx_pll_and_datapath_dly; (* async_reg = "true" *) wire i_in_meta; (* async_reg = "true" *) wire i_in_sync1; (* async_reg = "true" *) wire i_in_sync2; (* async_reg = "true" *) wire i_in_sync3; wire in0; LUT6 #( .INIT(64'hFFFFFFFFFFFF1110)) \FSM_sequential_sm_reset_tx[2]_i_1 (.I0(Q), .I1(\FSM_sequential_sm_reset_tx_reg[0] ), .I2(gtwiz_reset_tx_datapath_dly), .I3(gtwiz_reset_tx_pll_and_datapath_dly), .I4(\FSM_sequential_sm_reset_tx_reg[0]_0 ), .I5(\FSM_sequential_sm_reset_tx_reg[0]_1 ), .O(E)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(in0), .Q(i_in_meta), .R(1'b0)); FDRE #( .INIT(1'b0)) i_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync3), .Q(gtwiz_reset_tx_datapath_dly), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_meta), .Q(i_in_sync1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync1), .Q(i_in_sync2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync2), .Q(i_in_sync3), .R(1'b0)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_bit_synchronizer" *) module aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_35 (gtwiz_reset_tx_pll_and_datapath_dly, D, in0, drpclk_in, Q); output gtwiz_reset_tx_pll_and_datapath_dly; output [1:0]D; input in0; input [0:0]drpclk_in; input [2:0]Q; wire [1:0]D; wire [2:0]Q; wire [0:0]drpclk_in; wire gtwiz_reset_tx_pll_and_datapath_dly; (* async_reg = "true" *) wire i_in_meta; (* async_reg = "true" *) wire i_in_sync1; (* async_reg = "true" *) wire i_in_sync2; (* async_reg = "true" *) wire i_in_sync3; wire in0; (* SOFT_HLUTNM = "soft_lutpair0" *) LUT4 #( .INIT(16'h1F1E)) \FSM_sequential_sm_reset_tx[0]_i_1 (.I0(Q[1]), .I1(Q[2]), .I2(Q[0]), .I3(gtwiz_reset_tx_pll_and_datapath_dly), .O(D[0])); (* SOFT_HLUTNM = "soft_lutpair0" *) LUT4 #( .INIT(16'h0FF1)) \FSM_sequential_sm_reset_tx[1]_i_1 (.I0(Q[2]), .I1(gtwiz_reset_tx_pll_and_datapath_dly), .I2(Q[1]), .I3(Q[0]), .O(D[1])); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(in0), .Q(i_in_meta), .R(1'b0)); FDRE #( .INIT(1'b0)) i_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync3), .Q(gtwiz_reset_tx_pll_and_datapath_dly), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_meta), .Q(i_in_sync1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync1), .Q(i_in_sync2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync2), .Q(i_in_sync3), .R(1'b0)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_bit_synchronizer" *) module aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_36 (\FSM_sequential_sm_reset_rx_reg[0] , \FSM_sequential_sm_reset_rx_reg[2] , E, gtwiz_userclk_rx_active_in, drpclk_in, sm_reset_rx_timer_clr_reg, Q, sm_reset_rx_timer_clr_reg_0, gtwiz_reset_rx_any_sync, \gen_gtwizard_gthe3.rxuserrdy_int , \FSM_sequential_sm_reset_rx_reg[0]_0 , \FSM_sequential_sm_reset_rx_reg[0]_1 , \FSM_sequential_sm_reset_rx_reg[0]_2 , sm_reset_rx_pll_timer_sat, sm_reset_rx_timer_sat); output \FSM_sequential_sm_reset_rx_reg[0] ; output \FSM_sequential_sm_reset_rx_reg[2] ; output [0:0]E; input [0:0]gtwiz_userclk_rx_active_in; input [0:0]drpclk_in; input sm_reset_rx_timer_clr_reg; input [2:0]Q; input sm_reset_rx_timer_clr_reg_0; input gtwiz_reset_rx_any_sync; input \gen_gtwizard_gthe3.rxuserrdy_int ; input \FSM_sequential_sm_reset_rx_reg[0]_0 ; input \FSM_sequential_sm_reset_rx_reg[0]_1 ; input \FSM_sequential_sm_reset_rx_reg[0]_2 ; input sm_reset_rx_pll_timer_sat; input sm_reset_rx_timer_sat; wire [0:0]E; wire \FSM_sequential_sm_reset_rx[2]_i_3_n_0 ; wire \FSM_sequential_sm_reset_rx_reg[0] ; wire \FSM_sequential_sm_reset_rx_reg[0]_0 ; wire \FSM_sequential_sm_reset_rx_reg[0]_1 ; wire \FSM_sequential_sm_reset_rx_reg[0]_2 ; wire \FSM_sequential_sm_reset_rx_reg[2] ; wire [2:0]Q; wire [0:0]drpclk_in; wire \gen_gtwizard_gthe3.rxuserrdy_int ; wire gtwiz_reset_rx_any_sync; wire gtwiz_reset_userclk_rx_active_sync; wire [0:0]gtwiz_userclk_rx_active_in; (* async_reg = "true" *) wire i_in_meta; (* async_reg = "true" *) wire i_in_sync1; (* async_reg = "true" *) wire i_in_sync2; (* async_reg = "true" *) wire i_in_sync3; wire sm_reset_rx_pll_timer_sat; wire sm_reset_rx_timer_clr_i_2_n_0; wire sm_reset_rx_timer_clr_reg; wire sm_reset_rx_timer_clr_reg_0; wire sm_reset_rx_timer_sat; LUT3 #( .INIT(8'hFE)) \FSM_sequential_sm_reset_rx[2]_i_1 (.I0(\FSM_sequential_sm_reset_rx[2]_i_3_n_0 ), .I1(\FSM_sequential_sm_reset_rx_reg[0]_0 ), .I2(\FSM_sequential_sm_reset_rx_reg[0]_1 ), .O(E)); LUT6 #( .INIT(64'h2023202000000000)) \FSM_sequential_sm_reset_rx[2]_i_3 (.I0(sm_reset_rx_timer_clr_i_2_n_0), .I1(Q[1]), .I2(Q[2]), .I3(\FSM_sequential_sm_reset_rx_reg[0]_2 ), .I4(sm_reset_rx_pll_timer_sat), .I5(Q[0]), .O(\FSM_sequential_sm_reset_rx[2]_i_3_n_0 )); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(gtwiz_userclk_rx_active_in), .Q(i_in_meta), .R(1'b0)); FDRE #( .INIT(1'b0)) i_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync3), .Q(gtwiz_reset_userclk_rx_active_sync), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_meta), .Q(i_in_sync1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync1), .Q(i_in_sync2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync2), .Q(i_in_sync3), .R(1'b0)); LUT6 #( .INIT(64'hFFFFFAAF00000800)) rxuserrdy_out_i_1 (.I0(Q[2]), .I1(sm_reset_rx_timer_clr_i_2_n_0), .I2(Q[1]), .I3(Q[0]), .I4(gtwiz_reset_rx_any_sync), .I5(\gen_gtwizard_gthe3.rxuserrdy_int ), .O(\FSM_sequential_sm_reset_rx_reg[2] )); LUT6 #( .INIT(64'hFCCCEFFE0CCCE00E)) sm_reset_rx_timer_clr_i_1 (.I0(sm_reset_rx_timer_clr_i_2_n_0), .I1(sm_reset_rx_timer_clr_reg), .I2(Q[0]), .I3(Q[2]), .I4(Q[1]), .I5(sm_reset_rx_timer_clr_reg_0), .O(\FSM_sequential_sm_reset_rx_reg[0] )); LUT3 #( .INIT(8'h40)) sm_reset_rx_timer_clr_i_2 (.I0(sm_reset_rx_timer_clr_reg_0), .I1(sm_reset_rx_timer_sat), .I2(gtwiz_reset_userclk_rx_active_sync), .O(sm_reset_rx_timer_clr_i_2_n_0)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_bit_synchronizer" *) module aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_37 (gtwiz_reset_userclk_tx_active_sync, \FSM_sequential_sm_reset_tx_reg[2] , i_in_out_reg_0, gtwiz_userclk_tx_active_in, drpclk_in, Q, sm_reset_tx_timer_clr_reg, \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync , sm_reset_tx_timer_clr_reg_0, plllock_tx_sync, \FSM_sequential_sm_reset_tx_reg[0] , \FSM_sequential_sm_reset_tx_reg[0]_0 , \FSM_sequential_sm_reset_tx_reg[0]_1 , sm_reset_tx_pll_timer_sat); output gtwiz_reset_userclk_tx_active_sync; output \FSM_sequential_sm_reset_tx_reg[2] ; output i_in_out_reg_0; input [0:0]gtwiz_userclk_tx_active_in; input [0:0]drpclk_in; input [2:0]Q; input sm_reset_tx_timer_clr_reg; input \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ; input sm_reset_tx_timer_clr_reg_0; input plllock_tx_sync; input \FSM_sequential_sm_reset_tx_reg[0] ; input \FSM_sequential_sm_reset_tx_reg[0]_0 ; input \FSM_sequential_sm_reset_tx_reg[0]_1 ; input sm_reset_tx_pll_timer_sat; wire \FSM_sequential_sm_reset_tx_reg[0] ; wire \FSM_sequential_sm_reset_tx_reg[0]_0 ; wire \FSM_sequential_sm_reset_tx_reg[0]_1 ; wire \FSM_sequential_sm_reset_tx_reg[2] ; wire [2:0]Q; wire [0:0]drpclk_in; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ; wire gtwiz_reset_userclk_tx_active_sync; wire [0:0]gtwiz_userclk_tx_active_in; (* async_reg = "true" *) wire i_in_meta; wire i_in_out_reg_0; (* async_reg = "true" *) wire i_in_sync1; (* async_reg = "true" *) wire i_in_sync2; (* async_reg = "true" *) wire i_in_sync3; wire plllock_tx_sync; wire sm_reset_tx_pll_timer_sat; wire sm_reset_tx_timer_clr_i_2_n_0; wire sm_reset_tx_timer_clr_reg; wire sm_reset_tx_timer_clr_reg_0; LUT6 #( .INIT(64'h000F000088888888)) \FSM_sequential_sm_reset_tx[2]_i_5 (.I0(\FSM_sequential_sm_reset_tx_reg[0] ), .I1(gtwiz_reset_userclk_tx_active_sync), .I2(\FSM_sequential_sm_reset_tx_reg[0]_0 ), .I3(\FSM_sequential_sm_reset_tx_reg[0]_1 ), .I4(sm_reset_tx_pll_timer_sat), .I5(Q[0]), .O(i_in_out_reg_0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(gtwiz_userclk_tx_active_in), .Q(i_in_meta), .R(1'b0)); FDRE #( .INIT(1'b0)) i_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync3), .Q(gtwiz_reset_userclk_tx_active_sync), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_meta), .Q(i_in_sync1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync1), .Q(i_in_sync2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync2), .Q(i_in_sync3), .R(1'b0)); LUT5 #( .INIT(32'hEBEB282B)) sm_reset_tx_timer_clr_i_1 (.I0(sm_reset_tx_timer_clr_i_2_n_0), .I1(Q[2]), .I2(Q[1]), .I3(Q[0]), .I4(sm_reset_tx_timer_clr_reg), .O(\FSM_sequential_sm_reset_tx_reg[2] )); LUT6 #( .INIT(64'hA0C0A0C0F0F000F0)) sm_reset_tx_timer_clr_i_2 (.I0(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ), .I1(gtwiz_reset_userclk_tx_active_sync), .I2(sm_reset_tx_timer_clr_reg_0), .I3(Q[0]), .I4(plllock_tx_sync), .I5(Q[2]), .O(sm_reset_tx_timer_clr_i_2_n_0)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_bit_synchronizer" *) module aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_38 (plllock_rx_sync, i_in_out_reg_0, \FSM_sequential_sm_reset_rx_reg[1] , cplllock_out, drpclk_in, gtwiz_reset_rx_done_int_reg, \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync , Q, gtwiz_reset_rx_done_int_reg_0); output plllock_rx_sync; output i_in_out_reg_0; output \FSM_sequential_sm_reset_rx_reg[1] ; input [0:0]cplllock_out; input [0:0]drpclk_in; input gtwiz_reset_rx_done_int_reg; input \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ; input [2:0]Q; input gtwiz_reset_rx_done_int_reg_0; wire \FSM_sequential_sm_reset_rx_reg[1] ; wire [2:0]Q; wire [0:0]cplllock_out; wire [0:0]drpclk_in; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ; wire gtwiz_reset_rx_done_int; wire gtwiz_reset_rx_done_int_reg; wire gtwiz_reset_rx_done_int_reg_0; (* async_reg = "true" *) wire i_in_meta; wire i_in_out_reg_0; (* async_reg = "true" *) wire i_in_sync1; (* async_reg = "true" *) wire i_in_sync2; (* async_reg = "true" *) wire i_in_sync3; wire plllock_rx_sync; LUT6 #( .INIT(64'hAAC0FFFFAAC00000)) gtwiz_reset_rx_done_int_i_1 (.I0(plllock_rx_sync), .I1(gtwiz_reset_rx_done_int_reg), .I2(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ), .I3(Q[0]), .I4(gtwiz_reset_rx_done_int), .I5(gtwiz_reset_rx_done_int_reg_0), .O(i_in_out_reg_0)); LUT6 #( .INIT(64'h4C40000040400000)) gtwiz_reset_rx_done_int_i_2 (.I0(plllock_rx_sync), .I1(Q[2]), .I2(Q[0]), .I3(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ), .I4(Q[1]), .I5(gtwiz_reset_rx_done_int_reg), .O(gtwiz_reset_rx_done_int)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(cplllock_out), .Q(i_in_meta), .R(1'b0)); FDRE #( .INIT(1'b0)) i_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync3), .Q(plllock_rx_sync), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_meta), .Q(i_in_sync1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync1), .Q(i_in_sync2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync2), .Q(i_in_sync3), .R(1'b0)); LUT6 #( .INIT(64'h88880000F5FF5555)) sm_reset_rx_timer_clr_i_3 (.I0(Q[1]), .I1(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ), .I2(plllock_rx_sync), .I3(Q[0]), .I4(gtwiz_reset_rx_done_int_reg), .I5(Q[2]), .O(\FSM_sequential_sm_reset_rx_reg[1] )); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_bit_synchronizer" *) module aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_39 (plllock_tx_sync, gtwiz_reset_tx_done_int_reg, i_in_out_reg_0, cplllock_out, drpclk_in, gtwiz_reset_tx_done_int_reg_0, Q, sm_reset_tx_timer_sat, gtwiz_reset_tx_done_int_reg_1, \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync , \FSM_sequential_sm_reset_tx_reg[0] ); output plllock_tx_sync; output gtwiz_reset_tx_done_int_reg; output i_in_out_reg_0; input [0:0]cplllock_out; input [0:0]drpclk_in; input gtwiz_reset_tx_done_int_reg_0; input [2:0]Q; input sm_reset_tx_timer_sat; input gtwiz_reset_tx_done_int_reg_1; input \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ; input \FSM_sequential_sm_reset_tx_reg[0] ; wire \FSM_sequential_sm_reset_tx_reg[0] ; wire [2:0]Q; wire [0:0]cplllock_out; wire [0:0]drpclk_in; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ; wire gtwiz_reset_tx_done_int; wire gtwiz_reset_tx_done_int_i_2_n_0; wire gtwiz_reset_tx_done_int_reg; wire gtwiz_reset_tx_done_int_reg_0; wire gtwiz_reset_tx_done_int_reg_1; (* async_reg = "true" *) wire i_in_meta; wire i_in_out_reg_0; (* async_reg = "true" *) wire i_in_sync1; (* async_reg = "true" *) wire i_in_sync2; (* async_reg = "true" *) wire i_in_sync3; wire plllock_tx_sync; wire sm_reset_tx_timer_sat; LUT6 #( .INIT(64'h00CFA00000000000)) \FSM_sequential_sm_reset_tx[2]_i_4 (.I0(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ), .I1(plllock_tx_sync), .I2(Q[0]), .I3(Q[2]), .I4(Q[1]), .I5(\FSM_sequential_sm_reset_tx_reg[0] ), .O(i_in_out_reg_0)); LUT3 #( .INIT(8'hB8)) gtwiz_reset_tx_done_int_i_1 (.I0(gtwiz_reset_tx_done_int_i_2_n_0), .I1(gtwiz_reset_tx_done_int), .I2(gtwiz_reset_tx_done_int_reg_0), .O(gtwiz_reset_tx_done_int_reg)); LUT6 #( .INIT(64'h4444444444F44444)) gtwiz_reset_tx_done_int_i_2 (.I0(Q[0]), .I1(plllock_tx_sync), .I2(sm_reset_tx_timer_sat), .I3(gtwiz_reset_tx_done_int_reg_1), .I4(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ), .I5(Q[1]), .O(gtwiz_reset_tx_done_int_i_2_n_0)); LUT6 #( .INIT(64'h3000404000004040)) gtwiz_reset_tx_done_int_i_3 (.I0(plllock_tx_sync), .I1(Q[1]), .I2(Q[2]), .I3(\FSM_sequential_sm_reset_tx_reg[0] ), .I4(Q[0]), .I5(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ), .O(gtwiz_reset_tx_done_int)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(cplllock_out), .Q(i_in_meta), .R(1'b0)); FDRE #( .INIT(1'b0)) i_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync3), .Q(plllock_tx_sync), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_meta), .Q(i_in_sync1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync1), .Q(i_in_sync2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync2), .Q(i_in_sync3), .R(1'b0)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_bit_synchronizer" *) module aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_40 (\FSM_sequential_sm_reset_rx_reg[2] , \FSM_sequential_sm_reset_rx_reg[1] , sm_reset_rx_cdr_to_sat_reg, rxcdrlock_out, drpclk_in, sm_reset_rx_cdr_to_clr_reg, Q, plllock_rx_sync, sm_reset_rx_cdr_to_clr, \FSM_sequential_sm_reset_rx_reg[0] , sm_reset_rx_cdr_to_sat); output \FSM_sequential_sm_reset_rx_reg[2] ; output \FSM_sequential_sm_reset_rx_reg[1] ; output sm_reset_rx_cdr_to_sat_reg; input [0:0]rxcdrlock_out; input [0:0]drpclk_in; input sm_reset_rx_cdr_to_clr_reg; input [2:0]Q; input plllock_rx_sync; input sm_reset_rx_cdr_to_clr; input \FSM_sequential_sm_reset_rx_reg[0] ; input sm_reset_rx_cdr_to_sat; wire \FSM_sequential_sm_reset_rx_reg[0] ; wire \FSM_sequential_sm_reset_rx_reg[1] ; wire \FSM_sequential_sm_reset_rx_reg[2] ; wire [2:0]Q; wire [0:0]drpclk_in; (* async_reg = "true" *) wire i_in_meta; wire i_in_out_reg_n_0; (* async_reg = "true" *) wire i_in_sync1; (* async_reg = "true" *) wire i_in_sync2; (* async_reg = "true" *) wire i_in_sync3; wire plllock_rx_sync; wire [0:0]rxcdrlock_out; wire sm_reset_rx_cdr_to_clr; wire sm_reset_rx_cdr_to_clr_i_2_n_0; wire sm_reset_rx_cdr_to_clr_reg; wire sm_reset_rx_cdr_to_sat; wire sm_reset_rx_cdr_to_sat_reg; LUT6 #( .INIT(64'h000A000AC0C000C0)) \FSM_sequential_sm_reset_rx[2]_i_4 (.I0(sm_reset_rx_cdr_to_sat_reg), .I1(\FSM_sequential_sm_reset_rx_reg[0] ), .I2(Q[1]), .I3(Q[0]), .I4(plllock_rx_sync), .I5(Q[2]), .O(\FSM_sequential_sm_reset_rx_reg[1] )); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(rxcdrlock_out), .Q(i_in_meta), .R(1'b0)); FDRE #( .INIT(1'b0)) i_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync3), .Q(i_in_out_reg_n_0), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_meta), .Q(i_in_sync1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync1), .Q(i_in_sync2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) i_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(i_in_sync2), .Q(i_in_sync3), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair1" *) LUT2 #( .INIT(4'hE)) rxprogdivreset_out_i_2 (.I0(sm_reset_rx_cdr_to_sat), .I1(i_in_out_reg_n_0), .O(sm_reset_rx_cdr_to_sat_reg)); LUT6 #( .INIT(64'hFBFFFFFF0800AAAA)) sm_reset_rx_cdr_to_clr_i_1 (.I0(sm_reset_rx_cdr_to_clr_i_2_n_0), .I1(sm_reset_rx_cdr_to_clr_reg), .I2(Q[2]), .I3(plllock_rx_sync), .I4(Q[0]), .I5(sm_reset_rx_cdr_to_clr), .O(\FSM_sequential_sm_reset_rx_reg[2] )); (* SOFT_HLUTNM = "soft_lutpair1" *) LUT4 #( .INIT(16'h00EF)) sm_reset_rx_cdr_to_clr_i_2 (.I0(sm_reset_rx_cdr_to_sat), .I1(i_in_out_reg_n_0), .I2(Q[2]), .I3(Q[1]), .O(sm_reset_rx_cdr_to_clr_i_2_n_0)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_gthe3_channel" *) module aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_gthe3_channel (cplllock_out, drprdy_out, gthtxn_out, gthtxp_out, gtpowergood_out, rxcdrlock_out, rxoutclk_out, rxpmaresetdone_out, rxresetdone_out, txoutclk_out, txpmaresetdone_out, txresetdone_out, gtwiz_userdata_rx_out, drpdo_out, rxdatavalid_out, rxheadervalid_out, txbufstatus_out, rxbufstatus_out, rxheader_out, rst_in0, \gen_gtwizard_gthe3.cpllpd_ch_int , drpclk_in, drpen_in, drpwe_in, gthrxn_in, gthrxp_in, gtrefclk0_in, \gen_gtwizard_gthe3.gtrxreset_int , \gen_gtwizard_gthe3.gttxreset_int , rxcdrovrden_in, rxgearboxslip_in, rxpolarity_in, \gen_gtwizard_gthe3.rxprogdivreset_int , \gen_gtwizard_gthe3.rxuserrdy_int , rxusrclk_in, rxusrclk2_in, \gen_gtwizard_gthe3.txprogdivreset_int , \gen_gtwizard_gthe3.txuserrdy_int , txusrclk_in, txusrclk2_in, gtwiz_userdata_tx_in, drpdi_in, loopback_in, txheader_in, txsequence_in, drpaddr_in, lopt, lopt_1, lopt_2, lopt_3, lopt_4, lopt_5, lopt_6, lopt_7); output [0:0]cplllock_out; output [0:0]drprdy_out; output [0:0]gthtxn_out; output [0:0]gthtxp_out; output [0:0]gtpowergood_out; output [0:0]rxcdrlock_out; output [0:0]rxoutclk_out; output [0:0]rxpmaresetdone_out; output [0:0]rxresetdone_out; output [0:0]txoutclk_out; output [0:0]txpmaresetdone_out; output [0:0]txresetdone_out; output [31:0]gtwiz_userdata_rx_out; output [15:0]drpdo_out; output [0:0]rxdatavalid_out; output [0:0]rxheadervalid_out; output [0:0]txbufstatus_out; output [0:0]rxbufstatus_out; output [1:0]rxheader_out; output rst_in0; input \gen_gtwizard_gthe3.cpllpd_ch_int ; input [0:0]drpclk_in; input [0:0]drpen_in; input [0:0]drpwe_in; input [0:0]gthrxn_in; input [0:0]gthrxp_in; input [0:0]gtrefclk0_in; input \gen_gtwizard_gthe3.gtrxreset_int ; input \gen_gtwizard_gthe3.gttxreset_int ; input [0:0]rxcdrovrden_in; input [0:0]rxgearboxslip_in; input [0:0]rxpolarity_in; input \gen_gtwizard_gthe3.rxprogdivreset_int ; input \gen_gtwizard_gthe3.rxuserrdy_int ; input [0:0]rxusrclk_in; input [0:0]rxusrclk2_in; input \gen_gtwizard_gthe3.txprogdivreset_int ; input \gen_gtwizard_gthe3.txuserrdy_int ; input [0:0]txusrclk_in; input [0:0]txusrclk2_in; input [63:0]gtwiz_userdata_tx_in; input [15:0]drpdi_in; input [2:0]loopback_in; input [1:0]txheader_in; input [6:0]txsequence_in; input [8:0]drpaddr_in; input lopt; input lopt_1; output lopt_2; output lopt_3; input lopt_4; input lopt_5; output lopt_6; output lopt_7; wire [0:0]cplllock_out; wire [8:0]drpaddr_in; wire [0:0]drpclk_in; wire [15:0]drpdi_in; wire [15:0]drpdo_out; wire [0:0]drpen_in; wire [0:0]drprdy_out; wire [0:0]drpwe_in; wire \gen_gtwizard_gthe3.cpllpd_ch_int ; wire \gen_gtwizard_gthe3.gtrxreset_int ; wire \gen_gtwizard_gthe3.gttxreset_int ; wire \gen_gtwizard_gthe3.rxprogdivreset_int ; wire \gen_gtwizard_gthe3.rxuserrdy_int ; wire \gen_gtwizard_gthe3.txprogdivreset_int ; wire \gen_gtwizard_gthe3.txuserrdy_int ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_0 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_10 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_100 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_101 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_102 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_103 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_104 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_105 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_106 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_107 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_108 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_109 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_11 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_110 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_111 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_112 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_113 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_114 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_115 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_116 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_117 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_118 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_119 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_12 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_120 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_121 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_122 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_123 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_124 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_125 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_126 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_127 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_128 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_129 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_13 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_130 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_131 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_132 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_133 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_134 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_135 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_136 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_137 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_138 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_139 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_14 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_140 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_141 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_142 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_143 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_144 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_145 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_146 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_147 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_148 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_149 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_15 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_150 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_151 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_152 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_153 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_154 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_155 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_156 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_157 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_158 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_159 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_16 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_160 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_161 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_162 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_163 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_164 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_165 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_166 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_167 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_168 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_169 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_17 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_170 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_171 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_172 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_173 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_174 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_175 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_176 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_177 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_18 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_2 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_20 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_21 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_22 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_226 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_227 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_228 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_229 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_23 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_230 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_231 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_232 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_233 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_234 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_235 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_236 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_237 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_238 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_239 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_24 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_240 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_241 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_242 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_243 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_244 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_245 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_246 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_247 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_248 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_249 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_25 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_250 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_251 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_252 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_253 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_254 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_255 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_256 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_257 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_258 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_259 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_26 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_260 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_261 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_262 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_263 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_264 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_265 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_266 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_267 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_268 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_269 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_27 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_270 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_271 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_272 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_273 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_274 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_275 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_276 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_277 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_278 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_279 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_28 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_280 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_281 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_283 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_285 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_286 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_288 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_289 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_29 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_290 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_291 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_292 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_293 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_294 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_295 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_296 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_297 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_298 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_299 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_30 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_300 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_302 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_303 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_304 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_305 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_306 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_307 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_308 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_309 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_31 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_310 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_311 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_312 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_313 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_314 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_315 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_318 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_319 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_32 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_320 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_321 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_322 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_323 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_324 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_325 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_326 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_327 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_328 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_329 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_33 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_330 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_331 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_332 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_333 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_334 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_335 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_336 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_337 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_338 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_339 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_340 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_341 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_342 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_343 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_344 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_345 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_346 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_347 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_348 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_349 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_35 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_350 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_351 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_352 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_353 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_354 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_355 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_356 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_357 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_358 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_359 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_36 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_360 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_361 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_362 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_363 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_364 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_365 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_37 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_38 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_4 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_40 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_41 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_42 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_43 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_44 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_45 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_46 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_48 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_49 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_50 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_51 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_52 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_53 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_54 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_55 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_56 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_58 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_59 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_60 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_61 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_63 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_64 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_65 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_66 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_68 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_69 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_70 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_71 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_72 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_73 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_74 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_75 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_76 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_77 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_78 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_79 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_8 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_80 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_81 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_82 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_83 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_84 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_85 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_86 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_87 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_88 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_89 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_9 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_90 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_91 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_92 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_93 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_94 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_95 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_96 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_97 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_98 ; wire \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_99 ; wire [0:0]gthrxn_in; wire [0:0]gthrxp_in; wire [0:0]gthtxn_out; wire [0:0]gthtxp_out; wire [0:0]gtpowergood_out; wire [0:0]gtrefclk0_in; wire [31:0]gtwiz_userdata_rx_out; wire [63:0]gtwiz_userdata_tx_in; wire [2:0]loopback_in; wire lopt; wire lopt_1; wire \^lopt_2 ; wire \^lopt_3 ; wire rst_in0; wire [0:0]rxbufstatus_out; wire [0:0]rxcdrlock_out; wire [0:0]rxcdrovrden_in; wire [0:0]rxdatavalid_out; wire [0:0]rxgearboxslip_in; wire [1:0]rxheader_out; wire [0:0]rxheadervalid_out; wire [0:0]rxoutclk_out; wire [0:0]rxpmaresetdone_out; wire [0:0]rxpolarity_in; wire [0:0]rxresetdone_out; wire [0:0]rxusrclk2_in; wire [0:0]rxusrclk_in; wire [0:0]txbufstatus_out; wire [1:0]txheader_in; wire [0:0]txoutclk_out; wire [0:0]txpmaresetdone_out; wire [0:0]txresetdone_out; wire [6:0]txsequence_in; wire [0:0]txusrclk2_in; wire [0:0]txusrclk_in; wire xlnx_opt_; wire xlnx_opt__1; wire xlnx_opt__2; wire xlnx_opt__3; assign \^lopt_2 = lopt_4; assign \^lopt_3 = lopt_5; assign lopt_2 = xlnx_opt_; assign lopt_3 = xlnx_opt__1; assign lopt_6 = xlnx_opt__2; assign lopt_7 = xlnx_opt__3; (* OPT_MODIFIED = "MLO" *) BUFG_GT_SYNC BUFG_GT_SYNC (.CE(lopt), .CESYNC(xlnx_opt_), .CLK(rxoutclk_out), .CLR(lopt_1), .CLRSYNC(xlnx_opt__1)); (* OPT_MODIFIED = "MLO" *) BUFG_GT_SYNC BUFG_GT_SYNC_1 (.CE(\^lopt_2 ), .CESYNC(xlnx_opt__2), .CLK(txoutclk_out), .CLR(\^lopt_3 ), .CLRSYNC(xlnx_opt__3)); (* BOX_TYPE = "PRIMITIVE" *) GTHE3_CHANNEL #( .ACJTAG_DEBUG_MODE(1'b0), .ACJTAG_MODE(1'b0), .ACJTAG_RESET(1'b0), .ADAPT_CFG0(16'hF800), .ADAPT_CFG1(16'h0000), .ALIGN_COMMA_DOUBLE("FALSE"), .ALIGN_COMMA_ENABLE(10'b0000000000), .ALIGN_COMMA_WORD(1), .ALIGN_MCOMMA_DET("FALSE"), .ALIGN_MCOMMA_VALUE(10'b1010000011), .ALIGN_PCOMMA_DET("FALSE"), .ALIGN_PCOMMA_VALUE(10'b0101111100), .A_RXOSCALRESET(1'b0), .A_RXPROGDIVRESET(1'b0), .A_TXPROGDIVRESET(1'b0), .CBCC_DATA_SOURCE_SEL("ENCODED"), .CDR_SWAP_MODE_EN(1'b0), .CHAN_BOND_KEEP_ALIGN("FALSE"), .CHAN_BOND_MAX_SKEW(1), .CHAN_BOND_SEQ_1_1(10'b0000000000), .CHAN_BOND_SEQ_1_2(10'b0000000000), .CHAN_BOND_SEQ_1_3(10'b0000000000), .CHAN_BOND_SEQ_1_4(10'b0000000000), .CHAN_BOND_SEQ_1_ENABLE(4'b1111), .CHAN_BOND_SEQ_2_1(10'b0000000000), .CHAN_BOND_SEQ_2_2(10'b0000000000), .CHAN_BOND_SEQ_2_3(10'b0000000000), .CHAN_BOND_SEQ_2_4(10'b0000000000), .CHAN_BOND_SEQ_2_ENABLE(4'b1111), .CHAN_BOND_SEQ_2_USE("FALSE"), .CHAN_BOND_SEQ_LEN(1), .CLK_CORRECT_USE("FALSE"), .CLK_COR_KEEP_IDLE("FALSE"), .CLK_COR_MAX_LAT(12), .CLK_COR_MIN_LAT(8), .CLK_COR_PRECEDENCE("TRUE"), .CLK_COR_REPEAT_WAIT(0), .CLK_COR_SEQ_1_1(10'b0000000000), .CLK_COR_SEQ_1_2(10'b0000000000), .CLK_COR_SEQ_1_3(10'b0000000000), .CLK_COR_SEQ_1_4(10'b0000000000), .CLK_COR_SEQ_1_ENABLE(4'b1111), .CLK_COR_SEQ_2_1(10'b0000000000), .CLK_COR_SEQ_2_2(10'b0000000000), .CLK_COR_SEQ_2_3(10'b0000000000), .CLK_COR_SEQ_2_4(10'b0000000000), .CLK_COR_SEQ_2_ENABLE(4'b1111), .CLK_COR_SEQ_2_USE("FALSE"), .CLK_COR_SEQ_LEN(1), .CPLL_CFG0(16'h67F8), .CPLL_CFG1(16'hA4AC), .CPLL_CFG2(16'h0007), .CPLL_CFG3(6'h00), .CPLL_FBDIV(5), .CPLL_FBDIV_45(4), .CPLL_INIT_CFG0(16'h02B2), .CPLL_INIT_CFG1(8'h00), .CPLL_LOCK_CFG(16'h01E8), .CPLL_REFCLK_DIV(1), .DDI_CTRL(2'b00), .DDI_REALIGN_WAIT(15), .DEC_MCOMMA_DETECT("FALSE"), .DEC_PCOMMA_DETECT("FALSE"), .DEC_VALID_COMMA_ONLY("FALSE"), .DFE_D_X_REL_POS(1'b0), .DFE_VCM_COMP_EN(1'b0), .DMONITOR_CFG0(10'h000), .DMONITOR_CFG1(8'h00), .ES_CLK_PHASE_SEL(1'b0), .ES_CONTROL(6'b000000), .ES_ERRDET_EN("FALSE"), .ES_EYE_SCAN_EN("FALSE"), .ES_HORZ_OFFSET(12'h000), .ES_PMA_CFG(10'b0000000000), .ES_PRESCALE(5'b00000), .ES_QUALIFIER0(16'h0000), .ES_QUALIFIER1(16'h0000), .ES_QUALIFIER2(16'h0000), .ES_QUALIFIER3(16'h0000), .ES_QUALIFIER4(16'h0000), .ES_QUAL_MASK0(16'h0000), .ES_QUAL_MASK1(16'h0000), .ES_QUAL_MASK2(16'h0000), .ES_QUAL_MASK3(16'h0000), .ES_QUAL_MASK4(16'h0000), .ES_SDATA_MASK0(16'h0000), .ES_SDATA_MASK1(16'h0000), .ES_SDATA_MASK2(16'h0000), .ES_SDATA_MASK3(16'h0000), .ES_SDATA_MASK4(16'h0000), .EVODD_PHI_CFG(11'b00000000000), .EYE_SCAN_SWAP_EN(1'b0), .FTS_DESKEW_SEQ_ENABLE(4'b1111), .FTS_LANE_DESKEW_CFG(4'b1111), .FTS_LANE_DESKEW_EN("FALSE"), .GEARBOX_MODE(5'b00001), .GM_BIAS_SELECT(1'b0), .LOCAL_MASTER(1'b1), .OOBDIVCTL(2'b00), .OOB_PWRUP(1'b0), .PCI3_AUTO_REALIGN("OVR_1K_BLK"), .PCI3_PIPE_RX_ELECIDLE(1'b0), .PCI3_RX_ASYNC_EBUF_BYPASS(2'b00), .PCI3_RX_ELECIDLE_EI2_ENABLE(1'b0), .PCI3_RX_ELECIDLE_H2L_COUNT(6'b000000), .PCI3_RX_ELECIDLE_H2L_DISABLE(3'b000), .PCI3_RX_ELECIDLE_HI_COUNT(6'b000000), .PCI3_RX_ELECIDLE_LP4_DISABLE(1'b0), .PCI3_RX_FIFO_DISABLE(1'b0), .PCIE_BUFG_DIV_CTRL(16'h1000), .PCIE_RXPCS_CFG_GEN3(16'h02A4), .PCIE_RXPMA_CFG(16'h000A), .PCIE_TXPCS_CFG_GEN3(16'h24A4), .PCIE_TXPMA_CFG(16'h000A), .PCS_PCIE_EN("FALSE"), .PCS_RSVD0(16'b0000000000000000), .PCS_RSVD1(3'b000), .PD_TRANS_TIME_FROM_P2(12'h03C), .PD_TRANS_TIME_NONE_P2(8'h19), .PD_TRANS_TIME_TO_P2(8'h64), .PLL_SEL_MODE_GEN12(2'h0), .PLL_SEL_MODE_GEN3(2'h3), .PMA_RSV1(16'hF000), .PROCESS_PAR(3'b010), .RATE_SW_USE_DRP(1'b1), .RESET_POWERSAVE_DISABLE(1'b0), .RXBUFRESET_TIME(5'b00011), .RXBUF_ADDR_MODE("FAST"), .RXBUF_EIDLE_HI_CNT(4'b1000), .RXBUF_EIDLE_LO_CNT(4'b0000), .RXBUF_EN("TRUE"), .RXBUF_RESET_ON_CB_CHANGE("TRUE"), .RXBUF_RESET_ON_COMMAALIGN("FALSE"), .RXBUF_RESET_ON_EIDLE("FALSE"), .RXBUF_RESET_ON_RATE_CHANGE("TRUE"), .RXBUF_THRESH_OVFLW(57), .RXBUF_THRESH_OVRD("TRUE"), .RXBUF_THRESH_UNDFLW(3), .RXCDRFREQRESET_TIME(5'b00001), .RXCDRPHRESET_TIME(5'b00001), .RXCDR_CFG0(16'h0000), .RXCDR_CFG0_GEN3(16'h0000), .RXCDR_CFG1(16'h0000), .RXCDR_CFG1_GEN3(16'h0000), .RXCDR_CFG2(16'h07E6), .RXCDR_CFG2_GEN3(16'h07E6), .RXCDR_CFG3(16'h0000), .RXCDR_CFG3_GEN3(16'h0000), .RXCDR_CFG4(16'h0000), .RXCDR_CFG4_GEN3(16'h0000), .RXCDR_CFG5(16'h0000), .RXCDR_CFG5_GEN3(16'h0000), .RXCDR_FR_RESET_ON_EIDLE(1'b0), .RXCDR_HOLD_DURING_EIDLE(1'b0), .RXCDR_LOCK_CFG0(16'h4480), .RXCDR_LOCK_CFG1(16'h5FFF), .RXCDR_LOCK_CFG2(16'h77C3), .RXCDR_PH_RESET_ON_EIDLE(1'b0), .RXCFOK_CFG0(16'h4000), .RXCFOK_CFG1(16'h0065), .RXCFOK_CFG2(16'h002E), .RXDFELPMRESET_TIME(7'b0001111), .RXDFELPM_KL_CFG0(16'h0000), .RXDFELPM_KL_CFG1(16'h0002), .RXDFELPM_KL_CFG2(16'h0000), .RXDFE_CFG0(16'h0A00), .RXDFE_CFG1(16'h0000), .RXDFE_GC_CFG0(16'h0000), .RXDFE_GC_CFG1(16'h7870), .RXDFE_GC_CFG2(16'h0000), .RXDFE_H2_CFG0(16'h0000), .RXDFE_H2_CFG1(16'h0000), .RXDFE_H3_CFG0(16'h4000), .RXDFE_H3_CFG1(16'h0000), .RXDFE_H4_CFG0(16'h2000), .RXDFE_H4_CFG1(16'h0003), .RXDFE_H5_CFG0(16'h2000), .RXDFE_H5_CFG1(16'h0003), .RXDFE_H6_CFG0(16'h2000), .RXDFE_H6_CFG1(16'h0000), .RXDFE_H7_CFG0(16'h2000), .RXDFE_H7_CFG1(16'h0000), .RXDFE_H8_CFG0(16'h2000), .RXDFE_H8_CFG1(16'h0000), .RXDFE_H9_CFG0(16'h2000), .RXDFE_H9_CFG1(16'h0000), .RXDFE_HA_CFG0(16'h2000), .RXDFE_HA_CFG1(16'h0000), .RXDFE_HB_CFG0(16'h2000), .RXDFE_HB_CFG1(16'h0000), .RXDFE_HC_CFG0(16'h0000), .RXDFE_HC_CFG1(16'h0000), .RXDFE_HD_CFG0(16'h0000), .RXDFE_HD_CFG1(16'h0000), .RXDFE_HE_CFG0(16'h0000), .RXDFE_HE_CFG1(16'h0000), .RXDFE_HF_CFG0(16'h0000), .RXDFE_HF_CFG1(16'h0000), .RXDFE_OS_CFG0(16'h8000), .RXDFE_OS_CFG1(16'h0000), .RXDFE_UT_CFG0(16'h8000), .RXDFE_UT_CFG1(16'h0003), .RXDFE_VP_CFG0(16'hAA00), .RXDFE_VP_CFG1(16'h0033), .RXDLY_CFG(16'h001F), .RXDLY_LCFG(16'h0030), .RXELECIDLE_CFG("Sigcfg_4"), .RXGBOX_FIFO_INIT_RD_ADDR(4), .RXGEARBOX_EN("TRUE"), .RXISCANRESET_TIME(5'b00001), .RXLPM_CFG(16'h0000), .RXLPM_GC_CFG(16'h1000), .RXLPM_KH_CFG0(16'h0000), .RXLPM_KH_CFG1(16'h0002), .RXLPM_OS_CFG0(16'h8000), .RXLPM_OS_CFG1(16'h0002), .RXOOB_CFG(9'b000000110), .RXOOB_CLK_CFG("PMA"), .RXOSCALRESET_TIME(5'b00011), .RXOUT_DIV(1), .RXPCSRESET_TIME(5'b00011), .RXPHBEACON_CFG(16'h0000), .RXPHDLY_CFG(16'h2020), .RXPHSAMP_CFG(16'h2100), .RXPHSLIP_CFG(16'h6622), .RXPH_MONITOR_SEL(5'b00000), .RXPI_CFG0(2'b00), .RXPI_CFG1(2'b00), .RXPI_CFG2(2'b00), .RXPI_CFG3(2'b00), .RXPI_CFG4(1'b1), .RXPI_CFG5(1'b1), .RXPI_CFG6(3'b011), .RXPI_LPM(1'b0), .RXPI_VREFSEL(1'b0), .RXPMACLK_SEL("DATA"), .RXPMARESET_TIME(5'b00011), .RXPRBS_ERR_LOOPBACK(1'b0), .RXPRBS_LINKACQ_CNT(15), .RXSLIDE_AUTO_WAIT(7), .RXSLIDE_MODE("OFF"), .RXSYNC_MULTILANE(1'b0), .RXSYNC_OVRD(1'b0), .RXSYNC_SKIP_DA(1'b0), .RX_AFE_CM_EN(1'b0), .RX_BIAS_CFG0(16'h0AB4), .RX_BUFFER_CFG(6'b000000), .RX_CAPFF_SARC_ENB(1'b0), .RX_CLK25_DIV(5), .RX_CLKMUX_EN(1'b1), .RX_CLK_SLIP_OVRD(5'b00000), .RX_CM_BUF_CFG(4'b1010), .RX_CM_BUF_PD(1'b0), .RX_CM_SEL(2'b11), .RX_CM_TRIM(4'b1010), .RX_CTLE3_LPF(8'b00000001), .RX_DATA_WIDTH(32), .RX_DDI_SEL(6'b000000), .RX_DEFER_RESET_BUF_EN("TRUE"), .RX_DFELPM_CFG0(4'b0110), .RX_DFELPM_CFG1(1'b1), .RX_DFELPM_KLKH_AGC_STUP_EN(1'b1), .RX_DFE_AGC_CFG0(2'b10), .RX_DFE_AGC_CFG1(3'b100), .RX_DFE_KL_LPM_KH_CFG0(2'b01), .RX_DFE_KL_LPM_KH_CFG1(3'b100), .RX_DFE_KL_LPM_KL_CFG0(2'b01), .RX_DFE_KL_LPM_KL_CFG1(3'b100), .RX_DFE_LPM_HOLD_DURING_EIDLE(1'b0), .RX_DISPERR_SEQ_MATCH("TRUE"), .RX_DIVRESET_TIME(5'b00001), .RX_EN_HI_LR(1'b0), .RX_EYESCAN_VS_CODE(7'b0000000), .RX_EYESCAN_VS_NEG_DIR(1'b0), .RX_EYESCAN_VS_RANGE(2'b00), .RX_EYESCAN_VS_UT_SIGN(1'b0), .RX_FABINT_USRCLK_FLOP(1'b0), .RX_INT_DATAWIDTH(1), .RX_PMA_POWER_SAVE(1'b0), .RX_PROGDIV_CFG(0.000000), .RX_SAMPLE_PERIOD(3'b111), .RX_SIG_VALID_DLY(11), .RX_SUM_DFETAPREP_EN(1'b0), .RX_SUM_IREF_TUNE(4'b0000), .RX_SUM_RES_CTRL(2'b00), .RX_SUM_VCMTUNE(4'b0000), .RX_SUM_VCM_OVWR(1'b0), .RX_SUM_VREF_TUNE(3'b000), .RX_TUNE_AFE_OS(2'b10), .RX_WIDEMODE_CDR(1'b0), .RX_XCLK_SEL("RXDES"), .SAS_MAX_COM(64), .SAS_MIN_COM(36), .SATA_BURST_SEQ_LEN(4'b1110), .SATA_BURST_VAL(3'b100), .SATA_CPLL_CFG("VCO_3000MHZ"), .SATA_EIDLE_VAL(3'b100), .SATA_MAX_BURST(8), .SATA_MAX_INIT(21), .SATA_MAX_WAKE(7), .SATA_MIN_BURST(4), .SATA_MIN_INIT(12), .SATA_MIN_WAKE(4), .SHOW_REALIGN_COMMA("TRUE"), .SIM_MODE("FAST"), .SIM_RECEIVER_DETECT_PASS("TRUE"), .SIM_RESET_SPEEDUP("TRUE"), .SIM_TX_EIDLE_DRIVE_LEVEL(1'b0), .SIM_VERSION(2), .TAPDLY_SET_TX(2'h0), .TEMPERATUR_PAR(4'b0010), .TERM_RCAL_CFG(15'b100001000010000), .TERM_RCAL_OVRD(3'b000), .TRANS_TIME_RATE(8'h0E), .TST_RSV0(8'h00), .TST_RSV1(8'h00), .TXBUF_EN("TRUE"), .TXBUF_RESET_ON_RATE_CHANGE("TRUE"), .TXDLY_CFG(16'h0009), .TXDLY_LCFG(16'h0050), .TXDRVBIAS_N(4'b1010), .TXDRVBIAS_P(4'b1010), .TXFIFO_ADDR_CFG("LOW"), .TXGBOX_FIFO_INIT_RD_ADDR(4), .TXGEARBOX_EN("TRUE"), .TXOUT_DIV(1), .TXPCSRESET_TIME(5'b00011), .TXPHDLY_CFG0(16'h2020), .TXPHDLY_CFG1(16'h0075), .TXPH_CFG(16'h0980), .TXPH_MONITOR_SEL(5'b00000), .TXPI_CFG0(2'b00), .TXPI_CFG1(2'b00), .TXPI_CFG2(2'b00), .TXPI_CFG3(1'b1), .TXPI_CFG4(1'b1), .TXPI_CFG5(3'b011), .TXPI_GRAY_SEL(1'b0), .TXPI_INVSTROBE_SEL(1'b1), .TXPI_LPM(1'b0), .TXPI_PPMCLK_SEL("TXUSRCLK2"), .TXPI_PPM_CFG(8'b00000000), .TXPI_SYNFREQ_PPM(3'b001), .TXPI_VREFSEL(1'b0), .TXPMARESET_TIME(5'b00011), .TXSYNC_MULTILANE(1'b0), .TXSYNC_OVRD(1'b0), .TXSYNC_SKIP_DA(1'b0), .TX_CLK25_DIV(5), .TX_CLKMUX_EN(1'b1), .TX_DATA_WIDTH(64), .TX_DCD_CFG(6'b000010), .TX_DCD_EN(1'b0), .TX_DEEMPH0(6'b000000), .TX_DEEMPH1(6'b000000), .TX_DIVRESET_TIME(5'b00001), .TX_DRIVE_MODE("DIRECT"), .TX_EIDLE_ASSERT_DELAY(3'b100), .TX_EIDLE_DEASSERT_DELAY(3'b011), .TX_EML_PHI_TUNE(1'b0), .TX_FABINT_USRCLK_FLOP(1'b0), .TX_IDLE_DATA_ZERO(1'b0), .TX_INT_DATAWIDTH(1), .TX_LOOPBACK_DRIVE_HIZ("FALSE"), .TX_MAINCURSOR_SEL(1'b0), .TX_MARGIN_FULL_0(7'b1001111), .TX_MARGIN_FULL_1(7'b1001110), .TX_MARGIN_FULL_2(7'b1001100), .TX_MARGIN_FULL_3(7'b1001010), .TX_MARGIN_FULL_4(7'b1001000), .TX_MARGIN_LOW_0(7'b1000110), .TX_MARGIN_LOW_1(7'b1000101), .TX_MARGIN_LOW_2(7'b1000011), .TX_MARGIN_LOW_3(7'b1000010), .TX_MARGIN_LOW_4(7'b1000000), .TX_MODE_SEL(3'b000), .TX_PMADATA_OPT(1'b0), .TX_PMA_POWER_SAVE(1'b0), .TX_PROGCLK_SEL("PREPI"), .TX_PROGDIV_CFG(0.000000), .TX_QPI_STATUS_EN(1'b0), .TX_RXDETECT_CFG(14'h0032), .TX_RXDETECT_REF(3'b100), .TX_SAMPLE_PERIOD(3'b111), .TX_SARC_LPBK_ENB(1'b0), .TX_XCLK_SEL("TXOUT"), .USE_PCS_CLK_PHASE_SEL(1'b0), .WB_MODE(2'b00)) \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST (.BUFGTCE({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_289 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_290 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_291 }), .BUFGTCEMASK({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_292 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_293 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_294 }), .BUFGTDIV({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_357 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_358 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_359 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_360 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_361 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_362 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_363 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_364 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_365 }), .BUFGTRESET({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_295 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_296 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_297 }), .BUFGTRSTMASK({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_298 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_299 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_300 }), .CFGRESET(1'b0), .CLKRSVD0(1'b0), .CLKRSVD1(1'b0), .CPLLFBCLKLOST(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_0 ), .CPLLLOCK(cplllock_out), .CPLLLOCKDETCLK(1'b0), .CPLLLOCKEN(1'b1), .CPLLPD(\gen_gtwizard_gthe3.cpllpd_ch_int ), .CPLLREFCLKLOST(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_2 ), .CPLLREFCLKSEL({1'b0,1'b0,1'b1}), .CPLLRESET(1'b0), .DMONFIFORESET(1'b0), .DMONITORCLK(1'b0), .DMONITOROUT({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_258 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_259 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_260 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_261 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_262 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_263 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_264 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_265 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_266 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_267 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_268 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_269 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_270 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_271 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_272 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_273 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_274 }), .DRPADDR(drpaddr_in), .DRPCLK(drpclk_in), .DRPDI(drpdi_in), .DRPDO(drpdo_out), .DRPEN(drpen_in), .DRPRDY(drprdy_out), .DRPWE(drpwe_in), .EVODDPHICALDONE(1'b0), .EVODDPHICALSTART(1'b0), .EVODDPHIDRDEN(1'b0), .EVODDPHIDWREN(1'b0), .EVODDPHIXRDEN(1'b0), .EVODDPHIXWREN(1'b0), .EYESCANDATAERROR(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_4 ), .EYESCANMODE(1'b0), .EYESCANRESET(1'b0), .EYESCANTRIGGER(1'b0), .GTGREFCLK(1'b0), .GTHRXN(gthrxn_in), .GTHRXP(gthrxp_in), .GTHTXN(gthtxn_out), .GTHTXP(gthtxp_out), .GTNORTHREFCLK0(1'b0), .GTNORTHREFCLK1(1'b0), .GTPOWERGOOD(gtpowergood_out), .GTREFCLK0(gtrefclk0_in), .GTREFCLK1(1'b0), .GTREFCLKMONITOR(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_8 ), .GTRESETSEL(1'b0), .GTRSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .GTRXRESET(\gen_gtwizard_gthe3.gtrxreset_int ), .GTSOUTHREFCLK0(1'b0), .GTSOUTHREFCLK1(1'b0), .GTTXRESET(\gen_gtwizard_gthe3.gttxreset_int ), .LOOPBACK(loopback_in), .LPBKRXTXSEREN(1'b0), .LPBKTXRXSEREN(1'b0), .PCIEEQRXEQADAPTDONE(1'b0), .PCIERATEGEN3(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_9 ), .PCIERATEIDLE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_10 ), .PCIERATEQPLLPD({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_275 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_276 }), .PCIERATEQPLLRESET({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_277 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_278 }), .PCIERSTIDLE(1'b0), .PCIERSTTXSYNCSTART(1'b0), .PCIESYNCTXSYNCDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_11 ), .PCIEUSERGEN3RDY(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_12 ), .PCIEUSERPHYSTATUSRST(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_13 ), .PCIEUSERRATEDONE(1'b0), .PCIEUSERRATESTART(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_14 ), .PCSRSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .PCSRSVDIN2({1'b0,1'b0,1'b0,1'b0,1'b0}), .PCSRSVDOUT({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_70 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_71 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_72 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_73 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_74 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_75 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_76 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_77 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_78 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_79 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_80 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_81 }), .PHYSTATUS(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_15 ), .PINRSRVDAS({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_325 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_326 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_327 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_328 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_329 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_330 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_331 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_332 }), .PMARSVDIN({1'b0,1'b0,1'b0,1'b0,1'b0}), .QPLL0CLK(1'b0), .QPLL0REFCLK(1'b0), .QPLL1CLK(1'b0), .QPLL1REFCLK(1'b0), .RESETEXCEPTION(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_16 ), .RESETOVRD(1'b0), .RSTCLKENTX(1'b0), .RX8B10BEN(1'b0), .RXBUFRESET(1'b0), .RXBUFSTATUS({rxbufstatus_out,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_302 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_303 }), .RXBYTEISALIGNED(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_17 ), .RXBYTEREALIGN(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_18 ), .RXCDRFREQRESET(1'b0), .RXCDRHOLD(1'b0), .RXCDRLOCK(rxcdrlock_out), .RXCDROVRDEN(rxcdrovrden_in), .RXCDRPHDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_20 ), .RXCDRRESET(1'b0), .RXCDRRESETRSV(1'b0), .RXCHANBONDSEQ(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_21 ), .RXCHANISALIGNED(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_22 ), .RXCHANREALIGN(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_23 ), .RXCHBONDEN(1'b0), .RXCHBONDI({1'b0,1'b0,1'b0,1'b0,1'b0}), .RXCHBONDLEVEL({1'b0,1'b0,1'b0}), .RXCHBONDMASTER(1'b0), .RXCHBONDO({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_307 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_308 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_309 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_310 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_311 }), .RXCHBONDSLAVE(1'b0), .RXCLKCORCNT({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_279 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_280 }), .RXCOMINITDET(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_24 ), .RXCOMMADET(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_25 ), .RXCOMMADETEN(1'b0), .RXCOMSASDET(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_26 ), .RXCOMWAKEDET(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_27 ), .RXCTRL0({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_226 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_227 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_228 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_229 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_230 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_231 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_232 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_233 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_234 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_235 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_236 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_237 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_238 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_239 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_240 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_241 }), .RXCTRL1({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_242 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_243 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_244 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_245 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_246 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_247 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_248 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_249 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_250 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_251 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_252 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_253 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_254 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_255 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_256 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_257 }), .RXCTRL2({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_333 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_334 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_335 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_336 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_337 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_338 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_339 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_340 }), .RXCTRL3({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_341 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_342 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_343 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_344 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_345 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_346 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_347 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_348 }), .RXDATA({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_82 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_83 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_84 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_85 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_86 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_87 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_88 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_89 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_90 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_91 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_92 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_93 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_94 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_95 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_96 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_97 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_98 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_99 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_100 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_101 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_102 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_103 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_104 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_105 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_106 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_107 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_108 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_109 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_110 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_111 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_112 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_113 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_114 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_115 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_116 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_117 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_118 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_119 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_120 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_121 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_122 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_123 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_124 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_125 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_126 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_127 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_128 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_129 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_130 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_131 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_132 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_133 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_134 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_135 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_136 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_137 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_138 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_139 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_140 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_141 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_142 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_143 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_144 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_145 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_146 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_147 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_148 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_149 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_150 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_151 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_152 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_153 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_154 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_155 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_156 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_157 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_158 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_159 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_160 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_161 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_162 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_163 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_164 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_165 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_166 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_167 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_168 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_169 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_170 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_171 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_172 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_173 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_174 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_175 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_176 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_177 ,gtwiz_userdata_rx_out}), .RXDATAEXTENDRSVD({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_349 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_350 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_351 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_352 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_353 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_354 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_355 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_356 }), .RXDATAVALID({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_281 ,rxdatavalid_out}), .RXDFEAGCCTRL({1'b0,1'b1}), .RXDFEAGCHOLD(1'b0), .RXDFEAGCOVRDEN(1'b0), .RXDFELFHOLD(1'b0), .RXDFELFOVRDEN(1'b0), .RXDFELPMRESET(1'b0), .RXDFETAP10HOLD(1'b0), .RXDFETAP10OVRDEN(1'b0), .RXDFETAP11HOLD(1'b0), .RXDFETAP11OVRDEN(1'b0), .RXDFETAP12HOLD(1'b0), .RXDFETAP12OVRDEN(1'b0), .RXDFETAP13HOLD(1'b0), .RXDFETAP13OVRDEN(1'b0), .RXDFETAP14HOLD(1'b0), .RXDFETAP14OVRDEN(1'b0), .RXDFETAP15HOLD(1'b0), .RXDFETAP15OVRDEN(1'b0), .RXDFETAP2HOLD(1'b0), .RXDFETAP2OVRDEN(1'b0), .RXDFETAP3HOLD(1'b0), .RXDFETAP3OVRDEN(1'b0), .RXDFETAP4HOLD(1'b0), .RXDFETAP4OVRDEN(1'b0), .RXDFETAP5HOLD(1'b0), .RXDFETAP5OVRDEN(1'b0), .RXDFETAP6HOLD(1'b0), .RXDFETAP6OVRDEN(1'b0), .RXDFETAP7HOLD(1'b0), .RXDFETAP7OVRDEN(1'b0), .RXDFETAP8HOLD(1'b0), .RXDFETAP8OVRDEN(1'b0), .RXDFETAP9HOLD(1'b0), .RXDFETAP9OVRDEN(1'b0), .RXDFEUTHOLD(1'b0), .RXDFEUTOVRDEN(1'b0), .RXDFEVPHOLD(1'b0), .RXDFEVPOVRDEN(1'b0), .RXDFEVSEN(1'b0), .RXDFEXYDEN(1'b1), .RXDLYBYPASS(1'b1), .RXDLYEN(1'b0), .RXDLYOVRDEN(1'b0), .RXDLYSRESET(1'b0), .RXDLYSRESETDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_28 ), .RXELECIDLE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_29 ), .RXELECIDLEMODE({1'b1,1'b1}), .RXGEARBOXSLIP(rxgearboxslip_in), .RXHEADER({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_312 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_313 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_314 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_315 ,rxheader_out}), .RXHEADERVALID({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_283 ,rxheadervalid_out}), .RXLATCLK(1'b0), .RXLPMEN(1'b0), .RXLPMGCHOLD(1'b0), .RXLPMGCOVRDEN(1'b0), .RXLPMHFHOLD(1'b0), .RXLPMHFOVRDEN(1'b0), .RXLPMLFHOLD(1'b0), .RXLPMLFKLOVRDEN(1'b0), .RXLPMOSHOLD(1'b0), .RXLPMOSOVRDEN(1'b0), .RXMCOMMAALIGNEN(1'b0), .RXMONITOROUT({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_318 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_319 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_320 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_321 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_322 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_323 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_324 }), .RXMONITORSEL({1'b0,1'b0}), .RXOOBRESET(1'b0), .RXOSCALRESET(1'b0), .RXOSHOLD(1'b0), .RXOSINTCFG({1'b1,1'b1,1'b0,1'b1}), .RXOSINTDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_30 ), .RXOSINTEN(1'b1), .RXOSINTHOLD(1'b0), .RXOSINTOVRDEN(1'b0), .RXOSINTSTARTED(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_31 ), .RXOSINTSTROBE(1'b0), .RXOSINTSTROBEDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_32 ), .RXOSINTSTROBESTARTED(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_33 ), .RXOSINTTESTOVRDEN(1'b0), .RXOSOVRDEN(1'b0), .RXOUTCLK(rxoutclk_out), .RXOUTCLKFABRIC(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_35 ), .RXOUTCLKPCS(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_36 ), .RXOUTCLKSEL({1'b0,1'b1,1'b0}), .RXPCOMMAALIGNEN(1'b0), .RXPCSRESET(1'b0), .RXPD({1'b0,1'b0}), .RXPHALIGN(1'b0), .RXPHALIGNDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_37 ), .RXPHALIGNEN(1'b0), .RXPHALIGNERR(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_38 ), .RXPHDLYPD(1'b1), .RXPHDLYRESET(1'b0), .RXPHOVRDEN(1'b0), .RXPLLCLKSEL({1'b0,1'b0}), .RXPMARESET(1'b0), .RXPMARESETDONE(rxpmaresetdone_out), .RXPOLARITY(rxpolarity_in), .RXPRBSCNTRESET(1'b0), .RXPRBSERR(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_40 ), .RXPRBSLOCKED(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_41 ), .RXPRBSSEL({1'b0,1'b0,1'b0,1'b0}), .RXPRGDIVRESETDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_42 ), .RXPROGDIVRESET(\gen_gtwizard_gthe3.rxprogdivreset_int ), .RXQPIEN(1'b0), .RXQPISENN(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_43 ), .RXQPISENP(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_44 ), .RXRATE({1'b0,1'b0,1'b0}), .RXRATEDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_45 ), .RXRATEMODE(1'b0), .RXRECCLKOUT(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_46 ), .RXRESETDONE(rxresetdone_out), .RXSLIDE(1'b0), .RXSLIDERDY(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_48 ), .RXSLIPDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_49 ), .RXSLIPOUTCLK(1'b0), .RXSLIPOUTCLKRDY(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_50 ), .RXSLIPPMA(1'b0), .RXSLIPPMARDY(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_51 ), .RXSTARTOFSEQ({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_285 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_286 }), .RXSTATUS({\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_304 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_305 ,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_306 }), .RXSYNCALLIN(1'b0), .RXSYNCDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_52 ), .RXSYNCIN(1'b0), .RXSYNCMODE(1'b0), .RXSYNCOUT(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_53 ), .RXSYSCLKSEL({1'b0,1'b0}), .RXUSERRDY(\gen_gtwizard_gthe3.rxuserrdy_int ), .RXUSRCLK(rxusrclk_in), .RXUSRCLK2(rxusrclk2_in), .RXVALID(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_54 ), .SIGVALIDCLK(1'b0), .TSTIN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .TX8B10BBYPASS({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .TX8B10BEN(1'b0), .TXBUFDIFFCTRL({1'b0,1'b0,1'b0}), .TXBUFSTATUS({txbufstatus_out,\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_288 }), .TXCOMFINISH(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_55 ), .TXCOMINIT(1'b0), .TXCOMSAS(1'b0), .TXCOMWAKE(1'b0), .TXCTRL0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .TXCTRL1({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .TXCTRL2({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .TXDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,gtwiz_userdata_tx_in}), .TXDATAEXTENDRSVD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .TXDEEMPH(1'b0), .TXDETECTRX(1'b0), .TXDIFFCTRL({1'b1,1'b0,1'b0,1'b0}), .TXDIFFPD(1'b0), .TXDLYBYPASS(1'b1), .TXDLYEN(1'b0), .TXDLYHOLD(1'b0), .TXDLYOVRDEN(1'b0), .TXDLYSRESET(1'b0), .TXDLYSRESETDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_56 ), .TXDLYUPDOWN(1'b0), .TXELECIDLE(1'b0), .TXHEADER({1'b0,1'b0,1'b0,1'b0,txheader_in}), .TXINHIBIT(1'b0), .TXLATCLK(1'b0), .TXMAINCURSOR({1'b1,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .TXMARGIN({1'b0,1'b0,1'b0}), .TXOUTCLK(txoutclk_out), .TXOUTCLKFABRIC(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_58 ), .TXOUTCLKPCS(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_59 ), .TXOUTCLKSEL({1'b0,1'b1,1'b0}), .TXPCSRESET(1'b0), .TXPD({1'b0,1'b0}), .TXPDELECIDLEMODE(1'b0), .TXPHALIGN(1'b0), .TXPHALIGNDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_60 ), .TXPHALIGNEN(1'b0), .TXPHDLYPD(1'b1), .TXPHDLYRESET(1'b0), .TXPHDLYTSTCLK(1'b0), .TXPHINIT(1'b0), .TXPHINITDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_61 ), .TXPHOVRDEN(1'b0), .TXPIPPMEN(1'b0), .TXPIPPMOVRDEN(1'b0), .TXPIPPMPD(1'b0), .TXPIPPMSEL(1'b0), .TXPIPPMSTEPSIZE({1'b0,1'b0,1'b0,1'b0,1'b0}), .TXPISOPD(1'b0), .TXPLLCLKSEL({1'b0,1'b0}), .TXPMARESET(1'b0), .TXPMARESETDONE(txpmaresetdone_out), .TXPOLARITY(1'b0), .TXPOSTCURSOR({1'b0,1'b0,1'b0,1'b0,1'b0}), .TXPOSTCURSORINV(1'b0), .TXPRBSFORCEERR(1'b0), .TXPRBSSEL({1'b0,1'b0,1'b0,1'b0}), .TXPRECURSOR({1'b0,1'b0,1'b0,1'b0,1'b0}), .TXPRECURSORINV(1'b0), .TXPRGDIVRESETDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_63 ), .TXPROGDIVRESET(\gen_gtwizard_gthe3.txprogdivreset_int ), .TXQPIBIASEN(1'b0), .TXQPISENN(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_64 ), .TXQPISENP(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_65 ), .TXQPISTRONGPDOWN(1'b0), .TXQPIWEAKPUP(1'b0), .TXRATE({1'b0,1'b0,1'b0}), .TXRATEDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_66 ), .TXRATEMODE(1'b0), .TXRESETDONE(txresetdone_out), .TXSEQUENCE(txsequence_in), .TXSWING(1'b0), .TXSYNCALLIN(1'b0), .TXSYNCDONE(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_68 ), .TXSYNCIN(1'b0), .TXSYNCMODE(1'b0), .TXSYNCOUT(\gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_n_69 ), .TXSYSCLKSEL({1'b0,1'b0}), .TXUSERRDY(\gen_gtwizard_gthe3.txuserrdy_int ), .TXUSRCLK(txusrclk_in), .TXUSRCLK2(txusrclk2_in)); LUT1 #( .INIT(2'h1)) rst_in_meta_i_1__2 (.I0(cplllock_out), .O(rst_in0)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_gtwiz_reset" *) module aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_gtwiz_reset (\gen_gtwizard_gthe3.txprogdivreset_int , gtwiz_reset_tx_done_out, gtwiz_reset_rx_done_out, \gen_gtwizard_gthe3.gttxreset_int , \gen_gtwizard_gthe3.txuserrdy_int , \gen_gtwizard_gthe3.rxprogdivreset_int , \gen_gtwizard_gthe3.gtrxreset_int , \gen_gtwizard_gthe3.rxuserrdy_int , \gen_gtwizard_gthe3.cpllpd_ch_int , gtpowergood_out, gtwiz_userclk_tx_active_in, cplllock_out, gtwiz_userclk_rx_active_in, rxcdrlock_out, drpclk_in, gtwiz_reset_rx_pll_and_datapath_in, rst_in0, txusrclk2_in, rxusrclk2_in, \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync , gtwiz_reset_rx_datapath_in, \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ); output \gen_gtwizard_gthe3.txprogdivreset_int ; output [0:0]gtwiz_reset_tx_done_out; output [0:0]gtwiz_reset_rx_done_out; output \gen_gtwizard_gthe3.gttxreset_int ; output \gen_gtwizard_gthe3.txuserrdy_int ; output \gen_gtwizard_gthe3.rxprogdivreset_int ; output \gen_gtwizard_gthe3.gtrxreset_int ; output \gen_gtwizard_gthe3.rxuserrdy_int ; output \gen_gtwizard_gthe3.cpllpd_ch_int ; input [0:0]gtpowergood_out; input [0:0]gtwiz_userclk_tx_active_in; input [0:0]cplllock_out; input [0:0]gtwiz_userclk_rx_active_in; input [0:0]rxcdrlock_out; input [0:0]drpclk_in; input [0:0]gtwiz_reset_rx_pll_and_datapath_in; input rst_in0; input [0:0]txusrclk2_in; input [0:0]rxusrclk2_in; input \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ; input [0:0]gtwiz_reset_rx_datapath_in; input \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ; wire \FSM_sequential_sm_reset_all[2]_i_3_n_0 ; wire \FSM_sequential_sm_reset_all[2]_i_4_n_0 ; wire \FSM_sequential_sm_reset_rx[1]_i_2_n_0 ; wire \FSM_sequential_sm_reset_rx[2]_i_6_n_0 ; wire \FSM_sequential_sm_reset_tx[2]_i_3_n_0 ; wire bit_synchronizer_gtpowergood_inst_n_0; wire bit_synchronizer_gtwiz_reset_rx_pll_and_datapath_dly_inst_n_2; wire bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst_n_0; wire bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_0; wire bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_1; wire bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_2; wire bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_1; wire bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_2; wire bit_synchronizer_plllock_rx_inst_n_1; wire bit_synchronizer_plllock_rx_inst_n_2; wire bit_synchronizer_plllock_tx_inst_n_1; wire bit_synchronizer_plllock_tx_inst_n_2; wire bit_synchronizer_rxcdrlock_inst_n_0; wire bit_synchronizer_rxcdrlock_inst_n_1; wire bit_synchronizer_rxcdrlock_inst_n_2; wire [0:0]cplllock_out; wire [0:0]drpclk_in; wire \gen_gtwizard_gthe3.cpllpd_ch_int ; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int ; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int ; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ; wire \gen_gtwizard_gthe3.gtrxreset_int ; wire \gen_gtwizard_gthe3.gttxreset_int ; wire \gen_gtwizard_gthe3.rxprogdivreset_int ; wire \gen_gtwizard_gthe3.rxuserrdy_int ; wire \gen_gtwizard_gthe3.txprogdivreset_int ; wire \gen_gtwizard_gthe3.txuserrdy_int ; wire [0:0]gtpowergood_out; wire gttxreset_out_i_3_n_0; wire gtwiz_reset_all_sync; wire gtwiz_reset_rx_any_sync; wire gtwiz_reset_rx_datapath_dly; wire [0:0]gtwiz_reset_rx_datapath_in; wire gtwiz_reset_rx_datapath_int_i_1_n_0; wire gtwiz_reset_rx_datapath_int_reg_n_0; wire gtwiz_reset_rx_datapath_sync; wire gtwiz_reset_rx_done_int_reg_n_0; wire [0:0]gtwiz_reset_rx_done_out; wire [0:0]gtwiz_reset_rx_pll_and_datapath_in; wire gtwiz_reset_rx_pll_and_datapath_int_i_1_n_0; wire gtwiz_reset_rx_pll_and_datapath_int_reg_n_0; wire gtwiz_reset_rx_pll_and_datapath_sync; wire gtwiz_reset_tx_any_sync; wire gtwiz_reset_tx_datapath_sync; wire gtwiz_reset_tx_done_int_reg_n_0; wire [0:0]gtwiz_reset_tx_done_out; wire gtwiz_reset_tx_pll_and_datapath_dly; wire gtwiz_reset_tx_pll_and_datapath_int_i_1_n_0; wire gtwiz_reset_tx_pll_and_datapath_int_reg_n_0; wire gtwiz_reset_tx_pll_and_datapath_sync; wire gtwiz_reset_userclk_tx_active_sync; wire [0:0]gtwiz_userclk_rx_active_in; wire [0:0]gtwiz_userclk_tx_active_in; wire p_0_in; wire [9:0]p_0_in__0; wire [9:0]p_0_in__1; wire [2:0]p_1_in; wire plllock_rx_sync; wire plllock_tx_sync; wire reset_synchronizer_gtwiz_reset_rx_any_inst_n_1; wire reset_synchronizer_gtwiz_reset_rx_any_inst_n_2; wire reset_synchronizer_gtwiz_reset_rx_any_inst_n_3; wire reset_synchronizer_gtwiz_reset_tx_any_inst_n_1; wire reset_synchronizer_gtwiz_reset_tx_any_inst_n_2; wire reset_synchronizer_gtwiz_reset_tx_any_inst_n_3; wire rst_in0; wire [0:0]rxcdrlock_out; wire [0:0]rxusrclk2_in; wire sel; wire [2:0]sm_reset_all; wire [2:0]sm_reset_all__0; wire sm_reset_all_timer_clr_i_1_n_0; wire sm_reset_all_timer_clr_i_2_n_0; wire sm_reset_all_timer_clr_reg_n_0; wire [2:0]sm_reset_all_timer_ctr; wire sm_reset_all_timer_ctr0_n_0; wire \sm_reset_all_timer_ctr[0]_i_1_n_0 ; wire \sm_reset_all_timer_ctr[1]_i_1_n_0 ; wire \sm_reset_all_timer_ctr[2]_i_1_n_0 ; wire sm_reset_all_timer_sat; wire sm_reset_all_timer_sat_i_1_n_0; wire [2:0]sm_reset_rx; wire [2:0]sm_reset_rx__0; wire sm_reset_rx_cdr_to_clr; wire sm_reset_rx_cdr_to_clr_i_3_n_0; wire \sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ; wire \sm_reset_rx_cdr_to_ctr[0]_i_3_n_0 ; wire \sm_reset_rx_cdr_to_ctr[0]_i_4_n_0 ; wire \sm_reset_rx_cdr_to_ctr[0]_i_5_n_0 ; wire \sm_reset_rx_cdr_to_ctr[0]_i_6_n_0 ; wire \sm_reset_rx_cdr_to_ctr[0]_i_7_n_0 ; wire [25:0]sm_reset_rx_cdr_to_ctr_reg; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_0 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_1 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_10 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_11 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_12 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_13 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_14 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_15 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_2 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_3 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_4 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_5 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_6 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_7 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_8 ; wire \sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_9 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_0 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_1 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_10 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_11 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_12 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_13 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_14 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_15 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_2 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_3 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_4 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_5 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_6 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_7 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_8 ; wire \sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_9 ; wire \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_14 ; wire \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_15 ; wire \sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_7 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_0 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_1 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_10 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_11 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_12 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_13 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_14 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_15 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_2 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_3 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_4 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_5 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_6 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_7 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_8 ; wire \sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_9 ; wire sm_reset_rx_cdr_to_sat; wire sm_reset_rx_cdr_to_sat_i_1_n_0; wire sm_reset_rx_cdr_to_sat_i_2_n_0; wire sm_reset_rx_cdr_to_sat_i_3_n_0; wire sm_reset_rx_cdr_to_sat_i_4_n_0; wire sm_reset_rx_cdr_to_sat_i_5_n_0; wire sm_reset_rx_cdr_to_sat_i_6_n_0; wire sm_reset_rx_pll_timer_clr_i_1_n_0; wire sm_reset_rx_pll_timer_clr_reg_n_0; wire \sm_reset_rx_pll_timer_ctr[9]_i_1_n_0 ; wire \sm_reset_rx_pll_timer_ctr[9]_i_3_n_0 ; wire \sm_reset_rx_pll_timer_ctr[9]_i_4_n_0 ; wire [9:0]sm_reset_rx_pll_timer_ctr_reg; wire sm_reset_rx_pll_timer_sat; wire sm_reset_rx_pll_timer_sat_i_1_n_0; wire sm_reset_rx_pll_timer_sat_i_2_n_0; wire sm_reset_rx_pll_timer_sat_i_3_n_0; wire sm_reset_rx_timer_clr_reg_n_0; wire [2:0]sm_reset_rx_timer_ctr; wire sm_reset_rx_timer_ctr0_n_0; wire \sm_reset_rx_timer_ctr[0]_i_1_n_0 ; wire \sm_reset_rx_timer_ctr[1]_i_1_n_0 ; wire \sm_reset_rx_timer_ctr[2]_i_1_n_0 ; wire sm_reset_rx_timer_sat; wire sm_reset_rx_timer_sat_i_1_n_0; wire [2:0]sm_reset_tx; wire [2:0]sm_reset_tx__0; wire sm_reset_tx_pll_timer_clr_i_1_n_0; wire sm_reset_tx_pll_timer_clr_reg_n_0; wire \sm_reset_tx_pll_timer_ctr[9]_i_3_n_0 ; wire \sm_reset_tx_pll_timer_ctr[9]_i_4_n_0 ; wire [9:0]sm_reset_tx_pll_timer_ctr_reg; wire sm_reset_tx_pll_timer_sat; wire sm_reset_tx_pll_timer_sat_i_1_n_0; wire sm_reset_tx_pll_timer_sat_i_2_n_0; wire sm_reset_tx_pll_timer_sat_i_3_n_0; wire sm_reset_tx_timer_clr_reg_n_0; wire [2:0]sm_reset_tx_timer_ctr; wire sm_reset_tx_timer_sat; wire sm_reset_tx_timer_sat_i_1_n_0; wire txuserrdy_out_i_3_n_0; wire [0:0]txusrclk2_in; wire [7:1]\NLW_sm_reset_rx_cdr_to_ctr_reg[24]_i_1_CO_UNCONNECTED ; wire [7:2]\NLW_sm_reset_rx_cdr_to_ctr_reg[24]_i_1_O_UNCONNECTED ; LUT6 #( .INIT(64'h00FFF70000FFFFFF)) \FSM_sequential_sm_reset_all[0]_i_1 (.I0(gtwiz_reset_rx_done_int_reg_n_0), .I1(sm_reset_all_timer_sat), .I2(sm_reset_all_timer_clr_reg_n_0), .I3(sm_reset_all[2]), .I4(sm_reset_all[1]), .I5(sm_reset_all[0]), .O(sm_reset_all__0[0])); (* SOFT_HLUTNM = "soft_lutpair19" *) LUT3 #( .INIT(8'h34)) \FSM_sequential_sm_reset_all[1]_i_1 (.I0(sm_reset_all[2]), .I1(sm_reset_all[1]), .I2(sm_reset_all[0]), .O(sm_reset_all__0[1])); (* SOFT_HLUTNM = "soft_lutpair19" *) LUT3 #( .INIT(8'h4A)) \FSM_sequential_sm_reset_all[2]_i_2 (.I0(sm_reset_all[2]), .I1(sm_reset_all[0]), .I2(sm_reset_all[1]), .O(sm_reset_all__0[2])); (* SOFT_HLUTNM = "soft_lutpair16" *) LUT3 #( .INIT(8'h08)) \FSM_sequential_sm_reset_all[2]_i_3 (.I0(sm_reset_all_timer_sat), .I1(gtwiz_reset_rx_done_int_reg_n_0), .I2(sm_reset_all_timer_clr_reg_n_0), .O(\FSM_sequential_sm_reset_all[2]_i_3_n_0 )); (* SOFT_HLUTNM = "soft_lutpair16" *) LUT3 #( .INIT(8'h40)) \FSM_sequential_sm_reset_all[2]_i_4 (.I0(sm_reset_all_timer_clr_reg_n_0), .I1(sm_reset_all_timer_sat), .I2(gtwiz_reset_tx_done_int_reg_n_0), .O(\FSM_sequential_sm_reset_all[2]_i_4_n_0 )); (* FSM_ENCODED_STATES = "ST_RESET_ALL_BRANCH:000,ST_RESET_ALL_TX_PLL_WAIT:010,ST_RESET_ALL_RX_WAIT:101,ST_RESET_ALL_TX_PLL:001,ST_RESET_ALL_RX_PLL:100,ST_RESET_ALL_RX_DP:011,ST_RESET_ALL_INIT:111,iSTATE:110" *) FDRE #( .INIT(1'b1)) \FSM_sequential_sm_reset_all_reg[0] (.C(drpclk_in), .CE(bit_synchronizer_gtpowergood_inst_n_0), .D(sm_reset_all__0[0]), .Q(sm_reset_all[0]), .R(gtwiz_reset_all_sync)); (* FSM_ENCODED_STATES = "ST_RESET_ALL_BRANCH:000,ST_RESET_ALL_TX_PLL_WAIT:010,ST_RESET_ALL_RX_WAIT:101,ST_RESET_ALL_TX_PLL:001,ST_RESET_ALL_RX_PLL:100,ST_RESET_ALL_RX_DP:011,ST_RESET_ALL_INIT:111,iSTATE:110" *) FDRE #( .INIT(1'b1)) \FSM_sequential_sm_reset_all_reg[1] (.C(drpclk_in), .CE(bit_synchronizer_gtpowergood_inst_n_0), .D(sm_reset_all__0[1]), .Q(sm_reset_all[1]), .R(gtwiz_reset_all_sync)); (* FSM_ENCODED_STATES = "ST_RESET_ALL_BRANCH:000,ST_RESET_ALL_TX_PLL_WAIT:010,ST_RESET_ALL_RX_WAIT:101,ST_RESET_ALL_TX_PLL:001,ST_RESET_ALL_RX_PLL:100,ST_RESET_ALL_RX_DP:011,ST_RESET_ALL_INIT:111,iSTATE:110" *) FDRE #( .INIT(1'b1)) \FSM_sequential_sm_reset_all_reg[2] (.C(drpclk_in), .CE(bit_synchronizer_gtpowergood_inst_n_0), .D(sm_reset_all__0[2]), .Q(sm_reset_all[2]), .R(gtwiz_reset_all_sync)); (* SOFT_HLUTNM = "soft_lutpair11" *) LUT2 #( .INIT(4'h2)) \FSM_sequential_sm_reset_rx[1]_i_2 (.I0(sm_reset_rx_timer_sat), .I1(sm_reset_rx_timer_clr_reg_n_0), .O(\FSM_sequential_sm_reset_rx[1]_i_2_n_0 )); LUT6 #( .INIT(64'hDDFD8888DDDD8888)) \FSM_sequential_sm_reset_rx[2]_i_2 (.I0(sm_reset_rx[1]), .I1(sm_reset_rx[0]), .I2(sm_reset_rx_timer_sat), .I3(sm_reset_rx_timer_clr_reg_n_0), .I4(sm_reset_rx[2]), .I5(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ), .O(sm_reset_rx__0[2])); (* SOFT_HLUTNM = "soft_lutpair4" *) LUT5 #( .INIT(32'h00004000)) \FSM_sequential_sm_reset_rx[2]_i_6 (.I0(sm_reset_rx[0]), .I1(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ), .I2(sm_reset_rx[1]), .I3(sm_reset_rx_timer_sat), .I4(sm_reset_rx_timer_clr_reg_n_0), .O(\FSM_sequential_sm_reset_rx[2]_i_6_n_0 )); (* FSM_ENCODED_STATES = "ST_RESET_RX_WAIT_LOCK:011,ST_RESET_RX_WAIT_CDR:100,ST_RESET_RX_WAIT_USERRDY:101,ST_RESET_RX_WAIT_RESETDONE:110,ST_RESET_RX_DATAPATH:010,ST_RESET_RX_PLL:001,ST_RESET_RX_BRANCH:000,ST_RESET_RX_IDLE:111" *) FDRE #( .INIT(1'b0)) \FSM_sequential_sm_reset_rx_reg[0] (.C(drpclk_in), .CE(bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_2), .D(sm_reset_rx__0[0]), .Q(sm_reset_rx[0]), .R(gtwiz_reset_rx_any_sync)); (* FSM_ENCODED_STATES = "ST_RESET_RX_WAIT_LOCK:011,ST_RESET_RX_WAIT_CDR:100,ST_RESET_RX_WAIT_USERRDY:101,ST_RESET_RX_WAIT_RESETDONE:110,ST_RESET_RX_DATAPATH:010,ST_RESET_RX_PLL:001,ST_RESET_RX_BRANCH:000,ST_RESET_RX_IDLE:111" *) FDRE #( .INIT(1'b0)) \FSM_sequential_sm_reset_rx_reg[1] (.C(drpclk_in), .CE(bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_2), .D(sm_reset_rx__0[1]), .Q(sm_reset_rx[1]), .R(gtwiz_reset_rx_any_sync)); (* FSM_ENCODED_STATES = "ST_RESET_RX_WAIT_LOCK:011,ST_RESET_RX_WAIT_CDR:100,ST_RESET_RX_WAIT_USERRDY:101,ST_RESET_RX_WAIT_RESETDONE:110,ST_RESET_RX_DATAPATH:010,ST_RESET_RX_PLL:001,ST_RESET_RX_BRANCH:000,ST_RESET_RX_IDLE:111" *) FDRE #( .INIT(1'b0)) \FSM_sequential_sm_reset_rx_reg[2] (.C(drpclk_in), .CE(bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_2), .D(sm_reset_rx__0[2]), .Q(sm_reset_rx[2]), .R(gtwiz_reset_rx_any_sync)); (* SOFT_HLUTNM = "soft_lutpair12" *) LUT3 #( .INIT(8'h38)) \FSM_sequential_sm_reset_tx[2]_i_2 (.I0(sm_reset_tx[0]), .I1(sm_reset_tx[1]), .I2(sm_reset_tx[2]), .O(sm_reset_tx__0[2])); (* SOFT_HLUTNM = "soft_lutpair7" *) LUT2 #( .INIT(4'hE)) \FSM_sequential_sm_reset_tx[2]_i_3 (.I0(sm_reset_tx[1]), .I1(sm_reset_tx[2]), .O(\FSM_sequential_sm_reset_tx[2]_i_3_n_0 )); (* FSM_ENCODED_STATES = "ST_RESET_TX_BRANCH:000,ST_RESET_TX_WAIT_LOCK:011,ST_RESET_TX_WAIT_USERRDY:100,ST_RESET_TX_WAIT_RESETDONE:101,ST_RESET_TX_IDLE:110,ST_RESET_TX_DATAPATH:010,ST_RESET_TX_PLL:001" *) FDRE #( .INIT(1'b0)) \FSM_sequential_sm_reset_tx_reg[0] (.C(drpclk_in), .CE(bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst_n_0), .D(sm_reset_tx__0[0]), .Q(sm_reset_tx[0]), .R(gtwiz_reset_tx_any_sync)); (* FSM_ENCODED_STATES = "ST_RESET_TX_BRANCH:000,ST_RESET_TX_WAIT_LOCK:011,ST_RESET_TX_WAIT_USERRDY:100,ST_RESET_TX_WAIT_RESETDONE:101,ST_RESET_TX_IDLE:110,ST_RESET_TX_DATAPATH:010,ST_RESET_TX_PLL:001" *) FDRE #( .INIT(1'b0)) \FSM_sequential_sm_reset_tx_reg[1] (.C(drpclk_in), .CE(bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst_n_0), .D(sm_reset_tx__0[1]), .Q(sm_reset_tx[1]), .R(gtwiz_reset_tx_any_sync)); (* FSM_ENCODED_STATES = "ST_RESET_TX_BRANCH:000,ST_RESET_TX_WAIT_LOCK:011,ST_RESET_TX_WAIT_USERRDY:100,ST_RESET_TX_WAIT_RESETDONE:101,ST_RESET_TX_IDLE:110,ST_RESET_TX_DATAPATH:010,ST_RESET_TX_PLL:001" *) FDRE #( .INIT(1'b0)) \FSM_sequential_sm_reset_tx_reg[2] (.C(drpclk_in), .CE(bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst_n_0), .D(sm_reset_tx__0[2]), .Q(sm_reset_tx[2]), .R(gtwiz_reset_tx_any_sync)); aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_31 bit_synchronizer_gtpowergood_inst (.E(bit_synchronizer_gtpowergood_inst_n_0), .\FSM_sequential_sm_reset_all_reg[0] (\FSM_sequential_sm_reset_all[2]_i_3_n_0 ), .\FSM_sequential_sm_reset_all_reg[0]_0 (\FSM_sequential_sm_reset_all[2]_i_4_n_0 ), .Q(sm_reset_all), .drpclk_in(drpclk_in), .gtpowergood_out(gtpowergood_out)); aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_32 bit_synchronizer_gtwiz_reset_rx_datapath_dly_inst (.drpclk_in(drpclk_in), .gtwiz_reset_rx_datapath_dly(gtwiz_reset_rx_datapath_dly), .in0(gtwiz_reset_rx_datapath_sync)); aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_33 bit_synchronizer_gtwiz_reset_rx_pll_and_datapath_dly_inst (.D(sm_reset_rx__0[1:0]), .\FSM_sequential_sm_reset_rx_reg[0] (\FSM_sequential_sm_reset_rx[1]_i_2_n_0 ), .\FSM_sequential_sm_reset_rx_reg[0]_0 (\FSM_sequential_sm_reset_rx[2]_i_6_n_0 ), .Q(sm_reset_rx), .drpclk_in(drpclk_in), .\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync (\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ), .gtwiz_reset_rx_datapath_dly(gtwiz_reset_rx_datapath_dly), .i_in_out_reg_0(bit_synchronizer_gtwiz_reset_rx_pll_and_datapath_dly_inst_n_2), .in0(gtwiz_reset_rx_pll_and_datapath_sync)); aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_34 bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst (.E(bit_synchronizer_gtwiz_reset_tx_datapath_dly_inst_n_0), .\FSM_sequential_sm_reset_tx_reg[0] (\FSM_sequential_sm_reset_tx[2]_i_3_n_0 ), .\FSM_sequential_sm_reset_tx_reg[0]_0 (bit_synchronizer_plllock_tx_inst_n_2), .\FSM_sequential_sm_reset_tx_reg[0]_1 (bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_2), .Q(sm_reset_tx[0]), .drpclk_in(drpclk_in), .gtwiz_reset_tx_pll_and_datapath_dly(gtwiz_reset_tx_pll_and_datapath_dly), .in0(gtwiz_reset_tx_datapath_sync)); aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_35 bit_synchronizer_gtwiz_reset_tx_pll_and_datapath_dly_inst (.D(sm_reset_tx__0[1:0]), .Q(sm_reset_tx), .drpclk_in(drpclk_in), .gtwiz_reset_tx_pll_and_datapath_dly(gtwiz_reset_tx_pll_and_datapath_dly), .in0(gtwiz_reset_tx_pll_and_datapath_sync)); aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_36 bit_synchronizer_gtwiz_reset_userclk_rx_active_inst (.E(bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_2), .\FSM_sequential_sm_reset_rx_reg[0] (bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_0), .\FSM_sequential_sm_reset_rx_reg[0]_0 (bit_synchronizer_rxcdrlock_inst_n_1), .\FSM_sequential_sm_reset_rx_reg[0]_1 (bit_synchronizer_gtwiz_reset_rx_pll_and_datapath_dly_inst_n_2), .\FSM_sequential_sm_reset_rx_reg[0]_2 (sm_reset_rx_pll_timer_clr_reg_n_0), .\FSM_sequential_sm_reset_rx_reg[2] (bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_1), .Q(sm_reset_rx), .drpclk_in(drpclk_in), .\gen_gtwizard_gthe3.rxuserrdy_int (\gen_gtwizard_gthe3.rxuserrdy_int ), .gtwiz_reset_rx_any_sync(gtwiz_reset_rx_any_sync), .gtwiz_userclk_rx_active_in(gtwiz_userclk_rx_active_in), .sm_reset_rx_pll_timer_sat(sm_reset_rx_pll_timer_sat), .sm_reset_rx_timer_clr_reg(bit_synchronizer_plllock_rx_inst_n_2), .sm_reset_rx_timer_clr_reg_0(sm_reset_rx_timer_clr_reg_n_0), .sm_reset_rx_timer_sat(sm_reset_rx_timer_sat)); aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_37 bit_synchronizer_gtwiz_reset_userclk_tx_active_inst (.\FSM_sequential_sm_reset_tx_reg[0] (txuserrdy_out_i_3_n_0), .\FSM_sequential_sm_reset_tx_reg[0]_0 (\FSM_sequential_sm_reset_tx[2]_i_3_n_0 ), .\FSM_sequential_sm_reset_tx_reg[0]_1 (sm_reset_tx_pll_timer_clr_reg_n_0), .\FSM_sequential_sm_reset_tx_reg[2] (bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_1), .Q(sm_reset_tx), .drpclk_in(drpclk_in), .\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync (\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ), .gtwiz_reset_userclk_tx_active_sync(gtwiz_reset_userclk_tx_active_sync), .gtwiz_userclk_tx_active_in(gtwiz_userclk_tx_active_in), .i_in_out_reg_0(bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_2), .plllock_tx_sync(plllock_tx_sync), .sm_reset_tx_pll_timer_sat(sm_reset_tx_pll_timer_sat), .sm_reset_tx_timer_clr_reg(sm_reset_tx_timer_clr_reg_n_0), .sm_reset_tx_timer_clr_reg_0(gttxreset_out_i_3_n_0)); aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_38 bit_synchronizer_plllock_rx_inst (.\FSM_sequential_sm_reset_rx_reg[1] (bit_synchronizer_plllock_rx_inst_n_2), .Q(sm_reset_rx), .cplllock_out(cplllock_out), .drpclk_in(drpclk_in), .\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync (\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.rxresetdone_sync ), .gtwiz_reset_rx_done_int_reg(\FSM_sequential_sm_reset_rx[1]_i_2_n_0 ), .gtwiz_reset_rx_done_int_reg_0(gtwiz_reset_rx_done_int_reg_n_0), .i_in_out_reg_0(bit_synchronizer_plllock_rx_inst_n_1), .plllock_rx_sync(plllock_rx_sync)); aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_39 bit_synchronizer_plllock_tx_inst (.\FSM_sequential_sm_reset_tx_reg[0] (gttxreset_out_i_3_n_0), .Q(sm_reset_tx), .cplllock_out(cplllock_out), .drpclk_in(drpclk_in), .\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync (\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.txresetdone_sync ), .gtwiz_reset_tx_done_int_reg(bit_synchronizer_plllock_tx_inst_n_1), .gtwiz_reset_tx_done_int_reg_0(gtwiz_reset_tx_done_int_reg_n_0), .gtwiz_reset_tx_done_int_reg_1(sm_reset_tx_timer_clr_reg_n_0), .i_in_out_reg_0(bit_synchronizer_plllock_tx_inst_n_2), .plllock_tx_sync(plllock_tx_sync), .sm_reset_tx_timer_sat(sm_reset_tx_timer_sat)); aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_bit_synchronizer_40 bit_synchronizer_rxcdrlock_inst (.\FSM_sequential_sm_reset_rx_reg[0] (\FSM_sequential_sm_reset_rx[1]_i_2_n_0 ), .\FSM_sequential_sm_reset_rx_reg[1] (bit_synchronizer_rxcdrlock_inst_n_1), .\FSM_sequential_sm_reset_rx_reg[2] (bit_synchronizer_rxcdrlock_inst_n_0), .Q(sm_reset_rx), .drpclk_in(drpclk_in), .plllock_rx_sync(plllock_rx_sync), .rxcdrlock_out(rxcdrlock_out), .sm_reset_rx_cdr_to_clr(sm_reset_rx_cdr_to_clr), .sm_reset_rx_cdr_to_clr_reg(sm_reset_rx_cdr_to_clr_i_3_n_0), .sm_reset_rx_cdr_to_sat(sm_reset_rx_cdr_to_sat), .sm_reset_rx_cdr_to_sat_reg(bit_synchronizer_rxcdrlock_inst_n_2)); LUT2 #( .INIT(4'hE)) \gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST_i_1 (.I0(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int ), .I1(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int ), .O(\gen_gtwizard_gthe3.cpllpd_ch_int )); FDRE #( .INIT(1'b1)) gtrxreset_out_reg (.C(drpclk_in), .CE(1'b1), .D(reset_synchronizer_gtwiz_reset_rx_any_inst_n_3), .Q(\gen_gtwizard_gthe3.gtrxreset_int ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair10" *) LUT2 #( .INIT(4'h2)) gttxreset_out_i_3 (.I0(sm_reset_tx_timer_sat), .I1(sm_reset_tx_timer_clr_reg_n_0), .O(gttxreset_out_i_3_n_0)); FDRE #( .INIT(1'b1)) gttxreset_out_reg (.C(drpclk_in), .CE(1'b1), .D(reset_synchronizer_gtwiz_reset_tx_any_inst_n_2), .Q(\gen_gtwizard_gthe3.gttxreset_int ), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair13" *) LUT4 #( .INIT(16'hF740)) gtwiz_reset_rx_datapath_int_i_1 (.I0(sm_reset_all[2]), .I1(sm_reset_all[0]), .I2(sm_reset_all[1]), .I3(gtwiz_reset_rx_datapath_int_reg_n_0), .O(gtwiz_reset_rx_datapath_int_i_1_n_0)); FDRE #( .INIT(1'b0)) gtwiz_reset_rx_datapath_int_reg (.C(drpclk_in), .CE(1'b1), .D(gtwiz_reset_rx_datapath_int_i_1_n_0), .Q(gtwiz_reset_rx_datapath_int_reg_n_0), .R(gtwiz_reset_all_sync)); FDRE #( .INIT(1'b0)) gtwiz_reset_rx_done_int_reg (.C(drpclk_in), .CE(1'b1), .D(bit_synchronizer_plllock_rx_inst_n_1), .Q(gtwiz_reset_rx_done_int_reg_n_0), .R(gtwiz_reset_rx_any_sync)); LUT4 #( .INIT(16'hF704)) gtwiz_reset_rx_pll_and_datapath_int_i_1 (.I0(sm_reset_all[0]), .I1(sm_reset_all[2]), .I2(sm_reset_all[1]), .I3(gtwiz_reset_rx_pll_and_datapath_int_reg_n_0), .O(gtwiz_reset_rx_pll_and_datapath_int_i_1_n_0)); FDRE #( .INIT(1'b0)) gtwiz_reset_rx_pll_and_datapath_int_reg (.C(drpclk_in), .CE(1'b1), .D(gtwiz_reset_rx_pll_and_datapath_int_i_1_n_0), .Q(gtwiz_reset_rx_pll_and_datapath_int_reg_n_0), .R(gtwiz_reset_all_sync)); FDRE #( .INIT(1'b0)) gtwiz_reset_tx_done_int_reg (.C(drpclk_in), .CE(1'b1), .D(bit_synchronizer_plllock_tx_inst_n_1), .Q(gtwiz_reset_tx_done_int_reg_n_0), .R(gtwiz_reset_tx_any_sync)); (* SOFT_HLUTNM = "soft_lutpair13" *) LUT4 #( .INIT(16'hFB02)) gtwiz_reset_tx_pll_and_datapath_int_i_1 (.I0(sm_reset_all[0]), .I1(sm_reset_all[1]), .I2(sm_reset_all[2]), .I3(gtwiz_reset_tx_pll_and_datapath_int_reg_n_0), .O(gtwiz_reset_tx_pll_and_datapath_int_i_1_n_0)); FDRE #( .INIT(1'b0)) gtwiz_reset_tx_pll_and_datapath_int_reg (.C(drpclk_in), .CE(1'b1), .D(gtwiz_reset_tx_pll_and_datapath_int_i_1_n_0), .Q(gtwiz_reset_tx_pll_and_datapath_int_reg_n_0), .R(gtwiz_reset_all_sync)); FDRE #( .INIT(1'b0)) pllreset_rx_out_reg (.C(drpclk_in), .CE(1'b1), .D(reset_synchronizer_gtwiz_reset_rx_any_inst_n_1), .Q(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int ), .R(1'b0)); FDRE #( .INIT(1'b1)) pllreset_tx_out_reg (.C(drpclk_in), .CE(1'b1), .D(reset_synchronizer_gtwiz_reset_tx_any_inst_n_1), .Q(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int ), .R(1'b0)); aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer reset_synchronizer_gtwiz_reset_all_inst (.drpclk_in(drpclk_in), .gtwiz_reset_all_sync(gtwiz_reset_all_sync), .gtwiz_reset_rx_pll_and_datapath_in(gtwiz_reset_rx_pll_and_datapath_in)); aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_41 reset_synchronizer_gtwiz_reset_rx_any_inst (.\FSM_sequential_sm_reset_rx_reg[1] (reset_synchronizer_gtwiz_reset_rx_any_inst_n_1), .\FSM_sequential_sm_reset_rx_reg[1]_0 (reset_synchronizer_gtwiz_reset_rx_any_inst_n_2), .\FSM_sequential_sm_reset_rx_reg[1]_1 (reset_synchronizer_gtwiz_reset_rx_any_inst_n_3), .Q(sm_reset_rx), .drpclk_in(drpclk_in), .\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int (\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int ), .\gen_gtwizard_gthe3.gtrxreset_int (\gen_gtwizard_gthe3.gtrxreset_int ), .\gen_gtwizard_gthe3.rxprogdivreset_int (\gen_gtwizard_gthe3.rxprogdivreset_int ), .gtrxreset_out_reg(\FSM_sequential_sm_reset_rx[1]_i_2_n_0 ), .gtwiz_reset_rx_any_sync(gtwiz_reset_rx_any_sync), .gtwiz_reset_rx_datapath_in(gtwiz_reset_rx_datapath_in), .gtwiz_reset_rx_pll_and_datapath_in(gtwiz_reset_rx_pll_and_datapath_in), .plllock_rx_sync(plllock_rx_sync), .rst_in_out_reg_0(gtwiz_reset_rx_datapath_int_reg_n_0), .rst_in_out_reg_1(gtwiz_reset_rx_pll_and_datapath_int_reg_n_0), .rxprogdivreset_out_reg(bit_synchronizer_rxcdrlock_inst_n_2)); aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_42 reset_synchronizer_gtwiz_reset_rx_datapath_inst (.drpclk_in(drpclk_in), .gtwiz_reset_rx_datapath_in(gtwiz_reset_rx_datapath_in), .in0(gtwiz_reset_rx_datapath_sync), .rst_in_out_reg_0(gtwiz_reset_rx_datapath_int_reg_n_0)); aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_43 reset_synchronizer_gtwiz_reset_rx_pll_and_datapath_inst (.drpclk_in(drpclk_in), .gtwiz_reset_rx_pll_and_datapath_in(gtwiz_reset_rx_pll_and_datapath_in), .in0(gtwiz_reset_rx_pll_and_datapath_sync), .rst_in_out_reg_0(gtwiz_reset_rx_pll_and_datapath_int_reg_n_0)); aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_44 reset_synchronizer_gtwiz_reset_tx_any_inst (.\FSM_sequential_sm_reset_tx_reg[0] (reset_synchronizer_gtwiz_reset_tx_any_inst_n_3), .\FSM_sequential_sm_reset_tx_reg[1] (reset_synchronizer_gtwiz_reset_tx_any_inst_n_1), .\FSM_sequential_sm_reset_tx_reg[1]_0 (reset_synchronizer_gtwiz_reset_tx_any_inst_n_2), .Q(sm_reset_tx), .drpclk_in(drpclk_in), .\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int (\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int ), .\gen_gtwizard_gthe3.gttxreset_int (\gen_gtwizard_gthe3.gttxreset_int ), .\gen_gtwizard_gthe3.txuserrdy_int (\gen_gtwizard_gthe3.txuserrdy_int ), .gttxreset_out_reg(gttxreset_out_i_3_n_0), .gtwiz_reset_tx_any_sync(gtwiz_reset_tx_any_sync), .gtwiz_reset_userclk_tx_active_sync(gtwiz_reset_userclk_tx_active_sync), .plllock_tx_sync(plllock_tx_sync), .rst_in_out_reg_0(gtwiz_reset_tx_pll_and_datapath_int_reg_n_0), .txuserrdy_out_reg(txuserrdy_out_i_3_n_0)); aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_45 reset_synchronizer_gtwiz_reset_tx_datapath_inst (.drpclk_in(drpclk_in), .in0(gtwiz_reset_tx_datapath_sync)); aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_46 reset_synchronizer_gtwiz_reset_tx_pll_and_datapath_inst (.drpclk_in(drpclk_in), .in0(gtwiz_reset_tx_pll_and_datapath_sync), .rst_in_out_reg_0(gtwiz_reset_tx_pll_and_datapath_int_reg_n_0)); aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer reset_synchronizer_rx_done_inst (.gtwiz_reset_rx_done_out(gtwiz_reset_rx_done_out), .rst_in_sync2_reg_0(gtwiz_reset_rx_done_int_reg_n_0), .rxusrclk2_in(rxusrclk2_in)); aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer_47 reset_synchronizer_tx_done_inst (.gtwiz_reset_tx_done_out(gtwiz_reset_tx_done_out), .rst_in_sync2_reg_0(gtwiz_reset_tx_done_int_reg_n_0), .txusrclk2_in(txusrclk2_in)); aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_48 reset_synchronizer_txprogdivreset_inst (.drpclk_in(drpclk_in), .\gen_gtwizard_gthe3.txprogdivreset_int (\gen_gtwizard_gthe3.txprogdivreset_int ), .rst_in0(rst_in0)); FDRE #( .INIT(1'b1)) rxprogdivreset_out_reg (.C(drpclk_in), .CE(1'b1), .D(reset_synchronizer_gtwiz_reset_rx_any_inst_n_2), .Q(\gen_gtwizard_gthe3.rxprogdivreset_int ), .R(1'b0)); FDRE #( .INIT(1'b0)) rxuserrdy_out_reg (.C(drpclk_in), .CE(1'b1), .D(bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_1), .Q(\gen_gtwizard_gthe3.rxuserrdy_int ), .R(1'b0)); LUT5 #( .INIT(32'hEFFA200A)) sm_reset_all_timer_clr_i_1 (.I0(sm_reset_all_timer_clr_i_2_n_0), .I1(sm_reset_all[1]), .I2(sm_reset_all[2]), .I3(sm_reset_all[0]), .I4(sm_reset_all_timer_clr_reg_n_0), .O(sm_reset_all_timer_clr_i_1_n_0)); LUT6 #( .INIT(64'h0000B0003333BB33)) sm_reset_all_timer_clr_i_2 (.I0(gtwiz_reset_rx_done_int_reg_n_0), .I1(sm_reset_all[2]), .I2(gtwiz_reset_tx_done_int_reg_n_0), .I3(sm_reset_all_timer_sat), .I4(sm_reset_all_timer_clr_reg_n_0), .I5(sm_reset_all[1]), .O(sm_reset_all_timer_clr_i_2_n_0)); FDSE #( .INIT(1'b1)) sm_reset_all_timer_clr_reg (.C(drpclk_in), .CE(1'b1), .D(sm_reset_all_timer_clr_i_1_n_0), .Q(sm_reset_all_timer_clr_reg_n_0), .S(gtwiz_reset_all_sync)); LUT3 #( .INIT(8'h7F)) sm_reset_all_timer_ctr0 (.I0(sm_reset_all_timer_ctr[2]), .I1(sm_reset_all_timer_ctr[0]), .I2(sm_reset_all_timer_ctr[1]), .O(sm_reset_all_timer_ctr0_n_0)); LUT1 #( .INIT(2'h1)) \sm_reset_all_timer_ctr[0]_i_1 (.I0(sm_reset_all_timer_ctr[0]), .O(\sm_reset_all_timer_ctr[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair22" *) LUT2 #( .INIT(4'h6)) \sm_reset_all_timer_ctr[1]_i_1 (.I0(sm_reset_all_timer_ctr[0]), .I1(sm_reset_all_timer_ctr[1]), .O(\sm_reset_all_timer_ctr[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair22" *) LUT3 #( .INIT(8'h78)) \sm_reset_all_timer_ctr[2]_i_1 (.I0(sm_reset_all_timer_ctr[0]), .I1(sm_reset_all_timer_ctr[1]), .I2(sm_reset_all_timer_ctr[2]), .O(\sm_reset_all_timer_ctr[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \sm_reset_all_timer_ctr_reg[0] (.C(drpclk_in), .CE(sm_reset_all_timer_ctr0_n_0), .D(\sm_reset_all_timer_ctr[0]_i_1_n_0 ), .Q(sm_reset_all_timer_ctr[0]), .R(sm_reset_all_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_all_timer_ctr_reg[1] (.C(drpclk_in), .CE(sm_reset_all_timer_ctr0_n_0), .D(\sm_reset_all_timer_ctr[1]_i_1_n_0 ), .Q(sm_reset_all_timer_ctr[1]), .R(sm_reset_all_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_all_timer_ctr_reg[2] (.C(drpclk_in), .CE(sm_reset_all_timer_ctr0_n_0), .D(\sm_reset_all_timer_ctr[2]_i_1_n_0 ), .Q(sm_reset_all_timer_ctr[2]), .R(sm_reset_all_timer_clr_reg_n_0)); LUT5 #( .INIT(32'h0000FF80)) sm_reset_all_timer_sat_i_1 (.I0(sm_reset_all_timer_ctr[2]), .I1(sm_reset_all_timer_ctr[0]), .I2(sm_reset_all_timer_ctr[1]), .I3(sm_reset_all_timer_sat), .I4(sm_reset_all_timer_clr_reg_n_0), .O(sm_reset_all_timer_sat_i_1_n_0)); FDRE #( .INIT(1'b0)) sm_reset_all_timer_sat_reg (.C(drpclk_in), .CE(1'b1), .D(sm_reset_all_timer_sat_i_1_n_0), .Q(sm_reset_all_timer_sat), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair4" *) LUT3 #( .INIT(8'h40)) sm_reset_rx_cdr_to_clr_i_3 (.I0(sm_reset_rx_timer_clr_reg_n_0), .I1(sm_reset_rx_timer_sat), .I2(sm_reset_rx[1]), .O(sm_reset_rx_cdr_to_clr_i_3_n_0)); FDSE #( .INIT(1'b1)) sm_reset_rx_cdr_to_clr_reg (.C(drpclk_in), .CE(1'b1), .D(bit_synchronizer_rxcdrlock_inst_n_0), .Q(sm_reset_rx_cdr_to_clr), .S(gtwiz_reset_rx_any_sync)); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \sm_reset_rx_cdr_to_ctr[0]_i_1 (.I0(sm_reset_rx_cdr_to_ctr_reg[0]), .I1(sm_reset_rx_cdr_to_ctr_reg[1]), .I2(\sm_reset_rx_cdr_to_ctr[0]_i_3_n_0 ), .I3(\sm_reset_rx_cdr_to_ctr[0]_i_4_n_0 ), .I4(\sm_reset_rx_cdr_to_ctr[0]_i_5_n_0 ), .I5(\sm_reset_rx_cdr_to_ctr[0]_i_6_n_0 ), .O(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 )); LUT6 #( .INIT(64'hFFFFFFDFFFFFFFFF)) \sm_reset_rx_cdr_to_ctr[0]_i_3 (.I0(sm_reset_rx_cdr_to_ctr_reg[18]), .I1(sm_reset_rx_cdr_to_ctr_reg[19]), .I2(sm_reset_rx_cdr_to_ctr_reg[16]), .I3(sm_reset_rx_cdr_to_ctr_reg[17]), .I4(sm_reset_rx_cdr_to_ctr_reg[14]), .I5(sm_reset_rx_cdr_to_ctr_reg[15]), .O(\sm_reset_rx_cdr_to_ctr[0]_i_3_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFFE)) \sm_reset_rx_cdr_to_ctr[0]_i_4 (.I0(sm_reset_rx_cdr_to_ctr_reg[24]), .I1(sm_reset_rx_cdr_to_ctr_reg[25]), .I2(sm_reset_rx_cdr_to_ctr_reg[22]), .I3(sm_reset_rx_cdr_to_ctr_reg[23]), .I4(sm_reset_rx_cdr_to_ctr_reg[21]), .I5(sm_reset_rx_cdr_to_ctr_reg[20]), .O(\sm_reset_rx_cdr_to_ctr[0]_i_4_n_0 )); LUT6 #( .INIT(64'hFFFFFFDFFFFFFFFF)) \sm_reset_rx_cdr_to_ctr[0]_i_5 (.I0(sm_reset_rx_cdr_to_ctr_reg[13]), .I1(sm_reset_rx_cdr_to_ctr_reg[12]), .I2(sm_reset_rx_cdr_to_ctr_reg[10]), .I3(sm_reset_rx_cdr_to_ctr_reg[11]), .I4(sm_reset_rx_cdr_to_ctr_reg[9]), .I5(sm_reset_rx_cdr_to_ctr_reg[8]), .O(\sm_reset_rx_cdr_to_ctr[0]_i_5_n_0 )); LUT6 #( .INIT(64'hFFFFFFFFFFFFFFDF)) \sm_reset_rx_cdr_to_ctr[0]_i_6 (.I0(sm_reset_rx_cdr_to_ctr_reg[6]), .I1(sm_reset_rx_cdr_to_ctr_reg[7]), .I2(sm_reset_rx_cdr_to_ctr_reg[4]), .I3(sm_reset_rx_cdr_to_ctr_reg[5]), .I4(sm_reset_rx_cdr_to_ctr_reg[3]), .I5(sm_reset_rx_cdr_to_ctr_reg[2]), .O(\sm_reset_rx_cdr_to_ctr[0]_i_6_n_0 )); LUT1 #( .INIT(2'h1)) \sm_reset_rx_cdr_to_ctr[0]_i_7 (.I0(sm_reset_rx_cdr_to_ctr_reg[0]), .O(\sm_reset_rx_cdr_to_ctr[0]_i_7_n_0 )); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[0] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_15 ), .Q(sm_reset_rx_cdr_to_ctr_reg[0]), .R(sm_reset_rx_cdr_to_clr)); (* ADDER_THRESHOLD = "16" *) CARRY8 \sm_reset_rx_cdr_to_ctr_reg[0]_i_2 (.CI(1'b0), .CI_TOP(1'b0), .CO({\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_0 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_1 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_2 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_3 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_4 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_5 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_6 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_7 }), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1}), .O({\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_8 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_9 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_10 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_11 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_12 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_13 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_14 ,\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_15 }), .S({sm_reset_rx_cdr_to_ctr_reg[7:1],\sm_reset_rx_cdr_to_ctr[0]_i_7_n_0 })); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[10] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_13 ), .Q(sm_reset_rx_cdr_to_ctr_reg[10]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[11] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_12 ), .Q(sm_reset_rx_cdr_to_ctr_reg[11]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[12] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_11 ), .Q(sm_reset_rx_cdr_to_ctr_reg[12]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[13] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_10 ), .Q(sm_reset_rx_cdr_to_ctr_reg[13]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[14] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_9 ), .Q(sm_reset_rx_cdr_to_ctr_reg[14]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[15] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_8 ), .Q(sm_reset_rx_cdr_to_ctr_reg[15]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[16] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_15 ), .Q(sm_reset_rx_cdr_to_ctr_reg[16]), .R(sm_reset_rx_cdr_to_clr)); (* ADDER_THRESHOLD = "16" *) CARRY8 \sm_reset_rx_cdr_to_ctr_reg[16]_i_1 (.CI(\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_0 ), .CI_TOP(1'b0), .CO({\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_0 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_1 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_2 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_3 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_4 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_5 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_6 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_7 }), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .O({\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_8 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_9 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_10 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_11 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_12 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_13 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_14 ,\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_15 }), .S(sm_reset_rx_cdr_to_ctr_reg[23:16])); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[17] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_14 ), .Q(sm_reset_rx_cdr_to_ctr_reg[17]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[18] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_13 ), .Q(sm_reset_rx_cdr_to_ctr_reg[18]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[19] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_12 ), .Q(sm_reset_rx_cdr_to_ctr_reg[19]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[1] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_14 ), .Q(sm_reset_rx_cdr_to_ctr_reg[1]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[20] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_11 ), .Q(sm_reset_rx_cdr_to_ctr_reg[20]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[21] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_10 ), .Q(sm_reset_rx_cdr_to_ctr_reg[21]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[22] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_9 ), .Q(sm_reset_rx_cdr_to_ctr_reg[22]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[23] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_8 ), .Q(sm_reset_rx_cdr_to_ctr_reg[23]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[24] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_15 ), .Q(sm_reset_rx_cdr_to_ctr_reg[24]), .R(sm_reset_rx_cdr_to_clr)); (* ADDER_THRESHOLD = "16" *) CARRY8 \sm_reset_rx_cdr_to_ctr_reg[24]_i_1 (.CI(\sm_reset_rx_cdr_to_ctr_reg[16]_i_1_n_0 ), .CI_TOP(1'b0), .CO({\NLW_sm_reset_rx_cdr_to_ctr_reg[24]_i_1_CO_UNCONNECTED [7:1],\sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_7 }), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .O({\NLW_sm_reset_rx_cdr_to_ctr_reg[24]_i_1_O_UNCONNECTED [7:2],\sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_14 ,\sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_15 }), .S({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,sm_reset_rx_cdr_to_ctr_reg[25:24]})); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[25] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[24]_i_1_n_14 ), .Q(sm_reset_rx_cdr_to_ctr_reg[25]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[2] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_13 ), .Q(sm_reset_rx_cdr_to_ctr_reg[2]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[3] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_12 ), .Q(sm_reset_rx_cdr_to_ctr_reg[3]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[4] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_11 ), .Q(sm_reset_rx_cdr_to_ctr_reg[4]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[5] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_10 ), .Q(sm_reset_rx_cdr_to_ctr_reg[5]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[6] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_9 ), .Q(sm_reset_rx_cdr_to_ctr_reg[6]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[7] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_8 ), .Q(sm_reset_rx_cdr_to_ctr_reg[7]), .R(sm_reset_rx_cdr_to_clr)); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[8] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_15 ), .Q(sm_reset_rx_cdr_to_ctr_reg[8]), .R(sm_reset_rx_cdr_to_clr)); (* ADDER_THRESHOLD = "16" *) CARRY8 \sm_reset_rx_cdr_to_ctr_reg[8]_i_1 (.CI(\sm_reset_rx_cdr_to_ctr_reg[0]_i_2_n_0 ), .CI_TOP(1'b0), .CO({\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_0 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_1 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_2 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_3 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_4 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_5 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_6 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_7 }), .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .O({\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_8 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_9 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_10 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_11 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_12 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_13 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_14 ,\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_15 }), .S(sm_reset_rx_cdr_to_ctr_reg[15:8])); FDRE #( .INIT(1'b0)) \sm_reset_rx_cdr_to_ctr_reg[9] (.C(drpclk_in), .CE(\sm_reset_rx_cdr_to_ctr[0]_i_1_n_0 ), .D(\sm_reset_rx_cdr_to_ctr_reg[8]_i_1_n_14 ), .Q(sm_reset_rx_cdr_to_ctr_reg[9]), .R(sm_reset_rx_cdr_to_clr)); LUT3 #( .INIT(8'h0E)) sm_reset_rx_cdr_to_sat_i_1 (.I0(sm_reset_rx_cdr_to_sat), .I1(sm_reset_rx_cdr_to_sat_i_2_n_0), .I2(sm_reset_rx_cdr_to_clr), .O(sm_reset_rx_cdr_to_sat_i_1_n_0)); LUT6 #( .INIT(64'h0000000000008000)) sm_reset_rx_cdr_to_sat_i_2 (.I0(sm_reset_rx_cdr_to_sat_i_3_n_0), .I1(sm_reset_rx_cdr_to_sat_i_4_n_0), .I2(sm_reset_rx_cdr_to_sat_i_5_n_0), .I3(sm_reset_rx_cdr_to_sat_i_6_n_0), .I4(sm_reset_rx_cdr_to_ctr_reg[0]), .I5(sm_reset_rx_cdr_to_ctr_reg[1]), .O(sm_reset_rx_cdr_to_sat_i_2_n_0)); LUT6 #( .INIT(64'h0000000200000000)) sm_reset_rx_cdr_to_sat_i_3 (.I0(sm_reset_rx_cdr_to_ctr_reg[4]), .I1(sm_reset_rx_cdr_to_ctr_reg[5]), .I2(sm_reset_rx_cdr_to_ctr_reg[2]), .I3(sm_reset_rx_cdr_to_ctr_reg[3]), .I4(sm_reset_rx_cdr_to_ctr_reg[7]), .I5(sm_reset_rx_cdr_to_ctr_reg[6]), .O(sm_reset_rx_cdr_to_sat_i_3_n_0)); LUT6 #( .INIT(64'h0000000000000001)) sm_reset_rx_cdr_to_sat_i_4 (.I0(sm_reset_rx_cdr_to_ctr_reg[22]), .I1(sm_reset_rx_cdr_to_ctr_reg[23]), .I2(sm_reset_rx_cdr_to_ctr_reg[20]), .I3(sm_reset_rx_cdr_to_ctr_reg[21]), .I4(sm_reset_rx_cdr_to_ctr_reg[25]), .I5(sm_reset_rx_cdr_to_ctr_reg[24]), .O(sm_reset_rx_cdr_to_sat_i_4_n_0)); LUT6 #( .INIT(64'h0000002000000000)) sm_reset_rx_cdr_to_sat_i_5 (.I0(sm_reset_rx_cdr_to_ctr_reg[16]), .I1(sm_reset_rx_cdr_to_ctr_reg[17]), .I2(sm_reset_rx_cdr_to_ctr_reg[15]), .I3(sm_reset_rx_cdr_to_ctr_reg[14]), .I4(sm_reset_rx_cdr_to_ctr_reg[19]), .I5(sm_reset_rx_cdr_to_ctr_reg[18]), .O(sm_reset_rx_cdr_to_sat_i_5_n_0)); LUT6 #( .INIT(64'h0000002000000000)) sm_reset_rx_cdr_to_sat_i_6 (.I0(sm_reset_rx_cdr_to_ctr_reg[10]), .I1(sm_reset_rx_cdr_to_ctr_reg[11]), .I2(sm_reset_rx_cdr_to_ctr_reg[8]), .I3(sm_reset_rx_cdr_to_ctr_reg[9]), .I4(sm_reset_rx_cdr_to_ctr_reg[12]), .I5(sm_reset_rx_cdr_to_ctr_reg[13]), .O(sm_reset_rx_cdr_to_sat_i_6_n_0)); FDRE #( .INIT(1'b0)) sm_reset_rx_cdr_to_sat_reg (.C(drpclk_in), .CE(1'b1), .D(sm_reset_rx_cdr_to_sat_i_1_n_0), .Q(sm_reset_rx_cdr_to_sat), .R(1'b0)); LUT5 #( .INIT(32'hFFF3000B)) sm_reset_rx_pll_timer_clr_i_1 (.I0(sm_reset_rx_pll_timer_sat), .I1(sm_reset_rx[0]), .I2(sm_reset_rx[1]), .I3(sm_reset_rx[2]), .I4(sm_reset_rx_pll_timer_clr_reg_n_0), .O(sm_reset_rx_pll_timer_clr_i_1_n_0)); FDSE #( .INIT(1'b1)) sm_reset_rx_pll_timer_clr_reg (.C(drpclk_in), .CE(1'b1), .D(sm_reset_rx_pll_timer_clr_i_1_n_0), .Q(sm_reset_rx_pll_timer_clr_reg_n_0), .S(gtwiz_reset_rx_any_sync)); (* SOFT_HLUTNM = "soft_lutpair24" *) LUT1 #( .INIT(2'h1)) \sm_reset_rx_pll_timer_ctr[0]_i_1 (.I0(sm_reset_rx_pll_timer_ctr_reg[0]), .O(p_0_in__1[0])); (* SOFT_HLUTNM = "soft_lutpair24" *) LUT2 #( .INIT(4'h6)) \sm_reset_rx_pll_timer_ctr[1]_i_1 (.I0(sm_reset_rx_pll_timer_ctr_reg[1]), .I1(sm_reset_rx_pll_timer_ctr_reg[0]), .O(p_0_in__1[1])); (* SOFT_HLUTNM = "soft_lutpair15" *) LUT3 #( .INIT(8'h78)) \sm_reset_rx_pll_timer_ctr[2]_i_1 (.I0(sm_reset_rx_pll_timer_ctr_reg[1]), .I1(sm_reset_rx_pll_timer_ctr_reg[0]), .I2(sm_reset_rx_pll_timer_ctr_reg[2]), .O(p_0_in__1[2])); (* SOFT_HLUTNM = "soft_lutpair15" *) LUT4 #( .INIT(16'h7F80)) \sm_reset_rx_pll_timer_ctr[3]_i_1 (.I0(sm_reset_rx_pll_timer_ctr_reg[2]), .I1(sm_reset_rx_pll_timer_ctr_reg[0]), .I2(sm_reset_rx_pll_timer_ctr_reg[1]), .I3(sm_reset_rx_pll_timer_ctr_reg[3]), .O(p_0_in__1[3])); (* SOFT_HLUTNM = "soft_lutpair9" *) LUT5 #( .INIT(32'h7FFF8000)) \sm_reset_rx_pll_timer_ctr[4]_i_1 (.I0(sm_reset_rx_pll_timer_ctr_reg[3]), .I1(sm_reset_rx_pll_timer_ctr_reg[1]), .I2(sm_reset_rx_pll_timer_ctr_reg[0]), .I3(sm_reset_rx_pll_timer_ctr_reg[2]), .I4(sm_reset_rx_pll_timer_ctr_reg[4]), .O(p_0_in__1[4])); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \sm_reset_rx_pll_timer_ctr[5]_i_1 (.I0(sm_reset_rx_pll_timer_ctr_reg[4]), .I1(sm_reset_rx_pll_timer_ctr_reg[2]), .I2(sm_reset_rx_pll_timer_ctr_reg[0]), .I3(sm_reset_rx_pll_timer_ctr_reg[1]), .I4(sm_reset_rx_pll_timer_ctr_reg[3]), .I5(sm_reset_rx_pll_timer_ctr_reg[5]), .O(p_0_in__1[5])); (* SOFT_HLUTNM = "soft_lutpair18" *) LUT2 #( .INIT(4'h9)) \sm_reset_rx_pll_timer_ctr[6]_i_1 (.I0(\sm_reset_rx_pll_timer_ctr[9]_i_4_n_0 ), .I1(sm_reset_rx_pll_timer_ctr_reg[6]), .O(p_0_in__1[6])); (* SOFT_HLUTNM = "soft_lutpair18" *) LUT3 #( .INIT(8'hD2)) \sm_reset_rx_pll_timer_ctr[7]_i_1 (.I0(sm_reset_rx_pll_timer_ctr_reg[6]), .I1(\sm_reset_rx_pll_timer_ctr[9]_i_4_n_0 ), .I2(sm_reset_rx_pll_timer_ctr_reg[7]), .O(p_0_in__1[7])); (* SOFT_HLUTNM = "soft_lutpair6" *) LUT4 #( .INIT(16'hDF20)) \sm_reset_rx_pll_timer_ctr[8]_i_1 (.I0(sm_reset_rx_pll_timer_ctr_reg[7]), .I1(\sm_reset_rx_pll_timer_ctr[9]_i_4_n_0 ), .I2(sm_reset_rx_pll_timer_ctr_reg[6]), .I3(sm_reset_rx_pll_timer_ctr_reg[8]), .O(p_0_in__1[8])); LUT5 #( .INIT(32'hFFFFFFBF)) \sm_reset_rx_pll_timer_ctr[9]_i_1 (.I0(sm_reset_rx_pll_timer_ctr_reg[3]), .I1(sm_reset_rx_pll_timer_ctr_reg[2]), .I2(sm_reset_rx_pll_timer_ctr_reg[1]), .I3(sm_reset_rx_pll_timer_ctr_reg[0]), .I4(\sm_reset_rx_pll_timer_ctr[9]_i_3_n_0 ), .O(\sm_reset_rx_pll_timer_ctr[9]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair6" *) LUT5 #( .INIT(32'hF7FF0800)) \sm_reset_rx_pll_timer_ctr[9]_i_2 (.I0(sm_reset_rx_pll_timer_ctr_reg[8]), .I1(sm_reset_rx_pll_timer_ctr_reg[6]), .I2(\sm_reset_rx_pll_timer_ctr[9]_i_4_n_0 ), .I3(sm_reset_rx_pll_timer_ctr_reg[7]), .I4(sm_reset_rx_pll_timer_ctr_reg[9]), .O(p_0_in__1[9])); LUT6 #( .INIT(64'hFFFFFFEFFFFFFFFF)) \sm_reset_rx_pll_timer_ctr[9]_i_3 (.I0(sm_reset_rx_pll_timer_ctr_reg[8]), .I1(sm_reset_rx_pll_timer_ctr_reg[9]), .I2(sm_reset_rx_pll_timer_ctr_reg[6]), .I3(sm_reset_rx_pll_timer_ctr_reg[7]), .I4(sm_reset_rx_pll_timer_ctr_reg[4]), .I5(sm_reset_rx_pll_timer_ctr_reg[5]), .O(\sm_reset_rx_pll_timer_ctr[9]_i_3_n_0 )); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) \sm_reset_rx_pll_timer_ctr[9]_i_4 (.I0(sm_reset_rx_pll_timer_ctr_reg[4]), .I1(sm_reset_rx_pll_timer_ctr_reg[2]), .I2(sm_reset_rx_pll_timer_ctr_reg[0]), .I3(sm_reset_rx_pll_timer_ctr_reg[1]), .I4(sm_reset_rx_pll_timer_ctr_reg[3]), .I5(sm_reset_rx_pll_timer_ctr_reg[5]), .O(\sm_reset_rx_pll_timer_ctr[9]_i_4_n_0 )); FDRE #( .INIT(1'b0)) \sm_reset_rx_pll_timer_ctr_reg[0] (.C(drpclk_in), .CE(\sm_reset_rx_pll_timer_ctr[9]_i_1_n_0 ), .D(p_0_in__1[0]), .Q(sm_reset_rx_pll_timer_ctr_reg[0]), .R(sm_reset_rx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_rx_pll_timer_ctr_reg[1] (.C(drpclk_in), .CE(\sm_reset_rx_pll_timer_ctr[9]_i_1_n_0 ), .D(p_0_in__1[1]), .Q(sm_reset_rx_pll_timer_ctr_reg[1]), .R(sm_reset_rx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_rx_pll_timer_ctr_reg[2] (.C(drpclk_in), .CE(\sm_reset_rx_pll_timer_ctr[9]_i_1_n_0 ), .D(p_0_in__1[2]), .Q(sm_reset_rx_pll_timer_ctr_reg[2]), .R(sm_reset_rx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_rx_pll_timer_ctr_reg[3] (.C(drpclk_in), .CE(\sm_reset_rx_pll_timer_ctr[9]_i_1_n_0 ), .D(p_0_in__1[3]), .Q(sm_reset_rx_pll_timer_ctr_reg[3]), .R(sm_reset_rx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_rx_pll_timer_ctr_reg[4] (.C(drpclk_in), .CE(\sm_reset_rx_pll_timer_ctr[9]_i_1_n_0 ), .D(p_0_in__1[4]), .Q(sm_reset_rx_pll_timer_ctr_reg[4]), .R(sm_reset_rx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_rx_pll_timer_ctr_reg[5] (.C(drpclk_in), .CE(\sm_reset_rx_pll_timer_ctr[9]_i_1_n_0 ), .D(p_0_in__1[5]), .Q(sm_reset_rx_pll_timer_ctr_reg[5]), .R(sm_reset_rx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_rx_pll_timer_ctr_reg[6] (.C(drpclk_in), .CE(\sm_reset_rx_pll_timer_ctr[9]_i_1_n_0 ), .D(p_0_in__1[6]), .Q(sm_reset_rx_pll_timer_ctr_reg[6]), .R(sm_reset_rx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_rx_pll_timer_ctr_reg[7] (.C(drpclk_in), .CE(\sm_reset_rx_pll_timer_ctr[9]_i_1_n_0 ), .D(p_0_in__1[7]), .Q(sm_reset_rx_pll_timer_ctr_reg[7]), .R(sm_reset_rx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_rx_pll_timer_ctr_reg[8] (.C(drpclk_in), .CE(\sm_reset_rx_pll_timer_ctr[9]_i_1_n_0 ), .D(p_0_in__1[8]), .Q(sm_reset_rx_pll_timer_ctr_reg[8]), .R(sm_reset_rx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_rx_pll_timer_ctr_reg[9] (.C(drpclk_in), .CE(\sm_reset_rx_pll_timer_ctr[9]_i_1_n_0 ), .D(p_0_in__1[9]), .Q(sm_reset_rx_pll_timer_ctr_reg[9]), .R(sm_reset_rx_pll_timer_clr_reg_n_0)); LUT4 #( .INIT(16'h00EA)) sm_reset_rx_pll_timer_sat_i_1 (.I0(sm_reset_rx_pll_timer_sat), .I1(sm_reset_rx_pll_timer_sat_i_2_n_0), .I2(sm_reset_rx_pll_timer_sat_i_3_n_0), .I3(sm_reset_rx_pll_timer_clr_reg_n_0), .O(sm_reset_rx_pll_timer_sat_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair9" *) LUT4 #( .INIT(16'h0040)) sm_reset_rx_pll_timer_sat_i_2 (.I0(sm_reset_rx_pll_timer_ctr_reg[3]), .I1(sm_reset_rx_pll_timer_ctr_reg[2]), .I2(sm_reset_rx_pll_timer_ctr_reg[1]), .I3(sm_reset_rx_pll_timer_ctr_reg[0]), .O(sm_reset_rx_pll_timer_sat_i_2_n_0)); LUT6 #( .INIT(64'h0000000000000020)) sm_reset_rx_pll_timer_sat_i_3 (.I0(sm_reset_rx_pll_timer_ctr_reg[6]), .I1(sm_reset_rx_pll_timer_ctr_reg[7]), .I2(sm_reset_rx_pll_timer_ctr_reg[5]), .I3(sm_reset_rx_pll_timer_ctr_reg[4]), .I4(sm_reset_rx_pll_timer_ctr_reg[9]), .I5(sm_reset_rx_pll_timer_ctr_reg[8]), .O(sm_reset_rx_pll_timer_sat_i_3_n_0)); FDRE #( .INIT(1'b0)) sm_reset_rx_pll_timer_sat_reg (.C(drpclk_in), .CE(1'b1), .D(sm_reset_rx_pll_timer_sat_i_1_n_0), .Q(sm_reset_rx_pll_timer_sat), .R(1'b0)); FDSE #( .INIT(1'b1)) sm_reset_rx_timer_clr_reg (.C(drpclk_in), .CE(1'b1), .D(bit_synchronizer_gtwiz_reset_userclk_rx_active_inst_n_0), .Q(sm_reset_rx_timer_clr_reg_n_0), .S(gtwiz_reset_rx_any_sync)); LUT3 #( .INIT(8'h7F)) sm_reset_rx_timer_ctr0 (.I0(sm_reset_rx_timer_ctr[2]), .I1(sm_reset_rx_timer_ctr[0]), .I2(sm_reset_rx_timer_ctr[1]), .O(sm_reset_rx_timer_ctr0_n_0)); LUT1 #( .INIT(2'h1)) \sm_reset_rx_timer_ctr[0]_i_1 (.I0(sm_reset_rx_timer_ctr[0]), .O(\sm_reset_rx_timer_ctr[0]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair21" *) LUT2 #( .INIT(4'h6)) \sm_reset_rx_timer_ctr[1]_i_1 (.I0(sm_reset_rx_timer_ctr[0]), .I1(sm_reset_rx_timer_ctr[1]), .O(\sm_reset_rx_timer_ctr[1]_i_1_n_0 )); (* SOFT_HLUTNM = "soft_lutpair21" *) LUT3 #( .INIT(8'h78)) \sm_reset_rx_timer_ctr[2]_i_1 (.I0(sm_reset_rx_timer_ctr[0]), .I1(sm_reset_rx_timer_ctr[1]), .I2(sm_reset_rx_timer_ctr[2]), .O(\sm_reset_rx_timer_ctr[2]_i_1_n_0 )); FDRE #( .INIT(1'b0)) \sm_reset_rx_timer_ctr_reg[0] (.C(drpclk_in), .CE(sm_reset_rx_timer_ctr0_n_0), .D(\sm_reset_rx_timer_ctr[0]_i_1_n_0 ), .Q(sm_reset_rx_timer_ctr[0]), .R(sm_reset_rx_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_rx_timer_ctr_reg[1] (.C(drpclk_in), .CE(sm_reset_rx_timer_ctr0_n_0), .D(\sm_reset_rx_timer_ctr[1]_i_1_n_0 ), .Q(sm_reset_rx_timer_ctr[1]), .R(sm_reset_rx_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_rx_timer_ctr_reg[2] (.C(drpclk_in), .CE(sm_reset_rx_timer_ctr0_n_0), .D(\sm_reset_rx_timer_ctr[2]_i_1_n_0 ), .Q(sm_reset_rx_timer_ctr[2]), .R(sm_reset_rx_timer_clr_reg_n_0)); (* SOFT_HLUTNM = "soft_lutpair11" *) LUT5 #( .INIT(32'h0000FF80)) sm_reset_rx_timer_sat_i_1 (.I0(sm_reset_rx_timer_ctr[2]), .I1(sm_reset_rx_timer_ctr[0]), .I2(sm_reset_rx_timer_ctr[1]), .I3(sm_reset_rx_timer_sat), .I4(sm_reset_rx_timer_clr_reg_n_0), .O(sm_reset_rx_timer_sat_i_1_n_0)); FDRE #( .INIT(1'b0)) sm_reset_rx_timer_sat_reg (.C(drpclk_in), .CE(1'b1), .D(sm_reset_rx_timer_sat_i_1_n_0), .Q(sm_reset_rx_timer_sat), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair7" *) LUT5 #( .INIT(32'hEFEF1101)) sm_reset_tx_pll_timer_clr_i_1 (.I0(sm_reset_tx[1]), .I1(sm_reset_tx[2]), .I2(sm_reset_tx[0]), .I3(sm_reset_tx_pll_timer_sat), .I4(sm_reset_tx_pll_timer_clr_reg_n_0), .O(sm_reset_tx_pll_timer_clr_i_1_n_0)); FDSE #( .INIT(1'b1)) sm_reset_tx_pll_timer_clr_reg (.C(drpclk_in), .CE(1'b1), .D(sm_reset_tx_pll_timer_clr_i_1_n_0), .Q(sm_reset_tx_pll_timer_clr_reg_n_0), .S(gtwiz_reset_tx_any_sync)); (* SOFT_HLUTNM = "soft_lutpair23" *) LUT1 #( .INIT(2'h1)) \sm_reset_tx_pll_timer_ctr[0]_i_1 (.I0(sm_reset_tx_pll_timer_ctr_reg[0]), .O(p_0_in__0[0])); (* SOFT_HLUTNM = "soft_lutpair23" *) LUT2 #( .INIT(4'h6)) \sm_reset_tx_pll_timer_ctr[1]_i_1 (.I0(sm_reset_tx_pll_timer_ctr_reg[1]), .I1(sm_reset_tx_pll_timer_ctr_reg[0]), .O(p_0_in__0[1])); (* SOFT_HLUTNM = "soft_lutpair14" *) LUT3 #( .INIT(8'h78)) \sm_reset_tx_pll_timer_ctr[2]_i_1 (.I0(sm_reset_tx_pll_timer_ctr_reg[1]), .I1(sm_reset_tx_pll_timer_ctr_reg[0]), .I2(sm_reset_tx_pll_timer_ctr_reg[2]), .O(p_0_in__0[2])); (* SOFT_HLUTNM = "soft_lutpair14" *) LUT4 #( .INIT(16'h7F80)) \sm_reset_tx_pll_timer_ctr[3]_i_1 (.I0(sm_reset_tx_pll_timer_ctr_reg[2]), .I1(sm_reset_tx_pll_timer_ctr_reg[0]), .I2(sm_reset_tx_pll_timer_ctr_reg[1]), .I3(sm_reset_tx_pll_timer_ctr_reg[3]), .O(p_0_in__0[3])); (* SOFT_HLUTNM = "soft_lutpair8" *) LUT5 #( .INIT(32'h7FFF8000)) \sm_reset_tx_pll_timer_ctr[4]_i_1 (.I0(sm_reset_tx_pll_timer_ctr_reg[3]), .I1(sm_reset_tx_pll_timer_ctr_reg[1]), .I2(sm_reset_tx_pll_timer_ctr_reg[0]), .I3(sm_reset_tx_pll_timer_ctr_reg[2]), .I4(sm_reset_tx_pll_timer_ctr_reg[4]), .O(p_0_in__0[4])); LUT6 #( .INIT(64'h7FFFFFFF80000000)) \sm_reset_tx_pll_timer_ctr[5]_i_1 (.I0(sm_reset_tx_pll_timer_ctr_reg[4]), .I1(sm_reset_tx_pll_timer_ctr_reg[2]), .I2(sm_reset_tx_pll_timer_ctr_reg[0]), .I3(sm_reset_tx_pll_timer_ctr_reg[1]), .I4(sm_reset_tx_pll_timer_ctr_reg[3]), .I5(sm_reset_tx_pll_timer_ctr_reg[5]), .O(p_0_in__0[5])); (* SOFT_HLUTNM = "soft_lutpair17" *) LUT2 #( .INIT(4'h9)) \sm_reset_tx_pll_timer_ctr[6]_i_1 (.I0(\sm_reset_tx_pll_timer_ctr[9]_i_4_n_0 ), .I1(sm_reset_tx_pll_timer_ctr_reg[6]), .O(p_0_in__0[6])); (* SOFT_HLUTNM = "soft_lutpair17" *) LUT3 #( .INIT(8'hD2)) \sm_reset_tx_pll_timer_ctr[7]_i_1 (.I0(sm_reset_tx_pll_timer_ctr_reg[6]), .I1(\sm_reset_tx_pll_timer_ctr[9]_i_4_n_0 ), .I2(sm_reset_tx_pll_timer_ctr_reg[7]), .O(p_0_in__0[7])); (* SOFT_HLUTNM = "soft_lutpair5" *) LUT4 #( .INIT(16'hDF20)) \sm_reset_tx_pll_timer_ctr[8]_i_1 (.I0(sm_reset_tx_pll_timer_ctr_reg[7]), .I1(\sm_reset_tx_pll_timer_ctr[9]_i_4_n_0 ), .I2(sm_reset_tx_pll_timer_ctr_reg[6]), .I3(sm_reset_tx_pll_timer_ctr_reg[8]), .O(p_0_in__0[8])); LUT5 #( .INIT(32'hFFFFFFBF)) \sm_reset_tx_pll_timer_ctr[9]_i_1 (.I0(sm_reset_tx_pll_timer_ctr_reg[3]), .I1(sm_reset_tx_pll_timer_ctr_reg[2]), .I2(sm_reset_tx_pll_timer_ctr_reg[1]), .I3(sm_reset_tx_pll_timer_ctr_reg[0]), .I4(\sm_reset_tx_pll_timer_ctr[9]_i_3_n_0 ), .O(sel)); (* SOFT_HLUTNM = "soft_lutpair5" *) LUT5 #( .INIT(32'hF7FF0800)) \sm_reset_tx_pll_timer_ctr[9]_i_2 (.I0(sm_reset_tx_pll_timer_ctr_reg[8]), .I1(sm_reset_tx_pll_timer_ctr_reg[6]), .I2(\sm_reset_tx_pll_timer_ctr[9]_i_4_n_0 ), .I3(sm_reset_tx_pll_timer_ctr_reg[7]), .I4(sm_reset_tx_pll_timer_ctr_reg[9]), .O(p_0_in__0[9])); LUT6 #( .INIT(64'hFFFFFFEFFFFFFFFF)) \sm_reset_tx_pll_timer_ctr[9]_i_3 (.I0(sm_reset_tx_pll_timer_ctr_reg[8]), .I1(sm_reset_tx_pll_timer_ctr_reg[9]), .I2(sm_reset_tx_pll_timer_ctr_reg[6]), .I3(sm_reset_tx_pll_timer_ctr_reg[7]), .I4(sm_reset_tx_pll_timer_ctr_reg[4]), .I5(sm_reset_tx_pll_timer_ctr_reg[5]), .O(\sm_reset_tx_pll_timer_ctr[9]_i_3_n_0 )); LUT6 #( .INIT(64'h7FFFFFFFFFFFFFFF)) \sm_reset_tx_pll_timer_ctr[9]_i_4 (.I0(sm_reset_tx_pll_timer_ctr_reg[4]), .I1(sm_reset_tx_pll_timer_ctr_reg[2]), .I2(sm_reset_tx_pll_timer_ctr_reg[0]), .I3(sm_reset_tx_pll_timer_ctr_reg[1]), .I4(sm_reset_tx_pll_timer_ctr_reg[3]), .I5(sm_reset_tx_pll_timer_ctr_reg[5]), .O(\sm_reset_tx_pll_timer_ctr[9]_i_4_n_0 )); FDRE #( .INIT(1'b0)) \sm_reset_tx_pll_timer_ctr_reg[0] (.C(drpclk_in), .CE(sel), .D(p_0_in__0[0]), .Q(sm_reset_tx_pll_timer_ctr_reg[0]), .R(sm_reset_tx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_tx_pll_timer_ctr_reg[1] (.C(drpclk_in), .CE(sel), .D(p_0_in__0[1]), .Q(sm_reset_tx_pll_timer_ctr_reg[1]), .R(sm_reset_tx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_tx_pll_timer_ctr_reg[2] (.C(drpclk_in), .CE(sel), .D(p_0_in__0[2]), .Q(sm_reset_tx_pll_timer_ctr_reg[2]), .R(sm_reset_tx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_tx_pll_timer_ctr_reg[3] (.C(drpclk_in), .CE(sel), .D(p_0_in__0[3]), .Q(sm_reset_tx_pll_timer_ctr_reg[3]), .R(sm_reset_tx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_tx_pll_timer_ctr_reg[4] (.C(drpclk_in), .CE(sel), .D(p_0_in__0[4]), .Q(sm_reset_tx_pll_timer_ctr_reg[4]), .R(sm_reset_tx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_tx_pll_timer_ctr_reg[5] (.C(drpclk_in), .CE(sel), .D(p_0_in__0[5]), .Q(sm_reset_tx_pll_timer_ctr_reg[5]), .R(sm_reset_tx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_tx_pll_timer_ctr_reg[6] (.C(drpclk_in), .CE(sel), .D(p_0_in__0[6]), .Q(sm_reset_tx_pll_timer_ctr_reg[6]), .R(sm_reset_tx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_tx_pll_timer_ctr_reg[7] (.C(drpclk_in), .CE(sel), .D(p_0_in__0[7]), .Q(sm_reset_tx_pll_timer_ctr_reg[7]), .R(sm_reset_tx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_tx_pll_timer_ctr_reg[8] (.C(drpclk_in), .CE(sel), .D(p_0_in__0[8]), .Q(sm_reset_tx_pll_timer_ctr_reg[8]), .R(sm_reset_tx_pll_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_tx_pll_timer_ctr_reg[9] (.C(drpclk_in), .CE(sel), .D(p_0_in__0[9]), .Q(sm_reset_tx_pll_timer_ctr_reg[9]), .R(sm_reset_tx_pll_timer_clr_reg_n_0)); LUT4 #( .INIT(16'h00EA)) sm_reset_tx_pll_timer_sat_i_1 (.I0(sm_reset_tx_pll_timer_sat), .I1(sm_reset_tx_pll_timer_sat_i_2_n_0), .I2(sm_reset_tx_pll_timer_sat_i_3_n_0), .I3(sm_reset_tx_pll_timer_clr_reg_n_0), .O(sm_reset_tx_pll_timer_sat_i_1_n_0)); (* SOFT_HLUTNM = "soft_lutpair8" *) LUT4 #( .INIT(16'h0040)) sm_reset_tx_pll_timer_sat_i_2 (.I0(sm_reset_tx_pll_timer_ctr_reg[3]), .I1(sm_reset_tx_pll_timer_ctr_reg[2]), .I2(sm_reset_tx_pll_timer_ctr_reg[1]), .I3(sm_reset_tx_pll_timer_ctr_reg[0]), .O(sm_reset_tx_pll_timer_sat_i_2_n_0)); LUT6 #( .INIT(64'h0000000000000020)) sm_reset_tx_pll_timer_sat_i_3 (.I0(sm_reset_tx_pll_timer_ctr_reg[6]), .I1(sm_reset_tx_pll_timer_ctr_reg[7]), .I2(sm_reset_tx_pll_timer_ctr_reg[5]), .I3(sm_reset_tx_pll_timer_ctr_reg[4]), .I4(sm_reset_tx_pll_timer_ctr_reg[9]), .I5(sm_reset_tx_pll_timer_ctr_reg[8]), .O(sm_reset_tx_pll_timer_sat_i_3_n_0)); FDRE #( .INIT(1'b0)) sm_reset_tx_pll_timer_sat_reg (.C(drpclk_in), .CE(1'b1), .D(sm_reset_tx_pll_timer_sat_i_1_n_0), .Q(sm_reset_tx_pll_timer_sat), .R(1'b0)); FDSE #( .INIT(1'b1)) sm_reset_tx_timer_clr_reg (.C(drpclk_in), .CE(1'b1), .D(bit_synchronizer_gtwiz_reset_userclk_tx_active_inst_n_1), .Q(sm_reset_tx_timer_clr_reg_n_0), .S(gtwiz_reset_tx_any_sync)); LUT3 #( .INIT(8'h7F)) sm_reset_tx_timer_ctr0 (.I0(sm_reset_tx_timer_ctr[2]), .I1(sm_reset_tx_timer_ctr[0]), .I2(sm_reset_tx_timer_ctr[1]), .O(p_0_in)); LUT1 #( .INIT(2'h1)) \sm_reset_tx_timer_ctr[0]_i_1 (.I0(sm_reset_tx_timer_ctr[0]), .O(p_1_in[0])); (* SOFT_HLUTNM = "soft_lutpair20" *) LUT2 #( .INIT(4'h6)) \sm_reset_tx_timer_ctr[1]_i_1 (.I0(sm_reset_tx_timer_ctr[0]), .I1(sm_reset_tx_timer_ctr[1]), .O(p_1_in[1])); (* SOFT_HLUTNM = "soft_lutpair20" *) LUT3 #( .INIT(8'h78)) \sm_reset_tx_timer_ctr[2]_i_1 (.I0(sm_reset_tx_timer_ctr[0]), .I1(sm_reset_tx_timer_ctr[1]), .I2(sm_reset_tx_timer_ctr[2]), .O(p_1_in[2])); FDRE #( .INIT(1'b0)) \sm_reset_tx_timer_ctr_reg[0] (.C(drpclk_in), .CE(p_0_in), .D(p_1_in[0]), .Q(sm_reset_tx_timer_ctr[0]), .R(sm_reset_tx_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_tx_timer_ctr_reg[1] (.C(drpclk_in), .CE(p_0_in), .D(p_1_in[1]), .Q(sm_reset_tx_timer_ctr[1]), .R(sm_reset_tx_timer_clr_reg_n_0)); FDRE #( .INIT(1'b0)) \sm_reset_tx_timer_ctr_reg[2] (.C(drpclk_in), .CE(p_0_in), .D(p_1_in[2]), .Q(sm_reset_tx_timer_ctr[2]), .R(sm_reset_tx_timer_clr_reg_n_0)); (* SOFT_HLUTNM = "soft_lutpair10" *) LUT5 #( .INIT(32'h0000FF80)) sm_reset_tx_timer_sat_i_1 (.I0(sm_reset_tx_timer_ctr[2]), .I1(sm_reset_tx_timer_ctr[0]), .I2(sm_reset_tx_timer_ctr[1]), .I3(sm_reset_tx_timer_sat), .I4(sm_reset_tx_timer_clr_reg_n_0), .O(sm_reset_tx_timer_sat_i_1_n_0)); FDRE #( .INIT(1'b0)) sm_reset_tx_timer_sat_reg (.C(drpclk_in), .CE(1'b1), .D(sm_reset_tx_timer_sat_i_1_n_0), .Q(sm_reset_tx_timer_sat), .R(1'b0)); (* SOFT_HLUTNM = "soft_lutpair12" *) LUT4 #( .INIT(16'h0400)) txuserrdy_out_i_3 (.I0(sm_reset_tx[1]), .I1(sm_reset_tx[2]), .I2(sm_reset_tx_timer_clr_reg_n_0), .I3(sm_reset_tx_timer_sat), .O(txuserrdy_out_i_3_n_0)); FDRE #( .INIT(1'b0)) txuserrdy_out_reg (.C(drpclk_in), .CE(1'b1), .D(reset_synchronizer_gtwiz_reset_tx_any_inst_n_3), .Q(\gen_gtwizard_gthe3.txuserrdy_int ), .R(1'b0)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer" *) module aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer (gtwiz_reset_rx_done_out, rxusrclk2_in, rst_in_sync2_reg_0); output [0:0]gtwiz_reset_rx_done_out; input [0:0]rxusrclk2_in; input rst_in_sync2_reg_0; wire [0:0]gtwiz_reset_rx_done_out; (* async_reg = "true" *) wire rst_in_meta; wire rst_in_out_i_1_n_0; (* async_reg = "true" *) wire rst_in_sync1; (* async_reg = "true" *) wire rst_in_sync2; wire rst_in_sync2_reg_0; (* async_reg = "true" *) wire rst_in_sync3; wire [0:0]rxusrclk2_in; (* ASYNC_REG *) (* KEEP = "yes" *) FDCE #( .INIT(1'b0)) rst_in_meta_reg (.C(rxusrclk2_in), .CE(1'b1), .CLR(rst_in_out_i_1_n_0), .D(1'b1), .Q(rst_in_meta)); LUT1 #( .INIT(2'h1)) rst_in_out_i_1 (.I0(rst_in_sync2_reg_0), .O(rst_in_out_i_1_n_0)); FDCE #( .INIT(1'b0)) rst_in_out_reg (.C(rxusrclk2_in), .CE(1'b1), .CLR(rst_in_out_i_1_n_0), .D(rst_in_sync3), .Q(gtwiz_reset_rx_done_out)); (* ASYNC_REG *) (* KEEP = "yes" *) FDCE #( .INIT(1'b0)) rst_in_sync1_reg (.C(rxusrclk2_in), .CE(1'b1), .CLR(rst_in_out_i_1_n_0), .D(rst_in_meta), .Q(rst_in_sync1)); (* ASYNC_REG *) (* KEEP = "yes" *) FDCE #( .INIT(1'b0)) rst_in_sync2_reg (.C(rxusrclk2_in), .CE(1'b1), .CLR(rst_in_out_i_1_n_0), .D(rst_in_sync1), .Q(rst_in_sync2)); (* ASYNC_REG *) (* KEEP = "yes" *) FDCE #( .INIT(1'b0)) rst_in_sync3_reg (.C(rxusrclk2_in), .CE(1'b1), .CLR(rst_in_out_i_1_n_0), .D(rst_in_sync2), .Q(rst_in_sync3)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer" *) module aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_reset_inv_synchronizer_47 (gtwiz_reset_tx_done_out, txusrclk2_in, rst_in_sync2_reg_0); output [0:0]gtwiz_reset_tx_done_out; input [0:0]txusrclk2_in; input rst_in_sync2_reg_0; wire [0:0]gtwiz_reset_tx_done_out; (* async_reg = "true" *) wire rst_in_meta; wire rst_in_out_i_1__0_n_0; (* async_reg = "true" *) wire rst_in_sync1; (* async_reg = "true" *) wire rst_in_sync2; wire rst_in_sync2_reg_0; (* async_reg = "true" *) wire rst_in_sync3; wire [0:0]txusrclk2_in; (* ASYNC_REG *) (* KEEP = "yes" *) FDCE #( .INIT(1'b0)) rst_in_meta_reg (.C(txusrclk2_in), .CE(1'b1), .CLR(rst_in_out_i_1__0_n_0), .D(1'b1), .Q(rst_in_meta)); LUT1 #( .INIT(2'h1)) rst_in_out_i_1__0 (.I0(rst_in_sync2_reg_0), .O(rst_in_out_i_1__0_n_0)); FDCE #( .INIT(1'b0)) rst_in_out_reg (.C(txusrclk2_in), .CE(1'b1), .CLR(rst_in_out_i_1__0_n_0), .D(rst_in_sync3), .Q(gtwiz_reset_tx_done_out)); (* ASYNC_REG *) (* KEEP = "yes" *) FDCE #( .INIT(1'b0)) rst_in_sync1_reg (.C(txusrclk2_in), .CE(1'b1), .CLR(rst_in_out_i_1__0_n_0), .D(rst_in_meta), .Q(rst_in_sync1)); (* ASYNC_REG *) (* KEEP = "yes" *) FDCE #( .INIT(1'b0)) rst_in_sync2_reg (.C(txusrclk2_in), .CE(1'b1), .CLR(rst_in_out_i_1__0_n_0), .D(rst_in_sync1), .Q(rst_in_sync2)); (* ASYNC_REG *) (* KEEP = "yes" *) FDCE #( .INIT(1'b0)) rst_in_sync3_reg (.C(txusrclk2_in), .CE(1'b1), .CLR(rst_in_out_i_1__0_n_0), .D(rst_in_sync2), .Q(rst_in_sync3)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_reset_synchronizer" *) module aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer (gtwiz_reset_all_sync, drpclk_in, gtwiz_reset_rx_pll_and_datapath_in); output gtwiz_reset_all_sync; input [0:0]drpclk_in; input [0:0]gtwiz_reset_rx_pll_and_datapath_in; wire [0:0]drpclk_in; wire gtwiz_reset_all_sync; wire [0:0]gtwiz_reset_rx_pll_and_datapath_in; (* async_reg = "true" *) wire rst_in_meta; (* async_reg = "true" *) wire rst_in_sync1; (* async_reg = "true" *) wire rst_in_sync2; (* async_reg = "true" *) wire rst_in_sync3; (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(1'b0), .PRE(gtwiz_reset_rx_pll_and_datapath_in), .Q(rst_in_meta)); FDPE #( .INIT(1'b0)) rst_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync3), .PRE(gtwiz_reset_rx_pll_and_datapath_in), .Q(gtwiz_reset_all_sync)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_meta), .PRE(gtwiz_reset_rx_pll_and_datapath_in), .Q(rst_in_sync1)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync1), .PRE(gtwiz_reset_rx_pll_and_datapath_in), .Q(rst_in_sync2)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync2), .PRE(gtwiz_reset_rx_pll_and_datapath_in), .Q(rst_in_sync3)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_reset_synchronizer" *) module aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_41 (gtwiz_reset_rx_any_sync, \FSM_sequential_sm_reset_rx_reg[1] , \FSM_sequential_sm_reset_rx_reg[1]_0 , \FSM_sequential_sm_reset_rx_reg[1]_1 , drpclk_in, Q, \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int , rxprogdivreset_out_reg, \gen_gtwizard_gthe3.rxprogdivreset_int , plllock_rx_sync, gtrxreset_out_reg, \gen_gtwizard_gthe3.gtrxreset_int , rst_in_out_reg_0, gtwiz_reset_rx_datapath_in, gtwiz_reset_rx_pll_and_datapath_in, rst_in_out_reg_1); output gtwiz_reset_rx_any_sync; output \FSM_sequential_sm_reset_rx_reg[1] ; output \FSM_sequential_sm_reset_rx_reg[1]_0 ; output \FSM_sequential_sm_reset_rx_reg[1]_1 ; input [0:0]drpclk_in; input [2:0]Q; input \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int ; input rxprogdivreset_out_reg; input \gen_gtwizard_gthe3.rxprogdivreset_int ; input plllock_rx_sync; input gtrxreset_out_reg; input \gen_gtwizard_gthe3.gtrxreset_int ; input rst_in_out_reg_0; input [0:0]gtwiz_reset_rx_datapath_in; input [0:0]gtwiz_reset_rx_pll_and_datapath_in; input rst_in_out_reg_1; wire \FSM_sequential_sm_reset_rx_reg[1] ; wire \FSM_sequential_sm_reset_rx_reg[1]_0 ; wire \FSM_sequential_sm_reset_rx_reg[1]_1 ; wire [2:0]Q; wire [0:0]drpclk_in; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int ; wire \gen_gtwizard_gthe3.gtrxreset_int ; wire \gen_gtwizard_gthe3.rxprogdivreset_int ; wire gtrxreset_out_i_2_n_0; wire gtrxreset_out_reg; wire gtwiz_reset_rx_any; wire gtwiz_reset_rx_any_sync; wire [0:0]gtwiz_reset_rx_datapath_in; wire [0:0]gtwiz_reset_rx_pll_and_datapath_in; wire plllock_rx_sync; (* async_reg = "true" *) wire rst_in_meta; wire rst_in_out_reg_0; wire rst_in_out_reg_1; (* async_reg = "true" *) wire rst_in_sync1; (* async_reg = "true" *) wire rst_in_sync2; (* async_reg = "true" *) wire rst_in_sync3; wire rxprogdivreset_out_reg; LUT6 #( .INIT(64'h7FFFFFFF44884488)) gtrxreset_out_i_1 (.I0(Q[1]), .I1(gtrxreset_out_i_2_n_0), .I2(plllock_rx_sync), .I3(Q[0]), .I4(gtrxreset_out_reg), .I5(\gen_gtwizard_gthe3.gtrxreset_int ), .O(\FSM_sequential_sm_reset_rx_reg[1]_1 )); (* SOFT_HLUTNM = "soft_lutpair2" *) LUT2 #( .INIT(4'h1)) gtrxreset_out_i_2 (.I0(gtwiz_reset_rx_any_sync), .I1(Q[2]), .O(gtrxreset_out_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair2" *) LUT5 #( .INIT(32'hFDFF0100)) pllreset_rx_out_i_1 (.I0(Q[1]), .I1(Q[2]), .I2(gtwiz_reset_rx_any_sync), .I3(Q[0]), .I4(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_rx_int ), .O(\FSM_sequential_sm_reset_rx_reg[1] )); LUT4 #( .INIT(16'hFFFE)) rst_in_meta_i_1 (.I0(rst_in_out_reg_0), .I1(gtwiz_reset_rx_datapath_in), .I2(gtwiz_reset_rx_pll_and_datapath_in), .I3(rst_in_out_reg_1), .O(gtwiz_reset_rx_any)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(1'b0), .PRE(gtwiz_reset_rx_any), .Q(rst_in_meta)); FDPE #( .INIT(1'b0)) rst_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync3), .PRE(gtwiz_reset_rx_any), .Q(gtwiz_reset_rx_any_sync)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_meta), .PRE(gtwiz_reset_rx_any), .Q(rst_in_sync1)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync1), .PRE(gtwiz_reset_rx_any), .Q(rst_in_sync2)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync2), .PRE(gtwiz_reset_rx_any), .Q(rst_in_sync3)); LUT6 #( .INIT(64'hFFFBFFFF00120012)) rxprogdivreset_out_i_1 (.I0(Q[1]), .I1(Q[2]), .I2(Q[0]), .I3(gtwiz_reset_rx_any_sync), .I4(rxprogdivreset_out_reg), .I5(\gen_gtwizard_gthe3.rxprogdivreset_int ), .O(\FSM_sequential_sm_reset_rx_reg[1]_0 )); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_reset_synchronizer" *) module aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_42 (in0, drpclk_in, gtwiz_reset_rx_datapath_in, rst_in_out_reg_0); output in0; input [0:0]drpclk_in; input [0:0]gtwiz_reset_rx_datapath_in; input rst_in_out_reg_0; wire [0:0]drpclk_in; wire [0:0]gtwiz_reset_rx_datapath_in; wire in0; wire rst_in0_1; (* async_reg = "true" *) wire rst_in_meta; wire rst_in_out_reg_0; (* async_reg = "true" *) wire rst_in_sync1; (* async_reg = "true" *) wire rst_in_sync2; (* async_reg = "true" *) wire rst_in_sync3; LUT2 #( .INIT(4'hE)) rst_in_meta_i_1__1 (.I0(gtwiz_reset_rx_datapath_in), .I1(rst_in_out_reg_0), .O(rst_in0_1)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(1'b0), .PRE(rst_in0_1), .Q(rst_in_meta)); FDPE #( .INIT(1'b0)) rst_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync3), .PRE(rst_in0_1), .Q(in0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_meta), .PRE(rst_in0_1), .Q(rst_in_sync1)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync1), .PRE(rst_in0_1), .Q(rst_in_sync2)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync2), .PRE(rst_in0_1), .Q(rst_in_sync3)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_reset_synchronizer" *) module aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_43 (in0, drpclk_in, rst_in_out_reg_0, gtwiz_reset_rx_pll_and_datapath_in); output in0; input [0:0]drpclk_in; input rst_in_out_reg_0; input [0:0]gtwiz_reset_rx_pll_and_datapath_in; wire [0:0]drpclk_in; wire [0:0]gtwiz_reset_rx_pll_and_datapath_in; wire in0; wire p_0_in_0; (* async_reg = "true" *) wire rst_in_meta; wire rst_in_out_reg_0; (* async_reg = "true" *) wire rst_in_sync1; (* async_reg = "true" *) wire rst_in_sync2; (* async_reg = "true" *) wire rst_in_sync3; LUT2 #( .INIT(4'hE)) rst_in_meta_i_1__0 (.I0(rst_in_out_reg_0), .I1(gtwiz_reset_rx_pll_and_datapath_in), .O(p_0_in_0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(1'b0), .PRE(p_0_in_0), .Q(rst_in_meta)); FDPE #( .INIT(1'b0)) rst_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync3), .PRE(p_0_in_0), .Q(in0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_meta), .PRE(p_0_in_0), .Q(rst_in_sync1)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync1), .PRE(p_0_in_0), .Q(rst_in_sync2)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync2), .PRE(p_0_in_0), .Q(rst_in_sync3)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_reset_synchronizer" *) module aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_44 (gtwiz_reset_tx_any_sync, \FSM_sequential_sm_reset_tx_reg[1] , \FSM_sequential_sm_reset_tx_reg[1]_0 , \FSM_sequential_sm_reset_tx_reg[0] , drpclk_in, rst_in_out_reg_0, Q, \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int , plllock_tx_sync, gttxreset_out_reg, \gen_gtwizard_gthe3.gttxreset_int , txuserrdy_out_reg, gtwiz_reset_userclk_tx_active_sync, \gen_gtwizard_gthe3.txuserrdy_int ); output gtwiz_reset_tx_any_sync; output \FSM_sequential_sm_reset_tx_reg[1] ; output \FSM_sequential_sm_reset_tx_reg[1]_0 ; output \FSM_sequential_sm_reset_tx_reg[0] ; input [0:0]drpclk_in; input rst_in_out_reg_0; input [2:0]Q; input \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int ; input plllock_tx_sync; input gttxreset_out_reg; input \gen_gtwizard_gthe3.gttxreset_int ; input txuserrdy_out_reg; input gtwiz_reset_userclk_tx_active_sync; input \gen_gtwizard_gthe3.txuserrdy_int ; wire \FSM_sequential_sm_reset_tx_reg[0] ; wire \FSM_sequential_sm_reset_tx_reg[1] ; wire \FSM_sequential_sm_reset_tx_reg[1]_0 ; wire [2:0]Q; wire [0:0]drpclk_in; wire \gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int ; wire \gen_gtwizard_gthe3.gttxreset_int ; wire \gen_gtwizard_gthe3.txuserrdy_int ; wire gttxreset_out_i_2_n_0; wire gttxreset_out_reg; wire gtwiz_reset_tx_any_sync; wire gtwiz_reset_userclk_tx_active_sync; wire plllock_tx_sync; (* async_reg = "true" *) wire rst_in_meta; wire rst_in_out_reg_0; (* async_reg = "true" *) wire rst_in_sync1; (* async_reg = "true" *) wire rst_in_sync2; (* async_reg = "true" *) wire rst_in_sync3; wire txuserrdy_out_i_2_n_0; wire txuserrdy_out_reg; LUT6 #( .INIT(64'h7FFFFFFF44884488)) gttxreset_out_i_1 (.I0(Q[1]), .I1(gttxreset_out_i_2_n_0), .I2(plllock_tx_sync), .I3(Q[0]), .I4(gttxreset_out_reg), .I5(\gen_gtwizard_gthe3.gttxreset_int ), .O(\FSM_sequential_sm_reset_tx_reg[1]_0 )); LUT2 #( .INIT(4'h1)) gttxreset_out_i_2 (.I0(gtwiz_reset_tx_any_sync), .I1(Q[2]), .O(gttxreset_out_i_2_n_0)); (* SOFT_HLUTNM = "soft_lutpair3" *) LUT5 #( .INIT(32'hFDFF0100)) pllreset_tx_out_i_1 (.I0(Q[1]), .I1(Q[2]), .I2(gtwiz_reset_tx_any_sync), .I3(Q[0]), .I4(\gen_gtwizard_gthe3.gen_reset_controller_internal.gen_single_instance.gtwiz_reset_pllreset_tx_int ), .O(\FSM_sequential_sm_reset_tx_reg[1] )); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(1'b0), .PRE(rst_in_out_reg_0), .Q(rst_in_meta)); FDPE #( .INIT(1'b0)) rst_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync3), .PRE(rst_in_out_reg_0), .Q(gtwiz_reset_tx_any_sync)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_meta), .PRE(rst_in_out_reg_0), .Q(rst_in_sync1)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync1), .PRE(rst_in_out_reg_0), .Q(rst_in_sync2)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync2), .PRE(rst_in_out_reg_0), .Q(rst_in_sync3)); LUT6 #( .INIT(64'hDD55DD5588008C00)) txuserrdy_out_i_1 (.I0(txuserrdy_out_i_2_n_0), .I1(txuserrdy_out_reg), .I2(Q[0]), .I3(gtwiz_reset_userclk_tx_active_sync), .I4(gtwiz_reset_tx_any_sync), .I5(\gen_gtwizard_gthe3.txuserrdy_int ), .O(\FSM_sequential_sm_reset_tx_reg[0] )); (* SOFT_HLUTNM = "soft_lutpair3" *) LUT4 #( .INIT(16'h0110)) txuserrdy_out_i_2 (.I0(Q[2]), .I1(gtwiz_reset_tx_any_sync), .I2(Q[1]), .I3(Q[0]), .O(txuserrdy_out_i_2_n_0)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_reset_synchronizer" *) module aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_45 (in0, drpclk_in); output in0; input [0:0]drpclk_in; wire [0:0]drpclk_in; wire in0; (* async_reg = "true" *) wire rst_in_meta; (* async_reg = "true" *) wire rst_in_sync1; (* async_reg = "true" *) wire rst_in_sync2; (* async_reg = "true" *) wire rst_in_sync3; (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) rst_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(1'b0), .Q(rst_in_meta), .R(1'b0)); FDRE #( .INIT(1'b0)) rst_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync3), .Q(in0), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) rst_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_meta), .Q(rst_in_sync1), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) rst_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync1), .Q(rst_in_sync2), .R(1'b0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDRE #( .INIT(1'b0)) rst_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync2), .Q(rst_in_sync3), .R(1'b0)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_reset_synchronizer" *) module aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_46 (in0, drpclk_in, rst_in_out_reg_0); output in0; input [0:0]drpclk_in; input rst_in_out_reg_0; wire [0:0]drpclk_in; wire in0; (* async_reg = "true" *) wire rst_in_meta; wire rst_in_out_reg_0; (* async_reg = "true" *) wire rst_in_sync1; (* async_reg = "true" *) wire rst_in_sync2; (* async_reg = "true" *) wire rst_in_sync3; (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(1'b0), .PRE(rst_in_out_reg_0), .Q(rst_in_meta)); FDPE #( .INIT(1'b0)) rst_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync3), .PRE(rst_in_out_reg_0), .Q(in0)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_meta), .PRE(rst_in_out_reg_0), .Q(rst_in_sync1)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync1), .PRE(rst_in_out_reg_0), .Q(rst_in_sync2)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync2), .PRE(rst_in_out_reg_0), .Q(rst_in_sync3)); endmodule (* ORIG_REF_NAME = "gtwizard_ultrascale_v1_7_9_reset_synchronizer" *) module aurora_64b66b_0_gtwizard_ultrascale_v1_7_9_reset_synchronizer_48 (\gen_gtwizard_gthe3.txprogdivreset_int , drpclk_in, rst_in0); output \gen_gtwizard_gthe3.txprogdivreset_int ; input [0:0]drpclk_in; input rst_in0; wire [0:0]drpclk_in; wire \gen_gtwizard_gthe3.txprogdivreset_int ; wire rst_in0; (* async_reg = "true" *) wire rst_in_meta; (* async_reg = "true" *) wire rst_in_sync1; (* async_reg = "true" *) wire rst_in_sync2; (* async_reg = "true" *) wire rst_in_sync3; (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_meta_reg (.C(drpclk_in), .CE(1'b1), .D(1'b0), .PRE(rst_in0), .Q(rst_in_meta)); FDPE #( .INIT(1'b0)) rst_in_out_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync3), .PRE(rst_in0), .Q(\gen_gtwizard_gthe3.txprogdivreset_int )); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync1_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_meta), .PRE(rst_in0), .Q(rst_in_sync1)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync2_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync1), .PRE(rst_in0), .Q(rst_in_sync2)); (* ASYNC_REG *) (* KEEP = "yes" *) FDPE #( .INIT(1'b0)) rst_in_sync3_reg (.C(drpclk_in), .CE(1'b1), .D(rst_in_sync2), .PRE(rst_in0), .Q(rst_in_sync3)); endmodule `pragma protect begin_protected `pragma protect version = 1 `pragma protect encrypt_agent = "XILINX" `pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2020.2" `pragma protect key_keyowner="Cadence Design Systems.", key_keyname="cds_rsa_key", key_method="rsa" `pragma protect encoding = (enctype="BASE64", line_length=76, bytes=64) `pragma protect key_block SFoQ2tXDMrL2nCJbfpmHXuteJlKaWDWl3o9OY1miFvmYb8EDywmDpLUHQktJ/VoW+17fK5WHgFVI FZV1B91GDQ== `pragma protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa" `pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128) `pragma protect key_block mxGWDRjEAsKmBqldxevT1RKZvqK7vn0KlTODVXNGlRcGf9zOAmj0Z7Ppu79POBDb8oNQyCY+2q1q BddzhQfh5WLIVX9BNUMIF6M6IF0elM4GMSLHGeYEwqSaMPC+thuR8FGj1J7z6rH+43gDYhtIeyY+ ZuZUz/Pqg8Lu63Xwe+0= `pragma protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa" `pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) `pragma protect key_block HLwPjQzkuqv5FEDBriEJS2DikBeIHB/bWuVWooHY5ChdoHatcmqCHpSvnGxVzLwObZWHFys2nR9y P3zxywjtgtOWq/n3cYVa5li6eyiUmGXv2OE8nw1nLnAY1kzBvGd6VwQ45t6l4Hx5+oqpIfuU2KI2 7/Qpj2atiTN3Y+q5He/BMXLIxF9vWuU6XL/+HsxriGAumcZDuESdidlxOztbW1bFhYr1/qWwou2q wynnRVKYHL41aWycgFdkDoDEFFxv8ft8+F5Ux+J5Hg5XdgRULJc6uUQE/lDG3zOqzPftlODB52zU d0cm8gFOvSZ2nO8ZB8THnxoAGe33iIZJfMcefA== `pragma protect key_keyowner="ATRENTA", key_keyname="ATR-SG-2015-RSA-3", key_method="rsa" `pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) `pragma protect key_block jlR0iZ4fp9QXiFgaT07DMAK1YFLyBpsOGOOR9j2PWImFEh8oTBt4cvmGo+2z1Umbt9OMQwOhyepO QIsKLFzUXYUba+SFFLBoCiaww24KICecbUfd3VV5sg2bEJjAdtYTT6mJqyc3vQRvBlONeBFdIGy2 AXqdK7QtXGLsLAIF/z4FG8cfG6nSD6e16gccBC6+kl5MoShdnmebKLyoo6UKFdMbDK88sHvTcD9S LNCau6RK7FkTZg23FV0tf6cTP9Rray9YEcowm2AAh51Wldo2lGJ2W5iiDatRKH/W1bu7FGWZG+OT +VZE+Ckiuf4T6cuu+G5IbrtMv6a4U93R0gtxXQ== `pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VELOCE-RSA", key_method="rsa" `pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128) `pragma protect key_block p/kq+JjPPJbOTWT2SRiPJ99/iH6kkVGEiluRRXpuRN+j+cVPgJD1v4QVjw3zMWLlvTGB7OOqC+JG Lc62Wiizd/BFfGj2JYkTZMatcOWok7A87HK+vRTjr4nZMApD2jKaneJdU1279KsIEeRfImCQ2uRl QRNMH3PPdNGYCnOGgNk= `pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-2", key_method="rsa" `pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) `pragma protect key_block kyyI/O29YYc5VBwhz19i7AV7MC75r43hHVKAOTBiGBhRu8zZxCwGGcNFqc2HgHcWC6nq4jCIbIXf S3FDzPdasegnERlWvoob9/SXM88zKsyeTbUf+DRu5lB8SPROBMaIhnj375C5XLowL17MXZdmB6fV X5ukCg7cNhCjssKt/bIJibWkfna7hvj4ye+CLWmi3LdEiix8KTwRoBS3ZJrjM4/N6FfZkXerVxs+ txkhdsmG9ga1g/xErhTRilhqrV2WetlpX86qH/64sRGVxrWeEfNoHhMZsqEK0jWDx4WavKt8XY7W NDzMXLZ2m5Dv5HMiJWgFG+ntPwgiYYtBuwu7Eg== `pragma protect key_keyowner="Real Intent", key_keyname="RI-RSA-KEY-1", key_method="rsa" `pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) `pragma protect key_block tv6UL1ZWqo3dAIlhN5UTNGzJyqzdHpCqh217JPvIvHiWJgcFh2tw1n7HWnOPcK3VhCt31AGnCEFe HpTiinXvHna65L2X2HhtNUrsgvZlUuh/oQR273wp5JPFDPD97NQ4ELkGI+w26HTYLgZ70K5rQo87 D4AkQNRuzTRS5G12yb4RU7ZYgmkYLuq1UyqjlxyN62Del4XoqZyivOGw5H+7wlfkNRu98iQwqq12 jthZbH/ue5wxZJUcb7NmEwL+3abpyDNmWs1qORHOFoE3t97/9XMmeSCpM2+KnSKJvsV5VbuoTCOT 964fsEh7ey4IVb4aum095gQjLCqTmDm8DWFmaw== `pragma protect key_keyowner="Xilinx", key_keyname="xilinxt_2020_08", key_method="rsa" `pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) `pragma protect key_block Oxo3AgNmVWgrXtMKDIThYfXr0YJfyFr7Bsjn2ge/G72mb25MA8Dbkd9ZZPtwqU1poazNnTng5Cx5 s8C1zMNEoo38jNY8zEUBjCCuasJgeMo5xsiha+3ZIBiuHS0KLrjLaPFIQZdsYevb44fg6J5YQLn5 jd1M6YdNMd1VwSezDxtbk9sN8ExPrmtwum/6L1ia9j9UlIzPTEaJ60Xz7tloPsgsbkborO2JLiIk kIAY2q1b8tuhHzJ5DoXlvIo49wSDj75ncLrkwbAd26huob7aOmX1bS34pJLF17JzqYH0MoPJbHxb RPdD+qUawXFsMSs2fOLnZrNxeG8L+TyAT0N8tQ== `pragma protect key_keyowner="Metrics Technologies Inc.", key_keyname="DSim", key_method="rsa" `pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256) `pragma protect key_block CIR/vwxo0IBrPr5+bMp2YuBCQTNBRIIbqgEB18Oewkc8CuHzGCAgPyQUBUKaUG3bBy+KDOPVxBP5 cE/d3QYZAT11fyB1OMMTrjmEIZcr0Vk3nVTAnivoxxxkmdzPjkj0OcGcU9fMArPi3dfTgIsKdtCq 94+mV/70WeprgijzuZFWD7uH+gVioY/+rq/Wc1O6x1n949w8YGgSCTurUvhsobx2bonoC317J0Wm IX17XRkSBIFgzqA8iC+GV5oCfxIGkihKmXxjIJbMamlOdCOycEkjkh3JYmm7TLNxmI65iffsabR0 t5+iI0l8eJxFhElzWeREqE43cnJYLaKZBUA+DA== `pragma protect data_method = "AES128-CBC" `pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 55808) `pragma protect data_block xty1bzxPBpd5bdpG1VV8nS9o8YEpsWzpZKvh9IbslaC0+cde3Eohmh8pMOESxMBMjXq1CXFmW4s/ EqKmAnD2pcpgC8LxM1ZIA4jwVu0IG2OwKSHHAORJQb5B3fkupljPCBF0jXFggcZwGGcaNd16jl9P jgLoFb0jmId2J1ZiphO5B6yhamodAA8VQsKctOZOqPcEPoeJRBKiQ0Y4UZu078/CHhFQpeoTqgzm sxP9fLk81Rybnt0m5saecvg2NgdyozFteO9PxJrp3QF5+ovHJAnHmlBh4jcCfGaAc0zcZdC+avd5 6F1rcbcA5/P8GaWy7BQuMabf2CvY4SW6KS45wduKMFPNjHEBacGH+aUfzZmOI/vCL7toI53NN97o 6N4hzJbPHkaEbkJ5/TpnDYjOYIhYMgeC0TwkGbnwBpuu09a1B2uPQYg2tcNpXQDMUJgKN5M1dBsg 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= 0; parameter GRES_WIDTH = 10000; parameter GRES_START = 10000; //-------- STARTUP Globals -------------- wire GSR; wire GTS; wire GWE; wire PRLD; wire GRESTORE; tri1 p_up_tmp; tri (weak1, strong0) PLL_LOCKG = p_up_tmp; wire PROGB_GLBL; wire CCLKO_GLBL; wire FCSBO_GLBL; wire [3:0] DO_GLBL; wire [3:0] DI_GLBL; reg GSR_int; reg GTS_int; reg PRLD_int; reg GRESTORE_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_RUNTEST_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (strong1, weak0) GSR = GSR_int; assign (strong1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; assign (strong1, weak0) GRESTORE = GRESTORE_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end initial begin GRESTORE_int = 1'b0; #(GRES_START); GRESTORE_int = 1'b1; #(GRES_WIDTH); GRESTORE_int = 1'b0; end endmodule `endif