##################################################################################
 ##
 ## Project:  Aurora 64B/66B
 ## Company:  Xilinx
 ##
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 #################################################################################
 ##
 ##
 ##  aurora_64b66b_0
 ##
 ##
 ##  Description: This is the design constraints file for a 1 lane Aurora
 ##               core.
 ##               This is aurora.xdc
 ##               User should provide correct IO STANDARD for the LOC allocation.
 ##
 #################################################################################

 ################################ CLOCK CONSTRAINTS ##############################
### ## TX/RX OUTCLK constrain
### create_clock -period 6.400	 [get_pins -filter {REF_PIN_NAME=~*txoutclk_out[0]} -of_objects [get_cells -hierarchical -filter {NAME =~ *multi_gt_i*_gt_i*}]]
### set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins -filter {REF_PIN_NAME=~*txoutclk_out[0]} -of_objects [get_cells -hierarchical -filter {NAME =~ *multi_gt_i*_gt_i*}]] -include_generated_clocks]
### create_clock -period 6.400	 [get_pins -filter {REF_PIN_NAME=~*rxoutclk_out[0]} -of_objects [get_cells -hierarchical -filter {NAME =~ *multi_gt_i*_gt_i*}]]
### set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins -filter {REF_PIN_NAME=~*rxoutclk_out[0]} -of_objects [get_cells -hierarchical -filter {NAME =~ *multi_gt_i*_gt_i*}]] -include_generated_clocks]
### 
 ### Reference clock location; provided for reference
 ### set_property LOC AR9 [get_ports GTHQ0_P]
 ### set_property LOC AR8 [get_ports GTHQ0_N]

################################################################################

  ##############################################################################
   ##puts "Update Conditional pin locs based upon the board references"
   # below constraints are only placeholders
   # These are reference purpose and user should update it

   #set_property LOC E18 [get_ports init_clk]
   #set_property IOSTANDARD LVCMOS18 [get_ports init_clk]

   ##set_property LOC G19 [get_ports RESET]
   #set_property IOSTANDARD LVCMOS18 [get_ports RESET]

   ##set_property LOC K18 [get_ports PMA_INIT]
   #set_property IOSTANDARD LVCMOS18 [get_ports PMA_INIT]
   ##set_property LOC A20 [get_ports CHANNEL_UP]
   #set_property IOSTANDARD LVCMOS18 [get_ports CHANNEL_UP]
   ##set_property LOC A17 [get_ports LANE_UP]
   #set_property IOSTANDARD LVCMOS18 [get_ports LANE_UP]
################################################################################
################################################################################
  #*below constraints are copied from GT, need to update based upon the shared and non shared mode. ***
    # below false path constraints are copied from the GT wizards for CPLL based test cases
    # False path constraints
    # ----------------------------------------------------------------------------------------------------------------------
    # below constraints are related to the blocks of Ultrascale GT Wizard which are in Aurora core like
    # Tx and Rx user clock modules etc.
    # UltraScale FPGAs Transceivers Wizard IP example design-level XDC file
    # ----------------------------------------------------------------------------------------------------------------------
	 #set_false_path -through [get_cells -hierarchical -filter {NAME =~ *ultrascale_tx_userclk_1*gtwiz_userclk_tx_active_out_reg}]
	 #set_false_path -through [get_pins -filter {REF_PIN_NAME=~*CLR} -of_objects [get_cells -hierarchical -filter {NAME =~ *ultrascale_tx_userclk_1*gtwiz_userclk_tx_active_out_reg*}]]
  
	#set_false_path -through [get_cells -hierarchical -filter {NAME =~ *ultrascale_rx_userclk*gtwiz_userclk_rx_active_out_reg}] 
     #set_false_path -through [get_pins -filter {REF_PIN_NAME=~*CLR} -of_objects [get_cells -hierarchical -filter {NAME =~ *ultrascale_rx_userclk*bufg_gt_usrclk*inst*}]]
     set_false_path -through [get_pins -filter {REF_PIN_NAME=~*gtwiz_userclk_rx_reset_in} -of_objects [get_cells -hierarchical -filter {NAME =~ *ultrascale_rx_userclk}]]
	# ----------------------------------------------------------------------------------------------------------------------

################################################################################

 # below constraint is needed for core
 set_false_path -to [get_pins -hier *aurora_64b66b_0_cdc_to*/D]

################################################################################
#Note: GT based location constraints are available in the GT subcore referencec created in the project. 
#      Based upon the board chosen user need to edit the locations.
################################################################################