------------------------------------------------------- --! @file --! @author Julian Mendez (CERN - EP-ESE-BE) --! @version 6.0 --! @brief GBT-FPGA IP - Top Level ------------------------------------------------------- --! Include the IEEE VHDL standard library library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; --! Include the GBT-FPGA specific packages use work.gbt_bank_package.all; use work.vendor_specific_gbt_bank_package.all; --! @brief GBT_BANK - TOP Level --! @details --! The gbt_bank module implements the logic required to implement the encoding/decoding --! required to communicate or emulate a GBTx entity gbt_bankx12 is generic ( BLK_No : integer := 0; TX_OPTIMIZATION : integer range 0 to 1 := LATENCY_OPTIMIZED; --! TX_OPTIMIZATION: Latency mode for the Tx path (STANDARD or LATENCY_OPTIMIZED) RX_OPTIMIZATION : integer range 0 to 1 := STANDARD; --! RX_OPTIMIZATION: Latency mode for the Rx path (STANDARD or LATENCY_OPTIMIZED) TX_ENCODING : integer range 0 to 2 := GBT_FRAME; --! TX_ENCODING: Encoding scheme for the Tx datapath (GBT_FRAME or WIDE_BUS) RX_ENCODING : integer range 0 to 2 := GBT_FRAME --! RX_ENCODING: Encoding scheme for the Rx datapath (GBT_FRAME or WIDE_BUS) ); port ( --========-- -- Resets -- --========-- MGT_RESET_i : in std_logic; MGT_RXRESET_i : in std_logic_vector(11 downto 0); --! Reset the Rx path of the transceiver [Clock domain: MGT_CLK_i] GBT_TXRESET_i : in std_logic_vector(11 downto 0); --! Reset the Tx Scrambler/Encoder and the Tx Gearbox [Clock domain: GBT_TXFRAMECLK_i] GBT_RXRESET_i : in std_logic_vector(11 downto 0); --! Reset the Rx Decoder/Descrambler and the Rx gearbox [Clock domain: GBT_RXFRAMECLK_i] HPTD_RESET_i : in std_logic_vector(11 downto 0); --! Reset the Rx Decoder/Descrambler and the Rx gearbox [Clock domain: GBT_RXFRAMECLK_i] --========-- -- Clocks -- --========-- gtrefclk : in STD_LOGIC; DRPclk : in STD_LOGIC; tx_wordclk : in STD_LOGIC; mgt_en : in STD_LOGIC_VECTOR (11 downto 0); loopback : in STD_LOGIC_VECTOR (2 downto 0); cpll_locked : out STD_LOGIC_VECTOR (11 downto 0); rxn : in STD_LOGIC_VECTOR (11 downto 0); rxp : in STD_LOGIC_VECTOR (11 downto 0); txn : out STD_LOGIC_VECTOR (11 downto 0); txp : out STD_LOGIC_VECTOR (11 downto 0); GBT_TXCLKEn_i : in std_logic; --! Rx clock enable signal used when the Rx frameclock is different from 40MHz GBT_RXCLKEn_i : in std_logic_vector(11 downto 0); --! Rx clock enable signal used when the Rx frameclock is different from 40MHz MGT_RXWORDCLK_o : out std_logic_vector(11 downto 0); --! Rx Wordclock from the transceiver (could be used to clock the core with Clocking enable) --================-- -- GBT TX Control -- --================-- TX_ENCODING_SEL_i : in std_logic_vector(11 downto 0); --! Select the Tx encoding in dynamic mode ('1': GBT / '0': WideBus) GBT_ISDATAFLAG_i : in std_logic_vector(11 downto 0); --! Enable dataflag (header) [Clock domain: GBT_TXFRAMECLK_i] --=================-- -- GBT TX Status -- --=================-- TX_PHCOMPUTED_o : out std_logic_vector(11 downto 0); --! Tx frameclock and Tx wordclock alignement is computed (flag) TX_PHALIGNED_o : out std_logic_vector(11 downto 0); --! Tx frameclock and Tx wordclock are aligned (gearbox is working correctly) --================-- -- GBT RX Control -- --================-- RX_ENCODING_SEL_i : in std_logic_vector(11 downto 0); --! Select the Rx encoding in dynamic mode ('1': GBT / '0': WideBus) --=================-- -- GBT RX Status -- --=================-- GBT_RXREADY_o : out std_logic_vector(11 downto 0); --! GBT Encoding/Scrambler is ready[Clock domain: GBT_RXFRAMECLK_i] GBT_ISDATAFLAG_o : out std_logic_vector(11 downto 0); --! Header Is data flag [Clock domain: GBT_RXFRAMECLK_i] GBT_ERRORDETECTED_o : out std_logic_vector(11 downto 0); --! Pulsed when error has been corrected by the decoder [Clock domain: GBT_RXFRAMECLK_i] GBT_ERRORFLAG_o : out gbt_reg84_A(11 downto 0); --! Position of high level bits indicate the position of the bits flipped by the decoder [Clock domain: GBT_RXFRAMECLK_i] --=================-- -- MGT Status -- --=================-- MGT_TXREADY_o : out std_logic_vector(11 downto 0); --! Transceiver tx's path ready signal [Clock domain: MGT_CLK_i] MGT_RXREADY_o : out std_logic_vector(11 downto 0); --! Transceiver rx's path ready signal [Clock domain: MGT_CLK_i] MGT_HEADERFLAG_o : out std_logic_vector(11 downto 0); --! Pulsed when the MGT word contains the header [Clock domain: MGT_RXWORDCLK_o] MGT_RESET_TX_DONE_o : out std_logic_vector(11 downto 0); --! Transceiver tx's path ready signal [Clock domain: MGT_CLK_i] --========-- -- Data -- --========-- GBT_TXDATA_i : in gbt_reg84_A(11 downto 0); --! GBT Data to be encoded and transmit GBT_RXDATA_o : out gbt_reg84_A(11 downto 0); --! GBT Data received and decoded WB_TXDATA_i : in gbt_reg32_A(11 downto 0); --! (tx) Extra data (32bit) to replace the FEC when the WideBus encoding scheme is selected WB_RXDATA_o : out gbt_reg32_A(11 downto 0) --! (rx) Extra data (32bit) replacing the FEC when the WideBus encoding scheme is selected ); end gbt_bankx12; --! @brief GBT_BANK architecture - TOP Level --! @details The GBT_BANK architecture instantiates the Tx datapath, Rx datapath, Gearboxes for the clock domain --! crossing and the transceiver required to establish GBT links. architecture structural of gbt_bankx12 is --========-- -- GBT TX -- --========-- signal gbt_txencdata_s : gbt_reg120_A (11 downto 0); --! Encoded data buses used to connect the output of the datapath to the Tx gearbox signal gbt_txclkfromDesc_s : std_logic_vector(11 downto 0); --========-- -- MGT -- --========-- -- signal mgt_txwordclk_s : std_logic; --! Tx wordclock signal used to connect the clock from the transceiver to the Tx gearbox signal mgt_rxwordclk_s : std_logic_vector(11 downto 0); --! Rx wordclock signal used to connect the clock recovered from the data to the Rx gearbox signal mgt_txword_s : tx_word_A (11 downto 0); --! Tx word to the transceiver (from the Tx gearbox to the MGT) signal mgt_rxword_s : rx_word_A (11 downto 0); --! Rx word from the transceiver (from the transceiver to the Rx gearbox) signal mgt_headerflag_s : std_logic_vector(11 downto 0); --! Header flag to provide the header position over the 3/6 MGT word used to make the GBT word --========-- -- GBT Rx -- --========-- type array12X5 is array(0 to 12) of unsigned(4 downto 0); signal rx_data_good_cntr : array12X5; signal gbt_rxencdata_s : gbt_reg120_A (11 downto 0); --! Encoded data buses used to connect the output of the Rx gearbox to the datapath signal gbt_rx_reset : std_logic_vector(11 downto 0); signal gbt_rxgearboxready_s : std_logic_vector(11 downto 0); signal gbt_rxgearboxready_r : std_logic_vector(11 downto 0); signal rx_data_good : std_logic_vector(11 downto 0); signal GBT_ERRORDETECTED : std_logic_vector(11 downto 0); --=====================================================================================-- --=================================================================================================-- begin --========#### Architecture Body ####========-- --=================================================================================================-- GBT_ERRORDETECTED_o <= GBT_ERRORDETECTED; g_rx_data_good : for i in 0 to 11 generate process(mgt_rxwordclk_s) begin if(mgt_rxwordclk_s(i)'event and mgt_rxwordclk_s(i) = '1')then if(GBT_RXCLKEn_i(i) = '1')then if(GBT_ERRORDETECTED(i) = '1')then if(rx_data_good_cntr(i)(4) = '0')then rx_data_good(i) <= '0'; end if; rx_data_good_cntr(i) <= (others => '0'); elsif(rx_data_good_cntr(i)(4) = '0')then rx_data_good_cntr(i) <= rx_data_good_cntr(i) +1; else rx_data_good(i) <= '1'; end if; end if; end if; end process; end generate; mgt_inst: entity work.mgtx12 generic map(BLK_No => BLK_No) port map ( MGT_RESET => MGT_RESET_i, MGT_RXRESET => MGT_RXRESET_i, gtrefclk => gtrefclk, DRPclk => DRPclk, tx_wordclk => tx_wordclk, mgt_en => mgt_en, loopback => loopback, rx_data_good => rx_data_good, rxn => rxn, rxp => rxp, txn => txn, txp => txp, tx_data => mgt_txword_s, rx_data => mgt_rxword_s, rx_wordclk => mgt_rxwordclk_s, HPTD_reset => HPTD_reset_i, mgt_reset_tx_done => mgt_reset_tx_done_o, MGT_TXREADY => MGT_TXREADY_o, MGT_RXREADY => MGT_RXREADY_o, RX_HEADERFLAG_o => mgt_headerflag_s, cpll_locked => cpll_locked); --==================================== User Logic =====================================-- --! Multi instantiation of the GBT Tx datapath (Srambler and Encoder) for each link of the bank gbt_txdatapath_multilink_gen: for i in 0 to 11 generate gbt_txdatapath_inst: entity work.gbt_tx generic map ( TX_ENCODING => TX_ENCODING ) port map ( TX_RESET_I => GBT_TXRESET_i(i), TX_WORDCLK_I => tx_wordclk, TX_CLKEN_i => GBT_TXCLKEn_i, TX_ENCODING_SEL_i => TX_ENCODING_SEL_i(i), TX_ISDATA_SEL_I => GBT_ISDATAFLAG_i(i), TX_DATA_I => GBT_TXDATA_i(i), TX_EXTRA_DATA_WIDEBUS_I => WB_TXDATA_i(i), TX_FRAME_o => gbt_txencdata_s(i) ); end generate; --! Multi instantiation of the GBT Tx gearbox (from GBT word [120bit] to MGT words [20/40bit]) for each link of the bank gbt_txgearbox_multilink_gen: for i in 0 to 11 generate gbt_txgearbox_inst: entity work.gbt_tx_gearbox port map ( TX_RESET_I => GBT_TXRESET_i(i), TX_WORDCLK_I => tx_wordclk, TX_CLKEN_i => GBT_TXCLKEn_i, TX_PHALIGNED_o => TX_PHALIGNED_o(i), TX_PHCOMPUTED_o => TX_PHCOMPUTED_o(i), TX_FRAME_I => gbt_txencdata_s(i), TX_WORD_O => mgt_txword_s(i) ); end generate; MGT_HEADERFLAG_o <= mgt_headerflag_s; -- MGT_TXWORDCLK_o <= mgt_txwordclk_s; MGT_RXWORDCLK_o <= mgt_rxwordclk_s; --! Multi instantiation of the GBT Rx gearbox (from MGT word [20/40bit] to GBT word [120bit]) for each link of the bank gbt_rxgearbox_multilink_gen: for i in 0 to 11 generate gbt_rxgearbox_inst: entity work.gbt_rx_gearbox generic map ( RX_OPTIMIZATION => RX_OPTIMIZATION ) port map ( RX_RESET_I => GBT_RXRESET_i(i), RX_WORDCLK_I => mgt_rxwordclk_s(i), RX_HEADERFLAG_i => mgt_headerflag_s(i), READY_O => gbt_rxgearboxready_s(i), RX_WORD_I => mgt_rxword_s(i), RX_FRAME_O => gbt_rxencdata_s(i) ); end generate; --! Multi instantiation of the GBT Rx datapath (Decoder and Descrambler) for each link of the bank gbt_rx_reset <= not gbt_rxgearboxready_s; gbt_rxdatapath_multilink_gen: for i in 0 to 11 generate gbt_rxdatapath_inst: entity work.gbt_rx generic map ( RX_ENCODING => RX_ENCODING ) port map ( RX_RESET_I => gbt_rx_reset(i), RX_FRAMECLK_I => mgt_rxwordclk_s(i), RX_CLKEN_i => GBT_RXCLKEn_i(i), RX_ENCODING_SEL_i => RX_ENCODING_SEL_i(i), RX_READY_O => GBT_RXREADY_o(i), RX_ISDATA_FLAG_O => GBT_ISDATAFLAG_o(i), RX_ERROR_DETECTED => GBT_ERRORDETECTED(i), RX_BIT_MODIFIED_FLAG => GBT_ERRORFLAG_o(i), GBT_RXFRAME_i => gbt_rxencdata_s(i), RX_DATA_O => GBT_RXDATA_o(i), RX_EXTRA_DATA_WIDEBUS_O => WB_RXDATA_o(i) ); end generate; --=====================================================================================-- end structural; --=================================================================================================-- --#################################################################################################-- --=================================================================================================--