---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 02/19/2021 10:37:57 AM -- Design Name: -- Module Name: rst_cntr_ROM - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. Library xpm; use xpm.vcomponents.all; library UNISIM; use UNISIM.VComponents.all; entity cntr_rst_ctrl is Port ( clk : in STD_LOGIC; clk_phase : in STD_LOGIC_VECTOR (7 downto 0); ipb_rst : in std_logic; addr : in unsigned(8 downto 0); reset_ctrl : in STD_LOGIC_VECTOR (31 downto 0); ram_rsta_cntr : out STD_LOGIC; rst_cntr : out STD_LOGIC_VECTOR (511 downto 0)); end cntr_rst_ctrl; architecture Behavioral of cntr_rst_ctrl is signal wraparound : std_logic; signal SR : std_logic_vector(47 downto 0) := (others => '0'); signal rst_cycle : std_logic := '0'; signal ipb_rst_cycle : std_logic := '0'; signal start_addr : unsigned(8 downto 0); signal addr_p : unsigned(9 downto 0) := (others => '0'); signal reset_addr_p : unsigned(9 downto 0); signal addr_match : std_logic := '0'; signal SFP_match : std_logic := '0'; signal group_match : std_logic := '0'; signal reset_type : std_logic_vector(1 downto 0); signal reset_addr : unsigned(8 downto 0); signal rst_p : std_logic_vector(10 downto 0); type array6X32 is array(0 to 5) of bit_vector(31 downto 0); constant INIT_addr_p : array6X32 := (x"92492492", x"24924924", x"38e38e38", x"c0fc0fc0", x"00fff000", x"ff000000"); type array11X48 is array(0 to 10) of std_logic_vector(47 downto 0); signal P : array11X48 := (others => (others => '0')); signal C : array11X48 := (others => (others => '0')); begin g_rst_cntr: for i in 0 to 9 generate rst_cntr(48*i+47 downto 48*i) <= P(i); end generate; rst_cntr(511 downto 480) <= P(10)(31 downto 0); process(clk) begin if(clk'event and clk = '1')then if(rst_cycle = '1' and addr_p = reset_addr_p)then addr_match <= '1'; else addr_match <= '0'; end if; if(addr_p(5 downto 0) = reset_addr_p(5 downto 0) and (reset_addr_p(9) = '0' or reset_addr_p(7 downto 6) = "00"))then SFP_match <= '1'; else SFP_match <= '0'; end if; if(addr_p(9 downto 6) = reset_addr_p(3 downto 0))then group_match <= '1'; else group_match <= '0'; end if; end if; end process; process(clk, ipb_rst) begin if(ipb_rst = '1')then rst_cycle <= '1'; ipb_rst_cycle <= '1'; reset_type <= (others => '0'); reset_addr <= (others => '0'); start_addr <= (others => '0'); ram_rsta_cntr <= '1'; rst_p <= (others => '0'); elsif(clk'event and clk = '1')then if(clk_phase(7) = '1')then if(rst_cycle = '1')then if(addr = start_addr)then ipb_rst_cycle <= '0'; rst_cycle <= ipb_rst_cycle; end if; elsif(reset_ctrl(31) = '1')then rst_cycle <= '1'; reset_type <= reset_ctrl(30 downto 29); reset_addr <= unsigned(reset_ctrl(8 downto 0)); start_addr <= addr; end if; end if; for i in 0 to 10 loop if(i = to_integer(addr_p(9 downto 6)) and rst_cycle = '1' and clk_phase(3) = '1')then rst_p(i) <= '0'; else rst_p(i) <= '1'; end if; end loop; if(clk_phase(7) = '1')then case reset_type is when "00" => ram_rsta_cntr <= rst_cycle; when "01" => if(rst_cycle = '1' and addr_match = '1')then ram_rsta_cntr <= '1'; else ram_rsta_cntr <= '0'; end if; when "10" => if(rst_cycle = '1' and SFP_match = '1')then ram_rsta_cntr <= '1'; else ram_rsta_cntr <= '0'; end if; when others => if(rst_cycle = '1' and group_match = '1')then ram_rsta_cntr <= '1'; else ram_rsta_cntr <= '0'; end if; end case; end if; end if; end process; g_addr_p : for i in 0 to 5 generate i_addr_p : LUT5 generic map ( INIT => INIT_addr_p(i) -- Logic function ) port map ( O => addr_p(i+4), -- 1-bit output: LUT I0 => addr(4), -- 1-bit input: LUT I1 => addr(5), -- 1-bit input: LUT I2 => addr(6), -- 1-bit input: LUT I3 => addr(7), -- 1-bit input: LUT I4 => addr(8) -- 1-bit input: LUT ); i_reset_addr_p : LUT5 generic map ( INIT => INIT_addr_p(i) -- Logic function ) port map ( O => reset_addr_p(i+4), -- 1-bit output: LUT I0 => reset_addr(4), -- 1-bit input: LUT I1 => reset_addr(5), -- 1-bit input: LUT I2 => reset_addr(6), -- 1-bit input: LUT I3 => reset_addr(7), -- 1-bit input: LUT I4 => reset_addr(8) -- 1-bit input: LUT ); end generate g_addr_p; addr_p(3 downto 0) <= addr(3 downto 0); reset_addr_p(3 downto 0) <= reset_addr(3 downto 0); i_wraparound : LUT5 generic map ( INIT => X"a4924924" -- Logic function ) port map ( O => wraparound, -- 1-bit output: LUT I0 => addr(4), -- 1-bit input: LUT I1 => addr(5), -- 1-bit input: LUT I2 => addr(6), -- 1-bit input: LUT I3 => addr(7), -- 1-bit input: LUT I4 => addr(8) -- 1-bit input: LUT ); process(clk) begin if(clk'event and clk = '1')then if(clk_phase(7) = '1')then if(addr(3 downto 0) = x"f" and wraparound = '1')then SR(0) <= '1'; SR(32) <= '0'; else SR(0) <= '0'; SR(32) <= SR(31); end if; SR(47 downto 33) <= SR(46 downto 32); SR(31 downto 1) <= SR(30 downto 0); end if; end if; end process; process(clk) begin if(clk'event and clk = '1')then end if; end process; --process(clk) --begin -- if(clk'event and clk = '1')then -- for i in 0 to 9 loop -- rst_cntr(48*i+47 downto 48*i) <= P(i); -- end loop; -- rst_cntr(511 downto 480) <= P(10)(31 downto 0); -- end if; --end process; process(clk) begin if(clk'event and clk = '1')then for i in 0 to 10 loop case reset_type is when "00" => C(i) <= (others => '1'); when "01" => if(addr_match = '1')then C(i) <= (others => '1'); else C(i) <= (others => '0'); end if; when "10" => if(SFP_match = '1')then C(i) <= (others => '1'); else C(i) <= (others => '0'); end if; when others => if(group_match = '1')then C(i) <= (others => '1'); else C(i) <= (others => '0'); end if; end case; end loop; end if; end process; g_DSP : for i in 0 to 10 generate DSP48E2_inst : DSP48E2 generic map ( -- Feature Control Attributes: Data Path Selection AMULTSEL => "A", -- Selects A input to multiplier (A, AD) A_INPUT => "DIRECT", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port) BMULTSEL => "B", -- Selects B input to multiplier (AD, B) B_INPUT => "DIRECT", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port) PREADDINSEL => "A", -- Selects input to pre-adder (A, B) RND => X"000000000000", -- Rounding Constant USE_MULT => "MULTIPLY", -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) USE_SIMD => "ONE48", -- SIMD selection (FOUR12, ONE48, TWO24) USE_WIDEXOR => "FALSE", -- Use the Wide XOR function (FALSE, TRUE) XORSIMD => "XOR24_48_96", -- Mode of operation for the Wide XOR (XOR12, XOR24_48_96) -- Pattern Detector Attributes: Pattern Detection Configuration AUTORESET_PATDET => "NO_RESET", -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH AUTORESET_PRIORITY => "RESET", -- Priority of AUTORESET vs. CEP (CEP, RESET). MASK => X"3fffffffffff", -- 48-bit mask value for pattern detect (1=ignore) PATTERN => X"000000000000", -- 48-bit pattern match for pattern detect SEL_MASK => "MASK", -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2 SEL_PATTERN => "PATTERN", -- Select pattern value (C, PATTERN) USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect (NO_PATDET, PATDET) -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins IS_ALUMODE_INVERTED => "0000", -- Optional inversion for ALUMODE IS_CARRYIN_INVERTED => '0', -- Optional inversion for CARRYIN IS_CLK_INVERTED => '0', -- Optional inversion for CLK IS_INMODE_INVERTED => "00000", -- Optional inversion for INMODE IS_OPMODE_INVERTED => "000000000", -- Optional inversion for OPMODE IS_RSTALLCARRYIN_INVERTED => '0', -- Optional inversion for RSTALLCARRYIN IS_RSTALUMODE_INVERTED => '0', -- Optional inversion for RSTALUMODE IS_RSTA_INVERTED => '0', -- Optional inversion for RSTA IS_RSTB_INVERTED => '0', -- Optional inversion for RSTB IS_RSTCTRL_INVERTED => '0', -- Optional inversion for RSTCTRL IS_RSTC_INVERTED => '0', -- Optional inversion for RSTC IS_RSTD_INVERTED => '0', -- Optional inversion for RSTD IS_RSTINMODE_INVERTED => '0', -- Optional inversion for RSTINMODE IS_RSTM_INVERTED => '0', -- Optional inversion for RSTM IS_RSTP_INVERTED => '0', -- Optional inversion for RSTP -- Register Control Attributes: Pipeline Register Configuration ACASCREG => 1, -- Number of pipeline stages between A/ACIN and ACOUT (0-2) ADREG => 1, -- Pipeline stages for pre-adder (0-1) ALUMODEREG => 1, -- Pipeline stages for ALUMODE (0-1) AREG => 1, -- Pipeline stages for A (0-2) BCASCREG => 1, -- Number of pipeline stages between B/BCIN and BCOUT (0-2) BREG => 1, -- Pipeline stages for B (0-2) CARRYINREG => 1, -- Pipeline stages for CARRYIN (0-1) CARRYINSELREG => 1, -- Pipeline stages for CARRYINSEL (0-1) CREG => 1, -- Pipeline stages for C (0-1) DREG => 1, -- Pipeline stages for D (0-1) INMODEREG => 1, -- Pipeline stages for INMODE (0-1) MREG => 1, -- Multiplier pipeline stages (0-1) OPMODEREG => 1, -- Pipeline stages for OPMODE (0-1) PREG => 1 -- Number of pipeline stages for P (0-1) ) port map ( -- Data outputs: Data Ports P => P(i), -- 48-bit output: Primary data -- Cascade inputs: Cascade Ports ACIN => (others => '0'), -- 30-bit input: A cascade data BCIN => (others => '0'), -- 18-bit input: B cascade CARRYCASCIN => '0', -- 1-bit input: Cascade carry MULTSIGNIN => '0', -- 1-bit input: Multiplier sign cascade PCIN => (others => '0'), -- 48-bit input: P cascade -- Control inputs: Control Inputs/Status Bits ALUMODE => "1100", -- 4-bit input: ALU control, X and Z CARRYINSEL => "000", -- 3-bit input: Carry select CLK => clk, -- 1-bit input: Clock INMODE => "00000", -- 5-bit input: INMODE control OPMODE => "000110011", -- 9-bit input: Operation mode W=0, Z=0, Y=C, X=A:B, CIN=0 => P=(A:B) + C -- Data inputs: Data Ports A => SR(47 downto 18), -- 30-bit input: A data B => SR(17 downto 0), -- 18-bit input: B data C => C(i), -- 48-bit input: C data CARRYIN => '0', -- 1-bit input: Carry-in D => (others => '1'), -- 27-bit input: D data -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs CEA1 => '1', -- 1-bit input: Clock enable for 1st stage AREG CEA2 => '1', -- 1-bit input: Clock enable for 2nd stage AREG CEAD => '0', -- 1-bit input: Clock enable for ADREG CEALUMODE => '1', -- 1-bit input: Clock enable for ALUMODE CEB1 => '1', -- 1-bit input: Clock enable for 1st stage BREG CEB2 => '1', -- 1-bit input: Clock enable for 2nd stage BREG CEC => '1', -- 1-bit input: Clock enable for CREG CECARRYIN => '1', -- 1-bit input: Clock enable for CARRYINREG CECTRL => '1', -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG CED => '0', -- 1-bit input: Clock enable for DREG CEINMODE => '1', -- 1-bit input: Clock enable for INMODEREG CEM => '0', -- 1-bit input: Clock enable for MREG CEP => '1', -- 1-bit input: Clock enable for PREG RSTA => '0', -- 1-bit input: Reset for AREG RSTALLCARRYIN => '0', -- 1-bit input: Reset for CARRYINREG RSTALUMODE => '0', -- 1-bit input: Reset for ALUMODEREG RSTB => '0', -- 1-bit input: Reset for BREG RSTC => '0', -- 1-bit input: Reset for CREG RSTCTRL => '0', -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG RSTD => '0', -- 1-bit input: Reset for DREG and ADREG RSTINMODE => '0', -- 1-bit input: Reset for INMODEREG RSTM => '0', -- 1-bit input: Reset for MREG RSTP => rst_p(i) -- 1-bit input: Reset for PREG ); end generate g_DSP; end Behavioral;