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-- Company: 
-- Engineer: 
-- 
-- Create Date: 03/28/2019 02:20:23 PM
-- Design Name: 
-- Module Name: axi_chip2chip_slave - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use IEEE.std_logic_misc.all;
use work.ngFEC_pack.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity axi_chip2chip_slave is
    Port (
		aclk : in std_logic;
		aresetn : in std_logic;
		axi_in : in axi_rbus;
		axi_out : out axi_wbus;
    axi_c2c_s2m_intr_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    axi_c2c_m2s_intr_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    slave_status : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
    refclk1_in : IN STD_LOGIC;
    DRP_clk : IN STD_LOGIC;
    c2c_calib_done : OUT STD_LOGIC;
    txp : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    txn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    rxp : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    rxn : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
    );
end axi_chip2chip_slave;

architecture Behavioral of axi_chip2chip_slave is
COMPONENT axi_chip2chip_64B66B
  PORT (
    m_aclk : IN STD_LOGIC;
    m_aresetn : IN STD_LOGIC;
    m_axi_awid : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
    m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
    m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
    m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
    m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
    m_axi_awvalid : OUT STD_LOGIC;
    m_axi_awready : IN STD_LOGIC;
    m_axi_wuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
    m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    m_axi_wlast : OUT STD_LOGIC;
    m_axi_wvalid : OUT STD_LOGIC;
    m_axi_wready : IN STD_LOGIC;
    m_axi_bid : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
    m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
    m_axi_bvalid : IN STD_LOGIC;
    m_axi_bready : OUT STD_LOGIC;
    m_axi_arid : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
    m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
    m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
    m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
    m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
    m_axi_arvalid : OUT STD_LOGIC;
    m_axi_arready : IN STD_LOGIC;
    m_axi_rid : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
    m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
    m_axi_rlast : IN STD_LOGIC;
    m_axi_rvalid : IN STD_LOGIC;
    m_axi_rready : OUT STD_LOGIC;
    axi_c2c_s2m_intr_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    axi_c2c_m2s_intr_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    axi_c2c_phy_clk : IN STD_LOGIC;
    axi_c2c_aurora_channel_up : IN STD_LOGIC;
    axi_c2c_aurora_tx_tready : IN STD_LOGIC;
    axi_c2c_aurora_tx_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
    axi_c2c_aurora_tx_tvalid : OUT STD_LOGIC;
    axi_c2c_aurora_rx_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
    axi_c2c_aurora_rx_tvalid : IN STD_LOGIC;
    aurora_do_cc : OUT STD_LOGIC;
    aurora_pma_init_in : IN STD_LOGIC;
    aurora_init_clk : IN STD_LOGIC;
    aurora_pma_init_out : OUT STD_LOGIC;
    aurora_mmcm_not_locked : IN STD_LOGIC;
    aurora_reset_pb : OUT STD_LOGIC;
    axi_c2c_config_error_out : OUT STD_LOGIC;
    axi_c2c_link_status_out : OUT STD_LOGIC;
    axi_c2c_multi_bit_error_out : OUT STD_LOGIC
  );
END COMPONENT;
COMPONENT aurora_64b66b_0
  PORT (
    rxp : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    rxn : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    refclk1_in : IN STD_LOGIC;
    reset_pb : IN STD_LOGIC;
    power_down : IN STD_LOGIC;
    pma_init : IN STD_LOGIC;
    loopback : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
    txp : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    txn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    hard_err : OUT STD_LOGIC;
    soft_err : OUT STD_LOGIC;
    channel_up : OUT STD_LOGIC;
    lane_up : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
    tx_out_clk : OUT STD_LOGIC;
    gt_pll_lock : OUT STD_LOGIC;
    s_axi_tx_tdata : IN STD_LOGIC_VECTOR(0 TO 63);
    s_axi_tx_tvalid : IN STD_LOGIC;
    s_axi_tx_tready : OUT STD_LOGIC;
    m_axi_rx_tdata : OUT STD_LOGIC_VECTOR(0 TO 63);
    m_axi_rx_tvalid : OUT STD_LOGIC;
    mmcm_not_locked_out : OUT STD_LOGIC;
    gt0_drpaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
    gt0_drpdi : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
    gt0_drprdy : OUT STD_LOGIC;
    gt0_drpwe : IN STD_LOGIC;
    gt0_drpen : IN STD_LOGIC;
    gt0_drpdo : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
    init_clk : IN STD_LOGIC;
    link_reset_out : OUT STD_LOGIC;
    user_clk_out : OUT STD_LOGIC;
    sync_clk_out : OUT STD_LOGIC;
    gt_rxcdrovrden_in : IN STD_LOGIC;
    sys_reset_out : OUT STD_LOGIC;
    gt_reset_out : OUT STD_LOGIC;
    gt_powergood : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
  );
END COMPONENT;
signal resetn_sync : std_logic_vector(3 downto 0);
signal pma_init : STD_LOGIC;
signal rst_cntr : unsigned(4 downto 0);
signal channel_up : STD_LOGIC;
signal axi_c2c_aurora_tx_tready : STD_LOGIC;
signal axi_c2c_aurora_tx_tdata : STD_LOGIC_VECTOR(63 DOWNTO 0);
signal axi_c2c_aurora_tx_tdata_inv : STD_LOGIC_VECTOR(0 TO 63);
signal axi_c2c_aurora_tx_tvalid : STD_LOGIC;
signal axi_c2c_aurora_rx_tdata : STD_LOGIC_VECTOR(63 DOWNTO 0);
signal axi_c2c_aurora_rx_tdata_inv : STD_LOGIC_VECTOR(0 TO 63);
signal axi_c2c_aurora_rx_tvalid : STD_LOGIC;
--signal tx_lock : STD_LOGIC;
signal tx_out_clk : STD_LOGIC;
signal user_clk : STD_LOGIC;
signal sync_clk : STD_LOGIC;
signal pll_not_locked : STD_LOGIC;
signal system_reset : STD_LOGIC;
signal aurora_reset_pb : STD_LOGIC;
signal aurora_pma_init_out : STD_LOGIC;
--signal tx_resetdone : std_logic;
--signal rx_resetdone : std_logic;
signal soft_err : std_logic;
signal hard_err : std_logic;
signal t_axi_calib_done : std_logic;
signal t_axi_calib_error : std_logic;
signal axi_c2c_config_error : std_logic;

begin
c2c_calib_done <= t_axi_calib_done;
process(aclk, aresetn)
begin
	if(aresetn = '0')then
		resetn_sync <= x"0";
		rst_cntr <= "10000";
	elsif(aclk'event and aclk = '1')then
		resetn_sync <= resetn_sync(2 downto 0) & '1';
		if(rst_cntr(4) = '1')then
			rst_cntr <= rst_cntr + 1;
		end if;
	end if;
end process;
pma_init <= rst_cntr(4);
i_axi_chip2chip : axi_chip2chip_64B66B
  PORT MAP (
    m_aclk => aclk,
    m_aresetn => resetn_sync(3),
    m_axi_awid => axi_out.axi_awid,
    m_axi_awaddr => axi_out.axi_awaddr,
    m_axi_awlen => axi_out.axi_awlen,
    m_axi_awsize => axi_out.axi_awsize,
    m_axi_awburst => axi_out.axi_awburst,
    m_axi_awvalid => axi_out.axi_awvalid,
    m_axi_awready => axi_in.axi_awready,
    m_axi_wuser => open,
    m_axi_wdata => axi_out.axi_wdata,
    m_axi_wstrb => axi_out.axi_wstrb,
    m_axi_wlast => axi_out.axi_wlast,
    m_axi_wvalid => axi_out.axi_wvalid,
    m_axi_wready => axi_in.axi_wready,
    m_axi_bid => axi_in.axi_bid,
    m_axi_bresp => axi_in.axi_bresp,
    m_axi_bvalid => axi_in.axi_bvalid,
    m_axi_bready => axi_out.axi_bready,
    m_axi_arid => axi_out.axi_arid,
    m_axi_araddr => axi_out.axi_araddr,
    m_axi_arlen => axi_out.axi_arlen,
    m_axi_arsize => axi_out.axi_arsize,
    m_axi_arburst => axi_out.axi_arburst,
    m_axi_arvalid => axi_out.axi_arvalid,
    m_axi_arready => axi_in.axi_arready,
    m_axi_rid => axi_in.axi_rid,
    m_axi_rdata => axi_in.axi_rdata,
    m_axi_rresp => axi_in.axi_rresp,
    m_axi_rlast => axi_in.axi_rlast,
    m_axi_rvalid => axi_in.axi_rvalid,
    m_axi_rready => axi_out.axi_rready,
    axi_c2c_s2m_intr_in => axi_c2c_s2m_intr_in,
    axi_c2c_m2s_intr_out => axi_c2c_m2s_intr_out,
    axi_c2c_phy_clk => user_clk,
    axi_c2c_aurora_channel_up => channel_up,
    axi_c2c_aurora_tx_tready => axi_c2c_aurora_tx_tready,
    axi_c2c_aurora_tx_tdata => axi_c2c_aurora_tx_tdata,
    axi_c2c_aurora_tx_tvalid => axi_c2c_aurora_tx_tvalid,
    axi_c2c_aurora_rx_tdata => axi_c2c_aurora_rx_tdata,
    axi_c2c_aurora_rx_tvalid => axi_c2c_aurora_rx_tvalid,
    aurora_do_cc => open,
    aurora_pma_init_in => pma_init,
    aurora_init_clk => DRP_clk,
    aurora_pma_init_out => aurora_pma_init_out,
    aurora_mmcm_not_locked => pll_not_locked,
    aurora_reset_pb => aurora_reset_pb,
    axi_c2c_config_error_out => axi_c2c_config_error,
    axi_c2c_link_status_out => t_axi_calib_done,
    axi_c2c_multi_bit_error_out => t_axi_calib_error
  );
slave_status(0) <= channel_up;
--slave_status(1) <= rx_resetdone;
--slave_status(2) <= tx_resetdone;
slave_status(3) <= t_axi_calib_done;
slave_status(4) <= '0';
slave_status(5) <= soft_err;
slave_status(6) <= hard_err;
slave_status(7) <= t_axi_calib_error;
slave_status(8) <= axi_c2c_config_error;
slave_status(9) <= not aresetn;
slave_status(31 downto 10) <= (others => '0');
g_inv_tdata : for i in 0 to 63 generate
	axi_c2c_aurora_tx_tdata_inv(i) <= axi_c2c_aurora_tx_tdata(i);
	axi_c2c_aurora_rx_tdata(i) <= axi_c2c_aurora_rx_tdata_inv(i);
end generate;
i_aurora : aurora_64b66b_0
  PORT MAP (
    rxp => rxp,
    rxn => rxn,
    refclk1_in => refclk1_in,
    reset_pb => aurora_reset_pb,
    power_down => '0',
    pma_init => aurora_pma_init_out,
    loopback => "000",
    txp => txp,
    txn => txn,
    hard_err => hard_err,
    soft_err => soft_err,
    channel_up => channel_up,
    lane_up => open,
    tx_out_clk => tx_out_clk,
    gt_pll_lock => open,
    s_axi_tx_tdata => axi_c2c_aurora_tx_tdata_inv,
    s_axi_tx_tvalid => axi_c2c_aurora_tx_tvalid,
    s_axi_tx_tready => axi_c2c_aurora_tx_tready,
    m_axi_rx_tdata => axi_c2c_aurora_rx_tdata_inv,
    m_axi_rx_tvalid => axi_c2c_aurora_rx_tvalid,
    mmcm_not_locked_out => pll_not_locked,
    gt0_drpaddr => (others => '0'),
    gt0_drpdi => (others => '0'),
    gt0_drprdy => open,
    gt0_drpwe => '0',
    gt0_drpen => '0',
    gt0_drpdo => open,
    init_clk => DRP_clk,
    link_reset_out => open,
    user_clk_out => user_clk,
    sync_clk_out => sync_clk,
    gt_rxcdrovrden_in => '0',
    sys_reset_out => open,
    gt_reset_out => open,
    gt_powergood => open
  );
end Behavioral;