---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 12/22/2020 09:41:33 AM -- Design Name: -- Module Name: ttc_mgt_wrapper - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. library UNISIM; use UNISIM.VComponents.all; use work.ngFEC_pack.all; entity ttc_mgt_wrapper is generic (SIM : boolean := false); Port ( reset : in STD_LOGIC; rstoneven : in STD_LOGIC; clk125 : in STD_LOGIC; txrefclk_lock : in STD_LOGIC; txrefclk_in : in STD_LOGIC; rxrefclk_in : in STD_LOGIC; rx_data_good : in STD_LOGIC; rxslide : in STD_LOGIC; loopback_in : in std_logic_vector(2 downto 0); Si_IN_SEL1 : in STD_LOGIC; rx_p : in STD_LOGIC; rx_n : in STD_LOGIC; tx_p : out STD_LOGIC; tx_n : out STD_LOGIC; txusrclk_out : out STD_LOGIC; rxusrclk_out : out STD_LOGIC; tx_rdy : out STD_LOGIC; rx_rdy : out STD_LOGIC; mgt_rdy : out STD_LOGIC; refclkp_out : out STD_LOGIC; refclkn_out : out STD_LOGIC; ttc2_stat : out std_logic_vector(15 downto 0); mgt_txdata : in STD_LOGIC_VECTOR (31 downto 0); mgt_rxdata : out STD_LOGIC_VECTOR (31 downto 0)); end ttc_mgt_wrapper; architecture Behavioral of ttc_mgt_wrapper is COMPONENT ttc_mgt_example_init generic (SIM : boolean := false); PORT ( clk_freerun_in : in std_logic; reset_all_in : in std_logic; Si_IN_SEL1 : in std_logic; tx_init_done_in : in std_logic; rx_init_done_in : in std_logic; rx_data_good_in : in std_logic; reset_all_out : out std_logic; reset_rx_out : out std_logic; reset_tx_out : out std_logic; init_done_out : out std_logic; retry_ctr_out : out std_logic_vector(3 downto 0) ); end component; COMPONENT ttc_mgt_example_gtwiz_reset PORT ( gtwiz_reset_clk_freerun_in : IN STD_LOGIC; gtwiz_reset_all_in : IN STD_LOGIC; gtwiz_reset_tx_pll_and_datapath_in : IN STD_LOGIC; gtwiz_reset_tx_datapath_in : IN STD_LOGIC; gtwiz_reset_rx_pll_and_datapath_in : IN STD_LOGIC; gtwiz_reset_rx_datapath_in : IN STD_LOGIC; gtwiz_reset_rx_cdr_stable_out : OUT STD_LOGIC; gtwiz_reset_tx_done_out : OUT STD_LOGIC; gtwiz_reset_rx_done_out : OUT STD_LOGIC; gtwiz_reset_userclk_tx_active_in : IN STD_LOGIC; gtwiz_reset_userclk_rx_active_in : IN STD_LOGIC; gtpowergood_in : IN STD_LOGIC; txusrclk2_in : IN STD_LOGIC; plllock_tx_in : IN STD_LOGIC; txresetdone_in : IN STD_LOGIC; rxusrclk2_in : IN STD_LOGIC; plllock_rx_in : IN STD_LOGIC; rxcdrlock_in : IN STD_LOGIC; rxresetdone_in : IN STD_LOGIC; pllreset_tx_out : OUT STD_LOGIC; txprogdivreset_out : OUT STD_LOGIC; gttxreset_out : OUT STD_LOGIC; txuserrdy_out : OUT STD_LOGIC; pllreset_rx_out : OUT STD_LOGIC; rxprogdivreset_out : OUT STD_LOGIC; gtrxreset_out : OUT STD_LOGIC; rxuserrdy_out : OUT STD_LOGIC; tx_enabled_tie_in : IN STD_LOGIC; rx_enabled_tie_in : IN STD_LOGIC; shared_pll_tie_in : IN STD_LOGIC ); END COMPONENT; COMPONENT ttc_mgt PORT ( gtwiz_userclk_tx_active_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); gtwiz_userclk_rx_active_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); gtwiz_buffbypass_rx_reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); gtwiz_buffbypass_rx_start_user_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); gtwiz_buffbypass_rx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gtwiz_buffbypass_rx_error_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gtwiz_reset_tx_done_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); gtwiz_reset_rx_done_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); gtwiz_userdata_tx_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0); gtwiz_userdata_rx_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); gtrefclk00_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); gtrefclk01_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); gtsouthrefclk00_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); gtsouthrefclk01_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); gtsouthrefclk10_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); gtsouthrefclk11_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); qpll0refclksel_in : IN STD_LOGIC_VECTOR(2 DOWNTO 0); qpll0reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); qpll1refclksel_in : IN STD_LOGIC_VECTOR(2 DOWNTO 0); qpll1reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); qpll0lock_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); qpll0outclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); qpll0outrefclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); qpll1lock_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); qpll1outclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); qpll1outrefclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gthrxn_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); gthrxp_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); gtrxreset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); gttxreset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); loopback_in : IN STD_LOGIC_VECTOR(2 DOWNTO 0); rxpolarity_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); rxprogdivreset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); rxslide_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); rxuserrdy_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); rxusrclk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); rxusrclk2_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); txpolarity_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); txprogdivreset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); txuserrdy_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); txusrclk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); txusrclk2_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0); gthtxn_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gthtxp_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); gtpowergood_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); rxcdrlock_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); rxoutclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); rxpmaresetdone_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); rxrecclkout_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); rxresetdone_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); txoutclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); txpmaresetdone_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); txresetdone_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) ); END COMPONENT; signal qpll1refclksel : std_logic_vector(2 downto 0) := "000"; signal reset_all : std_logic; signal reset_all_init : std_logic; signal reset_tx_init : std_logic; signal reset_rx_init : std_logic; signal reset_tx_pll_and_datapath : std_logic; signal reset_rx_pll_and_datapath : std_logic; signal reset_tx : std_logic; signal tx_active : std_logic; signal txoutclk : std_logic; signal txusrclk : std_logic; signal txusrclk_reset : std_logic; signal reset_tx_done : std_logic; signal txpmaresetdone : std_logic; signal rxpmaresetdone : std_logic; signal rxusrclk_reset : std_logic; signal buffbypass_rx_done : std_logic; signal buffbypass_rx_error : std_logic; signal reset_rx_done : std_logic; signal rx_active : std_logic; signal rx_active_n : std_logic; signal rxoutclk : std_logic; signal rxrecclkout : std_logic; signal rxusrclk : std_logic; signal rx_init_done : std_logic; signal mgt_init_done : std_logic; signal buffbypass_rx_reset : std_logic; signal qpll0lock : std_logic; signal qpll1lock : std_logic; signal qpll0reset : std_logic; signal qpll1reset : std_logic; signal gtpowergood : std_logic; signal gtrxreset : std_logic; signal gttxreset : std_logic; signal tx_enabled_tie_in : std_logic; signal rxprogdivreset : std_logic; signal rxuserrdy : std_logic; signal txprogdivreset : std_logic; signal txuserrdy : std_logic; signal rxcdrlock : std_logic; signal rxresetdone : std_logic; signal txresetdone : std_logic; signal rxresetdone_sync : std_logic; signal txresetdone_sync : std_logic; begin txusrclk_out <= txusrclk; rxusrclk_out <= rxusrclk; tx_rdy <= reset_tx_done; rx_rdy <= rx_init_done; mgt_rdy <= mgt_init_done; i_rxrecclk : OBUFDS_GTE3 generic map( REFCLK_EN_TX_PATH => '1', REFCLK_ICNTL_TX => "00111") port map ( O => refclkp_out, OB => refclkn_out, CEB => '0', I => rxrecclkout ); i_txusrclk : entity work.ttc_mgt_example_gtwiz_userclk_tx port map( gtwiz_userclk_tx_srcclk_in => txoutclk, gtwiz_userclk_tx_reset_in => txusrclk_reset, gtwiz_userclk_tx_usrclk_out => txusrclk, gtwiz_userclk_tx_usrclk2_out => open, gtwiz_userclk_tx_active_out => tx_active ); rxusrclk_reset <= not rxpmaresetdone; txusrclk_reset <= not txpmaresetdone; i_rxusrclk : entity work.ttc_mgt_example_gtwiz_userclk_rx port map( gtwiz_userclk_rx_srcclk_in => rxoutclk, gtwiz_userclk_rx_reset_in => rxusrclk_reset, gtwiz_userclk_rx_usrclk_out => rxusrclk, gtwiz_userclk_rx_usrclk2_out => open, gtwiz_userclk_rx_active_out => rx_active ); reset_all <= reset or reset_all_init; rx_init_done <= reset_rx_done and buffbypass_rx_done; i_mgt_init : ttc_mgt_example_init generic map (SIM => SIM) port map( clk_freerun_in => clk125, reset_all_in => reset_all, Si_IN_SEL1 => Si_IN_SEL1, tx_init_done_in => reset_tx_done, rx_init_done_in => rx_init_done, rx_data_good_in => rx_data_good, reset_all_out => reset_all_init, reset_rx_out => reset_rx_init, reset_tx_out => reset_tx_init, init_done_out => mgt_init_done, retry_ctr_out => open ); reset_tx_pll_and_datapath <= '1' when reset_tx_init = '1' or txrefclk_lock = '0' else '0'; rx_active_n <= not rx_active; i_buffbypass_rx_reset : entity work.ttc_mgt_example_reset_synchronizer port map( clk_in => rxusrclk, rst_in => rx_active_n, rst_out => buffbypass_rx_reset ); ttc2_stat(0) <= buffbypass_rx_done; ttc2_stat(1) <= reset_rx_done; ttc2_stat(2) <= reset_tx_done; ttc2_stat(3) <= qpll0lock; ttc2_stat(4) <= qpll1lock; ttc2_stat(5) <= gtpowergood; ttc2_stat(6) <= buffbypass_rx_error; ttc2_stat(15 downto 7) <= (others => '0'); i_rxresetdone_sync : entity work.ttc_mgt_example_bit_synchronizer port map( clk_in => clk125, i_in => rxresetdone, o_out => rxresetdone_sync ); i_txresetdone_sync : entity work.ttc_mgt_example_bit_synchronizer port map( clk_in => clk125, i_in => txresetdone, o_out => txresetdone_sync ); reset_rx_pll_and_datapath <= rstoneven or reset_rx_init; i_reset_sm : ttc_mgt_example_gtwiz_reset port map ( gtwiz_reset_clk_freerun_in => clk125, gtwiz_reset_all_in => reset_all, gtwiz_reset_tx_pll_and_datapath_in => reset_tx_pll_and_datapath, gtwiz_reset_tx_datapath_in => '0', gtwiz_reset_rx_pll_and_datapath_in => reset_rx_pll_and_datapath, gtwiz_reset_rx_datapath_in => '0', gtwiz_reset_rx_cdr_stable_out => open, gtwiz_reset_tx_done_out => reset_tx_done, gtwiz_reset_rx_done_out => reset_rx_done, gtwiz_reset_userclk_tx_active_in => tx_active, gtwiz_reset_userclk_rx_active_in => rx_active, gtpowergood_in => gtpowergood, txusrclk2_in => txusrclk, plllock_tx_in => qpll0lock, txresetdone_in => txresetdone_sync, rxusrclk2_in => rxusrclk, plllock_rx_in => qpll1lock, rxcdrlock_in => rxcdrlock, rxresetdone_in => rxresetdone_sync, pllreset_tx_out => qpll0reset, txprogdivreset_out => txprogdivreset, gttxreset_out => gttxreset, txuserrdy_out => txuserrdy, pllreset_rx_out => qpll1reset, rxprogdivreset_out => rxprogdivreset, gtrxreset_out => gtrxreset, rxuserrdy_out => rxuserrdy, tx_enabled_tie_in => tx_enabled_tie_in, rx_enabled_tie_in => '1', shared_pll_tie_in => '0' ); tx_enabled_tie_in <= not Si_IN_SEL1; i_mgt : ttc_mgt PORT MAP ( gtwiz_userclk_tx_active_in(0) => tx_active, gtwiz_userclk_rx_active_in(0) => rx_active, gtwiz_buffbypass_rx_reset_in(0) => buffbypass_rx_reset, gtwiz_buffbypass_rx_start_user_in(0) => '0', gtwiz_buffbypass_rx_done_out(0) => buffbypass_rx_done, gtwiz_buffbypass_rx_error_out(0) => buffbypass_rx_error, gtwiz_reset_tx_done_in(0) => reset_tx_done, gtwiz_reset_rx_done_in(0) => reset_rx_done, gtwiz_userdata_tx_in => mgt_txdata, gtwiz_userdata_rx_out => mgt_rxdata, gtrefclk00_in(0) => '0', gtrefclk01_in(0) => '0', gtsouthrefclk00_in(0) => '0', gtsouthrefclk10_in(0) => txrefclk_in, gtsouthrefclk01_in(0) => rxrefclk_in, gtsouthrefclk11_in(0) => txrefclk_in, qpll0refclksel_in => "110", qpll1refclksel_in => qpll1refclksel, qpll0reset_in(0) => qpll0reset, qpll1reset_in(0) => qpll1reset, qpll0lock_out(0) => qpll0lock, qpll0outclk_out => open, qpll0outrefclk_out => open, qpll1lock_out(0) => qpll1lock, qpll1outclk_out => open, qpll1outrefclk_out => open, gthrxn_in(0) => rx_n, gthrxp_in(0) => rx_p, gtrxreset_in(0) => gtrxreset, gttxreset_in(0) => gttxreset, loopback_in => loopback_in, rxpolarity_in(0) => ttc_rxpolarity, rxprogdivreset_in(0) => rxprogdivreset, rxslide_in(0) => rxslide, rxuserrdy_in(0) => rxuserrdy, rxusrclk_in(0) => rxusrclk, rxusrclk2_in(0) => rxusrclk, txpolarity_in(0) => ttc_txpolarity, txprogdivreset_in(0) => txprogdivreset, txuserrdy_in(0) => txuserrdy, txusrclk_in(0) => txusrclk, txusrclk2_in(0) => txusrclk, gthtxn_out(0) => tx_n, gthtxp_out(0) => tx_p, gtpowergood_out(0) => gtpowergood, rxcdrlock_out(0) => rxcdrlock, rxoutclk_out(0) => rxoutclk, rxpmaresetdone_out(0) => rxpmaresetdone, rxrecclkout_out(0) => rxrecclkout, rxresetdone_out(0) => rxresetdone, txoutclk_out(0) => txoutclk, txpmaresetdone_out(0) => txpmaresetdone, txresetdone_out(0) => txresetdone ); qpll1refclksel <= "101" when Si_IN_SEL1 = '1' else "110"; end Behavioral;