---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 05/24/2019 12:03:55 PM -- Design Name: -- Module Name: DSP_counter - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. library UNISIM; use UNISIM.VComponents.all; Library xpm; use xpm.vcomponents.all; entity DSP_dividerX3 is generic (use_sync : std_logic_vector(2 downto 0) := "111"; pattern : std_logic_vector(15 downto 0) := x"0000"; mask : std_logic_vector(15 downto 0) := x"8000"); Port ( clk : in STD_LOGIC; ipb_clk : in STD_LOGIC; q : out STD_LOGIC; din : in STD_LOGIC_VECTOR(2 downto 0); rate : out STD_LOGIC_VECTOR(31 downto 0)); end DSP_dividerX3; architecture Behavioral of DSP_dividerX3 is constant pattern_i : std_logic_vector(47 downto 0) := x"00000000" & pattern; constant mask_i : std_logic_vector(47 downto 0) := x"ffffffff" & mask; signal P : std_logic_vector(47 downto 0) := (others => '0'); signal C : std_logic_vector(47 downto 0) := (others => '0'); signal rate_i : std_logic_vector(31 downto 0) := (others => '0'); signal d_sync : std_logic_vector(2 downto 0); signal match : std_logic; signal P0_q : std_logic; begin C(0) <= d_sync(0) xor P(0) when use_sync(0) = '1' else '1'; C(16) <= d_sync(1) xor P(16) when use_sync(1) = '1' else '1'; C(32) <= d_sync(2) xor P(32) when use_sync(2) = '1' else '1'; process(ipb_clk) begin if(ipb_clk'event and ipb_clk = '1')then rate <= rate_i; end if; end process; process(clk) begin if(clk'event and clk = '1')then P0_q <= P(0); q <= match and (P0_q xor pattern(0)); if(match = '1' and P0_q /= pattern(0))then rate_i <= P(47 downto 16); end if; end if; end process; DSP48E2_inst : DSP48E2 generic map ( -- Feature Control Attributes: Data Path Selection USE_MULT => "NONE", -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE) -- Pattern Detector Attributes: Pattern Detection Configuration AUTORESET_PATDET => "RESET_MATCH", -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH AUTORESET_PRIORITY => "RESET", -- Priority of AUTORESET vs. CEP (CEP, RESET). MASK => mask_i, -- 48-bit mask value for pattern detect (1=ignore) PATTERN => pattern_i, -- 48-bit pattern match for pattern detect USE_PATTERN_DETECT => "PATDET", -- Enable pattern detect (NO_PATDET, PATDET) CREG => 0, -- Pipeline stages for C (0-1) MREG => 0 -- Multiplier pipeline stages (0-1) ) port map ( P => P, -- 48-bit output: Primary data PATTERNDETECT => match, -- 1-bit output: Pattern detect -- Cascade inputs: Cascade Ports ACIN => (others => '0'), -- 30-bit input: A cascade data BCIN => (others => '0'), -- 18-bit input: B cascade CARRYCASCIN => '0', -- 1-bit input: Cascade carry MULTSIGNIN => '0', -- 1-bit input: Multiplier sign cascade PCIN => (others => '0'), -- 48-bit input: P cascade -- Control inputs: Control Inputs/Status Bits ALUMODE => "0000", -- 4-bit input: ALU control CARRYINSEL => "000", -- 3-bit input: Carry select CLK => clk, -- 1-bit input: Clock INMODE => "00000", -- 5-bit input: INMODE control OPMODE => "000001110", -- 9-bit input: Operation mode -- Data inputs: Data Ports A => (others => '1'), -- 30-bit input: A data B => (others => '1'), -- 18-bit input: B data C => C, -- 48-bit input: C data CARRYIN => '0', -- 1-bit input: Carry-in D => (others => '1'), -- 27-bit input: D data -- Reset/Clock Enable inputs: Reset/Clock Enable Inputs CEA1 => '0', -- 1-bit input: Clock enable for 1st stage AREG CEA2 => '0', -- 1-bit input: Clock enable for 2nd stage AREG CEAD => '0', -- 1-bit input: Clock enable for ADREG CEALUMODE => '1', -- 1-bit input: Clock enable for ALUMODE CEB1 => '0', -- 1-bit input: Clock enable for 1st stage BREG CEB2 => '0', -- 1-bit input: Clock enable for 2nd stage BREG CEC => '1', -- 1-bit input: Clock enable for CREG CECARRYIN => '1', -- 1-bit input: Clock enable for CARRYINREG CECTRL => '1', -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG CED => '0', -- 1-bit input: Clock enable for DREG CEINMODE => '1', -- 1-bit input: Clock enable for INMODEREG CEM => '0', -- 1-bit input: Clock enable for MREG CEP => '1', -- 1-bit input: Clock enable for PREG RSTA => '0', -- 1-bit input: Reset for AREG RSTALLCARRYIN => '0', -- 1-bit input: Reset for CARRYINREG RSTALUMODE => '0', -- 1-bit input: Reset for ALUMODEREG RSTB => '0', -- 1-bit input: Reset for BREG RSTC => '0', -- 1-bit input: Reset for CREG RSTCTRL => '0', -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG RSTD => '0', -- 1-bit input: Reset for DREG and ADREG RSTINMODE => '0', -- 1-bit input: Reset for INMODEREG RSTM => '0', -- 1-bit input: Reset for MREG RSTP => '0' -- 1-bit input: Reset for PREG ); g_sync : for i in 0 to 2 generate g_cdc : if use_sync(i) = '1' generate xpm_cdc_single_inst : xpm_cdc_single generic map ( DEST_SYNC_FF => 4, -- DECIMAL; range: 2-10 INIT_SYNC_FF => 1, -- DECIMAL; 0=disable simulation init values, 1=enable simulation init values SIM_ASSERT_CHK => 0, -- DECIMAL; 0=disable simulation messages, 1=enable simulation messages SRC_INPUT_REG => 0 -- DECIMAL; 0=do not register input, 1=register input ) port map ( dest_out => d_sync(i), -- 1-bit output: src_in synchronized to the destination clock domain. This output -- is registered. dest_clk => clk, -- 1-bit input: Clock signal for the destination clock domain. src_clk => '0', -- 1-bit input: optional; required when SRC_INPUT_REG = 1 src_in => din(i) -- 1-bit input: Input signal to be synchronized to dest_clk domain. ); end generate g_cdc; g_no_sync : if use_sync(i) = '0' generate d_sync(i) <= din(i); end generate g_no_sync; end generate g_sync; end Behavioral;