----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 12/29/2020 06:40:18 PM
-- Design Name: 
-- Module Name: tb_ttc_if - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity tb_ttc_if is
--  Port ( );
end tb_ttc_if;

architecture Behavioral of tb_ttc_if is
component TTC_if
		generic (SIM : boolean := true; txrefclk_use_rxrcvedclk : boolean := true);
    Port ( 
           reset : in STD_LOGIC;
           test : in STD_LOGIC;
           prbs_reset : in STD_LOGIC;
           loopback : in STD_LOGIC;
           ngFEC_rdy : in STD_LOGIC;
           clk125 : in STD_LOGIC;
           txrefclk_in : in STD_LOGIC;
           txrefclk_LOLb : in STD_LOGIC;
           rxrefclk_in : in STD_LOGIC;
           fabric_clk_RST : out STD_LOGIC;
           fabric_clk_out : out std_logic;
           rx_p : in STD_LOGIC;
           rx_n : in STD_LOGIC;
           tx_p : out STD_LOGIC;
           tx_n : out STD_LOGIC;
           refclkp_out : out STD_LOGIC;
           refclkn_out : out STD_LOGIC;
           ttc2_stat : out std_logic_vector(15 downto 0);
           ttc_rx_err : out std_logic;
           BCntRes : out std_logic;
           BC0_missing : out std_logic;
           WTE : out std_logic;
           TTC_counter : out std_logic_vector(8 downto 0));
end component;
signal reset : std_logic := '1';
signal clk125 : std_logic := '0';
signal txrefclk : std_logic := '0';
signal rxrefclk : std_logic := '0';
signal fabric_clk_RST : std_logic := '0';
signal fabric_clk_in : std_logic := '0';
signal TTC_rxp_g : std_logic := '0';
signal TTC_rxn_g : std_logic := '0';
signal TTC_txp_g : std_logic := '0';
signal TTC_txn_g : std_logic := '0';
signal TTC_rxp : std_logic := '0';
signal TTC_rxn : std_logic := '0';
signal TTC_txp : std_logic := '0';
signal TTC_txn : std_logic := '0';
signal TTC_rx_rcvclk_p : std_logic := '0';
signal TTC_rx_rcvclk_n : std_logic := '0';
signal BCntRes : std_logic := '0';
--signal  : std_logic := '0';

begin
ttc_gen : ttc_if generic map(SIM => false, txrefclk_use_rxrcvedclk => false) port map(
		reset => reset,
		test => '0',
		prbs_reset => '0',
		loopback => '1',
		clk125 => clk125,
		txrefclk_in => txrefclk,
		txrefclk_LOLb => '1',
		rxrefclk_in => rxrefclk,
		fabric_clk_RST => open,
		fabric_clk_out => open,
		ngFEC_rdy => '0',
		rx_p => TTC_txp_g,
		rx_n => TTC_txn_g,
		tx_p => TTC_txp_g,
		tx_n => TTC_txn_g,
		refclkp_out => open,
		refclkn_out => open,
		ttc2_stat => open,
		ttc_rx_err => open,
    BCntRes => open,
    BC0_missing => open,
    WTE => open,
    TTC_counter => open
	);
uut : ttc_if generic map(SIM => true, txrefclk_use_rxrcvedclk => false) port map(
		reset => reset,
		test => '0',
		prbs_reset => '0',
		loopback => '0',
		clk125 => clk125,
		txrefclk_in => txrefclk,
		txrefclk_LOLb => '1',
		rxrefclk_in => rxrefclk,
		fabric_clk_RST => fabric_clk_RST,
		fabric_clk_out => fabric_clk_in,
		ngFEC_rdy => '0',
		rx_p => TTC_rxp,
		rx_n => TTC_rxn,
		tx_p => TTC_txp,
		tx_n => TTC_txn,
		refclkp_out => TTC_rx_rcvclk_p,
		refclkn_out => TTC_rx_rcvclk_n,
		ttc2_stat => open,
		ttc_rx_err => open,
    BCntRes => BCntRes,
    BC0_missing => open,
    WTE => open,
    TTC_counter => open
	);
TTC_rxp <= TTC_txp_g;
TTC_rxn <= TTC_txn_g;
clk125 <= not clk125 after 4 ns;
rxrefclk <= not rxrefclk after 1.56 ns;
--txrefclk <= rxrefclk;
txrefclk <= TTC_rx_rcvclk_p;
  p_stimulis : process is
  begin
	  wait for 100 ns;
	  reset <= '0';
  end process p_stimulis;  
end Behavioral;