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-- Company: 
-- Engineer: 
-- 
-- Create Date: 03/13/2020 11:17:25 AM
-- Design Name: 
-- Module Name: stat_reg_tb - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use work.ngFEC_pack.all;

library UNISIM;
use UNISIM.VComponents.all;

entity stat_reg_tb is
end stat_reg_tb;

architecture Behavioral of stat_reg_tb is
component stat_reg_block
		generic (sim : boolean := true);
    Port ( clk : in STD_LOGIC;
           ipb_clk : in STD_LOGIC;
           ipb_rst : in STD_LOGIC;
           rx_wordclk : in STD_LOGIC_VECTOR (47 downto 0);
           reset_ctrl : in STD_LOGIC_VECTOR (31 downto 0);
           cntr_din : in STD_LOGIC_VECTOR (511 downto 0);
           rate_din : in STD_LOGIC_VECTOR (255 downto 0);
           stat_reg_in : in array_512x32bit;
           test_com : in STD_LOGIC_VECTOR (47 downto 0);
           ipb_mosi_i : in	ipb_wbus;
           ipb_miso_o : out ipb_rbus);
end component;
signal ipb_rst : std_logic := '1';
signal reset_counter : std_logic := '0';
signal clk : std_logic := '1';
signal ipb_clk : std_logic := '0';
signal ipb_addr : unsigned(10 downto 0);
signal cntr_din : std_logic_vector(511 downto 0) := (others => '0');
signal rate_din : std_logic_vector(255 downto 0) := (others => '0');
signal stat_reg	: array_512x32bit := (others => (others => '0'));
signal ipb_mosi : ipb_wbus;
signal ipb_miso : ipb_rbus;
signal rx_wordclk : std_logic_vector(47 downto 0) := (others => '0');
signal reset_ctrl : std_logic_vector(31 downto 0) := (others => '0');
signal test_com : std_logic_vector(47 downto 0) := (others => '0');

begin
	stat_regs_inst: stat_reg_block
	--===========================================--
	generic map (sim => true)
	port map
	(
		clk					=> clk,
		ipb_clk					=> ipb_clk,
		ipb_rst					=> ipb_rst,
		rx_wordclk => rx_wordclk,
		reset_ctrl				=> reset_ctrl,
		cntr_din => cntr_din,
		rate_din => rate_din,
		stat_reg_in => stat_reg,
		test_com => test_com,
		ipb_mosi_i			=> ipb_mosi,
		ipb_miso_o			=> ipb_miso
	);
clk <= not clk after 2ns;
ipb_clk <= not ipb_clk after 16ns;
g_rx_clk : for i in 0 to 47 generate
	rx_wordclk(i) <= not rx_wordclk(i) after 4.1 ns;
end generate;
ipb_mosi.ipb_write <= '0';
ipb_mosi.ipb_wdata <= (others => '0');
cntr_din(0) <= not cntr_din(0) after 20 ns;
cntr_din(64) <= not cntr_din(64) after 30 ns;
cntr_din(128) <= not cntr_din(128) after 40 ns;
cntr_din(256) <= not cntr_din(256) after 50 ns;
cntr_din(510) <= not cntr_din(510) after 60 ns;
cntr_din(511) <= not cntr_din(511) after 70 ns;
rate_din(0) <= not rate_din(0) after 10 ns;
rate_din(253) <= not rate_din(253) after 20 ns;
rate_din(255) <= not rate_din(255) after 30 ns;
stat_reg(0) <= x"12345678";
stat_reg(1) <= x"23456789";
stat_reg(127) <= x"3456789a";
stat_reg(128) <= x"456789ab";
--!!!!stat_reg(239 downto 192) are used for rate_test_com, will be ignored!!!
stat_reg(256) <= x"56789abc";
stat_reg(511) <= x"6789abcd";
test_com(0) <= '1';
ipb_mosi.ipb_addr <= x"00000" & '0' & std_logic_vector(ipb_addr);
process(ipb_clk,ipb_rst)
begin
	if(ipb_rst = '1')then
		ipb_mosi.ipb_strobe <= '0';
		ipb_addr <= "00000000000";
	elsif(ipb_clk'event and ipb_clk = '1')then
		if(ipb_addr(7 downto 0) = x"ff")then
			ipb_mosi.ipb_strobe <= '0';
		else
			ipb_mosi.ipb_strobe <= '1';
		end if;
		if(ipb_mosi.ipb_strobe = '1')then
			ipb_addr <= ipb_addr + 1;
		end if;
	end if;
end process;
stim_proc: process
  begin    
     -- hold reset state for 100 ns.
     wait for 160 ns;  
	     ipb_rst <= '0';
     wait for 10240*32 ns;  
	     reset_ctrl <= x"a00001fe";
     wait for 10*32 ns;  
	     reset_ctrl <= x"00000000";
     wait for 10240*32 ns;  
	     reset_ctrl <= x"a00001ff";
     wait for 10*32 ns;  
	     reset_ctrl <= x"00000000";
     wait for 10240*32 ns;  
	     reset_ctrl <= x"a0000040";
     wait for 10*32 ns;  
	     reset_ctrl <= x"00000000";
     wait;
  end process;
end Behavioral;