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-- Company: 
-- Engineer: 
-- 
-- Create Date: 02/21/2021 07:17:58 PM
-- Design Name: 
-- Module Name: rst_ctrl_tb - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity rst_ctrl_tb is
--  Port ( );
end rst_ctrl_tb;

architecture Behavioral of rst_ctrl_tb is
component cntr_rst_ctrl
    Port ( clk : in STD_LOGIC;
           clk_phase : in STD_LOGIC_VECTOR (7 downto 0);
           addr : in STD_LOGIC_VECTOR (8 downto 0);
           reset_ctrl : in STD_LOGIC_VECTOR (31 downto 0);
           ram_rsta_cntr : out STD_LOGIC;
           rst_cntr : out STD_LOGIC_VECTOR (511 downto 0));
end component;
signal addr_cntr : unsigned(8 downto 0) := (others => '0');
signal addr : std_logic_vector(8 downto 0) := (others => '0');	
signal reset_ctrl : std_logic_vector(31 downto 0) := (others => '0');	
type array16X32 is array(0 to 15) of std_logic_vector(31 downto 0);
signal rst_ctrl : array16X32;
signal rst_cntr : std_logic_vector(511 downto 0) := (others => '0');	
signal clk : std_logic := '1';
signal ram_rsta_cntr : std_logic := '1';
signal ipb_clk : std_logic := '0';
signal ipb_clk_div2 : std_logic := '0';
signal ipb_clk_div2_r : std_logic := '0';
signal clk_phase : std_logic_vector(7 downto 0) := (others => '0');	

begin
g_rst_ctrl : for i in 0 to 15 generate
	rst_ctrl(i) <= rst_cntr(i*32+31 downto i*32);
end generate;
addr <= std_logic_vector(addr_cntr);
clk <= not clk after 2 ns;
ipb_clk <= not ipb_clk after 16 ns;
uut : cntr_rst_ctrl
	port map(
		clk => clk,
		clk_phase => clk_phase,
		addr => addr,
		reset_ctrl => reset_ctrl,
		ram_rsta_cntr => ram_rsta_cntr,
		rst_cntr => rst_cntr
	);
process(ipb_clk)
begin
	if(ipb_clk'event and ipb_clk = '1')then
		ipb_clk_div2 <= not ipb_clk_div2;
	end if;
end process;
process(clk)
begin
	if(clk'event and clk = '1')then
		ipb_clk_div2_r <= ipb_clk_div2;
		clk_phase(0) <= ipb_clk_div2_r xor ipb_clk_div2;
		clk_phase(7 downto 1) <= clk_phase(6 downto 0);
		if(clk_phase(7) = '1')then
			addr_cntr <= addr_cntr + 1;
		end if;
	end if;
end process;
  p_stimulis : process is
  begin
	  wait for 1600 ns;
	  reset_ctrl <= x"80000000";
	  wait for 22*32ns;
 	  reset_ctrl <= x"a0000078";
	  wait for 512*32ns;
 	  reset_ctrl <= x"c0000023";
	  wait for 512*32ns;
 	  reset_ctrl <= x"e0000008";
	  wait for 512*32ns;
 	  reset_ctrl <= x"60000003";
 	  wait;
 end process p_stimulis;  


end Behavioral;