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-- Company: 
-- Engineer: 
-- 
-- Create Date: 04/16/2020 11:48:31 AM
-- Design Name: 
-- Module Name: dsp_divx2_tb - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
Library xpm;
use xpm.vcomponents.all;

entity dsp_divx2_tb is
--  Port ( );
end dsp_divx2_tb;

architecture Behavioral of dsp_divx2_tb is
component DSP_counterX4b
		generic (use_sync : std_logic_vector(3 downto 0) := "1111"); 
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC_VECTOR(3 downto 0);
           din : in  STD_LOGIC_VECTOR(3 downto 0);
           q : out  STD_LOGIC_VECTOR(47 downto 0));
end component;
component DSP_dividerX3
		generic (use_sync : std_logic_vector(2 downto 0) := "111"; 
		pattern : std_logic_vector(15 downto 0) := x"0000"; 
		mask : std_logic_vector(15 downto 0) := x"8000");
    Port ( clk : in STD_LOGIC;
           ipb_clk : in  STD_LOGIC;
           q : out STD_LOGIC;
           din : in  STD_LOGIC_VECTOR(2 downto 0);
           rate : out  STD_LOGIC_VECTOR(31 downto 0));
end component;
component DSP_dividerX2
		generic (use_sync : std_logic_vector(1 downto 0) := "11"; 
		pattern : std_logic_vector(23 downto 0) := x"008000"; 
		mask : std_logic_vector(23 downto 0) := x"ff8000");
    Port ( clk : in STD_LOGIC;
           ipb_clk : in  STD_LOGIC;
           q : out STD_LOGIC;
           din : in  STD_LOGIC_VECTOR(1 downto 0);
           rate : out  STD_LOGIC_VECTOR(23 downto 0));
end component;
component DSP_rate_counterX3
		generic (use_sync : std_logic_vector(2 downto 0) := "111"); 
    Port ( clk : in  STD_LOGIC;
           ipb_clk : in  STD_LOGIC;
           load : in  STD_LOGIC;
           din : in  STD_LOGIC_VECTOR(2 downto 0);
           rate : out  STD_LOGIC_VECTOR(47 downto 0));
end component;
signal ipb_clk : std_logic := '0';
signal clk250 : std_logic := '1';
signal clk : std_logic := '0';
signal RxFrame_ce : std_logic := '0';
signal rx_frameclk_div2 : std_logic := '0';
signal rx_test_comm_cnt : std_logic := '0';
signal reset : std_logic_vector(3 downto 0) := (others => '0');
signal dinX4 : std_logic_vector(3 downto 0) := (others => '0');
signal qX4 : std_logic_vector(47 downto 0) := (others => '0');
signal ngccm_status : std_logic_vector(15 downto 0) := (others => '0');
signal load : std_logic := '0';
signal test : std_logic := '0';
signal rate : std_logic_vector(23 downto 0) := (others => '0');
signal cnt1 : std_logic := '0';
signal cnt2 : std_logic := '0';
signal cnt3 : std_logic := '0';
signal cnt4 : std_logic := '0';
signal cnt5 : std_logic := '0';
signal rate0 : std_logic_vector(15 downto 0) := (others => '0');
signal rate1 : std_logic_vector(15 downto 0) := (others => '0');
signal rate2 : std_logic_vector(15 downto 0) := (others => '0');
signal rate3 : std_logic_vector(15 downto 0) := (others => '0');
signal rate4 : std_logic_vector(15 downto 0) := (others => '0');
signal rx_cnt : unsigned(2 downto 0) := (others => '0');
begin
i_DSP_counterX4b : DSP_counterX4b
	port map(
		clk => clk250,
		reset => reset,
		din => dinX4,
		q => qX4
	);
dinX4 <= not dinX4 after 4.1ns;
reset(0) <= '1' when qX4(11 downto 0) = x"017" else '0';
i_rate_ngccm_status0: DSP_dividerX3
		generic map(mask => x"ff00")
		PORT MAP (
      clk => clk250,
      ipb_clk => ipb_clk,
      din(0) => test,
      din(1) => cnt1,
      din(2) => cnt2,
      q => load,
      rate(15 downto 0) => rate0,
      rate(31 downto 16) => rate1
);
i_rate_test_comm: DSP_dividerX2
-- generic map(pattern => x"008000", mask => x"ff8000")
	PORT MAP (
    clk => clk250,
    ipb_clk => ipb_clk,
    din(0) => rx_frameclk_div2,
    din(1) => rx_test_comm_cnt,
    q => open,
    rate => rate);
	i_rate_ngccm_status1: DSP_rate_counterX3
		PORT MAP (
			clk => clk250,
			ipb_clk => ipb_clk,
			load => load,
			din(0) => cnt3,
			din(1) => cnt4,
			din(2) => cnt5,
      rate(15 downto 0) => rate2,
      rate(31 downto 16) => rate3,
      rate(47 downto 32) => rate4);
clk250 <= not clk250 after 2ns;
ipb_clk <= not ipb_clk after 16ns;
clk <= not clk after 4ns;
test <= clk;
cnt1 <= not cnt1 after 50ns;
cnt2 <= not cnt2 after 100ns;
cnt3 <= not cnt3 after 150ns;
cnt4 <= not cnt4 after 200ns;
cnt5 <= not cnt5 after 250ns;
ngccm_status(15) <= '1';
	process(clk)
	begin
		if(clk'event and clk = '1')then
			if(rx_cnt = "101")then
				rx_cnt <= "000";
				RxFrame_ce <= '1';
			else
				rx_cnt <= rx_cnt + 1;
				RxFrame_ce <= '0';
			end if;
			if(RxFrame_ce = '1')then
				rx_frameclk_div2 <= not rx_frameclk_div2;
				if(ngccm_status(15) = '1')then
					rx_test_comm_cnt <= not rx_test_comm_cnt;
				end if;
			end if;
		end if;
	end process;
end Behavioral;