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-- Company: 
-- Engineer: 
-- 
-- Create Date: 04/16/2020 11:48:31 AM
-- Design Name: 
-- Module Name: dsp_divx2_tb - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
Library xpm;
use xpm.vcomponents.all;

entity DSP_counterX4b_tb is
--  Port ( );
end DSP_counterX4b_tb;

architecture Behavioral of DSP_counterX4b_tb is
component DSP_counterX4b
		generic (use_sync : std_logic_vector(3 downto 0) := "1111"); 
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC_VECTOR(3 downto 0);
           din : in  STD_LOGIC_VECTOR(3 downto 0);
           q : out  STD_LOGIC_VECTOR(47 downto 0));
end component;
signal clk250 : std_logic := '1';
signal reset : std_logic_vector(3 downto 0) := (others => '0');
signal dinX4 : std_logic_vector(3 downto 0) := (others => '0');
signal qX4 : std_logic_vector(47 downto 0) := (others => '0');
begin
i_DSP_counterX4b : DSP_counterX4b
	port map(
		clk => clk250,
		reset => reset,
		din => dinX4,
		q => qX4
	);
dinX4 <= not dinX4 after 4.1ns;
reset(0) <= '1' when qX4(11 downto 0) = x"017" else '0';
clk250 <= not clk250 after 2ns;
end Behavioral;