Xilinx ISim DBG 004'7`5$8&8&8&8&8&(+`3`344p5p5f?T0%"  ' 3*6S=\>e?n =z E  K  .  8  9  : ; &8 A'9 A (: A); A A%*< 0+= ;,> F-? Q W.@ c 0A <O c >P J^ c L_ Xm c Zn   4!| 5" B# B$ B% B& ' ( ) * + ,}-./01*273D4R5e6x78 9 :~-./01*273D4R5e6x78 ; < - . / 0 1* 27 3D 4R 5e 6x 7 8! =! >"-"."/"0"1*"27"3D"4R"5e"6x"7"8 )%"&   D  ) ! = > ? = E K . 8 9 : ;   A  A  A  A A      w    4  5 B B B B  12 340   # ( 1  : D O Z e m u }    " # $ % & ( ) * +% ,7 .F /U 0d 1s 3 4 5 6      # $  %  &0  *0  +0  ,0 -0 .0 / 0 1 2$ "- A- A- A- A- - - - - /7>GP^ mt     - - - - 9/0    /0/0/0/0/0/0_topDSP_counterX4b_tbBehavioralglblvcomponentsi_DSP_counterX4bDSP_counterX4bline__61line__62line__63Initial61_0Initial69_1Initial75_2Initial46_3NetRegassign56_5NetRegassign57_6NetRegassign58_7NetRegassign59_8NetRegassign20_9\g_inc(0)\\g_inc(1)\\g_inc(2)\\g_inc(3)\g_inc\g_AB2(0)\\g_AB2(1)\\g_AB2(2)\\g_AB2(3)\g_ab2\g_sync(0)\xpm_cdc_single_instxpm_cdc_single\g_sync(1)\\g_sync(2)\\g_sync(3)\g_syncline__52line__53line__66line__187g_cdcg_no_syncconfig_drc_singlesim_checkInitial171_10Always237_11Always237_12Always238_13Always238_14Initial253_15NetRegassign221_35NetRegassign222_36NetRegassign230_37NetRegassign213_38clk250resetdinX4qX4GSRGTSGWEPRLDGRESTOREp_up_tmpPLL_LOCKGPROGB_GLBLCCLKO_GLBLFCSBO_GLBLDO_GLBLDI_GLBLGSR_intGTS_intPRLD_intGRESTORE_intJTAG_TDO_GLBLJTAG_TCK_GLBLJTAG_TDI_GLBLJTAG_TMS_GLBLJTAG_TRST_GLBLJTAG_CAPTURE_GLBLJTAG_RESET_GLBLJTAG_SHIFT_GLBLJTAG_UPDATE_GLBLJTAG_RUNTEST_GLBLJTAG_SEL1_GLBLJTAG_SEL2_GLBLJTAG_SEL3_GLBLJTAG_SEL4_GLBLJTAG_USER_TDO1_GLBLJTAG_USER_TDO2_GLBLJTAG_USER_TDO3_GLBLJTAG_USER_TDO4_GLBLROC_WIDTHTOC_WIDTHGRES_WIDTHGRES_STARTclkdinqPCOUTPP2CAB2reset_rdd_syncd_sync_rstuse_syncisrc_clksrc_indest_clkdest_outsyncstages_ffglblGSR_xpmcdcsrc_ffsrc_inqualasync_path_bitDEST_SYNC_FFINIT_SYNC_FFSIM_ASSERT_CHKSRC_INPUT_REGVERSIONdrc_err_flagD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sim_1/dsp_countx4b_tb.vhd/proj/xbuilds/2020.1_INT_0224_1736/installs/all_platforms/Vivado/2020.1/data/vhdl/src/std_2008/standard.vhd/proj/xbuilds/2020.1_INT_0224_1736/installs/all_platforms/Vivado/2020.1/data/vhdl/src/std_2008/textio.vhd/proj/xbuilds/2020.1_INT_0224_1736/installs/all_platforms/Vivado/2020.1/data/vhdl/src/ieee_2008/std_logic_1164.vhdl/proj/xbuilds/2020.1_INT_0224_1736/installs/all_platforms/Vivado/2020.1/data/vhdl/src/ieee_2008/std_logic_1164-body.vhdl/proj/xbuilds/2020.1_INT_0224_1736/installs/all_platforms/Vivado/2020.1/data/vhdl/src/ieee_2008/numeric_std.vhdl/proj/xbuilds/2020.1_INT_0224_1736/installs/all_platforms/Vivado/2020.1/data/vhdl/src/ieee_2008/numeric_std-body.vhdl/wrk/2020.1/nightly/2020_05_27_2902540/packages/customer/vivado/data/ip/xpm/xpm_VCOMP.vhdD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.sim/sim_1/behav/xsim/glbl.vD:/Design_collection/ngFECKU115_pcie/ngFECKU115_pcie.srcs/sources_1/DSP_counterX4b.vhd/wrk/2020.1/continuous/2020_05_27_2902540/data/vhdl/src/unisims/unisim_retarget_VCOMP.vhdp/wrk/2020.1/continuous/2020_05_27_2902540/data/vhdl/src/unisims/primitive/DSP48E2.vhd/proj/xbuilds/2020.1_INT_0224_1736/installs/all_platforms/Vivado/2020.1/data/vhdl/src/vital2000/restricted/timing_p.vhd/proj/xbuilds/2020.1_INT_0224_1736/installs/all_platforms/Vivado/2020.1/data/vhdl/src/vital2000/restricted/timing_b.vhd/proj/xbuilds/2020.1_INT_0224_1736/installs/all_platforms/Vivado/2020.1/data/vhdl/src/vital2000/restricted/prmtvs_p.vhd/proj/xbuilds/2020.1_INT_0224_1736/installs/all_platforms/Vivado/2020.1/data/vhdl/src/vital2000/restricted/prmtvs_b.vhd/wrk/2020.1/continuous/2020_05_27_2902540/data/vhdl/src/unisims/unisim_VPKG.vhd/wrk/2020.1/nightly/2020_05_27_2902540/packages/customer/vivado/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv/wrk/xhdhdnobkup2/tapodyu/Xsim_Clean/src/ext/xsimverific/vhdl_packages/mixed_lang_vltype.vhdTT**XX[[))DD & =>?./01345689:;>?@ABFGHLMNOP4789:;=B (8@ ((X8@  x  8 @    ` h   @Hhp@Hhp (HPpx(0 !"PX#$%J&J'J( J) (*8@+ (,(X-,@,.@-p-/p..0//1@1p12223334445666Pe7Xg80h9i:i;j<k=l>m?n@  A  B  C  DxEFpGHX`IZJZKZLZM ZN@oO`hA@HBC  D hEF`GHhpIdJdKdLdMdNoP A B C ( D E F G Hx I`o Jho Kpo Lxo Mo Np!Qpx"APX"B"C"Dp"E"Fh"G"H"Iz"Jz"K z"L(z"M0z"Nde%Rhp0S>SLS` h ZS