Vivado Simulator 2020.1
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: D:/Xilinx/Vivado/2020.1/bin/unwrapped/win64.o/xelab.exe -wto 547eb004b26648509e84d8b4a9e677c6 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot ctrl_reg_tb_behav xil_defaultlib.ctrl_reg_tb xil_defaultlib.glbl -log elaborate.log 
Using 2 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling package xil_defaultlib.ngfec_pack
Compiling package unisim.vcomponents
Compiling package ieee.vital_timing
Compiling package ieee.vital_primitives
Compiling package unisim.vpkg
Compiling module xil_defaultlib.glbl
Compiling architecture behavioral of entity xil_defaultlib.DSP_MUX [dsp_mux_default]
Compiling architecture dsp48e2_v of entity unisim.DSP48E2 [\DSP48E2(acascreg=0,adreg=0,alum...]
Compiling architecture behavioral of entity xil_defaultlib.DSP_MUX_b [dsp_mux_b_default]
Compiling architecture rtl of entity xil_defaultlib.ipb_user_control_regs [ipb_user_control_regs_default]
Compiling architecture behavioral of entity xil_defaultlib.ctrl_reg_tb
Built simulation snapshot ctrl_reg_tb_behav