# compile vhdl design source files
vhdl xil_defaultlib  \
"../../../../ngFECKU115_pcie.srcs/sources_1/DSP_counterX4b.vhd" \
"../../../../ngFECKU115_pcie.srcs/sources_1/DSP_dividerX2.vhd" \
"../../../../ngFECKU115_pcie.srcs/sources_1/DSP_dividerX3.vhd" \
"../../../../ngFECKU115_pcie.srcs/sources_1/DSP_rate_counterX3.vhd" \
"../../../../ngFECKU115_pcie.srcs/sim_1/dsp_divx2_tb.vhd" \

# Do not sort compile order
nosort