# compile vhdl design source files
vhdl xil_defaultlib  \
"../../../../ngFECKU115_pcie.srcs/sources_1/ngFEC_packX48.vhd" \
"../../../../ngFECKU115_pcie.srcs/sources_1/DSP_MUX.vhd" \
"../../../../ngFECKU115_pcie.srcs/sources_1/DSP_MUX_b.vhd" \
"../../../../ngFECKU115_pcie.srcs/sources_1/ipb/ipb_user_control_regs.vhd" \
"../../../../ngFECKU115_pcie.srcs/sim_1/new/ctrl_reg_tb.vhd" \

# Do not sort compile order
nosort